Not able to simulate for any other ITA_N except for N=16 (default)

[copparihollmann]

Dear @gamzeisl , @Xeratec and the rest of the ITA team,

We really like the work you've done, and it inspired us to use it as the core of our project for the AMD Open Hardware Competition.

We are writing to you today because we've encountered a significant roadblock that has halted our progress for the past three months. We are struggling to synthesize the accelerator with the default ITA_M=64 and ITA_N=16 configuration and have been unable to get simulations working for any other configuration.

You can check our work here: Link to repository

What we would like to have are the following paramters:

# --- 6. Set Verilog Defines (Macros) ---
# These macros are extracted from the Makefile and compile.tcl to align
# the Vivado project with the original compilation environment.
puts "INFO: Setting Verilog defines..."
set verilog_macros [list \
    "TARGET_ITA_HWPE" \
    "TARGET_ITA_HWPE_TEST" \
    "TARGET_RTL" \
    "TARGET_SIMULATION" \
    "TARGET_TEST" \
    "TARGET_VSIM" \
    "NO_STALLS=0" \
    "SINGLE_ATTENTION=0" \
    "ITA_N=8" \
    "N_PE=8" \
    "ITA_M=64" \
    "M_TILE_LEN=64" \
    "SEQ_LENGTH=64" \
    "EMBED_SIZE=128" \
    "PROJ_SPACE=192" \
    "FF_SIZE=256" \
    "BIAS=0" \
    "ACTIVATION=Identity" \
    "HCI_ASSERT_DELAY=\#41ps" \
]

The Synthesis Problem

When we attempt to synthesize the design with ITA_M=64 and ITA_N=16, we consistently encounter the following warning, which ultimately leads to a synthesis failure:

WARNING: [Synth 8-11357] Potential Runtime issue for 3D-RAM or RAM from Record/Structs for RAM inp1_reg with 9216 registers

We have spoken with other teams who have attempted to use ITA and they have confirmed running into the exact same issue. While we understand that this configuration might not be feasible for synthesis on our target FPGA, we have had success with other configurations, such as:

• N=8, M=64
• N=8, M=32
• N=4, M=32

All of these synthesize successfully. This leads us to the simulation problem.

The Simulation Problem

Unfortunately, while we can synthesize smaller configurations, the simulation only works for the default N=16 and M=64 setting. For any other configuration, the simulation hangs. Specifically, the simulation does not advance beyond step Q, which we find very strange.

We have done some digging into the and it appears to be a deadlock issue within the FIFO logic. Some FIFOs do not consume data, leading to a situation where other FIFOs become full, stalling the entire pipeline (I will follow up with more information on this).

We have been meticulous in ensuring that all hardcoded values in the PyITA test generator are updated for our different configurations and that our project macros are set correctly.

We've also experimented with changing AccDataWidth and TCDM_DW to 512 and 256, along with all related values, but with no success.

Environment and Troubleshooting

We have tried to resolve this on our own by testing in various environments, including:

• Vivado Versions: 2023.1 and 2024.2
• Operating Systems: Windows and Linux

So far, we have not been able to change a single parameter (besides simulation data) and have the simulation complete successfully. This leads us to a broader question: is the AccDataWidth of 1024 directly related to the N and M parameters or is there a some configuration we are missing to be able to finish simulation with a smaller ITA?

Our Request

We are reaching out to you as we are running out of time for the competition, with the deadline at the end of next month. The rest of our project is complete and ready to be integrated with ITA. It would be a huge shame to have to abandon our work due to this final hurdle. Any smaller configuration that we can simulate and synthesize would work for us.

Do you have any recommendations on how to correctly modify the parameters to create a smaller design that can still complete a simulation run?

We would be incredibly grateful for any help you could provide. Even guidance on getting a design with a smaller N value to work in QuestaSim (even without Vivado) would be a massive help. We are very familiar with the architecture at this point and would be more than happy to jump on a call to discuss the issue in more detail.

Thank you for your time and for your amazing work on this project!

PD.: you can find our .tcl file in the repository I shared

[copparihollmann]

On an extra note.

While simulation of ita_hwpe_tb doesnt work past Q for N=8 and M=64. Simulation for ita_tb also doesnt finish but it goes up to stek QK. Results for Q, V and K are wrong, but it does advance further than for ita_hwpe_tb.

This was the same problem we had with ita_hwpe_tb at the beginning when some of the macros and parameters were defined incorrectly either for the simulation or to generate the data through PyITA. This leads me to believe that the problem on why ita_tb doesnt work has to do with some definitions that were made through parameters either at the test data generation or some of the definitions in the ita_package.sv.

If you have any hints on what could we try to change next that would be extremely helpful as I imagine you know very well the effect of the different defined paramters.

Thank you in advance for the help!

[gamzeisl]

Please check this PR. I confirm that it works for N = 8 and M = 64.

[copparihollmann]

@gamzeisl Thank you for the push!

I just checked your PR and it also works correctly from my side. To be honest, we spent the last week everyday on debugging and while we found the problems with the _double_width_write.sv and the max_finder.sv, I really think there are a lot of changes that we would have taken too long for us to find. Thank you once again for the help!

I noticed that you introduce some more parametrization for N that also included M.

At the moment, Synthesis seems to still be a bit too big for N=8, M=64.

I have absolutely no problem on verifying the implementation of N=8, M=32. The only thing that would be hard for me to realize whether to change or not is the hardcoded values. If you could point me to those, I would be more than happy to take the work of introducing the parametrization and test for the correct values.

This would be the final piece of the puzzle for us!