Names for loops (clock enables, initial value after reset)

[satnam6502]

We've got clunky names for loops of various flavours of registers:

• Registers with no clock enable and a default initial value after reset (inputs: D, output Q). This is FDR in the Xilinx library.
• Registers with no clock enable and a specified initial value (compile time parameter INIT, inputs; D, output Q). This is FDR in the Xilinx library.
• Registers with a clock enable and a default initial value after reset (inputs: D, CE, output Q). This is FDRE in the Xilinx library.
• Registers with a clock enable and a specified initial value (compile time parameter INIT, inputs; D, CE, output Q). This is FDRE in the Xilinx library.

You can search for the descriptions of these registers in this Xilinx library guide.

All the registers we generate have two implicit input signals that we deliberately don't have access to in Cava but are wired up during netlist instantiation:

• C: the clock signal.
• R: a synchronous reset signal. All registers we generate have a synchronous reset at the start of execution which is asserted once and then never asserted again (otherwise our semantics do not apply). We could chose to switch to an asynchronous reset if required.

The latter case should be the only primitive element and the others defined as specializations of the component in library modules.

Now, given that our loop combinator is fused with a register how should we name the primitive loop combinator and all the specializations of it? We could follow the Xilinx naming convention:

• loop which (morally) instantiates a FDR
• loopInit which has a compile time constant for the initial reset value which instantiates a FDR
• loopCE which instantiates a FDRE
• loopInitCE which has a compile time constant for the initial reset value which instantiates a FDRE

Any better ideas?

Note that except for the Xilinx specific designs (and even then we might not) we don't directly instantiate these registers, instead generating an always block sensitive the clock and reset which the Xilinx Vivado synthesis tools then map into actual register primitives. I do check the synthesized circuits to make sure they generated the registers I expected.

Satnam

[jadephilipoom]

We could follow the Xilinx naming convention:

• loop which (morally) instantiates an FDR
• loopInit which has a compile time constant for the initial reset value which instantiates aFDR
• loopCE which instantiates a FDRE
• loopInitCE which has a compile time constant for the initial reset value which instantiates aFDRE

This sounds good to me!

[blaxill]

Our components specifying reset values set them after reset and select between FDS/FDR rather than FDR with different INIT right?

I would prefer not having multiple loops and instead just specify one with optional reset/enable values:

signal: option (signal Bit) (* optional clock enable *)
     -> option (signal B) (* optional reset value *)
     -> (signal A * signal B -> cava (signal B)) -> signal A -> cava (signal B)

[satnam6502]

Given that the common case in general involves not specifying and initial value after reset or a clock enable I feel it is better to have a name for the common case loop (e.g. loop). Also, I personally would dislike having to specify None and Some in the invocations of the loops.

[blaxill]

Yeah I agree having a name for the common case, but I wouldn't add explicit names for the others although I don't feel strongly and I'm happy with any choice.

[satnam6502]

Yeah, agreed, and I don't have super strong views either. I do find it confusing when I come across a function call that has several None arguments because unless I can remember the argument order I have to hunt around the code base to see what is happening (or pray for a better IDE).