uart.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 2025  Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and any partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Altera and sold by Altera or its authorized distributors.  Please
# refer to the Altera Software License Subscription Agreements 
# on the Quartus Prime software download page.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 24.1std.0 Build 1077 03/04/2025 SC Lite Edition
# Date created = 18:28:26  October 30, 2025
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		uart_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 24.1STD.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:28:26  OCTOBER 30, 2025"
set_global_assignment -name LAST_QUARTUS_VERSION "24.1std.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_FILE src/display.vhd
set_global_assignment -name VHDL_FILE src/fifo.vhd
set_global_assignment -name VHDL_FILE src/rx.vhd
set_global_assignment -name VHDL_FILE src/tx.vhd
set_global_assignment -name VHDL_FILE src/clk.vhd
set_global_assignment -name VHDL_FILE src/pkg.vhd
set_global_assignment -name VHDL_FILE src/top.vhd
set_location_assignment PIN_J20 -to HEX0[0]
set_location_assignment PIN_K20 -to HEX0[1]
set_location_assignment PIN_L18 -to HEX0[2]
set_location_assignment PIN_N18 -to HEX0[3]
set_location_assignment PIN_M20 -to HEX0[4]
set_location_assignment PIN_N19 -to HEX0[5]
set_location_assignment PIN_N20 -to HEX0[6]
set_location_assignment PIN_P11 -to clk
set_location_assignment PIN_B8 -to rst
set_location_assignment PIN_F21 -to HEX1[0]
set_location_assignment PIN_E22 -to HEX1[1]
set_location_assignment PIN_E21 -to HEX1[2]
set_location_assignment PIN_C19 -to HEX1[3]
set_location_assignment PIN_C20 -to HEX1[4]
set_location_assignment PIN_D19 -to HEX1[5]
set_location_assignment PIN_E17 -to HEX1[6]
set_location_assignment PIN_B20 -to HEX2[0]
set_location_assignment PIN_A20 -to HEX2[1]
set_location_assignment PIN_B19 -to HEX2[2]
set_location_assignment PIN_A21 -to HEX2[3]
set_location_assignment PIN_B21 -to HEX2[4]
set_location_assignment PIN_C22 -to HEX2[5]
set_location_assignment PIN_B22 -to HEX2[6]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top