PolarFire SoC LPDDR4 training fails at 800 MHz (and also at 400 MHz test)

[HarryStevensonHW]

Platform

SoC: PolarFire® SoC (custom board; design closely follows the MPFS Video Kit)
Memory: Micron MT53E1G32D2FW-046 AAT:B, x32, 1 rank
Config highlights: DQ width=32, Row=16, CK=800 MHz (1600 MT/s target). Also tried CK=400 MHz (800 MT/s).
Tooling: DDR training via HSS and DDR demo (log attached).

Symptom (consistent across runs)
Training repeatedly aborts during Read Gate / Read DQ/DQS Optimization with:
Filtering failures DQDQS Windows is too small → final training status = 0x1D.
Per-lane table shows dqdqs_err_done = 1 (all lanes). Example with lane tables and final 0x1D:
Writes are clean (runs show WRCALIB_RESULT = 0x00000000) Examples: clean write but read fails.
CA training passes and finds a stable vref_answer = 0x07, after which the flow returns to the user setting.
Global sampler phase printout stubbornly reports bclk_sclk_offset value = 0x05 on every sweep, even when we vary phase-related knobs.
What we tried (one knob at a time)

Electricals
DQ/DQS drive swept (e.g., 34/34, 40/40 (default), 60/60). 60/60 was clearly worse (no lane passes and write on the edge).
ODT permutations: DQ ODT RZQ/2, RZQ/4, disabled; DQS ODT 40→60 Ω, etc. Net effect: no improvement, sometimes regressed write (edge).
VrefDQ (data) swept (15%→20%→24%); VrefCA set to trained code 0x07 (~28%) so post-training “return to user” doesn’t detune CA. Still fails read.
DQDQS start window offset (RPC_156) set to 0x01 (confirmed in logs); leaving it at 0x06 was worse.

Phase / clocking
Enabled Advanced CA training with offsets 0°/45°/90°/135°; also changed CK push order. No change to the read-window failure.
Increased REFCLK_LPDDR4_1600_NUM_OFFSETS from 1→4 to broaden refclk phase sweep; training still reports the same small-window failure.
Stepped TIP_CONFIG_PARAMS_BCLK_VCOPHS across multiple values (0x01…0x07). Logs still show bclk_sclk_offset = 0x05 and the same read-window failure.
Disabled SSCG on the DDR PLL (set SSE_B=0 in ddr_pll/SSCG_REG_3). Jitter reduction didn’t help; same failure. (XML + log attached.)

Timings

Wide sweeps of RL (6→36) and WL (4→18) for 1600 MT/s. All runs fail with the same DQDQS window too small signature (write mostly OK).
Read post-amble changed to 1.5 tCK. No change.

Frequency sanity check
Also tested 400 MHz (800 MT/s). Training still failed with the same read-window error, indicating it’s not just high-speed margin. (Log attached.)
Repeatable facts from logs
Error line and code are consistent: “Filtering failures DQDQS Windows is too small” → status 0x1D. Examples across multiple runs:
bclk_sclk_offset is always 0x05, despite refclk/VCOPHS changes.

Current “best” baseline (still fails read)

DQ/DQS drive ≈ 40/40, DQ ODT ~80 Ω, DQS ODT ~40 Ω; VrefDQ ≈ 20%, VrefCA code 0x07; RPC_156 = 0x01; REFCLK_LPDDR4_1600_NUM_OFFSETS = 4; DDR-PLL SSCG disabled; RL/WL nominal for 1600 MT/s (multiple tried). Result: write OK, read DQ↔DQS window too small (0x1D), lanes show dqdqs_err_done=1.

Read-sampling phase control: Even after widening the refclk sweep and stepping BCLK_VCOPHS, the effective bclk_sclk_offset never changes from 0x05 in logs. Is there another register/sequence needed to actually move the read capture phase at LPDDR4-1600? (Any mapping from BCLK_VCOPHS → bclk_sclk_offset would help.)

Per-byte gate tuning: Guidance on forcing/offsetting Read Gate / DQS gate per-byte in TIP (registers or XML fields) to overcome board-level CK↔DQS flight-time skew.

Known-good template: A known-good HSS/TIP XML (or parameter set) for MT53E1G32D2FW-046 @ LPDDR4-1600 on MPFS (x32, 1-rank) would be invaluable.

Status/field decode: Official meaning of training status 0x1D, and the rdqdqs_status2 / dqdqs_state codes seen in the lane tables (attached) to better interpret what “too small” is flagging at each lane.

Any errata related to LPDDR4 TIP training at 1600 MT/s (or 800 MT/s), phase selection, or SSCG interactions.

Attachments (representative)
XML currently used (with DDR-PLL SSCG disabled): Polar_Cube_OBC_mss_cfg.xml.
Typical failing logs
Eye diagram at 800MHz.
MSS configuration file

Expectation
With vendor guidance on (a) how to reliably shift the read capture phase on MPFS LPDDR4 TIP, or (b) recommended per-byte gate tuning sequence/fields, we expect the read DQ↔DQS sampling point to land inside the eye and training to complete. The write path is already stable on our baseline.

xml.zip
DDR_Debug_Log.txt

[hughbreslin]

Hey @HarryStevensonHW could you open a tech support case on this issue so it can be looked into properly?

You can open a case here

[HarryStevensonHW]

Hi,
Sure.