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Target FPGA board and Xilinx primitives #7

@sauc

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@sauc

I'm having troubles while running a simulation of the JPEG Encoder (jpeg.encoder.hw.Encoder in the JPEG orc-apps repo). The behavioral simulation is correct, but, in the post-synthesis one, some tokens are not correctly stored into the BRAMs (timing is ok). I'm working with Vivado 2015.2 and questasim 10.4 and I'm targeting an Artix-7 xc7a100tcsg324-2. I've noticed that Xronos adopts a Virtex II xc2vp30-7-ff1152 FPGA and the related primitives by default. Is it possible that my problem is related to the primitive simulation models that are not matching from behavioral (where a Virtex II primitive is adopted) to post-synthesis (where Artix-7 primitives are istantiated)? Is there a way to change the referenced FPGA so that Xronos can insert the correct primitive?

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