From dfead4a78ec40704181c04be7c8a5c62666c0d4b Mon Sep 17 00:00:00 2001
From: Ilya Tuzov <38259080+IlyaTuzov@users.noreply.github.com>
Date: Wed, 16 Jul 2025 17:09:51 +0200
Subject: [PATCH] Update tristan-isolde-unified-access-page.html

updated tristan-isolde-unified-access-page.html from UPV
---
 tristan-isolde-unified-access-page.html | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/tristan-isolde-unified-access-page.html b/tristan-isolde-unified-access-page.html
index 3b20904..da7ffb1 100644
--- a/tristan-isolde-unified-access-page.html
+++ b/tristan-isolde-unified-access-page.html
@@ -1027,7 +1027,7 @@ <h3 id="2.2">
                 Wormhole NoC
             </td>
             <td>
-                Not ready yet
+                 <a href="https://gitlab.com/selene-riscv-platform/euros2pronoc/-/tree/AXI-MM-Network-Interface?ref_type=heads">NoC</a>
             </td>
             <td>
                 ISOLDE
@@ -1039,10 +1039,10 @@ <h3 id="2.2">
                 UPV
             </td>
             <td>
-                &nbsp;
+                Work in progress
             </td>
             <td>
-                TBD
+                In this architecture, all the communication among tiles is carried out through the network. A tile is an abstraction entity that encapsulates one or more IPs of a SoC and provides an AXI Memory-Mapped interface to them. The main components of every tile are the on-chip network switch, the Network Interface (NI), and a placeholder (a.k.a. UNIT), which is used to implement the desired Intellectual Property (IP) or Processing Element (PE).
             </td>
             <td>
                 MIT
@@ -1056,7 +1056,7 @@ <h3 id="2.2">
                 AXI Sniffer
             </td>
             <td>
-                Not ready yet
+                <a href="https://gitlab.com/selene-riscv-platform/selene-hardware/-/tree/master/interconnect/libnoc/mem_monitor">AXI Sniffer</a>
             </td>
             <td>
                 ISOLDE
@@ -1068,10 +1068,10 @@ <h3 id="2.2">
                 UPV
             </td>
             <td>
-                &nbsp;
+                Completed
             </td>
             <td>
-                TBD
+                This module monitors axi4 transactions and determines contention between the different initiators of transactions. The initiators of transactions are given by a world ID encoded in the QoS field of the AXI channels. Supports following contention tracking features: read contention monitoring backpressure channels, read contention blaming the head of the queue for all contention caused in the queue, cross read-write backpressure, write backpressure monitoring, cross write-read backpressure. 
             </td>
             <td>
                 MIT
@@ -3916,7 +3916,7 @@ <h3 id="4.3">
                 Bit-accurate FPGA fault injection (BAFFI) tool
             </td>
             <td>
-                &nbsp;
+                <a href="https://gitlab.com/selene-riscv-platform/DAVOS">BAFFI</a>
             </td>
             <td>
                 ISOLDE
@@ -3928,10 +3928,10 @@ <h3 id="4.3">
                 UPV
             </td>
             <td>
-                &nbsp;
+                Work in progress
             </td>
             <td>
-                TBD
+                BAFFI supports bit-accurate fault injection into Ultrascale+ and 7-series AMD FPGAs. Supports transient fault models representative for FPGA and ASIC designs. Adapted to the SELENE (NOEL-V) SoC in VCU118 evaluation board.
             </td>
             <td>
                 MIT