From f0da5743043c419ca1c787a74c26f9534a00c8ab Mon Sep 17 00:00:00 2001 From: Canberk Topal Date: Tue, 27 Sep 2022 10:16:35 +0100 Subject: [PATCH 1/2] merge [rtl] Change how we record debug causes --- rtl/cve2_controller.sv | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/rtl/cve2_controller.sv b/rtl/cve2_controller.sv index 16ef29dba4..2db945c714 100644 --- a/rtl/cve2_controller.sv +++ b/rtl/cve2_controller.sv @@ -109,6 +109,7 @@ module cve2_controller #( logic nmi_mode_q, nmi_mode_d; logic debug_mode_q, debug_mode_d; + dbg_cause_e debug_cause_d, debug_cause_q; logic load_err_q, load_err_d; logic store_err_q, store_err_d; logic exc_req_q, exc_req_d; @@ -312,6 +313,22 @@ module cve2_controller #( assign unused_irq_timer = irqs_i.irq_timer; + assign debug_cause_d = trigger_match_i ? DBG_CAUSE_TRIGGER : + ebreak_into_debug ? DBG_CAUSE_EBREAK : + debug_req_i ? DBG_CAUSE_HALTREQ : + do_single_step_d ? DBG_CAUSE_STEP : + DBG_CAUSE_NONE ; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + debug_cause_q <= DBG_CAUSE_NONE; + end else begin + debug_cause_q <= debug_cause_d; + end + end + + assign debug_cause_o = debug_cause_q; + ///////////////////// // Core controller // ///////////////////// @@ -346,7 +363,6 @@ module cve2_controller #( flush_id = 1'b0; debug_csr_save_o = 1'b0; - debug_cause_o = DBG_CAUSE_EBREAK; debug_mode_d = debug_mode_q; nmi_mode_d = nmi_mode_q; @@ -531,13 +547,6 @@ module cve2_controller #( debug_csr_save_o = 1'b1; csr_save_cause_o = 1'b1; - if (trigger_match_i) begin - debug_cause_o = DBG_CAUSE_TRIGGER; - end else if (debug_single_step_i) begin - debug_cause_o = DBG_CAUSE_STEP; - end else begin - debug_cause_o = DBG_CAUSE_HALTREQ; - end // enter debug mode debug_mode_d = 1'b1; @@ -567,7 +576,6 @@ module cve2_controller #( // dcsr debug_csr_save_o = 1'b1; - debug_cause_o = DBG_CAUSE_EBREAK; end // enter debug mode From b139ad1f60f0e1bb4b933876fa74081c107aac1c Mon Sep 17 00:00:00 2001 From: Harry Callahan Date: Tue, 11 Oct 2022 14:29:36 +0100 Subject: [PATCH 2/2] Fixup signal used when checking for ebreak cause --- rtl/cve2_controller.sv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/rtl/cve2_controller.sv b/rtl/cve2_controller.sv index 2db945c714..da8ab0c73c 100644 --- a/rtl/cve2_controller.sv +++ b/rtl/cve2_controller.sv @@ -313,8 +313,12 @@ module cve2_controller #( assign unused_irq_timer = irqs_i.irq_timer; + // Record the debug cause outside of the FSM + // The decision to enter debug_mode and the write of the cause to DCSR happen + // in seperate steps within the FSM. Hence, there are a small number of cycles + // where a change in external stimulus can cause the cause to be recorded incorrectly. assign debug_cause_d = trigger_match_i ? DBG_CAUSE_TRIGGER : - ebreak_into_debug ? DBG_CAUSE_EBREAK : + ebrk_insn_prio ? DBG_CAUSE_EBREAK : debug_req_i ? DBG_CAUSE_HALTREQ : do_single_step_d ? DBG_CAUSE_STEP : DBG_CAUSE_NONE ;