From 0d8830c5031447e4c76d3640eaea77351c356c50 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?St=C3=A9phane=20Chevigny?= Date: Sun, 4 Jun 2023 21:47:26 -0400 Subject: [PATCH 1/4] add support for de10_nano with mistral toolchain --- corescore.core | 25 +++++++++++++++- data/de10_nano_mistral.qsf | 14 +++++++++ rtl/corescore_de10_nano_mistral.v | 47 +++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 data/de10_nano_mistral.qsf create mode 100644 rtl/corescore_de10_nano_mistral.v diff --git a/corescore.core b/corescore.core index 885580a..3e1e0ea 100644 --- a/corescore.core +++ b/corescore.core @@ -132,7 +132,14 @@ filesets: - data/de10_nano.tcl: { file_type: tclSource } - rtl/de0_nano_clock_gen.v: { file_type: verilogSource } - rtl/corescore_de10_nano.v: { file_type: verilogSource } - + + de10_nano_mistral: + files: + - data/de10_nano_mistral.qsf : {file_type: QSF} + - rtl/corescore_emitter_uart.v: { file_type: verilogSource } + # - rtl/de10_nano_mistral_clock_gen.v: { file_type: verilogSource } + - rtl/corescore_de10_nano_mistral.v: { file_type: verilogSource } + de5_net: files: - data/de5_net.sdc: { file_type: SDC } @@ -498,6 +505,16 @@ targets: board_device_index : 2 toplevel: corescore_de10_nano + de10_nano_mistral: + default_tool: mistral + filesets: [rtl, de10_nano_mistral] + generate: [corescorecore_de10_nano_mistral] + tools: + mistral: + yosys_synth_options : [-family cyclonev -nodsp ] + device: 5CSEBA6U23I7 + toplevel: corescore_de10_nano_mistral + de5_net: default_tool: quartus filesets: [rtl, de5_net] @@ -851,11 +868,17 @@ generate: generator: corescorecore parameters: count: 61 + corescorecore_de10_nano: generator: corescorecore parameters: count: 271 + + corescorecore_de10_nano_mistral: + generator: corescorecore + parameters: + count: 60 corescorecore_de5_net: generator: corescorecore diff --git a/data/de10_nano_mistral.qsf b/data/de10_nano_mistral.qsf new file mode 100644 index 0000000..c5d701e --- /dev/null +++ b/data/de10_nano_mistral.qsf @@ -0,0 +1,14 @@ +set_location_assignment PIN_V11 -to i_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk + +#set_location_assignment PIN_W15 -to q +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q + +# GPIO0 Pin 1 +set_location_assignment PIN_Y15 -to o_uart_tx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_txd + +#KEY[0] +set_location_assignment PIN_AH17 -to i_rst_n +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_rst_n + diff --git a/rtl/corescore_de10_nano_mistral.v b/rtl/corescore_de10_nano_mistral.v new file mode 100644 index 0000000..5b6928c --- /dev/null +++ b/rtl/corescore_de10_nano_mistral.v @@ -0,0 +1,47 @@ + +module corescore_de10_nano_mistral + ( + input wire i_clk, + input wire i_rst_n, + output wire o_uart_tx); + + // wire clk; + // wire locked; + + //Create a 16MHz clock from 12MHz using PLL + // pll pll12 + // (.clock_in (i_clk), + // .clock_out (clk), + // .locked (locked)); + wire rst; + + assign rst = !i_rst_n; + + // always @(posedge clk) + // rst <= !locked; + + parameter memfile_emitter = "emitter.hex"; + + wire [7:0] tdata; + wire tlast; + wire tvalid; + wire tready; + + corescorecore corescorecore + (.i_clk (i_clk), + .i_rst (rst), + .o_tdata (tdata), + .o_tlast (tlast), + .o_tvalid (tvalid), + .i_tready (tready)); + + corescore_emitter_uart #(.clk_freq_hz (50_000_000)) emitter + (.i_clk (i_clk), + .i_rst (rst), + .i_data (tdata), + .i_valid (tvalid), + .o_ready (tready), + .o_uart_tx (o_uart_tx)); + +endmodule + From cc590e3ba7b5fbb65d0695ed2a098cc297902a16 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?St=C3=A9phane=20Chevigny?= Date: Sun, 4 Jun 2023 22:05:28 -0400 Subject: [PATCH 2/4] Remove reference of rtl/de10_nano_mistral_clock_gen.v in corescore.core --- corescore.core | 1 - 1 file changed, 1 deletion(-) diff --git a/corescore.core b/corescore.core index 3e1e0ea..f5f506e 100644 --- a/corescore.core +++ b/corescore.core @@ -137,7 +137,6 @@ filesets: files: - data/de10_nano_mistral.qsf : {file_type: QSF} - rtl/corescore_emitter_uart.v: { file_type: verilogSource } - # - rtl/de10_nano_mistral_clock_gen.v: { file_type: verilogSource } - rtl/corescore_de10_nano_mistral.v: { file_type: verilogSource } de5_net: From f786c3417441a88ac4e44fcdcce8610b337840a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?St=C3=A9phane=20Chevigny?= Date: Sat, 10 Jun 2023 16:01:02 -0400 Subject: [PATCH 3/4] Added clock divider to run soc at 12.5 MHz --- corescore.core | 3 ++- rtl/corescore_de10_nano_mistral.v | 30 ++++++++++++++++-------------- 2 files changed, 18 insertions(+), 15 deletions(-) diff --git a/corescore.core b/corescore.core index f5f506e..d64096d 100644 --- a/corescore.core +++ b/corescore.core @@ -511,6 +511,7 @@ targets: tools: mistral: yosys_synth_options : [-family cyclonev -nodsp ] + nextpnr_options: [--freq,12.5] device: 5CSEBA6U23I7 toplevel: corescore_de10_nano_mistral @@ -877,7 +878,7 @@ generate: corescorecore_de10_nano_mistral: generator: corescorecore parameters: - count: 60 + count: 74 corescorecore_de5_net: generator: corescorecore diff --git a/rtl/corescore_de10_nano_mistral.v b/rtl/corescore_de10_nano_mistral.v index 5b6928c..87805c7 100644 --- a/rtl/corescore_de10_nano_mistral.v +++ b/rtl/corescore_de10_nano_mistral.v @@ -5,21 +5,23 @@ module corescore_de10_nano_mistral input wire i_rst_n, output wire o_uart_tx); - // wire clk; - // wire locked; - - //Create a 16MHz clock from 12MHz using PLL - // pll pll12 - // (.clock_in (i_clk), - // .clock_out (clk), - // .locked (locked)); + + reg div_clk = 0; + reg counter = 0; + + + always@(posedge i_clk) begin + + counter <= counter + 1; + if(counter == 1) div_clk <= ~div_clk; + + end + + wire rst; assign rst = !i_rst_n; - // always @(posedge clk) - // rst <= !locked; - parameter memfile_emitter = "emitter.hex"; wire [7:0] tdata; @@ -28,15 +30,15 @@ module corescore_de10_nano_mistral wire tready; corescorecore corescorecore - (.i_clk (i_clk), + (.i_clk (div_clk), .i_rst (rst), .o_tdata (tdata), .o_tlast (tlast), .o_tvalid (tvalid), .i_tready (tready)); - corescore_emitter_uart #(.clk_freq_hz (50_000_000)) emitter - (.i_clk (i_clk), + corescore_emitter_uart #(.clk_freq_hz (12_500_000)) emitter + (.i_clk (div_clk), .i_rst (rst), .i_data (tdata), .i_valid (tvalid), From 2a4398341ee559f4510c750c1dd058c5b02730a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?St=C3=A9phane=20Chevigny?= Date: Mon, 31 Jul 2023 10:11:38 -0400 Subject: [PATCH 4/4] set 84 cores and update de10_nano_mistral.qsf --- corescore.core | 2 +- data/de10_nano_mistral.qsf | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/corescore.core b/corescore.core index d64096d..08892f6 100644 --- a/corescore.core +++ b/corescore.core @@ -878,7 +878,7 @@ generate: corescorecore_de10_nano_mistral: generator: corescorecore parameters: - count: 74 + count: 84 corescorecore_de5_net: generator: corescorecore diff --git a/data/de10_nano_mistral.qsf b/data/de10_nano_mistral.qsf index c5d701e..5501556 100644 --- a/data/de10_nano_mistral.qsf +++ b/data/de10_nano_mistral.qsf @@ -1,8 +1,6 @@ set_location_assignment PIN_V11 -to i_clk set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk -#set_location_assignment PIN_W15 -to q -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q # GPIO0 Pin 1 set_location_assignment PIN_Y15 -to o_uart_tx