Quick start example won't produce output

[AntonBabushkin]

Hi,
I am not able to successfully run a quick start example.
Could you please suggest what might be wrong.
Thanks.

Environment (Win10):

1. nmigen installed
2. Yosys (yosys-win32-mxebin-0.8.zip) installed
3. Minerva installed
4. Issue No module named 'jtagtap' #1 bypassed by commenting out missing module import and tap creation in file top.py

Execution log:

C:\Users\anton\OneDrive\Desktop\RISC-V\minerva>python build.py > minerva.v
Traceback (most recent call last):
File "build.py", line 48, in
main()
File "build.py", line 44, in main
print(verilog.convert(frag, name="minerva_cpu", ports=ports))
File "C:\Users\anton\AppData\Local\Programs\Python\Python37-32\lib\site-packages\nmigen\back\verilog.py", line 48, in convert
raise YosysError(error.strip())
nmigen.back.verilog.YosysError: ERROR: Parser error in line 5444: syntax error