From d6102c84bcb66e0a56b893c6b4337ece88d4a5d9 Mon Sep 17 00:00:00 2001
From: Fabian Beuke <mail@beuke.org>
Date: Mon, 30 Sep 2024 01:23:53 +0000
Subject: [PATCH 1/2] Merge pull request #9 from davidhcefx/patch-3

---
 .github/workflows/fetch.yml | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 .github/workflows/fetch.yml

diff --git a/.github/workflows/fetch.yml b/.github/workflows/fetch.yml
new file mode 100644
index 0000000000..c2c1ad4ae9
--- /dev/null
+++ b/.github/workflows/fetch.yml
@@ -0,0 +1,27 @@
+name: Fetch-upstream
+on:
+  schedule:
+  - cron: '0 0 * * 1'
+  workflow_dispatch:
+
+jobs:
+  fetch:
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v2
+      with:
+        fetch-depth: '5'
+
+    - name: Fetch upstream (dirty hacks)
+      run: |
+        mv .github .github~  # hide it from git
+        git reset --hard HEAD~3
+        git pull git://git.savannah.gnu.org/nano.git
+        mv .github~ .github
+
+    - name: Commit this script
+      run: |
+        git add .
+        git -c user.email='mail@beuke.org' -c user.name='Fabian Beuke' commit \
+          -m 'Merge pull request #9 from davidhcefx/patch-3'
+        git push --force

From 5ddb8aaea3f7c1ee1236554ecf6cd5100a9f46f1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nicol=C3=A1s=20Rivera?= <nico.a.rivera3@gmail.com>
Date: Mon, 30 Sep 2024 10:24:51 -0300
Subject: [PATCH 2/2] Create vhdl.nanorc

vhdl.nanorc file started at version 0.1.0
---
 syntax/vhdl.nanorc | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 syntax/vhdl.nanorc

diff --git a/syntax/vhdl.nanorc b/syntax/vhdl.nanorc
new file mode 100644
index 0000000000..b2df2f7895
--- /dev/null
+++ b/syntax/vhdl.nanorc
@@ -0,0 +1,36 @@
+## Syntax highlighting for VHDL.
+
+syntax vhdl "\.vhd$"
+header "library IEEE;"
+magic "VHDL"
+comment "--"
+
+# formatter
+# linter
+
+# Types.
+color cyan "\<(bit|bit_vector|character|boolean|integer|real|time|string)\>"
+color cyan "\<(severity_level|positive|natural|signed|unsigned|line|text)\>"
+color cyan "\<(std_logic|std_logic_vector|std_ulogic|std_ulogic_vector)\>"
+color cyan "\<(qsim_state|qsim_state_vector|qsim_12state|qsim_12state_vector|qsim_strength)\>"
+color cyan "\<(mux_bit|mux_vectory|reg_bit|reg_vector|wor_bit|wor_vector)\>"
+
+# Keywords.
+color orange "\<(access|after|alias|all|architecture|array|assert|attribute|begin|block|body)\>"
+color orange "\<(buffer|bus|case|component|configuration|constant|disconnect|downto)\>"
+color orange "\<(else|elsif|end|entity|exit|file|for|function|generate|generic|group)\>"
+color orange "\<(guarded|if|impure|in|inertial|inout|is|label|library|linkage|literal)\>"
+color orange "\<(loop|map|new|next|null|of|on|open|others|out|package|port|postponed)\>"
+color orange "\<(procedure|process|pure|range|record|register|reject|report|return)\>"
+color orange "\<(select|severity|signal|shared|subtype|then|to|transport|type|unaffected)\>"
+color orange "\<(units|until|use|variable|wait|when|while|with|note|warning|error|failure)\>"
+color orange "\<(and|nand|or|nor|xor|xnor|rol|ror|sla|sll|sra|srl|mod|rem|abs|not)\>"
+
+# Booleans.
+color red "\<(true|false)\>"
+
+# Strings
+color green ""([^"\]|\\.)*""
+
+# Comments.
+color yellow "--.*"