The assignment of the target register(s) of a branch instruction depends on the flags. The target register is only assigned if the branch is actually taken. The same applies to the flags if sf is true. So you may not abuse brr.never to load the relocated values of labels into a register - what a pity!
+The bkpt instruction is only mentioned once in the documentation, without further elaboration. It is intended to be + used with the V3D halt/run/step registers (see the addendum to section 10 below). This instruction puts the QPU in the + halt state in the same way as writing to the V3D halt register. + Unfortunately there doesn't seem to be a way to probe the QPU registers directly.
+In case you want to debug using breakpoints and the maximum ioctl timeout of 1 second is too short, it is recommended + to use the V3D QPU scheduler registers to schedule threads directly with unlimited run time. Keep in mind that this somewhat breaks + interrupts, as although the V3D_DBQITC register works as intended, it is quickly reset by the Linux kernel, so polling this register + at a high rate is required for reliable use of the host interrupt peripheral. Luckily, interrupts are no longer needed without + use of the mailbox interface.
+Care must be taken not to halt the QPU after the thrend instruction if the final two instructions still do work, such + as raising an interrupt. The thread end instruction starts a cleanup process that cannot be halted and the thread will be + terminated even if there are instructions left unexecuted. Additionally, since bkpt puts the QPU as a whole into a halt + state, it will remain halted even at the start of an eventual new thread.
The handling of Inf and NaN seems to be broken or just not implemented in Videocore IV. I.e. 0.0 + NaN = +Inf. In fact it only seems to support something like NaN but it uses the binary representation of ±Inf. @@ -186,6 +201,98 @@
The following tables contain the definitions for some of the undocumented registers.
+| V3D_DBQRUN - QPU Run Control | +||||
|---|---|---|---|---|
| Bit(s) | +Field name | +Description | +Type | +Reset | +
| 31:16 | +- | +Reserved | ++ | + |
| 15:0 | +RUN_QPU0_to_RUN_QPU15 | +QPU Run bits; reads 1 if QPU is running, write 1 to resume QPU if halted | +R/W | +1 | +
| V3D_DBQHLT - QPU Halt Control | +||||
|---|---|---|---|---|
| Bit(s) | +Field name | +Description | +Type | +Reset | +
| 31:16 | +- | +Reserved | ++ | + |
| 15:0 | +HLT_QPU0_to_HLT_QPU15 | +QPU Halt bits; reads 1 if QPU is halted, write 1 to halt QPU if running | +R/W | +0 | +
| V3D_DBQSTP - QPU Instruction Step Control | +||||
|---|---|---|---|---|
| Bit(s) | +Field name | +Description | +Type | +Reset | +
| 31:16 | +- | +Reserved | ++ | + |
| 15:0 | +STP_QPU0_to_STP_QPU15 | +QPU Step bits; write 1 while halted to advance the QPU program state by one instruction | +W | +0 | +
The documentation of the V3D_PCTRE register is wrong. You need to set bit 31 (allegedly reserved) to enable performance counters at all.