diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..99d88ee --- /dev/null +++ b/.gitattributes @@ -0,0 +1,3 @@ +# Auto detect text files and perform LF normalization +* text=auto +*.sh text eol=lf diff --git a/Makefile b/Makefile index 7df8171..93e178f 100644 --- a/Makefile +++ b/Makefile @@ -7,7 +7,7 @@ CROSS_COMPILE=arm-linux-gnueabihf- OUTPUT_DIR=$(CURDIR)/output BUILD_PATH=$(CURDIR)/build ROOTFS=$(CURDIR)/rootfs.img -Q= +Q=@ J=$(shell expr `grep ^processor /proc/cpuinfo | wc -l` \* 2) include chosen_board.mk @@ -26,7 +26,7 @@ clean: rm -rf $(BUILD_PATH) ## patch -patch: linux-sunxi/.git +patch: linux-sunxi/.git u-boot-sunxi/.git $(Q)$(CURDIR)/apply_patch.sh $(Q)rm -f $(K_DOT_CONFIG) @@ -100,15 +100,16 @@ endif libs: cedarx-libs/.git update: - $(Q)git stash - $(Q)git pull --rebase - $(Q)git submodule -q init - $(Q)git submodule -q foreach git stash save -q --include-untracked "make update stash" - -$(Q)git submodule -q foreach git fetch -q - -$(Q)git submodule -q foreach "git rebase origin HEAD || :" - -$(Q)git submodule -q foreach "git stash pop -q || :" - -$(Q)git stash pop -q - $(Q)git submodule status + $(Q)git pull +# $(Q)git stash +# $(Q)git pull --rebase +# $(Q)git submodule -q init +# $(Q)git submodule -q foreach git stash save -q --include-untracked "make update stash" +# -$(Q)git submodule -q foreach git fetch -q +# -$(Q)git submodule -q foreach "git rebase origin HEAD || :" +# -$(Q)git submodule -q foreach "git stash pop -q || :" +# -$(Q)git stash pop -q +# $(Q)git submodule status %/.git: $(Q)git submodule init diff --git a/allwinner-tools/livesuit/a20/default/env.cfg b/allwinner-tools/livesuit/a20/default/env.cfg index c8c0698..e2b493d 100755 --- a/allwinner-tools/livesuit/a20/default/env.cfg +++ b/allwinner-tools/livesuit/a20/default/env.cfg @@ -8,8 +8,8 @@ mmc_root=/dev/mmcblk0p7 init=/init loglevel=8 #set kernel cmdline if boot.img or recovery.img has no cmdline we will use this -setargs_nand=setenv bootargs console=${console} root=${nand_root} init=${init} loglevel=${loglevel} partitions=${partitions} -setargs_mmc=setenv bootargs console=${console} root=${mmc_root} init=${init} loglevel=${loglevel} partitions=${partitions} +setargs_nand=setenv bootargs coherent_pool=2M console=${console} root=${nand_root} init=${init} loglevel=${loglevel} partitions=${partitions} +setargs_mmc=setenv bootargs coherent_pool=2M console=${console} root=${mmc_root} init=${init} loglevel=${loglevel} partitions=${partitions} #nand command syntax: sunxi_flash read address partition_name read_bytes #0x40007800 = 0x40008000(kernel entry) - 0x800(boot.img header 2k) #boot_normal=sunxi_flash read 40007800 boot;boota 40007800 diff --git a/allwinner-tools/livesuit/a20/default/sys_partition.fex b/allwinner-tools/livesuit/a20/default/sys_partition.fex index 300593d..0584a3e 100755 --- a/allwinner-tools/livesuit/a20/default/sys_partition.fex +++ b/allwinner-tools/livesuit/a20/default/sys_partition.fex @@ -42,7 +42,7 @@ size = 16384 ;------------------------------>mmcblk0p5/nandb [partition] name = env - size = 4096 + size = 32768 downloadfile = "env.fex" verify = 1 ;------------------------------>mmcblk0p6/nandc @@ -52,12 +52,3 @@ size = 16384 downloadfile = "boot.fex" verify = 1 -[partition] - name = rootfs - size = 3686400 - downloadfile = "rootfs.fex" - verify = 1 - -[partition] - name = private - size = 4096 diff --git a/allwinner-tools/livesuit/a20/eFex/usb/fed_nand.axf b/allwinner-tools/livesuit/a20/eFex/usb/fed_nand.axf index 973d528..2f3b21e 100755 Binary files a/allwinner-tools/livesuit/a20/eFex/usb/fed_nand.axf and b/allwinner-tools/livesuit/a20/eFex/usb/fed_nand.axf differ diff --git a/allwinner-tools/livesuit/a20/eFex/usb/fes.fex b/allwinner-tools/livesuit/a20/eFex/usb/fes.fex index 520cac6..fb84463 100755 Binary files a/allwinner-tools/livesuit/a20/eFex/usb/fes.fex and b/allwinner-tools/livesuit/a20/eFex/usb/fes.fex differ diff --git a/allwinner-tools/livesuit/a20/eFex/usb/hw_scan.axf b/allwinner-tools/livesuit/a20/eFex/usb/hw_scan.axf index 47c84bd..59081cd 100755 Binary files a/allwinner-tools/livesuit/a20/eFex/usb/hw_scan.axf and b/allwinner-tools/livesuit/a20/eFex/usb/hw_scan.axf differ diff --git a/allwinner-tools/livesuit/a20/eFex/usb/toolsb.fex b/allwinner-tools/livesuit/a20/eFex/usb/toolsb.fex index 4e9aa5c..c3c6549 100755 Binary files a/allwinner-tools/livesuit/a20/eFex/usb/toolsb.fex and b/allwinner-tools/livesuit/a20/eFex/usb/toolsb.fex differ diff --git a/allwinner-tools/livesuit/a20/eFex/usb/update_boot0.axf b/allwinner-tools/livesuit/a20/eFex/usb/update_boot0.axf index f82f52d..d1a5132 100755 Binary files a/allwinner-tools/livesuit/a20/eFex/usb/update_boot0.axf and b/allwinner-tools/livesuit/a20/eFex/usb/update_boot0.axf differ diff --git a/allwinner-tools/livesuit/a20/eFex/usb/update_boot1.axf b/allwinner-tools/livesuit/a20/eFex/usb/update_boot1.axf index 7fd7042..607a983 100755 Binary files a/allwinner-tools/livesuit/a20/eFex/usb/update_boot1.axf and b/allwinner-tools/livesuit/a20/eFex/usb/update_boot1.axf differ diff --git a/allwinner-tools/livesuit/a20/eGon/boot1_nand.bin b/allwinner-tools/livesuit/a20/eGon/boot1_nand.bin index fd98f23..b305b53 100755 Binary files a/allwinner-tools/livesuit/a20/eGon/boot1_nand.bin and b/allwinner-tools/livesuit/a20/eGon/boot1_nand.bin differ diff --git a/allwinner-tools/livesuit/a20/eGon/boot1_sdcard.bin b/allwinner-tools/livesuit/a20/eGon/boot1_sdcard.bin index 00129f3..e474805 100755 Binary files a/allwinner-tools/livesuit/a20/eGon/boot1_sdcard.bin and b/allwinner-tools/livesuit/a20/eGon/boot1_sdcard.bin differ diff --git a/allwinner-tools/livesuit/a20/mod_update/script_parse b/allwinner-tools/livesuit/a20/mod_update/script_parse index 27ef1f7..f6c24fd 100755 --- a/allwinner-tools/livesuit/a20/mod_update/script_parse +++ b/allwinner-tools/livesuit/a20/mod_update/script_parse @@ -240,8 +240,8 @@ def check_part_name_valid(name): def check_part_size_valid(size): if not size.isdigit(): return (False, "invalid partition size, must be decimal base digit, unit: 512Bytes") -# if int(size) % 32768: -# return (False, "invalid partition size, must 16MB align, unit: 512Bytes") + if int(size) % 32768: + return (False, "invalid partition size, must 16MB align, unit: 512Bytes") return (True, "valid") def check_part_keydata_valid(keydata): @@ -318,7 +318,7 @@ def check_part_config(conf_lines): if int(value) % 16384: error_msg("L%d: %s" % (i+1, line)) error_msg("invalid partition size, must 16MB align, unit: KB") - #return False + return False elif cmp(mainkey, "partition_start") == 0: error_msg("L%d: %s" % (i+1, line)) diff --git a/allwinner-tools/livesuit/a20/mod_update/signature b/allwinner-tools/livesuit/a20/mod_update/signature new file mode 100755 index 0000000..67837a0 Binary files /dev/null and b/allwinner-tools/livesuit/a20/mod_update/signature differ diff --git a/allwinner-tools/livesuit/a20/mod_update/simg b/allwinner-tools/livesuit/a20/mod_update/simg new file mode 100755 index 0000000..12c5b13 Binary files /dev/null and b/allwinner-tools/livesuit/a20/mod_update/simg differ diff --git a/allwinner-tools/livesuit/a20/wboot/bootfs/boot.ini b/allwinner-tools/livesuit/a20/wboot/bootfs/boot.ini index d51995a..61881a8 100755 --- a/allwinner-tools/livesuit/a20/wboot/bootfs/boot.ini +++ b/allwinner-tools/livesuit/a20/wboot/bootfs/boot.ini @@ -3,6 +3,7 @@ start_os_name = linux timeout = -1 display_device= 0 display_mode = 0 +erase_flash=1 [linux] diff --git a/allwinner-tools/livesuit/a20/wboot/bootfs/boot_lvds.axf b/allwinner-tools/livesuit/a20/wboot/bootfs/boot_lvds.axf new file mode 100755 index 0000000..2acedb3 Binary files /dev/null and b/allwinner-tools/livesuit/a20/wboot/bootfs/boot_lvds.axf differ diff --git a/allwinner-tools/livesuit/a20/wboot/bootfs/boot_signature.axf b/allwinner-tools/livesuit/a20/wboot/bootfs/boot_signature.axf new file mode 100755 index 0000000..506ed50 Binary files /dev/null and b/allwinner-tools/livesuit/a20/wboot/bootfs/boot_signature.axf differ diff --git a/allwinner-tools/livesuit/a20/wboot/bootfs/drv_de.drv b/allwinner-tools/livesuit/a20/wboot/bootfs/drv_de.drv index d884b6f..caa9504 100755 Binary files a/allwinner-tools/livesuit/a20/wboot/bootfs/drv_de.drv and b/allwinner-tools/livesuit/a20/wboot/bootfs/drv_de.drv differ diff --git a/allwinner-tools/livesuit/a20/wboot/bootfs/drv_de_lvds.drv b/allwinner-tools/livesuit/a20/wboot/bootfs/drv_de_lvds.drv new file mode 100755 index 0000000..9c5cf47 Binary files /dev/null and b/allwinner-tools/livesuit/a20/wboot/bootfs/drv_de_lvds.drv differ diff --git a/allwinner-tools/livesuit/a20/wboot/bootfs/os_show/bootlogo.bmp b/allwinner-tools/livesuit/a20/wboot/bootfs/os_show/bootlogo.bmp index 73ca570..f02aa4d 100755 Binary files a/allwinner-tools/livesuit/a20/wboot/bootfs/os_show/bootlogo.bmp and b/allwinner-tools/livesuit/a20/wboot/bootfs/os_show/bootlogo.bmp differ diff --git a/allwinner-tools/livesuit/a20/wboot/bootfs/prvt.axf b/allwinner-tools/livesuit/a20/wboot/bootfs/prvt.axf index 40f4bd5..104a582 100755 Binary files a/allwinner-tools/livesuit/a20/wboot/bootfs/prvt.axf and b/allwinner-tools/livesuit/a20/wboot/bootfs/prvt.axf differ diff --git a/allwinner-tools/livesuit/a20/wboot/bootfs/sprite.axf b/allwinner-tools/livesuit/a20/wboot/bootfs/sprite.axf index affb8f7..072c427 100755 Binary files a/allwinner-tools/livesuit/a20/wboot/bootfs/sprite.axf and b/allwinner-tools/livesuit/a20/wboot/bootfs/sprite.axf differ diff --git a/allwinner-tools/livesuit/default/sys_config_linux.fex b/allwinner-tools/livesuit/default/sys_config_linux.fex index f9cdf5b..cfad456 100644 --- a/allwinner-tools/livesuit/default/sys_config_linux.fex +++ b/allwinner-tools/livesuit/default/sys_config_linux.fex @@ -8,8 +8,8 @@ pid =0x02000000 sid =0x02000100 bid =0x80 -eraseflag = 0 -jtag = 1 +eraseflag = 1 +jtag = 0 [fex_misc] @@ -62,7 +62,7 @@ num = 4 class_name = DISK name = env size_hi = 0 - size_lo = 2048 + size_lo = 32768 user_type = 0 ro = 0 @@ -70,15 +70,7 @@ num = 4 class_name = DISK name = boot size_hi = 0 - size_lo = 16384 - user_type = 0 - ro = 0 - -[partition3] - class_name = DISK - name = rootfs - size_hi = 0 - size_lo = 1843200 + size_lo = 32768 user_type = 0 ro = 0 @@ -120,8 +112,3 @@ part_name = boot pkt_name = KERNEL_000000000 encrypt = 0 -[download3] -part_name = rootfs -pkt_name = ROOTFS_000000000 -encrypt = 0 - diff --git a/configure b/configure index e3c2d7e..fa74034 100755 --- a/configure +++ b/configure @@ -41,9 +41,13 @@ generate_board_mk() { EOT ;; a20) + KERNEL_CONFIG=sun7i${android:+_nuclear}_defconfig + if [ -f patch/linux-sunxi/arch/arm/configs/${board}_defconfig ]; then + KERNEL_CONFIG=${board}_defconfig + fi cat <<-EOT MACH=sun7i - KERNEL_CONFIG=sun7i${android:+_nuclear}_defconfig + KERNEL_CONFIG=${KERNEL_CONFIG} EOT ;; *) diff --git a/linux-sunxi b/linux-sunxi index a7350cb..0c92978 160000 --- a/linux-sunxi +++ b/linux-sunxi @@ -1 +1 @@ -Subproject commit a7350cb6a9ec1aae510e26cdc730f05f12e13f9f +Subproject commit 0c92978520e9576a0631da949c13e79bae846494 diff --git a/patch/linux-sunxi/arch/arm/configs/pcduino3_nano_defconfig b/patch/linux-sunxi/arch/arm/configs/pcduino3_nano_defconfig new file mode 100644 index 0000000..6cb9e7e --- /dev/null +++ b/patch/linux-sunxi/arch/arm/configs/pcduino3_nano_defconfig @@ -0,0 +1,3064 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.4.79 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_KTIME_SCALAR=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_LOCKBREAK=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_NEED_MACH_IO_H=y +CONFIG_NEED_MACH_MEMORY_H=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y +CONFIG_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="+" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_FHANDLE=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_WATCH=y +CONFIG_AUDIT_TREE=y +CONFIG_AUDIT_LOGINUID_IMMUTABLE=y +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y +# CONFIG_IRQ_DOMAIN_DEBUG is not set + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +CONFIG_RCU_FAST_NO_HZ=y +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +# CONFIG_CGROUP_MEM_RES_CTLR is not set +# CONFIG_CGROUP_PERF is not set +# CONFIG_CGROUP_SCHED is not set +CONFIG_BLK_CGROUP=y +# CONFIG_DEBUG_BLK_CGROUP is not set +# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="../../linux-sunxi/rootfs/sun7i_rootfs.cpio.xz" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +CONFIG_INITRAMFS_COMPRESSION_XZ=y +# CONFIG_INITRAMFS_COMPRESSION_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_PANIC_TIMEOUT=0 +CONFIG_EXPERT=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +CONFIG_PERF_COUNTERS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_BSGLIB is not set +CONFIG_BLK_DEV_INTEGRITY=y +# CONFIG_BLK_DEV_THROTTLING is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_SUNXI_NAND_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_CFQ_GROUP_IOSCHED=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_SUN4I is not set +# CONFIG_ARCH_SUN5I is not set +CONFIG_ARCH_SUN7I=y +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set + +# +# System MMU +# + +# +# Allwinner's sunxi options +# +CONFIG_SUNXI_MULTIPLATFORM=y +CONFIG_SUNXI_SCALING_MIN=60 +CONFIG_PLAT_SUNXI=y + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARCH_HAS_BARRIERS=y +CONFIG_ARM_NR_BANKS=8 +CONFIG_CPU_HAS_PMU=y +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +# CONFIG_ARM_ERRATA_742230 is not set +# CONFIG_ARM_ERRATA_742231 is not set +# CONFIG_ARM_ERRATA_720789 is not set +# CONFIG_ARM_ERRATA_743622 is not set +# CONFIG_ARM_ERRATA_751472 is not set +# CONFIG_ARM_ERRATA_754322 is not set +# CONFIG_ARM_ERRATA_754327 is not set +# CONFIG_ARM_ERRATA_764369 is not set +# CONFIG_ARM_ERRATA_775420 is not set +CONFIG_ARM_GIC=y +# CONFIG_FIQ_DEBUGGER is not set + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_SMT is not set +CONFIG_HAVE_ARM_SCU=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_HAVE_ARM_TWD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=2 +CONFIG_HOTPLUG_CPU=y +CONFIG_LOCAL_TIMERS=y +CONFIG_ARCH_NR_GPIO=0 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HW_PERF_EVENTS=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +# CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="console=ttyS0,115200" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +# CONFIG_AUTO_ZRELADDR is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +CONFIG_HAS_WAKELOCK=y +CONFIG_WAKELOCK=y +# CONFIG_PM_RUNTIME is not set +# CONFIG_SUSPEND_TIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_TUNNEL=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_ANDROID_PARANOID_NETWORK is not set +CONFIG_NET_ACTIVITY_STATS=y +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_ACCT is not set +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_SECMARK is not set +CONFIG_NF_CONNTRACK_PROCFS=y +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CT_PROTO_UDPLITE is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +# CONFIG_NF_CONNTRACK_FTP is not set +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +# CONFIG_NF_CT_NETLINK is not set +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +# CONFIG_NETFILTER_XT_MARK is not set +# CONFIG_NETFILTER_XT_CONNMARK is not set + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +# CONFIG_NETFILTER_XT_TARGET_LOG is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +CONFIG_NETFILTER_XT_MATCH_ECN=y +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +CONFIG_NETFILTER_XT_MATCH_HL=y +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_IPVS is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA2 is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +CONFIG_IP_VS=y +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +# CONFIG_IP_VS_PROTO_TCP is not set +# CONFIG_IP_VS_PROTO_UDP is not set +# CONFIG_IP_VS_PROTO_AH_ESP is not set +# CONFIG_IP_VS_PROTO_ESP is not set +# CONFIG_IP_VS_PROTO_AH is not set +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +# CONFIG_IP_VS_RR is not set +# CONFIG_IP_VS_WRR is not set +# CONFIG_IP_VS_LC is not set +# CONFIG_IP_VS_WLC is not set +# CONFIG_IP_VS_LBLC is not set +# CONFIG_IP_VS_LBLCR is not set +# CONFIG_IP_VS_DH is not set +# CONFIG_IP_VS_SH is not set +# CONFIG_IP_VS_SED is not set +# CONFIG_IP_VS_NQ is not set + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS application helper +# +# CONFIG_IP_VS_NFCT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_RPFILTER=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_NF_NAT_FTP is not set +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y + +# +# IPv6: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV6 is not set +# CONFIG_NF_CONNTRACK_IPV6 is not set +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=y +CONFIG_GARP=y +CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +CONFIG_VLAN_8021Q_GVRP=y +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_RPS is not set +CONFIG_XPS=y +# CONFIG_NETPRIO_CGROUP is not set +CONFIG_BQL=y +CONFIG_HAVE_BPF_JIT=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=y +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=y +CONFIG_BT_HCIBTSDIO=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set +# CONFIG_CFG80211_ALLOW_RECONNECT is not set +# CONFIG_MAC80211 is not set +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_REGULATOR=m +CONFIG_RFKILL_GPIO=m +CONFIG_SUNXI_RFKILL=y +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +CONFIG_NFC=m +CONFIG_NFC_NCI=m +CONFIG_NFC_LLCP=y + +# +# Near Field Communication (NFC) devices +# +CONFIG_PN544_NFC=m +CONFIG_NFC_PN533=m + +# +# Device Drivers +# + +# +# hardware lib support +# +CONFIG_HARDWARE_LIB=y +CONFIG_HARDWARE_LIB_UTIL=m +CONFIG_HARDWARE_LIB_ADC=m +CONFIG_HARDWARE_LIB_GPIO=m +CONFIG_HARDWARE_LIB_PWM=m +CONFIG_HARDWARE_LIB_INTERRUPT=m +CONFIG_HARDWARE_LIB_SPI=y +CONFIG_HARDWARE_LIB_I2C=y +CONFIG_SUNXI_DVI_FIX=y +# CONFIG_HARDWARE_LIB_ROOTFS is not set +CONFIG_HARDWARE_LIB_KEYPAD=m +CONFIG_RTXX7X_SW=m + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_SYNC is not set +# CONFIG_CMA is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_CRYPTOLOOP=y +# CONFIG_BLK_DEV_DRBD is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=2 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_BLK_DEV_RBD is not set +CONFIG_SUNXI_NAND=y +CONFIG_SUNXI_NAND_COMPAT_DEV=y +# CONFIG_SUNXI_NAND_TEST is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_SUN4I_VIBRATOR is not set +# CONFIG_SUNXI_DBGREG is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_SUNXI_PWM is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_SENSORS_AK8975 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_UID_STAT is not set +# CONFIG_BMP085 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_WL127X_RFKILL is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_IWMC3200TOP is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_SR_VENDOR=y +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_ATA_VERBOSE_ERROR is not set +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +# CONFIG_SATA_AHCI_PLATFORM is not set +CONFIG_SW_SATA_AHCI_PLATFORM=y +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +# CONFIG_SATA_MV is not set + +# +# PATA SFF controllers with BMDMA +# + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_PLATFORM is not set + +# +# Generic fallback / legacy drivers +# +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +CONFIG_MII=y +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +CONFIG_TUN=y +# CONFIG_VETH is not set + +# +# CAIF transport drivers +# +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_SUNXI_EMAC=m +CONFIG_SUNXI_GMAC=y +CONFIG_GMAC_SCRIPT_SYS=y +CONFIG_GMAC_CLK_SYS=y +CONFIG_GMAC_RING=y +# CONFIG_GMAC_CHAINED is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MICREL_KS8995MA is not set +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=m +CONFIG_PPPOLAC=m +CONFIG_PPPOPNS=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +# CONFIG_SLIP is not set +CONFIG_SLHC=m + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_WIFI_CONTROL_FUNC is not set +# CONFIG_ATH_COMMON is not set +# CONFIG_BCMDHD is not set +# CONFIG_BRCMFMAC is not set +# CONFIG_BCM4330 is not set +# CONFIG_HOSTAP is not set +# CONFIG_IWM is not set +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set +CONFIG_RTL8192CU_SW=m +CONFIG_RTL8188EU=m +# CONFIG_RTL8189ES is not set +# CONFIG_RTL8723AS is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +CONFIG_WAN=y +# CONFIG_HDLC is not set +# CONFIG_DLCI is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +CONFIG_INPUT_KEYRESET=y + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_SUN4IKEYPAD is not set +# CONFIG_KEYBOARD_SUN4I_KEYBOARD is not set +# CONFIG_KEYBOARD_HV2605_KEYBOARD is not set +CONFIG_IR_SUNXI=m +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +CONFIG_INPUT_JOYSTICK=y +# CONFIG_JOYSTICK_ANALOG is not set +# CONFIG_JOYSTICK_A3D is not set +# CONFIG_JOYSTICK_ADI is not set +# CONFIG_JOYSTICK_COBRA is not set +# CONFIG_JOYSTICK_GF2K is not set +# CONFIG_JOYSTICK_GRIP is not set +# CONFIG_JOYSTICK_GRIP_MP is not set +# CONFIG_JOYSTICK_GUILLEMOT is not set +# CONFIG_JOYSTICK_INTERACT is not set +# CONFIG_JOYSTICK_SIDEWINDER is not set +# CONFIG_JOYSTICK_TMDC is not set +# CONFIG_JOYSTICK_IFORCE is not set +# CONFIG_JOYSTICK_WARRIOR is not set +# CONFIG_JOYSTICK_MAGELLAN is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_STINGER is not set +# CONFIG_JOYSTICK_TWIDJOY is not set +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JOYSTICK_AS5011 is not set +# CONFIG_JOYSTICK_JOYDUMP is not set +# CONFIG_JOYSTICK_XPAD is not set +CONFIG_INPUT_TABLET=y +# CONFIG_TABLET_USB_ACECAD is not set +# CONFIG_TABLET_USB_AIPTEK is not set +# CONFIG_TABLET_USB_GTCO is not set +# CONFIG_TABLET_USB_HANWANG is not set +# CONFIG_TABLET_USB_KBTAB is not set +# CONFIG_TABLET_USB_WACOM is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_GT801 is not set +# CONFIG_TOUCHSCREEN_GT811 is not set +# CONFIG_TOUCHSCREEN_GT818 is not set +# CONFIG_TOUCHSCREEN_SUN4I_TS is not set +# CONFIG_TOUCHSCREEN_FT5X_TS is not set +# CONFIG_TOUCHSCREEN_ZT8031 is not set +# CONFIG_TOUCHSCREEN_COASIA is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MPU3050 is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYCHORD is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_GPIO is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_CMA3000 is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set +CONFIG_GSENSOR=y +# CONFIG_SENSORS_BMA250 is not set +# CONFIG_MEMSIC_ECOMPASS is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +CONFIG_DEVKMEM=y +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_SUNXI=y +CONFIG_SERIAL_8250_NR_UARTS=8 +CONFIG_SERIAL_8250_RUNTIME_UARTS=8 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_DCC_TTY is not set +# CONFIG_RAMOOPS is not set +CONFIG_SUNXI_G2D=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=y +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +CONFIG_I2C_SUNXI=y +# CONFIG_SUNXI_IIC_PRINT_TRANSFER_INFO is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX_PCI is not set +CONFIG_SPI_SUNXI=y +# CONFIG_SUNXI_SPI_NDMA is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_SUNXI is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +CONFIG_AW_AXP=y +# CONFIG_AW_AXP18 is not set +# CONFIG_AW_AXP19 is not set +CONFIG_AW_AXP20=y +CONFIG_AXP_CHARGEINIT=y +CONFIG_AXP_CHGCHANGE=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_AXP152 is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MPCORE_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_RC5T583 is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +CONFIG_RC_CORE=y +CONFIG_LIRC=y +CONFIG_RC_MAP=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +CONFIG_IR_RC5_SZ_DECODER=y +CONFIG_IR_SANYO_DECODER=y +CONFIG_IR_MCE_KBD_DECODER=y +CONFIG_IR_LIRC_CODEC=y +# CONFIG_RC_ATI_REMOTE is not set +# CONFIG_IR_IMON is not set +# CONFIG_IR_MCEUSB is not set +# CONFIG_IR_REDRAT3 is not set +# CONFIG_IR_STREAMZAP is not set +# CONFIG_RC_LOOPBACK is not set +# CONFIG_IR_GPIO_CIR is not set +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA827X=y +CONFIG_MEDIA_TUNER_TDA18271=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_XC4000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_VMALLOC=m +CONFIG_VIDEOBUF_DMA_CONTIG=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_VIDEO_TUNER=m +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_VMALLOC=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_IR_I2C=y + +# +# Audio decoders, processors and mixers +# +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_WM8775=m + +# +# RDS decoders +# + +# +# Video decoders +# +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TVP5150=m + +# +# Video and audio decoders +# +CONFIG_VIDEO_CX25840=m + +# +# MPEG video encoders +# +CONFIG_VIDEO_CX2341X=m + +# +# Video encoders +# + +# +# Camera sensor devices +# +CONFIG_VIDEO_MT9V011=m + +# +# Flash devices +# + +# +# Video improvement chips +# + +# +# Miscelaneous helper chips +# +CONFIG_VIDEO_VIVI=m +CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_USBVISION=m +CONFIG_USB_ET61X251=m +CONFIG_USB_SN9C102=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_VIDEO_CPIA2=m +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_V4L_PLATFORM_DRIVERS=y +# CONFIG_SOC_CAMERA is not set +CONFIG_V4L_MEM2MEM_DRIVERS=y +# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set +CONFIG_VIDEO_SUNXI_CEDAR=y +CONFIG_VIDEO_DECODER_SUNXI=y +CONFIG_VIDEO_AVS_COUNTER=y +CONFIG_VIDEO_CSI_SUN4I=y +CONFIG_CSI_DEV_SEL=m +CONFIG_CSI0_SUN4I=m +CONFIG_CSI1_SUN4I=m +CONFIG_CSI_OV7670=m +CONFIG_CSI_GT2005=m +CONFIG_CSI_GC0308=m +CONFIG_CSI_GC2035=m +CONFIG_CSI_HI704=m +CONFIG_CSI_SP0838=m +CONFIG_CSI_MT9M112=m +CONFIG_CSI_MT9M113=m +CONFIG_CSI_OV2655=m +CONFIG_CSI_HI253=m +CONFIG_CSI_MT9D112=m +CONFIG_CSI_GC0307=m +CONFIG_CSI_OV5640=m +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_SI470X is not set +# CONFIG_USB_MR800 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_I2C_SI4713 is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_KEENE is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_RADIO_WL1273 is not set + +# +# Texas Instruments WL128x FM driver (ST based) +# +# CONFIG_RADIO_WL128X is not set +CONFIG_AUDIO_ENGINE=y +CONFIG_ACE_CONFIG=y +CONFIG_PA_CONTROL=y +CONFIG_PA_CONFIG=y + +# +# Graphics support +# +CONFIG_DRM=m +CONFIG_DRM_MALI=m +# CONFIG_DRM_UDL is not set +# CONFIG_ION is not set +CONFIG_MALI=m +CONFIG_MALI400=m +# CONFIG_MALI400_DEBUG is not set +# CONFIG_MALI400_GPU_UTILIZATION is not set +CONFIG_UMP=m +CONFIG_UMP_DEBUG=y +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +CONFIG_FB_SYS_FILLRECT=m +CONFIG_FB_SYS_COPYAREA=m +CONFIG_FB_SYS_IMAGEBLIT=m +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=m +# CONFIG_FB_WMT_GE_ROPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_SUNXI=y +CONFIG_FB_SUNXI_RESERVED_MEM=y +CONFIG_FB_SUNXI_UMP=y +CONFIG_FB_SUNXI_LCD=y +CONFIG_FB_SUNXI_HDMI=y +# CONFIG_HDMI_CEC is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_EXYNOS_VIDEO is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=m +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LP855X is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +CONFIG_FONT_PEARL_8x8=y +CONFIG_FONT_ACORN_8x8=y +CONFIG_FONT_MINI_4x6=y +CONFIG_FONT_SUN8x16=y +CONFIG_FONT_SUN12x22=y +CONFIG_FONT_10x18=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +# CONFIG_SND_ARMAACI is not set +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_SOC=y +CONFIG_SOUND_SUNXI=y +CONFIG_SND_SUNXI_SOC_CODEC=y +CONFIG_SND_SUNXI_SOC_HDMIAUDIO=y +# CONFIG_SND_SUNXI_SOC_SPDIF is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +CONFIG_HIDRAW=y +# CONFIG_UHID is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=m +CONFIG_HID_BELKIN=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELECOM=m +CONFIG_HID_EZKEY=m +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +CONFIG_HID_KEYTOUCH=y +CONFIG_HID_KYE=y +CONFIG_HID_UCLOGIC=y +CONFIG_HID_WALTOP=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PRIMAX=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_GREENASIA=m +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_WACOM=m +CONFIG_HID_WACOM_POWER_SUPPLY=y +CONFIG_HID_WIIMOTE=m +CONFIG_HID_WIIMOTE_EXT=y +CONFIG_HID_ZEROPLUS=m +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=m +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB_ARCH_HAS_XHCI is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_U132_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +CONFIG_USB_SUNXI_EHCI=y +CONFIG_USB_SUNXI_OHCI=y +CONFIG_USB_SUNXI_COMMON=y +CONFIG_USB_SW_SUNXI_HCD0=y +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_RENESAS_USBHS is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_STORAGE_ENE_UB6250=y +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_EZUSB=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRCABLE=y +CONFIG_USB_SERIAL_ARK3116=y +CONFIG_USB_SERIAL_BELKIN=y +CONFIG_USB_SERIAL_CH341=y +CONFIG_USB_SERIAL_WHITEHEAT=y +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=y +CONFIG_USB_SERIAL_CP210X=y +CONFIG_USB_SERIAL_CYPRESS_M8=y +CONFIG_USB_SERIAL_EMPEG=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_FUNSOFT=y +CONFIG_USB_SERIAL_VISOR=y +CONFIG_USB_SERIAL_IPAQ=y +CONFIG_USB_SERIAL_IR=y +CONFIG_USB_SERIAL_EDGEPORT=y +CONFIG_USB_SERIAL_EDGEPORT_TI=y +CONFIG_USB_SERIAL_F81232=y +CONFIG_USB_SERIAL_GARMIN=y +CONFIG_USB_SERIAL_IPW=y +CONFIG_USB_SERIAL_IUU=y +CONFIG_USB_SERIAL_KEYSPAN_PDA=y +CONFIG_USB_SERIAL_KEYSPAN=y +CONFIG_USB_SERIAL_KLSI=y +CONFIG_USB_SERIAL_KOBIL_SCT=y +CONFIG_USB_SERIAL_MCT_U232=y +CONFIG_USB_SERIAL_METRO=y +CONFIG_USB_SERIAL_MOS7720=y +CONFIG_USB_SERIAL_MOS7840=y +CONFIG_USB_SERIAL_MOTOROLA=y +CONFIG_USB_SERIAL_NAVMAN=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_OTI6858=y +CONFIG_USB_SERIAL_QCAUX=y +CONFIG_USB_SERIAL_QUALCOMM=y +CONFIG_USB_SERIAL_SPCP8X5=y +CONFIG_USB_SERIAL_HP4X=y +CONFIG_USB_SERIAL_SAFE=y +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIEMENS_MPI=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=y +CONFIG_USB_SERIAL_SYMBOL=y +CONFIG_USB_SERIAL_TI=y +CONFIG_USB_SERIAL_CYBERJACK=y +CONFIG_USB_SERIAL_XIRCOM=y +CONFIG_USB_SERIAL_WWAN=y +CONFIG_USB_SERIAL_OPTION=y +CONFIG_USB_SERIAL_OMNINET=y +CONFIG_USB_SERIAL_OPTICON=y +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=y +CONFIG_USB_SERIAL_ZIO=y +CONFIG_USB_SERIAL_SSU100=y +CONFIG_USB_SERIAL_DEBUG=y + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_RIO500=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_LED=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SISUSBVGA_CON=y +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=y +CONFIG_USB_IOWARRIOR=m +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +CONFIG_USB_YUREX=m +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_NET2272 is not set +CONFIG_USB_SW_SUNXI_UDC0_SELECT=m +# CONFIG_USB_DUMMY_HCD is not set +CONFIG_USB_SW_SUNXI_UDC0=m +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +CONFIG_USB_AUDIO=m +# CONFIG_GADGET_UAC1 is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_RNDIS=y +CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_G_HID=m +# CONFIG_USB_G_DBGP is not set +CONFIG_USB_G_WEBCAM=m + +# +# OTG and related infrastructure +# +# CONFIG_USB_OTG_WAKELOCK is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_USB_SW_SUNXI_USB=y +CONFIG_USB_SW_SUNXI_USB_MANAGER=y +# CONFIG_USB_SW_SUNXI_USB0_HOST_ONLY is not set +# CONFIG_USB_SW_SUNXI_USB0_OTG is not set +CONFIG_USB_SW_SUNXI_USB0_DEVICE_ONLY=y +# CONFIG_USB_SW_SUNXI_USB0_NULL is not set +CONFIG_USB_SW_SUNXI_USB_DEBUG=y +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y +# CONFIG_MMC_CLKGATE is not set +# CONFIG_MMC_EMBEDDED_SDIO is not set +# CONFIG_MMC_PARANOID_SD_INIT is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_DW is not set +CONFIG_MMC_SUNXI_NEW=y +# CONFIG_MMC_DEBUG_SUNXI is not set +CONFIG_MMC_PRE_DBGLVL_SUNXI=0 +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set + +# +# MMC/SD/SDIO Card Power Management Drivers +# +CONFIG_MMC_SUNXI_POWER_CONTROL=y + +# +# SUNXI MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_SUNXI is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA9633 is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_RENESAS_TPU is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_OT200 is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_SWITCH=y +# CONFIG_SWITCH_GPIO is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +CONFIG_RTC_DRV_SUN4I=y +# CONFIG_DMADEVICES is not set +CONFIG_AUXDISPLAY=y +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_STAGING=y +# CONFIG_USBIP_CORE is not set +# CONFIG_PRISM2_USB is not set +# CONFIG_ECHO is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_RTLLIB is not set +# CONFIG_R8712U is not set +# CONFIG_RTS5139 is not set +# CONFIG_TRANZPORT is not set +# CONFIG_LINE6_USB is not set +# CONFIG_USB_SERIAL_QUATECH2 is not set +# CONFIG_USB_SERIAL_QUATECH_USB2 is not set +# CONFIG_VT6656 is not set +# CONFIG_IIO is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_USB_ENESTORAGE is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_FT1000 is not set + +# +# Speakup console speech +# +# CONFIG_SPEAKUP is not set +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +# CONFIG_STAGING_MEDIA is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +# CONFIG_ASHMEM is not set +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_PERSISTENT_RAM=y +CONFIG_ANDROID_RAM_CONSOLE=y +# CONFIG_PERSISTENT_TRACER is not set +CONFIG_ANDROID_TIMED_OUTPUT=y +# CONFIG_ANDROID_TIMED_GPIO is not set +# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set +# CONFIG_ANDROID_SWITCH is not set +# CONFIG_ANDROID_INTF_ALARM_DEV is not set +# CONFIG_PHONE is not set +# CONFIG_USB_WPAN_HCD is not set +CONFIG_CLKDEV_LOOKUP=y + +# +# Hardware Spinlock drivers +# +CONFIG_IOMMU_SUPPORT=y + +# +# Remoteproc drivers (EXPERIMENTAL) +# + +# +# Rpmsg drivers (EXPERIMENTAL) +# +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +# CONFIG_XFS_DEBUG is not set +CONFIG_GFS2_FS=m +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_STATS=y +CONFIG_OCFS2_DEBUG_MASKLOG=y +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +CONFIG_NILFS2_FS=m +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_GENERIC_ACL=y + +# +# Caches +# +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +CONFIG_CACHEFILES=y +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +CONFIG_ROMFS_ON_BLOCK=y +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +# CONFIG_NFSD_FAULT_INJECTION is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=y +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set +# CONFIG_CIFS_XATTR is not set +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_FSCACHE is not set +CONFIG_NCP_FS=m +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set +CONFIG_CODA_FS=m +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +CONFIG_MAGIC_SYSRQ=y +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_SHIRQ=y +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR_NMI is not set +# CONFIG_HARDLOCKUP_DETECTOR_OTHER_CPU is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_LIST=y +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_BOOT_PRINTK_DELAY=y +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_CPU_STALL_VERBOSE is not set +# CONFIG_RCU_CPU_STALL_INFO is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_LKDTM is not set +# CONFIG_CPU_NOTIFIER_ERROR_INJECT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +CONFIG_DYNAMIC_DEBUG=y +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +CONFIG_STRICT_DEVMEM=y +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_RODATA is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_ENCRYPTED_KEYS=m +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +# CONFIG_SECURITY is not set +CONFIG_SECURITYFS=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +CONFIG_CRYPTO_GF128MUL=y +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +CONFIG_CRYPTO_SEQIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_ZLIB=y +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API=m +CONFIG_CRYPTO_USER_API_HASH=m +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_AVERAGE=y +# CONFIG_CORDIC is not set diff --git a/patch/linux-sunxi/arch/arm/configs/pcduino3b_lvds_defconfig b/patch/linux-sunxi/arch/arm/configs/pcduino3b_lvds_defconfig new file mode 100644 index 0000000..6cb9e7e --- /dev/null +++ b/patch/linux-sunxi/arch/arm/configs/pcduino3b_lvds_defconfig @@ -0,0 +1,3064 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.4.79 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_KTIME_SCALAR=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_LOCKBREAK=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_NEED_MACH_IO_H=y +CONFIG_NEED_MACH_MEMORY_H=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y +CONFIG_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="+" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_FHANDLE=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_WATCH=y +CONFIG_AUDIT_TREE=y +CONFIG_AUDIT_LOGINUID_IMMUTABLE=y +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y +# CONFIG_IRQ_DOMAIN_DEBUG is not set + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +CONFIG_RCU_FAST_NO_HZ=y +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +# CONFIG_CGROUP_MEM_RES_CTLR is not set +# CONFIG_CGROUP_PERF is not set +# CONFIG_CGROUP_SCHED is not set +CONFIG_BLK_CGROUP=y +# CONFIG_DEBUG_BLK_CGROUP is not set +# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="../../linux-sunxi/rootfs/sun7i_rootfs.cpio.xz" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +CONFIG_INITRAMFS_COMPRESSION_XZ=y +# CONFIG_INITRAMFS_COMPRESSION_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_PANIC_TIMEOUT=0 +CONFIG_EXPERT=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +CONFIG_PERF_COUNTERS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_BSGLIB is not set +CONFIG_BLK_DEV_INTEGRITY=y +# CONFIG_BLK_DEV_THROTTLING is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_SUNXI_NAND_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_CFQ_GROUP_IOSCHED=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_SUN4I is not set +# CONFIG_ARCH_SUN5I is not set +CONFIG_ARCH_SUN7I=y +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set + +# +# System MMU +# + +# +# Allwinner's sunxi options +# +CONFIG_SUNXI_MULTIPLATFORM=y +CONFIG_SUNXI_SCALING_MIN=60 +CONFIG_PLAT_SUNXI=y + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARCH_HAS_BARRIERS=y +CONFIG_ARM_NR_BANKS=8 +CONFIG_CPU_HAS_PMU=y +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +# CONFIG_ARM_ERRATA_742230 is not set +# CONFIG_ARM_ERRATA_742231 is not set +# CONFIG_ARM_ERRATA_720789 is not set +# CONFIG_ARM_ERRATA_743622 is not set +# CONFIG_ARM_ERRATA_751472 is not set +# CONFIG_ARM_ERRATA_754322 is not set +# CONFIG_ARM_ERRATA_754327 is not set +# CONFIG_ARM_ERRATA_764369 is not set +# CONFIG_ARM_ERRATA_775420 is not set +CONFIG_ARM_GIC=y +# CONFIG_FIQ_DEBUGGER is not set + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_SMT is not set +CONFIG_HAVE_ARM_SCU=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_HAVE_ARM_TWD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=2 +CONFIG_HOTPLUG_CPU=y +CONFIG_LOCAL_TIMERS=y +CONFIG_ARCH_NR_GPIO=0 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HW_PERF_EVENTS=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +# CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="console=ttyS0,115200" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +# CONFIG_AUTO_ZRELADDR is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +CONFIG_HAS_WAKELOCK=y +CONFIG_WAKELOCK=y +# CONFIG_PM_RUNTIME is not set +# CONFIG_SUSPEND_TIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_TUNNEL=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_ANDROID_PARANOID_NETWORK is not set +CONFIG_NET_ACTIVITY_STATS=y +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_ACCT is not set +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_SECMARK is not set +CONFIG_NF_CONNTRACK_PROCFS=y +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CT_PROTO_UDPLITE is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +# CONFIG_NF_CONNTRACK_FTP is not set +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +# CONFIG_NF_CT_NETLINK is not set +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +# CONFIG_NETFILTER_XT_MARK is not set +# CONFIG_NETFILTER_XT_CONNMARK is not set + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +# CONFIG_NETFILTER_XT_TARGET_LOG is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +CONFIG_NETFILTER_XT_MATCH_ECN=y +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +CONFIG_NETFILTER_XT_MATCH_HL=y +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_IPVS is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA2 is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +CONFIG_IP_VS=y +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +# CONFIG_IP_VS_PROTO_TCP is not set +# CONFIG_IP_VS_PROTO_UDP is not set +# CONFIG_IP_VS_PROTO_AH_ESP is not set +# CONFIG_IP_VS_PROTO_ESP is not set +# CONFIG_IP_VS_PROTO_AH is not set +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +# CONFIG_IP_VS_RR is not set +# CONFIG_IP_VS_WRR is not set +# CONFIG_IP_VS_LC is not set +# CONFIG_IP_VS_WLC is not set +# CONFIG_IP_VS_LBLC is not set +# CONFIG_IP_VS_LBLCR is not set +# CONFIG_IP_VS_DH is not set +# CONFIG_IP_VS_SH is not set +# CONFIG_IP_VS_SED is not set +# CONFIG_IP_VS_NQ is not set + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS application helper +# +# CONFIG_IP_VS_NFCT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_RPFILTER=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_NF_NAT_FTP is not set +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y + +# +# IPv6: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV6 is not set +# CONFIG_NF_CONNTRACK_IPV6 is not set +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=y +CONFIG_GARP=y +CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +CONFIG_VLAN_8021Q_GVRP=y +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_RPS is not set +CONFIG_XPS=y +# CONFIG_NETPRIO_CGROUP is not set +CONFIG_BQL=y +CONFIG_HAVE_BPF_JIT=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=y +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=y +CONFIG_BT_HCIBTSDIO=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set +# CONFIG_CFG80211_ALLOW_RECONNECT is not set +# CONFIG_MAC80211 is not set +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_REGULATOR=m +CONFIG_RFKILL_GPIO=m +CONFIG_SUNXI_RFKILL=y +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +CONFIG_NFC=m +CONFIG_NFC_NCI=m +CONFIG_NFC_LLCP=y + +# +# Near Field Communication (NFC) devices +# +CONFIG_PN544_NFC=m +CONFIG_NFC_PN533=m + +# +# Device Drivers +# + +# +# hardware lib support +# +CONFIG_HARDWARE_LIB=y +CONFIG_HARDWARE_LIB_UTIL=m +CONFIG_HARDWARE_LIB_ADC=m +CONFIG_HARDWARE_LIB_GPIO=m +CONFIG_HARDWARE_LIB_PWM=m +CONFIG_HARDWARE_LIB_INTERRUPT=m +CONFIG_HARDWARE_LIB_SPI=y +CONFIG_HARDWARE_LIB_I2C=y +CONFIG_SUNXI_DVI_FIX=y +# CONFIG_HARDWARE_LIB_ROOTFS is not set +CONFIG_HARDWARE_LIB_KEYPAD=m +CONFIG_RTXX7X_SW=m + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_SYNC is not set +# CONFIG_CMA is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_CRYPTOLOOP=y +# CONFIG_BLK_DEV_DRBD is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=2 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_BLK_DEV_RBD is not set +CONFIG_SUNXI_NAND=y +CONFIG_SUNXI_NAND_COMPAT_DEV=y +# CONFIG_SUNXI_NAND_TEST is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_SUN4I_VIBRATOR is not set +# CONFIG_SUNXI_DBGREG is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_SUNXI_PWM is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_SENSORS_AK8975 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_UID_STAT is not set +# CONFIG_BMP085 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_WL127X_RFKILL is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_IWMC3200TOP is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_SR_VENDOR=y +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_ATA_VERBOSE_ERROR is not set +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +# CONFIG_SATA_AHCI_PLATFORM is not set +CONFIG_SW_SATA_AHCI_PLATFORM=y +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +# CONFIG_SATA_MV is not set + +# +# PATA SFF controllers with BMDMA +# + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_PLATFORM is not set + +# +# Generic fallback / legacy drivers +# +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +CONFIG_MII=y +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +CONFIG_TUN=y +# CONFIG_VETH is not set + +# +# CAIF transport drivers +# +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_SUNXI_EMAC=m +CONFIG_SUNXI_GMAC=y +CONFIG_GMAC_SCRIPT_SYS=y +CONFIG_GMAC_CLK_SYS=y +CONFIG_GMAC_RING=y +# CONFIG_GMAC_CHAINED is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MICREL_KS8995MA is not set +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=m +CONFIG_PPPOLAC=m +CONFIG_PPPOPNS=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +# CONFIG_SLIP is not set +CONFIG_SLHC=m + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_WIFI_CONTROL_FUNC is not set +# CONFIG_ATH_COMMON is not set +# CONFIG_BCMDHD is not set +# CONFIG_BRCMFMAC is not set +# CONFIG_BCM4330 is not set +# CONFIG_HOSTAP is not set +# CONFIG_IWM is not set +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set +CONFIG_RTL8192CU_SW=m +CONFIG_RTL8188EU=m +# CONFIG_RTL8189ES is not set +# CONFIG_RTL8723AS is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +CONFIG_WAN=y +# CONFIG_HDLC is not set +# CONFIG_DLCI is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +CONFIG_INPUT_KEYRESET=y + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_SUN4IKEYPAD is not set +# CONFIG_KEYBOARD_SUN4I_KEYBOARD is not set +# CONFIG_KEYBOARD_HV2605_KEYBOARD is not set +CONFIG_IR_SUNXI=m +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +CONFIG_INPUT_JOYSTICK=y +# CONFIG_JOYSTICK_ANALOG is not set +# CONFIG_JOYSTICK_A3D is not set +# CONFIG_JOYSTICK_ADI is not set +# CONFIG_JOYSTICK_COBRA is not set +# CONFIG_JOYSTICK_GF2K is not set +# CONFIG_JOYSTICK_GRIP is not set +# CONFIG_JOYSTICK_GRIP_MP is not set +# CONFIG_JOYSTICK_GUILLEMOT is not set +# CONFIG_JOYSTICK_INTERACT is not set +# CONFIG_JOYSTICK_SIDEWINDER is not set +# CONFIG_JOYSTICK_TMDC is not set +# CONFIG_JOYSTICK_IFORCE is not set +# CONFIG_JOYSTICK_WARRIOR is not set +# CONFIG_JOYSTICK_MAGELLAN is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_STINGER is not set +# CONFIG_JOYSTICK_TWIDJOY is not set +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JOYSTICK_AS5011 is not set +# CONFIG_JOYSTICK_JOYDUMP is not set +# CONFIG_JOYSTICK_XPAD is not set +CONFIG_INPUT_TABLET=y +# CONFIG_TABLET_USB_ACECAD is not set +# CONFIG_TABLET_USB_AIPTEK is not set +# CONFIG_TABLET_USB_GTCO is not set +# CONFIG_TABLET_USB_HANWANG is not set +# CONFIG_TABLET_USB_KBTAB is not set +# CONFIG_TABLET_USB_WACOM is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_GT801 is not set +# CONFIG_TOUCHSCREEN_GT811 is not set +# CONFIG_TOUCHSCREEN_GT818 is not set +# CONFIG_TOUCHSCREEN_SUN4I_TS is not set +# CONFIG_TOUCHSCREEN_FT5X_TS is not set +# CONFIG_TOUCHSCREEN_ZT8031 is not set +# CONFIG_TOUCHSCREEN_COASIA is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MPU3050 is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYCHORD is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_GPIO is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_CMA3000 is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set +CONFIG_GSENSOR=y +# CONFIG_SENSORS_BMA250 is not set +# CONFIG_MEMSIC_ECOMPASS is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +CONFIG_DEVKMEM=y +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_SUNXI=y +CONFIG_SERIAL_8250_NR_UARTS=8 +CONFIG_SERIAL_8250_RUNTIME_UARTS=8 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_DCC_TTY is not set +# CONFIG_RAMOOPS is not set +CONFIG_SUNXI_G2D=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=y +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +CONFIG_I2C_SUNXI=y +# CONFIG_SUNXI_IIC_PRINT_TRANSFER_INFO is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX_PCI is not set +CONFIG_SPI_SUNXI=y +# CONFIG_SUNXI_SPI_NDMA is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_SUNXI is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +CONFIG_AW_AXP=y +# CONFIG_AW_AXP18 is not set +# CONFIG_AW_AXP19 is not set +CONFIG_AW_AXP20=y +CONFIG_AXP_CHARGEINIT=y +CONFIG_AXP_CHGCHANGE=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_AXP152 is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MPCORE_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_RC5T583 is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +CONFIG_RC_CORE=y +CONFIG_LIRC=y +CONFIG_RC_MAP=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +CONFIG_IR_RC5_SZ_DECODER=y +CONFIG_IR_SANYO_DECODER=y +CONFIG_IR_MCE_KBD_DECODER=y +CONFIG_IR_LIRC_CODEC=y +# CONFIG_RC_ATI_REMOTE is not set +# CONFIG_IR_IMON is not set +# CONFIG_IR_MCEUSB is not set +# CONFIG_IR_REDRAT3 is not set +# CONFIG_IR_STREAMZAP is not set +# CONFIG_RC_LOOPBACK is not set +# CONFIG_IR_GPIO_CIR is not set +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA827X=y +CONFIG_MEDIA_TUNER_TDA18271=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_XC4000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_VMALLOC=m +CONFIG_VIDEOBUF_DMA_CONTIG=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_VIDEO_TUNER=m +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_VMALLOC=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_IR_I2C=y + +# +# Audio decoders, processors and mixers +# +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_WM8775=m + +# +# RDS decoders +# + +# +# Video decoders +# +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TVP5150=m + +# +# Video and audio decoders +# +CONFIG_VIDEO_CX25840=m + +# +# MPEG video encoders +# +CONFIG_VIDEO_CX2341X=m + +# +# Video encoders +# + +# +# Camera sensor devices +# +CONFIG_VIDEO_MT9V011=m + +# +# Flash devices +# + +# +# Video improvement chips +# + +# +# Miscelaneous helper chips +# +CONFIG_VIDEO_VIVI=m +CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_USBVISION=m +CONFIG_USB_ET61X251=m +CONFIG_USB_SN9C102=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_VIDEO_CPIA2=m +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_V4L_PLATFORM_DRIVERS=y +# CONFIG_SOC_CAMERA is not set +CONFIG_V4L_MEM2MEM_DRIVERS=y +# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set +CONFIG_VIDEO_SUNXI_CEDAR=y +CONFIG_VIDEO_DECODER_SUNXI=y +CONFIG_VIDEO_AVS_COUNTER=y +CONFIG_VIDEO_CSI_SUN4I=y +CONFIG_CSI_DEV_SEL=m +CONFIG_CSI0_SUN4I=m +CONFIG_CSI1_SUN4I=m +CONFIG_CSI_OV7670=m +CONFIG_CSI_GT2005=m +CONFIG_CSI_GC0308=m +CONFIG_CSI_GC2035=m +CONFIG_CSI_HI704=m +CONFIG_CSI_SP0838=m +CONFIG_CSI_MT9M112=m +CONFIG_CSI_MT9M113=m +CONFIG_CSI_OV2655=m +CONFIG_CSI_HI253=m +CONFIG_CSI_MT9D112=m +CONFIG_CSI_GC0307=m +CONFIG_CSI_OV5640=m +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_SI470X is not set +# CONFIG_USB_MR800 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_I2C_SI4713 is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_KEENE is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_RADIO_WL1273 is not set + +# +# Texas Instruments WL128x FM driver (ST based) +# +# CONFIG_RADIO_WL128X is not set +CONFIG_AUDIO_ENGINE=y +CONFIG_ACE_CONFIG=y +CONFIG_PA_CONTROL=y +CONFIG_PA_CONFIG=y + +# +# Graphics support +# +CONFIG_DRM=m +CONFIG_DRM_MALI=m +# CONFIG_DRM_UDL is not set +# CONFIG_ION is not set +CONFIG_MALI=m +CONFIG_MALI400=m +# CONFIG_MALI400_DEBUG is not set +# CONFIG_MALI400_GPU_UTILIZATION is not set +CONFIG_UMP=m +CONFIG_UMP_DEBUG=y +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +CONFIG_FB_SYS_FILLRECT=m +CONFIG_FB_SYS_COPYAREA=m +CONFIG_FB_SYS_IMAGEBLIT=m +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=m +# CONFIG_FB_WMT_GE_ROPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_SUNXI=y +CONFIG_FB_SUNXI_RESERVED_MEM=y +CONFIG_FB_SUNXI_UMP=y +CONFIG_FB_SUNXI_LCD=y +CONFIG_FB_SUNXI_HDMI=y +# CONFIG_HDMI_CEC is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_EXYNOS_VIDEO is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=m +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LP855X is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +CONFIG_FONT_PEARL_8x8=y +CONFIG_FONT_ACORN_8x8=y +CONFIG_FONT_MINI_4x6=y +CONFIG_FONT_SUN8x16=y +CONFIG_FONT_SUN12x22=y +CONFIG_FONT_10x18=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +# CONFIG_SND_ARMAACI is not set +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_SOC=y +CONFIG_SOUND_SUNXI=y +CONFIG_SND_SUNXI_SOC_CODEC=y +CONFIG_SND_SUNXI_SOC_HDMIAUDIO=y +# CONFIG_SND_SUNXI_SOC_SPDIF is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +CONFIG_HIDRAW=y +# CONFIG_UHID is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=m +CONFIG_HID_BELKIN=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELECOM=m +CONFIG_HID_EZKEY=m +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +CONFIG_HID_KEYTOUCH=y +CONFIG_HID_KYE=y +CONFIG_HID_UCLOGIC=y +CONFIG_HID_WALTOP=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PRIMAX=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_GREENASIA=m +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_WACOM=m +CONFIG_HID_WACOM_POWER_SUPPLY=y +CONFIG_HID_WIIMOTE=m +CONFIG_HID_WIIMOTE_EXT=y +CONFIG_HID_ZEROPLUS=m +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=m +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB_ARCH_HAS_XHCI is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_U132_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +CONFIG_USB_SUNXI_EHCI=y +CONFIG_USB_SUNXI_OHCI=y +CONFIG_USB_SUNXI_COMMON=y +CONFIG_USB_SW_SUNXI_HCD0=y +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_RENESAS_USBHS is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_STORAGE_ENE_UB6250=y +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_EZUSB=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRCABLE=y +CONFIG_USB_SERIAL_ARK3116=y +CONFIG_USB_SERIAL_BELKIN=y +CONFIG_USB_SERIAL_CH341=y +CONFIG_USB_SERIAL_WHITEHEAT=y +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=y +CONFIG_USB_SERIAL_CP210X=y +CONFIG_USB_SERIAL_CYPRESS_M8=y +CONFIG_USB_SERIAL_EMPEG=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_FUNSOFT=y +CONFIG_USB_SERIAL_VISOR=y +CONFIG_USB_SERIAL_IPAQ=y +CONFIG_USB_SERIAL_IR=y +CONFIG_USB_SERIAL_EDGEPORT=y +CONFIG_USB_SERIAL_EDGEPORT_TI=y +CONFIG_USB_SERIAL_F81232=y +CONFIG_USB_SERIAL_GARMIN=y +CONFIG_USB_SERIAL_IPW=y +CONFIG_USB_SERIAL_IUU=y +CONFIG_USB_SERIAL_KEYSPAN_PDA=y +CONFIG_USB_SERIAL_KEYSPAN=y +CONFIG_USB_SERIAL_KLSI=y +CONFIG_USB_SERIAL_KOBIL_SCT=y +CONFIG_USB_SERIAL_MCT_U232=y +CONFIG_USB_SERIAL_METRO=y +CONFIG_USB_SERIAL_MOS7720=y +CONFIG_USB_SERIAL_MOS7840=y +CONFIG_USB_SERIAL_MOTOROLA=y +CONFIG_USB_SERIAL_NAVMAN=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_OTI6858=y +CONFIG_USB_SERIAL_QCAUX=y +CONFIG_USB_SERIAL_QUALCOMM=y +CONFIG_USB_SERIAL_SPCP8X5=y +CONFIG_USB_SERIAL_HP4X=y +CONFIG_USB_SERIAL_SAFE=y +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIEMENS_MPI=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=y +CONFIG_USB_SERIAL_SYMBOL=y +CONFIG_USB_SERIAL_TI=y +CONFIG_USB_SERIAL_CYBERJACK=y +CONFIG_USB_SERIAL_XIRCOM=y +CONFIG_USB_SERIAL_WWAN=y +CONFIG_USB_SERIAL_OPTION=y +CONFIG_USB_SERIAL_OMNINET=y +CONFIG_USB_SERIAL_OPTICON=y +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=y +CONFIG_USB_SERIAL_ZIO=y +CONFIG_USB_SERIAL_SSU100=y +CONFIG_USB_SERIAL_DEBUG=y + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_RIO500=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_LED=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SISUSBVGA_CON=y +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=y +CONFIG_USB_IOWARRIOR=m +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +CONFIG_USB_YUREX=m +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_NET2272 is not set +CONFIG_USB_SW_SUNXI_UDC0_SELECT=m +# CONFIG_USB_DUMMY_HCD is not set +CONFIG_USB_SW_SUNXI_UDC0=m +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +CONFIG_USB_AUDIO=m +# CONFIG_GADGET_UAC1 is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_RNDIS=y +CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_G_HID=m +# CONFIG_USB_G_DBGP is not set +CONFIG_USB_G_WEBCAM=m + +# +# OTG and related infrastructure +# +# CONFIG_USB_OTG_WAKELOCK is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_USB_SW_SUNXI_USB=y +CONFIG_USB_SW_SUNXI_USB_MANAGER=y +# CONFIG_USB_SW_SUNXI_USB0_HOST_ONLY is not set +# CONFIG_USB_SW_SUNXI_USB0_OTG is not set +CONFIG_USB_SW_SUNXI_USB0_DEVICE_ONLY=y +# CONFIG_USB_SW_SUNXI_USB0_NULL is not set +CONFIG_USB_SW_SUNXI_USB_DEBUG=y +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y +# CONFIG_MMC_CLKGATE is not set +# CONFIG_MMC_EMBEDDED_SDIO is not set +# CONFIG_MMC_PARANOID_SD_INIT is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_DW is not set +CONFIG_MMC_SUNXI_NEW=y +# CONFIG_MMC_DEBUG_SUNXI is not set +CONFIG_MMC_PRE_DBGLVL_SUNXI=0 +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set + +# +# MMC/SD/SDIO Card Power Management Drivers +# +CONFIG_MMC_SUNXI_POWER_CONTROL=y + +# +# SUNXI MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_SUNXI is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA9633 is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_RENESAS_TPU is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_OT200 is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_SWITCH=y +# CONFIG_SWITCH_GPIO is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +CONFIG_RTC_DRV_SUN4I=y +# CONFIG_DMADEVICES is not set +CONFIG_AUXDISPLAY=y +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_STAGING=y +# CONFIG_USBIP_CORE is not set +# CONFIG_PRISM2_USB is not set +# CONFIG_ECHO is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_RTLLIB is not set +# CONFIG_R8712U is not set +# CONFIG_RTS5139 is not set +# CONFIG_TRANZPORT is not set +# CONFIG_LINE6_USB is not set +# CONFIG_USB_SERIAL_QUATECH2 is not set +# CONFIG_USB_SERIAL_QUATECH_USB2 is not set +# CONFIG_VT6656 is not set +# CONFIG_IIO is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_USB_ENESTORAGE is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_FT1000 is not set + +# +# Speakup console speech +# +# CONFIG_SPEAKUP is not set +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +# CONFIG_STAGING_MEDIA is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +# CONFIG_ASHMEM is not set +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_PERSISTENT_RAM=y +CONFIG_ANDROID_RAM_CONSOLE=y +# CONFIG_PERSISTENT_TRACER is not set +CONFIG_ANDROID_TIMED_OUTPUT=y +# CONFIG_ANDROID_TIMED_GPIO is not set +# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set +# CONFIG_ANDROID_SWITCH is not set +# CONFIG_ANDROID_INTF_ALARM_DEV is not set +# CONFIG_PHONE is not set +# CONFIG_USB_WPAN_HCD is not set +CONFIG_CLKDEV_LOOKUP=y + +# +# Hardware Spinlock drivers +# +CONFIG_IOMMU_SUPPORT=y + +# +# Remoteproc drivers (EXPERIMENTAL) +# + +# +# Rpmsg drivers (EXPERIMENTAL) +# +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +# CONFIG_XFS_DEBUG is not set +CONFIG_GFS2_FS=m +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_STATS=y +CONFIG_OCFS2_DEBUG_MASKLOG=y +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +CONFIG_NILFS2_FS=m +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_GENERIC_ACL=y + +# +# Caches +# +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +CONFIG_CACHEFILES=y +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +CONFIG_ROMFS_ON_BLOCK=y +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +# CONFIG_NFSD_FAULT_INJECTION is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=y +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set +# CONFIG_CIFS_XATTR is not set +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_FSCACHE is not set +CONFIG_NCP_FS=m +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set +CONFIG_CODA_FS=m +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +CONFIG_MAGIC_SYSRQ=y +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_SHIRQ=y +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR_NMI is not set +# CONFIG_HARDLOCKUP_DETECTOR_OTHER_CPU is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_LIST=y +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_BOOT_PRINTK_DELAY=y +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_CPU_STALL_VERBOSE is not set +# CONFIG_RCU_CPU_STALL_INFO is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_LKDTM is not set +# CONFIG_CPU_NOTIFIER_ERROR_INJECT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +CONFIG_DYNAMIC_DEBUG=y +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +CONFIG_STRICT_DEVMEM=y +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_RODATA is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_ENCRYPTED_KEYS=m +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +# CONFIG_SECURITY is not set +CONFIG_SECURITYFS=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +CONFIG_CRYPTO_GF128MUL=y +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +CONFIG_CRYPTO_SEQIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_ZLIB=y +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API=m +CONFIG_CRYPTO_USER_API_HASH=m +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_AVERAGE=y +# CONFIG_CORDIC is not set diff --git a/patch/linux-sunxi/arch/arm/configs/sun7i_defconfig b/patch/linux-sunxi/arch/arm/configs/sun7i_defconfig index 347649f..690ef10 100644 --- a/patch/linux-sunxi/arch/arm/configs/sun7i_defconfig +++ b/patch/linux-sunxi/arch/arm/configs/sun7i_defconfig @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 3.4.67 Kernel Configuration +# Linux/arm 3.4.79 Kernel Configuration # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -170,6 +170,8 @@ CONFIG_HAVE_OPROFILE=y # CONFIG_JUMP_LABEL is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_USE_GENERIC_SMP_HELPERS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_CLK=y @@ -338,7 +340,6 @@ CONFIG_ARCH_SUN7I=y # Allwinner's sunxi options # CONFIG_SUNXI_MULTIPLATFORM=y -CONFIG_SUNXI_MALI_RESERVED_MEM=y CONFIG_SUNXI_SCALING_MIN=60 CONFIG_PLAT_SUNXI=y @@ -608,19 +609,42 @@ CONFIG_BRIDGE_NETFILTER=y # CONFIG_NETFILTER_NETLINK_ACCT is not set # CONFIG_NETFILTER_NETLINK_QUEUE is not set # CONFIG_NETFILTER_NETLINK_LOG is not set -# CONFIG_NF_CONNTRACK is not set +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_SECMARK is not set +CONFIG_NF_CONNTRACK_PROCFS=y +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CT_PROTO_UDPLITE is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +# CONFIG_NF_CONNTRACK_FTP is not set +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +# CONFIG_NF_CT_NETLINK is not set +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set CONFIG_NETFILTER_XTABLES=y # # Xtables combined modules # # CONFIG_NETFILTER_XT_MARK is not set +# CONFIG_NETFILTER_XT_CONNMARK is not set # # Xtables targets # # CONFIG_NETFILTER_XT_TARGET_AUDIT is not set # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set # CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set # CONFIG_NETFILTER_XT_TARGET_LED is not set # CONFIG_NETFILTER_XT_TARGET_LOG is not set @@ -636,7 +660,12 @@ CONFIG_NETFILTER_XTABLES=y # Xtables matches # # CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set # CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set # CONFIG_NETFILTER_XT_MATCH_CPU is not set # CONFIG_NETFILTER_XT_MATCH_DCCP is not set # CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set @@ -644,8 +673,10 @@ CONFIG_NETFILTER_XTABLES=y CONFIG_NETFILTER_XT_MATCH_ECN=y # CONFIG_NETFILTER_XT_MATCH_ESP is not set # CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set CONFIG_NETFILTER_XT_MATCH_HL=y # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_IPVS is not set # CONFIG_NETFILTER_XT_MATCH_LENGTH is not set # CONFIG_NETFILTER_XT_MATCH_LIMIT is not set # CONFIG_NETFILTER_XT_MATCH_MAC is not set @@ -662,6 +693,7 @@ CONFIG_NETFILTER_XT_MATCH_HL=y # CONFIG_NETFILTER_XT_MATCH_REALM is not set # CONFIG_NETFILTER_XT_MATCH_RECENT is not set # CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set # CONFIG_NETFILTER_XT_MATCH_STRING is not set # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set @@ -704,11 +736,14 @@ CONFIG_IP_VS_SH_TAB_BITS=8 # # IPVS application helper # +# CONFIG_IP_VS_NFCT is not set # # IP: Netfilter Configuration # -# CONFIG_NF_DEFRAG_IPV4 is not set +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y # CONFIG_IP_NF_QUEUE is not set CONFIG_IP_NF_IPTABLES=y CONFIG_IP_NF_MATCH_AH=y @@ -719,6 +754,18 @@ CONFIG_IP_NF_FILTER=y CONFIG_IP_NF_TARGET_REJECT=y CONFIG_IP_NF_TARGET_REJECT_SKERR=y # CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_NF_NAT_FTP is not set +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_SIP is not set # CONFIG_IP_NF_MANGLE is not set # CONFIG_IP_NF_RAW is not set CONFIG_IP_NF_ARPTABLES=y @@ -729,6 +776,7 @@ CONFIG_IP_NF_ARP_MANGLE=y # IPv6: Netfilter Configuration # # CONFIG_NF_DEFRAG_IPV6 is not set +# CONFIG_NF_CONNTRACK_IPV6 is not set # CONFIG_IP6_NF_QUEUE is not set # CONFIG_IP6_NF_IPTABLES is not set # CONFIG_BRIDGE_NF_EBTABLES is not set @@ -825,6 +873,7 @@ CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y CONFIG_RFKILL_REGULATOR=m CONFIG_RFKILL_GPIO=m +CONFIG_SUNXI_RFKILL=y # CONFIG_NET_9P is not set # CONFIG_CAIF is not set # CONFIG_CEPH_LIB is not set @@ -855,7 +904,7 @@ CONFIG_HARDWARE_LIB_SPI=y CONFIG_HARDWARE_LIB_I2C=y CONFIG_SUNXI_DVI_FIX=y # CONFIG_HARDWARE_LIB_ROOTFS is not set -# CONFIG_HARDWARE_LIB_KEYPAD is not set +CONFIG_HARDWARE_LIB_KEYPAD=m CONFIG_RTXX7X_SW=m # @@ -878,6 +927,7 @@ CONFIG_REGMAP_I2C=y CONFIG_REGMAP_SPI=y CONFIG_DMA_SHARED_BUFFER=y # CONFIG_SYNC is not set +# CONFIG_CMA is not set CONFIG_CONNECTOR=y CONFIG_PROC_EVENTS=y # CONFIG_MTD is not set @@ -908,7 +958,6 @@ CONFIG_SUNXI_NAND_COMPAT_DEV=y # CONFIG_SENSORS_LIS3LV02D is not set # CONFIG_AD525X_DPOT is not set # CONFIG_SUN4I_VIBRATOR is not set -# CONFIG_SUN4I_GPIO_UGLY is not set # CONFIG_SUNXI_DBGREG is not set # CONFIG_ATMEL_PWM is not set # CONFIG_SUNXI_PWM is not set @@ -998,7 +1047,40 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_DH is not set # CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_ATA_VERBOSE_ERROR is not set +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +# CONFIG_SATA_AHCI_PLATFORM is not set +CONFIG_SW_SATA_AHCI_PLATFORM=y +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +# CONFIG_SATA_MV is not set + +# +# PATA SFF controllers with BMDMA +# + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_PLATFORM is not set + +# +# Generic fallback / legacy drivers +# # CONFIG_MD is not set # CONFIG_TARGET_CORE is not set CONFIG_NETDEVICES=y @@ -1012,7 +1094,7 @@ CONFIG_MII=y # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_TUN is not set +CONFIG_TUN=y # CONFIG_VETH is not set # @@ -1036,6 +1118,11 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_SMSC is not set # CONFIG_NET_VENDOR_STMICRO is not set CONFIG_SUNXI_EMAC=y +CONFIG_SUNXI_GMAC=m +CONFIG_GMAC_SCRIPT_SYS=y +CONFIG_GMAC_CLK_SYS=y +CONFIG_GMAC_RING=y +# CONFIG_GMAC_CHAINED is not set CONFIG_PHYLIB=y # @@ -1096,7 +1183,7 @@ CONFIG_WLAN=y # CONFIG_LIBERTAS is not set # CONFIG_MWIFIEX is not set CONFIG_RTL8192CU_SW=m -# CONFIG_RTL8188EU is not set +CONFIG_RTL8188EU=m # CONFIG_RTL8189ES is not set # CONFIG_RTL8723AS is not set @@ -1156,7 +1243,7 @@ CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_SUN4IKEYPAD is not set # CONFIG_KEYBOARD_SUN4I_KEYBOARD is not set # CONFIG_KEYBOARD_HV2605_KEYBOARD is not set -# CONFIG_IR_SUNXI is not set +CONFIG_IR_SUNXI=m CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y @@ -1231,7 +1318,25 @@ CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set # CONFIG_TOUCHSCREEN_TOUCHWIN is not set # CONFIG_TOUCHSCREEN_PIXCIR is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set # CONFIG_TOUCHSCREEN_TSC_SERIO is not set # CONFIG_TOUCHSCREEN_TSC2005 is not set @@ -1636,6 +1741,11 @@ CONFIG_MEDIA_TUNER_XC5000=y CONFIG_MEDIA_TUNER_XC4000=y CONFIG_MEDIA_TUNER_MC44S803=y CONFIG_VIDEO_V4L2=y +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_VMALLOC=m +CONFIG_VIDEOBUF_DMA_CONTIG=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_VIDEO_TUNER=m CONFIG_VIDEOBUF2_CORE=y CONFIG_VIDEOBUF2_MEMOPS=y CONFIG_VIDEOBUF2_VMALLOC=y @@ -1648,6 +1758,9 @@ CONFIG_VIDEO_IR_I2C=y # # Audio decoders, processors and mixers # +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_WM8775=m # # RDS decoders @@ -1656,14 +1769,18 @@ CONFIG_VIDEO_IR_I2C=y # # Video decoders # +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TVP5150=m # # Video and audio decoders # +CONFIG_VIDEO_CX25840=m # # MPEG video encoders # +CONFIG_VIDEO_CX2341X=m # # Video encoders @@ -1672,6 +1789,7 @@ CONFIG_VIDEO_IR_I2C=y # # Camera sensor devices # +CONFIG_VIDEO_MT9V011=m # # Flash devices @@ -1688,20 +1806,75 @@ CONFIG_VIDEO_VIVI=m CONFIG_V4L_USB_DRIVERS=y CONFIG_USB_VIDEO_CLASS=y CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -# CONFIG_USB_GSPCA is not set -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_HDPVR is not set -# CONFIG_VIDEO_EM28XX is not set -# CONFIG_VIDEO_CX231XX is not set -# CONFIG_VIDEO_TM6000 is not set -# CONFIG_VIDEO_USBVISION is not set -# CONFIG_USB_ET61X251 is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_USB_PWC is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_USB_ZR364XX is not set -# CONFIG_USB_STKWEBCAM is not set -# CONFIG_USB_S2255 is not set +CONFIG_USB_GSPCA=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_USBVISION=m +CONFIG_USB_ET61X251=m +CONFIG_USB_SN9C102=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_VIDEO_CPIA2=m +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m CONFIG_V4L_PLATFORM_DRIVERS=y # CONFIG_SOC_CAMERA is not set CONFIG_V4L_MEM2MEM_DRIVERS=y @@ -1709,7 +1882,23 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_SUNXI_CEDAR=y CONFIG_VIDEO_DECODER_SUNXI=y CONFIG_VIDEO_AVS_COUNTER=y -# CONFIG_VIDEO_CSI_SUN4I is not set +CONFIG_VIDEO_CSI_SUN4I=y +CONFIG_CSI_DEV_SEL=m +CONFIG_CSI0_SUN4I=m +CONFIG_CSI1_SUN4I=m +CONFIG_CSI_OV7670=m +CONFIG_CSI_GT2005=m +CONFIG_CSI_GC0308=m +CONFIG_CSI_GC2035=m +CONFIG_CSI_HI704=m +CONFIG_CSI_SP0838=m +CONFIG_CSI_MT9M112=m +CONFIG_CSI_MT9M113=m +CONFIG_CSI_OV2655=m +CONFIG_CSI_HI253=m +CONFIG_CSI_MT9D112=m +CONFIG_CSI_GC0307=m +CONFIG_CSI_OV5640=m CONFIG_RADIO_ADAPTERS=y # CONFIG_RADIO_SI470X is not set # CONFIG_USB_MR800 is not set @@ -1855,7 +2044,7 @@ CONFIG_SND_USB_CAIAQ_INPUT=y CONFIG_SND_USB_6FIRE=m CONFIG_SND_SOC=y CONFIG_SOUND_SUNXI=y -# CONFIG_SND_SUNXI_SOC_CODEC is not set +CONFIG_SND_SUNXI_SOC_CODEC=y CONFIG_SND_SUNXI_SOC_HDMIAUDIO=y # CONFIG_SND_SUNXI_SOC_SPDIF is not set CONFIG_SND_SOC_I2C_AND_SPI=y @@ -2113,7 +2302,7 @@ CONFIG_USB_IOWARRIOR=m # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set CONFIG_USB_YUREX=m -CONFIG_USB_GADGET=y +CONFIG_USB_GADGET=m # CONFIG_USB_GADGET_DEBUG is not set # CONFIG_USB_GADGET_DEBUG_FILES is not set # CONFIG_USB_GADGET_DEBUG_FS is not set @@ -2124,28 +2313,36 @@ CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 # CONFIG_USB_MV_UDC is not set # CONFIG_USB_M66592 is not set # CONFIG_USB_NET2272 is not set -CONFIG_USB_SW_SUNXI_UDC0_SELECT=y +CONFIG_USB_SW_SUNXI_UDC0_SELECT=m # CONFIG_USB_DUMMY_HCD is not set -CONFIG_USB_SW_SUNXI_UDC0=y +CONFIG_USB_SW_SUNXI_UDC0=m CONFIG_USB_GADGET_DUALSPEED=y # CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_ETH is not set -# CONFIG_USB_G_NCM is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FUNCTIONFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_MASS_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set +CONFIG_USB_AUDIO=m +# CONFIG_GADGET_UAC1 is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m # CONFIG_USB_MIDI_GADGET is not set # CONFIG_USB_G_PRINTER is not set -CONFIG_USB_G_ANDROID=y -# CONFIG_USB_CDC_COMPOSITE is not set -# CONFIG_USB_G_ACM_MS is not set -# CONFIG_USB_G_MULTI is not set -# CONFIG_USB_G_HID is not set +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_RNDIS=y +CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_G_HID=m # CONFIG_USB_G_DBGP is not set -# CONFIG_USB_G_WEBCAM is not set +CONFIG_USB_G_WEBCAM=m # # OTG and related infrastructure @@ -2157,8 +2354,8 @@ CONFIG_USB_G_ANDROID=y CONFIG_USB_SW_SUNXI_USB=y CONFIG_USB_SW_SUNXI_USB_MANAGER=y # CONFIG_USB_SW_SUNXI_USB0_HOST_ONLY is not set -CONFIG_USB_SW_SUNXI_USB0_OTG=y -# CONFIG_USB_SW_SUNXI_USB0_DEVICE_ONLY is not set +# CONFIG_USB_SW_SUNXI_USB0_OTG is not set +CONFIG_USB_SW_SUNXI_USB0_DEVICE_ONLY=y # CONFIG_USB_SW_SUNXI_USB0_NULL is not set CONFIG_USB_SW_SUNXI_USB_DEBUG=y CONFIG_MMC=y diff --git a/patch/linux-sunxi/drivers/media/video/sun4i_csi/Kconfig b/patch/linux-sunxi/drivers/media/video/sun4i_csi/Kconfig new file mode 100644 index 0000000..764164b --- /dev/null +++ b/patch/linux-sunxi/drivers/media/video/sun4i_csi/Kconfig @@ -0,0 +1,119 @@ +config CSI_DEV_SEL + tristate + +config CSI0_SUN4I + tristate "CSI0 v4l2 driver for sun4i" + default m + depends on CSI_DEV_SEL&&I2C && VIDEO_DEV && VIDEO_V4L2 + select VIDEOBUF_DMA_CONTIG + +config CSI1_SUN4I + tristate "CSI1 v4l2 driver for sun4i" + default m + depends on CSI_DEV_SEL&&I2C && VIDEO_DEV && VIDEO_V4L2 + select VIDEOBUF_DMA_CONTIG + +config CSI_OV7670 + tristate "OmniVision OV7670 sensor support" + depends on I2C && VIDEO_V4L2 + select CSI_DEV_SEL + ---help--- + This is a Video4Linux2 sensor-level driver for the OmniVision + OV7670 VGA camera. + +config CSI_GT2005 + tristate "GalaxyCore GT2005 2M sensor support" + depends on I2C && VIDEO_V4L2 + select CSI_DEV_SEL + ---help--- + This is a Video4Linux2 sensor-level driver for the GalaxyCore + GT2005 2M camera. + +config CSI_GC0308 + tristate "GalaxyCore GC0308 VGA sensor support" + depends on I2C && VIDEO_V4L2 + select CSI_DEV_SEL + ---help--- + This is a Video4Linux2 sensor-level driver for the GalaxyCore + GC0308 VGA camera. + + +config CSI_GC2035 + tristate "GC2035 2M sensor support" + depends on I2C && VIDEO_V4L2 + select CSI_DEV_SEL + ---help--- + This is a Video4Linux2 sensor-level driver for the + GC2035 2M camera. + +config CSI_HI704 + tristate "HYNIX HI704 VGA sensor support" + depends on I2C && VIDEO_V4L2 + select CSI_DEV_SEL + ---help--- + This is a Video4Linux2 sensor-level driver for the Hynix + HI704 VGA camera. + +config CSI_SP0838 + tristate "Superpix SP0838 VGA sensor support" + depends on I2C && VIDEO_V4L2 + select CSI_DEV_SEL + ---help--- + This is a Video4Linux2 sensor-level driver for the Superpix + SP0838 VGA camera. + +config CSI_MT9M112 + tristate "Micron MT9M112 UXGA sensor support" + depends on I2C && VIDEO_V4L2 + select CSI_DEV_SEL + ---help--- + This is a Video4Linux2 sensor-level driver for the Micron + MT9M112 UXGA camera. + +config CSI_MT9M113 + tristate "Micron MT9M113 SXGA sensor support" + depends on I2C && VIDEO_V4L2 + select CSI_DEV_SEL + ---help--- + This is a Video4Linux2 sensor-level driver for the Micron + MT9M113 SXGA camera. + +config CSI_OV2655 + tristate "OmniVision OV2655 UXGA sensor support" + depends on I2C && VIDEO_V4L2 + select CSI_DEV_SEL + ---help--- + This is a Video4Linux2 sensor-level driver for the MOmniVision + OV2655 UXGA camera. + +config CSI_HI253 + tristate "Hynix HI253 UXGA sensor support" + depends on I2C && VIDEO_V4L2 + select CSI_DEV_SEL + ---help--- + This is a Video4Linux2 sensor-level driver for the Hynix + HI253 UXGA camera. + +config CSI_MT9D112 + tristate "Micron MT9D112 UXGA sensor support" + depends on I2C && VIDEO_V4L2 + select CSI_DEV_SEL + ---help--- + This is a Video4Linux2 sensor-level driver for the Micron + MT9D112 UXGA camera. + +config CSI_GC0307 + tristate "GalaxyCore GC0307 VGA sensor support" + depends on I2C && VIDEO_V4L2 + select CSI_DEV_SEL + ---help--- + This is a Video4Linux2 sensor-level driver for the GalaxyCore + GC0307 VGA camera. + +config CSI_OV5640 + tristate "OmniVision OV5640 5M sensor support" + depends on I2C && VIDEO_V4L2 + select CSI_DEV_SEL + ---help--- + This is a Video4Linux2 sensor-level driver for the OmniVision + OV5640 5M camera. diff --git a/patch/linux-sunxi/drivers/media/video/sun4i_csi/device/Makefile b/patch/linux-sunxi/drivers/media/video/sun4i_csi/device/Makefile new file mode 100644 index 0000000..d2a89ad --- /dev/null +++ b/patch/linux-sunxi/drivers/media/video/sun4i_csi/device/Makefile @@ -0,0 +1,13 @@ +obj-$(CONFIG_CSI_OV7670) += ov7670.o +obj-$(CONFIG_CSI_GT2005) += gt2005.o +obj-$(CONFIG_CSI_GC0308) += gc0308.o +obj-$(CONFIG_CSI_GC2035) += gc2035.o +obj-$(CONFIG_CSI_HI704) += hi704.o +obj-$(CONFIG_CSI_SP0838) += sp0838.o +obj-$(CONFIG_CSI_MT9M112) += mt9m112.o +obj-$(CONFIG_CSI_MT9M113) += mt9m113.o +obj-$(CONFIG_CSI_OV2655) += ov2655.o +obj-$(CONFIG_CSI_HI253) += hi253.o +obj-$(CONFIG_CSI_MT9D112) += mt9d112.o +obj-$(CONFIG_CSI_GC0307) += gc0307.o +obj-$(CONFIG_CSI_OV5640) += ov5640.o diff --git a/patch/linux-sunxi/drivers/media/video/sun4i_csi/device/gc0308.c b/patch/linux-sunxi/drivers/media/video/sun4i_csi/device/gc0308.c new file mode 100644 index 0000000..61f8f3b --- /dev/null +++ b/patch/linux-sunxi/drivers/media/video/sun4i_csi/device/gc0308.c @@ -0,0 +1,2394 @@ +/* + * drivers/media/video/sun4i_csi/device/gc0308.c + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * A V4L2 driver for GalaxyCore GC0308 cameras. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include //linux-3.0 +#include +#include +#include +#include +#include "../include/sun4i_csi_core.h" +#include "../include/sun4i_dev_csi.h" + +MODULE_AUTHOR("raymonxiu"); +MODULE_DESCRIPTION("A low-level driver for GalaxyCore GC0308 sensors"); +MODULE_LICENSE("GPL"); + +//for internel driver debug +#define DEV_DBG_EN 0 +#if(DEV_DBG_EN == 1) +#define csi_dev_dbg(x,arg...) printk(KERN_INFO"[CSI_DEBUG][GC0308]"x,##arg) +#else +#define csi_dev_dbg(x,arg...) +#endif +#define csi_dev_err(x,arg...) printk(KERN_INFO"[CSI_ERR][GC0308]"x,##arg) +#define csi_dev_print(x,arg...) printk(KERN_INFO"[CSI][GC0308]"x,##arg) + +#define MCLK_VER_B (49.5*1000*1000) +#define MCLK_VER_C (24*1000*1000) +#define VREF_POL CSI_HIGH +#define HREF_POL CSI_HIGH +#define CLK_POL CSI_RISING +#define IO_CFG 0 //0 for csi0 + +//define the voltage level of control signal +#define CSI_STBY_ON 1 +#define CSI_STBY_OFF 0 +#define CSI_RST_ON 0 +#define CSI_RST_OFF 1 +#define CSI_PWR_ON 1 +#define CSI_PWR_OFF 0 + + +#define V4L2_IDENT_SENSOR 0x0308 + +#define REG_TERM 0xff +#define VAL_TERM 0xff + + +#define REG_ADDR_STEP 1 +#define REG_DATA_STEP 1 +#define REG_STEP (REG_ADDR_STEP+REG_DATA_STEP) + + +/* + * Basic window sizes. These probably belong somewhere more globally + * useful. + */ +#define VGA_WIDTH 640 +#define VGA_HEIGHT 480 +#define QVGA_WIDTH 320 +#define QVGA_HEIGHT 240 +#define CIF_WIDTH 352 +#define CIF_HEIGHT 288 +#define QCIF_WIDTH 176 +#define QCIF_HEIGHT 144 + +/* + * Our nominal (default) frame rate. + */ +#define SENSOR_FRAME_RATE 10 + +/* + * The gc0308 sits on i2c with ID 0x42 + */ +#define I2C_ADDR 0x42 + +/* Registers */ +static enum sw_ic_ver magic_ver; + +/* + * Information we maintain about a known sensor. + */ +struct sensor_format_struct; /* coming later */ +__csi_subdev_info_t ccm_info_con = +{ + .mclk = MCLK_VER_C, + .vref = VREF_POL, + .href = HREF_POL, + .clock = CLK_POL, + .iocfg = IO_CFG, +}; + +struct sensor_info { + struct v4l2_subdev sd; + struct sensor_format_struct *fmt; /* Current format */ + __csi_subdev_info_t *ccm_info; + int width; + int height; + int brightness; + int contrast; + int saturation; + int hue; + int hflip; + int vflip; + int gain; + int autogain; + int exp; + enum v4l2_exposure_auto_type autoexp; + int autowb; + enum v4l2_whiteblance wb; + enum v4l2_colorfx clrfx; + enum v4l2_flash_mode flash_mode; + u8 clkrc; /* Clock divider value */ +}; + +static inline struct sensor_info *to_state(struct v4l2_subdev *sd) +{ + return container_of(sd, struct sensor_info, sd); +} + + +struct regval_list { + unsigned char reg_num[REG_ADDR_STEP]; + unsigned char value[REG_DATA_STEP]; +}; + + +/* + * The default register settings + * + */ +static struct regval_list sensor_default_regs_49p5M[] = { +{{0xfe},{0x00}}, +//MCLK=49.5MHz 10fps +{{0x01},{0xcb}}, //0x28 +{{0x02},{0x60}}, //0x00 +{{0x0f},{0x18}}, //0x21 +{{0xe2},{0x00}}, +{{0xe3},{0xFA}}, +{{0xe4},{0x03}}, +{{0xe5},{0xE8}}, +{{0xe6},{0x03}}, +{{0xe7},{0xE8}}, +{{0xe8},{0x03}}, +{{0xe9},{0xE8}}, +{{0xea},{0x09}}, +{{0xeb},{0xC4}}, +}; + +static struct regval_list sensor_default_regs_24M[] = { +{{0xfe},{0x00}}, +//MCLK=24MHz 10fps +{{0x0f},{0x05}}, //0x00 +{{0x01},{0xe1}}, //0x6a +{{0x02},{0x70}}, //0x70 +{{0xe2},{0x00}}, +{{0xe3},{0x96}}, +{{0xe4},{0x02}}, +{{0xe5},{0x58}}, +{{0xe6},{0x02}}, +{{0xe7},{0x58}}, +{{0xe8},{0x02}}, +{{0xe9},{0x58}}, +{{0xea},{0x0e}}, +{{0xeb},{0xa6}}, +}; + +static struct regval_list sensor_default_regs[] = { +{{0xfe},{0x00}}, +{{0xec},{0x20}}, +{{0x05},{0x00}}, +{{0x06},{0x00}}, +{{0x07},{0x00}}, +{{0x08},{0x00}}, +{{0x09},{0x01}}, +{{0x0a},{0xe8}}, +{{0x0b},{0x02}}, +{{0x0c},{0x88}}, +{{0x0d},{0x02}}, +{{0x0e},{0x02}}, +{{0x10},{0x26}}, +{{0x11},{0x0d}}, +{{0x12},{0x2a}}, +{{0x13},{0x00}}, +{{0x14},{0x11}}, +{{0x15},{0x0a}}, +{{0x16},{0x05}}, +{{0x17},{0x01}}, +{{0x18},{0x44}}, +{{0x19},{0x44}}, +{{0x1a},{0x2a}}, +{{0x1b},{0x00}}, +{{0x1c},{0x49}}, +{{0x1d},{0x9a}}, +{{0x1e},{0x61}}, +{{0x1f},{0x16}}, +{{0x20},{0x7f}}, +{{0x21},{0xfa}}, +{{0x22},{0x57}}, +{{0x24},{0xa2}}, //YCbYCr +{{0x25},{0x0f}}, +{{0x26},{0x03}}, // 0x01 +{{0x28},{0x00}}, +{{0x2d},{0x0a}}, +{{0x2f},{0x01}}, +{{0x30},{0xf7}}, +{{0x31},{0x50}}, +{{0x32},{0x00}}, +{{0x33},{0x28}}, +{{0x34},{0x2a}}, +{{0x35},{0x28}}, +{{0x39},{0x04}}, +{{0x3a},{0x20}}, +{{0x3b},{0x20}}, +{{0x3c},{0x00}}, +{{0x3d},{0x00}}, +{{0x3e},{0x00}}, +{{0x3f},{0x00}}, +{{0x50},{0x14}}, // 0x14 +{{0x52},{0x41}}, +{{0x53},{0x80}}, +{{0x54},{0x80}}, +{{0x55},{0x80}}, +{{0x56},{0x80}}, +{{0x8b},{0x20}}, +{{0x8c},{0x20}}, +{{0x8d},{0x20}}, +{{0x8e},{0x14}}, +{{0x8f},{0x10}}, +{{0x90},{0x14}}, +{{0x91},{0x3c}}, +{{0x92},{0x50}}, +//{{0x8b},{0x10}}, +//{{0x8c},{0x10}}, +//{{0x8d},{0x10}}, +//{{0x8e},{0x10}}, +//{{0x8f},{0x10}}, +//{{0x90},{0x10}}, +//{{0x91},{0x3c}}, +//{{0x92},{0x50}}, +{{0x5d},{0x12}}, +{{0x5e},{0x1a}}, +{{0x5f},{0x24}}, +{{0x60},{0x07}}, +{{0x61},{0x15}}, +{{0x62},{0x08}}, // 0x08 +{{0x64},{0x03}}, // 0x03 +{{0x66},{0xe8}}, +{{0x67},{0x86}}, +{{0x68},{0x82}}, +{{0x69},{0x18}}, +{{0x6a},{0x0f}}, +{{0x6b},{0x00}}, +{{0x6c},{0x5f}}, +{{0x6d},{0x8f}}, +{{0x6e},{0x55}}, +{{0x6f},{0x38}}, +{{0x70},{0x15}}, +{{0x71},{0x33}}, +{{0x72},{0xdc}}, +{{0x73},{0x00}}, +{{0x74},{0x02}}, +{{0x75},{0x3f}}, +{{0x76},{0x02}}, +{{0x77},{0x38}}, // 0x47 +{{0x78},{0x88}}, +{{0x79},{0x81}}, +{{0x7a},{0x81}}, +{{0x7b},{0x22}}, +{{0x7c},{0xff}}, +{{0x93},{0x48}}, //color matrix default +{{0x94},{0x02}}, +{{0x95},{0x07}}, +{{0x96},{0xe0}}, +{{0x97},{0x40}}, +{{0x98},{0xf0}}, +{{0xb1},{0x40}}, +{{0xb2},{0x40}}, +{{0xb3},{0x40}}, //0x40 +{{0xb6},{0xe0}}, +{{0xbd},{0x38}}, +{{0xbe},{0x36}}, +{{0xd0},{0xCB}}, +{{0xd1},{0x10}}, +{{0xd2},{0x90}}, +{{0xd3},{0x48}}, +{{0xd5},{0xF2}}, +{{0xd6},{0x16}}, +{{0xdb},{0x92}}, +{{0xdc},{0xA5}}, +{{0xdf},{0x23}}, +{{0xd9},{0x00}}, +{{0xda},{0x00}}, +{{0xe0},{0x09}}, +{{0xed},{0x04}}, +{{0xee},{0xa0}}, +{{0xef},{0x40}}, +{{0x80},{0x03}}, + +{{0x9F},{0x10}}, +{{0xA0},{0x20}}, +{{0xA1},{0x38}}, +{{0xA2},{0x4e}}, +{{0xA3},{0x63}}, +{{0xA4},{0x76}}, +{{0xA5},{0x87}}, +{{0xA6},{0xa2}}, +{{0xA7},{0xb8}}, +{{0xA8},{0xca}}, +{{0xA9},{0xd8}}, +{{0xAA},{0xe3}}, +{{0xAB},{0xeb}}, +{{0xAC},{0xf0}}, +{{0xAD},{0xF8}}, +{{0xAE},{0xFd}}, +{{0xAF},{0xFF}}, + +{{0xc0},{0x00}}, +{{0xc1},{0x10}}, +{{0xc2},{0x1c}}, +{{0xc3},{0x30}}, +{{0xc4},{0x43}}, +{{0xc5},{0x54}}, +{{0xc6},{0x65}}, +{{0xc7},{0x75}}, +{{0xc8},{0x93}}, +{{0xc9},{0xB0}}, +{{0xca},{0xCB}}, +{{0xcb},{0xE6}}, +{{0xcc},{0xFF}}, +{{0xf0},{0x02}}, +{{0xf1},{0x01}}, +{{0xf2},{0x02}}, +{{0xf3},{0x30}}, +{{0xf7},{0x12}}, +{{0xf8},{0x0a}}, +{{0xf9},{0x9f}}, +{{0xfa},{0x78}}, +{{0xfe},{0x01}}, +{{0x00},{0xf5}}, +{{0x02},{0x20}}, +{{0x04},{0x10}}, +{{0x05},{0x08}}, +{{0x06},{0x20}}, +{{0x08},{0x0a}}, +{{0x0a},{0xa0}}, +{{0x0b},{0x60}}, +{{0x0c},{0x08}}, +{{0x0e},{0x44}}, +{{0x0f},{0x32}}, +{{0x10},{0x41}}, +{{0x11},{0x37}}, +{{0x12},{0x22}}, +{{0x13},{0x19}}, +{{0x14},{0x44}}, +{{0x15},{0x44}}, +{{0x16},{0xc2}}, +{{0x17},{0xA8}}, +{{0x18},{0x18}}, +{{0x19},{0x50}}, +{{0x1a},{0xd8}}, +{{0x1b},{0xf5}}, +{{0x70},{0x40}}, +{{0x71},{0x58}}, +{{0x72},{0x30}}, +{{0x73},{0x48}}, +{{0x74},{0x20}}, +{{0x75},{0x60}}, +{{0x77},{0x20}}, +{{0x78},{0x32}}, +{{0x30},{0x03}}, +{{0x31},{0x40}}, +{{0x32},{0x10}}, +{{0x33},{0xe0}}, +{{0x34},{0xe0}}, +{{0x35},{0x00}}, +{{0x36},{0x80}}, +{{0x37},{0x00}}, +{{0x38},{0x04}}, +{{0x39},{0x09}}, +{{0x3a},{0x12}}, +{{0x3b},{0x1C}}, +{{0x3c},{0x28}}, +{{0x3d},{0x31}}, +{{0x3e},{0x44}}, +{{0x3f},{0x57}}, +{{0x40},{0x6C}}, +{{0x41},{0x81}}, +{{0x42},{0x94}}, +{{0x43},{0xA7}}, +{{0x44},{0xB8}}, +{{0x45},{0xD6}}, +{{0x46},{0xEE}}, +{{0x47},{0x0d}}, +{{0x62},{0xf7}}, +{{0x63},{0x68}}, +{{0x64},{0xd3}}, +{{0x65},{0xd3}}, +{{0x66},{0x60}}, +{{0xfe},{0x00}}, +}; + + +/* + * The white balance settings + * Here only tune the R G B channel gain. + * The white balance enalbe bit is modified in sensor_s_autowb and sensor_s_wb + */ +static struct regval_list sensor_wb_auto_regs[] = { + {{0x22},{0x57}}, + {{0x5a},{0x56}}, + {{0x5b},{0x40}}, + {{0x5c},{0x4a}} +}; + +static struct regval_list sensor_wb_cloud_regs[] = { + {{0x22},{0x55}}, + {{0x5a},{0x8c}}, + {{0x5b},{0x50}}, + {{0x5c},{0x40}} +}; + +static struct regval_list sensor_wb_daylight_regs[] = { + //tai yang guang + {{0x22},{0x55}}, + {{0x22},{0x55}}, + {{0x5a},{0x74}}, + {{0x5b},{0x52}}, + {{0x5c},{0x40}} +}; + +static struct regval_list sensor_wb_incandescence_regs[] = { + //bai re guang + {{0x22},{0x55}}, + {{0x5a},{0x48}}, + {{0x5b},{0x40}}, + {{0x5c},{0x5c}} +}; + +static struct regval_list sensor_wb_fluorescent_regs[] = { + //ri guang deng + {{0x22},{0x55}}, + {{0x5a},{0x40}}, + {{0x5b},{0x42}}, + {{0x5c},{0x50}} +}; + +static struct regval_list sensor_wb_tungsten_regs[] = { + //wu si deng + {{0x22},{0x55}}, + {{0x5a},{0x40}}, + {{0x5b},{0x54}}, + {{0x5c},{0x70}} +}; + +/* + * The color effect settings + */ +static struct regval_list sensor_colorfx_none_regs[] = { + {{0x23},{0x00}}, + {{0x2d},{0x0a}}, + {{0x20},{0xff}}, + {{0xd2},{0x90}}, + {{0x73},{0x00}}, + {{0x77},{0x54}}, + {{0xb3},{0x40}}, + {{0xb4},{0x80}}, + {{0xba},{0x00}}, + {{0xbb},{0x00}} +}; + +static struct regval_list sensor_colorfx_bw_regs[] = { + {{0x23},{0x02}}, + {{0x2d},{0x0a}}, + {{0x20},{0xff}}, + {{0xd2},{0x90}}, + {{0x73},{0x00}}, + + {{0xb3},{0x40}}, + {{0xb4},{0x80}}, + {{0xba},{0x00}}, + {{0xbb},{0x00}} +}; + +static struct regval_list sensor_colorfx_sepia_regs[] = { + {{0x23},{0x02}}, + {{0x2d},{0x0a}}, + {{0x20},{0xff}}, + {{0xd2},{0x90}}, + {{0x73},{0x00}}, + + {{0xb3},{0x40}}, + {{0xb4},{0x80}}, + {{0xba},{0xd0}}, + {{0xbb},{0x28}} +}; + +static struct regval_list sensor_colorfx_negative_regs[] = { + {{0x23},{0x01}}, + {{0x2d},{0x0a}}, + {{0x20},{0xff}}, + {{0xd2},{0x90}}, + {{0x73},{0x00}}, + + {{0xb3},{0x40}}, + {{0xb4},{0x80}}, + {{0xba},{0x00}}, + {{0xbb},{0x00}} +}; + +static struct regval_list sensor_colorfx_emboss_regs[] = { + {{0x23},{0x02}}, + {{0x2d},{0x0a}}, + {{0x20},{0xbf}}, + {{0xd2},{0x10}}, + {{0x73},{0x01}}, + + {{0x51},{0x40}}, + {{0x52},{0x40}}, + + {{0xb3},{0x40}}, + {{0xb4},{0x80}}, + {{0xba},{0x00}}, + {{0xbb},{0x00}} +}; + +static struct regval_list sensor_colorfx_sketch_regs[] = { + {{0x23},{0x02}}, + {{0x2d},{0x0a}}, + {{0x20},{0xbf}}, + {{0xd2},{0x10}}, + {{0x73},{0x01}}, + + {{0x51},{0x40}}, + {{0x52},{0x40}}, + + {{0xb3},{0x98}}, + {{0xb4},{0x06}}, + {{0xba},{0x00}}, + {{0xbb},{0x00}} +}; + +static struct regval_list sensor_colorfx_sky_blue_regs[] = { + {{0x23},{0x02}}, + {{0x2d},{0x0a}}, + {{0x20},{0xff}}, + {{0xd2},{0x90}}, + {{0x73},{0x00}}, + + {{0xb3},{0x40}}, + {{0xb4},{0x80}}, + {{0xba},{0x50}}, + {{0xbb},{0xe0}} +}; + +static struct regval_list sensor_colorfx_grass_green_regs[] = { + {{0x23},{0x02}}, + {{0x2d},{0x0a}}, + {{0x20},{0xff}}, + {{0xd2},{0x90}}, + {{0x73},{0x88}}, + + {{0xb3},{0x40}}, + {{0xb4},{0x80}}, + {{0xba},{0xc0}}, + {{0xbb},{0xc0}} +}; + +static struct regval_list sensor_colorfx_skin_whiten_regs[] = { + {{0x23},{0x02}}, + {{0x2d},{0x0a}}, + {{0x20},{0xbf}}, + {{0xd2},{0x10}}, + {{0x73},{0x01}}, + + {{0x51},{0x40}}, + {{0x52},{0x40}}, + + {{0xb3},{0x60}}, + {{0xb4},{0x40}}, + {{0xba},{0x00}}, + {{0xbb},{0x00}} +}; + +static struct regval_list sensor_colorfx_vivid_regs[] = { +//NULL +}; + +/* + * The brightness setttings + */ +static struct regval_list sensor_brightness_neg4_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_neg3_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_neg2_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_neg1_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_zero_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_pos1_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_pos2_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_pos3_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_pos4_regs[] = { +//NULL +}; + +/* + * The contrast setttings + */ +static struct regval_list sensor_contrast_neg4_regs[] = { +//NULL +}; + +static struct regval_list sensor_contrast_neg3_regs[] = { +//NULL +}; + +static struct regval_list sensor_contrast_neg2_regs[] = { +//NULL +}; + +static struct regval_list sensor_contrast_neg1_regs[] = { +//NULL +}; + +static struct regval_list sensor_contrast_zero_regs[] = { +//NULL +}; + +static struct regval_list sensor_contrast_pos1_regs[] = { +//NULL +}; + +static struct regval_list sensor_contrast_pos2_regs[] = { +//NULL +}; + +static struct regval_list sensor_contrast_pos3_regs[] = { +//NULL +}; + +static struct regval_list sensor_contrast_pos4_regs[] = { +//NULL +}; + +/* + * The saturation setttings + */ +static struct regval_list sensor_saturation_neg4_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_neg3_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_neg2_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_neg1_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_zero_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_pos1_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_pos2_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_pos3_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_pos4_regs[] = { +//NULL +}; + +/* + * The exposure target setttings + */ +static struct regval_list sensor_ev_neg4_regs[] = { + {{0xb5},{0xc0}}, + {{0xd3},{0x28}} +}; + +static struct regval_list sensor_ev_neg3_regs[] = { + {{0xb5},{0xd0}}, + {{0xd3},{0x30}} +}; + +static struct regval_list sensor_ev_neg2_regs[] = { + {{0xb5},{0xe0}}, + {{0xd3},{0x38}} +}; + +static struct regval_list sensor_ev_neg1_regs[] = { + {{0xb5},{0xf0}}, + {{0xd3},{0x40}} +}; + +static struct regval_list sensor_ev_zero_regs[] = { + {{0xb5},{0x00}}, + {{0xd3},{0x48}} +}; + +static struct regval_list sensor_ev_pos1_regs[] = { + {{0xb5},{0x10}}, + {{0xd3},{0x50}} +}; + +static struct regval_list sensor_ev_pos2_regs[] = { + {{0xb5},{0x20}}, + {{0xd3},{0x58}} +}; + +static struct regval_list sensor_ev_pos3_regs[] = { + {{0xb5},{0x30}}, + {{0xd3},{0x60}} +}; + +static struct regval_list sensor_ev_pos4_regs[] = { + {{0xb5},{0x40}}, + {{0xd3},{0x68}} +}; + + +/* + * Here we'll try to encapsulate the changes for just the output + * video format. + * + */ + + +static struct regval_list sensor_fmt_yuv422_yuyv[] = { + {{0x24},{0xa2}} //YCbYCr +}; + +static struct regval_list sensor_fmt_yuv422_yvyu[] = { + {{0x24},{0xa3}} //YCrYCb +}; + +static struct regval_list sensor_fmt_yuv422_vyuy[] = { + {{0x24},{0xa1}} //CrYCbY +}; + +static struct regval_list sensor_fmt_yuv422_uyvy[] = { + {{0x24},{0xa0}} //CbYCrY +}; + +static struct regval_list sensor_fmt_raw[] = { + {{0x24},{0xb7}}//raw +}; + + + +/* + * Low-level register I/O. + * + */ + + +/* + * On most platforms, we'd rather do straight i2c I/O. + */ +static int sensor_read(struct v4l2_subdev *sd, unsigned char *reg, + unsigned char *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 data[REG_STEP]; + struct i2c_msg msg; + int ret,i; + + for(i = 0; i < REG_ADDR_STEP; i++) + data[i] = reg[i]; + + data[REG_ADDR_STEP] = 0xff; + /* + * Send out the register address... + */ + msg.addr = client->addr; + msg.flags = 0; + msg.len = REG_ADDR_STEP; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret < 0) { + csi_dev_err("Error %d on register write\n", ret); + return ret; + } + /* + * ...then read back the result. + */ + + msg.flags = I2C_M_RD; + msg.len = REG_DATA_STEP; + msg.buf = &data[REG_ADDR_STEP]; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret >= 0) { + for(i = 0; i < REG_DATA_STEP; i++) + value[i] = data[i+REG_ADDR_STEP]; + ret = 0; + } + else { + csi_dev_err("Error %d on register read\n", ret); + } + return ret; +} + + +static int sensor_write(struct v4l2_subdev *sd, unsigned char *reg, + unsigned char *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct i2c_msg msg; + unsigned char data[REG_STEP]; + int ret,i; + + for(i = 0; i < REG_ADDR_STEP; i++) + data[i] = reg[i]; + for(i = REG_ADDR_STEP; i < REG_STEP; i++) + data[i] = value[i-REG_ADDR_STEP]; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = REG_STEP; + msg.buf = data; + + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret > 0) { + ret = 0; + } + else if (ret < 0) { + csi_dev_err("sensor_write error!\n"); + } + return ret; +} + + +/* + * Write a list of register settings; + */ +static int sensor_write_array(struct v4l2_subdev *sd, struct regval_list *vals , uint size) +{ + int i,ret; + + if (size == 0) + return -EINVAL; + + for(i = 0; i < size ; i++) + { + ret = sensor_write(sd, vals->reg_num, vals->value); + if (ret < 0) + { + csi_dev_err("sensor_write_err!\n"); + return ret; + } + udelay(100); + vals++; + } + + return 0; +} + + +/* + * Stuff that knows about the sensor. + */ + +static int sensor_power(struct v4l2_subdev *sd, int on) +{ + struct csi_dev *dev=(struct csi_dev *)dev_get_drvdata(sd->v4l2_dev->dev); + struct sensor_info *info = to_state(sd); + char csi_stby_str[32],csi_power_str[32],csi_reset_str[32]; + + if(info->ccm_info->iocfg == 0) { + strcpy(csi_stby_str,"csi_stby"); + strcpy(csi_power_str,"csi_power_en"); + strcpy(csi_reset_str,"csi_reset"); + } else if(info->ccm_info->iocfg == 1) { + strcpy(csi_stby_str,"csi_stby_b"); + strcpy(csi_power_str,"csi_power_en_b"); + strcpy(csi_reset_str,"csi_reset_b"); + } + + switch(on) + { + case CSI_SUBDEV_STBY_ON: + csi_dev_dbg("CSI_SUBDEV_STBY_ON\n"); + //reset off io + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + msleep(10); + //active mclk before stadby in + clk_enable(dev->csi_module_clk); + msleep(100); + //standby on io + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_STBY_ON,csi_stby_str); + msleep(100); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_STBY_OFF,csi_stby_str); + msleep(100); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_STBY_ON,csi_stby_str); + msleep(100); + //inactive mclk after stadby in + clk_disable(dev->csi_module_clk); + + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_ON,csi_reset_str); + msleep(10); + break; + case CSI_SUBDEV_STBY_OFF: + csi_dev_dbg("CSI_SUBDEV_STBY_OFF\n"); + //active mclk before stadby out + clk_enable(dev->csi_module_clk); + msleep(10); + //reset off io + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + msleep(10); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_ON,csi_reset_str); + msleep(100); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_STBY_OFF,csi_stby_str); + msleep(10); + break; + case CSI_SUBDEV_PWR_ON: + csi_dev_dbg("CSI_SUBDEV_PWR_ON\n"); + //inactive mclk before power on + clk_disable(dev->csi_module_clk); + //power on reset + gpio_set_one_pin_io_status(dev->csi_pin_hd,1,csi_stby_str);//set the gpio to output + gpio_set_one_pin_io_status(dev->csi_pin_hd,1,csi_reset_str);//set the gpio to output + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_STBY_ON,csi_stby_str); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_ON,csi_reset_str); + msleep(1); + //power supply + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_PWR_ON,csi_power_str); + msleep(10); + if(dev->dvdd) { + regulator_enable(dev->dvdd); + msleep(10); + } + if(dev->avdd) { + regulator_enable(dev->avdd); + msleep(10); + } + if(dev->iovdd) { + regulator_enable(dev->iovdd); + msleep(10); + } + //active mclk before power on + clk_enable(dev->csi_module_clk); + //reset after power on + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + msleep(10); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_ON,csi_reset_str); + msleep(100); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + msleep(100); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_STBY_OFF,csi_stby_str); + msleep(10); + break; + + case CSI_SUBDEV_PWR_OFF: + csi_dev_dbg("CSI_SUBDEV_PWR_OFF\n"); + //power supply off + if(dev->iovdd) { + regulator_disable(dev->iovdd); + msleep(10); + } + if(dev->avdd) { + regulator_disable(dev->avdd); + msleep(10); + } + if(dev->dvdd) { + regulator_disable(dev->dvdd); + msleep(10); + } + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_PWR_OFF,csi_power_str); + msleep(10); + + //inactive mclk after power off + clk_disable(dev->csi_module_clk); + + //set the io to hi-z + gpio_set_one_pin_io_status(dev->csi_pin_hd,0,csi_reset_str);//set the gpio to input + gpio_set_one_pin_io_status(dev->csi_pin_hd,0,csi_stby_str);//set the gpio to input + break; + default: + return -EINVAL; + } + + return 0; +} + +static int sensor_reset(struct v4l2_subdev *sd, u32 val) +{ + struct csi_dev *dev=(struct csi_dev *)dev_get_drvdata(sd->v4l2_dev->dev); + struct sensor_info *info = to_state(sd); + char csi_reset_str[32]; + + if(info->ccm_info->iocfg == 0) { + strcpy(csi_reset_str,"csi_reset"); + } else if(info->ccm_info->iocfg == 1) { + strcpy(csi_reset_str,"csi_reset_b"); + } + + switch(val) + { + case CSI_SUBDEV_RST_OFF: + csi_dev_dbg("CSI_SUBDEV_RST_OFF\n"); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + msleep(10); + break; + case CSI_SUBDEV_RST_ON: + csi_dev_dbg("CSI_SUBDEV_RST_ON\n"); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_ON,csi_reset_str); + msleep(10); + break; + case CSI_SUBDEV_RST_PUL: + csi_dev_dbg("CSI_SUBDEV_RST_PUL\n"); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + msleep(10); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_ON,csi_reset_str); + msleep(100); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + msleep(10); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int sensor_detect(struct v4l2_subdev *sd) +{ + int ret; + struct regval_list regs; + + regs.reg_num[0] = 0xfe; + regs.value[0] = 0x00; //PAGE 0x00 + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_detect!\n"); + return ret; + } + + regs.reg_num[0] = 0x00; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_detect!\n"); + return ret; + } + + if(regs.value[0] != 0x9b) + return -ENODEV; + + return 0; +} + +static int sensor_init(struct v4l2_subdev *sd, u32 val) +{ + int ret; + csi_dev_dbg("sensor_init\n"); + /*Make sure it is a target sensor*/ + ret = sensor_detect(sd); + if (ret) { + csi_dev_err("chip found is not an target chip.\n"); + return ret; + } + + switch(magic_ver) { + case SUNXI_VER_A10A: + case SUNXI_VER_A10B: + sensor_write_array(sd, sensor_default_regs_49p5M , ARRAY_SIZE(sensor_default_regs_49p5M)); + break; + case SUNXI_VER_A10C: + sensor_write_array(sd, sensor_default_regs_24M , ARRAY_SIZE(sensor_default_regs_24M)); + break; + default: + sensor_write_array(sd, sensor_default_regs_24M , ARRAY_SIZE(sensor_default_regs_24M)); + break; + } + return sensor_write_array(sd, sensor_default_regs , ARRAY_SIZE(sensor_default_regs)); +} + +static long sensor_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + int ret=0; + + switch(cmd){ + case CSI_SUBDEV_CMD_GET_INFO: + { + struct sensor_info *info = to_state(sd); + __csi_subdev_info_t *ccm_info = arg; + + csi_dev_dbg("CSI_SUBDEV_CMD_GET_INFO\n"); + + ccm_info->mclk = info->ccm_info->mclk ; + ccm_info->vref = info->ccm_info->vref ; + ccm_info->href = info->ccm_info->href ; + ccm_info->clock = info->ccm_info->clock; + ccm_info->iocfg = info->ccm_info->iocfg; + + csi_dev_dbg("ccm_info.mclk=%x\n ",info->ccm_info->mclk); + csi_dev_dbg("ccm_info.vref=%x\n ",info->ccm_info->vref); + csi_dev_dbg("ccm_info.href=%x\n ",info->ccm_info->href); + csi_dev_dbg("ccm_info.clock=%x\n ",info->ccm_info->clock); + csi_dev_dbg("ccm_info.iocfg=%x\n ",info->ccm_info->iocfg); + break; + } + case CSI_SUBDEV_CMD_SET_INFO: + { + struct sensor_info *info = to_state(sd); + __csi_subdev_info_t *ccm_info = arg; + + csi_dev_dbg("CSI_SUBDEV_CMD_SET_INFO\n"); + + info->ccm_info->mclk = ccm_info->mclk ; + info->ccm_info->vref = ccm_info->vref ; + info->ccm_info->href = ccm_info->href ; + info->ccm_info->clock = ccm_info->clock ; + info->ccm_info->iocfg = ccm_info->iocfg ; + + csi_dev_dbg("ccm_info.mclk=%x\n ",info->ccm_info->mclk); + csi_dev_dbg("ccm_info.vref=%x\n ",info->ccm_info->vref); + csi_dev_dbg("ccm_info.href=%x\n ",info->ccm_info->href); + csi_dev_dbg("ccm_info.clock=%x\n ",info->ccm_info->clock); + csi_dev_dbg("ccm_info.iocfg=%x\n ",info->ccm_info->iocfg); + + break; + } + default: + return -EINVAL; + } + return ret; +} + + +/* + * Store information about the video data format. + */ +static struct sensor_format_struct { + __u8 *desc; + //__u32 pixelformat; + enum v4l2_mbus_pixelcode mbus_code;//linux-3.0 + struct regval_list *regs; + int regs_size; + int bpp; /* Bytes per pixel */ +} sensor_formats[] = { + { + .desc = "YUYV 4:2:2", + .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,//linux-3.0 + .regs = sensor_fmt_yuv422_yuyv, + .regs_size = ARRAY_SIZE(sensor_fmt_yuv422_yuyv), + .bpp = 2, + }, + { + .desc = "YVYU 4:2:2", + .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,//linux-3.0 + .regs = sensor_fmt_yuv422_yvyu, + .regs_size = ARRAY_SIZE(sensor_fmt_yuv422_yvyu), + .bpp = 2, + }, + { + .desc = "UYVY 4:2:2", + .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,//linux-3.0 + .regs = sensor_fmt_yuv422_uyvy, + .regs_size = ARRAY_SIZE(sensor_fmt_yuv422_uyvy), + .bpp = 2, + }, + { + .desc = "VYUY 4:2:2", + .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,//linux-3.0 + .regs = sensor_fmt_yuv422_vyuy, + .regs_size = ARRAY_SIZE(sensor_fmt_yuv422_vyuy), + .bpp = 2, + }, + { + .desc = "Raw RGB Bayer", + .mbus_code = V4L2_MBUS_FMT_SBGGR8_1X8,//linux-3.0 + .regs = sensor_fmt_raw, + .regs_size = ARRAY_SIZE(sensor_fmt_raw), + .bpp = 1 + }, +}; +#define N_FMTS ARRAY_SIZE(sensor_formats) + + +/* + * Then there is the issue of window sizes. Try to capture the info here. + */ + + +static struct sensor_win_size { + int width; + int height; + int hstart; /* Start/stop values for the camera. Note */ + int hstop; /* that they do not always make complete */ + int vstart; /* sense to humans, but evidently the sensor */ + int vstop; /* will do the right thing... */ + struct regval_list *regs; /* Regs to tweak */ + int regs_size; + int (*set_size) (struct v4l2_subdev *sd); +/* h/vref stuff */ +} sensor_win_sizes[] = { + /* VGA */ + { + .width = VGA_WIDTH, + .height = VGA_HEIGHT, + .regs = NULL, + .regs_size = 0, + .set_size = NULL, + } +}; + +#define N_WIN_SIZES (ARRAY_SIZE(sensor_win_sizes)) + + + + +static int sensor_enum_fmt(struct v4l2_subdev *sd, unsigned index, + enum v4l2_mbus_pixelcode *code)//linux-3.0 +{ +// struct sensor_format_struct *ofmt; + + if (index >= N_FMTS)//linux-3.0 + return -EINVAL; + + *code = sensor_formats[index].mbus_code;//linux-3.0 + +// ofmt = sensor_formats + fmt->index; +// fmt->flags = 0; +// strcpy(fmt->description, ofmt->desc); +// fmt->pixelformat = ofmt->pixelformat; + return 0; +} + + +static int sensor_try_fmt_internal(struct v4l2_subdev *sd, + //struct v4l2_format *fmt, + struct v4l2_mbus_framefmt *fmt,//linux-3.0 + struct sensor_format_struct **ret_fmt, + struct sensor_win_size **ret_wsize) +{ + int index; + struct sensor_win_size *wsize; +// struct v4l2_pix_format *pix = &fmt->fmt.pix;//linux-3.0 + csi_dev_dbg("sensor_try_fmt_internal\n"); + for (index = 0; index < N_FMTS; index++) + if (sensor_formats[index].mbus_code == fmt->code)//linux-3.0 + break; + + if (index >= N_FMTS) { + /* default to first format */ + index = 0; + fmt->code = sensor_formats[0].mbus_code;//linux-3.0 + } + + if (ret_fmt != NULL) + *ret_fmt = sensor_formats + index; + + /* + * Fields: the sensor devices claim to be progressive. + */ + fmt->field = V4L2_FIELD_NONE;//linux-3.0 + + + /* + * Round requested image size down to the nearest + * we support, but not below the smallest. + */ + for (wsize = sensor_win_sizes; wsize < sensor_win_sizes + N_WIN_SIZES; + wsize++) + if (fmt->width >= wsize->width && fmt->height >= wsize->height)//linux-3.0 + break; + + if (wsize >= sensor_win_sizes + N_WIN_SIZES) + wsize--; /* Take the smallest one */ + if (ret_wsize != NULL) + *ret_wsize = wsize; + /* + * Note the size we'll actually handle. + */ + fmt->width = wsize->width;//linux-3.0 + fmt->height = wsize->height;//linux-3.0 + //pix->bytesperline = pix->width*sensor_formats[index].bpp;//linux-3.0 + //pix->sizeimage = pix->height*pix->bytesperline;//linux-3.0 + + return 0; +} + +static int sensor_try_fmt(struct v4l2_subdev *sd, + struct v4l2_mbus_framefmt *fmt)//linux-3.0 +{ + return sensor_try_fmt_internal(sd, fmt, NULL, NULL); +} + +/* + * Set a format. + */ +static int sensor_s_fmt(struct v4l2_subdev *sd, + struct v4l2_mbus_framefmt *fmt)//linux-3.0 +{ + int ret; + struct sensor_format_struct *sensor_fmt; + struct sensor_win_size *wsize; + struct sensor_info *info = to_state(sd); + + csi_dev_dbg("sensor_s_fmt\n"); + + ret = sensor_try_fmt_internal(sd, fmt, &sensor_fmt, &wsize); + if (ret) + return ret; + + sensor_write_array(sd, sensor_fmt->regs , sensor_fmt->regs_size); + + ret = 0; + if (wsize->regs) + { + ret = sensor_write_array(sd, wsize->regs , wsize->regs_size); + if (ret < 0) + return ret; + } + + if (wsize->set_size) + { + ret = wsize->set_size(sd); + if (ret < 0) + return ret; + } + + info->fmt = sensor_fmt; + info->width = wsize->width; + info->height = wsize->height; + + return 0; +} + +/* + * Implement G/S_PARM. There is a "high quality" mode we could try + * to do someday; for now, we just do the frame rate tweak. + */ +static int sensor_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) +{ + struct v4l2_captureparm *cp = &parms->parm.capture; + //struct sensor_info *info = to_state(sd); + + if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + memset(cp, 0, sizeof(struct v4l2_captureparm)); + cp->capability = V4L2_CAP_TIMEPERFRAME; + cp->timeperframe.numerator = 1; + cp->timeperframe.denominator = SENSOR_FRAME_RATE; + + return 0; +} + +static int sensor_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) +{ +// struct v4l2_captureparm *cp = &parms->parm.capture; + //struct v4l2_fract *tpf = &cp->timeperframe; + //struct sensor_info *info = to_state(sd); + //int div; + +// if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) +// return -EINVAL; +// if (cp->extendedmode != 0) +// return -EINVAL; + +// if (tpf->numerator == 0 || tpf->denominator == 0) +// div = 1; /* Reset to full rate */ +// else +// div = (tpf->numerator*SENSOR_FRAME_RATE)/tpf->denominator; +// +// if (div == 0) +// div = 1; +// else if (div > CLK_SCALE) +// div = CLK_SCALE; +// info->clkrc = (info->clkrc & 0x80) | div; +// tpf->numerator = 1; +// tpf->denominator = sensor_FRAME_RATE/div; +//sensor_write(sd, REG_CLKRC, info->clkrc); + return -EINVAL; +} + + +/* + * Code for dealing with controls. + * fill with different sensor module + * different sensor module has different settings here + * if not support the follow function ,retrun -EINVAL + */ + +/* *********************************************begin of ******************************************** */ +static int sensor_queryctrl(struct v4l2_subdev *sd, + struct v4l2_queryctrl *qc) +{ + /* Fill in min, max, step and default value for these controls. */ + /* see include/linux/videodev2.h for details */ + /* see sensor_s_parm and sensor_g_parm for the meaning of value */ + + switch (qc->id) { +// case V4L2_CID_BRIGHTNESS: +// return v4l2_ctrl_query_fill(qc, -4, 4, 1, 1); +// case V4L2_CID_CONTRAST: +// return v4l2_ctrl_query_fill(qc, -4, 4, 1, 1); +// case V4L2_CID_SATURATION: +// return v4l2_ctrl_query_fill(qc, -4, 4, 1, 1); +// case V4L2_CID_HUE: +// return v4l2_ctrl_query_fill(qc, -180, 180, 5, 0); + case V4L2_CID_VFLIP: + case V4L2_CID_HFLIP: + return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0); +// case V4L2_CID_GAIN: +// return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128); +// case V4L2_CID_AUTOGAIN: +// return v4l2_ctrl_query_fill(qc, 0, 1, 1, 1); + case V4L2_CID_EXPOSURE: + return v4l2_ctrl_query_fill(qc, -4, 4, 1, 0); + case V4L2_CID_EXPOSURE_AUTO: + return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0); + case V4L2_CID_DO_WHITE_BALANCE: + return v4l2_ctrl_query_fill(qc, 0, 5, 1, 0); + case V4L2_CID_AUTO_WHITE_BALANCE: + return v4l2_ctrl_query_fill(qc, 0, 1, 1, 1); + case V4L2_CID_COLORFX: + return v4l2_ctrl_query_fill(qc, 0, 9, 1, 0); + case V4L2_CID_CAMERA_FLASH_MODE: + return v4l2_ctrl_query_fill(qc, 0, 4, 1, 0); + } + return -EINVAL; +} + +static int sensor_g_hflip(struct v4l2_subdev *sd, __s32 *value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + regs.reg_num[0] = 0xfe; + regs.value[0] = 0x00; //page 0 + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_g_hflip!\n"); + return ret; + } + + regs.reg_num[0] = 0x14; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_g_hflip!\n"); + return ret; + } + + regs.value[0] &= (1<<0); + regs.value[0] = regs.value[0]>>0; //0x14 bit0 is mirror + + *value = regs.value[0]; + + info->hflip = *value; + return 0; +} + +static int sensor_s_hflip(struct v4l2_subdev *sd, int value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + regs.reg_num[0] = 0xfe; + regs.value[0] = 0x00; //page 0 + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_s_hflip!\n"); + return ret; + } + + regs.reg_num[0] = 0x14; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_s_hflip!\n"); + return ret; + } + + switch (value) { + case 0: + regs.value[0] &= 0xfe; + break; + case 1: + regs.value[0] |= 0x01; + break; + default: + return -EINVAL; + } + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_s_hflip!\n"); + return ret; + } + + msleep(100); + + info->hflip = value; + return 0; +} + +static int sensor_g_vflip(struct v4l2_subdev *sd, __s32 *value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + regs.reg_num[0] = 0xfe; + regs.value[0] = 0x00; //page 0 + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_g_vflip!\n"); + return ret; + } + + regs.reg_num[0] = 0x14; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_g_vflip!\n"); + return ret; + } + + regs.value[0] &= (1<<1); + regs.value[0] = regs.value[0]>>1; //0x14 bit1 is upsidedown + + *value = regs.value[0]; + + info->vflip = *value; + return 0; +} + +static int sensor_s_vflip(struct v4l2_subdev *sd, int value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + regs.reg_num[0] = 0xfe; + regs.value[0] = 0x00; //page 0 + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_s_vflip!\n"); + return ret; + } + + regs.reg_num[0] = 0x14; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_s_vflip!\n"); + return ret; + } + + switch (value) { + case 0: + regs.value[0] &= 0xfd; + break; + case 1: + regs.value[0] |= 0x02; + break; + default: + return -EINVAL; + } + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_s_vflip!\n"); + return ret; + } + + msleep(100); + + info->vflip = value; + return 0; +} + +static int sensor_g_autogain(struct v4l2_subdev *sd, __s32 *value) +{ + return -EINVAL; +} + +static int sensor_s_autogain(struct v4l2_subdev *sd, int value) +{ + return -EINVAL; +} + +static int sensor_g_autoexp(struct v4l2_subdev *sd, __s32 *value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + regs.reg_num[0] = 0xd2; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_g_autoexp!\n"); + return ret; + } + + regs.value[0] &= 0x80; + if (regs.value[0] == 0x80) { + *value = V4L2_EXPOSURE_AUTO; + } + else + { + *value = V4L2_EXPOSURE_MANUAL; + } + + info->autoexp = *value; + return 0; +} + +static int sensor_s_autoexp(struct v4l2_subdev *sd, + enum v4l2_exposure_auto_type value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + regs.reg_num[0] = 0xd2; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_s_autoexp!\n"); + return ret; + } + + switch (value) { + case V4L2_EXPOSURE_AUTO: + regs.value[0] |= 0x80; + break; + case V4L2_EXPOSURE_MANUAL: + regs.value[0] &= 0x7f; + break; + case V4L2_EXPOSURE_SHUTTER_PRIORITY: + return -EINVAL; + case V4L2_EXPOSURE_APERTURE_PRIORITY: + return -EINVAL; + default: + return -EINVAL; + } + + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_s_autoexp!\n"); + return ret; + } + + msleep(10); + + info->autoexp = value; + return 0; +} + +static int sensor_g_autowb(struct v4l2_subdev *sd, int *value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + regs.reg_num[0] = 0x22; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_g_autowb!\n"); + return ret; + } + + regs.value[0] &= (1<<1); + regs.value[0] = regs.value[0]>>1; //0x22 bit1 is awb enable + + *value = regs.value[0]; + info->autowb = *value; + + return 0; +} + +static int sensor_s_autowb(struct v4l2_subdev *sd, int value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + ret = sensor_write_array(sd, sensor_wb_auto_regs, ARRAY_SIZE(sensor_wb_auto_regs)); + if (ret < 0) { + csi_dev_err("sensor_write_array err at sensor_s_autowb!\n"); + return ret; + } + + regs.reg_num[0] = 0x22; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_s_autowb!\n"); + return ret; + } + + switch(value) { + case 0: + regs.value[0] &= 0xfd; + break; + case 1: + regs.value[0] |= 0x02; + break; + default: + break; + } + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_s_autowb!\n"); + return ret; + } + + msleep(100); + + info->autowb = value; + return 0; +} + +static int sensor_g_hue(struct v4l2_subdev *sd, __s32 *value) +{ + return -EINVAL; +} + +static int sensor_s_hue(struct v4l2_subdev *sd, int value) +{ + return -EINVAL; +} + +static int sensor_g_gain(struct v4l2_subdev *sd, __s32 *value) +{ + return -EINVAL; +} + +static int sensor_s_gain(struct v4l2_subdev *sd, int value) +{ + return -EINVAL; +} +/* *********************************************end of ******************************************** */ + +static int sensor_g_brightness(struct v4l2_subdev *sd, __s32 *value) +{ + struct sensor_info *info = to_state(sd); + + *value = info->brightness; + return 0; +} + +static int sensor_s_brightness(struct v4l2_subdev *sd, int value) +{ + int ret; + struct sensor_info *info = to_state(sd); + + switch (value) { + case -4: + ret = sensor_write_array(sd, sensor_brightness_neg4_regs, ARRAY_SIZE(sensor_brightness_neg4_regs)); + break; + case -3: + ret = sensor_write_array(sd, sensor_brightness_neg3_regs, ARRAY_SIZE(sensor_brightness_neg3_regs)); + break; + case -2: + ret = sensor_write_array(sd, sensor_brightness_neg2_regs, ARRAY_SIZE(sensor_brightness_neg2_regs)); + break; + case -1: + ret = sensor_write_array(sd, sensor_brightness_neg1_regs, ARRAY_SIZE(sensor_brightness_neg1_regs)); + break; + case 0: + ret = sensor_write_array(sd, sensor_brightness_zero_regs, ARRAY_SIZE(sensor_brightness_zero_regs)); + break; + case 1: + ret = sensor_write_array(sd, sensor_brightness_pos1_regs, ARRAY_SIZE(sensor_brightness_pos1_regs)); + break; + case 2: + ret = sensor_write_array(sd, sensor_brightness_pos2_regs, ARRAY_SIZE(sensor_brightness_pos2_regs)); + break; + case 3: + ret = sensor_write_array(sd, sensor_brightness_pos3_regs, ARRAY_SIZE(sensor_brightness_pos3_regs)); + break; + case 4: + ret = sensor_write_array(sd, sensor_brightness_pos4_regs, ARRAY_SIZE(sensor_brightness_pos4_regs)); + break; + default: + return -EINVAL; + } + + if (ret < 0) { + csi_dev_err("sensor_write_array err at sensor_s_brightness!\n"); + return ret; + } + + msleep(10); + + info->brightness = value; + return 0; +} + +static int sensor_g_contrast(struct v4l2_subdev *sd, __s32 *value) +{ + struct sensor_info *info = to_state(sd); + + *value = info->contrast; + return 0; +} + +static int sensor_s_contrast(struct v4l2_subdev *sd, int value) +{ + int ret; + struct sensor_info *info = to_state(sd); + + switch (value) { + case -4: + ret = sensor_write_array(sd, sensor_contrast_neg4_regs, ARRAY_SIZE(sensor_contrast_neg4_regs)); + break; + case -3: + ret = sensor_write_array(sd, sensor_contrast_neg3_regs, ARRAY_SIZE(sensor_contrast_neg3_regs)); + break; + case -2: + ret = sensor_write_array(sd, sensor_contrast_neg2_regs, ARRAY_SIZE(sensor_contrast_neg2_regs)); + break; + case -1: + ret = sensor_write_array(sd, sensor_contrast_neg1_regs, ARRAY_SIZE(sensor_contrast_neg1_regs)); + break; + case 0: + ret = sensor_write_array(sd, sensor_contrast_zero_regs, ARRAY_SIZE(sensor_contrast_zero_regs)); + break; + case 1: + ret = sensor_write_array(sd, sensor_contrast_pos1_regs, ARRAY_SIZE(sensor_contrast_pos1_regs)); + break; + case 2: + ret = sensor_write_array(sd, sensor_contrast_pos2_regs, ARRAY_SIZE(sensor_contrast_pos2_regs)); + break; + case 3: + ret = sensor_write_array(sd, sensor_contrast_pos3_regs, ARRAY_SIZE(sensor_contrast_pos3_regs)); + break; + case 4: + ret = sensor_write_array(sd, sensor_contrast_pos4_regs, ARRAY_SIZE(sensor_contrast_pos4_regs)); + break; + default: + return -EINVAL; + } + + if (ret < 0) { + csi_dev_err("sensor_write_array err at sensor_s_contrast!\n"); + return ret; + } + + msleep(10); + + info->contrast = value; + return 0; +} + +static int sensor_g_saturation(struct v4l2_subdev *sd, __s32 *value) +{ + struct sensor_info *info = to_state(sd); + + *value = info->saturation; + return 0; +} + +static int sensor_s_saturation(struct v4l2_subdev *sd, int value) +{ + int ret; + struct sensor_info *info = to_state(sd); + + switch (value) { + case -4: + ret = sensor_write_array(sd, sensor_saturation_neg4_regs, ARRAY_SIZE(sensor_saturation_neg4_regs)); + break; + case -3: + ret = sensor_write_array(sd, sensor_saturation_neg3_regs, ARRAY_SIZE(sensor_saturation_neg3_regs)); + break; + case -2: + ret = sensor_write_array(sd, sensor_saturation_neg2_regs, ARRAY_SIZE(sensor_saturation_neg2_regs)); + break; + case -1: + ret = sensor_write_array(sd, sensor_saturation_neg1_regs, ARRAY_SIZE(sensor_saturation_neg1_regs)); + break; + case 0: + ret = sensor_write_array(sd, sensor_saturation_zero_regs, ARRAY_SIZE(sensor_saturation_zero_regs)); + break; + case 1: + ret = sensor_write_array(sd, sensor_saturation_pos1_regs, ARRAY_SIZE(sensor_saturation_pos1_regs)); + break; + case 2: + ret = sensor_write_array(sd, sensor_saturation_pos2_regs, ARRAY_SIZE(sensor_saturation_pos2_regs)); + break; + case 3: + ret = sensor_write_array(sd, sensor_saturation_pos3_regs, ARRAY_SIZE(sensor_saturation_pos3_regs)); + break; + case 4: + ret = sensor_write_array(sd, sensor_saturation_pos4_regs, ARRAY_SIZE(sensor_saturation_pos4_regs)); + break; + default: + return -EINVAL; + } + + if (ret < 0) { + csi_dev_err("sensor_write_array err at sensor_s_saturation!\n"); + return ret; + } + + msleep(10); + + info->saturation = value; + return 0; +} + +static int sensor_g_exp(struct v4l2_subdev *sd, __s32 *value) +{ + struct sensor_info *info = to_state(sd); + + *value = info->exp; + return 0; +} + +static int sensor_s_exp(struct v4l2_subdev *sd, int value) +{ + int ret; + struct sensor_info *info = to_state(sd); + + switch (value) { + case -4: + ret = sensor_write_array(sd, sensor_ev_neg4_regs, ARRAY_SIZE(sensor_ev_neg4_regs)); + break; + case -3: + ret = sensor_write_array(sd, sensor_ev_neg3_regs, ARRAY_SIZE(sensor_ev_neg3_regs)); + break; + case -2: + ret = sensor_write_array(sd, sensor_ev_neg2_regs, ARRAY_SIZE(sensor_ev_neg2_regs)); + break; + case -1: + ret = sensor_write_array(sd, sensor_ev_neg1_regs, ARRAY_SIZE(sensor_ev_neg1_regs)); + break; + case 0: + ret = sensor_write_array(sd, sensor_ev_zero_regs, ARRAY_SIZE(sensor_ev_zero_regs)); + break; + case 1: + ret = sensor_write_array(sd, sensor_ev_pos1_regs, ARRAY_SIZE(sensor_ev_pos1_regs)); + break; + case 2: + ret = sensor_write_array(sd, sensor_ev_pos2_regs, ARRAY_SIZE(sensor_ev_pos2_regs)); + break; + case 3: + ret = sensor_write_array(sd, sensor_ev_pos3_regs, ARRAY_SIZE(sensor_ev_pos3_regs)); + break; + case 4: + ret = sensor_write_array(sd, sensor_ev_pos4_regs, ARRAY_SIZE(sensor_ev_pos4_regs)); + break; + default: + return -EINVAL; + } + + if (ret < 0) { + csi_dev_err("sensor_write_array err at sensor_s_exp!\n"); + return ret; + } + + msleep(10); + + info->exp = value; + return 0; +} + +static int sensor_g_wb(struct v4l2_subdev *sd, int *value) +{ + struct sensor_info *info = to_state(sd); + enum v4l2_whiteblance *wb_type = (enum v4l2_whiteblance*)value; + + *wb_type = info->wb; + + return 0; +} + +static int sensor_s_wb(struct v4l2_subdev *sd, + enum v4l2_whiteblance value) +{ + int ret; + struct sensor_info *info = to_state(sd); + + if (value == V4L2_WB_AUTO) { +// ret = sensor_s_autowb(sd, 1); +// return ret; + ret = sensor_write_array(sd, sensor_wb_auto_regs, ARRAY_SIZE(sensor_wb_auto_regs)); + info->autowb = 1; + } + else { +// ret = sensor_s_autowb(sd, 0); +// if(ret < 0) { +// csi_dev_err("sensor_s_autowb error, return %x!\n",ret); +// return ret; +// } + switch (value) { + case V4L2_WB_CLOUD: + ret = sensor_write_array(sd, sensor_wb_cloud_regs, ARRAY_SIZE(sensor_wb_cloud_regs)); + break; + case V4L2_WB_DAYLIGHT: + ret = sensor_write_array(sd, sensor_wb_daylight_regs, ARRAY_SIZE(sensor_wb_daylight_regs)); + break; + case V4L2_WB_INCANDESCENCE: + ret = sensor_write_array(sd, sensor_wb_incandescence_regs, ARRAY_SIZE(sensor_wb_incandescence_regs)); + break; + case V4L2_WB_FLUORESCENT: + ret = sensor_write_array(sd, sensor_wb_fluorescent_regs, ARRAY_SIZE(sensor_wb_fluorescent_regs)); + break; + case V4L2_WB_TUNGSTEN: + ret = sensor_write_array(sd, sensor_wb_tungsten_regs, ARRAY_SIZE(sensor_wb_tungsten_regs)); + break; + default: + return -EINVAL; + } + info->autowb = 0; + } + + if (ret < 0) { + csi_dev_err("sensor_s_wb error, return %x!\n",ret); + return ret; + } + + msleep(100); + + info->wb = value; + return 0; +} + +static int sensor_g_colorfx(struct v4l2_subdev *sd, + __s32 *value) +{ + struct sensor_info *info = to_state(sd); + enum v4l2_colorfx *clrfx_type = (enum v4l2_colorfx*)value; + + *clrfx_type = info->clrfx; + return 0; +} + +static int sensor_s_colorfx(struct v4l2_subdev *sd, + enum v4l2_colorfx value) +{ + int ret; + struct sensor_info *info = to_state(sd); + + switch (value) { + case V4L2_COLORFX_NONE: + ret = sensor_write_array(sd, sensor_colorfx_none_regs, ARRAY_SIZE(sensor_colorfx_none_regs)); + break; + case V4L2_COLORFX_BW: + ret = sensor_write_array(sd, sensor_colorfx_bw_regs, ARRAY_SIZE(sensor_colorfx_bw_regs)); + break; + case V4L2_COLORFX_SEPIA: + ret = sensor_write_array(sd, sensor_colorfx_sepia_regs, ARRAY_SIZE(sensor_colorfx_sepia_regs)); + break; + case V4L2_COLORFX_NEGATIVE: + ret = sensor_write_array(sd, sensor_colorfx_negative_regs, ARRAY_SIZE(sensor_colorfx_negative_regs)); + break; + case V4L2_COLORFX_EMBOSS: + ret = sensor_write_array(sd, sensor_colorfx_emboss_regs, ARRAY_SIZE(sensor_colorfx_emboss_regs)); + break; + case V4L2_COLORFX_SKETCH: + ret = sensor_write_array(sd, sensor_colorfx_sketch_regs, ARRAY_SIZE(sensor_colorfx_sketch_regs)); + break; + case V4L2_COLORFX_SKY_BLUE: + ret = sensor_write_array(sd, sensor_colorfx_sky_blue_regs, ARRAY_SIZE(sensor_colorfx_sky_blue_regs)); + break; + case V4L2_COLORFX_GRASS_GREEN: + ret = sensor_write_array(sd, sensor_colorfx_grass_green_regs, ARRAY_SIZE(sensor_colorfx_grass_green_regs)); + break; + case V4L2_COLORFX_SKIN_WHITEN: + ret = sensor_write_array(sd, sensor_colorfx_skin_whiten_regs, ARRAY_SIZE(sensor_colorfx_skin_whiten_regs)); + break; + case V4L2_COLORFX_VIVID: + ret = sensor_write_array(sd, sensor_colorfx_vivid_regs, ARRAY_SIZE(sensor_colorfx_vivid_regs)); + break; + default: + return -EINVAL; + } + + if (ret < 0) { + csi_dev_err("sensor_s_colorfx error, return %x!\n",ret); + return ret; + } + + msleep(10); + + info->clrfx = value; + return 0; +} + +static int sensor_g_flash_mode(struct v4l2_subdev *sd, + __s32 *value) +{ + struct sensor_info *info = to_state(sd); + enum v4l2_flash_mode *flash_mode = (enum v4l2_flash_mode*)value; + + *flash_mode = info->flash_mode; + return 0; +} + +static int sensor_s_flash_mode(struct v4l2_subdev *sd, + enum v4l2_flash_mode value) +{ + struct sensor_info *info = to_state(sd); + struct csi_dev *dev=(struct csi_dev *)dev_get_drvdata(sd->v4l2_dev->dev); + char csi_flash_str[32]; + int flash_on,flash_off; + + if(info->ccm_info->iocfg == 0) { + strcpy(csi_flash_str,"csi_flash"); + } else if(info->ccm_info->iocfg == 1) { + strcpy(csi_flash_str,"csi_flash_b"); + } + + flash_on = (dev->flash_pol!=0)?1:0; + flash_off = (flash_on==1)?0:1; + + switch (value) { + case V4L2_FLASH_MODE_OFF: + gpio_write_one_pin_value(dev->csi_pin_hd,flash_off,csi_flash_str); + break; + case V4L2_FLASH_MODE_AUTO: + return -EINVAL; + break; + case V4L2_FLASH_MODE_ON: + gpio_write_one_pin_value(dev->csi_pin_hd,flash_on,csi_flash_str); + break; + case V4L2_FLASH_MODE_TORCH: + return -EINVAL; + break; + case V4L2_FLASH_MODE_RED_EYE: + return -EINVAL; + break; + default: + return -EINVAL; + } + + info->flash_mode = value; + return 0; +} + +static int sensor_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) +{ + switch (ctrl->id) { + case V4L2_CID_BRIGHTNESS: + return sensor_g_brightness(sd, &ctrl->value); + case V4L2_CID_CONTRAST: + return sensor_g_contrast(sd, &ctrl->value); + case V4L2_CID_SATURATION: + return sensor_g_saturation(sd, &ctrl->value); + case V4L2_CID_HUE: + return sensor_g_hue(sd, &ctrl->value); + case V4L2_CID_VFLIP: + return sensor_g_vflip(sd, &ctrl->value); + case V4L2_CID_HFLIP: + return sensor_g_hflip(sd, &ctrl->value); + case V4L2_CID_GAIN: + return sensor_g_gain(sd, &ctrl->value); + case V4L2_CID_AUTOGAIN: + return sensor_g_autogain(sd, &ctrl->value); + case V4L2_CID_EXPOSURE: + return sensor_g_exp(sd, &ctrl->value); + case V4L2_CID_EXPOSURE_AUTO: + return sensor_g_autoexp(sd, &ctrl->value); + case V4L2_CID_DO_WHITE_BALANCE: + return sensor_g_wb(sd, &ctrl->value); + case V4L2_CID_AUTO_WHITE_BALANCE: + return sensor_g_autowb(sd, &ctrl->value); + case V4L2_CID_COLORFX: + return sensor_g_colorfx(sd, &ctrl->value); + case V4L2_CID_CAMERA_FLASH_MODE: + return sensor_g_flash_mode(sd, &ctrl->value); + } + return -EINVAL; +} + +static int sensor_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) +{ + switch (ctrl->id) { + case V4L2_CID_BRIGHTNESS: + return sensor_s_brightness(sd, ctrl->value); + case V4L2_CID_CONTRAST: + return sensor_s_contrast(sd, ctrl->value); + case V4L2_CID_SATURATION: + return sensor_s_saturation(sd, ctrl->value); + case V4L2_CID_HUE: + return sensor_s_hue(sd, ctrl->value); + case V4L2_CID_VFLIP: + return sensor_s_vflip(sd, ctrl->value); + case V4L2_CID_HFLIP: + return sensor_s_hflip(sd, ctrl->value); + case V4L2_CID_GAIN: + return sensor_s_gain(sd, ctrl->value); + case V4L2_CID_AUTOGAIN: + return sensor_s_autogain(sd, ctrl->value); + case V4L2_CID_EXPOSURE: + return sensor_s_exp(sd, ctrl->value); + case V4L2_CID_EXPOSURE_AUTO: + return sensor_s_autoexp(sd, + (enum v4l2_exposure_auto_type) ctrl->value); + case V4L2_CID_DO_WHITE_BALANCE: + return sensor_s_wb(sd, + (enum v4l2_whiteblance) ctrl->value); + case V4L2_CID_AUTO_WHITE_BALANCE: + return sensor_s_autowb(sd, ctrl->value); + case V4L2_CID_COLORFX: + return sensor_s_colorfx(sd, + (enum v4l2_colorfx) ctrl->value); + case V4L2_CID_CAMERA_FLASH_MODE: + return sensor_s_flash_mode(sd, + (enum v4l2_flash_mode) ctrl->value); + } + return -EINVAL; +} + +static int sensor_g_chip_ident(struct v4l2_subdev *sd, + struct v4l2_dbg_chip_ident *chip) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + + return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_SENSOR, 0); +} + + +/* ----------------------------------------------------------------------- */ + +static const struct v4l2_subdev_core_ops sensor_core_ops = { + .g_chip_ident = sensor_g_chip_ident, + .g_ctrl = sensor_g_ctrl, + .s_ctrl = sensor_s_ctrl, + .queryctrl = sensor_queryctrl, + .reset = sensor_reset, + .init = sensor_init, + .s_power = sensor_power, + .ioctl = sensor_ioctl, +}; + +static const struct v4l2_subdev_video_ops sensor_video_ops = { + .enum_mbus_fmt = sensor_enum_fmt,//linux-3.0 + .try_mbus_fmt = sensor_try_fmt,//linux-3.0 + .s_mbus_fmt = sensor_s_fmt,//linux-3.0 + .s_parm = sensor_s_parm,//linux-3.0 + .g_parm = sensor_g_parm,//linux-3.0 +}; + +static const struct v4l2_subdev_ops sensor_ops = { + .core = &sensor_core_ops, + .video = &sensor_video_ops, +}; + +/* ----------------------------------------------------------------------- */ + +static int sensor_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct v4l2_subdev *sd; + struct sensor_info *info; +// int ret; + info = kzalloc(sizeof(struct sensor_info), GFP_KERNEL); + if (info == NULL) + return -ENOMEM; + sd = &info->sd; + v4l2_i2c_subdev_init(sd, client, &sensor_ops); + + info->fmt = &sensor_formats[0]; + info->ccm_info = &ccm_info_con; + + info->brightness = 0; + info->contrast = 0; + info->saturation = 0; + info->hue = 0; + info->hflip = 0; + info->vflip = 0; + info->gain = 0; + info->autogain = 1; + info->exp = 0; + info->autoexp = 0; + info->autowb = 1; + info->wb = 0; + info->clrfx = 0; + +// info->clkrc = 1; /* 30fps */ + + magic_ver = sw_get_ic_ver(); + switch(magic_ver) { + case SUNXI_VER_A10A: + case SUNXI_VER_A10B: + info->ccm_info->mclk = MCLK_VER_B; + break; + case SUNXI_VER_A10C: + info->ccm_info->mclk = MCLK_VER_C; + break; + default: + info->ccm_info->mclk = MCLK_VER_C; + break; + } + return 0; +} + + +static int sensor_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + + v4l2_device_unregister_subdev(sd); + kfree(to_state(sd)); + return 0; +} + +static const struct i2c_device_id sensor_id[] = { + { "gc0308", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, sensor_id); + +//linux-3.0 +static struct i2c_driver sensor_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "gc0308", + }, + .probe = sensor_probe, + .remove = sensor_remove, + .id_table = sensor_id, +}; + +static __init int init_sensor(void) +{ + return i2c_add_driver(&sensor_driver); +} + +static __exit void exit_sensor(void) +{ + i2c_del_driver(&sensor_driver); +} + +module_init(init_sensor); +module_exit(exit_sensor); diff --git a/patch/linux-sunxi/drivers/media/video/sun4i_csi/device/gc2035.c b/patch/linux-sunxi/drivers/media/video/sun4i_csi/device/gc2035.c new file mode 100755 index 0000000..78d4ff1 --- /dev/null +++ b/patch/linux-sunxi/drivers/media/video/sun4i_csi/device/gc2035.c @@ -0,0 +1,3132 @@ +/* + * A V4L2 driver for GalaxyCore gc2035 cameras. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include //linux-3.0 +#include +#include +#include +#include +#include +//#include "../../../../power/axp_power/axp-gpio.h" +#include "../include/sun4i_csi_core.h" +#include "../include/sun4i_dev_csi.h" + +MODULE_AUTHOR("raymonxiu"); +MODULE_DESCRIPTION("A low-level driver for GalaxyCore gc2035 sensors"); +MODULE_LICENSE("GPL"); + +//for internel driver debug +#define DEV_DBG_EN 0 +#if(DEV_DBG_EN == 1) +#define csi_dev_dbg(x,arg...) printk("[CSI_DEBUG][GC2035]"x,##arg) +#else +#define csi_dev_dbg(x,arg...) +#endif + +#define csi_dev_err(x,arg...) printk("[CSI_ERR][GC2035]"x,##arg) +#define csi_dev_print(x,arg...) printk("[CSI][GC2035]"x,##arg) + +#define MCLK (24*1000*1000) +#define VREF_POL CSI_HIGH +#define HREF_POL CSI_HIGH +#define CLK_POL CSI_RISING +#define IO_CFG 0 //0:csi back 1:csi front +#define V4L2_IDENT_SENSOR 0x2035 + +//define the voltage level of control signal +#define CSI_STBY_ON 1 +#define CSI_STBY_OFF 0 +#define CSI_RST_ON 0 +#define CSI_RST_OFF 1 +#define CSI_PWR_ON 1 +#define CSI_PWR_OFF 0 + +#define REG_TERM 0xff +#define VAL_TERM 0xff + + +#define REG_ADDR_STEP 1 +#define REG_DATA_STEP 1 +#define REG_STEP (REG_ADDR_STEP+REG_DATA_STEP) + +/* + * Basic window sizes. These probably belong somewhere more globally + * useful. + */ +#define UXGA_WIDTH 1600 +#define UXGA_HEIGHT 1200 + +#define SXGA_WIDTH 1280 +#define SXGA_HEIGHT 1024 + + +#define HD720_WIDTH 1280 +#define HD720_HEIGHT 720 + +#define XGA_WIDTH 1024 +#define XGA_HEIGHT 768 + +#define SVGA_WIDTH 800 +#define SVGA_HEIGHT 600 + +#define VGA_WIDTH 640 +#define VGA_HEIGHT 480 + +#define QVGA_WIDTH 320 +#define QVGA_HEIGHT 240 + +#define CIF_WIDTH 352 +#define CIF_HEIGHT 288 + +#define QCIF_WIDTH 176 +#define QCIF_HEIGHT 144 + +/* + * Our nominal (default) frame rate. + */ +#define SENSOR_FRAME_RATE 8 + + + +/* + * The gc2035 sits on i2c with ID 0x78 + */ +#define I2C_ADDR 0x78 +#define GC2035_SENSOR_ID 0x2035 +/* Registers */ + +/* + * Information we maintain about a known sensor. + */ +struct sensor_format_struct; /* coming later */ +struct snesor_colorfx_struct; /* coming later */ +__csi_subdev_info_t ccm_info_con = +{ + .mclk = MCLK, + .vref = VREF_POL, + .href = HREF_POL, + .clock = CLK_POL, + .iocfg = IO_CFG, +}; + +struct sensor_info { + struct v4l2_subdev sd; + struct sensor_format_struct *fmt; /* Current format */ + __csi_subdev_info_t *ccm_info; + int width; + int height; + int brightness; + int contrast; + int saturation; + int hue; + int hflip; + int vflip; + int gain; + int autogain; + int exp; + enum v4l2_exposure_auto_type autoexp; + int autowb; + enum v4l2_whiteblance wb; + enum v4l2_colorfx clrfx; + enum v4l2_flash_mode flash_mode; + u8 clkrc; /* Clock divider value */ +}; + +static inline struct sensor_info *to_state(struct v4l2_subdev *sd) +{ + return container_of(sd, struct sensor_info, sd); +} + + + +/* + * The default register settings + * + */ + +struct regval_list { + unsigned char reg_num[REG_ADDR_STEP]; + unsigned char value[REG_DATA_STEP]; +}; + + + +static struct regval_list sensor_default_regs[] = { +{{0xfe},{0x80}}, +{{0xfe},{0x80}}, +{{0xfe},{0x80}}, +{{0xfc},{0x06}}, +{{0xf9},{0xfe}}, //[0] pll enable +{{0xfa},{0x00}}, +{{0xf6},{0x00}}, +{{0xf7},{0x17}}, //pll enable +{{0xf8},{0x00}}, +{{0xfe},{0x00}}, +{{0x82},{0x00}}, +{{0xb3},{0x60}}, +{{0xb4},{0x40}}, +{{0xb5},{0x60}}, +{{0x03},{0x05}}, +{{0x04},{0x2e}}, + +//measure window +{{0xfe},{0x00}}, +{{0xec},{0x04}}, +{{0xed},{0x04}}, +{{0xee},{0x60}}, +{{0xef},{0x90}}, + + + +{{0x0a},{0x00}}, //row start +{{0x0c},{0x02}}, //col start + +{{0x0d},{0x04}}, +{{0x0e},{0xc0}}, +{{0x0f},{0x06}}, //Window setting +{{0x10},{0x58}},// + +{{0x17},{0x14}}, //[0]mirror [1]flip +{{0x18},{0x0a}}, //sdark 4 row in even frame?? +{{0x19},{0x0a}}, //AD pipe number + +{{0x1a},{0x01}}, //CISCTL mode4 +{{0x1b},{0x48}}, +{{0x1e},{0x88}}, //analog mode1 [7] tx-high en +{{0x1f},{0x0f}}, //analog mode2 + +{{0x20},{0x05}}, //[0]adclk mode [1]rowclk_MODE [2]rsthigh_en +{{0x21},{0x0f}}, //[3]txlow_en +{{0x22},{0xf0}}, //[3:0]vref +{{0x23},{0xc3}}, //f3//ADC_r +{{0x24},{0x16}}, //pad drive + +//==============================aec +//AEC +{{0xfe},{0x01}}, +{{0x09},{0x00}}, + +{{0x11},{0x10}}, +{{0x47},{0x30}}, +{{0x0b},{0x90}}, +{{0x13},{0x78}}, //0x75 0x80 +{{0x1f},{0xc0}},//addd +{{0x20},{0x50}},//add 0x60 +{{0xfe},{0x00}}, +{{0xf7},{0x17}}, //pll enable +{{0xf8},{0x00}}, +{{0x05},{0x01}}, +{{0x06},{0x18}}, +{{0x07},{0x00}}, +{{0x08},{0x48}}, +{{0xfe},{0x01}}, +{{0x27},{0x00}}, +{{0x28},{0x6a}}, +{{0x29},{0x03}}, +{{0x2a},{0x50}},//8fps +{{0x2b},{0x04}}, +{{0x2c},{0xf8}}, +{{0x2d},{0x06}}, +{{0x2e},{0xa0}},//6fps +{{0x3e},{0x40}},//0x40 +{{0xfe},{0x00}}, +{{0xb6},{0x03}}, //AEC enable +{{0xfe},{0x00}}, + +///////BLK + +{{0x3f},{0x00}}, //prc close??? +{{0x40},{0xa7}}, // a7 77 +{{0x42},{0x7f}}, +{{0x43},{0x30}},//0x30 + +{{0x5c},{0x08}}, +//{{0x6c 3a //manual_offset },{real B channel +//{{0x6d 3a//manual_offset },{real B channel +//{{0x6e 36//manual_offset },{real R channel +//{{0x6f 36//manual_offset },{real R channel +{{0x5e},{0x20}},//0x20 +{{0x5f},{0x20}},//0x20 +{{0x60},{0x20}}, +{{0x61},{0x20}}, +{{0x62},{0x20}}, +{{0x63},{0x20}}, +{{0x64},{0x20}}, +{{0x65},{0x20}}, +{{0x66},{0x20}}, +{{0x67},{0x20}}, +{{0x68},{0x20}}, +{{0x69},{0x20}}, + +/////crop// +{{0x90},{0x01}}, //crop enable +{{0x95},{0x04}}, //1600x1200 +{{0x96},{0xb0}}, +{{0x97},{0x06}}, +{{0x98},{0x40}}, + +{{0xfe},{0x03}}, +{{0x42},{0x80}}, +{{0x43},{0x06}}, //output buf width //buf widthһûҪ +{{0x41},{0x00}}, // delay +{{0x40},{0x00}}, //fifo half full trig +{{0x17},{0x01}}, //wid mipiֵķƵΪʲôv +{{0xfe},{0x00}}, + +{{0x80},{0xff}},//block enable 0xff +{{0x81},{0x26}},//38 //skin_Y 8c_debug + +{{0x03},{0x05}}, +{{0x04},{0x2e}}, +{{0x84},{0x02}}, //output put foramat +{{0x86},{0x03}}, //sync plority +{{0x87},{0x80}}, //middle gamma on +{{0x8b},{0xbc}},//debug modeҪһ +{{0xa7},{0x80}},//B_channel_gain +{{0xa8},{0x80}},//B_channel_gain +{{0xb0},{0x80}}, //globle gain +{{0xc0},{0x40}}, + +#if 1 +////ba-wang/// +{{0xfe},{0x01}}, +{{0xc2},{0x10}},//0x1f +{{0xc3},{0x07}},//0x07 +{{0xc4},{0x03}},//0x03 +{{0xc8},{0x10}},//10 +{{0xc9},{0x0a}},//0x0a +{{0xca},{0x08}},//0x08 +{{0xbc},{0x3a}},// 3c +{{0xbd},{0x1c}},//0x1c +{{0xbe},{0x1a}},//0x1a +{{0xb6},{0x22}},// 0x30 +{{0xb7},{0x1c}},//0x1c +{{0xb8},{0x15}},//0x15 +{{0xc5},{0x00}}, +{{0xc6},{0x00}}, +{{0xc7},{0x00}}, +{{0xcb},{0x00}}, +{{0xcc},{0x00}}, +{{0xcd},{0x00}}, +{{0xbf},{0x0c}},//0x0c +{{0xc0},{0x04}},//0x04 +{{0xc1},{0x00}}, +{{0xb9},{0x00}}, +{{0xba},{0x00}}, +{{0xbb},{0x00}}, +{{0xaa},{0x00}}, +{{0xab},{0x00}}, +{{0xac},{0x00}}, +{{0xad},{0x00}}, +{{0xae},{0x00}}, +{{0xaf},{0x00}}, +{{0xb0},{0x00}}, +{{0xb1},{0x00}}, +{{0xb2},{0x00}}, +{{0xb3},{0x00}}, +{{0xb4},{0x00}}, +{{0xb5},{0x00}}, +{{0xd0},{0x01}}, +{{0xd2},{0x00}}, +{{0xd3},{0x00}}, +{{0xd8},{0x00}}, +{{0xda},{0x00}}, +{{0xdb},{0x00}}, +{{0xdc},{0x00}}, +{{0xde},{0x07}},//0x07 +{{0xdf},{0x00}}, +{{0xd4},{0x00}}, +{{0xd6},{0x00}}, +{{0xd7},{0x00}}, +{{0xa4},{0x00}}, +{{0xa5},{0x00}}, +{{0xa6},{0x04}}, +{{0xa7},{0x00}}, +{{0xa8},{0x00}}, +{{0xa9},{0x00}}, +{{0xa1},{0x80}}, +{{0xa2},{0x80}}, + + + +{{0xfe},{0x02}}, +{{0xa4},{0x00}}, +{{0xfe},{0x00}}, +//cc + +{{0xfe},{0x02}}, +{{0xc0},{0x01}}, +{{0xc1},{0x40}}, +{{0xc2},{0xfc}}, +{{0xc3},{0x05}}, +{{0xc4},{0xec}}, +{{0xc5},{0x42}}, +{{0xc6},{0xf8}}, +{{0xc7},{0x40}}, +{{0xc8},{0xf8}}, +{{0xc9},{0x06}}, +{{0xca},{0xfd}}, +{{0xcb},{0x3e}}, +{{0xcc},{0xf3}}, +{{0xcd},{0x36}}, +{{0xce},{0xf6}}, +{{0xcf},{0x04}}, +{{0xe3},{0x0c}}, +{{0xe4},{0x44}}, +{{0xe5},{0xe5}}, +{{0xfe},{0x00}}, + + +{{0xfe},{0x00}}, +//awb +{{0xfe},{0x01}}, +{{0x4f},{0x00}}, +{{0x4d},{0x10}}, ////////////////10 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4d},{0x20}}, ///////////////20 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4d},{0x30}}, //////////////////30 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x04}}, // office +{{0x4e},{0x00}}, +{{0x4e},{0x02}}, // d65 +{{0x4e},{0x04}},//d50 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4d},{0x40}}, //////////////////////40 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, // cwf +{{0x4e},{0x08}}, // cwf +{{0x4e},{0x04}}, // d50 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4d},{0x50}}, //////////////////50 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x10}}, // tl84 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4d},{0x60}}, /////////////////60 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4d},{0x70}}, ///////////////////70 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x20}}, // a +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4d},{0x80}}, /////////////////////80 +{{0x4e},{0x00}}, +{{0x4e},{0x40}}, // h +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4d},{0x90}}, //////////////////////90 +{{0x4e},{0x00}}, // h +{{0x4e},{0x40}}, // h +{{0x4e},{0x40}}, // h +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4d},{0xa0}}, /////////////////a0 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4d},{0xb0}}, //////////////////////////////////b0 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4d},{0xc0}}, //////////////////////////////////c0 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4d},{0xd0}}, ////////////////////////////d0 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4d},{0xe0}}, /////////////////////////////////e0 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4d},{0xf0}}, /////////////////////////////////f0 +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4e},{0x00}}, +{{0x4f},{0x01}}, +#endif +{{0xfe},{0x01}}, +{{0x50},{0xc8}}, +{{0x52},{0x40}}, +{{0x54},{0x60}}, +{{0x56},{0x06}}, +{{0x57},{0x20}}, //pre adjust +{{0x58},{0x01}}, +{{0x5c},{0xf0}}, +{{0x5d},{0x40}}, +{{0x5b},{0x02}}, //AWB_gain_delta +{{0x61},{0xaa}},//R/G stand +{{0x62},{0xaa}},//R/G stand +{{0x71},{0x00}}, +{{0x74},{0x10}}, //AWB_C_max +{{0x77},{0x08}}, //AWB_p2_x +{{0x78},{0xfd}}, //AWB_p2_y +{{0x86},{0x30}}, +{{0x87},{0x00}}, +{{0x88},{0x06}},//04 +{{0x8a},{0xc0}},//awb move mode +{{0x89},{0x75}}, +{{0x84},{0x08}}, //auto_window +{{0x8b},{0x00}}, //awb compare luma +{{0x8d},{0x70}}, //awb gain limit R +{{0x8e},{0x70}},//G +{{0x8f},{0xf4}},//B +{{0x5e},{0xa4}}, +{{0x5f},{0x60}}, +{{0x92},{0x58}}, +{{0xfe},{0x00}}, +{{0x82},{0x02}},//awb_en + +//{{0xfe },{0xec}}, luma_value + +{{0xfe},{0x01}}, + +{{0x1e},{0xf1}}, +{{0x9c},{0x00}}, //add abs slope 0x02 +{{0x21},{0xbf}}, +{{0xfe},{0x02}}, +{{0xa5},{0x60}}, //lsc_th //40 +{{0xa2},{0xc0}}, //lsc_dec_slope 0xa0 +{{0xa3},{0x30}}, //when total gain is bigger than the value},{ enter dark light mode 0x20 added +{{0xa4},{0x00}},//add +{{0xa6},{0x50}}, //dd_th +{{0xa7},{0x80}}, //ot_th 30 +{{0xab},{0x31}}, //[0]b_dn_effect_dark_inc_or_dec +{{0x88},{0x15}}, //[5:0]b_base +{{0xa9},{0x6c}}, //[7:4] ASDE_DN_b_slope_high 0x6c 0x6f + +{{0xb0},{0x66}}, //6edge effect slope 0x66 0x88 0x99 + +{{0xb3},{0x70}}, //saturation dec slope //0x70 0x40 +{{0xb4},{0x32}},//0x32 0x42 +{{0x8c},{0xf6}}, //[2]b_in_dark_inc +{{0x89},{0x03}}, //dn_c_weight 0x03 + +{{0xde},{0xbc}}, //b6[7]asde_autogray [3:0]auto_gray_value 0xb9 0xb8 +{{0x38},{0x06}}, //0aasde_autogray_slope 0x08 0x05 0x06 0x0a +{{0x39},{0x50}}, //50asde_autogray_threshold 0x50 0x30 + +{{0xfe},{0x00}}, +{{0x81},{0x24}}, //0x26 +{{0x87},{0x90}}, //[5:4]first_dn_en first_dd_en enable 0x80 0xb0 +{{0xfe},{0x02}}, +{{0x83},{0x00}},//[6]green_bks_auto [5]gobal_green_bks +{{0x84},{0x45}},//RB offset +{{0xd1},{0x3a}}, //saturation_cb 0x3a +{{0xd2},{0x3a}}, //saturation_Cr 0x38 +{{0xdc},{0x30}}, +{{0xdd},{0xb8}}, //edge_sa_g},{b +{{0xfe},{0x00}}, + + +//gamma high_3_low +{{0xfe},{0x02}}, +{{0x15},{0x05}}, +{{0x16},{0x0b}}, +{{0x17},{0x10}}, +{{0x18},{0x16}}, +{{0x19},{0x24}}, +{{0x1a},{0x32}}, +{{0x1b},{0x42}}, +{{0x1c},{0x4e}}, +{{0x1d},{0x64}}, +{{0x1e},{0x76}}, +{{0x1f},{0x86}}, +{{0x20},{0x94}}, +{{0x21},{0x9f}}, +{{0x22},{0xb4}}, +{{0x23},{0xc3}}, +{{0x24},{0xce}}, +{{0x25},{0xd7}}, +{{0x26},{0xe3}}, +{{0x27},{0xec}}, +{{0x28},{0xf7}}, +{{0x29},{0xff}}, + + + +//y-gamma +{{0x2b},{0x00}}, +{{0x2c},{0x04}}, +{{0x2d},{0x09}}, +{{0x2e},{0x18}}, +{{0x2f},{0x27}}, +{{0x30},{0x37}}, +{{0x31},{0x49}}, +{{0x32},{0x5c}}, +{{0x33},{0x7e}}, +{{0x34},{0xa0}}, +{{0x35},{0xc0}}, +{{0x36},{0xe0}}, +{{0x37},{0xff}}, +{{0xfe},{0x00}}, + +{{0xfe},{0x00}}, + +{{0x82},{0xfe}}, +//sleep 400 +{{0xf2},{0x70}}, +{{0xf3},{0xff}}, +{{0xf4},{0x00}}, +{{0xf5},{0x30}}, +{{0xfe},{0x01}}, +{{0x0b},{0x90}}, +{{0x87},{0x00}},//0x10 +{{0xfe},{0x00}}, + +/////},{0xup}},date +//?0x }},// + + + +{{0xfe},{0x02}}, +{{0xa6},{0x80}}, //dd_th +{{0xa7},{0x60}}, //ot_th //0x80 +{{0xa9},{0x66}}, //6f[7:4] ASDE_DN_b_slope_high 0x68 +{{0xb0},{0x88}}, //edge effect slope 0x99 +{{0x38},{0x08}}, //asde_autogray_slope 0x08 0x0f 0x0a 0b +{{0x39},{0x50}}, //asde_autogray_threshold 0x60 +{{0xfe},{0x00}}, +{{0x87},{0x90}}, //[5:4]first_dn_en first_dd_en 0x90 + +{{0xfe},{0x00}}, +{{0x90},{0x01}}, +{{0x95},{0x01}}, +{{0x96},{0xe0}}, +{{0x97},{0x02}}, +{{0x98},{0x80}}, +{{0xc8},{0x14}}, +{{0xf7},{0x0D}}, +{{0xf8},{0x83}}, +{{0xfa},{0x00}},//pll=4 + +{{0x05},{0x00}}, +{{0x06},{0xc4}}, +{{0x07},{0x00}}, +{{0x08},{0xae}}, +{{0xfe},{0x01}}, +{{0x27},{0x00}}, +{{0x28},{0xe5}}, +{{0x29},{0x05}}, +{{0x2a},{0x5e}},//18fps +{{0x2b},{0x07}}, +{{0x2c},{0x28}},//12.5fps +{{0x2d},{0x0a}}, +{{0x2e},{0xbc}},//8fps +{{0x3e},{0x40}},//0x40 0x00 + + + +{{0xfe},{0x03}}, +{{0x42},{0x04}}, +{{0x43},{0x05}}, //output buf width +{{0x41},{0x02}}, // delay +{{0x40},{0x40}}, //fifo half full trig +{{0x17},{0x00}}, //widv is 0 +{{0xfe},{0x00}}, +{{0xc8},{0x55}}, + +{{0xff},{0xff}}, +}; + +/* 1600X1200 UXGA capture */ +static struct regval_list sensor_uxga_regs[] ={ + + + {{0xfe},{0x00}}, + {{0x0a},{0x00}}, //row start + {{0x0c},{0x02}}, //col start + + {{0x0d},{0x04}}, + {{0x0e},{0xc0}}, + {{0x0f},{0x06}}, //Window setting + {{0x10},{0x58}},// + + + {{0x90},{0x01}}, //crop enable + {{0x95},{0x04}}, + {{0x96},{0xb0}}, + {{0x97},{0x06}}, + {{0x98},{0x40}}, + {{0x99},{0x11}}, + {{0xc8},{0x00}}, + + + + {{0xfa},{0x11}}, + + + {{0xfe},{0x03}}, + {{0x42},{0x80}}, + {{0x43},{0x06}}, //output buf width + {{0x41},{0x00}}, // delay + {{0x40},{0x00}}, //fifo half full trig + {{0x17},{0x01}}, //widv + {{0xfe},{0x00}}, + {{0xc8},{0x00}}, + +}; + +/* 1280X1024 SXGA */ +static struct regval_list sensor_sxga_regs[] = +{}; +/*1024*768*/ +static struct regval_list sensor_xga_regs[] = +{}; +/* 800X600 SVGA,30fps*/ +static struct regval_list sensor_svga_regs[] ={ + {{0xff},{0xff}}, +}; + + + +//1280*720---init---/// +static struct regval_list Gc2015_sensor_hd720_regs[] = { + + + {{0xfe },{0x00}}, + {{0x05},{0x01}}, +{{0x06},{0x9e}}, +{{0x07},{0x01}}, +{{0x08},{0x6d}}, + {{0x0a },{0xf0}}, //row start + {{0x0c },{0xa0}}, //col start + {{0x0d },{0x02}}, + {{0x0e },{0xd8}}, + {{0x0f },{0x05}}, //Window setting + {{0x10 },{0x18}}, + +{{0xfe},{0x01}}, +{{0x27},{0x00}}, +{{0x28},{0xd9}}, +{{0x29},{0x04}}, +{{0x2a},{0x3d}},//18fps +{{0x2b},{0x06}}, +{{0x2c},{0xc8}},//12.5fps +{{0x2d},{0x0a}}, +{{0x2e},{0x2c}},//8fps +{{0x3e},{0x40}},//0x40 0x00 + + //measure window +{{0xfe},{0x00}}, +{{0xec},{0x04}}, +{{0xed},{0x04}}, +{{0xee},{0x50}}, +{{0xef},{0x58}}, + + + + + {{0x90 },{0x01}}, //crop enable + {{0x95 },{0x02}}, + {{0x96 },{0xd0}}, + {{0x97 },{0x05}}, + {{0x98 },{0x00}}, + + + {{0xfe },{0x03}}, + {{0x42 },{0x80}}, + {{0x43 },{0x06}}, //output buf width + {{0x41 },{0x00}}, // delay + {{0x40 },{0x00}}, //fifo half full trig + {{0x17 },{0x01}}, //widv + {{0xfe },{0x00}}, + + + {{0x99},{0x11}}, + {{0xc8},{0x00}}, + + {{0xfa},{0x11}}, + + + + + + {{0xff},{0xff}}, + + + +}; + + +/* 640X480 VGA */ +static struct regval_list sensor_vga_regs[] = +{ + {{0xfe},{0x00}}, + + {{0x0a},{0x00}}, //row start + {{0x0c},{0x02}}, //col start + + {{0x0d},{0x04}}, + {{0x0e},{0xc0}}, + {{0x0f},{0x06}}, //Window setting + {{0x10},{0x58}},// + + + +{{0x05},{0x00}}, +{{0x06},{0xc4}}, +{{0x07},{0x00}}, +{{0x08},{0xae}}, +{{0xfe},{0x01}}, +{{0x27},{0x00}}, +{{0x28},{0xe5}}, +{{0x29},{0x05}}, +{{0x2a},{0x5e}},//18fps +{{0x2b},{0x07}}, +{{0x2c},{0x28}},//12.5fps +{{0x2d},{0x0a}}, +{{0x2e},{0xbc}},//8fps +{{0x3e},{0x40}},//0x40 0x00 + +{{0xfe},{0x00}}, +{{0xec},{0x04}}, +{{0xed},{0x04}}, +{{0xee},{0x60}}, +{{0xef},{0x90}}, + + + {{0x90},{0x01}}, + {{0x95},{0x01}}, + {{0x96},{0xe0}}, + {{0x97},{0x02}}, + {{0x98},{0x80}}, + {{0xc8},{0x15}}, + + + + {{0xfa},{0x00}}, + + + {{0xfe},{0x03}}, + {{0x42},{0x04}}, + {{0x43},{0x05}}, //output buf width + {{0x41},{0x02}}, // delay + {{0x40},{0x40}}, //fifo half full trig + {{0x17},{0x00}}, //widv is 0 + + {{0xfe},{0x00}}, + {{0xc8},{0x55}}, + {{0xb6},{0x03}},//aec on + {{0xff},{0xff}}, + +}; + +/* + * The white balance settings + * Here only tune the R G B channel gain. + * The white balance enalbe bit is modified in sensor_s_autowb and sensor_s_wb + */ +static struct regval_list sensor_wb_auto_regs[] = { + + {{0xb3},{0x61}}, + {{0xb4},{0x40}}, + {{0xb5},{0x61}}, + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_wb_cloud_regs[] = { + {{0xb3},{0x58}}, + {{0xb4},{0x40}}, + {{0xb5},{0x50}}, + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_wb_daylight_regs[] = { + //tai yang guang + //Sunny + {{0xb3},{0x58}}, + {{0xb4},{0x40}}, + {{0xb5},{0x50}}, + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_wb_incandescence_regs[] = { + //bai re guang + {{0xb3},{0x50}}, + {{0xb4},{0x40}}, + {{0xb5},{0xa8}}, + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_wb_fluorescent_regs[] = { + //ri guang deng + {{0xb3},{0x72}}, + {{0xb4},{0x40}}, + {{0xb5},{0x5b}}, + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_wb_tungsten_regs[] = { + //wu si deng + {{0xb3},{0xa0}}, + {{0xb4},{0x45}}, + {{0xb5},{0x40}}, + {{0xff},{0xff}}, +}; + +/* + * The color effect settings + */ + +static struct regval_list sensor_colorfx_none_regs[] = { + {{0xfe},{0x00}}, + {{0x83},{0xe0}}, + {{0xff},{0xff}}, + +}; + +static struct regval_list sensor_colorfx_bw_regs[] = { + +}; + +static struct regval_list sensor_colorfx_sepia_regs[] = { + {{0xfe},{0x00}}, + {{0x83},{0x82}}, + {{0xff},{0xff}}, + +}; + +static struct regval_list sensor_colorfx_negative_regs[] = { + {{0xfe},{0x00}}, + {{0x83},{0x01}}, + {{0xff},{0xff}}, + +}; + +static struct regval_list sensor_colorfx_emboss_regs[] = { + {{0xfe},{0x00}}, + {{0x83},{0x12}},///CAM_EFFECT_ENC_GRAYSCALE + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_colorfx_sketch_regs[] = { +//NULL +}; + +static struct regval_list sensor_colorfx_sky_blue_regs[] = { + {{0xfe},{0x00}}, + {{0x83},{0x62}}, + {{0xff},{0xff}}, + +}; + +static struct regval_list sensor_colorfx_grass_green_regs[] = { + {{0xfe},{0x00}}, + {{0x83},{0x52}}, + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_colorfx_skin_whiten_regs[] = { +//NULL +}; + +static struct regval_list sensor_colorfx_vivid_regs[] = { +//NULL +}; + +/* + * The brightness setttings + */ +static struct regval_list sensor_brightness_neg4_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_neg3_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_neg2_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_neg1_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_zero_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_pos1_regs[] = { + //NULL +}; + +static struct regval_list sensor_brightness_pos2_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_pos3_regs[] = { +//NULL +}; + +static struct regval_list sensor_brightness_pos4_regs[] = { +//NULL +}; + +/* + * The contrast setttings + */ +static struct regval_list sensor_contrast_neg4_regs[] = { + +}; + +static struct regval_list sensor_contrast_neg3_regs[] = { + +}; + +static struct regval_list sensor_contrast_neg2_regs[] = { + +}; + +static struct regval_list sensor_contrast_neg1_regs[] = { + +}; + +static struct regval_list sensor_contrast_zero_regs[] = { + +}; + +static struct regval_list sensor_contrast_pos1_regs[] = { + +}; + +static struct regval_list sensor_contrast_pos2_regs[] = { + +}; + +static struct regval_list sensor_contrast_pos3_regs[] = { + +}; + +static struct regval_list sensor_contrast_pos4_regs[] = { + +}; + +/* + * The saturation setttings + */ +static struct regval_list sensor_saturation_neg4_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_neg3_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_neg2_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_neg1_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_zero_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_pos1_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_pos2_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_pos3_regs[] = { +//NULL +}; + +static struct regval_list sensor_saturation_pos4_regs[] = { +//NULL +}; + +/* + * The exposure target setttings + */ +static struct regval_list sensor_ev_neg4_regs[] = { + {{0xfe},{0x01}}, + {{0x13},{0x40}}, + {{0xfe},{0x02}}, + {{0xd5},{0xc0}}, + {{0xfe},{0x00}}, + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_ev_neg3_regs[] = { + {{0xfe},{0x01}}, + {{0x13},{0x50}}, + {{0xfe},{0x02}}, + {{0xd5},{0xd0}}, + {{0xfe},{0x00}}, + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_ev_neg2_regs[] = { + {{0xfe},{0x01}}, + {{0x13},{0x60}}, + {{0xfe},{0x02}}, + {{0xd5},{0xe0}}, + {{0xfe},{0x00}}, + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_ev_neg1_regs[] = { + {{0xfe},{0x01}}, + {{0x13},{0x68}}, + {{0xfe},{0x02}}, + {{0xd5},{0xf0}}, + {{0xfe},{0x00}}, + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_ev_zero_regs[] = { + {{0xfe},{0x01}}, + {{0x13},{0x78}}, + {{0xfe},{0x02}}, + {{0xd5},{0x00}}, + {{0xfe},{0x00}}, + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_ev_pos1_regs[] = { + {{0xfe},{0x01}}, + {{0x13},{0x80}}, + {{0xfe},{0x02}}, + {{0xd5},{0x10}}, + {{0xfe},{0x00}}, + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_ev_pos2_regs[] = { + {{0xfe},{0x01}}, + {{0x13},{0x90}}, + {{0xfe},{0x02}}, + {{0xd5},{0x20}}, + {{0xfe},{0x00}}, + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_ev_pos3_regs[] = { + {{0xfe},{0x01}}, + {{0x13},{0xa0}}, + {{0xfe},{0x02}}, + {{0xd5},{0x30}}, + {{0xfe},{0x00}}, + {{0xff},{0xff}}, +}; + +static struct regval_list sensor_ev_pos4_regs[] = { + {{0xfe},{0x01}}, + {{0x13},{0xb0}}, + {{0xfe},{0x02}}, + {{0xd5},{0x50}}, + {{0xfe},{0x00}}, + {{0xff},{0xff}}, +}; + + +/* + * Here we'll try to encapsulate the changes for just the output + * video format. + * + */ + +static struct regval_list sensor_fmt_yuv422_yuyv[] = { + +}; + + +static struct regval_list sensor_fmt_yuv422_yvyu[] = { + +}; + +static struct regval_list sensor_fmt_yuv422_vyuy[] = { + +}; + +static struct regval_list sensor_fmt_yuv422_uyvy[] = { + +}; + +static struct regval_list sensor_fmt_raw[] = { + +}; + + + +/* + * Low-level register I/O. + * + */ + + +/* + * On most platforms, we'd rather do straight i2c I/O. + */ +static int sensor_read(struct v4l2_subdev *sd, unsigned char *reg, + unsigned char *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 data[REG_STEP]; + struct i2c_msg msg; + int ret,i; + + for(i = 0; i < REG_ADDR_STEP; i++) + data[i] = reg[i]; + + data[REG_ADDR_STEP] = 0xff; + /* + * Send out the register address... + */ + msg.addr = client->addr; + msg.flags = 0; + msg.len = REG_ADDR_STEP; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret < 0) { + csi_dev_err("Error %d on register write\n", ret); + return ret; + } + /* + * ...then read back the result. + */ + + msg.flags = I2C_M_RD; + msg.len = REG_DATA_STEP; + msg.buf = &data[REG_ADDR_STEP]; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret >= 0) { + for(i = 0; i < REG_DATA_STEP; i++) + value[i] = data[i+REG_ADDR_STEP]; + ret = 0; + } + else { + csi_dev_err("Error %d on register read\n", ret); + } + return ret; +} + + +static int sensor_write(struct v4l2_subdev *sd, unsigned char *reg, + unsigned char *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct i2c_msg msg; + unsigned char data[REG_STEP]; + int ret,i; + + for(i = 0; i < REG_ADDR_STEP; i++) + data[i] = reg[i]; + for(i = REG_ADDR_STEP; i < REG_STEP; i++) + data[i] = value[i-REG_ADDR_STEP]; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = REG_STEP; + msg.buf = data; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret > 0) { + ret = 0; + } + else if (ret < 0) { + csi_dev_err("sensor_write error!\n"); + } + return ret; +} + + + +/* + * Write a list of register settings; + */ +static int sensor_write_array(struct v4l2_subdev *sd, struct regval_list *vals , uint size) +{ + int i,ret; + if (size == 0) + return -EINVAL; + + for(i = 0; i < size ; i++) + { + if(vals->reg_num[0] == 0xff) { + mdelay(vals->value[0]); + } else { + ret = sensor_write(sd, vals->reg_num, vals->value); + if (ret < 0) + { + csi_dev_err("sensor_write_err!\n"); + return ret; + } + } + + vals++; + } + + return 0; +} + + +/* + * Stuff that knows about the sensor. + */ + +static int sensor_power(struct v4l2_subdev *sd, int on) +{ + struct csi_dev *dev=(struct csi_dev *)dev_get_drvdata(sd->v4l2_dev->dev); + struct sensor_info *info = to_state(sd); + char csi_stby_str[32],csi_power_str[32],csi_reset_str[32]; + + if(info->ccm_info->iocfg == 0) { + strcpy(csi_stby_str,"csi_stby"); + strcpy(csi_power_str,"csi_power_en"); + strcpy(csi_reset_str,"csi_reset"); + } else if(info->ccm_info->iocfg == 1) { + strcpy(csi_stby_str,"csi_stby_b"); + strcpy(csi_power_str,"csi_power_en_b"); + strcpy(csi_reset_str,"csi_reset_b"); + } + + switch(on) + { + case CSI_SUBDEV_STBY_ON: + csi_dev_dbg("CSI_SUBDEV_STBY_ON\n"); + //reset off io + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + msleep(10); + //active mclk before stadby in + clk_enable(dev->csi_module_clk); + msleep(100); + //standby on io + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_STBY_ON,csi_stby_str); + msleep(100); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_STBY_OFF,csi_stby_str); + msleep(100); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_STBY_ON,csi_stby_str); + msleep(100); + //inactive mclk after stadby in + clk_disable(dev->csi_module_clk); + + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_ON,csi_reset_str); + msleep(10); + break; + case CSI_SUBDEV_STBY_OFF: + csi_dev_dbg("CSI_SUBDEV_STBY_OFF\n"); + //active mclk before stadby out + clk_enable(dev->csi_module_clk); + msleep(10); + //reset off io + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + msleep(10); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_ON,csi_reset_str); + msleep(100); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_STBY_OFF,csi_stby_str); + msleep(10); + break; + case CSI_SUBDEV_PWR_ON: + csi_dev_dbg("CSI_SUBDEV_PWR_ON\n"); + //inactive mclk before power on + clk_disable(dev->csi_module_clk); + //power on reset + gpio_set_one_pin_io_status(dev->csi_pin_hd,1,csi_stby_str);//set the gpio to output + gpio_set_one_pin_io_status(dev->csi_pin_hd,1,csi_reset_str);//set the gpio to output + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_STBY_ON,csi_stby_str); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_ON,csi_reset_str); + msleep(1); + //power supply + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_PWR_ON,csi_power_str); + msleep(10); + if(dev->dvdd) { + regulator_enable(dev->dvdd); + msleep(10); + } + if(dev->avdd) { + regulator_enable(dev->avdd); + msleep(10); + } + if(dev->iovdd) { + regulator_enable(dev->iovdd); + msleep(10); + } + //active mclk before power on + clk_enable(dev->csi_module_clk); + //reset after power on + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + msleep(10); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_ON,csi_reset_str); + msleep(100); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + msleep(100); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_STBY_OFF,csi_stby_str); + msleep(10); + break; + + case CSI_SUBDEV_PWR_OFF: + csi_dev_dbg("CSI_SUBDEV_PWR_OFF\n"); + //power supply off + if(dev->iovdd) { + regulator_disable(dev->iovdd); + msleep(10); + } + if(dev->avdd) { + regulator_disable(dev->avdd); + msleep(10); + } + if(dev->dvdd) { + regulator_disable(dev->dvdd); + msleep(10); + } + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_PWR_OFF,csi_power_str); + msleep(10); + + //inactive mclk after power off + clk_disable(dev->csi_module_clk); + + //set the io to hi-z + gpio_set_one_pin_io_status(dev->csi_pin_hd,0,csi_reset_str);//set the gpio to input + gpio_set_one_pin_io_status(dev->csi_pin_hd,0,csi_stby_str);//set the gpio to input + break; + default: + return -EINVAL; + } + + return 0; +} + +static int sensor_reset(struct v4l2_subdev *sd, u32 val) +{ + struct csi_dev *dev=(struct csi_dev *)dev_get_drvdata(sd->v4l2_dev->dev); + struct sensor_info *info = to_state(sd); + char csi_reset_str[32]; + + if(info->ccm_info->iocfg == 0) { + strcpy(csi_reset_str,"csi_reset"); + } else if(info->ccm_info->iocfg == 1) { + strcpy(csi_reset_str,"csi_reset_b"); + } + + switch(val) + { + case CSI_SUBDEV_RST_OFF: + csi_dev_dbg("CSI_SUBDEV_RST_OFF\n"); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + msleep(10); + break; + case CSI_SUBDEV_RST_ON: + csi_dev_dbg("CSI_SUBDEV_RST_ON\n"); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_ON,csi_reset_str); + msleep(10); + break; + case CSI_SUBDEV_RST_PUL: + csi_dev_dbg("CSI_SUBDEV_RST_PUL\n"); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + msleep(10); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_ON,csi_reset_str); + msleep(100); + gpio_write_one_pin_value(dev->csi_pin_hd,CSI_RST_OFF,csi_reset_str); + msleep(10); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int sensor_detect(struct v4l2_subdev *sd) +{ + int ret; + unsigned int SENSOR_ID=0; + struct regval_list regs; + + //regs.reg_num[0] = 0xfe; + //regs.value[0] = 0x00; //PAGE 0x00 + //ret = sensor_write(sd, regs.reg_num, regs.value); +// if (ret < 0) { +// csi_dev_err("sensor_write err at sensor_detect!\n"); +// return ret; +// } + + regs.reg_num[0] = 0xf0; + ret = sensor_read(sd, regs.reg_num, regs.value); + SENSOR_ID|= (regs.value[0]<< 8); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_detect!\n"); + return ret; + } + + regs.reg_num[0] = 0xf1; + ret = sensor_read(sd, regs.reg_num, regs.value); + SENSOR_ID|= (regs.value[0]); + printk("GC2035_SENSOR_ID=%x",SENSOR_ID); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_detect!\n"); + return ret; + } + + if(SENSOR_ID != GC2035_SENSOR_ID) + return -ENODEV; + + return 0; +} + +static int sensor_init(struct v4l2_subdev *sd, u32 val) +{ + int ret; + csi_dev_dbg("sensor_init\n"); + /*Make sure it is a target sensor*/ + ret = sensor_detect(sd); + if (ret) { + csi_dev_err("chip found is not an target chip.\n"); + return ret; + } + + return sensor_write_array(sd, sensor_default_regs , ARRAY_SIZE(sensor_default_regs)); +} + +static long sensor_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + int ret=0; + + switch(cmd){ + case CSI_SUBDEV_CMD_GET_INFO: + { + struct sensor_info *info = to_state(sd); + __csi_subdev_info_t *ccm_info = arg; + + csi_dev_dbg("CSI_SUBDEV_CMD_GET_INFO\n"); + + ccm_info->mclk = info->ccm_info->mclk ; + ccm_info->vref = info->ccm_info->vref ; + ccm_info->href = info->ccm_info->href ; + ccm_info->clock = info->ccm_info->clock; + ccm_info->iocfg = info->ccm_info->iocfg; + + csi_dev_dbg("ccm_info.mclk=%x\n ",info->ccm_info->mclk); + csi_dev_dbg("ccm_info.vref=%x\n ",info->ccm_info->vref); + csi_dev_dbg("ccm_info.href=%x\n ",info->ccm_info->href); + csi_dev_dbg("ccm_info.clock=%x\n ",info->ccm_info->clock); + csi_dev_dbg("ccm_info.iocfg=%x\n ",info->ccm_info->iocfg); + + break; + } + case CSI_SUBDEV_CMD_SET_INFO: + { + struct sensor_info *info = to_state(sd); + __csi_subdev_info_t *ccm_info = arg; + + csi_dev_dbg("CSI_SUBDEV_CMD_SET_INFO\n"); + + info->ccm_info->mclk = ccm_info->mclk ; + info->ccm_info->vref = ccm_info->vref ; + info->ccm_info->href = ccm_info->href ; + info->ccm_info->clock = ccm_info->clock ; + info->ccm_info->iocfg = ccm_info->iocfg ; + + csi_dev_dbg("ccm_info.mclk=%x\n ",info->ccm_info->mclk); + csi_dev_dbg("ccm_info.vref=%x\n ",info->ccm_info->vref); + csi_dev_dbg("ccm_info.href=%x\n ",info->ccm_info->href); + csi_dev_dbg("ccm_info.clock=%x\n ",info->ccm_info->clock); + csi_dev_dbg("ccm_info.iocfg=%x\n ",info->ccm_info->iocfg); + + break; + } + default: + return -EINVAL; + } + return ret; +} + + +/* + * Store information about the video data format. + */ +static struct sensor_format_struct { + __u8 *desc; + //__u32 pixelformat; + enum v4l2_mbus_pixelcode mbus_code;//linux-3.0 + struct regval_list *regs; + int regs_size; + int bpp; /* Bytes per pixel */ +} sensor_formats[] = { + { + .desc = "YUYV 4:2:2", + .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,//linux-3.0 + .regs = sensor_fmt_yuv422_yuyv, + .regs_size = ARRAY_SIZE(sensor_fmt_yuv422_yuyv), + .bpp = 2, + }, + { + .desc = "YVYU 4:2:2", + .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,//linux-3.0 + .regs = sensor_fmt_yuv422_yvyu, + .regs_size = ARRAY_SIZE(sensor_fmt_yuv422_yvyu), + .bpp = 2, + }, + { + .desc = "UYVY 4:2:2", + .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,//linux-3.0 + .regs = sensor_fmt_yuv422_uyvy, + .regs_size = ARRAY_SIZE(sensor_fmt_yuv422_uyvy), + .bpp = 2, + }, + { + .desc = "VYUY 4:2:2", + .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,//linux-3.0 + .regs = sensor_fmt_yuv422_vyuy, + .regs_size = ARRAY_SIZE(sensor_fmt_yuv422_vyuy), + .bpp = 2, + }, + { + .desc = "Raw RGB Bayer", + .mbus_code = V4L2_MBUS_FMT_SBGGR8_1X8,//linux-3.0 + .regs = sensor_fmt_raw, + .regs_size = ARRAY_SIZE(sensor_fmt_raw), + .bpp = 1 + }, +}; +#define N_FMTS ARRAY_SIZE(sensor_formats) + + + +/* + * Then there is the issue of window sizes. Try to capture the info here. + */ + + +static struct sensor_win_size { + int width; + int height; + int hstart; /* Start/stop values for the camera. Note */ + int hstop; /* that they do not always make complete */ + int vstart; /* sense to humans, but evidently the sensor */ + int vstop; /* will do the right thing... */ + struct regval_list *regs; /* Regs to tweak */ + int regs_size; + int (*set_size) (struct v4l2_subdev *sd); +/* h/vref stuff */ +} sensor_win_sizes[] = { + /* UXGA */ + { + .width = UXGA_WIDTH, + .height = UXGA_HEIGHT, + .regs = sensor_uxga_regs, + .regs_size = ARRAY_SIZE(sensor_uxga_regs), + .set_size = NULL, + }, + /* XVGA */ + { + .width = SXGA_WIDTH, + .height = SXGA_HEIGHT, + .regs = sensor_sxga_regs, + .regs_size = ARRAY_SIZE(sensor_sxga_regs), + .set_size = NULL, + }, + /* 720p */ + { + .width = HD720_WIDTH, + .height = HD720_HEIGHT, + .regs = Gc2015_sensor_hd720_regs, + .regs_size = ARRAY_SIZE(Gc2015_sensor_hd720_regs), + .set_size = NULL, + }, + /* XGA */ + { + .width = XGA_WIDTH, + .height = XGA_HEIGHT, + .regs = sensor_xga_regs, + .regs_size = ARRAY_SIZE(sensor_xga_regs), + .set_size = NULL, + }, + /* SVGA */ + { + .width = SVGA_WIDTH, + .height = SVGA_HEIGHT, + .regs = sensor_svga_regs, + .regs_size = ARRAY_SIZE(sensor_svga_regs), + .set_size = NULL, + }, + /* VGA */ + { + .width = VGA_WIDTH, + .height = VGA_HEIGHT, + .regs = sensor_vga_regs, + .regs_size = ARRAY_SIZE(sensor_vga_regs), + .set_size = NULL, + }, +}; + +#define N_WIN_SIZES (ARRAY_SIZE(sensor_win_sizes)) + + + + +static int sensor_enum_fmt(struct v4l2_subdev *sd, unsigned index, + enum v4l2_mbus_pixelcode *code)//linux-3.0 +{ +// struct sensor_format_struct *ofmt; + + if (index >= N_FMTS)//linux-3.0 + return -EINVAL; + + *code = sensor_formats[index].mbus_code;//linux-3.0 + +// ofmt = sensor_formats + fmt->index; +// fmt->flags = 0; +// strcpy(fmt->description, ofmt->desc); +// fmt->pixelformat = ofmt->pixelformat; + return 0; +} + + +static int sensor_try_fmt_internal(struct v4l2_subdev *sd, + //struct v4l2_format *fmt, + struct v4l2_mbus_framefmt *fmt,//linux-3.0 + struct sensor_format_struct **ret_fmt, + struct sensor_win_size **ret_wsize) +{ + int index; + struct sensor_win_size *wsize; +// struct v4l2_pix_format *pix = &fmt->fmt.pix;//linux-3.0 + csi_dev_dbg("sensor_try_fmt_internal\n"); + for (index = 0; index < N_FMTS; index++) + if (sensor_formats[index].mbus_code == fmt->code)//linux-3.0 + break; + + if (index >= N_FMTS) { + /* default to first format */ + index = 0; + fmt->code = sensor_formats[0].mbus_code;//linux-3.0 + } + + if (ret_fmt != NULL) + *ret_fmt = sensor_formats + index; + + /* + * Fields: the sensor devices claim to be progressive. + */ + fmt->field = V4L2_FIELD_NONE;//linux-3.0 + + + /* + * Round requested image size down to the nearest + * we support, but not below the smallest. + */ + for (wsize = sensor_win_sizes; wsize < sensor_win_sizes + N_WIN_SIZES; + wsize++) + if (fmt->width >= wsize->width && fmt->height >= wsize->height)//linux-3.0 + break; + + if (wsize >= sensor_win_sizes + N_WIN_SIZES) + wsize--; /* Take the smallest one */ + if (ret_wsize != NULL) + *ret_wsize = wsize; + /* + * Note the size we'll actually handle. + */ + fmt->width = wsize->width;//linux-3.0 + fmt->height = wsize->height;//linux-3.0 + //pix->bytesperline = pix->width*sensor_formats[index].bpp;//linux-3.0 + //pix->sizeimage = pix->height*pix->bytesperline;//linux-3.0 + + return 0; +} + +static int sensor_try_fmt(struct v4l2_subdev *sd, + struct v4l2_mbus_framefmt *fmt)//linux-3.0 +{ + return sensor_try_fmt_internal(sd, fmt, NULL, NULL); +} + +/* + * Set a format. + */ +static int sensor_s_fmt(struct v4l2_subdev *sd, + struct v4l2_mbus_framefmt *fmt)//linux-3.0 +{ + int ret; + +#if 1 + unsigned int temp=0,shutter=0; + struct regval_list regs; +#endif + + + struct sensor_format_struct *sensor_fmt; + struct sensor_win_size *wsize; + struct sensor_info *info = to_state(sd); + + + + + + + + + + +// printk("chr wsize.width = [%d], wsize.height = [%d]\n", wsize->width, wsize->height); + //csi_dev_dbg("sensor_s_fmt\n"); + + //////////////shutter-gain/////////////// + ret = sensor_try_fmt_internal(sd, fmt, &sensor_fmt, &wsize); + if (ret) + return ret; + + + +#if 1 + + if((wsize->width==1600)&&(wsize->height==1200)) //capture mode >640*480 + { + // printk(" read 2035 exptime 11111111\n" ); + + regs.reg_num[0] = 0xfe; + regs.value[0] = 0x00; //page 0 + sensor_write(sd, regs.reg_num, regs.value); + + regs.reg_num[0] = 0xb6; + regs.value[0] = 0x02; //turn off aec + sensor_write(sd, regs.reg_num, regs.value); + + /*read shutter */ + regs.reg_num[0] = 0x03; + sensor_read(sd, regs.reg_num, regs.value); + + + temp |= (regs.value[0]<< 8); + // printk(" read 0x03 = [%x]\n", regs.value[0]); + + regs.reg_num[0] = 0x04; + sensor_read(sd, regs.reg_num,regs.value); + temp |= (regs.value[0] & 0xff); + // printk(" read 0x04 = [%x]\n", regs.value[0]); + + shutter=temp; + // printk(" shutter = [%x]\n", shutter); + + } + + +#endif + + + + + sensor_write_array(sd, sensor_fmt->regs , sensor_fmt->regs_size); + + + + #if 0 + + if((wsize->width==640)&&(wsize->height==480)) //capture mode >640*480 + { + msleep(300); + + } + #endif + + + + + ret = 0; + if (wsize->regs) + { + ret = sensor_write_array(sd, wsize->regs , wsize->regs_size); + if (ret < 0) + return ret; + } + + if (wsize->set_size) + { + ret = wsize->set_size(sd); + if (ret < 0) + return ret; + } + + + + ////////// + + #if 1 + if((wsize->width==1600)&&(wsize->height==1200)) + { + + + //printk(" write 2035 exptime 22222222\n" ); + + + regs.reg_num[0] = 0xfe; + regs.value[0] = 0x00; //page 0 + sensor_write(sd, regs.reg_num, regs.value); + + + + shutter= shutter /2; // 2 + + if(shutter < 1) shutter = 1; + regs.reg_num[0] = 0x03; + + regs.value[0] = ((shutter>>8)&0xff); + + // printk(" write0x03 = [%x]\n", regs.value[0]); + + sensor_write(sd, regs.reg_num, regs.value); + + + + regs.reg_num[0] = 0x04; + regs.value[0] = (shutter&0xff); + + //printk(" write0x03 = [%x]\n", regs.value[0]); + + sensor_write(sd, regs.reg_num, regs.value); + + msleep(550); + } + +#endif +///////////////////////////// + + + info->fmt = sensor_fmt; + info->width = wsize->width; + info->height = wsize->height; + + return 0; +} + +/* + * Implement G/S_PARM. There is a "high quality" mode we could try + * to do someday; for now, we just do the frame rate tweak. + */ +static int sensor_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) +{ + struct v4l2_captureparm *cp = &parms->parm.capture; + struct sensor_info *info = to_state(sd); + + if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + memset(cp, 0, sizeof(struct v4l2_captureparm)); + cp->capability = V4L2_CAP_TIMEPERFRAME; + cp->timeperframe.numerator = 1; + + if (info->width > SVGA_WIDTH && info->height > SVGA_HEIGHT) { + cp->timeperframe.denominator = SENSOR_FRAME_RATE/2; + } + else { + cp->timeperframe.denominator = SENSOR_FRAME_RATE; + } + + return 0; +} + +static int sensor_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) +{ +// struct v4l2_captureparm *cp = &parms->parm.capture; +// struct v4l2_fract *tpf = &cp->timeperframe; +// struct sensor_info *info = to_state(sd); +// int div; + +// if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) +// return -EINVAL; +// if (cp->extendedmode != 0) +// return -EINVAL; + +// if (tpf->numerator == 0 || tpf->denominator == 0) +// div = 1; /* Reset to full rate */ +// else { +// if (info->width > SVGA_WIDTH && info->height > SVGA_HEIGHT) { +// div = (tpf->numerator*SENSOR_FRAME_RATE/2)/tpf->denominator; +// } +// else { +// div = (tpf->numerator*SENSOR_FRAME_RATE)/tpf->denominator; +// } +// } +// +// if (div == 0) +// div = 1; +// else if (div > 8) +// div = 8; +// +// switch() +// +// info->clkrc = (info->clkrc & 0x80) | div; +// tpf->numerator = 1; +// tpf->denominator = sensor_FRAME_RATE/div; +// +// sensor_write(sd, REG_CLKRC, info->clkrc); + //return -EINVAL; + return 0; +} + + +/* + * Code for dealing with controls. + * fill with different sensor module + * different sensor module has different settings here + * if not support the follow function ,retrun -EINVAL + */ + +/* *********************************************begin of ******************************************** */ +static int sensor_queryctrl(struct v4l2_subdev *sd, + struct v4l2_queryctrl *qc) +{ + /* Fill in min, max, step and default value for these controls. */ + /* see include/linux/videodev2.h for details */ + /* see sensor_s_parm and sensor_g_parm for the meaning of value */ + printk("%s qc->id=%d\n", __FUNCTION__, (qc->id - V4L2_CID_BASE)); + switch (qc->id) { +// case V4L2_CID_BRIGHTNESS: +// return v4l2_ctrl_query_fill(qc, -4, 4, 1, 1); +// case V4L2_CID_CONTRAST: +// return v4l2_ctrl_query_fill(qc, -4, 4, 1, 1); +// case V4L2_CID_SATURATION: +// return v4l2_ctrl_query_fill(qc, -4, 4, 1, 1); +// case V4L2_CID_HUE: +// return v4l2_ctrl_query_fill(qc, -180, 180, 5, 0); + case V4L2_CID_VFLIP: + case V4L2_CID_HFLIP: + return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0); +// case V4L2_CID_GAIN: +// return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128); +// case V4L2_CID_AUTOGAIN: +// return v4l2_ctrl_query_fill(qc, 0, 1, 1, 1); + case V4L2_CID_EXPOSURE: + return v4l2_ctrl_query_fill(qc, -4, 4, 1, 0); + case V4L2_CID_EXPOSURE_AUTO: + return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0); + case V4L2_CID_DO_WHITE_BALANCE: + return v4l2_ctrl_query_fill(qc, 0, 5, 1, 0); + case V4L2_CID_AUTO_WHITE_BALANCE: + return v4l2_ctrl_query_fill(qc, 0, 1, 1, 1); + case V4L2_CID_COLORFX: + return v4l2_ctrl_query_fill(qc, 0, 9, 1, 0); + case V4L2_CID_CAMERA_FLASH_MODE: + return v4l2_ctrl_query_fill(qc, 0, 4, 1, 0); + } + return -EINVAL; +} + +static int sensor_g_hflip(struct v4l2_subdev *sd, __s32 *value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + regs.reg_num[0] = 0xfe; + regs.value[0] = 0x00; //page 0 + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_g_hflip!\n"); + return ret; + } + + regs.reg_num[0] = 0x17; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_g_hflip!\n"); + return ret; + } + + regs.value[0] &= (1<<0); + regs.value[0] = regs.value[0]>>0; //0x29 bit0 is mirror + + *value = regs.value[0]; + + info->hflip = *value; + return 0; +} + +static int sensor_s_hflip(struct v4l2_subdev *sd, int value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + regs.reg_num[0] = 0xfe; + regs.value[0] = 0x00; //page 0 + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_s_hflip!\n"); + return ret; + } + regs.reg_num[0] = 0x17; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_s_hflip!\n"); + return ret; + } + + regs.value[0] &= 0xfc; + switch (value) { + case 0: + regs.value[0] |= info->vflip<<1; + break; + case 1: + regs.value[0] |= (0x01|(info->vflip<<1)); + break; + default: + return -EINVAL; + } + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_s_hflip!\n"); + return ret; + } + + mdelay(20); + + info->hflip = value; + return 0; +} + +static int sensor_g_vflip(struct v4l2_subdev *sd, __s32 *value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + regs.reg_num[0] = 0xfe; + regs.value[0] = 0x00; //page 0 + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_g_vflip!\n"); + return ret; + } + + regs.reg_num[0] = 0x17; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_g_vflip!\n"); + return ret; + } + + regs.value[0] &= (1<<1); + regs.value[0] = regs.value[0]>>1; //0x29 bit1 is upsidedown + + *value = regs.value[0]; + + info->vflip = *value; + return 0; +} + +static int sensor_s_vflip(struct v4l2_subdev *sd, int value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + regs.reg_num[0] = 0xfe; + regs.value[0] = 0x00; //page 0 + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_s_vflip!\n"); + return ret; + } + + regs.reg_num[0] = 0x17; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_s_vflip!\n"); + return ret; + } + + regs.value[0] &= 0xfc; + switch (value) { + case 0: + regs.value[0] |=info->hflip; + break; + case 1: + regs.value[0] |= (0x02|info->hflip); + break; + default: + return -EINVAL; + } + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_s_vflip!\n"); + return ret; + } + + mdelay(20); + + info->vflip = value; + return 0; +} + +static int sensor_g_autogain(struct v4l2_subdev *sd, __s32 *value) +{ + return -EINVAL; +} + +static int sensor_s_autogain(struct v4l2_subdev *sd, int value) +{ + return -EINVAL; +} + +static int sensor_g_autoexp(struct v4l2_subdev *sd, __s32 *value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + regs.reg_num[0] = 0xfe; + regs.value[0] = 0x00; //page 0 + + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_g_autoexp!\n"); + return ret; + } + + regs.reg_num[0] = 0xb6; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_g_autoexp!\n"); + return ret; + } + + regs.value[0] &= 0x01; + if (regs.value[0] == 0x01) { + *value = V4L2_EXPOSURE_AUTO; + } + else + { + *value = V4L2_EXPOSURE_MANUAL; + } + + info->autoexp = *value; + return 0; +} + +static int sensor_s_autoexp(struct v4l2_subdev *sd, + enum v4l2_exposure_auto_type value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + regs.reg_num[0] = 0xfe; + regs.value[0] = 0x00; //page 0 + + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_s_autoexp!\n"); + return ret; + } + + regs.reg_num[0] = 0xb6; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_s_autoexp!\n"); + return ret; + } + + switch (value) { + case V4L2_EXPOSURE_AUTO: + regs.value[0] |= 0x01; + break; + case V4L2_EXPOSURE_MANUAL: + regs.value[0] &= 0xfe; + break; + case V4L2_EXPOSURE_SHUTTER_PRIORITY: + return -EINVAL; + case V4L2_EXPOSURE_APERTURE_PRIORITY: + return -EINVAL; + default: + return -EINVAL; + } + + //ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_s_autoexp!\n"); + return ret; + } + + mdelay(10); + + info->autoexp = value; + return 0; +} + +static int sensor_g_autowb(struct v4l2_subdev *sd, int *value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + regs.reg_num[0] = 0xfe; + regs.value[0] = 0x00; //page 0 + + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_g_autowb!\n"); + return ret; + } + + regs.reg_num[0] = 0x82; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_g_autowb!\n"); + return ret; + } + + regs.value[0] &= (1<<1); + regs.value[0] = regs.value[0]>>1; //0x42 bit1 is awb enable + + *value = regs.value[0]; + info->autowb = *value; + + return 0; +} + +static int sensor_s_autowb(struct v4l2_subdev *sd, int value) +{ + int ret; + struct sensor_info *info = to_state(sd); + struct regval_list regs; + + ret = sensor_write_array(sd, sensor_wb_auto_regs, ARRAY_SIZE(sensor_wb_auto_regs)); + if (ret < 0) { + csi_dev_err("sensor_write_array err at sensor_s_autowb!\n"); + return ret; + } + + regs.reg_num[0] = 0x82; + ret = sensor_read(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_read err at sensor_s_autowb!\n"); + return ret; + } + + switch(value) { + case 0: + regs.value[0] &= 0xfd; + break; + case 1: + regs.value[0] |= 0x02; + break; + default: + break; + } + ret = sensor_write(sd, regs.reg_num, regs.value); + if (ret < 0) { + csi_dev_err("sensor_write err at sensor_s_autowb!\n"); + return ret; + } + + mdelay(10); + + info->autowb = value; + return 0; +} + +static int sensor_g_hue(struct v4l2_subdev *sd, __s32 *value) +{ + return -EINVAL; +} + +static int sensor_s_hue(struct v4l2_subdev *sd, int value) +{ + return -EINVAL; +} + +static int sensor_g_gain(struct v4l2_subdev *sd, __s32 *value) +{ + return -EINVAL; +} + +static int sensor_s_gain(struct v4l2_subdev *sd, int value) +{ + return -EINVAL; +} +/* *********************************************end of ******************************************** */ + +static int sensor_g_brightness(struct v4l2_subdev *sd, __s32 *value) +{ + struct sensor_info *info = to_state(sd); + + *value = info->brightness; + return 0; +} + +static int sensor_s_brightness(struct v4l2_subdev *sd, int value) +{ + int ret; + struct sensor_info *info = to_state(sd); + + switch (value) { + case -4: + ret = sensor_write_array(sd, sensor_brightness_neg4_regs, ARRAY_SIZE(sensor_brightness_neg4_regs)); + break; + case -3: + ret = sensor_write_array(sd, sensor_brightness_neg3_regs, ARRAY_SIZE(sensor_brightness_neg3_regs)); + break; + case -2: + ret = sensor_write_array(sd, sensor_brightness_neg2_regs, ARRAY_SIZE(sensor_brightness_neg2_regs)); + break; + case -1: + ret = sensor_write_array(sd, sensor_brightness_neg1_regs, ARRAY_SIZE(sensor_brightness_neg1_regs)); + break; + case 0: + ret = sensor_write_array(sd, sensor_brightness_zero_regs, ARRAY_SIZE(sensor_brightness_zero_regs)); + break; + case 1: + ret = sensor_write_array(sd, sensor_brightness_pos1_regs, ARRAY_SIZE(sensor_brightness_pos1_regs)); + break; + case 2: + ret = sensor_write_array(sd, sensor_brightness_pos2_regs, ARRAY_SIZE(sensor_brightness_pos2_regs)); + break; + case 3: + ret = sensor_write_array(sd, sensor_brightness_pos3_regs, ARRAY_SIZE(sensor_brightness_pos3_regs)); + break; + case 4: + ret = sensor_write_array(sd, sensor_brightness_pos4_regs, ARRAY_SIZE(sensor_brightness_pos4_regs)); + break; + default: + return -EINVAL; + } + + if (ret < 0) { + csi_dev_err("sensor_write_array err at sensor_s_brightness!\n"); + return ret; + } + + mdelay(10); + + info->brightness = value; + return 0; +} + +static int sensor_g_contrast(struct v4l2_subdev *sd, __s32 *value) +{ + struct sensor_info *info = to_state(sd); + + *value = info->contrast; + return 0; +} + +static int sensor_s_contrast(struct v4l2_subdev *sd, int value) +{ + int ret; + struct sensor_info *info = to_state(sd); + + switch (value) { + case -4: + ret = sensor_write_array(sd, sensor_contrast_neg4_regs, ARRAY_SIZE(sensor_contrast_neg4_regs)); + break; + case -3: + ret = sensor_write_array(sd, sensor_contrast_neg3_regs, ARRAY_SIZE(sensor_contrast_neg3_regs)); + break; + case -2: + ret = sensor_write_array(sd, sensor_contrast_neg2_regs, ARRAY_SIZE(sensor_contrast_neg2_regs)); + break; + case -1: + ret = sensor_write_array(sd, sensor_contrast_neg1_regs, ARRAY_SIZE(sensor_contrast_neg1_regs)); + break; + case 0: + ret = sensor_write_array(sd, sensor_contrast_zero_regs, ARRAY_SIZE(sensor_contrast_zero_regs)); + break; + case 1: + ret = sensor_write_array(sd, sensor_contrast_pos1_regs, ARRAY_SIZE(sensor_contrast_pos1_regs)); + break; + case 2: + ret = sensor_write_array(sd, sensor_contrast_pos2_regs, ARRAY_SIZE(sensor_contrast_pos2_regs)); + break; + case 3: + ret = sensor_write_array(sd, sensor_contrast_pos3_regs, ARRAY_SIZE(sensor_contrast_pos3_regs)); + break; + case 4: + ret = sensor_write_array(sd, sensor_contrast_pos4_regs, ARRAY_SIZE(sensor_contrast_pos4_regs)); + break; + default: + return -EINVAL; + } + + if (ret < 0) { + csi_dev_err("sensor_write_array err at sensor_s_contrast!\n"); + return ret; + } + + mdelay(10); + + info->contrast = value; + return 0; +} + +static int sensor_g_saturation(struct v4l2_subdev *sd, __s32 *value) +{ + struct sensor_info *info = to_state(sd); + + *value = info->saturation; + return 0; +} + +static int sensor_s_saturation(struct v4l2_subdev *sd, int value) +{ + int ret; + struct sensor_info *info = to_state(sd); + + switch (value) { + case -4: + ret = sensor_write_array(sd, sensor_saturation_neg4_regs, ARRAY_SIZE(sensor_saturation_neg4_regs)); + break; + case -3: + ret = sensor_write_array(sd, sensor_saturation_neg3_regs, ARRAY_SIZE(sensor_saturation_neg3_regs)); + break; + case -2: + ret = sensor_write_array(sd, sensor_saturation_neg2_regs, ARRAY_SIZE(sensor_saturation_neg2_regs)); + break; + case -1: + ret = sensor_write_array(sd, sensor_saturation_neg1_regs, ARRAY_SIZE(sensor_saturation_neg1_regs)); + break; + case 0: + ret = sensor_write_array(sd, sensor_saturation_zero_regs, ARRAY_SIZE(sensor_saturation_zero_regs)); + break; + case 1: + ret = sensor_write_array(sd, sensor_saturation_pos1_regs, ARRAY_SIZE(sensor_saturation_pos1_regs)); + break; + case 2: + ret = sensor_write_array(sd, sensor_saturation_pos2_regs, ARRAY_SIZE(sensor_saturation_pos2_regs)); + break; + case 3: + ret = sensor_write_array(sd, sensor_saturation_pos3_regs, ARRAY_SIZE(sensor_saturation_pos3_regs)); + break; + case 4: + ret = sensor_write_array(sd, sensor_saturation_pos4_regs, ARRAY_SIZE(sensor_saturation_pos4_regs)); + break; + default: + return -EINVAL; + } + + if (ret < 0) { + csi_dev_err("sensor_write_array err at sensor_s_saturation!\n"); + return ret; + } + + mdelay(10); + + info->saturation = value; + return 0; +} + +static int sensor_g_exp(struct v4l2_subdev *sd, __s32 *value) +{ + struct sensor_info *info = to_state(sd); + + *value = info->exp; + return 0; +} + +static int sensor_s_exp(struct v4l2_subdev *sd, int value) +{ + int ret; + struct sensor_info *info = to_state(sd); + + switch (value) { + case -4: + ret = sensor_write_array(sd, sensor_ev_neg4_regs, ARRAY_SIZE(sensor_ev_neg4_regs)); + break; + case -3: + ret = sensor_write_array(sd, sensor_ev_neg3_regs, ARRAY_SIZE(sensor_ev_neg3_regs)); + break; + case -2: + ret = sensor_write_array(sd, sensor_ev_neg2_regs, ARRAY_SIZE(sensor_ev_neg2_regs)); + break; + case -1: + ret = sensor_write_array(sd, sensor_ev_neg1_regs, ARRAY_SIZE(sensor_ev_neg1_regs)); + break; + case 0: + ret = sensor_write_array(sd, sensor_ev_zero_regs, ARRAY_SIZE(sensor_ev_zero_regs)); + break; + case 1: + ret = sensor_write_array(sd, sensor_ev_pos1_regs, ARRAY_SIZE(sensor_ev_pos1_regs)); + break; + case 2: + ret = sensor_write_array(sd, sensor_ev_pos2_regs, ARRAY_SIZE(sensor_ev_pos2_regs)); + break; + case 3: + ret = sensor_write_array(sd, sensor_ev_pos3_regs, ARRAY_SIZE(sensor_ev_pos3_regs)); + break; + case 4: + ret = sensor_write_array(sd, sensor_ev_pos4_regs, ARRAY_SIZE(sensor_ev_pos4_regs)); + break; + default: + return -EINVAL; + } + + if (ret < 0) { + csi_dev_err("sensor_write_array err at sensor_s_exp!\n"); + return ret; + } + + mdelay(10); + + info->exp = value; + return 0; +} + +static int sensor_g_wb(struct v4l2_subdev *sd, int *value) +{ + struct sensor_info *info = to_state(sd); + enum v4l2_whiteblance *wb_type = (enum v4l2_whiteblance*)value; + + *wb_type = info->wb; + + return 0; +} + +static int sensor_s_wb(struct v4l2_subdev *sd, + enum v4l2_whiteblance value) +{ + int ret; + struct sensor_info *info = to_state(sd); + + if (value == V4L2_WB_AUTO) { + ret = sensor_s_autowb(sd, 1); + return ret; + } + else { + ret = sensor_s_autowb(sd, 0); + if(ret < 0) { + csi_dev_err("sensor_s_autowb error, return %x!\n",ret); + return ret; + } + + switch (value) { + case V4L2_WB_CLOUD: + ret = sensor_write_array(sd, sensor_wb_cloud_regs, ARRAY_SIZE(sensor_wb_cloud_regs)); + break; + case V4L2_WB_DAYLIGHT: + ret = sensor_write_array(sd, sensor_wb_daylight_regs, ARRAY_SIZE(sensor_wb_daylight_regs)); + break; + case V4L2_WB_INCANDESCENCE: + ret = sensor_write_array(sd, sensor_wb_incandescence_regs, ARRAY_SIZE(sensor_wb_incandescence_regs)); + break; + case V4L2_WB_FLUORESCENT: + ret = sensor_write_array(sd, sensor_wb_fluorescent_regs, ARRAY_SIZE(sensor_wb_fluorescent_regs)); + break; + case V4L2_WB_TUNGSTEN: + ret = sensor_write_array(sd, sensor_wb_tungsten_regs, ARRAY_SIZE(sensor_wb_tungsten_regs)); + break; + default: + return -EINVAL; + } + } + + if (ret < 0) { + csi_dev_err("sensor_s_wb error, return %x!\n",ret); + return ret; + } + + mdelay(10); + + info->wb = value; + return 0; +} + +static int sensor_g_colorfx(struct v4l2_subdev *sd, + __s32 *value) +{ + struct sensor_info *info = to_state(sd); + enum v4l2_colorfx *clrfx_type = (enum v4l2_colorfx*)value; + + *clrfx_type = info->clrfx; + return 0; +} + +static int sensor_s_colorfx(struct v4l2_subdev *sd, + enum v4l2_colorfx value) +{ + int ret; + struct sensor_info *info = to_state(sd); + + switch (value) { + case V4L2_COLORFX_NONE: + ret = sensor_write_array(sd, sensor_colorfx_none_regs, ARRAY_SIZE(sensor_colorfx_none_regs)); + break; + case V4L2_COLORFX_BW: + ret = sensor_write_array(sd, sensor_colorfx_bw_regs, ARRAY_SIZE(sensor_colorfx_bw_regs)); + break; + case V4L2_COLORFX_SEPIA: + ret = sensor_write_array(sd, sensor_colorfx_sepia_regs, ARRAY_SIZE(sensor_colorfx_sepia_regs)); + break; + case V4L2_COLORFX_NEGATIVE: + ret = sensor_write_array(sd, sensor_colorfx_negative_regs, ARRAY_SIZE(sensor_colorfx_negative_regs)); + break; + case V4L2_COLORFX_EMBOSS: + ret = sensor_write_array(sd, sensor_colorfx_emboss_regs, ARRAY_SIZE(sensor_colorfx_emboss_regs)); + break; + case V4L2_COLORFX_SKETCH: + ret = sensor_write_array(sd, sensor_colorfx_sketch_regs, ARRAY_SIZE(sensor_colorfx_sketch_regs)); + break; + case V4L2_COLORFX_SKY_BLUE: + ret = sensor_write_array(sd, sensor_colorfx_sky_blue_regs, ARRAY_SIZE(sensor_colorfx_sky_blue_regs)); + break; + case V4L2_COLORFX_GRASS_GREEN: + ret = sensor_write_array(sd, sensor_colorfx_grass_green_regs, ARRAY_SIZE(sensor_colorfx_grass_green_regs)); + break; + case V4L2_COLORFX_SKIN_WHITEN: + ret = sensor_write_array(sd, sensor_colorfx_skin_whiten_regs, ARRAY_SIZE(sensor_colorfx_skin_whiten_regs)); + break; + case V4L2_COLORFX_VIVID: + ret = sensor_write_array(sd, sensor_colorfx_vivid_regs, ARRAY_SIZE(sensor_colorfx_vivid_regs)); + break; + default: + return -EINVAL; + } + + if (ret < 0) { + csi_dev_err("sensor_s_colorfx error, return %x!\n",ret); + return ret; + } + + mdelay(10); + + info->clrfx = value; + return 0; +} + +static int sensor_g_flash_mode(struct v4l2_subdev *sd, + __s32 *value) +{ + struct sensor_info *info = to_state(sd); + enum v4l2_flash_mode *flash_mode = (enum v4l2_flash_mode*)value; + + *flash_mode = info->flash_mode; + return 0; +} + +static int sensor_s_flash_mode(struct v4l2_subdev *sd, + enum v4l2_flash_mode value) +{ + struct sensor_info *info = to_state(sd); + struct csi_dev *dev=(struct csi_dev *)dev_get_drvdata(sd->v4l2_dev->dev); + char csi_flash_str[32]; + int flash_on,flash_off; + + if(info->ccm_info->iocfg == 0) { + strcpy(csi_flash_str,"csi_flash"); + } else if(info->ccm_info->iocfg == 1) { + strcpy(csi_flash_str,"csi_flash_b"); + } + + flash_on = (dev->flash_pol!=0)?1:0; + flash_off = (flash_on==1)?0:1; + + switch (value) { + case V4L2_FLASH_MODE_OFF: + gpio_write_one_pin_value(dev->csi_pin_hd,flash_off,csi_flash_str); + break; + case V4L2_FLASH_MODE_AUTO: + return -EINVAL; + break; + case V4L2_FLASH_MODE_ON: + gpio_write_one_pin_value(dev->csi_pin_hd,flash_on,csi_flash_str); + break; + case V4L2_FLASH_MODE_TORCH: + return -EINVAL; + break; + case V4L2_FLASH_MODE_RED_EYE: + return -EINVAL; + break; + default: + return -EINVAL; + } + + info->flash_mode = value; + return 0; +} + +static int sensor_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) +{ + switch (ctrl->id) { + case V4L2_CID_BRIGHTNESS: + return sensor_g_brightness(sd, &ctrl->value); + case V4L2_CID_CONTRAST: + return sensor_g_contrast(sd, &ctrl->value); + case V4L2_CID_SATURATION: + return sensor_g_saturation(sd, &ctrl->value); + case V4L2_CID_HUE: + return sensor_g_hue(sd, &ctrl->value); + case V4L2_CID_VFLIP: + return sensor_g_vflip(sd, &ctrl->value); + case V4L2_CID_HFLIP: + return sensor_g_hflip(sd, &ctrl->value); + case V4L2_CID_GAIN: + return sensor_g_gain(sd, &ctrl->value); + case V4L2_CID_AUTOGAIN: + return sensor_g_autogain(sd, &ctrl->value); + case V4L2_CID_EXPOSURE: + return sensor_g_exp(sd, &ctrl->value); + case V4L2_CID_EXPOSURE_AUTO: + return sensor_g_autoexp(sd, &ctrl->value); + case V4L2_CID_DO_WHITE_BALANCE: + return sensor_g_wb(sd, &ctrl->value); + case V4L2_CID_AUTO_WHITE_BALANCE: + return sensor_g_autowb(sd, &ctrl->value); + case V4L2_CID_COLORFX: + return sensor_g_colorfx(sd, &ctrl->value); + case V4L2_CID_CAMERA_FLASH_MODE: + return sensor_g_flash_mode(sd, &ctrl->value); + } + return -EINVAL; +} + +static int sensor_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) +{ + switch (ctrl->id) { + case V4L2_CID_BRIGHTNESS: + return sensor_s_brightness(sd, ctrl->value); + case V4L2_CID_CONTRAST: + return sensor_s_contrast(sd, ctrl->value); + case V4L2_CID_SATURATION: + return sensor_s_saturation(sd, ctrl->value); + case V4L2_CID_HUE: + return sensor_s_hue(sd, ctrl->value); + case V4L2_CID_VFLIP: + return sensor_s_vflip(sd, ctrl->value); + case V4L2_CID_HFLIP: + return sensor_s_hflip(sd, ctrl->value); + case V4L2_CID_GAIN: + return sensor_s_gain(sd, ctrl->value); + case V4L2_CID_AUTOGAIN: + return sensor_s_autogain(sd, ctrl->value); + case V4L2_CID_EXPOSURE: + return sensor_s_exp(sd, ctrl->value); + case V4L2_CID_EXPOSURE_AUTO: + return sensor_s_autoexp(sd, + (enum v4l2_exposure_auto_type) ctrl->value); + case V4L2_CID_DO_WHITE_BALANCE: + return sensor_s_wb(sd, + (enum v4l2_whiteblance) ctrl->value); + case V4L2_CID_AUTO_WHITE_BALANCE: + return sensor_s_autowb(sd, ctrl->value); + case V4L2_CID_COLORFX: + return sensor_s_colorfx(sd, + (enum v4l2_colorfx) ctrl->value); + case V4L2_CID_CAMERA_FLASH_MODE: + return sensor_s_flash_mode(sd, + (enum v4l2_flash_mode) ctrl->value); + } + return -EINVAL; +} + + +static int sensor_g_chip_ident(struct v4l2_subdev *sd, + struct v4l2_dbg_chip_ident *chip) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + + return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_SENSOR, 0); +} + + +/* ----------------------------------------------------------------------- */ + +static const struct v4l2_subdev_core_ops sensor_core_ops = { + .g_chip_ident = sensor_g_chip_ident, + .g_ctrl = sensor_g_ctrl, + .s_ctrl = sensor_s_ctrl, + .queryctrl = sensor_queryctrl, + .reset = sensor_reset, + .init = sensor_init, + .s_power = sensor_power, + .ioctl = sensor_ioctl, +}; + +static const struct v4l2_subdev_video_ops sensor_video_ops = { + .enum_mbus_fmt = sensor_enum_fmt,//linux-3.0 + .try_mbus_fmt = sensor_try_fmt,//linux-3.0 + .s_mbus_fmt = sensor_s_fmt,//linux-3.0 + .s_parm = sensor_s_parm,//linux-3.0 + .g_parm = sensor_g_parm,//linux-3.0 +}; + +static const struct v4l2_subdev_ops sensor_ops = { + .core = &sensor_core_ops, + .video = &sensor_video_ops, +}; + +/* ----------------------------------------------------------------------- */ + +static int sensor_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct v4l2_subdev *sd; + struct sensor_info *info; +// int ret; + + info = kzalloc(sizeof(struct sensor_info), GFP_KERNEL); + if (info == NULL) + return -ENOMEM; + sd = &info->sd; + v4l2_i2c_subdev_init(sd, client, &sensor_ops); + + info->fmt = &sensor_formats[0]; + info->ccm_info = &ccm_info_con; + + info->brightness = 0; + info->contrast = 0; + info->saturation = 0; + info->hue = 0; + info->hflip = 0; + info->vflip = 0; + info->gain = 0; + info->autogain = 1; + info->exp = 0; + info->autoexp = 0; + info->autowb = 1; + info->wb = 0; + info->clrfx = 0; +// info->clkrc = 1; /* 30fps */ + + return 0; +} + + +static int sensor_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + + v4l2_device_unregister_subdev(sd); + kfree(to_state(sd)); + return 0; +} + +static const struct i2c_device_id sensor_id[] = { + { "gc2035", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, sensor_id); + +//linux-3.0 +static struct i2c_driver sensor_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "gc2035", + }, + .probe = sensor_probe, + .remove = sensor_remove, + .id_table = sensor_id, +}; +static __init int init_sensor(void) +{ + return i2c_add_driver(&sensor_driver); +} + +static __exit void exit_sensor(void) +{ + i2c_del_driver(&sensor_driver); +} + +module_init(init_sensor); +module_exit(exit_sensor); diff --git a/patch/linux-sunxi/drivers/net/ethernet/allwinner/gmac/gmac_core.c b/patch/linux-sunxi/drivers/net/ethernet/allwinner/gmac/gmac_core.c new file mode 100644 index 0000000..43937ca --- /dev/null +++ b/patch/linux-sunxi/drivers/net/ethernet/allwinner/gmac/gmac_core.c @@ -0,0 +1,1740 @@ +/******************************************************************************* + * Copyright © 2012, Shuge + * Author: shuge + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. + ********************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_GMAC_DEBUG_FS +#include +#include +#endif + +#include "sunxi_gmac.h" +#include "gmac_desc.h" +#include "gmac_ethtool.h" + +#undef GMAC_DEBUG +#ifdef GMAC_DEBUG +#define DBG(nlevel, klevel, fmt, args...) \ + ((void)(netif_msg_##nlevel(priv) && \ + printk(KERN_##klevel fmt, ## args))) +#else +#define DBG(nlevel, klevel, fmt, args...) do { } while (0) +#endif + +#undef RX_DEBUG +/*#define RX_DEBUG*/ +#ifdef RX_DEBUG +#define RX_DBG(fmt, args...) printk(fmt, ## args) +#else +#define RX_DBG(fmt, args...) do { } while (0) +#endif + +#undef XMIT_DEBUG +/*#define XMIT_DEBUG*/ +#ifdef XMIT_DEBUG +#define TX_DBG(fmt, args...) printk(fmt, ## args) +#else +#define TX_DBG(fmt, args...) do { } while (0) +#endif + +#define GMAC_ALIGN(x) L1_CACHE_ALIGN(x) +#define JUMBO_LEN 9000 + +#define GMAC_MAC_ADDRESS "00:00:00:00:00:00" +static char *mac_str = GMAC_MAC_ADDRESS; +module_param(mac_str, charp, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(mac_str, "MAC Address String.(xx:xx:xx:xx:xx:xx)"); + +#define TX_TIMEO 5000 +static int watchdog = TX_TIMEO; +module_param(watchdog, int, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds"); + +static int debug = -1; /* -1: default, 0: no output, 16: all */ +module_param(debug, int, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)"); + +static int phyaddr = -1; +module_param(phyaddr, int, S_IRUGO); +MODULE_PARM_DESC(phyaddr, "Physical device address"); + +#define DMA_TX_SIZE 256 +static int dma_txsize = DMA_TX_SIZE; +module_param(dma_txsize, int, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); + +#define DMA_RX_SIZE 256 +static int dma_rxsize = DMA_RX_SIZE; +module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); + +static int flow_ctrl = FLOW_OFF; +module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); + +static int pause = PAUSE_TIME; +module_param(pause, int, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(pause, "Flow Control Pause Time"); + +#define TC_DEFAULT 64 +static int tc = TC_DEFAULT; +module_param(tc, int, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(tc, "DMA threshold control value"); + +/* Pay attention to tune this parameter; take care of both + * hardware capability and network stabitily/performance impact. + * Many tests showed that ~4ms latency seems to be good enough. */ +#ifdef CONFIG_GMAC_TIMER +#define DEFAULT_PERIODIC_RATE 256 +static int tmrate = DEFAULT_PERIODIC_RATE; +module_param(tmrate, int, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)"); +#endif + +#define DMA_BUFFER_SIZE BUF_SIZE_2KiB +static int buf_sz = DMA_BUFFER_SIZE; +module_param(buf_sz, int, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(buf_sz, "DMA buffer size"); + +static int gmac_used; + +static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | + NETIF_MSG_LINK | NETIF_MSG_IFUP | + NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); + +static irqreturn_t gmac_interrupt(int irq, void *dev_id); + +#ifdef CONFIG_GMAC_DEBUG_FS +static int gmac_init_fs(struct net_device *dev); +static void gmac_exit_fs(void); +#endif + +#if defined(XMIT_DEBUG) || defined(RX_DEBUG) +static void print_pkt(unsigned char *buf, int len) +{ + int j; + printk("len = %d byte, buf addr: 0x%p", len, buf); + for (j = 0; j < len; j++) { + if ((j % 16) == 0) + printk("\n %03x:", j); + printk(" %02x", buf[j]); + } + printk("\n"); +} +#endif + +/* minimum number of free TX descriptors required to wake up TX process */ +#define GMAC_TX_THRESH(x) (x->dma_tx_size/4) + +static inline u32 gmac_tx_avail(struct gmac_priv *priv) +{ + return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; +} + +/** + * gmac_clk_ctl + * @flag: 0--disable, 1--enable. + * Description: enable and disable gmac clk. + */ +static void gmac_clk_ctl(struct gmac_priv *priv, unsigned int flag) +{ + int phy_interface = priv->plat->phy_interface; + u32 priv_clk_reg; + +#ifndef CONFIG_GMAC_CLK_SYS + int reg_value; + reg_value = readl(priv->clkbase + AHB1_GATING); + flag ? (reg_value |= GMAC_AHB_BIT) : (reg_value &= ~GMAC_AHB_BIT); + writel(reg_value, priv->clkbase + AHB1_GATING); +/* + reg_value = readl(priv->clkbase + AHB1_MOD_RESET); + flag ? (reg_value |= GMAC_RESET_BIT) : (reg_value &= ~GMAC_RESET_BIT); + writel(reg_value, priv->clkbase + AHB1_MOD_RESET); +*/ +#else + if (flag) { + clk_enable(priv->gmac_ahb_clk); + /* + clk_reset(priv->gmac_mod_clk, AW_CCU_CLK_NRESET); + */ + } else { + clk_disable(priv->gmac_ahb_clk); + /* + clk_reset(priv->gmac_mod_clk, AW_CCU_CLK_RESET); + */ + } +#endif + + /* We should set the interface type. */ + priv_clk_reg = readl(priv->gmac_clk_reg + GMAC_CLK_REG); + + if (phy_interface == PHY_INTERFACE_MODE_RGMII) + priv_clk_reg |= 0x00000004; + else + priv_clk_reg &= (~0x00000004); + + /* Set gmac transmit clock source. */ + priv_clk_reg &= (~0x00000003); + if (phy_interface == PHY_INTERFACE_MODE_RGMII + || phy_interface == PHY_INTERFACE_MODE_GMII) + priv_clk_reg |= 0x00000002; + + priv_clk_reg |= (0x00000003<<10); + + writel(priv_clk_reg, priv->gmac_clk_reg + GMAC_CLK_REG); +} + +/** + * gmac_adjust_link + * @dev: net device structure + * Description: it adjusts the link parameters. + */ +static void gmac_adjust_link(struct net_device *ndev) +{ + struct gmac_priv *priv = netdev_priv(ndev); + struct phy_device *phydev = ndev->phydev; + unsigned long flags; + int new_state = 0; + unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; + + if (phydev == NULL) + return; + + DBG(probe, DEBUG, "gmac_adjust_link: called. address %d link %d\n", + phydev->addr, phydev->link); + + spin_lock_irqsave(&priv->lock, flags); + if (phydev->link) { + u32 ctrl = readl(priv->ioaddr + GMAC_CONTROL); + + /* Now we make sure that we can be in full duplex mode. + * If not, we operate in half-duplex mode. */ + if (phydev->duplex != priv->oldduplex) { + new_state = 1; + if (!(phydev->duplex)) + ctrl &= ~GMAC_CTL_DM; + else + ctrl |= GMAC_CTL_DM; + priv->oldduplex = phydev->duplex; + } + /* Flow Control operation */ + if (phydev->pause) + core_flow_ctrl(priv->ioaddr, phydev->duplex, + fc, pause_time); + + if (phydev->speed != priv->speed) { + new_state = 1; + switch (phydev->speed) { + case 1000: + ctrl &= ~GMAC_CTL_PS; + break; + case 100: + case 10: + ctrl |= GMAC_CTL_PS; + if (phydev->speed == SPEED_100) + ctrl |= GMAC_CTL_FES; + else + ctrl &= ~GMAC_CTL_FES; + break; + default: + if (netif_msg_link(priv)) + pr_warning("%s: Speed (%d) is not 10" + " or 100!\n", ndev->name, phydev->speed); + break; + } + + priv->speed = phydev->speed; + } + + writel(ctrl, priv->ioaddr + GMAC_CONTROL); + + if (!priv->oldlink) { + new_state = 1; + priv->oldlink = 1; + } + } else if (priv->oldlink) { + new_state = 1; + priv->oldlink = 0; + priv->speed = 0; + priv->oldduplex = -1; + } + + if (new_state && netif_msg_link(priv)) + phy_print_status(phydev); + + spin_unlock_irqrestore(&priv->lock, flags); + + DBG(probe, DEBUG, "gmac_adjust_link: exiting\n"); +} + +/** + * gmac_init_phy - PHY initialization + * @dev: net device structure + * Description: it initializes the driver's PHY state, and attaches the PHY + * to the mac driver. + * Return value: + * 0 on success + */ +static int gmac_init_phy(struct net_device *ndev) +{ + struct gmac_priv *priv = netdev_priv(ndev); + struct phy_device *phydev; + char phy_id[MII_BUS_ID_SIZE + 3]; + char bus_id[MII_BUS_ID_SIZE]; + int phy_interface = priv->plat->phy_interface; + + /* Initialize the information of phy state. */ + priv->oldlink = 0; + priv->speed = 0; + priv->oldduplex = -1; + + snprintf(bus_id, MII_BUS_ID_SIZE, "sunxi_gmac-%x", priv->plat->bus_id); + snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, + priv->plat->phy_addr); + pr_debug("gmac_init_phy: trying to attach to %s\n", phy_id); + + phydev = phy_connect(ndev, phy_id, &gmac_adjust_link, 0, phy_interface); + + if (IS_ERR(phydev)) { + pr_err("%s: Could not attach to PHY\n", ndev->name); + return PTR_ERR(phydev); + } + + /* Stop Advertising 1000BASE Capability if interface is not GMII */ + if ((phy_interface == PHY_INTERFACE_MODE_MII) || + (phy_interface == PHY_INTERFACE_MODE_RMII)) + phydev->advertising &= ~(SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full); + + /* + * Broken HW is sometimes missing the pull-up resistor on the + * MDIO line, which results in reads to non-existent devices returning + * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent + * device as well. + * Note: phydev->phy_id is the result of reading the UID PHY registers. + */ + if (phydev->phy_id == 0) { + phy_disconnect(phydev); + return -ENODEV; + } + pr_debug("gmac_init_phy: %s: attached to PHY (UID 0x%x)" + " Link = %d\n", ndev->name, phydev->phy_id, phydev->link); + + return 0; +} + +/** + * display_ring + * @p: pointer to the ring. + * @size: size of the ring. + * Description: display all the descriptors within the ring. + */ +static void display_ring(dma_desc_t *p, int size) +{ + struct tmp_s { + u64 a; + unsigned int b; + unsigned int c; + }; + int i; + for (i = 0; i < size; i++) { + struct tmp_s *x = (struct tmp_s *)(p + i); + pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", + i, (unsigned int)virt_to_phys(&p[i]), + (unsigned int)(x->a), (unsigned int)((x->a) >> 32), + x->b, x->c); + pr_info("\n"); + } +} + +static int gmac_set_bfsize(int mtu, int bufsize) +{ + int ret = bufsize; + + if (mtu >= BUF_SIZE_4KiB) + ret = BUF_SIZE_8KiB; + else if (mtu >= BUF_SIZE_2KiB) + ret = BUF_SIZE_4KiB; + else if (mtu >= DMA_BUFFER_SIZE) + ret = BUF_SIZE_2KiB; + else + ret = DMA_BUFFER_SIZE; + + return ret; +} + +/** + * init_dma_desc_rings - init the RX/TX descriptor rings + * @dev: net device structure + * Description: this function initializes the DMA RX/TX descriptors + * and allocates the socket buffers. It suppors the chained and ring + * modes. + */ +static void init_dma_desc_rings(struct net_device *ndev) +{ + int i; + struct gmac_priv *priv = netdev_priv(ndev); + struct sk_buff *skb; + unsigned int txsize = priv->dma_tx_size; + unsigned int rxsize = priv->dma_rx_size; + unsigned int bfsize; + int dis_ic = 0; + int des3_as_data_buf = 0; + + /* Set the max buffer size according to the DESC mode + * and the MTU. Note that RING mode allows 16KiB bsize. */ + bfsize = gmac_set_16kib_bfsize(ndev->mtu); + + if (bfsize == BUF_SIZE_16KiB) + des3_as_data_buf = 1; + else + bfsize = gmac_set_bfsize(ndev->mtu, priv->dma_buf_sz); + +#ifdef CONFIG_GMAC_TIMER + /* Disable interrupts on completion for the reception if timer is on */ + if (likely(priv->tm->enable)) + dis_ic = 1; +#endif + + DBG(probe, INFO, "gmac: txsize %d, rxsize %d, bfsize %d\n", + txsize, rxsize, bfsize); + + priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL); + priv->rx_skbuff = kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL); + priv->dma_rx = + (dma_desc_t *)dma_alloc_coherent(NULL, + rxsize * sizeof(dma_desc_t), + &priv->dma_rx_phy, + GFP_KERNEL); + + priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize, + GFP_KERNEL); + priv->dma_tx = + (dma_desc_t *)dma_alloc_coherent(NULL, + txsize * sizeof(dma_desc_t), + &priv->dma_tx_phy, + GFP_KERNEL); + + if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) { + pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__); + return; + } + + DBG(probe, INFO, "gmac (%s) DMA desc: virt addr (Rx %p, " + "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n", + ndev->name, priv->dma_rx, priv->dma_tx, + (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy); + + /* RX INITIALIZATION */ + DBG(probe, INFO, "gmac: SKB addresses:\n" + "skb\t\tskb data\tdma data\n"); + + for (i = 0; i < rxsize; i++) { + dma_desc_t *p = priv->dma_rx + i; + + skb = __netdev_alloc_skb(ndev, bfsize + NET_IP_ALIGN, + GFP_KERNEL); + if (unlikely(skb == NULL)) { + pr_err("%s: Rx init fails; skb is NULL\n", __func__); + break; + } + skb_reserve(skb, NET_IP_ALIGN); + priv->rx_skbuff[i] = skb; + priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, + bfsize, DMA_FROM_DEVICE); + + p->desc2 = priv->rx_skbuff_dma[i]; + + gmac_init_desc3(des3_as_data_buf, p); + + DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], + priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]); + } + priv->cur_rx = 0; + priv->dirty_rx = (unsigned int)(i - rxsize); + priv->dma_buf_sz = bfsize; + buf_sz = bfsize; + + /* TX INITIALIZATION */ + for (i = 0; i < txsize; i++) { + priv->tx_skbuff[i] = NULL; + priv->dma_tx[i].desc2 = 0; + } + + /* In case of Chained mode this sets the des3 to the next + * element in the chain */ + gmac_init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize); + gmac_init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize); + + priv->dirty_tx = 0; + priv->cur_tx = 0; + + /* Clear the Rx/Tx descriptors */ + desc_init_rx(priv->dma_rx, rxsize, dis_ic); + desc_init_tx(priv->dma_tx, txsize); + + if (netif_msg_hw(priv)) { + printk("RX descriptor ring:\n"); + display_ring(priv->dma_rx, rxsize); + printk("TX descriptor ring:\n"); + display_ring(priv->dma_tx, txsize); + } +} + +static void dma_free_rx_skbufs(struct gmac_priv *priv) +{ + int i; + + for (i = 0; i < priv->dma_rx_size; i++) { + if (priv->rx_skbuff[i]) { + dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], + priv->dma_buf_sz, DMA_FROM_DEVICE); + dev_kfree_skb_any(priv->rx_skbuff[i]); + } + priv->rx_skbuff[i] = NULL; + } +} + +static void dma_free_tx_skbufs(struct gmac_priv *priv) +{ + int i; + + for (i = 0; i < priv->dma_tx_size; i++) { + if (priv->tx_skbuff[i] != NULL) { + dma_desc_t *p = priv->dma_tx + i; + if (p->desc2) + dma_unmap_single(priv->device, p->desc2, + desc_get_tx_len(p), + DMA_TO_DEVICE); + dev_kfree_skb_any(priv->tx_skbuff[i]); + priv->tx_skbuff[i] = NULL; + } + } +} + +static void free_dma_desc_resources(struct gmac_priv *priv) +{ + /* Release the DMA TX/RX socket buffers */ + dma_free_rx_skbufs(priv); + dma_free_tx_skbufs(priv); + + /* Free the region of consistent memory previously allocated for + * the DMA */ + dma_free_coherent(NULL, + priv->dma_tx_size * sizeof(dma_desc_t), + priv->dma_tx, priv->dma_tx_phy); + dma_free_coherent(NULL, + priv->dma_rx_size * sizeof(dma_desc_t), + priv->dma_rx, priv->dma_rx_phy); + kfree(priv->rx_skbuff_dma); + kfree(priv->rx_skbuff); + kfree(priv->tx_skbuff); +} + +/** + * gmac_dma_operation_mode - HW DMA operation mode + * @priv : pointer to the private device structure. + * Description: it sets the DMA operation mode: tx/rx DMA thresholds + * or Store-And-Forward capability. + */ +static void gmac_dma_operation_mode(struct gmac_priv *priv) +{ + if (likely(priv->plat->force_sf_dma_mode || + ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) { + /* + * In case of GMAC, SF mode can be enabled + * to perform the TX COE in HW. This depends on: + * 1) TX COE if actually supported + * 2) There is no bugged Jumbo frame support + * that needs to not insert csum in the TDES. + */ + dma_oper_mode(priv->ioaddr, + SF_DMA_MODE, SF_DMA_MODE); + tc = SF_DMA_MODE; + } else + dma_oper_mode(priv->ioaddr, tc, SF_DMA_MODE); +} + +/** + * gmac_tx: + * @priv: private driver structure + * Description: it reclaims resources after transmission completes. + */ +static void gmac_tx(struct gmac_priv *priv) +{ + unsigned int txsize = priv->dma_tx_size; + + spin_lock(&priv->tx_lock); + + while (priv->dirty_tx != priv->cur_tx) { + int last; + unsigned int entry = priv->dirty_tx % txsize; + struct sk_buff *skb = priv->tx_skbuff[entry]; + dma_desc_t *p = priv->dma_tx + entry; + + /* Check if the descriptor is owned by the DMA. */ + if (desc_get_tx_own(p)) + break; + + /* Verify tx error by looking at the last segment */ + last = desc_get_tx_ls(p); + if (likely(last)) { + int tx_error = + desc_get_tx_status(&priv->ndev->stats, + &priv->xstats, p, + priv->ioaddr); + if (likely(tx_error == 0)) { + priv->ndev->stats.tx_packets++; + priv->xstats.tx_pkt_n++; + } else + priv->ndev->stats.tx_errors++; + } + TX_DBG("%s: curr %d, dirty %d\n", __func__, + priv->cur_tx, priv->dirty_tx); + + if (likely(p->desc2)) + dma_unmap_single(priv->device, p->desc2, + desc_get_tx_len(p), + DMA_TO_DEVICE); + gmac_clean_desc3(p); + + if (likely(skb != NULL)) { + /* + * If there's room in the queue (limit it to size) + * we add this skb back into the pool, + * if it's the right size. + */ + if ((skb_queue_len(&priv->rx_recycle) < + priv->dma_rx_size) && + skb_recycle_check(skb, priv->dma_buf_sz)) + __skb_queue_head(&priv->rx_recycle, skb); + else + dev_kfree_skb(skb); + + priv->tx_skbuff[entry] = NULL; + } + + desc_release_tx(p); + + entry = (++priv->dirty_tx) % txsize; + } + if (unlikely(netif_queue_stopped(priv->ndev) && + gmac_tx_avail(priv) > GMAC_TX_THRESH(priv))) { + netif_tx_lock(priv->ndev); + if (netif_queue_stopped(priv->ndev) && + gmac_tx_avail(priv) > GMAC_TX_THRESH(priv)) { + TX_DBG("%s: restart transmit\n", __func__); + netif_wake_queue(priv->ndev); + } + netif_tx_unlock(priv->ndev); + } + spin_unlock(&priv->tx_lock); +} + +static inline void gmac_enable_irq(struct gmac_priv *priv) +{ +#ifdef CONFIG_GMAC_TIMER + if (likely(priv->tm->enable)) + priv->tm->timer_start(tmrate); + else +#endif + dma_en_irq(priv->ioaddr); +} + +static inline void gmac_disable_irq(struct gmac_priv *priv) +{ +#ifdef CONFIG_GMAC_TIMER + if (likely(priv->tm->enable)) + priv->tm->timer_stop(); + else +#endif + dma_dis_irq(priv->ioaddr); +} + +static int gmac_has_work(struct gmac_priv *priv) +{ + unsigned int has_work = 0; + int rxret, tx_work = 0; + + rxret = desc_get_rx_own(priv->dma_rx + (priv->cur_rx % priv->dma_rx_size)); + + if (priv->dirty_tx != priv->cur_tx) + tx_work = 1; + + if (likely(!rxret || tx_work)) + has_work = 1; + + return has_work; +} + +static inline void _gmac_schedule(struct gmac_priv *priv) +{ + if (likely(gmac_has_work(priv))) { + gmac_disable_irq(priv); + napi_schedule(&priv->napi); + } +} + +#ifdef CONFIG_GMAC_TIMER +void gmac_schedule(struct net_device *dev) +{ + struct gmac_priv *priv = netdev_priv(dev); + + priv->xstats.sched_timer_n++; + + _gmac_schedule(priv); +} + +static void gmac_no_timer_started(unsigned int x) +{; +}; + +static void gmac_no_timer_stopped(void) +{; +}; +#endif + +/** + * gmac_tx_err: + * @priv: pointer to the private device structure + * Description: it cleans the descriptors and restarts the transmission + * in case of errors. + */ +static void gmac_tx_err(struct gmac_priv *priv) +{ + netif_stop_queue(priv->ndev); + + dma_stop_tx(priv->ioaddr); + dma_free_tx_skbufs(priv); + desc_init_tx(priv->dma_tx, priv->dma_tx_size); + priv->dirty_tx = 0; + priv->cur_tx = 0; + dma_start_tx(priv->ioaddr); + + priv->ndev->stats.tx_errors++; + netif_wake_queue(priv->ndev); +} + + +static void gmac_dma_interrupt(struct gmac_priv *priv) +{ + int status; + + status = dma_interrupt(priv->ioaddr, &priv->xstats); + if (likely(status == handle_tx_rx)) + _gmac_schedule(priv); + + else if (unlikely(status == tx_hard_error_bump_tc)) { + /* Try to bump up the dma threshold on this failure */ + if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { + tc += 64; + dma_oper_mode(priv->ioaddr, tc, SF_DMA_MODE); + priv->xstats.threshold = tc; + } + } else if (unlikely(status == tx_hard_error)) + gmac_tx_err(priv); +} + +static void gmac_check_ether_addr(struct gmac_priv *priv) +{ + int i; + char *p = mac_str; + /* verify if the MAC address is valid, in case of failures it + * generates a random MAC address */ + if (!is_valid_ether_addr(priv->ndev->dev_addr)) { + if (!is_valid_ether_addr(priv->ndev->dev_addr)) { + for (i=0; i<6; i++,p++) + priv->ndev->dev_addr[i] = simple_strtoul(p, &p, 16); + } + + if (!is_valid_ether_addr(priv->ndev->dev_addr)) + random_ether_addr(priv->ndev->dev_addr); + } + printk(KERN_WARNING "%s: device MAC address %pM\n", priv->ndev->name, + priv->ndev->dev_addr); +} + +/** + * gmac_open - open entry point of the driver + * @dev : pointer to the device structure. + * Description: + * This function is the open entry point of the driver. + * Return value: + * 0 on success and an appropriate (-)ve integer as defined in errno.h + * file on failure. + */ +static int gmac_open(struct net_device *ndev) +{ + struct gmac_priv *priv = netdev_priv(ndev); + int ret; + + gmac_clk_ctl(priv, 1); + //gmac_check_ether_addr(priv); + + /* MDIO bus Registration */ + ret = gmac_mdio_register(ndev); + if (ret < 0) { + pr_debug("%s: MDIO bus (id: %d) registration failed", + __func__, priv->plat->bus_id); + goto out_err; + } + + ret = gmac_init_phy(ndev); + if (unlikely(ret)) { + pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret); + goto out_err; + } + + /* Create and initialize the TX/RX descriptors chains. */ + priv->dma_tx_size = GMAC_ALIGN(dma_txsize); + priv->dma_rx_size = GMAC_ALIGN(dma_rxsize); + priv->dma_buf_sz = GMAC_ALIGN(buf_sz); + init_dma_desc_rings(ndev); + + /* DMA initialization and SW reset */ + ret = gdma_init(priv->ioaddr, priv->plat->pbl, + priv->dma_tx_phy, priv->dma_rx_phy); + if (ret < 0) { + pr_err("%s: DMA initialization failed\n", __func__); + goto open_error; + } + + /* Copy the MAC addr into the HW */ + gmac_set_umac_addr(priv->ioaddr, ndev->dev_addr, 0); + + /* Initialize the MAC Core */ + core_init(priv->ioaddr); + + /* Request the IRQ lines */ + ret = request_irq(ndev->irq, gmac_interrupt, + IRQF_SHARED, ndev->name, ndev); + if (unlikely(ret < 0)) { + pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", + __func__, ndev->irq, ret); + goto open_error; + } + + /* Enable the MAC Rx/Tx */ + gmac_set_tx_rx(priv->ioaddr, true); + + /* Set the HW DMA mode and the COE */ + gmac_dma_operation_mode(priv); + + /* Extra statistics */ + memset(&priv->xstats, 0, sizeof(struct gmac_extra_stats)); + priv->xstats.threshold = tc; + +#ifdef CONFIG_GMAC_DEBUG_FS + ret = gmac_init_fs(ndev); + if (ret < 0) + pr_warning("%s: failed debugFS registration\n", __func__); +#endif + /* Start the ball rolling... */ + DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", ndev->name); + dma_start_tx(priv->ioaddr); + dma_start_rx(priv->ioaddr); + + /* Dump DMA/MAC registers */ + if (netif_msg_hw(priv)) { + core_dump_regs(priv->ioaddr); + dma_dump_regs(priv->ioaddr); + } + + if (ndev->phydev) + phy_start(ndev->phydev); + + napi_enable(&priv->napi); + skb_queue_head_init(&priv->rx_recycle); + netif_start_queue(ndev); + + return 0; + +open_error: + if (ndev->phydev) + phy_disconnect(ndev->phydev); + free_dma_desc_resources(priv); +out_err: + gmac_clk_ctl(priv, 0); + + return ret; +} + +/** + * gmac_release - close entry point of the driver + * @dev : device pointer. + * Description: + * This is the stop entry point of the driver. + */ +static int gmac_release(struct net_device *ndev) +{ + struct gmac_priv *priv = netdev_priv(ndev); + + /* Stop and disconnect the PHY */ + if (ndev->phydev) { + phy_stop(ndev->phydev); + phy_disconnect(ndev->phydev); + ndev->phydev = NULL; + } + + netif_stop_queue(ndev); + +#ifdef CONFIG_GMAC_TIMER + /* Stop and release the timer */ + gmac_close_ext_timer(); + if (priv->tm != NULL) + kfree(priv->tm); +#endif + napi_disable(&priv->napi); + skb_queue_purge(&priv->rx_recycle); + + /* Free the IRQ lines */ + free_irq(ndev->irq, ndev); + + /* Stop TX/RX DMA and clear the descriptors */ + dma_stop_tx(priv->ioaddr); + dma_stop_rx(priv->ioaddr); + + /* Release and free the Rx/Tx resources */ + free_dma_desc_resources(priv); + + /* Disable the MAC Rx/Tx */ + gmac_set_tx_rx(priv->ioaddr, false); + + netif_carrier_off(ndev); + +#ifdef CONFIG_GMAC_DEBUG_FS + gmac_exit_fs(); +#endif + gmac_mdio_unregister(ndev); + gmac_clk_ctl(priv, 0); + + return 0; +} + +/** + * gmac_xmit: + * @skb : the socket buffer + * @dev : device pointer + * Description : Tx entry point of the driver. + */ +static netdev_tx_t gmac_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct gmac_priv *priv = netdev_priv(dev); + unsigned int txsize = priv->dma_tx_size; + unsigned int entry; + int i, csum_insertion = 0; + int nfrags = skb_shinfo(skb)->nr_frags; + dma_desc_t *desc, *first; + unsigned int nopaged_len = skb_headlen(skb); + + if (unlikely(gmac_tx_avail(priv) < nfrags + 1)) { + if (!netif_queue_stopped(dev)) { + netif_stop_queue(dev); + /* This is a hard error, log it. */ + pr_err("%s: BUG! Tx Ring full when queue awake\n", + __func__); + } + return NETDEV_TX_BUSY; + } + + spin_lock(&priv->tx_lock); + + entry = priv->cur_tx % txsize; + +#ifdef XMIT_DEBUG + if ((skb->len > ETH_FRAME_LEN) || nfrags) + pr_info("gmac xmit:\n" + "\tskb addr %p - len: %d - nopaged_len: %d\n" + "\tn_frags: %d - ip_summed: %d - %s gso\n", + skb, skb->len, nopaged_len, nfrags, skb->ip_summed, + !skb_is_gso(skb) ? "isn't" : "is"); +#endif + + csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); + + desc = priv->dma_tx + entry; + first = desc; + +#ifdef XMIT_DEBUG + if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN)) + pr_debug("gmac xmit: skb len: %d, nopaged_len: %d,\n" + "\t\tn_frags: %d, ip_summed: %d\n", + skb->len, nopaged_len, nfrags, skb->ip_summed); +#endif + + priv->tx_skbuff[entry] = skb; + + if (gmac_is_jumbo_frm(skb->len)) { + entry = gmac_jumbo_frm(priv, skb, csum_insertion); + desc = priv->dma_tx + entry; + } else { + desc->desc2 = dma_map_single(priv->device, skb->data, + nopaged_len, DMA_TO_DEVICE); + desc_prepare_tx(desc, 1, nopaged_len, csum_insertion); + } + + for (i = 0; i < nfrags; i++) { + const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; + int len = skb_frag_size(frag); + + entry = (++priv->cur_tx) % txsize; + desc = priv->dma_tx + entry; + + TX_DBG("\t[entry %d] segment len: %d\n", entry, len); + desc->desc2 = skb_frag_dma_map(priv->device, frag, 0, + len, DMA_TO_DEVICE); + priv->tx_skbuff[entry] = NULL; + desc_prepare_tx(desc, 0, len, csum_insertion); + wmb(); + desc_set_tx_own(desc); + } + + /* Interrupt on completition only for the latest segment */ + desc_close_tx(desc); + +#ifdef CONFIG_GMAC_TIMER + /* Clean IC while using timer */ + if (likely(priv->tm->enable)) + desc_clear_tx_ic(desc); +#endif + + wmb(); + + /* To avoid raise condition */ + desc_set_tx_own(first); + + priv->cur_tx++; + +#ifdef XMIT_DEBUG + if (netif_msg_pktdata(priv)) { + pr_info("gmac xmit: current=%d, dirty=%d, entry=%d, " + "first=%p, nfrags=%d\n", + (priv->cur_tx % txsize), (priv->dirty_tx % txsize), + entry, first, nfrags); + display_ring(priv->dma_tx, txsize); + pr_info(">>> frame to be transmitted: "); + print_pkt(skb->data, skb->len); + } +#endif + + if (unlikely(gmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { + TX_DBG("%s: stop transmitted packets\n", __func__); + netif_stop_queue(dev); + } + + dev->stats.tx_bytes += skb->len; + + skb_tx_timestamp(skb); + + dma_en_tx(priv->ioaddr); + + spin_unlock(&priv->tx_lock); + + return NETDEV_TX_OK; +} + +static inline void gmac_rx_refill(struct gmac_priv *priv) +{ + unsigned int rxsize = priv->dma_rx_size; + int bfsize = priv->dma_buf_sz; + dma_desc_t *p = priv->dma_rx; + + for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { + unsigned int entry = priv->dirty_rx % rxsize; + if (likely(priv->rx_skbuff[entry] == NULL)) { + struct sk_buff *skb; + + skb = __skb_dequeue(&priv->rx_recycle); + if (skb == NULL) + skb = netdev_alloc_skb_ip_align(priv->ndev, + bfsize); + + if (unlikely(skb == NULL)) + break; + + priv->rx_skbuff[entry] = skb; + priv->rx_skbuff_dma[entry] = + dma_map_single(priv->device, skb->data, bfsize, + DMA_FROM_DEVICE); + + (p + entry)->desc2 = priv->rx_skbuff_dma[entry]; + + gmac_refill_desc3(bfsize, p + entry); + + RX_DBG(KERN_INFO "\trefill entry #%d\n", entry); + } + wmb(); + desc_set_rx_own(p + entry); + } +} + +static int gmac_rx(struct gmac_priv *priv, int limit) +{ + unsigned int rxsize = priv->dma_rx_size; + unsigned int entry = priv->cur_rx % rxsize; + unsigned int next_entry; + unsigned int count = 0; + dma_desc_t *p = priv->dma_rx + entry; + dma_desc_t *p_next; + +#ifdef RX_DEBUG + if (netif_msg_hw(priv)) { + pr_debug(">>> gmac_rx: descriptor ring:\n"); + display_ring(priv->dma_rx, rxsize); + } +#endif + + count = 0; + while (!desc_get_rx_own(p)) { + int status; + + if (count >= limit) + break; + + count++; + + next_entry = (++priv->cur_rx) % rxsize; + p_next = priv->dma_rx + next_entry; + prefetch(p_next); + + /* read the status of the incoming frame */ + status = (desc_get_rx_status(&priv->ndev->stats, + &priv->xstats, p)); + if (unlikely(status == discard_frame)) + priv->ndev->stats.rx_errors++; + else { + struct sk_buff *skb; + int frame_len; + + frame_len = desc_get_rx_frame_len(p); + /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 + * Type frames (LLC/LLC-SNAP) */ + if (unlikely(status != llc_snap)) + frame_len -= ETH_FCS_LEN; +#ifdef RX_DEBUG + if (frame_len > ETH_FRAME_LEN) + pr_debug("\tRX frame size %d, COE status: %d\n", + frame_len, status); + + if (netif_msg_hw(priv)) + pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", + p, entry, p->desc2); +#endif + skb = priv->rx_skbuff[entry]; + if (unlikely(!skb)) { + pr_err("%s: Inconsistent Rx descriptor chain\n", + priv->ndev->name); + priv->ndev->stats.rx_dropped++; + break; + } + prefetch(skb->data - NET_IP_ALIGN); + priv->rx_skbuff[entry] = NULL; + + skb_put(skb, frame_len); + dma_unmap_single(priv->device, + priv->rx_skbuff_dma[entry], + priv->dma_buf_sz, DMA_FROM_DEVICE); +#ifdef RX_DEBUG + if (netif_msg_pktdata(priv)) { + pr_info(" frame received (%dbytes)", frame_len); + print_pkt(skb->data, frame_len); + } +#endif + skb->protocol = eth_type_trans(skb, priv->ndev); + + if (unlikely(!priv->rx_coe)) { + /* No RX COE for old mac10/100 devices */ + skb_checksum_none_assert(skb); + netif_receive_skb(skb); + } else { + skb->ip_summed = CHECKSUM_UNNECESSARY; + napi_gro_receive(&priv->napi, skb); + } + + priv->ndev->stats.rx_packets++; + priv->ndev->stats.rx_bytes += frame_len; + } + entry = next_entry; + p = p_next; /* use prefetched values */ + } + + gmac_rx_refill(priv); + + priv->xstats.rx_pkt_n += count; + + return count; +} + +/** + * gmac_poll - gmac poll method (NAPI) + * @napi : pointer to the napi structure. + * @budget : maximum number of packets that the current CPU can receive from + * all interfaces. + * Description : + * This function implements the the reception process. + * Also it runs the TX completion thread + */ +static int gmac_poll(struct napi_struct *napi, int budget) +{ + struct gmac_priv *priv = container_of(napi, struct gmac_priv, napi); + int work_done = 0; + + priv->xstats.poll_n++; + gmac_tx(priv); + work_done = gmac_rx(priv, budget); + + if (work_done < budget) { + napi_complete(napi); + gmac_enable_irq(priv); + } + return work_done; +} + +/** + * gmac_tx_timeout + * @dev : Pointer to net device structure + * Description: this function is called when a packet transmission fails to + * complete within a reasonable tmrate. The driver will mark the error in the + * netdev structure and arrange for the device to be reset to a sane state + * in order to transmit a new packet. + */ +static void gmac_tx_timeout(struct net_device *ndev) +{ + struct gmac_priv *priv = netdev_priv(ndev); + + /* Clear Tx resources and restart transmitting again */ + gmac_tx_err(priv); +} + +/* Configuration changes (passed on by ifconfig) */ +static int gmac_config(struct net_device *ndev, struct ifmap *map) +{ + if (ndev->flags & IFF_UP) /* can't act on a running interface */ + return -EBUSY; + + /* Don't allow changing the I/O address */ + if (map->base_addr != ndev->base_addr) { + printk(KERN_WARNING "%s: can't change I/O address\n", ndev->name); + return -EOPNOTSUPP; + } + + /* Don't allow changing the IRQ */ + if (map->irq != ndev->irq) { + printk(KERN_WARNING "%s: can't change IRQ number %d\n", + ndev->name, ndev->irq); + return -EOPNOTSUPP; + } + + /* ignore other fields */ + return 0; +} + +/** + * gmac_set_rx_mode - entry point for multicast addressing + * @dev : pointer to the device structure + * Description: + * This function is a driver entry point which gets called by the kernel + * whenever multicast addresses must be enabled/disabled. + * Return value: + * void. + */ +static void gmac_set_rx_mode(struct net_device *ndev) +{ + struct gmac_priv *priv = netdev_priv(ndev); + + spin_lock(&priv->lock); + core_set_filter(ndev); + spin_unlock(&priv->lock); +} + +/** + * gmac_change_mtu - entry point to change MTU size for the device. + * @dev : device pointer. + * @new_mtu : the new MTU size for the device. + * Description: the Maximum Transfer Unit (MTU) is used by the network layer + * to drive packet transmission. Ethernet has an MTU of 1500 octets + * (ETH_DATA_LEN). This value can be changed with ifconfig. + * Return value: + * 0 on success and an appropriate (-)ve integer as defined in errno.h + * file on failure. + */ +static int gmac_change_mtu(struct net_device *ndev, int new_mtu) +{ + int max_mtu; + + if (netif_running(ndev)) { + pr_err("%s: must be stopped to change its MTU\n", ndev->name); + return -EBUSY; + } + + max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); + + if ((new_mtu < 46) || (new_mtu > max_mtu)) { + pr_err("%s: invalid MTU, max MTU is: %d\n", ndev->name, max_mtu); + return -EINVAL; + } + + ndev->mtu = new_mtu; + netdev_update_features(ndev); + + return 0; +} + +static netdev_features_t gmac_fix_features(struct net_device *ndev, + netdev_features_t features) +{ + struct gmac_priv *priv = netdev_priv(ndev); + + if (!priv->rx_coe) + features &= ~NETIF_F_RXCSUM; + if (!priv->plat->tx_coe) + features &= ~NETIF_F_ALL_CSUM; + + /* Some GMAC devices have a bugged Jumbo frame support that + * needs to have the Tx COE disabled for oversized frames + * (due to limited buffer sizes). In this case we disable + * the TX csum insertionin the TDES and not use SF. */ + if (priv->plat->bugged_jumbo && (ndev->mtu > ETH_DATA_LEN)) + features &= ~NETIF_F_ALL_CSUM; + + return features; +} + +static irqreturn_t gmac_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *)dev_id; + struct gmac_priv *priv = netdev_priv(dev); + + if (unlikely(!dev)) { + pr_err("%s: invalid dev pointer\n", __func__); + return IRQ_NONE; + } + + /* To handle GMAC own interrupts */ + core_irq_status((void __iomem *) dev->base_addr); + + gmac_dma_interrupt(priv); + + return IRQ_HANDLED; +} + +#ifdef CONFIG_NET_POLL_CONTROLLER +/* Polling receive - used by NETCONSOLE and other diagnostic tools + * to allow network I/O with interrupts disabled. */ +static void gmac_poll_controller(struct net_device *dev) +{ + disable_irq(dev->irq); + gmac_interrupt(dev->irq, dev); + enable_irq(dev->irq); +} +#endif + +/** + * gmac_ioctl - Entry point for the Ioctl + * @dev: Device pointer. + * @rq: An IOCTL specefic structure, that can contain a pointer to + * a proprietary structure used to pass information to the driver. + * @cmd: IOCTL command + * Description: + * Currently there are no special functionality supported in IOCTL, just the + * phy_mii_ioctl(...) can be invoked. + */ +static int gmac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) +{ + int ret; + + if (!netif_running(ndev)) + return -EINVAL; + + if (!ndev->phydev) + return -EINVAL; + + ret = phy_mii_ioctl(ndev->phydev, rq, cmd); + + return ret; +} + +#ifdef CONFIG_GMAC_DEBUG_FS +static struct dentry *gmac_fs_dir; +static struct dentry *gmac_rings_status; + +static int gmac_sysfs_ring_read(struct seq_file *seq, void *v) +{ + struct tmp_s { + u64 a; + unsigned int b; + unsigned int c; + }; + int i; + struct net_device *dev = seq->private; + struct gmac_priv *priv = netdev_priv(dev); + + seq_printk(seq, "=======================\n"); + seq_printk(seq, " RX descriptor ring\n"); + seq_printk(seq, "=======================\n"); + + for (i = 0; i < priv->dma_rx_size; i++) { + struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i); + seq_printk(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", + i, (unsigned int)(x->a), + (unsigned int)((x->a) >> 32), x->b, x->c); + seq_printk(seq, "\n"); + } + + seq_printk(seq, "\n"); + seq_printk(seq, "=======================\n"); + seq_printk(seq, " TX descriptor ring\n"); + seq_printk(seq, "=======================\n"); + + for (i = 0; i < priv->dma_tx_size; i++) { + struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i); + seq_printk(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", + i, (unsigned int)(x->a), + (unsigned int)((x->a) >> 32), x->b, x->c); + seq_printk(seq, "\n"); + } + + return 0; +} + +static int gmac_sysfs_ring_open(struct inode *inode, struct file *file) +{ + return single_open(file, gmac_sysfs_ring_read, inode->i_private); +} + +static const struct file_operations gmac_rings_status_fops = { + .owner = THIS_MODULE, + .open = gmac_sysfs_ring_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + + +static int gmac_init_fs(struct net_device *dev) +{ + /* Create debugfs entries */ + gmac_fs_dir = debugfs_create_dir(GMAC_RESOURCE_NAME, NULL); + + if (!gmac_fs_dir || IS_ERR(gmac_fs_dir)) { + pr_err("ERROR %s, debugfs create directory failed\n", + GMAC_RESOURCE_NAME); + + return -ENOMEM; + } + + /* Entry to report DMA RX/TX rings */ + gmac_rings_status = debugfs_create_file("descriptors_status", + S_IRUGO, gmac_fs_dir, dev, + &gmac_rings_status_fops); + + if (!gmac_rings_status || IS_ERR(gmac_rings_status)) { + pr_info("ERROR creating gmac ring debugfs file\n"); + debugfs_remove(gmac_fs_dir); + + return -ENOMEM; + } + + return 0; +} + +static void gmac_exit_fs(void) +{ + debugfs_remove(gmac_rings_status); + debugfs_remove(gmac_fs_dir); +} +#endif /* CONFIG_GMAC_DEBUG_FS */ + +static const struct net_device_ops gmac_netdev_ops = { + .ndo_open = gmac_open, + .ndo_start_xmit = gmac_xmit, + .ndo_stop = gmac_release, + .ndo_change_mtu = gmac_change_mtu, + .ndo_fix_features = gmac_fix_features, + .ndo_set_rx_mode = gmac_set_rx_mode, + .ndo_tx_timeout = gmac_tx_timeout, + .ndo_do_ioctl = gmac_ioctl, + .ndo_set_config = gmac_config, +#ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = gmac_poll_controller, +#endif + .ndo_set_mac_address = eth_mac_addr, +}; + +/** + * gmac_hw_init - Init the MAC device + * @priv : pointer to the private device structure. + * Description: this function detects which MAC device + * (GMAC/MAC10-100) has to attached, checks the HW capability + * (if supported) and sets the driver's features (for example + * to use the ring or chaine mode or support the normal/enh + * descriptor structure). + */ +static int gmac_hw_init(struct gmac_priv *priv) +{ + int ret = 0; + + priv->rx_coe = core_en_rx_coe(priv->ioaddr); + + return ret; +} + +/** + * gmac_dvr_probe + * @device: device pointer + * Description: this is the main probe function used to + * call the alloc_etherdev, allocate the priv structure. + */ +struct gmac_priv *gmac_dvr_probe(struct device *device, + void __iomem *addr, int irqnum) +{ + int ret = 0; + struct net_device *ndev = NULL; + struct gmac_priv *priv; + + ndev = alloc_etherdev(sizeof(struct gmac_priv)); + if (!ndev) { + printk(KERN_ERR "ERROR: Allocating netdevice is failed!\n"); + return NULL; + } + + SET_NETDEV_DEV(ndev, device); + + priv = netdev_priv(ndev); + priv->device = device; + priv->ndev = ndev; + priv->plat = device->platform_data; + + ether_setup(ndev); + + gmac_set_ethtool_ops(ndev); + priv->pause = pause; + priv->ioaddr = addr; + ndev->base_addr = (unsigned long)addr; + + /* Init MAC and get the capabilities */ + gmac_hw_init(priv); + + ndev->irq = irqnum; + ndev->netdev_ops = &gmac_netdev_ops; + + ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM + | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM; + ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; + ndev->watchdog_timeo = msecs_to_jiffies(watchdog); +#ifdef GMAC_VLAN_TAG_USED + /* Gmac support receive VLAN tag detection */ + ndev->features |= NETIF_F_HW_VLAN_RX; +#endif + priv->msg_enable = netif_msg_init(debug, default_msg_level); + + if (flow_ctrl) + priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ + + netif_napi_add(ndev, &priv->napi, gmac_poll, 64); + + spin_lock_init(&priv->lock); + spin_lock_init(&priv->tx_lock); + + gmac_check_ether_addr(priv); + ret = register_netdev(ndev); + if (ret) { + printk(KERN_ERR "ERROR: %i registering the device\n", ret); + goto error; + } + + return priv; + +error: + netif_napi_del(&priv->napi); + + unregister_netdev(ndev); + free_netdev(ndev); + + return NULL; +} + +/** + * gmac_dvr_remove + * @ndev: net device pointer + * Description: this function resets the TX/RX processes, disables the MAC RX/TX + * changes the link status, releases the DMA descriptor rings. + */ +int gmac_dvr_remove(struct net_device *ndev) +{ + struct gmac_priv *priv = netdev_priv(ndev); + + dma_stop_rx(priv->ioaddr); + dma_stop_tx(priv->ioaddr); + + gmac_set_tx_rx(priv->ioaddr, false); + netif_carrier_off(ndev); + unregister_netdev(ndev); + free_netdev(ndev); + + return 0; +} + +#ifdef CONFIG_PM +int gmac_suspend(struct net_device *ndev) +{ + struct gmac_priv *priv = netdev_priv(ndev); + int dis_ic = 0; + + if (!ndev || !netif_running(ndev)) + return 0; + + if (ndev->phydev) + phy_stop(ndev->phydev); + + spin_lock(&priv->lock); + + netif_device_detach(ndev); + netif_stop_queue(ndev); + + napi_disable(&priv->napi); + + /* Stop TX/RX DMA */ + dma_stop_tx(priv->ioaddr); + dma_stop_rx(priv->ioaddr); + /* Clear the Rx/Tx descriptors */ + desc_init_rx(priv->dma_rx, priv->dma_rx_size, + dis_ic); + desc_init_tx(priv->dma_tx, priv->dma_tx_size); + + gmac_set_tx_rx(priv->ioaddr, false); + + spin_unlock(&priv->lock); + return 0; +} + +int gmac_resume(struct net_device *ndev) +{ + struct gmac_priv *priv = netdev_priv(ndev); + + if (!netif_running(ndev)) + return 0; + + spin_lock(&priv->lock); + + netif_device_attach(ndev); + + /* Enable the MAC and DMA */ + gmac_set_tx_rx(priv->ioaddr, true); + dma_start_tx(priv->ioaddr); + dma_start_rx(priv->ioaddr); + + napi_enable(&priv->napi); + + netif_start_queue(ndev); + + spin_unlock(&priv->lock); + + if (ndev->phydev) + phy_start(ndev->phydev); + + return 0; +} + +int gmac_freeze(struct net_device *ndev) +{ + if (!ndev || !netif_running(ndev)) + return 0; + + return gmac_release(ndev); +} + +int gmac_restore(struct net_device *ndev) +{ + if (!ndev || !netif_running(ndev)) + return 0; + + return gmac_open(ndev); +} +#endif /* CONFIG_PM */ + +#ifndef MODULE +static int __init set_mac_addr(char *str) +{ + char *p = str; + + if (!p || !strlen(p)) + return 0; + + memcpy(mac_str, p, 18); + + return 0; +} +__setup("mac_addr=", set_mac_addr); +#endif + +static int __init gmac_init(void) +{ +#ifdef CONFIG_GMAC_SCRIPT_SYS + if (SCRIPT_PARSER_OK != script_parser_fetch("gmac_para", "gmac_used", &gmac_used, 1)) + printk(KERN_WARNING "emac_init fetch emac using configuration failed\n"); + + if (!gmac_used) { + printk(KERN_INFO "gmac driver is disabled\n"); + return 0; + } +#endif + + platform_device_register(&gmac_device); + return platform_driver_register(&gmac_driver); +} + +static void __exit gmac_remove(void) +{ + if (gmac_used != 1) { + pr_info("gmac is disabled\n"); + return; + } + platform_driver_unregister(&gmac_driver); + platform_device_unregister(&gmac_device); +} + +module_init(gmac_init); +module_exit(gmac_remove); + +MODULE_DESCRIPTION("SUN6I 10/100/1000Mbps Ethernet device driver"); +MODULE_AUTHOR("Shuge "); +MODULE_LICENSE("GPL v2"); diff --git a/patch/linux-sunxi/drivers/net/wireless/rtl8188eu/hal/rtl8188e/usb/rtl8188eu_led.c b/patch/linux-sunxi/drivers/net/wireless/rtl8188eu/hal/rtl8188e/usb/rtl8188eu_led.c new file mode 100644 index 0000000..5010283 --- /dev/null +++ b/patch/linux-sunxi/drivers/net/wireless/rtl8188eu/hal/rtl8188e/usb/rtl8188eu_led.c @@ -0,0 +1,176 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include +#include +#include +#include + +//================================================================================ +// LED object. +//================================================================================ + + +//================================================================================ +// Prototype of protected function. +//================================================================================ + + +//================================================================================ +// LED_819xUsb routines. +//================================================================================ + +// +// Description: +// Turn on LED according to LedPin specified. +// +void +SwLedOn( + _adapter *padapter, + PLED_871x pLed +) +{ + u8 LedCfg; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) + { + return; + } + + LedCfg = rtw_read8(padapter, REG_LEDCFG2); + switch(pLed->LedPin) + { + case LED_PIN_LED0: + rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); // SW control led0 on. + // add by liaods for pcduino + rtw_write8(padapter, REG_LEDCFG0, (LedCfg&0x70)|BIT5|BIT6); // SW control led0 on. + break; + + case LED_PIN_LED1: + rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x0f)|BIT5); // SW control led1 on. + break; + + default: + break; + } + + pLed->bLedOn = _TRUE; +} + + +// +// Description: +// Turn off LED according to LedPin specified. +// +void +SwLedOff( + _adapter *padapter, + PLED_871x pLed +) +{ + u8 LedCfg; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if((padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) + { + goto exit; + } + + + LedCfg = rtw_read8(padapter, REG_LEDCFG2);//0x4E + + switch(pLed->LedPin) + { + case LED_PIN_LED0: + if(pHalData->bLedOpenDrain == _TRUE) // Open-drain arrangement for controlling the LED) + { + LedCfg &= 0x90; // Set to software control. + rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3)); + // add by liaods for pcduino + rtw_write8(padapter, REG_LEDCFG0, (LedCfg|BIT3)); // SW control led0 on. + + LedCfg = rtw_read8(padapter, REG_MAC_PINMUX_CFG); + LedCfg &= 0xFE; + rtw_write8(padapter, REG_MAC_PINMUX_CFG, LedCfg); + } + else + { + rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT5|BIT6)); + rtw_write8(padapter, REG_LEDCFG0, (LedCfg|BIT3|BIT5|BIT6)); + } + break; + + case LED_PIN_LED1: + LedCfg &= 0x0f; // Set to software control. + rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3)); + break; + + default: + break; + } +exit: + pLed->bLedOn = _FALSE; + +} + +//================================================================================ +// Interface to manipulate LED objects. +//================================================================================ + + +//================================================================================ +// Default LED behavior. +//================================================================================ + +// +// Description: +// Initialize all LED_871x objects. +// +void +rtl8188eu_InitSwLeds( + _adapter *padapter + ) +{ + struct led_priv *pledpriv = &(padapter->ledpriv); + + pledpriv->LedControlHandler = LedControl871x; + + InitLed871x(padapter, &(pledpriv->SwLed0), LED_PIN_LED0); + + InitLed871x(padapter,&(pledpriv->SwLed1), LED_PIN_LED1); +} + + +// +// Description: +// DeInitialize all LED_819xUsb objects. +// +void +rtl8188eu_DeInitSwLeds( + _adapter *padapter + ) +{ + struct led_priv *ledpriv = &(padapter->ledpriv); + + DeInitLed871x( &(ledpriv->SwLed0) ); + DeInitLed871x( &(ledpriv->SwLed1) ); +} + diff --git a/patch/linux-sunxi/drivers/tty/serial/8250/8250.c b/patch/linux-sunxi/drivers/tty/serial/8250/8250.c new file mode 100644 index 0000000..9089d2e --- /dev/null +++ b/patch/linux-sunxi/drivers/tty/serial/8250/8250.c @@ -0,0 +1,3459 @@ +/* + * Driver for 8250/16550-type serial ports + * + * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * Copyright (C) 2001 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * A note about mapbase / membase + * + * mapbase is the physical address of the IO port. + * membase is an 'ioremapped' cookie. + */ + +#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SPARC +#include +#endif + +#include +#include + +#include "8250.h" + + +#ifdef CONFIG_SERIAL_8250_SUNXI +#define AW_UART_RBR 0x00 /* Receive Buffer Register */ +#define AW_UART_THR 0x00 /* Transmit Holding Register */ +#define AW_UART_DLL 0x00 /* Divisor Latch Low Register */ +#define AW_UART_DLH 0x04 /* Diviso Latch High Register */ +#define AW_UART_IER 0x04 /* Interrupt Enable Register */ +#define AW_UART_IIR 0x08 /* Interrrupt Identity Register */ +#define AW_UART_FCR 0x08 /* FIFO Control Register */ +#define AW_UART_LCR 0x0c /* Line Control Register */ +#define AW_UART_MCR 0x10 /* Modem Control Register */ +#define AW_UART_LSR 0x14 /* Line Status Register */ +#define AW_UART_MSR 0x18 /* Modem Status Register */ +#define AW_UART_SCH 0x1c /* Scratch Register */ +#define AW_UART_USR 0x7c /* Status Register */ +#define AW_UART_TFL 0x80 /* Transmit FIFO Level */ +#define AW_UART_RFL 0x84 /* RFL */ +#define AW_UART_HALT 0xa4 /* Halt TX Register */ + +//#define UART_USR (AW_UART_USR >> 2) +#define UART_HALT (AW_UART_HALT >> 2) +#define UART_SCH (AW_UART_SCH >> 2) +#define UART_FORCE_CFG (1 << 1) +#define UART_FORCE_UPDATE (1 << 2) +#endif + +/* + * Configuration: + * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option + * is unsafe when used on edge-triggered interrupts. + */ +static unsigned int share_irqs = SERIAL8250_SHARE_IRQS; + +static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS; + +static struct uart_driver serial8250_reg; + +static int serial_index(struct uart_port *port) +{ + return (serial8250_reg.minor - 64) + port->line; +} + +static unsigned int skip_txen_test; /* force skip of txen test at init time */ + +/* + * Debugging. + */ +#if 0 +#define DEBUG_AUTOCONF(fmt...) printk(fmt) +#else +#define DEBUG_AUTOCONF(fmt...) do { } while (0) +#endif + +#if 0 +#define DEBUG_INTR(fmt...) printk(fmt) +#else +#define DEBUG_INTR(fmt...) do { } while (0) +#endif + +#define PASS_LIMIT 512 + +#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) + + +#ifdef CONFIG_SERIAL_8250_DETECT_IRQ +#define CONFIG_SERIAL_DETECT_IRQ 1 +#endif +#ifdef CONFIG_SERIAL_8250_MANY_PORTS +#define CONFIG_SERIAL_MANY_PORTS 1 +#endif + +/* + * HUB6 is always on. This will be removed once the header + * files have been cleaned. + */ +#define CONFIG_HUB6 1 + +#include +/* + * SERIAL_PORT_DFNS tells us about built-in ports that have no + * standard enumeration mechanism. Platforms that can find all + * serial ports via mechanisms like ACPI or PCI need not supply it. + */ +#ifndef SERIAL_PORT_DFNS +#define SERIAL_PORT_DFNS +#endif + +static const struct old_serial_port old_serial_port[] = { + SERIAL_PORT_DFNS /* defined in asm/serial.h */ +}; + +#define UART_NR CONFIG_SERIAL_8250_NR_UARTS + +#ifdef CONFIG_SERIAL_8250_RSA + +#define PORT_RSA_MAX 4 +static unsigned long probe_rsa[PORT_RSA_MAX]; +static unsigned int probe_rsa_count; +#endif /* CONFIG_SERIAL_8250_RSA */ + +struct irq_info { + struct hlist_node node; + int irq; + spinlock_t lock; /* Protects list not the hash */ + struct list_head *head; +}; + +#define NR_IRQ_HASH 32 /* Can be adjusted later */ +static struct hlist_head irq_lists[NR_IRQ_HASH]; +static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */ + +/* + * Here we define the default xmit fifo size used for each type of UART. + */ +static const struct serial8250_config uart_config[] = { + [PORT_UNKNOWN] = { + .name = "unknown", + .fifo_size = 1, + .tx_loadsz = 1, + }, + [PORT_8250] = { + .name = "8250", + .fifo_size = 1, + .tx_loadsz = 1, + }, + [PORT_16450] = { + .name = "16450", + .fifo_size = 1, + .tx_loadsz = 1, + }, + [PORT_16550] = { + .name = "16550", + .fifo_size = 1, + .tx_loadsz = 1, + }, + [PORT_16550A] = { + .name = "16550A", + .fifo_size = 16, + .tx_loadsz = 16, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, + .flags = UART_CAP_FIFO, + }, + [PORT_CIRRUS] = { + .name = "Cirrus", + .fifo_size = 1, + .tx_loadsz = 1, + }, + [PORT_16650] = { + .name = "ST16650", + .fifo_size = 1, + .tx_loadsz = 1, + .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, + }, + [PORT_16650V2] = { + .name = "ST16650V2", + .fifo_size = 32, + .tx_loadsz = 16, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | + UART_FCR_T_TRIG_00, + .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, + }, + [PORT_16750] = { + .name = "TI16750", + .fifo_size = 64, + .tx_loadsz = 64, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | + UART_FCR7_64BYTE, + .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, + }, + [PORT_STARTECH] = { + .name = "Startech", + .fifo_size = 1, + .tx_loadsz = 1, + }, + [PORT_16C950] = { + .name = "16C950/954", + .fifo_size = 128, + .tx_loadsz = 128, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, + /* UART_CAP_EFR breaks billionon CF bluetooth card. */ + .flags = UART_CAP_FIFO | UART_CAP_SLEEP, + }, + [PORT_16654] = { + .name = "ST16654", + .fifo_size = 64, + .tx_loadsz = 32, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | + UART_FCR_T_TRIG_10, + .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, + }, + [PORT_16850] = { + .name = "XR16850", + .fifo_size = 128, + .tx_loadsz = 128, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, + .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, + }, + [PORT_RSA] = { + .name = "RSA", + .fifo_size = 2048, + .tx_loadsz = 2048, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, + .flags = UART_CAP_FIFO, + }, + [PORT_NS16550A] = { + .name = "NS16550A", + .fifo_size = 16, + .tx_loadsz = 16, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, + .flags = UART_CAP_FIFO | UART_NATSEMI, + }, + [PORT_XSCALE] = { + .name = "XScale", + .fifo_size = 32, + .tx_loadsz = 32, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, + .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE, + }, + [PORT_RM9000] = { + .name = "RM9000", + .fifo_size = 16, + .tx_loadsz = 16, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, + .flags = UART_CAP_FIFO, + }, + [PORT_OCTEON] = { + .name = "OCTEON", + .fifo_size = 64, + .tx_loadsz = 64, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, + .flags = UART_CAP_FIFO, + }, + [PORT_AR7] = { + .name = "AR7", + .fifo_size = 16, + .tx_loadsz = 16, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, + .flags = UART_CAP_FIFO | UART_CAP_AFE, + }, + [PORT_U6_16550A] = { + .name = "U6_16550A", + .fifo_size = 64, + .tx_loadsz = 32, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 + | UART_FCR_T_TRIG_10, + .flags = UART_CAP_FIFO | UART_CAP_AFE, + }, + [PORT_TEGRA] = { + .name = "Tegra", + .fifo_size = 32, + .tx_loadsz = 8, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | + UART_FCR_T_TRIG_01, + .flags = UART_CAP_FIFO | UART_CAP_RTOIE, + }, + [PORT_XR17D15X] = { + .name = "XR17D15X", + .fifo_size = 64, + .tx_loadsz = 64, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, + .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR, + }, +}; + +#if defined(CONFIG_MIPS_ALCHEMY) + +/* Au1x00 UART hardware has a weird register layout */ +static const u8 au_io_in_map[] = { + [UART_RX] = 0, + [UART_IER] = 2, + [UART_IIR] = 3, + [UART_LCR] = 5, + [UART_MCR] = 6, + [UART_LSR] = 7, + [UART_MSR] = 8, +}; + +static const u8 au_io_out_map[] = { + [UART_TX] = 1, + [UART_IER] = 2, + [UART_FCR] = 4, + [UART_LCR] = 5, + [UART_MCR] = 6, +}; + +/* sane hardware needs no mapping */ +static inline int map_8250_in_reg(struct uart_port *p, int offset) +{ + if (p->iotype != UPIO_AU) + return offset; + return au_io_in_map[offset]; +} + +static inline int map_8250_out_reg(struct uart_port *p, int offset) +{ + if (p->iotype != UPIO_AU) + return offset; + return au_io_out_map[offset]; +} + +#elif defined(CONFIG_SERIAL_8250_RM9K) + +static const u8 + regmap_in[8] = { + [UART_RX] = 0x00, + [UART_IER] = 0x0c, + [UART_IIR] = 0x14, + [UART_LCR] = 0x1c, + [UART_MCR] = 0x20, + [UART_LSR] = 0x24, + [UART_MSR] = 0x28, + [UART_SCR] = 0x2c + }, + regmap_out[8] = { + [UART_TX] = 0x04, + [UART_IER] = 0x0c, + [UART_FCR] = 0x18, + [UART_LCR] = 0x1c, + [UART_MCR] = 0x20, + [UART_LSR] = 0x24, + [UART_MSR] = 0x28, + [UART_SCR] = 0x2c + }; + +static inline int map_8250_in_reg(struct uart_port *p, int offset) +{ + if (p->iotype != UPIO_RM9000) + return offset; + return regmap_in[offset]; +} + +static inline int map_8250_out_reg(struct uart_port *p, int offset) +{ + if (p->iotype != UPIO_RM9000) + return offset; + return regmap_out[offset]; +} + +#else + +/* sane hardware needs no mapping */ +#define map_8250_in_reg(up, offset) (offset) +#define map_8250_out_reg(up, offset) (offset) + +#endif + +static unsigned int hub6_serial_in(struct uart_port *p, int offset) +{ + offset = map_8250_in_reg(p, offset) << p->regshift; + outb(p->hub6 - 1 + offset, p->iobase); + return inb(p->iobase + 1); +} + +static void hub6_serial_out(struct uart_port *p, int offset, int value) +{ + offset = map_8250_out_reg(p, offset) << p->regshift; + outb(p->hub6 - 1 + offset, p->iobase); + outb(value, p->iobase + 1); +} + +static unsigned int mem_serial_in(struct uart_port *p, int offset) +{ + offset = map_8250_in_reg(p, offset) << p->regshift; + return readb(p->membase + offset); +} + +static void mem_serial_out(struct uart_port *p, int offset, int value) +{ + offset = map_8250_out_reg(p, offset) << p->regshift; + writeb(value, p->membase + offset); +} + +static void mem32_serial_out(struct uart_port *p, int offset, int value) +{ + offset = map_8250_out_reg(p, offset) << p->regshift; + writel(value, p->membase + offset); +} + +static unsigned int mem32_serial_in(struct uart_port *p, int offset) +{ + offset = map_8250_in_reg(p, offset) << p->regshift; + return readl(p->membase + offset); +} + +static unsigned int au_serial_in(struct uart_port *p, int offset) +{ + offset = map_8250_in_reg(p, offset) << p->regshift; + return __raw_readl(p->membase + offset); +} + +static void au_serial_out(struct uart_port *p, int offset, int value) +{ + offset = map_8250_out_reg(p, offset) << p->regshift; + __raw_writel(value, p->membase + offset); +} + +static unsigned int io_serial_in(struct uart_port *p, int offset) +{ + offset = map_8250_in_reg(p, offset) << p->regshift; + return inb(p->iobase + offset); +} + +static void io_serial_out(struct uart_port *p, int offset, int value) +{ + offset = map_8250_out_reg(p, offset) << p->regshift; + outb(value, p->iobase + offset); +} + +static int serial8250_default_handle_irq(struct uart_port *port); + +static void set_io_from_upio(struct uart_port *p) +{ + struct uart_8250_port *up = + container_of(p, struct uart_8250_port, port); + switch (p->iotype) { + case UPIO_HUB6: + p->serial_in = hub6_serial_in; + p->serial_out = hub6_serial_out; + break; + + case UPIO_MEM: + p->serial_in = mem_serial_in; + p->serial_out = mem_serial_out; + break; + + case UPIO_RM9000: + case UPIO_MEM32: + p->serial_in = mem32_serial_in; + p->serial_out = mem32_serial_out; + break; + + case UPIO_AU: + p->serial_in = au_serial_in; + p->serial_out = au_serial_out; + break; + + default: + p->serial_in = io_serial_in; + p->serial_out = io_serial_out; + break; + } + /* Remember loaded iotype */ + up->cur_iotype = p->iotype; + p->handle_irq = serial8250_default_handle_irq; +} + +static void +serial_port_out_sync(struct uart_port *p, int offset, int value) +{ + switch (p->iotype) { + case UPIO_MEM: + case UPIO_MEM32: + case UPIO_AU: + p->serial_out(p, offset, value); + p->serial_in(p, UART_LCR); /* safe, no side-effects */ + break; + default: + p->serial_out(p, offset, value); + } +} + +/* Uart divisor latch read */ +static inline int _serial_dl_read(struct uart_8250_port *up) +{ + return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8; +} + +/* Uart divisor latch write */ +static inline void _serial_dl_write(struct uart_8250_port *up, int value) +{ + serial_out(up, UART_DLL, value & 0xff); + serial_out(up, UART_DLM, value >> 8 & 0xff); +} + +#if defined(CONFIG_MIPS_ALCHEMY) +/* Au1x00 haven't got a standard divisor latch */ +static int serial_dl_read(struct uart_8250_port *up) +{ + if (up->port.iotype == UPIO_AU) + return __raw_readl(up->port.membase + 0x28); + else + return _serial_dl_read(up); +} + +static void serial_dl_write(struct uart_8250_port *up, int value) +{ + if (up->port.iotype == UPIO_AU) + __raw_writel(value, up->port.membase + 0x28); + else + _serial_dl_write(up, value); +} +#elif defined(CONFIG_SERIAL_8250_RM9K) +static int serial_dl_read(struct uart_8250_port *up) +{ + return (up->port.iotype == UPIO_RM9000) ? + (((__raw_readl(up->port.membase + 0x10) << 8) | + (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) : + _serial_dl_read(up); +} + +static void serial_dl_write(struct uart_8250_port *up, int value) +{ + if (up->port.iotype == UPIO_RM9000) { + __raw_writel(value, up->port.membase + 0x08); + __raw_writel(value >> 8, up->port.membase + 0x10); + } else { + _serial_dl_write(up, value); + } +} +#else +#define serial_dl_read(up) _serial_dl_read(up) +#define serial_dl_write(up, value) _serial_dl_write(up, value) +#endif + +/* + * For the 16C950 + */ +static void serial_icr_write(struct uart_8250_port *up, int offset, int value) +{ + serial_out(up, UART_SCR, offset); + serial_out(up, UART_ICR, value); +} + +#ifndef CONFIG_SERIAL_8250_SUNXI +static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) +{ + unsigned int value; + + serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); + serial_out(up, UART_SCR, offset); + value = serial_in(up, UART_ICR); + serial_icr_write(up, UART_ACR, up->acr); + + return value; +} +#endif + +/* + * FIFO support. + */ +static void serial8250_clear_fifos(struct uart_8250_port *p) +{ + if (p->capabilities & UART_CAP_FIFO) { + serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO); + serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO | + UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); + serial_out(p, UART_FCR, 0); + } +} + +/* + * IER sleep support. UARTs which have EFRs need the "extended + * capability" bit enabled. Note that on XR16C850s, we need to + * reset LCR to write to IER. + */ +static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) +{ + if (p->capabilities & UART_CAP_SLEEP) { + if (p->capabilities & UART_CAP_EFR) { + serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); + serial_out(p, UART_EFR, UART_EFR_ECB); + serial_out(p, UART_LCR, 0); + } + serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); + if (p->capabilities & UART_CAP_EFR) { + serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); + serial_out(p, UART_EFR, 0); + serial_out(p, UART_LCR, 0); + } + } +} + +#ifdef CONFIG_SERIAL_8250_RSA +/* + * Attempts to turn on the RSA FIFO. Returns zero on failure. + * We set the port uart clock rate if we succeed. + */ +static int __enable_rsa(struct uart_8250_port *up) +{ + unsigned char mode; + int result; + + mode = serial_in(up, UART_RSA_MSR); + result = mode & UART_RSA_MSR_FIFO; + + if (!result) { + serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); + mode = serial_in(up, UART_RSA_MSR); + result = mode & UART_RSA_MSR_FIFO; + } + + if (result) + up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; + + return result; +} + +static void enable_rsa(struct uart_8250_port *up) +{ + if (up->port.type == PORT_RSA) { + if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { + spin_lock_irq(&up->port.lock); + __enable_rsa(up); + spin_unlock_irq(&up->port.lock); + } + if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) + serial_out(up, UART_RSA_FRR, 0); + } +} + +/* + * Attempts to turn off the RSA FIFO. Returns zero on failure. + * It is unknown why interrupts were disabled in here. However, + * the caller is expected to preserve this behaviour by grabbing + * the spinlock before calling this function. + */ +static void disable_rsa(struct uart_8250_port *up) +{ + unsigned char mode; + int result; + + if (up->port.type == PORT_RSA && + up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { + spin_lock_irq(&up->port.lock); + + mode = serial_in(up, UART_RSA_MSR); + result = !(mode & UART_RSA_MSR_FIFO); + + if (!result) { + serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); + mode = serial_in(up, UART_RSA_MSR); + result = !(mode & UART_RSA_MSR_FIFO); + } + + if (result) + up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; + spin_unlock_irq(&up->port.lock); + } +} +#endif /* CONFIG_SERIAL_8250_RSA */ + +/* + * This is a quickie test to see how big the FIFO is. + * It doesn't work at all the time, more's the pity. + */ +static int size_fifo(struct uart_8250_port *up) +{ +#ifndef CONFIG_SERIAL_8250_SUNXI + unsigned char old_fcr, old_mcr, old_lcr; + unsigned short old_dl; + int count; + + old_lcr = serial_in(up, UART_LCR); + serial_out(up, UART_LCR, 0); + old_fcr = serial_in(up, UART_FCR); + old_mcr = serial_in(up, UART_MCR); + serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | + UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); + serial_out(up, UART_MCR, UART_MCR_LOOP); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); + old_dl = serial_dl_read(up); + serial_dl_write(up, 0x0001); + serial_out(up, UART_LCR, 0x03); + for (count = 0; count < 256; count++) + serial_out(up, UART_TX, count); + mdelay(20);/* FIXME - schedule_timeout */ + for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) && + (count < 256); count++) + serial_in(up, UART_RX); + serial_out(up, UART_FCR, old_fcr); + serial_out(up, UART_MCR, old_mcr); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); + serial_dl_write(up, old_dl); + serial_out(up, UART_LCR, old_lcr); + + return count; +#else + return 64; +#endif +} + +#ifndef CONFIG_SERIAL_8250_SUNXI +/* + * Read UART ID using the divisor method - set DLL and DLM to zero + * and the revision will be in DLL and device type in DLM. We + * preserve the device state across this. + */ +static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) +{ + unsigned char old_dll, old_dlm, old_lcr; + unsigned int id; + + old_lcr = serial_in(p, UART_LCR); + serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A); + + old_dll = serial_in(p, UART_DLL); + old_dlm = serial_in(p, UART_DLM); + + serial_out(p, UART_DLL, 0); + serial_out(p, UART_DLM, 0); + + id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8; + + serial_out(p, UART_DLL, old_dll); + serial_out(p, UART_DLM, old_dlm); + serial_out(p, UART_LCR, old_lcr); + + return id; +} +#endif + +/* + * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. + * When this function is called we know it is at least a StarTech + * 16650 V2, but it might be one of several StarTech UARTs, or one of + * its clones. (We treat the broken original StarTech 16650 V1 as a + * 16550, and why not? Startech doesn't seem to even acknowledge its + * existence.) + * + * What evil have men's minds wrought... + */ +#ifndef CONFIG_SERIAL_8250_SUNXI +static void autoconfig_has_efr(struct uart_8250_port *up) +{ + unsigned int id1, id2, id3, rev; + + /* + * Everything with an EFR has SLEEP + */ + up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; + + /* + * First we check to see if it's an Oxford Semiconductor UART. + * + * If we have to do this here because some non-National + * Semiconductor clone chips lock up if you try writing to the + * LSR register (which serial_icr_read does) + */ + + /* + * Check for Oxford Semiconductor 16C950. + * + * EFR [4] must be set else this test fails. + * + * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) + * claims that it's needed for 952 dual UART's (which are not + * recommended for new designs). + */ + up->acr = 0; + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); + serial_out(up, UART_EFR, UART_EFR_ECB); + serial_out(up, UART_LCR, 0x00); + id1 = serial_icr_read(up, UART_ID1); + id2 = serial_icr_read(up, UART_ID2); + id3 = serial_icr_read(up, UART_ID3); + rev = serial_icr_read(up, UART_REV); + + DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); + + if (id1 == 0x16 && id2 == 0xC9 && + (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { + up->port.type = PORT_16C950; + + /* + * Enable work around for the Oxford Semiconductor 952 rev B + * chip which causes it to seriously miscalculate baud rates + * when DLL is 0. + */ + if (id3 == 0x52 && rev == 0x01) + up->bugs |= UART_BUG_QUOT; + return; + } + + /* + * We check for a XR16C850 by setting DLL and DLM to 0, and then + * reading back DLL and DLM. The chip type depends on the DLM + * value read back: + * 0x10 - XR16C850 and the DLL contains the chip revision. + * 0x12 - XR16C2850. + * 0x14 - XR16C854. + */ + id1 = autoconfig_read_divisor_id(up); + DEBUG_AUTOCONF("850id=%04x ", id1); + + id2 = id1 >> 8; + if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { + up->port.type = PORT_16850; + return; + } + + /* + * It wasn't an XR16C850. + * + * We distinguish between the '654 and the '650 by counting + * how many bytes are in the FIFO. I'm using this for now, + * since that's the technique that was sent to me in the + * serial driver update, but I'm not convinced this works. + * I've had problems doing this in the past. -TYT + */ + if (size_fifo(up) == 64) + up->port.type = PORT_16654; + else + up->port.type = PORT_16650V2; +} + +/* + * We detected a chip without a FIFO. Only two fall into + * this category - the original 8250 and the 16450. The + * 16450 has a scratch register (accessible with LCR=0) + */ +static void autoconfig_8250(struct uart_8250_port *up) +{ + unsigned char scratch, status1, status2; + + up->port.type = PORT_8250; + + scratch = serial_in(up, UART_SCR); + serial_out(up, UART_SCR, 0xa5); + status1 = serial_in(up, UART_SCR); + serial_out(up, UART_SCR, 0x5a); + status2 = serial_in(up, UART_SCR); + serial_out(up, UART_SCR, scratch); + + if (status1 == 0xa5 && status2 == 0x5a) + up->port.type = PORT_16450; +} + +static int broken_efr(struct uart_8250_port *up) +{ + /* + * Exar ST16C2550 "A2" devices incorrectly detect as + * having an EFR, and report an ID of 0x0201. See + * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html + */ + if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) + return 1; + + return 0; +} +#endif + +static inline int ns16550a_goto_highspeed(struct uart_8250_port *up) +{ + unsigned char status; + + status = serial_in(up, 0x04); /* EXCR2 */ +#define PRESL(x) ((x) & 0x30) + if (PRESL(status) == 0x10) { + /* already in high speed mode */ + return 0; + } else { + status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ + status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ + serial_out(up, 0x04, status); + } + return 1; +} + +/* + * We know that the chip has FIFOs. Does it have an EFR? The + * EFR is located in the same register position as the IIR and + * we know the top two bits of the IIR are currently set. The + * EFR should contain zero. Try to read the EFR. + */ +static void autoconfig_16550a(struct uart_8250_port *up) +{ +#ifndef CONFIG_SERIAL_8250_SUNXI + unsigned char status1, status2; + unsigned int iersave; + + up->port.type = PORT_16550A; + up->capabilities |= UART_CAP_FIFO; + + /* + * Check for presence of the EFR when DLAB is set. + * Only ST16C650V1 UARTs pass this test. + */ + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); + if (serial_in(up, UART_EFR) == 0) { + serial_out(up, UART_EFR, 0xA8); + if (serial_in(up, UART_EFR) != 0) { + DEBUG_AUTOCONF("EFRv1 "); + up->port.type = PORT_16650; + up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; + } else { + DEBUG_AUTOCONF("Motorola 8xxx DUART "); + } + serial_out(up, UART_EFR, 0); + return; + } + + /* + * Maybe it requires 0xbf to be written to the LCR. + * (other ST16C650V2 UARTs, TI16C752A, etc) + */ + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); + if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { + DEBUG_AUTOCONF("EFRv2 "); + autoconfig_has_efr(up); + return; + } + + /* + * Check for a National Semiconductor SuperIO chip. + * Attempt to switch to bank 2, read the value of the LOOP bit + * from EXCR1. Switch back to bank 0, change it in MCR. Then + * switch back to bank 2, read it from EXCR1 again and check + * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 + */ + serial_out(up, UART_LCR, 0); + status1 = serial_in(up, UART_MCR); + serial_out(up, UART_LCR, 0xE0); + status2 = serial_in(up, 0x02); /* EXCR1 */ + + if (!((status2 ^ status1) & UART_MCR_LOOP)) { + serial_out(up, UART_LCR, 0); + serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP); + serial_out(up, UART_LCR, 0xE0); + status2 = serial_in(up, 0x02); /* EXCR1 */ + serial_out(up, UART_LCR, 0); + serial_out(up, UART_MCR, status1); + + if ((status2 ^ status1) & UART_MCR_LOOP) { + unsigned short quot; + + serial_out(up, UART_LCR, 0xE0); + + quot = serial_dl_read(up); + quot <<= 3; + + if (ns16550a_goto_highspeed(up)) + serial_dl_write(up, quot); + + serial_out(up, UART_LCR, 0); + + up->port.uartclk = 921600*16; + up->port.type = PORT_NS16550A; + up->capabilities |= UART_NATSEMI; + return; + } + } + + /* + * No EFR. Try to detect a TI16750, which only sets bit 5 of + * the IIR when 64 byte FIFO mode is enabled when DLAB is set. + * Try setting it with and without DLAB set. Cheap clones + * set bit 5 without DLAB set. + */ + serial_out(up, UART_LCR, 0); + serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); + status1 = serial_in(up, UART_IIR) >> 5; + serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); + serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); + status2 = serial_in(up, UART_IIR) >> 5; + serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); + serial_out(up, UART_LCR, 0); + + DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); + + if (status1 == 6 && status2 == 7) { + up->port.type = PORT_16750; + up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; + return; + } + + /* + * Try writing and reading the UART_IER_UUE bit (b6). + * If it works, this is probably one of the Xscale platform's + * internal UARTs. + * We're going to explicitly set the UUE bit to 0 before + * trying to write and read a 1 just to make sure it's not + * already a 1 and maybe locked there before we even start start. + */ + iersave = serial_in(up, UART_IER); + serial_out(up, UART_IER, iersave & ~UART_IER_UUE); + if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { + /* + * OK it's in a known zero state, try writing and reading + * without disturbing the current state of the other bits. + */ + serial_out(up, UART_IER, iersave | UART_IER_UUE); + if (serial_in(up, UART_IER) & UART_IER_UUE) { + /* + * It's an Xscale. + * We'll leave the UART_IER_UUE bit set to 1 (enabled). + */ + DEBUG_AUTOCONF("Xscale "); + up->port.type = PORT_XSCALE; + up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE; + return; + } + } else { + /* + * If we got here we couldn't force the IER_UUE bit to 0. + * Log it and continue. + */ + DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); + } + serial_out(up, UART_IER, iersave); + + /* + * Exar uarts have EFR in a weird location + */ + if (up->port.flags & UPF_EXAR_EFR) { + up->port.type = PORT_XR17D15X; + up->capabilities |= UART_CAP_AFE | UART_CAP_EFR; + } + +#else + up->port.type = PORT_16550A; + up->capabilities |= UART_CAP_FIFO; +#endif + + /* + * We distinguish between 16550A and U6 16550A by counting + * how many bytes are in the FIFO. + */ + if (up->port.type == PORT_16550A && size_fifo(up) == 64) { + up->port.type = PORT_U6_16550A; + up->capabilities |= UART_CAP_AFE; + } +} + +/* + * This routine is called by rs_init() to initialize a specific serial + * port. It determines what type of UART chip this serial port is + * using: 8250, 16450, 16550, 16550A. The important question is + * whether or not this UART is a 16550A or not, since this will + * determine whether or not we can use its FIFO features or not. + */ +static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) +{ + unsigned char status1, scratch, scratch2, scratch3; + unsigned char save_lcr, save_mcr; + struct uart_port *port = &up->port; + unsigned long flags; + + if (!port->iobase && !port->mapbase && !port->membase) + return; + + DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ", + serial_index(port), port->iobase, port->membase); + + /* + * We really do need global IRQs disabled here - we're going to + * be frobbing the chips IRQ enable register to see if it exists. + */ + spin_lock_irqsave(&port->lock, flags); + + up->capabilities = 0; + up->bugs = 0; + + if (!(port->flags & UPF_BUGGY_UART)) { + /* + * Do a simple existence test first; if we fail this, + * there's no point trying anything else. + * + * 0x80 is used as a nonsense port to prevent against + * false positives due to ISA bus float. The + * assumption is that 0x80 is a non-existent port; + * which should be safe since include/asm/io.h also + * makes this assumption. + * + * Note: this is safe as long as MCR bit 4 is clear + * and the device is in "PC" mode. + */ + scratch = serial_in(up, UART_IER); + serial_out(up, UART_IER, 0); +#ifdef __i386__ + outb(0xff, 0x080); +#endif + /* + * Mask out IER[7:4] bits for test as some UARTs (e.g. TL + * 16C754B) allow only to modify them if an EFR bit is set. + */ + scratch2 = serial_in(up, UART_IER) & 0x0f; + serial_out(up, UART_IER, 0x0F); +#ifdef __i386__ + outb(0, 0x080); +#endif + scratch3 = serial_in(up, UART_IER) & 0x0f; + serial_out(up, UART_IER, scratch); + if (scratch2 != 0 || scratch3 != 0x0F) { + /* + * We failed; there's nothing here + */ + DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", + scratch2, scratch3); + goto out; + } + } + + save_mcr = serial_in(up, UART_MCR); + save_lcr = serial_in(up, UART_LCR); + + /* + * Check to see if a UART is really there. Certain broken + * internal modems based on the Rockwell chipset fail this + * test, because they apparently don't implement the loopback + * test mode. So this test is skipped on the COM 1 through + * COM 4 ports. This *should* be safe, since no board + * manufacturer would be stupid enough to design a board + * that conflicts with COM 1-4 --- we hope! + */ + if (!(port->flags & UPF_SKIP_TEST)) { + serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A); + status1 = serial_in(up, UART_MSR) & 0xF0; + serial_out(up, UART_MCR, save_mcr); + if (status1 != 0x90) { + DEBUG_AUTOCONF("LOOP test failed (%02x) ", + status1); + goto out; + } + } + + /* + * We're pretty sure there's a port here. Lets find out what + * type of port it is. The IIR top two bits allows us to find + * out if it's 8250 or 16450, 16550, 16550A or later. This + * determines what we test for next. + * + * We also initialise the EFR (if any) to zero for later. The + * EFR occupies the same register location as the FCR and IIR. + */ +#ifdef CONFIG_SERIAL_8250_SUNXI + autoconfig_16550a(up); +#else + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); + serial_out(up, UART_EFR, 0); + serial_out(up, UART_LCR, 0); + + serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); + scratch = serial_in(up, UART_IIR) >> 6; + + DEBUG_AUTOCONF("iir=%d ", scratch); + + switch (scratch) { + case 0: + autoconfig_8250(up); + break; + case 1: + port->type = PORT_UNKNOWN; + break; + case 2: + port->type = PORT_16550; + break; + case 3: + autoconfig_16550a(up); + break; + } + +#ifdef CONFIG_SERIAL_8250_RSA + /* + * Only probe for RSA ports if we got the region. + */ + if (port->type == PORT_16550A && probeflags & PROBE_RSA) { + int i; + + for (i = 0 ; i < probe_rsa_count; ++i) { + if (probe_rsa[i] == port->iobase && __enable_rsa(up)) { + port->type = PORT_RSA; + break; + } + } + } +#endif + + serial_out(up, UART_LCR, save_lcr); +#endif + + if (up->capabilities != uart_config[port->type].flags) { + printk(KERN_WARNING + "ttyS%d: detected caps %08x should be %08x\n", + serial_index(port), up->capabilities, + uart_config[port->type].flags); + } + + port->fifosize = uart_config[up->port.type].fifo_size; + up->capabilities = uart_config[port->type].flags; + up->tx_loadsz = uart_config[port->type].tx_loadsz; + + if (port->type == PORT_UNKNOWN) + goto out; + + /* + * Reset the UART. + */ +#ifdef CONFIG_SERIAL_8250_RSA + if (port->type == PORT_RSA) + serial_out(up, UART_RSA_FRR, 0); +#endif + serial_out(up, UART_MCR, save_mcr); + serial8250_clear_fifos(up); + serial_in(up, UART_RX); + if (up->capabilities & UART_CAP_UUE) + serial_out(up, UART_IER, UART_IER_UUE); + else + serial_out(up, UART_IER, 0); + + out: + spin_unlock_irqrestore(&port->lock, flags); + DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name); +} + +static void autoconfig_irq(struct uart_8250_port *up) +{ + struct uart_port *port = &up->port; + unsigned char save_mcr, save_ier; + unsigned char save_ICP = 0; + unsigned int ICP = 0; + unsigned long irqs; + int irq; + + if (port->flags & UPF_FOURPORT) { + ICP = (port->iobase & 0xfe0) | 0x1f; + save_ICP = inb_p(ICP); + outb_p(0x80, ICP); + inb_p(ICP); + } + + /* forget possible initially masked and pending IRQ */ + probe_irq_off(probe_irq_on()); + save_mcr = serial_in(up, UART_MCR); + save_ier = serial_in(up, UART_IER); + serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2); + + irqs = probe_irq_on(); + serial_out(up, UART_MCR, 0); + udelay(10); + if (port->flags & UPF_FOURPORT) { + serial_out(up, UART_MCR, + UART_MCR_DTR | UART_MCR_RTS); + } else { + serial_out(up, UART_MCR, + UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); + } + serial_out(up, UART_IER, 0x0f); /* enable all intrs */ + serial_in(up, UART_LSR); + serial_in(up, UART_RX); + serial_in(up, UART_IIR); + serial_in(up, UART_MSR); + serial_out(up, UART_TX, 0xFF); + udelay(20); + irq = probe_irq_off(irqs); + + serial_out(up, UART_MCR, save_mcr); + serial_out(up, UART_IER, save_ier); + + if (port->flags & UPF_FOURPORT) + outb_p(save_ICP, ICP); + + port->irq = (irq > 0) ? irq : 0; +} + +static inline void __stop_tx(struct uart_8250_port *p) +{ + if (p->ier & UART_IER_THRI) { + p->ier &= ~UART_IER_THRI; + serial_out(p, UART_IER, p->ier); + } +} + +static void serial8250_stop_tx(struct uart_port *port) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + + __stop_tx(up); + + /* + * We really want to stop the transmitter from sending. + */ + if (port->type == PORT_16C950) { + up->acr |= UART_ACR_TXDIS; + serial_icr_write(up, UART_ACR, up->acr); + } +} + +static void serial8250_start_tx(struct uart_port *port) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + + if (!(up->ier & UART_IER_THRI)) { + up->ier |= UART_IER_THRI; + serial_port_out(port, UART_IER, up->ier); + + if (up->bugs & UART_BUG_TXEN) { + unsigned char lsr; + lsr = serial_in(up, UART_LSR); + up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; + if ((port->type == PORT_RM9000) ? + (lsr & UART_LSR_THRE) : + (lsr & UART_LSR_TEMT)) + serial8250_tx_chars(up); + } + } + + /* + * Re-enable the transmitter if we disabled it. + */ + if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { + up->acr &= ~UART_ACR_TXDIS; + serial_icr_write(up, UART_ACR, up->acr); + } +} + +static void serial8250_stop_rx(struct uart_port *port) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + + up->ier &= ~UART_IER_RLSI; + up->port.read_status_mask &= ~UART_LSR_DR; + serial_port_out(port, UART_IER, up->ier); +} + +static void serial8250_enable_ms(struct uart_port *port) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + + /* no MSR capabilities */ + if (up->bugs & UART_BUG_NOMSR) + return; + + up->ier |= UART_IER_MSI; + serial_port_out(port, UART_IER, up->ier); +} + +/* + * Clear the Tegra rx fifo after a break + * + * FIXME: This needs to become a port specific callback once we have a + * framework for this + */ +static void clear_rx_fifo(struct uart_8250_port *up) +{ + unsigned int status, tmout = 10000; + do { + status = serial_in(up, UART_LSR); + if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) + status = serial_in(up, UART_RX); + else + break; + if (--tmout == 0) + break; + udelay(1); + } while (1); +} + +/* + * serial8250_rx_chars: processes according to the passed in LSR + * value, and returns the remaining LSR bits not handled + * by this Rx routine. + */ +unsigned char +serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr) +{ + struct uart_port *port = &up->port; + struct tty_struct *tty = port->state->port.tty; + unsigned char ch; + int max_count = 256; + char flag; + + do { + if (likely(lsr & UART_LSR_DR)) + ch = serial_in(up, UART_RX); + else + /* + * Intel 82571 has a Serial Over Lan device that will + * set UART_LSR_BI without setting UART_LSR_DR when + * it receives a break. To avoid reading from the + * receive buffer without UART_LSR_DR bit set, we + * just force the read character to be 0 + */ + ch = 0; + + flag = TTY_NORMAL; + port->icount.rx++; + + lsr |= up->lsr_saved_flags; + up->lsr_saved_flags = 0; + + if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { + /* + * For statistics only + */ + if (lsr & UART_LSR_BI) { + lsr &= ~(UART_LSR_FE | UART_LSR_PE); + port->icount.brk++; + /* + * If tegra port then clear the rx fifo to + * accept another break/character. + */ + if (port->type == PORT_TEGRA) + clear_rx_fifo(up); + + /* + * We do the SysRQ and SAK checking + * here because otherwise the break + * may get masked by ignore_status_mask + * or read_status_mask. + */ + if (uart_handle_break(port)) + goto ignore_char; + } else if (lsr & UART_LSR_PE) + port->icount.parity++; + else if (lsr & UART_LSR_FE) + port->icount.frame++; + if (lsr & UART_LSR_OE) + port->icount.overrun++; + + /* + * Mask off conditions which should be ignored. + */ + lsr &= port->read_status_mask; + + if (lsr & UART_LSR_BI) { + DEBUG_INTR("handling break...."); + flag = TTY_BREAK; + } else if (lsr & UART_LSR_PE) + flag = TTY_PARITY; + else if (lsr & UART_LSR_FE) + flag = TTY_FRAME; + } + +#ifndef CONFIG_SERIAL_8250_SUNXI + if (uart_handle_sysrq_char(port, ch)) + goto ignore_char; +#endif + + uart_insert_char(port, lsr, UART_LSR_OE, ch, flag); + +ignore_char: + lsr = serial_in(up, UART_LSR); + } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); + spin_unlock(&port->lock); + tty_flip_buffer_push(tty); + spin_lock(&port->lock); + return lsr; +} +EXPORT_SYMBOL_GPL(serial8250_rx_chars); + +void serial8250_tx_chars(struct uart_8250_port *up) +{ + struct uart_port *port = &up->port; + struct circ_buf *xmit = &port->state->xmit; + int count; + + if (port->x_char) { + serial_out(up, UART_TX, port->x_char); + port->icount.tx++; + port->x_char = 0; + return; + } + if (uart_tx_stopped(port)) { + serial8250_stop_tx(port); + return; + } + if (uart_circ_empty(xmit)) { + __stop_tx(up); + return; + } + + count = up->tx_loadsz; + do { + serial_out(up, UART_TX, xmit->buf[xmit->tail]); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + if (uart_circ_empty(xmit)) + break; + } while (--count > 0); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); + + DEBUG_INTR("THRE..."); + + if (uart_circ_empty(xmit)) + __stop_tx(up); +} +EXPORT_SYMBOL_GPL(serial8250_tx_chars); + +unsigned int serial8250_modem_status(struct uart_8250_port *up) +{ + struct uart_port *port = &up->port; + unsigned int status = serial_in(up, UART_MSR); + unsigned int mcr = serial_in(up, UART_MCR); + + status |= up->msr_saved_flags; + up->msr_saved_flags = 0; + if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && + port->state != NULL) { + if (status & UART_MSR_TERI) + port->icount.rng++; + if (status & UART_MSR_DDSR) + port->icount.dsr++; + if (status & UART_MSR_DDCD) + uart_handle_dcd_change(port, status & UART_MSR_DCD); + /* + * modified by yemao, 2011-12-1 13:28:32 + * Do not check the changement of CTS signal if Auto Flow Control is enabled + * so you must check this enable bit in MCR register + */ + if (!(mcr & UART_MCR_AFE) && (status & UART_MSR_DCTS)) { + uart_handle_cts_change(port, status & UART_MSR_CTS); + } + wake_up_interruptible(&port->state->port.delta_msr_wait); + } + + return status; +} +EXPORT_SYMBOL_GPL(serial8250_modem_status); + +/* + * This handles the interrupt from one port. + */ +int serial8250_handle_irq(struct uart_port *port, unsigned int iir) +{ + unsigned char status; + unsigned long flags; + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + +#ifdef CONFIG_SERIAL_8250_SUNXI + if ((iir & 0x7) == UART_IIR_BUSY) { + if (serial_in(up, UART_USR)&1) { + serial_out(up, UART_HALT, UART_FORCE_CFG); + serial_out(up, UART_LCR, up->lcr); + serial_out(up, UART_HALT, UART_FORCE_CFG |UART_FORCE_UPDATE); + while(serial_in(up, UART_HALT)&UART_FORCE_UPDATE); + serial_out(up, UART_HALT, 0x00); + serial_in(up, UART_USR); + } else + serial_out(up, UART_LCR, up->lcr); + return 1; + } +#endif + + if (iir & UART_IIR_NO_INT) + return 0; + + spin_lock_irqsave(&port->lock, flags); + + status = serial_port_in(port, UART_LSR); + + DEBUG_INTR("status = %x...", status); + + if (status & (UART_LSR_DR | UART_LSR_BI)) + status = serial8250_rx_chars(up, status); + serial8250_modem_status(up); + if (status & UART_LSR_THRE) + serial8250_tx_chars(up); + + spin_unlock_irqrestore(&port->lock, flags); + return 1; +} +EXPORT_SYMBOL_GPL(serial8250_handle_irq); + +static int serial8250_default_handle_irq(struct uart_port *port) +{ + unsigned int iir = serial_port_in(port, UART_IIR); + + return serial8250_handle_irq(port, iir); +} + +/* + * This is the serial driver's interrupt routine. + * + * Arjan thinks the old way was overly complex, so it got simplified. + * Alan disagrees, saying that need the complexity to handle the weird + * nature of ISA shared interrupts. (This is a special exception.) + * + * In order to handle ISA shared interrupts properly, we need to check + * that all ports have been serviced, and therefore the ISA interrupt + * line has been de-asserted. + * + * This means we need to loop through all ports. checking that they + * don't have an interrupt pending. + */ +static irqreturn_t serial8250_interrupt(int irq, void *dev_id) +{ + struct irq_info *i = dev_id; + struct list_head *l, *end = NULL; + int pass_counter = 0, handled = 0; + + DEBUG_INTR("serial8250_interrupt(%d)...", irq); + + spin_lock(&i->lock); + + l = i->head; + do { + struct uart_8250_port *up; + struct uart_port *port; + + up = list_entry(l, struct uart_8250_port, list); + port = &up->port; + + if (port->handle_irq(port)) { + handled = 1; + end = NULL; + } else if (end == NULL) { + end = l; + } + + l = l->next; + + if (l == i->head && pass_counter++ > PASS_LIMIT) { + /* If we hit this, we're dead. */ + printk_ratelimited(KERN_ERR + "serial8250: too much work for irq%d\n", irq); + break; + } + } while (l != end); + + spin_unlock(&i->lock); + + DEBUG_INTR("end.\n"); + + return IRQ_RETVAL(handled); +} + +/* + * To support ISA shared interrupts, we need to have one interrupt + * handler that ensures that the IRQ line has been deasserted + * before returning. Failing to do this will result in the IRQ + * line being stuck active, and, since ISA irqs are edge triggered, + * no more IRQs will be seen. + */ +static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up) +{ + spin_lock_irq(&i->lock); + + if (!list_empty(i->head)) { + if (i->head == &up->list) + i->head = i->head->next; + list_del(&up->list); + } else { + BUG_ON(i->head != &up->list); + i->head = NULL; + } + spin_unlock_irq(&i->lock); + /* List empty so throw away the hash node */ + if (i->head == NULL) { + hlist_del(&i->node); + kfree(i); + } +} + +static int serial_link_irq_chain(struct uart_8250_port *up) +{ + struct hlist_head *h; + struct hlist_node *n; + struct irq_info *i; + int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0; + + mutex_lock(&hash_mutex); + + h = &irq_lists[up->port.irq % NR_IRQ_HASH]; + + hlist_for_each(n, h) { + i = hlist_entry(n, struct irq_info, node); + if (i->irq == up->port.irq) + break; + } + + if (n == NULL) { + i = kzalloc(sizeof(struct irq_info), GFP_KERNEL); + if (i == NULL) { + mutex_unlock(&hash_mutex); + return -ENOMEM; + } + spin_lock_init(&i->lock); + i->irq = up->port.irq; + hlist_add_head(&i->node, h); + } + mutex_unlock(&hash_mutex); + + spin_lock_irq(&i->lock); + + if (i->head) { + list_add(&up->list, i->head); + spin_unlock_irq(&i->lock); + + ret = 0; + } else { + INIT_LIST_HEAD(&up->list); + i->head = &up->list; + spin_unlock_irq(&i->lock); + irq_flags |= up->port.irqflags; + ret = request_irq(up->port.irq, serial8250_interrupt, + irq_flags, "serial", i); + if (ret < 0) + serial_do_unlink(i, up); + } + + return ret; +} + +static void serial_unlink_irq_chain(struct uart_8250_port *up) +{ + struct irq_info *i; + struct hlist_node *n; + struct hlist_head *h; + + mutex_lock(&hash_mutex); + + h = &irq_lists[up->port.irq % NR_IRQ_HASH]; + + hlist_for_each(n, h) { + i = hlist_entry(n, struct irq_info, node); + if (i->irq == up->port.irq) + break; + } + + BUG_ON(n == NULL); + BUG_ON(i->head == NULL); + + if (list_empty(i->head)) + free_irq(up->port.irq, i); + + serial_do_unlink(i, up); + mutex_unlock(&hash_mutex); +} + +/* + * This function is used to handle ports that do not have an + * interrupt. This doesn't work very well for 16450's, but gives + * barely passable results for a 16550A. (Although at the expense + * of much CPU overhead). + */ +static void serial8250_timeout(unsigned long data) +{ + struct uart_8250_port *up = (struct uart_8250_port *)data; + + up->port.handle_irq(&up->port); + mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port)); +} + +static void serial8250_backup_timeout(unsigned long data) +{ + struct uart_8250_port *up = (struct uart_8250_port *)data; + unsigned int iir, ier = 0, lsr; + unsigned long flags; + + spin_lock_irqsave(&up->port.lock, flags); + + /* + * Must disable interrupts or else we risk racing with the interrupt + * based handler. + */ + if (up->port.irq) { + ier = serial_in(up, UART_IER); + serial_out(up, UART_IER, 0); + } + + iir = serial_in(up, UART_IIR); + + /* + * This should be a safe test for anyone who doesn't trust the + * IIR bits on their UART, but it's specifically designed for + * the "Diva" UART used on the management processor on many HP + * ia64 and parisc boxes. + */ + lsr = serial_in(up, UART_LSR); + up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; + if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) && + (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) && + (lsr & UART_LSR_THRE)) { + iir &= ~(UART_IIR_ID | UART_IIR_NO_INT); + iir |= UART_IIR_THRI; + } + + if (!(iir & UART_IIR_NO_INT)) + serial8250_tx_chars(up); + + if (up->port.irq) + serial_out(up, UART_IER, ier); + + spin_unlock_irqrestore(&up->port.lock, flags); + + /* Standard timer interval plus 0.2s to keep the port running */ + mod_timer(&up->timer, + jiffies + uart_poll_timeout(&up->port) + HZ / 5); +} + +static unsigned int serial8250_tx_empty(struct uart_port *port) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + unsigned long flags; + unsigned int lsr; + + spin_lock_irqsave(&port->lock, flags); + lsr = serial_port_in(port, UART_LSR); + up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; + spin_unlock_irqrestore(&port->lock, flags); + + return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0; +} + +static unsigned int serial8250_get_mctrl(struct uart_port *port) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + unsigned int status; + unsigned int ret; + + status = serial8250_modem_status(up); + + ret = 0; + if (status & UART_MSR_DCD) + ret |= TIOCM_CAR; + if (status & UART_MSR_RI) + ret |= TIOCM_RNG; + if (status & UART_MSR_DSR) + ret |= TIOCM_DSR; + if (status & UART_MSR_CTS) + ret |= TIOCM_CTS; + return ret; +} + +static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + unsigned char mcr = 0; + + if (mctrl & TIOCM_RTS) + mcr |= UART_MCR_RTS; + if (mctrl & TIOCM_DTR) + mcr |= UART_MCR_DTR; + if (mctrl & TIOCM_OUT1) + mcr |= UART_MCR_OUT1; + if (mctrl & TIOCM_OUT2) + mcr |= UART_MCR_OUT2; + if (mctrl & TIOCM_LOOP) + mcr |= UART_MCR_LOOP; + + mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; + serial_port_out(port, UART_MCR, mcr); +} + +static void serial8250_break_ctl(struct uart_port *port, int break_state) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + if (break_state == -1) + up->lcr |= UART_LCR_SBC; + else + up->lcr &= ~UART_LCR_SBC; + + +#ifdef CONFIG_SERIAL_8250_SUNXI + if (serial_in(up, UART_USR)&0x01) { + serial_out(up, UART_HALT, UART_FORCE_CFG); + serial_out(up, UART_LCR, up->lcr); + serial_out(up, UART_HALT, UART_FORCE_CFG |UART_FORCE_UPDATE); + while(serial_in(up, UART_HALT)&UART_FORCE_UPDATE); + } else +#endif + serial_port_out(port, UART_LCR, up->lcr); + spin_unlock_irqrestore(&port->lock, flags); +} + +/* + * Wait for transmitter & holding register to empty + */ +static void wait_for_xmitr(struct uart_8250_port *up, int bits) +{ + unsigned int status, tmout = 10000; + + /* Wait up to 10ms for the character(s) to be sent. */ + for (;;) { + status = serial_in(up, UART_LSR); + + up->lsr_saved_flags |= status & LSR_SAVE_FLAGS; + + if ((status & bits) == bits) + break; + if (--tmout == 0) + break; + udelay(1); + } + + /* Wait up to 1s for flow control if necessary */ + if (up->port.flags & UPF_CONS_FLOW) { + unsigned int tmout; + for (tmout = 1000000; tmout; tmout--) { + unsigned int msr = serial_in(up, UART_MSR); + up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; + if (msr & UART_MSR_CTS) + break; + udelay(1); + touch_nmi_watchdog(); + } + } +} + +#ifdef CONFIG_CONSOLE_POLL +/* + * Console polling routines for writing and reading from the uart while + * in an interrupt or debug context. + */ + +static int serial8250_get_poll_char(struct uart_port *port) +{ + unsigned char lsr = serial_port_in(port, UART_LSR); + + if (!(lsr & UART_LSR_DR)) + return NO_POLL_CHAR; + + return serial_port_in(port, UART_RX); +} + + +static void serial8250_put_poll_char(struct uart_port *port, + unsigned char c) +{ + unsigned int ier; + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + + /* + * First save the IER then disable the interrupts + */ + ier = serial_port_in(port, UART_IER); + if (up->capabilities & UART_CAP_UUE) + serial_port_out(port, UART_IER, UART_IER_UUE); + else + serial_port_out(port, UART_IER, 0); + + wait_for_xmitr(up, BOTH_EMPTY); + /* + * Send the character out. + * If a LF, also do CR... + */ + serial_port_out(port, UART_TX, c); + if (c == 10) { + wait_for_xmitr(up, BOTH_EMPTY); + serial_port_out(port, UART_TX, 13); + } + + /* + * Finally, wait for transmitter to become empty + * and restore the IER + */ + wait_for_xmitr(up, BOTH_EMPTY); + serial_port_out(port, UART_IER, ier); +} + +#endif /* CONFIG_CONSOLE_POLL */ + +static int serial8250_startup(struct uart_port *port) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + unsigned long flags; + unsigned char lsr, iir; + int retval; + + port->fifosize = uart_config[up->port.type].fifo_size; + up->tx_loadsz = uart_config[up->port.type].tx_loadsz; + up->capabilities = uart_config[up->port.type].flags; + up->mcr = 0; + + if (port->iotype != up->cur_iotype) + set_io_from_upio(port); + + if (port->type == PORT_16C950) { + /* Wake up and initialize UART */ + up->acr = 0; + serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); + serial_port_out(port, UART_EFR, UART_EFR_ECB); + serial_port_out(port, UART_IER, 0); + serial_port_out(port, UART_LCR, 0); + serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ + serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); + serial_port_out(port, UART_EFR, UART_EFR_ECB); + serial_port_out(port, UART_LCR, 0); + } + +#ifdef CONFIG_SERIAL_8250_RSA + /* + * If this is an RSA port, see if we can kick it up to the + * higher speed clock. + */ + enable_rsa(up); +#endif + + /* + * Clear the FIFO buffers and disable them. + * (they will be reenabled in set_termios()) + */ + serial8250_clear_fifos(up); + + /* + * Clear the interrupt registers. + */ + serial_port_in(port, UART_LSR); + serial_port_in(port, UART_RX); + serial_port_in(port, UART_IIR); + serial_port_in(port, UART_MSR); + + /* + * At this point, there's no way the LSR could still be 0xff; + * if it is, then bail out, because there's likely no UART + * here. + */ + if (!(port->flags & UPF_BUGGY_UART) && + (serial_port_in(port, UART_LSR) == 0xff)) { + printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n", + serial_index(port)); + return -ENODEV; + } + + /* + * For a XR16C850, we need to set the trigger levels + */ + if (port->type == PORT_16850) { + unsigned char fctr; + + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); + + fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); + serial_port_out(port, UART_FCTR, + fctr | UART_FCTR_TRGD | UART_FCTR_RX); + serial_port_out(port, UART_TRG, UART_TRG_96); + serial_port_out(port, UART_FCTR, + fctr | UART_FCTR_TRGD | UART_FCTR_TX); + serial_port_out(port, UART_TRG, UART_TRG_96); + + serial_port_out(port, UART_LCR, 0); + } + + if (port->irq) { + unsigned char iir1; + /* + * Test for UARTs that do not reassert THRE when the + * transmitter is idle and the interrupt has already + * been cleared. Real 16550s should always reassert + * this interrupt whenever the transmitter is idle and + * the interrupt is enabled. Delays are necessary to + * allow register changes to become visible. + */ + spin_lock_irqsave(&port->lock, flags); + if (up->port.irqflags & IRQF_SHARED) + disable_irq_nosync(port->irq); + + wait_for_xmitr(up, UART_LSR_THRE); + serial_port_out_sync(port, UART_IER, UART_IER_THRI); + udelay(1); /* allow THRE to set */ + iir1 = serial_port_in(port, UART_IIR); + serial_port_out(port, UART_IER, 0); + serial_port_out_sync(port, UART_IER, UART_IER_THRI); + udelay(1); /* allow a working UART time to re-assert THRE */ + iir = serial_port_in(port, UART_IIR); + serial_port_out(port, UART_IER, 0); + + if (port->irqflags & IRQF_SHARED) + enable_irq(port->irq); + spin_unlock_irqrestore(&port->lock, flags); + + /* + * If the interrupt is not reasserted, or we otherwise + * don't trust the iir, setup a timer to kick the UART + * on a regular basis. + */ + if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) || + up->port.flags & UPF_BUG_THRE) { + up->bugs |= UART_BUG_THRE; + pr_debug("ttyS%d - using backup timer\n", + serial_index(port)); + } + } + + /* + * The above check will only give an accurate result the first time + * the port is opened so this value needs to be preserved. + */ + if (up->bugs & UART_BUG_THRE) { + up->timer.function = serial8250_backup_timeout; + up->timer.data = (unsigned long)up; + mod_timer(&up->timer, jiffies + + uart_poll_timeout(port) + HZ / 5); + } + + /* + * If the "interrupt" for this port doesn't correspond with any + * hardware interrupt, we use a timer-based system. The original + * driver used to do this with IRQ0. + */ + if (!port->irq) { + up->timer.data = (unsigned long)up; + mod_timer(&up->timer, jiffies + uart_poll_timeout(port)); + } else { + retval = serial_link_irq_chain(up); + if (retval) + return retval; + } + + /* + * Now, initialize the UART + */ + serial_port_out(port, UART_LCR, UART_LCR_WLEN8); + + spin_lock_irqsave(&port->lock, flags); + if (up->port.flags & UPF_FOURPORT) { + if (!up->port.irq) + up->port.mctrl |= TIOCM_OUT1; + } else + /* + * Most PC uarts need OUT2 raised to enable interrupts. + */ + if (port->irq) + up->port.mctrl |= TIOCM_OUT2; + + serial8250_set_mctrl(port, port->mctrl); + + /* Serial over Lan (SoL) hack: + Intel 8257x Gigabit ethernet chips have a + 16550 emulation, to be used for Serial Over Lan. + Those chips take a longer time than a normal + serial device to signalize that a transmission + data was queued. Due to that, the above test generally + fails. One solution would be to delay the reading of + iir. However, this is not reliable, since the timeout + is variable. So, let's just don't test if we receive + TX irq. This way, we'll never enable UART_BUG_TXEN. + */ + if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST) + goto dont_test_tx_en; + + /* + * Do a quick test to see if we receive an + * interrupt when we enable the TX irq. + */ + serial_port_out(port, UART_IER, UART_IER_THRI); + lsr = serial_port_in(port, UART_LSR); + iir = serial_port_in(port, UART_IIR); + serial_port_out(port, UART_IER, 0); + + if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { + if (!(up->bugs & UART_BUG_TXEN)) { + up->bugs |= UART_BUG_TXEN; + pr_debug("ttyS%d - enabling bad tx status workarounds\n", + serial_index(port)); + } + } else { + up->bugs &= ~UART_BUG_TXEN; + } + +dont_test_tx_en: + spin_unlock_irqrestore(&port->lock, flags); + + /* + * Clear the interrupt registers again for luck, and clear the + * saved flags to avoid getting false values from polling + * routines or the previous session. + */ + serial_port_in(port, UART_LSR); + serial_port_in(port, UART_RX); + serial_port_in(port, UART_IIR); + serial_port_in(port, UART_MSR); + up->lsr_saved_flags = 0; + up->msr_saved_flags = 0; + + /* + * Finally, enable interrupts. Note: Modem status interrupts + * are set via set_termios(), which will be occurring imminently + * anyway, so we don't enable them here. + */ + up->ier = UART_IER_RLSI | UART_IER_RDI; + serial_port_out(port, UART_IER, up->ier); + + if (port->flags & UPF_FOURPORT) { + unsigned int icp; + /* + * Enable interrupts on the AST Fourport board + */ + icp = (port->iobase & 0xfe0) | 0x01f; + outb_p(0x80, icp); + inb_p(icp); + } + + return 0; +} + +static void serial8250_shutdown(struct uart_port *port) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + unsigned long flags; + + /* + * Disable interrupts from this port + */ + up->ier = 0; + serial_port_out(port, UART_IER, 0); + + spin_lock_irqsave(&port->lock, flags); + if (port->flags & UPF_FOURPORT) { + /* reset interrupts on the AST Fourport board */ + inb((port->iobase & 0xfe0) | 0x1f); + port->mctrl |= TIOCM_OUT1; + } else + port->mctrl &= ~TIOCM_OUT2; + + serial8250_set_mctrl(port, port->mctrl); + spin_unlock_irqrestore(&port->lock, flags); + + /* + * Disable break condition and FIFOs + */ + serial_port_out(port, UART_LCR, + serial_port_in(port, UART_LCR) & ~UART_LCR_SBC); + serial8250_clear_fifos(up); + +#ifdef CONFIG_SERIAL_8250_RSA + /* + * Reset the RSA board back to 115kbps compat mode. + */ + disable_rsa(up); +#endif + + /* + * Read data port to reset things, and then unlink from + * the IRQ chain. + */ + serial_port_in(port, UART_RX); + + del_timer_sync(&up->timer); + up->timer.function = serial8250_timeout; + if (port->irq) + serial_unlink_irq_chain(up); +} + +static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud) +{ + unsigned int quot; + + /* + * Handle magic divisors for baud rates above baud_base on + * SMSC SuperIO chips. + */ + if ((port->flags & UPF_MAGIC_MULTIPLIER) && + baud == (port->uartclk/4)) + quot = 0x8001; + else if ((port->flags & UPF_MAGIC_MULTIPLIER) && + baud == (port->uartclk/8)) + quot = 0x8002; + else + quot = uart_get_divisor(port, baud); + + return quot; +} + +void +serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, + struct ktermios *old) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + unsigned char cval, fcr = 0; + unsigned long flags; + unsigned int baud, quot; + + switch (termios->c_cflag & CSIZE) { + case CS5: + cval = UART_LCR_WLEN5; + break; + case CS6: + cval = UART_LCR_WLEN6; + break; + case CS7: + cval = UART_LCR_WLEN7; + break; + default: + case CS8: + cval = UART_LCR_WLEN8; + break; + } + + if (termios->c_cflag & CSTOPB) + cval |= UART_LCR_STOP; + if (termios->c_cflag & PARENB) + cval |= UART_LCR_PARITY; + if (!(termios->c_cflag & PARODD)) + cval |= UART_LCR_EPAR; +#ifdef CMSPAR + if (termios->c_cflag & CMSPAR) + cval |= UART_LCR_SPAR; +#endif + + /* + * Ask the core to calculate the divisor for us. + */ + baud = uart_get_baud_rate(port, termios, old, + port->uartclk / 16 / 0xffff, + port->uartclk / 16); + quot = serial8250_get_divisor(port, baud); + + /* + * Oxford Semi 952 rev B workaround + */ + if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) + quot++; + + if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) { + fcr = uart_config[port->type].fcr; + if (baud < 2400) { + fcr &= ~UART_FCR_TRIGGER_MASK; + fcr |= UART_FCR_TRIGGER_1; + } + } + + /* + * MCR-based auto flow control. When AFE is enabled, RTS will be + * deasserted when the receive FIFO contains more characters than + * the trigger, or the MCR RTS bit is cleared. In the case where + * the remote UART is not using CTS auto flow control, we must + * have sufficient FIFO entries for the latency of the remote + * UART to respond. IOW, at least 32 bytes of FIFO. + */ + if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) { + up->mcr &= ~UART_MCR_AFE; + if (termios->c_cflag & CRTSCTS) + up->mcr |= UART_MCR_AFE; + } + + /* + * Ok, we're now changing the port state. Do it with + * interrupts disabled. + */ + spin_lock_irqsave(&port->lock, flags); + + /* + * Update the per-port timeout. + */ + uart_update_timeout(port, termios->c_cflag, baud); + + port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; + if (termios->c_iflag & INPCK) + port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; + if (termios->c_iflag & (BRKINT | PARMRK)) + port->read_status_mask |= UART_LSR_BI; + + /* + * Characteres to ignore + */ + port->ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; + if (termios->c_iflag & IGNBRK) { + port->ignore_status_mask |= UART_LSR_BI; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + port->ignore_status_mask |= UART_LSR_OE; + } + + /* + * ignore all characters if CREAD is not set + */ + if ((termios->c_cflag & CREAD) == 0) + port->ignore_status_mask |= UART_LSR_DR; + + /* + * CTS flow control flag and modem status interrupts + */ + up->ier &= ~UART_IER_MSI; + if (!(up->bugs & UART_BUG_NOMSR) && + UART_ENABLE_MS(&up->port, termios->c_cflag)) + up->ier |= UART_IER_MSI; + if (up->capabilities & UART_CAP_UUE) + up->ier |= UART_IER_UUE; + if (up->capabilities & UART_CAP_RTOIE) + up->ier |= UART_IER_RTOIE; + + serial_port_out(port, UART_IER, up->ier); + + if (up->capabilities & UART_CAP_EFR) { + unsigned char efr = 0; + /* + * TI16C752/Startech hardware flow control. FIXME: + * - TI16C752 requires control thresholds to be set. + * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. + */ + if (termios->c_cflag & CRTSCTS) + efr |= UART_EFR_CTS; + + serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); + if (port->flags & UPF_EXAR_EFR) + serial_port_out(port, UART_XR_EFR, efr); + else + serial_port_out(port, UART_EFR, efr); + } + +#ifdef CONFIG_ARCH_OMAP + /* Workaround to enable 115200 baud on OMAP1510 internal ports */ + if (cpu_is_omap1510() && is_omap_port(up)) { + if (baud == 115200) { + quot = 1; + serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1); + } else + serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0); + } +#endif + + /* + * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2, + * otherwise just set DLAB + */ + if (up->capabilities & UART_NATSEMI) + serial_port_out(port, UART_LCR, 0xe0); + else + { +#ifdef CONFIG_SERIAL_8250_SUNXI + /* + *Because our platform hardware so much ugly which likes my English + *I must check line status to ensure it no busy when set LCR value, + *if miserable the line status is busy,it must set UART_FORCE_CFG bit + *first before set LCR without DLAB,it also viable if you only want + *to set DLAB to set baud. More informations can be get for sw spec + * */ + if(serial_in(up, UART_USR)&0x01) + serial_out(up, UART_HALT, UART_FORCE_CFG); + else + serial_out(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ +#endif + serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB); + } + + serial_dl_write(up, quot); + + /* + * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR + * is written without DLAB set, this mode will be disabled. + */ + if (port->type == PORT_16750) + serial_port_out(port, UART_FCR, fcr); + + serial_port_out(port, UART_LCR, cval); /* reset DLAB */ + up->lcr = cval; /* Save LCR */ + +#ifdef CONFIG_SERIAL_8250_SUNXI + serial_out(up, UART_LCR, cval); + + /* + *When baud and LCR be set finish, it must set UART_FORCE_UPDATE bit + *to let operations take effect, the UART_FORCE_UPDATE will clear + *by self when update successfully + * */ + if(serial_in(up, UART_HALT) & UART_FORCE_CFG){ + serial_out(up, UART_HALT, UART_FORCE_CFG | UART_FORCE_UPDATE); + while(serial_in(up, UART_HALT) & UART_FORCE_UPDATE); + serial_out(up, UART_HALT, 0x00); + } +#endif + if (port->type != PORT_16750) { + /* emulated UARTs (Lucent Venus 167x) need two steps */ + if (fcr & UART_FCR_ENABLE_FIFO) + serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO); + serial_port_out(port, UART_FCR, fcr); /* set fcr */ + } + serial8250_set_mctrl(port, port->mctrl); + spin_unlock_irqrestore(&port->lock, flags); + /* Don't rewrite B0 */ + if (tty_termios_baud_rate(termios)) + tty_termios_encode_baud_rate(termios, baud, baud); +} +EXPORT_SYMBOL(serial8250_do_set_termios); + +static void +serial8250_set_termios(struct uart_port *port, struct ktermios *termios, + struct ktermios *old) +{ + if (port->set_termios) + port->set_termios(port, termios, old); + else + serial8250_do_set_termios(port, termios, old); +} + +static void +serial8250_set_ldisc(struct uart_port *port, int new) +{ + if (new == N_PPS) { + port->flags |= UPF_HARDPPS_CD; + serial8250_enable_ms(port); + } else + port->flags &= ~UPF_HARDPPS_CD; +} + + +void serial8250_do_pm(struct uart_port *port, unsigned int state, + unsigned int oldstate) +{ + struct uart_8250_port *p = + container_of(port, struct uart_8250_port, port); + + serial8250_set_sleep(p, state != 0); +} +EXPORT_SYMBOL(serial8250_do_pm); + +static void +serial8250_pm(struct uart_port *port, unsigned int state, + unsigned int oldstate) +{ + if (port->pm) + port->pm(port, state, oldstate); + else + serial8250_do_pm(port, state, oldstate); +} + +static unsigned int serial8250_port_size(struct uart_8250_port *pt) +{ + if (pt->port.iotype == UPIO_AU) + return 0x1000; +#ifdef CONFIG_ARCH_OMAP + if (is_omap_port(pt)) + return 0x16 << pt->port.regshift; +#endif + return 8 << pt->port.regshift; +} + +/* + * Resource handling. + */ +static int serial8250_request_std_resource(struct uart_8250_port *up) +{ + unsigned int size = serial8250_port_size(up); + struct uart_port *port = &up->port; + int ret = 0; + + switch (port->iotype) { + case UPIO_AU: + case UPIO_TSI: + case UPIO_MEM32: + case UPIO_MEM: + if (!port->mapbase) + break; + + if (!request_mem_region(port->mapbase, size, "serial")) { + ret = -EBUSY; + break; + } + + if (port->flags & UPF_IOREMAP) { + port->membase = ioremap_nocache(port->mapbase, size); + if (!port->membase) { + release_mem_region(port->mapbase, size); + ret = -ENOMEM; + } + } + break; + + case UPIO_HUB6: + case UPIO_PORT: + if (!request_region(port->iobase, size, "serial")) + ret = -EBUSY; + break; + } + return ret; +} + +static void serial8250_release_std_resource(struct uart_8250_port *up) +{ + unsigned int size = serial8250_port_size(up); + struct uart_port *port = &up->port; + + switch (port->iotype) { + case UPIO_AU: + case UPIO_TSI: + case UPIO_MEM32: + case UPIO_MEM: + if (!port->mapbase) + break; + + if (port->flags & UPF_IOREMAP) { + iounmap(port->membase); + port->membase = NULL; + } + + release_mem_region(port->mapbase, size); + break; + + case UPIO_HUB6: + case UPIO_PORT: + release_region(port->iobase, size); + break; + } +} + +static int serial8250_request_rsa_resource(struct uart_8250_port *up) +{ + unsigned long start = UART_RSA_BASE << up->port.regshift; + unsigned int size = 8 << up->port.regshift; + struct uart_port *port = &up->port; + int ret = -EINVAL; + + switch (port->iotype) { + case UPIO_HUB6: + case UPIO_PORT: + start += port->iobase; + if (request_region(start, size, "serial-rsa")) + ret = 0; + else + ret = -EBUSY; + break; + } + + return ret; +} + +static void serial8250_release_rsa_resource(struct uart_8250_port *up) +{ + unsigned long offset = UART_RSA_BASE << up->port.regshift; + unsigned int size = 8 << up->port.regshift; + struct uart_port *port = &up->port; + + switch (port->iotype) { + case UPIO_HUB6: + case UPIO_PORT: + release_region(port->iobase + offset, size); + break; + } +} + +static void serial8250_release_port(struct uart_port *port) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + + serial8250_release_std_resource(up); + if (port->type == PORT_RSA) + serial8250_release_rsa_resource(up); +} + +static int serial8250_request_port(struct uart_port *port) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + int ret = 0; + + ret = serial8250_request_std_resource(up); + if (ret == 0 && port->type == PORT_RSA) { + ret = serial8250_request_rsa_resource(up); + if (ret < 0) + serial8250_release_std_resource(up); + } + + return ret; +} + +static void serial8250_config_port(struct uart_port *port, int flags) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + int probeflags = PROBE_ANY; + int ret; + + /* + * Find the region that we can probe for. This in turn + * tells us whether we can probe for the type of port. + */ + ret = serial8250_request_std_resource(up); + if (ret < 0) + return; + + ret = serial8250_request_rsa_resource(up); + if (ret < 0) + probeflags &= ~PROBE_RSA; + + if (port->iotype != up->cur_iotype) + set_io_from_upio(port); + + if (flags & UART_CONFIG_TYPE) + autoconfig(up, probeflags); + + /* if access method is AU, it is a 16550 with a quirk */ + if (port->type == PORT_16550A && port->iotype == UPIO_AU) + up->bugs |= UART_BUG_NOMSR; + + if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) + autoconfig_irq(up); + + if (port->type != PORT_RSA && probeflags & PROBE_RSA) + serial8250_release_rsa_resource(up); + if (port->type == PORT_UNKNOWN) + serial8250_release_std_resource(up); +} + +static int +serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) +{ + if (ser->irq >= nr_irqs || ser->irq < 0 || + ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || + ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || + ser->type == PORT_STARTECH) + return -EINVAL; + return 0; +} + +static const char * +serial8250_type(struct uart_port *port) +{ + int type = port->type; + + if (type >= ARRAY_SIZE(uart_config)) + type = 0; + return uart_config[type].name; +} + +static struct uart_ops serial8250_pops = { + .tx_empty = serial8250_tx_empty, + .set_mctrl = serial8250_set_mctrl, + .get_mctrl = serial8250_get_mctrl, + .stop_tx = serial8250_stop_tx, + .start_tx = serial8250_start_tx, + .stop_rx = serial8250_stop_rx, + .enable_ms = serial8250_enable_ms, + .break_ctl = serial8250_break_ctl, + .startup = serial8250_startup, + .shutdown = serial8250_shutdown, + .set_termios = serial8250_set_termios, + .set_ldisc = serial8250_set_ldisc, + .pm = serial8250_pm, + .type = serial8250_type, + .release_port = serial8250_release_port, + .request_port = serial8250_request_port, + .config_port = serial8250_config_port, + .verify_port = serial8250_verify_port, +#ifdef CONFIG_CONSOLE_POLL + .poll_get_char = serial8250_get_poll_char, + .poll_put_char = serial8250_put_poll_char, +#endif +}; + +static struct uart_8250_port serial8250_ports[UART_NR]; + +static void (*serial8250_isa_config)(int port, struct uart_port *up, + unsigned short *capabilities); + +void serial8250_set_isa_configurator( + void (*v)(int port, struct uart_port *up, unsigned short *capabilities)) +{ + serial8250_isa_config = v; +} +EXPORT_SYMBOL(serial8250_set_isa_configurator); + +static void __init serial8250_isa_init_ports(void) +{ + struct uart_8250_port *up; + static int first = 1; + int i, irqflag = 0; + + if (!first) + return; + first = 0; + + for (i = 0; i < nr_uarts; i++) { + struct uart_8250_port *up = &serial8250_ports[i]; + struct uart_port *port = &up->port; + + port->line = i; + spin_lock_init(&port->lock); + + init_timer(&up->timer); + up->timer.function = serial8250_timeout; + + /* + * ALPHA_KLUDGE_MCR needs to be killed. + */ + up->mcr_mask = ~ALPHA_KLUDGE_MCR; + up->mcr_force = ALPHA_KLUDGE_MCR; + + port->ops = &serial8250_pops; + } + + if (share_irqs) + irqflag = IRQF_SHARED; + + for (i = 0, up = serial8250_ports; + i < ARRAY_SIZE(old_serial_port) && i < nr_uarts; + i++, up++) { + struct uart_port *port = &up->port; + + port->iobase = old_serial_port[i].port; + port->irq = irq_canonicalize(old_serial_port[i].irq); + port->irqflags = old_serial_port[i].irqflags; + port->uartclk = old_serial_port[i].baud_base * 16; + port->flags = old_serial_port[i].flags; + port->hub6 = old_serial_port[i].hub6; + port->membase = old_serial_port[i].iomem_base; + port->iotype = old_serial_port[i].io_type; + port->regshift = old_serial_port[i].iomem_reg_shift; + set_io_from_upio(port); + port->irqflags |= irqflag; + if (serial8250_isa_config != NULL) + serial8250_isa_config(i, &up->port, &up->capabilities); + + } +} + +static void +serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type) +{ + up->port.type = type; + up->port.fifosize = uart_config[type].fifo_size; + up->capabilities = uart_config[type].flags; + up->tx_loadsz = uart_config[type].tx_loadsz; +} + +static void __init +serial8250_register_ports(struct uart_driver *drv, struct device *dev) +{ + int i; + + for (i = 0; i < nr_uarts; i++) { + struct uart_8250_port *up = &serial8250_ports[i]; + up->cur_iotype = 0xFF; + } + + serial8250_isa_init_ports(); + + for (i = 0; i < nr_uarts; i++) { + struct uart_8250_port *up = &serial8250_ports[i]; + + up->port.dev = dev; + + if (up->port.flags & UPF_FIXED_TYPE) + serial8250_init_fixed_type_port(up, up->port.type); + + uart_add_one_port(drv, &up->port); + } +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE + +static void serial8250_console_putchar(struct uart_port *port, int ch) +{ + struct uart_8250_port *up = + container_of(port, struct uart_8250_port, port); + + wait_for_xmitr(up, UART_LSR_THRE); + serial_port_out(port, UART_TX, ch); +} + +/* + * Print a string to the serial port trying not to disturb + * any possible real use of the port... + * + * The console_lock must be held when we get here. + */ +static void +serial8250_console_write(struct console *co, const char *s, unsigned int count) +{ + struct uart_8250_port *up = &serial8250_ports[co->index]; + struct uart_port *port = &up->port; + unsigned long flags; + unsigned int ier; + int locked = 1; + + touch_nmi_watchdog(); + + local_irq_save(flags); + if (port->sysrq) { + /* serial8250_handle_irq() already took the lock */ + locked = 0; + } else if (oops_in_progress) { + locked = spin_trylock(&port->lock); + } else + spin_lock(&port->lock); + + /* + * First save the IER then disable the interrupts + */ + ier = serial_port_in(port, UART_IER); + + if (up->capabilities & UART_CAP_UUE) + serial_port_out(port, UART_IER, UART_IER_UUE); + else + serial_port_out(port, UART_IER, 0); + + uart_console_write(port, s, count, serial8250_console_putchar); + + /* + * Finally, wait for transmitter to become empty + * and restore the IER + */ + wait_for_xmitr(up, BOTH_EMPTY); + serial_port_out(port, UART_IER, ier); + + /* + * The receive handling will happen properly because the + * receive ready bit will still be set; it is not cleared + * on read. However, modem control will not, we must + * call it if we have saved something in the saved flags + * while processing with interrupts off. + */ + if (up->msr_saved_flags) + serial8250_modem_status(up); + + if (locked) + spin_unlock(&port->lock); + local_irq_restore(flags); +} + +static int __init serial8250_console_setup(struct console *co, char *options) +{ + struct uart_port *port; + int baud = 9600; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + if (co->index >= nr_uarts) + co->index = 0; + port = &serial8250_ports[co->index].port; + if (!port->iobase && !port->membase) + return -ENODEV; + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static int serial8250_console_early_setup(void) +{ + return serial8250_find_port_for_earlycon(); +} + +static struct console serial8250_console = { + .name = "ttyS", + .write = serial8250_console_write, + .device = uart_console_device, + .setup = serial8250_console_setup, + .early_setup = serial8250_console_early_setup, + .flags = CON_PRINTBUFFER | CON_ANYTIME, + .index = -1, + .data = &serial8250_reg, +}; + +static int __init serial8250_console_init(void) +{ + if (nr_uarts > UART_NR) + nr_uarts = UART_NR; + + serial8250_isa_init_ports(); + register_console(&serial8250_console); + return 0; +} +console_initcall(serial8250_console_init); + +int serial8250_find_port(struct uart_port *p) +{ + int line; + struct uart_port *port; + + for (line = 0; line < nr_uarts; line++) { + port = &serial8250_ports[line].port; + if (uart_match_port(p, port)) + return line; + } + return -ENODEV; +} + +#define SERIAL8250_CONSOLE &serial8250_console +#else +#define SERIAL8250_CONSOLE NULL +#endif + +static struct uart_driver serial8250_reg = { + .owner = THIS_MODULE, + .driver_name = "serial", + .dev_name = "ttyS", + .major = TTY_MAJOR, + .minor = 64, + .cons = SERIAL8250_CONSOLE, +}; + +/* + * early_serial_setup - early registration for 8250 ports + * + * Setup an 8250 port structure prior to console initialisation. Use + * after console initialisation will cause undefined behaviour. + */ +int __init early_serial_setup(struct uart_port *port) +{ + struct uart_port *p; + + if (port->line >= ARRAY_SIZE(serial8250_ports)) + return -ENODEV; + + serial8250_isa_init_ports(); + p = &serial8250_ports[port->line].port; + p->iobase = port->iobase; + p->membase = port->membase; + p->irq = port->irq; + p->irqflags = port->irqflags; + p->uartclk = port->uartclk; + p->fifosize = port->fifosize; + p->regshift = port->regshift; + p->iotype = port->iotype; + p->flags = port->flags; + p->mapbase = port->mapbase; + p->private_data = port->private_data; + p->type = port->type; + p->line = port->line; + + set_io_from_upio(p); + if (port->serial_in) + p->serial_in = port->serial_in; + if (port->serial_out) + p->serial_out = port->serial_out; + if (port->handle_irq) + p->handle_irq = port->handle_irq; + else + p->handle_irq = serial8250_default_handle_irq; + + return 0; +} + +/** + * serial8250_suspend_port - suspend one serial port + * @line: serial line number + * + * Suspend one serial port. + */ +void serial8250_suspend_port(int line) +{ + uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port); +} + +/** + * serial8250_resume_port - resume one serial port + * @line: serial line number + * + * Resume one serial port. + */ +void serial8250_resume_port(int line) +{ + struct uart_8250_port *up = &serial8250_ports[line]; + struct uart_port *port = &up->port; + + if (up->capabilities & UART_NATSEMI) { + /* Ensure it's still in high speed mode */ + serial_port_out(port, UART_LCR, 0xE0); + + ns16550a_goto_highspeed(up); + + serial_port_out(port, UART_LCR, 0); + port->uartclk = 921600*16; + } + uart_resume_port(&serial8250_reg, port); +} + +/* + * Register a set of serial devices attached to a platform device. The + * list is terminated with a zero flags entry, which means we expect + * all entries to have at least UPF_BOOT_AUTOCONF set. + */ +static int __devinit serial8250_probe(struct platform_device *dev) +{ + struct plat_serial8250_port *p = dev->dev.platform_data; + struct uart_port port; + int ret, i, irqflag = 0; + + memset(&port, 0, sizeof(struct uart_port)); + + if (share_irqs) + irqflag = IRQF_SHARED; + + for (i = 0; p && p->flags != 0; p++, i++) { + port.iobase = p->iobase; + port.membase = p->membase; + port.irq = p->irq; + port.irqflags = p->irqflags; + port.uartclk = p->uartclk; + port.regshift = p->regshift; + port.iotype = p->iotype; + port.flags = p->flags; + port.mapbase = p->mapbase; + port.hub6 = p->hub6; + port.private_data = p->private_data; + port.type = p->type; + port.serial_in = p->serial_in; + port.serial_out = p->serial_out; + port.handle_irq = p->handle_irq; + port.set_termios = p->set_termios; + port.pm = p->pm; + port.dev = &dev->dev; + port.irqflags |= irqflag; + ret = serial8250_register_port(&port); + if (ret < 0) { + dev_err(&dev->dev, "unable to register port at index %d " + "(IO%lx MEM%llx IRQ%d): %d\n", i, + p->iobase, (unsigned long long)p->mapbase, + p->irq, ret); + } + } + return 0; +} + +/* + * Remove serial ports registered against a platform device. + */ +static int __devexit serial8250_remove(struct platform_device *dev) +{ + int i; + + for (i = 0; i < nr_uarts; i++) { + struct uart_8250_port *up = &serial8250_ports[i]; + + if (up->port.dev == &dev->dev) + serial8250_unregister_port(i); + } + return 0; +} + +static int serial8250_suspend(struct platform_device *dev, pm_message_t state) +{ + int i; + + for (i = 0; i < UART_NR; i++) { + struct uart_8250_port *up = &serial8250_ports[i]; + + if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) + uart_suspend_port(&serial8250_reg, &up->port); + } + + return 0; +} + +static int serial8250_resume(struct platform_device *dev) +{ + int i; + + for (i = 0; i < UART_NR; i++) { + struct uart_8250_port *up = &serial8250_ports[i]; + + if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) + serial8250_resume_port(i); + } + + return 0; +} + +static struct platform_driver serial8250_isa_driver = { + .probe = serial8250_probe, + .remove = __devexit_p(serial8250_remove), + .suspend = serial8250_suspend, + .resume = serial8250_resume, + .driver = { + .name = "serial8250", + .owner = THIS_MODULE, + }, +}; + +/* + * This "device" covers _all_ ISA 8250-compatible serial devices listed + * in the table in include/asm/serial.h + */ +static struct platform_device *serial8250_isa_devs; + +/* + * serial8250_register_port and serial8250_unregister_port allows for + * 16x50 serial ports to be configured at run-time, to support PCMCIA + * modems and PCI multiport cards. + */ +static DEFINE_MUTEX(serial_mutex); + +static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port) +{ + int i; + + /* + * First, find a port entry which matches. + */ + for (i = 0; i < nr_uarts; i++) + if (uart_match_port(&serial8250_ports[i].port, port)) + return &serial8250_ports[i]; + + /* + * We didn't find a matching entry, so look for the first + * free entry. We look for one which hasn't been previously + * used (indicated by zero iobase). + */ + for (i = 0; i < nr_uarts; i++) + if (serial8250_ports[i].port.type == PORT_UNKNOWN && + serial8250_ports[i].port.iobase == 0) + return &serial8250_ports[i]; + + /* + * That also failed. Last resort is to find any entry which + * doesn't have a real port associated with it. + */ + for (i = 0; i < nr_uarts; i++) + if (serial8250_ports[i].port.type == PORT_UNKNOWN) + return &serial8250_ports[i]; + + return NULL; +} + +/** + * serial8250_register_port - register a serial port + * @port: serial port template + * + * Configure the serial port specified by the request. If the + * port exists and is in use, it is hung up and unregistered + * first. + * + * The port is then probed and if necessary the IRQ is autodetected + * If this fails an error is returned. + * + * On success the port is ready to use and the line number is returned. + */ +int serial8250_register_port(struct uart_port *port) +{ + struct uart_8250_port *uart; + int ret = -ENOSPC; + + if (port->uartclk == 0) + return -EINVAL; + + mutex_lock(&serial_mutex); + + uart = serial8250_find_match_or_unused(port); + if (uart) { + uart_remove_one_port(&serial8250_reg, &uart->port); + + uart->port.iobase = port->iobase; + uart->port.membase = port->membase; + uart->port.irq = port->irq; + uart->port.irqflags = port->irqflags; + uart->port.uartclk = port->uartclk; + uart->port.fifosize = port->fifosize; + uart->port.regshift = port->regshift; + uart->port.iotype = port->iotype; + uart->port.flags = port->flags | UPF_BOOT_AUTOCONF; + uart->port.mapbase = port->mapbase; + uart->port.private_data = port->private_data; + if (port->dev) + uart->port.dev = port->dev; + + if (port->flags & UPF_FIXED_TYPE) + serial8250_init_fixed_type_port(uart, port->type); + + set_io_from_upio(&uart->port); + /* Possibly override default I/O functions. */ + if (port->serial_in) + uart->port.serial_in = port->serial_in; + if (port->serial_out) + uart->port.serial_out = port->serial_out; + if (port->handle_irq) + uart->port.handle_irq = port->handle_irq; + /* Possibly override set_termios call */ + if (port->set_termios) + uart->port.set_termios = port->set_termios; + if (port->pm) + uart->port.pm = port->pm; + + if (serial8250_isa_config != NULL) + serial8250_isa_config(0, &uart->port, + &uart->capabilities); + + ret = uart_add_one_port(&serial8250_reg, &uart->port); + if (ret == 0) + ret = uart->port.line; + } + mutex_unlock(&serial_mutex); + + return ret; +} +EXPORT_SYMBOL(serial8250_register_port); + +/** + * serial8250_unregister_port - remove a 16x50 serial port at runtime + * @line: serial line number + * + * Remove one serial port. This may not be called from interrupt + * context. We hand the port back to the our control. + */ +void serial8250_unregister_port(int line) +{ + struct uart_8250_port *uart = &serial8250_ports[line]; + + mutex_lock(&serial_mutex); + uart_remove_one_port(&serial8250_reg, &uart->port); + if (serial8250_isa_devs) { + uart->port.flags &= ~UPF_BOOT_AUTOCONF; + uart->port.type = PORT_UNKNOWN; + uart->port.dev = &serial8250_isa_devs->dev; + uart->capabilities = uart_config[uart->port.type].flags; + uart_add_one_port(&serial8250_reg, &uart->port); + } else { + uart->port.dev = NULL; + } + mutex_unlock(&serial_mutex); +} +EXPORT_SYMBOL(serial8250_unregister_port); + +static int __init serial8250_init(void) +{ + int ret; + + if (nr_uarts > UART_NR) + nr_uarts = UART_NR; + + printk(KERN_INFO "Serial: 8250/16550 driver, " + "%d ports, IRQ sharing %sabled\n", nr_uarts, + share_irqs ? "en" : "dis"); + +#ifdef CONFIG_SPARC + ret = sunserial_register_minors(&serial8250_reg, UART_NR); +#else + serial8250_reg.nr = UART_NR; + ret = uart_register_driver(&serial8250_reg); +#endif + if (ret) + goto out; + + serial8250_isa_devs = platform_device_alloc("serial8250", + PLAT8250_DEV_LEGACY); + if (!serial8250_isa_devs) { + ret = -ENOMEM; + goto unreg_uart_drv; + } + + ret = platform_device_add(serial8250_isa_devs); + if (ret) + goto put_dev; + + serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev); + + ret = platform_driver_register(&serial8250_isa_driver); + if (ret == 0) + goto out; + + platform_device_del(serial8250_isa_devs); +put_dev: + platform_device_put(serial8250_isa_devs); +unreg_uart_drv: +#ifdef CONFIG_SPARC + sunserial_unregister_minors(&serial8250_reg, UART_NR); +#else + uart_unregister_driver(&serial8250_reg); +#endif +out: + return ret; +} + +static void __exit serial8250_exit(void) +{ + struct platform_device *isa_dev = serial8250_isa_devs; + + /* + * This tells serial8250_unregister_port() not to re-register + * the ports (thereby making serial8250_isa_driver permanently + * in use.) + */ + serial8250_isa_devs = NULL; + + platform_driver_unregister(&serial8250_isa_driver); + platform_device_unregister(isa_dev); + +#ifdef CONFIG_SPARC + sunserial_unregister_minors(&serial8250_reg, UART_NR); +#else + uart_unregister_driver(&serial8250_reg); +#endif +} + +module_init(serial8250_init); +module_exit(serial8250_exit); + +EXPORT_SYMBOL(serial8250_suspend_port); +EXPORT_SYMBOL(serial8250_resume_port); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Generic 8250/16x50 serial driver"); + +module_param(share_irqs, uint, 0644); +MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices" + " (unsafe)"); + +module_param(nr_uarts, uint, 0644); +MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")"); + +module_param(skip_txen_test, uint, 0644); +MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time"); + +#ifdef CONFIG_SERIAL_8250_RSA +module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); +MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); +#endif +MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); diff --git a/patch/linux-sunxi/drivers/usb/gadget/Kconfig b/patch/linux-sunxi/drivers/usb/gadget/Kconfig new file mode 100644 index 0000000..e2fc4dd --- /dev/null +++ b/patch/linux-sunxi/drivers/usb/gadget/Kconfig @@ -0,0 +1,1011 @@ +# +# USB Gadget support on a system involves +# (a) a peripheral controller, and +# (b) the gadget driver using it. +# +# NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !! +# +# - Host systems (like PCs) need CONFIG_USB (with "A" jacks). +# - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks). +# - Some systems have both kinds of controllers. +# +# With help from a special transceiver and a "Mini-AB" jack, systems with +# both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG). +# + +menuconfig USB_GADGET + tristate "USB Gadget Support" + select NLS + help + USB is a master/slave protocol, organized with one master + host (such as a PC) controlling up to 127 peripheral devices. + The USB hardware is asymmetric, which makes it easier to set up: + you can't connect a "to-the-host" connector to a peripheral. + + Linux can run in the host, or in the peripheral. In both cases + you need a low level bus controller driver, and some software + talking to it. Peripheral controllers are often discrete silicon, + or are integrated with the CPU in a microcontroller. The more + familiar host side controllers have names like "EHCI", "OHCI", + or "UHCI", and are usually integrated into southbridges on PC + motherboards. + + Enable this configuration option if you want to run Linux inside + a USB peripheral device. Configure one hardware driver for your + peripheral/device side bus controller, and a "gadget driver" for + your peripheral protocol. (If you use modular gadget drivers, + you may configure more than one.) + + If in doubt, say "N" and don't enable these drivers; most people + don't have this kind of hardware (except maybe inside Linux PDAs). + + For more information, see and + the kernel DocBook documentation for this API. + +if USB_GADGET + +config USB_GADGET_DEBUG + boolean "Debugging messages (DEVELOPMENT)" + depends on DEBUG_KERNEL + help + Many controller and gadget drivers will print some debugging + messages if you use this option to ask for those messages. + + Avoid enabling these messages, even if you're actively + debugging such a driver. Many drivers will emit so many + messages that the driver timings are affected, which will + either create new failure modes or remove the one you're + trying to track down. Never enable these messages for a + production build. + +config USB_GADGET_DEBUG_FILES + boolean "Debugging information files (DEVELOPMENT)" + depends on PROC_FS + help + Some of the drivers in the "gadget" framework can expose + debugging information in files such as /proc/driver/udc + (for a peripheral controller). The information in these + files may help when you're troubleshooting or bringing up a + driver on a new board. Enable these files by choosing "Y" + here. If in doubt, or to conserve kernel memory, say "N". + +config USB_GADGET_DEBUG_FS + boolean "Debugging information files in debugfs (DEVELOPMENT)" + depends on DEBUG_FS + help + Some of the drivers in the "gadget" framework can expose + debugging information in files under /sys/kernel/debug/. + The information in these files may help when you're + troubleshooting or bringing up a driver on a new board. + Enable these files by choosing "Y" here. If in doubt, or + to conserve kernel memory, say "N". + +config USB_GADGET_VBUS_DRAW + int "Maximum VBUS Power usage (2-500 mA)" + range 2 500 + default 2 + help + Some devices need to draw power from USB when they are + configured, perhaps to operate circuitry or to recharge + batteries. This is in addition to any local power supply, + such as an AC adapter or batteries. + + Enter the maximum power your device draws through USB, in + milliAmperes. The permitted range of values is 2 - 500 mA; + 0 mA would be legal, but can make some hosts misbehave. + + This value will be used except for system-specific gadget + drivers that have more specific information. + +config USB_GADGET_STORAGE_NUM_BUFFERS + int "Number of storage pipeline buffers" + range 2 4 + default 2 + help + Usually 2 buffers are enough to establish a good buffering + pipeline. The number may be increased in order to compensate + for a bursty VFS behaviour. For instance there may be CPU wake up + latencies that makes the VFS to appear bursty in a system with + an CPU on-demand governor. Especially if DMA is doing IO to + offload the CPU. In this case the CPU will go into power + save often and spin up occasionally to move data within VFS. + If selecting USB_GADGET_DEBUG_FILES this value may be set by + a module parameter as well. + If unsure, say 2. + +# +# USB Peripheral Controller Support +# +# The order here is alphabetical, except that integrated controllers go +# before discrete ones so they will be the initial/default value: +# - integrated/SOC controllers first +# - licensed IP used in both SOC and discrete versions +# - discrete ones (including all PCI-only controllers) +# - debug/dummy gadget+hcd is last. +# +choice + prompt "USB Peripheral Controller" + help + A USB device uses a controller to talk to its host. + Systems should have only one such upstream link. + Many controller drivers are platform-specific; these + often need board-specific hooks. + +# +# Integrated controllers +# + +config USB_AT91 + tristate "Atmel AT91 USB Device Port" + depends on ARCH_AT91 + help + Many Atmel AT91 processors (such as the AT91RM2000) have a + full speed USB Device Port with support for five configurable + endpoints (plus endpoint zero). + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "at91_udc" and force all + gadget drivers to also be dynamically linked. + +config USB_ATMEL_USBA + tristate "Atmel USBA" + select USB_GADGET_DUALSPEED + depends on AVR32 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 + help + USBA is the integrated high-speed USB Device controller on + the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel. + +config USB_FSL_USB2 + tristate "Freescale Highspeed USB DR Peripheral Controller" + depends on FSL_SOC || ARCH_MXC + select USB_GADGET_DUALSPEED + select USB_FSL_MPH_DR_OF if OF + help + Some of Freescale PowerPC processors have a High Speed + Dual-Role(DR) USB controller, which supports device mode. + + The number of programmable endpoints is different through + SOC revisions. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "fsl_usb2_udc" and force + all gadget drivers to also be dynamically linked. + +config USB_FUSB300 + tristate "Faraday FUSB300 USB Peripheral Controller" + depends on !PHYS_ADDR_T_64BIT + select USB_GADGET_DUALSPEED + help + Faraday usb device controller FUSB300 driver + +config USB_OMAP + tristate "OMAP USB Device Controller" + depends on ARCH_OMAP + select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3 || MACH_OMAP_H4_OTG + select USB_OTG_UTILS if ARCH_OMAP + help + Many Texas Instruments OMAP processors have flexible full + speed USB device controllers, with support for up to 30 + endpoints (plus endpoint zero). This driver supports the + controller in the OMAP 1611, and should work with controllers + in other OMAP processors too, given minor tweaks. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "omap_udc" and force all + gadget drivers to also be dynamically linked. + +config USB_PXA25X + tristate "PXA 25x or IXP 4xx" + depends on (ARCH_PXA && PXA25x) || ARCH_IXP4XX + select USB_OTG_UTILS + help + Intel's PXA 25x series XScale ARM-5TE processors include + an integrated full speed USB 1.1 device controller. The + controller in the IXP 4xx series is register-compatible. + + It has fifteen fixed-function endpoints, as well as endpoint + zero (for control transfers). + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "pxa25x_udc" and force all + gadget drivers to also be dynamically linked. + +# if there's only one gadget driver, using only two bulk endpoints, +# don't waste memory for the other endpoints +config USB_PXA25X_SMALL + depends on USB_PXA25X + bool + default n if USB_ETH_RNDIS + default y if USB_ZERO + default y if USB_ETH + default y if USB_G_SERIAL + +config USB_R8A66597 + tristate "Renesas R8A66597 USB Peripheral Controller" + select USB_GADGET_DUALSPEED + help + R8A66597 is a discrete USB host and peripheral controller chip that + supports both full and high speed USB 2.0 data transfers. + It has nine configurable endpoints, and endpoint zero. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "r8a66597_udc" and force all + gadget drivers to also be dynamically linked. + +config USB_RENESAS_USBHS_UDC + tristate 'Renesas USBHS controller' + depends on USB_RENESAS_USBHS + select USB_GADGET_DUALSPEED + help + Renesas USBHS is a discrete USB host and peripheral controller chip + that supports both full and high speed USB 2.0 data transfers. + It has nine or more configurable endpoints, and endpoint zero. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "renesas_usbhs" and force all + gadget drivers to also be dynamically linked. + +config USB_PXA27X + tristate "PXA 27x" + depends on ARCH_PXA && (PXA27x || PXA3xx) + select USB_OTG_UTILS + help + Intel's PXA 27x series XScale ARM v5TE processors include + an integrated full speed USB 1.1 device controller. + + It has up to 23 endpoints, as well as endpoint zero (for + control transfers). + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "pxa27x_udc" and force all + gadget drivers to also be dynamically linked. + +config USB_S3C_HSOTG + tristate "S3C HS/OtG USB Device controller" + depends on S3C_DEV_USB_HSOTG + select USB_GADGET_DUALSPEED + help + The Samsung S3C64XX USB2.0 high-speed gadget controller + integrated into the S3C64XX series SoC. + +config USB_IMX + tristate "Freescale i.MX1 USB Peripheral Controller" + depends on ARCH_MXC + help + Freescale's i.MX1 includes an integrated full speed + USB 1.1 device controller. + + It has Six fixed-function endpoints, as well as endpoint + zero (for control transfers). + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "imx_udc" and force all + gadget drivers to also be dynamically linked. + +config USB_S3C2410 + tristate "S3C2410 USB Device Controller" + depends on ARCH_S3C24XX + help + Samsung's S3C2410 is an ARM-4 processor with an integrated + full speed USB 1.1 device controller. It has 4 configurable + endpoints, as well as endpoint zero (for control transfers). + + This driver has been tested on the S3C2410, S3C2412, and + S3C2440 processors. + +config USB_S3C2410_DEBUG + boolean "S3C2410 udc debug messages" + depends on USB_S3C2410 + +config USB_S3C_HSUDC + tristate "S3C2416, S3C2443 and S3C2450 USB Device Controller" + depends on ARCH_S3C24XX + select USB_GADGET_DUALSPEED + help + Samsung's S3C2416, S3C2443 and S3C2450 is an ARM9 based SoC + integrated with dual speed USB 2.0 device controller. It has + 8 endpoints, as well as endpoint zero. + + This driver has been tested on S3C2416 and S3C2450 processors. + +config USB_MV_UDC + tristate "Marvell USB2.0 Device Controller" + select USB_GADGET_DUALSPEED + help + Marvell Socs (including PXA and MMP series) include a high speed + USB2.0 OTG controller, which can be configured as high speed or + full speed USB peripheral. + +# +# Controllers available in both integrated and discrete versions +# + +# musb builds in ../musb along with host support +config USB_GADGET_MUSB_HDRC + tristate "Inventra HDRC USB Peripheral (TI, ADI, ...)" + depends on USB_MUSB_HDRC + select USB_GADGET_DUALSPEED + help + This OTG-capable silicon IP is used in dual designs including + the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin + +config USB_M66592 + tristate "Renesas M66592 USB Peripheral Controller" + select USB_GADGET_DUALSPEED + help + M66592 is a discrete USB peripheral controller chip that + supports both full and high speed USB 2.0 data transfers. + It has seven configurable endpoints, and endpoint zero. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "m66592_udc" and force all + gadget drivers to also be dynamically linked. + +# +# Controllers available only in discrete form (and all PCI controllers) +# + +config USB_AMD5536UDC + tristate "AMD5536 UDC" + depends on PCI + select USB_GADGET_DUALSPEED + help + The AMD5536 UDC is part of the AMD Geode CS5536, an x86 southbridge. + It is a USB Highspeed DMA capable USB device controller. Beside ep0 + it provides 4 IN and 4 OUT endpoints (bulk or interrupt type). + The UDC port supports OTG operation, and may be used as a host port + if it's not being used to implement peripheral or OTG roles. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "amd5536udc" and force all + gadget drivers to also be dynamically linked. + +config USB_FSL_QE + tristate "Freescale QE/CPM USB Device Controller" + depends on FSL_SOC && (QUICC_ENGINE || CPM) + help + Some of Freescale PowerPC processors have a Full Speed + QE/CPM2 USB controller, which support device mode with 4 + programmable endpoints. This driver supports the + controller in the MPC8360 and MPC8272, and should work with + controllers having QE or CPM2, given minor tweaks. + + Set CONFIG_USB_GADGET to "m" to build this driver as a + dynamically linked module called "fsl_qe_udc". + +config USB_CI13XXX_PCI + tristate "MIPS USB CI13xxx PCI UDC" + depends on PCI + select USB_GADGET_DUALSPEED + help + MIPS USB IP core family device controller + Currently it only supports IP part number CI13412 + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "ci13xxx_udc" and force all + gadget drivers to also be dynamically linked. + +config USB_NET2272 + tristate "PLX NET2272" + select USB_GADGET_DUALSPEED + help + PLX NET2272 is a USB peripheral controller which supports + both full and high speed USB 2.0 data transfers. + + It has three configurable endpoints, as well as endpoint zero + (for control transfer). + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "net2272" and force all + gadget drivers to also be dynamically linked. + +config USB_NET2272_DMA + boolean "Support external DMA controller" + depends on USB_NET2272 + help + The NET2272 part can optionally support an external DMA + controller, but your board has to have support in the + driver itself. + + If unsure, say "N" here. The driver works fine in PIO mode. + +config USB_NET2280 + tristate "NetChip 228x" + depends on PCI + select USB_GADGET_DUALSPEED + help + NetChip 2280 / 2282 is a PCI based USB peripheral controller which + supports both full and high speed USB 2.0 data transfers. + + It has six configurable endpoints, as well as endpoint zero + (for control transfers) and several endpoints with dedicated + functions. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "net2280" and force all + gadget drivers to also be dynamically linked. + +config USB_GOKU + tristate "Toshiba TC86C001 'Goku-S'" + depends on PCI + help + The Toshiba TC86C001 is a PCI device which includes controllers + for full speed USB devices, IDE, I2C, SIO, plus a USB host (OHCI). + + The device controller has three configurable (bulk or interrupt) + endpoints, plus endpoint zero (for control transfers). + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "goku_udc" and to force all + gadget drivers to also be dynamically linked. + +config USB_LANGWELL + tristate "Intel Langwell USB Device Controller" + depends on PCI + depends on !PHYS_ADDR_T_64BIT + select USB_GADGET_DUALSPEED + help + Intel Langwell USB Device Controller is a High-Speed USB + On-The-Go device controller. + + The number of programmable endpoints is different through + controller revision. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "langwell_udc" and force all + gadget drivers to also be dynamically linked. + +config USB_EG20T + tristate "Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7831) UDC" + depends on PCI + select USB_GADGET_DUALSPEED + help + This is a USB device driver for EG20T PCH. + EG20T PCH is the platform controller hub that is used in Intel's + general embedded platform. EG20T PCH has USB device interface. + Using this interface, it is able to access system devices connected + to USB device. + This driver enables USB device function. + USB device is a USB peripheral controller which + supports both full and high speed USB 2.0 data transfers. + This driver supports both control transfer and bulk transfer modes. + This driver dose not support interrupt transfer or isochronous + transfer modes. + + This driver also can be used for LAPIS Semiconductor's ML7213 which is + for IVI(In-Vehicle Infotainment) use. + ML7831 is for general purpose use. + ML7213/ML7831 is companion chip for Intel Atom E6xx series. + ML7213/ML7831 is completely compatible for Intel EG20T PCH. + +config USB_CI13XXX_MSM + tristate "MIPS USB CI13xxx for MSM" + depends on ARCH_MSM + select USB_GADGET_DUALSPEED + select USB_MSM_OTG + help + MSM SoC has chipidea USB controller. This driver uses + ci13xxx_udc core. + This driver depends on OTG driver for PHY initialization, + clock management, powering up VBUS, and power management. + This driver is not supported on boards like trout which + has an external PHY. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "ci13xxx_msm" and force all + gadget drivers to also be dynamically linked. + +config USB_SW_SUNXI_UDC0_SELECT + tristate "SoftWinner SUNXI USB Peripheral Controller" + depends on USB_SW_SUNXI_USB_MANAGER + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + select USB_SW_SUNXI_UDC0 + help + SUNXI USB device/OTG controller driver + + Note: This is a dummy menu item which selects the real driver. Due + to Kconfig limitation in this kernel version it needs to be tristate + as the other driver options. Even if selected to build as module, + this driver will be built in to kernel image. + +# +# LAST -- dummy/emulated controller +# + +config USB_DUMMY_HCD + tristate "Dummy HCD (DEVELOPMENT)" + depends on USB=y || (USB=m && USB_GADGET=m) + select USB_GADGET_DUALSPEED + select USB_GADGET_SUPERSPEED + help + This host controller driver emulates USB, looping all data transfer + requests back to a USB "gadget driver" in the same host. The host + side is the master; the gadget side is the slave. Gadget drivers + can be high, full, or low speed; and they have access to endpoints + like those from NET2280, PXA2xx, or SA1100 hardware. + + This may help in some stages of creating a driver to embed in a + Linux device, since it lets you debug several parts of the gadget + driver without its hardware or drivers being involved. + + Since such a gadget side driver needs to interoperate with a host + side Linux-USB device driver, this may help to debug both sides + of a USB protocol stack. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "dummy_hcd" and force all + gadget drivers to also be dynamically linked. + +# NOTE: Please keep dummy_hcd LAST so that "real hardware" appears +# first and will be selected by default. + +endchoice + +# +# Workaround current module building limitation of sunxi USB +# +config USB_SW_SUNXI_UDC0 + tristate "SoftWinner SUNXI USB Peripheral Controller" + depends on USB_SW_SUNXI_USB_MANAGER + + +# Selected by UDC drivers that support high-speed operation. +config USB_GADGET_DUALSPEED + bool + +# Selected by UDC drivers that support super-speed opperation +config USB_GADGET_SUPERSPEED + bool + depends on USB_GADGET_DUALSPEED + +# +# USB Gadget Drivers +# +choice + tristate "USB Gadget Drivers" + default USB_ETH + help + A Linux "Gadget Driver" talks to the USB Peripheral Controller + driver through the abstract "gadget" API. Some other operating + systems call these "client" drivers, of which "class drivers" + are a subset (implementing a USB device class specification). + A gadget driver implements one or more USB functions using + the peripheral hardware. + + Gadget drivers are hardware-neutral, or "platform independent", + except that they sometimes must understand quirks or limitations + of the particular controllers they work with. For example, when + a controller doesn't support alternate configurations or provide + enough of the right types of endpoints, the gadget driver might + not be able work with that controller, or might need to implement + a less common variant of a device class protocol. + +# this first set of drivers all depend on bulk-capable hardware. + +config USB_ZERO + tristate "Gadget Zero (DEVELOPMENT)" + help + Gadget Zero is a two-configuration device. It either sinks and + sources bulk data; or it loops back a configurable number of + transfers. It also implements control requests, for "chapter 9" + conformance. The driver needs only two bulk-capable endpoints, so + it can work on top of most device-side usb controllers. It's + useful for testing, and is also a working example showing how + USB "gadget drivers" can be written. + + Make this be the first driver you try using on top of any new + USB peripheral controller driver. Then you can use host-side + test software, like the "usbtest" driver, to put your hardware + and its driver through a basic set of functional tests. + + Gadget Zero also works with the host-side "usb-skeleton" driver, + and with many kinds of host-side test software. You may need + to tweak product and vendor IDs before host software knows about + this device, and arrange to select an appropriate configuration. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "g_zero". + +config USB_ZERO_HNPTEST + boolean "HNP Test Device" + depends on USB_ZERO && USB_OTG + help + You can configure this device to enumerate using the device + identifiers of the USB-OTG test device. That means that when + this gadget connects to another OTG device, with this one using + the "B-Peripheral" role, that device will use HNP to let this + one serve as the USB host instead (in the "B-Host" role). + +config USB_AUDIO + tristate "Audio Gadget (EXPERIMENTAL)" + depends on SND + select SND_PCM + help + This Gadget Audio driver is compatible with USB Audio Class + specification 2.0. It implements 1 AudioControl interface, + 1 AudioStreaming Interface each for USB-OUT and USB-IN. + Number of channels, sample rate and sample size can be + specified as module parameters. + This driver doesn't expect any real Audio codec to be present + on the device - the audio streams are simply sinked to and + sourced from a virtual ALSA sound card created. The user-space + application may choose to do whatever it wants with the data + received from the USB Host and choose to provide whatever it + wants as audio data to the USB Host. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "g_audio". + +config GADGET_UAC1 + bool "UAC 1.0 (Legacy)" + depends on USB_AUDIO + help + If you instead want older UAC Spec-1.0 driver that also has audio + paths hardwired to the Audio codec chip on-board and doesn't work + without one. + +config USB_ETH + tristate "Ethernet Gadget (with CDC Ethernet support)" + depends on NET + select CRC32 + help + This driver implements Ethernet style communication, in one of + several ways: + + - The "Communication Device Class" (CDC) Ethernet Control Model. + That protocol is often avoided with pure Ethernet adapters, in + favor of simpler vendor-specific hardware, but is widely + supported by firmware for smart network devices. + + - On hardware can't implement that protocol, a simple CDC subset + is used, placing fewer demands on USB. + + - CDC Ethernet Emulation Model (EEM) is a newer standard that has + a simpler interface that can be used by more USB hardware. + + RNDIS support is an additional option, more demanding than than + subset. + + Within the USB device, this gadget driver exposes a network device + "usbX", where X depends on what other networking devices you have. + Treat it like a two-node Ethernet link: host, and gadget. + + The Linux-USB host-side "usbnet" driver interoperates with this + driver, so that deep I/O queues can be supported. On 2.4 kernels, + use "CDCEther" instead, if you're using the CDC option. That CDC + mode should also interoperate with standard CDC Ethernet class + drivers on other host operating systems. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "g_ether". + +config USB_ETH_RNDIS + bool "RNDIS support" + depends on USB_ETH + default y + help + Microsoft Windows XP bundles the "Remote NDIS" (RNDIS) protocol, + and Microsoft provides redistributable binary RNDIS drivers for + older versions of Windows. + + If you say "y" here, the Ethernet gadget driver will try to provide + a second device configuration, supporting RNDIS to talk to such + Microsoft USB hosts. + + To make MS-Windows work with this, use Documentation/usb/linux.inf + as the "driver info file". For versions of MS-Windows older than + XP, you'll need to download drivers from Microsoft's website; a URL + is given in comments found in that info file. + +config USB_ETH_EEM + bool "Ethernet Emulation Model (EEM) support" + depends on USB_ETH + default n + help + CDC EEM is a newer USB standard that is somewhat simpler than CDC ECM + and therefore can be supported by more hardware. Technically ECM and + EEM are designed for different applications. The ECM model extends + the network interface to the target (e.g. a USB cable modem), and the + EEM model is for mobile devices to communicate with hosts using + ethernet over USB. For Linux gadgets, however, the interface with + the host is the same (a usbX device), so the differences are minimal. + + If you say "y" here, the Ethernet gadget driver will use the EEM + protocol rather than ECM. If unsure, say "n". + +config USB_G_NCM + tristate "Network Control Model (NCM) support" + depends on NET + select CRC32 + help + This driver implements USB CDC NCM subclass standard. NCM is + an advanced protocol for Ethernet encapsulation, allows grouping + of several ethernet frames into one USB transfer and different + alignment possibilities. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "g_ncm". + +config USB_GADGETFS + tristate "Gadget Filesystem (EXPERIMENTAL)" + depends on EXPERIMENTAL + help + This driver provides a filesystem based API that lets user mode + programs implement a single-configuration USB device, including + endpoint I/O and control requests that don't relate to enumeration. + All endpoints, transfer speeds, and transfer types supported by + the hardware are available, through read() and write() calls. + + Currently, this option is still labelled as EXPERIMENTAL because + of existing race conditions in the underlying in-kernel AIO core. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "gadgetfs". + +config USB_FUNCTIONFS + tristate "Function Filesystem (EXPERIMENTAL)" + depends on EXPERIMENTAL + select USB_FUNCTIONFS_GENERIC if !(USB_FUNCTIONFS_ETH || USB_FUNCTIONFS_RNDIS) + help + The Function Filesystem (FunctionFS) lets one create USB + composite functions in user space in the same way GadgetFS + lets one create USB gadgets in user space. This allows creation + of composite gadgets such that some of the functions are + implemented in kernel space (for instance Ethernet, serial or + mass storage) and other are implemented in user space. + + If you say "y" or "m" here you will be able what kind of + configurations the gadget will provide. + + Say "y" to link the driver statically, or "m" to build + a dynamically linked module called "g_ffs". + +config USB_FUNCTIONFS_ETH + bool "Include configuration with CDC ECM (Ethernet)" + depends on USB_FUNCTIONFS && NET + help + Include a configuration with CDC ECM function (Ethernet) and the + Function Filesystem. + +config USB_FUNCTIONFS_RNDIS + bool "Include configuration with RNDIS (Ethernet)" + depends on USB_FUNCTIONFS && NET + help + Include a configuration with RNDIS function (Ethernet) and the Filesystem. + +config USB_FUNCTIONFS_GENERIC + bool "Include 'pure' configuration" + depends on USB_FUNCTIONFS + help + Include a configuration with the Function Filesystem alone with + no Ethernet interface. + +config USB_FILE_STORAGE + tristate "File-backed Storage Gadget (DEPRECATED)" + depends on BLOCK + help + The File-backed Storage Gadget acts as a USB Mass Storage + disk drive. As its storage repository it can use a regular + file or a block device (in much the same way as the "loop" + device driver), specified as a module parameter. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "g_file_storage". + + NOTE: This driver is deprecated. Its replacement is the + Mass Storage Gadget. + +config USB_FILE_STORAGE_TEST + bool "File-backed Storage Gadget testing version" + depends on USB_FILE_STORAGE + default n + help + Say "y" to generate the larger testing version of the + File-backed Storage Gadget, useful for probing the + behavior of USB Mass Storage hosts. Not needed for + normal operation. + +config USB_MASS_STORAGE + tristate "Mass Storage Gadget" + depends on BLOCK + help + The Mass Storage Gadget acts as a USB Mass Storage disk drive. + As its storage repository it can use a regular file or a block + device (in much the same way as the "loop" device driver), + specified as a module parameter or sysfs option. + + This driver is an updated replacement for the deprecated + File-backed Storage Gadget (g_file_storage). + + Say "y" to link the driver statically, or "m" to build + a dynamically linked module called "g_mass_storage". + +config USB_G_SERIAL + tristate "Serial Gadget (with CDC ACM and CDC OBEX support)" + help + The Serial Gadget talks to the Linux-USB generic serial driver. + This driver supports a CDC-ACM module option, which can be used + to interoperate with MS-Windows hosts or with the Linux-USB + "cdc-acm" driver. + + This driver also supports a CDC-OBEX option. You will need a + user space OBEX server talking to /dev/ttyGS*, since the kernel + itself doesn't implement the OBEX protocol. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "g_serial". + + For more information, see Documentation/usb/gadget_serial.txt + which includes instructions and a "driver info file" needed to + make MS-Windows work with CDC ACM. + +config USB_MIDI_GADGET + tristate "MIDI Gadget (EXPERIMENTAL)" + depends on SND && EXPERIMENTAL + select SND_RAWMIDI + help + The MIDI Gadget acts as a USB Audio device, with one MIDI + input and one MIDI output. These MIDI jacks appear as + a sound "card" in the ALSA sound system. Other MIDI + connections can then be made on the gadget system, using + ALSA's aconnect utility etc. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "g_midi". + +config USB_G_PRINTER + tristate "Printer Gadget" + help + The Printer Gadget channels data between the USB host and a + userspace program driving the print engine. The user space + program reads and writes the device file /dev/g_printer to + receive or send printer data. It can use ioctl calls to + the device file to get or set printer status. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "g_printer". + + For more information, see Documentation/usb/gadget_printer.txt + which includes sample code for accessing the device file. + +config USB_G_ANDROID + boolean "Android Composite Gadget" + help + The Android Composite Gadget supports multiple USB + functions: adb, acm, mass storage, mtp, accessory + and rndis. + Each function can be configured and enabled/disabled + dynamically from userspace through a sysfs interface. + +config USB_CDC_COMPOSITE + tristate "CDC Composite Device (Ethernet and ACM)" + depends on NET + help + This driver provides two functions in one configuration: + a CDC Ethernet (ECM) link, and a CDC ACM (serial port) link. + + This driver requires four bulk and two interrupt endpoints, + plus the ability to handle altsettings. Not all peripheral + controllers are that capable. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module. + +config USB_G_NOKIA + tristate "Nokia composite gadget" + depends on PHONET + help + The Nokia composite gadget provides support for acm, obex + and phonet in only one composite gadget driver. + + It's only really useful for N900 hardware. If you're building + a kernel for N900, say Y or M here. If unsure, say N. + +config USB_G_ACM_MS + tristate "CDC Composite Device (ACM and mass storage)" + depends on BLOCK + help + This driver provides two functions in one configuration: + a mass storage, and a CDC ACM (serial port) link. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "g_acm_ms". + +config USB_G_MULTI + tristate "Multifunction Composite Gadget (EXPERIMENTAL)" + depends on BLOCK && NET + select USB_G_MULTI_CDC if !USB_G_MULTI_RNDIS + help + The Multifunction Composite Gadget provides Ethernet (RNDIS + and/or CDC Ethernet), mass storage and ACM serial link + interfaces. + + You will be asked to choose which of the two configurations is + to be available in the gadget. At least one configuration must + be chosen to make the gadget usable. Selecting more than one + configuration will prevent Windows from automatically detecting + the gadget as a composite gadget, so an INF file will be needed to + use the gadget. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "g_multi". + +config USB_G_MULTI_RNDIS + bool "RNDIS + CDC Serial + Storage configuration" + depends on USB_G_MULTI + default y + help + This option enables a configuration with RNDIS, CDC Serial and + Mass Storage functions available in the Multifunction Composite + Gadget. This is the configuration dedicated for Windows since RNDIS + is Microsoft's protocol. + + If unsure, say "y". + +config USB_G_MULTI_CDC + bool "CDC Ethernet + CDC Serial + Storage configuration" + depends on USB_G_MULTI + default n + help + This option enables a configuration with CDC Ethernet (ECM), CDC + Serial and Mass Storage functions available in the Multifunction + Composite Gadget. + + If unsure, say "y". + +config USB_G_HID + tristate "HID Gadget" + help + The HID gadget driver provides generic emulation of USB + Human Interface Devices (HID). + + For more information, see Documentation/usb/gadget_hid.txt which + includes sample code for accessing the device files. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "g_hid". + +config USB_G_DBGP + tristate "EHCI Debug Device Gadget" + help + This gadget emulates an EHCI Debug device. This is useful when you want + to interact with an EHCI Debug Port. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "g_dbgp". + +if USB_G_DBGP +choice + prompt "EHCI Debug Device mode" + default USB_G_DBGP_SERIAL + +config USB_G_DBGP_PRINTK + depends on USB_G_DBGP + bool "printk" + help + Directly printk() received data. No interaction. + +config USB_G_DBGP_SERIAL + depends on USB_G_DBGP + bool "serial" + help + Userland can interact using /dev/ttyGSxxx. +endchoice +endif + +# put drivers that need isochronous transfer support (for audio +# or video class gadget drivers), or specific hardware, here. +config USB_G_WEBCAM + tristate "USB Webcam Gadget" + depends on VIDEO_DEV + help + The Webcam Gadget acts as a composite USB Audio and Video Class + device. It provides a userspace API to process UVC control requests + and stream video data to the host. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "g_webcam". + +endchoice + +endif # USB_GADGET diff --git a/patch/linux-sunxi/drivers/usb/sunxi_usb/Kconfig b/patch/linux-sunxi/drivers/usb/sunxi_usb/Kconfig new file mode 100644 index 0000000..831db08 --- /dev/null +++ b/patch/linux-sunxi/drivers/usb/sunxi_usb/Kconfig @@ -0,0 +1,74 @@ +# +# softwinner SUNXI USB2.0 Dual Role Controller Driver. +# + +#--------------------------------------------- +#- +#- config USB2.0 Dual Role Controller. +#- +#--------------------------------------------- +menuconfig USB_SW_SUNXI_USB + boolean "SUNXI USB2.0 Dual Role Controller support" + depends on (ARCH_SUN4I || ARCH_SUN5I || ARCH_SUN7I) && USB_MUSB_SUNXI=n + help + SUNXI USB2.0 Dual Role Controller + +config USB_SW_SUNXI_USB_MANAGER + boolean "SUNXI USB2.0 Manager" + depends on USB_SW_SUNXI_USB + help + manager all usb controller. + +#--------------------------------------------- +#- +#- usb0 mode select. +#- +#--------------------------------------------- +choice + + prompt "USB0 Controller support" + depends on (USB_SW_SUNXI_USB && USB_SW_SUNXI_USB_MANAGER) + default USB_SW_SUNXI_USB0_OTG + help + usb0 Controller mode select. choice "device only", then usb0 can only use for device. + choice "host only", then usb0 can only use for host. choice "OTG", then usb0 can only + use device and host. + + For "device only" and "OTG" modes, you need CONFIG_USB_SW_SUNXI_UDC0, "SoftWinner + SUNXI USB Peripheral Controller", enabled under USB gadget config. + +config USB_SW_SUNXI_USB0_HOST_ONLY + boolean "host only support" + select USB_SW_SUNXI_HCD0 + help + usb0 can only use for host. + +config USB_SW_SUNXI_USB0_OTG + boolean "otg support" + select USB_SW_SUNXI_HCD0 + select USB_SW_SUNXI_UDC0 + help + usb0 can only use for device and host. + +config USB_SW_SUNXI_USB0_DEVICE_ONLY + boolean "device only support" + select USB_SW_SUNXI_UDC0 +# depends on USB_SW_SUNXI_UDC0 + depends on USB_GADGET + help + usb0 can only use for device. + +config USB_SW_SUNXI_USB0_NULL + boolean "usb manager not support" + help + usb0 do not monitor hardware, then driver insmod should by application. + + + +endchoice + +config USB_SW_SUNXI_USB_DEBUG + tristate "SUNXI USB driver debug message" + depends on USB_SW_SUNXI_USB + help + SUNXI USB driver debug message. diff --git a/patch/linux-sunxi/drivers/usb/sunxi_usb/udc/sw_udc.c b/patch/linux-sunxi/drivers/usb/sunxi_usb/udc/sw_udc.c new file mode 100644 index 0000000..17f9567 --- /dev/null +++ b/patch/linux-sunxi/drivers/usb/sunxi_usb/udc/sw_udc.c @@ -0,0 +1,3869 @@ +/* + * drivers/usb/sunxi_usb/udc/sw_udc.c + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * javen + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "sw_udc_config.h" +#include "sw_udc_board.h" + +#include "sw_udc_debug.h" +#include "sw_udc_dma.h" + +//--------------------------------------------------------------- +// 宏 定义 +//--------------------------------------------------------------- +#define DRIVER_DESC "SoftWinner USB Device Controller" +#define DRIVER_VERSION "20080411" +#define DRIVER_AUTHOR "SoftWinner USB Developer" + +//--------------------------------------------------------------- +// 全局变量 定义 +//--------------------------------------------------------------- +static const char gadget_name[] = "sw_usb_udc"; +static const char driver_desc[] = DRIVER_DESC; + +static struct sw_udc *the_controller = NULL; +static u32 usbd_port_no = 0; +static sw_udc_io_t g_sw_udc_io; +static u32 usb_connect = 0; +static u32 is_controller_alive = 0; +static u8 is_udc_enable = 0; /* is udc enable by gadget? */ + +//#ifdef CONFIG_USB_SW_SUNXI_USB0_OTG +static struct platform_device *g_udc_pdev = NULL; +//#endif + +static u8 crq_bRequest = 0; +static const unsigned char TestPkt[54] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xEE, 0xEE, 0xEE, + 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xBF, 0xDF, + 0xEF, 0xF7, 0xFB, 0xFD, 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, + 0xFB, 0xFD, 0x7E, 0x00}; + +//--------------------------------------------------------------- +// 函数 定义 +//--------------------------------------------------------------- + +/*满足DMA传输的条件如下: + * 1、驱动支持DMA传输 + * 2、非ep0 + * 3、大于一个包 + */ +#define is_sw_udc_dma_capable(len, maxpacket, epnum) (is_udc_support_dma() \ + && (len > maxpacket) \ + && epnum) + + +static void cfg_udc_command(enum sw_udc_cmd_e cmd); +static void cfg_vbus_draw(unsigned int ma); + +static __u32 is_peripheral_active(void) +{ + return is_controller_alive; +} + +/* +********************************************************** +* 关USB模块中断 +********************************************************** +*/ +static void disable_irq_udc(struct sw_udc *dev) +{ +// disable_irq(dev->irq_no); +} + +/* +********************************************************** +* 开USB模块中断 +********************************************************** +*/ +static void enable_irq_udc(struct sw_udc *dev) +{ +// enable_irq(dev->irq_no); +} + +/* +******************************************************************************* +* sw_udc_udc_done +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static void sw_udc_done(struct sw_udc_ep *ep, + struct sw_udc_request *req, int status) +{ + unsigned halted = ep->halted; + + DMSG_TEST("d: ep(0x%p, %d), req(0x%p, 0x%p, %d, %d)\n\n", + ep, ep->num, + req, &(req->req), req->req.length, req->req.actual); + + //DMSG_INFO("d: (0x%p, %d, %d)\n\n", &(req->req), req->req.length, req->req.actual); + //DMSG_INFO("d\n\n"); + + list_del_init(&req->queue); + + if (likely (req->req.status == -EINPROGRESS)) + req->req.status = status; + else + status = req->req.status; + + ep->halted = 1; + spin_unlock(&ep->dev->lock); + req->req.complete(&ep->ep, &req->req); + spin_lock(&ep->dev->lock); + ep->halted = halted; +} + +/* +******************************************************************************* +* sw_udc_nuke +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static void sw_udc_nuke(struct sw_udc *udc, struct sw_udc_ep *ep, int status) +{ + /* Sanity check */ + if (&ep->queue == NULL) + return; + + while (!list_empty (&ep->queue)) { + struct sw_udc_request *req; + req = list_entry (ep->queue.next, struct sw_udc_request, + queue); + DMSG_INFO("nuke: ep num is %d\n", ep->num); + sw_udc_done(ep, req, status); + } +} + +/* +******************************************************************************* +* sw_udc_clear_ep_state +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static inline void sw_udc_clear_ep_state(struct sw_udc *dev) +{ + unsigned i = 0; + + /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint + * fifos, and pending transactions mustn't be continued in any case. + */ + + for (i = 1; i < SW_UDC_ENDPOINTS; i++){ + sw_udc_nuke(dev, &dev->ep[i], -ECONNABORTED); + } +} + +/* +******************************************************************************* +* sw_udc_fifo_count_out +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static inline int sw_udc_fifo_count_out(__hdle usb_bsp_hdle, __u8 ep_index) +{ + if(ep_index){ + return USBC_ReadLenFromFifo(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX); + }else{ + return USBC_ReadLenFromFifo(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0); + } +} + +/* +******************************************************************************* +* sw_udc_write_packet +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static inline int sw_udc_write_packet(int fifo, + struct sw_udc_request *req, + unsigned max) +{ + unsigned len = min(req->req.length - req->req.actual, max); + u8 *buf = req->req.buf + req->req.actual; + + prefetch(buf); + + DMSG_DBG_UDC("W: req.actual(%d), req.length(%d), len(%d), total(%d)\n", + req->req.actual, req->req.length, len, req->req.actual + len); + + req->req.actual += len; + + udelay(5); + USBC_WritePacket(g_sw_udc_io.usb_bsp_hdle, fifo, len, buf); + + return len; +} + +/* +******************************************************************************* +* pio_write_fifo +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int pio_write_fifo(struct sw_udc_ep *ep, struct sw_udc_request *req) +{ + unsigned count = 0; + int is_last = 0; + u32 idx = 0; + int fifo_reg = 0; + __s32 ret = 0; + u8 old_ep_index = 0; + + idx = ep->bEndpointAddress & 0x7F; + + /* select ep */ + old_ep_index = USBC_GetActiveEp(g_sw_udc_io.usb_bsp_hdle); + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, idx); + + /* select fifo */ + fifo_reg = USBC_SelectFIFO(g_sw_udc_io.usb_bsp_hdle, idx); + + count = sw_udc_write_packet(fifo_reg, req, ep->ep.maxpacket); + + /* last packet is often short (sometimes a zlp) */ + if(count != ep->ep.maxpacket){ + is_last = 1; + }else if (req->req.length != req->req.actual || req->req.zero){ + is_last = 0; + }else{ + is_last = 2; + } + + DMSG_TEST("pw: ep(0x%p, %d), req(0x%p, 0x%p, %d, %d), cnt(%d, %d)\n", + ep, ep->num, + req, &(req->req), req->req.length, req->req.actual, + count, is_last); + + if(idx){ //ep1~4 + ret = USBC_Dev_WriteDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX, is_last); + if(ret != 0){ + DMSG_PANIC("ERR: USBC_Dev_WriteDataStatus, failed\n"); + req->req.status = -EOVERFLOW; + } + }else{ //ep0 + ret = USBC_Dev_WriteDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, is_last); + if(ret != 0){ + DMSG_PANIC("ERR: USBC_Dev_WriteDataStatus, failed\n"); + req->req.status = -EOVERFLOW; + } + } + + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, old_ep_index); + + if(is_last){ + if (!idx) { /* ep0 */ + ep->dev->ep0state=EP0_IDLE; + sw_udc_done(ep, req, 0); + } + + is_last = 1; + } + + return is_last; +} + +/* +******************************************************************************* +* dma_write_fifo +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int dma_write_fifo(struct sw_udc_ep *ep, struct sw_udc_request *req) +{ + u32 left_len = 0; + u32 idx = 0; + int fifo_reg = 0; + u8 old_ep_index = 0; + + DMSG_TEST("dw: ep(0x%p, %d), req(0x%p, 0x%p, %d, %d)\n", + ep, ep->num, + req, &(req->req), req->req.length, req->req.actual); + + if(ep->dma_working){ +/* + DMSG_PANIC("ERR: dma is busy, write fifo. ep(0x%p, %d), req(0x%p, 0x%p, 0x%x, %d, %d)\n\n", + ep, ep->num, + req, &(req->req), (u32)req->req.buf, req->req.length, req->req.actual); +*/ + return 0; + } + + idx = ep->bEndpointAddress & 0x7F; + + /* select ep */ + old_ep_index = USBC_GetActiveEp(g_sw_udc_io.usb_bsp_hdle); + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, idx); + + /* select fifo */ + fifo_reg = USBC_SelectFIFO(g_sw_udc_io.usb_bsp_hdle, idx); + + /* auto_set, tx_mode, dma_tx_en, mode1 */ + USBC_Dev_ConfigEpDma(ep->dev->sw_udc_io->usb_bsp_hdle, USBC_EP_TYPE_TX); + + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, old_ep_index); + + /* 截取非整包部分 */ + left_len = req->req.length - req->req.actual; + left_len = left_len - (left_len % ep->ep.maxpacket); + + ep->dma_working = 1; + ep->dma_transfer_len = left_len; + + sw_udc_dma_set_config(ep, req, (__u32)req->req.buf, left_len); + sw_udc_dma_start(ep, fifo_reg, (__u32)req->req.buf, left_len); + + return 0; +} + +/* +******************************************************************************* +* sw_udc_write_fifo +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* 0 = still running, 1 = completed, negative = errno +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_write_fifo(struct sw_udc_ep *ep, struct sw_udc_request *req) +{ + if(is_sw_udc_dma_capable((req->req.length - req->req.actual), ep->ep.maxpacket, ep->num)){ + return dma_write_fifo(ep, req); + }else{ + return pio_write_fifo(ep, req); + } +} + +/* +******************************************************************************* +* sw_udc_read_packet +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static inline int sw_udc_read_packet(int fifo, u8 *buf, + struct sw_udc_request *req, unsigned avail) +{ + unsigned len = 0; + + len = min(req->req.length - req->req.actual, avail); + req->req.actual += len; + + DMSG_DBG_UDC("R: req.actual(%d), req.length(%d), len(%d), total(%d)\n", + req->req.actual, req->req.length, len, req->req.actual + len); + + USBC_ReadPacket(g_sw_udc_io.usb_bsp_hdle, fifo, len, buf); + + return len; +} + +/* +******************************************************************************* +* pio_read_fifo +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* 0 = still running, 1 = completed, negative = errno +* +* note: +* void +* +******************************************************************************* +*/ +static int pio_read_fifo(struct sw_udc_ep *ep, struct sw_udc_request *req) +{ + u8 *buf = NULL; + unsigned bufferspace = 0; + int is_last = 1; + unsigned avail = 0; + int fifo_count = 0; + u32 idx = 0; + int fifo_reg = 0; + __s32 ret = 0; + u8 old_ep_index = 0; + + idx = ep->bEndpointAddress & 0x7F; + + /* select fifo */ + fifo_reg = USBC_SelectFIFO(g_sw_udc_io.usb_bsp_hdle, idx); + + if(!req->req.length){ + DMSG_PANIC("ERR: req->req.length == 0\n"); + return 1; + } + + buf = req->req.buf + req->req.actual; + bufferspace = req->req.length - req->req.actual; + if (!bufferspace) { + DMSG_PANIC("ERR: buffer full!\n"); + return -1; + } + + /* select ep */ + old_ep_index = USBC_GetActiveEp(g_sw_udc_io.usb_bsp_hdle); + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, idx); + + fifo_count = sw_udc_fifo_count_out(g_sw_udc_io.usb_bsp_hdle, idx); + if(fifo_count > ep->ep.maxpacket){ + avail = ep->ep.maxpacket; + }else{ + avail = fifo_count; + } + + fifo_count = sw_udc_read_packet(fifo_reg, buf, req, avail); + + /* checking this with ep0 is not accurate as we already + * read a control request + **/ + if (idx != 0 && fifo_count < ep->ep.maxpacket) { + is_last = 1; + /* overflowed this request? flush extra data */ + if (fifo_count != avail) + req->req.status = -EOVERFLOW; + } else { + is_last = (req->req.length <= req->req.actual) ? 1 : 0; + } + + DMSG_TEST("pr: ep(0x%p, %d), req(0x%p, 0x%p, %d, %d), cnt(%d, %d)\n", + ep, ep->num, + req, &(req->req), req->req.length, req->req.actual, + fifo_count, is_last); + + if (idx){ + ret = USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX, is_last); + if(ret != 0){ + DMSG_PANIC("ERR: pio_read_fifo: USBC_Dev_WriteDataStatus, failed\n"); + req->req.status = -EOVERFLOW; + } + }else{ + ret = USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, is_last); + if(ret != 0){ + DMSG_PANIC("ERR: pio_read_fifo: USBC_Dev_WriteDataStatus, failed\n"); + req->req.status = -EOVERFLOW; + } + } + + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, old_ep_index); + + if(is_last){ + if(!idx){ + ep->dev->ep0state = EP0_IDLE; + } + + sw_udc_done(ep, req, 0); + is_last = 1; + } + + return is_last; +} + +/* +******************************************************************************* +* dma_read_fifo +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int dma_read_fifo(struct sw_udc_ep *ep, struct sw_udc_request *req) +{ + u32 left_len = 0; + u32 idx = 0; + int fifo_reg = 0; + u8 old_ep_index = 0; + + DMSG_TEST("dr: ep(0x%p, %d), req(0x%p, 0x%p, %d, %d)\n", + ep, ep->num, + req, &(req->req), req->req.length, req->req.actual); + + if(ep->dma_working){ +/* + DMSG_PANIC("ERR: dma is busy, read fifo. ep(0x%p, %d), req(0x%p, 0x%p, 0x%x, %d, %d)\n\n", + ep, ep->num, + req, &(req->req), (u32)req->req.buf, req->req.length, req->req.actual); +*/ + return 0; + } + + idx = ep->bEndpointAddress & 0x7F; + + /* select ep */ + old_ep_index = USBC_GetActiveEp(g_sw_udc_io.usb_bsp_hdle); + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, idx); + + /* select fifo */ + fifo_reg = USBC_SelectFIFO(g_sw_udc_io.usb_bsp_hdle, idx); + + /* auto_set, tx_mode, dma_tx_en, mode1 */ + USBC_Dev_ConfigEpDma(ep->dev->sw_udc_io->usb_bsp_hdle, USBC_EP_TYPE_RX); + + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, old_ep_index); + + /* 截取非整包部分 */ + left_len = req->req.length - req->req.actual; + left_len = left_len - (left_len % ep->ep.maxpacket); + + ep->dma_working = 1; + ep->dma_transfer_len = left_len; + sw_udc_dma_set_config(ep, req, (__u32)req->req.buf, left_len); + sw_udc_dma_start(ep, fifo_reg, (__u32)req->req.buf, left_len); + + return 0; +} + +/* +******************************************************************************* +* sw_udc_read_fifo +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* 0 = still running, 1 = completed, negative = errno +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_read_fifo(struct sw_udc_ep *ep, struct sw_udc_request *req) +{ + if(is_sw_udc_dma_capable((req->req.length - req->req.actual), ep->ep.maxpacket, ep->num)){ + return dma_read_fifo(ep, req); + }else{ + return pio_read_fifo(ep, req); + } +} + +/* +******************************************************************************* +* sw_udc_read_fifo_crq +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_read_fifo_crq(struct usb_ctrlrequest *crq) +{ + u32 fifo_count = 0; + u32 i = 0; + u8 *pOut = (u8 *) crq; + u32 fifo = 0; + + fifo = USBC_SelectFIFO(g_sw_udc_io.usb_bsp_hdle, 0); + fifo_count = USBC_ReadLenFromFifo(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0); + + if(fifo_count != 8){ + i = 0; + + while(i < 16 && (fifo_count != 8) ){ + fifo_count = USBC_ReadLenFromFifo(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0); + i++; + } + + if(i >= 16){ + DMSG_PANIC("ERR: get ep0 fifo len failed\n"); + } + } + + return USBC_ReadPacket(g_sw_udc_io.usb_bsp_hdle, fifo, fifo_count, pOut); +} + +/* +******************************************************************************* +* sw_udc_get_status +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_get_status(struct sw_udc *dev, struct usb_ctrlrequest *crq) +{ + u16 status = 0; + u8 buf[8]; + u8 ep_num = crq->wIndex & 0x7F; + u8 is_in = crq->wIndex & USB_DIR_IN; + u32 fifo = 0; + + switch (crq->bRequestType & USB_RECIP_MASK) { + case USB_RECIP_INTERFACE: + buf[0] = 0x00; + buf[1] = 0x00; + break; + + case USB_RECIP_DEVICE: + status = dev->devstatus; + buf[0] = 0x01; + buf[1] = 0x00; + break; + + case USB_RECIP_ENDPOINT: + if (ep_num > 4 || crq->wLength > 2){ + return 1; + } + + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, ep_num); + if (ep_num == 0) { + status = USBC_Dev_IsEpStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0); + } else { + if (is_in) { + status = USBC_Dev_IsEpStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX); + } else { + status = USBC_Dev_IsEpStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX); + } + } + status = status ? 1 : 0; + if (status) { + buf[0] = 0x01; + buf[1] = 0x00; + } else { + buf[0] = 0x00; + buf[1] = 0x00; + } + break; + + default: + return 1; + } + + /* Seems to be needed to get it working. ouch :( */ + udelay(5); + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 0); + + fifo = USBC_SelectFIFO(g_sw_udc_io.usb_bsp_hdle, 0); + USBC_WritePacket(g_sw_udc_io.usb_bsp_hdle, fifo, crq->wLength, buf); + USBC_Dev_WriteDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + + return 0; +} + +static int sw_udc_set_halt(struct usb_ep *_ep, int value); + +#if 1 + +/* +******************************************************************************* +* sw_udc_handle_ep0_idle +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static void sw_udc_handle_ep0_idle(struct sw_udc *dev, + struct sw_udc_ep *ep, + struct usb_ctrlrequest *crq, + u32 ep0csr) +{ + int len = 0, ret = 0, tmp = 0; + + /* start control request? */ + if (!USBC_Dev_IsReadDataReady(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0)){ + DMSG_WRN("ERR: data is ready, can not read data.\n"); + return; + } + + sw_udc_nuke(dev, ep, -EPROTO); + + len = sw_udc_read_fifo_crq(crq); + if (len != sizeof(*crq)) { + DMSG_PANIC("setup begin: fifo READ ERROR" + " wanted %d bytes got %d. Stalling out...\n", + sizeof(*crq), len); + + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 0); + USBC_Dev_EpSendStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0); + + return; + } + + DMSG_DBG_UDC("ep0: bRequest = %d bRequestType %d wLength = %d\n", + crq->bRequest, crq->bRequestType, crq->wLength); + + /* cope with automagic for some standard requests. */ + dev->req_std = ((crq->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD); + dev->req_config = 0; + dev->req_pending = 1; + + if(dev->req_std){ //standard request + switch (crq->bRequest) { + case USB_REQ_SET_CONFIGURATION: + DMSG_DBG_UDC("USB_REQ_SET_CONFIGURATION ... \n"); + + if (crq->bRequestType == USB_RECIP_DEVICE) { + dev->req_config = 1; + } + break; + + case USB_REQ_SET_INTERFACE: + DMSG_DBG_UDC("USB_REQ_SET_INTERFACE ... \n"); + + if (crq->bRequestType == USB_RECIP_INTERFACE) { + dev->req_config = 1; + } + break; + + case USB_REQ_SET_ADDRESS: + DMSG_DBG_UDC("USB_REQ_SET_ADDRESS ... \n"); + + if (crq->bRequestType == USB_RECIP_DEVICE) { + tmp = crq->wValue & 0x7F; + dev->address = tmp; + + //rx接收完毕、dataend、tx_pakect准备就绪 + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + + dev->ep0state = EP0_END_XFER; + + crq_bRequest = USB_REQ_SET_ADDRESS; + + return; + } + break; + + case USB_REQ_GET_STATUS: + DMSG_DBG_UDC("USB_REQ_GET_STATUS ... \n"); + + if (!sw_udc_get_status(dev, crq)) { + return; + } + break; + + case USB_REQ_CLEAR_FEATURE: + //--<1>--数据方向必须为 host to device + if(x_test_bit(crq->bRequestType, 7)){ + DMSG_PANIC("USB_REQ_CLEAR_FEATURE: data is not host to device\n"); + break; + } + + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + + //--<3>--数据阶段 + if(crq->bRequestType == USB_RECIP_DEVICE){ + /* wValue 0-1 */ + if(crq->wValue){ + dev->devstatus &= ~(1 << USB_DEVICE_REMOTE_WAKEUP); + }else{ + int k = 0; + for(k = 0;k < SW_UDC_ENDPOINTS;k++){ + sw_udc_set_halt(&dev->ep[k].ep, 0); + } + } + + }else if(crq->bRequestType == USB_RECIP_INTERFACE){ + //--<2>--令牌阶段结束 + + //不处理 + + }else if(crq->bRequestType == USB_RECIP_ENDPOINT){ + //--<3>--解除禁用ep + //sw_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0); + //dev->devstatus &= ~(1 << USB_DEVICE_REMOTE_WAKEUP); + /* wValue 0-1 */ + if(crq->wValue){ + dev->devstatus &= ~(1 << USB_DEVICE_REMOTE_WAKEUP); + }else{ + sw_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0); + } + + }else{ + DMSG_PANIC("PANIC : nonsupport set feature request. (%d)\n", crq->bRequestType); + USBC_Dev_EpSendStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0); + } + + dev->ep0state = EP0_IDLE; + + return; + //break; + + case USB_REQ_SET_FEATURE: + //--<1>--数据方向必须为 host to device + if(x_test_bit(crq->bRequestType, 7)){ + DMSG_PANIC("USB_REQ_SET_FEATURE: data is not host to device\n"); + break; + } + + //--<3>--数据阶段 + if(crq->bRequestType == USB_RECIP_DEVICE){ + if((crq->wValue == USB_DEVICE_TEST_MODE) && (crq->wIndex == 0x0400)){ + //setup packet包接收完毕 + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + + dev->ep0state = EP0_END_XFER; + crq_bRequest = USB_REQ_SET_FEATURE; + + return; + } + + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + dev->devstatus |= (1 << USB_DEVICE_REMOTE_WAKEUP); + }else if(crq->bRequestType == USB_RECIP_INTERFACE){ + //--<2>--令牌阶段结束 + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + //不处理 + + }else if(crq->bRequestType == USB_RECIP_ENDPOINT){ + //--<3>--禁用ep + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + sw_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1); + }else{ + DMSG_PANIC("PANIC : nonsupport set feature request. (%d)\n", crq->bRequestType); + + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + USBC_Dev_EpSendStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0); + } + + dev->ep0state = EP0_IDLE; + + return; + //break; + + default: + /* 只收setup数据包，不能置DataEnd */ + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 0); + break; + } + }else{ + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 0); + } + + if(crq->bRequestType & USB_DIR_IN){ + dev->ep0state = EP0_IN_DATA_PHASE; + }else{ + dev->ep0state = EP0_OUT_DATA_PHASE; + } + + spin_unlock(&dev->lock); + ret = dev->driver->setup(&dev->gadget, crq); + spin_lock(&dev->lock); + if (ret < 0) { + if (dev->req_config) { + DMSG_PANIC("ERR: config change %02x fail %d?\n", crq->bRequest, ret); + return; + } + + if(ret == -EOPNOTSUPP){ + DMSG_PANIC("ERR: Operation not supported\n"); + }else{ + DMSG_PANIC("ERR: dev->driver->setup failed. (%d)\n", ret); + } + + udelay(5); + + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + USBC_Dev_EpSendStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0); + + dev->ep0state = EP0_IDLE; + /* deferred i/o == no response yet */ + } else if (dev->req_pending) { +// DMSG_PANIC("ERR: dev->req_pending... what now?\n"); + dev->req_pending=0; + } + + if(crq->bRequest == USB_REQ_SET_CONFIGURATION || crq->bRequest == USB_REQ_SET_INTERFACE){ + //rx_packet包接收完毕 + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + } + + return; +} + + +#else + +/* +******************************************************************************* +* sw_udc_handle_ep0_idle +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static void sw_udc_handle_ep0_idle(struct sw_udc *dev, + struct sw_udc_ep *ep, + struct usb_ctrlrequest *crq, + u32 ep0csr) +{ + int len = 0, ret = 0, tmp = 0; + + /* start control request? */ + if (!USBC_Dev_IsReadDataReady(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0)){ + DMSG_WRN("ERR: data is ready, can not read data.\n"); + return; + } + + sw_udc_nuke(dev, ep, -EPROTO); + + len = sw_udc_read_fifo_crq(crq); + if (len != sizeof(*crq)) { + DMSG_PANIC("setup begin: fifo READ ERROR" + " wanted %d bytes got %d. Stalling out...\n", + sizeof(*crq), len); + + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 0); + USBC_Dev_EpSendStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0); + + return; + } + + DMSG_DBG_UDC("ep0: bRequest = %d bRequestType %d wLength = %d\n", + crq->bRequest, crq->bRequestType, crq->wLength); + + /* cope with automagic for some standard requests. */ + dev->req_std = ((crq->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD); + dev->req_config = 0; + dev->req_pending = 1; + + switch (crq->bRequest) { + case USB_REQ_SET_CONFIGURATION: + DMSG_DBG_UDC("USB_REQ_SET_CONFIGURATION ... \n"); + + if (crq->bRequestType == USB_RECIP_DEVICE) { + dev->req_config = 1; + } + break; + + case USB_REQ_SET_INTERFACE: + DMSG_DBG_UDC("USB_REQ_SET_INTERFACE ... \n"); + + if (crq->bRequestType == USB_RECIP_INTERFACE) { + dev->req_config = 1; + } + break; + + case USB_REQ_SET_ADDRESS: + DMSG_DBG_UDC("USB_REQ_SET_ADDRESS ... \n"); + + if (crq->bRequestType == USB_RECIP_DEVICE) { + tmp = crq->wValue & 0x7F; + dev->address = tmp; + + //rx接收完毕、dataend、tx_pakect准备就绪 + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + + dev->ep0state = EP0_END_XFER; + + crq_bRequest = USB_REQ_SET_ADDRESS; + + return; + } + break; + + case USB_REQ_GET_STATUS: + DMSG_DBG_UDC("USB_REQ_GET_STATUS ... \n"); + if (dev->req_std) { + if (!sw_udc_get_status(dev, crq)) { + return; + } + } + break; + + case USB_REQ_CLEAR_FEATURE: + //--<1>--数据方向必须为 host to device + if(x_test_bit(crq->bRequestType, 7) == 1){ + DMSG_PANIC("USB_REQ_CLEAR_FEATURE: data is not host to device\n"); + break; + } + + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + + //--<3>--数据阶段 + if(crq->bRequestType == USB_RECIP_DEVICE){ + /* wValue 0-1 */ + if(crq->wValue){ + dev->devstatus &= ~(1 << USB_DEVICE_REMOTE_WAKEUP); + }else{ + int k = 0; + for(k = 0;k < SW_UDC_ENDPOINTS;k++){ + sw_udc_set_halt(&dev->ep[k].ep, 0); + } + } + + }else if(crq->bRequestType == USB_RECIP_INTERFACE){ + //--<2>--令牌阶段结束 + + //不处理 + + }else if(crq->bRequestType == USB_RECIP_ENDPOINT){ + //--<3>--解除禁用ep + //sw_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0); + //dev->devstatus &= ~(1 << USB_DEVICE_REMOTE_WAKEUP); + /* wValue 0-1 */ + if(crq->wValue){ + dev->devstatus &= ~(1 << USB_DEVICE_REMOTE_WAKEUP); + }else{ + sw_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0); + } + + }else{ + DMSG_PANIC("PANIC : nonsupport set feature request. (%d)\n", crq->bRequestType); + USBC_Dev_EpSendStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0); + } + //--<4>-- + dev->ep0state = EP0_IDLE; + + return; + //break; + + case USB_REQ_SET_FEATURE: + //--<1>--数据方向必须为 host to device + if(x_test_bit(crq->bRequestType, 7) == 1){ + DMSG_PANIC("USB_REQ_SET_FEATURE: data is not host to device\n"); + break; + } + //--<3>--数据阶段 + if(crq->bRequestType == USB_RECIP_DEVICE){ + if((crq->wValue == USB_DEVICE_TEST_MODE) && (crq->wIndex == 0x0400)){ + //setup packet包接收完毕 + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + + dev->ep0state = EP0_END_XFER; + crq_bRequest = USB_REQ_SET_FEATURE; + + return; + } + + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + dev->devstatus |= (1 << USB_DEVICE_REMOTE_WAKEUP); + + }else if(crq->bRequestType == USB_RECIP_INTERFACE){ + //--<2>--令牌阶段结束 + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + //不处理 + + }else if(crq->bRequestType == USB_RECIP_ENDPOINT){ + //--<3>--禁用ep + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + sw_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1); + }else{ + DMSG_PANIC("PANIC : nonsupport set feature request. (%d)\n", crq->bRequestType); + + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + USBC_Dev_EpSendStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0); + } + //--<4>-- + dev->ep0state = EP0_IDLE; + + return; + //break; + + default: + /* 只收setup数据包，不能置DataEnd */ + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 0); + break; + } + + if(crq->bRequestType & USB_DIR_IN){ + dev->ep0state = EP0_IN_DATA_PHASE; + }else{ + dev->ep0state = EP0_OUT_DATA_PHASE; + } + + ret = dev->driver->setup(&dev->gadget, crq); + if (ret < 0) { + if (dev->req_config) { + DMSG_PANIC("ERR: config change %02x fail %d?\n", crq->bRequest, ret); + return; + } + + if(ret == -EOPNOTSUPP){ + DMSG_PANIC("ERR: Operation not supported\n"); + }else{ + DMSG_PANIC("ERR: dev->driver->setup failed. (%d)\n", ret); + } + + udelay(5); + + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + USBC_Dev_EpSendStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0); + + dev->ep0state = EP0_IDLE; + /* deferred i/o == no response yet */ + } else if (dev->req_pending) { +// DMSG_PANIC("ERR: dev->req_pending... what now?\n"); + dev->req_pending=0; + } + + if(crq->bRequest == USB_REQ_SET_CONFIGURATION || crq->bRequest == USB_REQ_SET_INTERFACE){ + //rx_packet包接收完毕 + USBC_Dev_ReadDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + } + + return; +} + +#endif + +/* +******************************************************************************* +* FunctionName +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static void sw_udc_handle_ep0(struct sw_udc *dev) +{ + u32 ep0csr = 0; + struct sw_udc_ep *ep = &dev->ep[0]; + struct sw_udc_request *req = NULL; + struct usb_ctrlrequest crq; + +DMSG_DBG_UDC("sw_udc_handle_ep0--1--\n"); + + if(list_empty(&ep->queue)){ + req = NULL; + }else{ + req = list_entry(ep->queue.next, struct sw_udc_request, queue); + } + +DMSG_DBG_UDC("sw_udc_handle_ep0--2--\n"); + + + /* We make the assumption that sw_udc_UDC_IN_CSR1_REG equal to + * sw_udc_UDC_EP0_CSR_REG when index is zero */ + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, 0); + + /* clear stall status */ + if (USBC_Dev_IsEpStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0)) { + DMSG_PANIC("ERR: ep0 stall\n"); + + sw_udc_nuke(dev, ep, -EPIPE); + USBC_Dev_EpClearStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0); + dev->ep0state = EP0_IDLE; + + return; + } + + /* clear setup end */ + if (USBC_Dev_Ctrl_IsSetupEnd(g_sw_udc_io.usb_bsp_hdle)) { + DMSG_PANIC("handle_ep0: ep0 setup end\n"); + + sw_udc_nuke(dev, ep, 0); + USBC_Dev_Ctrl_ClearSetupEnd(g_sw_udc_io.usb_bsp_hdle); + dev->ep0state = EP0_IDLE; + } + + +DMSG_DBG_UDC("sw_udc_handle_ep0--3--%d\n", dev->ep0state); + + + ep0csr = USBC_Readw(USBC_REG_RXCSR(g_sw_udc_io.usb_bsp_hdle)); + + switch (dev->ep0state) { + case EP0_IDLE: + sw_udc_handle_ep0_idle(dev, ep, &crq, ep0csr); + break; + + case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */ + DMSG_DBG_UDC("EP0_IN_DATA_PHASE ... what now?\n"); + + if (!USBC_Dev_IsWriteDataReady(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0) && req) { + sw_udc_write_fifo(ep, req); + } + break; + + case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */ + DMSG_DBG_UDC("EP0_OUT_DATA_PHASE ... what now?\n"); + + if (USBC_Dev_IsReadDataReady(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0) && req ) { + sw_udc_read_fifo(ep,req); + } + break; + + case EP0_END_XFER: + DMSG_DBG_UDC("EP0_END_XFER ... what now?\n"); + DMSG_DBG_UDC("crq_bRequest = 0x%x\n", crq_bRequest); + + switch (crq_bRequest){ + case USB_REQ_SET_ADDRESS: + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, 0); + + USBC_Dev_Ctrl_ClearSetupEnd(g_sw_udc_io.usb_bsp_hdle); + USBC_Dev_SetAddress(g_sw_udc_io.usb_bsp_hdle, dev->address); + + DMSG_INFO_UDC("Set address %d\n", dev->address); + break; + + case USB_REQ_SET_FEATURE: + { + u32 fifo = 0; + + fifo = USBC_SelectFIFO(g_sw_udc_io.usb_bsp_hdle, 0); + USBC_WritePacket(g_sw_udc_io.usb_bsp_hdle, fifo, 54, (u32 *)TestPkt); + USBC_EnterMode_TestPacket(g_sw_udc_io.usb_bsp_hdle); + USBC_Dev_WriteDataStatus(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1); + } + break; + + default: + break; + } + + crq_bRequest = 0; + + dev->ep0state = EP0_IDLE; + break; + + case EP0_STALL: + DMSG_DBG_UDC("EP0_STALL ... what now?\n"); + dev->ep0state = EP0_IDLE; + break; + } + +DMSG_DBG_UDC("sw_udc_handle_ep0--4--%d\n", dev->ep0state); + + + return; +} + +/* +******************************************************************************* +* FunctionName +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static void sw_udc_handle_ep(struct sw_udc_ep *ep) +{ + struct sw_udc_request *req = NULL; + int is_in = ep->bEndpointAddress & USB_DIR_IN; + u32 idx = 0; + u8 old_ep_index = 0; + u32 is_done = 0; + + idx = ep->bEndpointAddress & 0x7F; + + old_ep_index = USBC_GetActiveEp(g_sw_udc_io.usb_bsp_hdle); + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, idx); + + if (is_in) { + if (USBC_Dev_IsEpStall(g_sw_udc_io.usb_bsp_hdle, + USBC_EP_TYPE_TX)) { + DMSG_PANIC("ERR: tx ep(%d) is stall\n", idx); + USBC_Dev_EpClearStall(g_sw_udc_io.usb_bsp_hdle, + USBC_EP_TYPE_TX); + goto end; + } + } else { + if (USBC_Dev_IsEpStall(g_sw_udc_io.usb_bsp_hdle, + USBC_EP_TYPE_RX)) { + DMSG_PANIC("ERR: rx ep(%d) is stall\n", idx); + USBC_Dev_EpClearStall(g_sw_udc_io.usb_bsp_hdle, + USBC_EP_TYPE_RX); + goto end; + } + } + + /* get req */ + if (likely(!list_empty(&ep->queue))) + req = list_entry(ep->queue.next, struct sw_udc_request, queue); + else + req = NULL; + + if (req) { + + /*DMSG_INFO("b: (0x%p, %d, %d)\n", &(req->req), + req->req.length, req->req.actual);*/ + + if (is_in) { + /* ϣʹһ + * ûд꣬ͽŴ */ + if (req->req.length <= req->req.actual) { + sw_udc_done(ep, req, 0); + is_done = 1; + goto next; + } else { + if (!USBC_Dev_IsWriteDataReady( + g_sw_udc_io.usb_bsp_hdle, + USBC_EP_TYPE_TX)) + sw_udc_write_fifo(ep, req); + } + } else { + if (USBC_Dev_IsReadDataReady(g_sw_udc_io.usb_bsp_hdle, + USBC_EP_TYPE_RX)) + is_done = sw_udc_read_fifo(ep, req); + } + } + +next: + /* do next req */ + if (is_done) { + if (likely(!list_empty(&ep->queue))) + req = list_entry(ep->queue.next, struct sw_udc_request, + queue); + else + req = NULL; + + if (req) { + + /*DMSG_INFO("n: (0x%p, %d, %d)\n", &(req->req), + req->req.length, req->req.actual);*/ + + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, idx); + + if (is_in && !USBC_Dev_IsWriteDataReady( + g_sw_udc_io.usb_bsp_hdle, + USBC_EP_TYPE_TX)) + sw_udc_write_fifo(ep, req); + else if (!is_in && USBC_Dev_IsReadDataReady( + g_sw_udc_io.usb_bsp_hdle, + USBC_EP_TYPE_RX)) + sw_udc_read_fifo(ep, req); + + } + } + +end: + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, old_ep_index); + + return; +} + +/* +******************************************************************************* +* filtrate_irq_misc +* +* Description: +* 过滤没用的中断, 保留 disconect, reset, resume, suspend +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static u32 filtrate_irq_misc(u32 irq_misc) +{ + u32 irq = irq_misc; + + irq &= ~(USBC_INTUSB_VBUS_ERROR | USBC_INTUSB_SESSION_REQ | USBC_INTUSB_CONNECT | USBC_INTUSB_SOF); + USBC_INT_ClearMiscPending(g_sw_udc_io.usb_bsp_hdle, USBC_INTUSB_VBUS_ERROR); + USBC_INT_ClearMiscPending(g_sw_udc_io.usb_bsp_hdle, USBC_INTUSB_SESSION_REQ); + USBC_INT_ClearMiscPending(g_sw_udc_io.usb_bsp_hdle, USBC_INTUSB_CONNECT); + USBC_INT_ClearMiscPending(g_sw_udc_io.usb_bsp_hdle, USBC_INTUSB_SOF); + + return irq; +} + +/* +******************************************************************************* +* clear_all_irq +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static void clear_all_irq(void) +{ + USBC_INT_ClearEpPendingAll(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX); + USBC_INT_ClearEpPendingAll(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX); + USBC_INT_ClearMiscPendingAll(g_sw_udc_io.usb_bsp_hdle); +} + +/* +******************************************************************************* +* throw_away_all_urb +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static void throw_away_all_urb(struct sw_udc *dev) +{ + int k = 0; + + DMSG_INFO_UDC("irq: reset happen, throw away all urb\n"); + for(k = 0; k < SW_UDC_ENDPOINTS; k++){ + sw_udc_nuke(dev, (struct sw_udc_ep * )&(dev->ep[k]), -ESHUTDOWN); + } +} + +/* +******************************************************************************* +* sw_udc_clean_dma_status +* +* Description: +* 清空ep关于DMA的所有状态, 一般在DMA异常的时间调用 +* +* Parameters: +* qh : input. +* +* Return value: +* void +* +* note: +* called with controller irqlocked +* +******************************************************************************* +*/ +void sw_udc_clean_dma_status(struct sw_udc_ep *ep) +{ + u8 ep_index = 0; + u8 old_ep_index = 0; + struct sw_udc_request *req = NULL; + + ep_index = ep->bEndpointAddress & 0x7F; + + old_ep_index = USBC_GetActiveEp(g_sw_udc_io.usb_bsp_hdle); + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, ep_index); + + if((ep->bEndpointAddress) & USB_DIR_IN){ //dma_mode1 + /* clear ep dma status */ + USBC_Dev_ClearEpDma(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX); + + /* select bus to pio */ + sw_udc_switch_bus_to_pio(ep, 1); + }else{ //dma_mode0 + /* clear ep dma status */ + USBC_Dev_ClearEpDma(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX); + + /* select bus to pio */ + sw_udc_switch_bus_to_pio(ep, 0); + } + + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, old_ep_index); + + /* done req */ + while(likely (!list_empty(&ep->queue))){ + req = list_entry(ep->queue.next, struct sw_udc_request, queue); + if(req){ + req->req.status = -ECONNRESET; + req->req.actual = 0; + sw_udc_done(ep, req, -ECONNRESET); + } + } + + return; +} + +/* +******************************************************************************* +* sw_udc_stop_dma_work +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static void sw_udc_stop_dma_work(struct sw_udc *dev) +{ + __u32 i = 0; + struct sw_udc_ep *ep = NULL; + + for(i = 0; i < SW_UDC_ENDPOINTS; i++){ + ep = &dev->ep[i]; + + if(sw_udc_dma_is_busy(ep)){ + DMSG_PANIC("wrn: ep(%d) must stop working\n", i); + + sw_udc_dma_stop(ep); + sw_udc_clean_dma_status(ep); + } + } + + return; +} + +/* +******************************************************************************* +* sw_udc_irq +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static irqreturn_t sw_udc_irq(int dummy, void *_dev) +{ + struct sw_udc *dev = _dev; + int usb_irq = 0; + int tx_irq = 0; + int rx_irq = 0; + int i = 0; + u32 old_ep_idx = 0; + unsigned long flags = 0; + + spin_lock_irqsave(&dev->lock, flags); + + /* Driver connected ? */ + if (!dev->driver || !is_peripheral_active()) { + DMSG_PANIC("ERR: functoin driver is not exist, or udc is not active.\n"); + + /* Clear interrupts */ + clear_all_irq(); + + spin_unlock_irqrestore(&dev->lock, flags); + + return IRQ_NONE; + } + + /* Save index */ + old_ep_idx = USBC_GetActiveEp(g_sw_udc_io.usb_bsp_hdle); + + /* Read status registers */ + usb_irq = USBC_INT_MiscPending(g_sw_udc_io.usb_bsp_hdle); + tx_irq = USBC_INT_EpPending(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX); + rx_irq = USBC_INT_EpPending(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX); + + DMSG_TEST("\n\nirq: usb_irq=%02x, tx_irq=%02x, rx_irq=%02x\n", + usb_irq, tx_irq, rx_irq); + + usb_irq = filtrate_irq_misc(usb_irq); + + /* + * Now, handle interrupts. There's two types : + * - Reset, Resume, Suspend coming -> usb_int_reg + * - EP -> ep_int_reg + */ + + /* RESET */ + if (usb_irq & USBC_INTUSB_RESET) { + DMSG_INFO_UDC("IRQ: reset\n"); + + USBC_INT_ClearMiscPending(g_sw_udc_io.usb_bsp_hdle, USBC_INTUSB_RESET); + clear_all_irq(); + + usb_connect = 1; + + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, 0); + USBC_Dev_SetAddress_default(g_sw_udc_io.usb_bsp_hdle); + + if(is_udc_support_dma()){ + sw_udc_stop_dma_work(dev); + } + + throw_away_all_urb(dev); + + dev->address = 0; + dev->ep0state = EP0_IDLE; +// dev->gadget.speed = USB_SPEED_FULL; + + spin_unlock_irqrestore(&dev->lock, flags); + + return IRQ_HANDLED; + } + + /* RESUME */ + if (usb_irq & USBC_INTUSB_RESUME) { + DMSG_INFO_UDC("IRQ: resume\n"); + + /* clear interrupt */ + USBC_INT_ClearMiscPending(g_sw_udc_io.usb_bsp_hdle, USBC_INTUSB_RESUME); + + if (dev->gadget.speed != USB_SPEED_UNKNOWN + && dev->driver + && dev->driver->resume) { + spin_unlock(&dev->lock); + dev->driver->resume(&dev->gadget); + spin_lock(&dev->lock); + } + } + + /* SUSPEND */ + if (usb_irq & USBC_INTUSB_SUSPEND) { + DMSG_INFO_UDC("IRQ: suspend\n"); + + /* clear interrupt */ + USBC_INT_ClearMiscPending(g_sw_udc_io.usb_bsp_hdle, USBC_INTUSB_SUSPEND); + + if(dev->gadget.speed != USB_SPEED_UNKNOWN){ + usb_connect = 0; + }else{ + DMSG_INFO_UDC("ERR: usb speed is unkown\n"); + } + + if (dev->gadget.speed != USB_SPEED_UNKNOWN + && dev->driver + && dev->driver->suspend) { + spin_unlock(&dev->lock); + dev->driver->suspend(&dev->gadget); + spin_lock(&dev->lock); + } + + dev->ep0state = EP0_IDLE; + + } + + /* DISCONNECT */ + if(usb_irq & USBC_INTUSB_DISCONNECT){ + DMSG_INFO_UDC("IRQ: disconnect\n"); + + USBC_INT_ClearMiscPending(g_sw_udc_io.usb_bsp_hdle, USBC_INTUSB_DISCONNECT); + + dev->ep0state = EP0_IDLE; + + usb_connect = 0; + } + + /* EP */ + /* control traffic */ + /* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready + * generate an interrupt + */ + if (tx_irq & USBC_INTTx_FLAG_EP0) { + DMSG_DBG_UDC("USB ep0 irq\n"); + + /* Clear the interrupt bit by setting it to 1 */ + USBC_INT_ClearEpPending(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX, 0); + + if(dev->gadget.speed == USB_SPEED_UNKNOWN){ + if(USBC_Dev_QueryTransferMode(g_sw_udc_io.usb_bsp_hdle) == USBC_TS_MODE_HS){ + dev->gadget.speed = USB_SPEED_HIGH; + + DMSG_INFO_UDC("\n+++++++++++++++++++++++++++++++++++++\n"); + DMSG_INFO_UDC(" usb enter high speed.\n"); + DMSG_INFO_UDC("\n+++++++++++++++++++++++++++++++++++++\n"); + }else{ + dev->gadget.speed= USB_SPEED_FULL; + + DMSG_INFO_UDC("\n+++++++++++++++++++++++++++++++++++++\n"); + DMSG_INFO_UDC(" usb enter full speed.\n"); + DMSG_INFO_UDC("\n+++++++++++++++++++++++++++++++++++++\n"); + } + } + + sw_udc_handle_ep0(dev); + } + + /* ȶȡ, PCķٶȿС */ + + /* rx endpoint data transfers */ + for (i = 1; i < SW_UDC_ENDPOINTS; i++) { + u32 tmp = 1 << i; + + if (rx_irq & tmp) { + DMSG_DBG_UDC("USB rx ep%d irq\n", i); + + /* Clear the interrupt bit by setting it to 1 */ + USBC_INT_ClearEpPending(g_sw_udc_io.usb_bsp_hdle, + USBC_EP_TYPE_RX, i); + + sw_udc_handle_ep(&dev->ep[i]); + } + } + + /* tx endpoint data transfers */ + for (i = 1; i < SW_UDC_ENDPOINTS; i++) { + u32 tmp = 1 << i; + + if (tx_irq & tmp) { + DMSG_DBG_UDC("USB tx ep%d irq\n", i); + + /* Clear the interrupt bit by setting it to 1 */ + USBC_INT_ClearEpPending(g_sw_udc_io.usb_bsp_hdle, + USBC_EP_TYPE_TX, i); + + sw_udc_handle_ep(&dev->ep[i]); + } + } + + DMSG_TEST("irq: %d irq end.\n", dev->irq_no); + + /* Restore old index */ + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, old_ep_idx); + + spin_unlock_irqrestore(&dev->lock, flags); + + return IRQ_HANDLED; +} + +/* +******************************************************************************* +* sw_udc_dma_completion +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +void sw_udc_dma_completion(struct sw_udc *dev, struct sw_udc_ep *ep, struct sw_udc_request *req) +{ + unsigned long flags = 0; + __u8 old_ep_index = 0; + __u32 dma_transmit_len = 0; + int is_complete = 0; + struct sw_udc_request *req_next = NULL; + + if(dev == NULL || ep == NULL || req == NULL){ + DMSG_PANIC("ERR: argment invaild. (0x%p, 0x%p, 0x%p)\n", dev, ep, req); + return; + } + + spin_lock_irqsave(&ep->dev->lock, flags); + + old_ep_index = USBC_GetActiveEp(dev->sw_udc_io->usb_bsp_hdle); + USBC_SelectActiveEp(dev->sw_udc_io->usb_bsp_hdle, ep->num); + + DMSG_TEST("dq: ep(0x%p, %d), req(0x%p, 0x%p, %d, %d)\n", + ep, ep->num, + req, &(req->req), req->req.length, req->req.actual); + + if((ep->bEndpointAddress) & USB_DIR_IN){ //tx, dma_mode1 + USBC_Dev_ClearEpDma(dev->sw_udc_io->usb_bsp_hdle, USBC_EP_TYPE_TX); + }else{ //rx, dma_mode0 + USBC_Dev_ClearEpDma(dev->sw_udc_io->usb_bsp_hdle, USBC_EP_TYPE_RX); + } + + dma_transmit_len = sw_udc_dma_transmit_length(ep, ((ep->bEndpointAddress) & USB_DIR_IN), (__u32)req->req.buf); + if(dma_transmit_len < req->req.length){ + DMSG_PANIC("WRN: DMA recieve data not complete, (%d, %d, %d)\n", + req->req.length, req->req.actual, dma_transmit_len); + + if((ep->bEndpointAddress) & USB_DIR_IN){ + USBC_Dev_ClearEpDma(dev->sw_udc_io->usb_bsp_hdle, USBC_EP_TYPE_TX); + USBC_Dev_WriteDataStatus(dev->sw_udc_io->usb_bsp_hdle, USBC_EP_TYPE_TX, 1); + }else{ + USBC_Dev_ClearEpDma(dev->sw_udc_io->usb_bsp_hdle, USBC_EP_TYPE_RX); + USBC_Dev_ReadDataStatus(dev->sw_udc_io->usb_bsp_hdle, USBC_EP_TYPE_RX, 1); + } + } + + /* 如果本次传输有数据没有传输完毕，得接着传输 */ + req->req.actual += dma_transmit_len; + if(req->req.length > req->req.actual){ + DMSG_INFO_UDC("dma irq, transfer left data\n"); + + if(((ep->bEndpointAddress & USB_DIR_IN) != 0) + && !USBC_Dev_IsWriteDataReady(dev->sw_udc_io->usb_bsp_hdle, USBC_EP_TYPE_TX)){ + if(sw_udc_write_fifo(ep, req)){ + req = NULL; + is_complete = 1; + } + }else if(((ep->bEndpointAddress & USB_DIR_IN) != 0) + && USBC_Dev_IsReadDataReady(dev->sw_udc_io->usb_bsp_hdle, USBC_EP_TYPE_RX)){ + if(sw_udc_read_fifo(ep, req)){ + req = NULL; + is_complete = 1; + } + } + }else{ /* 如果DMA完成的传输了数据，就done */ + sw_udc_done(ep, req, 0); + is_complete = 1; + } + + /* 如果DMA完成的传输了数据，就done */ + + if(is_complete){ + ep->dma_working = 0; + ep->dma_transfer_len = 0; + } + + //------------------------------------------------- + //发起下一次传输 + //------------------------------------------------- + if(is_complete){ + if(likely (!list_empty(&ep->queue))){ + req_next = list_entry(ep->queue.next, struct sw_udc_request, queue); + }else{ + req_next = NULL; + } + + if(req_next){ + DMSG_TEST("do next req: ep(0x%p, %d), req(0x%p, 0x%p, %d, %d)\n", + ep, ep->num, + req_next, &(req_next->req), req_next->req.length, req_next->req.actual); + + if(((ep->bEndpointAddress & USB_DIR_IN) != 0) + && !USBC_Dev_IsWriteDataReady(dev->sw_udc_io->usb_bsp_hdle, USBC_EP_TYPE_TX)){ + sw_udc_write_fifo(ep, req_next); + }else if(((ep->bEndpointAddress & USB_DIR_IN) == 0) + && USBC_Dev_IsReadDataReady(dev->sw_udc_io->usb_bsp_hdle, USBC_EP_TYPE_RX)){ + sw_udc_read_fifo(ep, req_next); + } + } + } + + USBC_SelectActiveEp(dev->sw_udc_io->usb_bsp_hdle, old_ep_index); + + DMSG_TEST("de\n"); + + spin_unlock_irqrestore(&ep->dev->lock, flags); + + return; +} + +/*------------------------- sw_udc_ep_ops ----------------------------------*/ + +static inline struct sw_udc_ep *to_sw_udc_ep(struct usb_ep *ep) +{ + return container_of(ep, struct sw_udc_ep, ep); +} + +static inline struct sw_udc *to_sw_udc(struct usb_gadget *gadget) +{ + return container_of(gadget, struct sw_udc, gadget); +} + +static inline struct sw_udc_request *to_sw_udc_req(struct usb_request *req) +{ + return container_of(req, struct sw_udc_request, req); +} + +/* +******************************************************************************* +* sw_udc_ep_enable +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_ep_enable(struct usb_ep *_ep, + const struct usb_endpoint_descriptor *desc) +{ + struct sw_udc *dev = NULL; + struct sw_udc_ep *ep = NULL; + u32 max = 0; + unsigned long flags = 0; + u32 old_ep_index = 0; + __u32 fifo_addr = 0; + + if(_ep == NULL || desc == NULL){ + DMSG_PANIC("ERR: invalid argment\n"); + return -EINVAL; + } + + if (_ep->name == ep0name || desc->bDescriptorType != USB_DT_ENDPOINT){ + DMSG_PANIC("PANIC : _ep->name(%s) == ep0name || desc->bDescriptorType(%d) != USB_DT_ENDPOINT\n", + _ep->name , desc->bDescriptorType); + return -EINVAL; + } + + ep = to_sw_udc_ep(_ep); + if(ep == NULL){ + DMSG_PANIC("ERR: usbd_ep_enable, ep = NULL\n"); + return -EINVAL; + } + + if(ep->desc){ + DMSG_PANIC("ERR: usbd_ep_enable, ep->desc is not NULL, ep%d(%s)\n", ep->num, _ep->name); + return -EINVAL; + } + + DMSG_INFO_UDC("ep enable: ep%d(0x%p, %s, %d, %d)\n", + ep->num, _ep, _ep->name, + (desc->bEndpointAddress & USB_DIR_IN), _ep->maxpacket); + + dev = ep->dev; + if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN){ + DMSG_PANIC("PANIC : dev->driver = 0x%p ?= NULL dev->gadget->speed =%d ?= USB_SPEED_UNKNOWN\n", + dev->driver ,dev->gadget.speed); + return -ESHUTDOWN; + } + + max = le16_to_cpu(desc->wMaxPacketSize) & 0x1fff; + + spin_lock_irqsave(&ep->dev->lock, flags); + + _ep->maxpacket = max & 0x7ff; + ep->desc = desc; + ep->halted = 0; + ep->bEndpointAddress = desc->bEndpointAddress; + + /* select fifo address, 预先固定分配 + * 从1K的位置开始，每个ep分配1K的空间 + */ + fifo_addr = ep->num * 1024; + + if(!is_peripheral_active()){ + DMSG_PANIC("ERR: usb device is not active\n"); + goto end; + } + + old_ep_index = USBC_GetActiveEp(g_sw_udc_io.usb_bsp_hdle); + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, ep->num); + + //set max packet ,type, direction, address; reset fifo counters, enable irq + if ((ep->bEndpointAddress) & USB_DIR_IN){ /* tx */ + USBC_Dev_ConfigEp(g_sw_udc_io.usb_bsp_hdle, USBC_TS_TYPE_BULK, USBC_EP_TYPE_TX, SW_UDC_FIFO_NUM, _ep->maxpacket & 0x7ff); + USBC_ConfigFifo(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX, SW_UDC_FIFO_NUM, 512, fifo_addr); + + //开启该ep的tx_irq en + USBC_INT_EnableEp(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX, ep->num); + }else{ /* rx */ + USBC_Dev_ConfigEp(g_sw_udc_io.usb_bsp_hdle, USBC_TS_TYPE_BULK, USBC_EP_TYPE_RX, SW_UDC_FIFO_NUM, _ep->maxpacket & 0x7ff); + USBC_ConfigFifo(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX, SW_UDC_FIFO_NUM, 512, fifo_addr); + + //开启该ep的rx_irq + USBC_INT_EnableEp(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX, ep->num); + } + + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, old_ep_index); + +end: + spin_unlock_irqrestore(&ep->dev->lock, flags); + + sw_udc_set_halt(_ep, 0); + + return 0; +} + +/* +******************************************************************************* +* sw_udc_ep_disable +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_ep_disable(struct usb_ep *_ep) +{ + struct sw_udc_ep *ep = NULL; + u32 old_ep_index = 0; + unsigned long flags = 0; + + if (!_ep) { + DMSG_PANIC("ERR: invalid argment\n"); + return -EINVAL; + } + + ep = to_sw_udc_ep(_ep); + if(ep == NULL){ + DMSG_PANIC("ERR: usbd_ep_disable: ep = NULL\n"); + return -EINVAL; + } + + if (!ep->desc) { + DMSG_PANIC("ERR: %s not enabled\n", _ep ? ep->ep.name : NULL); + return -EINVAL; + } + + DMSG_INFO_UDC("ep disable: ep%d(0x%p, %s, %d, %x)\n", + ep->num, _ep, _ep->name, + (ep->bEndpointAddress & USB_DIR_IN), _ep->maxpacket); + + spin_lock_irqsave(&ep->dev->lock, flags); + + DMSG_DBG_UDC("ep_disable: %s\n", _ep->name); + + ep->desc = NULL; + ep->halted = 1; + + sw_udc_nuke (ep->dev, ep, -ESHUTDOWN); + + if(!is_peripheral_active()){ + DMSG_PANIC("ERR: usb device is not active\n"); + goto end; + } + + old_ep_index = USBC_GetActiveEp(g_sw_udc_io.usb_bsp_hdle); + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, ep->num); + + if ((ep->bEndpointAddress) & USB_DIR_IN){ /* tx */ + USBC_Dev_ConfigEp_Default(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX); + USBC_INT_DisableEp(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX, ep->num); + }else{ /* rx */ + USBC_Dev_ConfigEp_Default(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX); + USBC_INT_DisableEp(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX, ep->num); + } + + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, old_ep_index); + +end: + spin_unlock_irqrestore(&ep->dev->lock, flags); + + DMSG_DBG_UDC("%s disabled\n", _ep->name); + + return 0; +} + +/* +******************************************************************************* +* FunctionName +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static struct usb_request * sw_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags) +{ + struct sw_udc_request *req = NULL; + + if(!_ep){ + DMSG_PANIC("ERR: invalid argment\n"); + return NULL; + } + + req = kzalloc (sizeof(struct sw_udc_request), mem_flags); + if(!req){ + DMSG_PANIC("ERR: kzalloc failed\n"); + return NULL; + } + + memset(req, 0, sizeof(struct sw_udc_request)); + + INIT_LIST_HEAD (&req->queue); + + DMSG_INFO_UDC("alloc request: ep(0x%p, %s, %d), req(0x%p)\n", + _ep, _ep->name, _ep->maxpacket, req); + + return &req->req; +} + +/* +******************************************************************************* +* sw_udc_free_request +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static void sw_udc_free_request(struct usb_ep *_ep, struct usb_request *_req) +{ + struct sw_udc_request *req = NULL; + + if(_ep == NULL || _req == NULL){ + DMSG_PANIC("ERR: invalid argment\n"); + return; + } + + req = to_sw_udc_req(_req); + if(req == NULL){ + DMSG_PANIC("ERR: invalid argment\n"); + return; + } + + DMSG_INFO_UDC("free request: ep(0x%p, %s, %d), req(0x%p)\n", + _ep, _ep->name, _ep->maxpacket, req); + + kfree(req); + + return; +} + +/* +******************************************************************************* +* FunctionName +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) +{ + struct sw_udc_request *req = NULL; + struct sw_udc_ep *ep = NULL; + struct sw_udc *dev = NULL; + unsigned long flags = 0; + u8 old_ep_index = 0; + + if(_ep == NULL || _req == NULL ){ + DMSG_PANIC("ERR: invalid argment\n"); + return -EINVAL; + } + + ep = to_sw_udc_ep(_ep); + if ((ep == NULL || (!ep->desc && _ep->name != ep0name))){ + DMSG_PANIC("ERR: sw_udc_queue: inval 2\n"); + return -EINVAL; + } + + dev = ep->dev; + if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN){ + DMSG_PANIC("ERR : dev->driver=0x%p, dev->gadget.speed=%x\n", + dev->driver, dev->gadget.speed); + return -ESHUTDOWN; + } + + if (!_req->complete || !_req->buf){ + DMSG_PANIC("ERR: usbd_queue: _req is invalid\n"); + return -EINVAL; + } + + req = to_sw_udc_req(_req); + if (!req){ + DMSG_PANIC("ERR: req is NULL\n"); + return -EINVAL; + } + + spin_lock_irqsave(&ep->dev->lock, flags); + + _req->status = -EINPROGRESS; + _req->actual = 0; + + list_add_tail(&req->queue, &ep->queue); + + if(!is_peripheral_active()){ + DMSG_PANIC("warn: peripheral is active\n"); + goto end; + } + + DMSG_TEST("\n\nq: ep(0x%p, %d), req(0x%p, 0x%p, %d, %d)\n", + ep, ep->num, + req, _req, _req->length, _req->actual); + + //DMSG_INFO("\n\nq: (0x%p, %d, %d)\n", _req,_req->length, _req->actual); + //DMSG_INFO("\nq\n"); + + old_ep_index = USBC_GetActiveEp(g_sw_udc_io.usb_bsp_hdle); + if (ep->bEndpointAddress) { + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, ep->bEndpointAddress & 0x7F); + } else { + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, 0); + } + + /* ֻһ,ôͱִ */ + if (!ep->halted && (&req->queue == ep->queue.next)) { + if (ep->bEndpointAddress == 0 /* ep0 */) { + switch (dev->ep0state) { + case EP0_IN_DATA_PHASE: + if (!USBC_Dev_IsWriteDataReady(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX) + && sw_udc_write_fifo(ep, req)) { + dev->ep0state = EP0_IDLE; + req = NULL; + } + break; + + case EP0_OUT_DATA_PHASE: + if ((!_req->length) + || (USBC_Dev_IsReadDataReady(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX) + && sw_udc_read_fifo(ep, req))) { + dev->ep0state = EP0_IDLE; + req = NULL; + } + break; + + default: + spin_unlock_irqrestore(&ep->dev->lock, flags); + return -EL2HLT; + } + } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0 + && !USBC_Dev_IsWriteDataReady(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX)) { + if(sw_udc_write_fifo(ep, req)){ + req = NULL; + } + } else if ((ep->bEndpointAddress & USB_DIR_IN) == 0 + && USBC_Dev_IsReadDataReady(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX)) { + if(sw_udc_read_fifo(ep, req)){ + req = NULL; + } + } + } + + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, old_ep_index); +end: + /*DMSG_INFO("qe\n");*/ + + spin_unlock_irqrestore(&ep->dev->lock, flags); + + return 0; +} + +/* +******************************************************************************* +* sw_udc_dequeue +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req) +{ + struct sw_udc_ep *ep = NULL; + struct sw_udc *udc = NULL; + int retval = -EINVAL; + unsigned long flags = 0; + struct sw_udc_request *req = NULL; + + DMSG_DBG_UDC("(%p,%p)\n", _ep, _req); + + if(!the_controller->driver){ + DMSG_PANIC("ERR: sw_udc_dequeue: driver is null\n"); + return -ESHUTDOWN; + } + + if(!_ep || !_req){ + DMSG_PANIC("ERR: sw_udc_dequeue: invalid argment\n"); + return retval; + } + + ep = to_sw_udc_ep(_ep); + if(ep == NULL){ + DMSG_PANIC("ERR: ep == NULL\n"); + return -EINVAL; + } + + udc = to_sw_udc(ep->gadget); + if(udc == NULL){ + DMSG_PANIC("ERR: ep == NULL\n"); + return -EINVAL; + } + + DMSG_INFO_UDC("dequeue: ep(0x%p, %d), _req(0x%p, %d, %d)\n", + ep, ep->num, + _req, _req->length, _req->actual); + + spin_lock_irqsave(&ep->dev->lock, flags); + + list_for_each_entry (req, &ep->queue, queue) { + if (&req->req == _req) { + list_del_init (&req->queue); + _req->status = -ECONNRESET; + retval = 0; + break; + } + } + + if (retval == 0) { + DMSG_DBG_UDC("dequeued req %p from %s, len %d buf %p\n", + req, _ep->name, _req->length, _req->buf); + + sw_udc_done(ep, req, -ECONNRESET); + } + + spin_unlock_irqrestore(&ep->dev->lock, flags); + + return retval; +} + +/* +******************************************************************************* +* sw_udc_set_halt +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_set_halt(struct usb_ep *_ep, int value) +{ + struct sw_udc_ep *ep = NULL; + unsigned long flags = 0; + u32 idx = 0; + __u8 old_ep_index = 0; + + if(_ep == NULL){ + DMSG_PANIC("ERR: invalid argment\n"); + return -EINVAL; + } + + ep = to_sw_udc_ep(_ep); + if(ep == NULL){ + DMSG_PANIC("ERR: invalid argment\n"); + return -EINVAL; + } + + if(!ep->desc && ep->ep.name != ep0name){ + DMSG_PANIC("ERR: !ep->desc && ep->ep.name != ep0name\n"); + return -EINVAL; + } + + if(!is_peripheral_active()){ + DMSG_PANIC("ERR: usb device is not active\n"); + return 0; + } + + spin_lock_irqsave(&ep->dev->lock, flags); + + idx = ep->bEndpointAddress & 0x7F; + + old_ep_index = USBC_GetActiveEp(g_sw_udc_io.usb_bsp_hdle); + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, idx); + + if (idx == 0) { + USBC_Dev_EpClearStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0); + } else { + if ((ep->bEndpointAddress & USB_DIR_IN) != 0) { + if(value){ + USBC_Dev_EpSendStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX); + }else{ + USBC_Dev_EpClearStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX); + } + } else { + if(value){ + USBC_Dev_EpSendStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX); + }else{ + USBC_Dev_EpClearStall(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX); + } + } + } + + ep->halted = value ? 1 : 0; + + USBC_SelectActiveEp(g_sw_udc_io.usb_bsp_hdle, old_ep_index); + + spin_unlock_irqrestore(&ep->dev->lock, flags); + + return 0; +} + +static const struct usb_ep_ops sw_udc_ep_ops = { + .enable = sw_udc_ep_enable, + .disable = sw_udc_ep_disable, + + .alloc_request = sw_udc_alloc_request, + .free_request = sw_udc_free_request, + + .queue = sw_udc_queue, + .dequeue = sw_udc_dequeue, + + .set_halt = sw_udc_set_halt, +}; + + +/* +******************************************************************************* +* sw_udc_get_frame +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_get_frame(struct usb_gadget *_gadget) +{ + if(!is_peripheral_active()){ + DMSG_PANIC("ERR: usb device is not active\n"); + return 0; + } + + return USBC_REG_FRNUM(g_sw_udc_io.usb_bsp_hdle); +} + +/* +******************************************************************************* +* sw_udc_wakeup +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_wakeup(struct usb_gadget *_gadget) +{ + if(!is_peripheral_active()){ + DMSG_PANIC("ERR: usb device is not active\n"); + return 0; + } + + return 0; +} + +/* +******************************************************************************* +* sw_udc_set_selfpowered +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_set_selfpowered(struct usb_gadget *gadget, int value) +{ + if(!is_peripheral_active()){ + DMSG_PANIC("ERR: usb device is not active\n"); + return 0; + } + + return 0; +} + +static void sw_udc_disable(struct sw_udc *dev); +static void sw_udc_enable(struct sw_udc *dev); + +/* +******************************************************************************* +* FunctionName +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_set_pullup(struct sw_udc *udc, int is_on) +{ + DMSG_DBG_UDC("sw_udc_set_pullup\n"); + + is_udc_enable = is_on; + if(!is_peripheral_active()){ + DMSG_PANIC("ERR: usb device is not active\n"); + return 0; + } + + + if(is_on){ + sw_udc_enable(udc); + }else{ + if (udc->gadget.speed != USB_SPEED_UNKNOWN) { + if (udc->driver && udc->driver->disconnect) + udc->driver->disconnect(&udc->gadget); + } + + sw_udc_disable(udc); + } + + return 0; +} + +/* +******************************************************************************* +* sw_udc_vbus_session +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_vbus_session(struct usb_gadget *gadget, int is_active) +{ + struct sw_udc *udc = to_sw_udc(gadget); + + DMSG_DBG_UDC("sw_udc_vbus_session\n"); + + if(!is_peripheral_active()){ + DMSG_PANIC("ERR: usb device is not active\n"); + return 0; + } + + udc->vbus = (is_active != 0); + sw_udc_set_pullup(udc, is_active); + + return 0; +} + +/* +******************************************************************************* +* sw_udc_pullup +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_pullup(struct usb_gadget *gadget, int is_on) +{ + struct sw_udc *udc = to_sw_udc(gadget); + + DMSG_INFO_UDC("sw_udc_pullup, is_on = %d\n", is_on); + + sw_udc_set_pullup(udc, is_on); + + return 0; +} + +/* +******************************************************************************* +* sw_udc_vbus_draw +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_vbus_draw(struct usb_gadget *_gadget, unsigned ma) +{ + if(!is_peripheral_active()){ + DMSG_PANIC("ERR: usb device is not active\n"); + return 0; + } + + DMSG_DBG_UDC("sw_udc_vbus_draw\n"); + + cfg_vbus_draw(ma); + + return 0; +} + +static int sun4i_start(struct usb_gadget_driver *driver, + int (*bind)(struct usb_gadget *)); +static int sun4i_stop(struct usb_gadget_driver *driver); + +static const struct usb_gadget_ops sw_udc_ops = { + .get_frame = sw_udc_get_frame, + .wakeup = sw_udc_wakeup, + .set_selfpowered = sw_udc_set_selfpowered, + .pullup = sw_udc_pullup, + .vbus_session = sw_udc_vbus_session, + .vbus_draw = sw_udc_vbus_draw, + .start = sun4i_start, + .stop = sun4i_stop, +}; + +//--------------------------------------------------------------- +// gadget driver handling +//--------------------------------------------------------------- + +/* +******************************************************************************* +* sw_udc_reinit +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static void sw_udc_reinit(struct sw_udc *dev) +{ + u32 i = 0; + + /* device/ep0 records init */ + INIT_LIST_HEAD (&dev->gadget.ep_list); + INIT_LIST_HEAD (&dev->gadget.ep0->ep_list); + dev->ep0state = EP0_IDLE; + + for (i = 0; i < SW_UDC_ENDPOINTS; i++) { + struct sw_udc_ep *ep = &dev->ep[i]; + + if (i != 0) { + list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list); + } + + ep->dev = dev; + ep->desc = NULL; + ep->halted = 0; + INIT_LIST_HEAD (&ep->queue); + } + + return; +} + +/* +******************************************************************************* +* FunctionName +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static void sw_udc_enable(struct sw_udc *dev) +{ + DMSG_DBG_UDC("sw_udc_enable called\n"); + + /* dev->gadget.speed = USB_SPEED_UNKNOWN; */ + dev->gadget.speed = USB_SPEED_UNKNOWN; + +#ifdef CONFIG_USB_GADGET_DUALSPEED + DMSG_INFO_UDC("CONFIG_USB_GADGET_DUALSPEED\n"); + + USBC_Dev_ConfigTransferMode(g_sw_udc_io.usb_bsp_hdle, USBC_TS_TYPE_BULK, USBC_TS_MODE_HS); +#else + USBC_Dev_ConfigTransferMode(g_sw_udc_io.usb_bsp_hdle, USBC_TS_TYPE_BULK, USBC_TS_MODE_FS); +#endif + + /* Enable reset and suspend interrupt interrupts */ + USBC_INT_EnableUsbMiscUint(g_sw_udc_io.usb_bsp_hdle, USBC_BP_INTUSB_SUSPEND); + USBC_INT_EnableUsbMiscUint(g_sw_udc_io.usb_bsp_hdle, USBC_BP_INTUSB_RESUME); + USBC_INT_EnableUsbMiscUint(g_sw_udc_io.usb_bsp_hdle, USBC_BP_INTUSB_RESET); + USBC_INT_EnableUsbMiscUint(g_sw_udc_io.usb_bsp_hdle, USBC_BP_INTUSB_DISCONNECT); + + /* Enable ep0 interrupt */ + USBC_INT_EnableEp(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX, 0); + + cfg_udc_command(SW_UDC_P_ENABLE); + + return ; +} + +/* +******************************************************************************* +* sw_udc_disable +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static void sw_udc_disable(struct sw_udc *dev) +{ + DMSG_DBG_UDC("sw_udc_disable\n"); + + /* Disable all interrupts */ + USBC_INT_DisableUsbMiscAll(g_sw_udc_io.usb_bsp_hdle); + USBC_INT_DisableEpAll(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX); + USBC_INT_DisableEpAll(g_sw_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX); + + /* Clear the interrupt registers */ + clear_all_irq(); + cfg_udc_command(SW_UDC_P_DISABLE); + + /* Set speed to unknown */ + dev->gadget.speed = USB_SPEED_UNKNOWN; + + return; +} + +s32 usbd_start_work(void) +{ + DMSG_INFO_UDC("usbd_start_work\n"); + + if (!is_peripheral_active()) { + DMSG_PANIC("ERR: usb device is not active\n"); + return 0; + } + + enable_irq_udc(the_controller); + USBC_Dev_ConectSwitch(g_sw_udc_io.usb_bsp_hdle, USBC_DEVICE_SWITCH_ON); + + return 0; +} + +s32 usbd_stop_work(void) +{ + DMSG_INFO_UDC("usbd_stop_work\n"); + + if (!is_peripheral_active()) { + DMSG_PANIC("ERR: usb device is not active\n"); + return 0; + } + + disable_irq_udc(the_controller); + USBC_Dev_ConectSwitch(g_sw_udc_io.usb_bsp_hdle, USBC_DEVICE_SWITCH_OFF); //默认为pulldown + + return 0; +} + +/* +******************************************************************************* +* FunctionName +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sun4i_start(struct usb_gadget_driver *driver, + int (*bind)(struct usb_gadget *)) +{ + struct sw_udc *udc = the_controller; + int retval = 0; + + /* Sanity checks */ + if(!udc){ + DMSG_PANIC("ERR: udc is null\n"); + return -ENODEV; + } + + if (udc->driver){ + DMSG_PANIC("ERR: udc->driver is not null\n"); + return -EBUSY; + } + + if (!bind || !driver->setup || driver->max_speed < USB_SPEED_FULL) { + DMSG_PANIC("ERR: Invalid driver: bind %p setup %p speed %d\n", + bind, driver->setup, driver->max_speed); + return -EINVAL; + } + +#if defined(MODULE) + if (!driver->unbind) { + DMSG_PANIC("Invalid driver: no unbind method\n"); + return -EINVAL; + } +#endif + + /* Hook the driver */ + udc->driver = driver; + udc->gadget.dev.driver = &driver->driver; + + /* Bind the driver */ + if ((retval = device_add(&udc->gadget.dev)) != 0) { + DMSG_PANIC("ERR: Error in device_add() : %d\n",retval); + goto register_error; + } + + DMSG_INFO_UDC("[%s]: binding gadget driver '%s'\n", gadget_name, driver->driver.name); + + if ((retval = bind (&udc->gadget)) != 0) { + DMSG_PANIC("ERR: Error in bind() : %d\n",retval); + device_del(&udc->gadget.dev); + goto register_error; + } + + /* Enable udc */ + sw_udc_set_pullup(udc, 1); + + return 0; + +register_error: + udc->driver = NULL; + udc->gadget.dev.driver = NULL; + + return retval; +} + +/* +******************************************************************************* +* usb_gadget_unregister_driver +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sun4i_stop(struct usb_gadget_driver *driver) +{ + struct sw_udc *udc = the_controller; + + if(!udc){ + DMSG_PANIC("ERR: udc is null\n"); + return -ENODEV; + } + + if(!driver || driver != udc->driver || !driver->unbind){ + DMSG_PANIC("ERR: driver is null\n"); + return -EINVAL; + } + + DMSG_INFO_UDC("[%s]: usb_gadget_unregister_driver() '%s'\n", gadget_name, driver->driver.name); + + if(driver->disconnect){ + driver->disconnect(&udc->gadget); + } + + /* Disable udc */ + sw_udc_set_pullup(udc, 0); + + /* unbind gadget driver */ + driver->unbind(&udc->gadget); + udc->gadget.dev.driver = NULL; + device_del(&udc->gadget.dev); + udc->driver = NULL; + + + return 0; +} + +static struct sw_udc sw_udc = { + .gadget = { + .ops = &sw_udc_ops, + .ep0 = &sw_udc.ep[0].ep, + .name = gadget_name, + .dev = { + .init_name = "gadget", + }, + }, + + /* control endpoint */ + .ep[0] = { + .num = 0, + .ep = { + .name = ep0name, + .ops = &sw_udc_ep_ops, + .maxpacket = EP0_FIFO_SIZE, + }, + .dev = &sw_udc, + }, + + /* first group of endpoints */ + .ep[1] = { + .num = 1, + .ep = { + .name = "ep1-bulk", + .ops = &sw_udc_ep_ops, + .maxpacket = SW_UDC_EP_FIFO_SIZE, + }, + .dev = &sw_udc, + .fifo_size = (SW_UDC_EP_FIFO_SIZE * (SW_UDC_FIFO_NUM + 1)), + .bEndpointAddress = 1, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + }, + + .ep[2] = { + .num = 2, + .ep = { + .name = "ep2-bulk", + .ops = &sw_udc_ep_ops, + .maxpacket = SW_UDC_EP_FIFO_SIZE, + }, + .dev = &sw_udc, + .fifo_size = (SW_UDC_EP_FIFO_SIZE * (SW_UDC_FIFO_NUM + 1)), + .bEndpointAddress = 2, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + }, + + .ep[3] = { + .num = 3, + .ep = { + .name = "ep3-bulk", + .ops = &sw_udc_ep_ops, + .maxpacket = SW_UDC_EP_FIFO_SIZE, + }, + .dev = &sw_udc, + .fifo_size = (SW_UDC_EP_FIFO_SIZE * (SW_UDC_FIFO_NUM + 1)), + .bEndpointAddress = 3, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + }, + + .ep[4] = { + .num = 4, + .ep = { + .name = "ep4-bulk", + .ops = &sw_udc_ep_ops, + .maxpacket = SW_UDC_EP_FIFO_SIZE, + }, + .dev = &sw_udc, + .fifo_size = (SW_UDC_EP_FIFO_SIZE * (SW_UDC_FIFO_NUM + 1)), + .bEndpointAddress = 4, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + }, + + .ep[5] = { + .num = 5, + .ep = { + .name = "ep5-int", + .ops = &sw_udc_ep_ops, + .maxpacket = SW_UDC_EP_FIFO_SIZE, + }, + .dev = &sw_udc, + .fifo_size = (SW_UDC_EP_FIFO_SIZE * (SW_UDC_FIFO_NUM + 1)), + .bEndpointAddress = 5, + .bmAttributes = USB_ENDPOINT_XFER_INT, + }, +}; + +int sw_usb_device_enable(void) +{ + struct platform_device *pdev = g_udc_pdev; + struct sw_udc *udc = &sw_udc; + int retval = 0; + int irq = SW_INT_IRQNO_USB0; + + DMSG_INFO_UDC("sw_usb_device_enable start\n"); + + if(pdev == NULL){ + DMSG_PANIC("pdev is null\n"); + return -1; + } + + usbd_port_no = 0; + usb_connect = 0; + crq_bRequest = 0; + is_controller_alive = 1; + + memset(&g_sw_udc_io, 0, sizeof(sw_udc_io_t)); + + retval = sw_udc_io_init(usbd_port_no, pdev, &g_sw_udc_io); + if(retval != 0){ + DMSG_PANIC("ERR: sw_udc_io_init failed\n"); + return -1; + } + + udc->sw_udc_io = &g_sw_udc_io; + udc->usbc_no = usbd_port_no; + strcpy((char *)udc->driver_name, gadget_name); + udc->irq_no = irq; + + if(is_udc_support_dma()){ + retval = sw_udc_dma_probe(udc); + if(retval != 0){ + DMSG_PANIC("ERR: sw_udc_dma_probe failef\n"); + retval = -EBUSY; + goto err; + } + } + + retval = request_irq(irq, sw_udc_irq, + IRQF_DISABLED, gadget_name, udc); + if (retval != 0) { + DMSG_PANIC("ERR: cannot get irq %i, err %d\n", irq, retval); + retval = -EBUSY; + goto err; + } + + /* Enable udc */ + if (!is_udc_enable) + sw_udc_set_pullup(udc, 1); + + DMSG_INFO_UDC("sw_usb_device_enable end\n"); + + return 0; + +err: + if(is_udc_support_dma()){ + sw_udc_dma_remove(udc); + } + + sw_udc_io_exit(usbd_port_no, pdev, &g_sw_udc_io); + + return retval; +} +EXPORT_SYMBOL(sw_usb_device_enable); + +int sw_usb_device_disable(void) +{ + struct platform_device *pdev = g_udc_pdev; + struct sw_udc *udc = NULL; + unsigned long flags = 0; + + DMSG_INFO_UDC("sw_usb_device_disable start\n"); + + if(pdev == NULL){ + DMSG_PANIC("pdev is null\n"); + return -1; + } + + udc = platform_get_drvdata(pdev); + if(udc == NULL){ + DMSG_PANIC("udc is null\n"); + return -1; + } + + /* disable usb controller */ + if (udc->driver && udc->driver->disconnect) + udc->driver->disconnect(&udc->gadget); + + /* Disable udc */ + sw_udc_set_pullup(udc, 0); + + if(is_udc_support_dma()){ + sw_udc_dma_remove(udc); + } + + free_irq(udc->irq_no, udc); + + sw_udc_io_exit(usbd_port_no, pdev, &g_sw_udc_io); + + spin_lock_irqsave(&udc->lock, flags); + + memset(&g_sw_udc_io, 0, sizeof(sw_udc_io_t)); + + usbd_port_no = 0; + usb_connect = 0; + crq_bRequest = 0; + is_controller_alive = 0; + + spin_unlock_irqrestore(&udc->lock, flags); + + DMSG_INFO_UDC("sw_usb_device_disable end\n"); + + return 0; +} +EXPORT_SYMBOL(sw_usb_device_disable); + +/* +******************************************************************************* +* sw_udc_probe_otg +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_probe_otg(struct platform_device *pdev) +{ + struct sw_udc *udc = &sw_udc; + + g_udc_pdev = pdev; + + spin_lock_init (&udc->lock); + + device_initialize(&udc->gadget.dev); + udc->gadget.dev.parent = &pdev->dev; + udc->gadget.dev.dma_mask = pdev->dev.dma_mask; + + sw_udc_reinit(udc); + + the_controller = udc; + platform_set_drvdata(pdev, udc); + + return usb_add_gadget_udc(&pdev->dev, &udc->gadget); +} + +/* +******************************************************************************* +* sw_udc_remove_otg +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_remove_otg(struct platform_device *pdev) +{ + struct sw_udc *udc = NULL; + + g_udc_pdev = NULL; + + udc = platform_get_drvdata(pdev); + if (udc->driver){ + DMSG_PANIC("ERR: invalid argment, udc->driver(0x%p)\n", udc->driver); + return -EBUSY; + } + usb_del_gadget_udc(&udc->gadget); + return 0; +} + + +/* +******************************************************************************* +* sw_udc_probe_device_only +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_probe_device_only(struct platform_device *pdev) +{ + struct sw_udc *udc = &sw_udc; +// struct device *dev = &pdev->dev; + int retval = 0; + int irq = SW_INT_IRQNO_USB0; + + memset(&g_sw_udc_io, 0, sizeof(sw_udc_io_t)); + + retval = sw_udc_io_init(usbd_port_no, pdev, &g_sw_udc_io); + if(retval != 0){ + DMSG_PANIC("ERR: sw_udc_io_init failed\n"); + return -1; + } + + spin_lock_init (&udc->lock); + + device_initialize(&udc->gadget.dev); + udc->gadget.dev.parent = &pdev->dev; + udc->gadget.dev.dma_mask = pdev->dev.dma_mask; + + is_controller_alive = 1; + the_controller = udc; + platform_set_drvdata(pdev, udc); + + sw_udc_disable(udc); + sw_udc_reinit(udc); + + udc->sw_udc_io = &g_sw_udc_io; + udc->usbc_no = usbd_port_no; + strcpy((char *)udc->driver_name, gadget_name); + udc->irq_no = irq; + + if(is_udc_support_dma()){ + retval = sw_udc_dma_probe(udc); + if(retval != 0){ + DMSG_PANIC("ERR: sw_udc_dma_probe failef\n"); + retval = -EBUSY; + goto err; + } + } + + retval = request_irq(irq, sw_udc_irq, + IRQF_DISABLED, gadget_name, udc); + if (retval != 0) { + DMSG_PANIC("ERR: cannot get irq %i, err %d\n", irq, retval); + retval = -EBUSY; + goto err; + } + + retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget); + if (retval) + goto err; + + return 0; + +err: + if(is_udc_support_dma()){ + sw_udc_dma_remove(udc); + } + + sw_udc_io_exit(usbd_port_no, pdev, &g_sw_udc_io); + + return retval; +} + +/* +******************************************************************************* +* sw_udc_remove_device_only +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_remove_device_only(struct platform_device *pdev) +{ + struct sw_udc *udc = platform_get_drvdata(pdev); + + if (udc->driver){ + DMSG_PANIC("ERR: invalid argment\n"); + return -EBUSY; + } + + if(is_udc_support_dma()){ + sw_udc_dma_remove(udc); + } + + free_irq(udc->irq_no, udc); + + sw_udc_io_exit(usbd_port_no, pdev, &g_sw_udc_io); + + return 0; +} + +/* +******************************************************************************* +* sw_udc_probe +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int __init sw_udc_probe(struct platform_device *pdev) +{ +#ifdef CONFIG_USB_SW_SUNXI_USB0_OTG + struct sw_udc_mach_info *udc_cfg = pdev->dev.platform_data; + + switch(udc_cfg->port_info->port_type){ + case USB_PORT_TYPE_DEVICE: + return sw_udc_probe_device_only(pdev); + //break; + + case USB_PORT_TYPE_OTG: + return sw_udc_probe_otg(pdev); + //break; + + default: + DMSG_PANIC("ERR: unkown port_type(%d)\n", udc_cfg->port_info->port_type); + } + + return 0; +#else + return sw_udc_probe_device_only(pdev); +#endif +} + +static int __devexit sw_udc_remove(struct platform_device *pdev) +{ +#ifdef CONFIG_USB_SW_SUNXI_USB0_OTG + struct sw_udc_mach_info *udc_cfg = pdev->dev.platform_data; + + switch(udc_cfg->port_info->port_type){ + case USB_PORT_TYPE_DEVICE: + return sw_udc_remove_device_only(pdev); + //break; + + case USB_PORT_TYPE_OTG: + return sw_udc_remove_otg(pdev); + //break; + + default: + DMSG_PANIC("ERR: unkown port_type(%d)\n", udc_cfg->port_info->port_type); + } + + return 0; +#else + return sw_udc_remove_device_only(pdev); +#endif +} + +/* +******************************************************************************* +* sw_udc_suspend +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_suspend(struct platform_device *pdev, pm_message_t message) +{ + struct sw_udc *udc = platform_get_drvdata(pdev); + + DMSG_INFO_UDC("sw_udc_suspend start\n"); + + if(!is_peripheral_active()){ + DMSG_INFO_UDC("udc is disable, need not enter to suspend\n"); + return 0; + } + + /* 如果 USB 没有接 PC, 就可以进入 suspend。 + * 如果 USB 接了 PC, 就不进入 suspend + */ + if(usb_connect){ + DMSG_PANIC("ERR: usb is connect to PC, can not suspend\n"); + return -EBUSY; + } + + /* soft disconnect */ + cfg_udc_command(SW_UDC_P_DISABLE); + + /* disable usb controller */ + if (udc->driver && udc->driver->disconnect) { + udc->driver->disconnect(&udc->gadget); + } + + sw_udc_disable(udc); + + /* close USB clock */ + close_usb_clock(&g_sw_udc_io); + + DMSG_INFO_UDC("sw_udc_suspend end\n"); + + return 0; +} + +/* +******************************************************************************* +* sw_udc_resume +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int sw_udc_resume(struct platform_device *pdev) +{ + struct sw_udc *udc = platform_get_drvdata(pdev); + + DMSG_INFO_UDC("sw_udc_resume start\n"); + + if(!is_peripheral_active()){ + DMSG_INFO_UDC("udc is disable, need not enter to resume\n"); + return 0; + } + + /* open USB clock */ + open_usb_clock(&g_sw_udc_io); + + if (is_udc_enable){ + /* enable usb controller */ + sw_udc_set_pullup(udc, 1); + } + + DMSG_INFO_UDC("sw_udc_resume end\n"); + + return 0; +} + +static struct platform_driver sw_udc_driver = { + .driver = { + .name = (char *)gadget_name, + .bus = &platform_bus_type, + .owner = THIS_MODULE, + }, + +// .probe = sw_udc_probe, + .remove = __devexit_p(sw_udc_remove), + .suspend = sw_udc_suspend, + .resume = sw_udc_resume, +}; + +static void cfg_udc_command(enum sw_udc_cmd_e cmd) +{ + struct sw_udc *udc = the_controller; + + switch (cmd) + { + case SW_UDC_P_ENABLE: + { + if(udc->driver){ + usbd_start_work(); + }else{ + DMSG_INFO("udc->driver is null, udc is need not start\n"); + } + } + break; + + case SW_UDC_P_DISABLE: + { + if(udc->driver){ + usbd_stop_work(); + }else{ + DMSG_INFO("udc->driver is null, udc is need not stop\n"); + } + } + break; + + case SW_UDC_P_RESET : + DMSG_PANIC("ERR: reset is not support\n"); + break; + + default: + DMSG_PANIC("ERR: unkown cmd(%d)\n",cmd); + break; + } + + return ; +} + +static void cfg_vbus_draw(unsigned int ma) +{ + return; +} + +/* +******************************************************************************* +* udc_init +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static int __init udc_init(void) +{ + DMSG_INFO_UDC("udc_init: version %s\n", DRIVER_VERSION); + + usb_connect = 0; + + /* driver register */ + return platform_driver_probe(&sw_udc_driver, sw_udc_probe); +} + +/* +******************************************************************************* +* udc_exit +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static void __exit udc_exit(void) +{ + DMSG_INFO_UDC("udc_exit: version %s\n", DRIVER_VERSION); + /*TODO: add remove udc gadget driver*/ + platform_driver_unregister(&sw_udc_driver); + + return ; +} + +//module_init(udc_init); +fs_initcall(udc_init); +module_exit(udc_exit); + +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_VERSION(DRIVER_VERSION); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:softwinner-usbgadget"); + + diff --git a/patch/linux-sunxi/drivers/usb/sunxi_usb/usbc/usbc_phy.c b/patch/linux-sunxi/drivers/usb/sunxi_usb/usbc/usbc_phy.c new file mode 100644 index 0000000..96d09d3 --- /dev/null +++ b/patch/linux-sunxi/drivers/usb/sunxi_usb/usbc/usbc_phy.c @@ -0,0 +1,669 @@ +/* + * drivers/usb/sunxi_usb/usbc/usbc_phy.c + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * daniel + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include "usbc_i.h" + + +/* + *************************************************************************** + * + * 定义USB PHY控制寄存器位 + * + *************************************************************************** + */ + +//Common Control Bits for Both PHYs +#define USBC_PHY_PLL_BW 0x03 +#define USBC_PHY_RES45_CAL_EN 0x0c + +//Private Control Bits for Each PHY +#define USBC_PHY_TX_AMPLITUDE_TUNE 0x20 +#define USBC_PHY_TX_SLEWRATE_TUNE 0x22 +#define USBC_PHY_VBUSVALID_TH_SEL 0x25 +#define USBC_PHY_PULLUP_RES_SEL 0x27 +#define USBC_PHY_OTG_FUNC_EN 0x28 +#define USBC_PHY_VBUS_DET_EN 0x29 +#define USBC_PHY_DISCON_TH_SEL 0x2a + +#if 0 +/* + *************************************************************************** + * + * read out one bit of USB PHY register + * + *************************************************************************** + */ +static __u32 __USBC_PHY_REG_READ(__u32 usbc_base_addr, __u32 usbc_phy_reg_addr) +{ + __u32 reg_val = 0; + __u32 i = 0; + + USBC_Writeb(usbc_phy_reg_addr, USBC_REG_PHYCTL(USBC0_REGS_BASE) + 1); + for(i=0; i<0x4; i++); + reg_val = USBC_Readb(USBC_REG_PHYCTL(USBC0_REGS_BASE) + 2); + if(usbc_base_addr == USBC0_REGS_BASE) + return (reg_val & 0x1); + else + return ((reg_val >> 1) & 0x1); +} + +/* + *************************************************************************** + * + * Write one bit of USB PHY register + * + *************************************************************************** + */ +static void __USBC_PHY_REG_WRITE(__u32 usbc_base_addr, __u32 usbc_phy_reg_addr, __u32 usbc_phy_reg_data) +{ + __u32 reg_val = 0; + + USBC_Writeb(usbc_phy_reg_addr, USBC_REG_PHYCTL(USBC0_REGS_BASE) + 1); + reg_val = USBC_Readb(USBC_REG_PHYCTL(USBC0_REGS_BASE)); + reg_val &= ~(0x1 << 7); + reg_val |= (usbc_phy_reg_data & 0x1) << 7; + if(usbc_base_addr == USBC0_REGS_BASE){ + reg_val &= ~0x1; + USBC_Writeb(reg_val, USBC_REG_PHYCTL(USBC0_REGS_BASE)); + reg_val |= 0x1; + USBC_Writeb(reg_val, USBC_REG_PHYCTL(USBC0_REGS_BASE)); + reg_val &= ~0x1; + USBC_Writeb(reg_val, USBC_REG_PHYCTL(USBC0_REGS_BASE)); + }else{ + reg_val &= ~0x2; + USBC_Writeb(reg_val, USBC_REG_PHYCTL(USBC0_REGS_BASE)); + reg_val |= 0x2; + USBC_Writeb(reg_val, USBC_REG_PHYCTL(USBC0_REGS_BASE)); + reg_val &= ~0x2; + USBC_Writeb(reg_val, USBC_REG_PHYCTL(USBC0_REGS_BASE)); + } +} + + +/* + *************************************************************************** + * + * Set USB PLL BandWidth, val = 0~3, defualt = 0x2 + * + *************************************************************************** + */ +/* +static void __USBC_PHY_SET_PLL_BW(__u32 val) +{ + __USBC_PHY_REG_WRITE(USBC0_REGS_BASE, USBC_PHY_PLL_BW, val); + __USBC_PHY_REG_WRITE(USBC0_REGS_BASE, USBC_PHY_PLL_BW + 1, val >> 1); +} +*/ + +/* + *************************************************************************** + * + * Enable/Disable USB res45 Calibration, val = 0--Disable；1--Enable, default = 0 + * + *************************************************************************** + */ +static void __USBC_PHY_RES45_CALIBRATION_ENABLE(__u32 val) +{ + __USBC_PHY_REG_WRITE(USBC0_REGS_BASE, USBC_PHY_RES45_CAL_EN, val); +} + +/* + *************************************************************************** + * + * Set USB TX Signal Amplitude, val = 0~3, default = 0x0 + * + *************************************************************************** + */ +static void __USBC_PHY_SET_TX_AMPLITUDE(__u32 usbc_base_addr, __u32 val) +{ + __USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_TX_AMPLITUDE_TUNE, val); + __USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_TX_AMPLITUDE_TUNE + 1, val >> 1); +} + +/* + *************************************************************************** + * + * Set USB TX Signal Slew Rate, val = 0~7, default = 0x5 + * + *************************************************************************** + */ +static void __USBC_PHY_SET_TX_SLEWRATE(__u32 usbc_base_addr, __u32 val) +{ + __USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_TX_SLEWRATE_TUNE, val); + __USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_TX_SLEWRATE_TUNE + 1, val >> 1); + __USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_TX_SLEWRATE_TUNE + 2, val >> 2); +} + +/* + *************************************************************************** + * + * Set USB VBUS Valid Threshold, val = 0~3, default = 2 + * + *************************************************************************** + */ +/* +static void __USBC_PHY_SET_VBUS_VALID_THRESHOLD(__u32 usbc_base_addr, __u32 val) +{ + __USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_VBUSVALID_TH_SEL, val); + __USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_VBUSVALID_TH_SEL + 1, val >> 1); +} +*/ + +/* + *************************************************************************** + * + * Enable/Diasble USB OTG Function, val = 0--Disable；1--Enable, default = 1 + * + *************************************************************************** + */ +/* +static void __USBC_PHY_OTG_FUNC_ENABLE(__u32 usbc_base_addr, __u32 val) +{ + __USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_OTG_FUNC_EN, val); +} +*/ + +/* + *************************************************************************** + * + * Enable/Diasble USB VBUS Detect Function, val = 0--Disable；1--Enable, default = 1 + * + *************************************************************************** + */ +/* +static void __USBC_PHY_VBUS_DET_ENABLE(__u32 usbc_base_addr, __u32 val) +{ + __USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_VBUS_DET_EN, val); +} +*/ + +/* + *************************************************************************** + * + * Set USB Disconnect Detect Threshold, val = 0~3, default = 1 + * + *************************************************************************** + */ +static void __USBC_PHY_SET_DISCON_DET_THRESHOLD(__u32 usbc_base_addr, __u32 val) +{ + __USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_DISCON_TH_SEL, val); + __USBC_PHY_REG_WRITE(usbc_base_addr, USBC_PHY_DISCON_TH_SEL + 1, val >> 1); +} +#endif + +/* +*********************************************************************************** +* USBC_PHY_SetCommonConfig +* +* Description: +* Phy的公共设置，用于USB PHY的公共初始化 +* +* Arguments: +* NULL +* +* Returns: +* NULL +* +* note: +* 无 +* +*********************************************************************************** +*/ +void USBC_PHY_SetCommonConfig(void) +{ + //__USBC_PHY_RES45_CALIBRATION_ENABLE(1); +} + +/* +*********************************************************************************** +* USBC_PHY_SetPrivateConfig +* +* Description: +* USB PHY的各自设置 +* +* Arguments: +* hUSB : input. USBC_open_otg获得的句柄, 记录了USBC所需要的一些关键数据 +* +* Returns: +* NULL +* +* note: +* 无 +* +*********************************************************************************** +*/ +void USBC_PHY_SetPrivateConfig(__hdle hUSB) +{ +// __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB; +// +// if(usbc_otg == NULL){ +// return ; +// } +// +// USBC_REG_set_bit_l(0, USBC_REG_PHYTUNE(usbc_otg->base_addr)); +// USBC_REG_set_bit_l(7, USBC_REG_PHYTUNE(usbc_otg->base_addr)); +// USBC_REG_set_bit_l(6, USBC_REG_PHYTUNE(usbc_otg->base_addr)); +// USBC_REG_set_bit_l(5, USBC_REG_PHYTUNE(usbc_otg->base_addr)); +// USBC_REG_set_bit_l(4, USBC_REG_PHYTUNE(usbc_otg->base_addr)); +// //__USBC_PHY_SET_TX_AMPLITUDE(usbc_otg->base_addr, 2); +// //__USBC_PHY_SET_TX_SLEWRATE(usbc_otg->base_addr, 6); +// //__USBC_PHY_SET_DISCON_DET_THRESHOLD(usbc_otg->base_addr, 3); +} + +/* +*********************************************************************************** +* USBC_PHY_GetCommonConfig +* +* Description: +* 读取Phy的公共设置，主要用于Debug，看Phy的设置是否正确 +* +* Arguments: +* NULL +* +* Returns: +* 32bits的USB PHY公共设置值 +* +* note: +* 无 +* +*********************************************************************************** +*/ +__u32 USBC_PHY_GetCommonConfig(void) +{ + __u32 reg_val = 0; +/* + __u32 i = 0; + + reg_val = 0; + for(i=0; i<0x20; i++) + { + reg_val = reg_val << 1; + reg_val |= __USBC_PHY_REG_READ(USBC0_REGS_BASE, (0x1f - i)) & 0x1; + } +*/ + return reg_val; +} + +/* +*********************************************************************************** +* usb_phy0_write +*Description: +* 写usb phy0的phy寄存器，主要用于phy0 standby时的写入 +* +*Arguments: +* address, data, dmask +* +*returns: +* return the data wrote +* +*note: +* no +************************************************************************************ +*/ + +static __u32 usb_phy0_write(__u32 addr, __u32 data, __u32 dmask, __u32 usbc_base_addr) +{ + __u32 i=0; + + data = data & 0x0f; + addr = addr & 0x0f; + dmask = dmask & 0x0f; + + USBC_Writeb((dmask<<4)|data, usbc_base_addr + 0x404 + 2); + USBC_Writeb(addr|0x10, usbc_base_addr + 0x404); + for(i=0;i<5;i++); + USBC_Writeb(addr|0x30, usbc_base_addr + 0x404); + for(i=0;i<5;i++); + USBC_Writeb(addr|0x10, usbc_base_addr + 0x404); + for(i=0;i<5;i++); + return (USBC_Readb(usbc_base_addr + 0x404 + 3) & 0x0f); +} + +/* +******************************************************************************* +* USBC_phy_Standby +* +* Description: +* Standby the usb phy with the input usb phy index number +* +* Parameters: +* usb phy index number, which used to select the phy to standby +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +void USBC_phy_Standby(__hdle hUSB, __u32 phy_index) +{ + __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB; + + if(phy_index == 0){ + usb_phy0_write(0xB, 0x8, 0xf, usbc_otg->base_addr); + usb_phy0_write(0x7, 0xf, 0xf, usbc_otg->base_addr); + usb_phy0_write(0x1, 0xf, 0xf, usbc_otg->base_addr); + usb_phy0_write(0x2, 0xf, 0xf, usbc_otg->base_addr); + } + + return; +} + +/* +******************************************************************************* +* USBC_Phy_Standby_Recover +* +* Description: +* Recover the standby phy with the input index number +* +* Parameters: +* usb phy index number +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +void USBC_Phy_Standby_Recover(__hdle hUSB, __u32 phy_index) +{ + __u32 i; + + if(phy_index == 0){ + for(i=0; i<0x10; i++); + } + + return; +} + +/* +******************************************************************************* +* USBC_Phy_GetCsr +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static __u32 USBC_Phy_GetCsr(__u32 usbc_no) +{ + __u32 val = 0x0; + + switch(usbc_no){ + case 0: + val = SW_VA_USB0_IO_BASE + 0x404; + break; + + case 1: + val = SW_VA_USB0_IO_BASE + 0x404; + break; + + case 2: + val = SW_VA_USB0_IO_BASE + 0x404; + break; + + default: + break; + } + + return val; +} + +/* +******************************************************************************* +* USBC_Phy_TpRead +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +#if 0 +static __u32 USBC_Phy_TpRead(__u32 usbc_no, __u32 addr, __u32 len) +{ + __u32 temp = 0, ret = 0; + __u32 i=0; + __u32 j=0; + + for(j = len; j > 0; j--) + { + /* set the bit address to be read */ + temp = USBC_Readl(USBC_Phy_GetCsr(usbc_no)); + temp &= ~(0xff << 8); + temp |= ((addr + j -1) << 8); + USBC_Writel(temp, USBC_Phy_GetCsr(usbc_no)); + + for(i = 0; i < 0x4; i++); + + temp = USBC_Readl(USBC_Phy_GetCsr(usbc_no)); + ret <<= 1; + ret |= ((temp >> (16 + usbc_no)) & 0x1); + } + + return ret; +} +#endif + +/* +******************************************************************************* +* USBC_Phy_TpWrite +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static __u32 USBC_Phy_TpWrite(__u32 usbc_no, __u32 addr, __u32 data, __u32 len) +{ + __u32 temp = 0, dtmp = 0; +// __u32 i=0; + __u32 j=0; + + dtmp = data; + for(j = 0; j < len; j++) + { + /* set the bit address to be write */ + temp = USBC_Readl(USBC_Phy_GetCsr(usbc_no)); + temp &= ~(0xff << 8); + temp |= ((addr + j) << 8); + USBC_Writel(temp, USBC_Phy_GetCsr(usbc_no)); + + temp = USBC_Readb(USBC_Phy_GetCsr(usbc_no)); + temp &= ~(0x1 << 7); + temp |= (dtmp & 0x1) << 7; + temp &= ~(0x1 << (usbc_no << 1)); + USBC_Writeb(temp, USBC_Phy_GetCsr(usbc_no)); + + temp = USBC_Readb(USBC_Phy_GetCsr(usbc_no)); + temp |= (0x1 << (usbc_no << 1)); + USBC_Writeb( temp, USBC_Phy_GetCsr(usbc_no)); + + temp = USBC_Readb(USBC_Phy_GetCsr(usbc_no)); + temp &= ~(0x1 << (usbc_no <<1 )); + USBC_Writeb(temp, USBC_Phy_GetCsr(usbc_no)); + dtmp >>= 1; + } + + return data; +} + +/* +******************************************************************************* +* USBC_Phy_Read +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +#if 0 +static __u32 USBC_Phy_Read(__u32 usbc_no, __u32 addr, __u32 len) +{ + return USBC_Phy_TpRead(usbc_no, addr, len); +} +#endif + +/* +******************************************************************************* +* USBC_Phy_Write +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +static __u32 USBC_Phy_Write(__u32 usbc_no, __u32 addr, __u32 data, __u32 len) +{ + return USBC_Phy_TpWrite(usbc_no, addr, data, len); +} + +/* +******************************************************************************* +* UsbPhyInit +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +void UsbPhyInit(__u32 usbc_no) +{ +// DMSG_INFO("csr1: usbc%d: 0x%x\n", usbc_no, (u32)USBC_Readl(USBC_Phy_GetCsr(usbc_no))); + + /* 调节45欧阻抗 */ + if(usbc_no == 0){ + USBC_Phy_Write(usbc_no, 0x0c, 0x01, 1); + } + +// DMSG_INFO("csr2-0: usbc%d: 0x%x\n", usbc_no, (u32)USBC_Phy_Read(usbc_no, 0x0c, 1)); + + /* 调整 USB0 PHY 的幅度和速率 */ + USBC_Phy_Write(usbc_no, 0x20, 0x14, 5); + +// DMSG_INFO("csr2-1: usbc%d: 0x%x\n", usbc_no, (u32)USBC_Phy_Read(usbc_no, 0x20, 5)); + + /* 调节 disconnect 域值 */ +#ifdef CONFIG_ARCH_SUN4I + USBC_Phy_Write(usbc_no, 0x2a, 3, 2); +#else + USBC_Phy_Write(usbc_no, 0x2a, 2, 2); +#endif + +// DMSG_INFO("csr2: usbc%d: 0x%x\n", usbc_no, (u32)USBC_Phy_Read(usbc_no, 0x2a, 2)); +// DMSG_INFO("csr3: usbc%d: 0x%x\n", usbc_no, (u32)USBC_Readl(USBC_Phy_GetCsr(usbc_no))); + + return; +} +EXPORT_SYMBOL(UsbPhyInit); + +/* +******************************************************************************* +* UsbPhyEndReset +* +* Description: +* void +* +* Parameters: +* void +* +* Return value: +* void +* +* note: +* void +* +******************************************************************************* +*/ +void UsbPhyEndReset(__u32 usbc_no) +{ + int i; + + if(usbc_no == 0){ + //Disable Sequelch Detect for a while before Release USB Reset + USBC_Phy_Write(usbc_no, 0x3c, 0x2, 2); + for(i=0; i<0x100; i++); + USBC_Phy_Write(usbc_no, 0x3c, 0x0, 2); + } + + return; +} + diff --git a/patch/linux-sunxi/drivers/video/sunxi/hdmi/hdmi_core.c b/patch/linux-sunxi/drivers/video/sunxi/hdmi/hdmi_core.c index 07c322a..8b97f3b 100644 --- a/patch/linux-sunxi/drivers/video/sunxi/hdmi/hdmi_core.c +++ b/patch/linux-sunxi/drivers/video/sunxi/hdmi/hdmi_core.c @@ -242,9 +242,33 @@ static __s32 get_audio_info(__s32 sample_rate) * ACR_N 32000 44100 48000 88200 96000 176400 192000 * 4096 6272 6144 12544 12288 25088 24576 */ - __inf("sample_rate:%d in get_audio_info\n", sample_rate); + /* FIXME: for scratch */ + if ( sample_rate >= 22000 && sample_rate <= 22100 ) + sample_rate = 22050; + printk("sample_rate:%d in get_audio_info\n", sample_rate); switch (sample_rate) { + case 8000: + audio_info.ACR_N = 1024; + audio_info.CH_STATUS0 = (3 << 24); + audio_info.CH_STATUS1 = 0x0000000b; + break; + case 16000: + audio_info.ACR_N = 2048; + audio_info.CH_STATUS0 = (3 << 24); + audio_info.CH_STATUS1 = 0x0000000b; + break; + case 11025: + audio_info.ACR_N = 1568; + audio_info.CH_STATUS0 = (0 << 24); + audio_info.CH_STATUS1 = 0x0000000b; + break; + case 22050: + audio_info.ACR_N = 3136; + audio_info.CH_STATUS0 = (0 << 24); + audio_info.CH_STATUS1 = 0x0000000b; + break; + case 32000: audio_info.ACR_N = 4096; audio_info.CH_STATUS0 = (3 << 24); diff --git a/patch/linux-sunxi/drivers/video/sunxi/hdmi/hdmi_i2c.c b/patch/linux-sunxi/drivers/video/sunxi/hdmi/hdmi_i2c.c new file mode 100644 index 0000000..e4469d6 --- /dev/null +++ b/patch/linux-sunxi/drivers/video/sunxi/hdmi/hdmi_i2c.c @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2013 Jari Helaakoski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../disp/sunxi_disp_regs.h" +#include "hdmi_core.h" + +#define Abort_Current_Operation 0 +#define Special_Offset_Address_Read 1 +#define Explicit_Offset_Address_Write 2 +#define Implicit_Offset_Address_Write 3 +#define Explicit_Offset_Address_Read 4 +#define Implicit_Offset_Address_Read 5 +#define Explicit_Offset_Address_E_DDC_Read 6 +#define Implicit_Offset_Address_E_DDC_Read 7 + +#define Command_Ok 0x11 + +struct i2c_adapter sunxi_hdmi_i2c_adapter; + +static int init_connection(void __iomem *base_addr) +{ + /* Make sure that HDMI core functionality is initialized. + Currently support I2C only when HDMI is connected */ + if (!(readl(HDMI_HPD) & 0x01)) { + pr_info("HDMI not connected\n"); + return -EIO; + } + + /* Reset */ + writel(0, HDMI_I2C_GENERAL_2); + writel(0x80000001, HDMI_I2C_GENERAL); + hdmi_delay_ms(1); + + if (readl(HDMI_I2C_GENERAL) & 0x1) { + pr_info("EDID not ready\n"); + return -EIO; + } + + /* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */ + writel(0x0d, HDMI_I2C_CLK); + + /* ddc address 0x60 */ + /*writeb(0x60, HDMI_BASE + HDMI_I2C_LINE_CTRL);*/ + + /* slave address 0xa0 */ + /*writeb(0xa0 >> 1, HDMI_BASE + HDMI_I2C_LINE_CTRL);*/ + + /* enable analog sda/scl pad */ + writel((0 << 12) | (3 << 8), HDMI_I2C_LINE_CTRL); + return 0; +} + +static int do_command(void __iomem *base_addr, + int command, u8 address, u8 len, u8 chip_addr) +{ + __u32 begin_ms, end_ms; + u8 block = 0; + + /* set FIFO read */ + writel(readl(HDMI_I2C_GENERAL) & 0xfffffeff, + HDMI_I2C_GENERAL); + + writel((block << 24) | (0x60 << 16) | (chip_addr << 8) | + address, HDMI_I2C_ADDR); + + /* FIFO address clear */ + writel(readl(HDMI_I2C_GENERAL_2) | 0x80000000, + HDMI_I2C_GENERAL_2); + + /* nbyte to access */ + writel(len, HDMI_I2C_DATA_LENGTH); + + /* set cmd type */ + writel(command, HDMI_I2C_CMD); + + /* start and cmd */ + writel(readl(HDMI_I2C_GENERAL) | 0x40000000, + HDMI_I2C_GENERAL); + + begin_ms = (jiffies * 1000) / HZ; + while (readl(HDMI_I2C_GENERAL) & 0x40000000) { + end_ms = (jiffies * 1000) / HZ; + if ((end_ms - begin_ms) > 1000) { + pr_warning("ddc read timeout 0x%X\n", + readl(HDMI_I2C_GENERAL)); + return -ETIMEDOUT; + } + schedule(); + } + + if (Command_Ok != readl(HDMI_I2C_STATUS)) + return -EIO; + + return 0; +} + +static int do_read(void __iomem *base_addr, + struct i2c_msg *msg, int command, u8 chip_addr) +{ + int i = 0; + int err = 0; + u8 bufPos = 0; + + while (bufPos < msg->len) { + u8 readLen = (msg->len > 16) ? 16 : msg->len; + + err = do_command(base_addr, command, + msg->addr, readLen, + chip_addr); + + if (err != 0) + return err; + + for (i = 0; i < readLen; i++) + *msg->buf++ = readb(HDMI_I2C_DATA); + + bufPos += readLen; + chip_addr += readLen; + } + return err; +} + +static int hdmi_i2c_sunxi_xfer(struct i2c_adapter *adap, + struct i2c_msg *msgs, int num) +{ + int i = 0; + int err = 0; + u8 chip_addr = 0; + int command = Implicit_Offset_Address_Read; + void __iomem *base_addr = (void __iomem *)adap->algo_data; + + if (init_connection(base_addr)) + return -EIO; + + for (i = 0; i < num; i++) { + if (msgs[i].flags & I2C_M_RD) { + err = do_read(base_addr, &msgs[i], command, chip_addr); + } else { + command = Explicit_Offset_Address_Read; + chip_addr = *msgs[i].buf; + err = do_command(base_addr, command, + msgs[i].addr, 0, + chip_addr); + } + + pr_debug("%s msgs[i].addr:0x%X msgs[i].len:%i" + " msgs[i].flags:0x%X err:%i\n", + __func__, msgs[i].addr, msgs[i].len, + msgs[i].flags, err); + + if (err) + break; + + } + + if (err) + return err; + + return i; +} + +static unsigned int hdmi_i2c_sunxi_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C|I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm hdmi_i2c_sunxi_algorithm = { + .master_xfer = hdmi_i2c_sunxi_xfer, + .functionality = hdmi_i2c_sunxi_functionality, +}; + +int hdmi_i2c_sunxi_probe(struct platform_device *dev) +{ + int ret; + strlcpy(sunxi_hdmi_i2c_adapter.name, "sunxi-hdmi-i2c", + sizeof(sunxi_hdmi_i2c_adapter.name)); + sunxi_hdmi_i2c_adapter.owner = THIS_MODULE; + sunxi_hdmi_i2c_adapter.retries = 2; + sunxi_hdmi_i2c_adapter.timeout = 5*HZ; + sunxi_hdmi_i2c_adapter.class = I2C_CLASS_DDC; + sunxi_hdmi_i2c_adapter.algo = &hdmi_i2c_sunxi_algorithm; + sunxi_hdmi_i2c_adapter.dev.parent = &dev->dev; + sunxi_hdmi_i2c_adapter.algo_data = (void *)0xf1c16000; + sunxi_hdmi_i2c_adapter.nr = 10; + + + //ret = i2c_add_adapter(&sunxi_hdmi_i2c_adapter); + ret = i2c_add_numbered_adapter(&sunxi_hdmi_i2c_adapter); + if (ret < 0) { + pr_warning("I2C: Failed to add bus\n"); + return ret; + } + + platform_set_drvdata(dev, &sunxi_hdmi_i2c_adapter); + + + + pr_info("I2C: %s: HDMI I2C adapter\n", + dev_name(&sunxi_hdmi_i2c_adapter.dev)); + return 0; +} + +int hdmi_i2c_sunxi_remove(struct platform_device *dev) +{ + struct i2c_adapter *i2c = platform_get_drvdata(dev); + if (i2c) + i2c_del_adapter(i2c); + + return 0; +} + +#if 0 /* Legacy comment */ +void send_ini_sequence() +{ + int i, j; + + set_wbit(HDMI_I2C_UNKNOWN_0, BIT3); + for (i = 0; i < 9; i++) { + for (j = 0; j < 200; j++) /*for simulation, delete it*/ + ; + clr_wbit(HDMI_I2C_UNKNOWN_0, BIT2); + + for (j = 0; j < 200; j++) /*for simulation, delete it*/ + ; + set_wbit(HDMI_I2C_UNKNOWN_0, BIT2); + } + + clr_wbit(HDMI_I2C_UNKNOWN_0, BIT3); + clr_wbit(HDMI_I2C_UNKNOWN_0, BIT1); +} +#endif diff --git a/patch/linux-sunxi/rootfs/sun7i_rootfs.cpio.xz b/patch/linux-sunxi/rootfs/sun7i_rootfs.cpio.xz index 94d8af3..2ddecbf 100644 Binary files a/patch/linux-sunxi/rootfs/sun7i_rootfs.cpio.xz and b/patch/linux-sunxi/rootfs/sun7i_rootfs.cpio.xz differ diff --git a/patch/linux-sunxi/usr/initramfs_data.cpio.xz b/patch/linux-sunxi/usr/initramfs_data.cpio.xz new file mode 100644 index 0000000..2ddecbf Binary files /dev/null and b/patch/linux-sunxi/usr/initramfs_data.cpio.xz differ diff --git a/patch/u-boot-sunxi/Makefile b/patch/u-boot-sunxi/Makefile new file mode 100644 index 0000000..87f79ec --- /dev/null +++ b/patch/u-boot-sunxi/Makefile @@ -0,0 +1,1419 @@ +# +# (C) Copyright 2000-2013 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +VERSION = 2014 +PATCHLEVEL = 04 +SUBLEVEL = +EXTRAVERSION = -rc3 +NAME = + +# *DOCUMENTATION* +# To see a list of typical targets execute "make help" +# More info can be located in ./README +# Comments in this file are targeted only to the developer, do not +# expect to learn how to build the kernel reading this file. + +# Do not: +# o use make's built-in rules and variables +# (this increases performance and avoids hard-to-debug behaviour); +# o print "Entering directory ..."; +MAKEFLAGS += -rR --no-print-directory + +# Avoid funny character set dependencies +unexport LC_ALL +LC_COLLATE=C +LC_NUMERIC=C +export LC_COLLATE LC_NUMERIC + +# We are using a recursive build, so we need to do a little thinking +# to get the ordering right. +# +# Most importantly: sub-Makefiles should only ever modify files in +# their own directory. If in some directory we have a dependency on +# a file in another dir (which doesn't happen often, but it's often +# unavoidable when linking the built-in.o targets which finally +# turn into vmlinux), we will call a sub make in that other dir, and +# after that we are sure that everything which is in that other dir +# is now up to date. +# +# The only cases where we need to modify files which have global +# effects are thus separated out and done before the recursive +# descending is started. They are now explicitly listed as the +# prepare rule. + +# To put more focus on warnings, be less verbose as default +# Use 'make V=1' to see the full commands + +ifeq ("$(origin V)", "command line") + KBUILD_VERBOSE = $(V) +endif +ifndef KBUILD_VERBOSE + KBUILD_VERBOSE = 0 +endif + +# Call a source code checker (by default, "sparse") as part of the +# C compilation. +# +# Use 'make C=1' to enable checking of only re-compiled files. +# Use 'make C=2' to enable checking of *all* source files, regardless +# of whether they are re-compiled or not. +# +# See the file "Documentation/sparse.txt" for more details, including +# where to get the "sparse" utility. + +ifeq ("$(origin C)", "command line") + KBUILD_CHECKSRC = $(C) +endif +ifndef KBUILD_CHECKSRC + KBUILD_CHECKSRC = 0 +endif + +# Use make M=dir to specify directory of external module to build +# Old syntax make ... SUBDIRS=$PWD is still supported +# Setting the environment variable KBUILD_EXTMOD take precedence +ifdef SUBDIRS + KBUILD_EXTMOD ?= $(SUBDIRS) +endif + +ifeq ("$(origin M)", "command line") + KBUILD_EXTMOD := $(M) +endif + +# kbuild supports saving output files in a separate directory. +# To locate output files in a separate directory two syntaxes are supported. +# In both cases the working directory must be the root of the kernel src. +# 1) O= +# Use "make O=dir/to/store/output/files/" +# +# 2) Set KBUILD_OUTPUT +# Set the environment variable KBUILD_OUTPUT to point to the directory +# where the output files shall be placed. +# export KBUILD_OUTPUT=dir/to/store/output/files/ +# make +# +# The O= assignment takes precedence over the KBUILD_OUTPUT environment +# variable. + + +# KBUILD_SRC is set on invocation of make in OBJ directory +# KBUILD_SRC is not intended to be used by the regular user (for now) +ifeq ($(KBUILD_SRC),) + +# OK, Make called in directory where kernel src resides +# Do we want to locate output files in a separate directory? +ifeq ("$(origin O)", "command line") + KBUILD_OUTPUT := $(O) +endif + +ifeq ("$(origin W)", "command line") + export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W) +endif + +# That's our default target when none is given on the command line +PHONY := _all +_all: + +# Cancel implicit rules on top Makefile +$(CURDIR)/Makefile Makefile: ; + +ifneq ($(KBUILD_OUTPUT),) +# Invoke a second make in the output directory, passing relevant variables +# check that the output directory actually exists +saved-output := $(KBUILD_OUTPUT) +KBUILD_OUTPUT := $(shell mkdir -p $(KBUILD_OUTPUT) && cd $(KBUILD_OUTPUT) \ + && /bin/pwd) +$(if $(KBUILD_OUTPUT),, \ + $(error output directory "$(saved-output)" does not exist)) + +PHONY += $(MAKECMDGOALS) sub-make + +$(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make + @: + +sub-make: FORCE + $(if $(KBUILD_VERBOSE:1=),@)$(MAKE) -C $(KBUILD_OUTPUT) \ + KBUILD_SRC=$(CURDIR) \ + KBUILD_EXTMOD="$(KBUILD_EXTMOD)" -f $(CURDIR)/Makefile \ + $(filter-out _all sub-make,$(MAKECMDGOALS)) + +# Leave processing to above invocation of make +skip-makefile := 1 +endif # ifneq ($(KBUILD_OUTPUT),) +endif # ifeq ($(KBUILD_SRC),) + +# We process the rest of the Makefile if this is the final invocation of make +ifeq ($(skip-makefile),) + +# If building an external module we do not care about the all: rule +# but instead _all depend on modules +PHONY += all +ifeq ($(KBUILD_EXTMOD),) +_all: all +else +_all: modules +endif + +srctree := $(if $(KBUILD_SRC),$(KBUILD_SRC),$(CURDIR)) +objtree := $(CURDIR) +src := $(srctree) +obj := $(objtree) + +VPATH := $(srctree)$(if $(KBUILD_EXTMOD),:$(KBUILD_EXTMOD)) + +export srctree objtree VPATH + +MKCONFIG := $(srctree)/mkconfig +export MKCONFIG + +# Make sure CDPATH settings don't interfere +unexport CDPATH + +######################################################################### + +HOSTARCH := $(shell uname -m | \ + sed -e s/i.86/x86/ \ + -e s/sun4u/sparc64/ \ + -e s/arm.*/arm/ \ + -e s/sa110/arm/ \ + -e s/ppc64/powerpc/ \ + -e s/ppc/powerpc/ \ + -e s/macppc/powerpc/\ + -e s/sh.*/sh/) + +HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \ + sed -e 's/\(cygwin\).*/cygwin/') + +export HOSTARCH HOSTOS + +# Deal with colliding definitions from tcsh etc. +VENDOR= + +######################################################################### + +# set default to nothing for native builds +ifeq ($(HOSTARCH),$(ARCH)) +CROSS_COMPILE ?= +endif + +# SHELL used by kbuild +CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ + else if [ -x /bin/bash ]; then echo /bin/bash; \ + else echo sh; fi ; fi) + +HOSTCC = gcc +HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer + +ifeq ($(HOSTOS),cygwin) +HOSTCFLAGS += -ansi +endif + +# Mac OS X / Darwin's C preprocessor is Apple specific. It +# generates numerous errors and warnings. We want to bypass it +# and use GNU C's cpp. To do this we pass the -traditional-cpp +# option to the compiler. Note that the -traditional-cpp flag +# DOES NOT have the same semantics as GNU C's flag, all it does +# is invoke the GNU preprocessor in stock ANSI/ISO C fashion. +# +# Apple's linker is similar, thanks to the new 2 stage linking +# multiple symbol definitions are treated as errors, hence the +# -multiply_defined suppress option to turn off this error. +# +ifeq ($(HOSTOS),darwin) +# get major and minor product version (e.g. '10' and '6' for Snow Leopard) +DARWIN_MAJOR_VERSION = $(shell sw_vers -productVersion | cut -f 1 -d '.') +DARWIN_MINOR_VERSION = $(shell sw_vers -productVersion | cut -f 2 -d '.') + +os_x_before = $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \ + $(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;) + +# Snow Leopards build environment has no longer restrictions as described above +HOSTCC = $(call os_x_before, 10, 5, "cc", "gcc") +HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp") +HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress") +endif + +# Decide whether to build built-in, modular, or both. +# Normally, just do built-in. + +KBUILD_MODULES := +KBUILD_BUILTIN := 1 + +# If we have only "make modules", don't compile built-in objects. +# When we're building modules with modversions, we need to consider +# the built-in objects during the descend as well, in order to +# make sure the checksums are up to date before we record them. + +ifeq ($(MAKECMDGOALS),modules) + KBUILD_BUILTIN := $(if $(CONFIG_MODVERSIONS),1) +endif + +# If we have "make modules", compile modules +# in addition to whatever we do anyway. +# Just "make" or "make all" shall build modules as well + +# U-Boot does not need modules +#ifneq ($(filter all _all modules,$(MAKECMDGOALS)),) +# KBUILD_MODULES := 1 +#endif + +#ifeq ($(MAKECMDGOALS),) +# KBUILD_MODULES := 1 +#endif + +export KBUILD_MODULES KBUILD_BUILTIN +export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD + +# Beautify output +# --------------------------------------------------------------------------- +# +# Normally, we echo the whole command before executing it. By making +# that echo $($(quiet)$(cmd)), we now have the possibility to set +# $(quiet) to choose other forms of output instead, e.g. +# +# quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@ +# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $< +# +# If $(quiet) is empty, the whole command will be printed. +# If it is set to "quiet_", only the short version will be printed. +# If it is set to "silent_", nothing will be printed at all, since +# the variable $(silent_cmd_cc_o_c) doesn't exist. +# +# A simple variant is to prefix commands with $(Q) - that's useful +# for commands that shall be hidden in non-verbose mode. +# +# $(Q)ln $@ :< +# +# If KBUILD_VERBOSE equals 0 then the above command will be hidden. +# If KBUILD_VERBOSE equals 1 then the above command is displayed. + +ifeq ($(KBUILD_VERBOSE),1) + quiet = + Q = +else + quiet=quiet_ + Q = @ +endif + +# If the user is running make -s (silent mode), suppress echoing of +# commands + +ifneq ($(filter s% -s%,$(MAKEFLAGS)),) + quiet=silent_ +endif + +export quiet Q KBUILD_VERBOSE + + +# Look for make include files relative to root of kernel src +MAKEFLAGS += --include-dir=$(srctree) + +# We need some generic definitions (do not try to remake the file). +$(srctree)/scripts/Kbuild.include: ; +include $(srctree)/scripts/Kbuild.include + +# Make variables (CC, etc...) + +AS = $(CROSS_COMPILE)as +# Always use GNU ld +ifneq ($(shell $(CROSS_COMPILE)ld.bfd -v 2> /dev/null),) +LD = $(CROSS_COMPILE)ld.bfd +else +LD = $(CROSS_COMPILE)ld +endif +CC = $(CROSS_COMPILE)gcc +CPP = $(CC) -E +AR = $(CROSS_COMPILE)ar +NM = $(CROSS_COMPILE)nm +LDR = $(CROSS_COMPILE)ldr +STRIP = $(CROSS_COMPILE)strip +OBJCOPY = $(CROSS_COMPILE)objcopy +OBJDUMP = $(CROSS_COMPILE)objdump +AWK = awk +RANLIB = $(CROSS_COMPILE)RANLIB +DTC = dtc +CHECK = sparse + +CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ + -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF) + +KBUILD_CPPFLAGS := -D__KERNEL__ + +KBUILD_CFLAGS := -Wall -Wstrict-prototypes \ + -Wno-format-security \ + -fno-builtin -ffreestanding +KBUILD_AFLAGS := -D__ASSEMBLY__ + +# Read UBOOTRELEASE from include/config/uboot.release (if it exists) +UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null) +UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION) + +export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION +export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR +export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC +export CPP AR NM LDR STRIP OBJCOPY OBJDUMP +export MAKE AWK +export DTC CHECK CHECKFLAGS + +export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS +export KBUILD_CFLAGS KBUILD_AFLAGS + +# When compiling out-of-tree modules, put MODVERDIR in the module +# tree rather than in the kernel tree. The kernel tree might +# even be read-only. +export MODVERDIR := $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/).tmp_versions + +# Files to ignore in find ... statements + +RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o -name CVS \ + -o -name .pc -o -name .hg -o -name .git \) -prune -o +export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \ + --exclude CVS --exclude .pc --exclude .hg --exclude .git + +# =========================================================================== +# Rules shared between *config targets and build targets + +# Basic helpers built in scripts/ +PHONY += scripts_basic +scripts_basic: + $(Q)$(MAKE) $(build)=scripts/basic + $(Q)rm -f .tmp_quiet_recordmcount + +# To avoid any implicit rule to kick in, define an empty command. +scripts/basic/%: scripts_basic ; + +PHONY += outputmakefile +# outputmakefile generates a Makefile in the output directory, if using a +# separate output directory. This allows convenient use of make in the +# output directory. +outputmakefile: +ifneq ($(KBUILD_SRC),) + $(Q)ln -fsn $(srctree) source + $(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkmakefile \ + $(srctree) $(objtree) $(VERSION) $(PATCHLEVEL) +endif + +# To make sure we do not include .config for any of the *config targets +# catch them early, and hand them over to scripts/kconfig/Makefile +# It is allowed to specify more targets when calling make, including +# mixing *config targets and build targets. +# For example 'make oldconfig all'. +# Detect when mixed targets is specified, and make a second invocation +# of make so .config is not included in this case either (for *config). + +version_h := include/generated/version_autogenerated.h +timestamp_h := include/generated/timestamp_autogenerated.h + +no-dot-config-targets := clean clobber mrproper distclean \ + help %docs check% coccicheck \ + ubootversion backup tools-only + +config-targets := 0 +mixed-targets := 0 +dot-config := 1 + +ifneq ($(filter $(no-dot-config-targets), $(MAKECMDGOALS)),) + ifeq ($(filter-out $(no-dot-config-targets), $(MAKECMDGOALS)),) + dot-config := 0 + endif +endif + +ifeq ($(KBUILD_EXTMOD),) + ifneq ($(filter config %config,$(MAKECMDGOALS)),) + config-targets := 1 + ifneq ($(filter-out config %config,$(MAKECMDGOALS)),) + mixed-targets := 1 + endif + endif +endif + +ifeq ($(mixed-targets),1) +# =========================================================================== +# We're called with mixed targets (*config and build targets). +# Handle them one by one. + +PHONY += $(MAKECMDGOALS) build-one-by-one + +$(MAKECMDGOALS): build-one-by-one + @: + +build-one-by-one: + $(Q)set -e; \ + for i in $(MAKECMDGOALS); do \ + $(MAKE) -f $(srctree)/Makefile $$i; \ + done + +else +ifeq ($(config-targets),1) +# =========================================================================== +# *config targets only - make sure prerequisites are updated, and descend +# in scripts/kconfig to make the *config target + +# Read arch specific Makefile to set KBUILD_DEFCONFIG as needed. +# KBUILD_DEFCONFIG may point out an alternative default configuration +# used for 'make defconfig' + +unconfig: + @rm -f $(obj)include/config.h $(obj)include/config.mk \ + $(obj)board/*/config.tmp $(obj)board/*/*/config.tmp \ + $(obj)include/autoconf.mk $(obj)include/autoconf.mk.dep \ + $(obj)include/spl-autoconf.mk \ + $(obj)include/tpl-autoconf.mk + +#%_config:: outputmakefile +%_config:: unconfig + @$(MKCONFIG) -A $(@:_config=) + +sinclude $(obj).boards.depend +$(obj).boards.depend: boards.cfg + @awk '(NF && $$1 !~ /^#/) { print $$7 ": " $$7 "_config; $$(MAKE)" }' $< > $@ + @awk '(NF && $$1 !~ /^#/ && tolower($$7) != $$7) { print tolower($$7) ": " $$7 "_config; $$(MAKE)" }' $< > $@ + @awk '(NF && $$1 !~ /^#/ && tolower($$7) != $$7) { print ".PHONY: " tolower($$7) "_config"; print tolower($$7)"_config: " $$7 "_config" }' $< >> $@ + +else +# =========================================================================== +# Build targets only - this includes vmlinux, arch specific targets, clean +# targets and others. In general all targets except *config targets. + +# load ARCH, BOARD, and CPU configuration +-include include/config.mk + +ifeq ($(dot-config),1) +# Read in config +-include include/autoconf.mk +-include include/autoconf.mk.dep + +# load other configuration +include $(srctree)/config.mk + +ifeq ($(wildcard include/config.mk),) +$(error "System not configured - see README") +endif + +# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use +# that (or fail if absent). Otherwise, search for a linker script in a +# standard location. + +ifndef LDSCRIPT + #LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds.debug + ifdef CONFIG_SYS_LDSCRIPT + # need to strip off double quotes + LDSCRIPT := $(srctree)/$(CONFIG_SYS_LDSCRIPT:"%"=%) + endif +endif + +# If there is no specified link script, we look in a number of places for it +ifndef LDSCRIPT + ifeq ($(CONFIG_NAND_U_BOOT),y) + LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-nand.lds + ifeq ($(wildcard $(LDSCRIPT)),) + LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot-nand.lds + endif + endif + ifeq ($(wildcard $(LDSCRIPT)),) + LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds + endif + ifeq ($(wildcard $(LDSCRIPT)),) + LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot.lds + endif + ifeq ($(wildcard $(LDSCRIPT)),) + LDSCRIPT := $(srctree)/arch/$(ARCH)/cpu/u-boot.lds + endif +endif + +else + + +endif # $(dot-config) + +KBUILD_CFLAGS += -Os #-fomit-frame-pointer + +ifdef BUILD_TAG +KBUILD_CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"' +endif + +KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector) + +KBUILD_CFLAGS += -g +# $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g +# option to the assembler. +KBUILD_AFLAGS += -g + +# Report stack usage if supported +ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-stack-usage.sh $(CC)),y) + KBUILD_CFLAGS += -fstack-usage +endif + +KBUILD_CFLAGS += $(call cc-option,-Wno-format-nonliteral) + +# turn jbsr into jsr for m68k +ifeq ($(ARCH),m68k) +ifeq ($(findstring 3.4,$(shell $(CC) --version)),3.4) +KBUILD_AFLAGS += -Wa,-gstabs,-S +endif +endif + +ifneq ($(CONFIG_SYS_TEXT_BASE),) +KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) +endif + +export CONFIG_SYS_TEXT_BASE + +# Use UBOOTINCLUDE when you must reference the include/ directory. +# Needed to be compatible with the O= option +UBOOTINCLUDE := \ + -Iinclude \ + $(if $(KBUILD_SRC), -I$(srctree)/include) \ + -I$(srctree)/arch/$(ARCH)/include + +NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include) +CHECKFLAGS += $(NOSTDINC_FLAGS) + +# FIX ME +cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \ + $(NOSTDINC_FLAGS) +c_flags := $(KBUILD_CFLAGS) $(cpp_flags) + +######################################################################### +# U-Boot objects....order is important (i.e. start must be first) + +head-y := $(CPUDIR)/start.o +head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o +head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o + +HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n) + +libs-y += lib/ +libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ +libs-y += $(CPUDIR)/ +ifdef SOC +libs-y += $(CPUDIR)/$(SOC)/ +endif +libs-$(CONFIG_OF_EMBED) += dts/ +libs-y += arch/$(ARCH)/lib/ +libs-y += fs/ +libs-y += net/ +libs-y += disk/ +libs-y += drivers/ +libs-$(CONFIG_DM) += drivers/core/ +libs-y += drivers/dma/ +libs-y += drivers/gpio/ +libs-y += drivers/i2c/ +libs-y += drivers/input/ +libs-y += drivers/mmc/ +libs-y += drivers/mtd/ +libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/ +libs-y += drivers/mtd/onenand/ +libs-$(CONFIG_CMD_UBI) += drivers/mtd/ubi/ +libs-y += drivers/mtd/spi/ +libs-y += drivers/net/ +libs-y += drivers/net/phy/ +libs-y += drivers/pci/ +libs-y += drivers/power/ \ + drivers/power/fuel_gauge/ \ + drivers/power/mfd/ \ + drivers/power/pmic/ \ + drivers/power/battery/ +libs-y += drivers/spi/ +libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/ +libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ +libs-y += drivers/serial/ +libs-y += drivers/usb/eth/ +libs-y += drivers/usb/gadget/ +libs-y += drivers/usb/host/ +libs-y += drivers/usb/musb/ +libs-y += drivers/usb/musb-new/ +libs-y += drivers/usb/phy/ +libs-y += drivers/usb/ulpi/ +libs-y += common/ +libs-y += lib/libfdt/ +libs-$(CONFIG_API) += api/ +libs-$(CONFIG_HAS_POST) += post/ +libs-y += test/ +libs-y += test/dm/ +libs-$(CONFIG_DM_DEMO) += drivers/demo/ + +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610)) +libs-y += arch/$(ARCH)/imx-common/ +endif + +libs-$(CONFIG_ARM) += arch/arm/cpu/ +libs-$(CONFIG_PPC) += arch/powerpc/cpu/ + +libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/) + +libs-y := $(sort $(libs-y)) + +u-boot-dirs := $(patsubst %/,%,$(filter %/, $(libs-y))) tools examples + +u-boot-alldirs := $(sort $(u-boot-dirs) $(patsubst %/,%,$(filter %/, $(libs-)))) + +libs-y := $(patsubst %/, %/built-in.o, $(libs-y)) + +u-boot-init := $(head-y) +u-boot-main := $(libs-y) + + +# Add GCC lib +ifdef CONFIG_USE_PRIVATE_LIBGCC +ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y) +PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a +else +PLATFORM_LIBGCC = -L $(CONFIG_USE_PRIVATE_LIBGCC) -lgcc +endif +else +PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc +endif +PLATFORM_LIBS += $(PLATFORM_LIBGCC) +export PLATFORM_LIBS + +# Special flags for CPP when processing the linker script. +# Pass the version down so we can handle backwards compatibility +# on the fly. +LDPPFLAGS += \ + -include $(srctree)/include/u-boot/u-boot.lds.h \ + -DCPUDIR=$(CPUDIR) \ + $(shell $(LD) --version | \ + sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') + +######################################################################### +######################################################################### + +ifneq ($(CONFIG_BOARD_SIZE_LIMIT),) +BOARD_SIZE_CHECK = \ + @actual=`wc -c $@ | awk '{print $$1}'`; \ + limit=`printf "%d" $(CONFIG_BOARD_SIZE_LIMIT)`; \ + if test $$actual -gt $$limit; then \ + echo "$@ exceeds file size limit:" >&2 ; \ + echo " limit: $$limit bytes" >&2 ; \ + echo " actual: $$actual bytes" >&2 ; \ + echo " excess: $$((actual - limit)) bytes" >&2; \ + exit 1; \ + fi +else +BOARD_SIZE_CHECK = +endif + +# Statically apply RELA-style relocations (currently arm64 only) +ifneq ($(CONFIG_STATIC_RELA),) +# $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base +DO_STATIC_RELA = \ + start=$$($(NM) $(1) | grep __rel_dyn_start | cut -f 1 -d ' '); \ + end=$$($(NM) $(1) | grep __rel_dyn_end | cut -f 1 -d ' '); \ + tools/relocate-rela $(2) $(3) $$start $$end +else +DO_STATIC_RELA = +endif + +# Always append ALL so that arch config.mk's can add custom ones +ALL-y += u-boot.srec u-boot.bin System.map + +ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin +ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin +ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl +ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin +ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img +ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin +ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin +ALL-$(CONFIG_OF_HOSTFILE) += u-boot.dtb +ifneq ($(CONFIG_SPL_TARGET),) +ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) +endif +ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf + +# enable combined SPL/u-boot/dtb rules for tegra +ifneq ($(CONFIG_TEGRA),) +ifeq ($(CONFIG_SPL),y) +ifeq ($(CONFIG_OF_SEPARATE),y) +ALL-y += u-boot-dtb-tegra.bin +else +ALL-y += u-boot-nodtb-tegra.bin +endif +endif +endif + +LDFLAGS_u-boot += $(LDFLAGS_FINAL) +ifneq ($(CONFIG_SYS_TEXT_BASE),) +LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) +endif + +quiet_cmd_objcopy = OBJCOPY $@ +cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ + +quiet_cmd_mkimage = MKIMAGE $@ +cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) + +quiet_cmd_cat = CAT $@ +cmd_cat = cat $(filter-out $(PHONY), $^) > $@ + +append = cat $(filter-out $< $(PHONY), $^) >> $@ + +quiet_cmd_pad_cat = CAT $@ +cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@ + +all: $(ALL-y) + +PHONY += dtbs +dtbs dts/dt.dtb: checkdtc u-boot + $(Q)$(MAKE) $(build)=dts dtbs + +u-boot-dtb.bin: u-boot.bin dts/dt.dtb FORCE + $(call if_changed,cat) + +quiet_cmd_copy = COPY $@ + cmd_copy = cp $< $@ + +u-boot.dtb: dts/dt.dtb + $(call cmd,copy) + +OBJCOPYFLAGS_u-boot.hex := -O ihex + +OBJCOPYFLAGS_u-boot.srec := -O srec + +u-boot.hex u-boot.srec: u-boot FORCE + $(call if_changed,objcopy) + +OBJCOPYFLAGS_u-boot.bin := -O binary + +u-boot.bin: u-boot FORCE + $(call if_changed,objcopy) + $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE)) + $(BOARD_SIZE_CHECK) + +u-boot.ldr: u-boot + $(CREATE_LDR_ENV) + $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS) + $(BOARD_SIZE_CHECK) + +OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex + +OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec + +u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE + $(call if_changed,objcopy) + +# +# U-Boot entry point, needed for booting of full-blown U-Boot +# from the SPL U-Boot version. +# +ifndef CONFIG_SYS_UBOOT_START +CONFIG_SYS_UBOOT_START := 0 +endif + +MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \ + -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" + +MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \ + -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) + +MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ + -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage + +u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE + $(call if_changed,mkimage) + +u-boot.imx: u-boot.bin + $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ + +u-boot.sha1: u-boot.bin + tools/ubsha1 u-boot.bin + +u-boot.dis: u-boot + $(OBJDUMP) -d $< > $@ + +ifdef CONFIG_TPL +SPL_PAYLOAD := tpl/u-boot-with-tpl.bin +else +SPL_PAYLOAD := u-boot.bin +endif + +OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ + --pad-to=$(CONFIG_SPL_PAD_TO) +u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE + $(call if_changed,pad_cat) + +OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \ + --pad-to=$(CONFIG_TPL_PAD_TO) +tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE + $(call if_changed,pad_cat) + +SPL: spl/u-boot-spl.bin FORCE + $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ + +u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE + $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ + +MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE) + +u-boot.ubl: u-boot-with-spl.bin FORCE + $(call if_changed,mkimage) + +MKIMAGEFLAGS_u-boot-spl.ais = -s -n $(if $(CONFIG_AIS_CONFIG_FILE), \ + $(srctree)/$(CONFIG_AIS_CONFIG_FILE:"%"=%),"/dev/null") \ + -T aisimage -e $(CONFIG_SPL_TEXT_BASE) +spl/u-boot-spl.ais: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_MAX_SIZE) +u-boot.ais: spl/u-boot-spl.ais u-boot.img FORCE + $(call if_changed,pad_cat) + +u-boot.sb: u-boot.bin spl/u-boot-spl.bin + $(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot.sb + +# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL. +# Both images are created using mkimage (crc etc), so that the ROM +# bootloader can check its integrity. Padding needs to be done to the +# SPL image (with mkimage header) and not the binary. Otherwise the resulting image +# which is loaded/copied by the ROM bootloader to SRAM doesn't fit. +# The resulting image containing both U-Boot images is called u-boot.spr +MKIMAGEFLAGS_u-boot-spl.img = -A $(ARCH) -T firmware -C none \ + -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER +spl/u-boot-spl.img: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS_u-boot.spr = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ + --gap-fill=0xff +u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE + $(call if_changed,pad_cat) + +ifneq ($(CONFIG_SUNXI),) +OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \ + --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff +u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE + $(call if_changed,pad_cat) +endif + +ifneq ($(CONFIG_TEGRA),) +OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE) +u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE + $(call if_changed,pad_cat) + +ifeq ($(CONFIG_OF_SEPARATE),y) +u-boot-dtb-tegra.bin: u-boot-nodtb-tegra.bin dts/dt.dtb FORCE + $(call if_changed,cat) +endif +endif + +u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE + $(call if_changed,cat) + +# PPC4xx needs the SPL at the end of the image, since the reset vector +# is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target +# and need to introduce a new build target with the full blown U-Boot +# at the start padded up to the start of the SPL image. And then concat +# the SPL image to the end. + +OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \ + --pad-to=$(CONFIG_UBOOT_PAD_TO) --gap-fill=0xff +u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE + $(call if_changed,pad_cat) + +# Create a new ELF from a raw binary file. This is useful for arm64 +# where static relocation needs to be performed on the raw binary, +# but certain simulators only accept an ELF file (but don't do the +# relocation). +# FIXME refactor dts/Makefile to share target/arch detection +u-boot.elf: u-boot.bin + @$(OBJCOPY) -B aarch64 -I binary -O elf64-littleaarch64 \ + $< u-boot-elf.o + @$(LD) u-boot-elf.o -o $@ \ + --defsym=_start=$(CONFIG_SYS_TEXT_BASE) \ + -Ttext=$(CONFIG_SYS_TEXT_BASE) + +# Rule to link u-boot +# May be overridden by arch/$(ARCH)/config.mk +quiet_cmd_u-boot__ ?= LD $@ + cmd_u-boot__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_u-boot) -o $@ \ + -T u-boot.lds $(u-boot-init) \ + --start-group $(u-boot-main) --end-group \ + $(PLATFORM_LIBS) -Map u-boot.map + +u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds + $(call if_changed,u-boot__) +ifeq ($(CONFIG_KALLSYMS),y) + smap=`$(call SYSTEM_MAP,u-boot) | \ + awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \ + $(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \ + -c $(srctree)/common/system_map.c -o common/system_map.o + $(call cmd,u-boot__) common/system_map.o +endif + +# The actual objects are generated when descending, +# make sure no implicit rule kicks in +$(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ; + +# Handle descending into subdirectories listed in $(vmlinux-dirs) +# Preset locale variables to speed up the build process. Limit locale +# tweaks to this spot to avoid wrong language settings when running +# make menuconfig etc. +# Error messages still appears in the original language + +PHONY += $(u-boot-dirs) +$(u-boot-dirs): prepare scripts + $(Q)$(MAKE) $(build)=$@ + +tools: prepare +# The "tools" are needed early +$(filter-out tools, $(u-boot-dirs)): tools +# The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC +# is "yes"), so compile examples after U-Boot is compiled. +examples: $(filter-out examples, $(u-boot-dirs)) + +define filechk_uboot.release + echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" +endef + +# Store (new) UBOOTRELEASE string in include/config/uboot.release +include/config/uboot.release: Makefile FORCE + $(call filechk,uboot.release) + + +# Things we need to do before we recursively start building the kernel +# or the modules are listed in "prepare". +# A multi level approach is used. prepareN is processed before prepareN-1. +# archprepare is used in arch Makefiles and when processed asm symlink, +# version.h and scripts_basic is processed / created. + +# Listed in dependency order +PHONY += prepare archprepare prepare0 prepare1 prepare2 prepare3 + +# prepare3 is used to check if we are building in a separate output directory, +# and if so do: +# 1) Check that make has not been executed in the kernel src $(srctree) +prepare3: include/config/uboot.release +ifneq ($(KBUILD_SRC),) + @$(kecho) ' Using $(srctree) as source for u-boot' + $(Q)if [ -f $(srctree)/include/config.mk ]; then \ + echo >&2 " $(srctree) is not clean, please run 'make mrproper'"; \ + echo >&2 " in the '$(srctree)' directory.";\ + /bin/false; \ + fi; +endif + +# prepare2 creates a makefile if using a separate output directory +prepare2: prepare3 outputmakefile + +prepare1: prepare2 $(version_h) $(timestamp_h) +ifeq ($(__HAVE_ARCH_GENERIC_BOARD),) +ifeq ($(CONFIG_SYS_GENERIC_BOARD),y) + @echo >&2 " Your architecture does not support generic board." + @echo >&2 " Please undefine CONFIG_SYS_GENERIC_BOARD in your board config file." + @/bin/false +endif +endif +ifeq ($(wildcard $(LDSCRIPT)),) + @echo >&2 " Could not find linker script." + @/bin/false +endif + +archprepare: prepare1 scripts_basic + +prepare0: archprepare FORCE + $(Q)$(MAKE) $(build)=. + +# All the preparing.. +prepare: prepare0 + +# Generate some files +# --------------------------------------------------------------------------- + +define filechk_version.h + (echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \ + echo \#define U_BOOT_VERSION \"U-Boot \" PLAIN_VERSION; \ + echo \#define CC_VERSION_STRING \"$$($(CC) --version | head -n 1)\"; \ + echo \#define LD_VERSION_STRING \"$$($(LD) --version | head -n 1)\"; ) +endef + +define filechk_timestamp.h + (LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \ + LC_ALL=C date +'#define U_BOOT_TIME "%T"') +endef + +$(version_h): include/config/uboot.release FORCE + $(call filechk,version.h) + +$(timestamp_h): $(srctree)/Makefile FORCE + $(call filechk,timestamp.h) + +# +# Auto-generate the autoconf.mk file (which is included by all makefiles) +# +# This target actually generates 2 files; autoconf.mk and autoconf.mk.dep. +# the dep file is only include in this top level makefile to determine when +# to regenerate the autoconf.mk file. + +quiet_cmd_autoconf_dep = GEN $@ + cmd_autoconf_dep = $(CC) -x c -DDO_DEPS_ONLY -M $(c_flags) \ + -MQ include/autoconf.mk $(srctree)/include/common.h > $@ || rm $@ + +include/autoconf.mk.dep: include/config.h include/common.h + $(call cmd,autoconf_dep) + +quiet_cmd_autoconf = GEN $@ + cmd_autoconf = \ + $(CPP) $(c_flags) -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \ + sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp > $@; \ + rm $@.tmp + +include/autoconf.mk: include/config.h + $(call cmd,autoconf) + +# --------------------------------------------------------------------------- + +PHONY += depend dep +depend dep: + @echo '*** Warning: make $@ is unnecessary now.' + +# --------------------------------------------------------------------------- +quiet_cmd_cpp_lds = LDS $@ +cmd_cpp_lds = $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ \ + -x assembler-with-cpp -P -o $@ $< + +u-boot.lds: $(LDSCRIPT) prepare FORCE + $(call if_changed,cpp_lds) + +PHONY += nand_spl +nand_spl: prepare + $(Q)$(MAKE) $(build)=nand_spl/board/$(BOARDDIR) all + @echo >&2 + @echo >&2 "==================== WARNING =====================" + @echo >&2 "nand_spl will not be included in v2014.07 release." + @echo >&2 "Please switch over to SPL." + @echo >&2 "Otherwise, this board will be removed." + @echo >&2 "==================================================" + @echo >&2 + +nand_spl/u-boot-spl-16k.bin: nand_spl + @: + +u-boot-nand.bin: nand_spl/u-boot-spl-16k.bin u-boot.bin FORCE + $(call if_changed,cat) + +spl/u-boot-spl.bin: spl/u-boot-spl + @: +spl/u-boot-spl: tools prepare + $(Q)$(MAKE) obj=spl -f $(srctree)/spl/Makefile all + +spl/sunxi-spl.bin: spl/u-boot-spl + @: + +tpl/u-boot-tpl.bin: tools prepare + $(Q)$(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y + +TAG_SUBDIRS := $(u-boot-dirs) include + +FIND := find +FINDFLAGS := -L + +tags ctags: + ctags -w -o ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ + -name '*.[chS]' -print` + +etags: + etags -a -o $(obj)etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ + -name '*.[chS]' -print` +cscope: + $(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) -name '*.[chS]' -print > \ + cscope.files + cscope -b -q -k + +SYSTEM_MAP = \ + $(NM) $1 | \ + grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + LC_ALL=C sort +System.map: u-boot + @$(call SYSTEM_MAP,$<) > $@ + +checkdtc: + @if test $(call dtc-version) -lt 0104; then \ + echo '*** Your dtc is too old, please upgrade to dtc 1.4 or newer'; \ + false; \ + fi + +######################################################################### + +# ARM relocations should all be R_ARM_RELATIVE (32-bit) or +# R_AARCH64_RELATIVE (64-bit). +checkarmreloc: u-boot + @RELOC="`$(CROSS_COMPILE)readelf -r -W $< | cut -d ' ' -f 4 | \ + grep R_A | sort -u`"; \ + if test "$$RELOC" != "R_ARM_RELATIVE" -a \ + "$$RELOC" != "R_AARCH64_RELATIVE"; then \ + echo "$< contains unexpected relocations: $$RELOC"; \ + false; \ + fi + +env: scripts_basic + $(Q)$(MAKE) $(build)=tools/$@ + +tools-only: scripts_basic $(version_h) $(timestamp_h) + $(Q)$(MAKE) $(build)=tools + +tools-all: export HOST_TOOLS_ALL=y +tools-all: env tools ; + +cross_tools: export CROSS_BUILD_TOOLS=y +cross_tools: tools ; + +.PHONY : CHANGELOG +CHANGELOG: + git log --no-merges U-Boot-1_1_5.. | \ + unexpand -a | sed -e 's/\s\s*$$//' > $@ + +include/license.h: tools/bin2header COPYING + cat COPYING | gzip -9 -c | ./tools/bin2header license_gzip > include/license.h +######################################################################### + +### +# Cleaning is done on three levels. +# make clean Delete most generated files +# Leave enough to build external modules +# make mrproper Delete the current configuration, and all generated files +# make distclean Remove editor backup files, patch leftover files and the like + +# Directories & files removed with 'make clean' +CLEAN_DIRS += $(MODVERDIR) +CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h \ + include/autoconf.mk* include/spl-autoconf.mk \ + include/tpl-autoconf.mk + +# Directories & files removed with 'make clobber' +CLOBBER_DIRS += $(patsubst %,spl/%, $(filter-out Makefile, \ + $(shell ls -1 spl 2>/dev/null))) \ + tpl +CLOBBER_FILES += u-boot* MLO* SPL System.map nand_spl/u-boot* + +# Directories & files removed with 'make mrproper' +MRPROPER_DIRS += include/config include/generated +MRPROPER_FILES += .config .config.old \ + tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \ + include/config.h include/config.mk + +# clean - Delete most, but leave enough to build external modules +# +clean: rm-dirs := $(CLEAN_DIRS) +clean: rm-files := $(CLEAN_FILES) + +clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $(srctree)/$f/Makefile),$f)) + +clean-dirs := $(addprefix _clean_, $(clean-dirs) doc/DocBook) + +PHONY += $(clean-dirs) clean archclean +$(clean-dirs): + $(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$@) + +# TODO: Do not use *.cfgtmp +clean: $(clean-dirs) + $(call cmd,rmdirs) + $(call cmd,rmfiles) + @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \ + \( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \ + -o -name '*.ko.*' -o -name '*.su' -o -name '*.cfgtmp' \ + -o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \ + -o -name '*.symtypes' -o -name 'modules.order' \ + -o -name modules.builtin -o -name '.tmp_*.o.*' \ + -o -name '*.gcno' \) -type f -print | xargs rm -f + @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \ + -path './nand_spl/*' -type l -print | xargs rm -f + +# clobber +# +clobber: rm-dirs := $(CLOBBER_DIRS) +clobber: rm-files := $(CLOBBER_FILES) + +PHONY += clobber + +clobber: clean + $(call cmd,rmdirs) + $(call cmd,rmfiles) + +# mrproper - Delete all generated files, including .config +# +mrproper: rm-dirs := $(wildcard $(MRPROPER_DIRS)) +mrproper: rm-files := $(wildcard $(MRPROPER_FILES)) +mrproper-dirs := $(addprefix _mrproper_,scripts) + +PHONY += $(mrproper-dirs) mrproper archmrproper +$(mrproper-dirs): + $(Q)$(MAKE) $(clean)=$(patsubst _mrproper_%,%,$@) + +mrproper: clobber $(mrproper-dirs) + $(call cmd,rmdirs) + $(call cmd,rmfiles) + @rm -f arch/*/include/asm/arch arch/*/include/asm/proc + +# distclean +# +PHONY += distclean + +distclean: mrproper + @find $(srctree) $(RCS_FIND_IGNORE) \ + \( -name '*.orig' -o -name '*.rej' -o -name '*~' \ + -o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \ + -o -name '.*.rej' -o -name '*.pyc' \ + -o -name '*%' -o -name '.*.cmd' -o -name 'core' \) \ + -type f -print | xargs rm -f + +backup: + F=`basename $(srctree)` ; cd .. ; \ + gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F + +help: + @echo 'Cleaning targets:' + @echo ' clean - Remove most generated files but keep the config and' + @echo ' necessities for testing u-boot' + @echo ' clobber - Remove most generated files but keep the config' + @echo ' mrproper - Remove all generated files + config + various backup files' + @echo ' distclean - mrproper + remove editor backup and patch files' + @echo '' +# uncomment after adding Kconfig feature +# @echo 'Configuration targets:' +# @$(MAKE) -f $(srctree)/scripts/kconfig/Makefile help +# @echo '' + @echo 'Other generic targets:' + @echo ' all - Build all necessary images depending on configuration' + @echo ' u-boot - Build the bare u-boot' + @echo ' dir/ - Build all files in dir and below' + @echo ' dir/file.[oisS] - Build specified target only' + @echo ' dir/file.lst - Build specified mixed source/assembly target only' + @echo ' (requires a recent binutils and recent build (System.map))' + @echo ' tags/TAGS - Generate tags file for editors' + @echo ' cscope - Generate cscope index' + @echo ' ubootrelease - Output the release version string' + @echo ' ubootversion - Output the version stored in Makefile' + @echo '' + @echo 'Static analysers' + @echo ' checkstack - Generate a list of stack hogs' + @echo '' + @echo 'Documentation targets:' + @$(MAKE) -f $(srctree)/doc/DocBook/Makefile dochelp + @echo '' + @echo ' make V=0|1 [targets] 0 => quiet build (default), 1 => verbose build' + @echo ' make V=2 [targets] 2 => give reason for rebuild of target' + @echo ' make O=dir [targets] Locate all output files in "dir", including .config' + @echo ' make C=1 [targets] Check all c source with $$CHECK (sparse by default)' + @echo ' make C=2 [targets] Force check of all c source with $$CHECK' + @echo ' make RECORDMCOUNT_WARN=1 [targets] Warn about ignored mcount sections' + @echo ' make W=n [targets] Enable extra gcc checks, n=1,2,3 where' + @echo ' 1: warnings which may be relevant and do not occur too often' + @echo ' 2: warnings which occur quite often but may still be relevant' + @echo ' 3: more obscure warnings, can most likely be ignored' + @echo ' Multiple levels can be combined with W=12 or W=123' + @echo '' + @echo 'Execute "make" or "make all" to build all targets marked with [*] ' + @echo 'For further info see the ./README file' + + +# Documentation targets +# --------------------------------------------------------------------------- +%docs: scripts_basic FORCE + $(Q)$(MAKE) $(build)=scripts build_docproc + $(Q)$(MAKE) $(build)=doc/DocBook $@ + +# Dummies... +PHONY += prepare scripts +prepare: ; +scripts: ; + +endif #ifeq ($(config-targets),1) +endif #ifeq ($(mixed-targets),1) + +PHONY += checkstack ubootrelease ubootversion + +checkstack: + $(OBJDUMP) -d u-boot $$(find . -name u-boot-spl) | \ + $(PERL) $(src)/scripts/checkstack.pl $(ARCH) + +ubootrelease: + @echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" + +ubootversion: + @echo $(UBOOTVERSION) + +# Single targets +# --------------------------------------------------------------------------- +# Single targets are compatible with: +# - build with mixed source and output +# - build with separate output dir 'make O=...' +# - external modules +# +# target-dir => where to store outputfile +# build-dir => directory in kernel source tree to use + +ifeq ($(KBUILD_EXTMOD),) + build-dir = $(patsubst %/,%,$(dir $@)) + target-dir = $(dir $@) +else + zap-slash=$(filter-out .,$(patsubst %/,%,$(dir $@))) + build-dir = $(KBUILD_EXTMOD)$(if $(zap-slash),/$(zap-slash)) + target-dir = $(if $(KBUILD_EXTMOD),$(dir $<),$(dir $@)) +endif + +%.s: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.i: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.o: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.lst: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.s: %.S prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.o: %.S prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.symtypes: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) + +# Modules +/: prepare scripts FORCE + $(cmd_crmodverdir) + $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \ + $(build)=$(build-dir) +%/: prepare scripts FORCE + $(cmd_crmodverdir) + $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \ + $(build)=$(build-dir) +%.ko: prepare scripts FORCE + $(cmd_crmodverdir) + $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \ + $(build)=$(build-dir) $(@:.ko=.o) + $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost + +# FIXME Should go into a make.lib or something +# =========================================================================== + +quiet_cmd_rmdirs = $(if $(wildcard $(rm-dirs)),CLEAN $(wildcard $(rm-dirs))) + cmd_rmdirs = rm -rf $(rm-dirs) + +quiet_cmd_rmfiles = $(if $(wildcard $(rm-files)),CLEAN $(wildcard $(rm-files))) + cmd_rmfiles = rm -f $(rm-files) + +# read all saved command lines + +targets := $(wildcard $(sort $(targets))) +cmd_files := $(wildcard .*.cmd $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd)) + +ifneq ($(cmd_files),) + $(cmd_files): ; # Do not try to update included dependency files + include $(cmd_files) +endif + +# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=dir +# Usage: +# $(Q)$(MAKE) $(clean)=dir +clean := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.clean obj + +endif # skip-makefile + +PHONY += FORCE +FORCE: + +# Declare the contents of the .PHONY variable as phony. We keep that +# information in a variable so we can use it in if_changed and friends. +.PHONY: $(PHONY) diff --git a/patch/u-boot-sunxi/board/sunxi/Makefile b/patch/u-boot-sunxi/board/sunxi/Makefile index e25b8eb..0e1de3b 100644 --- a/patch/u-boot-sunxi/board/sunxi/Makefile +++ b/patch/u-boot-sunxi/board/sunxi/Makefile @@ -6,95 +6,71 @@ # (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -# See file CREDITS for list of people who contributed to this -# project. +# SPDX-License-Identifier: GPL-2.0+ # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB := $(obj)lib$(BOARD).o - -COBJS-y := board.o -COBJS-$(CONFIG_A10_MID_1GB) += dram_sun4i_360_1024_iow16.o -COBJS-$(CONFIG_A10S_OLINUXINO_M) += dram_a10s_olinuxino_m.o -COBJS-$(CONFIG_A13_OLINUXINO) += dram_a13_olinuxino.o -COBJS-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o -COBJS-$(CONFIG_A13_MID) += dram_a13_mid.o -COBJS-$(CONFIG_A20_OLINUXINO_M) += dram_a20_olinuxino_m.o -COBJS-$(CONFIG_AUXTEK_T003) += dram_auxtek_t003.o +obj-y += board.o +obj-$(CONFIG_A10_MID_1GB) += dram_sun4i_360_1024_iow16.o +obj-$(CONFIG_A10_OLINUXINO_L) += dram_a10_olinuxino_l.o +obj-$(CONFIG_A10S_OLINUXINO_M) += dram_a10s_olinuxino_m.o +obj-$(CONFIG_A13_OLINUXINO) += dram_a13_olinuxino.o +obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o +obj-$(CONFIG_A13_MID) += dram_a13_mid.o +obj-$(CONFIG_A20_OLINUXINO_M) += dram_sun7i_384_1024_iow16.o +obj-$(CONFIG_AUXTEK_T003) += dram_auxtek_t003.o # This is not a typo, uses the same mem settings as the a10s-olinuxino-m -COBJS-$(CONFIG_AUXTEK_T004) += dram_a10s_olinuxino_m.o -COBJS-$(CONFIG_BA10_TV_BOX) += dram_sun4i_384_1024_iow8.o -COBJS-$(CONFIG_COBY_MID7042) += dram_sun4i_408_1024_iow16.o -COBJS-$(CONFIG_COBY_MID8042) += dram_sun4i_360_1024_iow16.o -COBJS-$(CONFIG_COBY_MID9742) += dram_sun4i_408_1024_iow16.o -COBJS-$(CONFIG_MARSBOARD_A10) += dram_sun4i_360_1024_iow16.o -COBJS-$(CONFIG_MARSBOARD_A20) += dram_sun4i_360_1024_iow16.o -COBJS-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o -COBJS-$(CONFIG_CUBIEBOARD_512) += dram_cubieboard_512.o -COBJS-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o -COBJS-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o -COBJS-$(CONFIG_DNS_M82) += dram_sun4i_360_1024_iow16.o -COBJS-$(CONFIG_EOMA68_A10) += dram_sun4i_360_1024_iow8.o -COBJS-$(CONFIG_EOMA68_A20) += dram_eoma68_a20.o -COBJS-$(CONFIG_EU3000) += dram_eu3000.o -COBJS-$(CONFIG_GOOSEBERRY_A721) += dram_gooseberry_a721.o -COBJS-$(CONFIG_H6) += dram_h6.o -COBJS-$(CONFIG_HACKBERRY) += dram_hackberry.o -COBJS-$(CONFIG_A7HD) += dram_sun4i_360_1024_iow8.o -COBJS-$(CONFIG_INET97F_II) += dram_sun4i_408_512.o -COBJS-$(CONFIG_MEFAFEIS_A08) += dram_megafeis_a08.o -COBJS-$(CONFIG_MELE_A1000) += dram_sun4i_360_512.o -COBJS-$(CONFIG_MELE_A1000G) += dram_sun4i_360_1024_iow8.o -COBJS-$(CONFIG_MELE_A3700) += dram_sun4i_360_1024_iow8.o -COBJS-$(CONFIG_MINI_X) += dram_sun4i_360_512.o -COBJS-$(CONFIG_MINI_X_1GB) += dram_sun4i_360_1024_iow16.o -COBJS-$(CONFIG_MINI_X_A10S) += dram_mini_x_a10s.o -COBJS-$(CONFIG_MK802) += dram_sun4i_360_512.o -COBJS-$(CONFIG_MK802_1GB) += dram_sun4i_360_1024_iow16.o -COBJS-$(CONFIG_MK802_A10S) += dram_mk802_a10s.o -COBJS-$(CONFIG_MK802II) += dram_sun4i_408_1024_iow8.o -COBJS-$(CONFIG_PCDUINO) += dram_sun4i_408_1024_iow8.o -COBJS-$(CONFIG_PCDUINO3) += dram_pcduino3.o -COBJS-$(CONFIG_PENGPOD700) += dram_sun4i_384_1024_iow8.o -COBJS-$(CONFIG_PENGPOD1000) += dram_sun4i_408_1024_iow16.o -COBJS-$(CONFIG_POV_PROTAB2) += dram_pov_protab2.o -COBJS-$(CONFIG_POV_PROTAB2_XXL) += dram_pov_protab2_xxl.o -COBJS-$(CONFIG_R7DONGLE) += dram_r7dongle.o -COBJS-$(CONFIG_SANEI_N90) += dram_sanei_n90.o -COBJS-$(CONFIG_UHOST_U1A) += dram_sun4i_360_1024_iow8.o -COBJS-$(CONFIG_WOBO_I5) += dram_wobo_i5.o -COBJS-$(CONFIG_XZPAD700) += dram_xzpad700.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################## +obj-$(CONFIG_AUXTEK_T004) += dram_a10s_olinuxino_m.o +obj-$(CONFIG_BA10_TV_BOX) += dram_sun4i_384_1024_iow8.o +obj-$(CONFIG_COBY_MID7042) += dram_sun4i_408_1024_iow16.o +obj-$(CONFIG_COBY_MID8042) += dram_sun4i_360_1024_iow16.o +obj-$(CONFIG_COBY_MID9742) += dram_sun4i_408_1024_iow16.o +obj-$(CONFIG_MARSBOARD_A10) += dram_sun4i_360_1024_iow16.o +obj-$(CONFIG_MARSBOARD_A20) += dram_sun4i_360_1024_iow16.o +obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o +obj-$(CONFIG_CUBIEBOARD_512) += dram_cubieboard_512.o +obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o +obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o +obj-$(CONFIG_DNS_M82) += dram_sun4i_360_1024_iow16.o +obj-$(CONFIG_EOMA68_A10) += dram_sun4i_360_1024_iow8.o +obj-$(CONFIG_EOMA68_A20) += dram_sun7i_384_1024_iow16.o +obj-$(CONFIG_EU3000) += dram_eu3000.o +obj-$(CONFIG_GOOSEBERRY_A721) += dram_gooseberry_a721.o +obj-$(CONFIG_H6) += dram_h6.o +obj-$(CONFIG_HACKBERRY) += dram_hackberry.o +obj-$(CONFIG_HCORE_HC860) += dram_sun4i_384_1024_iow16.o +obj-$(CONFIG_A7HD) += dram_sun4i_360_1024_iow8.o +obj-$(CONFIG_INTERRA3) += dram_mk802ii_a20.o +obj-$(CONFIG_INET_86VZ) += dram_a10s_olinuxino_m.o +obj-$(CONFIG_INET97F_II) += dram_sun4i_408_512.o +obj-$(CONFIG_INET_K70HC) += dram_inet_k70hc.o +obj-$(CONFIG_ITEADA10) += dram_cubieboard.o +obj-$(CONFIG_ITEADA20) += dram_cubieboard2.o +obj-$(CONFIG_JESURUN_Q5) += dram_sun4i_312_1024_iow8.o +obj-$(CONFIG_K1001L1C) += dram_a20_olinuxino_m.o +obj-$(CONFIG_MEFAFEIS_A08) += dram_megafeis_a08.o +obj-$(CONFIG_MELE_A1000) += dram_sun4i_360_512.o +obj-$(CONFIG_MELE_A1000G) += dram_sun4i_360_1024_iow8.o +obj-$(CONFIG_MELE_A3700) += dram_sun4i_360_1024_iow8.o +obj-$(CONFIG_MINI_X) += dram_sun4i_360_512.o +obj-$(CONFIG_MINI_X_1GB) += dram_sun4i_360_1024_iow16.o +obj-$(CONFIG_MINI_X_A10S) += dram_mini_x_a10s.o +obj-$(CONFIG_MK802) += dram_sun4i_360_512.o +obj-$(CONFIG_MK802_1GB) += dram_sun4i_360_1024_iow16.o +obj-$(CONFIG_MK802_A10S) += dram_mk802_a10s.o +obj-$(CONFIG_MK802II) += dram_sun4i_408_1024_iow8.o +obj-$(CONFIG_MK802II_A20) += dram_mk802ii_a20.o +obj-$(CONFIG_MK808C_A20) += dram_sun7i_384_1024_iow16.o +obj-$(CONFIG_PCDUINO) += dram_sun4i_408_1024_iow8.o +obj-$(CONFIG_PCDUINO3) += dram_pcduino3.o +obj-$(CONFIG_PCDUINO3_LVDS) += dram_pcduino3.o +obj-$(CONFIG_PCDUINO3_NANO) += dram_pcduino3.o +obj-$(CONFIG_PENGPOD700) += dram_sun4i_384_1024_iow8.o +obj-$(CONFIG_PENGPOD1000) += dram_sun4i_408_1024_iow16.o +obj-$(CONFIG_POV_PROTAB2) += dram_pov_protab2.o +obj-$(CONFIG_POV_PROTAB2_XXL) += dram_pov_protab2_xxl.o +obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o +obj-$(CONFIG_SANEI_N90) += dram_sanei_n90.o +obj-$(CONFIG_UHOST_U1A) += dram_sun4i_360_1024_iow8.o +obj-$(CONFIG_WEXLER_TAB_7200) += dram_wexler_tab_7200.o +obj-$(CONFIG_WOBO_I5) += dram_wobo_i5.o +obj-$(CONFIG_XZPAD700) += dram_xzpad700.o +obj-$(CONFIG_ZATAB) += dram_zatab.o diff --git a/patch/u-boot-sunxi/board/sunxi/dram_pcduino3.c b/patch/u-boot-sunxi/board/sunxi/dram_pcduino3.c index 69e61cf..2066172 100644 --- a/patch/u-boot-sunxi/board/sunxi/dram_pcduino3.c +++ b/patch/u-boot-sunxi/board/sunxi/dram_pcduino3.c @@ -1,10 +1,10 @@ /* this file is generated, don't edit it yourself */ -#include +#include "common.h" #include static struct dram_para dram_para = { - .clock = 480, + .clock = 408, .type = 3, .rank_num = 1, .density = 4096, @@ -17,15 +17,15 @@ static struct dram_para dram_para = { .tpr0 = 0x42d899b7, .tpr1 = 0xa090, .tpr2 = 0x22a00, - .tpr3 = 0x0, - .tpr4 = 0x1, - .tpr5 = 0x0, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, .emr1 = 0x4, .emr2 = 0x10, - .emr3 = 0x0, + .emr3 = 0, }; -int sunxi_dram_init(void) +unsigned long sunxi_dram_init(void) { return dramc_init(&dram_para); } diff --git a/patch/u-boot-sunxi/boards.cfg b/patch/u-boot-sunxi/boards.cfg index 456072b..d6c3d77 100644 --- a/patch/u-boot-sunxi/boards.cfg +++ b/patch/u-boot-sunxi/boards.cfg @@ -38,11 +38,15 @@ # It can be used from a shell: # tools/reformat.py -i -d '-' -s 8 boards0.cfg && mv boards0.cfg boards.cfg # It can directly be invoked from vim: -# :%tools/reformat.py -i -d '-' -s 8 +# :%!tools/reformat.py -i -d '-' -s 8 # # Status, Arch, CPU:SPLCPU, SoC, Vendor, Board name, Target, Options, Maintainers ########################################################################################################### +Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng +Active arc arc700 - synopsys - axs101 - Alexey Brodkin +Active arc arc700 - synopsys arcangel4 - Alexey Brodkin +Active arc arc700 - synopsys arcangel4-be - Alexey Brodkin Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij Active arm arm1136 mx31 - - imx31_phycore - - Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk @@ -59,17 +63,15 @@ Active arm arm720t - armltd integrator Active arm arm920t - armltd integrator integratorap_cm920t integratorap:CM920T Linus Walleij Active arm arm920t - armltd integrator integratorcp_cm920t integratorcp:CM920T Linus Walleij Active arm arm920t a320 faraday - a320evb - Po-Yu Chuang -Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek at91rm9200ek Andreas Bießmann +Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek - Andreas Bießmann Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek_ram at91rm9200ek:RAMBOOT Andreas Bießmann -Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2 eb_cpux9k2 Jens Scharsig +Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2 - Jens Scharsig Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig -Active arm arm920t at91 eukrea cpuat91 cpuat91 cpuat91 Eric Benard +Active arm arm920t at91 eukrea cpuat91 cpuat91 - Eric Benard Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard -Active arm arm920t imx - - mx1ads - - Active arm arm920t imx - - scb9328 - Torsten Koschorrek Active arm arm920t ks8695 - - cm4008 - Greg Ungerer Active arm arm920t ks8695 - - cm41xx - - -Active arm arm920t s3c24x0 friendlyarm mini2440 mini2440 - Gabriel Huau Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Müller Active arm arm920t s3c24x0 samsung - smdk2410 - David Müller Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij @@ -119,6 +121,7 @@ Active arm arm926ejs at91 calao tny_a9260 Active arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre +Active arm arm926ejs at91 calao usb_a9263 usb_a9263_dataflash usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH Mateusz Kulikowski Active arm arm926ejs at91 egnite ethernut5 ethernut5 ethernut5:AT91SAM9XE egnite GmbH Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer Active arm arm926ejs at91 emk top9000 top9000su_xe top9000:SU9000 Reinhard Meyer @@ -137,9 +140,12 @@ Active arm arm926ejs at91 eukrea cpu9260 Active arm arm926ejs at91 ronetix pm9261 pm9261 pm9261:AT91SAM9261 Ilko Iliev Active arm arm926ejs at91 ronetix pm9263 pm9263 pm9263:AT91SAM9263 Ilko Iliev Active arm arm926ejs at91 ronetix pm9g45 pm9g45 pm9g45:AT91SAM9G45 Ilko Iliev +Active arm arm926ejs at91 siemens corvus corvus corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH Heiko Schocher +Active arm arm926ejs at91 siemens taurus axm taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM Heiko Schocher +Active arm arm926ejs at91 siemens taurus taurus taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS Heiko Schocher Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig -Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx cam_enc_4xx Heiko Schocher +Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx - Heiko Schocher Active arm arm926ejs davinci Barix ipam390 ipam390 - Heiko Schocher Active arm arm926ejs davinci davinci da8xxevm da830evm - Nick Thompson Active arm arm926ejs davinci davinci da8xxevm da850_am18xxevm da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 Sudhakar Rajashekhara @@ -166,9 +172,11 @@ Active arm arm926ejs kirkwood d-link - Active arm arm926ejs kirkwood iomega - iconnect - Luka Perkov Active arm arm926ejs kirkwood karo tk71 tk71 - - Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp +Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_128m16 km_kirkwood:KM_KIRKWOOD_128M16 Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp +Active arm arm926ejs kirkwood keymile km_arm kmsugp1 km_kirkwood:KM_SUGP1 Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm mgcoge3un km_kirkwood:KM_MGCOGE3UN Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm portl2 km_kirkwood:KM_PORTL2 Valentin Longchamp @@ -196,25 +204,26 @@ Active arm arm926ejs mb86r0x syteco jadecpu Active arm arm926ejs mx25 freescale mx25pdk mx25pdk mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg Fabio Estevam Active arm arm926ejs mx25 karo tx25 tx25 - John Rigby Active arm arm926ejs mx25 syteco zmx25 zmx25 - Matthias Weisser +Active arm arm926ejs mx27 armadeus apf27 apf27 - Philippe Reynes :Eric Jarrige Active arm arm926ejs mx27 logicpd imx27lite imx27lite - Wolfgang Denk Active arm arm926ejs mx27 logicpd imx27lite magnesium - Heiko Schocher -Active arm arm926ejs mxs bluegiga apx4devkit apx4devkit apx4devkit Lauri Hintsala -Active arm arm926ejs mxs denx m28evk m28evk m28evk Marek Vasut -Active arm arm926ejs mxs freescale mx23evk mx23evk mx23evk Otavio Salvador +Active arm arm926ejs mxs bluegiga apx4devkit apx4devkit - Lauri Hintsala +Active arm arm926ejs mxs creative xfi3 xfi3 - Marek Vasut +Active arm arm926ejs mxs denx m28evk m28evk - Marek Vasut +Active arm arm926ejs mxs freescale mx23evk mx23evk - Otavio Salvador Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam -Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino mx23_olinuxino Marek Vasut +Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino - Marek Vasut +Active arm arm926ejs mxs ppcag bg0900 bg0900 - Marek Vasut +Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team :Alessandro Rubini Active arm arm926ejs nomadik st nhk8815 nhk8815_onenand nhk8815:BOOT_ONENAND Nomadik Linux Team :Alessandro Rubini Active arm arm926ejs omap ti - omap5912osk - Rishi Bhattacharya -Active arm arm926ejs omap ti omap730p2 omap730p2 omap730p2:CS3_BOOT Dave Peverley -Active arm arm926ejs omap ti omap730p2 omap730p2_cs0boot omap730p2:CS0_BOOT Dave Peverley -Active arm arm926ejs omap ti omap730p2 omap730p2_cs3boot omap730p2:CS3_BOOT Dave Peverley Active arm arm926ejs orion5x LaCie - edminiv2 - Albert ARIBAUD Active arm arm926ejs pantheon Marvell - dkb - Lei Wen -Active arm arm926ejs spear spear - x600 x600 Stefan Roese +Active arm arm926ejs spear spear - x600 - Stefan Roese Active arm arm926ejs spear spear spear300 spear300 spear3xx_evb:spear300 Vipin Kumar Active arm arm926ejs spear spear spear300 spear300_nand spear3xx_evb:spear300,nand - Active arm arm926ejs spear spear spear300 spear300_usbtty spear3xx_evb:spear300,usbtty - @@ -243,35 +252,47 @@ Active arm arm946es - armltd integrator Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - - Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel -Active arm armv7 am33xx isee igep0033 igep0033 - Enric Balletbo i Serra -Active arm armv7 am33xx phytec pcm051 pcm051 pcm051 Lars Poeschel +Active arm armv7 am33xx BuR kwb kwb kwb:SERIAL1,CONS_INDEX=1 Hannes Petermaier +Active arm armv7 am33xx BuR tseries tseries_mmc tseries:SERIAL1,CONS_INDEX=1,EMMC_BOOT Hannes Petermaier +Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier +Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier +Active arm armv7 am33xx compulab cm_t335 cm_t335 - Igor Grinberg +Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra +Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel +Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier Active arm armv7 am33xx siemens rut rut - Roger Meier +Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini Active arm armv7 am33xx ti am335x am335x_evm_norboot am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT Tom Rini Active arm armv7 am33xx ti am335x am335x_evm_spiboot am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT Tom Rini -Active arm armv7 am33xx ti am335x am335x_evm_uart1 am335x_evm:SERIAL2,CONS_INDEX=1,NAND Tom Rini -Active arm armv7 am33xx ti am335x am335x_evm_uart2 am335x_evm:SERIAL3,CONS_INDEX=1,NAND Tom Rini -Active arm armv7 am33xx ti am335x am335x_evm_uart3 am335x_evm:SERIAL4,CONS_INDEX=1,NAND Tom Rini -Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=1,NAND Tom Rini -Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=1,NAND Tom Rini +Active arm armv7 am33xx ti am335x am335x_evm_uart1 am335x_evm:SERIAL2,CONS_INDEX=2,NAND Tom Rini +Active arm armv7 am33xx ti am335x am335x_evm_uart2 am335x_evm:SERIAL3,CONS_INDEX=3,NAND Tom Rini +Active arm armv7 am33xx ti am335x am335x_evm_uart3 am335x_evm:SERIAL4,CONS_INDEX=4,NAND Tom Rini +Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=5,NAND Tom Rini +Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND Tom Rini Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini -Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 - -Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter +Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla +Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter Active arm armv7 am33xx ti ti816x ti816x_evm - - +Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_mmc sama5d3_xplained:SAMA5D3,SYS_USE_MMC Bo Shen +Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_nandflash sama5d3_xplained:SAMA5D3,SYS_USE_NANDFLASH Bo Shen Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen Active arm armv7 at91 atmel sama5d3xek sama5d3xek_spiflash sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH Bo Shen +Active arm armv7 bcm281xx broadcom bcm28155_ap bcm28155_ap bcm28155_ap Tim Kryger Active arm armv7 exynos samsung arndale arndale - Inderpal Singh Active arm armv7 exynos samsung origen origen - Chander Kashyap Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde +Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap Active arm armv7 exynos samsung trats trats - Lukasz Majewski -Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Minkyu Kang +Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek +Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak Active arm armv7 highbank - highbank highbank - Rob Herring Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - @@ -283,9 +304,11 @@ Active arm armv7 mx5 freescale mx53smd Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic +Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam +Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese Active arm armv7 mx6 boundary nitrogen6x mx6qsabrelite nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE Eric Nelson Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Eric Nelson Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 Eric Nelson @@ -299,25 +322,27 @@ Active arm armv7 mx6 freescale mx6qsabreauto Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam -Active arm armv7 mx6 freescale titanium titanium titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg Stefan Roese +Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat Active arm armv7 omap3 comelit dig297 dig297 - Luca Ceresoli Active arm armv7 omap3 compulab cm_t35 cm_t35 - Igor Grinberg Active arm armv7 omap3 corscience tricorder tricorder - Thomas Weber +Active arm armv7 omap3 corscience tricorder tricorder_flash tricorder:FLASHCARD Thomas Weber Active arm armv7 omap3 htkw mcx mcx - Ilya Yanok -Active arm armv7 omap3 isee igep00x0 igep0020 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND Enric Balletbo i Serra -Active arm armv7 omap3 isee igep00x0 igep0020_nand igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND - -Active arm armv7 omap3 isee igep00x0 igep0030 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND Enric Balletbo i Serra -Active arm armv7 omap3 isee igep00x0 igep0030_nand igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND - -Active arm armv7 omap3 isee igep00x0 igep0032 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND Enric Balletbo i Serra +Active arm armv7 omap3 isee igep00x0 igep0020 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND Enric Balletbo i Serra +Active arm armv7 omap3 isee igep00x0 igep0020_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND - +Active arm armv7 omap3 isee igep00x0 igep0030 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND Enric Balletbo i Serra +Active arm armv7 omap3 isee igep00x0 igep0030_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND - +Active arm armv7 omap3 isee igep00x0 igep0032 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND Enric Balletbo i Serra Active arm armv7 omap3 logicpd am3517evm am3517_evm - Vaibhav Hiremath Active arm armv7 omap3 logicpd omap3som omap3_logic - Peter Barada Active arm armv7 omap3 logicpd zoom1 omap3_zoom1 - Nishanth Menon -Active arm armv7 omap3 logicpd zoom2 omap3_zoom2 - Tom Rix Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohár +Active arm armv7 omap3 technexion tao3530 omap3_ha tao3530:SYS_BOARD_OMAP3_HA Stefan Roese +Active arm armv7 omap3 technexion tao3530 tao3530 - Tapani Utriainen Active arm armv7 omap3 technexion twister twister - Stefano Babic Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic Active arm armv7 omap3 ti am3517crane am3517_crane - Nagendra T S @@ -329,14 +354,20 @@ Active arm armv7 omap3 ti sdp3430 Active arm armv7 omap3 timll devkit8000 devkit8000 - Thomas Weber Active arm armv7 omap4 ti panda omap4_panda - Sricharan R Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R -Active arm armv7 omap5 ti dra7xx dra7xx_evm - Lokesh Vutla +Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla +Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla Active arm armv7 omap5 ti omap5_uevm omap5_uevm - - Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu :Tetsuyuki Kobayashi -Active arm armv7 s5pc1xx samsung goni s5p_goni - Minkyu Kang +Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu +Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu +Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu +Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu +Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - Active arm armv7 sunxi - sunxi A10_MID_1GB sun4i:A10_MID_1GB,SPL - +Active arm armv7 sunxi - sunxi A10-OLinuXino-Lime sun4i:A10_OLINUXINO_L,STATUSLED=226,SPL,SUNXI_EMAC - Active arm armv7 sunxi - sunxi A10s-OLinuXino-M sun5i:A10S_OLINUXINO_M,STATUSLED=131,AXP152_POWER,CONS_INDEX=1,SPL,SUNXI_EMAC - Active arm armv7 sunxi - sunxi A10s-OLinuXino-M_FEL sun5i:A10S_OLINUXINO_M,STATUSLED=131,AXP152_POWER,CONS_INDEX=1,SPL_FEL,SUNXI_EMAC - Active arm armv7 sunxi - sunxi A13-OLinuXino sun5i:A13_OLINUXINO,SPL,STATUSLED=201,CONS_INDEX=2 - @@ -353,11 +384,14 @@ Active arm armv7 sunxi - sunxi Active arm armv7 sunxi - sunxi Coby_MID7042 sun4i:COBY_MID7042,SPL - Active arm armv7 sunxi - sunxi Coby_MID8042 sun4i:COBY_MID8042,SPL - Active arm armv7 sunxi - sunxi Coby_MID9742 sun4i:COBY_MID9742,SPL - +Active arm armv7 sunxi - sunxi Iteaduino_Plus_A10 sun4i:ITEADA10,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 - +Active arm armv7 sunxi - sunxi Iteaduino_Plus_A20 sun7i:ITEADA20,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 - +Active arm armv7 sunxi - sunxi Colombus sun6i:COLOMBUS,AXP221_POWER,ENABLE_DLDO1_POWER - Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 - -Active arm armv7 sunxi - sunxi Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 - -Active arm armv7 sunxi - sunxi Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 - -Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_EMAC,STATUSLED=245,STATUSLED1=244,STATUSLED2=235,STATUSLED3=231 - -Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_EMAC,STATUSLED=245,STATUSLED1=244,STATUSLED2=235,STATUSLED3=231 - +Active arm armv7 sunxi - sunxi Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS - +Active arm armv7 sunxi - sunxi Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS - +Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII,STATUSLED=245,STATUSLED1=244,STATUSLED2=235,STATUSLED3=231,FAST_MBUS - +Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII,STATUSLED=245,STATUSLED1=244,STATUSLED2=235,STATUSLED3=231,FAST_MBUS - Active arm armv7 sunxi - sunxi Cubieboard_512 sun4i:CUBIEBOARD_512,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 - Active arm armv7 sunxi - sunxi Cubieboard_FEL sun4i:CUBIEBOARD,SPL_FEL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 - Active arm armv7 sunxi - sunxi DNS_M82 sun4i:DNS_M82,SPL - @@ -369,8 +403,15 @@ Active arm armv7 sunxi - sunxi Active arm armv7 sunxi - sunxi Gooseberry_A721 sun4i:GOOSEBERRY_A721,SPL - Active arm armv7 sunxi - sunxi H6 sun4i:H6,SPL - Active arm armv7 sunxi - sunxi Hackberry sun4i:HACKBERRY,SPL - +Active arm armv7 sunxi - sunxi HCore_HC860 sun4i:HCORE_HC860,SPL - Active arm armv7 sunxi - sunxi Hyundai_A7HD sun4i:A7HD,SPL - +Active arm armv7 sunxi - sunxi Interra-3 sun7i:INTERRA3,SPL,SUNXI_GMAC,FAST_MBUS,MMC_SUNXI_SLOT=2 - +Active arm armv7 sunxi - sunxi INet_86VZ sun5i:INET_86VZ,SPL - +Active arm armv7 sunxi - sunxi INet_86VZ_FEL sun5i:INET_86VZ,SPL_FEL,UART0_PORT_F - Active arm armv7 sunxi - sunxi INet97F-II sun4i:INET97F_II,SPL - +Active arm armv7 sunxi - sunxi INet_K70HC sun7i:INET_K70HC,SPL - +Active arm armv7 sunxi - sunxi Jesurun-Q5 sun4i:JESURUN_Q5,SPL,SUNXI_EMAC,STATUSLED=244 - +Active arm armv7 sunxi - sunxi K1001L1C sun7i:K1001L1C,SPL - Active arm armv7 sunxi - sunxi Marsboard_A10 sun4i:MARSBOARD_A10,SPL,SUNXI_EMAC,NO_AXP - Active arm armv7 sunxi - sunxi Marsboard_A20 sun7i:MARSBOARD_A20,SPL,SUNXI_EMAC,NO_AXP - Active arm armv7 sunxi - sunxi Marsboard_A20_debug sun7i:MARSBOARD_A20,SPL,SUNXI_EMAC,NO_AXP,SYS_SECONDARY_ON - @@ -385,9 +426,14 @@ Active arm armv7 sunxi - sunxi Active arm armv7 sunxi - sunxi mk802 sun4i:MK802,SPL,NO_AXP - Active arm armv7 sunxi - sunxi mk802-1gb sun4i:MK802_1GB,SPL,NO_AXP - Active arm armv7 sunxi - sunxi mk802_a10s sun5i:MK802_A10S,SPL,AXP152_POWER,STATUSLED=34 - +Active arm armv7 sunxi - sunxi mk802ii_A20 sun7i:MK802II_A20,SPL - Active arm armv7 sunxi - sunxi mk802ii sun4i:MK802II,SPL - +Active arm armv7 sunxi - sunxi mk808c_A20 sun7i:MK808C_A20,SPL - Active arm armv7 sunxi - sunxi pcDuino sun4i:PCDUINO,SPL,SUNXI_EMAC - -Active arm armv7 sunxi - sunxi pcDuino3 sun7i:PCDUINO3,SPL,SUNXI_EMAC +Active arm armv7 sunxi - sunxi pcDuino3 sun7i:PCDUINO3,SPL - +Active arm armv7 sunxi - sunxi pcDuino3_LVDS sun7i:PCDUINO3_LVDS,SPL - +Active arm armv7 sunxi - sunxi pcDuino3B_LVDS sun7i:PCDUINO3_LVDS,SPL - +Active arm armv7 sunxi - sunxi pcDuino3_NANO sun7i:PCDUINO3_NANO,SPL - Active arm armv7 sunxi - sunxi pengpod1000 sun4i:PENGPOD1000,SPL - Active arm armv7 sunxi - sunxi pengpod700 sun4i:PENGPOD700,SPL - Active arm armv7 sunxi - sunxi PoV_ProTab2_IPS9 sun4i:POV_PROTAB2,SPL - @@ -401,17 +447,24 @@ Active arm armv7 sunxi - sunxi Active arm armv7 sunxi - sunxi sun5i_sdcon sun5i:UART0_PORT_F,SUNXI_EMAC - Active arm armv7 sunxi - sunxi sun5i_uart1 sun5i:CONS_INDEX=2,SUNXI_EMAC - Active arm armv7 sunxi - sunxi uhost_u1a sun4i:UHOST_U1A,SPL,STATUSLED=34 - +Active arm armv7 sunxi - sunxi Wexler_TAB_7200 sun7i:WEXLER_TAB_7200,SPL - Active arm armv7 sunxi - sunxi wobo-i5 sun5i:WOBO_I5,SPL,STATUSLED=34 - Active arm armv7 sunxi - sunxi xzpad700 sun5i:XZPAD700,SPL - +Active arm armv7 sunxi - sunxi zatab sun4i:ZATAB,SPL - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang -Active arm armv7 zynq xilinx zynq zynq - Michal Simek -Active arm armv7 zynq xilinx zynq zynq_dcc zynq:ZYNQ_DCC Michal Simek +Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_zc770_xm012 zynq_zc770:ZC770_XM012 Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren -Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding -Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding -Active arm armv7:arm720t tegra20 avionic-design tec tec - Thierry Reding +Active arm armv7:arm720t tegra124 nvidia venice2 venice2 - Tom Warren +Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel +Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel +Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren @@ -419,18 +472,9 @@ Active arm armv7:arm720t tegra20 nvidia seaboard Active arm armv7:arm720t tegra20 nvidia ventana ventana - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra20 nvidia whistler whistler - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra20 toradex colibri_t20_iris colibri_t20_iris - Lucas Stach +Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren -Active arm ixp - - - actux2 - Michael Schwingen -Active arm ixp - - - actux3 - Michael Schwingen -Active arm ixp - - - actux4 - Michael Schwingen -Active arm ixp - - - dvlhost - Michael Schwingen -Active arm ixp - - actux1 actux1_4_16 actux1:FLASH2X2 Michael Schwingen -Active arm ixp - - actux1 actux1_4_32 actux1:FLASH2X2,RAM_32MB Michael Schwingen -Active arm ixp - - actux1 actux1_8_16 actux1:FLASH1X8 Michael Schwingen -Active arm ixp - - actux1 actux1_8_32 actux1:FLASH1X8,RAM_32MB Michael Schwingen -Active arm ixp - prodrive pdnb3 pdnb3 - Stefan Roese -Active arm ixp - prodrive pdnb3 scpu pdnb3:SCPU Stefan Roese Active arm pxa - - - balloon3 - Marek Vasut Active arm pxa - - - h2200 - Lukasz Dalek Active arm pxa - - - palmld - Marek Vasut @@ -458,45 +502,36 @@ Active avr32 at32ap at32ap700x in-circuit - Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson Active avr32 at32ap at32ap700x miromico - hammerhead - Julien May :Alex Raimondi Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald -Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang :Blackfin Team +Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang +Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang :Chong Huang -Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf527-sdp - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf533-stamp - Sonic Zhang :Blackfin Team +Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang +Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang +Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang +Active blackfin blackfin - - - bf527-sdp - Sonic Zhang +Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang +Active blackfin blackfin - - - bf533-stamp - Sonic Zhang Active blackfin blackfin - - - bf537-minotaur - Martin Strubel -Active blackfin blackfin - - - bf537-pnav - Sonic Zhang :Blackfin Team +Active blackfin blackfin - - - bf537-pnav - Sonic Zhang Active blackfin blackfin - - - bf537-srv1 - Martin Strubel -Active blackfin blackfin - - - bf537-stamp - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang :Blackfin Team +Active blackfin blackfin - - - bf537-stamp - Sonic Zhang +Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang +Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin :Valentin Yakovenkov -Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang :Blackfin Team -Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang :Blackfin Team +Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang +Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang Active blackfin blackfin - - - blackstamp - Wojtek Skulski :Wojtek Skulski :Benjamin Matthews Active blackfin blackfin - - - blackvme - Wojtek Skulski :Wojtek Skulski :Benjamin Matthews Active blackfin blackfin - - - br4 - Dimitar Penev -Active blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards -Active blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards -Active blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards -Active blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards -Active blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards -Active blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule Active blackfin blackfin - - - ip04 - Brent Kandetzki Active blackfin blackfin - - - pr1 - Dimitar Penev -Active blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards -Active blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards -Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang :Blackfin Team +Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew Active m68k mcf523x - freescale m5235evb M5235EVB_Flash32 M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 TsiChung Liew -Active m68k mcf52x2 - - - idmr - - Active m68k mcf52x2 - - cobra5272 cobra5272 - - Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282 eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 Jens Scharsig Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282_internal eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 Jens Scharsig @@ -505,7 +540,6 @@ Active m68k mcf52x2 - freescale m5208evbe Active m68k mcf52x2 - freescale m5249evb M5249EVB - - Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser -Active m68k mcf52x2 - freescale m5271evb M5271EVB - - Active m68k mcf52x2 - freescale m5272c3 M5272C3 - - Active m68k mcf52x2 - freescale m5275evb M5275EVB - - Active m68k mcf52x2 - freescale m5282evb M5282EVB - - @@ -543,10 +577,10 @@ Active m68k mcf547x_8x - freescale m548xevb Active m68k mcf547x_8x - freescale m548xevb M5485GFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew Active m68k mcf547x_8x - freescale m548xevb M5485HFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO TsiChung Liew Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek -Active mips mips32 - - qemu-malta qemu_malta qemu-malta:MIPS32,SYS_BIG_ENDIAN - -Active mips mips32 - - qemu-malta qemu_maltael qemu-malta:MIPS32,SYS_LITTLE_ENDIAN - Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN - +Active mips mips32 - imgtec malta malta malta:SYS_BIG_ENDIAN Paul Burton +Active mips mips32 - imgtec malta maltael malta:SYS_LITTLE_ENDIAN Paul Burton Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM - Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND - Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE - @@ -622,7 +656,7 @@ Active powerpc mpc5xxx - - icecube Active powerpc mpc5xxx - - icecube lite5200b IceCube:MPC5200_DDR,LITE5200B - Active powerpc mpc5xxx - - icecube lite5200b_LOWBOOT IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000 - Active powerpc mpc5xxx - - icecube lite5200b_PM IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM - -Active powerpc mpc5xxx - - mcc200 mcc200 mcc200 - +Active powerpc mpc5xxx - - mcc200 mcc200 - - Active powerpc mpc5xxx - - mcc200 mcc200_COM12 mcc200:CONSOLE_COM12 - Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000 - Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot_SDRAM mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM - @@ -665,19 +699,17 @@ Active powerpc mpc5xxx - intercontrol digsy_mtc Active powerpc mpc5xxx - manroland - hmi1001 - - Active powerpc mpc5xxx - manroland - mucmc52 - Heiko Schocher Active powerpc mpc5xxx - manroland - uc101 - Heiko Schocher -Active powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz -Active powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz -Active powerpc mpc5xxx - phytec pcm030 pcm030 pcm030 Jon Smirl +Active powerpc mpc5xxx - phytec pcm030 pcm030 - Jon Smirl Active powerpc mpc5xxx - phytec pcm030 pcm030_LOWBOOT pcm030:SYS_TEXT_BASE=0xFF000000 Jon Smirl Active powerpc mpc5xxx - tqc tqm5200 aev - - Active powerpc mpc5xxx - tqc tqm5200 cam5200 TQM5200:CAM5200,TQM5200S,TQM5200_B - Active powerpc mpc5xxx - tqc tqm5200 cam5200_niosflash TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH - -Active powerpc mpc5xxx - tqc tqm5200 charon charon Heiko Schocher +Active powerpc mpc5xxx - tqc tqm5200 charon - Heiko Schocher Active powerpc mpc5xxx - tqc tqm5200 fo300 TQM5200:FO300 - Active powerpc mpc5xxx - tqc tqm5200 MiniFAP TQM5200:MINIFAP - Active powerpc mpc5xxx - tqc tqm5200 TB5200 - - Active powerpc mpc5xxx - tqc tqm5200 TB5200_B TB5200:TQM5200_B - -Active powerpc mpc5xxx - tqc tqm5200 TQM5200 TQM5200: - +Active powerpc mpc5xxx - tqc tqm5200 TQM5200 - - Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B TQM5200:TQM5200_B - Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B_HIGHBOOT TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000 - Active powerpc mpc5xxx - tqc tqm5200 TQM5200_STK100 TQM5200:STK52XX_REV100 - @@ -685,19 +717,14 @@ Active powerpc mpc5xxx - tqc tqm5200 Active powerpc mpc5xxx - tqc tqm5200 TQM5200S_HIGHBOOT TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000 - Active powerpc mpc824x - - - utx8245 - Greg Allen Active powerpc mpc824x - - a3000 A3000 - - -Active powerpc mpc824x - - cpc45 CPC45 CPC45 Josef Wagner +Active powerpc mpc824x - - cpc45 CPC45 - Josef Wagner Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk Active powerpc mpc824x - - eXalion eXalion - Torsten Demke -Active powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso -Active powerpc mpc824x - - linkstation linkstation_HGLAN linkstation:HGLAN=1 Guennadi Liakhovetski Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson Active powerpc mpc824x - - mvblue MVBLUE - - -Active powerpc mpc824x - - pn62 PN62 - Wolfgang Grandegger Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson -Active powerpc mpc824x - etin - debris - Sangmoon Kim -Active powerpc mpc824x - etin - kvme080 - Sangmoon Kim Active powerpc mpc8260 - - - atc - Wolfgang Denk Active powerpc mpc8260 - - - ep8260 - Frank Panno Active powerpc mpc8260 - - - ep82xxm - - @@ -706,16 +733,12 @@ Active powerpc mpc8260 - - - Active powerpc mpc8260 - - - ppmc8260 - Brad Kemp Active powerpc mpc8260 - - - sacsng - Jerry Van Baren Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen -Active powerpc mpc8260 - - cpu86 CPU86 CPU86 Wolfgang Denk +Active powerpc mpc8260 - - cpu86 CPU86 - Wolfgang Denk Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk -Active powerpc mpc8260 - - cpu87 CPU87 CPU87 - +Active powerpc mpc8260 - - cpu87 CPU87 - - Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM - -Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen -Active powerpc mpc8260 - - ep8248 ep8248E ep8248 Yuli Barcohen Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger -Active powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen -Active powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher Active powerpc mpc8260 - - pm826 PM825 PM826:PCI,SYS_TEXT_BASE=0xFF000000 Wolfgang Denk @@ -726,29 +749,10 @@ Active powerpc mpc8260 - - pm826 Active powerpc mpc8260 - - pm826 PM826_BIGFLASH PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk Active powerpc mpc8260 - - pm826 PM826_ROMBOOT PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk Active powerpc mpc8260 - - pm826 PM826_ROMBOOT_BIGFLASH PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk -Active powerpc mpc8260 - - pm828 PM828 PM828 - +Active powerpc mpc8260 - - pm828 PM828 - - Active powerpc mpc8260 - - pm828 PM828_PCI PM828:PCI - Active powerpc mpc8260 - - pm828 PM828_ROMBOOT PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - Active powerpc mpc8260 - - pm828 PM828_ROMBOOT_PCI PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - -Active powerpc mpc8260 - - rattler Rattler Rattler Yuli Barcohen -Active powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen -Active powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen Active powerpc mpc8260 - freescale mpc8266ads MPC8266ADS - Rune Torgersen Active powerpc mpc8260 - funkwerk vovpn-gw VoVPN-GW_66MHz VoVPN-GW:CLKIN_66MHz - Active powerpc mpc8260 - keymile km82xx mgcoge km82xx:MGCOGE Holger Brunck @@ -766,21 +770,21 @@ Active powerpc mpc8260 - tqc tqm8260 Active powerpc mpc8260 - tqc tqm8260 TQM8265_AA TQM8260:MPC8265,300MHz,BUSMODE_60x Wolfgang Denk Active powerpc mpc8260 - tqc tqm8272 TQM8272 - - Active powerpc mpc83xx - - - mpc8308_p1m - Ilya Yanok -Active powerpc mpc83xx - - sbc8349 sbc8349 sbc8349 Paul Gortmaker +Active powerpc mpc83xx - - sbc8349 sbc8349 - Paul Gortmaker Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_33 sbc8349:PCI,PCI_33M Paul Gortmaker Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_66 sbc8349:PCI,PCI_66M Paul Gortmaker Active powerpc mpc83xx - - ve8313 ve8313 - Heiko Schocher Active powerpc mpc83xx - esd vme8349 caddy2 vme8349:CADDY2 Reinhard Arlt -Active powerpc mpc83xx - esd vme8349 vme8349 vme8349 Reinhard Arlt +Active powerpc mpc83xx - esd vme8349 vme8349 - Reinhard Arlt Active powerpc mpc83xx - freescale mpc8308rdb MPC8308RDB - Ilya Yanok Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_33 MPC8313ERDB:SYS_33MHZ - Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_66 MPC8313ERDB:SYS_66MHZ - Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_33 MPC8313ERDB:SYS_33MHZ,NAND - Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_66 MPC8313ERDB:SYS_66MHZ,NAND - -Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB MPC8315ERDB Dave Liu +Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB - Dave Liu Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB_NAND MPC8315ERDB:NAND_U_BOOT Dave Liu Active powerpc mpc83xx - freescale mpc8323erdb MPC8323ERDB - Michael Barkowski -Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS MPC832XEMDS: Dave Liu +Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS - Dave Liu Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_ATM MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_33 MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_66 MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu @@ -799,10 +803,7 @@ Active powerpc mpc83xx - freescale mpc8360emds Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_33 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_66 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu -Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK MPC8360ERDK Anton Vorontsov -Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov -Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_66 MPC8360ERDK Anton Vorontsov -Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS MPC837XEMDS Dave Liu +Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck @@ -813,12 +814,10 @@ Active powerpc mpc83xx - keymile km83xx Active powerpc mpc83xx - keymile km83xx suvd3 suvd3:SUVD3 Holger Brunck Active powerpc mpc83xx - keymile km83xx tuge1 tuxx1:TUGE1 Holger Brunck Active powerpc mpc83xx - keymile km83xx tuxx1 tuxx1:TUXX1 Holger Brunck -Active powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz -Active powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid Active powerpc mpc83xx - tqc tqm834x TQM834x - - -Active powerpc mpc85xx - - sbc8548 sbc8548 sbc8548 Paul Gortmaker +Active powerpc mpc85xx - - sbc8548 sbc8548 - Paul Gortmaker Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33 sbc8548:PCI,33 Paul Gortmaker Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33_PCIE sbc8548:PCI,33,PCIE Paul Gortmaker Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66 sbc8548:PCI,66 Paul Gortmaker @@ -826,12 +825,12 @@ Active powerpc mpc85xx - - sbc8548 Active powerpc mpc85xx - - socrates socrates - - Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 - -Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 - -Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND_SYSCLK100 BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100 Poonam Aggrwal Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH BSC9131RDB:BSC9131RDB,SPIFLASH Poonam Aggrwal @@ -845,64 +844,79 @@ Active powerpc mpc85xx - freescale bsc9132qds Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu +Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu Active powerpc mpc85xx - freescale corenet_ds P3041DS - - -Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P3041DS_SECURE_BOOT P3041DS:SECURE_BOOT - -Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P4080DS - - -Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P4080DS_SECURE_BOOT P4080DS:SECURE_BOOT - -Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P5020DS - - -Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P5020DS_SECURE_BOOT P5020DS:SECURE_BOOT - -Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P5040DS - - -Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS MPC8536DS - +Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS - - Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT - Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND - Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SDCARD MPC8536DS:SDCARD - Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SPIFLASH MPC8536DS:SPIFLASH - Active powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala -Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS MPC8541CDS Kumar Gala +Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS - Kumar Gala Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala Active powerpc mpc85xx - freescale mpc8544ds MPC8544DS - - -Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS MPC8548CDS - +Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS - - Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_36BIT MPC8548CDS:36BIT - Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_legacy MPC8548CDS:LEGACY - -Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS MPC8555CDS Kumar Gala +Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS - Kumar Gala Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala Active powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala Active powerpc mpc85xx - freescale mpc8568mds MPC8568MDS - - -Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS MPC8569MDS - +Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS - - Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM - Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND - -Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS MPC8572DS - +Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - - Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT - Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND - -Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_NAND P1010RDB:P1010RDB,36BIT,NAND - -Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_NAND_SECBOOT P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT - -Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_NOR P1010RDB:P1010RDB,36BIT - -Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_NOR_SECBOOT P1010RDB:P1010RDB,36BIT,SECURE_BOOT - -Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_SDCARD P1010RDB:P1010RDB,36BIT,SDCARD - -Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_SPIFLASH P1010RDB:P1010RDB,36BIT,SPIFLASH - -Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB,36BIT,SPIFLASH,SECURE_BOOT - -Active powerpc mpc85xx - freescale p1010rdb P1010RDB_NAND P1010RDB:P1010RDB,NAND - -Active powerpc mpc85xx - freescale p1010rdb P1010RDB_NAND_SECBOOT P1010RDB:P1010RDB,NAND_SECBOOT,SECURE_BOOT - -Active powerpc mpc85xx - freescale p1010rdb P1010RDB_NOR P1010RDB:P1010RDB - -Active powerpc mpc85xx - freescale p1010rdb P1010RDB_NOR_SECBOOT P1010RDB:P1010RDB,SECURE_BOOT - -Active powerpc mpc85xx - freescale p1010rdb P1010RDB_SDCARD P1010RDB:P1010RDB,SDCARD - -Active powerpc mpc85xx - freescale p1010rdb P1010RDB_SPIFLASH P1010RDB:P1010RDB,SPIFLASH - -Active powerpc mpc85xx - freescale p1010rdb P1010RDB_SPIFLASH_SECBOOT P1010RDB:P1010RDB,SPIFLASH,SECURE_BOOT - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR P1010RDB:P1010RDB_PA,36BIT - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR_SECBOOT P1010RDB:P1010RDB_PA,36BIT,SECURE_BOOT - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SDCARD P1010RDB:P1010RDB_PA,36BIT,SDCARD - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SPIFLASH P1010RDB:P1010RDB_PA,36BIT,SPIFLASH - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NAND P1010RDB:P1010RDB_PA,NAND - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NAND_SECBOOT P1010RDB:P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NOR P1010RDB:P1010RDB_PA - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NOR_SECBOOT P1010RDB:P1010RDB_PA,SECURE_BOOT - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SDCARD P1010RDB:P1010RDB_PA,SDCARD - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SPIFLASH P1010RDB:P1010RDB_PA,SPIFLASH - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PA,SPIFLASH,SECURE_BOOT - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NAND P1010RDB:P1010RDB_PB,36BIT,NAND - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NOR P1010RDB:P1010RDB_PB,36BIT - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB:P1010RDB_PB,36BIT,SECURE_BOOT - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SDCARD P1010RDB:P1010RDB_PB,36BIT,SDCARD - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SPIFLASH P1010RDB:P1010RDB_PB,36BIT,SPIFLASH - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NAND P1010RDB:P1010RDB_PB,NAND - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NAND_SECBOOT P1010RDB:P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NOR P1010RDB:P1010RDB_PB - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NOR_SECBOOT P1010RDB:P1010RDB_PB,SECURE_BOOT - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SDCARD P1010RDB:P1010RDB_PB,SDCARD - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SPIFLASH P1010RDB:P1010RDB_PB,SPIFLASH - +Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PB,SPIFLASH,SECURE_BOOT - Active powerpc mpc85xx - freescale p1022ds P1022DS - Timur Tabi Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT P1022DS:36BIT Timur Tabi Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_NAND P1022DS:36BIT,NAND Timur Tabi @@ -911,8 +925,8 @@ Active powerpc mpc85xx - freescale p1022ds Active powerpc mpc85xx - freescale p1022ds P1022DS_NAND P1022DS:NAND Timur Tabi Active powerpc mpc85xx - freescale p1022ds P1022DS_SDCARD P1022DS:SDCARD Timur Tabi Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi -Active powerpc mpc85xx - freescale p1023rdb P1023RDB P1023RDB - -Active powerpc mpc85xx - freescale p1023rds P1023RDS P1023RDS Roy Zang +Active powerpc mpc85xx - freescale p1023rdb P1023RDB - - +Active powerpc mpc85xx - freescale p1023rds P1023RDS - Roy Zang Active powerpc mpc85xx - freescale p1023rds P1023RDS_NAND P1023RDS:NAND Roy Zang Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB - Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT - @@ -997,32 +1011,53 @@ Active powerpc mpc85xx - freescale p2020ds Active powerpc mpc85xx - freescale p2020ds P2020DS_SDCARD P2020DS:SDCARD - Active powerpc mpc85xx - freescale p2020ds P2020DS_SPIFLASH P2020DS:SPIFLASH - Active powerpc mpc85xx - freescale p2041rdb P2041RDB - - -Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SECURE_BOOT P2041RDB:SECURE_BOOT - -Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal +Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal +Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal +Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 - +Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081 - +Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 - +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 - -Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 - -Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach +Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp +Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek -Active powerpc mpc85xx - stx stxssa stxssa stxssa Dan Malek +Active powerpc mpc85xx - stx stxssa stxssa - Dan Malek Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek Active powerpc mpc85xx - xes - xpedite520x - - Active powerpc mpc85xx - xes - xpedite537x - - Active powerpc mpc85xx - xes - xpedite550x - - Active powerpc mpc86xx - - - sbc8641d - Paul Gortmaker Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - - -Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN MPC8641HPCN Kumar Gala +Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala Active powerpc mpc86xx - xes - xpedite517x - - Active powerpc mpc8xx - - - hermes - Wolfgang Denk @@ -1032,10 +1067,6 @@ Active powerpc mpc8xx - - - Active powerpc mpc8xx - - - spc1920 - - Active powerpc mpc8xx - - - svm_sc8xx - John Zhan Active powerpc mpc8xx - - - v37 - - -Active powerpc mpc8xx - - adder Adder - Yuli Barcohen -Active powerpc mpc8xx - - adder Adder87x Adder Yuli Barcohen -Active powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen -Active powerpc mpc8xx - - adder AdderUSB Adder Yuli Barcohen Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark Active powerpc mpc8xx - - fads MPC86xADS - - @@ -1054,7 +1085,7 @@ Active powerpc mpc8xx - - ivm Active powerpc mpc8xx - - ivm IVMS8_256 IVMS8:IVMS8_64M Wolfgang Denk Active powerpc mpc8xx - - netphone NETPHONE NETPHONE:NETPHONE_VERSION=1 - Active powerpc mpc8xx - - netphone NETPHONE_V2 NETPHONE:NETPHONE_VERSION=2 - -Active powerpc mpc8xx - - netta NETTA NETTA - +Active powerpc mpc8xx - - netta NETTA - - Active powerpc mpc8xx - - netta NETTA_6412 NETTA:NETTA_6412=1 - Active powerpc mpc8xx - - netta NETTA_6412_SWAPHOOK NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1 - Active powerpc mpc8xx - - netta NETTA_ISDN NETTA:NETTA_ISDN=1 - @@ -1068,7 +1099,7 @@ Active powerpc mpc8xx - - netvia Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk Active powerpc mpc8xx - - rbc823 RBC823 - - -Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW RPXlite_DW - +Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW - - Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64 RPXlite_DW:RPXlite_64MHz - Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 - Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_LCD RPXlite_DW:LCD,NEC_NL6448BC20 - @@ -1128,7 +1159,6 @@ Active powerpc ppc4xx - - w7o Active powerpc ppc4xx - - w7o W7OLMG - Erik Theisen Active powerpc ppc4xx - amcc - acadia - Stefan Roese Active powerpc ppc4xx - amcc - bamboo - Stefan Roese -Active powerpc ppc4xx - amcc - bluestone - Tirumala Marri Active powerpc ppc4xx - amcc - bubinga - - Active powerpc ppc4xx - amcc - ebony - Stefan Roese Active powerpc ppc4xx - amcc - katmai - Stefan Roese @@ -1139,22 +1169,14 @@ Active powerpc ppc4xx - amcc - Active powerpc ppc4xx - amcc - taihu - John Otken Active powerpc ppc4xx - amcc - taishan - Stefan Roese Active powerpc ppc4xx - amcc - yucca - - -Active powerpc ppc4xx - amcc acadia acadia_nand acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese -Active powerpc ppc4xx - amcc bamboo bamboo_nand bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese -Active powerpc ppc4xx - amcc canyonlands canyonlands_nand canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese -Active powerpc ppc4xx - amcc canyonlands glacier_nand canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese -Active powerpc ppc4xx - amcc kilauea haleakala_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese -Active powerpc ppc4xx - amcc kilauea kilauea_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese -Active powerpc ppc4xx - amcc sequoia rainier_nand sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese -Active powerpc ppc4xx - amcc sequoia sequoia_nand sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese @@ -1164,7 +1186,6 @@ Active powerpc ppc4xx - avnet fx12mm Active powerpc ppc4xx - avnet fx12mm fx12mm_flash fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval_flash v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda -Active powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff Active powerpc ppc4xx - dave PPChameleonEVB CATcenter CATcenter:PPCHAMELEON_MODULE_MODEL=1 - Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_25 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 - Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_33 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 - @@ -1214,8 +1235,6 @@ Active powerpc ppc4xx - mpl mip405 Active powerpc ppc4xx - mpl pip405 PIP405 - Denis Peter Active powerpc ppc4xx - prodrive - alpr - Stefan Roese Active powerpc ppc4xx - prodrive - p3p440 - Stefan Roese -Active powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer (travis.sawyer@sandburst.com> -Active powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer (travis.sawyer@sandburst.com> Active powerpc ppc4xx - xes - xpedite1000 - Peter Tyser Active powerpc ppc4xx - xilinx ml507 ml507 ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda Active powerpc ppc4xx - xilinx ml507 ml507_flash ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda @@ -1241,6 +1260,7 @@ Active sh sh4 - renesas r0p7734 Active sh sh4 - renesas r2dplus r2dplus - Nobuhiro Iwamatsu :Nobuhiro Iwamatsu Active sh sh4 - renesas r7780mp r7780mp - Nobuhiro Iwamatsu :Nobuhiro Iwamatsu Active sh sh4 - renesas sh7752evb sh7752evb - - +Active sh sh4 - renesas sh7753evb sh7753evb - - Active sh sh4 - renesas sh7757lcr sh7757lcr - - Active sh sh4 - renesas sh7763rdp sh7763rdp - Nobuhiro Iwamatsu :Nobuhiro Iwamatsu Active sh sh4 - renesas sh7785lcr sh7785lcr - - @@ -1251,12 +1271,57 @@ Active sparc leon3 - gaisler - Active sparc leon3 - gaisler - gr_xc3s_1500 - - Active sparc leon3 - gaisler - grsim - - Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 - +# The following were moved to "Orphan" in March, 2014 +Orphan blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards +Orphan blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards +Orphan blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards +Orphan blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards +Orphan blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards +Orphan blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards +Orphan blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards +Orphan blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards +Orphan powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz +Orphan powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz +Orphan powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso +Orphan powerpc mpc824x - etin - debris - Sangmoon Kim +Orphan powerpc mpc824x - etin - kvme080 - Sangmoon Kim +Orphan powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen +Orphan powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen +Orphan powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen +Orphan powerpc mpc8260 - - rattler Rattler - Yuli Barcohen +Orphan powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen +Orphan powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen +Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov +Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov +Orphan powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz +Orphan powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz +Orphan powerpc mpc8xx - - adder Adder - Yuli Barcohen +Orphan powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen +Orphan powerpc ppc4xx - amcc - bluestone - Tirumala Marri +Orphan powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff +Orphan powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer +Orphan powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer +# The following were move to "Orphan" in September, 2013 Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski -Orphan arm arm925t - ti - omap1510inn - Kshitij Gupta Orphan arm pxa - - - lubbock - (dead address) Kyle Harris -Orphan powerpc 74xx_7xx - - evb64260 EVB64260 EVB64260 - -Orphan powerpc 74xx_7xx - - evb64260 EVB64260_750CX EVB64260 Eran Man +Orphan powerpc 74xx_7xx - - evb64260 EVB64260 - - Orphan powerpc mpc824x - - mousse MOUSSE - - Orphan powerpc mpc8260 - - - rsdproto - - Orphan powerpc mpc8260 - - rpxsuper RPXsuper - - diff --git a/patch/u-boot-sunxi/make_uboot_patch.sh b/patch/u-boot-sunxi/make_uboot_patch.sh new file mode 100755 index 0000000..15c974f --- /dev/null +++ b/patch/u-boot-sunxi/make_uboot_patch.sh @@ -0,0 +1,48 @@ +#!/bin/sh +# make_uboot_patch.sh, save add/changed files patch dir +# run command "git status" to get the changed files +cd `dirname $0` +TOP_DIR=`pwd`/../ +TMP_PATCH_DIR=`pwd`/../patch_tmp/patch/u-boot-sunxi/ +changes=`git status -s | grep " M " | cut -b 4-` +adds=`git status -s | grep "?? " | cut -d ' ' -f2` +rm -rf ${TMP_PATCH_DIR}/ +mkdir -p ${TMP_PATCH_DIR}/ + +for i in $changes +do + if [ -f $i ]; then + echo "copy $i" + dest=${TMP_PATCH_DIR}/`dirname $i` + mkdir -p $dest && + cp $i $dest + fi +done + +for i in $adds +do + if [ -d $i ]; then + echo "add dir $i" + dest=${TMP_PATCH_DIR}/`dirname $i` + mkdir -p $dest && + cp $i $dest -ar + elif [ -f $i ]; then + echo "add file $i" + dest=${TMP_PATCH_DIR}/`dirname $i` + mkdir -p $dest && + cp $i $dest + fi +done + +cd $TMP_PATCH_DIR/ +find ./ -name "*.cmd" | xargs rm -rf +find ./ -name "*.mod.c" | xargs rm -rf +find ./ -name "*.ko" | xargs rm -rf +find ./ -name "modules.builtin" | xargs rm -rf +find ./ -name "modules.order" | xargs rm -rf + +cd $TMP_PATCH_DIR/../../ +tar zcf patch.tgz ./patch +tar zxf patch.tgz -C $TOP_DIR +rm -rf ${TOP_DIR}/kernel_patch_tmp/ +echo "generated kernel patch to $TOP_DIR/patch/u-boot-sunxi" diff --git a/scripts/mk_livesuit_img.sh b/scripts/mk_livesuit_img.sh index 6b6a4a8..80d1d81 100755 --- a/scripts/mk_livesuit_img.sh +++ b/scripts/mk_livesuit_img.sh @@ -253,7 +253,7 @@ pack_cmd() fi } -function do_pack_a20() +do_pack_a20() { echo "Packing for linux" export PATH=${LIVESUIT_DIR}/a20/mod_update:${LIVESUIT_DIR}/a20/eDragonEx:${LIVESUIT_DIR}/a20/fsbuild200:$PATH @@ -294,6 +294,11 @@ function do_pack_a20() if [ -f ${BUILD_DIR}/bootlogo.bmp ]; then cp ${BUILD_DIR}/bootlogo.bmp bootfs/os_show/ -f fi + + if [ "$BOARD" = "pcduino3_lvds" ] || [ "$BOARD" = "pcduino3b_lvds" ]; then + cp bootfs/boot_lvds.axf bootfs/boot.axf -f + cp bootfs/drv_de_lvds.drv bootfs/drv_de.drv -f + fi pack_cmd update_mbr sys_partition.bin 4 pack_cmd update_boot0 boot0_nand.bin sys_config.bin NAND diff --git a/sunxi-boards/sys_config/a20/pcduino3.fex b/sunxi-boards/sys_config/a20/pcduino3.fex index c005604..7182cbd 100644 --- a/sunxi-boards/sys_config/a20/pcduino3.fex +++ b/sunxi-boards/sys_config/a20/pcduino3.fex @@ -96,7 +96,7 @@ standby_mode = 0 ;------------------------------------------------------------------------------- [dram_para] dram_baseaddr = 0x40000000 -dram_clk = 480 +dram_clk = 408 dram_type = 3 dram_rank_num = 0xffffffff dram_chip_density = 0xffffffff @@ -153,24 +153,24 @@ emac_reset = port:PA17<1> ;--------------------------------------------------------- [gmac_para] gmac_used = 1 -gmac_rxd3 = port:PA00<5> -gmac_rxd2 = port:PA01<5> -gmac_rxd1 = port:PA02<5> -gmac_rxd0 = port:PA03<5> -gmac_txd3 = port:PA04<5> -gmac_txd2 = port:PA05<5> -gmac_txd1 = port:PA06<5> -gmac_txd0 = port:PA07<5> -gmac_rxclk = port:PA08<5> -gmac_rxerr = port:PA09<0> -gmac_rxctl = port:PA10<5> -gmac_mdc = port:PA11<5> -gmac_mdio = port:PA12<5> -gmac_txctl = port:PA13<5> -gmac_txclk = port:PA14<0> -gmac_txck = port:PA15<5> -gmac_clkin = port:PA16<5> -gmac_txerr = port:PA17<0> +gmac_rxd3 = port:PA00<5><3> +gmac_rxd2 = port:PA01<5><3> +gmac_rxd1 = port:PA02<5><3> +gmac_rxd0 = port:PA03<5><3> +gmac_txd3 = port:PA04<5><3> +gmac_txd2 = port:PA05<5><3> +gmac_txd1 = port:PA06<5><3> +gmac_txd0 = port:PA07<5><3> +gmac_rxclk = port:PA08<5><3> +gmac_rxerr = port:PA09<0><3> +gmac_rxctl = port:PA10<5><3> +gmac_mdc = port:PA11<5><3> +gmac_mdio = port:PA12<5><3> +gmac_txctl = port:PA13<5><3> +gmac_txclk = port:PA14<0><3> +gmac_txck = port:PA15<5><3> +gmac_clkin = port:PA16<5><3> +gmac_txerr = port:PA17<0><3> ;------------------------------------------------------------------------------- ;i2c configuration @@ -218,8 +218,8 @@ uart_ring = port:PA17<4><1> uart_used = 1 uart_port = 2 uart_type = 4 -uart_tx = port:PI18<3><1> -uart_rx = port:PI19<3><1> +uart_tx = port:PI18<0><2> +uart_rx = port:PI19<1><2> uart_rts = port:PI16<3><1> uart_cts = port:PI17<3><1> @@ -266,11 +266,11 @@ uart_rx = port:PA15<3><1> [spi0_para] spi_used = 1 spi_cs_bitmap = 1 -spi_cs0 = port:PI10<2> +spi_cs0 = port:PI10<0><2> spi_cs1 = port:PI14<2> -spi_sclk = port:PI11<2> -spi_mosi = port:PI12<2> -spi_miso = port:PI13<2> +spi_sclk = port:PI11<0><2> +spi_mosi = port:PI12<0><2> +spi_miso = port:PI13<0><2> [spi1_para] spi_used = 0 @@ -284,11 +284,11 @@ spi_miso = port:PA03<3> [spi2_para] spi_used = 1 spi_cs_bitmap = 1 -spi_cs0 = port:PC19<3> +spi_cs0 = port:PC19<0><2> spi_cs1 = port:PB13<2> -spi_sclk = port:PC20<3> -spi_mosi = port:PC21<3> -spi_miso = port:PC22<3> +spi_sclk = port:PC20<0><2> +spi_mosi = port:PC21<0><2> +spi_miso = port:PC22<0><2> [spi3_para] spi_used = 0 @@ -339,17 +339,17 @@ rtp_exchange_x_y_flag = 0 ; tp_int_port & tp_io_port use the same port ;------------------------------------------------------------------------------- [ctp_para] -ctp_used = 0 +ctp_used = 1 ctp_twi_id = 2 -ctp_twi_name = -ctp_screen_max_x = 800 -ctp_screen_max_y = 480 +ctp_twi_name = "gslX680" +ctp_screen_max_x = 1024 +ctp_screen_max_y = 600 ctp_revert_x_flag = 0 ctp_revert_y_flag = 0 ctp_exchange_x_y_flag = 0 -ctp_int_port = port:PH21<6> -ctp_wakeup = port:PB13<1><1> +ctp_int_port = port:PH10<6> +ctp_wakeup = ;------------------------------------------------------------------------------- ;touch key configuration @@ -485,20 +485,20 @@ lcd1_hue = 50 [lcd0_para] lcd_used = 0 -lcd_x = 800 -lcd_y = 480 -lcd_width = 0 -lcd_height = 0 -lcd_dclk_freq = 33 -lcd_pwm_not_used = 0 +lcd_x = 1024 +lcd_y = 600 +lcd_width = 0 +lcd_height = 0 +lcd_dclk_freq = 51 +lcd_pwm_not_used = 1 lcd_pwm_ch = 0 lcd_pwm_freq = 10000 lcd_pwm_pol = 0 -lcd_if = 0 -lcd_hbp = 46 -lcd_ht = 1055 -lcd_vbp = 23 -lcd_vt = 1050 +lcd_if = 3 +lcd_hbp = 310 +lcd_ht = 1340 +lcd_vbp = 30 +lcd_vt = 1268 lcd_vspw = 0 lcd_hspw = 0 lcd_hv_if = 0 @@ -526,34 +526,16 @@ lcd_power = port:PH08<1><0><1> lcd_pwm_used = 0 lcd_pwm = port:PB02<2><0> -lcdd0 = port:PD00<2><0> -lcdd1 = port:PD01<2><0> -lcdd2 = port:PD02<2><0> -lcdd3 = port:PD03<2><0> -lcdd4 = port:PD04<2><0> -lcdd5 = port:PD05<2><0> -lcdd6 = port:PD06<2><0> -lcdd7 = port:PD07<2><0> -lcdd8 = port:PD08<2><0> -lcdd9 = port:PD09<2><0> -lcdd10 = port:PD10<2><0> -lcdd11 = port:PD11<2><0> -lcdd12 = port:PD12<2><0> -lcdd13 = port:PD13<2><0> -lcdd14 = port:PD14<2><0> -lcdd15 = port:PD15<2><0> -lcdd16 = port:PD16<2><0> -lcdd17 = port:PD17<2><0> -lcdd18 = port:PD18<2><0> -lcdd19 = port:PD19<2><0> -lcdd20 = port:PD20<2><0> -lcdd21 = port:PD21<2><0> -lcdd22 = port:PD22<2><0> -lcdd23 = port:PD23<2><0> -lcdclk = port:PD24<2><0> -lcdde = port:PD25<2><0> -lcdhsync = port:PD26<2><0> -lcdvsync = port:PD27<2><0> +lcdd0 = port:PD00<3> +lcdd1 = port:PD01<3> +lcdd2 = port:PD02<3> +lcdd3 = port:PD03<3> +lcdd4 = port:PD04<3> +lcdd5 = port:PD05<3> +lcdd6 = port:PD06<3> +lcdd7 = port:PD07<3> +lcdd8 = port:PD08<3> +lcdd9 = port:PD09<3> ;---------------------------------------------------------------------------------- ;lcd1 configuration @@ -584,18 +566,20 @@ lcdvsync = port:PD27<2><0> [lcd1_para] lcd_used = 0 -lcd_x = 0 -lcd_y = 0 -lcd_dclk_freq = 0 +lcd_x = 1024 +lcd_y = 600 +lcd_width = 0 +lcd_height = 0 +lcd_dclk_freq = 51 lcd_pwm_not_used = 0 -lcd_pwm_ch = 1 -lcd_pwm_freq = 0 +lcd_pwm_ch = 0 +lcd_pwm_freq = 10000 lcd_pwm_pol = 0 -lcd_if = 0 -lcd_hbp = 0 -lcd_ht = 0 -lcd_vbp = 0 -lcd_vt = 0 +lcd_if = 3 +lcd_hbp = 310 +lcd_ht = 1340 +lcd_vbp = 30 +lcd_vt = 1268 lcd_vspw = 0 lcd_hspw = 0 lcd_hv_if = 0 @@ -614,48 +598,30 @@ lcd_gamma_tbl_0 = 0x00000000 lcd_gamma_tbl_1 = 0x00010101 lcd_gamma_tbl_255 = 0x00ffffff -lcd_bl_en_used = 0 -lcd_bl_en = +lcd_bl_en_used = 1 +lcd_bl_en = port:PH07<1><1> -lcd_power_used = 0 -lcd_power = +lcd_power_used = 1 +lcd_power = port:PH08<1><1> -lcd_pwm_used = 0 -lcd_pwm = port:PI03<2><0> +lcd_pwm_used = 1 +lcd_pwm = port:PH06<1><0> lcd_gpio_0 = lcd_gpio_1 = lcd_gpio_2 = lcd_gpio_3 = -lcdd0 = port:PH00<2><0> -lcdd1 = port:PH01<2><0> -lcdd2 = port:PH02<2><0> -lcdd3 = port:PH03<2><0> -lcdd4 = port:PH04<2><0> -lcdd5 = port:PH05<2><0> -lcdd6 = port:PH06<2><0> -lcdd7 = port:PH07<2><0> -lcdd8 = port:PH08<2><0> -lcdd9 = port:PH09<2><0> -lcdd10 = port:PH10<2><0> -lcdd11 = port:PH11<2><0> -lcdd12 = port:PH12<2><0> -lcdd13 = port:PH13<2><0> -lcdd14 = port:PH14<2><0> -lcdd15 = port:PH15<2><0> -lcdd16 = port:PH16<2><0> -lcdd17 = port:PH17<2><0> -lcdd18 = port:PH18<2><0> -lcdd19 = port:PH19<2><0> -lcdd20 = port:PH20<2><0> -lcdd21 = port:PH21<2><0> -lcdd22 = port:PH22<2><0> -lcdd23 = port:PH23<2><0> -lcdclk = port:PH24<2><0> -lcdde = port:PH25<2><0> -lcdhsync = port:PH26<2><0> -lcdvsync = port:PH27<2><0> +lcdd10 = port:PD10<3> +lcdd11 = port:PD11<3> +lcdd12 = port:PD12<3> +lcdd13 = port:PD13<3> +lcdd14 = port:PD14<3> +lcdd15 = port:PD15<3> +lcdd16 = port:PD16<3> +lcdd17 = port:PD17<3> +lcdd18 = port:PD18<3> +lcdd19 = port:PD19<3> ;------------------------------------------------------------------------------- ;tv out dac configuration @@ -743,11 +709,11 @@ siv121d = 0 ;-------------------------------------------------------------------------------- [csi0_para] -csi_used = 0 +csi_used = 1 csi_dev_qty = 1 csi_stby_mode = 0 -csi_mname = "gc0308" +csi_mname = "gc2035" csi_if = 0 csi_iovdd = "" csi_avdd = "" @@ -761,7 +727,7 @@ csi_flash_pol = 0 csi_facing = 0 csi_twi_id = 1 -csi_twi_addr = 0x42 +csi_twi_addr = 0x78 csi_pck = port:PE00<3> csi_ck = port:PE01<3> csi_hsync = port:PE02<3> @@ -774,9 +740,9 @@ csi_d4 = port:PE08<3> csi_d5 = port:PE09<3> csi_d6 = port:PE10<3> csi_d7 = port:PE11<3> -csi_reset = port:PH13<1><0> -csi_power_en = -csi_stby = port:PH16<1><0> +csi_reset = port:PH27<1><1> +csi_power_en = port:PH26<1><0> +csi_stby = [csi1_para] csi_used = 0 @@ -833,7 +799,7 @@ tvin_channel_num = 4 ;------------------------------------------------------------------------------- [sata_para] sata_used = 1 -sata_power_en = +sata_power_en = port:PH02<1><1> ;------------------------------------------------------------------------------- @@ -1013,7 +979,7 @@ kp_out7 = port:PH27<4><1> ;------------------------------------------------------------------------------- [usbc0] usb_used = 1 -usb_port_type = 1 +usb_port_type = 0 usb_detect_type = 0 usb_id_gpio = port:PH04<0><1> usb_det_vbus_gpio = "axp_ctrl" @@ -1031,7 +997,7 @@ usb_restric_capacity= 5 usb_used = 1 usb_port_type = 1 usb_detect_type = 0 -usb_drv_vbus_gpio = port:PH06<1><0><0> +usb_drv_vbus_gpio = port:PH11<1><0><0> usb_restrict_gpio = usb_host_init_state = 1 usb_restric_flag = 0 @@ -1319,6 +1285,7 @@ spdif_din = [audio_para] audio_used = 1 audio_pa_ctrl = port:PH15<1><0> +capture_used = 1 [switch_para] switch_used = 0 @@ -1327,8 +1294,8 @@ switch_used = 0 ;ir --- infra remote configuration ;------------------------------------------------------------------------------- [ir_para] -ir_used = 0 -ir_rx = port:PB04<2> +ir_used = 1 +ir0_rx = port:PB04<2> ;------------------------------------------------------------------------------- @@ -1503,33 +1470,61 @@ LV8_volt = 1050 [gpio_para] gpio_used = 1 -gpio_num = 24 -gpio_pin_0 = port:PI19<0><1> -gpio_pin_1 = port:PI18<0><1> -gpio_pin_2 = port:PH07<0><1> -gpio_pin_3 = port:PH06<0><1> -gpio_pin_4 = port:PH08<0><1> -gpio_pin_5 = port:PB02<0><1> -gpio_pin_6 = port:PI03<0><1> -gpio_pin_7 = port:PH09<0><1> -gpio_pin_8 = port:PH10<0><1> -gpio_pin_9 = port:PH05<0><1> -gpio_pin_10 = port:PI10<0><1> -gpio_pin_11 = port:PI12<0><1> -gpio_pin_12 = port:PI13<0><1> -gpio_pin_13 = port:PI11<0><1> -gpio_pin_14 = port:PH11<0><1> -gpio_pin_15 = port:PH12<0><1> -gpio_pin_16 = port:PH13<0><1> -gpio_pin_17 = port:PH14<0><1> +gpio_num = 51 +gpio_pin_0 = port:PI19<1><2> +gpio_pin_1 = port:PI18<0><2> +gpio_pin_2 = port:PH07<0><2> +gpio_pin_3 = port:PH06<0><2> +gpio_pin_4 = port:PH08<0><2> +gpio_pin_5 = port:PB02<0><2> +gpio_pin_6 = port:PI03<0><2> +gpio_pin_7 = port:PH09<0><2> +gpio_pin_8 = port:PH10<0><2> +gpio_pin_9 = port:PH05<0><2> +gpio_pin_10 = port:PI10<0><2> +gpio_pin_11 = port:PI12<0><2> +gpio_pin_12 = port:PI13<0><2> +gpio_pin_13 = port:PI11<0><2> +gpio_pin_14 = port:PH11<0><2> +gpio_pin_15 = port:PH12<0><2> +gpio_pin_16 = port:PH13<0><2> +gpio_pin_17 = port:PH14<0><2> gpio_pin_18 = port:PH15<1><0> gpio_pin_19 = port:PH16<1><0> -gpio_pin_20 = port:PC19<0><1> -gpio_pin_21 = port:PC21<0><1> -gpio_pin_22 = port:PC22<0><1> -gpio_pin_23 = port:PC20<0><1> -; Redeclared gpio_pin_0 as gpio_pin_24, for sun4i-gpio driver -gpio_pin_24 = port:PI19<0><1> +gpio_pin_20 = port:PC19<0><2> +gpio_pin_21 = port:PC21<0><2> +gpio_pin_22 = port:PC22<0><2> +gpio_pin_23 = port:PC20<0><2> +gpio_pin_24 = port:PD10<3> +gpio_pin_25 = port:PD11<3> +gpio_pin_26 = port:PD12<3> +gpio_pin_27 = port:PD13<3> +gpio_pin_28 = port:PD14<3> +gpio_pin_29 = port:PD15<3> +gpio_pin_30 = port:PD16<3> +gpio_pin_31 = port:PD17<3> +gpio_pin_32 = port:PD18<3> +gpio_pin_33 = port:PD19<3> +gpio_pin_34 = port:PE04<3> +gpio_pin_35 = port:PE05<3> +gpio_pin_36 = port:PE06<3> +gpio_pin_37 = port:PE07<3> +gpio_pin_38 = port:PE08<3> +gpio_pin_39 = port:PE09<3> +gpio_pin_40 = port:PE10<3> +gpio_pin_41 = port:PE11<3> +gpio_pin_42 = port:PB19<2> +gpio_pin_43 = port:PB18<2> +gpio_pin_44 = port:PE02<3> +gpio_pin_45 = port:PE03<3> +gpio_pin_46 = port:PE00<3> +gpio_pin_47 = port:PE01<3> +gpio_pin_48 = port:PH26<1><0> +gpio_pin_49 = port:PH27<1><1> + +; usb_power_en +gpio_pin_50 = port:PD02<1><1> +gpio_pin_51 = port:PI19<0><1> [sb_pwm0] pwm_gpio = port:PH06<1> @@ -1549,3 +1544,16 @@ pwm_gpio = port:PI10<1> [sb_pwm5] pwm_gpio = port:PI12<1> +[sb_keypad_para] +sb_key_used = 1 +key_num = 3 +; BACK ==> KEY_ESC +key_pin_0 = port:PH17<6><1><3> +key_code_0 = 1 +; MENU ==> KEY_SPACE +key_pin_1 = port:PH18<6><1><3> +key_code_1 = 57 +; HOME ==> KEY_ENTER +key_pin_2 = port:PH19<6><1><3> +key_code_2 = 28 + diff --git a/sunxi-boards/sys_config/a20/pcduino3_lvds.fex b/sunxi-boards/sys_config/a20/pcduino3_lvds.fex new file mode 100644 index 0000000..07eea4f --- /dev/null +++ b/sunxi-boards/sys_config/a20/pcduino3_lvds.fex @@ -0,0 +1,1533 @@ +;A20 PAD application +;------------------------------------------------------------------------------- +; 说明： +; 1. 脚本中的字符串区分大小写，用户可以修改"="后面的数值，但是不要修改前面的字符串 +; 2. 新增主键和子键的名称必须控制在32个字符以内，不包括32个 +; 3. 所以的注释以“;”开始，单独占据一行 +; 4. 注释不可和配置项同行，例如：主键和子健后面不能添加任何形式的注释 +; +; gpio的描述形式：Port:端口+组内序号<功能分配><内部电阻状态><驱动能力><输出电平状态> +; 例如：port:PA0<0> +;------------------------------------------------------------------------------- + +[product] +version = "100" +machine = "pcduino3-v10" + +[platform] +eraseflag = 1 + +[target] +boot_clock = 912 +dcdc2_vol = 1400 +dcdc3_vol = 1250 +ldo2_vol = 3000 +ldo3_vol = 2800 +ldo4_vol = 2800 +power_start = 3 +storage_type = -1 + +[clock] +pll3 = 297 +pll4 = 300 +pll6 = 600 +pll7 = 297 +pll8 = 336 + +[card_boot] +logical_start = 40960 +sprite_gpio0 = port:PH15<1><0> +sprite_work_delay = 1000 +sprite_err_delay = 100 + +[card0_boot_para] +card_ctrl = 0 +card_high_speed = 1 +card_line = 4 +sdc_d1 = port:PF0<2><1> +sdc_d0 = port:PF1<2><1> +sdc_clk = port:PF2<2><1> +sdc_cmd = port:PF3<2><1> +sdc_d3 = port:PF4<2><1> +sdc_d2 = port:PF5<2><1> + +[card2_boot_para] +card_ctrl = 2 +card_high_speed = 1 +card_line = 4 +sdc_cmd = port:PC6<3><1> +sdc_clk = port:PC7<3><1> +sdc_d0 = port:PC8<3><1> +sdc_d1 = port:PC9<3><1> +sdc_d2 = port:PC10<3><1> +sdc_d3 = port:PC11<3><1> + +[twi_para] +twi_port = 0 +twi_scl = port:PB0<2> +twi_sda = port:PB1<2> + +[uart_para] +uart_debug_port = 0 +uart_debug_tx = port:PB22<2><1> +uart_debug_rx = port:PB23<2><1> + +[uart_force_debug] +uart_debug_port = 0 +uart_debug_tx =port:PF2<4><1> +uart_debug_rx =port:PF4<4><1> + +[jtag_para] +jtag_enable = 0 +jtag_ms = port:PB14<3> +jtag_ck = port:PB15<3> +jtag_do = port:PB16<3> +jtag_di = port:PB17<3> + +;--------------------------------------------------------------------------------------------------------- +; if 1 == standby_mode, then support super standby; +; else, support normal standby. +;--------------------------------------------------------------------------------------------------------- +[pm_para] +standby_mode = 0 + +;------------------------------------------------------------------------------- +;sdram configuration +;------------------------------------------------------------------------------- +[dram_para] +dram_baseaddr = 0x40000000 +dram_clk = 408 +dram_type = 3 +dram_rank_num = 0xffffffff +dram_chip_density = 0xffffffff +dram_io_width = 0xffffffff +dram_bus_width = 0xffffffff +dram_cas = 9 +dram_zq = 0x7a +dram_odt_en = 0 +dram_size = 0xffffffff +dram_tpr0 = 0x42d899b7 +dram_tpr1 = 0xa090 +dram_tpr2 = 0x22a00 +dram_tpr3 = 0x0 +dram_tpr4 = 0x0 +dram_tpr5 = 0x0 +dram_emr1 = 0x4 +dram_emr2 = 0x10 +dram_emr3 = 0x0 + +;------------------------------------------------------------------------------- +;Mali configuration +;------------------------------------------------------------------------------- +[mali_para] +mali_used = 1 +mali_clkdiv = 1 + +;------------------------------------------------------------------------------- +;Ethernet MAC configuration +;------------------------------------------------------------------------------- +[emac_para] +emac_used = 1 +emac_rxd3 = port:PA00<2> +emac_rxd2 = port:PA01<2> +emac_rxd1 = port:PA02<2> +emac_rxd0 = port:PA03<2> +emac_txd3 = port:PA04<2> +emac_txd2 = port:PA05<2> +emac_txd1 = port:PA06<2> +emac_txd0 = port:PA07<2> +emac_rxclk = port:PA08<2> +emac_rxerr = port:PA09<2> +emac_rxdV = port:PA10<2> +emac_mdc = port:PA11<2> +emac_mdio = port:PA12<2> +emac_txen = port:PA13<2> +emac_txclk = port:PA14<2> +emac_crs = port:PA15<2> +emac_col = port:PA16<2> +emac_reset = port:PA17<1> + + +;------------------------------------------------------------- +; GMAC configuration +;--------------------------------------------------------- +[gmac_para] +gmac_used = 1 +gmac_rxd3 = port:PA00<5><3> +gmac_rxd2 = port:PA01<5><3> +gmac_rxd1 = port:PA02<5><3> +gmac_rxd0 = port:PA03<5><3> +gmac_txd3 = port:PA04<5><3> +gmac_txd2 = port:PA05<5><3> +gmac_txd1 = port:PA06<5><3> +gmac_txd0 = port:PA07<5><3> +gmac_rxclk = port:PA08<5><3> +gmac_rxerr = port:PA09<0><3> +gmac_rxctl = port:PA10<5><3> +gmac_mdc = port:PA11<5><3> +gmac_mdio = port:PA12<5><3> +gmac_txctl = port:PA13<5><3> +gmac_txclk = port:PA14<0><3> +gmac_txck = port:PA15<5><3> +gmac_clkin = port:PA16<5><3> +gmac_txerr = port:PA17<0><3> + +;------------------------------------------------------------------------------- +;i2c configuration +;------------------------------------------------------------------------------- +[twi0_para] +twi0_used = 1 +twi0_scl = port:PB0<2> +twi0_sda = port:PB1<2> + +[twi1_para] +twi1_used = 1 +twi1_scl = port:PB18<2> +twi1_sda = port:PB19<2> + +[twi2_para] +twi2_used = 1 +twi2_scl = port:PB20<2> +twi2_sda = port:PB21<2> + +;------------------------------------------------------------------------------- +;uart configuration +;uart_type --- 2 (2 wire), 4 (4 wire), 8 (8 wire, full function) +;------------------------------------------------------------------------------- +[uart_para0] +uart_used = 1 +uart_port = 0 +uart_type = 2 +uart_tx = port:PB22<2><1> +uart_rx = port:PB23<2><1> + +[uart_para1] +uart_used = 0 +uart_port = 1 +uart_type = 8 +uart_tx = port:PA10<4><1> +uart_rx = port:PA11<4><1> +uart_rts = port:PA12<4><1> +uart_cts = port:PA13<4><1> +uart_dtr = port:PA14<4><1> +uart_dsr = port:PA15<4><1> +uart_dcd = port:PA16<4><1> +uart_ring = port:PA17<4><1> + +[uart_para2] +uart_used = 1 +uart_port = 2 +uart_type = 4 +uart_tx = port:PI18<0><2> +uart_rx = port:PI19<1><2> +uart_rts = port:PI16<3><1> +uart_cts = port:PI17<3><1> + +[uart_para3] +uart_used = 0 +uart_port = 3 +uart_type = 4 +uart_tx = port:PH00<4><1> +uart_rx = port:PH01<4><1> +uart_rts = port:PH02<4><1> +uart_cts = port:PH03<4><1> + +[uart_para4] +uart_used = 0 +uart_port = 4 +uart_type = 2 +uart_tx = port:PH04<4><1> +uart_rx = port:PH05<4><1> + +[uart_para5] +uart_used = 0 +uart_port = 5 +uart_type = 2 +uart_tx = port:PH06<4><1> +uart_rx = port:PH07<4><1> + +[uart_para6] +uart_used = 0 +uart_port = 6 +uart_type = 2 +uart_tx = port:PA12<3><1> +uart_rx = port:PA13<3><1> + +[uart_para7] +uart_used = 0 +uart_port = 7 +uart_type = 2 +uart_tx = port:PA14<3><1> +uart_rx = port:PA15<3><1> + +;------------------------------------------------------------------------------- +;spi configuration +;------------------------------------------------------------------------------- +[spi0_para] +spi_used = 1 +spi_cs_bitmap = 1 +spi_cs0 = port:PI10<0><2> +spi_cs1 = port:PI14<2> +spi_sclk = port:PI11<0><2> +spi_mosi = port:PI12<0><2> +spi_miso = port:PI13<0><2> + +[spi1_para] +spi_used = 0 +spi_cs_bitmap = 1 +spi_cs0 = port:PA00<3> +spi_cs1 = port:PA04<3> +spi_sclk = port:PA01<3> +spi_mosi = port:PA02<3> +spi_miso = port:PA03<3> + +[spi2_para] +spi_used = 1 +spi_cs_bitmap = 1 +spi_cs0 = port:PC19<0><2> +spi_cs1 = port:PB13<2> +spi_sclk = port:PC20<0><2> +spi_mosi = port:PC21<0><2> +spi_miso = port:PC22<0><2> + +[spi3_para] +spi_used = 0 +spi_cs_bitmap = 1 +spi_cs0 = port:PA05<3> +spi_cs1 = port:PA09<3> +spi_sclk = port:PA06<3> +spi_mosi = port:PA07<3> +spi_miso = port:PA08<3> + +[spi_devices] +spi_dev_num = 2 + +[spi_board0] +modalias = "spidev" +max_speed_hz = 12000000 +bus_num = 0 +chip_select = 0 +mode = 3 +full_duplex = 0 +manual_cs = 0 + +[spi_board1] +modalias = "spidev" +max_speed_hz = 12000000 +bus_num = 2 +chip_select = 0 +mode = 0 +full_duplex = 0 +manual_cs = 0 + +;---------------------------------------------------------------------------------- +;resistance tp configuration +;---------------------------------------------------------------------------------- +[rtp_para] +rtp_used = 1 +rtp_screen_size = 5 +rtp_regidity_level = 5 +rtp_press_threshold_enable = 0 +rtp_press_threshold = 0x1f40 +rtp_sensitive_level = 0xf +rtp_exchange_x_y_flag = 0 +;------------------------------------------------------------------------------- +;capacitor tp configuration +;external int function +;wakeup output function +;notice: +; tp_int_port & tp_io_port use the same port +;------------------------------------------------------------------------------- +[ctp_para] +ctp_used = 1 +ctp_twi_id = 2 +ctp_twi_name = "gslX680" +ctp_screen_max_x = 1024 +ctp_screen_max_y = 600 +ctp_revert_x_flag = 0 +ctp_revert_y_flag = 0 +ctp_exchange_x_y_flag = 0 + +ctp_int_port = port:PH10<6> +ctp_wakeup = + +;------------------------------------------------------------------------------- +;touch key configuration +;------------------------------------------------------------------------------- +[tkey_para] +tkey_used = 0 +tkey_twi_id = 2 +tkey_twi_addr = 0x62 +tkey_int = port:PI13<6> + +;------------------------------------------------------------------------------- +;motor configuration +;------------------------------------------------------------------------------- +[motor_para] +motor_used = 0 +motor_shake = port:PB03<1><1> + +;------------------------------------------------------------------------------- +;nand flash configuration +;------------------------------------------------------------------------------- +[nand_para] +nand_used = 1 +nand_we = port:PC00<2> +nand_ale = port:PC01<2> +nand_cle = port:PC02<2> +nand_ce1 = port:PC03<2> +nand_ce0 = port:PC04<2> +nand_nre = port:PC05<2> +nand_rb0 = port:PC06<2> +nand_rb1 = port:PC07<2> +nand_d0 = port:PC08<2> +nand_d1 = port:PC09<2> +nand_d2 = port:PC10<2> +nand_d3 = port:PC11<2> +nand_d4 = port:PC12<2> +nand_d5 = port:PC13<2> +nand_d6 = port:PC14<2> +nand_d7 = port:PC15<2> +nand_wp = port:PC16<2> +nand_ce2 = port:PC17<2> +nand_ce3 = port:PC18<2> +nand_ce4 = +nand_ce5 = +nand_ce6 = +nand_ce7 = +nand_spi = port:PC23<3> +nand_ndqs = port:PC24<2> +good_block_ratio = 0 + +;------------------------------------------------------------------------------- +;disp init configuration +; +;disp_mode (0:screen0 1:screen1 2:two_diff_screen_diff_contents +; 3:two_same_screen_diff_contets 4:two_diff_screen_same_contents) +;screenx_output_type (0:none; 1:lcd; 2:tv; 3:hdmi; 4:vga) +;screenx_output_mode (used for tv/hdmi output, 0:480i 1:576i 2:480p 3:576p 4:720p50 5:720p60 6:1080i50 7:1080i60 8:1080p24 9:1080p50 10:1080p60 11:pal 14:ntsc) +;screenx_output_mode (used for vga output, 0:1680*1050 1:1440*900 2:1360*768 3:1280*1024 4:1024*768 5:800*600 6:640*480 10:1920*1080 11:1280*720) +;fbx format (4:RGB655 5:RGB565 6:RGB556 7:ARGB1555 8:RGBA5551 9:RGB888 10:ARGB8888 12:ARGB4444) +;fbx pixel sequence (0:ARGB 1:BGRA 2:ABGR 3:RGBA) --- 0 for linux, 2 for android +;lcd0_bright (lcd0 init bright,the range:[0,256],default:197 +;lcd1_bright (lcd1 init bright,the range:[0,256],default:197 +;------------------------------------------------------------------------------- + +[boot_disp] +output_type = 1 +output_mode = 4 + +[disp_init] +disp_init_enable = 1 +disp_mode = 1 + +screen0_output_type = 1 +screen0_output_mode = 4 + +screen1_output_type = 1 +screen1_output_mode = 4 + +fb0_framebuffer_num = 2 +fb0_format = 10 +fb0_pixel_sequence = 0 +fb0_scaler_mode_enable = 1 +fb0_width = 0 +fb0_height = 0 + +fb1_framebuffer_num = 2 +fb1_format = 10 +fb1_pixel_sequence = 0 +fb1_scaler_mode_enable = 0 +fb1_width = 0 +fb1_height = 0 + +lcd0_backlight = 197 +lcd1_backlight = 197 + +lcd0_bright = 50 +lcd0_contrast = 50 +lcd0_saturation = 57 +lcd0_hue = 50 + +lcd1_bright = 50 +lcd1_contrast = 50 +lcd1_saturation = 57 +lcd1_hue = 50 + +;------------------------------------------------------------------------------- +;lcd0 configuration + +;lcd_dclk_freq: in MHZ unit +;lcd_pwm_freq: in HZ unit +;lcd_if: 0:hv(sync+de); 1:8080; 2:ttl; 3:lvds; 4:hv2dsi +;lcd_width: width of lcd in mm +;lcd_height: height of lcd in mm +;lcd_hbp: hsync back porch +;lcd_ht: hsync total cycle +;lcd_vbp: vsync back porch +;lcd_vt: vysnc total cycle *2 +;lcd_hv_if: 0:hv parallel 1:hv serial +;lcd_hv_smode: 0:RGB888 1:CCIR656 +;lcd_hv_s888_if serial RGB format +;lcd_hv_syuv_if: serial YUV format +;lcd_hspw: hsync plus width +;lcd_vspw: vysnc plus width +;lcd_lvds_ch: 0:single channel; 1:dual channel +;lcd_lvds_mode: 0:NS mode; 1:JEIDA mode +;lcd_lvds_bitwidth: 0:24bit; 1:18bit +;lcd_lvds_io_cross: 0:normal; 1:pn cross +;lcd_cpu_if: 0:18bit; 1:16bit mode0; 2:16bit mode1; 3:16bit mode2; 4:16bit mode3; 5:9bit; 6:8bit 256K; 7:8bit 65K +;lcd_frm: 0:disable; 1:enable rgb666 dither; 2:enable rgb656 dither + +;lcd_gpio_0: SCL +;lcd_gpio_1 SDA +;------------------------------------------------------------------------------- +[lcd0_para] +lcd_used = 0 + +lcd_x = 1024 +lcd_y = 600 +lcd_width = 0 +lcd_height = 0 +lcd_dclk_freq = 51 +lcd_pwm_not_used = 1 +lcd_pwm_ch = 0 +lcd_pwm_freq = 10000 +lcd_pwm_pol = 0 +lcd_if = 3 +lcd_hbp = 310 +lcd_ht = 1340 +lcd_vbp = 30 +lcd_vt = 1268 +lcd_vspw = 0 +lcd_hspw = 0 +lcd_hv_if = 0 +lcd_hv_smode = 0 +lcd_hv_s888_if = 0 +lcd_hv_syuv_if = 0 +lcd_lvds_ch = 0 +lcd_lvds_mode = 0 +lcd_lvds_bitwidth = 0 +lcd_lvds_io_cross = 0 +lcd_cpu_if = 0 +lcd_frm = 0 +lcd_io_cfg0 = 0x10000000 +lcd_gamma_correction_en = 0 +lcd_gamma_tbl_0 = 0x00000000 +lcd_gamma_tbl_1 = 0x00010101 +lcd_gamma_tbl_255 = 0x00ffffff + +lcd_bl_en_used = 0 +lcd_bl_en = port:PH07<1><0><1> + +lcd_power_used = 0 +lcd_power = port:PH08<1><0><1> + +lcd_pwm_used = 0 +lcd_pwm = port:PB02<2><0> + +lcdd0 = port:PD00<3> +lcdd1 = port:PD01<3> +lcdd2 = port:PD02<3> +lcdd3 = port:PD03<3> +lcdd4 = port:PD04<3> +lcdd5 = port:PD05<3> +lcdd6 = port:PD06<3> +lcdd7 = port:PD07<3> +lcdd8 = port:PD08<3> +lcdd9 = port:PD09<3> + +;---------------------------------------------------------------------------------- +;lcd1 configuration + +;lcd_dclk_freq: in MHZ unit +;lcd_pwm_freq: in HZ unit +;lcd_if: 0:hv(sync+de); 1:8080; 2:ttl; 3:lvds +;lcd_hbp: hsync back porch +;lcd_ht: hsync total cycle +;lcd_vbp: vsync back porch +;lcd_vt: vysnc total cycle *2 +;lcd_hv_if: 0:hv parallel 1:hv serial +;lcd_hv_smode: 0:RGB888 1:CCIR656 +;lcd_hv_s888_if serial RGB format +;lcd_hv_syuv_if: serial YUV format +;lcd_hspw: hsync plus width +;lcd_vspw: vysnc plus width +;lcd_lvds_ch: 0:single channel; 1:dual channel +;lcd_lvds_mode: 0:NS mode; 1:JEIDA mode +;lcd_lvds_bitwidth: 0:24bit; 1:18bit +;lcd_lvds_io_cross: 0:normal; 1:pn cross +;lcd_cpu_if: 0:18bit; 1:16bit mode0; 2:16bit mode1; 3:16bit mode2; 4:16bit mode3; 5:9bit; 6:8bit 256K; 7:8bit 65K +;lcd_frm: 0:disable; 1:enable rgb666 dither; 2:enable rgb656 dither + +;lcd_gpio_0: SCL +;lcd_gpio_1 SDA +;---------------------------------------------------------------------------------- +[lcd1_para] +lcd_used = 1 + +lcd_x = 1024 +lcd_y = 600 +lcd_width = 0 +lcd_height = 0 +lcd_dclk_freq = 51 +lcd_pwm_not_used = 0 +lcd_pwm_ch = 0 +lcd_pwm_freq = 10000 +lcd_pwm_pol = 0 +lcd_if = 3 +lcd_hbp = 310 +lcd_ht = 1340 +lcd_vbp = 30 +lcd_vt = 1268 +lcd_vspw = 0 +lcd_hspw = 0 +lcd_hv_if = 0 +lcd_hv_smode = 0 +lcd_hv_s888_if = 0 +lcd_hv_syuv_if = 0 +lcd_lvds_ch = 0 +lcd_lvds_mode = 0 +lcd_lvds_bitwidth = 0 +lcd_lvds_io_cross = 0 +lcd_cpu_if = 0 +lcd_frm = 0 +lcd_io_cfg0 = 0 +lcd_gamma_correction_en = 0 +lcd_gamma_tbl_0 = 0x00000000 +lcd_gamma_tbl_1 = 0x00010101 +lcd_gamma_tbl_255 = 0x00ffffff + +lcd_bl_en_used = 1 +lcd_bl_en = port:PH07<1><1> + +lcd_power_used = 1 +lcd_power = port:PH08<1><1> + +lcd_pwm_used = 1 +lcd_pwm = port:PH06<1><0> + +lcd_gpio_0 = +lcd_gpio_1 = +lcd_gpio_2 = +lcd_gpio_3 = + +lcdd10 = port:PD10<3> +lcdd11 = port:PD11<3> +lcdd12 = port:PD12<3> +lcdd13 = port:PD13<3> +lcdd14 = port:PD14<3> +lcdd15 = port:PD15<3> +lcdd16 = port:PD16<3> +lcdd17 = port:PD17<3> +lcdd18 = port:PD18<3> +lcdd19 = port:PD19<3> + +;------------------------------------------------------------------------------- +;tv out dac configuration +;dacx_src: 0:composite; 1:luma; 2:chroma; 4:Y; 5:Pb; 6: Pr; 7:none +;------------------------------------------------------------------------------- +[tv_out_dac_para] +dac_used = 1 +dac0_src = 4 +dac1_src = 5 +dac2_src = 6 +dac3_src = 0 + +;---------------------------------------------------------------------------------- +;hdmi configuration +;---------------------------------------------------------------------------------- +[hdmi_para] +hdmi_used = 1 +hdcp_enable = 0 + +[i2s2_para] +i2s_channel = 2 +i2s_master = 4 +i2s_select = 1 +audio_format = 1 +signal_inversion = 1 +over_sample_rate = 256 +sample_resolution = 16 +word_select_size = 32 +pcm_sync_period = 256 +msb_lsb_first = 0 +sign_extend = 0 +slot_index = 0 +slot_width = 16 +frame_width = 1 +tx_data_mode = 0 +rx_data_mode = 0 +;i2s_mclk = port:PB05<2><1> +;i2s_bclk = port:PB06<2><1> +;i2s_lrclk = port:PB07<2><1> +;i2s_dout0 = port:PB08<2><1> +;i2s_dout1 = +;i2s_dout2 = +;i2s_dout3 = +;i2s_din = port:PB12<2><1> + + +[camera_list_para] +camera_list_para_used = 1 +ov7670 = 0 +gc0308 = 1 +gt2005 = 0 +hi704 = 0 +sp0838 = 0 +mt9m112 = 0 +mt9m113 = 0 +ov2655 = 0 +hi253 = 0 +gc0307 = 0 +mt9d112 = 0 +ov5640 = 1 +gc2015 = 0 +ov2643 = 0 +gc0329 = 0 +gc0309 = 0 +tvp5150 = 0 +s5k4ec = 0 +ov5650_mv9335 = 0 +siv121d = 0 + +;-------------------------------------------------------------------------------- +;csi gpio configuration +;csi_if: 0:hv_8bit 1:hv_16bit 2:hv_24bit 3:bt656 1ch 4:bt656 2ch 5:bt656 4ch +;csi_mode: 0:sample one csi to one buffer 1:sample two csi to one buffer +;csi_dev_qty: The quantity of devices linked to csi interface +;csi_vflip: flip in vertical direction 0:disable 1:enable +;csi_hflip: flip in horizontal direction 0:disable 1:enable +;csi_stby_mode: 0:not shut down power at standby 1:shut down power at standby +;csi_iovdd: camera module io power , pmu power supply +;csi_avdd: camera module analog power , pmu power supply +;csi_dvdd: camera module core power , pmu power supply +;pmu_ldo3: fill "axp20_pll" +;pmu_ldo4: fill "axp20_hdmi" +;fill "" when not using any pmu power supply +;csi_flash_pol: the active polority of the flash light IO 0:low active 1:high active +;-------------------------------------------------------------------------------- + +[csi0_para] +csi_used = 1 + +csi_dev_qty = 1 +csi_stby_mode = 0 +csi_mname = "gc2035" +csi_if = 0 +csi_iovdd = "" +csi_avdd = "" +csi_dvdd = "" +csi_vol_iovdd = +csi_vol_dvdd = +csi_vol_avdd = +csi_vflip = 0 +csi_hflip = 0 +csi_flash_pol = 0 +csi_facing = 0 + +csi_twi_id = 1 +csi_twi_addr = 0x78 +csi_pck = port:PE00<3> +csi_ck = port:PE01<3> +csi_hsync = port:PE02<3> +csi_vsync = port:PE03<3> +csi_d0 = port:PE04<3> +csi_d1 = port:PE05<3> +csi_d2 = port:PE06<3> +csi_d3 = port:PE07<3> +csi_d4 = port:PE08<3> +csi_d5 = port:PE09<3> +csi_d6 = port:PE10<3> +csi_d7 = port:PE11<3> +csi_reset = port:PH27<1><1> +csi_power_en = port:PH26<1><0> +csi_stby = + +[csi1_para] +csi_used = 0 + +csi_dev_qty = 1 +csi_stby_mode = 0 +csi_mname = "gc0308" +csi_if = 0 +csi_iovdd = "" +csi_avdd = "" +csi_dvdd = "" +csi_vol_iovdd = +csi_vol_dvdd = +csi_vol_avdd = +csi_vflip = 0 +csi_hflip = 0 +csi_flash_pol = 0 +csi_facing = 1 + +csi_twi_id = 1 +csi_twi_addr = 0x42 +csi_pck = port:PG00<3> +csi_ck = port:PG01<3> +csi_hsync = port:PG02<3> +csi_vsync = port:PG03<3> +csi_d0 = port:PG04<3> +csi_d1 = port:PG05<3> +csi_d2 = port:PG06<3> +csi_d3 = port:PG07<3> +csi_d4 = port:PG08<3> +csi_d5 = port:PG09<3> +csi_d6 = port:PG10<3> +csi_d7 = port:PG11<3> +csi_reset = port:PH14<1><0> +csi_power_en = +csi_stby = port:PH17<1><0> + +;------------------------------------------------------------------------------- +;tv configuration +; +;------------------------------------------------------------------------------- +[tvout_para] +tvout_used = 1 +tvout_channel_num = 1 + +[tvin_para] +tvin_used = 0 +tvin_channel_num = 4 + + +;------------------------------------------------------------------------------- +;sata configuration +; +;------------------------------------------------------------------------------- +[sata_para] +sata_used = 1 +sata_power_en = port:PH02<1><1> + + +;------------------------------------------------------------------------------- +; SDMMC PINS MAPPING +; ------------------------------------------------------------------------------ +; Config Guide +; sdc_used: 1-enable card, 0-disable card +; sdc_detmode: card detect mode +; 1-detect card by gpio polling +; 2-detect card by gpio irq(must use IO with irq function) +; 3-no detect, always in for boot card +; 4-manually insert and remove by /proc/driver/sunxi-mmc.x/insert +; sdc_buswidth: card bus width, 1-1bit, 4-4bit, 8-8bit +; sdc_use_wp: 1-with write protect IO, 0-no write protect IO +; sdc_isio: for sdio card +; sdc_regulator: power control. +; other: GPIO Mapping configuration +; ------------------------------------------------------------------------------ +; Note: +; 1 if detmode=2, sdc_det's config=6 +; else if detmode=1, sdc_det's config=0 +; else sdc_det IO is not necessary +; 2 if the customer wants to support UHS-I and HS200 features, he must provide +; an independent power supply for the card. This is only used in platforms +; that supports SD3.0 cards and eMMC4.4+ flashes +;------------------------------------------------------------------------------- +[mmc0_para] +sdc_used = 1 +sdc_detmode = 1 +sdc_buswidth = 4 +sdc_clk = port:PF02<2><1><2> +sdc_cmd = port:PF03<2><1><2> +sdc_d0 = port:PF01<2><1><2> +sdc_d1 = port:PF00<2><1><2> +sdc_d2 = port:PF05<2><1><2> +sdc_d3 = port:PF04<2><1><2> +sdc_det = port:PH1<0><1> +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 0 +sdc_regulator = "none" + +[mmc1_para] +sdc_used = 0 +sdc_detmode = 4 +sdc_buswidth = 4 +sdc_clk = port:PG00<2><1><2> +sdc_cmd = port:PG01<2><1><2> +sdc_d0 = port:PG02<2><1><2> +sdc_d1 = port:PG03<2><1><2> +sdc_d2 = port:PG04<2><1><2> +sdc_d3 = port:PG05<2><1><2> +sdc_det = +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 0 +sdc_regulator = "none" + +[mmc2_para] +sdc_used = 0 +sdc_detmode = 3 +sdc_buswidth = 4 +sdc_cmd = port:PC06<3><1><2> +sdc_clk = port:PC07<3><1><2> +sdc_d0 = port:PC08<3><1><2> +sdc_d1 = port:PC09<3><1><2> +sdc_d2 = port:PC10<3><1><2> +sdc_d3 = port:PC11<3><1><2> +sdc_det = +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 0 +sdc_regulator = "none" + +[mmc3_para] +sdc_used = 0 +sdc_detmode = 4 +sdc_buswidth = 4 +sdc_cmd = port:PI04<2><1><2> +sdc_clk = port:PI05<2><1><2> +sdc_d0 = port:PI06<2><1><2> +sdc_d1 = port:PI07<2><1><2> +sdc_d2 = port:PI08<2><1><2> +sdc_d3 = port:PI09<2><1><2> +sdc_det = +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 1 +sdc_regulator = "none" + +; ------------------------------------------------------------------------------ +; memory stick configuration +;------------------------------------------------------------------------------- +[ms_para] +ms_used = 0 +ms_bs = port:PH06<5> +ms_clk = port:PH07<5> +ms_d0 = port:PH08<5> +ms_d1 = port:PH09<5> +ms_d2 = port:PH10<5> +ms_d3 = port:PH11<5> +ms_det = + +; ------------------------------------------------------------------------------ +; sim card configuration +;------------------------------------------------------------------------------- +[smc_para] +smc_used = 0 +smc_rst = port:PH13<5> +smc_vppen = port:PH14<5> +smc_vppp = port:PH15<5> +smc_det = port:PH16<5> +smc_vccen = port:PH17<5> +smc_sck = port:PH18<5> +smc_sda = port:PH19<5> + +;------------------------------------------------------------------------------- +;ps2 configuration +;------------------------------------------------------------------------------- +[ps2_0_para] +ps2_used = 0 +ps2_scl = port:PI20<2><1> +ps2_sda = port:PI21<2><1> + +[ps2_1_para] +ps2_used = 0 +ps2_scl = port:PI14<3><1> +ps2_sda = port:PI15<3><1> + +;------------------------------------------------------------------------------- +;can bus configuration +;------------------------------------------------------------------------------- +[can_para] +can_used = 0 +can_tx = port:PA16<3> +can_rx = port:PA17<3> + +;------------------------------------------------------------------------------- +;key matrix +;------------------------------------------------------------------------------- +[keypad_para] +kp_used = 0 +kp_in_size = 8 +kp_out_size = 8 +kp_in0 = port:PH08<4><1> +kp_in1 = port:PH09<4><1> +kp_in2 = port:PH10<4><1> +kp_in3 = port:PH11<4><1> +kp_in4 = port:PH14<4><1> +kp_in5 = port:PH15<4><1> +kp_in6 = port:PH16<4><1> +kp_in7 = port:PH17<4><1> +kp_out0 = port:PH18<4><1> +kp_out1 = port:PH19<4><1> +kp_out2 = port:PH22<4><1> +kp_out3 = port:PH23<4><1> +kp_out4 = port:PH24<4><1> +kp_out5 = port:PH25<4><1> +kp_out6 = port:PH26<4><1> +kp_out7 = port:PH27<4><1> + + +;------------------------------------------------------------------------------- +;[usbc0]：控制器0的配置。 +;usb_used：USB使能标志。置1，表示系统中USB模块可用,置0,则表示系统USB禁用。 +;usb_port_type：USB端口的使用情况。 0：device only;1：host only;2：OTG +;usb_detect_type：USB端口的检查方式。0：不做检测;1：vbus/id检查;2：id/dpdm检查 +;usb_id_gpio：USB ID pin脚配置。具体请参考gpio配置说明。 +;usb_det_vbus_gpio：USB DET_VBUS pin脚配置。具体请参考gpio配置说明。 +;usb_drv_vbus_gpio：USB DRY_VBUS pin脚配置。具体请参考gpio配置说明。 +;usb_det_vbus_gpio: "axp_ctrl",表示axp 提供 +;usb_restrict_gpio usb限流控制pin +;usb_restric_flag: usb限流标置 +;------------------------------------------------------------------------------- +;------------------------------------------------------------------------------- +;--- USB0控制标志 +;------------------------------------------------------------------------------- +[usbc0] +usb_used = 1 +usb_port_type = 0 +usb_detect_type = 0 +usb_id_gpio = port:PH04<0><1> +usb_det_vbus_gpio = "axp_ctrl" +usb_drv_vbus_gpio = port:PB09<1><0><0> +;usb_restrict_gpio = port:PH00<1><0><0> +usb_host_init_state = 0 +usb_restric_flag = 0 +usb_restric_voltage = 3550000 +usb_restric_capacity= 5 + +;------------------------------------------------------------------------------- +;--- USB1控制标志 +;------------------------------------------------------------------------------ +[usbc1] +usb_used = 1 +usb_port_type = 1 +usb_detect_type = 0 +usb_drv_vbus_gpio = port:PH11<1><0><0> +usb_restrict_gpio = +usb_host_init_state = 1 +usb_restric_flag = 0 + +;------------------------------------------------------------------------------ +;--- USB2控制标志 +;------------------------------------------------------------------------------ +[usbc2] +usb_used = 1 +usb_port_type = 1 +usb_detect_type = 0 +usb_drv_vbus_gpio = port:PH03<1><0><0> +usb_restrict_gpio = + +usb_host_init_state = 1 +usb_restric_flag = 0 + +;-------------------------------- +;--- USB Device +;-------------------------------- +[usb_feature] +vendor_id = 0x18D1 +mass_storage_id = 0x0001 +adb_id = 0x0002 + +manufacturer_name = "USB Developer" +product_name = "Android" +serial_number = "20080411" + +[msc_feature] +vendor_name = "USB 2.0" +product_name = "USB Flash Driver" +release = 100 +luns = 1 + +;------------------------------------------------------------------------------- +; G sensor configuration +; gs_twi_id --- TWI ID for controlling Gsensor (0: TWI0, 1: TWI1, 2: TWI2) +;------------------------------------------------------------------------------- +[gsensor_para] +gsensor_used = 0 +gsensor_twi_id = 1 +gsensor_int1 = +gsensor_int2 = + +;------------------------------------------------------------------------------- +; gps gpio configuration +; gps_spi_id --- the index of SPI controller. 0: SPI0, 1: SPI1, 2: SPI2, 15: no SPI used +; gps_spi_cs_num --- the chip select number of SPI controller. 0: SPI CS0, 1: SPI CS1 +; gps_lradc --- the lradc number for GPS used. 0 and 1 is valid, set 2 if not use lradc +;------------------------------------------------------------------------------- +[gps_para] +gps_used = 0 +gps_spi_id = 2 +gps_spi_cs_num = 0 +gps_lradc = 1 +gps_clk = port:PI00<2> +gps_sign = port:PI01<2> +gps_mag = port:PI02<2> +gps_vcc_en = port:PC22<1><0> +gps_osc_en = port:PI14<1><0> +gps_rx_en = port:PI15<1><0> + +;-------------------------------------------------------------------------------- +;wifi configuration +;wifi_sdc_id --- 0- SDC0, 1- SDC1, 2- SDC2, 3- SDC3 +;wifi_usbc_id --- 0- USB0, 1- USB1, 2- USB2 +;wifi_usbc_type -- 1- EHCI(speed 2.0), 2- OHCI(speed 1.0) +;wifi_mod_sel --- 0- none, 1- bcm40181, 2- bcm40183(wifi+bt), +; 3 - rtl8723as(wifi+bt), 4- rtl8189es(SM89E00), +; 5 - rtl8192cu, 6 - rtl8188eu, 7 - ap6210 +;-------------------------------------------------------------------------------- +[wifi_para] +wifi_used = 1 +wifi_sdc_id = 3 +wifi_usbc_id = 2 +wifi_usbc_type = 1 +wifi_mod_sel = 7 +wifi_power = "" + +; 1 - bcm40181 sdio wifi gpio config +;bcm40181_shdn = port:PH09<1><0> +;bcm40181_host_wake = port:PH10<0><0> + +; 2 - bcm40183 sdio wifi gpio config +;bcm40183_wl_regon = port:PH09<1><0> +;bcm40183_wl_host_wake = port:PH10<0><0> +;bcm40183_bt_rst = port:PB05<1><0> +;bcm40183_bt_regon = port:PB05<1><0> +;bcm40183_bt_wake = port:PI20<1><0> +;bcm40183_bt_host_wake = port:PI21<0><0> + +; 3 - rtl8723as sdio wifi + bt gpio config +rtk_rtl8723as_wl_dis = port:PH09<1><0> +rtk_rtl8723as_bt_dis = port:PB05<1><0> +rtk_rtl8723as_wl_host_wake = port:PH10<0><0> +rtk_rtl8723as_bt_host_wake = port:PI21<0><0> + +; 4 - rtl8189es sdio wifi gpio config +;rtl8189es_shdn = port:PH09<1><0> +;rtl8189es_wakeup = port:PH10<1><1> + +; 5 - rtl8192cu usb wifi + +; 6 - rtl8188eu usb wifi + +; 7 - ap6210 sdio wifi + bt gpio config +ap6xxx_wl_regon = port:PH09<1><0> +ap6xxx_wl_host_wake = port:PH10<0><0> +ap6xxx_bt_regon = port:PB05<1><0> +ap6xxx_bt_wake = port:PI20<1><0> +ap6xxx_bt_host_wake = port:PI21<0><0> + + +[usb_wifi_para] +usb_wifi_used = 0 +usb_wifi_usbc_num = 2 + +;------------------------------------------------------------------------------- +;3G configuration +;------------------------------------------------------------------------------- +[3g_para] +3g_used = 0 +3g_usbc_num = 2 +3g_uart_num = 0 +3g_pwr = +3g_wakeup = +3g_int = + +;------------------------------------------------------------------------------- +;gyroscope +;------------------------------------------------------------------------------- +[gy_para] +gy_used = 0 +gy_twi_id = 1 +gy_twi_addr = 0x00 +gy_int1 = port:PH18<6><1> +gy_int2 = port:PH19<6><1> + +;------------------------------------------------------------------------------- +;light sensor +;------------------------------------------------------------------------------- +[ls_para] +ls_used = 0 +ls_twi_id = 1 +ls_twi_addr = 0x00 +ls_int = port:PH20<6><1> + +;------------------------------------------------------------------------------- +;compass +;------------------------------------------------------------------------------- +[compass_para] +compass_used = 0 +compass_twi_id = 1 +compass_twi_addr = 0x00 +compass_int = port:PI13<6><1> + +;------------------------------------------------------------------------------- +;blue tooth +;bt_used ---- blue tooth used (0- no used, 1- used) +;bt_uard_id ---- uart index +;------------------------------------------------------------------------------- +[bt_para] +bt_used = 0 +bt_uart_id = 2 +bt_wakeup = port:PI20<1> +bt_gpio = port:PI21<1> +bt_rst = port:PB05<1> + +;-------------------------------------------------------------------------------- +;i2s_master:1: SND_SOC_DAIFMT_CBM_CFM(codec clk & FRM master) use +; 2: SND_SOC_DAIFMT_CBS_CFM(codec clk slave & FRM master) not use +; 3: SND_SOC_DAIFMT_CBM_CFS(codec clk master & frame slave) not use +; 4: SND_SOC_DAIFMT_CBS_CFS(codec clk & FRM slave) use +;i2s_select:0 is pcm.1 is i2s +;audio_format: 1:SND_SOC_DAIFMT_I2S(standard i2s format). use +; 2:SND_SOC_DAIFMT_RIGHT_J(right justfied format). +; 3:SND_SOC_DAIFMT_LEFT_J(left justfied format) +; 4:SND_SOC_DAIFMT_DSP_A(pcm. MSB is available on 2nd BCLK rising edge after LRC rising edge). use +; 5:SND_SOC_DAIFMT_DSP_B(pcm. MSB is available on 1nd BCLK rising edge after LRC rising edge) +;signal_inversion:1:SND_SOC_DAIFMT_NB_NF(normal bit clock + frame) use +; 2:SND_SOC_DAIFMT_NB_IF(normal BCLK + inv FRM) +; 3:SND_SOC_DAIFMT_IB_NF(invert BCLK + nor FRM) use +; 4:SND_SOC_DAIFMT_IB_IF(invert BCLK + FRM) +;over_sample_rate: support 128fs/192fs/256fs/384fs/512fs/768fs +;sample_resolution :16bits/20bits/24bits +;word_select_size :16bits/20bits/24bits/32bits +;pcm_sync_period :16/32/64/128/256 +;msb_lsb_first :0: msb first; 1: lsb first +;sign_extend :0: zero pending; 1: sign extend +;slot_index :slot index: 0: the 1st slot - 3: the 4th slot +;slot_width :8 bit width / 16 bit width +;frame_width :0: long frame = 2 clock width; 1: short frame +;tx_data_mode :0: 16bit linear PCM; 1: 8bit linear PCM; 2: 8bit u-law; 3: 8bit a-law +;rx_data_mode :0: 16bit linear PCM; 1: 8bit linear PCM; 2: 8bit u-law; 3: 8bit a-law +;-------------------------------------------------------------------------------- +[i2s_para] +i2s_used = 0 +i2s_channel = 2 +i2s_master = 4 +i2s_select = 1 +audio_format = 1 +signal_inversion = 1 +over_sample_rate = 256 +sample_resolution = 16 +word_select_size = 32 +pcm_sync_period = 256 +msb_lsb_first = 0 +sign_extend = 0 +slot_index = 0 +slot_width = 16 +frame_width = 1 +tx_data_mode = 0 +rx_data_mode = 0 +i2s_mclk = port:PB05<2><1> +i2s_bclk = port:PB06<2><1> +i2s_lrclk = port:PB07<2><1> +i2s_dout0 = port:PB08<2><1> +i2s_dout1 = +i2s_dout2 = +i2s_dout3 = +i2s_din = port:PB12<2><1> + + +;-------------------------------------------------------------------------------- +;pcm_master:1: SND_SOC_DAIFMT_CBM_CFM(codec clk & FRM master) use +; 2: SND_SOC_DAIFMT_CBS_CFM(codec clk slave & FRM master) not use +; 3: SND_SOC_DAIFMT_CBM_CFS(codec clk master & frame slave) not use +; 4: SND_SOC_DAIFMT_CBS_CFS(codec clk & FRM slave) use +;pcm_select:1 is pcm.0 is i2s +;audio_format: 1:SND_SOC_DAIFMT_I2S(standard i2s format). use +; 2:SND_SOC_DAIFMT_RIGHT_J(right justfied format). +; 3:SND_SOC_DAIFMT_LEFT_J(left justfied format) +; 4:SND_SOC_DAIFMT_DSP_A(pcm. MSB is available on 2nd BCLK rising edge after LRC rising edge). use +; 5:SND_SOC_DAIFMT_DSP_B(pcm. MSB is available on 1nd BCLK rising edge after LRC rising edge) +;signal_inversion:1:SND_SOC_DAIFMT_NB_NF(normal bit clock + frame) use +; 2:SND_SOC_DAIFMT_NB_IF(normal BCLK + inv FRM) +; 3:SND_SOC_DAIFMT_IB_NF(invert BCLK + nor FRM) use +; 4:SND_SOC_DAIFMT_IB_IF(invert BCLK + FRM) +;over_sample_rate: support 128fs/192fs/256fs/384fs/512fs/768fs +;sample_resolution :16bits/20bits/24bits +;word_select_size :16bits/20bits/24bits/32bits +;pcm_sync_period :16/32/64/128/256 +;msb_lsb_first :0: msb first; 1: lsb first +;sign_extend :0: zero pending; 1: sign extend +;slot_index :slot index: 0: the 1st slot - 3: the 4th slot +;slot_width :8 bit width / 16 bit width +;frame_width :0: long frame = 2 clock width; 1: short frame +;tx_data_mode :0: 16bit linear PCM; 1: 8bit linear PCM; 2: 8bit u-law; 3: 8bit a-law +;rx_data_mode :0: 16bit linear PCM; 1: 8bit linear PCM; 2: 8bit u-law; 3: 8bit a-law +;-------------------------------------------------------------------------------- +[pcm_para] +pcm_used = 0 +pcm_channel = 2 +pcm_master = 4 +pcm_select = 1 +audio_format = 4 +signal_inversion = 1 +over_sample_rate = 256 +sample_resolution = 16 +word_select_size = 32 +pcm_sync_period = 256 +msb_lsb_first = 0 +sign_extend = 0 +slot_index = 0 +slot_width = 16 +frame_width = 1 +tx_data_mode = 0 +rx_data_mode = 0 +pcm_mclk = port:PA09<6><1> +pcm_bclk = port:PA14<6><1> +pcm_lrclk = port:PA15<6><1> +pcm_dout0 = port:PA16<6><1> +pcm_dout1 = +pcm_dout2 = +pcm_dout3 = +pcm_din = port:PA17<6><1> + +[spdif_para] +spdif_used = 0 +spdif_mclk = +spdif_dout = port:PB13<4><1> +spdif_din = + +[audio_para] +audio_used = 1 +audio_pa_ctrl = port:PH15<1><0> +capture_used = 1 + +[switch_para] +switch_used = 0 + +;------------------------------------------------------------------------------- +;ir --- infra remote configuration +;------------------------------------------------------------------------------- +[ir_para] +ir_used = 1 +ir0_rx = port:PB04<2> + + +;------------------------------------------------------------------------------- +;pmu_twi_addr ---slave address +;pmu_twi_id ---i2c bus number (0 TWI0, 1 TWI2, 2 TWI3) +;pmu_irq_id ---irq number (0 irq0,1 irq1,……) +;pmu_battery_rdc ---battery initial resistance,mΩ,根据实际电池内阻填写 +;pmu_battery_cap ---battery capability,mAh，根据实际电池容量填写 +;pmu_init_chgcur ---set initial charging current limite,mA，300/400/500/600/700/800/900/1000/1100/1200/1300/1400/1500/1600/1700/1800 +;pmu_suspend_chgcur ---set suspend charging current limite,mA，300/400/500/600/700/800/900/1000/1100/1200/1300/1400/1500/1600/1700/1800 +;pmu_resume_chgcur ---set resume charging current limite,mA，300/400/500/600/700/800/900/1000/1100/1200/1300/1400/1500/1600/1700/1800 +;pmu_shutdown_chgcur ---set shutdown charging current limite,mA，300/400/500/600/700/800/900/1000/1100/1200/1300/1400/1500/1600/1700/1800 +;pmu_init_chgvol ---set initial charing target voltage,mV,4100/4150/4200/4360 +;pmu_init_chgend_rate ---set initial charing end current rate,10/15 +;pmu_init_chg_enabled ---set initial charing enabled,0:关闭,1:打开 +;pmu_init_adc_freq ---set initial adc frequency,Hz,25/50/100/200 +;pmu_init_adc_freqc ---set initial coulomb adc coufrequency,Hz,25/50/100/200 +;pmu_init_chg_pretime ---set initial pre-charging time,min,40/50/60/70 +;pmu_init_chg_csttime ---set initial constance-charging time,min,360/480/600/720 +;pmu_bat_para1 ---battery indication at 3.1328V +;pmu_bat_para2 ---battery indication at 3.2736V +;pmu_bat_para3 ---battery indication at 3.4144V +;pmu_bat_para4 ---battery indication at 3.5552V +;pmu_bat_para5 ---battery indication at 3.6256V +;pmu_bat_para6 ---battery indication at 3.6608V +;pmu_bat_para7 ---battery indication at 3.6960V +;pmu_bat_para8 ---battery indication at 3.7312V +;pmu_bat_para9 ---battery indication at 3.7664V +;pmu_bat_para10 ---battery indication at 3.8016V +;pmu_bat_para11 ---battery indication at 3.8368V +;pmu_bat_para12 ---battery indication at 3.8720V +;pmu_bat_para13 ---battery indication at 3.9424V +;pmu_bat_para14 ---battery indication at 4.0128V +;pmu_bat_para15 ---battery indication at 4.0832V +;pmu_bat_para16 ---battery indication at 4.1536V +;pmu_usbvol ---set usb-ac limited voltage level,mV,4000/4100/4200/4300/4400/4500/4600/4700,0 - not limite +;pmu_usbcur ---set usb-ac limited voltage level,mA,100/500/900, 0 - not limite +;pmu_usbvol_pc ---set usb-pc limited voltage level,mV,4000/4100/4200/4300/4400/4500/4600/4700,0 - not limite +;pmu_usbcur_pc ---set usb-pc limited voltage level,mA,100/500/900, 0 - not limite +;pmu_pwroff_vol ---set protect voltage when system start up,mV,2600/2700/2800/2900/3000/3100/3200/3300 +;pmu_pwron_vol ---set protect voltage after system start up,mV,2600/2700/2800/2900/3000/3100/3200/3300 +;pmu_pekoff_time ---set pek off time,ms, 4000/6000/8000/10000 +;pmu_pekoff_en ---set pek off enable, 0:关闭,1:打开 +;pmu_peklong_time ---set pek pek long irq time,ms,1000/1500/2000/2500 +;pmu_pekon_time ---set pek on time,ms,128/1000/2000/3000 +;pmu_pwrok_time ---set pmu pwrok delay time,ms,8/64 +;pmu_pwrnoe_time ---set pmu n_oe power down delay time,ms,128/1000/2000/3000 +;pmu_intotp_en ---set pmu power down when overtempertur enable,0:关闭，1：打开 +;pmu_suspendpwroff_vol ---set pmu shutdown voltage when cpu is suspend and battery voltage is low +;pmu_batdeten ---set pmu battery detect enabled,0:关闭，1：打开 +;------------------------------------------------------------------------------- +[pmu_para] +pmu_used = 1 +pmu_twi_addr = 0x34 +pmu_twi_id = 0 +pmu_irq_id = 32 +pmu_battery_rdc = 100 +pmu_battery_cap = 3200 +pmu_init_chgcur = 300 +pmu_earlysuspend_chgcur = 600 +pmu_suspend_chgcur = 1000 +pmu_resume_chgcur = 300 +pmu_shutdown_chgcur = 1000 +pmu_init_chgvol = 4200 +pmu_init_chgend_rate = 15 +pmu_init_chg_enabled = 1 +pmu_init_adc_freq = 100 +pmu_init_adc_freqc = 100 +pmu_init_chg_pretime = 50 +pmu_init_chg_csttime = 720 + +pmu_bat_para1 = 0 +pmu_bat_para2 = 0 +pmu_bat_para3 = 0 +pmu_bat_para4 = 0 +pmu_bat_para5 = 5 +pmu_bat_para6 = 8 +pmu_bat_para7 = 11 +pmu_bat_para8 = 22 +pmu_bat_para9 = 33 +pmu_bat_para10 = 43 +pmu_bat_para11 = 50 +pmu_bat_para12 = 59 +pmu_bat_para13 = 71 +pmu_bat_para14 = 83 +pmu_bat_para15 = 92 +pmu_bat_para16 = 100 + +pmu_usbvol_limit = 1 +pmu_usbcur_limit = 0 +pmu_usbvol = 4000 +pmu_usbcur = 0 + +pmu_usbvol_pc = 4000 +pmu_usbcur_pc = 0 + +pmu_pwroff_vol = 3300 +pmu_pwron_vol = 2900 + +pmu_pekoff_time = 6000 +pmu_pekoff_en = 1 +pmu_peklong_time = 1500 +pmu_pekon_time = 1000 +pmu_pwrok_time = 64 +pmu_pwrnoe_time = 2000 +pmu_intotp_en = 1 + +pmu_used2 = 0 +pmu_adpdet = port:PH02<0> +pmu_init_chgcur2 = 400 +pmu_earlysuspend_chgcur2 = 600 +pmu_suspend_chgcur2 = 1200 +pmu_resume_chgcur2 = 400 +pmu_shutdown_chgcur2 = 1200 + +pmu_suspendpwroff_vol = 3500 + +pmu_batdeten = 0 + +[recovery_key] +key_min =4 +key_max =6 + +;---------------------------------------------------------------------------------- +; dvfs voltage-frequency table configuration +; +; max_freq: cpu maximum frequency, based on Hz, can not be more than 1008MHz +; min_freq: cpu minimum frequency, based on Hz, can not be less than 60MHz +; +; LV_count: count of LV_freq/LV_volt, must be < 16 +; +; LV1: core vdd is 1.45v if cpu frequency is (912Mhz, 1008Mhz] +; LV2: core vdd is 1.40v if cpu frequency is (864Mhz, 912Mhz] +; LV3: core vdd is 1.30v if cpu frequency is (792Mhz, 864Mhz] +; LV4: core vdd is 1.25v if cpu frequency is (720Mhz, 792Mhz] +; LV5: core vdd is 1.20v if cpu frequency is (624Mhz, 720Mhz] +; LV6: core vdd is 1.15v if cpu frequency is (528Mhz, 624Mhz] +; LV7: core vdd is 1.10v if cpu frequency is (312Mhz, 528Mhz] +; LV8: core vdd is 1.05v if cpu frequency is ( 60Mhz, 312Mhz] +; +;---------------------------------------------------------------------------------- +[dvfs_table] +max_freq = 912000000 +normal_freq = 720000000 +min_freq = 60000000 + +LV_count = 8 + +LV1_freq = 1008000000 +LV1_volt = 1450 + +LV2_freq = 912000000 +LV2_volt = 1400 + +LV3_freq = 864000000 +LV3_volt = 1300 + +LV4_freq = 792000000 +LV4_volt = 1250 + +LV5_freq = 720000000 +LV5_volt = 1200 + +LV6_freq = 624000000 +LV6_volt = 1150 + +LV7_freq = 528000000 +LV7_volt = 1100 + +LV8_freq = 312000000 +LV8_volt = 1050 + +[gpio_para] +gpio_used = 1 +gpio_num = 25 +gpio_pin_0 = port:PI19<1><2> +gpio_pin_1 = port:PI18<0><2> +gpio_pin_2 = port:PH07<1><1> +gpio_pin_3 = port:PH06<1><0> +gpio_pin_4 = port:PH08<1><1> +gpio_pin_5 = port:PB02<0><2> +gpio_pin_6 = port:PI03<0><2> +gpio_pin_7 = port:PH09<0><2> +gpio_pin_8 = port:PH10<6> +gpio_pin_9 = port:PH05<0><2> +gpio_pin_10 = port:PI10<0><2> +gpio_pin_11 = port:PI12<0><2> +gpio_pin_12 = port:PI13<0><2> +gpio_pin_13 = port:PI11<0><2> +gpio_pin_14 = port:PH11<0><2> +gpio_pin_15 = port:PH12<0><2> +gpio_pin_16 = port:PH13<0><2> +gpio_pin_17 = port:PH14<0><2> +gpio_pin_18 = port:PH15<1><0> +gpio_pin_19 = port:PH16<1><0> +gpio_pin_20 = port:PC19<0><2> +gpio_pin_21 = port:PC21<0><2> +gpio_pin_22 = port:PC22<0><2> +gpio_pin_23 = port:PC20<0><2> +; usb_power_en +gpio_pin_24 = port:PD02<1><1> + +; Redeclared gpio_pin_0 as gpio_pin_24, for sun4i-gpio driver +gpio_pin_25 = port:PI19<0><1> + +[sb_pwm0] +pwm_gpio = port:PH06<1> + +[sb_pwm1] +pwm_gpio = port:PB02<2> + +[sb_pwm2] +pwm_gpio = port:PI03<2> + +[sb_pwm3] +pwm_gpio = port:PH05<1> + +[sb_pwm4] +pwm_gpio = port:PI10<1> + +[sb_pwm5] +pwm_gpio = port:PI12<1> + +[sb_keypad_para] +sb_key_used = 1 +key_num = 3 +; BACK ==> KEY_ESC +key_pin_0 = port:PH17<6><1><3> +key_code_0 = 1 +; MENU ==> KEY_SPACE +key_pin_1 = port:PH18<6><1><3> +key_code_1 = 57 +; HOME ==> KEY_ENTER +key_pin_2 = port:PH19<6><1><3> +key_code_2 = 28 diff --git a/sunxi-boards/sys_config/a20/pcduino3_nano.fex b/sunxi-boards/sys_config/a20/pcduino3_nano.fex new file mode 100644 index 0000000..7182cbd --- /dev/null +++ b/sunxi-boards/sys_config/a20/pcduino3_nano.fex @@ -0,0 +1,1559 @@ +;A20 PAD application +;------------------------------------------------------------------------------- +; 说明： +; 1. 脚本中的字符串区分大小写，用户可以修改"="后面的数值，但是不要修改前面的字符串 +; 2. 新增主键和子键的名称必须控制在32个字符以内，不包括32个 +; 3. 所以的注释以“;”开始，单独占据一行 +; 4. 注释不可和配置项同行，例如：主键和子健后面不能添加任何形式的注释 +; +; gpio的描述形式：Port:端口+组内序号<功能分配><内部电阻状态><驱动能力><输出电平状态> +; 例如：port:PA0<0> +;------------------------------------------------------------------------------- + +[product] +version = "100" +machine = "pcduino3-v10" + +[platform] +eraseflag = 1 + +[target] +boot_clock = 912 +dcdc2_vol = 1400 +dcdc3_vol = 1250 +ldo2_vol = 3000 +ldo3_vol = 2800 +ldo4_vol = 2800 +power_start = 3 +storage_type = -1 + +[clock] +pll3 = 297 +pll4 = 300 +pll6 = 600 +pll7 = 297 +pll8 = 336 + +[card_boot] +logical_start = 40960 +sprite_gpio0 = port:PH15<1><0> +sprite_work_delay = 1000 +sprite_err_delay = 100 + +[card0_boot_para] +card_ctrl = 0 +card_high_speed = 1 +card_line = 4 +sdc_d1 = port:PF0<2><1> +sdc_d0 = port:PF1<2><1> +sdc_clk = port:PF2<2><1> +sdc_cmd = port:PF3<2><1> +sdc_d3 = port:PF4<2><1> +sdc_d2 = port:PF5<2><1> + +[card2_boot_para] +card_ctrl = 2 +card_high_speed = 1 +card_line = 4 +sdc_cmd = port:PC6<3><1> +sdc_clk = port:PC7<3><1> +sdc_d0 = port:PC8<3><1> +sdc_d1 = port:PC9<3><1> +sdc_d2 = port:PC10<3><1> +sdc_d3 = port:PC11<3><1> + +[twi_para] +twi_port = 0 +twi_scl = port:PB0<2> +twi_sda = port:PB1<2> + +[uart_para] +uart_debug_port = 0 +uart_debug_tx = port:PB22<2><1> +uart_debug_rx = port:PB23<2><1> + +[uart_force_debug] +uart_debug_port = 0 +uart_debug_tx =port:PF2<4><1> +uart_debug_rx =port:PF4<4><1> + +[jtag_para] +jtag_enable = 0 +jtag_ms = port:PB14<3> +jtag_ck = port:PB15<3> +jtag_do = port:PB16<3> +jtag_di = port:PB17<3> + +;--------------------------------------------------------------------------------------------------------- +; if 1 == standby_mode, then support super standby; +; else, support normal standby. +;--------------------------------------------------------------------------------------------------------- +[pm_para] +standby_mode = 0 + +;------------------------------------------------------------------------------- +;sdram configuration +;------------------------------------------------------------------------------- +[dram_para] +dram_baseaddr = 0x40000000 +dram_clk = 408 +dram_type = 3 +dram_rank_num = 0xffffffff +dram_chip_density = 0xffffffff +dram_io_width = 0xffffffff +dram_bus_width = 0xffffffff +dram_cas = 9 +dram_zq = 0x7a +dram_odt_en = 0 +dram_size = 0xffffffff +dram_tpr0 = 0x42d899b7 +dram_tpr1 = 0xa090 +dram_tpr2 = 0x22a00 +dram_tpr3 = 0x0 +dram_tpr4 = 0x0 +dram_tpr5 = 0x0 +dram_emr1 = 0x4 +dram_emr2 = 0x10 +dram_emr3 = 0x0 + +;------------------------------------------------------------------------------- +;Mali configuration +;------------------------------------------------------------------------------- +[mali_para] +mali_used = 1 +mali_clkdiv = 1 + +;------------------------------------------------------------------------------- +;Ethernet MAC configuration +;------------------------------------------------------------------------------- +[emac_para] +emac_used = 1 +emac_rxd3 = port:PA00<2> +emac_rxd2 = port:PA01<2> +emac_rxd1 = port:PA02<2> +emac_rxd0 = port:PA03<2> +emac_txd3 = port:PA04<2> +emac_txd2 = port:PA05<2> +emac_txd1 = port:PA06<2> +emac_txd0 = port:PA07<2> +emac_rxclk = port:PA08<2> +emac_rxerr = port:PA09<2> +emac_rxdV = port:PA10<2> +emac_mdc = port:PA11<2> +emac_mdio = port:PA12<2> +emac_txen = port:PA13<2> +emac_txclk = port:PA14<2> +emac_crs = port:PA15<2> +emac_col = port:PA16<2> +emac_reset = port:PA17<1> + + +;------------------------------------------------------------- +; GMAC configuration +;--------------------------------------------------------- +[gmac_para] +gmac_used = 1 +gmac_rxd3 = port:PA00<5><3> +gmac_rxd2 = port:PA01<5><3> +gmac_rxd1 = port:PA02<5><3> +gmac_rxd0 = port:PA03<5><3> +gmac_txd3 = port:PA04<5><3> +gmac_txd2 = port:PA05<5><3> +gmac_txd1 = port:PA06<5><3> +gmac_txd0 = port:PA07<5><3> +gmac_rxclk = port:PA08<5><3> +gmac_rxerr = port:PA09<0><3> +gmac_rxctl = port:PA10<5><3> +gmac_mdc = port:PA11<5><3> +gmac_mdio = port:PA12<5><3> +gmac_txctl = port:PA13<5><3> +gmac_txclk = port:PA14<0><3> +gmac_txck = port:PA15<5><3> +gmac_clkin = port:PA16<5><3> +gmac_txerr = port:PA17<0><3> + +;------------------------------------------------------------------------------- +;i2c configuration +;------------------------------------------------------------------------------- +[twi0_para] +twi0_used = 1 +twi0_scl = port:PB0<2> +twi0_sda = port:PB1<2> + +[twi1_para] +twi1_used = 1 +twi1_scl = port:PB18<2> +twi1_sda = port:PB19<2> + +[twi2_para] +twi2_used = 1 +twi2_scl = port:PB20<2> +twi2_sda = port:PB21<2> + +;------------------------------------------------------------------------------- +;uart configuration +;uart_type --- 2 (2 wire), 4 (4 wire), 8 (8 wire, full function) +;------------------------------------------------------------------------------- +[uart_para0] +uart_used = 1 +uart_port = 0 +uart_type = 2 +uart_tx = port:PB22<2><1> +uart_rx = port:PB23<2><1> + +[uart_para1] +uart_used = 0 +uart_port = 1 +uart_type = 8 +uart_tx = port:PA10<4><1> +uart_rx = port:PA11<4><1> +uart_rts = port:PA12<4><1> +uart_cts = port:PA13<4><1> +uart_dtr = port:PA14<4><1> +uart_dsr = port:PA15<4><1> +uart_dcd = port:PA16<4><1> +uart_ring = port:PA17<4><1> + +[uart_para2] +uart_used = 1 +uart_port = 2 +uart_type = 4 +uart_tx = port:PI18<0><2> +uart_rx = port:PI19<1><2> +uart_rts = port:PI16<3><1> +uart_cts = port:PI17<3><1> + +[uart_para3] +uart_used = 0 +uart_port = 3 +uart_type = 4 +uart_tx = port:PH00<4><1> +uart_rx = port:PH01<4><1> +uart_rts = port:PH02<4><1> +uart_cts = port:PH03<4><1> + +[uart_para4] +uart_used = 0 +uart_port = 4 +uart_type = 2 +uart_tx = port:PH04<4><1> +uart_rx = port:PH05<4><1> + +[uart_para5] +uart_used = 0 +uart_port = 5 +uart_type = 2 +uart_tx = port:PH06<4><1> +uart_rx = port:PH07<4><1> + +[uart_para6] +uart_used = 0 +uart_port = 6 +uart_type = 2 +uart_tx = port:PA12<3><1> +uart_rx = port:PA13<3><1> + +[uart_para7] +uart_used = 0 +uart_port = 7 +uart_type = 2 +uart_tx = port:PA14<3><1> +uart_rx = port:PA15<3><1> + +;------------------------------------------------------------------------------- +;spi configuration +;------------------------------------------------------------------------------- +[spi0_para] +spi_used = 1 +spi_cs_bitmap = 1 +spi_cs0 = port:PI10<0><2> +spi_cs1 = port:PI14<2> +spi_sclk = port:PI11<0><2> +spi_mosi = port:PI12<0><2> +spi_miso = port:PI13<0><2> + +[spi1_para] +spi_used = 0 +spi_cs_bitmap = 1 +spi_cs0 = port:PA00<3> +spi_cs1 = port:PA04<3> +spi_sclk = port:PA01<3> +spi_mosi = port:PA02<3> +spi_miso = port:PA03<3> + +[spi2_para] +spi_used = 1 +spi_cs_bitmap = 1 +spi_cs0 = port:PC19<0><2> +spi_cs1 = port:PB13<2> +spi_sclk = port:PC20<0><2> +spi_mosi = port:PC21<0><2> +spi_miso = port:PC22<0><2> + +[spi3_para] +spi_used = 0 +spi_cs_bitmap = 1 +spi_cs0 = port:PA05<3> +spi_cs1 = port:PA09<3> +spi_sclk = port:PA06<3> +spi_mosi = port:PA07<3> +spi_miso = port:PA08<3> + +[spi_devices] +spi_dev_num = 2 + +[spi_board0] +modalias = "spidev" +max_speed_hz = 12000000 +bus_num = 0 +chip_select = 0 +mode = 3 +full_duplex = 0 +manual_cs = 0 + +[spi_board1] +modalias = "spidev" +max_speed_hz = 12000000 +bus_num = 2 +chip_select = 0 +mode = 0 +full_duplex = 0 +manual_cs = 0 + +;---------------------------------------------------------------------------------- +;resistance tp configuration +;---------------------------------------------------------------------------------- +[rtp_para] +rtp_used = 1 +rtp_screen_size = 5 +rtp_regidity_level = 5 +rtp_press_threshold_enable = 0 +rtp_press_threshold = 0x1f40 +rtp_sensitive_level = 0xf +rtp_exchange_x_y_flag = 0 +;------------------------------------------------------------------------------- +;capacitor tp configuration +;external int function +;wakeup output function +;notice: +; tp_int_port & tp_io_port use the same port +;------------------------------------------------------------------------------- +[ctp_para] +ctp_used = 1 +ctp_twi_id = 2 +ctp_twi_name = "gslX680" +ctp_screen_max_x = 1024 +ctp_screen_max_y = 600 +ctp_revert_x_flag = 0 +ctp_revert_y_flag = 0 +ctp_exchange_x_y_flag = 0 + +ctp_int_port = port:PH10<6> +ctp_wakeup = + +;------------------------------------------------------------------------------- +;touch key configuration +;------------------------------------------------------------------------------- +[tkey_para] +tkey_used = 0 +tkey_twi_id = 2 +tkey_twi_addr = 0x62 +tkey_int = port:PI13<6> + +;------------------------------------------------------------------------------- +;motor configuration +;------------------------------------------------------------------------------- +[motor_para] +motor_used = 0 +motor_shake = port:PB03<1><1> + +;------------------------------------------------------------------------------- +;nand flash configuration +;------------------------------------------------------------------------------- +[nand_para] +nand_used = 1 +nand_we = port:PC00<2> +nand_ale = port:PC01<2> +nand_cle = port:PC02<2> +nand_ce1 = port:PC03<2> +nand_ce0 = port:PC04<2> +nand_nre = port:PC05<2> +nand_rb0 = port:PC06<2> +nand_rb1 = port:PC07<2> +nand_d0 = port:PC08<2> +nand_d1 = port:PC09<2> +nand_d2 = port:PC10<2> +nand_d3 = port:PC11<2> +nand_d4 = port:PC12<2> +nand_d5 = port:PC13<2> +nand_d6 = port:PC14<2> +nand_d7 = port:PC15<2> +nand_wp = port:PC16<2> +nand_ce2 = port:PC17<2> +nand_ce3 = port:PC18<2> +nand_ce4 = +nand_ce5 = +nand_ce6 = +nand_ce7 = +nand_spi = port:PC23<3> +nand_ndqs = port:PC24<2> +good_block_ratio = 0 + +;------------------------------------------------------------------------------- +;disp init configuration +; +;disp_mode (0:screen0 1:screen1 2:two_diff_screen_diff_contents +; 3:two_same_screen_diff_contets 4:two_diff_screen_same_contents) +;screenx_output_type (0:none; 1:lcd; 2:tv; 3:hdmi; 4:vga) +;screenx_output_mode (used for tv/hdmi output, 0:480i 1:576i 2:480p 3:576p 4:720p50 5:720p60 6:1080i50 7:1080i60 8:1080p24 9:1080p50 10:1080p60 11:pal 14:ntsc) +;screenx_output_mode (used for vga output, 0:1680*1050 1:1440*900 2:1360*768 3:1280*1024 4:1024*768 5:800*600 6:640*480 10:1920*1080 11:1280*720) +;fbx format (4:RGB655 5:RGB565 6:RGB556 7:ARGB1555 8:RGBA5551 9:RGB888 10:ARGB8888 12:ARGB4444) +;fbx pixel sequence (0:ARGB 1:BGRA 2:ABGR 3:RGBA) --- 0 for linux, 2 for android +;lcd0_bright (lcd0 init bright,the range:[0,256],default:197 +;lcd1_bright (lcd1 init bright,the range:[0,256],default:197 +;------------------------------------------------------------------------------- + +[boot_disp] +output_type = 3 +output_mode = 5 + +[disp_init] +disp_init_enable = 1 +disp_mode = 0 + +screen0_output_type = 3 +screen0_output_mode = 5 + +screen1_output_type = 0 +screen1_output_mode = 4 + +fb0_framebuffer_num = 2 +fb0_format = 10 +fb0_pixel_sequence = 0 +fb0_scaler_mode_enable = 1 +fb0_width = 0 +fb0_height = 0 + +fb1_framebuffer_num = 2 +fb1_format = 10 +fb1_pixel_sequence = 0 +fb1_scaler_mode_enable = 0 +fb1_width = 0 +fb1_height = 0 + +lcd0_backlight = 197 +lcd1_backlight = 197 + +lcd0_bright = 50 +lcd0_contrast = 50 +lcd0_saturation = 57 +lcd0_hue = 50 + +lcd1_bright = 50 +lcd1_contrast = 50 +lcd1_saturation = 57 +lcd1_hue = 50 + +;------------------------------------------------------------------------------- +;lcd0 configuration + +;lcd_dclk_freq: in MHZ unit +;lcd_pwm_freq: in HZ unit +;lcd_if: 0:hv(sync+de); 1:8080; 2:ttl; 3:lvds; 4:hv2dsi +;lcd_width: width of lcd in mm +;lcd_height: height of lcd in mm +;lcd_hbp: hsync back porch +;lcd_ht: hsync total cycle +;lcd_vbp: vsync back porch +;lcd_vt: vysnc total cycle *2 +;lcd_hv_if: 0:hv parallel 1:hv serial +;lcd_hv_smode: 0:RGB888 1:CCIR656 +;lcd_hv_s888_if serial RGB format +;lcd_hv_syuv_if: serial YUV format +;lcd_hspw: hsync plus width +;lcd_vspw: vysnc plus width +;lcd_lvds_ch: 0:single channel; 1:dual channel +;lcd_lvds_mode: 0:NS mode; 1:JEIDA mode +;lcd_lvds_bitwidth: 0:24bit; 1:18bit +;lcd_lvds_io_cross: 0:normal; 1:pn cross +;lcd_cpu_if: 0:18bit; 1:16bit mode0; 2:16bit mode1; 3:16bit mode2; 4:16bit mode3; 5:9bit; 6:8bit 256K; 7:8bit 65K +;lcd_frm: 0:disable; 1:enable rgb666 dither; 2:enable rgb656 dither + +;lcd_gpio_0: SCL +;lcd_gpio_1 SDA +;------------------------------------------------------------------------------- +[lcd0_para] +lcd_used = 0 + +lcd_x = 1024 +lcd_y = 600 +lcd_width = 0 +lcd_height = 0 +lcd_dclk_freq = 51 +lcd_pwm_not_used = 1 +lcd_pwm_ch = 0 +lcd_pwm_freq = 10000 +lcd_pwm_pol = 0 +lcd_if = 3 +lcd_hbp = 310 +lcd_ht = 1340 +lcd_vbp = 30 +lcd_vt = 1268 +lcd_vspw = 0 +lcd_hspw = 0 +lcd_hv_if = 0 +lcd_hv_smode = 0 +lcd_hv_s888_if = 0 +lcd_hv_syuv_if = 0 +lcd_lvds_ch = 0 +lcd_lvds_mode = 0 +lcd_lvds_bitwidth = 0 +lcd_lvds_io_cross = 0 +lcd_cpu_if = 0 +lcd_frm = 0 +lcd_io_cfg0 = 0x10000000 +lcd_gamma_correction_en = 0 +lcd_gamma_tbl_0 = 0x00000000 +lcd_gamma_tbl_1 = 0x00010101 +lcd_gamma_tbl_255 = 0x00ffffff + +lcd_bl_en_used = 0 +lcd_bl_en = port:PH07<1><0><1> + +lcd_power_used = 0 +lcd_power = port:PH08<1><0><1> + +lcd_pwm_used = 0 +lcd_pwm = port:PB02<2><0> + +lcdd0 = port:PD00<3> +lcdd1 = port:PD01<3> +lcdd2 = port:PD02<3> +lcdd3 = port:PD03<3> +lcdd4 = port:PD04<3> +lcdd5 = port:PD05<3> +lcdd6 = port:PD06<3> +lcdd7 = port:PD07<3> +lcdd8 = port:PD08<3> +lcdd9 = port:PD09<3> + +;---------------------------------------------------------------------------------- +;lcd1 configuration + +;lcd_dclk_freq: in MHZ unit +;lcd_pwm_freq: in HZ unit +;lcd_if: 0:hv(sync+de); 1:8080; 2:ttl; 3:lvds +;lcd_hbp: hsync back porch +;lcd_ht: hsync total cycle +;lcd_vbp: vsync back porch +;lcd_vt: vysnc total cycle *2 +;lcd_hv_if: 0:hv parallel 1:hv serial +;lcd_hv_smode: 0:RGB888 1:CCIR656 +;lcd_hv_s888_if serial RGB format +;lcd_hv_syuv_if: serial YUV format +;lcd_hspw: hsync plus width +;lcd_vspw: vysnc plus width +;lcd_lvds_ch: 0:single channel; 1:dual channel +;lcd_lvds_mode: 0:NS mode; 1:JEIDA mode +;lcd_lvds_bitwidth: 0:24bit; 1:18bit +;lcd_lvds_io_cross: 0:normal; 1:pn cross +;lcd_cpu_if: 0:18bit; 1:16bit mode0; 2:16bit mode1; 3:16bit mode2; 4:16bit mode3; 5:9bit; 6:8bit 256K; 7:8bit 65K +;lcd_frm: 0:disable; 1:enable rgb666 dither; 2:enable rgb656 dither + +;lcd_gpio_0: SCL +;lcd_gpio_1 SDA +;---------------------------------------------------------------------------------- +[lcd1_para] +lcd_used = 0 + +lcd_x = 1024 +lcd_y = 600 +lcd_width = 0 +lcd_height = 0 +lcd_dclk_freq = 51 +lcd_pwm_not_used = 0 +lcd_pwm_ch = 0 +lcd_pwm_freq = 10000 +lcd_pwm_pol = 0 +lcd_if = 3 +lcd_hbp = 310 +lcd_ht = 1340 +lcd_vbp = 30 +lcd_vt = 1268 +lcd_vspw = 0 +lcd_hspw = 0 +lcd_hv_if = 0 +lcd_hv_smode = 0 +lcd_hv_s888_if = 0 +lcd_hv_syuv_if = 0 +lcd_lvds_ch = 0 +lcd_lvds_mode = 0 +lcd_lvds_bitwidth = 0 +lcd_lvds_io_cross = 0 +lcd_cpu_if = 0 +lcd_frm = 0 +lcd_io_cfg0 = 0 +lcd_gamma_correction_en = 0 +lcd_gamma_tbl_0 = 0x00000000 +lcd_gamma_tbl_1 = 0x00010101 +lcd_gamma_tbl_255 = 0x00ffffff + +lcd_bl_en_used = 1 +lcd_bl_en = port:PH07<1><1> + +lcd_power_used = 1 +lcd_power = port:PH08<1><1> + +lcd_pwm_used = 1 +lcd_pwm = port:PH06<1><0> + +lcd_gpio_0 = +lcd_gpio_1 = +lcd_gpio_2 = +lcd_gpio_3 = + +lcdd10 = port:PD10<3> +lcdd11 = port:PD11<3> +lcdd12 = port:PD12<3> +lcdd13 = port:PD13<3> +lcdd14 = port:PD14<3> +lcdd15 = port:PD15<3> +lcdd16 = port:PD16<3> +lcdd17 = port:PD17<3> +lcdd18 = port:PD18<3> +lcdd19 = port:PD19<3> + +;------------------------------------------------------------------------------- +;tv out dac configuration +;dacx_src: 0:composite; 1:luma; 2:chroma; 4:Y; 5:Pb; 6: Pr; 7:none +;------------------------------------------------------------------------------- +[tv_out_dac_para] +dac_used = 1 +dac0_src = 4 +dac1_src = 5 +dac2_src = 6 +dac3_src = 0 + +;---------------------------------------------------------------------------------- +;hdmi configuration +;---------------------------------------------------------------------------------- +[hdmi_para] +hdmi_used = 1 +hdcp_enable = 0 + +[i2s2_para] +i2s_channel = 2 +i2s_master = 4 +i2s_select = 1 +audio_format = 1 +signal_inversion = 1 +over_sample_rate = 256 +sample_resolution = 16 +word_select_size = 32 +pcm_sync_period = 256 +msb_lsb_first = 0 +sign_extend = 0 +slot_index = 0 +slot_width = 16 +frame_width = 1 +tx_data_mode = 0 +rx_data_mode = 0 +;i2s_mclk = port:PB05<2><1> +;i2s_bclk = port:PB06<2><1> +;i2s_lrclk = port:PB07<2><1> +;i2s_dout0 = port:PB08<2><1> +;i2s_dout1 = +;i2s_dout2 = +;i2s_dout3 = +;i2s_din = port:PB12<2><1> + + +[camera_list_para] +camera_list_para_used = 1 +ov7670 = 0 +gc0308 = 1 +gt2005 = 0 +hi704 = 0 +sp0838 = 0 +mt9m112 = 0 +mt9m113 = 0 +ov2655 = 0 +hi253 = 0 +gc0307 = 0 +mt9d112 = 0 +ov5640 = 1 +gc2015 = 0 +ov2643 = 0 +gc0329 = 0 +gc0309 = 0 +tvp5150 = 0 +s5k4ec = 0 +ov5650_mv9335 = 0 +siv121d = 0 + +;-------------------------------------------------------------------------------- +;csi gpio configuration +;csi_if: 0:hv_8bit 1:hv_16bit 2:hv_24bit 3:bt656 1ch 4:bt656 2ch 5:bt656 4ch +;csi_mode: 0:sample one csi to one buffer 1:sample two csi to one buffer +;csi_dev_qty: The quantity of devices linked to csi interface +;csi_vflip: flip in vertical direction 0:disable 1:enable +;csi_hflip: flip in horizontal direction 0:disable 1:enable +;csi_stby_mode: 0:not shut down power at standby 1:shut down power at standby +;csi_iovdd: camera module io power , pmu power supply +;csi_avdd: camera module analog power , pmu power supply +;csi_dvdd: camera module core power , pmu power supply +;pmu_ldo3: fill "axp20_pll" +;pmu_ldo4: fill "axp20_hdmi" +;fill "" when not using any pmu power supply +;csi_flash_pol: the active polority of the flash light IO 0:low active 1:high active +;-------------------------------------------------------------------------------- + +[csi0_para] +csi_used = 1 + +csi_dev_qty = 1 +csi_stby_mode = 0 +csi_mname = "gc2035" +csi_if = 0 +csi_iovdd = "" +csi_avdd = "" +csi_dvdd = "" +csi_vol_iovdd = +csi_vol_dvdd = +csi_vol_avdd = +csi_vflip = 0 +csi_hflip = 0 +csi_flash_pol = 0 +csi_facing = 0 + +csi_twi_id = 1 +csi_twi_addr = 0x78 +csi_pck = port:PE00<3> +csi_ck = port:PE01<3> +csi_hsync = port:PE02<3> +csi_vsync = port:PE03<3> +csi_d0 = port:PE04<3> +csi_d1 = port:PE05<3> +csi_d2 = port:PE06<3> +csi_d3 = port:PE07<3> +csi_d4 = port:PE08<3> +csi_d5 = port:PE09<3> +csi_d6 = port:PE10<3> +csi_d7 = port:PE11<3> +csi_reset = port:PH27<1><1> +csi_power_en = port:PH26<1><0> +csi_stby = + +[csi1_para] +csi_used = 0 + +csi_dev_qty = 1 +csi_stby_mode = 0 +csi_mname = "gc0308" +csi_if = 0 +csi_iovdd = "" +csi_avdd = "" +csi_dvdd = "" +csi_vol_iovdd = +csi_vol_dvdd = +csi_vol_avdd = +csi_vflip = 0 +csi_hflip = 0 +csi_flash_pol = 0 +csi_facing = 1 + +csi_twi_id = 1 +csi_twi_addr = 0x42 +csi_pck = port:PG00<3> +csi_ck = port:PG01<3> +csi_hsync = port:PG02<3> +csi_vsync = port:PG03<3> +csi_d0 = port:PG04<3> +csi_d1 = port:PG05<3> +csi_d2 = port:PG06<3> +csi_d3 = port:PG07<3> +csi_d4 = port:PG08<3> +csi_d5 = port:PG09<3> +csi_d6 = port:PG10<3> +csi_d7 = port:PG11<3> +csi_reset = port:PH14<1><0> +csi_power_en = +csi_stby = port:PH17<1><0> + +;------------------------------------------------------------------------------- +;tv configuration +; +;------------------------------------------------------------------------------- +[tvout_para] +tvout_used = 1 +tvout_channel_num = 1 + +[tvin_para] +tvin_used = 0 +tvin_channel_num = 4 + + +;------------------------------------------------------------------------------- +;sata configuration +; +;------------------------------------------------------------------------------- +[sata_para] +sata_used = 1 +sata_power_en = port:PH02<1><1> + + +;------------------------------------------------------------------------------- +; SDMMC PINS MAPPING +; ------------------------------------------------------------------------------ +; Config Guide +; sdc_used: 1-enable card, 0-disable card +; sdc_detmode: card detect mode +; 1-detect card by gpio polling +; 2-detect card by gpio irq(must use IO with irq function) +; 3-no detect, always in for boot card +; 4-manually insert and remove by /proc/driver/sunxi-mmc.x/insert +; sdc_buswidth: card bus width, 1-1bit, 4-4bit, 8-8bit +; sdc_use_wp: 1-with write protect IO, 0-no write protect IO +; sdc_isio: for sdio card +; sdc_regulator: power control. +; other: GPIO Mapping configuration +; ------------------------------------------------------------------------------ +; Note: +; 1 if detmode=2, sdc_det's config=6 +; else if detmode=1, sdc_det's config=0 +; else sdc_det IO is not necessary +; 2 if the customer wants to support UHS-I and HS200 features, he must provide +; an independent power supply for the card. This is only used in platforms +; that supports SD3.0 cards and eMMC4.4+ flashes +;------------------------------------------------------------------------------- +[mmc0_para] +sdc_used = 1 +sdc_detmode = 1 +sdc_buswidth = 4 +sdc_clk = port:PF02<2><1><2> +sdc_cmd = port:PF03<2><1><2> +sdc_d0 = port:PF01<2><1><2> +sdc_d1 = port:PF00<2><1><2> +sdc_d2 = port:PF05<2><1><2> +sdc_d3 = port:PF04<2><1><2> +sdc_det = port:PH1<0><1> +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 0 +sdc_regulator = "none" + +[mmc1_para] +sdc_used = 0 +sdc_detmode = 4 +sdc_buswidth = 4 +sdc_clk = port:PG00<2><1><2> +sdc_cmd = port:PG01<2><1><2> +sdc_d0 = port:PG02<2><1><2> +sdc_d1 = port:PG03<2><1><2> +sdc_d2 = port:PG04<2><1><2> +sdc_d3 = port:PG05<2><1><2> +sdc_det = +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 0 +sdc_regulator = "none" + +[mmc2_para] +sdc_used = 0 +sdc_detmode = 3 +sdc_buswidth = 4 +sdc_cmd = port:PC06<3><1><2> +sdc_clk = port:PC07<3><1><2> +sdc_d0 = port:PC08<3><1><2> +sdc_d1 = port:PC09<3><1><2> +sdc_d2 = port:PC10<3><1><2> +sdc_d3 = port:PC11<3><1><2> +sdc_det = +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 0 +sdc_regulator = "none" + +[mmc3_para] +sdc_used = 0 +sdc_detmode = 4 +sdc_buswidth = 4 +sdc_cmd = port:PI04<2><1><2> +sdc_clk = port:PI05<2><1><2> +sdc_d0 = port:PI06<2><1><2> +sdc_d1 = port:PI07<2><1><2> +sdc_d2 = port:PI08<2><1><2> +sdc_d3 = port:PI09<2><1><2> +sdc_det = +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 1 +sdc_regulator = "none" + +; ------------------------------------------------------------------------------ +; memory stick configuration +;------------------------------------------------------------------------------- +[ms_para] +ms_used = 0 +ms_bs = port:PH06<5> +ms_clk = port:PH07<5> +ms_d0 = port:PH08<5> +ms_d1 = port:PH09<5> +ms_d2 = port:PH10<5> +ms_d3 = port:PH11<5> +ms_det = + +; ------------------------------------------------------------------------------ +; sim card configuration +;------------------------------------------------------------------------------- +[smc_para] +smc_used = 0 +smc_rst = port:PH13<5> +smc_vppen = port:PH14<5> +smc_vppp = port:PH15<5> +smc_det = port:PH16<5> +smc_vccen = port:PH17<5> +smc_sck = port:PH18<5> +smc_sda = port:PH19<5> + +;------------------------------------------------------------------------------- +;ps2 configuration +;------------------------------------------------------------------------------- +[ps2_0_para] +ps2_used = 0 +ps2_scl = port:PI20<2><1> +ps2_sda = port:PI21<2><1> + +[ps2_1_para] +ps2_used = 0 +ps2_scl = port:PI14<3><1> +ps2_sda = port:PI15<3><1> + +;------------------------------------------------------------------------------- +;can bus configuration +;------------------------------------------------------------------------------- +[can_para] +can_used = 0 +can_tx = port:PA16<3> +can_rx = port:PA17<3> + +;------------------------------------------------------------------------------- +;key matrix +;------------------------------------------------------------------------------- +[keypad_para] +kp_used = 0 +kp_in_size = 8 +kp_out_size = 8 +kp_in0 = port:PH08<4><1> +kp_in1 = port:PH09<4><1> +kp_in2 = port:PH10<4><1> +kp_in3 = port:PH11<4><1> +kp_in4 = port:PH14<4><1> +kp_in5 = port:PH15<4><1> +kp_in6 = port:PH16<4><1> +kp_in7 = port:PH17<4><1> +kp_out0 = port:PH18<4><1> +kp_out1 = port:PH19<4><1> +kp_out2 = port:PH22<4><1> +kp_out3 = port:PH23<4><1> +kp_out4 = port:PH24<4><1> +kp_out5 = port:PH25<4><1> +kp_out6 = port:PH26<4><1> +kp_out7 = port:PH27<4><1> + + +;------------------------------------------------------------------------------- +;[usbc0]：控制器0的配置。 +;usb_used：USB使能标志。置1，表示系统中USB模块可用,置0,则表示系统USB禁用。 +;usb_port_type：USB端口的使用情况。 0：device only;1：host only;2：OTG +;usb_detect_type：USB端口的检查方式。0：不做检测;1：vbus/id检查;2：id/dpdm检查 +;usb_id_gpio：USB ID pin脚配置。具体请参考gpio配置说明。 +;usb_det_vbus_gpio：USB DET_VBUS pin脚配置。具体请参考gpio配置说明。 +;usb_drv_vbus_gpio：USB DRY_VBUS pin脚配置。具体请参考gpio配置说明。 +;usb_det_vbus_gpio: "axp_ctrl",表示axp 提供 +;usb_restrict_gpio usb限流控制pin +;usb_restric_flag: usb限流标置 +;------------------------------------------------------------------------------- +;------------------------------------------------------------------------------- +;--- USB0控制标志 +;------------------------------------------------------------------------------- +[usbc0] +usb_used = 1 +usb_port_type = 0 +usb_detect_type = 0 +usb_id_gpio = port:PH04<0><1> +usb_det_vbus_gpio = "axp_ctrl" +usb_drv_vbus_gpio = port:PB09<1><0><0> +;usb_restrict_gpio = port:PH00<1><0><0> +usb_host_init_state = 0 +usb_restric_flag = 0 +usb_restric_voltage = 3550000 +usb_restric_capacity= 5 + +;------------------------------------------------------------------------------- +;--- USB1控制标志 +;------------------------------------------------------------------------------ +[usbc1] +usb_used = 1 +usb_port_type = 1 +usb_detect_type = 0 +usb_drv_vbus_gpio = port:PH11<1><0><0> +usb_restrict_gpio = +usb_host_init_state = 1 +usb_restric_flag = 0 + +;------------------------------------------------------------------------------ +;--- USB2控制标志 +;------------------------------------------------------------------------------ +[usbc2] +usb_used = 1 +usb_port_type = 1 +usb_detect_type = 0 +usb_drv_vbus_gpio = port:PH03<1><0><0> +usb_restrict_gpio = + +usb_host_init_state = 1 +usb_restric_flag = 0 + +;-------------------------------- +;--- USB Device +;-------------------------------- +[usb_feature] +vendor_id = 0x18D1 +mass_storage_id = 0x0001 +adb_id = 0x0002 + +manufacturer_name = "USB Developer" +product_name = "Android" +serial_number = "20080411" + +[msc_feature] +vendor_name = "USB 2.0" +product_name = "USB Flash Driver" +release = 100 +luns = 1 + +;------------------------------------------------------------------------------- +; G sensor configuration +; gs_twi_id --- TWI ID for controlling Gsensor (0: TWI0, 1: TWI1, 2: TWI2) +;------------------------------------------------------------------------------- +[gsensor_para] +gsensor_used = 0 +gsensor_twi_id = 1 +gsensor_int1 = +gsensor_int2 = + +;------------------------------------------------------------------------------- +; gps gpio configuration +; gps_spi_id --- the index of SPI controller. 0: SPI0, 1: SPI1, 2: SPI2, 15: no SPI used +; gps_spi_cs_num --- the chip select number of SPI controller. 0: SPI CS0, 1: SPI CS1 +; gps_lradc --- the lradc number for GPS used. 0 and 1 is valid, set 2 if not use lradc +;------------------------------------------------------------------------------- +[gps_para] +gps_used = 0 +gps_spi_id = 2 +gps_spi_cs_num = 0 +gps_lradc = 1 +gps_clk = port:PI00<2> +gps_sign = port:PI01<2> +gps_mag = port:PI02<2> +gps_vcc_en = port:PC22<1><0> +gps_osc_en = port:PI14<1><0> +gps_rx_en = port:PI15<1><0> + +;-------------------------------------------------------------------------------- +;wifi configuration +;wifi_sdc_id --- 0- SDC0, 1- SDC1, 2- SDC2, 3- SDC3 +;wifi_usbc_id --- 0- USB0, 1- USB1, 2- USB2 +;wifi_usbc_type -- 1- EHCI(speed 2.0), 2- OHCI(speed 1.0) +;wifi_mod_sel --- 0- none, 1- bcm40181, 2- bcm40183(wifi+bt), +; 3 - rtl8723as(wifi+bt), 4- rtl8189es(SM89E00), +; 5 - rtl8192cu, 6 - rtl8188eu, 7 - ap6210 +;-------------------------------------------------------------------------------- +[wifi_para] +wifi_used = 1 +wifi_sdc_id = 3 +wifi_usbc_id = 2 +wifi_usbc_type = 1 +wifi_mod_sel = 7 +wifi_power = "" + +; 1 - bcm40181 sdio wifi gpio config +;bcm40181_shdn = port:PH09<1><0> +;bcm40181_host_wake = port:PH10<0><0> + +; 2 - bcm40183 sdio wifi gpio config +;bcm40183_wl_regon = port:PH09<1><0> +;bcm40183_wl_host_wake = port:PH10<0><0> +;bcm40183_bt_rst = port:PB05<1><0> +;bcm40183_bt_regon = port:PB05<1><0> +;bcm40183_bt_wake = port:PI20<1><0> +;bcm40183_bt_host_wake = port:PI21<0><0> + +; 3 - rtl8723as sdio wifi + bt gpio config +rtk_rtl8723as_wl_dis = port:PH09<1><0> +rtk_rtl8723as_bt_dis = port:PB05<1><0> +rtk_rtl8723as_wl_host_wake = port:PH10<0><0> +rtk_rtl8723as_bt_host_wake = port:PI21<0><0> + +; 4 - rtl8189es sdio wifi gpio config +;rtl8189es_shdn = port:PH09<1><0> +;rtl8189es_wakeup = port:PH10<1><1> + +; 5 - rtl8192cu usb wifi + +; 6 - rtl8188eu usb wifi + +; 7 - ap6210 sdio wifi + bt gpio config +ap6xxx_wl_regon = port:PH09<1><0> +ap6xxx_wl_host_wake = port:PH10<0><0> +ap6xxx_bt_regon = port:PB05<1><0> +ap6xxx_bt_wake = port:PI20<1><0> +ap6xxx_bt_host_wake = port:PI21<0><0> + + +[usb_wifi_para] +usb_wifi_used = 0 +usb_wifi_usbc_num = 2 + +;------------------------------------------------------------------------------- +;3G configuration +;------------------------------------------------------------------------------- +[3g_para] +3g_used = 0 +3g_usbc_num = 2 +3g_uart_num = 0 +3g_pwr = +3g_wakeup = +3g_int = + +;------------------------------------------------------------------------------- +;gyroscope +;------------------------------------------------------------------------------- +[gy_para] +gy_used = 0 +gy_twi_id = 1 +gy_twi_addr = 0x00 +gy_int1 = port:PH18<6><1> +gy_int2 = port:PH19<6><1> + +;------------------------------------------------------------------------------- +;light sensor +;------------------------------------------------------------------------------- +[ls_para] +ls_used = 0 +ls_twi_id = 1 +ls_twi_addr = 0x00 +ls_int = port:PH20<6><1> + +;------------------------------------------------------------------------------- +;compass +;------------------------------------------------------------------------------- +[compass_para] +compass_used = 0 +compass_twi_id = 1 +compass_twi_addr = 0x00 +compass_int = port:PI13<6><1> + +;------------------------------------------------------------------------------- +;blue tooth +;bt_used ---- blue tooth used (0- no used, 1- used) +;bt_uard_id ---- uart index +;------------------------------------------------------------------------------- +[bt_para] +bt_used = 0 +bt_uart_id = 2 +bt_wakeup = port:PI20<1> +bt_gpio = port:PI21<1> +bt_rst = port:PB05<1> + +;-------------------------------------------------------------------------------- +;i2s_master:1: SND_SOC_DAIFMT_CBM_CFM(codec clk & FRM master) use +; 2: SND_SOC_DAIFMT_CBS_CFM(codec clk slave & FRM master) not use +; 3: SND_SOC_DAIFMT_CBM_CFS(codec clk master & frame slave) not use +; 4: SND_SOC_DAIFMT_CBS_CFS(codec clk & FRM slave) use +;i2s_select:0 is pcm.1 is i2s +;audio_format: 1:SND_SOC_DAIFMT_I2S(standard i2s format). use +; 2:SND_SOC_DAIFMT_RIGHT_J(right justfied format). +; 3:SND_SOC_DAIFMT_LEFT_J(left justfied format) +; 4:SND_SOC_DAIFMT_DSP_A(pcm. MSB is available on 2nd BCLK rising edge after LRC rising edge). use +; 5:SND_SOC_DAIFMT_DSP_B(pcm. MSB is available on 1nd BCLK rising edge after LRC rising edge) +;signal_inversion:1:SND_SOC_DAIFMT_NB_NF(normal bit clock + frame) use +; 2:SND_SOC_DAIFMT_NB_IF(normal BCLK + inv FRM) +; 3:SND_SOC_DAIFMT_IB_NF(invert BCLK + nor FRM) use +; 4:SND_SOC_DAIFMT_IB_IF(invert BCLK + FRM) +;over_sample_rate: support 128fs/192fs/256fs/384fs/512fs/768fs +;sample_resolution :16bits/20bits/24bits +;word_select_size :16bits/20bits/24bits/32bits +;pcm_sync_period :16/32/64/128/256 +;msb_lsb_first :0: msb first; 1: lsb first +;sign_extend :0: zero pending; 1: sign extend +;slot_index :slot index: 0: the 1st slot - 3: the 4th slot +;slot_width :8 bit width / 16 bit width +;frame_width :0: long frame = 2 clock width; 1: short frame +;tx_data_mode :0: 16bit linear PCM; 1: 8bit linear PCM; 2: 8bit u-law; 3: 8bit a-law +;rx_data_mode :0: 16bit linear PCM; 1: 8bit linear PCM; 2: 8bit u-law; 3: 8bit a-law +;-------------------------------------------------------------------------------- +[i2s_para] +i2s_used = 0 +i2s_channel = 2 +i2s_master = 4 +i2s_select = 1 +audio_format = 1 +signal_inversion = 1 +over_sample_rate = 256 +sample_resolution = 16 +word_select_size = 32 +pcm_sync_period = 256 +msb_lsb_first = 0 +sign_extend = 0 +slot_index = 0 +slot_width = 16 +frame_width = 1 +tx_data_mode = 0 +rx_data_mode = 0 +i2s_mclk = port:PB05<2><1> +i2s_bclk = port:PB06<2><1> +i2s_lrclk = port:PB07<2><1> +i2s_dout0 = port:PB08<2><1> +i2s_dout1 = +i2s_dout2 = +i2s_dout3 = +i2s_din = port:PB12<2><1> + + +;-------------------------------------------------------------------------------- +;pcm_master:1: SND_SOC_DAIFMT_CBM_CFM(codec clk & FRM master) use +; 2: SND_SOC_DAIFMT_CBS_CFM(codec clk slave & FRM master) not use +; 3: SND_SOC_DAIFMT_CBM_CFS(codec clk master & frame slave) not use +; 4: SND_SOC_DAIFMT_CBS_CFS(codec clk & FRM slave) use +;pcm_select:1 is pcm.0 is i2s +;audio_format: 1:SND_SOC_DAIFMT_I2S(standard i2s format). use +; 2:SND_SOC_DAIFMT_RIGHT_J(right justfied format). +; 3:SND_SOC_DAIFMT_LEFT_J(left justfied format) +; 4:SND_SOC_DAIFMT_DSP_A(pcm. MSB is available on 2nd BCLK rising edge after LRC rising edge). use +; 5:SND_SOC_DAIFMT_DSP_B(pcm. MSB is available on 1nd BCLK rising edge after LRC rising edge) +;signal_inversion:1:SND_SOC_DAIFMT_NB_NF(normal bit clock + frame) use +; 2:SND_SOC_DAIFMT_NB_IF(normal BCLK + inv FRM) +; 3:SND_SOC_DAIFMT_IB_NF(invert BCLK + nor FRM) use +; 4:SND_SOC_DAIFMT_IB_IF(invert BCLK + FRM) +;over_sample_rate: support 128fs/192fs/256fs/384fs/512fs/768fs +;sample_resolution :16bits/20bits/24bits +;word_select_size :16bits/20bits/24bits/32bits +;pcm_sync_period :16/32/64/128/256 +;msb_lsb_first :0: msb first; 1: lsb first +;sign_extend :0: zero pending; 1: sign extend +;slot_index :slot index: 0: the 1st slot - 3: the 4th slot +;slot_width :8 bit width / 16 bit width +;frame_width :0: long frame = 2 clock width; 1: short frame +;tx_data_mode :0: 16bit linear PCM; 1: 8bit linear PCM; 2: 8bit u-law; 3: 8bit a-law +;rx_data_mode :0: 16bit linear PCM; 1: 8bit linear PCM; 2: 8bit u-law; 3: 8bit a-law +;-------------------------------------------------------------------------------- +[pcm_para] +pcm_used = 0 +pcm_channel = 2 +pcm_master = 4 +pcm_select = 1 +audio_format = 4 +signal_inversion = 1 +over_sample_rate = 256 +sample_resolution = 16 +word_select_size = 32 +pcm_sync_period = 256 +msb_lsb_first = 0 +sign_extend = 0 +slot_index = 0 +slot_width = 16 +frame_width = 1 +tx_data_mode = 0 +rx_data_mode = 0 +pcm_mclk = port:PA09<6><1> +pcm_bclk = port:PA14<6><1> +pcm_lrclk = port:PA15<6><1> +pcm_dout0 = port:PA16<6><1> +pcm_dout1 = +pcm_dout2 = +pcm_dout3 = +pcm_din = port:PA17<6><1> + +[spdif_para] +spdif_used = 0 +spdif_mclk = +spdif_dout = port:PB13<4><1> +spdif_din = + +[audio_para] +audio_used = 1 +audio_pa_ctrl = port:PH15<1><0> +capture_used = 1 + +[switch_para] +switch_used = 0 + +;------------------------------------------------------------------------------- +;ir --- infra remote configuration +;------------------------------------------------------------------------------- +[ir_para] +ir_used = 1 +ir0_rx = port:PB04<2> + + +;------------------------------------------------------------------------------- +;pmu_twi_addr ---slave address +;pmu_twi_id ---i2c bus number (0 TWI0, 1 TWI2, 2 TWI3) +;pmu_irq_id ---irq number (0 irq0,1 irq1,……) +;pmu_battery_rdc ---battery initial resistance,mΩ,根据实际电池内阻填写 +;pmu_battery_cap ---battery capability,mAh，根据实际电池容量填写 +;pmu_init_chgcur ---set initial charging current limite,mA，300/400/500/600/700/800/900/1000/1100/1200/1300/1400/1500/1600/1700/1800 +;pmu_suspend_chgcur ---set suspend charging current limite,mA，300/400/500/600/700/800/900/1000/1100/1200/1300/1400/1500/1600/1700/1800 +;pmu_resume_chgcur ---set resume charging current limite,mA，300/400/500/600/700/800/900/1000/1100/1200/1300/1400/1500/1600/1700/1800 +;pmu_shutdown_chgcur ---set shutdown charging current limite,mA，300/400/500/600/700/800/900/1000/1100/1200/1300/1400/1500/1600/1700/1800 +;pmu_init_chgvol ---set initial charing target voltage,mV,4100/4150/4200/4360 +;pmu_init_chgend_rate ---set initial charing end current rate,10/15 +;pmu_init_chg_enabled ---set initial charing enabled,0:关闭,1:打开 +;pmu_init_adc_freq ---set initial adc frequency,Hz,25/50/100/200 +;pmu_init_adc_freqc ---set initial coulomb adc coufrequency,Hz,25/50/100/200 +;pmu_init_chg_pretime ---set initial pre-charging time,min,40/50/60/70 +;pmu_init_chg_csttime ---set initial constance-charging time,min,360/480/600/720 +;pmu_bat_para1 ---battery indication at 3.1328V +;pmu_bat_para2 ---battery indication at 3.2736V +;pmu_bat_para3 ---battery indication at 3.4144V +;pmu_bat_para4 ---battery indication at 3.5552V +;pmu_bat_para5 ---battery indication at 3.6256V +;pmu_bat_para6 ---battery indication at 3.6608V +;pmu_bat_para7 ---battery indication at 3.6960V +;pmu_bat_para8 ---battery indication at 3.7312V +;pmu_bat_para9 ---battery indication at 3.7664V +;pmu_bat_para10 ---battery indication at 3.8016V +;pmu_bat_para11 ---battery indication at 3.8368V +;pmu_bat_para12 ---battery indication at 3.8720V +;pmu_bat_para13 ---battery indication at 3.9424V +;pmu_bat_para14 ---battery indication at 4.0128V +;pmu_bat_para15 ---battery indication at 4.0832V +;pmu_bat_para16 ---battery indication at 4.1536V +;pmu_usbvol ---set usb-ac limited voltage level,mV,4000/4100/4200/4300/4400/4500/4600/4700,0 - not limite +;pmu_usbcur ---set usb-ac limited voltage level,mA,100/500/900, 0 - not limite +;pmu_usbvol_pc ---set usb-pc limited voltage level,mV,4000/4100/4200/4300/4400/4500/4600/4700,0 - not limite +;pmu_usbcur_pc ---set usb-pc limited voltage level,mA,100/500/900, 0 - not limite +;pmu_pwroff_vol ---set protect voltage when system start up,mV,2600/2700/2800/2900/3000/3100/3200/3300 +;pmu_pwron_vol ---set protect voltage after system start up,mV,2600/2700/2800/2900/3000/3100/3200/3300 +;pmu_pekoff_time ---set pek off time,ms, 4000/6000/8000/10000 +;pmu_pekoff_en ---set pek off enable, 0:关闭,1:打开 +;pmu_peklong_time ---set pek pek long irq time,ms,1000/1500/2000/2500 +;pmu_pekon_time ---set pek on time,ms,128/1000/2000/3000 +;pmu_pwrok_time ---set pmu pwrok delay time,ms,8/64 +;pmu_pwrnoe_time ---set pmu n_oe power down delay time,ms,128/1000/2000/3000 +;pmu_intotp_en ---set pmu power down when overtempertur enable,0:关闭，1：打开 +;pmu_suspendpwroff_vol ---set pmu shutdown voltage when cpu is suspend and battery voltage is low +;pmu_batdeten ---set pmu battery detect enabled,0:关闭，1：打开 +;------------------------------------------------------------------------------- +[pmu_para] +pmu_used = 1 +pmu_twi_addr = 0x34 +pmu_twi_id = 0 +pmu_irq_id = 32 +pmu_battery_rdc = 100 +pmu_battery_cap = 3200 +pmu_init_chgcur = 300 +pmu_earlysuspend_chgcur = 600 +pmu_suspend_chgcur = 1000 +pmu_resume_chgcur = 300 +pmu_shutdown_chgcur = 1000 +pmu_init_chgvol = 4200 +pmu_init_chgend_rate = 15 +pmu_init_chg_enabled = 1 +pmu_init_adc_freq = 100 +pmu_init_adc_freqc = 100 +pmu_init_chg_pretime = 50 +pmu_init_chg_csttime = 720 + +pmu_bat_para1 = 0 +pmu_bat_para2 = 0 +pmu_bat_para3 = 0 +pmu_bat_para4 = 0 +pmu_bat_para5 = 5 +pmu_bat_para6 = 8 +pmu_bat_para7 = 11 +pmu_bat_para8 = 22 +pmu_bat_para9 = 33 +pmu_bat_para10 = 43 +pmu_bat_para11 = 50 +pmu_bat_para12 = 59 +pmu_bat_para13 = 71 +pmu_bat_para14 = 83 +pmu_bat_para15 = 92 +pmu_bat_para16 = 100 + +pmu_usbvol_limit = 1 +pmu_usbcur_limit = 0 +pmu_usbvol = 4000 +pmu_usbcur = 0 + +pmu_usbvol_pc = 4000 +pmu_usbcur_pc = 0 + +pmu_pwroff_vol = 3300 +pmu_pwron_vol = 2900 + +pmu_pekoff_time = 6000 +pmu_pekoff_en = 1 +pmu_peklong_time = 1500 +pmu_pekon_time = 1000 +pmu_pwrok_time = 64 +pmu_pwrnoe_time = 2000 +pmu_intotp_en = 1 + +pmu_used2 = 0 +pmu_adpdet = port:PH02<0> +pmu_init_chgcur2 = 400 +pmu_earlysuspend_chgcur2 = 600 +pmu_suspend_chgcur2 = 1200 +pmu_resume_chgcur2 = 400 +pmu_shutdown_chgcur2 = 1200 + +pmu_suspendpwroff_vol = 3500 + +pmu_batdeten = 0 + +[recovery_key] +key_min =4 +key_max =6 + +;---------------------------------------------------------------------------------- +; dvfs voltage-frequency table configuration +; +; max_freq: cpu maximum frequency, based on Hz, can not be more than 1008MHz +; min_freq: cpu minimum frequency, based on Hz, can not be less than 60MHz +; +; LV_count: count of LV_freq/LV_volt, must be < 16 +; +; LV1: core vdd is 1.45v if cpu frequency is (912Mhz, 1008Mhz] +; LV2: core vdd is 1.40v if cpu frequency is (864Mhz, 912Mhz] +; LV3: core vdd is 1.30v if cpu frequency is (792Mhz, 864Mhz] +; LV4: core vdd is 1.25v if cpu frequency is (720Mhz, 792Mhz] +; LV5: core vdd is 1.20v if cpu frequency is (624Mhz, 720Mhz] +; LV6: core vdd is 1.15v if cpu frequency is (528Mhz, 624Mhz] +; LV7: core vdd is 1.10v if cpu frequency is (312Mhz, 528Mhz] +; LV8: core vdd is 1.05v if cpu frequency is ( 60Mhz, 312Mhz] +; +;---------------------------------------------------------------------------------- +[dvfs_table] +max_freq = 912000000 +normal_freq = 720000000 +min_freq = 60000000 + +LV_count = 8 + +LV1_freq = 1008000000 +LV1_volt = 1450 + +LV2_freq = 912000000 +LV2_volt = 1400 + +LV3_freq = 864000000 +LV3_volt = 1300 + +LV4_freq = 792000000 +LV4_volt = 1250 + +LV5_freq = 720000000 +LV5_volt = 1200 + +LV6_freq = 624000000 +LV6_volt = 1150 + +LV7_freq = 528000000 +LV7_volt = 1100 + +LV8_freq = 312000000 +LV8_volt = 1050 + +[gpio_para] +gpio_used = 1 +gpio_num = 51 +gpio_pin_0 = port:PI19<1><2> +gpio_pin_1 = port:PI18<0><2> +gpio_pin_2 = port:PH07<0><2> +gpio_pin_3 = port:PH06<0><2> +gpio_pin_4 = port:PH08<0><2> +gpio_pin_5 = port:PB02<0><2> +gpio_pin_6 = port:PI03<0><2> +gpio_pin_7 = port:PH09<0><2> +gpio_pin_8 = port:PH10<0><2> +gpio_pin_9 = port:PH05<0><2> +gpio_pin_10 = port:PI10<0><2> +gpio_pin_11 = port:PI12<0><2> +gpio_pin_12 = port:PI13<0><2> +gpio_pin_13 = port:PI11<0><2> +gpio_pin_14 = port:PH11<0><2> +gpio_pin_15 = port:PH12<0><2> +gpio_pin_16 = port:PH13<0><2> +gpio_pin_17 = port:PH14<0><2> +gpio_pin_18 = port:PH15<1><0> +gpio_pin_19 = port:PH16<1><0> +gpio_pin_20 = port:PC19<0><2> +gpio_pin_21 = port:PC21<0><2> +gpio_pin_22 = port:PC22<0><2> +gpio_pin_23 = port:PC20<0><2> +gpio_pin_24 = port:PD10<3> +gpio_pin_25 = port:PD11<3> +gpio_pin_26 = port:PD12<3> +gpio_pin_27 = port:PD13<3> +gpio_pin_28 = port:PD14<3> +gpio_pin_29 = port:PD15<3> +gpio_pin_30 = port:PD16<3> +gpio_pin_31 = port:PD17<3> +gpio_pin_32 = port:PD18<3> +gpio_pin_33 = port:PD19<3> +gpio_pin_34 = port:PE04<3> +gpio_pin_35 = port:PE05<3> +gpio_pin_36 = port:PE06<3> +gpio_pin_37 = port:PE07<3> +gpio_pin_38 = port:PE08<3> +gpio_pin_39 = port:PE09<3> +gpio_pin_40 = port:PE10<3> +gpio_pin_41 = port:PE11<3> +gpio_pin_42 = port:PB19<2> +gpio_pin_43 = port:PB18<2> +gpio_pin_44 = port:PE02<3> +gpio_pin_45 = port:PE03<3> +gpio_pin_46 = port:PE00<3> +gpio_pin_47 = port:PE01<3> +gpio_pin_48 = port:PH26<1><0> +gpio_pin_49 = port:PH27<1><1> + +; usb_power_en +gpio_pin_50 = port:PD02<1><1> +gpio_pin_51 = port:PI19<0><1> + +[sb_pwm0] +pwm_gpio = port:PH06<1> + +[sb_pwm1] +pwm_gpio = port:PB02<2> + +[sb_pwm2] +pwm_gpio = port:PI03<2> + +[sb_pwm3] +pwm_gpio = port:PH05<1> + +[sb_pwm4] +pwm_gpio = port:PI10<1> + +[sb_pwm5] +pwm_gpio = port:PI12<1> + +[sb_keypad_para] +sb_key_used = 1 +key_num = 3 +; BACK ==> KEY_ESC +key_pin_0 = port:PH17<6><1><3> +key_code_0 = 1 +; MENU ==> KEY_SPACE +key_pin_1 = port:PH18<6><1><3> +key_code_1 = 57 +; HOME ==> KEY_ENTER +key_pin_2 = port:PH19<6><1><3> +key_code_2 = 28 + diff --git a/sunxi-boards/sys_config/a20/pcduino3b_lvds.fex b/sunxi-boards/sys_config/a20/pcduino3b_lvds.fex new file mode 100644 index 0000000..07eea4f --- /dev/null +++ b/sunxi-boards/sys_config/a20/pcduino3b_lvds.fex @@ -0,0 +1,1533 @@ +;A20 PAD application +;------------------------------------------------------------------------------- +; 说明： +; 1. 脚本中的字符串区分大小写，用户可以修改"="后面的数值，但是不要修改前面的字符串 +; 2. 新增主键和子键的名称必须控制在32个字符以内，不包括32个 +; 3. 所以的注释以“;”开始，单独占据一行 +; 4. 注释不可和配置项同行，例如：主键和子健后面不能添加任何形式的注释 +; +; gpio的描述形式：Port:端口+组内序号<功能分配><内部电阻状态><驱动能力><输出电平状态> +; 例如：port:PA0<0> +;------------------------------------------------------------------------------- + +[product] +version = "100" +machine = "pcduino3-v10" + +[platform] +eraseflag = 1 + +[target] +boot_clock = 912 +dcdc2_vol = 1400 +dcdc3_vol = 1250 +ldo2_vol = 3000 +ldo3_vol = 2800 +ldo4_vol = 2800 +power_start = 3 +storage_type = -1 + +[clock] +pll3 = 297 +pll4 = 300 +pll6 = 600 +pll7 = 297 +pll8 = 336 + +[card_boot] +logical_start = 40960 +sprite_gpio0 = port:PH15<1><0> +sprite_work_delay = 1000 +sprite_err_delay = 100 + +[card0_boot_para] +card_ctrl = 0 +card_high_speed = 1 +card_line = 4 +sdc_d1 = port:PF0<2><1> +sdc_d0 = port:PF1<2><1> +sdc_clk = port:PF2<2><1> +sdc_cmd = port:PF3<2><1> +sdc_d3 = port:PF4<2><1> +sdc_d2 = port:PF5<2><1> + +[card2_boot_para] +card_ctrl = 2 +card_high_speed = 1 +card_line = 4 +sdc_cmd = port:PC6<3><1> +sdc_clk = port:PC7<3><1> +sdc_d0 = port:PC8<3><1> +sdc_d1 = port:PC9<3><1> +sdc_d2 = port:PC10<3><1> +sdc_d3 = port:PC11<3><1> + +[twi_para] +twi_port = 0 +twi_scl = port:PB0<2> +twi_sda = port:PB1<2> + +[uart_para] +uart_debug_port = 0 +uart_debug_tx = port:PB22<2><1> +uart_debug_rx = port:PB23<2><1> + +[uart_force_debug] +uart_debug_port = 0 +uart_debug_tx =port:PF2<4><1> +uart_debug_rx =port:PF4<4><1> + +[jtag_para] +jtag_enable = 0 +jtag_ms = port:PB14<3> +jtag_ck = port:PB15<3> +jtag_do = port:PB16<3> +jtag_di = port:PB17<3> + +;--------------------------------------------------------------------------------------------------------- +; if 1 == standby_mode, then support super standby; +; else, support normal standby. +;--------------------------------------------------------------------------------------------------------- +[pm_para] +standby_mode = 0 + +;------------------------------------------------------------------------------- +;sdram configuration +;------------------------------------------------------------------------------- +[dram_para] +dram_baseaddr = 0x40000000 +dram_clk = 408 +dram_type = 3 +dram_rank_num = 0xffffffff +dram_chip_density = 0xffffffff +dram_io_width = 0xffffffff +dram_bus_width = 0xffffffff +dram_cas = 9 +dram_zq = 0x7a +dram_odt_en = 0 +dram_size = 0xffffffff +dram_tpr0 = 0x42d899b7 +dram_tpr1 = 0xa090 +dram_tpr2 = 0x22a00 +dram_tpr3 = 0x0 +dram_tpr4 = 0x0 +dram_tpr5 = 0x0 +dram_emr1 = 0x4 +dram_emr2 = 0x10 +dram_emr3 = 0x0 + +;------------------------------------------------------------------------------- +;Mali configuration +;------------------------------------------------------------------------------- +[mali_para] +mali_used = 1 +mali_clkdiv = 1 + +;------------------------------------------------------------------------------- +;Ethernet MAC configuration +;------------------------------------------------------------------------------- +[emac_para] +emac_used = 1 +emac_rxd3 = port:PA00<2> +emac_rxd2 = port:PA01<2> +emac_rxd1 = port:PA02<2> +emac_rxd0 = port:PA03<2> +emac_txd3 = port:PA04<2> +emac_txd2 = port:PA05<2> +emac_txd1 = port:PA06<2> +emac_txd0 = port:PA07<2> +emac_rxclk = port:PA08<2> +emac_rxerr = port:PA09<2> +emac_rxdV = port:PA10<2> +emac_mdc = port:PA11<2> +emac_mdio = port:PA12<2> +emac_txen = port:PA13<2> +emac_txclk = port:PA14<2> +emac_crs = port:PA15<2> +emac_col = port:PA16<2> +emac_reset = port:PA17<1> + + +;------------------------------------------------------------- +; GMAC configuration +;--------------------------------------------------------- +[gmac_para] +gmac_used = 1 +gmac_rxd3 = port:PA00<5><3> +gmac_rxd2 = port:PA01<5><3> +gmac_rxd1 = port:PA02<5><3> +gmac_rxd0 = port:PA03<5><3> +gmac_txd3 = port:PA04<5><3> +gmac_txd2 = port:PA05<5><3> +gmac_txd1 = port:PA06<5><3> +gmac_txd0 = port:PA07<5><3> +gmac_rxclk = port:PA08<5><3> +gmac_rxerr = port:PA09<0><3> +gmac_rxctl = port:PA10<5><3> +gmac_mdc = port:PA11<5><3> +gmac_mdio = port:PA12<5><3> +gmac_txctl = port:PA13<5><3> +gmac_txclk = port:PA14<0><3> +gmac_txck = port:PA15<5><3> +gmac_clkin = port:PA16<5><3> +gmac_txerr = port:PA17<0><3> + +;------------------------------------------------------------------------------- +;i2c configuration +;------------------------------------------------------------------------------- +[twi0_para] +twi0_used = 1 +twi0_scl = port:PB0<2> +twi0_sda = port:PB1<2> + +[twi1_para] +twi1_used = 1 +twi1_scl = port:PB18<2> +twi1_sda = port:PB19<2> + +[twi2_para] +twi2_used = 1 +twi2_scl = port:PB20<2> +twi2_sda = port:PB21<2> + +;------------------------------------------------------------------------------- +;uart configuration +;uart_type --- 2 (2 wire), 4 (4 wire), 8 (8 wire, full function) +;------------------------------------------------------------------------------- +[uart_para0] +uart_used = 1 +uart_port = 0 +uart_type = 2 +uart_tx = port:PB22<2><1> +uart_rx = port:PB23<2><1> + +[uart_para1] +uart_used = 0 +uart_port = 1 +uart_type = 8 +uart_tx = port:PA10<4><1> +uart_rx = port:PA11<4><1> +uart_rts = port:PA12<4><1> +uart_cts = port:PA13<4><1> +uart_dtr = port:PA14<4><1> +uart_dsr = port:PA15<4><1> +uart_dcd = port:PA16<4><1> +uart_ring = port:PA17<4><1> + +[uart_para2] +uart_used = 1 +uart_port = 2 +uart_type = 4 +uart_tx = port:PI18<0><2> +uart_rx = port:PI19<1><2> +uart_rts = port:PI16<3><1> +uart_cts = port:PI17<3><1> + +[uart_para3] +uart_used = 0 +uart_port = 3 +uart_type = 4 +uart_tx = port:PH00<4><1> +uart_rx = port:PH01<4><1> +uart_rts = port:PH02<4><1> +uart_cts = port:PH03<4><1> + +[uart_para4] +uart_used = 0 +uart_port = 4 +uart_type = 2 +uart_tx = port:PH04<4><1> +uart_rx = port:PH05<4><1> + +[uart_para5] +uart_used = 0 +uart_port = 5 +uart_type = 2 +uart_tx = port:PH06<4><1> +uart_rx = port:PH07<4><1> + +[uart_para6] +uart_used = 0 +uart_port = 6 +uart_type = 2 +uart_tx = port:PA12<3><1> +uart_rx = port:PA13<3><1> + +[uart_para7] +uart_used = 0 +uart_port = 7 +uart_type = 2 +uart_tx = port:PA14<3><1> +uart_rx = port:PA15<3><1> + +;------------------------------------------------------------------------------- +;spi configuration +;------------------------------------------------------------------------------- +[spi0_para] +spi_used = 1 +spi_cs_bitmap = 1 +spi_cs0 = port:PI10<0><2> +spi_cs1 = port:PI14<2> +spi_sclk = port:PI11<0><2> +spi_mosi = port:PI12<0><2> +spi_miso = port:PI13<0><2> + +[spi1_para] +spi_used = 0 +spi_cs_bitmap = 1 +spi_cs0 = port:PA00<3> +spi_cs1 = port:PA04<3> +spi_sclk = port:PA01<3> +spi_mosi = port:PA02<3> +spi_miso = port:PA03<3> + +[spi2_para] +spi_used = 1 +spi_cs_bitmap = 1 +spi_cs0 = port:PC19<0><2> +spi_cs1 = port:PB13<2> +spi_sclk = port:PC20<0><2> +spi_mosi = port:PC21<0><2> +spi_miso = port:PC22<0><2> + +[spi3_para] +spi_used = 0 +spi_cs_bitmap = 1 +spi_cs0 = port:PA05<3> +spi_cs1 = port:PA09<3> +spi_sclk = port:PA06<3> +spi_mosi = port:PA07<3> +spi_miso = port:PA08<3> + +[spi_devices] +spi_dev_num = 2 + +[spi_board0] +modalias = "spidev" +max_speed_hz = 12000000 +bus_num = 0 +chip_select = 0 +mode = 3 +full_duplex = 0 +manual_cs = 0 + +[spi_board1] +modalias = "spidev" +max_speed_hz = 12000000 +bus_num = 2 +chip_select = 0 +mode = 0 +full_duplex = 0 +manual_cs = 0 + +;---------------------------------------------------------------------------------- +;resistance tp configuration +;---------------------------------------------------------------------------------- +[rtp_para] +rtp_used = 1 +rtp_screen_size = 5 +rtp_regidity_level = 5 +rtp_press_threshold_enable = 0 +rtp_press_threshold = 0x1f40 +rtp_sensitive_level = 0xf +rtp_exchange_x_y_flag = 0 +;------------------------------------------------------------------------------- +;capacitor tp configuration +;external int function +;wakeup output function +;notice: +; tp_int_port & tp_io_port use the same port +;------------------------------------------------------------------------------- +[ctp_para] +ctp_used = 1 +ctp_twi_id = 2 +ctp_twi_name = "gslX680" +ctp_screen_max_x = 1024 +ctp_screen_max_y = 600 +ctp_revert_x_flag = 0 +ctp_revert_y_flag = 0 +ctp_exchange_x_y_flag = 0 + +ctp_int_port = port:PH10<6> +ctp_wakeup = + +;------------------------------------------------------------------------------- +;touch key configuration +;------------------------------------------------------------------------------- +[tkey_para] +tkey_used = 0 +tkey_twi_id = 2 +tkey_twi_addr = 0x62 +tkey_int = port:PI13<6> + +;------------------------------------------------------------------------------- +;motor configuration +;------------------------------------------------------------------------------- +[motor_para] +motor_used = 0 +motor_shake = port:PB03<1><1> + +;------------------------------------------------------------------------------- +;nand flash configuration +;------------------------------------------------------------------------------- +[nand_para] +nand_used = 1 +nand_we = port:PC00<2> +nand_ale = port:PC01<2> +nand_cle = port:PC02<2> +nand_ce1 = port:PC03<2> +nand_ce0 = port:PC04<2> +nand_nre = port:PC05<2> +nand_rb0 = port:PC06<2> +nand_rb1 = port:PC07<2> +nand_d0 = port:PC08<2> +nand_d1 = port:PC09<2> +nand_d2 = port:PC10<2> +nand_d3 = port:PC11<2> +nand_d4 = port:PC12<2> +nand_d5 = port:PC13<2> +nand_d6 = port:PC14<2> +nand_d7 = port:PC15<2> +nand_wp = port:PC16<2> +nand_ce2 = port:PC17<2> +nand_ce3 = port:PC18<2> +nand_ce4 = +nand_ce5 = +nand_ce6 = +nand_ce7 = +nand_spi = port:PC23<3> +nand_ndqs = port:PC24<2> +good_block_ratio = 0 + +;------------------------------------------------------------------------------- +;disp init configuration +; +;disp_mode (0:screen0 1:screen1 2:two_diff_screen_diff_contents +; 3:two_same_screen_diff_contets 4:two_diff_screen_same_contents) +;screenx_output_type (0:none; 1:lcd; 2:tv; 3:hdmi; 4:vga) +;screenx_output_mode (used for tv/hdmi output, 0:480i 1:576i 2:480p 3:576p 4:720p50 5:720p60 6:1080i50 7:1080i60 8:1080p24 9:1080p50 10:1080p60 11:pal 14:ntsc) +;screenx_output_mode (used for vga output, 0:1680*1050 1:1440*900 2:1360*768 3:1280*1024 4:1024*768 5:800*600 6:640*480 10:1920*1080 11:1280*720) +;fbx format (4:RGB655 5:RGB565 6:RGB556 7:ARGB1555 8:RGBA5551 9:RGB888 10:ARGB8888 12:ARGB4444) +;fbx pixel sequence (0:ARGB 1:BGRA 2:ABGR 3:RGBA) --- 0 for linux, 2 for android +;lcd0_bright (lcd0 init bright,the range:[0,256],default:197 +;lcd1_bright (lcd1 init bright,the range:[0,256],default:197 +;------------------------------------------------------------------------------- + +[boot_disp] +output_type = 1 +output_mode = 4 + +[disp_init] +disp_init_enable = 1 +disp_mode = 1 + +screen0_output_type = 1 +screen0_output_mode = 4 + +screen1_output_type = 1 +screen1_output_mode = 4 + +fb0_framebuffer_num = 2 +fb0_format = 10 +fb0_pixel_sequence = 0 +fb0_scaler_mode_enable = 1 +fb0_width = 0 +fb0_height = 0 + +fb1_framebuffer_num = 2 +fb1_format = 10 +fb1_pixel_sequence = 0 +fb1_scaler_mode_enable = 0 +fb1_width = 0 +fb1_height = 0 + +lcd0_backlight = 197 +lcd1_backlight = 197 + +lcd0_bright = 50 +lcd0_contrast = 50 +lcd0_saturation = 57 +lcd0_hue = 50 + +lcd1_bright = 50 +lcd1_contrast = 50 +lcd1_saturation = 57 +lcd1_hue = 50 + +;------------------------------------------------------------------------------- +;lcd0 configuration + +;lcd_dclk_freq: in MHZ unit +;lcd_pwm_freq: in HZ unit +;lcd_if: 0:hv(sync+de); 1:8080; 2:ttl; 3:lvds; 4:hv2dsi +;lcd_width: width of lcd in mm +;lcd_height: height of lcd in mm +;lcd_hbp: hsync back porch +;lcd_ht: hsync total cycle +;lcd_vbp: vsync back porch +;lcd_vt: vysnc total cycle *2 +;lcd_hv_if: 0:hv parallel 1:hv serial +;lcd_hv_smode: 0:RGB888 1:CCIR656 +;lcd_hv_s888_if serial RGB format +;lcd_hv_syuv_if: serial YUV format +;lcd_hspw: hsync plus width +;lcd_vspw: vysnc plus width +;lcd_lvds_ch: 0:single channel; 1:dual channel +;lcd_lvds_mode: 0:NS mode; 1:JEIDA mode +;lcd_lvds_bitwidth: 0:24bit; 1:18bit +;lcd_lvds_io_cross: 0:normal; 1:pn cross +;lcd_cpu_if: 0:18bit; 1:16bit mode0; 2:16bit mode1; 3:16bit mode2; 4:16bit mode3; 5:9bit; 6:8bit 256K; 7:8bit 65K +;lcd_frm: 0:disable; 1:enable rgb666 dither; 2:enable rgb656 dither + +;lcd_gpio_0: SCL +;lcd_gpio_1 SDA +;------------------------------------------------------------------------------- +[lcd0_para] +lcd_used = 0 + +lcd_x = 1024 +lcd_y = 600 +lcd_width = 0 +lcd_height = 0 +lcd_dclk_freq = 51 +lcd_pwm_not_used = 1 +lcd_pwm_ch = 0 +lcd_pwm_freq = 10000 +lcd_pwm_pol = 0 +lcd_if = 3 +lcd_hbp = 310 +lcd_ht = 1340 +lcd_vbp = 30 +lcd_vt = 1268 +lcd_vspw = 0 +lcd_hspw = 0 +lcd_hv_if = 0 +lcd_hv_smode = 0 +lcd_hv_s888_if = 0 +lcd_hv_syuv_if = 0 +lcd_lvds_ch = 0 +lcd_lvds_mode = 0 +lcd_lvds_bitwidth = 0 +lcd_lvds_io_cross = 0 +lcd_cpu_if = 0 +lcd_frm = 0 +lcd_io_cfg0 = 0x10000000 +lcd_gamma_correction_en = 0 +lcd_gamma_tbl_0 = 0x00000000 +lcd_gamma_tbl_1 = 0x00010101 +lcd_gamma_tbl_255 = 0x00ffffff + +lcd_bl_en_used = 0 +lcd_bl_en = port:PH07<1><0><1> + +lcd_power_used = 0 +lcd_power = port:PH08<1><0><1> + +lcd_pwm_used = 0 +lcd_pwm = port:PB02<2><0> + +lcdd0 = port:PD00<3> +lcdd1 = port:PD01<3> +lcdd2 = port:PD02<3> +lcdd3 = port:PD03<3> +lcdd4 = port:PD04<3> +lcdd5 = port:PD05<3> +lcdd6 = port:PD06<3> +lcdd7 = port:PD07<3> +lcdd8 = port:PD08<3> +lcdd9 = port:PD09<3> + +;---------------------------------------------------------------------------------- +;lcd1 configuration + +;lcd_dclk_freq: in MHZ unit +;lcd_pwm_freq: in HZ unit +;lcd_if: 0:hv(sync+de); 1:8080; 2:ttl; 3:lvds +;lcd_hbp: hsync back porch +;lcd_ht: hsync total cycle +;lcd_vbp: vsync back porch +;lcd_vt: vysnc total cycle *2 +;lcd_hv_if: 0:hv parallel 1:hv serial +;lcd_hv_smode: 0:RGB888 1:CCIR656 +;lcd_hv_s888_if serial RGB format +;lcd_hv_syuv_if: serial YUV format +;lcd_hspw: hsync plus width +;lcd_vspw: vysnc plus width +;lcd_lvds_ch: 0:single channel; 1:dual channel +;lcd_lvds_mode: 0:NS mode; 1:JEIDA mode +;lcd_lvds_bitwidth: 0:24bit; 1:18bit +;lcd_lvds_io_cross: 0:normal; 1:pn cross +;lcd_cpu_if: 0:18bit; 1:16bit mode0; 2:16bit mode1; 3:16bit mode2; 4:16bit mode3; 5:9bit; 6:8bit 256K; 7:8bit 65K +;lcd_frm: 0:disable; 1:enable rgb666 dither; 2:enable rgb656 dither + +;lcd_gpio_0: SCL +;lcd_gpio_1 SDA +;---------------------------------------------------------------------------------- +[lcd1_para] +lcd_used = 1 + +lcd_x = 1024 +lcd_y = 600 +lcd_width = 0 +lcd_height = 0 +lcd_dclk_freq = 51 +lcd_pwm_not_used = 0 +lcd_pwm_ch = 0 +lcd_pwm_freq = 10000 +lcd_pwm_pol = 0 +lcd_if = 3 +lcd_hbp = 310 +lcd_ht = 1340 +lcd_vbp = 30 +lcd_vt = 1268 +lcd_vspw = 0 +lcd_hspw = 0 +lcd_hv_if = 0 +lcd_hv_smode = 0 +lcd_hv_s888_if = 0 +lcd_hv_syuv_if = 0 +lcd_lvds_ch = 0 +lcd_lvds_mode = 0 +lcd_lvds_bitwidth = 0 +lcd_lvds_io_cross = 0 +lcd_cpu_if = 0 +lcd_frm = 0 +lcd_io_cfg0 = 0 +lcd_gamma_correction_en = 0 +lcd_gamma_tbl_0 = 0x00000000 +lcd_gamma_tbl_1 = 0x00010101 +lcd_gamma_tbl_255 = 0x00ffffff + +lcd_bl_en_used = 1 +lcd_bl_en = port:PH07<1><1> + +lcd_power_used = 1 +lcd_power = port:PH08<1><1> + +lcd_pwm_used = 1 +lcd_pwm = port:PH06<1><0> + +lcd_gpio_0 = +lcd_gpio_1 = +lcd_gpio_2 = +lcd_gpio_3 = + +lcdd10 = port:PD10<3> +lcdd11 = port:PD11<3> +lcdd12 = port:PD12<3> +lcdd13 = port:PD13<3> +lcdd14 = port:PD14<3> +lcdd15 = port:PD15<3> +lcdd16 = port:PD16<3> +lcdd17 = port:PD17<3> +lcdd18 = port:PD18<3> +lcdd19 = port:PD19<3> + +;------------------------------------------------------------------------------- +;tv out dac configuration +;dacx_src: 0:composite; 1:luma; 2:chroma; 4:Y; 5:Pb; 6: Pr; 7:none +;------------------------------------------------------------------------------- +[tv_out_dac_para] +dac_used = 1 +dac0_src = 4 +dac1_src = 5 +dac2_src = 6 +dac3_src = 0 + +;---------------------------------------------------------------------------------- +;hdmi configuration +;---------------------------------------------------------------------------------- +[hdmi_para] +hdmi_used = 1 +hdcp_enable = 0 + +[i2s2_para] +i2s_channel = 2 +i2s_master = 4 +i2s_select = 1 +audio_format = 1 +signal_inversion = 1 +over_sample_rate = 256 +sample_resolution = 16 +word_select_size = 32 +pcm_sync_period = 256 +msb_lsb_first = 0 +sign_extend = 0 +slot_index = 0 +slot_width = 16 +frame_width = 1 +tx_data_mode = 0 +rx_data_mode = 0 +;i2s_mclk = port:PB05<2><1> +;i2s_bclk = port:PB06<2><1> +;i2s_lrclk = port:PB07<2><1> +;i2s_dout0 = port:PB08<2><1> +;i2s_dout1 = +;i2s_dout2 = +;i2s_dout3 = +;i2s_din = port:PB12<2><1> + + +[camera_list_para] +camera_list_para_used = 1 +ov7670 = 0 +gc0308 = 1 +gt2005 = 0 +hi704 = 0 +sp0838 = 0 +mt9m112 = 0 +mt9m113 = 0 +ov2655 = 0 +hi253 = 0 +gc0307 = 0 +mt9d112 = 0 +ov5640 = 1 +gc2015 = 0 +ov2643 = 0 +gc0329 = 0 +gc0309 = 0 +tvp5150 = 0 +s5k4ec = 0 +ov5650_mv9335 = 0 +siv121d = 0 + +;-------------------------------------------------------------------------------- +;csi gpio configuration +;csi_if: 0:hv_8bit 1:hv_16bit 2:hv_24bit 3:bt656 1ch 4:bt656 2ch 5:bt656 4ch +;csi_mode: 0:sample one csi to one buffer 1:sample two csi to one buffer +;csi_dev_qty: The quantity of devices linked to csi interface +;csi_vflip: flip in vertical direction 0:disable 1:enable +;csi_hflip: flip in horizontal direction 0:disable 1:enable +;csi_stby_mode: 0:not shut down power at standby 1:shut down power at standby +;csi_iovdd: camera module io power , pmu power supply +;csi_avdd: camera module analog power , pmu power supply +;csi_dvdd: camera module core power , pmu power supply +;pmu_ldo3: fill "axp20_pll" +;pmu_ldo4: fill "axp20_hdmi" +;fill "" when not using any pmu power supply +;csi_flash_pol: the active polority of the flash light IO 0:low active 1:high active +;-------------------------------------------------------------------------------- + +[csi0_para] +csi_used = 1 + +csi_dev_qty = 1 +csi_stby_mode = 0 +csi_mname = "gc2035" +csi_if = 0 +csi_iovdd = "" +csi_avdd = "" +csi_dvdd = "" +csi_vol_iovdd = +csi_vol_dvdd = +csi_vol_avdd = +csi_vflip = 0 +csi_hflip = 0 +csi_flash_pol = 0 +csi_facing = 0 + +csi_twi_id = 1 +csi_twi_addr = 0x78 +csi_pck = port:PE00<3> +csi_ck = port:PE01<3> +csi_hsync = port:PE02<3> +csi_vsync = port:PE03<3> +csi_d0 = port:PE04<3> +csi_d1 = port:PE05<3> +csi_d2 = port:PE06<3> +csi_d3 = port:PE07<3> +csi_d4 = port:PE08<3> +csi_d5 = port:PE09<3> +csi_d6 = port:PE10<3> +csi_d7 = port:PE11<3> +csi_reset = port:PH27<1><1> +csi_power_en = port:PH26<1><0> +csi_stby = + +[csi1_para] +csi_used = 0 + +csi_dev_qty = 1 +csi_stby_mode = 0 +csi_mname = "gc0308" +csi_if = 0 +csi_iovdd = "" +csi_avdd = "" +csi_dvdd = "" +csi_vol_iovdd = +csi_vol_dvdd = +csi_vol_avdd = +csi_vflip = 0 +csi_hflip = 0 +csi_flash_pol = 0 +csi_facing = 1 + +csi_twi_id = 1 +csi_twi_addr = 0x42 +csi_pck = port:PG00<3> +csi_ck = port:PG01<3> +csi_hsync = port:PG02<3> +csi_vsync = port:PG03<3> +csi_d0 = port:PG04<3> +csi_d1 = port:PG05<3> +csi_d2 = port:PG06<3> +csi_d3 = port:PG07<3> +csi_d4 = port:PG08<3> +csi_d5 = port:PG09<3> +csi_d6 = port:PG10<3> +csi_d7 = port:PG11<3> +csi_reset = port:PH14<1><0> +csi_power_en = +csi_stby = port:PH17<1><0> + +;------------------------------------------------------------------------------- +;tv configuration +; +;------------------------------------------------------------------------------- +[tvout_para] +tvout_used = 1 +tvout_channel_num = 1 + +[tvin_para] +tvin_used = 0 +tvin_channel_num = 4 + + +;------------------------------------------------------------------------------- +;sata configuration +; +;------------------------------------------------------------------------------- +[sata_para] +sata_used = 1 +sata_power_en = port:PH02<1><1> + + +;------------------------------------------------------------------------------- +; SDMMC PINS MAPPING +; ------------------------------------------------------------------------------ +; Config Guide +; sdc_used: 1-enable card, 0-disable card +; sdc_detmode: card detect mode +; 1-detect card by gpio polling +; 2-detect card by gpio irq(must use IO with irq function) +; 3-no detect, always in for boot card +; 4-manually insert and remove by /proc/driver/sunxi-mmc.x/insert +; sdc_buswidth: card bus width, 1-1bit, 4-4bit, 8-8bit +; sdc_use_wp: 1-with write protect IO, 0-no write protect IO +; sdc_isio: for sdio card +; sdc_regulator: power control. +; other: GPIO Mapping configuration +; ------------------------------------------------------------------------------ +; Note: +; 1 if detmode=2, sdc_det's config=6 +; else if detmode=1, sdc_det's config=0 +; else sdc_det IO is not necessary +; 2 if the customer wants to support UHS-I and HS200 features, he must provide +; an independent power supply for the card. This is only used in platforms +; that supports SD3.0 cards and eMMC4.4+ flashes +;------------------------------------------------------------------------------- +[mmc0_para] +sdc_used = 1 +sdc_detmode = 1 +sdc_buswidth = 4 +sdc_clk = port:PF02<2><1><2> +sdc_cmd = port:PF03<2><1><2> +sdc_d0 = port:PF01<2><1><2> +sdc_d1 = port:PF00<2><1><2> +sdc_d2 = port:PF05<2><1><2> +sdc_d3 = port:PF04<2><1><2> +sdc_det = port:PH1<0><1> +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 0 +sdc_regulator = "none" + +[mmc1_para] +sdc_used = 0 +sdc_detmode = 4 +sdc_buswidth = 4 +sdc_clk = port:PG00<2><1><2> +sdc_cmd = port:PG01<2><1><2> +sdc_d0 = port:PG02<2><1><2> +sdc_d1 = port:PG03<2><1><2> +sdc_d2 = port:PG04<2><1><2> +sdc_d3 = port:PG05<2><1><2> +sdc_det = +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 0 +sdc_regulator = "none" + +[mmc2_para] +sdc_used = 0 +sdc_detmode = 3 +sdc_buswidth = 4 +sdc_cmd = port:PC06<3><1><2> +sdc_clk = port:PC07<3><1><2> +sdc_d0 = port:PC08<3><1><2> +sdc_d1 = port:PC09<3><1><2> +sdc_d2 = port:PC10<3><1><2> +sdc_d3 = port:PC11<3><1><2> +sdc_det = +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 0 +sdc_regulator = "none" + +[mmc3_para] +sdc_used = 0 +sdc_detmode = 4 +sdc_buswidth = 4 +sdc_cmd = port:PI04<2><1><2> +sdc_clk = port:PI05<2><1><2> +sdc_d0 = port:PI06<2><1><2> +sdc_d1 = port:PI07<2><1><2> +sdc_d2 = port:PI08<2><1><2> +sdc_d3 = port:PI09<2><1><2> +sdc_det = +sdc_use_wp = 0 +sdc_wp = +sdc_isio = 1 +sdc_regulator = "none" + +; ------------------------------------------------------------------------------ +; memory stick configuration +;------------------------------------------------------------------------------- +[ms_para] +ms_used = 0 +ms_bs = port:PH06<5> +ms_clk = port:PH07<5> +ms_d0 = port:PH08<5> +ms_d1 = port:PH09<5> +ms_d2 = port:PH10<5> +ms_d3 = port:PH11<5> +ms_det = + +; ------------------------------------------------------------------------------ +; sim card configuration +;------------------------------------------------------------------------------- +[smc_para] +smc_used = 0 +smc_rst = port:PH13<5> +smc_vppen = port:PH14<5> +smc_vppp = port:PH15<5> +smc_det = port:PH16<5> +smc_vccen = port:PH17<5> +smc_sck = port:PH18<5> +smc_sda = port:PH19<5> + +;------------------------------------------------------------------------------- +;ps2 configuration +;------------------------------------------------------------------------------- +[ps2_0_para] +ps2_used = 0 +ps2_scl = port:PI20<2><1> +ps2_sda = port:PI21<2><1> + +[ps2_1_para] +ps2_used = 0 +ps2_scl = port:PI14<3><1> +ps2_sda = port:PI15<3><1> + +;------------------------------------------------------------------------------- +;can bus configuration +;------------------------------------------------------------------------------- +[can_para] +can_used = 0 +can_tx = port:PA16<3> +can_rx = port:PA17<3> + +;------------------------------------------------------------------------------- +;key matrix +;------------------------------------------------------------------------------- +[keypad_para] +kp_used = 0 +kp_in_size = 8 +kp_out_size = 8 +kp_in0 = port:PH08<4><1> +kp_in1 = port:PH09<4><1> +kp_in2 = port:PH10<4><1> +kp_in3 = port:PH11<4><1> +kp_in4 = port:PH14<4><1> +kp_in5 = port:PH15<4><1> +kp_in6 = port:PH16<4><1> +kp_in7 = port:PH17<4><1> +kp_out0 = port:PH18<4><1> +kp_out1 = port:PH19<4><1> +kp_out2 = port:PH22<4><1> +kp_out3 = port:PH23<4><1> +kp_out4 = port:PH24<4><1> +kp_out5 = port:PH25<4><1> +kp_out6 = port:PH26<4><1> +kp_out7 = port:PH27<4><1> + + +;------------------------------------------------------------------------------- +;[usbc0]：控制器0的配置。 +;usb_used：USB使能标志。置1，表示系统中USB模块可用,置0,则表示系统USB禁用。 +;usb_port_type：USB端口的使用情况。 0：device only;1：host only;2：OTG +;usb_detect_type：USB端口的检查方式。0：不做检测;1：vbus/id检查;2：id/dpdm检查 +;usb_id_gpio：USB ID pin脚配置。具体请参考gpio配置说明。 +;usb_det_vbus_gpio：USB DET_VBUS pin脚配置。具体请参考gpio配置说明。 +;usb_drv_vbus_gpio：USB DRY_VBUS pin脚配置。具体请参考gpio配置说明。 +;usb_det_vbus_gpio: "axp_ctrl",表示axp 提供 +;usb_restrict_gpio usb限流控制pin +;usb_restric_flag: usb限流标置 +;------------------------------------------------------------------------------- +;------------------------------------------------------------------------------- +;--- USB0控制标志 +;------------------------------------------------------------------------------- +[usbc0] +usb_used = 1 +usb_port_type = 0 +usb_detect_type = 0 +usb_id_gpio = port:PH04<0><1> +usb_det_vbus_gpio = "axp_ctrl" +usb_drv_vbus_gpio = port:PB09<1><0><0> +;usb_restrict_gpio = port:PH00<1><0><0> +usb_host_init_state = 0 +usb_restric_flag = 0 +usb_restric_voltage = 3550000 +usb_restric_capacity= 5 + +;------------------------------------------------------------------------------- +;--- USB1控制标志 +;------------------------------------------------------------------------------ +[usbc1] +usb_used = 1 +usb_port_type = 1 +usb_detect_type = 0 +usb_drv_vbus_gpio = port:PH11<1><0><0> +usb_restrict_gpio = +usb_host_init_state = 1 +usb_restric_flag = 0 + +;------------------------------------------------------------------------------ +;--- USB2控制标志 +;------------------------------------------------------------------------------ +[usbc2] +usb_used = 1 +usb_port_type = 1 +usb_detect_type = 0 +usb_drv_vbus_gpio = port:PH03<1><0><0> +usb_restrict_gpio = + +usb_host_init_state = 1 +usb_restric_flag = 0 + +;-------------------------------- +;--- USB Device +;-------------------------------- +[usb_feature] +vendor_id = 0x18D1 +mass_storage_id = 0x0001 +adb_id = 0x0002 + +manufacturer_name = "USB Developer" +product_name = "Android" +serial_number = "20080411" + +[msc_feature] +vendor_name = "USB 2.0" +product_name = "USB Flash Driver" +release = 100 +luns = 1 + +;------------------------------------------------------------------------------- +; G sensor configuration +; gs_twi_id --- TWI ID for controlling Gsensor (0: TWI0, 1: TWI1, 2: TWI2) +;------------------------------------------------------------------------------- +[gsensor_para] +gsensor_used = 0 +gsensor_twi_id = 1 +gsensor_int1 = +gsensor_int2 = + +;------------------------------------------------------------------------------- +; gps gpio configuration +; gps_spi_id --- the index of SPI controller. 0: SPI0, 1: SPI1, 2: SPI2, 15: no SPI used +; gps_spi_cs_num --- the chip select number of SPI controller. 0: SPI CS0, 1: SPI CS1 +; gps_lradc --- the lradc number for GPS used. 0 and 1 is valid, set 2 if not use lradc +;------------------------------------------------------------------------------- +[gps_para] +gps_used = 0 +gps_spi_id = 2 +gps_spi_cs_num = 0 +gps_lradc = 1 +gps_clk = port:PI00<2> +gps_sign = port:PI01<2> +gps_mag = port:PI02<2> +gps_vcc_en = port:PC22<1><0> +gps_osc_en = port:PI14<1><0> +gps_rx_en = port:PI15<1><0> + +;-------------------------------------------------------------------------------- +;wifi configuration +;wifi_sdc_id --- 0- SDC0, 1- SDC1, 2- SDC2, 3- SDC3 +;wifi_usbc_id --- 0- USB0, 1- USB1, 2- USB2 +;wifi_usbc_type -- 1- EHCI(speed 2.0), 2- OHCI(speed 1.0) +;wifi_mod_sel --- 0- none, 1- bcm40181, 2- bcm40183(wifi+bt), +; 3 - rtl8723as(wifi+bt), 4- rtl8189es(SM89E00), +; 5 - rtl8192cu, 6 - rtl8188eu, 7 - ap6210 +;-------------------------------------------------------------------------------- +[wifi_para] +wifi_used = 1 +wifi_sdc_id = 3 +wifi_usbc_id = 2 +wifi_usbc_type = 1 +wifi_mod_sel = 7 +wifi_power = "" + +; 1 - bcm40181 sdio wifi gpio config +;bcm40181_shdn = port:PH09<1><0> +;bcm40181_host_wake = port:PH10<0><0> + +; 2 - bcm40183 sdio wifi gpio config +;bcm40183_wl_regon = port:PH09<1><0> +;bcm40183_wl_host_wake = port:PH10<0><0> +;bcm40183_bt_rst = port:PB05<1><0> +;bcm40183_bt_regon = port:PB05<1><0> +;bcm40183_bt_wake = port:PI20<1><0> +;bcm40183_bt_host_wake = port:PI21<0><0> + +; 3 - rtl8723as sdio wifi + bt gpio config +rtk_rtl8723as_wl_dis = port:PH09<1><0> +rtk_rtl8723as_bt_dis = port:PB05<1><0> +rtk_rtl8723as_wl_host_wake = port:PH10<0><0> +rtk_rtl8723as_bt_host_wake = port:PI21<0><0> + +; 4 - rtl8189es sdio wifi gpio config +;rtl8189es_shdn = port:PH09<1><0> +;rtl8189es_wakeup = port:PH10<1><1> + +; 5 - rtl8192cu usb wifi + +; 6 - rtl8188eu usb wifi + +; 7 - ap6210 sdio wifi + bt gpio config +ap6xxx_wl_regon = port:PH09<1><0> +ap6xxx_wl_host_wake = port:PH10<0><0> +ap6xxx_bt_regon = port:PB05<1><0> +ap6xxx_bt_wake = port:PI20<1><0> +ap6xxx_bt_host_wake = port:PI21<0><0> + + +[usb_wifi_para] +usb_wifi_used = 0 +usb_wifi_usbc_num = 2 + +;------------------------------------------------------------------------------- +;3G configuration +;------------------------------------------------------------------------------- +[3g_para] +3g_used = 0 +3g_usbc_num = 2 +3g_uart_num = 0 +3g_pwr = +3g_wakeup = +3g_int = + +;------------------------------------------------------------------------------- +;gyroscope +;------------------------------------------------------------------------------- +[gy_para] +gy_used = 0 +gy_twi_id = 1 +gy_twi_addr = 0x00 +gy_int1 = port:PH18<6><1> +gy_int2 = port:PH19<6><1> + +;------------------------------------------------------------------------------- +;light sensor +;------------------------------------------------------------------------------- +[ls_para] +ls_used = 0 +ls_twi_id = 1 +ls_twi_addr = 0x00 +ls_int = port:PH20<6><1> + +;------------------------------------------------------------------------------- +;compass +;------------------------------------------------------------------------------- +[compass_para] +compass_used = 0 +compass_twi_id = 1 +compass_twi_addr = 0x00 +compass_int = port:PI13<6><1> + +;------------------------------------------------------------------------------- +;blue tooth +;bt_used ---- blue tooth used (0- no used, 1- used) +;bt_uard_id ---- uart index +;------------------------------------------------------------------------------- +[bt_para] +bt_used = 0 +bt_uart_id = 2 +bt_wakeup = port:PI20<1> +bt_gpio = port:PI21<1> +bt_rst = port:PB05<1> + +;-------------------------------------------------------------------------------- +;i2s_master:1: SND_SOC_DAIFMT_CBM_CFM(codec clk & FRM master) use +; 2: SND_SOC_DAIFMT_CBS_CFM(codec clk slave & FRM master) not use +; 3: SND_SOC_DAIFMT_CBM_CFS(codec clk master & frame slave) not use +; 4: SND_SOC_DAIFMT_CBS_CFS(codec clk & FRM slave) use +;i2s_select:0 is pcm.1 is i2s +;audio_format: 1:SND_SOC_DAIFMT_I2S(standard i2s format). use +; 2:SND_SOC_DAIFMT_RIGHT_J(right justfied format). +; 3:SND_SOC_DAIFMT_LEFT_J(left justfied format) +; 4:SND_SOC_DAIFMT_DSP_A(pcm. MSB is available on 2nd BCLK rising edge after LRC rising edge). use +; 5:SND_SOC_DAIFMT_DSP_B(pcm. MSB is available on 1nd BCLK rising edge after LRC rising edge) +;signal_inversion:1:SND_SOC_DAIFMT_NB_NF(normal bit clock + frame) use +; 2:SND_SOC_DAIFMT_NB_IF(normal BCLK + inv FRM) +; 3:SND_SOC_DAIFMT_IB_NF(invert BCLK + nor FRM) use +; 4:SND_SOC_DAIFMT_IB_IF(invert BCLK + FRM) +;over_sample_rate: support 128fs/192fs/256fs/384fs/512fs/768fs +;sample_resolution :16bits/20bits/24bits +;word_select_size :16bits/20bits/24bits/32bits +;pcm_sync_period :16/32/64/128/256 +;msb_lsb_first :0: msb first; 1: lsb first +;sign_extend :0: zero pending; 1: sign extend +;slot_index :slot index: 0: the 1st slot - 3: the 4th slot +;slot_width :8 bit width / 16 bit width +;frame_width :0: long frame = 2 clock width; 1: short frame +;tx_data_mode :0: 16bit linear PCM; 1: 8bit linear PCM; 2: 8bit u-law; 3: 8bit a-law +;rx_data_mode :0: 16bit linear PCM; 1: 8bit linear PCM; 2: 8bit u-law; 3: 8bit a-law +;-------------------------------------------------------------------------------- +[i2s_para] +i2s_used = 0 +i2s_channel = 2 +i2s_master = 4 +i2s_select = 1 +audio_format = 1 +signal_inversion = 1 +over_sample_rate = 256 +sample_resolution = 16 +word_select_size = 32 +pcm_sync_period = 256 +msb_lsb_first = 0 +sign_extend = 0 +slot_index = 0 +slot_width = 16 +frame_width = 1 +tx_data_mode = 0 +rx_data_mode = 0 +i2s_mclk = port:PB05<2><1> +i2s_bclk = port:PB06<2><1> +i2s_lrclk = port:PB07<2><1> +i2s_dout0 = port:PB08<2><1> +i2s_dout1 = +i2s_dout2 = +i2s_dout3 = +i2s_din = port:PB12<2><1> + + +;-------------------------------------------------------------------------------- +;pcm_master:1: SND_SOC_DAIFMT_CBM_CFM(codec clk & FRM master) use +; 2: SND_SOC_DAIFMT_CBS_CFM(codec clk slave & FRM master) not use +; 3: SND_SOC_DAIFMT_CBM_CFS(codec clk master & frame slave) not use +; 4: SND_SOC_DAIFMT_CBS_CFS(codec clk & FRM slave) use +;pcm_select:1 is pcm.0 is i2s +;audio_format: 1:SND_SOC_DAIFMT_I2S(standard i2s format). use +; 2:SND_SOC_DAIFMT_RIGHT_J(right justfied format). +; 3:SND_SOC_DAIFMT_LEFT_J(left justfied format) +; 4:SND_SOC_DAIFMT_DSP_A(pcm. MSB is available on 2nd BCLK rising edge after LRC rising edge). use +; 5:SND_SOC_DAIFMT_DSP_B(pcm. MSB is available on 1nd BCLK rising edge after LRC rising edge) +;signal_inversion:1:SND_SOC_DAIFMT_NB_NF(normal bit clock + frame) use +; 2:SND_SOC_DAIFMT_NB_IF(normal BCLK + inv FRM) +; 3:SND_SOC_DAIFMT_IB_NF(invert BCLK + nor FRM) use +; 4:SND_SOC_DAIFMT_IB_IF(invert BCLK + FRM) +;over_sample_rate: support 128fs/192fs/256fs/384fs/512fs/768fs +;sample_resolution :16bits/20bits/24bits +;word_select_size :16bits/20bits/24bits/32bits +;pcm_sync_period :16/32/64/128/256 +;msb_lsb_first :0: msb first; 1: lsb first +;sign_extend :0: zero pending; 1: sign extend +;slot_index :slot index: 0: the 1st slot - 3: the 4th slot +;slot_width :8 bit width / 16 bit width +;frame_width :0: long frame = 2 clock width; 1: short frame +;tx_data_mode :0: 16bit linear PCM; 1: 8bit linear PCM; 2: 8bit u-law; 3: 8bit a-law +;rx_data_mode :0: 16bit linear PCM; 1: 8bit linear PCM; 2: 8bit u-law; 3: 8bit a-law +;-------------------------------------------------------------------------------- +[pcm_para] +pcm_used = 0 +pcm_channel = 2 +pcm_master = 4 +pcm_select = 1 +audio_format = 4 +signal_inversion = 1 +over_sample_rate = 256 +sample_resolution = 16 +word_select_size = 32 +pcm_sync_period = 256 +msb_lsb_first = 0 +sign_extend = 0 +slot_index = 0 +slot_width = 16 +frame_width = 1 +tx_data_mode = 0 +rx_data_mode = 0 +pcm_mclk = port:PA09<6><1> +pcm_bclk = port:PA14<6><1> +pcm_lrclk = port:PA15<6><1> +pcm_dout0 = port:PA16<6><1> +pcm_dout1 = +pcm_dout2 = +pcm_dout3 = +pcm_din = port:PA17<6><1> + +[spdif_para] +spdif_used = 0 +spdif_mclk = +spdif_dout = port:PB13<4><1> +spdif_din = + +[audio_para] +audio_used = 1 +audio_pa_ctrl = port:PH15<1><0> +capture_used = 1 + +[switch_para] +switch_used = 0 + +;------------------------------------------------------------------------------- +;ir --- infra remote configuration +;------------------------------------------------------------------------------- +[ir_para] +ir_used = 1 +ir0_rx = port:PB04<2> + + +;------------------------------------------------------------------------------- +;pmu_twi_addr ---slave address +;pmu_twi_id ---i2c bus number (0 TWI0, 1 TWI2, 2 TWI3) +;pmu_irq_id ---irq number (0 irq0,1 irq1,……) +;pmu_battery_rdc ---battery initial resistance,mΩ,根据实际电池内阻填写 +;pmu_battery_cap ---battery capability,mAh，根据实际电池容量填写 +;pmu_init_chgcur ---set initial charging current limite,mA，300/400/500/600/700/800/900/1000/1100/1200/1300/1400/1500/1600/1700/1800 +;pmu_suspend_chgcur ---set suspend charging current limite,mA，300/400/500/600/700/800/900/1000/1100/1200/1300/1400/1500/1600/1700/1800 +;pmu_resume_chgcur ---set resume charging current limite,mA，300/400/500/600/700/800/900/1000/1100/1200/1300/1400/1500/1600/1700/1800 +;pmu_shutdown_chgcur ---set shutdown charging current limite,mA，300/400/500/600/700/800/900/1000/1100/1200/1300/1400/1500/1600/1700/1800 +;pmu_init_chgvol ---set initial charing target voltage,mV,4100/4150/4200/4360 +;pmu_init_chgend_rate ---set initial charing end current rate,10/15 +;pmu_init_chg_enabled ---set initial charing enabled,0:关闭,1:打开 +;pmu_init_adc_freq ---set initial adc frequency,Hz,25/50/100/200 +;pmu_init_adc_freqc ---set initial coulomb adc coufrequency,Hz,25/50/100/200 +;pmu_init_chg_pretime ---set initial pre-charging time,min,40/50/60/70 +;pmu_init_chg_csttime ---set initial constance-charging time,min,360/480/600/720 +;pmu_bat_para1 ---battery indication at 3.1328V +;pmu_bat_para2 ---battery indication at 3.2736V +;pmu_bat_para3 ---battery indication at 3.4144V +;pmu_bat_para4 ---battery indication at 3.5552V +;pmu_bat_para5 ---battery indication at 3.6256V +;pmu_bat_para6 ---battery indication at 3.6608V +;pmu_bat_para7 ---battery indication at 3.6960V +;pmu_bat_para8 ---battery indication at 3.7312V +;pmu_bat_para9 ---battery indication at 3.7664V +;pmu_bat_para10 ---battery indication at 3.8016V +;pmu_bat_para11 ---battery indication at 3.8368V +;pmu_bat_para12 ---battery indication at 3.8720V +;pmu_bat_para13 ---battery indication at 3.9424V +;pmu_bat_para14 ---battery indication at 4.0128V +;pmu_bat_para15 ---battery indication at 4.0832V +;pmu_bat_para16 ---battery indication at 4.1536V +;pmu_usbvol ---set usb-ac limited voltage level,mV,4000/4100/4200/4300/4400/4500/4600/4700,0 - not limite +;pmu_usbcur ---set usb-ac limited voltage level,mA,100/500/900, 0 - not limite +;pmu_usbvol_pc ---set usb-pc limited voltage level,mV,4000/4100/4200/4300/4400/4500/4600/4700,0 - not limite +;pmu_usbcur_pc ---set usb-pc limited voltage level,mA,100/500/900, 0 - not limite +;pmu_pwroff_vol ---set protect voltage when system start up,mV,2600/2700/2800/2900/3000/3100/3200/3300 +;pmu_pwron_vol ---set protect voltage after system start up,mV,2600/2700/2800/2900/3000/3100/3200/3300 +;pmu_pekoff_time ---set pek off time,ms, 4000/6000/8000/10000 +;pmu_pekoff_en ---set pek off enable, 0:关闭,1:打开 +;pmu_peklong_time ---set pek pek long irq time,ms,1000/1500/2000/2500 +;pmu_pekon_time ---set pek on time,ms,128/1000/2000/3000 +;pmu_pwrok_time ---set pmu pwrok delay time,ms,8/64 +;pmu_pwrnoe_time ---set pmu n_oe power down delay time,ms,128/1000/2000/3000 +;pmu_intotp_en ---set pmu power down when overtempertur enable,0:关闭，1：打开 +;pmu_suspendpwroff_vol ---set pmu shutdown voltage when cpu is suspend and battery voltage is low +;pmu_batdeten ---set pmu battery detect enabled,0:关闭，1：打开 +;------------------------------------------------------------------------------- +[pmu_para] +pmu_used = 1 +pmu_twi_addr = 0x34 +pmu_twi_id = 0 +pmu_irq_id = 32 +pmu_battery_rdc = 100 +pmu_battery_cap = 3200 +pmu_init_chgcur = 300 +pmu_earlysuspend_chgcur = 600 +pmu_suspend_chgcur = 1000 +pmu_resume_chgcur = 300 +pmu_shutdown_chgcur = 1000 +pmu_init_chgvol = 4200 +pmu_init_chgend_rate = 15 +pmu_init_chg_enabled = 1 +pmu_init_adc_freq = 100 +pmu_init_adc_freqc = 100 +pmu_init_chg_pretime = 50 +pmu_init_chg_csttime = 720 + +pmu_bat_para1 = 0 +pmu_bat_para2 = 0 +pmu_bat_para3 = 0 +pmu_bat_para4 = 0 +pmu_bat_para5 = 5 +pmu_bat_para6 = 8 +pmu_bat_para7 = 11 +pmu_bat_para8 = 22 +pmu_bat_para9 = 33 +pmu_bat_para10 = 43 +pmu_bat_para11 = 50 +pmu_bat_para12 = 59 +pmu_bat_para13 = 71 +pmu_bat_para14 = 83 +pmu_bat_para15 = 92 +pmu_bat_para16 = 100 + +pmu_usbvol_limit = 1 +pmu_usbcur_limit = 0 +pmu_usbvol = 4000 +pmu_usbcur = 0 + +pmu_usbvol_pc = 4000 +pmu_usbcur_pc = 0 + +pmu_pwroff_vol = 3300 +pmu_pwron_vol = 2900 + +pmu_pekoff_time = 6000 +pmu_pekoff_en = 1 +pmu_peklong_time = 1500 +pmu_pekon_time = 1000 +pmu_pwrok_time = 64 +pmu_pwrnoe_time = 2000 +pmu_intotp_en = 1 + +pmu_used2 = 0 +pmu_adpdet = port:PH02<0> +pmu_init_chgcur2 = 400 +pmu_earlysuspend_chgcur2 = 600 +pmu_suspend_chgcur2 = 1200 +pmu_resume_chgcur2 = 400 +pmu_shutdown_chgcur2 = 1200 + +pmu_suspendpwroff_vol = 3500 + +pmu_batdeten = 0 + +[recovery_key] +key_min =4 +key_max =6 + +;---------------------------------------------------------------------------------- +; dvfs voltage-frequency table configuration +; +; max_freq: cpu maximum frequency, based on Hz, can not be more than 1008MHz +; min_freq: cpu minimum frequency, based on Hz, can not be less than 60MHz +; +; LV_count: count of LV_freq/LV_volt, must be < 16 +; +; LV1: core vdd is 1.45v if cpu frequency is (912Mhz, 1008Mhz] +; LV2: core vdd is 1.40v if cpu frequency is (864Mhz, 912Mhz] +; LV3: core vdd is 1.30v if cpu frequency is (792Mhz, 864Mhz] +; LV4: core vdd is 1.25v if cpu frequency is (720Mhz, 792Mhz] +; LV5: core vdd is 1.20v if cpu frequency is (624Mhz, 720Mhz] +; LV6: core vdd is 1.15v if cpu frequency is (528Mhz, 624Mhz] +; LV7: core vdd is 1.10v if cpu frequency is (312Mhz, 528Mhz] +; LV8: core vdd is 1.05v if cpu frequency is ( 60Mhz, 312Mhz] +; +;---------------------------------------------------------------------------------- +[dvfs_table] +max_freq = 912000000 +normal_freq = 720000000 +min_freq = 60000000 + +LV_count = 8 + +LV1_freq = 1008000000 +LV1_volt = 1450 + +LV2_freq = 912000000 +LV2_volt = 1400 + +LV3_freq = 864000000 +LV3_volt = 1300 + +LV4_freq = 792000000 +LV4_volt = 1250 + +LV5_freq = 720000000 +LV5_volt = 1200 + +LV6_freq = 624000000 +LV6_volt = 1150 + +LV7_freq = 528000000 +LV7_volt = 1100 + +LV8_freq = 312000000 +LV8_volt = 1050 + +[gpio_para] +gpio_used = 1 +gpio_num = 25 +gpio_pin_0 = port:PI19<1><2> +gpio_pin_1 = port:PI18<0><2> +gpio_pin_2 = port:PH07<1><1> +gpio_pin_3 = port:PH06<1><0> +gpio_pin_4 = port:PH08<1><1> +gpio_pin_5 = port:PB02<0><2> +gpio_pin_6 = port:PI03<0><2> +gpio_pin_7 = port:PH09<0><2> +gpio_pin_8 = port:PH10<6> +gpio_pin_9 = port:PH05<0><2> +gpio_pin_10 = port:PI10<0><2> +gpio_pin_11 = port:PI12<0><2> +gpio_pin_12 = port:PI13<0><2> +gpio_pin_13 = port:PI11<0><2> +gpio_pin_14 = port:PH11<0><2> +gpio_pin_15 = port:PH12<0><2> +gpio_pin_16 = port:PH13<0><2> +gpio_pin_17 = port:PH14<0><2> +gpio_pin_18 = port:PH15<1><0> +gpio_pin_19 = port:PH16<1><0> +gpio_pin_20 = port:PC19<0><2> +gpio_pin_21 = port:PC21<0><2> +gpio_pin_22 = port:PC22<0><2> +gpio_pin_23 = port:PC20<0><2> +; usb_power_en +gpio_pin_24 = port:PD02<1><1> + +; Redeclared gpio_pin_0 as gpio_pin_24, for sun4i-gpio driver +gpio_pin_25 = port:PI19<0><1> + +[sb_pwm0] +pwm_gpio = port:PH06<1> + +[sb_pwm1] +pwm_gpio = port:PB02<2> + +[sb_pwm2] +pwm_gpio = port:PI03<2> + +[sb_pwm3] +pwm_gpio = port:PH05<1> + +[sb_pwm4] +pwm_gpio = port:PI10<1> + +[sb_pwm5] +pwm_gpio = port:PI12<1> + +[sb_keypad_para] +sb_key_used = 1 +key_num = 3 +; BACK ==> KEY_ESC +key_pin_0 = port:PH17<6><1><3> +key_code_0 = 1 +; MENU ==> KEY_SPACE +key_pin_1 = port:PH18<6><1><3> +key_code_1 = 57 +; HOME ==> KEY_ENTER +key_pin_2 = port:PH19<6><1><3> +key_code_2 = 28 diff --git a/u-boot-sunxi b/u-boot-sunxi index 8a4621c..87ca6dc 160000 --- a/u-boot-sunxi +++ b/u-boot-sunxi @@ -1 +1 @@ -Subproject commit 8a4621c488f33089d831168bfa5bae210a5684c8 +Subproject commit 87ca6dc0262d18b76e4749fc6505ef596039656a