From 1aa4d0d4a7025a83ecd97316acc0b377e5d21bdc Mon Sep 17 00:00:00 2001 From: commarmi76 Date: Sun, 9 Nov 2025 21:15:54 +0100 Subject: [PATCH 1/3] Update ttgo_t3stm32.dts to config OLED display Update ttgo_t3stm32.dts to config OLED display --- boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts | 22 +++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts b/boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts index 66b58178bf15f..03783cf879fe0 100644 --- a/boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts +++ b/boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts @@ -28,6 +28,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,display = &ssd1306; }; leds: leds { @@ -118,12 +119,12 @@ stm32_lp_tick_source: &lptim1 { }; &spi1 { - pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5 + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>; pinctrl-names = "default"; status = "okay"; - cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>, <&gpiob 12 GPIO_ACTIVE_LOW>; sdhc0: sdhc@0 { compatible = "zephyr,sdhc-spi-slot"; @@ -136,6 +137,23 @@ stm32_lp_tick_source: &lptim1 { }; spi-max-frequency = <24000000>; }; + + ssd1306: ssd1306@0 { + compatible = "solomon,ssd1306fb"; + reg = <1>; + label = "OLED_SSD1306"; + spi-max-frequency = <8000000>; + width = <128>; + height = <64>; + segment-offset = <0>; + page-offset = <0>; + display-offset = <0>; + multiplex-ratio = <63>; + segment-remap; + com-invdir; + prechargep = <0xF1>; + data-cmd-gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>; + }; }; &subghzspi { From 304d56a0ac9c8e3846471fd92728e35d35f4e23b Mon Sep 17 00:00:00 2001 From: commarmi76 Date: Sun, 9 Nov 2025 21:38:13 +0100 Subject: [PATCH 2/3] Update ttgo_t3stm32.dts fix --- boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts b/boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts index 03783cf879fe0..e6f31de584b2a 100644 --- a/boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts +++ b/boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts @@ -138,7 +138,7 @@ stm32_lp_tick_source: &lptim1 { spi-max-frequency = <24000000>; }; - ssd1306: ssd1306@0 { + ssd1306: ssd1306@1 { compatible = "solomon,ssd1306fb"; reg = <1>; label = "OLED_SSD1306"; From 511aa3ac53dbab499e164bcc9754e82893911a94 Mon Sep 17 00:00:00 2001 From: commarmi76 Date: Wed, 26 Nov 2025 15:42:43 +0100 Subject: [PATCH 3/3] Update ttgo_t3stm32.dts This board does not need DIO3 to power the TCXO oscillator --- boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts b/boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts index e6f31de584b2a..88f0992835bda 100644 --- a/boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts +++ b/boards/lilygo/ttgo_t3stm32/ttgo_t3stm32.dts @@ -163,8 +163,7 @@ stm32_lp_tick_source: &lptim1 { status = "okay"; tx-enable-gpios = <&gpiob 2 GPIO_ACTIVE_LOW>; /* FE_CTRL1 */ rx-enable-gpios = <&gpiob 6 GPIO_ACTIVE_LOW>; /* FE_CTRL2 */ - dio3-tcxo-voltage = ; - tcxo-power-startup-delay-ms = <5>; + /* High-power output is selected as a consequence of using * tx/rx-enable-gpio to control FE_CTRL1 and FE_CTRL2. Low-power * output would require both FE_CTRL1 and FE_CTRL2 to be high,