The inline assembly codeblocks in locktest.c is for x86_64 and so it fails to compile on other architectures example: ppc64le and arm64

[rhmcruiser]

Issue: The inline assembly language code blocks used in locktest.c for various atomic operations is for primarily for x86_64 architecture and locktest is not #ifdef conditionally compiled , so it fails to build on other architectures as the inline assembly instructions are not interpreted by the compiler.

Would be great to make provision for arm64 and ppcle inline asm code in locktest.c so that this test can be used on non-x8664 architectures would be great.

[rhmcruiser]

Build on ppc64le :

[root@ibm-p8-01-lp6 locktest]# ls
LICENSE locktest.c Makefile README.md

[root@ibm-p8-01-lp6 locktest]# make
cc -Wall -D_GNU_SOURCE -lpthread locktest.c -g -o locktest
locktest.c: In function ‘atomic64_or’:
locktest.c:52:2: error: impossible constraint in ‘asm’
asm volatile(LOCK_PREFIX "orq %1,%0"
^
make: *** [locktest] Error 1

[rhmcruiser]

Hopefully putting together some atomics for ppc64 assembly code:

uint64_t atomic_or_64(volatile uint64_t *target, uint64_t bits)
{
type lock;

asm volatile(
"1: lwarx %[lock],0,%[target]\n"
" or %[lock],%[bits],%[lock]\n"
" stwcx. %[lock],0,%[target]\n"
" bne- 1b"
: [lock] "=&r" (lock)
: [target] "r" (target), [bits] "r" (bits)
: "cc");

return lock; \

}

uint64_t atomic_and_64_nv(volatile uint64_t *target, uint64_t bits)
{

type lock;

asm volatile(
"1: lwarx %[lock],0,%[target]\n"
" and %[lock],%[bits],%[lock]\n"
" stwcx. %[lock],0,%[target]\n"
" bne- 1b"
: [lock] "=&r" (lock)
: [target] "r" (target), [bits] "r" (bits)
: "cc");

return lock;
}

[lczerner]

Right, this was always x86_64 only. To support additional architectures, ideally I would like to be able to automatically use the infrastructure from linux kernel. Meantime just copying the assembly parts for various architectures is an option.