From ac4893eac45677edd86f7bef4e4d601d57dd7bbc Mon Sep 17 00:00:00 2001 From: Ivan Pechenezhskiy Date: Wed, 16 Dec 2015 22:07:08 -0600 Subject: [PATCH 1/2] Add data readback support for DACs build 8 --- ghz_fpga_server.py | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/ghz_fpga_server.py b/ghz_fpga_server.py index c6dd9a94..ab1b7f16 100644 --- a/ghz_fpga_server.py +++ b/ghz_fpga_server.py @@ -758,6 +758,10 @@ def run(self, runners, reps, setupPkts, setupState, sync, getTimingData, # sequence. results = yield readAll # wait for read to complete + # List the DACs that support the data readback. + timingDataDACs = [runner.dev.devName for runner in runners + if isinstance(runner, dac.DacRunner_Build8)] + if getTimingData: answers = [] # Cache of already-parsed data from a particular board. @@ -770,7 +774,14 @@ def run(self, runners, reps, setupPkts, setupState, sync, getTimingData, boardName, channel = dataChannelName.split('::') channel = int(channel) elif 'DAC' in dataChannelName: - raise RuntimeError('DAC data readback not supported') + # Ensure that dataChannelName is among the DACs + # that support the data readback. + if dataChannelName in timingDataDACs: + boardName = dataChannelName + channel = None + else: + raise RuntimeError('DAC data readback ' + + ' supported only for DAC build 8') elif 'ADC' in dataChannelName: # ADC average mode boardName = dataChannelName @@ -791,6 +802,8 @@ def run(self, runners, reps, setupPkts, setupState, sync, getTimingData, results[idx]['read']] # Array of all timing results (DAC) extracted = runner.extract(result) + if isinstance(runner, dac.DacRunner_Build8): + extracted = (extracted,) extractedData[boardName] = extracted # Add extracted data to list of data to be returned if channel != None: @@ -1390,7 +1403,7 @@ def adc_mixer_table(self, c, channel, data): getTimingData='b', setupPkts='?{(((ww), s, ((s?)(s?)(s?)...))...)}', setupState='*s', - returns=['*4i', '*3i', '']) + returns=['*4i', '*3i', '*i', '']) def run_sequence(self, c, reps=30, getTimingData=True, setupPkts=[], setupState=[]): """Executes a sequence on one or more boards. @@ -1424,7 +1437,9 @@ def run_sequence(self, c, reps=30, getTimingData=True, setupPkts=[], (demod channel, stat, retrigger, I/Q). retrigger indexes multiple triggers in a sequence. - If only DACs present, we return no data. + If only DACs present, we return no data unless the build + number for at least some of the DAC boards is 8. + In the later case, the data is returned as *i. ADC boards must be either all in average mode or all in demodulate mode. From bf2ab8c7a504bd82f3f64383f987b87b27479c43 Mon Sep 17 00:00:00 2001 From: Ivan Pechenezhskiy Date: Wed, 16 Dec 2015 22:09:15 -0600 Subject: [PATCH 2/2] Add a comment --- ghz_fpga_server.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/ghz_fpga_server.py b/ghz_fpga_server.py index ab1b7f16..6f29ec71 100644 --- a/ghz_fpga_server.py +++ b/ghz_fpga_server.py @@ -802,6 +802,8 @@ def run(self, runners, reps, setupPkts, setupState, sync, getTimingData, results[idx]['read']] # Array of all timing results (DAC) extracted = runner.extract(result) + # Wrap the DAC timing results in a tuple for + # the data format consistency. if isinstance(runner, dac.DacRunner_Build8): extracted = (extracted,) extractedData[boardName] = extracted