From 2a5cf759eda4bf6217d2e5f23122cb10e37a6e3b Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 1 May 2019 20:23:38 -0700 Subject: [PATCH 01/57] csr implemented, needs testing --- Top.DualPortedMemory.memory.v | 20 + firrtl_black_box_resource_files.f | 1 + src/main/scala/components/control.scala | 44 +- src/main/scala/components/csr.scala | 506 ++++ src/main/scala/components/helpers.scala | 216 ++ src/main/scala/single-cycle/cpu.scala | 22 +- src/main/scala/testing/CPUTesterDriver.scala | 29 +- src/main/scala/testing/InstTests.scala | 143 ++ src/test/resources/risc-v/sw | Bin 5620 -> 5812 bytes src/test/resources/risc-v/sw.riscv | 1 + src/verilog/Top.DualPortedMemory.memory.v | 20 + src/verilog/obj_dir/VTop | Bin 0 -> 219584 bytes src/verilog/obj_dir/VTop.cpp | 2181 ++++++++++++++++++ src/verilog/obj_dir/VTop.h | 136 ++ src/verilog/obj_dir/VTop.mk | 66 + src/verilog/obj_dir/VTop__ALLcls.cpp | 3 + src/verilog/obj_dir/VTop__ALLcls.d | 5 + src/verilog/obj_dir/VTop__ALLsup.cpp | 3 + src/verilog/obj_dir/VTop__ALLsup.d | 5 + src/verilog/obj_dir/VTop__Syms.cpp | 21 + src/verilog/obj_dir/VTop__Syms.h | 37 + src/verilog/obj_dir/VTop__ver.d | 1 + src/verilog/obj_dir/VTop__verFiles.dat | 12 + src/verilog/obj_dir/VTop_classes.mk | 38 + src/verilog/obj_dir/testbench.d | 6 + src/verilog/obj_dir/verilated.d | 7 + src/verilog/testbench.cpp | 33 + 27 files changed, 3533 insertions(+), 23 deletions(-) create mode 100644 Top.DualPortedMemory.memory.v create mode 100644 firrtl_black_box_resource_files.f create mode 100644 src/main/scala/components/csr.scala create mode 100644 src/verilog/Top.DualPortedMemory.memory.v create mode 100755 src/verilog/obj_dir/VTop create mode 100644 src/verilog/obj_dir/VTop.cpp create mode 100644 src/verilog/obj_dir/VTop.h create mode 100644 src/verilog/obj_dir/VTop.mk create mode 100644 src/verilog/obj_dir/VTop__ALLcls.cpp create mode 100644 src/verilog/obj_dir/VTop__ALLcls.d create mode 100644 src/verilog/obj_dir/VTop__ALLsup.cpp create mode 100644 src/verilog/obj_dir/VTop__ALLsup.d create mode 100644 src/verilog/obj_dir/VTop__Syms.cpp create mode 100644 src/verilog/obj_dir/VTop__Syms.h create mode 100644 src/verilog/obj_dir/VTop__ver.d create mode 100644 src/verilog/obj_dir/VTop__verFiles.dat create mode 100644 src/verilog/obj_dir/VTop_classes.mk create mode 100644 src/verilog/obj_dir/testbench.d create mode 100644 src/verilog/obj_dir/verilated.d create mode 100644 src/verilog/testbench.cpp diff --git a/Top.DualPortedMemory.memory.v b/Top.DualPortedMemory.memory.v new file mode 100644 index 00000000..a41466f6 --- /dev/null +++ b/Top.DualPortedMemory.memory.v @@ -0,0 +1,20 @@ +module BindsTo_0_DualPortedMemory( + input clock, + input reset, + input [31:0] io_imem_address, + output [31:0] io_imem_instruction, + input [31:0] io_dmem_address, + input [31:0] io_dmem_writedata, + input io_dmem_memread, + input io_dmem_memwrite, + input [1:0] io_dmem_maskmode, + input io_dmem_sext, + output [31:0] io_dmem_readdata +); + +initial begin + $readmemh("test", DualPortedMemory.memory); +end + endmodule + +bind DualPortedMemory BindsTo_0_DualPortedMemory BindsTo_0_DualPortedMemory_Inst(.*); \ No newline at end of file diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f new file mode 100644 index 00000000..900ea4d4 --- /dev/null +++ b/firrtl_black_box_resource_files.f @@ -0,0 +1 @@ +/riscv/Top.DualPortedMemory.memory.v \ No newline at end of file diff --git a/src/main/scala/components/control.scala b/src/main/scala/components/control.scala index 3f589a74..d41bffab 100644 --- a/src/main/scala/components/control.scala +++ b/src/main/scala/components/control.scala @@ -26,6 +26,7 @@ class Control extends Module { val io = IO(new Bundle { val opcode = Input(UInt(7.W)) + val validinst = Output(Bool()) val branch = Output(Bool()) val memread = Output(Bool()) val toreg = Output(UInt(2.W)) @@ -39,36 +40,39 @@ class Control extends Module { val signals = ListLookup(io.opcode, - /*default*/ List(false.B, false.B, 3.U, false.B, false.B, false.B, false.B, 0.U, 0.U), - Array( /* branch, memread, toreg, add, memwrite, immediate, regwrite, alusrc1, jump */ + /*default*/ List(false.B, false.B, false.B, 4.U, false.B, false.B, false.B, false.B, 0.U, 0.U), + Array( /* valid instr, branch, memread, toreg, add, memwrite, immediate, regwrite, alusrc1, jump */ // R-format - BitPat("b0110011") -> List(false.B, false.B, 0.U, false.B, false.B, false.B, true.B, 0.U, 0.U), + BitPat("b0110011") -> List(true.B, false.B, false.B, 0.U, false.B, false.B, false.B, true.B, 0.U, 0.U), // I-format - BitPat("b0010011") -> List(false.B, false.B, 0.U, false.B, false.B, true.B, true.B, 0.U, 0.U), + BitPat("b0010011") -> List(true.B, false.B, false.B, 0.U, false.B, false.B, true.B, true.B, 0.U, 0.U), // load - BitPat("b0000011") -> List(false.B, true.B, 1.U, true.B, false.B, true.B, true.B, 0.U, 0.U), + BitPat("b0000011") -> List(true.B, false.B, true.B, 1.U, true.B, false.B, true.B, true.B, 0.U, 0.U), // store - BitPat("b0100011") -> List(false.B, false.B, 0.U, true.B, true.B, true.B, false.B, 0.U, 0.U), + BitPat("b0100011") -> List(true.B, false.B, false.B, 0.U, true.B, true.B, true.B, false.B, 0.U, 0.U), // beq - BitPat("b1100011") -> List(true.B, false.B, 0.U, false.B, false.B, false.B, false.B, 0.U, 0.U), + BitPat("b1100011") -> List(true.B, true.B, false.B, 0.U, false.B, false.B, false.B, false.B, 0.U, 0.U), // lui - BitPat("b0110111") -> List(false.B, false.B, 0.U, true.B, false.B, true.B, true.B, 1.U, 0.U), + BitPat("b0110111") -> List(true.B, false.B, false.B, 0.U, true.B, false.B, true.B, true.B, 1.U, 0.U), // auipc - BitPat("b0010111") -> List(false.B, false.B, 0.U, true.B, false.B, true.B, true.B, 2.U, 0.U), + BitPat("b0010111") -> List(true.B, false.B, false.B, 0.U, true.B, false.B, true.B, true.B, 2.U, 0.U), // jal - BitPat("b1101111") -> List(false.B, false.B, 2.U, false.B, false.B, false.B, true.B, 1.U, 2.U), + BitPat("b1101111") -> List(true.B, false.B, false.B, 2.U, false.B, false.B, false.B, true.B, 1.U, 2.U), // jalr - BitPat("b1100111") -> List(false.B, false.B, 2.U, false.B, false.B, true.B, true.B, 0.U, 3.U) + BitPat("b1100111") -> List(true.B, false.B, false.B, 2.U, false.B, false.B, true.B, true.B, 0.U, 3.U), + //csr + BitPat("b1110011") -> List(true.B, false.B, false.B, 3.U, false.B, false.B, false.B, false.B, 0.U, 0.U) ) // Array ) // ListLookup - io.branch := signals(0) - io.memread := signals(1) - io.toreg := signals(2) - io.add := signals(3) - io.memwrite := signals(4) - io.immediate := signals(5) - io.regwrite := signals(6) - io.alusrc1 := signals(7) - io.jump := signals(8) + io.validinst := signals(0) + io.branch := signals(1) + io.memread := signals(2) + io.toreg := signals(3) + io.add := signals(4) + io.memwrite := signals(5) + io.immediate := signals(6) + io.regwrite := signals(7) + io.alusrc1 := signals(8) + io.jump := signals(9) } diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala new file mode 100644 index 00000000..a353d112 --- /dev/null +++ b/src/main/scala/components/csr.scala @@ -0,0 +1,506 @@ +/* Describes register file that maintains machine state */ + +package dinocpu + +import chisel3._ +import collection.mutable.LinkedHashMap +import chisel3.util._ +import chisel3.util.BitPat +import chisel3.util.experimental.BoringUtils +import Util._ + +import scala.math._ + +object MCauses { + //with interrupt + val machine_soft_int = 0x80000003 + val machine_timer_int = 0x80000007 + val machine_ext_int = 0x8000000b + + //non interrupt + val misaligned_fetch = 0x0 + val fetch_access = 0x1 + val illegal_instruction = 0x2 + val breakpoint = 0x3 + val misaligned_load = 0x4 + val load_access = 0x5 + val misaligned_store = 0x6 + val store_access = 0x7 + val machine_ecall = 0xb + val all = { + val res = collection.mutable.ArrayBuffer[Int]() + res += machine_soft_int + res += machine_timer_int + res += machine_ext_int + + res += misaligned_fetch + res += fetch_access + res += illegal_instruction + res += breakpoint + res += misaligned_load + res += load_access + res += misaligned_store + res += store_access + res += machine_ecall + res.toArray + } +} + +object MCSRs { + //machine information registers + val mvendorid = 0xf11 //vendor id + val marchid = 0xf12 //architecture id + val mimpid = 0xf13 //implementation id + val mhartid = 0xf14 //hardware thread id + //machine trap setup + val mstatus = 0x300 //machine status reg + val misa = 0x301 //isa and extensions + val medeleg = 0x302 //machine exception delegation reg + val mideleg = 0x303 //machine interrupt delegation reg + val mie = 0x304 //machine iterrupt-enable reg + val mtvec = 0x305 //machine trap handler base address + val mcounteren = 0x306 //machine counter enable + + //machine trap handling + val mscratch = 0x340 //scratch reg for machine trap handlers + val mepc = 0x341 //machine exception program counter + val mcause = 0x342 //machine trap cause + val mtval = 0x343 //machine bad address or instruction + val mip = 0x344 //machine interrupt pending + + //machine memory protection + //DONT NEED + + //machine counter/timers + val mcycle = 0xb00 //machine cycle counter + val minstret = 0xb02 //machine instructions retured counter + val mcycleh = 0xb80 + val minstreth = 0xb82 + //performance counter setup + val mcounterinhibit = 0x320 + val all = { + val res = collection.mutable.ArrayBuffer[Int]() + res += mstatus + res += misa + res += medeleg + res += mideleg + res += mie + res += mtvec + res += mscratch + res += mepc + res += mcause + res += mtval + res += mip + res += mcycle + res += minstret + res += mcycleh + res += minstreth + res += mvendorid + res += marchid + res += mhartid + res += mimpid + res += mcounterinhibit + res.toArray + } +} + +class MStatus extends Bundle{ + val sd = Bool() //dirty fs or xs + val wpri1 = UInt(8.W) //reserved, zero + val tsr = Bool() //trap on sret + val tw = Bool() //timeout for supervisor wait for interrupt + val tvm = Bool() //trap virtual memory + val mxr = Bool() //make executable readable + val sum = Bool() //supervisor user mem access + val mprv = Bool() //modify priv, access memorr as mpp + val xs = UInt(2.W) //user extension state + val fs = UInt(2.W) //float state + //previous privilege + val mpp = UInt(2.W) + val wpri2 = UInt(2.W) + val spp = UInt(1.W) + //previous interrupt enable + val mpie = Bool() + val wpri3 = Bool() //reserved, zero + val spie = Bool() + val upie = Bool() + //interrupt enable + val mie = Bool() //machine interrupt enable + val wpri4 = Bool() //reserved, zero + val sie = Bool() //supervisor interrupt enable + val uie = Bool() //user interrupt enable +} + +class MISA extends Bundle{ + val mxl = UInt(2.W) //rv32, 64 , 128 + val wlrl = UInt(4.W) //reserved + val extensions = UInt(26.W) //isa extensions +} + +class MVendorID extends Bundle{ + val bank = UInt(25.W) + val offset = UInt(7.W) +} + +class MTVec extends Bundle{ + val base = UInt(30.W) + val mode = UInt(2.W) +} + +class MIx extends Bundle{ + val wpri1 = UInt(20.W) + val meix = Bool() + val wpri2 = UInt(1.W) + val seix = Bool() + val ueix = Bool() + val mtix = Bool() + val wpri3 = UInt(1.W) + val stix = Bool() + val utix = Bool() + val msix = Bool() + val wpri4 = UInt(1.W) + val ssix = Bool() + val usix = Bool() +} + +class XCounterEnInhibit extends Bundle{ + val hpm31 = Bool() + val hpm30 = Bool() + val hpm29 = Bool() + val hpm28 = Bool() + val hpm27 = Bool() + val hpm26 = Bool() + val hpm25 = Bool() + val hpm24 = Bool() + val hpm23 = Bool() + val hpm22 = Bool() + val hpm21 = Bool() + val hpm20 = Bool() + val hpm19 = Bool() + val hpm18 = Bool() + val hpm17 = Bool() + val hpm16 = Bool() + val hpm15 = Bool() + val hpm14 = Bool() + val hpm13 = Bool() + val hpm12 = Bool() + val hpm11 = Bool() + val hpm10 = Bool() + val hpm9 = Bool() + val hpm8 = Bool() + val hpm7 = Bool() + val hpm6 = Bool() + val hpm5 = Bool() + val hpm4 = Bool() + val hpm3 = Bool() + val ir = Bool() + val tmzero = Bool() + val cy = Bool() +} + +class MCause extends Bundle{ + val interrupt = Bool() + val exceptioncode = UInt(31.W) +} + +object MCSRCmd{ + // commands + val size = 3.W + val execute = 0.asUInt(size) + val nop = 0.asUInt(size) + val write = 1.asUInt(size) + val set = 2.asUInt(size) + val clear = 3.asUInt(size) + val interrupt = 4.asUInt(size) + val read = 5.asUInt(size) + + val SIZE = 3.W + val MSB = 31 + val LSB = 20 + val TRAPADDR = "h80000000".U + val MPRV = 3 +} + +class CSRRegFileIO extends Bundle{ + //val hartid = Input(UInt(32.W)) + val rw = new Bundle { + val rdata = Output(UInt(32.W)) // + val wdata = Input(UInt(32.W)) // + } + + val csr_stall = Output(Bool())//not needed in single cycle + val eret = Output(Bool())// + + val decode = new Bundle { + val inst = Input(UInt(32.W)) // + val immid = Input(UInt(32.W)) // + val read_illegal = Output(Bool()) + val write_illegal = Output(Bool()) + val system_illegal = Output(Bool()) + } + + val status = Output(new MStatus())//not needed in this design but useful if more ISA extensions + val evec = Output(UInt(32.W)) // + val exception = Input(Bool()) // + val retire = Input(Bool()) // + val pc = Input(UInt(32.W)) // + val time = Output(UInt(32.W))// +} + +class CSRRegFile extends Module{ + //INIT CSR + val io = IO(new CSRRegFileIO) + io := DontCare + + val reset_mstatus = WireInit(0.U.asTypeOf(new MStatus())) + reset_mstatus.mpp := MCSRCmd.MPRV//machine mode + + val reg_mstatus = RegInit(reset_mstatus) + val reg_mepc = Reg(UInt(32.W)) + val reg_mcause = RegInit(0.U.asTypeOf(new MCause())) + val reg_mtval = Reg(UInt(32.W)) + val reg_mscratch = Reg(UInt(32.W)) + val reg_mtimecmp = Reg(UInt(64.W)) + val reg_medeleg = Reg(UInt(32.W)) + + val reg_mip = RegInit(0.U.asTypeOf(new MIx())) + val reg_mie = RegInit(0.U.asTypeOf(new MIx())) + val reg_wfi = RegInit(false.B) + val reg_mtvec = RegInit(0.U.asTypeOf(new MTVec())) + + val reg_time = WideCounter(64) + val reg_instret = WideCounter(64, io.retire) + + val reg_mcounterinhibit = RegInit(0.U.asTypeOf(new XCounterEnInhibit())) + val reg_mcounteren = RegInit(0.U.asTypeOf(new XCounterEnInhibit())) + + val read_mstatus = io.status.asUInt() + val isa_string = "I" + val reg_misa = RegInit((BigInt(0) | isa_string.map(x => 1 << (x - 'A')).reduce(_|_)).U.asTypeOf(new MISA())) + val reg_mvendorid = RegInit(0.U.asTypeOf(new MVendorID())) + + + val read_mapping = collection.mutable.LinkedHashMap[Int,Bits]( + MCSRs.mcounterinhibit -> reg_mcounterinhibit.asUInt, + MCSRs.mcycle -> reg_time, + MCSRs.minstret -> reg_instret, + MCSRs.mimpid -> 0.U, + MCSRs.marchid -> 0.U, + MCSRs.mvendorid -> 0.U, + MCSRs.misa -> reg_misa.asUInt, + MCSRs.mstatus -> read_mstatus, + MCSRs.mtvec -> MCSRCmd.TRAPADDR, + MCSRs.mip -> reg_mip.asUInt(), + MCSRs.mie -> reg_mie.asUInt(), + MCSRs.mscratch -> reg_mscratch, + MCSRs.mepc -> reg_mepc, + MCSRs.mtval -> reg_mtval, + MCSRs.mcause -> reg_mcause.asUInt(), + MCSRs.mhartid -> 0.U, + MCSRs.medeleg -> reg_medeleg) + + read_mapping += MCSRs.mcycleh -> 0.U + read_mapping += MCSRs.minstreth -> 0.U + + //CSR DECODE + val cmd = if( io.decode.inst(6, 0) == ("b1110011".U) ) { + if( (io.decode.inst(19, 15) == ("b011".U)) || (io.decode.inst(19, 15) == ("b111".U)) ){ + MCSRCmd.clear //CSRRC{i} + }else if( (io.decode.inst(19, 15) == ("b010".U)) || (io.decode.inst(19, 15) == ("b110".U)) ){ + MCSRCmd.set //CSRRS{i} + }else if( (io.decode.inst(19, 15) == ("b001".U)) || (io.decode.inst(19, 15) == ("b101".U)) ){ + MCSRCmd.write //CSRRW{i} + }else if( (io.decode.inst(19, 15) == ("b000".U)) ) { + MCSRCmd.interrupt //ebreak, ecall + } + }else{ + MCSRCmd.nop + } + + val csr = io.decode.inst(MCSRCmd.MSB, MCSRCmd.LSB) + val system_insn = cmd == MCSRCmd.interrupt + val cpu_ren = cmd != MCSRCmd.nop && !system_insn + + + val decoded_addr = read_mapping map { case (k, v) => k -> (csr === k) } + val priv_sufficient = MCSRCmd.MPRV >= csr(9,8) + val read_only = csr(11,10).andR + val cpu_wen = cpu_ren && cmd != MCSRCmd.read && priv_sufficient + val wen = cpu_wen && !read_only + val wdata = readModifyWriteCSR(cmd.asInstanceOf[UInt], io.rw.rdata, io.rw.wdata) + + val opcode = 1.U << csr(2,0) + val insn_call = system_insn && opcode(0) + val insn_break = system_insn && opcode(1) + val insn_ret = system_insn && opcode(2) && priv_sufficient + val insn_wfi = system_insn && opcode(5) && priv_sufficient + + private def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map( { case(k: Int, _: Bits) => csr === k }).reduce(_ || _) + io.decode.read_illegal := 3 < csr(9,8) || !decodeAny(read_mapping) + io.decode.write_illegal := csr(11,10).andR + io.decode.system_illegal := 3 < csr(9,8) + + io.status := reg_mstatus + + io.eret := insn_call || insn_break || insn_ret + + // ILLEGAL INSTR + when (io.exception) { + reg_mcause.interrupt := MCauses.illegal_instruction & "h80000000".U + reg_mcause.exceptioncode := MCauses.illegal_instruction & "h7fffffff".U + io.evec := "h80000004".U + reg_mepc := io.pc // misaligned memory exceptions not supported... + } + + assert(PopCount(insn_ret :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") + + when (reg_time >= reg_mtimecmp) { + reg_mip.mtix := true + } + + //MRET + when (insn_ret && !csr(10)) { + reg_mstatus.mie := reg_mstatus.mpie + reg_mstatus.mpie := true + io.evec := reg_mepc + } + + //ECALL + when(insn_call){ + io.evec := "h80000004".U + reg_mcause.interrupt := MCauses.machine_ecall & "h80000000".U + reg_mcause.exceptioncode := MCauses.machine_ecall & "h7fffffff".U + } + + //EBREAK + when(insn_break){ + io.evec := "h80000004".U + reg_mcause.interrupt := MCauses.breakpoint & "h80000000".U + reg_mcause.exceptioncode := MCauses.breakpoint & "h7fffffff".U + } + + io.time := reg_time + io.csr_stall := reg_wfi + + + io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) + + when (wen) { + //MISA IS FIXED IN THIS IMPLEMENATION + + //MVENDORID IS FIXED IN THIS IMPLEMENTATION + + //MARCHID IS FIXED IN THIS IMPLEMENTATION + + //MIMPID IS FIXED IN THIS IMPLEMENTATION + + //MHARTID IS FIXED IN THIS IMPLEMENTATION + + //MSTATUS + /* Only need to worry about m mode interrupts so no need to worry about setting + * mpie, mpp, and mie correctly with respect to other modes. + * non implemented modes wired to 0 + */ + when (decoded_addr(MCSRs.mstatus)) { + val new_mstatus = wdata.asTypeOf(new MStatus()) + reg_mstatus.mie := new_mstatus.mie + reg_mstatus.mpie := new_mstatus.mpie + //unused bits in mstatus m-mode only specified by spec + reg_mstatus.spp := 0 + reg_mstatus.uie := 0 + reg_mstatus.upie := 0 + reg_mstatus.mprv := 0 + reg_mstatus.mxr := 0 + reg_mstatus.sum := 0 + reg_mstatus.tvm := 0 + reg_mstatus.tw := 0 + reg_mstatus.tsr := 0 + reg_mstatus.fs := 0 + reg_mstatus.xs := 0 + reg_mstatus.sd := 0 + } + + //MTVEC IS FIXED IN THIS IMPLEMENTATION + + //MDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION + + //MIDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION + + + //MIP + /* mtip read only, cleared on timercmp write + * meip read only, set by external interrupt controller + */ + when (decoded_addr(MCSRs.mip)) { + val new_mip = wdata.asTypeOf(new MIx()) + reg_mip.msix := new_mip.msix + reg_mip.seix := 0 + reg_mip.ueix := 0 + reg_mip.stix := 0 + reg_mip.utix := 0 + reg_mip.ssix := 0 + reg_mip.usix := 0 + + } + //MIE + /* deals with external interrupts similar to mip but + * m mode bits are r and w + */ + when (decoded_addr(MCSRs.mie)) { + val new_mie = wdata.asTypeOf(new MIx()) + reg_mie.meix := new_mie.meix + reg_mie.msix := new_mie.msix + reg_mie.mtix := new_mie.mtix + reg_mip.seix := 0 + reg_mip.ueix := 0 + reg_mip.stix := 0 + reg_mip.utix := 0 + reg_mip.ssix := 0 + reg_mip.usix := 0 + + } + //MCOUNTEREB IS FIXED IN THIS IMPLEMENTATION BECAUSE NO S | U MODE + + //MCOUNTINHIBIT + /* stops counting cycles and retired instructions if need be + * + */ + when (decoded_addr(MCSRs.mcounterinhibit)) { + val new_mcounterinhibit = wdata.asTypeOf(new XCounterEnInhibit()) + reg_mcounterinhibit := new_mcounterinhibit + if( reg_mcounterinhibit.cy == false.B) { + writeCounter(MCSRs.mcycle, reg_time, wdata) + } + if( reg_mcounterinhibit.ir == false.B){ + writeCounter(MCSRs.minstret, reg_instret, wdata) + } + } + + //MSCRATCH + when (decoded_addr(MCSRs.mscratch)) { reg_mscratch := wdata } + + //MEPC + /* hardcoded to be 32 bit aligned because no compressed isa last 2 bits 0 + */ + when (decoded_addr(MCSRs.mepc)) { reg_mepc := (wdata(32-1,0) >> 2.U) << 2.U } + //MCAUSE + /* Only write to on interrupt for hardware. software can write whenever + * masks msb and 5 lsb from wdata + */ + when (decoded_addr(MCSRs.mcause)) { + reg_mcause.interrupt := (wdata & ((BigInt(1) << (32-1)) + 31).U) & "h80000000".U /* only implement 5 LSBs and MSB */ + reg_mcause.exceptioncode := (wdata & ((BigInt(1) << (32-1)) + 31).U) & "h7fffffff".U /* only implement 5 LSBs and MSB */ + + } + + when (decoded_addr(MCSRs.mtval)) { reg_mtval := wdata(32-1,0) } + when (decoded_addr(MCSRs.medeleg)) { reg_medeleg := wdata(32-1,0) } + } + def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { + val hi = lo + MCSRs.mcycleh - MCSRs.mcycle + when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } + when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } + } + def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = +(Mux(cmd.isOneOf(MCSRCmd.set, MCSRCmd.clear), rdata, 0.U) | wdata) & ~Mux(cmd === MCSRCmd.clear, wdata, 0.U) +} diff --git a/src/main/scala/components/helpers.scala b/src/main/scala/components/helpers.scala index d0bbcd9d..053b46e5 100644 --- a/src/main/scala/components/helpers.scala +++ b/src/main/scala/components/helpers.scala @@ -4,7 +4,223 @@ package dinocpu import chisel3._ import chisel3.util._ +import scala.math._ +import scala.collection.mutable.ArrayBuffer +object Util +{ + implicit def intToUInt(x: Int): UInt = x.U + implicit def intToBoolean(x: Int): Boolean = if (x != 0) true else false + implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0 + implicit def booleanToBool(x: Boolean): Bool = x.B + implicit def sextToConv(x: UInt) = new AnyRef { + def sextTo(n: Int): UInt = Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) + } + + implicit def wcToUInt(c: WideCounter): UInt = c.value + implicit class UIntIsOneOf(val x: UInt) extends AnyVal { + def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).reduce(_||_) + + def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) + } + + implicit class UIntToAugmentedUInt(val x: UInt) extends AnyVal { + def sextTo(n: Int): UInt = { + require(x.getWidth <= n) + if (x.getWidth == n) x + else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) + } + + def padTo(n: Int): UInt = { + require(x.getWidth <= n) + if (x.getWidth == n) x + else Cat(0.U((n - x.getWidth).W), x) + } + + def extract(hi: Int, lo: Int): UInt = { + if (hi == lo-1) 0.U + else x(hi, lo) + } + + def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds + } +} + + +//do two masks have at least 1 bit match? +object maskMatch +{ + def apply(msk1: UInt, msk2: UInt): Bool = + { + val br_match = (msk1 & msk2) =/= 0.U + return br_match + } +} + +//clear one-bit in the Mask as specified by the idx +object clearMaskBit +{ + def apply(msk: UInt, idx: UInt): UInt = + { + return (msk & ~(1.U << idx))(msk.getWidth-1, 0) + } +} + +//shift a register over by one bit +object PerformShiftRegister +{ + def apply(reg_val: Bits, new_bit: Bool): Bits = + { + reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt(), new_bit.asUInt()).asUInt() + reg_val + } +} + +object Split +{ + // is there a better way to do do this? + def apply(x: Bits, n0: Int) = { + val w = checkWidth(x, n0) + (x(w-1,n0), x(n0-1,0)) + } + def apply(x: Bits, n1: Int, n0: Int) = { + val w = checkWidth(x, n1, n0) + (x(w-1,n1), x(n1-1,n0), x(n0-1,0)) + } + def apply(x: Bits, n2: Int, n1: Int, n0: Int) = { + val w = checkWidth(x, n2, n1, n0) + (x(w-1,n2), x(n2-1,n1), x(n1-1,n0), x(n0-1,0)) + } + + private def checkWidth(x: Bits, n: Int*) = { + val w = x.getWidth + def decreasing(x: Seq[Int]): Boolean = + if (x.tail.isEmpty) true + else x.head > x.tail.head && decreasing(x.tail) + require(decreasing(w :: n.toList)) + w + } +} + + +// a counter that clock gates most of its MSBs using the LSB carry-out +case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true) +{ + private val isWide = width > 2*inc.getWidth + private val smallWidth = if (isWide) inc.getWidth max log2Ceil(width) else width + private val small = if (reset) RegInit(0.asUInt(smallWidth.W)) else Reg(UInt(smallWidth.W)) + private val nextSmall = small +& inc + small := nextSmall + + private val large = if (isWide) { + val r = if (reset) RegInit(0.asUInt((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W)) + when (nextSmall(smallWidth)) { r := r + 1.U } + r + } else null + + val value = if (isWide) Cat(large, small) else small + lazy val carryOut = { + val lo = (small ^ nextSmall) >> 1 + if (!isWide) lo else { + val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1 + Cat(hi, lo) + } + } + + def := (x: UInt) = { + small := x + if (isWide) large := x >> smallWidth + } +} + +// taken from rocket FPU +object RegEn +{ + def apply[T <: Data](data: T, en: Bool) = + { + val r = Reg(data) + when (en) { r := data } + r + } + def apply[T <: Bits](data: T, en: Bool, resetVal: T) = + { + val r = RegInit(resetVal) + when (en) { r := data } + r + } +} + +object Str +{ + def apply(s: String): UInt = { + var i = BigInt(0) + require(s.forall(validChar _)) + for (c <- s) + i = (i << 8) | c + i.asUInt((s.length*8).W) + } + def apply(x: Char): Bits = { + require(validChar(x)) + val lit = x.asUInt(8.W) + lit + } + def apply(x: UInt): Bits = apply(x, 10) + def apply(x: UInt, radix: Int): Bits = { + val rad = radix.U + val digs = digits(radix) + val w = x.getWidth + require(w > 0) + + var q = x + var s = digs(q % rad) + for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { + q = q / rad + s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digs(q % rad)), s) + } + s + } + def apply(x: SInt): Bits = apply(x, 10) + def apply(x: SInt, radix: Int): Bits = { + val neg = x < 0.S + val abs = Mux(neg, -x, x).asUInt() + if (radix != 10) { + Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) + } else { + val rad = radix.U + val digs = digits(radix) + val w = abs.getWidth + require(w > 0) + + var q = abs + var s = digs(q % rad) + var needSign = neg + for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { + q = q / rad + val placeSpace = q === 0.U + val space = Mux(needSign, Str('-'), Str(' ')) + needSign = needSign && !placeSpace + s = Cat(Mux(placeSpace, space, digs(q % rad)), s) + } + Cat(Mux(needSign, Str('-'), Str(' ')), s) + } + } + + def bigIntToString(x: BigInt): String = { + val s = new StringBuilder + var b = x + while (b != 0) { + s += (x & 0xFF).toChar + b = b >> 8 + } + s.toString + } + + private def digit(d: Int): Char = (if (d < 10) '0'+d else 'a'-10+d).toChar + private def digits(radix: Int): Vec[Bits] = + VecInit((0 until radix).map(i => Str(digit(i)))) + + private def validChar(x: Char) = x == (x & 0xFF) +} /** * A simple adder which takes two inputs and returns the sum * diff --git a/src/main/scala/single-cycle/cpu.scala b/src/main/scala/single-cycle/cpu.scala index db452f13..1d61f544 100644 --- a/src/main/scala/single-cycle/cpu.scala +++ b/src/main/scala/single-cycle/cpu.scala @@ -19,6 +19,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { val pc = RegInit(0.U) val control = Module(new Control()) val registers = Module(new RegisterFile()) + val csr = Module(new CSRRegFile()) val aluControl = Module(new ALUControl()) val alu = Module(new ALU()) val immGen = Module(new ImmediateGenerator()) @@ -27,6 +28,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { val branchAdd = Module(new Adder()) val (cycleCount, _) = Counter(true.B, 1 << 30) + //FETCH io.imem.address := pc pcPlusFour.io.inputx := pc @@ -35,6 +37,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { val instruction = io.imem.instruction val opcode = instruction(6,0) + //DECODE control.io.opcode := opcode registers.io.readreg1 := instruction(19,15) @@ -50,7 +53,8 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { immGen.io.instruction := instruction val imm = immGen.io.sextImm - + + //ALU branchCtrl.io.branch := control.io.branch branchCtrl.io.funct3 := instruction(14,12) branchCtrl.io.inputx := registers.io.readdata1 @@ -68,6 +72,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { alu.io.inputy := alu_inputy alu.io.operation := aluControl.io.operation + //MEMORY io.dmem.address := alu.io.result io.dmem.writedata := registers.io.readdata2 io.dmem.memread := control.io.memread @@ -75,6 +80,19 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { io.dmem.maskmode := instruction(13,12) io.dmem.sext := ~instruction(14) + //WRITEBACK + csr.io.decode.inst := instruction + csr.io.decode.immid := imm + csr.io.rw.wdata := registers.io.readdata2 + + + csr.io.retire := true.B //mem is synchronous in this deisgn. no flushing as far as i'm aware + csr.io.exception := !control.io.validinst || csr.io.decode.read_illegal || + csr.io.decode.write_illegal || csr.io.decode.system_illegal //illegal inst exception? + csr.io.pc := pc + + + val write_data = Wire(UInt()) when (control.io.toreg === 1.U) { write_data := io.dmem.readdata @@ -93,6 +111,8 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { next_pc := branchAdd.io.result } .elsewhen (control.io.jump === 3.U) { next_pc := alu.io.result & Cat(Fill(31, 1.U), 0.U) + } .elsewhen (csr.io.eret || !control.io.validinst) { + next_pc := csr.io.evec } .otherwise { next_pc := pcPlusFour.io.result } diff --git a/src/main/scala/testing/CPUTesterDriver.scala b/src/main/scala/testing/CPUTesterDriver.scala index 05338665..b3e1efbe 100644 --- a/src/main/scala/testing/CPUTesterDriver.scala +++ b/src/main/scala/testing/CPUTesterDriver.scala @@ -59,6 +59,12 @@ class CPUTesterDriver(cpuType: String, simulator.reset(5) } + def initCSR(vals: Map[Int, BigInt]) { + for ((num, value) <- vals) { + simulator.poke(s"cpu.csr.read_mapping_$num", value) + } + } + def initRegs(vals: Map[Int, BigInt]) { for ((num, value) <- vals) { simulator.poke(s"cpu.registers.regs_$num", value) @@ -75,6 +81,22 @@ class CPUTesterDriver(cpuType: String, } } + def checkCSR(vals: Map[Int, BigInt]): Boolean = { + var success = true + for ((num, value) <- vals) { + try { + simulator.expect(s"cpu.csr.read_mapping_$num", value) + } catch { + case _: TreadleException => { + success = false + val real = simulator.peek(s"cpu.csr.read_mapping_$num") + println(s"CSR $num failed to match. Was $real. Should be $value") + } + } + } + success + } + def checkRegs(vals: Map[Int, BigInt]): Boolean = { var success = true for ((num, value) <- vals) { @@ -128,6 +150,8 @@ class CPUTesterDriver(cpuType: String, case class CPUTestCase( binary: String, cycles: Map[String, Int], + initCSR: Map[Int, BigInt], + checkCSR: Map[Int, BigInt], initRegs: Map[Int, BigInt], checkRegs: Map[Int, BigInt], initMem: Map[Int, BigInt], @@ -143,10 +167,11 @@ case class CPUTestCase( object CPUTesterDriver { def apply(testCase: CPUTestCase, cpuType: String, branchPredictor: String = ""): Boolean = { val driver = new CPUTesterDriver(cpuType, branchPredictor, testCase.binary, testCase.extraName) + driver.initCSR(testCase.initCSR) driver.initRegs(testCase.initRegs) driver.initMemory(testCase.initMem) driver.run(testCase.cycles(cpuType)) - val success = driver.checkRegs(testCase.checkRegs) - success && driver.checkMemory(testCase.checkMem) + val success = driver.checkCSR(testCase.checkCSR) + success && driver.checkRegs(testCase.checkRegs) && driver.checkMemory(testCase.checkMem) } } diff --git a/src/main/scala/testing/InstTests.scala b/src/main/scala/testing/InstTests.scala index b265a169..d63bbbf6 100644 --- a/src/main/scala/testing/InstTests.scala +++ b/src/main/scala/testing/InstTests.scala @@ -9,6 +9,8 @@ package dinocpu * Each test case looks like: * - binary to run in src/test/resources/risc-v * - number of cycles to run for each CPU type + * - initial values for csr registers + * - final values to check for csr registers * - initial values for registers * - final values to check for registers * - initial values for memory @@ -30,71 +32,85 @@ object InstTests { val rtype = List[CPUTestCase]( CPUTestCase("add1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), CPUTestCase("add2", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1234, 20 -> 5678), Map(0 -> 0, 10 -> 6912), Map(), Map()), CPUTestCase("add0", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1234, 6 -> 3456), Map(0 -> 0, 5 -> 1234, 6 -> 3456), Map(), Map()), CPUTestCase("or", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1234, 6 -> 5678), Map(7 -> 5886), Map(), Map()), CPUTestCase("sub", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1234, 6 -> 5678), Map(7 -> BigInt("FFFFEEA4", 16)), Map(), Map()), CPUTestCase("and", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1234, 6 -> 5678), Map(7 -> 1026), Map(), Map()), CPUTestCase("xor", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> 1234, 5 -> 5678), Map(5 -> 5678, 7 -> 1234, 6 -> 4860), Map(), Map()), CPUTestCase("slt", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> 1234, 5 -> 5678), Map(5 -> 5678, 7 -> 1234, 6 -> 1), Map(), Map()), CPUTestCase("slt1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> -1, 5 -> 1), Map(5 -> 1, 6 -> 1), Map(), Map()), CPUTestCase("sltu", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> -1, 5 -> 1), Map(5 -> 1, 6 -> 0), Map(), Map()), CPUTestCase("sltu1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> 20, 5 -> 100), Map(5 -> 100, 6 -> 1), Map(), Map()), CPUTestCase("sll", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> 32, 5 -> 2), Map(7 -> 32, 5 -> 2, 6 -> 128), Map(), Map()), CPUTestCase("srl", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> 32, 5 -> 2), Map(7 -> 32, 5 -> 2, 6 -> 8), Map(), Map()), CPUTestCase("sra", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> twoscomp(-2), 5 -> 31), Map(5 -> 31, 6 -> twoscomp(-1)), Map(), Map()) @@ -103,41 +119,49 @@ object InstTests { val rtypeMultiCycle = List[CPUTestCase]( CPUTestCase("addfwd", Map("single-cycle" -> 10, "pipelined" -> 14), + Map(), Map()), Map(5 -> 1, 10 -> 0), Map(5 -> 1, 10 -> 10), Map(), Map()), CPUTestCase("swapxor", Map("single-cycle" -> 3, "pipelined" -> 7), + Map(), Map()), Map(7 -> 5678, 5 -> 1234), Map(5 -> 5678,7->1234), Map(), Map()), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), + Map(), Map()), Map(5 -> 512, 6->1), Map(7->1), Map(), Map(), "-512"), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), + Map(), Map()), Map(5 -> 1234, 6->1), Map(7->0), Map(), Map(), "-1234"), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), + Map(), Map()), Map(5 -> twoscomp(-65536), 6->1), Map(7->0), // This algorithm doesn't work for negative numbers Map(), Map(), "--65536"), CPUTestCase("oppsign", Map("single-cycle" -> 2, "pipelined" -> 7), + Map(), Map()), Map(5 -> 512, 6->twoscomp(-1024),7->0), Map(7->1), Map(), Map(), "-true"), CPUTestCase("oppsign", Map("single-cycle" -> 2, "pipelined" -> 7), + Map(), Map()), Map(5 -> 512, 6->1024,7->0), Map(7->0), Map(), Map(), "-false"), CPUTestCase("rotR", Map("single-cycle" -> 4, "pipelined" -> 8), + Map(), Map()), Map(5 -> twoscomp(-1), 6->1, 7->32), Map(7->twoscomp(-1)), Map(), Map()) @@ -146,59 +170,118 @@ object InstTests { val itype = List[CPUTestCase]( CPUTestCase("addi1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(0 -> 0, 10 -> 17), Map(), Map()), CPUTestCase("slli", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1), Map(0 -> 0, 5 -> 1, 6 -> 128), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1024), Map(0 -> 0, 5 -> 1024, 6 -> 8), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> twoscomp(-1024)), Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), Map(), Map(), "-negative"), CPUTestCase("srli", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 128), Map(0 -> 0, 5 -> 128, 6 -> 1), Map(), Map()), CPUTestCase("andi", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 200), Map(), Map()), CPUTestCase("ori", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 511), Map(), Map()), CPUTestCase("xori", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 311), Map(), Map()), CPUTestCase("slti", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1),6->1), Map(), Map()), CPUTestCase("sltiu", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), Map(), Map()) + CPUTestCase("csrrc", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrci", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrs", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrsi", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrw", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrwi", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) + CPUTestCase("ecall", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) + CPUTestCase("ebreak", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) ) val itypeMultiCycle = List[CPUTestCase]( CPUTestCase("addi2", Map("single-cycle" -> 2, "pipelined" -> 6), + Map(), Map()), Map(), Map(0 -> 0, 10 -> 17, 11 -> 93), Map(), Map()) @@ -207,91 +290,109 @@ object InstTests { val branch = List[CPUTestCase]( CPUTestCase("beq", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-False"), CPUTestCase("beq", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-True"), CPUTestCase("bne", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("bne", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-True"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-False-equal"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-True"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), Map(), Map(), "-False-signed"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), Map(), Map(), "-True-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-False"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(), Map(), "-True"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), Map(), Map(), "-False-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), Map(), Map(), "-True-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-True-equal"), CPUTestCase("bltu", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("bltu", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(), Map(), "-True"), CPUTestCase("bgeu", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(), Map(), "-False"), CPUTestCase("bgeu", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(), Map(), "-True") @@ -313,51 +414,61 @@ object InstTests { val memory = List[CPUTestCase]( CPUTestCase("lw1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(5 -> BigInt("ffffffff", 16)), Map(), Map()), CPUTestCase("lb", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(5 -> BigInt("04", 16)), Map(), Map()), CPUTestCase("lh", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(5 -> BigInt("0304", 16)), Map(), Map()), CPUTestCase("lbu", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(5 -> BigInt("f4", 16)), Map(), Map()), CPUTestCase("lhu", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(5 -> BigInt("f3f4", 16)), Map(), Map()), CPUTestCase("lb1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(5 -> BigInt("fffffff4", 16)), Map(), Map()), CPUTestCase("lh1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(5 -> BigInt("fffff3f4", 16)), Map(), Map()), CPUTestCase("sw", Map("single-cycle" -> 6, "pipelined" -> 10), + Map(), Map()), Map(5 -> 1234), Map(6 -> 1234), Map(), Map(0x100 -> 1234)), CPUTestCase("sb", Map("single-cycle" -> 6, "pipelined" -> 10), + Map(), Map()), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffffff01", 16))), CPUTestCase("sh", Map("single-cycle" -> 6, "pipelined" -> 10), + Map(), Map()), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffff0001", 16))) @@ -366,6 +477,7 @@ object InstTests { val memoryMultiCycle = List[CPUTestCase]( CPUTestCase("lwfwd", Map("single-cycle" -> 2, "pipelined" -> 7), + Map(), Map()), Map(5 -> BigInt("ffffffff", 16), 10 -> 5), Map(5 -> 1, 10 -> 6), Map(), Map()), @@ -384,21 +496,37 @@ object InstTests { val utype = List[CPUTestCase]( CPUTestCase("auipc0", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc2", Map("single-cycle" -> 2, "pipelined" -> 6), + Map(), Map()), Map(10 -> 1234), Map(10 -> (17 << 12)), Map(), Map()), CPUTestCase("lui0", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), + CPUTestCase("auipc1", + Map("single-cycle" -> 2, "pipelined" -> 6), + Map(), Map()), + Map(10 -> 1234), + Map(10 -> 4), + Map(), Map()), + CPUTestCase("auipc3", + Map("single-cycle" -> 2, "pipelined" -> 6), + Map(), Map()), + Map(10 -> 1234), + Map(10 -> ((17 << 12) + 4)), + Map(), Map()), CPUTestCase("lui1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(10 -> 1234), Map(10 -> 4096), Map(), Map()) @@ -407,11 +535,13 @@ object InstTests { val utypeMultiCycle = List[CPUTestCase]( CPUTestCase("auipc1", Map("single-cycle" -> 2, "pipelined" -> 6), + Map(), Map()), Map(10 -> 1234), Map(10 -> 4), Map(), Map()), CPUTestCase("auipc3", Map("single-cycle" -> 2, "pipelined" -> 6), + Map(), Map()), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()) @@ -420,16 +550,19 @@ object InstTests { val jump = List[CPUTestCase]( CPUTestCase("jal", Map("single-cycle" -> 2, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr0", Map("single-cycle" -> 2, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 10 -> 28), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr1", Map("single-cycle" -> 2, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 10 -> 20), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -438,21 +571,25 @@ object InstTests { val smallApplications = List[CPUTestCase]( CPUTestCase("fibonacci", Map("single-cycle" -> 300, "pipelined" -> 1000), + Map(), Map()), Map(6->11), Map(6->11,5->89), Map(), Map()), CPUTestCase("naturalsum", Map("single-cycle" -> 200, "pipelined" -> 500), + Map(), Map()), Map(), Map(5->55), Map(), Map()), CPUTestCase("multiplier", Map("single-cycle" -> 1000, "pipelined" -> 1000), + Map(), Map()), Map(5->23,6->20,8->0x1000), Map(5->23*20), Map(), Map()), CPUTestCase("divider", Map("single-cycle" -> 1000, "pipelined" -> 2000), + Map(), Map()), Map(5->1260,6->30), Map(7->42), Map(), Map()) @@ -461,31 +598,37 @@ object InstTests { val fullApplications = List[CPUTestCase]( CPUTestCase("multiply.riscv", Map("single-cycle" -> 42342, "pipelined" -> 100000), + Map(), Map()), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("median.riscv", Map("single-cycle" -> 9433, "pipelined" -> 100000), + Map(), Map()), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("qsort.riscv", Map("single-cycle" -> 263290, "pipelined" -> 300000), + Map(), Map()), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("rsort.riscv", Map("single-cycle" -> 263290, "pipelined" -> 250000), + Map(), Map()), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("towers.riscv", Map("single-cycle" -> 12653, "pipelined" -> 100000), + Map(), Map()), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("vvadd.riscv", Map("single-cycle" -> 5484, "pipelined" -> 20000), + Map(), Map()), Map(), Map(10->12345678), Map(), Map()) diff --git a/src/test/resources/risc-v/sw b/src/test/resources/risc-v/sw index 2aef06ce26a4592ff64114ab77cfa4668c361c18..4a12e983891160077c00550ebb56842279d81919 100755 GIT binary patch delta 399 zcmeyOy+wC|g76$s1~4#TP+(wW&|qL^VB2VXmY;btQ^Dr{{C}AziLgjIN&=M>Wfmuw zF);E2nXE-+#zvV&1qKrnfQ8}Xe>Nc304~JHzyoBnfCwNE z0Lse&X%-eR7szK~u!k_gqyW$~Jv4bMRK5~}8%QaV0imc07-A+*711{dc5w`GjCXQ% z_wYEUlZuPui%SxVN`T_X$|j!`F%i@QdtNWGq@*Y_sk9`ucrv4? zJ)^;7M^S50b)Z$u3=9Pz7k~hZ2m^!EOy%fFdL;1Bb}0+vZ4EE5xDCfkUJOimCH z@zsGS29k^nJV25KL;!&R0~3QXgbC#{GROg0EG!T~kh~Te-*ECr5q-|2;^O$?lEk8t z$swX96O*(j9}yK{)R}x!)Oxawm;f(}2m`|ckVYV8og679&AJ3AVm6skOn7pSm;mc7 JAWt2{0{~*pAWHxM diff --git a/src/test/resources/risc-v/sw.riscv b/src/test/resources/risc-v/sw.riscv index e62cbd8f..896bceb5 100644 --- a/src/test/resources/risc-v/sw.riscv +++ b/src/test/resources/risc-v/sw.riscv @@ -2,6 +2,7 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: + addi t0, x0, 7 sw t0, 0x400(zero) nop nop diff --git a/src/verilog/Top.DualPortedMemory.memory.v b/src/verilog/Top.DualPortedMemory.memory.v new file mode 100644 index 00000000..a41466f6 --- /dev/null +++ b/src/verilog/Top.DualPortedMemory.memory.v @@ -0,0 +1,20 @@ +module BindsTo_0_DualPortedMemory( + input clock, + input reset, + input [31:0] io_imem_address, + output [31:0] io_imem_instruction, + input [31:0] io_dmem_address, + input [31:0] io_dmem_writedata, + input io_dmem_memread, + input io_dmem_memwrite, + input [1:0] io_dmem_maskmode, + input io_dmem_sext, + output [31:0] io_dmem_readdata +); + +initial begin + $readmemh("test", DualPortedMemory.memory); +end + endmodule + +bind DualPortedMemory BindsTo_0_DualPortedMemory BindsTo_0_DualPortedMemory_Inst(.*); \ No newline at end of file diff --git a/src/verilog/obj_dir/VTop b/src/verilog/obj_dir/VTop new file mode 100755 index 0000000000000000000000000000000000000000..5e32ec84da8414f913821ae1cd31e4bff90c1c11 GIT binary patch literal 219584 zcmc$H3w%_?_5Usq2?!=WsPRcat>6QL5(P0Dl(iQn8i6SF(SQ&Hr0v@llQ1YP8lyrFxg8ZM0OPrSkuN&&<6$yPFM^+W!wf=H5AT z=FB-~&YYP!Gk5m3(D(~`1cL$ZU(dj~0jA22Q;>3>gkmuHp`Xka^01`?X7|q$akvR)yprhBRT!FK;~M_AR{+2rm4= z!hgLx^N6qh?z;MGna7e|y9I*9fyQ8A55g|T|NJ-fn7fXiQ8l%2)F)BTOjL&P_i0pm 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-*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See VTop.h for the primary calling header + +#include "VTop.h" // For This +#include "VTop__Syms.h" + + +//-------------------- +// STATIC VARIABLES + + +//-------------------- + +VL_CTOR_IMP(VTop) { + VTop__Syms* __restrict vlSymsp = __VlSymsp = new VTop__Syms(this, name()); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Reset internal values + + // Reset structure values + _ctor_var_reset(); +} + +void VTop::__Vconfigure(VTop__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +VTop::~VTop() { + delete __VlSymsp; __VlSymsp=NULL; +} + +//-------------------- + + +void VTop::eval() { + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VTop::eval\n"); ); + VTop__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +#ifdef VL_DEBUG + // Debug assertions + _eval_debug_assertions(); +#endif // VL_DEBUG + // Initialize + if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + while (VL_LIKELY(__Vchange)) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); + _eval(vlSymsp); + __Vchange = _change_request(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge"); + } +} + +void VTop::_eval_initial_loop(VTop__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + _eval_initial(vlSymsp); + int __VclockLoop = 0; + QData __Vchange = 1; + while (VL_LIKELY(__Vchange)) { + _eval_settle(vlSymsp); + _eval(vlSymsp); + __Vchange = _change_request(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge"); + } +} + +//-------------------- +// Internal Methods + +void VTop::_initial__TOP__1(VTop__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_initial__TOP__1\n"); ); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // INITIAL at Top.v:1440 + vlTOPp->io_success = 0U; +} + +VL_INLINE_OPT void VTop::_sequent__TOP__2(VTop__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_sequent__TOP__2\n"); ); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + VL_SIG8(__Vdlyvset__Top__DOT__mem__DOT__memory__v0,0,0); + VL_SIG8(__Vdlyvset__Top__DOT__mem__DOT__memory__v1,0,0); + VL_SIG16(__Vdlyvdim0__Top__DOT__mem__DOT__memory__v0,13,0); + VL_SIG16(__Vdlyvdim0__Top__DOT__mem__DOT__memory__v1,13,0); + VL_SIG(__Vdlyvval__Top__DOT__mem__DOT__memory__v0,31,0); + VL_SIG(__Vdlyvval__Top__DOT__mem__DOT__memory__v1,31,0); + VL_SIGW(__Vtemp1,95,0,3); + VL_SIGW(__Vtemp2,95,0,3); + VL_SIGW(__Vtemp3,95,0,3); + VL_SIGW(__Vtemp5,95,0,3); + VL_SIGW(__Vtemp6,95,0,3); + VL_SIGW(__Vtemp7,95,0,3); + VL_SIGW(__Vtemp8,95,0,3); + VL_SIGW(__Vtemp9,95,0,3); + VL_SIGW(__Vtemp15,95,0,3); + VL_SIGW(__Vtemp16,95,0,3); + // Body + // ALWAYS at Top.v:1335 + if (VL_UNLIKELY((((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & (3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))) + & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) + | (IData)(vlTOPp->reset)))))) { + VL_FWRITEF(0x80000002U,"Assertion failed\n at memory.scala:70 assert(io.dmem.address < size.U)\n"); + } + if (VL_UNLIKELY((((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & (3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))) + & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) + | (IData)(vlTOPp->reset)))))) { + VL_WRITEF("[%0t] %%Error: Top.v:1357: Assertion failed in %NTop.mem\n", + 64,VL_TIME_Q(),vlSymsp->name()); + VL_STOP_MT("Top.v",1357,""); + } + if (VL_UNLIKELY(((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) + & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) + | (IData)(vlTOPp->reset)))))) { + VL_FWRITEF(0x80000002U,"Assertion failed\n at memory.scala:99 assert(io.dmem.address < size.U)\n"); + } + if (VL_UNLIKELY(((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) + & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) + | (IData)(vlTOPp->reset)))))) { + VL_WRITEF("[%0t] %%Error: Top.v:1379: Assertion failed in %NTop.mem\n", + 64,VL_TIME_Q(),vlSymsp->name()); + VL_STOP_MT("Top.v",1379,""); + } + __Vdlyvset__Top__DOT__mem__DOT__memory__v0 = 0U; + __Vdlyvset__Top__DOT__mem__DOT__memory__v1 = 0U; + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((1U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((2U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((3U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((4U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((5U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((6U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((7U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((8U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((9U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0xaU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0xbU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0xcU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0xdU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0xeU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0xfU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x10U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x11U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x12U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x13U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x14U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x15U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x16U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x17U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x18U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x19U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:1136 + vlTOPp->Top__DOT__cpu__DOT__pc = ((IData)(vlTOPp->reset) + ? 0U : (((((0U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? + (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + == vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) + : + ((1U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? + (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + != vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) + : + ((4U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? + VL_LTS_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) + : + ((5U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? + VL_GTES_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) + : + ((6U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? + (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + < vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) + : + (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + >= vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2)))))) + & ((0x33U + != + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U + != + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((3U + != + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x23U + != + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & (0x63U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction))))))) + | (2U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_jump))) + ? vlTOPp->Top__DOT__cpu__DOT__branchAdd_io_result + : ( + (3U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_jump)) + ? + (0xfffffffeU + & (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) + : + ((IData)(4U) + + vlTOPp->Top__DOT__cpu__DOT__pcPlusFour_io_inputx)))); + // ALWAYS at Top.v:1335 + if (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) + & (2U != (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))))) { + VL_EXTEND_WI(71,32, __Vtemp1, vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data); + __Vtemp2[0U] = 0xffU; + __Vtemp2[1U] = 0U; + __Vtemp2[2U] = 0U; + VL_SHIFTL_WWI(71,71,6, __Vtemp3, __Vtemp2, + (0x18U & ((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10) + << 3U))); + __Vtemp5[0U] = (__Vtemp1[0U] & (~ __Vtemp3[0U])); + __Vtemp5[1U] = (__Vtemp1[1U] & (~ __Vtemp3[1U])); + __Vtemp5[2U] = (__Vtemp1[2U] & (~ __Vtemp3[2U])); + VL_EXTEND_WW(79,71, __Vtemp6, __Vtemp5); + VL_EXTEND_WI(79,32, __Vtemp7, vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data); + __Vtemp8[0U] = 0xffffU; + __Vtemp8[1U] = 0U; + __Vtemp8[2U] = 0U; + VL_SHIFTL_WWI(79,79,6, __Vtemp9, __Vtemp8, + (0x18U & ((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10) + << 3U))); + VL_EXTEND_WI(95,32, __Vtemp15, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2); + VL_SHIFTL_WWI(95,95,6, __Vtemp16, __Vtemp15, + (0x18U & ((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10) + << 3U))); + __Vdlyvval__Top__DOT__mem__DOT__memory__v0 + = (((0U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? __Vtemp6[0U] + : (__Vtemp7[0U] & (~ __Vtemp9[0U]))) + | __Vtemp16[0U]); + __Vdlyvset__Top__DOT__mem__DOT__memory__v0 = 1U; + __Vdlyvdim0__Top__DOT__mem__DOT__memory__v0 + = (0x3fffU & (IData)((vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U))); + } + if (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) + & (2U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))))) { + __Vdlyvval__Top__DOT__mem__DOT__memory__v1 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2; + __Vdlyvset__Top__DOT__mem__DOT__memory__v1 = 1U; + __Vdlyvdim0__Top__DOT__mem__DOT__memory__v1 + = (0x3fffU & (IData)((vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U))); + } + // ALWAYSPOST at Top.v:1336 + if (__Vdlyvset__Top__DOT__mem__DOT__memory__v0) { + vlTOPp->Top__DOT__mem__DOT__memory[__Vdlyvdim0__Top__DOT__mem__DOT__memory__v0] + = __Vdlyvval__Top__DOT__mem__DOT__memory__v0; + } + if (__Vdlyvset__Top__DOT__mem__DOT__memory__v1) { + vlTOPp->Top__DOT__mem__DOT__memory[__Vdlyvdim0__Top__DOT__mem__DOT__memory__v1] + = __Vdlyvval__Top__DOT__mem__DOT__memory__v1; + } + vlTOPp->Top__DOT__cpu__DOT__pcPlusFour_io_inputx + = vlTOPp->Top__DOT__cpu__DOT__pc; + vlTOPp->Top__DOT__mem_io_imem_instruction = ((0x10000U + <= vlTOPp->Top__DOT__cpu__DOT__pc) + ? 0U + : + vlTOPp->Top__DOT__mem__DOT__memory + [(0x3fffU + & (vlTOPp->Top__DOT__cpu__DOT__pc + >> 2U))]); + vlTOPp->Top__DOT__cpu__DOT__registers_io_wen = + (((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x23U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | (0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))) + & (0U != (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))); + vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite + = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((3U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & (0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_jump = ( + (0x33U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x13U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((3U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x23U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x63U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x37U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x17U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x6fU + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : + ((0x67U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 3U + : 0U))))))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_toreg = + ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 1U : ((0x23U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x63U + == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : + ((0x37U + == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : ((0x17U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x6fU + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : + ((0x67U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : 3U))))))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1 + = ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x23U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x63U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : ( + (0x37U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 1U + : + ((0x17U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : + (0x6fU + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction))))))))); + vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 + : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 + : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 + : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 + : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 + : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 + : ((0x19U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 + : ((0x18U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 + : ((0x17U == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 + : ((0x16U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 + : ( + (0x15U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 + : + ((0x14U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 + : + ((0x13U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 + : + ((0x12U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 + : + ((0x11U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 + : + ((0x10U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 + : + ((0xfU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 + : + ((0xeU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 + : + ((0xdU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 + : + ((0xcU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 + : + ((0xbU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 + : + ((0xaU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 + : + ((9U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 + : + ((8U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 + : + ((7U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 + : + ((6U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 + : + ((5U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 + : + ((4U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 + : + ((3U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 + : + ((2U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 + : + ((1U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 + : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); + vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2 + = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 + : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 + : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 + : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 + : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 + : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 + : ((0x19U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 + : ((0x18U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 + : ((0x17U == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 + : ((0x16U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 + : ( + (0x15U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 + : + ((0x14U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 + : + ((0x13U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 + : + ((0x12U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 + : + ((0x11U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 + : + ((0x10U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 + : + ((0xfU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 + : + ((0xeU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 + : + ((0xdU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 + : + ((0xcU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 + : + ((0xbU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 + : + ((0xaU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 + : + ((9U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 + : + ((8U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 + : + ((7U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 + : + ((6U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 + : + ((5U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 + : + ((4U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 + : + ((3U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 + : + ((2U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 + : + ((1U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 + : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_immediate + = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x6fU != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & (0x67U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))); + vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + = ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0xfffffU : 0U) << 0xcU) | (0xfffU & + (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))); + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx = ((0U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) + ? vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + : + ((1U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) + ? 0U + : vlTOPp->Top__DOT__cpu__DOT__pc)); + vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation + = (((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | (0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))) + ? 2U : ((0U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) + | (0U + == + (0x7fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x19U)))) + ? 2U + : 3U) + : ((1U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? 6U + : ((2U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 4U : ((3U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 5U : ((4U == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 9U + : ((5U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? + ((0U + == + (0x7fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x19U))) + ? 7U + : 8U) + : + ((6U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 1U + : + ((7U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 0U + : 0xfU))))))))); + vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm = + ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + : ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + : ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0x7ffU : 0U) << 0x15U) | + ((0x100000U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xbU)) | ((0xff000U + & vlTOPp->Top__DOT__mem_io_imem_instruction) + | ((0x800U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 9U)) + | (0x7feU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U)))))) + : ((0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + : ((0x63U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0x7ffffU : 0U) << 0xdU) + | ((0x1000U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x13U)) + | ((0x800U & (vlTOPp->Top__DOT__mem_io_imem_instruction + << 4U)) + | ((0x7e0U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U)) + | (0x1eU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))))) + : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + : ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? ((((0x80000000U + & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0xfffffU : 0U) + << 0xcU) | ((0xfe0U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U)) + | (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) + : ((0x13U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + : ((0x73U == + (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU)) + : 0U))))))))); + vlTOPp->Top__DOT__cpu__DOT__branchAdd_io_result + = (vlTOPp->Top__DOT__cpu__DOT__pc + vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm); + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy = ((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) + ? vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm + : vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2); + vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3 = (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + | vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy); + vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 = + (VL_ULL(0x7fffffffffffffff) & ((0U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3)) + : ((2U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : ( + (3U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : + ((4U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + VL_LTS_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : + ((5U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + < vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : + ((6U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + ((QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx)) + << + (0x1fU + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) + : (QData)((IData)( + ((7U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + >> + (0x1fU + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) + : + ((8U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + VL_SHIFTRS_III(32,32,5, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, + (0x1fU + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) + : + ((9U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + ^ vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy) + : + ((0xaU + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + (~ vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3) + : 0U)))))))))))))); + vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data + = vlTOPp->Top__DOT__mem__DOT__memory[(0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))]; + vlTOPp->Top__DOT__mem__DOT___GEN_14 = ((2U != (3U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? ((0U + == + (3U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? (0xffU + & vlTOPp->Top__DOT__mem__DOT__memory + [ + (0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))]) + : (0xffffU + & vlTOPp->Top__DOT__mem__DOT__memory + [ + (0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))])) + : vlTOPp->Top__DOT__mem__DOT__memory + [(0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))]); + vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata + = ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) + ? ((0x4000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? vlTOPp->Top__DOT__mem__DOT___GEN_14 + : ((0U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? ((((0x80U + & vlTOPp->Top__DOT__mem__DOT___GEN_14) + ? 0xffffffU + : 0U) + << 8U) + | (0xffU + & vlTOPp->Top__DOT__mem__DOT___GEN_14)) + : ((1U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? ( + (((0x8000U + & vlTOPp->Top__DOT__mem__DOT___GEN_14) + ? 0xffffU + : 0U) + << 0x10U) + | (0xffffU + & vlTOPp->Top__DOT__mem__DOT___GEN_14)) + : vlTOPp->Top__DOT__mem__DOT___GEN_14))) + : ((2U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) + ? ((IData)(4U) + vlTOPp->Top__DOT__cpu__DOT__pc) + : (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10))); +} + +void VTop::_settle__TOP__3(VTop__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_settle__TOP__3\n"); ); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->Top__DOT__cpu__DOT__pcPlusFour_io_inputx + = vlTOPp->Top__DOT__cpu__DOT__pc; + vlTOPp->Top__DOT__mem_io_imem_instruction = ((0x10000U + <= vlTOPp->Top__DOT__cpu__DOT__pc) + ? 0U + : + vlTOPp->Top__DOT__mem__DOT__memory + [(0x3fffU + & (vlTOPp->Top__DOT__cpu__DOT__pc + >> 2U))]); + vlTOPp->Top__DOT__cpu__DOT__registers_io_wen = + (((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x23U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | (0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))) + & (0U != (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))); + vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite + = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((3U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & (0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_jump = ( + (0x33U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x13U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((3U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x23U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x63U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x37U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x17U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x6fU + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : + ((0x67U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 3U + : 0U))))))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_toreg = + ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 1U : ((0x23U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x63U + == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : + ((0x37U + == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : ((0x17U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x6fU + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : + ((0x67U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : 3U))))))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1 + = ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x23U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x63U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : ( + (0x37U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 1U + : + ((0x17U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : + (0x6fU + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction))))))))); + vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 + : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 + : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 + : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 + : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 + : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 + : ((0x19U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 + : ((0x18U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 + : ((0x17U == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 + : ((0x16U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 + : ( + (0x15U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 + : + ((0x14U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 + : + ((0x13U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 + : + ((0x12U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 + : + ((0x11U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 + : + ((0x10U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 + : + ((0xfU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 + : + ((0xeU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 + : + ((0xdU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 + : + ((0xcU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 + : + ((0xbU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 + : + ((0xaU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 + : + ((9U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 + : + ((8U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 + : + ((7U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 + : + ((6U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 + : + ((5U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 + : + ((4U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 + : + ((3U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 + : + ((2U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 + : + ((1U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 + : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); + vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2 + = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 + : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 + : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 + : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 + : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 + : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 + : ((0x19U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 + : ((0x18U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 + : ((0x17U == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 + : ((0x16U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 + : ( + (0x15U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 + : + ((0x14U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 + : + ((0x13U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 + : + ((0x12U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 + : + ((0x11U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 + : + ((0x10U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 + : + ((0xfU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 + : + ((0xeU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 + : + ((0xdU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 + : + ((0xcU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 + : + ((0xbU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 + : + ((0xaU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 + : + ((9U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 + : + ((8U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 + : + ((7U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 + : + ((6U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 + : + ((5U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 + : + ((4U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 + : + ((3U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 + : + ((2U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 + : + ((1U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 + : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_immediate + = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x6fU != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & (0x67U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))); + vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + = ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0xfffffU : 0U) << 0xcU) | (0xfffU & + (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))); + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx = ((0U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) + ? vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + : + ((1U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) + ? 0U + : vlTOPp->Top__DOT__cpu__DOT__pc)); + vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation + = (((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | (0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))) + ? 2U : ((0U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) + | (0U + == + (0x7fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x19U)))) + ? 2U + : 3U) + : ((1U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? 6U + : ((2U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 4U : ((3U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 5U : ((4U == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 9U + : ((5U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? + ((0U + == + (0x7fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x19U))) + ? 7U + : 8U) + : + ((6U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 1U + : + ((7U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 0U + : 0xfU))))))))); + vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm = + ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + : ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + : ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0x7ffU : 0U) << 0x15U) | + ((0x100000U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xbU)) | ((0xff000U + & vlTOPp->Top__DOT__mem_io_imem_instruction) + | ((0x800U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 9U)) + | (0x7feU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U)))))) + : ((0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + : ((0x63U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0x7ffffU : 0U) << 0xdU) + | ((0x1000U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x13U)) + | ((0x800U & (vlTOPp->Top__DOT__mem_io_imem_instruction + << 4U)) + | ((0x7e0U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U)) + | (0x1eU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))))) + : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + : ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? ((((0x80000000U + & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0xfffffU : 0U) + << 0xcU) | ((0xfe0U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U)) + | (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) + : ((0x13U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + : ((0x73U == + (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU)) + : 0U))))))))); + vlTOPp->Top__DOT__cpu__DOT__branchAdd_io_result + = (vlTOPp->Top__DOT__cpu__DOT__pc + vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm); + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy = ((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) + ? vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm + : vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2); + vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3 = (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + | vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy); + vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 = + (VL_ULL(0x7fffffffffffffff) & ((0U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3)) + : ((2U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : ( + (3U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : + ((4U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + VL_LTS_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : + ((5U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + < vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : + ((6U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + ((QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx)) + << + (0x1fU + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) + : (QData)((IData)( + ((7U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + >> + (0x1fU + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) + : + ((8U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + VL_SHIFTRS_III(32,32,5, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, + (0x1fU + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) + : + ((9U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + ^ vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy) + : + ((0xaU + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + (~ vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3) + : 0U)))))))))))))); + vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data + = vlTOPp->Top__DOT__mem__DOT__memory[(0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))]; + vlTOPp->Top__DOT__mem__DOT___GEN_14 = ((2U != (3U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? ((0U + == + (3U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? (0xffU + & vlTOPp->Top__DOT__mem__DOT__memory + [ + (0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))]) + : (0xffffU + & vlTOPp->Top__DOT__mem__DOT__memory + [ + (0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))])) + : vlTOPp->Top__DOT__mem__DOT__memory + [(0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))]); + vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata + = ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) + ? ((0x4000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? vlTOPp->Top__DOT__mem__DOT___GEN_14 + : ((0U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? ((((0x80U + & vlTOPp->Top__DOT__mem__DOT___GEN_14) + ? 0xffffffU + : 0U) + << 8U) + | (0xffU + & vlTOPp->Top__DOT__mem__DOT___GEN_14)) + : ((1U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? ( + (((0x8000U + & vlTOPp->Top__DOT__mem__DOT___GEN_14) + ? 0xffffU + : 0U) + << 0x10U) + | (0xffffU + & vlTOPp->Top__DOT__mem__DOT___GEN_14)) + : vlTOPp->Top__DOT__mem__DOT___GEN_14))) + : ((2U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) + ? ((IData)(4U) + vlTOPp->Top__DOT__cpu__DOT__pc) + : (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10))); +} + +void VTop::_eval(VTop__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval\n"); ); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + if (((IData)(vlTOPp->clock) & (~ (IData)(vlTOPp->__Vclklast__TOP__clock)))) { + vlTOPp->_sequent__TOP__2(vlSymsp); + } + // Final + vlTOPp->__Vclklast__TOP__clock = vlTOPp->clock; +} + +void VTop::_eval_initial(VTop__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval_initial\n"); ); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_initial__TOP__1(vlSymsp); +} + +void VTop::final() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::final\n"); ); + // Variables + VTop__Syms* __restrict vlSymsp = this->__VlSymsp; + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void VTop::_eval_settle(VTop__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval_settle\n"); ); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_settle__TOP__3(vlSymsp); +} + +VL_INLINE_OPT QData VTop::_change_request(VTop__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_change_request\n"); ); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // Change detection + QData __req = false; // Logically a bool + return __req; +} + +#ifdef VL_DEBUG +void VTop::_eval_debug_assertions() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((clock & 0xfeU))) { + Verilated::overWidthError("clock");} + if (VL_UNLIKELY((reset & 0xfeU))) { + Verilated::overWidthError("reset");} +} +#endif // VL_DEBUG + +void VTop::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_ctor_var_reset\n"); ); + // Body + clock = VL_RAND_RESET_I(1); + reset = VL_RAND_RESET_I(1); + io_success = VL_RAND_RESET_I(1); + Top__DOT__mem_io_imem_instruction = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__control_io_toreg = VL_RAND_RESET_I(2); + Top__DOT__cpu__DOT__control_io_memwrite = VL_RAND_RESET_I(1); + Top__DOT__cpu__DOT__control_io_immediate = VL_RAND_RESET_I(1); + Top__DOT__cpu__DOT__control_io_alusrc1 = VL_RAND_RESET_I(2); + Top__DOT__cpu__DOT__control_io_jump = VL_RAND_RESET_I(2); + Top__DOT__cpu__DOT__registers_io_writedata = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers_io_wen = VL_RAND_RESET_I(1); + Top__DOT__cpu__DOT__registers_io_readdata1 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers_io_readdata2 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__aluControl_io_operation = VL_RAND_RESET_I(4); + Top__DOT__cpu__DOT__alu_io_inputx = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__alu_io_inputy = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__immGen_io_sextImm = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__pcPlusFour_io_inputx = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__branchAdd_io_result = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__pc = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_0 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_1 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_2 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_3 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_4 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_5 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_6 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_7 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_8 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_9 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_10 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_11 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_12 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_13 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_14 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_15 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_16 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_17 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_18 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_19 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_20 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_21 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_22 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_23 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_24 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_25 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_26 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_27 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_28 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_29 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_30 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_31 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__alu__DOT___T_3 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__alu__DOT___GEN_10 = VL_RAND_RESET_Q(63); + Top__DOT__cpu__DOT__immGen__DOT___T_26 = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<16384; ++__Vi0) { + Top__DOT__mem__DOT__memory[__Vi0] = VL_RAND_RESET_I(32); + }} + Top__DOT__mem__DOT__memory___05FT_49_data = VL_RAND_RESET_I(32); + Top__DOT__mem__DOT___GEN_14 = VL_RAND_RESET_I(32); + __Vclklast__TOP__clock = VL_RAND_RESET_I(1); +} diff --git a/src/verilog/obj_dir/VTop.h b/src/verilog/obj_dir/VTop.h new file mode 100644 index 00000000..116188ff --- /dev/null +++ b/src/verilog/obj_dir/VTop.h @@ -0,0 +1,136 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Primary design header +// +// This header should be included by all source files instantiating the design. +// The class here is then constructed to instantiate the design. +// See the Verilator manual for examples. + +#ifndef _VTop_H_ +#define _VTop_H_ + +#include "verilated_heavy.h" + +class VTop__Syms; + +//---------- + +VL_MODULE(VTop) { + public: + + // PORTS + // The application code writes and reads these signals to + // propagate new values into/out from the Verilated model. + VL_IN8(clock,0,0); + VL_IN8(reset,0,0); + VL_OUT8(io_success,0,0); + + // LOCAL SIGNALS + // Internals; generally not touched by application code + VL_SIG8(Top__DOT__cpu__DOT__control_io_toreg,1,0); + VL_SIG8(Top__DOT__cpu__DOT__control_io_memwrite,0,0); + VL_SIG8(Top__DOT__cpu__DOT__control_io_immediate,0,0); + VL_SIG8(Top__DOT__cpu__DOT__control_io_alusrc1,1,0); + VL_SIG8(Top__DOT__cpu__DOT__control_io_jump,1,0); + VL_SIG8(Top__DOT__cpu__DOT__registers_io_wen,0,0); + VL_SIG8(Top__DOT__cpu__DOT__aluControl_io_operation,3,0); + VL_SIG(Top__DOT__mem_io_imem_instruction,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers_io_writedata,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers_io_readdata1,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers_io_readdata2,31,0); + VL_SIG(Top__DOT__cpu__DOT__alu_io_inputx,31,0); + VL_SIG(Top__DOT__cpu__DOT__alu_io_inputy,31,0); + VL_SIG(Top__DOT__cpu__DOT__immGen_io_sextImm,31,0); + VL_SIG(Top__DOT__cpu__DOT__pcPlusFour_io_inputx,31,0); + VL_SIG(Top__DOT__cpu__DOT__branchAdd_io_result,31,0); + VL_SIG(Top__DOT__cpu__DOT__pc,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_0,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_1,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_2,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_3,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_4,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_5,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_6,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_7,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_8,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_9,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_10,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_11,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_12,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_13,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_14,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_15,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_16,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_17,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_18,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_19,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_20,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_21,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_22,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_23,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_24,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_25,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_26,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_27,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_28,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_29,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_30,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_31,31,0); + VL_SIG(Top__DOT__cpu__DOT__alu__DOT___T_3,31,0); + VL_SIG(Top__DOT__cpu__DOT__immGen__DOT___T_26,31,0); + VL_SIG(Top__DOT__mem__DOT__memory___05FT_49_data,31,0); + VL_SIG(Top__DOT__mem__DOT___GEN_14,31,0); + VL_SIG64(Top__DOT__cpu__DOT__alu__DOT___GEN_10,62,0); + VL_SIG(Top__DOT__mem__DOT__memory[16384],31,0); + + // LOCAL VARIABLES + // Internals; generally not touched by application code + VL_SIG8(__Vclklast__TOP__clock,0,0); + + // INTERNAL VARIABLES + // Internals; generally not touched by application code + VTop__Syms* __VlSymsp; // Symbol table + + // PARAMETERS + // Parameters marked /*verilator public*/ for use by application code + + // CONSTRUCTORS + private: + VTop& operator= (const VTop&); ///< Copying not allowed + VTop(const VTop&); ///< Copying not allowed + public: + /// Construct the model; called by application code + /// The special name may be used to make a wrapper with a + /// single model invisible WRT DPI scope names. + VTop(const char* name="TOP"); + /// Destroy the model; called (often implicitly) by application code + ~VTop(); + + // API METHODS + /// Evaluate the model. Application must call when inputs change. + void eval(); + /// Simulation complete, run final blocks. Application must call on completion. + void final(); + + // INTERNAL METHODS + private: + static void _eval_initial_loop(VTop__Syms* __restrict vlSymsp); + public: + void __Vconfigure(VTop__Syms* symsp, bool first); + private: + static QData _change_request(VTop__Syms* __restrict vlSymsp); + void _ctor_var_reset(); + public: + static void _eval(VTop__Syms* __restrict vlSymsp); + private: +#ifdef VL_DEBUG + void _eval_debug_assertions(); +#endif // VL_DEBUG + public: + static void _eval_initial(VTop__Syms* __restrict vlSymsp); + static void _eval_settle(VTop__Syms* __restrict vlSymsp); + static void _initial__TOP__1(VTop__Syms* __restrict vlSymsp); + static void _sequent__TOP__2(VTop__Syms* __restrict vlSymsp); + static void _settle__TOP__3(VTop__Syms* __restrict vlSymsp); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/src/verilog/obj_dir/VTop.mk b/src/verilog/obj_dir/VTop.mk new file mode 100644 index 00000000..d3f88421 --- /dev/null +++ b/src/verilog/obj_dir/VTop.mk @@ -0,0 +1,66 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable +# +# Execute this makefile from the object directory: +# make -f VTop.mk + +default: VTop + +### Constants... +# Perl executable (from $PERL) +PERL = perl +# Path to Verilator kit (from $VERILATOR_ROOT) +VERILATOR_ROOT = /usr/share/verilator +# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) +SYSTEMC_INCLUDE ?= +# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) +SYSTEMC_LIBDIR ?= + +### Switches... +# SystemC output mode? 0/1 (from --sc) +VM_SC = 0 +# Legacy or SystemC output mode? 0/1 (from --sc) +VM_SP_OR_SC = $(VM_SC) +# Deprecated +VM_PCLI = 1 +# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) +VM_SC_TARGET_ARCH = linux + +### Vars... +# Design prefix (from --prefix) +VM_PREFIX = VTop +# Module prefix (from --prefix) +VM_MODPREFIX = VTop +# User CFLAGS (from -CFLAGS on Verilator command line) +VM_USER_CFLAGS = \ + +# User LDLIBS (from -LDFLAGS on Verilator command line) +VM_USER_LDLIBS = \ + +# User .cpp files (from .cpp's on Verilator command line) +VM_USER_CLASSES = \ + testbench \ + +# User .cpp directories (from .cpp's on Verilator command line) +VM_USER_DIR = \ + . \ + + +### Default rules... +# Include list of all generated classes +include VTop_classes.mk +# Include global rules +include $(VERILATOR_ROOT)/include/verilated.mk + +### Executable rules... (from --exe) +VPATH += $(VM_USER_DIR) + +testbench.o: testbench.cpp + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< + +### Link rules... (from --exe) +VTop: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a + $(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) 2>&1 | c++filt + + +# Verilated -*- Makefile -*- diff --git a/src/verilog/obj_dir/VTop__ALLcls.cpp b/src/verilog/obj_dir/VTop__ALLcls.cpp new file mode 100644 index 00000000..22511a67 --- /dev/null +++ b/src/verilog/obj_dir/VTop__ALLcls.cpp @@ -0,0 +1,3 @@ +// DESCRIPTION: Generated by verilator_includer via makefile +#define VL_INCLUDE_OPT include +#include "VTop.cpp" diff --git a/src/verilog/obj_dir/VTop__ALLcls.d b/src/verilog/obj_dir/VTop__ALLcls.d new file mode 100644 index 00000000..e0058e71 --- /dev/null +++ b/src/verilog/obj_dir/VTop__ALLcls.d @@ -0,0 +1,5 @@ +VTop__ALLcls.o: VTop__ALLcls.cpp VTop.cpp VTop.h \ + /usr/share/verilator/include/verilated_heavy.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilatedos.h VTop__Syms.h diff --git a/src/verilog/obj_dir/VTop__ALLsup.cpp b/src/verilog/obj_dir/VTop__ALLsup.cpp new file mode 100644 index 00000000..2aa533ee --- /dev/null +++ b/src/verilog/obj_dir/VTop__ALLsup.cpp @@ -0,0 +1,3 @@ +// DESCRIPTION: Generated by verilator_includer via makefile +#define VL_INCLUDE_OPT include +#include "VTop__Syms.cpp" diff --git a/src/verilog/obj_dir/VTop__ALLsup.d b/src/verilog/obj_dir/VTop__ALLsup.d new file mode 100644 index 00000000..cf982fbd --- /dev/null +++ b/src/verilog/obj_dir/VTop__ALLsup.d @@ -0,0 +1,5 @@ +VTop__ALLsup.o: VTop__ALLsup.cpp VTop__Syms.cpp VTop__Syms.h \ + /usr/share/verilator/include/verilated_heavy.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilatedos.h VTop.h diff --git a/src/verilog/obj_dir/VTop__Syms.cpp b/src/verilog/obj_dir/VTop__Syms.cpp new file mode 100644 index 00000000..8d3e9168 --- /dev/null +++ b/src/verilog/obj_dir/VTop__Syms.cpp @@ -0,0 +1,21 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table implementation internals + +#include "VTop__Syms.h" +#include "VTop.h" + +// FUNCTIONS +VTop__Syms::VTop__Syms(VTop* topp, const char* namep) + // Setup locals + : __Vm_namep(namep) + , __Vm_didInit(false) + // Setup submodule names +{ + // Pointer to top level + TOPp = topp; + // Setup each module's pointers to their submodules + // Setup each module's pointer back to symbol table (for public functions) + TOPp->__Vconfigure(this, true); + // Setup scope names + __Vscope_Top__mem.configure(this,name(),"Top.mem"); +} diff --git a/src/verilog/obj_dir/VTop__Syms.h b/src/verilog/obj_dir/VTop__Syms.h new file mode 100644 index 00000000..7ce62123 --- /dev/null +++ b/src/verilog/obj_dir/VTop__Syms.h @@ -0,0 +1,37 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table internal header +// +// Internal details; most calling programs do not need this header + +#ifndef _VTop__Syms_H_ +#define _VTop__Syms_H_ + +#include "verilated_heavy.h" + +// INCLUDE MODULE CLASSES +#include "VTop.h" + +// SYMS CLASS +class VTop__Syms : public VerilatedSyms { + public: + + // LOCAL STATE + const char* __Vm_namep; + bool __Vm_didInit; + + // SUBCELL STATE + VTop* TOPp; + + // SCOPE NAMES + VerilatedScope __Vscope_Top__mem; + + // CREATORS + VTop__Syms(VTop* topp, const char* namep); + ~VTop__Syms() {} + + // METHODS + inline const char* name() { return __Vm_namep; } + +} VL_ATTR_ALIGNED(64); + +#endif // guard diff --git a/src/verilog/obj_dir/VTop__ver.d b/src/verilog/obj_dir/VTop__ver.d new file mode 100644 index 00000000..e6618c98 --- /dev/null +++ b/src/verilog/obj_dir/VTop__ver.d @@ -0,0 +1 @@ +obj_dir/VTop.cpp obj_dir/VTop.h obj_dir/VTop.mk obj_dir/VTop__Syms.cpp obj_dir/VTop__Syms.h obj_dir/VTop__ver.d obj_dir/VTop_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin Top.v diff --git a/src/verilog/obj_dir/VTop__verFiles.dat b/src/verilog/obj_dir/VTop__verFiles.dat new file mode 100644 index 00000000..090b1097 --- /dev/null +++ b/src/verilog/obj_dir/VTop__verFiles.dat @@ -0,0 +1,12 @@ +# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. +C "--cc Top.v --exe testbench.cpp" +S 5279832 27263155 1541808233 963237689 1519110675 0 "/usr/bin/verilator_bin" +S 64006 10630799 1554939392 89651087 1554938775 745850810 "Top.v" +T 81093 11144428 1554939420 685597879 1554939420 685597879 "obj_dir/VTop.cpp" +T 5774 11144427 1554939420 685597879 1554939420 685597879 "obj_dir/VTop.h" +T 1753 11144430 1554939420 685597879 1554939420 685597879 "obj_dir/VTop.mk" +T 596 11144426 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__Syms.cpp" +T 758 11144425 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__Syms.h" +T 194 11144431 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__ver.d" +T 0 0 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__verFiles.dat" +T 1150 11144429 1554939420 685597879 1554939420 685597879 "obj_dir/VTop_classes.mk" diff --git a/src/verilog/obj_dir/VTop_classes.mk b/src/verilog/obj_dir/VTop_classes.mk new file mode 100644 index 00000000..4e59be86 --- /dev/null +++ b/src/verilog/obj_dir/VTop_classes.mk @@ -0,0 +1,38 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Make include file with class lists +# +# This file lists generated Verilated files, for including in higher level makefiles. +# See VTop.mk for the caller. + +### Switches... +# Coverage output mode? 0/1 (from --coverage) +VM_COVERAGE = 0 +# Threaded output mode? 0/1/N threads (from --threads) +VM_THREADS = 0 +# Tracing output mode? 0/1 (from --trace) +VM_TRACE = 0 + +### Object file lists... +# Generated module classes, fast-path, compile with highest optimization +VM_CLASSES_FAST += \ + VTop \ + +# Generated module classes, non-fast-path, compile with low/medium optimization +VM_CLASSES_SLOW += \ + +# Generated support classes, fast-path, compile with highest optimization +VM_SUPPORT_FAST += \ + +# Generated support classes, non-fast-path, compile with low/medium optimization +VM_SUPPORT_SLOW += \ + VTop__Syms \ + +# Global classes, need linked once per executable, fast-path, compile with highest optimization +VM_GLOBAL_FAST += \ + verilated \ + +# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization +VM_GLOBAL_SLOW += \ + + +# Verilated -*- Makefile -*- diff --git a/src/verilog/obj_dir/testbench.d b/src/verilog/obj_dir/testbench.d new file mode 100644 index 00000000..984246f0 --- /dev/null +++ b/src/verilog/obj_dir/testbench.d @@ -0,0 +1,6 @@ +testbench.o: ../testbench.cpp VTop.h \ + /usr/share/verilator/include/verilated_heavy.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated.h diff --git a/src/verilog/obj_dir/verilated.d b/src/verilog/obj_dir/verilated.d new file mode 100644 index 00000000..378ca2d9 --- /dev/null +++ b/src/verilog/obj_dir/verilated.d @@ -0,0 +1,7 @@ +verilated.o: /usr/share/verilator/include/verilated.cpp \ + /usr/share/verilator/include/verilated_imp.h \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilated_heavy.h \ + /usr/share/verilator/include/verilated_syms.h diff --git a/src/verilog/testbench.cpp b/src/verilog/testbench.cpp new file mode 100644 index 00000000..05a0db31 --- /dev/null +++ b/src/verilog/testbench.cpp @@ -0,0 +1,33 @@ +#include "VTop.h" +#include + vluint64_t main_time = 0; // Current simulation time + // This is a 64-bit integer to reduce wrap over issues and + // allow modulus. You can also use a double, if you wish. + + double sc_time_stamp () { // Called by $time in Verilog + return main_time; // converts to double, to match + // what SystemC does + } + + +int main(int argc, char** argv, char** env){ + Verilated::commandArgs(argc, argv); + VTop* top = new VTop; + //reset + top->reset = 1; + top->clock = 0; + top->eval(); + top->clock = 1; + top->eval(); + top->reset = 0; + + while(!Verilated::gotFinish()){ + top->clock = 0; + top->eval(); + + top->clock = 1; + top->eval(); + } + delete top; + exit(0); +} From 684d5a38237d3f168d367a7301b34f61ecb4b7ef Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 1 May 2019 20:30:40 -0700 Subject: [PATCH 02/57] csr implemented, needs testing, cleaned verilog stuff --- src/verilog/Top.DualPortedMemory.memory.v | 20 - src/verilog/obj_dir/VTop | Bin 219584 -> 0 bytes src/verilog/obj_dir/VTop.cpp | 2181 --------------------- src/verilog/obj_dir/VTop.h | 136 -- src/verilog/obj_dir/VTop.mk | 66 - src/verilog/obj_dir/VTop__ALLcls.cpp | 3 - src/verilog/obj_dir/VTop__ALLcls.d | 5 - src/verilog/obj_dir/VTop__ALLsup.cpp | 3 - src/verilog/obj_dir/VTop__ALLsup.d | 5 - src/verilog/obj_dir/VTop__Syms.cpp | 21 - src/verilog/obj_dir/VTop__Syms.h | 37 - src/verilog/obj_dir/VTop__ver.d | 1 - src/verilog/obj_dir/VTop__verFiles.dat | 12 - src/verilog/obj_dir/VTop_classes.mk | 38 - src/verilog/obj_dir/testbench.d | 6 - src/verilog/obj_dir/verilated.d | 7 - 16 files changed, 2541 deletions(-) delete mode 100644 src/verilog/Top.DualPortedMemory.memory.v delete mode 100755 src/verilog/obj_dir/VTop delete mode 100644 src/verilog/obj_dir/VTop.cpp delete mode 100644 src/verilog/obj_dir/VTop.h delete mode 100644 src/verilog/obj_dir/VTop.mk delete mode 100644 src/verilog/obj_dir/VTop__ALLcls.cpp delete mode 100644 src/verilog/obj_dir/VTop__ALLcls.d delete mode 100644 src/verilog/obj_dir/VTop__ALLsup.cpp delete mode 100644 src/verilog/obj_dir/VTop__ALLsup.d delete mode 100644 src/verilog/obj_dir/VTop__Syms.cpp delete mode 100644 src/verilog/obj_dir/VTop__Syms.h delete mode 100644 src/verilog/obj_dir/VTop__ver.d delete mode 100644 src/verilog/obj_dir/VTop__verFiles.dat delete mode 100644 src/verilog/obj_dir/VTop_classes.mk delete mode 100644 src/verilog/obj_dir/testbench.d delete mode 100644 src/verilog/obj_dir/verilated.d diff --git a/src/verilog/Top.DualPortedMemory.memory.v b/src/verilog/Top.DualPortedMemory.memory.v deleted file mode 100644 index a41466f6..00000000 --- a/src/verilog/Top.DualPortedMemory.memory.v +++ /dev/null @@ -1,20 +0,0 @@ -module BindsTo_0_DualPortedMemory( - input clock, - input reset, - input [31:0] io_imem_address, - output [31:0] io_imem_instruction, - input [31:0] io_dmem_address, - input [31:0] io_dmem_writedata, - input io_dmem_memread, - input io_dmem_memwrite, - input [1:0] io_dmem_maskmode, - input io_dmem_sext, - output [31:0] io_dmem_readdata -); - -initial begin - $readmemh("test", DualPortedMemory.memory); -end - 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z-u<6>S?{;k?|BdOzNUVO`)A>w@V0#3zT-Z;YK!>oZJ%$izenj^@Xy}g#{1iL)cb8Y zLlpnn@Amo^V0LUtnZtSi;kM}WAC@u zmw>tVr)KN@DL&YaQ**O(zx}=~ZWdbh`SW=HT;4zLVp~$L^WtAqufhHD{6-JA_aETl zQdU0h)q6$r`w_PO?>AplqKESMXW!etmy8cvcP**^A3LH{?|R%tqvu+5SNxH5|3OD8 NI@?y1H+WxD{}0teW&i*H diff --git a/src/verilog/obj_dir/VTop.cpp b/src/verilog/obj_dir/VTop.cpp deleted file mode 100644 index 5aa4cf83..00000000 --- a/src/verilog/obj_dir/VTop.cpp +++ /dev/null @@ -1,2181 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See VTop.h for the primary calling header - -#include "VTop.h" // For This -#include "VTop__Syms.h" - - -//-------------------- -// STATIC VARIABLES - - -//-------------------- - -VL_CTOR_IMP(VTop) { - VTop__Syms* __restrict vlSymsp = __VlSymsp = new VTop__Syms(this, name()); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Reset internal values - - // Reset structure values - _ctor_var_reset(); -} - -void VTop::__Vconfigure(VTop__Syms* vlSymsp, bool first) { - if (0 && first) {} // Prevent unused - this->__VlSymsp = vlSymsp; -} - -VTop::~VTop() { - delete __VlSymsp; __VlSymsp=NULL; -} - -//-------------------- - - -void VTop::eval() { - VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VTop::eval\n"); ); - VTop__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; -#ifdef VL_DEBUG - // Debug assertions - _eval_debug_assertions(); -#endif // VL_DEBUG - // Initialize - if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); - // Evaluate till stable - int __VclockLoop = 0; - QData __Vchange = 1; - while (VL_LIKELY(__Vchange)) { - VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); - _eval(vlSymsp); - __Vchange = _change_request(vlSymsp); - if (VL_UNLIKELY(++__VclockLoop > 100)) VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge"); - } -} - -void VTop::_eval_initial_loop(VTop__Syms* __restrict vlSymsp) { - vlSymsp->__Vm_didInit = true; - _eval_initial(vlSymsp); - int __VclockLoop = 0; - QData __Vchange = 1; - while (VL_LIKELY(__Vchange)) { - _eval_settle(vlSymsp); - _eval(vlSymsp); - __Vchange = _change_request(vlSymsp); - if (VL_UNLIKELY(++__VclockLoop > 100)) VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge"); - } -} - -//-------------------- -// Internal Methods - -void VTop::_initial__TOP__1(VTop__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_initial__TOP__1\n"); ); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - // INITIAL at Top.v:1440 - vlTOPp->io_success = 0U; -} - -VL_INLINE_OPT void VTop::_sequent__TOP__2(VTop__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_sequent__TOP__2\n"); ); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Variables - VL_SIG8(__Vdlyvset__Top__DOT__mem__DOT__memory__v0,0,0); - VL_SIG8(__Vdlyvset__Top__DOT__mem__DOT__memory__v1,0,0); - VL_SIG16(__Vdlyvdim0__Top__DOT__mem__DOT__memory__v0,13,0); - VL_SIG16(__Vdlyvdim0__Top__DOT__mem__DOT__memory__v1,13,0); - VL_SIG(__Vdlyvval__Top__DOT__mem__DOT__memory__v0,31,0); - VL_SIG(__Vdlyvval__Top__DOT__mem__DOT__memory__v1,31,0); - VL_SIGW(__Vtemp1,95,0,3); - VL_SIGW(__Vtemp2,95,0,3); - VL_SIGW(__Vtemp3,95,0,3); - VL_SIGW(__Vtemp5,95,0,3); - VL_SIGW(__Vtemp6,95,0,3); - VL_SIGW(__Vtemp7,95,0,3); - VL_SIGW(__Vtemp8,95,0,3); - VL_SIGW(__Vtemp9,95,0,3); - VL_SIGW(__Vtemp15,95,0,3); - VL_SIGW(__Vtemp16,95,0,3); - // Body - // ALWAYS at Top.v:1335 - if (VL_UNLIKELY((((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & (3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))) - & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) - | (IData)(vlTOPp->reset)))))) { - VL_FWRITEF(0x80000002U,"Assertion failed\n at memory.scala:70 assert(io.dmem.address < size.U)\n"); - } - if (VL_UNLIKELY((((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & (3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))) - & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) - | (IData)(vlTOPp->reset)))))) { - VL_WRITEF("[%0t] %%Error: Top.v:1357: Assertion failed in %NTop.mem\n", - 64,VL_TIME_Q(),vlSymsp->name()); - VL_STOP_MT("Top.v",1357,""); - } - if (VL_UNLIKELY(((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) - & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) - | (IData)(vlTOPp->reset)))))) { - VL_FWRITEF(0x80000002U,"Assertion failed\n at memory.scala:99 assert(io.dmem.address < size.U)\n"); - } - if (VL_UNLIKELY(((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) - & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) - | (IData)(vlTOPp->reset)))))) { - VL_WRITEF("[%0t] %%Error: Top.v:1379: Assertion failed in %NTop.mem\n", - 64,VL_TIME_Q(),vlSymsp->name()); - VL_STOP_MT("Top.v",1379,""); - } - __Vdlyvset__Top__DOT__mem__DOT__memory__v0 = 0U; - __Vdlyvset__Top__DOT__mem__DOT__memory__v1 = 0U; - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((1U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((2U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((3U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((4U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((5U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((6U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((7U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((8U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((9U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0xaU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0xbU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0xcU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0xdU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0xeU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0xfU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x10U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x11U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x12U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x13U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x14U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x15U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x16U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x17U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x18U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x19U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:1136 - vlTOPp->Top__DOT__cpu__DOT__pc = ((IData)(vlTOPp->reset) - ? 0U : (((((0U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? - (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - == vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) - : - ((1U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? - (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - != vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) - : - ((4U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? - VL_LTS_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) - : - ((5U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? - VL_GTES_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) - : - ((6U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? - (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - < vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) - : - (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - >= vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2)))))) - & ((0x33U - != - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U - != - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((3U - != - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x23U - != - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & (0x63U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction))))))) - | (2U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_jump))) - ? vlTOPp->Top__DOT__cpu__DOT__branchAdd_io_result - : ( - (3U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_jump)) - ? - (0xfffffffeU - & (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) - : - ((IData)(4U) - + vlTOPp->Top__DOT__cpu__DOT__pcPlusFour_io_inputx)))); - // ALWAYS at Top.v:1335 - if (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) - & (2U != (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))))) { - VL_EXTEND_WI(71,32, __Vtemp1, vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data); - __Vtemp2[0U] = 0xffU; - __Vtemp2[1U] = 0U; - __Vtemp2[2U] = 0U; - VL_SHIFTL_WWI(71,71,6, __Vtemp3, __Vtemp2, - (0x18U & ((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10) - << 3U))); - __Vtemp5[0U] = (__Vtemp1[0U] & (~ __Vtemp3[0U])); - __Vtemp5[1U] = (__Vtemp1[1U] & (~ __Vtemp3[1U])); - __Vtemp5[2U] = (__Vtemp1[2U] & (~ __Vtemp3[2U])); - VL_EXTEND_WW(79,71, __Vtemp6, __Vtemp5); - VL_EXTEND_WI(79,32, __Vtemp7, vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data); - __Vtemp8[0U] = 0xffffU; - __Vtemp8[1U] = 0U; - __Vtemp8[2U] = 0U; - VL_SHIFTL_WWI(79,79,6, __Vtemp9, __Vtemp8, - (0x18U & ((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10) - << 3U))); - VL_EXTEND_WI(95,32, __Vtemp15, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2); - VL_SHIFTL_WWI(95,95,6, __Vtemp16, __Vtemp15, - (0x18U & ((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10) - << 3U))); - __Vdlyvval__Top__DOT__mem__DOT__memory__v0 - = (((0U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? __Vtemp6[0U] - : (__Vtemp7[0U] & (~ __Vtemp9[0U]))) - | __Vtemp16[0U]); - __Vdlyvset__Top__DOT__mem__DOT__memory__v0 = 1U; - __Vdlyvdim0__Top__DOT__mem__DOT__memory__v0 - = (0x3fffU & (IData)((vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U))); - } - if (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) - & (2U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))))) { - __Vdlyvval__Top__DOT__mem__DOT__memory__v1 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2; - __Vdlyvset__Top__DOT__mem__DOT__memory__v1 = 1U; - __Vdlyvdim0__Top__DOT__mem__DOT__memory__v1 - = (0x3fffU & (IData)((vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U))); - } - // ALWAYSPOST at Top.v:1336 - if (__Vdlyvset__Top__DOT__mem__DOT__memory__v0) { - vlTOPp->Top__DOT__mem__DOT__memory[__Vdlyvdim0__Top__DOT__mem__DOT__memory__v0] - = __Vdlyvval__Top__DOT__mem__DOT__memory__v0; - } - if (__Vdlyvset__Top__DOT__mem__DOT__memory__v1) { - vlTOPp->Top__DOT__mem__DOT__memory[__Vdlyvdim0__Top__DOT__mem__DOT__memory__v1] - = __Vdlyvval__Top__DOT__mem__DOT__memory__v1; - } - vlTOPp->Top__DOT__cpu__DOT__pcPlusFour_io_inputx - = vlTOPp->Top__DOT__cpu__DOT__pc; - vlTOPp->Top__DOT__mem_io_imem_instruction = ((0x10000U - <= vlTOPp->Top__DOT__cpu__DOT__pc) - ? 0U - : - vlTOPp->Top__DOT__mem__DOT__memory - [(0x3fffU - & (vlTOPp->Top__DOT__cpu__DOT__pc - >> 2U))]); - vlTOPp->Top__DOT__cpu__DOT__registers_io_wen = - (((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x23U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | (0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))) - & (0U != (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))); - vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite - = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((3U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & (0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_jump = ( - (0x33U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x13U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((3U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x23U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x63U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x37U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x17U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x6fU - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : - ((0x67U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 3U - : 0U))))))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_toreg = - ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 1U : ((0x23U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x63U - == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : - ((0x37U - == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : ((0x17U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x6fU - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : - ((0x67U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : 3U))))))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1 - = ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x23U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x63U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : ( - (0x37U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 1U - : - ((0x17U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : - (0x6fU - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction))))))))); - vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 - : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 - : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 - : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 - : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 - : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 - : ((0x19U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 - : ((0x18U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 - : ((0x17U == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 - : ((0x16U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 - : ( - (0x15U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 - : - ((0x14U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 - : - ((0x13U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 - : - ((0x12U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 - : - ((0x11U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 - : - ((0x10U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 - : - ((0xfU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 - : - ((0xeU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 - : - ((0xdU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 - : - ((0xcU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 - : - ((0xbU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 - : - ((0xaU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 - : - ((9U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 - : - ((8U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 - : - ((7U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 - : - ((6U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 - : - ((5U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 - : - ((4U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 - : - ((3U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 - : - ((2U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 - : - ((1U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 - : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); - vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2 - = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 - : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 - : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 - : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 - : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 - : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 - : ((0x19U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 - : ((0x18U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 - : ((0x17U == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 - : ((0x16U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 - : ( - (0x15U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 - : - ((0x14U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 - : - ((0x13U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 - : - ((0x12U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 - : - ((0x11U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 - : - ((0x10U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 - : - ((0xfU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 - : - ((0xeU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 - : - ((0xdU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 - : - ((0xcU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 - : - ((0xbU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 - : - ((0xaU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 - : - ((9U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 - : - ((8U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 - : - ((7U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 - : - ((6U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 - : - ((5U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 - : - ((4U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 - : - ((3U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 - : - ((2U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 - : - ((1U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 - : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_immediate - = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x6fU != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & (0x67U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))); - vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - = ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0xfffffU : 0U) << 0xcU) | (0xfffU & - (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))); - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx = ((0U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) - ? vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - : - ((1U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) - ? 0U - : vlTOPp->Top__DOT__cpu__DOT__pc)); - vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation - = (((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | (0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))) - ? 2U : ((0U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) - | (0U - == - (0x7fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x19U)))) - ? 2U - : 3U) - : ((1U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? 6U - : ((2U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 4U : ((3U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 5U : ((4U == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 9U - : ((5U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? - ((0U - == - (0x7fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x19U))) - ? 7U - : 8U) - : - ((6U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 1U - : - ((7U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 0U - : 0xfU))))))))); - vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm = - ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - : ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - : ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0x7ffU : 0U) << 0x15U) | - ((0x100000U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xbU)) | ((0xff000U - & vlTOPp->Top__DOT__mem_io_imem_instruction) - | ((0x800U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 9U)) - | (0x7feU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U)))))) - : ((0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - : ((0x63U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0x7ffffU : 0U) << 0xdU) - | ((0x1000U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x13U)) - | ((0x800U & (vlTOPp->Top__DOT__mem_io_imem_instruction - << 4U)) - | ((0x7e0U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U)) - | (0x1eU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))))) - : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - : ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? ((((0x80000000U - & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0xfffffU : 0U) - << 0xcU) | ((0xfe0U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U)) - | (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) - : ((0x13U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - : ((0x73U == - (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU)) - : 0U))))))))); - vlTOPp->Top__DOT__cpu__DOT__branchAdd_io_result - = (vlTOPp->Top__DOT__cpu__DOT__pc + vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm); - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy = ((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) - ? vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm - : vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2); - vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3 = (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - | vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy); - vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 = - (VL_ULL(0x7fffffffffffffff) & ((0U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3)) - : ((2U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : ( - (3U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : - ((4U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - VL_LTS_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : - ((5U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - < vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : - ((6U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - ((QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx)) - << - (0x1fU - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) - : (QData)((IData)( - ((7U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - >> - (0x1fU - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) - : - ((8U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - VL_SHIFTRS_III(32,32,5, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, - (0x1fU - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) - : - ((9U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - ^ vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy) - : - ((0xaU - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - (~ vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3) - : 0U)))))))))))))); - vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data - = vlTOPp->Top__DOT__mem__DOT__memory[(0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))]; - vlTOPp->Top__DOT__mem__DOT___GEN_14 = ((2U != (3U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? ((0U - == - (3U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? (0xffU - & vlTOPp->Top__DOT__mem__DOT__memory - [ - (0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))]) - : (0xffffU - & vlTOPp->Top__DOT__mem__DOT__memory - [ - (0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))])) - : vlTOPp->Top__DOT__mem__DOT__memory - [(0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))]); - vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata - = ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) - ? ((0x4000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? vlTOPp->Top__DOT__mem__DOT___GEN_14 - : ((0U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? ((((0x80U - & vlTOPp->Top__DOT__mem__DOT___GEN_14) - ? 0xffffffU - : 0U) - << 8U) - | (0xffU - & vlTOPp->Top__DOT__mem__DOT___GEN_14)) - : ((1U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? ( - (((0x8000U - & vlTOPp->Top__DOT__mem__DOT___GEN_14) - ? 0xffffU - : 0U) - << 0x10U) - | (0xffffU - & vlTOPp->Top__DOT__mem__DOT___GEN_14)) - : vlTOPp->Top__DOT__mem__DOT___GEN_14))) - : ((2U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) - ? ((IData)(4U) + vlTOPp->Top__DOT__cpu__DOT__pc) - : (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10))); -} - -void VTop::_settle__TOP__3(VTop__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_settle__TOP__3\n"); ); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - vlTOPp->Top__DOT__cpu__DOT__pcPlusFour_io_inputx - = vlTOPp->Top__DOT__cpu__DOT__pc; - vlTOPp->Top__DOT__mem_io_imem_instruction = ((0x10000U - <= vlTOPp->Top__DOT__cpu__DOT__pc) - ? 0U - : - vlTOPp->Top__DOT__mem__DOT__memory - [(0x3fffU - & (vlTOPp->Top__DOT__cpu__DOT__pc - >> 2U))]); - vlTOPp->Top__DOT__cpu__DOT__registers_io_wen = - (((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x23U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | (0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))) - & (0U != (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))); - vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite - = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((3U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & (0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_jump = ( - (0x33U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x13U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((3U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x23U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x63U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x37U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x17U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x6fU - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : - ((0x67U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 3U - : 0U))))))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_toreg = - ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 1U : ((0x23U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x63U - == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : - ((0x37U - == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : ((0x17U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x6fU - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : - ((0x67U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : 3U))))))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1 - = ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x23U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x63U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : ( - (0x37U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 1U - : - ((0x17U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : - (0x6fU - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction))))))))); - vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 - : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 - : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 - : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 - : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 - : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 - : ((0x19U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 - : ((0x18U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 - : ((0x17U == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 - : ((0x16U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 - : ( - (0x15U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 - : - ((0x14U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 - : - ((0x13U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 - : - ((0x12U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 - : - ((0x11U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 - : - ((0x10U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 - : - ((0xfU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 - : - ((0xeU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 - : - ((0xdU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 - : - ((0xcU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 - : - ((0xbU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 - : - ((0xaU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 - : - ((9U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 - : - ((8U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 - : - ((7U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 - : - ((6U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 - : - ((5U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 - : - ((4U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 - : - ((3U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 - : - ((2U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 - : - ((1U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 - : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); - vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2 - = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 - : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 - : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 - : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 - : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 - : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 - : ((0x19U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 - : ((0x18U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 - : ((0x17U == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 - : ((0x16U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 - : ( - (0x15U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 - : - ((0x14U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 - : - ((0x13U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 - : - ((0x12U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 - : - ((0x11U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 - : - ((0x10U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 - : - ((0xfU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 - : - ((0xeU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 - : - ((0xdU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 - : - ((0xcU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 - : - ((0xbU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 - : - ((0xaU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 - : - ((9U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 - : - ((8U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 - : - ((7U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 - : - ((6U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 - : - ((5U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 - : - ((4U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 - : - ((3U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 - : - ((2U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 - : - ((1U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 - : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_immediate - = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x6fU != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & (0x67U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))); - vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - = ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0xfffffU : 0U) << 0xcU) | (0xfffU & - (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))); - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx = ((0U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) - ? vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - : - ((1U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) - ? 0U - : vlTOPp->Top__DOT__cpu__DOT__pc)); - vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation - = (((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | (0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))) - ? 2U : ((0U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) - | (0U - == - (0x7fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x19U)))) - ? 2U - : 3U) - : ((1U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? 6U - : ((2U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 4U : ((3U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 5U : ((4U == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 9U - : ((5U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? - ((0U - == - (0x7fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x19U))) - ? 7U - : 8U) - : - ((6U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 1U - : - ((7U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 0U - : 0xfU))))))))); - vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm = - ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - : ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - : ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0x7ffU : 0U) << 0x15U) | - ((0x100000U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xbU)) | ((0xff000U - & vlTOPp->Top__DOT__mem_io_imem_instruction) - | ((0x800U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 9U)) - | (0x7feU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U)))))) - : ((0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - : ((0x63U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0x7ffffU : 0U) << 0xdU) - | ((0x1000U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x13U)) - | ((0x800U & (vlTOPp->Top__DOT__mem_io_imem_instruction - << 4U)) - | ((0x7e0U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U)) - | (0x1eU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))))) - : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - : ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? ((((0x80000000U - & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0xfffffU : 0U) - << 0xcU) | ((0xfe0U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U)) - | (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) - : ((0x13U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - : ((0x73U == - (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU)) - : 0U))))))))); - vlTOPp->Top__DOT__cpu__DOT__branchAdd_io_result - = (vlTOPp->Top__DOT__cpu__DOT__pc + vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm); - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy = ((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) - ? vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm - : vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2); - vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3 = (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - | vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy); - vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 = - (VL_ULL(0x7fffffffffffffff) & ((0U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3)) - : ((2U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : ( - (3U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : - ((4U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - VL_LTS_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : - ((5U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - < vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : - ((6U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - ((QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx)) - << - (0x1fU - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) - : (QData)((IData)( - ((7U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - >> - (0x1fU - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) - : - ((8U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - VL_SHIFTRS_III(32,32,5, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, - (0x1fU - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) - : - ((9U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - ^ vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy) - : - ((0xaU - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - (~ vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3) - : 0U)))))))))))))); - vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data - = vlTOPp->Top__DOT__mem__DOT__memory[(0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))]; - vlTOPp->Top__DOT__mem__DOT___GEN_14 = ((2U != (3U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? ((0U - == - (3U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? (0xffU - & vlTOPp->Top__DOT__mem__DOT__memory - [ - (0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))]) - : (0xffffU - & vlTOPp->Top__DOT__mem__DOT__memory - [ - (0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))])) - : vlTOPp->Top__DOT__mem__DOT__memory - [(0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))]); - vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata - = ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) - ? ((0x4000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? vlTOPp->Top__DOT__mem__DOT___GEN_14 - : ((0U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? ((((0x80U - & vlTOPp->Top__DOT__mem__DOT___GEN_14) - ? 0xffffffU - : 0U) - << 8U) - | (0xffU - & vlTOPp->Top__DOT__mem__DOT___GEN_14)) - : ((1U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? ( - (((0x8000U - & vlTOPp->Top__DOT__mem__DOT___GEN_14) - ? 0xffffU - : 0U) - << 0x10U) - | (0xffffU - & vlTOPp->Top__DOT__mem__DOT___GEN_14)) - : vlTOPp->Top__DOT__mem__DOT___GEN_14))) - : ((2U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) - ? ((IData)(4U) + vlTOPp->Top__DOT__cpu__DOT__pc) - : (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10))); -} - -void VTop::_eval(VTop__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval\n"); ); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - if (((IData)(vlTOPp->clock) & (~ (IData)(vlTOPp->__Vclklast__TOP__clock)))) { - vlTOPp->_sequent__TOP__2(vlSymsp); - } - // Final - vlTOPp->__Vclklast__TOP__clock = vlTOPp->clock; -} - -void VTop::_eval_initial(VTop__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval_initial\n"); ); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - vlTOPp->_initial__TOP__1(vlSymsp); -} - -void VTop::final() { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::final\n"); ); - // Variables - VTop__Syms* __restrict vlSymsp = this->__VlSymsp; - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; -} - -void VTop::_eval_settle(VTop__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval_settle\n"); ); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - vlTOPp->_settle__TOP__3(vlSymsp); -} - -VL_INLINE_OPT QData VTop::_change_request(VTop__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_change_request\n"); ); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - // Change detection - QData __req = false; // Logically a bool - return __req; -} - -#ifdef VL_DEBUG -void VTop::_eval_debug_assertions() { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval_debug_assertions\n"); ); - // Body - if (VL_UNLIKELY((clock & 0xfeU))) { - Verilated::overWidthError("clock");} - if (VL_UNLIKELY((reset & 0xfeU))) { - Verilated::overWidthError("reset");} -} -#endif // VL_DEBUG - -void VTop::_ctor_var_reset() { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_ctor_var_reset\n"); ); - // Body - clock = VL_RAND_RESET_I(1); - reset = VL_RAND_RESET_I(1); - io_success = VL_RAND_RESET_I(1); - Top__DOT__mem_io_imem_instruction = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__control_io_toreg = VL_RAND_RESET_I(2); - Top__DOT__cpu__DOT__control_io_memwrite = VL_RAND_RESET_I(1); - Top__DOT__cpu__DOT__control_io_immediate = VL_RAND_RESET_I(1); - Top__DOT__cpu__DOT__control_io_alusrc1 = VL_RAND_RESET_I(2); - Top__DOT__cpu__DOT__control_io_jump = VL_RAND_RESET_I(2); - Top__DOT__cpu__DOT__registers_io_writedata = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers_io_wen = VL_RAND_RESET_I(1); - Top__DOT__cpu__DOT__registers_io_readdata1 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers_io_readdata2 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__aluControl_io_operation = VL_RAND_RESET_I(4); - Top__DOT__cpu__DOT__alu_io_inputx = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__alu_io_inputy = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__immGen_io_sextImm = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__pcPlusFour_io_inputx = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__branchAdd_io_result = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__pc = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_0 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_1 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_2 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_3 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_4 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_5 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_6 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_7 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_8 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_9 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_10 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_11 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_12 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_13 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_14 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_15 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_16 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_17 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_18 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_19 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_20 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_21 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_22 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_23 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_24 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_25 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_26 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_27 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_28 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_29 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_30 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_31 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__alu__DOT___T_3 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__alu__DOT___GEN_10 = VL_RAND_RESET_Q(63); - Top__DOT__cpu__DOT__immGen__DOT___T_26 = VL_RAND_RESET_I(32); - { int __Vi0=0; for (; __Vi0<16384; ++__Vi0) { - Top__DOT__mem__DOT__memory[__Vi0] = VL_RAND_RESET_I(32); - }} - Top__DOT__mem__DOT__memory___05FT_49_data = VL_RAND_RESET_I(32); - Top__DOT__mem__DOT___GEN_14 = VL_RAND_RESET_I(32); - __Vclklast__TOP__clock = VL_RAND_RESET_I(1); -} diff --git a/src/verilog/obj_dir/VTop.h b/src/verilog/obj_dir/VTop.h deleted file mode 100644 index 116188ff..00000000 --- a/src/verilog/obj_dir/VTop.h +++ /dev/null @@ -1,136 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Primary design header -// -// This header should be included by all source files instantiating the design. -// The class here is then constructed to instantiate the design. -// See the Verilator manual for examples. - -#ifndef _VTop_H_ -#define _VTop_H_ - -#include "verilated_heavy.h" - -class VTop__Syms; - -//---------- - -VL_MODULE(VTop) { - public: - - // PORTS - // The application code writes and reads these signals to - // propagate new values into/out from the Verilated model. - VL_IN8(clock,0,0); - VL_IN8(reset,0,0); - VL_OUT8(io_success,0,0); - - // LOCAL SIGNALS - // Internals; generally not touched by application code - VL_SIG8(Top__DOT__cpu__DOT__control_io_toreg,1,0); - VL_SIG8(Top__DOT__cpu__DOT__control_io_memwrite,0,0); - VL_SIG8(Top__DOT__cpu__DOT__control_io_immediate,0,0); - VL_SIG8(Top__DOT__cpu__DOT__control_io_alusrc1,1,0); - VL_SIG8(Top__DOT__cpu__DOT__control_io_jump,1,0); - VL_SIG8(Top__DOT__cpu__DOT__registers_io_wen,0,0); - VL_SIG8(Top__DOT__cpu__DOT__aluControl_io_operation,3,0); - VL_SIG(Top__DOT__mem_io_imem_instruction,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers_io_writedata,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers_io_readdata1,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers_io_readdata2,31,0); - VL_SIG(Top__DOT__cpu__DOT__alu_io_inputx,31,0); - VL_SIG(Top__DOT__cpu__DOT__alu_io_inputy,31,0); - VL_SIG(Top__DOT__cpu__DOT__immGen_io_sextImm,31,0); - VL_SIG(Top__DOT__cpu__DOT__pcPlusFour_io_inputx,31,0); - VL_SIG(Top__DOT__cpu__DOT__branchAdd_io_result,31,0); - VL_SIG(Top__DOT__cpu__DOT__pc,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_0,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_1,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_2,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_3,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_4,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_5,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_6,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_7,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_8,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_9,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_10,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_11,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_12,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_13,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_14,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_15,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_16,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_17,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_18,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_19,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_20,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_21,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_22,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_23,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_24,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_25,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_26,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_27,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_28,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_29,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_30,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_31,31,0); - VL_SIG(Top__DOT__cpu__DOT__alu__DOT___T_3,31,0); - VL_SIG(Top__DOT__cpu__DOT__immGen__DOT___T_26,31,0); - VL_SIG(Top__DOT__mem__DOT__memory___05FT_49_data,31,0); - VL_SIG(Top__DOT__mem__DOT___GEN_14,31,0); - VL_SIG64(Top__DOT__cpu__DOT__alu__DOT___GEN_10,62,0); - VL_SIG(Top__DOT__mem__DOT__memory[16384],31,0); - - // LOCAL VARIABLES - // Internals; generally not touched by application code - VL_SIG8(__Vclklast__TOP__clock,0,0); - - // INTERNAL VARIABLES - // Internals; generally not touched by application code - VTop__Syms* __VlSymsp; // Symbol table - - // PARAMETERS - // Parameters marked /*verilator public*/ for use by application code - - // CONSTRUCTORS - private: - VTop& operator= (const VTop&); ///< Copying not allowed - VTop(const VTop&); ///< Copying not allowed - public: - /// Construct the model; called by application code - /// The special name may be used to make a wrapper with a - /// single model invisible WRT DPI scope names. - VTop(const char* name="TOP"); - /// Destroy the model; called (often implicitly) by application code - ~VTop(); - - // API METHODS - /// Evaluate the model. Application must call when inputs change. - void eval(); - /// Simulation complete, run final blocks. Application must call on completion. - void final(); - - // INTERNAL METHODS - private: - static void _eval_initial_loop(VTop__Syms* __restrict vlSymsp); - public: - void __Vconfigure(VTop__Syms* symsp, bool first); - private: - static QData _change_request(VTop__Syms* __restrict vlSymsp); - void _ctor_var_reset(); - public: - static void _eval(VTop__Syms* __restrict vlSymsp); - private: -#ifdef VL_DEBUG - void _eval_debug_assertions(); -#endif // VL_DEBUG - public: - static void _eval_initial(VTop__Syms* __restrict vlSymsp); - static void _eval_settle(VTop__Syms* __restrict vlSymsp); - static void _initial__TOP__1(VTop__Syms* __restrict vlSymsp); - static void _sequent__TOP__2(VTop__Syms* __restrict vlSymsp); - static void _settle__TOP__3(VTop__Syms* __restrict vlSymsp); -} VL_ATTR_ALIGNED(128); - -#endif // guard diff --git a/src/verilog/obj_dir/VTop.mk b/src/verilog/obj_dir/VTop.mk deleted file mode 100644 index d3f88421..00000000 --- a/src/verilog/obj_dir/VTop.mk +++ /dev/null @@ -1,66 +0,0 @@ -# Verilated -*- Makefile -*- -# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable -# -# Execute this makefile from the object directory: -# make -f VTop.mk - -default: VTop - -### Constants... -# Perl executable (from $PERL) -PERL = perl -# Path to Verilator kit (from $VERILATOR_ROOT) -VERILATOR_ROOT = /usr/share/verilator -# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) -SYSTEMC_INCLUDE ?= -# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) -SYSTEMC_LIBDIR ?= - -### Switches... -# SystemC output mode? 0/1 (from --sc) -VM_SC = 0 -# Legacy or SystemC output mode? 0/1 (from --sc) -VM_SP_OR_SC = $(VM_SC) -# Deprecated -VM_PCLI = 1 -# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) -VM_SC_TARGET_ARCH = linux - -### Vars... -# Design prefix (from --prefix) -VM_PREFIX = VTop -# Module prefix (from --prefix) -VM_MODPREFIX = VTop -# User CFLAGS (from -CFLAGS on Verilator command line) -VM_USER_CFLAGS = \ - -# User LDLIBS (from -LDFLAGS on Verilator command line) -VM_USER_LDLIBS = \ - -# User .cpp files (from .cpp's on Verilator command line) -VM_USER_CLASSES = \ - testbench \ - -# User .cpp directories (from .cpp's on Verilator command line) -VM_USER_DIR = \ - . \ - - -### Default rules... -# Include list of all generated classes -include VTop_classes.mk -# Include global rules -include $(VERILATOR_ROOT)/include/verilated.mk - -### Executable rules... (from --exe) -VPATH += $(VM_USER_DIR) - -testbench.o: testbench.cpp - $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< - -### Link rules... (from --exe) -VTop: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a - $(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) 2>&1 | c++filt - - -# Verilated -*- Makefile -*- diff --git a/src/verilog/obj_dir/VTop__ALLcls.cpp b/src/verilog/obj_dir/VTop__ALLcls.cpp deleted file mode 100644 index 22511a67..00000000 --- a/src/verilog/obj_dir/VTop__ALLcls.cpp +++ /dev/null @@ -1,3 +0,0 @@ -// DESCRIPTION: Generated by verilator_includer via makefile -#define VL_INCLUDE_OPT include -#include "VTop.cpp" diff --git a/src/verilog/obj_dir/VTop__ALLcls.d b/src/verilog/obj_dir/VTop__ALLcls.d deleted file mode 100644 index e0058e71..00000000 --- a/src/verilog/obj_dir/VTop__ALLcls.d +++ /dev/null @@ -1,5 +0,0 @@ -VTop__ALLcls.o: VTop__ALLcls.cpp VTop.cpp VTop.h \ - /usr/share/verilator/include/verilated_heavy.h \ - /usr/share/verilator/include/verilated.h \ - /usr/share/verilator/include/verilated_config.h \ - /usr/share/verilator/include/verilatedos.h VTop__Syms.h diff --git a/src/verilog/obj_dir/VTop__ALLsup.cpp b/src/verilog/obj_dir/VTop__ALLsup.cpp deleted file mode 100644 index 2aa533ee..00000000 --- a/src/verilog/obj_dir/VTop__ALLsup.cpp +++ /dev/null @@ -1,3 +0,0 @@ -// DESCRIPTION: Generated by verilator_includer via makefile -#define VL_INCLUDE_OPT include -#include "VTop__Syms.cpp" diff --git a/src/verilog/obj_dir/VTop__ALLsup.d b/src/verilog/obj_dir/VTop__ALLsup.d deleted file mode 100644 index cf982fbd..00000000 --- a/src/verilog/obj_dir/VTop__ALLsup.d +++ /dev/null @@ -1,5 +0,0 @@ -VTop__ALLsup.o: VTop__ALLsup.cpp VTop__Syms.cpp VTop__Syms.h \ - /usr/share/verilator/include/verilated_heavy.h \ - /usr/share/verilator/include/verilated.h \ - /usr/share/verilator/include/verilated_config.h \ - /usr/share/verilator/include/verilatedos.h VTop.h diff --git a/src/verilog/obj_dir/VTop__Syms.cpp b/src/verilog/obj_dir/VTop__Syms.cpp deleted file mode 100644 index 8d3e9168..00000000 --- a/src/verilog/obj_dir/VTop__Syms.cpp +++ /dev/null @@ -1,21 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Symbol table implementation internals - -#include "VTop__Syms.h" -#include "VTop.h" - -// FUNCTIONS -VTop__Syms::VTop__Syms(VTop* topp, const char* namep) - // Setup locals - : __Vm_namep(namep) - , __Vm_didInit(false) - // Setup submodule names -{ - // Pointer to top level - TOPp = topp; - // Setup each module's pointers to their submodules - // Setup each module's pointer back to symbol table (for public functions) - TOPp->__Vconfigure(this, true); - // Setup scope names - __Vscope_Top__mem.configure(this,name(),"Top.mem"); -} diff --git a/src/verilog/obj_dir/VTop__Syms.h b/src/verilog/obj_dir/VTop__Syms.h deleted file mode 100644 index 7ce62123..00000000 --- a/src/verilog/obj_dir/VTop__Syms.h +++ /dev/null @@ -1,37 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Symbol table internal header -// -// Internal details; most calling programs do not need this header - -#ifndef _VTop__Syms_H_ -#define _VTop__Syms_H_ - -#include "verilated_heavy.h" - -// INCLUDE MODULE CLASSES -#include "VTop.h" - -// SYMS CLASS -class VTop__Syms : public VerilatedSyms { - public: - - // LOCAL STATE - const char* __Vm_namep; - bool __Vm_didInit; - - // SUBCELL STATE - VTop* TOPp; - - // SCOPE NAMES - VerilatedScope __Vscope_Top__mem; - - // CREATORS - VTop__Syms(VTop* topp, const char* namep); - ~VTop__Syms() {} - - // METHODS - inline const char* name() { return __Vm_namep; } - -} VL_ATTR_ALIGNED(64); - -#endif // guard diff --git a/src/verilog/obj_dir/VTop__ver.d b/src/verilog/obj_dir/VTop__ver.d deleted file mode 100644 index e6618c98..00000000 --- a/src/verilog/obj_dir/VTop__ver.d +++ /dev/null @@ -1 +0,0 @@ -obj_dir/VTop.cpp obj_dir/VTop.h obj_dir/VTop.mk obj_dir/VTop__Syms.cpp obj_dir/VTop__Syms.h obj_dir/VTop__ver.d obj_dir/VTop_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin Top.v diff --git a/src/verilog/obj_dir/VTop__verFiles.dat b/src/verilog/obj_dir/VTop__verFiles.dat deleted file mode 100644 index 090b1097..00000000 --- a/src/verilog/obj_dir/VTop__verFiles.dat +++ /dev/null @@ -1,12 +0,0 @@ -# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. -C "--cc Top.v --exe testbench.cpp" -S 5279832 27263155 1541808233 963237689 1519110675 0 "/usr/bin/verilator_bin" -S 64006 10630799 1554939392 89651087 1554938775 745850810 "Top.v" -T 81093 11144428 1554939420 685597879 1554939420 685597879 "obj_dir/VTop.cpp" -T 5774 11144427 1554939420 685597879 1554939420 685597879 "obj_dir/VTop.h" -T 1753 11144430 1554939420 685597879 1554939420 685597879 "obj_dir/VTop.mk" -T 596 11144426 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__Syms.cpp" -T 758 11144425 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__Syms.h" -T 194 11144431 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__ver.d" -T 0 0 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__verFiles.dat" -T 1150 11144429 1554939420 685597879 1554939420 685597879 "obj_dir/VTop_classes.mk" diff --git a/src/verilog/obj_dir/VTop_classes.mk b/src/verilog/obj_dir/VTop_classes.mk deleted file mode 100644 index 4e59be86..00000000 --- a/src/verilog/obj_dir/VTop_classes.mk +++ /dev/null @@ -1,38 +0,0 @@ -# Verilated -*- Makefile -*- -# DESCRIPTION: Verilator output: Make include file with class lists -# -# This file lists generated Verilated files, for including in higher level makefiles. -# See VTop.mk for the caller. - -### Switches... -# Coverage output mode? 0/1 (from --coverage) -VM_COVERAGE = 0 -# Threaded output mode? 0/1/N threads (from --threads) -VM_THREADS = 0 -# Tracing output mode? 0/1 (from --trace) -VM_TRACE = 0 - -### Object file lists... -# Generated module classes, fast-path, compile with highest optimization -VM_CLASSES_FAST += \ - VTop \ - -# Generated module classes, non-fast-path, compile with low/medium optimization -VM_CLASSES_SLOW += \ - -# Generated support classes, fast-path, compile with highest optimization -VM_SUPPORT_FAST += \ - -# Generated support classes, non-fast-path, compile with low/medium optimization -VM_SUPPORT_SLOW += \ - VTop__Syms \ - -# Global classes, need linked once per executable, fast-path, compile with highest optimization -VM_GLOBAL_FAST += \ - verilated \ - -# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization -VM_GLOBAL_SLOW += \ - - -# Verilated -*- Makefile -*- diff --git a/src/verilog/obj_dir/testbench.d b/src/verilog/obj_dir/testbench.d deleted file mode 100644 index 984246f0..00000000 --- a/src/verilog/obj_dir/testbench.d +++ /dev/null @@ -1,6 +0,0 @@ -testbench.o: ../testbench.cpp VTop.h \ - /usr/share/verilator/include/verilated_heavy.h \ - /usr/share/verilator/include/verilated.h \ - /usr/share/verilator/include/verilated_config.h \ - /usr/share/verilator/include/verilatedos.h \ - /usr/share/verilator/include/verilated.h diff --git a/src/verilog/obj_dir/verilated.d b/src/verilog/obj_dir/verilated.d deleted file mode 100644 index 378ca2d9..00000000 --- a/src/verilog/obj_dir/verilated.d +++ /dev/null @@ -1,7 +0,0 @@ -verilated.o: /usr/share/verilator/include/verilated.cpp \ - /usr/share/verilator/include/verilated_imp.h \ - /usr/share/verilator/include/verilatedos.h \ - /usr/share/verilator/include/verilated.h \ - /usr/share/verilator/include/verilated_config.h \ - /usr/share/verilator/include/verilated_heavy.h \ - /usr/share/verilator/include/verilated_syms.h From f470ef291f697cf8208445bc06ab70093a39f335 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 1 May 2019 20:27:55 -0700 Subject: [PATCH 03/57] Delete Top.DualPortedMemory.memory.v --- Top.DualPortedMemory.memory.v | 20 -------------------- 1 file changed, 20 deletions(-) delete mode 100644 Top.DualPortedMemory.memory.v diff --git a/Top.DualPortedMemory.memory.v b/Top.DualPortedMemory.memory.v deleted file mode 100644 index a41466f6..00000000 --- a/Top.DualPortedMemory.memory.v +++ /dev/null @@ -1,20 +0,0 @@ -module BindsTo_0_DualPortedMemory( - input clock, - input reset, - input [31:0] io_imem_address, - output [31:0] io_imem_instruction, - input [31:0] io_dmem_address, - input [31:0] io_dmem_writedata, - input io_dmem_memread, - input io_dmem_memwrite, - input [1:0] io_dmem_maskmode, - input io_dmem_sext, - output [31:0] io_dmem_readdata -); - -initial begin - $readmemh("test", DualPortedMemory.memory); -end - endmodule - -bind DualPortedMemory BindsTo_0_DualPortedMemory BindsTo_0_DualPortedMemory_Inst(.*); \ No newline at end of file From efcbabfc7f6d93e1d7f4e83a19632fa335801342 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 1 May 2019 20:28:06 -0700 Subject: [PATCH 04/57] Delete firrtl_black_box_resource_files.f --- firrtl_black_box_resource_files.f | 1 - 1 file changed, 1 deletion(-) delete mode 100644 firrtl_black_box_resource_files.f diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f deleted file mode 100644 index 900ea4d4..00000000 --- a/firrtl_black_box_resource_files.f +++ /dev/null @@ -1 +0,0 @@ -/riscv/Top.DualPortedMemory.memory.v \ No newline at end of file From 466ebd9abb9263efae895265b67dd8355259c862 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 14 May 2019 18:41:04 -0700 Subject: [PATCH 05/57] resolved test file conflict again --- src/main/scala/components/csr.scala | 10 +- src/main/scala/testing/InstTests.scala | 208 ++++----- src/test/resources/risc-v/Makefile | 2 +- "src/test/resources/risc-v/\\" | 619 +++++++++++++++++++++++++ src/test/resources/risc-v/add0 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/add1 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/add2 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/addfwd | Bin 4592 -> 4784 bytes src/test/resources/risc-v/addi1 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/addi2 | Bin 4560 -> 4752 bytes src/test/resources/risc-v/and | Bin 4552 -> 4748 bytes src/test/resources/risc-v/andi | Bin 4556 -> 4748 bytes src/test/resources/risc-v/auipc0 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/auipc1 | Bin 4560 -> 4752 bytes src/test/resources/risc-v/auipc2 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/auipc3 | Bin 4560 -> 4752 bytes src/test/resources/risc-v/beq | Bin 4648 -> 4840 bytes src/test/resources/risc-v/bge | Bin 4648 -> 4840 bytes src/test/resources/risc-v/bgeu | Bin 4648 -> 4840 bytes src/test/resources/risc-v/blt | Bin 4648 -> 4840 bytes src/test/resources/risc-v/bltu | Bin 4648 -> 4840 bytes src/test/resources/risc-v/bne | Bin 4648 -> 4840 bytes src/test/resources/risc-v/csrrc | Bin 0 -> 4748 bytes src/test/resources/risc-v/csrrc.riscv | 12 + src/test/resources/risc-v/csrrci | Bin 0 -> 4748 bytes src/test/resources/risc-v/csrrci.riscv | 12 + src/test/resources/risc-v/csrrs | Bin 0 -> 4748 bytes src/test/resources/risc-v/csrrs.riscv | 12 + src/test/resources/risc-v/csrrsi | Bin 0 -> 4748 bytes src/test/resources/risc-v/csrrsi.riscv | 12 + src/test/resources/risc-v/csrrw | Bin 0 -> 4748 bytes src/test/resources/risc-v/csrrw.riscv | 12 + src/test/resources/risc-v/csrrwi | Bin 0 -> 4748 bytes src/test/resources/risc-v/csrrwi.riscv | 12 + src/test/resources/risc-v/divider | Bin 5740 -> 5932 bytes src/test/resources/risc-v/fibonacci | Bin 5672 -> 5864 bytes src/test/resources/risc-v/jal | Bin 4604 -> 4796 bytes src/test/resources/risc-v/jalr0 | Bin 4604 -> 4800 bytes src/test/resources/risc-v/jalr1 | Bin 4604 -> 4800 bytes src/test/resources/risc-v/lb | Bin 5620 -> 5812 bytes src/test/resources/risc-v/lb1 | Bin 5620 -> 5812 bytes src/test/resources/risc-v/lbu | Bin 5620 -> 5812 bytes src/test/resources/risc-v/lh | Bin 5620 -> 5812 bytes src/test/resources/risc-v/lh1 | Bin 5620 -> 5812 bytes src/test/resources/risc-v/lhu | Bin 5620 -> 5812 bytes src/test/resources/risc-v/lui0 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/lui1 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/lw1 | Bin 5620 -> 5812 bytes src/test/resources/risc-v/lwfwd | Bin 5620 -> 5816 bytes src/test/resources/risc-v/multiplier | Bin 5672 -> 5864 bytes src/test/resources/risc-v/naturalsum | Bin 5672 -> 5864 bytes src/test/resources/risc-v/oppsign | Bin 4560 -> 4756 bytes src/test/resources/risc-v/or | Bin 4552 -> 4744 bytes src/test/resources/risc-v/ori | Bin 4552 -> 4748 bytes src/test/resources/risc-v/power2 | Bin 4564 -> 4756 bytes src/test/resources/risc-v/rotR | Bin 4568 -> 4760 bytes src/test/resources/risc-v/sb | Bin 5620 -> 5812 bytes src/test/resources/risc-v/sh | Bin 5620 -> 5812 bytes src/test/resources/risc-v/sll | Bin 4552 -> 4748 bytes src/test/resources/risc-v/slli | Bin 4556 -> 4748 bytes src/test/resources/risc-v/slt | Bin 4552 -> 4748 bytes src/test/resources/risc-v/slt1 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/slti | Bin 4556 -> 4748 bytes src/test/resources/risc-v/sltiu | Bin 4556 -> 4748 bytes src/test/resources/risc-v/sltu | Bin 4556 -> 4748 bytes src/test/resources/risc-v/sltu1 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/sort | Bin 5808 -> 6004 bytes src/test/resources/risc-v/sra | Bin 4552 -> 4748 bytes src/test/resources/risc-v/srai | Bin 4556 -> 4748 bytes src/test/resources/risc-v/srl | Bin 4552 -> 4748 bytes src/test/resources/risc-v/srli | Bin 4556 -> 4748 bytes src/test/resources/risc-v/sub | Bin 4552 -> 4748 bytes src/test/resources/risc-v/sw | Bin 5812 -> 5812 bytes src/test/resources/risc-v/sw.riscv | 1 - src/test/resources/risc-v/swapxor | Bin 4564 -> 4760 bytes src/test/resources/risc-v/test | Bin 5644 -> 5836 bytes src/test/resources/risc-v/xor | Bin 4552 -> 4748 bytes src/test/resources/risc-v/xori | Bin 4556 -> 4748 bytes src/test/scala/grading/Lab1Tests.scala | 2 + src/test/scala/grading/Lab2Tests.scala | 76 ++- 80 files changed, 877 insertions(+), 113 deletions(-) create mode 100644 "src/test/resources/risc-v/\\" create mode 100755 src/test/resources/risc-v/csrrc create mode 100644 src/test/resources/risc-v/csrrc.riscv create mode 100755 src/test/resources/risc-v/csrrci create mode 100644 src/test/resources/risc-v/csrrci.riscv create mode 100755 src/test/resources/risc-v/csrrs create mode 100644 src/test/resources/risc-v/csrrs.riscv create mode 100755 src/test/resources/risc-v/csrrsi create mode 100644 src/test/resources/risc-v/csrrsi.riscv create mode 100755 src/test/resources/risc-v/csrrw create mode 100644 src/test/resources/risc-v/csrrw.riscv create mode 100755 src/test/resources/risc-v/csrrwi create mode 100644 src/test/resources/risc-v/csrrwi.riscv diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index a353d112..b4417d26 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -5,8 +5,6 @@ package dinocpu import chisel3._ import collection.mutable.LinkedHashMap import chisel3.util._ -import chisel3.util.BitPat -import chisel3.util.experimental.BoringUtils import Util._ import scala.math._ @@ -221,6 +219,8 @@ object MCSRCmd{ val MPRV = 3 } + +//reorder bundles class CSRRegFileIO extends Bundle{ //val hartid = Input(UInt(32.W)) val rw = new Bundle { @@ -229,7 +229,7 @@ class CSRRegFileIO extends Bundle{ } val csr_stall = Output(Bool())//not needed in single cycle - val eret = Output(Bool())// + val eret = Output(Bool())// change ret names val decode = new Bundle { val inst = Input(UInt(32.W)) // @@ -241,8 +241,8 @@ class CSRRegFileIO extends Bundle{ val status = Output(new MStatus())//not needed in this design but useful if more ISA extensions val evec = Output(UInt(32.W)) // - val exception = Input(Bool()) // - val retire = Input(Bool()) // + val exception = Input(Bool()) // rename to illgl inst + val retire = Input(Bool()) // rename to retire inst val pc = Input(UInt(32.W)) // val time = Output(UInt(32.W))// } diff --git a/src/main/scala/testing/InstTests.scala b/src/main/scala/testing/InstTests.scala index d63bbbf6..dec66e85 100644 --- a/src/main/scala/testing/InstTests.scala +++ b/src/main/scala/testing/InstTests.scala @@ -32,85 +32,85 @@ object InstTests { val rtype = List[CPUTestCase]( CPUTestCase("add1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), CPUTestCase("add2", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 20 -> 5678), Map(0 -> 0, 10 -> 6912), Map(), Map()), CPUTestCase("add0", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 3456), Map(0 -> 0, 5 -> 1234, 6 -> 3456), Map(), Map()), CPUTestCase("or", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 5678), Map(7 -> 5886), Map(), Map()), CPUTestCase("sub", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 5678), Map(7 -> BigInt("FFFFEEA4", 16)), Map(), Map()), CPUTestCase("and", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 5678), Map(7 -> 1026), Map(), Map()), CPUTestCase("xor", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> 1234, 5 -> 5678), Map(5 -> 5678, 7 -> 1234, 6 -> 4860), Map(), Map()), CPUTestCase("slt", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> 1234, 5 -> 5678), Map(5 -> 5678, 7 -> 1234, 6 -> 1), Map(), Map()), CPUTestCase("slt1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> -1, 5 -> 1), Map(5 -> 1, 6 -> 1), Map(), Map()), CPUTestCase("sltu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> -1, 5 -> 1), Map(5 -> 1, 6 -> 0), Map(), Map()), CPUTestCase("sltu1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> 20, 5 -> 100), Map(5 -> 100, 6 -> 1), Map(), Map()), CPUTestCase("sll", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> 32, 5 -> 2), Map(7 -> 32, 5 -> 2, 6 -> 128), Map(), Map()), CPUTestCase("srl", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> 32, 5 -> 2), Map(7 -> 32, 5 -> 2, 6 -> 8), Map(), Map()), CPUTestCase("sra", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> twoscomp(-2), 5 -> 31), Map(5 -> 31, 6 -> twoscomp(-1)), Map(), Map()) @@ -119,49 +119,49 @@ object InstTests { val rtypeMultiCycle = List[CPUTestCase]( CPUTestCase("addfwd", Map("single-cycle" -> 10, "pipelined" -> 14), - Map(), Map()), + Map(), Map(), Map(5 -> 1, 10 -> 0), Map(5 -> 1, 10 -> 10), Map(), Map()), CPUTestCase("swapxor", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map()), + Map(), Map(), Map(7 -> 5678, 5 -> 1234), Map(5 -> 5678,7->1234), Map(), Map()), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map()), + Map(), Map(), Map(5 -> 512, 6->1), Map(7->1), Map(), Map(), "-512"), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6->1), Map(7->0), Map(), Map(), "-1234"), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map()), + Map(), Map(), Map(5 -> twoscomp(-65536), 6->1), Map(7->0), // This algorithm doesn't work for negative numbers Map(), Map(), "--65536"), CPUTestCase("oppsign", Map("single-cycle" -> 2, "pipelined" -> 7), - Map(), Map()), + Map(), Map(), Map(5 -> 512, 6->twoscomp(-1024),7->0), Map(7->1), Map(), Map(), "-true"), CPUTestCase("oppsign", Map("single-cycle" -> 2, "pipelined" -> 7), - Map(), Map()), + Map(), Map(), Map(5 -> 512, 6->1024,7->0), Map(7->0), Map(), Map(), "-false"), CPUTestCase("rotR", Map("single-cycle" -> 4, "pipelined" -> 8), - Map(), Map()), + Map(), Map(), Map(5 -> twoscomp(-1), 6->1, 7->32), Map(7->twoscomp(-1)), Map(), Map()) @@ -170,109 +170,109 @@ object InstTests { val itype = List[CPUTestCase]( CPUTestCase("addi1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(0 -> 0, 10 -> 17), Map(), Map()), CPUTestCase("slli", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1), Map(0 -> 0, 5 -> 1, 6 -> 128), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1024), Map(0 -> 0, 5 -> 1024, 6 -> 8), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> twoscomp(-1024)), Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), Map(), Map(), "-negative"), CPUTestCase("srli", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 128), Map(0 -> 0, 5 -> 128, 6 -> 1), Map(), Map()), CPUTestCase("andi", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 200), Map(), Map()), CPUTestCase("ori", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 511), Map(), Map()), CPUTestCase("xori", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 311), Map(), Map()), CPUTestCase("slti", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1),6->1), Map(), Map()), CPUTestCase("sltiu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), - Map(), Map()) + Map(), Map()), CPUTestCase("csrrc", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), - Map(), Map()) + Map(), Map()), CPUTestCase("csrrci", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), - Map(), Map()) + Map(), Map()), CPUTestCase("csrrs", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), - Map(), Map()) + Map(), Map()), CPUTestCase("csrrsi", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), - Map(), Map()) + Map(), Map()), CPUTestCase("csrrw", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), - Map(), Map()) + Map(), Map()), CPUTestCase("csrrwi", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), - Map(), Map()) + Map(), Map()), CPUTestCase("ecall", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), - Map(), Map()) + Map(), Map()), CPUTestCase("ebreak", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), Map(), Map()) @@ -281,7 +281,7 @@ object InstTests { val itypeMultiCycle = List[CPUTestCase]( CPUTestCase("addi2", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map()), + Map(), Map(), Map(), Map(0 -> 0, 10 -> 17, 11 -> 93), Map(), Map()) @@ -290,109 +290,109 @@ object InstTests { val branch = List[CPUTestCase]( CPUTestCase("beq", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-False"), CPUTestCase("beq", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-True"), CPUTestCase("bne", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("bne", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-True"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-False-equal"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-True"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), Map(), Map(), "-False-signed"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), Map(), Map(), "-True-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-False"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(), Map(), "-True"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), Map(), Map(), "-False-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), Map(), Map(), "-True-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-True-equal"), CPUTestCase("bltu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("bltu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(), Map(), "-True"), CPUTestCase("bgeu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(), Map(), "-False"), CPUTestCase("bgeu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(), Map(), "-True") @@ -414,61 +414,61 @@ object InstTests { val memory = List[CPUTestCase]( CPUTestCase("lw1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(5 -> BigInt("ffffffff", 16)), Map(), Map()), CPUTestCase("lb", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(5 -> BigInt("04", 16)), Map(), Map()), CPUTestCase("lh", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(5 -> BigInt("0304", 16)), Map(), Map()), CPUTestCase("lbu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(5 -> BigInt("f4", 16)), Map(), Map()), CPUTestCase("lhu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(5 -> BigInt("f3f4", 16)), Map(), Map()), CPUTestCase("lb1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(5 -> BigInt("fffffff4", 16)), Map(), Map()), CPUTestCase("lh1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(5 -> BigInt("fffff3f4", 16)), Map(), Map()), CPUTestCase("sw", Map("single-cycle" -> 6, "pipelined" -> 10), - Map(), Map()), + Map(), Map(), Map(5 -> 1234), Map(6 -> 1234), Map(), Map(0x100 -> 1234)), CPUTestCase("sb", Map("single-cycle" -> 6, "pipelined" -> 10), - Map(), Map()), + Map(), Map(), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffffff01", 16))), CPUTestCase("sh", Map("single-cycle" -> 6, "pipelined" -> 10), - Map(), Map()), + Map(), Map(), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffff0001", 16))) @@ -477,7 +477,7 @@ object InstTests { val memoryMultiCycle = List[CPUTestCase]( CPUTestCase("lwfwd", Map("single-cycle" -> 2, "pipelined" -> 7), - Map(), Map()), + Map(), Map(), Map(5 -> BigInt("ffffffff", 16), 10 -> 5), Map(5 -> 1, 10 -> 6), Map(), Map()), @@ -496,37 +496,37 @@ object InstTests { val utype = List[CPUTestCase]( CPUTestCase("auipc0", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc2", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map()), - Map(10 -> 1234), - Map(10 -> (17 << 12)), - Map(), Map()), - CPUTestCase("lui0", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc1", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map()), + Map(), Map(), Map(10 -> 1234), - Map(10 -> 4), + Map(10 -> (17 << 12)), Map(), Map()), CPUTestCase("auipc3", Map("single-cycle" -> 2, "pipelined" -> 6), + Map(), Map(), + Map(10 -> 1234), + Map(10 -> 4), Map(), Map()), + CPUTestCase("lui0", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()), CPUTestCase("lui1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(10 -> 1234), Map(10 -> 4096), Map(), Map()) @@ -535,13 +535,13 @@ object InstTests { val utypeMultiCycle = List[CPUTestCase]( CPUTestCase("auipc1", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map()), + Map(), Map(), Map(10 -> 1234), Map(10 -> 4), Map(), Map()), CPUTestCase("auipc3", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map()), + Map(), Map(), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()) @@ -550,19 +550,19 @@ object InstTests { val jump = List[CPUTestCase]( CPUTestCase("jal", Map("single-cycle" -> 2, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr0", Map("single-cycle" -> 2, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 10 -> 28), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr1", Map("single-cycle" -> 2, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 10 -> 20), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -571,25 +571,25 @@ object InstTests { val smallApplications = List[CPUTestCase]( CPUTestCase("fibonacci", Map("single-cycle" -> 300, "pipelined" -> 1000), - Map(), Map()), + Map(), Map(), Map(6->11), Map(6->11,5->89), Map(), Map()), CPUTestCase("naturalsum", Map("single-cycle" -> 200, "pipelined" -> 500), - Map(), Map()), + Map(), Map(), Map(), Map(5->55), Map(), Map()), CPUTestCase("multiplier", Map("single-cycle" -> 1000, "pipelined" -> 1000), - Map(), Map()), + Map(), Map(), Map(5->23,6->20,8->0x1000), Map(5->23*20), Map(), Map()), CPUTestCase("divider", Map("single-cycle" -> 1000, "pipelined" -> 2000), - Map(), Map()), + Map(), Map(), Map(5->1260,6->30), Map(7->42), Map(), Map()) @@ -598,37 +598,37 @@ object InstTests { val fullApplications = List[CPUTestCase]( CPUTestCase("multiply.riscv", Map("single-cycle" -> 42342, "pipelined" -> 100000), - Map(), Map()), + Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("median.riscv", Map("single-cycle" -> 9433, "pipelined" -> 100000), - Map(), Map()), + Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("qsort.riscv", Map("single-cycle" -> 263290, "pipelined" -> 300000), - Map(), Map()), + Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("rsort.riscv", Map("single-cycle" -> 263290, "pipelined" -> 250000), - Map(), Map()), + Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("towers.riscv", Map("single-cycle" -> 12653, "pipelined" -> 100000), - Map(), Map()), + Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("vvadd.riscv", Map("single-cycle" -> 5484, "pipelined" -> 20000), - Map(), Map()), + Map(), Map(), Map(), Map(10->12345678), Map(), Map()) diff --git a/src/test/resources/risc-v/Makefile b/src/test/resources/risc-v/Makefile index 170b6280..157a74ee 100644 --- a/src/test/resources/risc-v/Makefile +++ b/src/test/resources/risc-v/Makefile @@ -1,5 +1,5 @@ -RISCV ?= /opt/riscv +RISCV ?= /home/nganjehl/riscv-gnu-toolchain RISCVBIN = $(RISCV)/bin SOURCES = $(wildcard *.riscv) diff --git "a/src/test/resources/risc-v/\\" "b/src/test/resources/risc-v/\\" new file mode 100644 index 00000000..71f4c040 --- /dev/null +++ "b/src/test/resources/risc-v/\\" @@ -0,0 +1,619 @@ +// Lists of different instruction test cases for use with different CPU models + +package dinocpu + +/** + * This object contains a set of lists of tests. Each list is a different set of + * instruction types and corresponds to a RISC-V program in resources/risc-v + * + * Each test case looks like: + * - binary to run in src/test/resources/risc-v + * - number of cycles to run for each CPU type + * - initial values for csr registers + * - final values to check for csr registers + * - initial values for registers + * - final values to check for registers + * - initial values for memory + * - final values to check for memory + * - extra name information + */ +object InstTests { + + val maxInt = BigInt("FFFFFFFF", 16) + + def twoscomp(v: BigInt) : BigInt = { + if (v < 0) { + return maxInt + v + 1 + } else { + return v + } + } + + val rtype = List[CPUTestCase]( + CPUTestCase("add1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1234), + Map(0 -> 0, 5 -> 1234, 6 -> 1234), + Map(), Map()), + CPUTestCase("add2", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1234, 20 -> 5678), + Map(0 -> 0, 10 -> 6912), + Map(), Map()), + CPUTestCase("add0", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1234, 6 -> 3456), + Map(0 -> 0, 5 -> 1234, 6 -> 3456), + Map(), Map()), + CPUTestCase("or", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1234, 6 -> 5678), + Map(7 -> 5886), + Map(), Map()), + CPUTestCase("sub", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1234, 6 -> 5678), + Map(7 -> BigInt("FFFFEEA4", 16)), + Map(), Map()), + CPUTestCase("and", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1234, 6 -> 5678), + Map(7 -> 1026), + Map(), Map()), + CPUTestCase("xor", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> 1234, 5 -> 5678), + Map(5 -> 5678, 7 -> 1234, 6 -> 4860), + Map(), Map()), + CPUTestCase("slt", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> 1234, 5 -> 5678), + Map(5 -> 5678, 7 -> 1234, 6 -> 1), + Map(), Map()), + CPUTestCase("slt1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> -1, 5 -> 1), + Map(5 -> 1, 6 -> 1), + Map(), Map()), + CPUTestCase("sltu", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> -1, 5 -> 1), + Map(5 -> 1, 6 -> 0), + Map(), Map()), + CPUTestCase("sltu1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> 20, 5 -> 100), + Map(5 -> 100, 6 -> 1), + Map(), Map()), + CPUTestCase("sll", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> 32, 5 -> 2), + Map(7 -> 32, 5 -> 2, 6 -> 128), + Map(), Map()), + CPUTestCase("srl", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> 32, 5 -> 2), + Map(7 -> 32, 5 -> 2, 6 -> 8), + Map(), Map()), + CPUTestCase("sra", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> twoscomp(-2), 5 -> 31), + Map(5 -> 31, 6 -> twoscomp(-1)), + Map(), Map()) + ) + + val rtypeMultiCycle = List[CPUTestCase]( + CPUTestCase("addfwd", + Map("single-cycle" -> 10, "five-cycle" -> 0, "pipelined" -> 14), + Map(), Map(), + Map(5 -> 1, 10 -> 0), + Map(5 -> 1, 10 -> 10), + Map(), Map()), + CPUTestCase("swapxor", + Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), + Map(), Map(), + Map(7 -> 5678, 5 -> 1234), + Map(5 -> 5678,7->1234), + Map(), Map()), + CPUTestCase("power2", + Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), + Map(), Map(), + Map(5 -> 512, 6->1), + Map(7->1), + Map(), Map(), "-512"), + CPUTestCase("power2", + Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), + Map(), Map(), + Map(5 -> 1234, 6->1), + Map(7->0), + Map(), Map(), "-1234"), + CPUTestCase("power2", + Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), + Map(), Map(), + Map(5 -> twoscomp(-65536), 6->1), + Map(7->0), // This algorithm doesn't work for negative numbers + Map(), Map(), "--65536"), + CPUTestCase("oppsign", + Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), + Map(), Map(), + Map(5 -> 512, 6->twoscomp(-1024),7->0), + Map(7->1), + Map(), Map(), "-true"), + CPUTestCase("oppsign", + Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), + Map(), Map(), + Map(5 -> 512, 6->1024,7->0), + Map(7->0), + Map(), Map(), "-false"), + CPUTestCase("rotR", + Map("single-cycle" -> 4, "five-cycle" -> 0, "pipelined" -> 8), + Map(), Map(), + Map(5 -> twoscomp(-1), 6->1, 7->32), + Map(7->twoscomp(-1)), + Map(), Map()) + ) + + val itype = List[CPUTestCase]( + CPUTestCase("addi1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(0 -> 0, 10 -> 17), + Map(), Map()), + CPUTestCase("slli", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1), + Map(0 -> 0, 5 -> 1, 6 -> 128), + Map(), Map()), + CPUTestCase("srai", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1024), + Map(0 -> 0, 5 -> 1024, 6 -> 8), + Map(), Map()), + CPUTestCase("srai", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> twoscomp(-1024)), + Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), + Map(), Map(), "-negative"), + CPUTestCase("srli", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 128), + Map(0 -> 0, 5 -> 128, 6 -> 1), + Map(), Map()), + CPUTestCase("andi", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 456), + Map(0 -> 0, 5 -> 456, 6 -> 200), + Map(), Map()), + CPUTestCase("ori", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 456), + Map(0 -> 0, 5 -> 456, 6 -> 511), + Map(), Map()), + CPUTestCase("xori", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 456), + Map(0 -> 0, 5 -> 456, 6 -> 311), + Map(), Map()), + CPUTestCase("slti", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> twoscomp(-1)), + Map(0 -> 0, 5 -> twoscomp(-1),6->1), + Map(), Map()), + CPUTestCase("sltiu", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> twoscomp(-1)), + Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), + Map(), Map()) + CPUTestCase("csrrc", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrci", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrs", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrsi", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrw", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrwi", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + CPUTestCase("ecall", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + CPUTestCase("ebreak", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + ) + + val itypeMultiCycle = List[CPUTestCase]( + CPUTestCase("addi2", + Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 6), + Map(), Map(), + Map(), + Map(0 -> 0, 10 -> 17, 11 -> 93), + Map(), Map()) + ) + + val branch = List[CPUTestCase]( + CPUTestCase("beq", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(), Map(), "-False"), + CPUTestCase("beq", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(), Map(), "-True"), + CPUTestCase("bne", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(), Map(), "-False"), + CPUTestCase("bne", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(), Map(), "-True"), + CPUTestCase("blt", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), + Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> 5678), + Map(), Map(), "-False"), + CPUTestCase("blt", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(), Map(), "-False-equal"), + CPUTestCase("blt", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(), Map(), "-True"), + CPUTestCase("blt", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), + Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), + Map(), Map(), "-False-signed"), + CPUTestCase("blt", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), + Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), + Map(), Map(), "-True-signed"), + CPUTestCase("bge", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(), Map(), "-False"), + CPUTestCase("bge", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), + Map(5 -> 1235, 6 -> 1, 7 -> 9012, 28 -> 5678), + Map(), Map(), "-True"), + CPUTestCase("bge", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), + Map(5 -> 0, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), + Map(), Map(), "-False-signed"), + CPUTestCase("bge", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), + Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), + Map(), Map(), "-True-signed"), + CPUTestCase("bge", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(), Map(), "-True-equal"), + CPUTestCase("bltu", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), + Map(5 -> 0, 6 -> 1, 7 -> maxInt, 28 -> 5678), + Map(), Map(), "-False"), + CPUTestCase("bltu", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), + Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> maxInt), + Map(), Map(), "-True"), + CPUTestCase("bgeu", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), + Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> maxInt), + Map(), Map(), "-False"), + CPUTestCase("bgeu", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), + Map(5 -> 1235, 6 -> 1, 7 -> maxInt, 28 -> 5678), + Map(), Map(), "-True") + ) + + val memory = List[CPUTestCase]( + CPUTestCase("lw1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(5 -> BigInt("ffffffff", 16)), + Map(), Map()), + CPUTestCase("lb", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(5 -> BigInt("04", 16)), + Map(), Map()), + CPUTestCase("lh", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(5 -> BigInt("0304", 16)), + Map(), Map()), + CPUTestCase("lbu", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(5 -> BigInt("f4", 16)), + Map(), Map()), + CPUTestCase("lhu", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(5 -> BigInt("f3f4", 16)), + Map(), Map()), + CPUTestCase("lb1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(5 -> BigInt("fffffff4", 16)), + Map(), Map()), + CPUTestCase("lh1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(5 -> BigInt("fffff3f4", 16)), + Map(), Map()), + CPUTestCase("sw", + Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), + Map(), Map(), + Map(5 -> 1234), + Map(6 -> 1234), + Map(), Map(0x100 -> 1234)), + CPUTestCase("sb", + Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), + Map(), Map(), + Map(5 -> 1), + Map(6 -> 1), + Map(), Map(0x100 -> BigInt("ffffff01", 16))), + CPUTestCase("sh", + Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), + Map(), Map(), + Map(5 -> 1), + Map(6 -> 1), + Map(), Map(0x100 -> BigInt("ffff0001", 16))) + ) + + val memoryMultiCycle = List[CPUTestCase]( + CPUTestCase("lwfwd", + Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), + Map(), Map(), + Map(5 -> BigInt("ffffffff", 16), 10 -> 5), + Map(5 -> 1, 10 -> 6), + Map(), Map()) + ) + + val utype = List[CPUTestCase]( + CPUTestCase("auipc0", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(10 -> 1234), + Map(10 -> 0), + Map(), Map()), + CPUTestCase("auipc1", + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), Map(), + Map(10 -> 1234), + Map(10 -> 4), + Map(), Map()), + CPUTestCase("auipc2", + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), Map(), + Map(10 -> 1234), + Map(10 -> (17 << 12)), + Map(), Map()), + CPUTestCase("auipc3", + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), Map(), + Map(10 -> 1234), + Map(10 -> ((17 << 12) + 4)), + Map(), Map()), + CPUTestCase("lui0", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(10 -> 1234), + Map(10 -> 0), + Map(), Map()), + CPUTestCase("lui1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(10 -> 1234), + Map(10 -> 4096), + Map(), Map()) + ) + + val jump = List[CPUTestCase]( + CPUTestCase("jal", + Map("single-cycle" -> 2, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234), + Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), + Map(), Map()), + CPUTestCase("jalr0", + Map("single-cycle" -> 2, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 10 -> 28), + Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), + Map(), Map()), + CPUTestCase("jalr1", + Map("single-cycle" -> 2, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 10 -> 20), + Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), + Map(), Map()) + ) + + val smallApplications = List[CPUTestCase]( + CPUTestCase("fibonacci", + Map("single-cycle" -> 300, "five-cycle" -> 0, "pipelined" -> 1000), + Map(), Map(), + Map(6->11), + Map(6->11,5->89), + Map(), Map()), + CPUTestCase("naturalsum", + Map("single-cycle" -> 200, "five-cycle" -> 0, "pipelined" -> 500), + Map(), Map(), + Map(), + Map(5->55), + Map(), Map()), + CPUTestCase("multiplier", + Map("single-cycle" -> 1000, "five-cycle" -> 0, "pipelined" -> 1000), + Map(), Map(), + Map(5->23,6->20,8->0x1000), + Map(5->23*20), + Map(), Map()), + CPUTestCase("divider", + Map("single-cycle" -> 1000, "five-cycle" -> 0, "pipelined" -> 2000), + Map(), Map(), + Map(5->1260,6->30), + Map(7->42), + Map(), Map()) + ) + + val fullApplications = List[CPUTestCase]( + CPUTestCase("multiply.riscv", + Map("single-cycle" -> 42342, "five-cycle" -> 0, "pipelined" -> 100000), + Map(), Map(), + Map(), + Map(10->12345678), + Map(), Map()), + CPUTestCase("median.riscv", + Map("single-cycle" -> 9433, "five-cycle" -> 0, "pipelined" -> 100000), + Map(), Map(), + Map(), + Map(10->12345678), + Map(), Map()), + CPUTestCase("qsort.riscv", + Map("single-cycle" -> 263290, "five-cycle" -> 0, "pipelined" -> 300000), + Map(), Map(), + Map(), + Map(10->12345678), + Map(), Map()), + CPUTestCase("rsort.riscv", + Map("single-cycle" -> 263290, "five-cycle" -> 0, "pipelined" -> 250000), + Map(), Map(), + Map(), + Map(10->12345678), + Map(), Map()), + CPUTestCase("towers.riscv", + Map("single-cycle" -> 12653, "five-cycle" -> 0, "pipelined" -> 100000), + Map(), Map(), + Map(), + Map(10->12345678), + Map(), Map()), + CPUTestCase("vvadd.riscv", + Map("single-cycle" -> 5484, "five-cycle" -> 0, "pipelined" -> 20000), + Map(), Map(), + Map(), + Map(10->12345678), + Map(), Map()) + ) + + // Mapping from group name to list of tests + val tests = Map( + "rtype" -> rtype, + "rtypeMultiCycle" -> rtypeMultiCycle, + "itype" -> itype, + "itypeMultiCycle" -> itypeMultiCycle, + "branch" -> branch, + "memory" -> memory, + "memoryMultiCycle" -> memoryMultiCycle, + "utype" -> utype, + "jump" -> jump, + "smallApplications" -> smallApplications + ) + + // All of the tests + val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ + memory ++ memoryMultiCycle ++ utype ++ jump ++ smallApplications + + // Mapping from full name of test to test + val nameMap = (allTests ++ fullApplications).map(x => x.name() -> x).toMap +} diff --git a/src/test/resources/risc-v/add0 b/src/test/resources/risc-v/add0 index d53471e009316c86f3934f992b57e694aeb4b896..7785b2a23a0449eeae29e2d41438fe25f49896e4 100755 GIT binary patch delta 362 zcmX@3+@m@{L3oZJ0~nYvC@?TGXfUubux>Pd$}j0C2^22MEKV+CVB`lfS&PbyjWUf2 z3??SZ3o`?iA_Hayrpe|4s`U&!5K#e!kN*`wOcofQk--td1d{?l{RSWwlDrKX-vf;w zj>eBe<1-|tOkOP@ZxZa{7~&Z3tb#gUaw zzAT_8s0a3~USdf}QD#zUNow(AM!{fFMW8jz3=9Pz+dx1@8lvid=2eOPoDgh^yH*Ej_ delta 172 zcmeBCJ)=B9L6}950SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRZ=!6b;U z0AxuBKmPd$}j0C2^22MEKV+CVB`lfS&PbyjWUf2 z3??SZ3o`?iA_Hayrpe|4s`U&!5K#e!kN*`wOcofQk--td1d{?l{RSWwlDrKX-vf;w zj>eBe<1-|tOkOP@ZxZa{7~&Z3tb#gUaw zzAT_8s0a3~USdf}QD#zUNow(AM!{fFMW8jz3=9Pz+dx1@8lvid=2eOPoDgh^yH*Ej_ delta 172 zcmeBCJ)=B9L6}950SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRZ=!6b;U z0AxuBKmPd$}j0C2^22MEKV+CVB`lfS&PbyjWUf2 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a/src/test/resources/risc-v/srai b/src/test/resources/risc-v/srai index 77de1aac2b9b74636846228de6e997cf9145597f..aba76a2c763924c81a6cea53e85f4e9237286191 100755 GIT binary patch delta 362 zcmX@3+@m@{L3oZJ0~nYvC@?TGXfUubux>Pd$}j0C2^22MEKV+CVB`lfS&PbyjWUf2 z3??SZ3o`?iA_Hayrpe|4s`U&!5K#e!kN*`wOcofQk--td1d{?l{RSWwlDrKX-vf;w zj>eBe<1-W&Otb#gUaw zzAT_8s0a3~USdf}QD#zUNow(AM!{fFMW8jz3=9Pz+dx1@8lvid=2eOPoDgipCH;n)Q delta 172 zcmeBCJ)=B9L6}950SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRZ=!6b;U z0AxuBKm9d-GyTYZ0WEh&Nd_HfkWYWp`Wjpg%i{Eg!2Y@?}SeLDwl1IwzK zx0-Qtdh*LJm$U7G9V|m>$*I7{*9x|1Utq(7bt=}Zs$+kT%8Jt-oY^w{*73Dts&f6) zf*us~bwS@0G-#Fh6A+2i286gzCZSBkbP|tEqz=&udY!9|==KK}Lm^OigFy6$y|fOs z7TQQfHKe)<7PX_!HwJ(iPaX2%PreFMP?BXEpY-;WT z?qC*tGgNSZ{W8GRjWuv?#|g}C??bti^V>N0hMJJmj)yW@u!;xY%c6q2qA*j7_h^Nb LpSwe&^~2mZBlAYM delta 172 zcmeBCJ)t~7L6||10SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRN+!6b+; z4`fLQAmp{t_(ov<*HMJ1CX1@$H-X-qyMs4-bYNPrile*#b)GZ3>( aHWZR(T>%s^pByNp%z7WlQk={vBn$v&92lGc diff --git a/src/test/resources/risc-v/srli b/src/test/resources/risc-v/srli index 87b05f25c45a9587e01c4c2f1d369e77a8c3d0e6..30a5d305399df85ffd90d6e5edf6d017af6215fb 100755 GIT binary patch delta 362 zcmX@3+@m@{L3oZJ0~nYvC@?TGXfUubux>Pd$}j0C2^22MEKV+CVB`lfS&PbyjWUf2 z3??SZ3o`?iA_Hayrpe|4s`U&!5K#e!kN*`wOcofQk--td1d{?l{RSWwlDrKX-vf;w zj>eBe<1-W&Otb#gUaw zzAT_8s0a3~USdf}QD#zUNow(AM!{fFMW8jz3=9Pz+dx1@8lvid=2eOPoDgipCH;n)Q delta 172 zcmeBCJ)=B9L6}950SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRZ=!6b;U z0AxuBKm}Dw^i&075JRaA2yr(YD>)RCaXd0na)?g99bSf_)#;x1gh1Wu_eH1I zp4Uoip^Z%F=JHrHkVb-tMgxFAKRp*HMJ1CX1@$H-X-qyMs4-bYNPrile*#b)GZ3>( aHWZR(T>%s^pByNp%z7WlQk={vBn$v&92lGc diff --git a/src/test/resources/risc-v/sw b/src/test/resources/risc-v/sw index 4a12e983891160077c00550ebb56842279d81919..ee8e7f8550d9ffee090debde842add9e6f2bbe4d 100755 GIT binary patch delta 30 mcmdm@yG3__z-AVKKg<&gSSE>-FzReB6-j1f)R}x!^fmyfb_%Wl delta 31 ncmdm@yG3__0P|#~g3bT=|1wV!DPc6&Tq=^x$Y?P6rs!<|zHke) diff --git a/src/test/resources/risc-v/sw.riscv b/src/test/resources/risc-v/sw.riscv index 896bceb5..e62cbd8f 100644 --- a/src/test/resources/risc-v/sw.riscv +++ b/src/test/resources/risc-v/sw.riscv @@ -2,7 +2,6 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: - addi t0, x0, 7 sw t0, 0x400(zero) nop nop diff --git a/src/test/resources/risc-v/swapxor b/src/test/resources/risc-v/swapxor index a0dbb0374ae18e40842afa874e32fd5b9a96c120..58591543c63c92d869e5c477380674f5dd16b1e0 100755 GIT binary patch literal 4760 zcmeHLy-ve05I*-$LR6xN30Q()V2V)N5ec+PmN|1Mzp|qk@;Nxo@t6tv0AbV=4TcLsVeFH0wGw4~EeH%Ef zWzbUnq`)r<{JOwJfrEMy=`@jk0(>Nt2F~wBNhn4$tb}ZE}WM~ Y9WV1XXFv1I9WVDu6ta6<^t%6k1DYaDF#rGn delta 202 zcmbQCdPRAHf-sLD0~nYvC@?TGXfUucuxvDb%RezihMAdxadNhRs*{2QM2P@c0fY@A zL40K(tsnpq1M&6I_-0`KWF|p<&ZOev_~MepqLRs}f_f8^G$vmV)R1Ka$}>T}Ks1`oIz1_lA31?Fh-&S-ppka{Hj zacJ_Xlb4EEm;}2xhB(GMxw?D$#m6(m$2$cF$GiHufZ0jK#qq@@iA5zqab#tapNW_V z>VbWvmsnC#l$lgol3F}5QERe`Xn-il-OLOO1t9A|fJKCXL27cNs4}ktko5s5!V1Lf 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zcmeBCJ)=B9L6}950SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRZ=!6b;U z0AxuBKm 1), + Map(), Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), @@ -48,6 +49,7 @@ class Lab1Grader extends JUnitSuite { success = CPUTesterDriver(CPUTestCase("add2", Map("single-cycle" -> 1), + Map(), Map(), Map(5 -> 1234, 20 -> 5678), Map(0 -> 0, 10 -> 6912), Map(), Map()), diff --git a/src/test/scala/grading/Lab2Tests.scala b/src/test/scala/grading/Lab2Tests.scala index eb3a701a..dae07001 100644 --- a/src/test/scala/grading/Lab2Tests.scala +++ b/src/test/scala/grading/Lab2Tests.scala @@ -53,61 +53,85 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase](CPUTestCase("add1", Map("single-cycle" -> 1), + Map(), + Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), CPUTestCase("addi1", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(0 -> 0, 10 -> 17), Map(), Map()), CPUTestCase("addi2", Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 6), + Map(), + Map(), Map(), Map(0 -> 0, 10 -> 17, 11 -> 93), Map(), Map()), CPUTestCase("slli", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> 1), Map(0 -> 0, 5 -> 1, 6 -> 128), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> 1024), Map(0 -> 0, 5 -> 1024, 6 -> 8), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> twoscomp(-1024)), Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), Map(), Map(), "-negative"), CPUTestCase("srli", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> 128), Map(0 -> 0, 5 -> 128, 6 -> 1), Map(), Map()), CPUTestCase("andi", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 200), Map(), Map()), CPUTestCase("ori", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 511), Map(), Map()), CPUTestCase("xori", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 311), Map(), Map()), CPUTestCase("slti", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1),6->1), Map(), Map()), CPUTestCase("sltiu", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), Map(), Map()) @@ -142,11 +166,15 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("lw1", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(5 -> BigInt("ffffffff", 16)), Map(), Map()), CPUTestCase("lwfwd", Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), + Map(), + Map(), Map(5 -> BigInt("ffffffff", 16), 10 -> 5), Map(5 -> 1, 10 -> 6), Map(), Map()) @@ -179,31 +207,43 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("auipc0", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc1", Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(10 -> 1234), Map(10 -> 4), Map(), Map()), CPUTestCase("auipc2", Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(10 -> 1234), Map(10 -> (17 << 12)), Map(), Map()), CPUTestCase("auipc3", Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()), CPUTestCase("lui0", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("lui1", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(10 -> 1234), Map(10 -> 4096), Map(), Map()) @@ -239,6 +279,8 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("sw", Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), + Map(), + Map(), Map(5 -> 1234), Map(6 -> 1234), Map(), Map(0x100 -> 1234)) @@ -271,41 +313,57 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("lb", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(5 -> BigInt("04", 16)), Map(), Map()), CPUTestCase("lh", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(5 -> BigInt("0304", 16)), Map(), Map()), CPUTestCase("lbu", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(5 -> BigInt("f4", 16)), Map(), Map()), CPUTestCase("lhu", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(5 -> BigInt("f3f4", 16)), Map(), Map()), CPUTestCase("lb1", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(5 -> BigInt("fffffff4", 16)), Map(), Map()), CPUTestCase("lh1", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(5 -> BigInt("fffff3f4", 16)), Map(), Map()), CPUTestCase("sb", Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), + Map(), + Map(), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffffff01", 16))), CPUTestCase("sh", Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), + Map(), + Map(), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffff0001", 16))) @@ -364,6 +422,8 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("jal", Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -399,11 +459,15 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("jalr0", Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(5 -> 1234, 10 -> 28), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr1", Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(5 -> 1234, 10 -> 20), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -440,21 +504,29 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("fibonacci", Map("single-cycle" -> 300, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(6->11), Map(6->11,5->89), Map(), Map()), CPUTestCase("naturalsum", Map("single-cycle" -> 200, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(), Map(5->55), Map(), Map()), CPUTestCase("multiplier", - Map("single-cycle" -> 1000, "five-cycle" -> 6, "pipelined" -> 6), - Map(5->23,6->20), + Map("single-cycle" -> 1000, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), + Map(5->23,6->20), Map(5->23*20), Map(), Map()), CPUTestCase("divider", Map("single-cycle" -> 1000, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(5->1260,6->30), Map(7->42), Map(), Map()) From a753229ae416f9771c1a9cde275d599cb1aa8603 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 14 May 2019 18:43:55 -0700 Subject: [PATCH 06/57] resolved test file conflict 3rd time --- src/main/scala/testing/InstTests.scala | 107 ++++++++++++++----------- 1 file changed, 58 insertions(+), 49 deletions(-) diff --git a/src/main/scala/testing/InstTests.scala b/src/main/scala/testing/InstTests.scala index dec66e85..4ae85614 100644 --- a/src/main/scala/testing/InstTests.scala +++ b/src/main/scala/testing/InstTests.scala @@ -227,55 +227,7 @@ object InstTests { Map(), Map(), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), - Map(), Map()), - CPUTestCase("csrrc", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrci", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrs", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrsi", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrw", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrwi", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()), - CPUTestCase("ecall", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()), - CPUTestCase("ebreak", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) + Map(), Map()) ) val itypeMultiCycle = List[CPUTestCase]( @@ -567,6 +519,57 @@ object InstTests { Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) ) + + val csr = List[CPUTestCase]( + CPUTestCase("csrrc", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()), + CPUTestCase("csrrci", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()), + CPUTestCase("csrrs", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()), + CPUTestCase("csrrsi", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()), + CPUTestCase("csrrw", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()), + CPUTestCase("csrrwi", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()), + CPUTestCase("ecall", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()), + CPUTestCase("ebreak", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + ) val smallApplications = List[CPUTestCase]( CPUTestCase("fibonacci", @@ -647,12 +650,18 @@ object InstTests { "utype" -> utype, "utypeMultiCycle" -> utypeMultiCycle, "jump" -> jump, + "csr" -> csr, "smallApplications" -> smallApplications ) // All of the tests +<<<<<<< HEAD val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ branchMultiCycle ++ memory ++ memoryMultiCycle ++ utype ++ utypeMultiCycle ++ jump ++ smallApplications +======= + val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ + memory ++ memoryMultiCycle ++ utype ++ jump ++ csr ++ smallApplications +>>>>>>> 5d9a896... addes seperate csr test category, still having argument mismatch errors // Mapping from full name of test to test val nameMap = (allTests ++ fullApplications).map(x => x.name() -> x).toMap From c37e759d0d801d93639e72c14524bdadf2e2430f Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 14 May 2019 18:49:46 -0700 Subject: [PATCH 07/57] resolved lab merge conflicts --- src/main/scala/single-cycle/cpu.scala | 1 + src/main/scala/testing/InstTests.scala | 13 +++++-------- src/test/scala/labs/Lab2Test.scala | 1 + 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/src/main/scala/single-cycle/cpu.scala b/src/main/scala/single-cycle/cpu.scala index 1d61f544..1f2e4fa8 100644 --- a/src/main/scala/single-cycle/cpu.scala +++ b/src/main/scala/single-cycle/cpu.scala @@ -121,6 +121,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { val structures = List( (control, "control"), (registers, "registers"), + (csr, "csr"), (aluControl, "aluControl"), (alu, "alu"), (immGen, "immGen"), diff --git a/src/main/scala/testing/InstTests.scala b/src/main/scala/testing/InstTests.scala index 4ae85614..2df44caf 100644 --- a/src/main/scala/testing/InstTests.scala +++ b/src/main/scala/testing/InstTests.scala @@ -523,9 +523,10 @@ object InstTests { val csr = List[CPUTestCase]( CPUTestCase("csrrc", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), + Map( 0x300 -> 0x1888 ), + Map( 0x300 -> 0xffffe777 ), + Map( 6 -> 0xfffffffb), + Map( 6 -> 0xfffffffb), Map(), Map()), CPUTestCase("csrrci", Map("single-cycle" -> 1, "pipelined" -> 5), @@ -657,11 +658,7 @@ object InstTests { // All of the tests <<<<<<< HEAD val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ branchMultiCycle ++ - memory ++ memoryMultiCycle ++ utype ++ utypeMultiCycle ++ jump ++ smallApplications -======= - val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ - memory ++ memoryMultiCycle ++ utype ++ jump ++ csr ++ smallApplications ->>>>>>> 5d9a896... addes seperate csr test category, still having argument mismatch errors + memory ++ memoryMultiCycle ++ utype ++ utypeMultiCycle ++ jump ++ csr ++ smallApplications // Mapping from full name of test to test val nameMap = (allTests ++ fullApplications).map(x => x.name() -> x).toMap diff --git a/src/test/scala/labs/Lab2Test.scala b/src/test/scala/labs/Lab2Test.scala index 580ca77c..21590724 100644 --- a/src/test/scala/labs/Lab2Test.scala +++ b/src/test/scala/labs/Lab2Test.scala @@ -144,6 +144,7 @@ class SingleCycleStoreTesterLab2 extends CPUFlatSpec { */ class SingleCycleLoadStoreTesterLab2 extends CPUFlatSpec { +<<<<<<< HEAD val tests = InstTests.tests("memory") for (test <- tests) { "Single Cycle CPU" should s"run load/store instruction test ${test.binary}${test.extraName}" in { From 8a808d445f3c1f9bd272e29e7b43062ee29ac20f Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Fri, 10 May 2019 20:00:50 -0700 Subject: [PATCH 08/57] corrected csr to regfile wiring, enable mie by default --- Top.DualPortedMemory.memory.v | 20 +++++++++ firrtl_black_box_resource_files.f | 1 + src/main/scala/components/csr.scala | 58 +++++++++++++++++++------- src/main/scala/single-cycle/cpu.scala | 6 ++- src/test/resources/risc-v/csrrc | Bin 4748 -> 4752 bytes src/test/resources/risc-v/csrrc.riscv | 1 + stale_outputs_checked | 0 7 files changed, 68 insertions(+), 18 deletions(-) create mode 100644 Top.DualPortedMemory.memory.v create mode 100644 firrtl_black_box_resource_files.f create mode 100644 stale_outputs_checked diff --git a/Top.DualPortedMemory.memory.v b/Top.DualPortedMemory.memory.v new file mode 100644 index 00000000..a41466f6 --- /dev/null +++ b/Top.DualPortedMemory.memory.v @@ -0,0 +1,20 @@ +module BindsTo_0_DualPortedMemory( + input clock, + input reset, + input [31:0] io_imem_address, + output [31:0] io_imem_instruction, + input [31:0] io_dmem_address, + input [31:0] io_dmem_writedata, + input io_dmem_memread, + input io_dmem_memwrite, + input [1:0] io_dmem_maskmode, + input io_dmem_sext, + output [31:0] io_dmem_readdata +); + +initial begin + $readmemh("test", DualPortedMemory.memory); +end + endmodule + +bind DualPortedMemory BindsTo_0_DualPortedMemory BindsTo_0_DualPortedMemory_Inst(.*); \ No newline at end of file diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f new file mode 100644 index 00000000..900ea4d4 --- /dev/null +++ b/firrtl_black_box_resource_files.f @@ -0,0 +1 @@ +/riscv/Top.DualPortedMemory.memory.v \ No newline at end of file diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index b4417d26..8aaef9b7 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -238,7 +238,8 @@ class CSRRegFileIO extends Bundle{ val write_illegal = Output(Bool()) val system_illegal = Output(Bool()) } - + + val regwrite = Output(Bool()) val status = Output(new MStatus())//not needed in this design but useful if more ISA extensions val evec = Output(UInt(32.W)) // val exception = Input(Bool()) // rename to illgl inst @@ -254,6 +255,7 @@ class CSRRegFile extends Module{ val reset_mstatus = WireInit(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := MCSRCmd.MPRV//machine mode + reset_mstatus.mie := true.B//machine mode val reg_mstatus = RegInit(reset_mstatus) val reg_mepc = Reg(UInt(32.W)) @@ -303,29 +305,53 @@ class CSRRegFile extends Module{ read_mapping += MCSRs.minstreth -> 0.U //CSR DECODE - val cmd = if( io.decode.inst(6, 0) == ("b1110011".U) ) { - if( (io.decode.inst(19, 15) == ("b011".U)) || (io.decode.inst(19, 15) == ("b111".U)) ){ - MCSRCmd.clear //CSRRC{i} - }else if( (io.decode.inst(19, 15) == ("b010".U)) || (io.decode.inst(19, 15) == ("b110".U)) ){ - MCSRCmd.set //CSRRS{i} - }else if( (io.decode.inst(19, 15) == ("b001".U)) || (io.decode.inst(19, 15) == ("b101".U)) ){ - MCSRCmd.write //CSRRW{i} - }else if( (io.decode.inst(19, 15) == ("b000".U)) ) { - MCSRCmd.interrupt //ebreak, ecall + val cmd = WireInit(3.U(3.W)) + + when( io.decode.inst(6, 0) === ("b1110011".U)){ + switch(io.decode.inst(14, 12)){ + is("b011".U){ + cmd := MCSRCmd.clear + io.regwrite := true.B + } + is("b111".U){ + cmd := MCSRCmd.clear + io.regwrite := true.B + } + is("b010".U){ + cmd := MCSRCmd.set + io.regwrite := true.B + } + is("b110".U){ + cmd := MCSRCmd.set + io.regwrite := true.B + } + is("b001".U){ + cmd := MCSRCmd.write + io.regwrite := true.B + } + is("b101".U){ + cmd := MCSRCmd.write + io.regwrite := false.B + } + is("b000".U){ + cmd := MCSRCmd.interrupt + io.regwrite := false.B + } } - }else{ - MCSRCmd.nop + }.otherwise{ + cmd := MCSRCmd.nop + io.regwrite := false.B } val csr = io.decode.inst(MCSRCmd.MSB, MCSRCmd.LSB) - val system_insn = cmd == MCSRCmd.interrupt - val cpu_ren = cmd != MCSRCmd.nop && !system_insn + val system_insn = cmd === MCSRCmd.interrupt + val cpu_ren = cmd =/= MCSRCmd.nop && !system_insn val decoded_addr = read_mapping map { case (k, v) => k -> (csr === k) } val priv_sufficient = MCSRCmd.MPRV >= csr(9,8) val read_only = csr(11,10).andR - val cpu_wen = cpu_ren && cmd != MCSRCmd.read && priv_sufficient + val cpu_wen = cpu_ren && cmd =/= MCSRCmd.read && priv_sufficient val wen = cpu_wen && !read_only val wdata = readModifyWriteCSR(cmd.asInstanceOf[UInt], io.rw.rdata, io.rw.wdata) @@ -352,7 +378,7 @@ class CSRRegFile extends Module{ reg_mepc := io.pc // misaligned memory exceptions not supported... } - assert(PopCount(insn_ret :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") + //assert(PopCount(insn_ret :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") when (reg_time >= reg_mtimecmp) { reg_mip.mtix := true diff --git a/src/main/scala/single-cycle/cpu.scala b/src/main/scala/single-cycle/cpu.scala index 1f2e4fa8..554436e7 100644 --- a/src/main/scala/single-cycle/cpu.scala +++ b/src/main/scala/single-cycle/cpu.scala @@ -44,7 +44,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { registers.io.readreg2 := instruction(24,20) registers.io.writereg := instruction(11,7) - registers.io.wen := control.io.regwrite && (registers.io.writereg =/= 0.U) + registers.io.wen := (control.io.regwrite || csr.io.regwrite) && (registers.io.writereg =/= 0.U) aluControl.io.add := control.io.add aluControl.io.immediate := control.io.immediate @@ -83,7 +83,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { //WRITEBACK csr.io.decode.inst := instruction csr.io.decode.immid := imm - csr.io.rw.wdata := registers.io.readdata2 + csr.io.rw.wdata := registers.io.readdata1 csr.io.retire := true.B //mem is synchronous in this deisgn. no flushing as far as i'm aware @@ -98,6 +98,8 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { write_data := io.dmem.readdata } .elsewhen (control.io.toreg === 2.U) { write_data := pcPlusFour.io.result + } .elsewhen (control.io.toreg === 3.U) { + write_data := csr.io.rw.rdata } .otherwise { write_data := alu.io.result } diff --git a/src/test/resources/risc-v/csrrc b/src/test/resources/risc-v/csrrc index 70e16b78a4fc2af91a91272e7e64b4bb0cd2e425..ae8450446fea3927213f4ff6defba08a33a33a6d 100755 GIT binary patch delta 70 zcmeBCouE2FfpNh^MP*hQ1_lP1jh@^2S%jGj>L&?QFv@JM6o_YJl$m@}P#H-66;x-m Zn5-(K&d4#@S4f>TN05QRcrv4qFaU)*5W)Ze delta 81 zcmbQB+M_x_fpN}6MP*hA1_lO+jh@^2C$k7tFiLE$6^LhKl$d;1P#H)v3aK-iOx6UF WERzF;)Fm Date: Fri, 10 May 2019 20:05:46 -0700 Subject: [PATCH 09/57] added mret in InsTest --- src/main/scala/testing/InstTests.scala | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/main/scala/testing/InstTests.scala b/src/main/scala/testing/InstTests.scala index 2df44caf..71f077b7 100644 --- a/src/main/scala/testing/InstTests.scala +++ b/src/main/scala/testing/InstTests.scala @@ -569,7 +569,14 @@ object InstTests { Map(), Map(), Map(), Map(), + Map(), Map()), + CPUTestCase("mret", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), Map(), Map()) + ) val smallApplications = List[CPUTestCase]( From 374a9fcdb0d8c3df853b7d97cc3d769380b2a237 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Fri, 10 May 2019 20:29:52 -0700 Subject: [PATCH 10/57] corrected csrrwi reg enable flag, addes all csrrx tests --- src/main/scala/components/csr.scala | 3 ++- src/test/resources/risc-v/csrrc | Bin 4752 -> 4756 bytes src/test/resources/risc-v/csrrc.riscv | 3 ++- src/test/resources/risc-v/csrrci | Bin 4748 -> 4752 bytes src/test/resources/risc-v/csrrci.riscv | 1 + src/test/resources/risc-v/csrrs | Bin 4748 -> 4756 bytes src/test/resources/risc-v/csrrs.riscv | 2 ++ src/test/resources/risc-v/csrrsi | Bin 4748 -> 4752 bytes src/test/resources/risc-v/csrrsi.riscv | 3 ++- src/test/resources/risc-v/csrrw | Bin 4748 -> 4756 bytes src/test/resources/risc-v/csrrw.riscv | 2 ++ src/test/resources/risc-v/csrrwi | Bin 4748 -> 4752 bytes src/test/resources/risc-v/csrrwi.riscv | 1 + 13 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 8aaef9b7..ea554d6c 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -256,6 +256,7 @@ class CSRRegFile extends Module{ val reset_mstatus = WireInit(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := MCSRCmd.MPRV//machine mode reset_mstatus.mie := true.B//machine mode + reset_mstatus.mie := true.B//machine mode val reg_mstatus = RegInit(reset_mstatus) val reg_mepc = Reg(UInt(32.W)) @@ -331,7 +332,7 @@ class CSRRegFile extends Module{ } is("b101".U){ cmd := MCSRCmd.write - io.regwrite := false.B + io.regwrite := true.B } is("b000".U){ cmd := MCSRCmd.interrupt diff --git a/src/test/resources/risc-v/csrrc b/src/test/resources/risc-v/csrrc index ae8450446fea3927213f4ff6defba08a33a33a6d..09586dbea884f3517335980bb04f64615964f162 100755 GIT binary patch delta 111 zcmbQBIz@GY0^^d2ips1C3=9kk8$EaO%YLZ;Y{YCJ4CJHZ%}fE4r3Dfh6*kuj#4|D~ lOuj3q3?vza)ER9iYXV80$$>)Z5(R<`48}n1Fu(|9000R45~KhC delta 104 zcmbQDIze@U0^@>-ips1q3=9l18$EaOOBU3BHexmq2J+GHWO;!^Mw!ix0`ZKDGLs() p0yPORFi1^q6cU~+BP76RF8O0{~Cs5!e6# delta 104 zcmbQB+M_x_fpN}6MP*hA1_lO+jh;LB#UAk+2m?82c(SxWBBR9ST7h^*Mv2LH1(ks$ eqmVkI$z)9+$uc=mNL?aRkb%J%s1*hnp$q`>)(@fp diff --git a/src/test/resources/risc-v/csrrsi.riscv b/src/test/resources/risc-v/csrrsi.riscv index da67d74d..b592ae70 100644 --- a/src/test/resources/risc-v/csrrsi.riscv +++ b/src/test/resources/risc-v/csrrsi.riscv @@ -2,11 +2,12 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: - csrrsi t0, mstatus, 0x1f + csrrsi t0, mstatus, 0x18 nop nop nop nop nop + add t0, x0, t0 _last: diff --git a/src/test/resources/risc-v/csrrw b/src/test/resources/risc-v/csrrw index b48a4ec3b4ac65758f529c05eb4defcbe27d1abf..6327126fefb710b56fb29937de88b220622a02f6 100755 GIT binary patch delta 78 zcmeBCouWEHfpN)1MP*h61_lO&jh@^2S%jHC@J|wuVBX9WFj-t6kx^lDr9eC*qr&8y hg33Vhub?`k&16*}bw-}azC!A(1%eC=#*-O^gaI3u61@Nb delta 102 zcmbQD+M_x_fpN}6MP*hA1_lO+jh@^2#Xk!%8wdk=Xn3-`Kq8~W=0<^dMn;Lr4+Vi* n1Q-~kCN~NRPnHo9U^JPmE2PfKBFMmy0v5{wie*f$6%q#k@~RWc diff --git a/src/test/resources/risc-v/csrrw.riscv b/src/test/resources/risc-v/csrrw.riscv index 2666481a..e4d7a0e8 100644 --- a/src/test/resources/risc-v/csrrw.riscv +++ b/src/test/resources/risc-v/csrrw.riscv @@ -2,6 +2,7 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: + addi t1, x0, 0xff csrrw t0, mstatus, t1 nop @@ -9,4 +10,5 @@ _start: nop nop nop + add t0, x0, t0 _last: diff --git a/src/test/resources/risc-v/csrrwi b/src/test/resources/risc-v/csrrwi index b8629172963279c962f1e0993b9b3659ade931a2..1df91787a586f31625713a037dae21db76d6263c 100755 GIT binary patch delta 70 zcmeBCouE2FfpNh^MP*hQ1_lP1jh^TEnKv^9OcobNWR%%lDG<-dC^Pw{pfZsBE2z$B ZF Date: Mon, 13 May 2019 15:52:36 -0700 Subject: [PATCH 11/57] added incomplete misaligned mem exception handeling --- src/main/scala/components/csr.scala | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index ea554d6c..99530059 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -378,6 +378,25 @@ class CSRRegFile extends Module{ io.evec := "h80000004".U reg_mepc := io.pc // misaligned memory exceptions not supported... } + + //MISALIGNED MEM ACCESS + /* + when (io.???) { //fetchexcept? + reg_mcause.interrupt := MCauses.misaligned_fetch & "h80000000".U + reg_mcause.exceptioncode := MCauses.misaligned_fetch & "h7fffffff".U + io.evec := "h80000004".U + reg_mepc := ??? + }.elsewhen (io.???){ ///loadexception? + reg_mcause.interrupt := MCauses.misaligned_load & "h80000000".U + reg_mcause.exceptioncode := MCauses.misaligned_load & "h7fffffff".U + io.evec := "h80000004".U + reg_mepc := ??? + }.elsewhen(io.???){ //storeexception? + reg_mcause.interrupt := MCauses.misaligned_store & "h80000000".U + reg_mcause.exceptioncode := MCauses.misaligned_store & "h7fffffff".U + io.evec := "h80000004".U + reg_mepc := ??? + }*/ //assert(PopCount(insn_ret :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") From d510b1733e4878d92c1924adfcd5b07f67bc471d Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Mon, 13 May 2019 18:21:26 -0700 Subject: [PATCH 12/57] csr and system calls finsihed and tested, fully working, commented code a bit --- src/main/scala/components/csr.scala | 191 ++++++++++--------------- src/main/scala/single-cycle/cpu.scala | 23 ++- src/test/resources/risc-v/Makefile | 2 +- src/test/resources/risc-v/csrrc.riscv | 2 - src/test/resources/risc-v/csrrci.riscv | 1 - src/test/resources/risc-v/csrrs.riscv | 2 - src/test/resources/risc-v/csrrsi.riscv | 3 +- src/test/resources/risc-v/csrrw.riscv | 2 - src/test/resources/risc-v/csrrwi.riscv | 3 +- src/test/resources/risc-v/ebreak.riscv | 12 ++ src/test/resources/risc-v/ecall.riscv | 12 ++ src/test/resources/risc-v/mret.riscv | 12 ++ 12 files changed, 121 insertions(+), 144 deletions(-) create mode 100644 src/test/resources/risc-v/ebreak.riscv create mode 100644 src/test/resources/risc-v/ecall.riscv create mode 100644 src/test/resources/risc-v/mret.riscv diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 99530059..f7648b70 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -25,23 +25,6 @@ object MCauses { val misaligned_store = 0x6 val store_access = 0x7 val machine_ecall = 0xb - val all = { - val res = collection.mutable.ArrayBuffer[Int]() - res += machine_soft_int - res += machine_timer_int - res += machine_ext_int - - res += misaligned_fetch - res += fetch_access - res += illegal_instruction - res += breakpoint - res += misaligned_load - res += load_access - res += misaligned_store - res += store_access - res += machine_ecall - res.toArray - } } object MCSRs { @@ -76,30 +59,6 @@ object MCSRs { val minstreth = 0xb82 //performance counter setup val mcounterinhibit = 0x320 - val all = { - val res = collection.mutable.ArrayBuffer[Int]() - res += mstatus - res += misa - res += medeleg - res += mideleg - res += mie - res += mtvec - res += mscratch - res += mepc - res += mcause - res += mtval - res += mip - res += mcycle - res += minstret - res += mcycleh - res += minstreth - res += mvendorid - res += marchid - res += mhartid - res += mimpid - res += mcounterinhibit - res.toArray - } } class MStatus extends Bundle{ @@ -218,71 +177,82 @@ object MCSRCmd{ val TRAPADDR = "h80000000".U val MPRV = 3 } - - -//reorder bundles -class CSRRegFileIO extends Bundle{ - //val hartid = Input(UInt(32.W)) - val rw = new Bundle { - val rdata = Output(UInt(32.W)) // - val wdata = Input(UInt(32.W)) // - } - - val csr_stall = Output(Bool())//not needed in single cycle - val eret = Output(Bool())// change ret names - val decode = new Bundle { +class CSRRegFile extends Module{ + //INIT CSR + val io = IO(new Bundle{ + val illegal_inst = Input(Bool())// + val retire_inst = Input(Bool())// + val pc = Input(UInt(32.W)) // + val read_data = Input(UInt(32.W)) // val inst = Input(UInt(32.W)) // val immid = Input(UInt(32.W)) // + val read_illegal = Output(Bool()) val write_illegal = Output(Bool()) val system_illegal = Output(Bool()) - } - - val regwrite = Output(Bool()) - val status = Output(new MStatus())//not needed in this design but useful if more ISA extensions - val evec = Output(UInt(32.W)) // - val exception = Input(Bool()) // rename to illgl inst - val retire = Input(Bool()) // rename to retire inst - val pc = Input(UInt(32.W)) // - val time = Output(UInt(32.W))// -} - -class CSRRegFile extends Module{ - //INIT CSR - val io = IO(new CSRRegFileIO) + val csr_stall = Output(Bool())//not needed in single cycle + val eret = Output(Bool())//return vector from a trap + val evec = Output(UInt(32.W)) //trap address + val write_data = Output(UInt(32.W)) // + val reg_write = Output(Bool())// + val status = Output(new MStatus())//not needed in this design but useful if more ISA extensions + val time = Output(UInt(32.W))// + }) io := DontCare val reset_mstatus = WireInit(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := MCSRCmd.MPRV//machine mode reset_mstatus.mie := true.B//machine mode - reset_mstatus.mie := true.B//machine mode + //contains info about system interrupts and privlidge mode val reg_mstatus = RegInit(reset_mstatus) + //exception program counter, set when exception raised val reg_mepc = Reg(UInt(32.W)) + //contains cause of exception val reg_mcause = RegInit(0.U.asTypeOf(new MCause())) + //register that can hold data to assist with exceptions/traps val reg_mtval = Reg(UInt(32.W)) + //scratch register for trap handler, useful for switching between mode memory spaces val reg_mscratch = Reg(UInt(32.W)) + //register used to set time for when timer interrupt should be raised val reg_mtimecmp = Reg(UInt(64.W)) + //register to indicate if trap handler should go directly to a specifc modes' trap handler + //rather than trap to machine mode then swap context to a less privileged mode. used to save + //performance, our implementation does not implement hardware to do this. val reg_medeleg = Reg(UInt(32.W)) + //indicates if we have a pending iterrupt for different interrupt types and modes val reg_mip = RegInit(0.U.asTypeOf(new MIx())) + //indicates which interrupts are enabled val reg_mie = RegInit(0.U.asTypeOf(new MIx())) + //used to halt cpu if WFI inst is seen, or can also just do nothing. This cpu doesn't + //implement WFI inst....yet val reg_wfi = RegInit(false.B) + //trap vector/address val reg_mtvec = RegInit(0.U.asTypeOf(new MTVec())) - + //current cpu time given in cycles val reg_time = WideCounter(64) - val reg_instret = WideCounter(64, io.retire) - + //number of instructions that have been completed + val reg_instret = WideCounter(64, io.retire_inst) + //performance counters, not implemented val reg_mcounterinhibit = RegInit(0.U.asTypeOf(new XCounterEnInhibit())) + //performance counter control val reg_mcounteren = RegInit(0.U.asTypeOf(new XCounterEnInhibit())) - + //machine status, contains interrupt bits, and priviledge mode val read_mstatus = io.status.asUInt() val isa_string = "I" - val reg_misa = RegInit((BigInt(0) | isa_string.map(x => 1 << (x - 'A')).reduce(_|_)).U.asTypeOf(new MISA())) + //takes user defined ISA string character by character and calculates ascii number for each, + //aligns the result to be a multiple of 2 then ors the results together to fit into MISA + //this tells the system what extensions are implemented + //val reg_misa = RegInit((BigInt(0) | isa_string.map(x => 1 << (x - 'A')).reduce(_|_)).U.asTypeOf(new MISA())) + //same as above but hardcoded for only I extension + val reg_misa = RegInit(16.U.asTypeOf(new MISA())) + //if we are a company we can hardcode our implementation info here val reg_mvendorid = RegInit(0.U.asTypeOf(new MVendorID())) - + //this hashmap associates CSR addresses to the actual register contents + //this is done to make decoding and working with csr's easier (avoid manual specification) val read_mapping = collection.mutable.LinkedHashMap[Int,Bits]( MCSRs.mcounterinhibit -> reg_mcounterinhibit.asUInt, MCSRs.mcycle -> reg_time, @@ -300,103 +270,88 @@ class CSRRegFile extends Module{ MCSRs.mtval -> reg_mtval, MCSRs.mcause -> reg_mcause.asUInt(), MCSRs.mhartid -> 0.U, - MCSRs.medeleg -> reg_medeleg) + MCSRs.medeleg -> reg_medeleg, + MCSRs.mcycleh -> 0.U, + MCSRs.minstreth -> 0.U + ) - read_mapping += MCSRs.mcycleh -> 0.U - read_mapping += MCSRs.minstreth -> 0.U - //CSR DECODE val cmd = WireInit(3.U(3.W)) - when( io.decode.inst(6, 0) === ("b1110011".U)){ - switch(io.decode.inst(14, 12)){ + when( io.inst(6, 0) === ("b1110011".U)){ + switch(io.inst(14, 12)){ is("b011".U){ cmd := MCSRCmd.clear - io.regwrite := true.B + io.reg_write := true.B } is("b111".U){ cmd := MCSRCmd.clear - io.regwrite := true.B + io.reg_write := true.B } is("b010".U){ cmd := MCSRCmd.set - io.regwrite := true.B + io.reg_write := true.B } is("b110".U){ cmd := MCSRCmd.set - io.regwrite := true.B + io.reg_write := true.B } is("b001".U){ cmd := MCSRCmd.write - io.regwrite := true.B + io.reg_write := true.B } is("b101".U){ cmd := MCSRCmd.write - io.regwrite := true.B + io.reg_write := true.B } is("b000".U){ cmd := MCSRCmd.interrupt - io.regwrite := false.B + io.reg_write := false.B } } }.otherwise{ cmd := MCSRCmd.nop - io.regwrite := false.B + io.reg_write := false.B } - val csr = io.decode.inst(MCSRCmd.MSB, MCSRCmd.LSB) + val csr = io.inst(MCSRCmd.MSB, MCSRCmd.LSB) val system_insn = cmd === MCSRCmd.interrupt val cpu_ren = cmd =/= MCSRCmd.nop && !system_insn - + //map is an infix operator on read_mapping. takes argument from decoded_addr() and applies it to + //read_mapping which provides a set if it exists then checks if the csr in the set corresponds to + //what the csr instruction specified. used for easier when statements below val decoded_addr = read_mapping map { case (k, v) => k -> (csr === k) } val priv_sufficient = MCSRCmd.MPRV >= csr(9,8) val read_only = csr(11,10).andR val cpu_wen = cpu_ren && cmd =/= MCSRCmd.read && priv_sufficient val wen = cpu_wen && !read_only - val wdata = readModifyWriteCSR(cmd.asInstanceOf[UInt], io.rw.rdata, io.rw.wdata) + val wdata = readModifyWriteCSR(cmd.asInstanceOf[UInt], io.write_data, Mux(io.inst(14),io.immid, io.read_data)) + //harware optimization? change this later? val opcode = 1.U << csr(2,0) val insn_call = system_insn && opcode(0) val insn_break = system_insn && opcode(1) val insn_ret = system_insn && opcode(2) && priv_sufficient + //wait for interrupt inst not implemented val insn_wfi = system_insn && opcode(5) && priv_sufficient private def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map( { case(k: Int, _: Bits) => csr === k }).reduce(_ || _) - io.decode.read_illegal := 3 < csr(9,8) || !decodeAny(read_mapping) - io.decode.write_illegal := csr(11,10).andR - io.decode.system_illegal := 3 < csr(9,8) + io.read_illegal := 3 < csr(9,8) || !decodeAny(read_mapping) + io.write_illegal := csr(11,10).andR + io.system_illegal := 3 < csr(9,8) io.status := reg_mstatus io.eret := insn_call || insn_break || insn_ret // ILLEGAL INSTR - when (io.exception) { + when (io.illegal_inst) { reg_mcause.interrupt := MCauses.illegal_instruction & "h80000000".U reg_mcause.exceptioncode := MCauses.illegal_instruction & "h7fffffff".U - io.evec := "h80000004".U + io.evec := "h80000000".U reg_mepc := io.pc // misaligned memory exceptions not supported... } - - //MISALIGNED MEM ACCESS - /* - when (io.???) { //fetchexcept? - reg_mcause.interrupt := MCauses.misaligned_fetch & "h80000000".U - reg_mcause.exceptioncode := MCauses.misaligned_fetch & "h7fffffff".U - io.evec := "h80000004".U - reg_mepc := ??? - }.elsewhen (io.???){ ///loadexception? - reg_mcause.interrupt := MCauses.misaligned_load & "h80000000".U - reg_mcause.exceptioncode := MCauses.misaligned_load & "h7fffffff".U - io.evec := "h80000004".U - reg_mepc := ??? - }.elsewhen(io.???){ //storeexception? - reg_mcause.interrupt := MCauses.misaligned_store & "h80000000".U - reg_mcause.exceptioncode := MCauses.misaligned_store & "h7fffffff".U - io.evec := "h80000004".U - reg_mepc := ??? - }*/ //assert(PopCount(insn_ret :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") @@ -420,7 +375,7 @@ class CSRRegFile extends Module{ //EBREAK when(insn_break){ - io.evec := "h80000004".U + io.evec := "h80000008".U reg_mcause.interrupt := MCauses.breakpoint & "h80000000".U reg_mcause.exceptioncode := MCauses.breakpoint & "h7fffffff".U } @@ -429,7 +384,7 @@ class CSRRegFile extends Module{ io.csr_stall := reg_wfi - io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) + io.write_data := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) when (wen) { //MISA IS FIXED IN THIS IMPLEMENATION diff --git a/src/main/scala/single-cycle/cpu.scala b/src/main/scala/single-cycle/cpu.scala index 554436e7..5a95dd1a 100644 --- a/src/main/scala/single-cycle/cpu.scala +++ b/src/main/scala/single-cycle/cpu.scala @@ -44,7 +44,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { registers.io.readreg2 := instruction(24,20) registers.io.writereg := instruction(11,7) - registers.io.wen := (control.io.regwrite || csr.io.regwrite) && (registers.io.writereg =/= 0.U) + registers.io.wen := (control.io.regwrite || csr.io.reg_write) && (registers.io.writereg =/= 0.U) aluControl.io.add := control.io.add aluControl.io.immediate := control.io.immediate @@ -55,6 +55,13 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { val imm = immGen.io.sextImm //ALU + csr.io.inst := instruction + csr.io.immid := imm + csr.io.read_data := registers.io.readdata1 + csr.io.retire_inst := true.B //mem is synchronous in this deisgn. no flushing as far as i'm aware + csr.io.illegal_inst := !control.io.validinst || csr.io.read_illegal || csr.io.write_illegal || csr.io.system_illegal //illegal inst exception? + csr.io.pc := pc + branchCtrl.io.branch := control.io.branch branchCtrl.io.funct3 := instruction(14,12) branchCtrl.io.inputx := registers.io.readdata1 @@ -81,25 +88,13 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { io.dmem.sext := ~instruction(14) //WRITEBACK - csr.io.decode.inst := instruction - csr.io.decode.immid := imm - csr.io.rw.wdata := registers.io.readdata1 - - - csr.io.retire := true.B //mem is synchronous in this deisgn. no flushing as far as i'm aware - csr.io.exception := !control.io.validinst || csr.io.decode.read_illegal || - csr.io.decode.write_illegal || csr.io.decode.system_illegal //illegal inst exception? - csr.io.pc := pc - - - val write_data = Wire(UInt()) when (control.io.toreg === 1.U) { write_data := io.dmem.readdata } .elsewhen (control.io.toreg === 2.U) { write_data := pcPlusFour.io.result } .elsewhen (control.io.toreg === 3.U) { - write_data := csr.io.rw.rdata + write_data := csr.io.write_data } .otherwise { write_data := alu.io.result } diff --git a/src/test/resources/risc-v/Makefile b/src/test/resources/risc-v/Makefile index 157a74ee..170b6280 100644 --- a/src/test/resources/risc-v/Makefile +++ b/src/test/resources/risc-v/Makefile @@ -1,5 +1,5 @@ -RISCV ?= /home/nganjehl/riscv-gnu-toolchain +RISCV ?= /opt/riscv RISCVBIN = $(RISCV)/bin SOURCES = $(wildcard *.riscv) diff --git a/src/test/resources/risc-v/csrrc.riscv b/src/test/resources/risc-v/csrrc.riscv index 36dd8e2c..8d2d4eb3 100644 --- a/src/test/resources/risc-v/csrrc.riscv +++ b/src/test/resources/risc-v/csrrc.riscv @@ -2,7 +2,6 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: - addi t1, x0, 0x7ff #disable interrupt mie csrrc t0, mstatus, t1 nop @@ -10,5 +9,4 @@ _start: nop nop nop - add t0, x0, t0 # _last: diff --git a/src/test/resources/risc-v/csrrci.riscv b/src/test/resources/risc-v/csrrci.riscv index a75ab400..bdc85239 100644 --- a/src/test/resources/risc-v/csrrci.riscv +++ b/src/test/resources/risc-v/csrrci.riscv @@ -9,5 +9,4 @@ _start: nop nop nop - add t0, x0, t0 _last: diff --git a/src/test/resources/risc-v/csrrs.riscv b/src/test/resources/risc-v/csrrs.riscv index b4a9f0ca..2214b34a 100644 --- a/src/test/resources/risc-v/csrrs.riscv +++ b/src/test/resources/risc-v/csrrs.riscv @@ -2,7 +2,6 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: - addi t1, x0, 0x18 #set mpie to 1 and attempt to set spp (should stay false) csrrs t0, mstatus, t1 nop @@ -10,5 +9,4 @@ _start: nop nop nop - add t0, x0, t0 _last: diff --git a/src/test/resources/risc-v/csrrsi.riscv b/src/test/resources/risc-v/csrrsi.riscv index b592ae70..734abdd1 100644 --- a/src/test/resources/risc-v/csrrsi.riscv +++ b/src/test/resources/risc-v/csrrsi.riscv @@ -2,12 +2,11 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: - csrrsi t0, mstatus, 0x18 + csrrsi t0, mstatus, 0x7 #attempt to enable non m interrupts nop nop nop nop nop - add t0, x0, t0 _last: diff --git a/src/test/resources/risc-v/csrrw.riscv b/src/test/resources/risc-v/csrrw.riscv index e4d7a0e8..2666481a 100644 --- a/src/test/resources/risc-v/csrrw.riscv +++ b/src/test/resources/risc-v/csrrw.riscv @@ -2,7 +2,6 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: - addi t1, x0, 0xff csrrw t0, mstatus, t1 nop @@ -10,5 +9,4 @@ _start: nop nop nop - add t0, x0, t0 _last: diff --git a/src/test/resources/risc-v/csrrwi.riscv b/src/test/resources/risc-v/csrrwi.riscv index 6afa768c..447e36ce 100644 --- a/src/test/resources/risc-v/csrrwi.riscv +++ b/src/test/resources/risc-v/csrrwi.riscv @@ -2,12 +2,11 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: - csrrwi t0, mstatus, 0x1f + csrrwi t0, mstatus, 0x17 nop nop nop nop nop - add t0, x0, t0 _last: diff --git a/src/test/resources/risc-v/ebreak.riscv b/src/test/resources/risc-v/ebreak.riscv new file mode 100644 index 00000000..96e89dcf --- /dev/null +++ b/src/test/resources/risc-v/ebreak.riscv @@ -0,0 +1,12 @@ +.text + .align 2 # Make sure we're aligned to 4 bytes + .globl _start +_start: + ebreak + + nop + nop + nop + nop + nop +_last: diff --git a/src/test/resources/risc-v/ecall.riscv b/src/test/resources/risc-v/ecall.riscv new file mode 100644 index 00000000..ab3b17dc --- /dev/null +++ b/src/test/resources/risc-v/ecall.riscv @@ -0,0 +1,12 @@ +.text + .align 2 # Make sure we're aligned to 4 bytes + .globl _start +_start: + ecall + + nop + nop + nop + nop + nop +_last: diff --git a/src/test/resources/risc-v/mret.riscv b/src/test/resources/risc-v/mret.riscv new file mode 100644 index 00000000..34810898 --- /dev/null +++ b/src/test/resources/risc-v/mret.riscv @@ -0,0 +1,12 @@ +.text + .align 2 # Make sure we're aligned to 4 bytes + .globl _start +_start: + mret + + nop + nop + nop + nop + nop +_last: From 561b99ecca877c2b44533a1d197ec4c30cd048f0 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 14 May 2019 17:25:10 -0700 Subject: [PATCH 13/57] unaligned mem access code wasn't push for some reason --- src/main/scala/components/csr.scala | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index f7648b70..17606f84 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -352,6 +352,26 @@ class CSRRegFile extends Module{ io.evec := "h80000000".U reg_mepc := io.pc // misaligned memory exceptions not supported... } + + //UNALIGNED MEM ACCESS + /* + when(io.???){ + reg_mcause.interrupt := MCauses.misaligned_fetch & "h80000000".U + reg_mcause.exceptioncode := MCauses.misaligned_fetch & "h7fffffff".U + io.evec := "h80000000".U + reg_mepc := + }.elsewhen(io.???){ + reg_mcause.interrupt := MCauses.misaligned_load & "h80000000".U + reg_mcause.exceptioncode := MCauses.misaligned_load & "h7fffffff".U + io.evec := "h80000000".U + reg_mepc := + }.elsewhen(io.???){ + reg_mcause.interrupt := MCauses.misaligned_store & "h80000000".U + reg_mcause.exceptioncode := MCauses.misaligned_store & "h7fffffff".U + io.evec := "h80000000".U + reg_mepc := + + }*/ //assert(PopCount(insn_ret :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") From 666880fd5d35c827cf5c184a503e3e16a9a16407 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 14 May 2019 17:29:50 -0700 Subject: [PATCH 14/57] 1st step cleanup --- Top.DualPortedMemory.memory.v | 20 - firrtl_black_box_resource_files.f | 1 - src/{verilog => cpp}/testbench.cpp | 0 "src/test/resources/risc-v/\\" | 619 ----------------------------- src/test/resources/risc-v/csrrc | Bin 4756 -> 4748 bytes src/test/resources/risc-v/csrrci | Bin 4752 -> 4748 bytes src/test/resources/risc-v/csrrs | Bin 4756 -> 4748 bytes src/test/resources/risc-v/csrrsi | Bin 4752 -> 4748 bytes src/test/resources/risc-v/csrrw | Bin 4756 -> 4748 bytes src/test/resources/risc-v/csrrwi | Bin 4752 -> 4748 bytes src/test/resources/risc-v/ebreak | Bin 0 -> 4748 bytes src/test/resources/risc-v/ecall | Bin 0 -> 4748 bytes src/test/resources/risc-v/mret | Bin 0 -> 4748 bytes stale_outputs_checked | 0 14 files changed, 640 deletions(-) delete mode 100644 Top.DualPortedMemory.memory.v delete mode 100644 firrtl_black_box_resource_files.f rename src/{verilog => cpp}/testbench.cpp (100%) delete mode 100644 "src/test/resources/risc-v/\\" create mode 100755 src/test/resources/risc-v/ebreak create mode 100755 src/test/resources/risc-v/ecall create mode 100755 src/test/resources/risc-v/mret delete mode 100644 stale_outputs_checked diff --git a/Top.DualPortedMemory.memory.v b/Top.DualPortedMemory.memory.v deleted file mode 100644 index a41466f6..00000000 --- a/Top.DualPortedMemory.memory.v +++ /dev/null @@ -1,20 +0,0 @@ -module BindsTo_0_DualPortedMemory( - input clock, - input reset, - input [31:0] io_imem_address, - output [31:0] io_imem_instruction, - input [31:0] io_dmem_address, - input [31:0] io_dmem_writedata, - input io_dmem_memread, - input io_dmem_memwrite, - input [1:0] io_dmem_maskmode, - input io_dmem_sext, - output [31:0] io_dmem_readdata -); - -initial begin - $readmemh("test", DualPortedMemory.memory); -end - endmodule - -bind DualPortedMemory BindsTo_0_DualPortedMemory BindsTo_0_DualPortedMemory_Inst(.*); \ No newline at end of file diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f deleted file mode 100644 index 900ea4d4..00000000 --- a/firrtl_black_box_resource_files.f +++ /dev/null @@ -1 +0,0 @@ -/riscv/Top.DualPortedMemory.memory.v \ No newline at end of file diff --git a/src/verilog/testbench.cpp b/src/cpp/testbench.cpp similarity index 100% rename from src/verilog/testbench.cpp rename to src/cpp/testbench.cpp diff --git "a/src/test/resources/risc-v/\\" "b/src/test/resources/risc-v/\\" deleted file mode 100644 index 71f4c040..00000000 --- "a/src/test/resources/risc-v/\\" +++ /dev/null @@ -1,619 +0,0 @@ -// Lists of different instruction test cases for use with different CPU models - -package dinocpu - -/** - * This object contains a set of lists of tests. Each list is a different set of - * instruction types and corresponds to a RISC-V program in resources/risc-v - * - * Each test case looks like: - * - binary to run in src/test/resources/risc-v - * - number of cycles to run for each CPU type - * - initial values for csr registers - * - final values to check for csr registers - * - initial values for registers - * - final values to check for registers - * - initial values for memory - * - final values to check for memory - * - extra name information - */ -object InstTests { - - val maxInt = BigInt("FFFFFFFF", 16) - - def twoscomp(v: BigInt) : BigInt = { - if (v < 0) { - return maxInt + v + 1 - } else { - return v - } - } - - val rtype = List[CPUTestCase]( - CPUTestCase("add1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1234), - Map(0 -> 0, 5 -> 1234, 6 -> 1234), - Map(), Map()), - CPUTestCase("add2", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1234, 20 -> 5678), - Map(0 -> 0, 10 -> 6912), - Map(), Map()), - CPUTestCase("add0", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1234, 6 -> 3456), - Map(0 -> 0, 5 -> 1234, 6 -> 3456), - Map(), Map()), - CPUTestCase("or", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1234, 6 -> 5678), - Map(7 -> 5886), - Map(), Map()), - CPUTestCase("sub", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1234, 6 -> 5678), - Map(7 -> BigInt("FFFFEEA4", 16)), - Map(), Map()), - CPUTestCase("and", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1234, 6 -> 5678), - Map(7 -> 1026), - Map(), Map()), - CPUTestCase("xor", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> 1234, 5 -> 5678), - Map(5 -> 5678, 7 -> 1234, 6 -> 4860), - Map(), Map()), - CPUTestCase("slt", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> 1234, 5 -> 5678), - Map(5 -> 5678, 7 -> 1234, 6 -> 1), - Map(), Map()), - CPUTestCase("slt1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> -1, 5 -> 1), - Map(5 -> 1, 6 -> 1), - Map(), Map()), - CPUTestCase("sltu", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> -1, 5 -> 1), - Map(5 -> 1, 6 -> 0), - Map(), Map()), - CPUTestCase("sltu1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> 20, 5 -> 100), - Map(5 -> 100, 6 -> 1), - Map(), Map()), - CPUTestCase("sll", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> 32, 5 -> 2), - Map(7 -> 32, 5 -> 2, 6 -> 128), - Map(), Map()), - CPUTestCase("srl", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> 32, 5 -> 2), - Map(7 -> 32, 5 -> 2, 6 -> 8), - Map(), Map()), - CPUTestCase("sra", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> twoscomp(-2), 5 -> 31), - Map(5 -> 31, 6 -> twoscomp(-1)), - Map(), Map()) - ) - - val rtypeMultiCycle = List[CPUTestCase]( - CPUTestCase("addfwd", - Map("single-cycle" -> 10, "five-cycle" -> 0, "pipelined" -> 14), - Map(), Map(), - Map(5 -> 1, 10 -> 0), - Map(5 -> 1, 10 -> 10), - Map(), Map()), - CPUTestCase("swapxor", - Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), - Map(), Map(), - Map(7 -> 5678, 5 -> 1234), - Map(5 -> 5678,7->1234), - Map(), Map()), - CPUTestCase("power2", - Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), - Map(), Map(), - Map(5 -> 512, 6->1), - Map(7->1), - Map(), Map(), "-512"), - CPUTestCase("power2", - Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), - Map(), Map(), - Map(5 -> 1234, 6->1), - Map(7->0), - Map(), Map(), "-1234"), - CPUTestCase("power2", - Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), - Map(), Map(), - Map(5 -> twoscomp(-65536), 6->1), - Map(7->0), // This algorithm doesn't work for negative numbers - Map(), Map(), "--65536"), - CPUTestCase("oppsign", - Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), - Map(), Map(), - Map(5 -> 512, 6->twoscomp(-1024),7->0), - Map(7->1), - Map(), Map(), "-true"), - CPUTestCase("oppsign", - Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), - Map(), Map(), - Map(5 -> 512, 6->1024,7->0), - Map(7->0), - Map(), Map(), "-false"), - CPUTestCase("rotR", - Map("single-cycle" -> 4, "five-cycle" -> 0, "pipelined" -> 8), - Map(), Map(), - Map(5 -> twoscomp(-1), 6->1, 7->32), - Map(7->twoscomp(-1)), - Map(), Map()) - ) - - val itype = List[CPUTestCase]( - CPUTestCase("addi1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(0 -> 0, 10 -> 17), - Map(), Map()), - CPUTestCase("slli", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1), - Map(0 -> 0, 5 -> 1, 6 -> 128), - Map(), Map()), - CPUTestCase("srai", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1024), - Map(0 -> 0, 5 -> 1024, 6 -> 8), - Map(), Map()), - CPUTestCase("srai", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> twoscomp(-1024)), - Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), - Map(), Map(), "-negative"), - CPUTestCase("srli", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 128), - Map(0 -> 0, 5 -> 128, 6 -> 1), - Map(), Map()), - CPUTestCase("andi", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 456), - Map(0 -> 0, 5 -> 456, 6 -> 200), - Map(), Map()), - CPUTestCase("ori", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 456), - Map(0 -> 0, 5 -> 456, 6 -> 511), - Map(), Map()), - CPUTestCase("xori", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 456), - Map(0 -> 0, 5 -> 456, 6 -> 311), - Map(), Map()), - CPUTestCase("slti", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> twoscomp(-1)), - Map(0 -> 0, 5 -> twoscomp(-1),6->1), - Map(), Map()), - CPUTestCase("sltiu", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> twoscomp(-1)), - Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), - Map(), Map()) - CPUTestCase("csrrc", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - CPUTestCase("csrrci", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - CPUTestCase("csrrs", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - CPUTestCase("csrrsi", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - CPUTestCase("csrrw", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - CPUTestCase("csrrwi", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - CPUTestCase("ecall", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - CPUTestCase("ebreak", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - ) - - val itypeMultiCycle = List[CPUTestCase]( - CPUTestCase("addi2", - Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 6), - Map(), Map(), - Map(), - Map(0 -> 0, 10 -> 17, 11 -> 93), - Map(), Map()) - ) - - val branch = List[CPUTestCase]( - CPUTestCase("beq", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(), Map(), "-False"), - CPUTestCase("beq", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(), Map(), "-True"), - CPUTestCase("bne", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(), Map(), "-False"), - CPUTestCase("bne", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(), Map(), "-True"), - CPUTestCase("blt", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), - Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> 5678), - Map(), Map(), "-False"), - CPUTestCase("blt", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(), Map(), "-False-equal"), - CPUTestCase("blt", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(), Map(), "-True"), - CPUTestCase("blt", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), - Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), - Map(), Map(), "-False-signed"), - CPUTestCase("blt", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), - Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), - Map(), Map(), "-True-signed"), - CPUTestCase("bge", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(), Map(), "-False"), - CPUTestCase("bge", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), - Map(5 -> 1235, 6 -> 1, 7 -> 9012, 28 -> 5678), - Map(), Map(), "-True"), - CPUTestCase("bge", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), - Map(5 -> 0, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), - Map(), Map(), "-False-signed"), - CPUTestCase("bge", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), - Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), - Map(), Map(), "-True-signed"), - CPUTestCase("bge", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(), Map(), "-True-equal"), - CPUTestCase("bltu", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), - Map(5 -> 0, 6 -> 1, 7 -> maxInt, 28 -> 5678), - Map(), Map(), "-False"), - CPUTestCase("bltu", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), - Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> maxInt), - Map(), Map(), "-True"), - CPUTestCase("bgeu", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), - Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> maxInt), - Map(), Map(), "-False"), - CPUTestCase("bgeu", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), - Map(5 -> 1235, 6 -> 1, 7 -> maxInt, 28 -> 5678), - Map(), Map(), "-True") - ) - - val memory = List[CPUTestCase]( - CPUTestCase("lw1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(5 -> BigInt("ffffffff", 16)), - Map(), Map()), - CPUTestCase("lb", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(5 -> BigInt("04", 16)), - Map(), Map()), - CPUTestCase("lh", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(5 -> BigInt("0304", 16)), - Map(), Map()), - CPUTestCase("lbu", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(5 -> BigInt("f4", 16)), - Map(), Map()), - CPUTestCase("lhu", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(5 -> BigInt("f3f4", 16)), - Map(), Map()), - CPUTestCase("lb1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(5 -> BigInt("fffffff4", 16)), - Map(), Map()), - CPUTestCase("lh1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(5 -> BigInt("fffff3f4", 16)), - Map(), Map()), - CPUTestCase("sw", - Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), - Map(), Map(), - Map(5 -> 1234), - Map(6 -> 1234), - Map(), Map(0x100 -> 1234)), - CPUTestCase("sb", - Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), - Map(), Map(), - Map(5 -> 1), - Map(6 -> 1), - Map(), Map(0x100 -> BigInt("ffffff01", 16))), - CPUTestCase("sh", - Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), - Map(), Map(), - Map(5 -> 1), - Map(6 -> 1), - Map(), Map(0x100 -> BigInt("ffff0001", 16))) - ) - - val memoryMultiCycle = List[CPUTestCase]( - CPUTestCase("lwfwd", - Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), - Map(), Map(), - Map(5 -> BigInt("ffffffff", 16), 10 -> 5), - Map(5 -> 1, 10 -> 6), - Map(), Map()) - ) - - val utype = List[CPUTestCase]( - CPUTestCase("auipc0", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(10 -> 1234), - Map(10 -> 0), - Map(), Map()), - CPUTestCase("auipc1", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), Map(), - Map(10 -> 1234), - Map(10 -> 4), - Map(), Map()), - CPUTestCase("auipc2", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), Map(), - Map(10 -> 1234), - Map(10 -> (17 << 12)), - Map(), Map()), - CPUTestCase("auipc3", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), Map(), - Map(10 -> 1234), - Map(10 -> ((17 << 12) + 4)), - Map(), Map()), - CPUTestCase("lui0", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(10 -> 1234), - Map(10 -> 0), - Map(), Map()), - CPUTestCase("lui1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(10 -> 1234), - Map(10 -> 4096), - Map(), Map()) - ) - - val jump = List[CPUTestCase]( - CPUTestCase("jal", - Map("single-cycle" -> 2, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234), - Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), - Map(), Map()), - CPUTestCase("jalr0", - Map("single-cycle" -> 2, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 10 -> 28), - Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), - Map(), Map()), - CPUTestCase("jalr1", - Map("single-cycle" -> 2, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 10 -> 20), - Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), - Map(), Map()) - ) - - val smallApplications = List[CPUTestCase]( - CPUTestCase("fibonacci", - Map("single-cycle" -> 300, "five-cycle" -> 0, "pipelined" -> 1000), - Map(), Map(), - Map(6->11), - Map(6->11,5->89), - Map(), Map()), - CPUTestCase("naturalsum", - Map("single-cycle" -> 200, "five-cycle" -> 0, "pipelined" -> 500), - Map(), Map(), - Map(), - Map(5->55), - Map(), Map()), - CPUTestCase("multiplier", - Map("single-cycle" -> 1000, "five-cycle" -> 0, "pipelined" -> 1000), - Map(), Map(), - Map(5->23,6->20,8->0x1000), - Map(5->23*20), - Map(), Map()), - CPUTestCase("divider", - Map("single-cycle" -> 1000, "five-cycle" -> 0, "pipelined" -> 2000), - Map(), Map(), - Map(5->1260,6->30), - Map(7->42), - Map(), Map()) - ) - - val fullApplications = List[CPUTestCase]( - CPUTestCase("multiply.riscv", - Map("single-cycle" -> 42342, "five-cycle" -> 0, "pipelined" -> 100000), - Map(), Map(), - Map(), - Map(10->12345678), - Map(), Map()), - CPUTestCase("median.riscv", - Map("single-cycle" -> 9433, "five-cycle" -> 0, "pipelined" -> 100000), - Map(), Map(), - Map(), - Map(10->12345678), - Map(), Map()), - CPUTestCase("qsort.riscv", - Map("single-cycle" -> 263290, "five-cycle" -> 0, "pipelined" -> 300000), - Map(), Map(), - Map(), - Map(10->12345678), - Map(), Map()), - CPUTestCase("rsort.riscv", - Map("single-cycle" -> 263290, "five-cycle" -> 0, "pipelined" -> 250000), - Map(), Map(), - Map(), - Map(10->12345678), - Map(), Map()), - CPUTestCase("towers.riscv", - Map("single-cycle" -> 12653, "five-cycle" -> 0, "pipelined" -> 100000), - Map(), Map(), - Map(), - Map(10->12345678), - Map(), Map()), - CPUTestCase("vvadd.riscv", - Map("single-cycle" -> 5484, "five-cycle" -> 0, "pipelined" -> 20000), - Map(), Map(), - Map(), - Map(10->12345678), - Map(), Map()) - ) - - // Mapping from group name to list of tests - val tests = Map( - "rtype" -> rtype, - "rtypeMultiCycle" -> rtypeMultiCycle, - "itype" -> itype, - "itypeMultiCycle" -> itypeMultiCycle, - "branch" -> branch, - "memory" -> memory, - "memoryMultiCycle" -> memoryMultiCycle, - "utype" -> utype, - "jump" -> jump, - "smallApplications" -> smallApplications - ) - - // All of the tests - val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ - memory ++ memoryMultiCycle ++ utype ++ jump ++ smallApplications - - // Mapping from full name of test to test - val nameMap = (allTests ++ fullApplications).map(x => x.name() -> x).toMap -} diff --git a/src/test/resources/risc-v/csrrc b/src/test/resources/risc-v/csrrc index 09586dbea884f3517335980bb04f64615964f162..70e16b78a4fc2af91a91272e7e64b4bb0cd2e425 100755 GIT binary patch delta 102 zcmbQD+M_x_fpN}6MP*hA1_lO+jh@^2#XlP{8wdk=Xn3-`Kq8~W=0<^dMn;Lr4+Vi* n1Q-~kCN~NRPnHo9U^JPmE2PfKBFMmy0v5{wie*f$6%q#k{E8Fm delta 78 zcmeBCouWEHfpN)1MP*h61_lO&jh@^2S%jHC)K3zSVBX9WFj-t6kx^lDr9eC*qr&8y hg33Vhub?`k&16*}bw-}azC!A(1%eC=#*-O^gaI8O0{~Cs5!e6# diff --git a/src/test/resources/risc-v/csrrw b/src/test/resources/risc-v/csrrw index 6327126fefb710b56fb29937de88b220622a02f6..b48a4ec3b4ac65758f529c05eb4defcbe27d1abf 100755 GIT binary patch delta 102 zcmbQD+M_x_fpN}6MP*hA1_lO+jh@^2#Xk!%8wdk=Xn3-`Kq8~W=0<^dMn;Lr4+Vi* n1Q-~kCN~NRPnHo9U^JPmE2PfKBFMmy0v5{wie*f$6%q#k@~RWc delta 78 zcmeBCouWEHfpN)1MP*h61_lO&jh@^2S%jHC@J|wuVBX9WFj-t6kx^lDr9eC*qr&8y hg33Vhub?`k&16*}bw-}azC!A(1%eC=#*-O^gaI3u61@Nb diff --git a/src/test/resources/risc-v/csrrwi b/src/test/resources/risc-v/csrrwi index 1df91787a586f31625713a037dae21db76d6263c..5fbc628c22ddd35431f26cdcad70a9c8377e00dc 100755 GIT binary patch delta 103 zcmbQB+M_x_fpN}6MP*hA1_lO+jh;LCMY#=xfowE9Sy~{GQDSqgKs+O(#N@kz%0QA) dNS)DSvL=vZnH(sjE|Dq7z+ep23ImK#1^}a*4!i&W delta 92 zcmeBCouE2FfpNh^MP*hQ1_lP1jh;LCCHW16foycVnJHkhxIiMK%;rjgct%E<$u|X+ gf#hF7bw-QHszU0F9Fu*8)LC-{85oQwGYSa<059Ybc>n+a diff --git a/src/test/resources/risc-v/ebreak b/src/test/resources/risc-v/ebreak new file mode 100755 index 0000000000000000000000000000000000000000..0b06c789f7a44e2ebfe515717e0b1a67757944e8 GIT binary patch literal 4748 zcmeI0ze)o^5XR^74-~-@o2ZS7h1DUK)IwsSD3T^NR_mTw^e`r2cMV$kB0iL_B0hl5 z+_IO;A!uha1Dl!eo4IBAb(z=xc6)|?8lzfWb&>i|w%nf-=%TTE4ao?bSm|s}!V{dhoVv+F%2*DcQB?$rtgVd=>El zbSBHDZ4mM1Wd@S@zS+s7{pB{V!`o{i1i0|v6P)W}@onFpbm0W+=g@%Ao;TeS04S2aJX z`TLreH4n*DWm%Mi%#=1DeliJtm_Nob_R-F!;rek0 zv*uf&0^;feEL~d*`;MH!Ofx7bd!@3sF7~~nB;>T?p^PPk5)*V NeRC{ys;>2WzX7JDMwkEq literal 0 HcmV?d00001 diff --git a/src/test/resources/risc-v/mret b/src/test/resources/risc-v/mret new file mode 100755 index 0000000000000000000000000000000000000000..9707950ab455ab6ac785b5c770f1e9a523ef2b8d GIT binary patch literal 4748 zcmeI0%}T>S5XUD?TNFeqUaDRyc<>ZT+oPA1)(?El zbSBHDX%O`0Wd=4g|CxW5<#(Ld{@s=5dElZ1pWsvnn{S79(t!r{FQ5t)JFmGv0P0xM zsZcA|C&|GCm;e)C0!)AjFaajO1egF5U;<2l3H(0+4UOgzKBIWTV{EEKk5=FvU|CVC zb}MNuo4-8S&$b8F=tF6%Q-+VP9URfVz=j9=RP0$*!+C?sveO=fwoJb@ye)l0ZhlFV zoW3dOhk|}AXqc(k1Pc&TsSOA*nJywZ70X33H?ca$&afBWhoalRz8wgGx;q?-{-BrE zk=8;Rsp!vbTRfIVf{5p1fIzQjMn;&8viZqXCVnvxq^tvJj7p+s6Ki_oALA5#w6m!? zKki^Qd^0p~hI1ca>1=iMoj8G+?x3JtN-O*6pzj?^LQFdz%GiQkJa}IgW!x2wGPSvn NR!Di@1RL!ieBUD%Mw9>m literal 0 HcmV?d00001 diff --git a/stale_outputs_checked b/stale_outputs_checked deleted file mode 100644 index e69de29b..00000000 From c839878359b0d7ad9c8cfdbd803a8f36b204606e Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 14 May 2019 17:35:22 -0700 Subject: [PATCH 15/57] reverted test binary --- src/test/resources/risc-v/add0 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/add1 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/add2 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/addfwd | Bin 4784 -> 4592 bytes src/test/resources/risc-v/addi1 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/addi2 | Bin 4752 -> 4560 bytes src/test/resources/risc-v/and | Bin 4748 -> 4552 bytes src/test/resources/risc-v/andi | Bin 4748 -> 4556 bytes src/test/resources/risc-v/auipc0 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/auipc1 | Bin 4752 -> 4560 bytes src/test/resources/risc-v/auipc2 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/auipc3 | Bin 4752 -> 4560 bytes src/test/resources/risc-v/beq | Bin 4840 -> 4648 bytes src/test/resources/risc-v/bge | Bin 4840 -> 4648 bytes src/test/resources/risc-v/bgeu | Bin 4840 -> 4648 bytes src/test/resources/risc-v/blt | Bin 4840 -> 4648 bytes src/test/resources/risc-v/bltu | Bin 4840 -> 4648 bytes src/test/resources/risc-v/bne | Bin 4840 -> 4648 bytes src/test/resources/risc-v/divider | Bin 5932 -> 5740 bytes src/test/resources/risc-v/fibonacci | Bin 5864 -> 5672 bytes src/test/resources/risc-v/jal | Bin 4796 -> 4604 bytes src/test/resources/risc-v/jalr0 | Bin 4800 -> 4604 bytes src/test/resources/risc-v/jalr1 | Bin 4800 -> 4604 bytes src/test/resources/risc-v/lb | Bin 5812 -> 5620 bytes src/test/resources/risc-v/lb1 | Bin 5812 -> 5620 bytes src/test/resources/risc-v/lbu | Bin 5812 -> 5620 bytes src/test/resources/risc-v/lh | Bin 5812 -> 5620 bytes src/test/resources/risc-v/lh1 | Bin 5812 -> 5620 bytes src/test/resources/risc-v/lhu | Bin 5812 -> 5620 bytes src/test/resources/risc-v/lui0 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/lui1 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/lw1 | Bin 5812 -> 5620 bytes src/test/resources/risc-v/lwfwd | Bin 5816 -> 5620 bytes src/test/resources/risc-v/multiplier | Bin 5864 -> 5672 bytes src/test/resources/risc-v/naturalsum | Bin 5864 -> 5672 bytes src/test/resources/risc-v/oppsign | Bin 4756 -> 4560 bytes src/test/resources/risc-v/or | Bin 4744 -> 4552 bytes src/test/resources/risc-v/ori | Bin 4748 -> 4552 bytes src/test/resources/risc-v/power2 | Bin 4756 -> 4564 bytes src/test/resources/risc-v/rotR | Bin 4760 -> 4568 bytes src/test/resources/risc-v/sb | Bin 5812 -> 5620 bytes src/test/resources/risc-v/sh | Bin 5812 -> 5620 bytes src/test/resources/risc-v/sll | Bin 4748 -> 4552 bytes src/test/resources/risc-v/slli | Bin 4748 -> 4556 bytes src/test/resources/risc-v/slt | Bin 4748 -> 4552 bytes src/test/resources/risc-v/slt1 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/slti | Bin 4748 -> 4556 bytes src/test/resources/risc-v/sltiu | Bin 4748 -> 4556 bytes src/test/resources/risc-v/sltu | Bin 4748 -> 4556 bytes src/test/resources/risc-v/sltu1 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/sort | Bin 6004 -> 5808 bytes src/test/resources/risc-v/sra | Bin 4748 -> 4552 bytes src/test/resources/risc-v/srai | Bin 4748 -> 4556 bytes src/test/resources/risc-v/srl | Bin 4748 -> 4552 bytes src/test/resources/risc-v/srli | Bin 4748 -> 4556 bytes src/test/resources/risc-v/sub | Bin 4748 -> 4552 bytes src/test/resources/risc-v/sw | Bin 5812 -> 5812 bytes src/test/resources/risc-v/sw.riscv | 1 + src/test/resources/risc-v/swapxor | Bin 4760 -> 4564 bytes src/test/resources/risc-v/test | Bin 5836 -> 5644 bytes src/test/resources/risc-v/xor | Bin 4748 -> 4552 bytes src/test/resources/risc-v/xori | Bin 4748 -> 4556 bytes 62 files changed, 1 insertion(+) diff --git a/src/test/resources/risc-v/add0 b/src/test/resources/risc-v/add0 index 7785b2a23a0449eeae29e2d41438fe25f49896e4..d53471e009316c86f3934f992b57e694aeb4b896 100755 GIT binary patch delta 172 zcmeBCJ)=B9L6}950SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRZ=!6b;U z0AxuBKmPd$}j0C2^22MEKV+CVB`lfS&PbyjWUf2 z3??SZ3o`?iA_Hayrpe|4s`U&!5K#e!kN*`wOcofQk--td1d{?l{RSWwlDrKX-vf;w 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aHWZR(T>%s^pByNp%z7WlQk={vBn$v&92lGc literal 4748 zcmeI0&q~8U5XL9{CxT+dOVxu49y~>9d-GyTYZ0WEh&Nd_Hfo?YWp^$06J1?B^VtqRUZv)G! znzfp7b9(a2FPF3JfgLPEY00U;$JYwBXkTE%gLNv_tg2&wkIIVE9-P@S{nqidW2$of z(}Erp^mRes6g12e7IET&03F_Ah%C+KyqI-=VjTnvRk-3B&5Yc1=;Opl{BSXwa+5F%t6U`0yDQaIDqvG(%M4Eo_ud$1Rw6m$X z3%G+>@Xb)c0rtxPQ#aPYxg94kyS)$PQqFJV+&gMQPCFjTXu&ETd@qX%?ux=pE#9LQ MQhx3Zjn)ry-v@F=umAu6 diff --git a/src/test/resources/risc-v/xori b/src/test/resources/risc-v/xori index 396860922f85c9b034b5aae423c504258465b4b4..9970b919c31c6a83ea7945a3034911e94d0ee4e1 100755 GIT binary patch delta 172 zcmeBCJ)=B9L6}950SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRZ=!6b;U z0AxuBKmPd$}j0C2^22MEKV+CVB`lfS&PbyjWUf2 z3??SZ3o`?iA_Hayrpe|4s`U&!5K#e!kN*`wOcofQk--td1d{?l{RSWwlDrKX-vf;w zj>eBe<1tb#gUaw zzAT_8s0a3~USdf}QD#zUNow(AM!{fFMW8jz3=9Pz+dx1@8lvid=2eOPoDgis&H;(`S From 159b1c6f7025df4e6a26473a3b9401755b62418d Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 14 May 2019 17:40:36 -0700 Subject: [PATCH 16/57] more cleanup --- src/test/resources/risc-v/sw | Bin 5812 -> 5620 bytes src/test/resources/risc-v/sw.riscv | 1 - 2 files changed, 1 deletion(-) diff --git a/src/test/resources/risc-v/sw b/src/test/resources/risc-v/sw index 4a12e983891160077c00550ebb56842279d81919..2aef06ce26a4592ff64114ab77cfa4668c361c18 100755 GIT binary patch delta 207 zcmdm@`$c<#f-s9H0~nYvC@?TGXfUubux>Oy%fFdL;1Bb}0+vZ4EE5xDCfkUJOimCH z@zsGS29k^nJV25KL;!&R0~3QXgbC#{GROg0EG!T~kh~Te-*ECr5q-|2;^O$?lEk8t z$swX96O*(j9}yK{)R}x!)Oxawm;f(}2m`|ckVYV8og679&AJ3AVm6skOn7pSm;mc7 JAWt2{0{~*pAWHxM delta 399 zcmeyOy+wC|g76$s1~4#TP+(wW&|qL^VB2VXmY;btQ^Dr{{C}AziLgjIN&=M>Wfmuw zF);E2nXE-+#zvV&1qKrnfQ8}Xe>Nc304~JHzyoBnfCwNE z0Lse&X%-eR7szK~u!k_gqyW$~Jv4bMRK5~}8%QaV0imc07-A+*711{dc5w`GjCXQ% z_wYEUlZuPui%SxVN`T_X$|j!`F%i@QdtNWGq@*Y_sk9`ucrv4? zJ)^;7M^S50b)Z$u3=9Pz7k~hZ2m^!E Date: Wed, 15 May 2019 16:13:08 -0700 Subject: [PATCH 17/57] forgot to remove merge tag in lab2test --- src/test/scala/labs/Lab2Test.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/src/test/scala/labs/Lab2Test.scala b/src/test/scala/labs/Lab2Test.scala index 21590724..580ca77c 100644 --- a/src/test/scala/labs/Lab2Test.scala +++ b/src/test/scala/labs/Lab2Test.scala @@ -144,7 +144,6 @@ class SingleCycleStoreTesterLab2 extends CPUFlatSpec { */ class SingleCycleLoadStoreTesterLab2 extends CPUFlatSpec { -<<<<<<< HEAD val tests = InstTests.tests("memory") for (test <- tests) { "Single Cycle CPU" should s"run load/store instruction test ${test.binary}${test.extraName}" in { From e318c683bd53db48aab6abbb64a2e7ac19011b67 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 16:49:52 -0700 Subject: [PATCH 18/57] removed csr test params from lab2test grader, and fivecycle option --- src/test/scala/grading/Lab2Tests.scala | 140 +++++++------------------ 1 file changed, 35 insertions(+), 105 deletions(-) diff --git a/src/test/scala/grading/Lab2Tests.scala b/src/test/scala/grading/Lab2Tests.scala index dae07001..d4d02b38 100644 --- a/src/test/scala/grading/Lab2Tests.scala +++ b/src/test/scala/grading/Lab2Tests.scala @@ -53,85 +53,63 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase](CPUTestCase("add1", Map("single-cycle" -> 1), - Map(), - Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), CPUTestCase("addi1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(0 -> 0, 10 -> 17), Map(), Map()), CPUTestCase("addi2", - Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 6), Map(), Map(0 -> 0, 10 -> 17, 11 -> 93), Map(), Map()), CPUTestCase("slli", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> 1), Map(0 -> 0, 5 -> 1, 6 -> 128), Map(), Map()), CPUTestCase("srai", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> 1024), Map(0 -> 0, 5 -> 1024, 6 -> 8), Map(), Map()), CPUTestCase("srai", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> twoscomp(-1024)), Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), Map(), Map(), "-negative"), CPUTestCase("srli", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> 128), Map(0 -> 0, 5 -> 128, 6 -> 1), Map(), Map()), CPUTestCase("andi", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 200), Map(), Map()), CPUTestCase("ori", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 511), Map(), Map()), CPUTestCase("xori", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 311), Map(), Map()), CPUTestCase("slti", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1),6->1), Map(), Map()), CPUTestCase("sltiu", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), Map(), Map()) @@ -165,16 +143,12 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("lw1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(5 -> BigInt("ffffffff", 16)), Map(), Map()), CPUTestCase("lwfwd", - Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 7), Map(5 -> BigInt("ffffffff", 16), 10 -> 5), Map(5 -> 1, 10 -> 6), Map(), Map()) @@ -206,44 +180,32 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("auipc0", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc1", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 6), Map(10 -> 1234), Map(10 -> 4), Map(), Map()), CPUTestCase("auipc2", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 6), Map(10 -> 1234), Map(10 -> (17 << 12)), Map(), Map()), CPUTestCase("auipc3", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 6), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()), CPUTestCase("lui0", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("lui1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(10 -> 1234), Map(10 -> 4096), Map(), Map()) @@ -278,9 +240,7 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("sw", - Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), - Map(), - Map(), + Map("single-cycle" -> 6, "pipelined" -> 10), Map(5 -> 1234), Map(6 -> 1234), Map(), Map(0x100 -> 1234)) @@ -312,58 +272,42 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("lb", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(5 -> BigInt("04", 16)), Map(), Map()), CPUTestCase("lh", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(5 -> BigInt("0304", 16)), Map(), Map()), CPUTestCase("lbu", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(5 -> BigInt("f4", 16)), Map(), Map()), CPUTestCase("lhu", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(5 -> BigInt("f3f4", 16)), Map(), Map()), CPUTestCase("lb1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(5 -> BigInt("fffffff4", 16)), Map(), Map()), CPUTestCase("lh1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(5 -> BigInt("fffff3f4", 16)), Map(), Map()), CPUTestCase("sb", - Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), - Map(), - Map(), + Map("single-cycle" -> 6, "pipelined" -> 10), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffffff01", 16))), CPUTestCase("sh", - Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), - Map(), - Map(), + Map("single-cycle" -> 6, "pipelined" -> 10), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffff0001", 16))) @@ -421,9 +365,7 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("jal", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 6), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -458,16 +400,12 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("jalr0", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 6), Map(5 -> 1234, 10 -> 28), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr1", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 6), Map(5 -> 1234, 10 -> 20), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -503,30 +441,22 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("fibonacci", - Map("single-cycle" -> 300, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 300, "pipelined" -> 6), Map(6->11), Map(6->11,5->89), Map(), Map()), CPUTestCase("naturalsum", - Map("single-cycle" -> 200, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 200, "pipelined" -> 6), Map(), Map(5->55), Map(), Map()), CPUTestCase("multiplier", - Map("single-cycle" -> 1000, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 1000, "pipelined" -> 6), Map(5->23,6->20), Map(5->23*20), Map(), Map()), CPUTestCase("divider", - Map("single-cycle" -> 1000, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 1000, "pipelined" -> 6), Map(5->1260,6->30), Map(7->42), Map(), Map()) From 951de839e6303abc556526e3b4ccc8e0dc05879c Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 20:00:09 -0700 Subject: [PATCH 19/57] refactored csr to avoid using utils, restored helpers.scala --- src/main/scala/components/csr.scala | 198 ++++++++++++++------- src/main/scala/components/helpers.scala | 217 ------------------------ 2 files changed, 132 insertions(+), 283 deletions(-) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 17606f84..7b5d0bde 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -5,28 +5,63 @@ package dinocpu import chisel3._ import collection.mutable.LinkedHashMap import chisel3.util._ -import Util._ +//import Util._ import scala.math._ object MCauses { //with interrupt - val machine_soft_int = 0x80000003 - val machine_timer_int = 0x80000007 - val machine_ext_int = 0x8000000b + val machine_soft_int = "h80000003".U + val machine_timer_int = "h80000007".U + val machine_ext_int = "h8000000b".U //non interrupt - val misaligned_fetch = 0x0 - val fetch_access = 0x1 - val illegal_instruction = 0x2 - val breakpoint = 0x3 - val misaligned_load = 0x4 - val load_access = 0x5 - val misaligned_store = 0x6 - val store_access = 0x7 - val machine_ecall = 0xb + val misaligned_fetch = "h0".U + val fetch_access = "h1".U + val illegal_instruction = "h2".U + val breakpoint = "h3".U + val misaligned_load = "h4".U + val load_access = "h5".U + val misaligned_store = "h6".U + val store_access = "h7".U + val machine_ecall = "hb".U } +/* +object MCSRs { + //machine information registers + val mvendorid = "hf11".U //vendor id + val marchid = "hf12".U //architecture id + val mimpid = "hf13".U //implementation id + val mhartid = "hf14".U //hardware thread id + //machine trap setup + val mstatus = "h300".U //machine status reg + val misa = "h301".U //isa and extensions + val medeleg = "h302".U //machine exception delegation reg + val mideleg = "h303".U //machine interrupt delegation reg + val mie = "h304".U //machine iterrupt-enable reg + val mtvec = "h305".U //machine trap handler base address + val mcounteren = "h306".U //machine counter enable + + //machine trap handling + val mscratch = "h340".U //scratch reg for machine trap handlers + val mepc = "h341".U //machine exception program counter + val mcause = "h342".U //machine trap cause + val mtval = "h343".U //machine bad address or instruction + val mip = "h344".U //machine interrupt pending + + //machine memory protection + //DONT NEED + + //machine counter/timers + val mcycle = "hb00".U //machine cycle counter + val minstret = "hb02".U //machine instructions retured counter + val mcycleh = "hb80".U + val minstreth = "hb82".U + //performance counter setup + val mcounterinhibit = "h320".U +} +*/ object MCSRs { //machine information registers val mvendorid = 0xf11 //vendor id @@ -175,29 +210,29 @@ object MCSRCmd{ val MSB = 31 val LSB = 20 val TRAPADDR = "h80000000".U - val MPRV = 3 + val MPRV = 3.U } class CSRRegFile extends Module{ //INIT CSR val io = IO(new Bundle{ - val illegal_inst = Input(Bool())// - val retire_inst = Input(Bool())// - val pc = Input(UInt(32.W)) // - val read_data = Input(UInt(32.W)) // - val inst = Input(UInt(32.W)) // - val immid = Input(UInt(32.W)) // + val illegal_inst = Input(Bool())//an exception signal for a non existent instruction or bad fields + val retire_inst = Input(Bool())//asserted if a valid instruction has finished + val pc = Input(UInt(32.W)) //current program counter value + val read_data = Input(UInt(32.W))//data from reg file used in csr instructions + val inst = Input(UInt(32.W)) //full instruction used for decoding csrs internally + val immid = Input(UInt(32.W)) //sext immidiate for immidiate csr instructions - val read_illegal = Output(Bool()) - val write_illegal = Output(Bool()) - val system_illegal = Output(Bool()) - val csr_stall = Output(Bool())//not needed in single cycle + val read_illegal = Output(Bool())//an exception raised interally by a bad csr inst, used to raise illegal inst signal + val write_illegal = Output(Bool())//raised interally by a bad csr inst, used to raise illegal inst signal + val system_illegal = Output(Bool())//bad syscall instruction raised interally, used to raise illegal inst signal + val csr_stall = Output(Bool())//used in conjunction with wait for interrupt inst, not needed in single cycle val eret = Output(Bool())//return vector from a trap val evec = Output(UInt(32.W)) //trap address - val write_data = Output(UInt(32.W)) // - val reg_write = Output(Bool())// + val write_data = Output(UInt(32.W)) //previous csr reg state sent to GP registers + val reg_write = Output(Bool())//should we allow write_data to be written into GP registers? val status = Output(new MStatus())//not needed in this design but useful if more ISA extensions - val time = Output(UInt(32.W))// + val time = Output(UInt(32.W))//time of operation in cpu cycles }) io := DontCare @@ -255,8 +290,8 @@ class CSRRegFile extends Module{ //this is done to make decoding and working with csr's easier (avoid manual specification) val read_mapping = collection.mutable.LinkedHashMap[Int,Bits]( MCSRs.mcounterinhibit -> reg_mcounterinhibit.asUInt, - MCSRs.mcycle -> reg_time, - MCSRs.minstret -> reg_instret, + MCSRs.mcycle -> reg_time.value, + MCSRs.minstret -> reg_instret.value, MCSRs.mimpid -> 0.U, MCSRs.marchid -> 0.U, MCSRs.mvendorid -> 0.U, @@ -321,7 +356,7 @@ class CSRRegFile extends Module{ //map is an infix operator on read_mapping. takes argument from decoded_addr() and applies it to //read_mapping which provides a set if it exists then checks if the csr in the set corresponds to //what the csr instruction specified. used for easier when statements below - val decoded_addr = read_mapping map { case (k, v) => k -> (csr === k) } + val decoded_addr = read_mapping map { case (k, v) => k -> (csr === k.U) } val priv_sufficient = MCSRCmd.MPRV >= csr(9,8) val read_only = csr(11,10).andR val cpu_wen = cpu_ren && cmd =/= MCSRCmd.read && priv_sufficient @@ -336,10 +371,10 @@ class CSRRegFile extends Module{ //wait for interrupt inst not implemented val insn_wfi = system_insn && opcode(5) && priv_sufficient - private def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map( { case(k: Int, _: Bits) => csr === k }).reduce(_ || _) - io.read_illegal := 3 < csr(9,8) || !decodeAny(read_mapping) + private def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map( { case(k: Int, _: Bits) => csr === k.U }).reduce(_ || _) + io.read_illegal := 3.U < csr(9,8) || !decodeAny(read_mapping) io.write_illegal := csr(11,10).andR - io.system_illegal := 3 < csr(9,8) + io.system_illegal := 3.U < csr(9,8) io.status := reg_mstatus @@ -375,14 +410,14 @@ class CSRRegFile extends Module{ //assert(PopCount(insn_ret :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") - when (reg_time >= reg_mtimecmp) { - reg_mip.mtix := true + when (reg_time.value >= reg_mtimecmp) { + reg_mip.mtix := true.B } //MRET when (insn_ret && !csr(10)) { reg_mstatus.mie := reg_mstatus.mpie - reg_mstatus.mpie := true + reg_mstatus.mpie := true.B io.evec := reg_mepc } @@ -400,7 +435,7 @@ class CSRRegFile extends Module{ reg_mcause.exceptioncode := MCauses.breakpoint & "h7fffffff".U } - io.time := reg_time + io.time := reg_time.value io.csr_stall := reg_wfi @@ -427,18 +462,18 @@ class CSRRegFile extends Module{ reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie //unused bits in mstatus m-mode only specified by spec - reg_mstatus.spp := 0 - reg_mstatus.uie := 0 - reg_mstatus.upie := 0 - reg_mstatus.mprv := 0 - reg_mstatus.mxr := 0 - reg_mstatus.sum := 0 - reg_mstatus.tvm := 0 - reg_mstatus.tw := 0 - reg_mstatus.tsr := 0 - reg_mstatus.fs := 0 - reg_mstatus.xs := 0 - reg_mstatus.sd := 0 + reg_mstatus.spp := 0.U + reg_mstatus.uie := 0.U + reg_mstatus.upie := 0.U + reg_mstatus.mprv := 0.U + reg_mstatus.mxr := 0.U + reg_mstatus.sum := 0.U + reg_mstatus.tvm := 0.U + reg_mstatus.tw := 0.U + reg_mstatus.tsr := 0.U + reg_mstatus.fs := 0.U + reg_mstatus.xs := 0.U + reg_mstatus.sd := 0.U } //MTVEC IS FIXED IN THIS IMPLEMENTATION @@ -455,12 +490,12 @@ class CSRRegFile extends Module{ when (decoded_addr(MCSRs.mip)) { val new_mip = wdata.asTypeOf(new MIx()) reg_mip.msix := new_mip.msix - reg_mip.seix := 0 - reg_mip.ueix := 0 - reg_mip.stix := 0 - reg_mip.utix := 0 - reg_mip.ssix := 0 - reg_mip.usix := 0 + reg_mip.seix := 0.U + reg_mip.ueix := 0.U + reg_mip.stix := 0.U + reg_mip.utix := 0.U + reg_mip.ssix := 0.U + reg_mip.usix := 0.U } //MIE @@ -472,12 +507,12 @@ class CSRRegFile extends Module{ reg_mie.meix := new_mie.meix reg_mie.msix := new_mie.msix reg_mie.mtix := new_mie.mtix - reg_mip.seix := 0 - reg_mip.ueix := 0 - reg_mip.stix := 0 - reg_mip.utix := 0 - reg_mip.ssix := 0 - reg_mip.usix := 0 + reg_mip.seix := 0.U + reg_mip.ueix := 0.U + reg_mip.stix := 0.U + reg_mip.utix := 0.U + reg_mip.ssix := 0.U + reg_mip.usix := 0.U } //MCOUNTEREB IS FIXED IN THIS IMPLEMENTATION BECAUSE NO S | U MODE @@ -489,10 +524,10 @@ class CSRRegFile extends Module{ when (decoded_addr(MCSRs.mcounterinhibit)) { val new_mcounterinhibit = wdata.asTypeOf(new XCounterEnInhibit()) reg_mcounterinhibit := new_mcounterinhibit - if( reg_mcounterinhibit.cy == false.B) { + when( reg_mcounterinhibit.cy === false.B) { writeCounter(MCSRs.mcycle, reg_time, wdata) } - if( reg_mcounterinhibit.ir == false.B){ + when( reg_mcounterinhibit.ir === false.B){ writeCounter(MCSRs.minstret, reg_instret, wdata) } } @@ -519,9 +554,40 @@ class CSRRegFile extends Module{ } def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { val hi = lo + MCSRs.mcycleh - MCSRs.mcycle - when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } - when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } + when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.value.getWidth-33, 0), ctr.value(31, 0)) } + when (decoded_addr(lo)) { ctr := Cat(ctr.value(ctr.value.getWidth-1, 32), wdata) } } + def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = -(Mux(cmd.isOneOf(MCSRCmd.set, MCSRCmd.clear), rdata, 0.U) | wdata) & ~Mux(cmd === MCSRCmd.clear, wdata, 0.U) +(Mux(Seq(MCSRCmd.set, MCSRCmd.clear).map(cmd === _).reduce(_||_), rdata, 0.U) | wdata) & ~Mux(cmd === MCSRCmd.clear, wdata, 0.U) +} + +case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true) +{ + private val isWide = width > 2*inc.getWidth + private val smallWidth = if (isWide) inc.getWidth max log2Ceil(width) else width + private val small = if (reset) RegInit(0.asUInt(smallWidth.W)) else Reg(UInt(smallWidth.W)) + private val nextSmall = small +& inc + small := nextSmall + + private val large = if (isWide) { + val r = if (reset) RegInit(0.asUInt((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W)) + when (nextSmall(smallWidth)) { r := r + 1.U } + r + } else null + + val value = if (isWide) Cat(large, small) else small + lazy val carryOut = { + val lo = (small ^ nextSmall) >> 1 + if (!isWide) lo else { + val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1 + Cat(hi, lo) + } + } + + def := (x: UInt) = { + small := x + if (isWide) large := x >> smallWidth + } } + diff --git a/src/main/scala/components/helpers.scala b/src/main/scala/components/helpers.scala index 053b46e5..1818febd 100644 --- a/src/main/scala/components/helpers.scala +++ b/src/main/scala/components/helpers.scala @@ -4,223 +4,6 @@ package dinocpu import chisel3._ import chisel3.util._ -import scala.math._ -import scala.collection.mutable.ArrayBuffer - -object Util -{ - implicit def intToUInt(x: Int): UInt = x.U - implicit def intToBoolean(x: Int): Boolean = if (x != 0) true else false - implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0 - implicit def booleanToBool(x: Boolean): Bool = x.B - implicit def sextToConv(x: UInt) = new AnyRef { - def sextTo(n: Int): UInt = Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) - } - - implicit def wcToUInt(c: WideCounter): UInt = c.value - implicit class UIntIsOneOf(val x: UInt) extends AnyVal { - def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).reduce(_||_) - - def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) - } - - implicit class UIntToAugmentedUInt(val x: UInt) extends AnyVal { - def sextTo(n: Int): UInt = { - require(x.getWidth <= n) - if (x.getWidth == n) x - else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) - } - - def padTo(n: Int): UInt = { - require(x.getWidth <= n) - if (x.getWidth == n) x - else Cat(0.U((n - x.getWidth).W), x) - } - - def extract(hi: Int, lo: Int): UInt = { - if (hi == lo-1) 0.U - else x(hi, lo) - } - - def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds - } -} - - -//do two masks have at least 1 bit match? -object maskMatch -{ - def apply(msk1: UInt, msk2: UInt): Bool = - { - val br_match = (msk1 & msk2) =/= 0.U - return br_match - } -} - -//clear one-bit in the Mask as specified by the idx -object clearMaskBit -{ - def apply(msk: UInt, idx: UInt): UInt = - { - return (msk & ~(1.U << idx))(msk.getWidth-1, 0) - } -} - -//shift a register over by one bit -object PerformShiftRegister -{ - def apply(reg_val: Bits, new_bit: Bool): Bits = - { - reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt(), new_bit.asUInt()).asUInt() - reg_val - } -} - -object Split -{ - // is there a better way to do do this? - def apply(x: Bits, n0: Int) = { - val w = checkWidth(x, n0) - (x(w-1,n0), x(n0-1,0)) - } - def apply(x: Bits, n1: Int, n0: Int) = { - val w = checkWidth(x, n1, n0) - (x(w-1,n1), x(n1-1,n0), x(n0-1,0)) - } - def apply(x: Bits, n2: Int, n1: Int, n0: Int) = { - val w = checkWidth(x, n2, n1, n0) - (x(w-1,n2), x(n2-1,n1), x(n1-1,n0), x(n0-1,0)) - } - - private def checkWidth(x: Bits, n: Int*) = { - val w = x.getWidth - def decreasing(x: Seq[Int]): Boolean = - if (x.tail.isEmpty) true - else x.head > x.tail.head && decreasing(x.tail) - require(decreasing(w :: n.toList)) - w - } -} - - -// a counter that clock gates most of its MSBs using the LSB carry-out -case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true) -{ - private val isWide = width > 2*inc.getWidth - private val smallWidth = if (isWide) inc.getWidth max log2Ceil(width) else width - private val small = if (reset) RegInit(0.asUInt(smallWidth.W)) else Reg(UInt(smallWidth.W)) - private val nextSmall = small +& inc - small := nextSmall - - private val large = if (isWide) { - val r = if (reset) RegInit(0.asUInt((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W)) - when (nextSmall(smallWidth)) { r := r + 1.U } - r - } else null - - val value = if (isWide) Cat(large, small) else small - lazy val carryOut = { - val lo = (small ^ nextSmall) >> 1 - if (!isWide) lo else { - val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1 - Cat(hi, lo) - } - } - - def := (x: UInt) = { - small := x - if (isWide) large := x >> smallWidth - } -} - -// taken from rocket FPU -object RegEn -{ - def apply[T <: Data](data: T, en: Bool) = - { - val r = Reg(data) - when (en) { r := data } - r - } - def apply[T <: Bits](data: T, en: Bool, resetVal: T) = - { - val r = RegInit(resetVal) - when (en) { r := data } - r - } -} - -object Str -{ - def apply(s: String): UInt = { - var i = BigInt(0) - require(s.forall(validChar _)) - for (c <- s) - i = (i << 8) | c - i.asUInt((s.length*8).W) - } - def apply(x: Char): Bits = { - require(validChar(x)) - val lit = x.asUInt(8.W) - lit - } - def apply(x: UInt): Bits = apply(x, 10) - def apply(x: UInt, radix: Int): Bits = { - val rad = radix.U - val digs = digits(radix) - val w = x.getWidth - require(w > 0) - - var q = x - var s = digs(q % rad) - for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { - q = q / rad - s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digs(q % rad)), s) - } - s - } - def apply(x: SInt): Bits = apply(x, 10) - def apply(x: SInt, radix: Int): Bits = { - val neg = x < 0.S - val abs = Mux(neg, -x, x).asUInt() - if (radix != 10) { - Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) - } else { - val rad = radix.U - val digs = digits(radix) - val w = abs.getWidth - require(w > 0) - - var q = abs - var s = digs(q % rad) - var needSign = neg - for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { - q = q / rad - val placeSpace = q === 0.U - val space = Mux(needSign, Str('-'), Str(' ')) - needSign = needSign && !placeSpace - s = Cat(Mux(placeSpace, space, digs(q % rad)), s) - } - Cat(Mux(needSign, Str('-'), Str(' ')), s) - } - } - - def bigIntToString(x: BigInt): String = { - val s = new StringBuilder - var b = x - while (b != 0) { - s += (x & 0xFF).toChar - b = b >> 8 - } - s.toString - } - - private def digit(d: Int): Char = (if (d < 10) '0'+d else 'a'-10+d).toChar - private def digits(radix: Int): Vec[Bits] = - VecInit((0 until radix).map(i => Str(digit(i)))) - - private def validChar(x: Char) = x == (x & 0xFF) -} /** * A simple adder which takes two inputs and returns the sum * From e987292146367160a64fd05fd74795bd4c2a0710 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 20:00:37 -0700 Subject: [PATCH 20/57] refactored csr to avoid using utils, restored helpers.scala --- src/main/scala/components/csr.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 7b5d0bde..9b6612cb 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -5,7 +5,6 @@ package dinocpu import chisel3._ import collection.mutable.LinkedHashMap import chisel3.util._ -//import Util._ import scala.math._ From 0cc9d93b7129b57076257aa5b477ca0879318a4b Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 20:05:41 -0700 Subject: [PATCH 21/57] refactored csr to avoid using utils, restored helpers.scala, added comments and removed some garbage code --- src/main/scala/components/csr.scala | 41 +++++------------------------ 1 file changed, 6 insertions(+), 35 deletions(-) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 9b6612cb..0dd388ed 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -26,41 +26,6 @@ object MCauses { val machine_ecall = "hb".U } -/* -object MCSRs { - //machine information registers - val mvendorid = "hf11".U //vendor id - val marchid = "hf12".U //architecture id - val mimpid = "hf13".U //implementation id - val mhartid = "hf14".U //hardware thread id - //machine trap setup - val mstatus = "h300".U //machine status reg - val misa = "h301".U //isa and extensions - val medeleg = "h302".U //machine exception delegation reg - val mideleg = "h303".U //machine interrupt delegation reg - val mie = "h304".U //machine iterrupt-enable reg - val mtvec = "h305".U //machine trap handler base address - val mcounteren = "h306".U //machine counter enable - - //machine trap handling - val mscratch = "h340".U //scratch reg for machine trap handlers - val mepc = "h341".U //machine exception program counter - val mcause = "h342".U //machine trap cause - val mtval = "h343".U //machine bad address or instruction - val mip = "h344".U //machine interrupt pending - - //machine memory protection - //DONT NEED - - //machine counter/timers - val mcycle = "hb00".U //machine cycle counter - val minstret = "hb02".U //machine instructions retured counter - val mcycleh = "hb80".U - val minstreth = "hb82".U - //performance counter setup - val mcounterinhibit = "h320".U -} -*/ object MCSRs { //machine information registers val mvendorid = 0xf11 //vendor id @@ -551,16 +516,22 @@ class CSRRegFile extends Module{ when (decoded_addr(MCSRs.mtval)) { reg_mtval := wdata(32-1,0) } when (decoded_addr(MCSRs.medeleg)) { reg_medeleg := wdata(32-1,0) } } + + //takes counter data and data to write and modifies it 32 bits at a time def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { val hi = lo + MCSRs.mcycleh - MCSRs.mcycle when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.value.getWidth-33, 0), ctr.value(31, 0)) } when (decoded_addr(lo)) { ctr := Cat(ctr.value(ctr.value.getWidth-1, 32), wdata) } } + //takes in csr command and sees if it maps to any int the defined sequence and determines + //resulting csr data with bitwise operations def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = (Mux(Seq(MCSRCmd.set, MCSRCmd.clear).map(cmd === _).reduce(_||_), rdata, 0.U) | wdata) & ~Mux(cmd === MCSRCmd.clear, wdata, 0.U) } +//used for timers and performance counters. case class lets us use comparison +//operators on the content of the object rather than the reference to the object case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true) { private val isWide = width > 2*inc.getWidth From 336d7f3ad8bd4268fe3337e9bcaa121e1e9accf6 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 20:10:33 -0700 Subject: [PATCH 22/57] Removed CSR stuff for time being until we find a good way of testing it --- src/main/scala/testing/CPUTesterDriver.scala | 30 +----- src/main/scala/testing/InstTests.scala | 100 +------------------ 2 files changed, 4 insertions(+), 126 deletions(-) diff --git a/src/main/scala/testing/CPUTesterDriver.scala b/src/main/scala/testing/CPUTesterDriver.scala index b3e1efbe..858955ad 100644 --- a/src/main/scala/testing/CPUTesterDriver.scala +++ b/src/main/scala/testing/CPUTesterDriver.scala @@ -59,12 +59,6 @@ class CPUTesterDriver(cpuType: String, simulator.reset(5) } - def initCSR(vals: Map[Int, BigInt]) { - for ((num, value) <- vals) { - simulator.poke(s"cpu.csr.read_mapping_$num", value) - } - } - def initRegs(vals: Map[Int, BigInt]) { for ((num, value) <- vals) { simulator.poke(s"cpu.registers.regs_$num", value) @@ -81,22 +75,6 @@ class CPUTesterDriver(cpuType: String, } } - def checkCSR(vals: Map[Int, BigInt]): Boolean = { - var success = true - for ((num, value) <- vals) { - try { - simulator.expect(s"cpu.csr.read_mapping_$num", value) - } catch { - case _: TreadleException => { - success = false - val real = simulator.peek(s"cpu.csr.read_mapping_$num") - println(s"CSR $num failed to match. Was $real. Should be $value") - } - } - } - success - } - def checkRegs(vals: Map[Int, BigInt]): Boolean = { var success = true for ((num, value) <- vals) { @@ -150,8 +128,6 @@ class CPUTesterDriver(cpuType: String, case class CPUTestCase( binary: String, cycles: Map[String, Int], - initCSR: Map[Int, BigInt], - checkCSR: Map[Int, BigInt], initRegs: Map[Int, BigInt], checkRegs: Map[Int, BigInt], initMem: Map[Int, BigInt], @@ -167,11 +143,9 @@ case class CPUTestCase( object CPUTesterDriver { def apply(testCase: CPUTestCase, cpuType: String, branchPredictor: String = ""): Boolean = { val driver = new CPUTesterDriver(cpuType, branchPredictor, testCase.binary, testCase.extraName) - driver.initCSR(testCase.initCSR) - driver.initRegs(testCase.initRegs) driver.initMemory(testCase.initMem) driver.run(testCase.cycles(cpuType)) - val success = driver.checkCSR(testCase.checkCSR) - success && driver.checkRegs(testCase.checkRegs) && driver.checkMemory(testCase.checkMem) + val success = driver.checkRegs(testCase.checkRegs) + success && driver.checkMemory(testCase.checkMem) } } diff --git a/src/main/scala/testing/InstTests.scala b/src/main/scala/testing/InstTests.scala index 71f077b7..a3f818fb 100644 --- a/src/main/scala/testing/InstTests.scala +++ b/src/main/scala/testing/InstTests.scala @@ -9,8 +9,6 @@ package dinocpu * Each test case looks like: * - binary to run in src/test/resources/risc-v * - number of cycles to run for each CPU type - * - initial values for csr registers - * - final values to check for csr registers * - initial values for registers * - final values to check for registers * - initial values for memory @@ -32,85 +30,71 @@ object InstTests { val rtype = List[CPUTestCase]( CPUTestCase("add1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), CPUTestCase("add2", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1234, 20 -> 5678), Map(0 -> 0, 10 -> 6912), Map(), Map()), CPUTestCase("add0", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1234, 6 -> 3456), Map(0 -> 0, 5 -> 1234, 6 -> 3456), Map(), Map()), CPUTestCase("or", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1234, 6 -> 5678), Map(7 -> 5886), Map(), Map()), CPUTestCase("sub", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1234, 6 -> 5678), Map(7 -> BigInt("FFFFEEA4", 16)), Map(), Map()), CPUTestCase("and", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1234, 6 -> 5678), Map(7 -> 1026), Map(), Map()), CPUTestCase("xor", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> 1234, 5 -> 5678), Map(5 -> 5678, 7 -> 1234, 6 -> 4860), Map(), Map()), CPUTestCase("slt", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> 1234, 5 -> 5678), Map(5 -> 5678, 7 -> 1234, 6 -> 1), Map(), Map()), CPUTestCase("slt1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> -1, 5 -> 1), Map(5 -> 1, 6 -> 1), Map(), Map()), CPUTestCase("sltu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> -1, 5 -> 1), Map(5 -> 1, 6 -> 0), Map(), Map()), CPUTestCase("sltu1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> 20, 5 -> 100), Map(5 -> 100, 6 -> 1), Map(), Map()), CPUTestCase("sll", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> 32, 5 -> 2), Map(7 -> 32, 5 -> 2, 6 -> 128), Map(), Map()), CPUTestCase("srl", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> 32, 5 -> 2), Map(7 -> 32, 5 -> 2, 6 -> 8), Map(), Map()), CPUTestCase("sra", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> twoscomp(-2), 5 -> 31), Map(5 -> 31, 6 -> twoscomp(-1)), Map(), Map()) @@ -119,49 +103,41 @@ object InstTests { val rtypeMultiCycle = List[CPUTestCase]( CPUTestCase("addfwd", Map("single-cycle" -> 10, "pipelined" -> 14), - Map(), Map(), Map(5 -> 1, 10 -> 0), Map(5 -> 1, 10 -> 10), Map(), Map()), CPUTestCase("swapxor", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map(), Map(7 -> 5678, 5 -> 1234), Map(5 -> 5678,7->1234), Map(), Map()), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map(), Map(5 -> 512, 6->1), Map(7->1), Map(), Map(), "-512"), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map(), Map(5 -> 1234, 6->1), Map(7->0), Map(), Map(), "-1234"), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map(), Map(5 -> twoscomp(-65536), 6->1), Map(7->0), // This algorithm doesn't work for negative numbers Map(), Map(), "--65536"), CPUTestCase("oppsign", Map("single-cycle" -> 2, "pipelined" -> 7), - Map(), Map(), Map(5 -> 512, 6->twoscomp(-1024),7->0), Map(7->1), Map(), Map(), "-true"), CPUTestCase("oppsign", Map("single-cycle" -> 2, "pipelined" -> 7), - Map(), Map(), Map(5 -> 512, 6->1024,7->0), Map(7->0), Map(), Map(), "-false"), CPUTestCase("rotR", Map("single-cycle" -> 4, "pipelined" -> 8), - Map(), Map(), Map(5 -> twoscomp(-1), 6->1, 7->32), Map(7->twoscomp(-1)), Map(), Map()) @@ -170,61 +146,51 @@ object InstTests { val itype = List[CPUTestCase]( CPUTestCase("addi1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(0 -> 0, 10 -> 17), Map(), Map()), CPUTestCase("slli", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1), Map(0 -> 0, 5 -> 1, 6 -> 128), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1024), Map(0 -> 0, 5 -> 1024, 6 -> 8), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> twoscomp(-1024)), Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), Map(), Map(), "-negative"), CPUTestCase("srli", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 128), Map(0 -> 0, 5 -> 128, 6 -> 1), Map(), Map()), CPUTestCase("andi", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 200), Map(), Map()), CPUTestCase("ori", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 511), Map(), Map()), CPUTestCase("xori", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 311), Map(), Map()), CPUTestCase("slti", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1),6->1), Map(), Map()), CPUTestCase("sltiu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), Map(), Map()) @@ -233,7 +199,6 @@ object InstTests { val itypeMultiCycle = List[CPUTestCase]( CPUTestCase("addi2", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map(), Map(), Map(0 -> 0, 10 -> 17, 11 -> 93), Map(), Map()) @@ -242,109 +207,91 @@ object InstTests { val branch = List[CPUTestCase]( CPUTestCase("beq", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-False"), CPUTestCase("beq", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-True"), CPUTestCase("bne", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("bne", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-True"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-False-equal"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-True"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), Map(), Map(), "-False-signed"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), Map(), Map(), "-True-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-False"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(), Map(), "-True"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), Map(), Map(), "-False-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), Map(), Map(), "-True-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-True-equal"), CPUTestCase("bltu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("bltu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(), Map(), "-True"), CPUTestCase("bgeu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(), Map(), "-False"), CPUTestCase("bgeu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(), Map(), "-True") @@ -366,61 +313,51 @@ object InstTests { val memory = List[CPUTestCase]( CPUTestCase("lw1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(5 -> BigInt("ffffffff", 16)), Map(), Map()), CPUTestCase("lb", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(5 -> BigInt("04", 16)), Map(), Map()), CPUTestCase("lh", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(5 -> BigInt("0304", 16)), Map(), Map()), CPUTestCase("lbu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(5 -> BigInt("f4", 16)), Map(), Map()), CPUTestCase("lhu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(5 -> BigInt("f3f4", 16)), Map(), Map()), CPUTestCase("lb1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(5 -> BigInt("fffffff4", 16)), Map(), Map()), CPUTestCase("lh1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(5 -> BigInt("fffff3f4", 16)), Map(), Map()), CPUTestCase("sw", Map("single-cycle" -> 6, "pipelined" -> 10), - Map(), Map(), Map(5 -> 1234), Map(6 -> 1234), Map(), Map(0x100 -> 1234)), CPUTestCase("sb", Map("single-cycle" -> 6, "pipelined" -> 10), - Map(), Map(), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffffff01", 16))), CPUTestCase("sh", Map("single-cycle" -> 6, "pipelined" -> 10), - Map(), Map(), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffff0001", 16))) @@ -429,7 +366,6 @@ object InstTests { val memoryMultiCycle = List[CPUTestCase]( CPUTestCase("lwfwd", Map("single-cycle" -> 2, "pipelined" -> 7), - Map(), Map(), Map(5 -> BigInt("ffffffff", 16), 10 -> 5), Map(5 -> 1, 10 -> 6), Map(), Map()), @@ -448,37 +384,31 @@ object InstTests { val utype = List[CPUTestCase]( CPUTestCase("auipc0", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc2", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map(), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc1", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map(), Map(10 -> 1234), Map(10 -> (17 << 12)), Map(), Map()), CPUTestCase("auipc3", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map(), Map(10 -> 1234), Map(10 -> 4), Map(), Map()), CPUTestCase("lui0", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()), CPUTestCase("lui1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(10 -> 1234), Map(10 -> 4096), Map(), Map()) @@ -487,13 +417,11 @@ object InstTests { val utypeMultiCycle = List[CPUTestCase]( CPUTestCase("auipc1", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map(), Map(10 -> 1234), Map(10 -> 4), Map(), Map()), CPUTestCase("auipc3", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map(), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()) @@ -502,19 +430,16 @@ object InstTests { val jump = List[CPUTestCase]( CPUTestCase("jal", Map("single-cycle" -> 2, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr0", Map("single-cycle" -> 2, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 10 -> 28), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr1", Map("single-cycle" -> 2, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 10 -> 20), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -523,56 +448,46 @@ object InstTests { val csr = List[CPUTestCase]( CPUTestCase("csrrc", Map("single-cycle" -> 1, "pipelined" -> 5), - Map( 0x300 -> 0x1888 ), - Map( 0x300 -> 0xffffe777 ), - Map( 6 -> 0xfffffffb), - Map( 6 -> 0xfffffffb), + Map(), + Map(), Map(), Map()), CPUTestCase("csrrci", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()), CPUTestCase("csrrs", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()), CPUTestCase("csrrsi", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()), CPUTestCase("csrrw", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()), CPUTestCase("csrrwi", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()), CPUTestCase("ecall", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()), CPUTestCase("ebreak", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()), CPUTestCase("mret", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()) @@ -582,25 +497,21 @@ object InstTests { val smallApplications = List[CPUTestCase]( CPUTestCase("fibonacci", Map("single-cycle" -> 300, "pipelined" -> 1000), - Map(), Map(), Map(6->11), Map(6->11,5->89), Map(), Map()), CPUTestCase("naturalsum", Map("single-cycle" -> 200, "pipelined" -> 500), - Map(), Map(), Map(), Map(5->55), Map(), Map()), CPUTestCase("multiplier", Map("single-cycle" -> 1000, "pipelined" -> 1000), - Map(), Map(), Map(5->23,6->20,8->0x1000), Map(5->23*20), Map(), Map()), CPUTestCase("divider", Map("single-cycle" -> 1000, "pipelined" -> 2000), - Map(), Map(), Map(5->1260,6->30), Map(7->42), Map(), Map()) @@ -609,37 +520,31 @@ object InstTests { val fullApplications = List[CPUTestCase]( CPUTestCase("multiply.riscv", Map("single-cycle" -> 42342, "pipelined" -> 100000), - Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("median.riscv", Map("single-cycle" -> 9433, "pipelined" -> 100000), - Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("qsort.riscv", Map("single-cycle" -> 263290, "pipelined" -> 300000), - Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("rsort.riscv", Map("single-cycle" -> 263290, "pipelined" -> 250000), - Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("towers.riscv", Map("single-cycle" -> 12653, "pipelined" -> 100000), - Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("vvadd.riscv", Map("single-cycle" -> 5484, "pipelined" -> 20000), - Map(), Map(), Map(), Map(10->12345678), Map(), Map()) @@ -663,7 +568,6 @@ object InstTests { ) // All of the tests -<<<<<<< HEAD val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ branchMultiCycle ++ memory ++ memoryMultiCycle ++ utype ++ utypeMultiCycle ++ jump ++ csr ++ smallApplications From a6e1b2a375d787229707ec62aa3daf12395f33ad Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 20:15:09 -0700 Subject: [PATCH 23/57] removed csr from grading tests --- src/test/scala/grading/Lab1Tests.scala | 2 -- src/test/scala/grading/Lab2Tests.scala | 2 -- 2 files changed, 4 deletions(-) diff --git a/src/test/scala/grading/Lab1Tests.scala b/src/test/scala/grading/Lab1Tests.scala index b013ae42..b18fb5ec 100644 --- a/src/test/scala/grading/Lab1Tests.scala +++ b/src/test/scala/grading/Lab1Tests.scala @@ -41,7 +41,6 @@ class Lab1Grader extends JUnitSuite { var success = CPUTesterDriver(CPUTestCase("add1", Map("single-cycle" -> 1), - Map(), Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), @@ -49,7 +48,6 @@ class Lab1Grader extends JUnitSuite { success = CPUTesterDriver(CPUTestCase("add2", Map("single-cycle" -> 1), - Map(), Map(), Map(5 -> 1234, 20 -> 5678), Map(0 -> 0, 10 -> 6912), Map(), Map()), diff --git a/src/test/scala/grading/Lab2Tests.scala b/src/test/scala/grading/Lab2Tests.scala index d4d02b38..e14d3d18 100644 --- a/src/test/scala/grading/Lab2Tests.scala +++ b/src/test/scala/grading/Lab2Tests.scala @@ -93,8 +93,6 @@ class Lab2Grader extends JUnitSuite { Map(), Map()), CPUTestCase("ori", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 511), Map(), Map()), From 9508e1d1062fe2530fc3537825292936e29b8c1d Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 20:29:28 -0700 Subject: [PATCH 24/57] corrected a missing line in CPUTesterDriver --- src/main/scala/testing/CPUTesterDriver.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/testing/CPUTesterDriver.scala b/src/main/scala/testing/CPUTesterDriver.scala index 858955ad..05338665 100644 --- a/src/main/scala/testing/CPUTesterDriver.scala +++ b/src/main/scala/testing/CPUTesterDriver.scala @@ -143,6 +143,7 @@ case class CPUTestCase( object CPUTesterDriver { def apply(testCase: CPUTestCase, cpuType: String, branchPredictor: String = ""): Boolean = { val driver = new CPUTesterDriver(cpuType, branchPredictor, testCase.binary, testCase.extraName) + driver.initRegs(testCase.initRegs) driver.initMemory(testCase.initMem) driver.run(testCase.cycles(cpuType)) val success = driver.checkRegs(testCase.checkRegs) From 1b6a6451884b3e6b1b2e76b9321c5064d7230029 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 21:20:36 -0700 Subject: [PATCH 25/57] fixed some tests failing --- src/main/scala/components/helpers.scala | 1 + src/main/scala/testing/InstTests.scala | 64 +--------------------- src/test/scala/grading/Lab2Tests.scala | 72 ++++++++++++------------- 3 files changed, 39 insertions(+), 98 deletions(-) diff --git a/src/main/scala/components/helpers.scala b/src/main/scala/components/helpers.scala index 1818febd..d0bbcd9d 100644 --- a/src/main/scala/components/helpers.scala +++ b/src/main/scala/components/helpers.scala @@ -4,6 +4,7 @@ package dinocpu import chisel3._ import chisel3.util._ + /** * A simple adder which takes two inputs and returns the sum * diff --git a/src/main/scala/testing/InstTests.scala b/src/main/scala/testing/InstTests.scala index a3f818fb..b265a169 100644 --- a/src/main/scala/testing/InstTests.scala +++ b/src/main/scala/testing/InstTests.scala @@ -389,23 +389,13 @@ object InstTests { Map(), Map()), CPUTestCase("auipc2", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(10 -> 1234), - Map(10 -> 0), - Map(), Map()), - CPUTestCase("auipc1", - Map("single-cycle" -> 2, "pipelined" -> 6), Map(10 -> 1234), Map(10 -> (17 << 12)), Map(), Map()), - CPUTestCase("auipc3", - Map("single-cycle" -> 2, "pipelined" -> 6), - Map(10 -> 1234), - Map(10 -> 4), - Map(), Map()), CPUTestCase("lui0", Map("single-cycle" -> 1, "pipelined" -> 5), Map(10 -> 1234), - Map(10 -> ((17 << 12) + 4)), + Map(10 -> 0), Map(), Map()), CPUTestCase("lui1", Map("single-cycle" -> 1, "pipelined" -> 5), @@ -443,55 +433,6 @@ object InstTests { Map(5 -> 1234, 10 -> 20), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) - ) - - val csr = List[CPUTestCase]( - CPUTestCase("csrrc", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrci", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrs", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrsi", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrw", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrwi", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("ecall", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("ebreak", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("mret", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()) - ) val smallApplications = List[CPUTestCase]( @@ -563,13 +504,12 @@ object InstTests { "utype" -> utype, "utypeMultiCycle" -> utypeMultiCycle, "jump" -> jump, - "csr" -> csr, "smallApplications" -> smallApplications ) // All of the tests val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ branchMultiCycle ++ - memory ++ memoryMultiCycle ++ utype ++ utypeMultiCycle ++ jump ++ csr ++ smallApplications + memory ++ memoryMultiCycle ++ utype ++ utypeMultiCycle ++ jump ++ smallApplications // Mapping from full name of test to test val nameMap = (allTests ++ fullApplications).map(x => x.name() -> x).toMap diff --git a/src/test/scala/grading/Lab2Tests.scala b/src/test/scala/grading/Lab2Tests.scala index e14d3d18..eb3a701a 100644 --- a/src/test/scala/grading/Lab2Tests.scala +++ b/src/test/scala/grading/Lab2Tests.scala @@ -57,57 +57,57 @@ class Lab2Grader extends JUnitSuite { Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), CPUTestCase("addi1", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(0 -> 0, 10 -> 17), Map(), Map()), CPUTestCase("addi2", - Map("single-cycle" -> 2, "pipelined" -> 6), + Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 6), Map(), Map(0 -> 0, 10 -> 17, 11 -> 93), Map(), Map()), CPUTestCase("slli", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> 1), Map(0 -> 0, 5 -> 1, 6 -> 128), Map(), Map()), CPUTestCase("srai", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> 1024), Map(0 -> 0, 5 -> 1024, 6 -> 8), Map(), Map()), CPUTestCase("srai", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> twoscomp(-1024)), Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), Map(), Map(), "-negative"), CPUTestCase("srli", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> 128), Map(0 -> 0, 5 -> 128, 6 -> 1), Map(), Map()), CPUTestCase("andi", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 200), Map(), Map()), CPUTestCase("ori", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 511), Map(), Map()), CPUTestCase("xori", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 311), Map(), Map()), CPUTestCase("slti", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1),6->1), Map(), Map()), CPUTestCase("sltiu", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), Map(), Map()) @@ -141,12 +141,12 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("lw1", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(5 -> BigInt("ffffffff", 16)), Map(), Map()), CPUTestCase("lwfwd", - Map("single-cycle" -> 2, "pipelined" -> 7), + Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), Map(5 -> BigInt("ffffffff", 16), 10 -> 5), Map(5 -> 1, 10 -> 6), Map(), Map()) @@ -178,32 +178,32 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("auipc0", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc1", - Map("single-cycle" -> 2, "pipelined" -> 6), + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), Map(10 -> 1234), Map(10 -> 4), Map(), Map()), CPUTestCase("auipc2", - Map("single-cycle" -> 2, "pipelined" -> 6), + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), Map(10 -> 1234), Map(10 -> (17 << 12)), Map(), Map()), CPUTestCase("auipc3", - Map("single-cycle" -> 2, "pipelined" -> 6), + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()), CPUTestCase("lui0", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("lui1", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(10 -> 1234), Map(10 -> 4096), Map(), Map()) @@ -238,7 +238,7 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("sw", - Map("single-cycle" -> 6, "pipelined" -> 10), + Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), Map(5 -> 1234), Map(6 -> 1234), Map(), Map(0x100 -> 1234)) @@ -270,42 +270,42 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("lb", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(5 -> BigInt("04", 16)), Map(), Map()), CPUTestCase("lh", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(5 -> BigInt("0304", 16)), Map(), Map()), CPUTestCase("lbu", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(5 -> BigInt("f4", 16)), Map(), Map()), CPUTestCase("lhu", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(5 -> BigInt("f3f4", 16)), Map(), Map()), CPUTestCase("lb1", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(5 -> BigInt("fffffff4", 16)), Map(), Map()), CPUTestCase("lh1", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(5 -> BigInt("fffff3f4", 16)), Map(), Map()), CPUTestCase("sb", - Map("single-cycle" -> 6, "pipelined" -> 10), + Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffffff01", 16))), CPUTestCase("sh", - Map("single-cycle" -> 6, "pipelined" -> 10), + Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffff0001", 16))) @@ -363,7 +363,7 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("jal", - Map("single-cycle" -> 2, "pipelined" -> 6), + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -398,12 +398,12 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("jalr0", - Map("single-cycle" -> 2, "pipelined" -> 6), + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), Map(5 -> 1234, 10 -> 28), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr1", - Map("single-cycle" -> 2, "pipelined" -> 6), + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), Map(5 -> 1234, 10 -> 20), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -439,22 +439,22 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("fibonacci", - Map("single-cycle" -> 300, "pipelined" -> 6), + Map("single-cycle" -> 300, "five-cycle" -> 6, "pipelined" -> 6), Map(6->11), Map(6->11,5->89), Map(), Map()), CPUTestCase("naturalsum", - Map("single-cycle" -> 200, "pipelined" -> 6), + Map("single-cycle" -> 200, "five-cycle" -> 6, "pipelined" -> 6), Map(), Map(5->55), Map(), Map()), CPUTestCase("multiplier", - Map("single-cycle" -> 1000, "pipelined" -> 6), - Map(5->23,6->20), + Map("single-cycle" -> 1000, "five-cycle" -> 6, "pipelined" -> 6), + Map(5->23,6->20), Map(5->23*20), Map(), Map()), CPUTestCase("divider", - Map("single-cycle" -> 1000, "pipelined" -> 6), + Map("single-cycle" -> 1000, "five-cycle" -> 6, "pipelined" -> 6), Map(5->1260,6->30), Map(7->42), Map(), Map()) From 381b251c30db2870b4d91ad80b2270687dbd2266 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Thu, 16 May 2019 14:52:45 -0700 Subject: [PATCH 26/57] added comment to credit rocket chip for some implementation details --- src/main/scala/components/csr.scala | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 0dd388ed..798f0f0f 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -1,3 +1,7 @@ +/* The following code is based on https://github.com/freechipsproject/rocket-chip + * implementation of the csr unit + */ + /* Describes register file that maintains machine state */ package dinocpu From 4ad7ac5470e77d22ac0e9cd4a3f6721e2a4a8855 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 1 May 2019 20:23:38 -0700 Subject: [PATCH 27/57] csr unit class created --- Top.DualPortedMemory.memory.v | 20 + firrtl_black_box_resource_files.f | 1 + src/main/scala/components/control.scala | 44 +- src/main/scala/components/csr.scala | 506 ++++ src/main/scala/components/helpers.scala | 216 ++ src/main/scala/single-cycle/cpu.scala | 22 +- src/main/scala/testing/CPUTesterDriver.scala | 29 +- src/main/scala/testing/InstTests.scala | 143 ++ src/test/resources/risc-v/sw | Bin 5620 -> 5812 bytes src/test/resources/risc-v/sw.riscv | 1 + src/verilog/Top.DualPortedMemory.memory.v | 20 + src/verilog/obj_dir/VTop | Bin 0 -> 219584 bytes src/verilog/obj_dir/VTop.cpp | 2181 ++++++++++++++++++ src/verilog/obj_dir/VTop.h | 136 ++ src/verilog/obj_dir/VTop.mk | 66 + src/verilog/obj_dir/VTop__ALLcls.cpp | 3 + src/verilog/obj_dir/VTop__ALLcls.d | 5 + src/verilog/obj_dir/VTop__ALLsup.cpp | 3 + src/verilog/obj_dir/VTop__ALLsup.d | 5 + src/verilog/obj_dir/VTop__Syms.cpp | 21 + src/verilog/obj_dir/VTop__Syms.h | 37 + src/verilog/obj_dir/VTop__ver.d | 1 + src/verilog/obj_dir/VTop__verFiles.dat | 12 + src/verilog/obj_dir/VTop_classes.mk | 38 + src/verilog/obj_dir/testbench.d | 6 + src/verilog/obj_dir/verilated.d | 7 + src/verilog/testbench.cpp | 33 + 27 files changed, 3533 insertions(+), 23 deletions(-) create mode 100644 Top.DualPortedMemory.memory.v create mode 100644 firrtl_black_box_resource_files.f create mode 100644 src/main/scala/components/csr.scala create mode 100644 src/verilog/Top.DualPortedMemory.memory.v create mode 100755 src/verilog/obj_dir/VTop create mode 100644 src/verilog/obj_dir/VTop.cpp create mode 100644 src/verilog/obj_dir/VTop.h create mode 100644 src/verilog/obj_dir/VTop.mk create mode 100644 src/verilog/obj_dir/VTop__ALLcls.cpp create mode 100644 src/verilog/obj_dir/VTop__ALLcls.d create mode 100644 src/verilog/obj_dir/VTop__ALLsup.cpp create mode 100644 src/verilog/obj_dir/VTop__ALLsup.d create mode 100644 src/verilog/obj_dir/VTop__Syms.cpp create mode 100644 src/verilog/obj_dir/VTop__Syms.h create mode 100644 src/verilog/obj_dir/VTop__ver.d create mode 100644 src/verilog/obj_dir/VTop__verFiles.dat create mode 100644 src/verilog/obj_dir/VTop_classes.mk create mode 100644 src/verilog/obj_dir/testbench.d create mode 100644 src/verilog/obj_dir/verilated.d create mode 100644 src/verilog/testbench.cpp diff --git a/Top.DualPortedMemory.memory.v b/Top.DualPortedMemory.memory.v new file mode 100644 index 00000000..a41466f6 --- /dev/null +++ b/Top.DualPortedMemory.memory.v @@ -0,0 +1,20 @@ +module BindsTo_0_DualPortedMemory( + input clock, + input reset, + input [31:0] io_imem_address, + output [31:0] io_imem_instruction, + input [31:0] io_dmem_address, + input [31:0] io_dmem_writedata, + input io_dmem_memread, + input io_dmem_memwrite, + input [1:0] io_dmem_maskmode, + input io_dmem_sext, + output [31:0] io_dmem_readdata +); + +initial begin + $readmemh("test", DualPortedMemory.memory); +end + endmodule + +bind DualPortedMemory BindsTo_0_DualPortedMemory BindsTo_0_DualPortedMemory_Inst(.*); \ No newline at end of file diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f new file mode 100644 index 00000000..900ea4d4 --- /dev/null +++ b/firrtl_black_box_resource_files.f @@ -0,0 +1 @@ +/riscv/Top.DualPortedMemory.memory.v \ No newline at end of file diff --git a/src/main/scala/components/control.scala b/src/main/scala/components/control.scala index 3f589a74..d41bffab 100644 --- a/src/main/scala/components/control.scala +++ b/src/main/scala/components/control.scala @@ -26,6 +26,7 @@ class Control extends Module { val io = IO(new Bundle { val opcode = Input(UInt(7.W)) + val validinst = Output(Bool()) val branch = Output(Bool()) val memread = Output(Bool()) val toreg = Output(UInt(2.W)) @@ -39,36 +40,39 @@ class Control extends Module { val signals = ListLookup(io.opcode, - /*default*/ List(false.B, false.B, 3.U, false.B, false.B, false.B, false.B, 0.U, 0.U), - Array( /* branch, memread, toreg, add, memwrite, immediate, regwrite, alusrc1, jump */ + /*default*/ List(false.B, false.B, false.B, 4.U, false.B, false.B, false.B, false.B, 0.U, 0.U), + Array( /* valid instr, branch, memread, toreg, add, memwrite, immediate, regwrite, alusrc1, jump */ // R-format - BitPat("b0110011") -> List(false.B, false.B, 0.U, false.B, false.B, false.B, true.B, 0.U, 0.U), + BitPat("b0110011") -> List(true.B, false.B, false.B, 0.U, false.B, false.B, false.B, true.B, 0.U, 0.U), // I-format - BitPat("b0010011") -> List(false.B, false.B, 0.U, false.B, false.B, true.B, true.B, 0.U, 0.U), + BitPat("b0010011") -> List(true.B, false.B, false.B, 0.U, false.B, false.B, true.B, true.B, 0.U, 0.U), // load - BitPat("b0000011") -> List(false.B, true.B, 1.U, true.B, false.B, true.B, true.B, 0.U, 0.U), + BitPat("b0000011") -> List(true.B, false.B, true.B, 1.U, true.B, false.B, true.B, true.B, 0.U, 0.U), // store - BitPat("b0100011") -> List(false.B, false.B, 0.U, true.B, true.B, true.B, false.B, 0.U, 0.U), + BitPat("b0100011") -> List(true.B, false.B, false.B, 0.U, true.B, true.B, true.B, false.B, 0.U, 0.U), // beq - BitPat("b1100011") -> List(true.B, false.B, 0.U, false.B, false.B, false.B, false.B, 0.U, 0.U), + BitPat("b1100011") -> List(true.B, true.B, false.B, 0.U, false.B, false.B, false.B, false.B, 0.U, 0.U), // lui - BitPat("b0110111") -> List(false.B, false.B, 0.U, true.B, false.B, true.B, true.B, 1.U, 0.U), + BitPat("b0110111") -> List(true.B, false.B, false.B, 0.U, true.B, false.B, true.B, true.B, 1.U, 0.U), // auipc - BitPat("b0010111") -> List(false.B, false.B, 0.U, true.B, false.B, true.B, true.B, 2.U, 0.U), + BitPat("b0010111") -> List(true.B, false.B, false.B, 0.U, true.B, false.B, true.B, true.B, 2.U, 0.U), // jal - BitPat("b1101111") -> List(false.B, false.B, 2.U, false.B, false.B, false.B, true.B, 1.U, 2.U), + BitPat("b1101111") -> List(true.B, false.B, false.B, 2.U, false.B, false.B, false.B, true.B, 1.U, 2.U), // jalr - BitPat("b1100111") -> List(false.B, false.B, 2.U, false.B, false.B, true.B, true.B, 0.U, 3.U) + BitPat("b1100111") -> List(true.B, false.B, false.B, 2.U, false.B, false.B, true.B, true.B, 0.U, 3.U), + //csr + BitPat("b1110011") -> List(true.B, false.B, false.B, 3.U, false.B, false.B, false.B, false.B, 0.U, 0.U) ) // Array ) // ListLookup - io.branch := signals(0) - io.memread := signals(1) - io.toreg := signals(2) - io.add := signals(3) - io.memwrite := signals(4) - io.immediate := signals(5) - io.regwrite := signals(6) - io.alusrc1 := signals(7) - io.jump := signals(8) + io.validinst := signals(0) + io.branch := signals(1) + io.memread := signals(2) + io.toreg := signals(3) + io.add := signals(4) + io.memwrite := signals(5) + io.immediate := signals(6) + io.regwrite := signals(7) + io.alusrc1 := signals(8) + io.jump := signals(9) } diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala new file mode 100644 index 00000000..a353d112 --- /dev/null +++ b/src/main/scala/components/csr.scala @@ -0,0 +1,506 @@ +/* Describes register file that maintains machine state */ + +package dinocpu + +import chisel3._ +import collection.mutable.LinkedHashMap +import chisel3.util._ +import chisel3.util.BitPat +import chisel3.util.experimental.BoringUtils +import Util._ + +import scala.math._ + +object MCauses { + //with interrupt + val machine_soft_int = 0x80000003 + val machine_timer_int = 0x80000007 + val machine_ext_int = 0x8000000b + + //non interrupt + val misaligned_fetch = 0x0 + val fetch_access = 0x1 + val illegal_instruction = 0x2 + val breakpoint = 0x3 + val misaligned_load = 0x4 + val load_access = 0x5 + val misaligned_store = 0x6 + val store_access = 0x7 + val machine_ecall = 0xb + val all = { + val res = collection.mutable.ArrayBuffer[Int]() + res += machine_soft_int + res += machine_timer_int + res += machine_ext_int + + res += misaligned_fetch + res += fetch_access + res += illegal_instruction + res += breakpoint + res += misaligned_load + res += load_access + res += misaligned_store + res += store_access + res += machine_ecall + res.toArray + } +} + +object MCSRs { + //machine information registers + val mvendorid = 0xf11 //vendor id + val marchid = 0xf12 //architecture id + val mimpid = 0xf13 //implementation id + val mhartid = 0xf14 //hardware thread id + //machine trap setup + val mstatus = 0x300 //machine status reg + val misa = 0x301 //isa and extensions + val medeleg = 0x302 //machine exception delegation reg + val mideleg = 0x303 //machine interrupt delegation reg + val mie = 0x304 //machine iterrupt-enable reg + val mtvec = 0x305 //machine trap handler base address + val mcounteren = 0x306 //machine counter enable + + //machine trap handling + val mscratch = 0x340 //scratch reg for machine trap handlers + val mepc = 0x341 //machine exception program counter + val mcause = 0x342 //machine trap cause + val mtval = 0x343 //machine bad address or instruction + val mip = 0x344 //machine interrupt pending + + //machine memory protection + //DONT NEED + + //machine counter/timers + val mcycle = 0xb00 //machine cycle counter + val minstret = 0xb02 //machine instructions retured counter + val mcycleh = 0xb80 + val minstreth = 0xb82 + //performance counter setup + val mcounterinhibit = 0x320 + val all = { + val res = collection.mutable.ArrayBuffer[Int]() + res += mstatus + res += misa + res += medeleg + res += mideleg + res += mie + res += mtvec + res += mscratch + res += mepc + res += mcause + res += mtval + res += mip + res += mcycle + res += minstret + res += mcycleh + res += minstreth + res += mvendorid + res += marchid + res += mhartid + res += mimpid + res += mcounterinhibit + res.toArray + } +} + +class MStatus extends Bundle{ + val sd = Bool() //dirty fs or xs + val wpri1 = UInt(8.W) //reserved, zero + val tsr = Bool() //trap on sret + val tw = Bool() //timeout for supervisor wait for interrupt + val tvm = Bool() //trap virtual memory + val mxr = Bool() //make executable readable + val sum = Bool() //supervisor user mem access + val mprv = Bool() //modify priv, access memorr as mpp + val xs = UInt(2.W) //user extension state + val fs = UInt(2.W) //float state + //previous privilege + val mpp = UInt(2.W) + val wpri2 = UInt(2.W) + val spp = UInt(1.W) + //previous interrupt enable + val mpie = Bool() + val wpri3 = Bool() //reserved, zero + val spie = Bool() + val upie = Bool() + //interrupt enable + val mie = Bool() //machine interrupt enable + val wpri4 = Bool() //reserved, zero + val sie = Bool() //supervisor interrupt enable + val uie = Bool() //user interrupt enable +} + +class MISA extends Bundle{ + val mxl = UInt(2.W) //rv32, 64 , 128 + val wlrl = UInt(4.W) //reserved + val extensions = UInt(26.W) //isa extensions +} + +class MVendorID extends Bundle{ + val bank = UInt(25.W) + val offset = UInt(7.W) +} + +class MTVec extends Bundle{ + val base = UInt(30.W) + val mode = UInt(2.W) +} + +class MIx extends Bundle{ + val wpri1 = UInt(20.W) + val meix = Bool() + val wpri2 = UInt(1.W) + val seix = Bool() + val ueix = Bool() + val mtix = Bool() + val wpri3 = UInt(1.W) + val stix = Bool() + val utix = Bool() + val msix = Bool() + val wpri4 = UInt(1.W) + val ssix = Bool() + val usix = Bool() +} + +class XCounterEnInhibit extends Bundle{ + val hpm31 = Bool() + val hpm30 = Bool() + val hpm29 = Bool() + val hpm28 = Bool() + val hpm27 = Bool() + val hpm26 = Bool() + val hpm25 = Bool() + val hpm24 = Bool() + val hpm23 = Bool() + val hpm22 = Bool() + val hpm21 = Bool() + val hpm20 = Bool() + val hpm19 = Bool() + val hpm18 = Bool() + val hpm17 = Bool() + val hpm16 = Bool() + val hpm15 = Bool() + val hpm14 = Bool() + val hpm13 = Bool() + val hpm12 = Bool() + val hpm11 = Bool() + val hpm10 = Bool() + val hpm9 = Bool() + val hpm8 = Bool() + val hpm7 = Bool() + val hpm6 = Bool() + val hpm5 = Bool() + val hpm4 = Bool() + val hpm3 = Bool() + val ir = Bool() + val tmzero = Bool() + val cy = Bool() +} + +class MCause extends Bundle{ + val interrupt = Bool() + val exceptioncode = UInt(31.W) +} + +object MCSRCmd{ + // commands + val size = 3.W + val execute = 0.asUInt(size) + val nop = 0.asUInt(size) + val write = 1.asUInt(size) + val set = 2.asUInt(size) + val clear = 3.asUInt(size) + val interrupt = 4.asUInt(size) + val read = 5.asUInt(size) + + val SIZE = 3.W + val MSB = 31 + val LSB = 20 + val TRAPADDR = "h80000000".U + val MPRV = 3 +} + +class CSRRegFileIO extends Bundle{ + //val hartid = Input(UInt(32.W)) + val rw = new Bundle { + val rdata = Output(UInt(32.W)) // + val wdata = Input(UInt(32.W)) // + } + + val csr_stall = Output(Bool())//not needed in single cycle + val eret = Output(Bool())// + + val decode = new Bundle { + val inst = Input(UInt(32.W)) // + val immid = Input(UInt(32.W)) // + val read_illegal = Output(Bool()) + val write_illegal = Output(Bool()) + val system_illegal = Output(Bool()) + } + + val status = Output(new MStatus())//not needed in this design but useful if more ISA extensions + val evec = Output(UInt(32.W)) // + val exception = Input(Bool()) // + val retire = Input(Bool()) // + val pc = Input(UInt(32.W)) // + val time = Output(UInt(32.W))// +} + +class CSRRegFile extends Module{ + //INIT CSR + val io = IO(new CSRRegFileIO) + io := DontCare + + val reset_mstatus = WireInit(0.U.asTypeOf(new MStatus())) + reset_mstatus.mpp := MCSRCmd.MPRV//machine mode + + val reg_mstatus = RegInit(reset_mstatus) + val reg_mepc = Reg(UInt(32.W)) + val reg_mcause = RegInit(0.U.asTypeOf(new MCause())) + val reg_mtval = Reg(UInt(32.W)) + val reg_mscratch = Reg(UInt(32.W)) + val reg_mtimecmp = Reg(UInt(64.W)) + val reg_medeleg = Reg(UInt(32.W)) + + val reg_mip = RegInit(0.U.asTypeOf(new MIx())) + val reg_mie = RegInit(0.U.asTypeOf(new MIx())) + val reg_wfi = RegInit(false.B) + val reg_mtvec = RegInit(0.U.asTypeOf(new MTVec())) + + val reg_time = WideCounter(64) + val reg_instret = WideCounter(64, io.retire) + + val reg_mcounterinhibit = RegInit(0.U.asTypeOf(new XCounterEnInhibit())) + val reg_mcounteren = RegInit(0.U.asTypeOf(new XCounterEnInhibit())) + + val read_mstatus = io.status.asUInt() + val isa_string = "I" + val reg_misa = RegInit((BigInt(0) | isa_string.map(x => 1 << (x - 'A')).reduce(_|_)).U.asTypeOf(new MISA())) + val reg_mvendorid = RegInit(0.U.asTypeOf(new MVendorID())) + + + val read_mapping = collection.mutable.LinkedHashMap[Int,Bits]( + MCSRs.mcounterinhibit -> reg_mcounterinhibit.asUInt, + MCSRs.mcycle -> reg_time, + MCSRs.minstret -> reg_instret, + MCSRs.mimpid -> 0.U, + MCSRs.marchid -> 0.U, + MCSRs.mvendorid -> 0.U, + MCSRs.misa -> reg_misa.asUInt, + MCSRs.mstatus -> read_mstatus, + MCSRs.mtvec -> MCSRCmd.TRAPADDR, + MCSRs.mip -> reg_mip.asUInt(), + MCSRs.mie -> reg_mie.asUInt(), + MCSRs.mscratch -> reg_mscratch, + MCSRs.mepc -> reg_mepc, + MCSRs.mtval -> reg_mtval, + MCSRs.mcause -> reg_mcause.asUInt(), + MCSRs.mhartid -> 0.U, + MCSRs.medeleg -> reg_medeleg) + + read_mapping += MCSRs.mcycleh -> 0.U + read_mapping += MCSRs.minstreth -> 0.U + + //CSR DECODE + val cmd = if( io.decode.inst(6, 0) == ("b1110011".U) ) { + if( (io.decode.inst(19, 15) == ("b011".U)) || (io.decode.inst(19, 15) == ("b111".U)) ){ + MCSRCmd.clear //CSRRC{i} + }else if( (io.decode.inst(19, 15) == ("b010".U)) || (io.decode.inst(19, 15) == ("b110".U)) ){ + MCSRCmd.set //CSRRS{i} + }else if( (io.decode.inst(19, 15) == ("b001".U)) || (io.decode.inst(19, 15) == ("b101".U)) ){ + MCSRCmd.write //CSRRW{i} + }else if( (io.decode.inst(19, 15) == ("b000".U)) ) { + MCSRCmd.interrupt //ebreak, ecall + } + }else{ + MCSRCmd.nop + } + + val csr = io.decode.inst(MCSRCmd.MSB, MCSRCmd.LSB) + val system_insn = cmd == MCSRCmd.interrupt + val cpu_ren = cmd != MCSRCmd.nop && !system_insn + + + val decoded_addr = read_mapping map { case (k, v) => k -> (csr === k) } + val priv_sufficient = MCSRCmd.MPRV >= csr(9,8) + val read_only = csr(11,10).andR + val cpu_wen = cpu_ren && cmd != MCSRCmd.read && priv_sufficient + val wen = cpu_wen && !read_only + val wdata = readModifyWriteCSR(cmd.asInstanceOf[UInt], io.rw.rdata, io.rw.wdata) + + val opcode = 1.U << csr(2,0) + val insn_call = system_insn && opcode(0) + val insn_break = system_insn && opcode(1) + val insn_ret = system_insn && opcode(2) && priv_sufficient + val insn_wfi = system_insn && opcode(5) && priv_sufficient + + private def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map( { case(k: Int, _: Bits) => csr === k }).reduce(_ || _) + io.decode.read_illegal := 3 < csr(9,8) || !decodeAny(read_mapping) + io.decode.write_illegal := csr(11,10).andR + io.decode.system_illegal := 3 < csr(9,8) + + io.status := reg_mstatus + + io.eret := insn_call || insn_break || insn_ret + + // ILLEGAL INSTR + when (io.exception) { + reg_mcause.interrupt := MCauses.illegal_instruction & "h80000000".U + reg_mcause.exceptioncode := MCauses.illegal_instruction & "h7fffffff".U + io.evec := "h80000004".U + reg_mepc := io.pc // misaligned memory exceptions not supported... + } + + assert(PopCount(insn_ret :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") + + when (reg_time >= reg_mtimecmp) { + reg_mip.mtix := true + } + + //MRET + when (insn_ret && !csr(10)) { + reg_mstatus.mie := reg_mstatus.mpie + reg_mstatus.mpie := true + io.evec := reg_mepc + } + + //ECALL + when(insn_call){ + io.evec := "h80000004".U + reg_mcause.interrupt := MCauses.machine_ecall & "h80000000".U + reg_mcause.exceptioncode := MCauses.machine_ecall & "h7fffffff".U + } + + //EBREAK + when(insn_break){ + io.evec := "h80000004".U + reg_mcause.interrupt := MCauses.breakpoint & "h80000000".U + reg_mcause.exceptioncode := MCauses.breakpoint & "h7fffffff".U + } + + io.time := reg_time + io.csr_stall := reg_wfi + + + io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) + + when (wen) { + //MISA IS FIXED IN THIS IMPLEMENATION + + //MVENDORID IS FIXED IN THIS IMPLEMENTATION + + //MARCHID IS FIXED IN THIS IMPLEMENTATION + + //MIMPID IS FIXED IN THIS IMPLEMENTATION + + //MHARTID IS FIXED IN THIS IMPLEMENTATION + + //MSTATUS + /* Only need to worry about m mode interrupts so no need to worry about setting + * mpie, mpp, and mie correctly with respect to other modes. + * non implemented modes wired to 0 + */ + when (decoded_addr(MCSRs.mstatus)) { + val new_mstatus = wdata.asTypeOf(new MStatus()) + reg_mstatus.mie := new_mstatus.mie + reg_mstatus.mpie := new_mstatus.mpie + //unused bits in mstatus m-mode only specified by spec + reg_mstatus.spp := 0 + reg_mstatus.uie := 0 + reg_mstatus.upie := 0 + reg_mstatus.mprv := 0 + reg_mstatus.mxr := 0 + reg_mstatus.sum := 0 + reg_mstatus.tvm := 0 + reg_mstatus.tw := 0 + reg_mstatus.tsr := 0 + reg_mstatus.fs := 0 + reg_mstatus.xs := 0 + reg_mstatus.sd := 0 + } + + //MTVEC IS FIXED IN THIS IMPLEMENTATION + + //MDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION + + //MIDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION + + + //MIP + /* mtip read only, cleared on timercmp write + * meip read only, set by external interrupt controller + */ + when (decoded_addr(MCSRs.mip)) { + val new_mip = wdata.asTypeOf(new MIx()) + reg_mip.msix := new_mip.msix + reg_mip.seix := 0 + reg_mip.ueix := 0 + reg_mip.stix := 0 + reg_mip.utix := 0 + reg_mip.ssix := 0 + reg_mip.usix := 0 + + } + //MIE + /* deals with external interrupts similar to mip but + * m mode bits are r and w + */ + when (decoded_addr(MCSRs.mie)) { + val new_mie = wdata.asTypeOf(new MIx()) + reg_mie.meix := new_mie.meix + reg_mie.msix := new_mie.msix + reg_mie.mtix := new_mie.mtix + reg_mip.seix := 0 + reg_mip.ueix := 0 + reg_mip.stix := 0 + reg_mip.utix := 0 + reg_mip.ssix := 0 + reg_mip.usix := 0 + + } + //MCOUNTEREB IS FIXED IN THIS IMPLEMENTATION BECAUSE NO S | U MODE + + //MCOUNTINHIBIT + /* stops counting cycles and retired instructions if need be + * + */ + when (decoded_addr(MCSRs.mcounterinhibit)) { + val new_mcounterinhibit = wdata.asTypeOf(new XCounterEnInhibit()) + reg_mcounterinhibit := new_mcounterinhibit + if( reg_mcounterinhibit.cy == false.B) { + writeCounter(MCSRs.mcycle, reg_time, wdata) + } + if( reg_mcounterinhibit.ir == false.B){ + writeCounter(MCSRs.minstret, reg_instret, wdata) + } + } + + //MSCRATCH + when (decoded_addr(MCSRs.mscratch)) { reg_mscratch := wdata } + + //MEPC + /* hardcoded to be 32 bit aligned because no compressed isa last 2 bits 0 + */ + when (decoded_addr(MCSRs.mepc)) { reg_mepc := (wdata(32-1,0) >> 2.U) << 2.U } + //MCAUSE + /* Only write to on interrupt for hardware. software can write whenever + * masks msb and 5 lsb from wdata + */ + when (decoded_addr(MCSRs.mcause)) { + reg_mcause.interrupt := (wdata & ((BigInt(1) << (32-1)) + 31).U) & "h80000000".U /* only implement 5 LSBs and MSB */ + reg_mcause.exceptioncode := (wdata & ((BigInt(1) << (32-1)) + 31).U) & "h7fffffff".U /* only implement 5 LSBs and MSB */ + + } + + when (decoded_addr(MCSRs.mtval)) { reg_mtval := wdata(32-1,0) } + when (decoded_addr(MCSRs.medeleg)) { reg_medeleg := wdata(32-1,0) } + } + def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { + val hi = lo + MCSRs.mcycleh - MCSRs.mcycle + when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } + when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } + } + def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = +(Mux(cmd.isOneOf(MCSRCmd.set, MCSRCmd.clear), rdata, 0.U) | wdata) & ~Mux(cmd === MCSRCmd.clear, wdata, 0.U) +} diff --git a/src/main/scala/components/helpers.scala b/src/main/scala/components/helpers.scala index d0bbcd9d..053b46e5 100644 --- a/src/main/scala/components/helpers.scala +++ b/src/main/scala/components/helpers.scala @@ -4,7 +4,223 @@ package dinocpu import chisel3._ import chisel3.util._ +import scala.math._ +import scala.collection.mutable.ArrayBuffer +object Util +{ + implicit def intToUInt(x: Int): UInt = x.U + implicit def intToBoolean(x: Int): Boolean = if (x != 0) true else false + implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0 + implicit def booleanToBool(x: Boolean): Bool = x.B + implicit def sextToConv(x: UInt) = new AnyRef { + def sextTo(n: Int): UInt = Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) + } + + implicit def wcToUInt(c: WideCounter): UInt = c.value + implicit class UIntIsOneOf(val x: UInt) extends AnyVal { + def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).reduce(_||_) + + def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) + } + + implicit class UIntToAugmentedUInt(val x: UInt) extends AnyVal { + def sextTo(n: Int): UInt = { + require(x.getWidth <= n) + if (x.getWidth == n) x + else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) + } + + def padTo(n: Int): UInt = { + require(x.getWidth <= n) + if (x.getWidth == n) x + else Cat(0.U((n - x.getWidth).W), x) + } + + def extract(hi: Int, lo: Int): UInt = { + if (hi == lo-1) 0.U + else x(hi, lo) + } + + def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds + } +} + + +//do two masks have at least 1 bit match? +object maskMatch +{ + def apply(msk1: UInt, msk2: UInt): Bool = + { + val br_match = (msk1 & msk2) =/= 0.U + return br_match + } +} + +//clear one-bit in the Mask as specified by the idx +object clearMaskBit +{ + def apply(msk: UInt, idx: UInt): UInt = + { + return (msk & ~(1.U << idx))(msk.getWidth-1, 0) + } +} + +//shift a register over by one bit +object PerformShiftRegister +{ + def apply(reg_val: Bits, new_bit: Bool): Bits = + { + reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt(), new_bit.asUInt()).asUInt() + reg_val + } +} + +object Split +{ + // is there a better way to do do this? + def apply(x: Bits, n0: Int) = { + val w = checkWidth(x, n0) + (x(w-1,n0), x(n0-1,0)) + } + def apply(x: Bits, n1: Int, n0: Int) = { + val w = checkWidth(x, n1, n0) + (x(w-1,n1), x(n1-1,n0), x(n0-1,0)) + } + def apply(x: Bits, n2: Int, n1: Int, n0: Int) = { + val w = checkWidth(x, n2, n1, n0) + (x(w-1,n2), x(n2-1,n1), x(n1-1,n0), x(n0-1,0)) + } + + private def checkWidth(x: Bits, n: Int*) = { + val w = x.getWidth + def decreasing(x: Seq[Int]): Boolean = + if (x.tail.isEmpty) true + else x.head > x.tail.head && decreasing(x.tail) + require(decreasing(w :: n.toList)) + w + } +} + + +// a counter that clock gates most of its MSBs using the LSB carry-out +case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true) +{ + private val isWide = width > 2*inc.getWidth + private val smallWidth = if (isWide) inc.getWidth max log2Ceil(width) else width + private val small = if (reset) RegInit(0.asUInt(smallWidth.W)) else Reg(UInt(smallWidth.W)) + private val nextSmall = small +& inc + small := nextSmall + + private val large = if (isWide) { + val r = if (reset) RegInit(0.asUInt((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W)) + when (nextSmall(smallWidth)) { r := r + 1.U } + r + } else null + + val value = if (isWide) Cat(large, small) else small + lazy val carryOut = { + val lo = (small ^ nextSmall) >> 1 + if (!isWide) lo else { + val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1 + Cat(hi, lo) + } + } + + def := (x: UInt) = { + small := x + if (isWide) large := x >> smallWidth + } +} + +// taken from rocket FPU +object RegEn +{ + def apply[T <: Data](data: T, en: Bool) = + { + val r = Reg(data) + when (en) { r := data } + r + } + def apply[T <: Bits](data: T, en: Bool, resetVal: T) = + { + val r = RegInit(resetVal) + when (en) { r := data } + r + } +} + +object Str +{ + def apply(s: String): UInt = { + var i = BigInt(0) + require(s.forall(validChar _)) + for (c <- s) + i = (i << 8) | c + i.asUInt((s.length*8).W) + } + def apply(x: Char): Bits = { + require(validChar(x)) + val lit = x.asUInt(8.W) + lit + } + def apply(x: UInt): Bits = apply(x, 10) + def apply(x: UInt, radix: Int): Bits = { + val rad = radix.U + val digs = digits(radix) + val w = x.getWidth + require(w > 0) + + var q = x + var s = digs(q % rad) + for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { + q = q / rad + s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digs(q % rad)), s) + } + s + } + def apply(x: SInt): Bits = apply(x, 10) + def apply(x: SInt, radix: Int): Bits = { + val neg = x < 0.S + val abs = Mux(neg, -x, x).asUInt() + if (radix != 10) { + Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) + } else { + val rad = radix.U + val digs = digits(radix) + val w = abs.getWidth + require(w > 0) + + var q = abs + var s = digs(q % rad) + var needSign = neg + for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { + q = q / rad + val placeSpace = q === 0.U + val space = Mux(needSign, Str('-'), Str(' ')) + needSign = needSign && !placeSpace + s = Cat(Mux(placeSpace, space, digs(q % rad)), s) + } + Cat(Mux(needSign, Str('-'), Str(' ')), s) + } + } + + def bigIntToString(x: BigInt): String = { + val s = new StringBuilder + var b = x + while (b != 0) { + s += (x & 0xFF).toChar + b = b >> 8 + } + s.toString + } + + private def digit(d: Int): Char = (if (d < 10) '0'+d else 'a'-10+d).toChar + private def digits(radix: Int): Vec[Bits] = + VecInit((0 until radix).map(i => Str(digit(i)))) + + private def validChar(x: Char) = x == (x & 0xFF) +} /** * A simple adder which takes two inputs and returns the sum * diff --git a/src/main/scala/single-cycle/cpu.scala b/src/main/scala/single-cycle/cpu.scala index db452f13..1d61f544 100644 --- a/src/main/scala/single-cycle/cpu.scala +++ b/src/main/scala/single-cycle/cpu.scala @@ -19,6 +19,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { val pc = RegInit(0.U) val control = Module(new Control()) val registers = Module(new RegisterFile()) + val csr = Module(new CSRRegFile()) val aluControl = Module(new ALUControl()) val alu = Module(new ALU()) val immGen = Module(new ImmediateGenerator()) @@ -27,6 +28,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { val branchAdd = Module(new Adder()) val (cycleCount, _) = Counter(true.B, 1 << 30) + //FETCH io.imem.address := pc pcPlusFour.io.inputx := pc @@ -35,6 +37,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { val instruction = io.imem.instruction val opcode = instruction(6,0) + //DECODE control.io.opcode := opcode registers.io.readreg1 := instruction(19,15) @@ -50,7 +53,8 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { immGen.io.instruction := instruction val imm = immGen.io.sextImm - + + //ALU branchCtrl.io.branch := control.io.branch branchCtrl.io.funct3 := instruction(14,12) branchCtrl.io.inputx := registers.io.readdata1 @@ -68,6 +72,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { alu.io.inputy := alu_inputy alu.io.operation := aluControl.io.operation + //MEMORY io.dmem.address := alu.io.result io.dmem.writedata := registers.io.readdata2 io.dmem.memread := control.io.memread @@ -75,6 +80,19 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { io.dmem.maskmode := instruction(13,12) io.dmem.sext := ~instruction(14) + //WRITEBACK + csr.io.decode.inst := instruction + csr.io.decode.immid := imm + csr.io.rw.wdata := registers.io.readdata2 + + + csr.io.retire := true.B //mem is synchronous in this deisgn. no flushing as far as i'm aware + csr.io.exception := !control.io.validinst || csr.io.decode.read_illegal || + csr.io.decode.write_illegal || csr.io.decode.system_illegal //illegal inst exception? + csr.io.pc := pc + + + val write_data = Wire(UInt()) when (control.io.toreg === 1.U) { write_data := io.dmem.readdata @@ -93,6 +111,8 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { next_pc := branchAdd.io.result } .elsewhen (control.io.jump === 3.U) { next_pc := alu.io.result & Cat(Fill(31, 1.U), 0.U) + } .elsewhen (csr.io.eret || !control.io.validinst) { + next_pc := csr.io.evec } .otherwise { next_pc := pcPlusFour.io.result } diff --git a/src/main/scala/testing/CPUTesterDriver.scala b/src/main/scala/testing/CPUTesterDriver.scala index 05338665..b3e1efbe 100644 --- a/src/main/scala/testing/CPUTesterDriver.scala +++ b/src/main/scala/testing/CPUTesterDriver.scala @@ -59,6 +59,12 @@ class CPUTesterDriver(cpuType: String, simulator.reset(5) } + def initCSR(vals: Map[Int, BigInt]) { + for ((num, value) <- vals) { + simulator.poke(s"cpu.csr.read_mapping_$num", value) + } + } + def initRegs(vals: Map[Int, BigInt]) { for ((num, value) <- vals) { simulator.poke(s"cpu.registers.regs_$num", value) @@ -75,6 +81,22 @@ class CPUTesterDriver(cpuType: String, } } + def checkCSR(vals: Map[Int, BigInt]): Boolean = { + var success = true + for ((num, value) <- vals) { + try { + simulator.expect(s"cpu.csr.read_mapping_$num", value) + } catch { + case _: TreadleException => { + success = false + val real = simulator.peek(s"cpu.csr.read_mapping_$num") + println(s"CSR $num failed to match. Was $real. Should be $value") + } + } + } + success + } + def checkRegs(vals: Map[Int, BigInt]): Boolean = { var success = true for ((num, value) <- vals) { @@ -128,6 +150,8 @@ class CPUTesterDriver(cpuType: String, case class CPUTestCase( binary: String, cycles: Map[String, Int], + initCSR: Map[Int, BigInt], + checkCSR: Map[Int, BigInt], initRegs: Map[Int, BigInt], checkRegs: Map[Int, BigInt], initMem: Map[Int, BigInt], @@ -143,10 +167,11 @@ case class CPUTestCase( object CPUTesterDriver { def apply(testCase: CPUTestCase, cpuType: String, branchPredictor: String = ""): Boolean = { val driver = new CPUTesterDriver(cpuType, branchPredictor, testCase.binary, testCase.extraName) + driver.initCSR(testCase.initCSR) driver.initRegs(testCase.initRegs) driver.initMemory(testCase.initMem) driver.run(testCase.cycles(cpuType)) - val success = driver.checkRegs(testCase.checkRegs) - success && driver.checkMemory(testCase.checkMem) + val success = driver.checkCSR(testCase.checkCSR) + success && driver.checkRegs(testCase.checkRegs) && driver.checkMemory(testCase.checkMem) } } diff --git a/src/main/scala/testing/InstTests.scala b/src/main/scala/testing/InstTests.scala index b265a169..d63bbbf6 100644 --- a/src/main/scala/testing/InstTests.scala +++ b/src/main/scala/testing/InstTests.scala @@ -9,6 +9,8 @@ package dinocpu * Each test case looks like: * - binary to run in src/test/resources/risc-v * - number of cycles to run for each CPU type + * - initial values for csr registers + * - final values to check for csr registers * - initial values for registers * - final values to check for registers * - initial values for memory @@ -30,71 +32,85 @@ object InstTests { val rtype = List[CPUTestCase]( CPUTestCase("add1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), CPUTestCase("add2", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1234, 20 -> 5678), Map(0 -> 0, 10 -> 6912), Map(), Map()), CPUTestCase("add0", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1234, 6 -> 3456), Map(0 -> 0, 5 -> 1234, 6 -> 3456), Map(), Map()), CPUTestCase("or", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1234, 6 -> 5678), Map(7 -> 5886), Map(), Map()), CPUTestCase("sub", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1234, 6 -> 5678), Map(7 -> BigInt("FFFFEEA4", 16)), Map(), Map()), CPUTestCase("and", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1234, 6 -> 5678), Map(7 -> 1026), Map(), Map()), CPUTestCase("xor", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> 1234, 5 -> 5678), Map(5 -> 5678, 7 -> 1234, 6 -> 4860), Map(), Map()), CPUTestCase("slt", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> 1234, 5 -> 5678), Map(5 -> 5678, 7 -> 1234, 6 -> 1), Map(), Map()), CPUTestCase("slt1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> -1, 5 -> 1), Map(5 -> 1, 6 -> 1), Map(), Map()), CPUTestCase("sltu", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> -1, 5 -> 1), Map(5 -> 1, 6 -> 0), Map(), Map()), CPUTestCase("sltu1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> 20, 5 -> 100), Map(5 -> 100, 6 -> 1), Map(), Map()), CPUTestCase("sll", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> 32, 5 -> 2), Map(7 -> 32, 5 -> 2, 6 -> 128), Map(), Map()), CPUTestCase("srl", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> 32, 5 -> 2), Map(7 -> 32, 5 -> 2, 6 -> 8), Map(), Map()), CPUTestCase("sra", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(7 -> twoscomp(-2), 5 -> 31), Map(5 -> 31, 6 -> twoscomp(-1)), Map(), Map()) @@ -103,41 +119,49 @@ object InstTests { val rtypeMultiCycle = List[CPUTestCase]( CPUTestCase("addfwd", Map("single-cycle" -> 10, "pipelined" -> 14), + Map(), Map()), Map(5 -> 1, 10 -> 0), Map(5 -> 1, 10 -> 10), Map(), Map()), CPUTestCase("swapxor", Map("single-cycle" -> 3, "pipelined" -> 7), + Map(), Map()), Map(7 -> 5678, 5 -> 1234), Map(5 -> 5678,7->1234), Map(), Map()), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), + Map(), Map()), Map(5 -> 512, 6->1), Map(7->1), Map(), Map(), "-512"), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), + Map(), Map()), Map(5 -> 1234, 6->1), Map(7->0), Map(), Map(), "-1234"), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), + Map(), Map()), Map(5 -> twoscomp(-65536), 6->1), Map(7->0), // This algorithm doesn't work for negative numbers Map(), Map(), "--65536"), CPUTestCase("oppsign", Map("single-cycle" -> 2, "pipelined" -> 7), + Map(), Map()), Map(5 -> 512, 6->twoscomp(-1024),7->0), Map(7->1), Map(), Map(), "-true"), CPUTestCase("oppsign", Map("single-cycle" -> 2, "pipelined" -> 7), + Map(), Map()), Map(5 -> 512, 6->1024,7->0), Map(7->0), Map(), Map(), "-false"), CPUTestCase("rotR", Map("single-cycle" -> 4, "pipelined" -> 8), + Map(), Map()), Map(5 -> twoscomp(-1), 6->1, 7->32), Map(7->twoscomp(-1)), Map(), Map()) @@ -146,59 +170,118 @@ object InstTests { val itype = List[CPUTestCase]( CPUTestCase("addi1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(0 -> 0, 10 -> 17), Map(), Map()), CPUTestCase("slli", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1), Map(0 -> 0, 5 -> 1, 6 -> 128), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 1024), Map(0 -> 0, 5 -> 1024, 6 -> 8), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> twoscomp(-1024)), Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), Map(), Map(), "-negative"), CPUTestCase("srli", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 128), Map(0 -> 0, 5 -> 128, 6 -> 1), Map(), Map()), CPUTestCase("andi", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 200), Map(), Map()), CPUTestCase("ori", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 511), Map(), Map()), CPUTestCase("xori", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 311), Map(), Map()), CPUTestCase("slti", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1),6->1), Map(), Map()), CPUTestCase("sltiu", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), Map(), Map()) + CPUTestCase("csrrc", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrci", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrs", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrsi", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrw", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrwi", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) + CPUTestCase("ecall", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) + CPUTestCase("ebreak", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), + Map(), + Map(), + Map(), Map()) ) val itypeMultiCycle = List[CPUTestCase]( CPUTestCase("addi2", Map("single-cycle" -> 2, "pipelined" -> 6), + Map(), Map()), Map(), Map(0 -> 0, 10 -> 17, 11 -> 93), Map(), Map()) @@ -207,91 +290,109 @@ object InstTests { val branch = List[CPUTestCase]( CPUTestCase("beq", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-False"), CPUTestCase("beq", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-True"), CPUTestCase("bne", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("bne", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-True"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-False-equal"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-True"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), Map(), Map(), "-False-signed"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), Map(), Map(), "-True-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-False"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(), Map(), "-True"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), Map(), Map(), "-False-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), Map(), Map(), "-True-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-True-equal"), CPUTestCase("bltu", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("bltu", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(), Map(), "-True"), CPUTestCase("bgeu", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(), Map(), "-False"), CPUTestCase("bgeu", Map("single-cycle" -> 3, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(), Map(), "-True") @@ -313,51 +414,61 @@ object InstTests { val memory = List[CPUTestCase]( CPUTestCase("lw1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(5 -> BigInt("ffffffff", 16)), Map(), Map()), CPUTestCase("lb", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(5 -> BigInt("04", 16)), Map(), Map()), CPUTestCase("lh", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(5 -> BigInt("0304", 16)), Map(), Map()), CPUTestCase("lbu", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(5 -> BigInt("f4", 16)), Map(), Map()), CPUTestCase("lhu", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(5 -> BigInt("f3f4", 16)), Map(), Map()), CPUTestCase("lb1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(5 -> BigInt("fffffff4", 16)), Map(), Map()), CPUTestCase("lh1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(), Map(5 -> BigInt("fffff3f4", 16)), Map(), Map()), CPUTestCase("sw", Map("single-cycle" -> 6, "pipelined" -> 10), + Map(), Map()), Map(5 -> 1234), Map(6 -> 1234), Map(), Map(0x100 -> 1234)), CPUTestCase("sb", Map("single-cycle" -> 6, "pipelined" -> 10), + Map(), Map()), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffffff01", 16))), CPUTestCase("sh", Map("single-cycle" -> 6, "pipelined" -> 10), + Map(), Map()), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffff0001", 16))) @@ -366,6 +477,7 @@ object InstTests { val memoryMultiCycle = List[CPUTestCase]( CPUTestCase("lwfwd", Map("single-cycle" -> 2, "pipelined" -> 7), + Map(), Map()), Map(5 -> BigInt("ffffffff", 16), 10 -> 5), Map(5 -> 1, 10 -> 6), Map(), Map()), @@ -384,21 +496,37 @@ object InstTests { val utype = List[CPUTestCase]( CPUTestCase("auipc0", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc2", Map("single-cycle" -> 2, "pipelined" -> 6), + Map(), Map()), Map(10 -> 1234), Map(10 -> (17 << 12)), Map(), Map()), CPUTestCase("lui0", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), + CPUTestCase("auipc1", + Map("single-cycle" -> 2, "pipelined" -> 6), + Map(), Map()), + Map(10 -> 1234), + Map(10 -> 4), + Map(), Map()), + CPUTestCase("auipc3", + Map("single-cycle" -> 2, "pipelined" -> 6), + Map(), Map()), + Map(10 -> 1234), + Map(10 -> ((17 << 12) + 4)), + Map(), Map()), CPUTestCase("lui1", Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map()), Map(10 -> 1234), Map(10 -> 4096), Map(), Map()) @@ -407,11 +535,13 @@ object InstTests { val utypeMultiCycle = List[CPUTestCase]( CPUTestCase("auipc1", Map("single-cycle" -> 2, "pipelined" -> 6), + Map(), Map()), Map(10 -> 1234), Map(10 -> 4), Map(), Map()), CPUTestCase("auipc3", Map("single-cycle" -> 2, "pipelined" -> 6), + Map(), Map()), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()) @@ -420,16 +550,19 @@ object InstTests { val jump = List[CPUTestCase]( CPUTestCase("jal", Map("single-cycle" -> 2, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr0", Map("single-cycle" -> 2, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 10 -> 28), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr1", Map("single-cycle" -> 2, "pipelined" -> 9), + Map(), Map()), Map(5 -> 1234, 10 -> 20), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -438,21 +571,25 @@ object InstTests { val smallApplications = List[CPUTestCase]( CPUTestCase("fibonacci", Map("single-cycle" -> 300, "pipelined" -> 1000), + Map(), Map()), Map(6->11), Map(6->11,5->89), Map(), Map()), CPUTestCase("naturalsum", Map("single-cycle" -> 200, "pipelined" -> 500), + Map(), Map()), Map(), Map(5->55), Map(), Map()), CPUTestCase("multiplier", Map("single-cycle" -> 1000, "pipelined" -> 1000), + Map(), Map()), Map(5->23,6->20,8->0x1000), Map(5->23*20), Map(), Map()), CPUTestCase("divider", Map("single-cycle" -> 1000, "pipelined" -> 2000), + Map(), Map()), Map(5->1260,6->30), Map(7->42), Map(), Map()) @@ -461,31 +598,37 @@ object InstTests { val fullApplications = List[CPUTestCase]( CPUTestCase("multiply.riscv", Map("single-cycle" -> 42342, "pipelined" -> 100000), + Map(), Map()), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("median.riscv", Map("single-cycle" -> 9433, "pipelined" -> 100000), + Map(), Map()), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("qsort.riscv", Map("single-cycle" -> 263290, "pipelined" -> 300000), + Map(), Map()), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("rsort.riscv", Map("single-cycle" -> 263290, "pipelined" -> 250000), + Map(), Map()), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("towers.riscv", Map("single-cycle" -> 12653, "pipelined" -> 100000), + Map(), Map()), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("vvadd.riscv", Map("single-cycle" -> 5484, "pipelined" -> 20000), + Map(), Map()), Map(), Map(10->12345678), Map(), Map()) diff --git a/src/test/resources/risc-v/sw b/src/test/resources/risc-v/sw index 2aef06ce26a4592ff64114ab77cfa4668c361c18..4a12e983891160077c00550ebb56842279d81919 100755 GIT binary patch delta 399 zcmeyOy+wC|g76$s1~4#TP+(wW&|qL^VB2VXmY;btQ^Dr{{C}AziLgjIN&=M>Wfmuw zF);E2nXE-+#zvV&1qKrnfQ8}Xe>Nc304~JHzyoBnfCwNE z0Lse&X%-eR7szK~u!k_gqyW$~Jv4bMRK5~}8%QaV0imc07-A+*711{dc5w`GjCXQ% z_wYEUlZuPui%SxVN`T_X$|j!`F%i@QdtNWGq@*Y_sk9`ucrv4? zJ)^;7M^S50b)Z$u3=9Pz7k~hZ2m^!EOy%fFdL;1Bb}0+vZ4EE5xDCfkUJOimCH z@zsGS29k^nJV25KL;!&R0~3QXgbC#{GROg0EG!T~kh~Te-*ECr5q-|2;^O$?lEk8t z$swX96O*(j9}yK{)R}x!)Oxawm;f(}2m`|ckVYV8og679&AJ3AVm6skOn7pSm;mc7 JAWt2{0{~*pAWHxM diff --git a/src/test/resources/risc-v/sw.riscv b/src/test/resources/risc-v/sw.riscv index e62cbd8f..896bceb5 100644 --- a/src/test/resources/risc-v/sw.riscv +++ b/src/test/resources/risc-v/sw.riscv @@ -2,6 +2,7 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: + addi t0, x0, 7 sw t0, 0x400(zero) nop nop diff --git a/src/verilog/Top.DualPortedMemory.memory.v b/src/verilog/Top.DualPortedMemory.memory.v new file mode 100644 index 00000000..a41466f6 --- /dev/null +++ b/src/verilog/Top.DualPortedMemory.memory.v @@ -0,0 +1,20 @@ +module BindsTo_0_DualPortedMemory( + input clock, + input reset, + input [31:0] io_imem_address, + output [31:0] io_imem_instruction, + input [31:0] io_dmem_address, + input [31:0] io_dmem_writedata, + input io_dmem_memread, + input io_dmem_memwrite, + input [1:0] io_dmem_maskmode, + input io_dmem_sext, + output [31:0] io_dmem_readdata +); + +initial begin + $readmemh("test", DualPortedMemory.memory); +end + endmodule + +bind DualPortedMemory BindsTo_0_DualPortedMemory BindsTo_0_DualPortedMemory_Inst(.*); \ No newline at end of file diff --git a/src/verilog/obj_dir/VTop b/src/verilog/obj_dir/VTop new file mode 100755 index 0000000000000000000000000000000000000000..5e32ec84da8414f913821ae1cd31e4bff90c1c11 GIT binary patch literal 219584 zcmc$H3w%_?_5Usq2?!=WsPRcat>6QL5(P0Dl(iQn8i6SF(SQ&Hr0v@llQ1YP8lyrFxg8ZM0OPrSkuN&&<6$yPFM^+W!wf=H5AT z=FB-~&YYP!Gk5m3(D(~`1cL$ZU(dj~0jA22Q;>3>gkmuHp`Xka^01`?X7|q$akvR)yprhBRT!FK;~M_AR{+2rm4= z!hgLx^N6qh?z;MGna7e|y9I*9fyQ8A55g|T|NJ-fn7fXiQ8l%2)F)BTOjL&P_i0pm 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-*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See VTop.h for the primary calling header + +#include "VTop.h" // For This +#include "VTop__Syms.h" + + +//-------------------- +// STATIC VARIABLES + + +//-------------------- + +VL_CTOR_IMP(VTop) { + VTop__Syms* __restrict vlSymsp = __VlSymsp = new VTop__Syms(this, name()); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Reset internal values + + // Reset structure values + _ctor_var_reset(); +} + +void VTop::__Vconfigure(VTop__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +VTop::~VTop() { + delete __VlSymsp; __VlSymsp=NULL; +} + +//-------------------- + + +void VTop::eval() { + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VTop::eval\n"); ); + VTop__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +#ifdef VL_DEBUG + // Debug assertions + _eval_debug_assertions(); +#endif // VL_DEBUG + // Initialize + if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + while (VL_LIKELY(__Vchange)) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); + _eval(vlSymsp); + __Vchange = _change_request(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge"); + } +} + +void VTop::_eval_initial_loop(VTop__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + _eval_initial(vlSymsp); + int __VclockLoop = 0; + QData __Vchange = 1; + while (VL_LIKELY(__Vchange)) { + _eval_settle(vlSymsp); + _eval(vlSymsp); + __Vchange = _change_request(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge"); + } +} + +//-------------------- +// Internal Methods + +void VTop::_initial__TOP__1(VTop__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_initial__TOP__1\n"); ); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // INITIAL at Top.v:1440 + vlTOPp->io_success = 0U; +} + +VL_INLINE_OPT void VTop::_sequent__TOP__2(VTop__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_sequent__TOP__2\n"); ); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + VL_SIG8(__Vdlyvset__Top__DOT__mem__DOT__memory__v0,0,0); + VL_SIG8(__Vdlyvset__Top__DOT__mem__DOT__memory__v1,0,0); + VL_SIG16(__Vdlyvdim0__Top__DOT__mem__DOT__memory__v0,13,0); + VL_SIG16(__Vdlyvdim0__Top__DOT__mem__DOT__memory__v1,13,0); + VL_SIG(__Vdlyvval__Top__DOT__mem__DOT__memory__v0,31,0); + VL_SIG(__Vdlyvval__Top__DOT__mem__DOT__memory__v1,31,0); + VL_SIGW(__Vtemp1,95,0,3); + VL_SIGW(__Vtemp2,95,0,3); + VL_SIGW(__Vtemp3,95,0,3); + VL_SIGW(__Vtemp5,95,0,3); + VL_SIGW(__Vtemp6,95,0,3); + VL_SIGW(__Vtemp7,95,0,3); + VL_SIGW(__Vtemp8,95,0,3); + VL_SIGW(__Vtemp9,95,0,3); + VL_SIGW(__Vtemp15,95,0,3); + VL_SIGW(__Vtemp16,95,0,3); + // Body + // ALWAYS at Top.v:1335 + if (VL_UNLIKELY((((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & (3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))) + & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) + | (IData)(vlTOPp->reset)))))) { + VL_FWRITEF(0x80000002U,"Assertion failed\n at memory.scala:70 assert(io.dmem.address < size.U)\n"); + } + if (VL_UNLIKELY((((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & (3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))) + & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) + | (IData)(vlTOPp->reset)))))) { + VL_WRITEF("[%0t] %%Error: Top.v:1357: Assertion failed in %NTop.mem\n", + 64,VL_TIME_Q(),vlSymsp->name()); + VL_STOP_MT("Top.v",1357,""); + } + if (VL_UNLIKELY(((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) + & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) + | (IData)(vlTOPp->reset)))))) { + VL_FWRITEF(0x80000002U,"Assertion failed\n at memory.scala:99 assert(io.dmem.address < size.U)\n"); + } + if (VL_UNLIKELY(((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) + & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) + | (IData)(vlTOPp->reset)))))) { + VL_WRITEF("[%0t] %%Error: Top.v:1379: Assertion failed in %NTop.mem\n", + 64,VL_TIME_Q(),vlSymsp->name()); + VL_STOP_MT("Top.v",1379,""); + } + __Vdlyvset__Top__DOT__mem__DOT__memory__v0 = 0U; + __Vdlyvset__Top__DOT__mem__DOT__memory__v1 = 0U; + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((1U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((2U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((3U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((4U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((5U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((6U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((7U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((8U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((9U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0xaU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0xbU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0xcU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0xdU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0xeU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0xfU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x10U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x11U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x12U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x13U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x14U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x15U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x16U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x17U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x18U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x19U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:490 + if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { + if ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) { + vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; + } + } + // ALWAYS at Top.v:1136 + vlTOPp->Top__DOT__cpu__DOT__pc = ((IData)(vlTOPp->reset) + ? 0U : (((((0U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? + (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + == vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) + : + ((1U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? + (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + != vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) + : + ((4U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? + VL_LTS_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) + : + ((5U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? + VL_GTES_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) + : + ((6U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? + (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + < vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) + : + (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + >= vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2)))))) + & ((0x33U + != + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U + != + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((3U + != + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x23U + != + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & (0x63U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction))))))) + | (2U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_jump))) + ? vlTOPp->Top__DOT__cpu__DOT__branchAdd_io_result + : ( + (3U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_jump)) + ? + (0xfffffffeU + & (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) + : + ((IData)(4U) + + vlTOPp->Top__DOT__cpu__DOT__pcPlusFour_io_inputx)))); + // ALWAYS at Top.v:1335 + if (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) + & (2U != (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))))) { + VL_EXTEND_WI(71,32, __Vtemp1, vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data); + __Vtemp2[0U] = 0xffU; + __Vtemp2[1U] = 0U; + __Vtemp2[2U] = 0U; + VL_SHIFTL_WWI(71,71,6, __Vtemp3, __Vtemp2, + (0x18U & ((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10) + << 3U))); + __Vtemp5[0U] = (__Vtemp1[0U] & (~ __Vtemp3[0U])); + __Vtemp5[1U] = (__Vtemp1[1U] & (~ __Vtemp3[1U])); + __Vtemp5[2U] = (__Vtemp1[2U] & (~ __Vtemp3[2U])); + VL_EXTEND_WW(79,71, __Vtemp6, __Vtemp5); + VL_EXTEND_WI(79,32, __Vtemp7, vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data); + __Vtemp8[0U] = 0xffffU; + __Vtemp8[1U] = 0U; + __Vtemp8[2U] = 0U; + VL_SHIFTL_WWI(79,79,6, __Vtemp9, __Vtemp8, + (0x18U & ((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10) + << 3U))); + VL_EXTEND_WI(95,32, __Vtemp15, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2); + VL_SHIFTL_WWI(95,95,6, __Vtemp16, __Vtemp15, + (0x18U & ((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10) + << 3U))); + __Vdlyvval__Top__DOT__mem__DOT__memory__v0 + = (((0U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? __Vtemp6[0U] + : (__Vtemp7[0U] & (~ __Vtemp9[0U]))) + | __Vtemp16[0U]); + __Vdlyvset__Top__DOT__mem__DOT__memory__v0 = 1U; + __Vdlyvdim0__Top__DOT__mem__DOT__memory__v0 + = (0x3fffU & (IData)((vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U))); + } + if (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) + & (2U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))))) { + __Vdlyvval__Top__DOT__mem__DOT__memory__v1 + = vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2; + __Vdlyvset__Top__DOT__mem__DOT__memory__v1 = 1U; + __Vdlyvdim0__Top__DOT__mem__DOT__memory__v1 + = (0x3fffU & (IData)((vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U))); + } + // ALWAYSPOST at Top.v:1336 + if (__Vdlyvset__Top__DOT__mem__DOT__memory__v0) { + vlTOPp->Top__DOT__mem__DOT__memory[__Vdlyvdim0__Top__DOT__mem__DOT__memory__v0] + = __Vdlyvval__Top__DOT__mem__DOT__memory__v0; + } + if (__Vdlyvset__Top__DOT__mem__DOT__memory__v1) { + vlTOPp->Top__DOT__mem__DOT__memory[__Vdlyvdim0__Top__DOT__mem__DOT__memory__v1] + = __Vdlyvval__Top__DOT__mem__DOT__memory__v1; + } + vlTOPp->Top__DOT__cpu__DOT__pcPlusFour_io_inputx + = vlTOPp->Top__DOT__cpu__DOT__pc; + vlTOPp->Top__DOT__mem_io_imem_instruction = ((0x10000U + <= vlTOPp->Top__DOT__cpu__DOT__pc) + ? 0U + : + vlTOPp->Top__DOT__mem__DOT__memory + [(0x3fffU + & (vlTOPp->Top__DOT__cpu__DOT__pc + >> 2U))]); + vlTOPp->Top__DOT__cpu__DOT__registers_io_wen = + (((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x23U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | (0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))) + & (0U != (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))); + vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite + = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((3U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & (0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_jump = ( + (0x33U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x13U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((3U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x23U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x63U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x37U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x17U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x6fU + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : + ((0x67U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 3U + : 0U))))))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_toreg = + ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 1U : ((0x23U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x63U + == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : + ((0x37U + == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : ((0x17U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x6fU + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : + ((0x67U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : 3U))))))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1 + = ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x23U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x63U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : ( + (0x37U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 1U + : + ((0x17U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : + (0x6fU + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction))))))))); + vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 + : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 + : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 + : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 + : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 + : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 + : ((0x19U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 + : ((0x18U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 + : ((0x17U == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 + : ((0x16U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 + : ( + (0x15U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 + : + ((0x14U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 + : + ((0x13U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 + : + ((0x12U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 + : + ((0x11U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 + : + ((0x10U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 + : + ((0xfU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 + : + ((0xeU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 + : + ((0xdU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 + : + ((0xcU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 + : + ((0xbU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 + : + ((0xaU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 + : + ((9U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 + : + ((8U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 + : + ((7U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 + : + ((6U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 + : + ((5U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 + : + ((4U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 + : + ((3U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 + : + ((2U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 + : + ((1U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 + : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); + vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2 + = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 + : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 + : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 + : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 + : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 + : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 + : ((0x19U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 + : ((0x18U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 + : ((0x17U == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 + : ((0x16U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 + : ( + (0x15U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 + : + ((0x14U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 + : + ((0x13U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 + : + ((0x12U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 + : + ((0x11U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 + : + ((0x10U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 + : + ((0xfU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 + : + ((0xeU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 + : + ((0xdU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 + : + ((0xcU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 + : + ((0xbU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 + : + ((0xaU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 + : + ((9U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 + : + ((8U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 + : + ((7U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 + : + ((6U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 + : + ((5U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 + : + ((4U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 + : + ((3U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 + : + ((2U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 + : + ((1U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 + : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_immediate + = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x6fU != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & (0x67U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))); + vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + = ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0xfffffU : 0U) << 0xcU) | (0xfffU & + (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))); + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx = ((0U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) + ? vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + : + ((1U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) + ? 0U + : vlTOPp->Top__DOT__cpu__DOT__pc)); + vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation + = (((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | (0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))) + ? 2U : ((0U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) + | (0U + == + (0x7fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x19U)))) + ? 2U + : 3U) + : ((1U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? 6U + : ((2U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 4U : ((3U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 5U : ((4U == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 9U + : ((5U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? + ((0U + == + (0x7fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x19U))) + ? 7U + : 8U) + : + ((6U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 1U + : + ((7U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 0U + : 0xfU))))))))); + vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm = + ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + : ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + : ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0x7ffU : 0U) << 0x15U) | + ((0x100000U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xbU)) | ((0xff000U + & vlTOPp->Top__DOT__mem_io_imem_instruction) + | ((0x800U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 9U)) + | (0x7feU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U)))))) + : ((0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + : ((0x63U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0x7ffffU : 0U) << 0xdU) + | ((0x1000U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x13U)) + | ((0x800U & (vlTOPp->Top__DOT__mem_io_imem_instruction + << 4U)) + | ((0x7e0U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U)) + | (0x1eU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))))) + : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + : ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? ((((0x80000000U + & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0xfffffU : 0U) + << 0xcU) | ((0xfe0U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U)) + | (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) + : ((0x13U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + : ((0x73U == + (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU)) + : 0U))))))))); + vlTOPp->Top__DOT__cpu__DOT__branchAdd_io_result + = (vlTOPp->Top__DOT__cpu__DOT__pc + vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm); + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy = ((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) + ? vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm + : vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2); + vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3 = (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + | vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy); + vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 = + (VL_ULL(0x7fffffffffffffff) & ((0U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3)) + : ((2U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : ( + (3U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : + ((4U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + VL_LTS_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : + ((5U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + < vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : + ((6U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + ((QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx)) + << + (0x1fU + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) + : (QData)((IData)( + ((7U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + >> + (0x1fU + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) + : + ((8U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + VL_SHIFTRS_III(32,32,5, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, + (0x1fU + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) + : + ((9U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + ^ vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy) + : + ((0xaU + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + (~ vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3) + : 0U)))))))))))))); + vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data + = vlTOPp->Top__DOT__mem__DOT__memory[(0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))]; + vlTOPp->Top__DOT__mem__DOT___GEN_14 = ((2U != (3U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? ((0U + == + (3U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? (0xffU + & vlTOPp->Top__DOT__mem__DOT__memory + [ + (0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))]) + : (0xffffU + & vlTOPp->Top__DOT__mem__DOT__memory + [ + (0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))])) + : vlTOPp->Top__DOT__mem__DOT__memory + [(0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))]); + vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata + = ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) + ? ((0x4000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? vlTOPp->Top__DOT__mem__DOT___GEN_14 + : ((0U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? ((((0x80U + & vlTOPp->Top__DOT__mem__DOT___GEN_14) + ? 0xffffffU + : 0U) + << 8U) + | (0xffU + & vlTOPp->Top__DOT__mem__DOT___GEN_14)) + : ((1U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? ( + (((0x8000U + & vlTOPp->Top__DOT__mem__DOT___GEN_14) + ? 0xffffU + : 0U) + << 0x10U) + | (0xffffU + & vlTOPp->Top__DOT__mem__DOT___GEN_14)) + : vlTOPp->Top__DOT__mem__DOT___GEN_14))) + : ((2U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) + ? ((IData)(4U) + vlTOPp->Top__DOT__cpu__DOT__pc) + : (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10))); +} + +void VTop::_settle__TOP__3(VTop__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_settle__TOP__3\n"); ); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->Top__DOT__cpu__DOT__pcPlusFour_io_inputx + = vlTOPp->Top__DOT__cpu__DOT__pc; + vlTOPp->Top__DOT__mem_io_imem_instruction = ((0x10000U + <= vlTOPp->Top__DOT__cpu__DOT__pc) + ? 0U + : + vlTOPp->Top__DOT__mem__DOT__memory + [(0x3fffU + & (vlTOPp->Top__DOT__cpu__DOT__pc + >> 2U))]); + vlTOPp->Top__DOT__cpu__DOT__registers_io_wen = + (((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x23U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | (0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))) + & (0U != (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))); + vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite + = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((3U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & (0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_jump = ( + (0x33U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x13U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((3U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x23U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x63U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x37U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x17U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x6fU + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : + ((0x67U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 3U + : 0U))))))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_toreg = + ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 1U : ((0x23U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x63U + == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : + ((0x37U + == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : ((0x17U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : + ((0x6fU + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : + ((0x67U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : 3U))))))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1 + = ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x23U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U : ((0x63U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 0U + : ( + (0x37U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 1U + : + ((0x17U + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? 2U + : + (0x6fU + == + (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction))))))))); + vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 + : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 + : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 + : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 + : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 + : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 + : ((0x19U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 + : ((0x18U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 + : ((0x17U == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 + : ((0x16U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 + : ( + (0x15U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 + : + ((0x14U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 + : + ((0x13U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 + : + ((0x12U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 + : + ((0x11U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 + : + ((0x10U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 + : + ((0xfU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 + : + ((0xeU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 + : + ((0xdU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 + : + ((0xcU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 + : + ((0xbU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 + : + ((0xaU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 + : + ((9U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 + : + ((8U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 + : + ((7U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 + : + ((6U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 + : + ((5U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 + : + ((4U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 + : + ((3U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 + : + ((2U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 + : + ((1U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 + : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); + vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2 + = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 + : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 + : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 + : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 + : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 + : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 + : ((0x19U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 + : ((0x18U == (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 + : ((0x17U == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 + : ((0x16U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 + : ( + (0x15U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 + : + ((0x14U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 + : + ((0x13U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 + : + ((0x12U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 + : + ((0x11U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 + : + ((0x10U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 + : + ((0xfU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 + : + ((0xeU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 + : + ((0xdU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 + : + ((0xcU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 + : + ((0xbU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 + : + ((0xaU + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 + : + ((9U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 + : + ((8U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 + : + ((7U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 + : + ((6U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 + : + ((5U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 + : + ((4U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 + : + ((3U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 + : + ((2U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 + : + ((1U + == + (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))) + ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 + : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); + vlTOPp->Top__DOT__cpu__DOT__control_io_immediate + = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x6fU != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & (0x67U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))); + vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + = ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0xfffffU : 0U) << 0xcU) | (0xfffU & + (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U))); + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx = ((0U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) + ? vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 + : + ((1U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) + ? 0U + : vlTOPp->Top__DOT__cpu__DOT__pc)); + vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation + = (((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + | (0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))) + ? 2U : ((0U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) + | (0U + == + (0x7fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x19U)))) + ? 2U + : 3U) + : ((1U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? 6U + : ((2U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 4U : ((3U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 5U : ((4U == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 9U + : ((5U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? + ((0U + == + (0x7fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x19U))) + ? 7U + : 8U) + : + ((6U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 1U + : + ((7U + == + (7U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? 0U + : 0xfU))))))))); + vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm = + ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + : ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + : ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0x7ffU : 0U) << 0x15U) | + ((0x100000U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xbU)) | ((0xff000U + & vlTOPp->Top__DOT__mem_io_imem_instruction) + | ((0x800U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 9U)) + | (0x7feU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U)))))) + : ((0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + : ((0x63U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0x7ffffU : 0U) << 0xdU) + | ((0x1000U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x13U)) + | ((0x800U & (vlTOPp->Top__DOT__mem_io_imem_instruction + << 4U)) + | ((0x7e0U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U)) + | (0x1eU & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))))) + : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + : ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? ((((0x80000000U + & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? 0xfffffU : 0U) + << 0xcU) | ((0xfe0U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0x14U)) + | (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 7U)))) + : ((0x13U == (0x7fU + & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 + : ((0x73U == + (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) + ? (0x1fU + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xfU)) + : 0U))))))))); + vlTOPp->Top__DOT__cpu__DOT__branchAdd_io_result + = (vlTOPp->Top__DOT__cpu__DOT__pc + vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm); + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy = ((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) + ? vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm + : vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2); + vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3 = (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + | vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy); + vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 = + (VL_ULL(0x7fffffffffffffff) & ((0U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3)) + : ((2U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : ( + (3U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : + ((4U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + VL_LTS_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : + ((5U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? (QData)((IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + < vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) + : + ((6U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + ((QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx)) + << + (0x1fU + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) + : (QData)((IData)( + ((7U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + >> + (0x1fU + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) + : + ((8U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + VL_SHIFTRS_III(32,32,5, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, + (0x1fU + & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) + : + ((9U + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx + ^ vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy) + : + ((0xaU + == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) + ? + (~ vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3) + : 0U)))))))))))))); + vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data + = vlTOPp->Top__DOT__mem__DOT__memory[(0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))]; + vlTOPp->Top__DOT__mem__DOT___GEN_14 = ((2U != (3U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? ((0U + == + (3U + & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) + ? (0xffU + & vlTOPp->Top__DOT__mem__DOT__memory + [ + (0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))]) + : (0xffffU + & vlTOPp->Top__DOT__mem__DOT__memory + [ + (0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))])) + : vlTOPp->Top__DOT__mem__DOT__memory + [(0x3fffU + & (IData)( + (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 + >> 2U)))]); + vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata + = ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) + ? ((0x4000U & vlTOPp->Top__DOT__mem_io_imem_instruction) + ? vlTOPp->Top__DOT__mem__DOT___GEN_14 + : ((0U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? ((((0x80U + & vlTOPp->Top__DOT__mem__DOT___GEN_14) + ? 0xffffffU + : 0U) + << 8U) + | (0xffU + & vlTOPp->Top__DOT__mem__DOT___GEN_14)) + : ((1U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction + >> 0xcU))) ? ( + (((0x8000U + & vlTOPp->Top__DOT__mem__DOT___GEN_14) + ? 0xffffU + : 0U) + << 0x10U) + | (0xffffU + & vlTOPp->Top__DOT__mem__DOT___GEN_14)) + : vlTOPp->Top__DOT__mem__DOT___GEN_14))) + : ((2U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) + ? ((IData)(4U) + vlTOPp->Top__DOT__cpu__DOT__pc) + : (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10))); +} + +void VTop::_eval(VTop__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval\n"); ); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + if (((IData)(vlTOPp->clock) & (~ (IData)(vlTOPp->__Vclklast__TOP__clock)))) { + vlTOPp->_sequent__TOP__2(vlSymsp); + } + // Final + vlTOPp->__Vclklast__TOP__clock = vlTOPp->clock; +} + +void VTop::_eval_initial(VTop__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval_initial\n"); ); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_initial__TOP__1(vlSymsp); +} + +void VTop::final() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::final\n"); ); + // Variables + VTop__Syms* __restrict vlSymsp = this->__VlSymsp; + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void VTop::_eval_settle(VTop__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval_settle\n"); ); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_settle__TOP__3(vlSymsp); +} + +VL_INLINE_OPT QData VTop::_change_request(VTop__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_change_request\n"); ); + VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // Change detection + QData __req = false; // Logically a bool + return __req; +} + +#ifdef VL_DEBUG +void VTop::_eval_debug_assertions() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((clock & 0xfeU))) { + Verilated::overWidthError("clock");} + if (VL_UNLIKELY((reset & 0xfeU))) { + Verilated::overWidthError("reset");} +} +#endif // VL_DEBUG + +void VTop::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_ctor_var_reset\n"); ); + // Body + clock = VL_RAND_RESET_I(1); + reset = VL_RAND_RESET_I(1); + io_success = VL_RAND_RESET_I(1); + Top__DOT__mem_io_imem_instruction = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__control_io_toreg = VL_RAND_RESET_I(2); + Top__DOT__cpu__DOT__control_io_memwrite = VL_RAND_RESET_I(1); + Top__DOT__cpu__DOT__control_io_immediate = VL_RAND_RESET_I(1); + Top__DOT__cpu__DOT__control_io_alusrc1 = VL_RAND_RESET_I(2); + Top__DOT__cpu__DOT__control_io_jump = VL_RAND_RESET_I(2); + Top__DOT__cpu__DOT__registers_io_writedata = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers_io_wen = VL_RAND_RESET_I(1); + Top__DOT__cpu__DOT__registers_io_readdata1 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers_io_readdata2 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__aluControl_io_operation = VL_RAND_RESET_I(4); + Top__DOT__cpu__DOT__alu_io_inputx = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__alu_io_inputy = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__immGen_io_sextImm = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__pcPlusFour_io_inputx = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__branchAdd_io_result = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__pc = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_0 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_1 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_2 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_3 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_4 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_5 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_6 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_7 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_8 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_9 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_10 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_11 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_12 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_13 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_14 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_15 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_16 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_17 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_18 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_19 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_20 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_21 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_22 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_23 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_24 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_25 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_26 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_27 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_28 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_29 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_30 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__registers__DOT__regs_31 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__alu__DOT___T_3 = VL_RAND_RESET_I(32); + Top__DOT__cpu__DOT__alu__DOT___GEN_10 = VL_RAND_RESET_Q(63); + Top__DOT__cpu__DOT__immGen__DOT___T_26 = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<16384; ++__Vi0) { + Top__DOT__mem__DOT__memory[__Vi0] = VL_RAND_RESET_I(32); + }} + Top__DOT__mem__DOT__memory___05FT_49_data = VL_RAND_RESET_I(32); + Top__DOT__mem__DOT___GEN_14 = VL_RAND_RESET_I(32); + __Vclklast__TOP__clock = VL_RAND_RESET_I(1); +} diff --git a/src/verilog/obj_dir/VTop.h b/src/verilog/obj_dir/VTop.h new file mode 100644 index 00000000..116188ff --- /dev/null +++ b/src/verilog/obj_dir/VTop.h @@ -0,0 +1,136 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Primary design header +// +// This header should be included by all source files instantiating the design. +// The class here is then constructed to instantiate the design. +// See the Verilator manual for examples. + +#ifndef _VTop_H_ +#define _VTop_H_ + +#include "verilated_heavy.h" + +class VTop__Syms; + +//---------- + +VL_MODULE(VTop) { + public: + + // PORTS + // The application code writes and reads these signals to + // propagate new values into/out from the Verilated model. + VL_IN8(clock,0,0); + VL_IN8(reset,0,0); + VL_OUT8(io_success,0,0); + + // LOCAL SIGNALS + // Internals; generally not touched by application code + VL_SIG8(Top__DOT__cpu__DOT__control_io_toreg,1,0); + VL_SIG8(Top__DOT__cpu__DOT__control_io_memwrite,0,0); + VL_SIG8(Top__DOT__cpu__DOT__control_io_immediate,0,0); + VL_SIG8(Top__DOT__cpu__DOT__control_io_alusrc1,1,0); + VL_SIG8(Top__DOT__cpu__DOT__control_io_jump,1,0); + VL_SIG8(Top__DOT__cpu__DOT__registers_io_wen,0,0); + VL_SIG8(Top__DOT__cpu__DOT__aluControl_io_operation,3,0); + VL_SIG(Top__DOT__mem_io_imem_instruction,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers_io_writedata,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers_io_readdata1,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers_io_readdata2,31,0); + VL_SIG(Top__DOT__cpu__DOT__alu_io_inputx,31,0); + VL_SIG(Top__DOT__cpu__DOT__alu_io_inputy,31,0); + VL_SIG(Top__DOT__cpu__DOT__immGen_io_sextImm,31,0); + VL_SIG(Top__DOT__cpu__DOT__pcPlusFour_io_inputx,31,0); + VL_SIG(Top__DOT__cpu__DOT__branchAdd_io_result,31,0); + VL_SIG(Top__DOT__cpu__DOT__pc,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_0,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_1,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_2,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_3,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_4,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_5,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_6,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_7,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_8,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_9,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_10,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_11,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_12,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_13,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_14,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_15,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_16,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_17,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_18,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_19,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_20,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_21,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_22,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_23,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_24,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_25,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_26,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_27,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_28,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_29,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_30,31,0); + VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_31,31,0); + VL_SIG(Top__DOT__cpu__DOT__alu__DOT___T_3,31,0); + VL_SIG(Top__DOT__cpu__DOT__immGen__DOT___T_26,31,0); + VL_SIG(Top__DOT__mem__DOT__memory___05FT_49_data,31,0); + VL_SIG(Top__DOT__mem__DOT___GEN_14,31,0); + VL_SIG64(Top__DOT__cpu__DOT__alu__DOT___GEN_10,62,0); + VL_SIG(Top__DOT__mem__DOT__memory[16384],31,0); + + // LOCAL VARIABLES + // Internals; generally not touched by application code + VL_SIG8(__Vclklast__TOP__clock,0,0); + + // INTERNAL VARIABLES + // Internals; generally not touched by application code + VTop__Syms* __VlSymsp; // Symbol table + + // PARAMETERS + // Parameters marked /*verilator public*/ for use by application code + + // CONSTRUCTORS + private: + VTop& operator= (const VTop&); ///< Copying not allowed + VTop(const VTop&); ///< Copying not allowed + public: + /// Construct the model; called by application code + /// The special name may be used to make a wrapper with a + /// single model invisible WRT DPI scope names. + VTop(const char* name="TOP"); + /// Destroy the model; called (often implicitly) by application code + ~VTop(); + + // API METHODS + /// Evaluate the model. Application must call when inputs change. + void eval(); + /// Simulation complete, run final blocks. Application must call on completion. + void final(); + + // INTERNAL METHODS + private: + static void _eval_initial_loop(VTop__Syms* __restrict vlSymsp); + public: + void __Vconfigure(VTop__Syms* symsp, bool first); + private: + static QData _change_request(VTop__Syms* __restrict vlSymsp); + void _ctor_var_reset(); + public: + static void _eval(VTop__Syms* __restrict vlSymsp); + private: +#ifdef VL_DEBUG + void _eval_debug_assertions(); +#endif // VL_DEBUG + public: + static void _eval_initial(VTop__Syms* __restrict vlSymsp); + static void _eval_settle(VTop__Syms* __restrict vlSymsp); + static void _initial__TOP__1(VTop__Syms* __restrict vlSymsp); + static void _sequent__TOP__2(VTop__Syms* __restrict vlSymsp); + static void _settle__TOP__3(VTop__Syms* __restrict vlSymsp); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/src/verilog/obj_dir/VTop.mk b/src/verilog/obj_dir/VTop.mk new file mode 100644 index 00000000..d3f88421 --- /dev/null +++ b/src/verilog/obj_dir/VTop.mk @@ -0,0 +1,66 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable +# +# Execute this makefile from the object directory: +# make -f VTop.mk + +default: VTop + +### Constants... +# Perl executable (from $PERL) +PERL = perl +# Path to Verilator kit (from $VERILATOR_ROOT) +VERILATOR_ROOT = /usr/share/verilator +# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) +SYSTEMC_INCLUDE ?= +# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) +SYSTEMC_LIBDIR ?= + +### Switches... +# SystemC output mode? 0/1 (from --sc) +VM_SC = 0 +# Legacy or SystemC output mode? 0/1 (from --sc) +VM_SP_OR_SC = $(VM_SC) +# Deprecated +VM_PCLI = 1 +# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) +VM_SC_TARGET_ARCH = linux + +### Vars... +# Design prefix (from --prefix) +VM_PREFIX = VTop +# Module prefix (from --prefix) +VM_MODPREFIX = VTop +# User CFLAGS (from -CFLAGS on Verilator command line) +VM_USER_CFLAGS = \ + +# User LDLIBS (from -LDFLAGS on Verilator command line) +VM_USER_LDLIBS = \ + +# User .cpp files (from .cpp's on Verilator command line) +VM_USER_CLASSES = \ + testbench \ + +# User .cpp directories (from .cpp's on Verilator command line) +VM_USER_DIR = \ + . \ + + +### Default rules... +# Include list of all generated classes +include VTop_classes.mk +# Include global rules +include $(VERILATOR_ROOT)/include/verilated.mk + +### Executable rules... (from --exe) +VPATH += $(VM_USER_DIR) + +testbench.o: testbench.cpp + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< + +### Link rules... (from --exe) +VTop: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a + $(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) 2>&1 | c++filt + + +# Verilated -*- Makefile -*- diff --git a/src/verilog/obj_dir/VTop__ALLcls.cpp b/src/verilog/obj_dir/VTop__ALLcls.cpp new file mode 100644 index 00000000..22511a67 --- /dev/null +++ b/src/verilog/obj_dir/VTop__ALLcls.cpp @@ -0,0 +1,3 @@ +// DESCRIPTION: Generated by verilator_includer via makefile +#define VL_INCLUDE_OPT include +#include "VTop.cpp" diff --git a/src/verilog/obj_dir/VTop__ALLcls.d b/src/verilog/obj_dir/VTop__ALLcls.d new file mode 100644 index 00000000..e0058e71 --- /dev/null +++ b/src/verilog/obj_dir/VTop__ALLcls.d @@ -0,0 +1,5 @@ +VTop__ALLcls.o: VTop__ALLcls.cpp VTop.cpp VTop.h \ + /usr/share/verilator/include/verilated_heavy.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilatedos.h VTop__Syms.h diff --git a/src/verilog/obj_dir/VTop__ALLsup.cpp b/src/verilog/obj_dir/VTop__ALLsup.cpp new file mode 100644 index 00000000..2aa533ee --- /dev/null +++ b/src/verilog/obj_dir/VTop__ALLsup.cpp @@ -0,0 +1,3 @@ +// DESCRIPTION: Generated by verilator_includer via makefile +#define VL_INCLUDE_OPT include +#include "VTop__Syms.cpp" diff --git a/src/verilog/obj_dir/VTop__ALLsup.d b/src/verilog/obj_dir/VTop__ALLsup.d new file mode 100644 index 00000000..cf982fbd --- /dev/null +++ b/src/verilog/obj_dir/VTop__ALLsup.d @@ -0,0 +1,5 @@ +VTop__ALLsup.o: VTop__ALLsup.cpp VTop__Syms.cpp VTop__Syms.h \ + /usr/share/verilator/include/verilated_heavy.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilatedos.h VTop.h diff --git a/src/verilog/obj_dir/VTop__Syms.cpp b/src/verilog/obj_dir/VTop__Syms.cpp new file mode 100644 index 00000000..8d3e9168 --- /dev/null +++ b/src/verilog/obj_dir/VTop__Syms.cpp @@ -0,0 +1,21 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table implementation internals + +#include "VTop__Syms.h" +#include "VTop.h" + +// FUNCTIONS +VTop__Syms::VTop__Syms(VTop* topp, const char* namep) + // Setup locals + : __Vm_namep(namep) + , __Vm_didInit(false) + // Setup submodule names +{ + // Pointer to top level + TOPp = topp; + // Setup each module's pointers to their submodules + // Setup each module's pointer back to symbol table (for public functions) + TOPp->__Vconfigure(this, true); + // Setup scope names + __Vscope_Top__mem.configure(this,name(),"Top.mem"); +} diff --git a/src/verilog/obj_dir/VTop__Syms.h b/src/verilog/obj_dir/VTop__Syms.h new file mode 100644 index 00000000..7ce62123 --- /dev/null +++ b/src/verilog/obj_dir/VTop__Syms.h @@ -0,0 +1,37 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table internal header +// +// Internal details; most calling programs do not need this header + +#ifndef _VTop__Syms_H_ +#define _VTop__Syms_H_ + +#include "verilated_heavy.h" + +// INCLUDE MODULE CLASSES +#include "VTop.h" + +// SYMS CLASS +class VTop__Syms : public VerilatedSyms { + public: + + // LOCAL STATE + const char* __Vm_namep; + bool __Vm_didInit; + + // SUBCELL STATE + VTop* TOPp; + + // SCOPE NAMES + VerilatedScope __Vscope_Top__mem; + + // CREATORS + VTop__Syms(VTop* topp, const char* namep); + ~VTop__Syms() {} + + // METHODS + inline const char* name() { return __Vm_namep; } + +} VL_ATTR_ALIGNED(64); + +#endif // guard diff --git a/src/verilog/obj_dir/VTop__ver.d b/src/verilog/obj_dir/VTop__ver.d new file mode 100644 index 00000000..e6618c98 --- /dev/null +++ b/src/verilog/obj_dir/VTop__ver.d @@ -0,0 +1 @@ +obj_dir/VTop.cpp obj_dir/VTop.h obj_dir/VTop.mk obj_dir/VTop__Syms.cpp obj_dir/VTop__Syms.h obj_dir/VTop__ver.d obj_dir/VTop_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin Top.v diff --git a/src/verilog/obj_dir/VTop__verFiles.dat b/src/verilog/obj_dir/VTop__verFiles.dat new file mode 100644 index 00000000..090b1097 --- /dev/null +++ b/src/verilog/obj_dir/VTop__verFiles.dat @@ -0,0 +1,12 @@ +# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. +C "--cc Top.v --exe testbench.cpp" +S 5279832 27263155 1541808233 963237689 1519110675 0 "/usr/bin/verilator_bin" +S 64006 10630799 1554939392 89651087 1554938775 745850810 "Top.v" +T 81093 11144428 1554939420 685597879 1554939420 685597879 "obj_dir/VTop.cpp" +T 5774 11144427 1554939420 685597879 1554939420 685597879 "obj_dir/VTop.h" +T 1753 11144430 1554939420 685597879 1554939420 685597879 "obj_dir/VTop.mk" +T 596 11144426 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__Syms.cpp" +T 758 11144425 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__Syms.h" +T 194 11144431 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__ver.d" +T 0 0 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__verFiles.dat" +T 1150 11144429 1554939420 685597879 1554939420 685597879 "obj_dir/VTop_classes.mk" diff --git a/src/verilog/obj_dir/VTop_classes.mk b/src/verilog/obj_dir/VTop_classes.mk new file mode 100644 index 00000000..4e59be86 --- /dev/null +++ b/src/verilog/obj_dir/VTop_classes.mk @@ -0,0 +1,38 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Make include file with class lists +# +# This file lists generated Verilated files, for including in higher level makefiles. +# See VTop.mk for the caller. + +### Switches... +# Coverage output mode? 0/1 (from --coverage) +VM_COVERAGE = 0 +# Threaded output mode? 0/1/N threads (from --threads) +VM_THREADS = 0 +# Tracing output mode? 0/1 (from --trace) +VM_TRACE = 0 + +### Object file lists... +# Generated module classes, fast-path, compile with highest optimization +VM_CLASSES_FAST += \ + VTop \ + +# Generated module classes, non-fast-path, compile with low/medium optimization +VM_CLASSES_SLOW += \ + +# Generated support classes, fast-path, compile with highest optimization +VM_SUPPORT_FAST += \ + +# Generated support classes, non-fast-path, compile with low/medium optimization +VM_SUPPORT_SLOW += \ + VTop__Syms \ + +# Global classes, need linked once per executable, fast-path, compile with highest optimization +VM_GLOBAL_FAST += \ + verilated \ + +# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization +VM_GLOBAL_SLOW += \ + + +# Verilated -*- Makefile -*- diff --git a/src/verilog/obj_dir/testbench.d b/src/verilog/obj_dir/testbench.d new file mode 100644 index 00000000..984246f0 --- /dev/null +++ b/src/verilog/obj_dir/testbench.d @@ -0,0 +1,6 @@ +testbench.o: ../testbench.cpp VTop.h \ + /usr/share/verilator/include/verilated_heavy.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated.h diff --git a/src/verilog/obj_dir/verilated.d b/src/verilog/obj_dir/verilated.d new file mode 100644 index 00000000..378ca2d9 --- /dev/null +++ b/src/verilog/obj_dir/verilated.d @@ -0,0 +1,7 @@ +verilated.o: /usr/share/verilator/include/verilated.cpp \ + /usr/share/verilator/include/verilated_imp.h \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilated_heavy.h \ + /usr/share/verilator/include/verilated_syms.h diff --git a/src/verilog/testbench.cpp b/src/verilog/testbench.cpp new file mode 100644 index 00000000..05a0db31 --- /dev/null +++ b/src/verilog/testbench.cpp @@ -0,0 +1,33 @@ +#include "VTop.h" +#include + vluint64_t main_time = 0; // Current simulation time + // This is a 64-bit integer to reduce wrap over issues and + // allow modulus. You can also use a double, if you wish. + + double sc_time_stamp () { // Called by $time in Verilog + return main_time; // converts to double, to match + // what SystemC does + } + + +int main(int argc, char** argv, char** env){ + Verilated::commandArgs(argc, argv); + VTop* top = new VTop; + //reset + top->reset = 1; + top->clock = 0; + top->eval(); + top->clock = 1; + top->eval(); + top->reset = 0; + + while(!Verilated::gotFinish()){ + top->clock = 0; + top->eval(); + + top->clock = 1; + top->eval(); + } + delete top; + exit(0); +} From 491c5630acbb893ba932f8ddae0f35160e5131e9 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 1 May 2019 20:30:40 -0700 Subject: [PATCH 28/57] cleaned generated verilog and verilator --- src/verilog/Top.DualPortedMemory.memory.v | 20 - src/verilog/obj_dir/VTop | Bin 219584 -> 0 bytes src/verilog/obj_dir/VTop.cpp | 2181 --------------------- src/verilog/obj_dir/VTop.h | 136 -- src/verilog/obj_dir/VTop.mk | 66 - src/verilog/obj_dir/VTop__ALLcls.cpp | 3 - src/verilog/obj_dir/VTop__ALLcls.d | 5 - src/verilog/obj_dir/VTop__ALLsup.cpp | 3 - src/verilog/obj_dir/VTop__ALLsup.d | 5 - src/verilog/obj_dir/VTop__Syms.cpp | 21 - src/verilog/obj_dir/VTop__Syms.h | 37 - src/verilog/obj_dir/VTop__ver.d | 1 - src/verilog/obj_dir/VTop__verFiles.dat | 12 - src/verilog/obj_dir/VTop_classes.mk | 38 - src/verilog/obj_dir/testbench.d | 6 - src/verilog/obj_dir/verilated.d | 7 - 16 files changed, 2541 deletions(-) delete mode 100644 src/verilog/Top.DualPortedMemory.memory.v delete mode 100755 src/verilog/obj_dir/VTop delete mode 100644 src/verilog/obj_dir/VTop.cpp delete mode 100644 src/verilog/obj_dir/VTop.h delete mode 100644 src/verilog/obj_dir/VTop.mk delete mode 100644 src/verilog/obj_dir/VTop__ALLcls.cpp delete mode 100644 src/verilog/obj_dir/VTop__ALLcls.d delete mode 100644 src/verilog/obj_dir/VTop__ALLsup.cpp delete mode 100644 src/verilog/obj_dir/VTop__ALLsup.d delete mode 100644 src/verilog/obj_dir/VTop__Syms.cpp delete mode 100644 src/verilog/obj_dir/VTop__Syms.h delete mode 100644 src/verilog/obj_dir/VTop__ver.d delete mode 100644 src/verilog/obj_dir/VTop__verFiles.dat delete mode 100644 src/verilog/obj_dir/VTop_classes.mk delete mode 100644 src/verilog/obj_dir/testbench.d delete mode 100644 src/verilog/obj_dir/verilated.d diff --git a/src/verilog/Top.DualPortedMemory.memory.v b/src/verilog/Top.DualPortedMemory.memory.v deleted file mode 100644 index a41466f6..00000000 --- a/src/verilog/Top.DualPortedMemory.memory.v +++ /dev/null @@ -1,20 +0,0 @@ -module BindsTo_0_DualPortedMemory( - input clock, - input reset, - input [31:0] io_imem_address, - output [31:0] io_imem_instruction, - input [31:0] io_dmem_address, - input [31:0] io_dmem_writedata, - input io_dmem_memread, - input io_dmem_memwrite, - input [1:0] io_dmem_maskmode, - input io_dmem_sext, - output [31:0] io_dmem_readdata -); - -initial begin - $readmemh("test", DualPortedMemory.memory); -end - endmodule - -bind DualPortedMemory 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z-u<6>S?{;k?|BdOzNUVO`)A>w@V0#3zT-Z;YK!>oZJ%$izenj^@Xy}g#{1iL)cb8Y zLlpnn@Amo^V0LUtnZtSi;kM}WAC@u zmw>tVr)KN@DL&YaQ**O(zx}=~ZWdbh`SW=HT;4zLVp~$L^WtAqufhHD{6-JA_aETl zQdU0h)q6$r`w_PO?>AplqKESMXW!etmy8cvcP**^A3LH{?|R%tqvu+5SNxH5|3OD8 NI@?y1H+WxD{}0teW&i*H diff --git a/src/verilog/obj_dir/VTop.cpp b/src/verilog/obj_dir/VTop.cpp deleted file mode 100644 index 5aa4cf83..00000000 --- a/src/verilog/obj_dir/VTop.cpp +++ /dev/null @@ -1,2181 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See VTop.h for the primary calling header - -#include "VTop.h" // For This -#include "VTop__Syms.h" - - -//-------------------- -// STATIC VARIABLES - - -//-------------------- - -VL_CTOR_IMP(VTop) { - VTop__Syms* __restrict vlSymsp = __VlSymsp = new VTop__Syms(this, name()); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Reset internal values - - // Reset structure values - _ctor_var_reset(); -} - -void VTop::__Vconfigure(VTop__Syms* vlSymsp, bool first) { - if (0 && first) {} // Prevent unused - this->__VlSymsp = vlSymsp; -} - -VTop::~VTop() { - delete __VlSymsp; __VlSymsp=NULL; -} - -//-------------------- - - -void VTop::eval() { - VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VTop::eval\n"); ); - VTop__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; -#ifdef VL_DEBUG - // Debug assertions - _eval_debug_assertions(); -#endif // VL_DEBUG - // Initialize - if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); - // Evaluate till stable - int __VclockLoop = 0; - QData __Vchange = 1; - while (VL_LIKELY(__Vchange)) { - VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); - _eval(vlSymsp); - __Vchange = _change_request(vlSymsp); - if (VL_UNLIKELY(++__VclockLoop > 100)) VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge"); - } -} - -void VTop::_eval_initial_loop(VTop__Syms* __restrict vlSymsp) { - vlSymsp->__Vm_didInit = true; - _eval_initial(vlSymsp); - int __VclockLoop = 0; - QData __Vchange = 1; - while (VL_LIKELY(__Vchange)) { - _eval_settle(vlSymsp); - _eval(vlSymsp); - __Vchange = _change_request(vlSymsp); - if (VL_UNLIKELY(++__VclockLoop > 100)) VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge"); - } -} - -//-------------------- -// Internal Methods - -void VTop::_initial__TOP__1(VTop__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_initial__TOP__1\n"); ); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - // INITIAL at Top.v:1440 - vlTOPp->io_success = 0U; -} - -VL_INLINE_OPT void VTop::_sequent__TOP__2(VTop__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_sequent__TOP__2\n"); ); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Variables - VL_SIG8(__Vdlyvset__Top__DOT__mem__DOT__memory__v0,0,0); - VL_SIG8(__Vdlyvset__Top__DOT__mem__DOT__memory__v1,0,0); - VL_SIG16(__Vdlyvdim0__Top__DOT__mem__DOT__memory__v0,13,0); - VL_SIG16(__Vdlyvdim0__Top__DOT__mem__DOT__memory__v1,13,0); - VL_SIG(__Vdlyvval__Top__DOT__mem__DOT__memory__v0,31,0); - VL_SIG(__Vdlyvval__Top__DOT__mem__DOT__memory__v1,31,0); - VL_SIGW(__Vtemp1,95,0,3); - VL_SIGW(__Vtemp2,95,0,3); - VL_SIGW(__Vtemp3,95,0,3); - VL_SIGW(__Vtemp5,95,0,3); - VL_SIGW(__Vtemp6,95,0,3); - VL_SIGW(__Vtemp7,95,0,3); - VL_SIGW(__Vtemp8,95,0,3); - VL_SIGW(__Vtemp9,95,0,3); - VL_SIGW(__Vtemp15,95,0,3); - VL_SIGW(__Vtemp16,95,0,3); - // Body - // ALWAYS at Top.v:1335 - if (VL_UNLIKELY((((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & (3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))) - & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) - | (IData)(vlTOPp->reset)))))) { - VL_FWRITEF(0x80000002U,"Assertion failed\n at memory.scala:70 assert(io.dmem.address < size.U)\n"); - } - if (VL_UNLIKELY((((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & (3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))) - & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) - | (IData)(vlTOPp->reset)))))) { - VL_WRITEF("[%0t] %%Error: Top.v:1357: Assertion failed in %NTop.mem\n", - 64,VL_TIME_Q(),vlSymsp->name()); - VL_STOP_MT("Top.v",1357,""); - } - if (VL_UNLIKELY(((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) - & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) - | (IData)(vlTOPp->reset)))))) { - VL_FWRITEF(0x80000002U,"Assertion failed\n at memory.scala:99 assert(io.dmem.address < size.U)\n"); - } - if (VL_UNLIKELY(((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) - & (~ ((0x10000U > (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) - | (IData)(vlTOPp->reset)))))) { - VL_WRITEF("[%0t] %%Error: Top.v:1379: Assertion failed in %NTop.mem\n", - 64,VL_TIME_Q(),vlSymsp->name()); - VL_STOP_MT("Top.v",1379,""); - } - __Vdlyvset__Top__DOT__mem__DOT__memory__v0 = 0U; - __Vdlyvset__Top__DOT__mem__DOT__memory__v1 = 0U; - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((1U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((2U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((3U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((4U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((5U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((6U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((7U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((8U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((9U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0xaU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0xbU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0xcU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0xdU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0xeU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0xfU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x10U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x11U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x12U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x13U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x14U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x15U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x16U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x17U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x18U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x19U == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:490 - if (vlTOPp->Top__DOT__cpu__DOT__registers_io_wen) { - if ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) { - vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata; - } - } - // ALWAYS at Top.v:1136 - vlTOPp->Top__DOT__cpu__DOT__pc = ((IData)(vlTOPp->reset) - ? 0U : (((((0U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? - (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - == vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) - : - ((1U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? - (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - != vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) - : - ((4U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? - VL_LTS_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) - : - ((5U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? - VL_GTES_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) - : - ((6U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? - (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - < vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2) - : - (vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - >= vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2)))))) - & ((0x33U - != - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U - != - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((3U - != - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x23U - != - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & (0x63U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction))))))) - | (2U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_jump))) - ? vlTOPp->Top__DOT__cpu__DOT__branchAdd_io_result - : ( - (3U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_jump)) - ? - (0xfffffffeU - & (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10)) - : - ((IData)(4U) - + vlTOPp->Top__DOT__cpu__DOT__pcPlusFour_io_inputx)))); - // ALWAYS at Top.v:1335 - if (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) - & (2U != (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))))) { - VL_EXTEND_WI(71,32, __Vtemp1, vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data); - __Vtemp2[0U] = 0xffU; - __Vtemp2[1U] = 0U; - __Vtemp2[2U] = 0U; - VL_SHIFTL_WWI(71,71,6, __Vtemp3, __Vtemp2, - (0x18U & ((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10) - << 3U))); - __Vtemp5[0U] = (__Vtemp1[0U] & (~ __Vtemp3[0U])); - __Vtemp5[1U] = (__Vtemp1[1U] & (~ __Vtemp3[1U])); - __Vtemp5[2U] = (__Vtemp1[2U] & (~ __Vtemp3[2U])); - VL_EXTEND_WW(79,71, __Vtemp6, __Vtemp5); - VL_EXTEND_WI(79,32, __Vtemp7, vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data); - __Vtemp8[0U] = 0xffffU; - __Vtemp8[1U] = 0U; - __Vtemp8[2U] = 0U; - VL_SHIFTL_WWI(79,79,6, __Vtemp9, __Vtemp8, - (0x18U & ((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10) - << 3U))); - VL_EXTEND_WI(95,32, __Vtemp15, vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2); - VL_SHIFTL_WWI(95,95,6, __Vtemp16, __Vtemp15, - (0x18U & ((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10) - << 3U))); - __Vdlyvval__Top__DOT__mem__DOT__memory__v0 - = (((0U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? __Vtemp6[0U] - : (__Vtemp7[0U] & (~ __Vtemp9[0U]))) - | __Vtemp16[0U]); - __Vdlyvset__Top__DOT__mem__DOT__memory__v0 = 1U; - __Vdlyvdim0__Top__DOT__mem__DOT__memory__v0 - = (0x3fffU & (IData)((vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U))); - } - if (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite) - & (2U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))))) { - __Vdlyvval__Top__DOT__mem__DOT__memory__v1 - = vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2; - __Vdlyvset__Top__DOT__mem__DOT__memory__v1 = 1U; - __Vdlyvdim0__Top__DOT__mem__DOT__memory__v1 - = (0x3fffU & (IData)((vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U))); - } - // ALWAYSPOST at Top.v:1336 - if (__Vdlyvset__Top__DOT__mem__DOT__memory__v0) { - vlTOPp->Top__DOT__mem__DOT__memory[__Vdlyvdim0__Top__DOT__mem__DOT__memory__v0] - = __Vdlyvval__Top__DOT__mem__DOT__memory__v0; - } - if (__Vdlyvset__Top__DOT__mem__DOT__memory__v1) { - vlTOPp->Top__DOT__mem__DOT__memory[__Vdlyvdim0__Top__DOT__mem__DOT__memory__v1] - = __Vdlyvval__Top__DOT__mem__DOT__memory__v1; - } - vlTOPp->Top__DOT__cpu__DOT__pcPlusFour_io_inputx - = vlTOPp->Top__DOT__cpu__DOT__pc; - vlTOPp->Top__DOT__mem_io_imem_instruction = ((0x10000U - <= vlTOPp->Top__DOT__cpu__DOT__pc) - ? 0U - : - vlTOPp->Top__DOT__mem__DOT__memory - [(0x3fffU - & (vlTOPp->Top__DOT__cpu__DOT__pc - >> 2U))]); - vlTOPp->Top__DOT__cpu__DOT__registers_io_wen = - (((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x23U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | (0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))) - & (0U != (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))); - vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite - = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((3U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & (0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_jump = ( - (0x33U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x13U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((3U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x23U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x63U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x37U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x17U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x6fU - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : - ((0x67U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 3U - : 0U))))))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_toreg = - ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 1U : ((0x23U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x63U - == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : - ((0x37U - == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : ((0x17U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x6fU - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : - ((0x67U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : 3U))))))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1 - = ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x23U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x63U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : ( - (0x37U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 1U - : - ((0x17U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : - (0x6fU - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction))))))))); - vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 - : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 - : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 - : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 - : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 - : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 - : ((0x19U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 - : ((0x18U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 - : ((0x17U == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 - : ((0x16U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 - : ( - (0x15U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 - : - ((0x14U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 - : - ((0x13U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 - : - ((0x12U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 - : - ((0x11U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 - : - ((0x10U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 - : - ((0xfU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 - : - ((0xeU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 - : - ((0xdU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 - : - ((0xcU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 - : - ((0xbU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 - : - ((0xaU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 - : - ((9U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 - : - ((8U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 - : - ((7U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 - : - ((6U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 - : - ((5U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 - : - ((4U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 - : - ((3U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 - : - ((2U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 - : - ((1U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 - : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); - vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2 - = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 - : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 - : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 - : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 - : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 - : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 - : ((0x19U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 - : ((0x18U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 - : ((0x17U == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 - : ((0x16U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 - : ( - (0x15U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 - : - ((0x14U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 - : - ((0x13U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 - : - ((0x12U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 - : - ((0x11U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 - : - ((0x10U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 - : - ((0xfU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 - : - ((0xeU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 - : - ((0xdU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 - : - ((0xcU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 - : - ((0xbU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 - : - ((0xaU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 - : - ((9U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 - : - ((8U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 - : - ((7U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 - : - ((6U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 - : - ((5U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 - : - ((4U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 - : - ((3U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 - : - ((2U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 - : - ((1U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 - : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_immediate - = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x6fU != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & (0x67U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))); - vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - = ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0xfffffU : 0U) << 0xcU) | (0xfffU & - (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))); - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx = ((0U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) - ? vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - : - ((1U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) - ? 0U - : vlTOPp->Top__DOT__cpu__DOT__pc)); - vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation - = (((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | (0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))) - ? 2U : ((0U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) - | (0U - == - (0x7fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x19U)))) - ? 2U - : 3U) - : ((1U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? 6U - : ((2U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 4U : ((3U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 5U : ((4U == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 9U - : ((5U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? - ((0U - == - (0x7fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x19U))) - ? 7U - : 8U) - : - ((6U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 1U - : - ((7U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 0U - : 0xfU))))))))); - vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm = - ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - : ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - : ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0x7ffU : 0U) << 0x15U) | - ((0x100000U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xbU)) | ((0xff000U - & vlTOPp->Top__DOT__mem_io_imem_instruction) - | ((0x800U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 9U)) - | (0x7feU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U)))))) - : ((0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - : ((0x63U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0x7ffffU : 0U) << 0xdU) - | ((0x1000U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x13U)) - | ((0x800U & (vlTOPp->Top__DOT__mem_io_imem_instruction - << 4U)) - | ((0x7e0U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U)) - | (0x1eU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))))) - : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - : ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? ((((0x80000000U - & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0xfffffU : 0U) - << 0xcU) | ((0xfe0U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U)) - | (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) - : ((0x13U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - : ((0x73U == - (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU)) - : 0U))))))))); - vlTOPp->Top__DOT__cpu__DOT__branchAdd_io_result - = (vlTOPp->Top__DOT__cpu__DOT__pc + vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm); - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy = ((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) - ? vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm - : vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2); - vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3 = (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - | vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy); - vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 = - (VL_ULL(0x7fffffffffffffff) & ((0U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3)) - : ((2U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : ( - (3U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : - ((4U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - VL_LTS_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : - ((5U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - < vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : - ((6U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - ((QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx)) - << - (0x1fU - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) - : (QData)((IData)( - ((7U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - >> - (0x1fU - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) - : - ((8U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - VL_SHIFTRS_III(32,32,5, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, - (0x1fU - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) - : - ((9U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - ^ vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy) - : - ((0xaU - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - (~ vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3) - : 0U)))))))))))))); - vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data - = vlTOPp->Top__DOT__mem__DOT__memory[(0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))]; - vlTOPp->Top__DOT__mem__DOT___GEN_14 = ((2U != (3U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? ((0U - == - (3U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? (0xffU - & vlTOPp->Top__DOT__mem__DOT__memory - [ - (0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))]) - : (0xffffU - & vlTOPp->Top__DOT__mem__DOT__memory - [ - (0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))])) - : vlTOPp->Top__DOT__mem__DOT__memory - [(0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))]); - vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata - = ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) - ? ((0x4000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? vlTOPp->Top__DOT__mem__DOT___GEN_14 - : ((0U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? ((((0x80U - & vlTOPp->Top__DOT__mem__DOT___GEN_14) - ? 0xffffffU - : 0U) - << 8U) - | (0xffU - & vlTOPp->Top__DOT__mem__DOT___GEN_14)) - : ((1U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? ( - (((0x8000U - & vlTOPp->Top__DOT__mem__DOT___GEN_14) - ? 0xffffU - : 0U) - << 0x10U) - | (0xffffU - & vlTOPp->Top__DOT__mem__DOT___GEN_14)) - : vlTOPp->Top__DOT__mem__DOT___GEN_14))) - : ((2U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) - ? ((IData)(4U) + vlTOPp->Top__DOT__cpu__DOT__pc) - : (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10))); -} - -void VTop::_settle__TOP__3(VTop__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_settle__TOP__3\n"); ); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - vlTOPp->Top__DOT__cpu__DOT__pcPlusFour_io_inputx - = vlTOPp->Top__DOT__cpu__DOT__pc; - vlTOPp->Top__DOT__mem_io_imem_instruction = ((0x10000U - <= vlTOPp->Top__DOT__cpu__DOT__pc) - ? 0U - : - vlTOPp->Top__DOT__mem__DOT__memory - [(0x3fffU - & (vlTOPp->Top__DOT__cpu__DOT__pc - >> 2U))]); - vlTOPp->Top__DOT__cpu__DOT__registers_io_wen = - (((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x23U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | (0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))) - & (0U != (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))); - vlTOPp->Top__DOT__cpu__DOT__control_io_memwrite - = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((3U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & (0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_jump = ( - (0x33U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x13U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((3U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x23U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x63U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x37U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x17U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x6fU - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : - ((0x67U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 3U - : 0U))))))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_toreg = - ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 1U : ((0x23U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x63U - == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : - ((0x37U - == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : ((0x17U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : - ((0x6fU - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : - ((0x67U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : 3U))))))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1 - = ((0x33U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x23U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U : ((0x63U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 0U - : ( - (0x37U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 1U - : - ((0x17U - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? 2U - : - (0x6fU - == - (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction))))))))); - vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 - : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 - : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 - : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 - : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 - : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 - : ((0x19U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 - : ((0x18U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 - : ((0x17U == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 - : ((0x16U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 - : ( - (0x15U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 - : - ((0x14U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 - : - ((0x13U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 - : - ((0x12U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 - : - ((0x11U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 - : - ((0x10U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 - : - ((0xfU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 - : - ((0xeU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 - : - ((0xdU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 - : - ((0xcU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 - : - ((0xbU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 - : - ((0xaU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 - : - ((9U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 - : - ((8U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 - : - ((7U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 - : - ((6U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 - : - ((5U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 - : - ((4U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 - : - ((3U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 - : - ((2U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 - : - ((1U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 - : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); - vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2 - = ((0x1fU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_31 - : ((0x1eU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_30 - : ((0x1dU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_29 - : ((0x1cU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_28 - : ((0x1bU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_27 - : ((0x1aU == (0x1fU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_26 - : ((0x19U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_25 - : ((0x18U == (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_24 - : ((0x17U == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_23 - : ((0x16U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_22 - : ( - (0x15U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_21 - : - ((0x14U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_20 - : - ((0x13U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_19 - : - ((0x12U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_18 - : - ((0x11U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_17 - : - ((0x10U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_16 - : - ((0xfU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_15 - : - ((0xeU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_14 - : - ((0xdU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_13 - : - ((0xcU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_12 - : - ((0xbU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_11 - : - ((0xaU - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_10 - : - ((9U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_9 - : - ((8U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_8 - : - ((7U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_7 - : - ((6U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_6 - : - ((5U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_5 - : - ((4U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_4 - : - ((3U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_3 - : - ((2U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_2 - : - ((1U - == - (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))) - ? vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_1 - : vlTOPp->Top__DOT__cpu__DOT__registers__DOT__regs_0))))))))))))))))))))))))))))))); - vlTOPp->Top__DOT__cpu__DOT__control_io_immediate - = ((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x6fU != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & (0x67U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))))); - vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - = ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0xfffffU : 0U) << 0xcU) | (0xfffU & - (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U))); - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx = ((0U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) - ? vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata1 - : - ((1U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_alusrc1)) - ? 0U - : vlTOPp->Top__DOT__cpu__DOT__pc)); - vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation - = (((0x33U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x13U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | ((0x63U != (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - & ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - | (0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)))))))) - ? 2U : ((0U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? (((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) - | (0U - == - (0x7fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x19U)))) - ? 2U - : 3U) - : ((1U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? 6U - : ((2U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 4U : ((3U == (7U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 5U : ((4U == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 9U - : ((5U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? - ((0U - == - (0x7fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x19U))) - ? 7U - : 8U) - : - ((6U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 1U - : - ((7U - == - (7U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? 0U - : 0xfU))))))))); - vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm = - ((0x37U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - : ((0x17U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? (0xfffff000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - : ((0x6fU == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0x7ffU : 0U) << 0x15U) | - ((0x100000U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xbU)) | ((0xff000U - & vlTOPp->Top__DOT__mem_io_imem_instruction) - | ((0x800U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 9U)) - | (0x7feU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U)))))) - : ((0x67U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - : ((0x63U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? ((((0x80000000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0x7ffffU : 0U) << 0xdU) - | ((0x1000U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x13U)) - | ((0x800U & (vlTOPp->Top__DOT__mem_io_imem_instruction - << 4U)) - | ((0x7e0U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U)) - | (0x1eU & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))))) - : ((3U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - : ((0x23U == (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? ((((0x80000000U - & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? 0xfffffU : 0U) - << 0xcU) | ((0xfe0U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0x14U)) - | (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 7U)))) - : ((0x13U == (0x7fU - & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? vlTOPp->Top__DOT__cpu__DOT__immGen__DOT___T_26 - : ((0x73U == - (0x7fU & vlTOPp->Top__DOT__mem_io_imem_instruction)) - ? (0x1fU - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xfU)) - : 0U))))))))); - vlTOPp->Top__DOT__cpu__DOT__branchAdd_io_result - = (vlTOPp->Top__DOT__cpu__DOT__pc + vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm); - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy = ((IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_immediate) - ? vlTOPp->Top__DOT__cpu__DOT__immGen_io_sextImm - : vlTOPp->Top__DOT__cpu__DOT__registers_io_readdata2); - vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3 = (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - | vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy); - vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 = - (VL_ULL(0x7fffffffffffffff) & ((0U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3)) - : ((2U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - + vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : ( - (3U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - - vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : - ((4U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - VL_LTS_III(1,32,32, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : - ((5U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? (QData)((IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - < vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy))) - : - ((6U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - ((QData)((IData)(vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx)) - << - (0x1fU - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) - : (QData)((IData)( - ((7U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - >> - (0x1fU - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) - : - ((8U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - VL_SHIFTRS_III(32,32,5, vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx, - (0x1fU - & vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy)) - : - ((9U - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - (vlTOPp->Top__DOT__cpu__DOT__alu_io_inputx - ^ vlTOPp->Top__DOT__cpu__DOT__alu_io_inputy) - : - ((0xaU - == (IData)(vlTOPp->Top__DOT__cpu__DOT__aluControl_io_operation)) - ? - (~ vlTOPp->Top__DOT__cpu__DOT__alu__DOT___T_3) - : 0U)))))))))))))); - vlTOPp->Top__DOT__mem__DOT__memory___05FT_49_data - = vlTOPp->Top__DOT__mem__DOT__memory[(0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))]; - vlTOPp->Top__DOT__mem__DOT___GEN_14 = ((2U != (3U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? ((0U - == - (3U - & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) - ? (0xffU - & vlTOPp->Top__DOT__mem__DOT__memory - [ - (0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))]) - : (0xffffU - & vlTOPp->Top__DOT__mem__DOT__memory - [ - (0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))])) - : vlTOPp->Top__DOT__mem__DOT__memory - [(0x3fffU - & (IData)( - (vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10 - >> 2U)))]); - vlTOPp->Top__DOT__cpu__DOT__registers_io_writedata - = ((1U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) - ? ((0x4000U & vlTOPp->Top__DOT__mem_io_imem_instruction) - ? vlTOPp->Top__DOT__mem__DOT___GEN_14 - : ((0U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? ((((0x80U - & vlTOPp->Top__DOT__mem__DOT___GEN_14) - ? 0xffffffU - : 0U) - << 8U) - | (0xffU - & vlTOPp->Top__DOT__mem__DOT___GEN_14)) - : ((1U == (3U & (vlTOPp->Top__DOT__mem_io_imem_instruction - >> 0xcU))) ? ( - (((0x8000U - & vlTOPp->Top__DOT__mem__DOT___GEN_14) - ? 0xffffU - : 0U) - << 0x10U) - | (0xffffU - & vlTOPp->Top__DOT__mem__DOT___GEN_14)) - : vlTOPp->Top__DOT__mem__DOT___GEN_14))) - : ((2U == (IData)(vlTOPp->Top__DOT__cpu__DOT__control_io_toreg)) - ? ((IData)(4U) + vlTOPp->Top__DOT__cpu__DOT__pc) - : (IData)(vlTOPp->Top__DOT__cpu__DOT__alu__DOT___GEN_10))); -} - -void VTop::_eval(VTop__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval\n"); ); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - if (((IData)(vlTOPp->clock) & (~ (IData)(vlTOPp->__Vclklast__TOP__clock)))) { - vlTOPp->_sequent__TOP__2(vlSymsp); - } - // Final - vlTOPp->__Vclklast__TOP__clock = vlTOPp->clock; -} - -void VTop::_eval_initial(VTop__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval_initial\n"); ); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - vlTOPp->_initial__TOP__1(vlSymsp); -} - -void VTop::final() { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::final\n"); ); - // Variables - VTop__Syms* __restrict vlSymsp = this->__VlSymsp; - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; -} - -void VTop::_eval_settle(VTop__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval_settle\n"); ); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - vlTOPp->_settle__TOP__3(vlSymsp); -} - -VL_INLINE_OPT QData VTop::_change_request(VTop__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_change_request\n"); ); - VTop* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - // Change detection - QData __req = false; // Logically a bool - return __req; -} - -#ifdef VL_DEBUG -void VTop::_eval_debug_assertions() { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_eval_debug_assertions\n"); ); - // Body - if (VL_UNLIKELY((clock & 0xfeU))) { - Verilated::overWidthError("clock");} - if (VL_UNLIKELY((reset & 0xfeU))) { - Verilated::overWidthError("reset");} -} -#endif // VL_DEBUG - -void VTop::_ctor_var_reset() { - VL_DEBUG_IF(VL_DBG_MSGF("+ VTop::_ctor_var_reset\n"); ); - // Body - clock = VL_RAND_RESET_I(1); - reset = VL_RAND_RESET_I(1); - io_success = VL_RAND_RESET_I(1); - Top__DOT__mem_io_imem_instruction = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__control_io_toreg = VL_RAND_RESET_I(2); - Top__DOT__cpu__DOT__control_io_memwrite = VL_RAND_RESET_I(1); - Top__DOT__cpu__DOT__control_io_immediate = VL_RAND_RESET_I(1); - Top__DOT__cpu__DOT__control_io_alusrc1 = VL_RAND_RESET_I(2); - Top__DOT__cpu__DOT__control_io_jump = VL_RAND_RESET_I(2); - Top__DOT__cpu__DOT__registers_io_writedata = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers_io_wen = VL_RAND_RESET_I(1); - Top__DOT__cpu__DOT__registers_io_readdata1 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers_io_readdata2 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__aluControl_io_operation = VL_RAND_RESET_I(4); - Top__DOT__cpu__DOT__alu_io_inputx = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__alu_io_inputy = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__immGen_io_sextImm = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__pcPlusFour_io_inputx = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__branchAdd_io_result = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__pc = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_0 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_1 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_2 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_3 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_4 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_5 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_6 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_7 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_8 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_9 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_10 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_11 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_12 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_13 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_14 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_15 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_16 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_17 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_18 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_19 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_20 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_21 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_22 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_23 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_24 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_25 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_26 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_27 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_28 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_29 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_30 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__registers__DOT__regs_31 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__alu__DOT___T_3 = VL_RAND_RESET_I(32); - Top__DOT__cpu__DOT__alu__DOT___GEN_10 = VL_RAND_RESET_Q(63); - Top__DOT__cpu__DOT__immGen__DOT___T_26 = VL_RAND_RESET_I(32); - { int __Vi0=0; for (; __Vi0<16384; ++__Vi0) { - Top__DOT__mem__DOT__memory[__Vi0] = VL_RAND_RESET_I(32); - }} - Top__DOT__mem__DOT__memory___05FT_49_data = VL_RAND_RESET_I(32); - Top__DOT__mem__DOT___GEN_14 = VL_RAND_RESET_I(32); - __Vclklast__TOP__clock = VL_RAND_RESET_I(1); -} diff --git a/src/verilog/obj_dir/VTop.h b/src/verilog/obj_dir/VTop.h deleted file mode 100644 index 116188ff..00000000 --- a/src/verilog/obj_dir/VTop.h +++ /dev/null @@ -1,136 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Primary design header -// -// This header should be included by all source files instantiating the design. -// The class here is then constructed to instantiate the design. -// See the Verilator manual for examples. - -#ifndef _VTop_H_ -#define _VTop_H_ - -#include "verilated_heavy.h" - -class VTop__Syms; - -//---------- - -VL_MODULE(VTop) { - public: - - // PORTS - // The application code writes and reads these signals to - // propagate new values into/out from the Verilated model. - VL_IN8(clock,0,0); - VL_IN8(reset,0,0); - VL_OUT8(io_success,0,0); - - // LOCAL SIGNALS - // Internals; generally not touched by application code - VL_SIG8(Top__DOT__cpu__DOT__control_io_toreg,1,0); - VL_SIG8(Top__DOT__cpu__DOT__control_io_memwrite,0,0); - VL_SIG8(Top__DOT__cpu__DOT__control_io_immediate,0,0); - VL_SIG8(Top__DOT__cpu__DOT__control_io_alusrc1,1,0); - VL_SIG8(Top__DOT__cpu__DOT__control_io_jump,1,0); - VL_SIG8(Top__DOT__cpu__DOT__registers_io_wen,0,0); - VL_SIG8(Top__DOT__cpu__DOT__aluControl_io_operation,3,0); - VL_SIG(Top__DOT__mem_io_imem_instruction,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers_io_writedata,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers_io_readdata1,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers_io_readdata2,31,0); - VL_SIG(Top__DOT__cpu__DOT__alu_io_inputx,31,0); - VL_SIG(Top__DOT__cpu__DOT__alu_io_inputy,31,0); - VL_SIG(Top__DOT__cpu__DOT__immGen_io_sextImm,31,0); - VL_SIG(Top__DOT__cpu__DOT__pcPlusFour_io_inputx,31,0); - VL_SIG(Top__DOT__cpu__DOT__branchAdd_io_result,31,0); - VL_SIG(Top__DOT__cpu__DOT__pc,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_0,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_1,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_2,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_3,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_4,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_5,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_6,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_7,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_8,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_9,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_10,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_11,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_12,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_13,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_14,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_15,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_16,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_17,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_18,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_19,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_20,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_21,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_22,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_23,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_24,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_25,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_26,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_27,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_28,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_29,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_30,31,0); - VL_SIG(Top__DOT__cpu__DOT__registers__DOT__regs_31,31,0); - VL_SIG(Top__DOT__cpu__DOT__alu__DOT___T_3,31,0); - VL_SIG(Top__DOT__cpu__DOT__immGen__DOT___T_26,31,0); - VL_SIG(Top__DOT__mem__DOT__memory___05FT_49_data,31,0); - VL_SIG(Top__DOT__mem__DOT___GEN_14,31,0); - VL_SIG64(Top__DOT__cpu__DOT__alu__DOT___GEN_10,62,0); - VL_SIG(Top__DOT__mem__DOT__memory[16384],31,0); - - // LOCAL VARIABLES - // Internals; generally not touched by application code - VL_SIG8(__Vclklast__TOP__clock,0,0); - - // INTERNAL VARIABLES - // Internals; generally not touched by application code - VTop__Syms* __VlSymsp; // Symbol table - - // PARAMETERS - // Parameters marked /*verilator public*/ for use by application code - - // CONSTRUCTORS - private: - VTop& operator= (const VTop&); ///< Copying not allowed - VTop(const VTop&); ///< Copying not allowed - public: - /// Construct the model; called by application code - /// The special name may be used to make a wrapper with a - /// single model invisible WRT DPI scope names. - VTop(const char* name="TOP"); - /// Destroy the model; called (often implicitly) by application code - ~VTop(); - - // API METHODS - /// Evaluate the model. Application must call when inputs change. - void eval(); - /// Simulation complete, run final blocks. Application must call on completion. - void final(); - - // INTERNAL METHODS - private: - static void _eval_initial_loop(VTop__Syms* __restrict vlSymsp); - public: - void __Vconfigure(VTop__Syms* symsp, bool first); - private: - static QData _change_request(VTop__Syms* __restrict vlSymsp); - void _ctor_var_reset(); - public: - static void _eval(VTop__Syms* __restrict vlSymsp); - private: -#ifdef VL_DEBUG - void _eval_debug_assertions(); -#endif // VL_DEBUG - public: - static void _eval_initial(VTop__Syms* __restrict vlSymsp); - static void _eval_settle(VTop__Syms* __restrict vlSymsp); - static void _initial__TOP__1(VTop__Syms* __restrict vlSymsp); - static void _sequent__TOP__2(VTop__Syms* __restrict vlSymsp); - static void _settle__TOP__3(VTop__Syms* __restrict vlSymsp); -} VL_ATTR_ALIGNED(128); - -#endif // guard diff --git a/src/verilog/obj_dir/VTop.mk b/src/verilog/obj_dir/VTop.mk deleted file mode 100644 index d3f88421..00000000 --- a/src/verilog/obj_dir/VTop.mk +++ /dev/null @@ -1,66 +0,0 @@ -# Verilated -*- Makefile -*- -# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable -# -# Execute this makefile from the object directory: -# make -f VTop.mk - -default: VTop - -### Constants... -# Perl executable (from $PERL) -PERL = perl -# Path to Verilator kit (from $VERILATOR_ROOT) -VERILATOR_ROOT = /usr/share/verilator -# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) -SYSTEMC_INCLUDE ?= -# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) -SYSTEMC_LIBDIR ?= - -### Switches... -# SystemC output mode? 0/1 (from --sc) -VM_SC = 0 -# Legacy or SystemC output mode? 0/1 (from --sc) -VM_SP_OR_SC = $(VM_SC) -# Deprecated -VM_PCLI = 1 -# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) -VM_SC_TARGET_ARCH = linux - -### Vars... -# Design prefix (from --prefix) -VM_PREFIX = VTop -# Module prefix (from --prefix) -VM_MODPREFIX = VTop -# User CFLAGS (from -CFLAGS on Verilator command line) -VM_USER_CFLAGS = \ - -# User LDLIBS (from -LDFLAGS on Verilator command line) -VM_USER_LDLIBS = \ - -# User .cpp files (from .cpp's on Verilator command line) -VM_USER_CLASSES = \ - testbench \ - -# User .cpp directories (from .cpp's on Verilator command line) -VM_USER_DIR = \ - . \ - - -### Default rules... -# Include list of all generated classes -include VTop_classes.mk -# Include global rules -include $(VERILATOR_ROOT)/include/verilated.mk - -### Executable rules... (from --exe) -VPATH += $(VM_USER_DIR) - -testbench.o: testbench.cpp - $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< - -### Link rules... (from --exe) -VTop: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a - $(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) 2>&1 | c++filt - - -# Verilated -*- Makefile -*- diff --git a/src/verilog/obj_dir/VTop__ALLcls.cpp b/src/verilog/obj_dir/VTop__ALLcls.cpp deleted file mode 100644 index 22511a67..00000000 --- a/src/verilog/obj_dir/VTop__ALLcls.cpp +++ /dev/null @@ -1,3 +0,0 @@ -// DESCRIPTION: Generated by verilator_includer via makefile -#define VL_INCLUDE_OPT include -#include "VTop.cpp" diff --git a/src/verilog/obj_dir/VTop__ALLcls.d b/src/verilog/obj_dir/VTop__ALLcls.d deleted file mode 100644 index e0058e71..00000000 --- a/src/verilog/obj_dir/VTop__ALLcls.d +++ /dev/null @@ -1,5 +0,0 @@ -VTop__ALLcls.o: VTop__ALLcls.cpp VTop.cpp VTop.h \ - /usr/share/verilator/include/verilated_heavy.h \ - /usr/share/verilator/include/verilated.h \ - /usr/share/verilator/include/verilated_config.h \ - /usr/share/verilator/include/verilatedos.h VTop__Syms.h diff --git a/src/verilog/obj_dir/VTop__ALLsup.cpp b/src/verilog/obj_dir/VTop__ALLsup.cpp deleted file mode 100644 index 2aa533ee..00000000 --- a/src/verilog/obj_dir/VTop__ALLsup.cpp +++ /dev/null @@ -1,3 +0,0 @@ -// DESCRIPTION: Generated by verilator_includer via makefile -#define VL_INCLUDE_OPT include -#include "VTop__Syms.cpp" diff --git a/src/verilog/obj_dir/VTop__ALLsup.d b/src/verilog/obj_dir/VTop__ALLsup.d deleted file mode 100644 index cf982fbd..00000000 --- a/src/verilog/obj_dir/VTop__ALLsup.d +++ /dev/null @@ -1,5 +0,0 @@ -VTop__ALLsup.o: VTop__ALLsup.cpp VTop__Syms.cpp VTop__Syms.h \ - /usr/share/verilator/include/verilated_heavy.h \ - /usr/share/verilator/include/verilated.h \ - /usr/share/verilator/include/verilated_config.h \ - /usr/share/verilator/include/verilatedos.h VTop.h diff --git a/src/verilog/obj_dir/VTop__Syms.cpp b/src/verilog/obj_dir/VTop__Syms.cpp deleted file mode 100644 index 8d3e9168..00000000 --- a/src/verilog/obj_dir/VTop__Syms.cpp +++ /dev/null @@ -1,21 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Symbol table implementation internals - -#include "VTop__Syms.h" -#include "VTop.h" - -// FUNCTIONS -VTop__Syms::VTop__Syms(VTop* topp, const char* namep) - // Setup locals - : __Vm_namep(namep) - , __Vm_didInit(false) - // Setup submodule names -{ - // Pointer to top level - TOPp = topp; - // Setup each module's pointers to their submodules - // Setup each module's pointer back to symbol table (for public functions) - TOPp->__Vconfigure(this, true); - // Setup scope names - __Vscope_Top__mem.configure(this,name(),"Top.mem"); -} diff --git a/src/verilog/obj_dir/VTop__Syms.h b/src/verilog/obj_dir/VTop__Syms.h deleted file mode 100644 index 7ce62123..00000000 --- a/src/verilog/obj_dir/VTop__Syms.h +++ /dev/null @@ -1,37 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Symbol table internal header -// -// Internal details; most calling programs do not need this header - -#ifndef _VTop__Syms_H_ -#define _VTop__Syms_H_ - -#include "verilated_heavy.h" - -// INCLUDE MODULE CLASSES -#include "VTop.h" - -// SYMS CLASS -class VTop__Syms : public VerilatedSyms { - public: - - // LOCAL STATE - const char* __Vm_namep; - bool __Vm_didInit; - - // SUBCELL STATE - VTop* TOPp; - - // SCOPE NAMES - VerilatedScope __Vscope_Top__mem; - - // CREATORS - VTop__Syms(VTop* topp, const char* namep); - ~VTop__Syms() {} - - // METHODS - inline const char* name() { return __Vm_namep; } - -} VL_ATTR_ALIGNED(64); - -#endif // guard diff --git a/src/verilog/obj_dir/VTop__ver.d b/src/verilog/obj_dir/VTop__ver.d deleted file mode 100644 index e6618c98..00000000 --- a/src/verilog/obj_dir/VTop__ver.d +++ /dev/null @@ -1 +0,0 @@ -obj_dir/VTop.cpp obj_dir/VTop.h obj_dir/VTop.mk obj_dir/VTop__Syms.cpp obj_dir/VTop__Syms.h obj_dir/VTop__ver.d obj_dir/VTop_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin Top.v diff --git a/src/verilog/obj_dir/VTop__verFiles.dat b/src/verilog/obj_dir/VTop__verFiles.dat deleted file mode 100644 index 090b1097..00000000 --- a/src/verilog/obj_dir/VTop__verFiles.dat +++ /dev/null @@ -1,12 +0,0 @@ -# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. -C "--cc Top.v --exe testbench.cpp" -S 5279832 27263155 1541808233 963237689 1519110675 0 "/usr/bin/verilator_bin" -S 64006 10630799 1554939392 89651087 1554938775 745850810 "Top.v" -T 81093 11144428 1554939420 685597879 1554939420 685597879 "obj_dir/VTop.cpp" -T 5774 11144427 1554939420 685597879 1554939420 685597879 "obj_dir/VTop.h" -T 1753 11144430 1554939420 685597879 1554939420 685597879 "obj_dir/VTop.mk" -T 596 11144426 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__Syms.cpp" -T 758 11144425 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__Syms.h" -T 194 11144431 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__ver.d" -T 0 0 1554939420 685597879 1554939420 685597879 "obj_dir/VTop__verFiles.dat" -T 1150 11144429 1554939420 685597879 1554939420 685597879 "obj_dir/VTop_classes.mk" diff --git a/src/verilog/obj_dir/VTop_classes.mk b/src/verilog/obj_dir/VTop_classes.mk deleted file mode 100644 index 4e59be86..00000000 --- a/src/verilog/obj_dir/VTop_classes.mk +++ /dev/null @@ -1,38 +0,0 @@ -# Verilated -*- Makefile -*- -# DESCRIPTION: Verilator output: Make include file with class lists -# -# This file lists generated Verilated files, for including in higher level makefiles. -# See VTop.mk for the caller. - -### Switches... -# Coverage output mode? 0/1 (from --coverage) -VM_COVERAGE = 0 -# Threaded output mode? 0/1/N threads (from --threads) -VM_THREADS = 0 -# Tracing output mode? 0/1 (from --trace) -VM_TRACE = 0 - -### Object file lists... -# Generated module classes, fast-path, compile with highest optimization -VM_CLASSES_FAST += \ - VTop \ - -# Generated module classes, non-fast-path, compile with low/medium optimization -VM_CLASSES_SLOW += \ - -# Generated support classes, fast-path, compile with highest optimization -VM_SUPPORT_FAST += \ - -# Generated support classes, non-fast-path, compile with low/medium optimization -VM_SUPPORT_SLOW += \ - VTop__Syms \ - -# Global classes, need linked once per executable, fast-path, compile with highest optimization -VM_GLOBAL_FAST += \ - verilated \ - -# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization -VM_GLOBAL_SLOW += \ - - -# Verilated -*- Makefile -*- diff --git a/src/verilog/obj_dir/testbench.d b/src/verilog/obj_dir/testbench.d deleted file mode 100644 index 984246f0..00000000 --- a/src/verilog/obj_dir/testbench.d +++ /dev/null @@ -1,6 +0,0 @@ -testbench.o: ../testbench.cpp VTop.h \ - /usr/share/verilator/include/verilated_heavy.h \ - /usr/share/verilator/include/verilated.h \ - /usr/share/verilator/include/verilated_config.h \ - /usr/share/verilator/include/verilatedos.h \ - /usr/share/verilator/include/verilated.h diff --git a/src/verilog/obj_dir/verilated.d b/src/verilog/obj_dir/verilated.d deleted file mode 100644 index 378ca2d9..00000000 --- a/src/verilog/obj_dir/verilated.d +++ /dev/null @@ -1,7 +0,0 @@ -verilated.o: /usr/share/verilator/include/verilated.cpp \ - /usr/share/verilator/include/verilated_imp.h \ - /usr/share/verilator/include/verilatedos.h \ - /usr/share/verilator/include/verilated.h \ - /usr/share/verilator/include/verilated_config.h \ - /usr/share/verilator/include/verilated_heavy.h \ - /usr/share/verilator/include/verilated_syms.h From 8c9df1ab996a5293435e923944dff9e1b8940f30 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 1 May 2019 20:27:55 -0700 Subject: [PATCH 29/57] Delete Top.DualPortedMemory.memory.v --- Top.DualPortedMemory.memory.v | 20 -------------------- 1 file changed, 20 deletions(-) delete mode 100644 Top.DualPortedMemory.memory.v diff --git a/Top.DualPortedMemory.memory.v b/Top.DualPortedMemory.memory.v deleted file mode 100644 index a41466f6..00000000 --- a/Top.DualPortedMemory.memory.v +++ /dev/null @@ -1,20 +0,0 @@ -module BindsTo_0_DualPortedMemory( - input clock, - input reset, - input [31:0] io_imem_address, - output [31:0] io_imem_instruction, - input [31:0] io_dmem_address, - input [31:0] io_dmem_writedata, - input io_dmem_memread, - input io_dmem_memwrite, - input [1:0] io_dmem_maskmode, - input io_dmem_sext, - output [31:0] io_dmem_readdata -); - -initial begin - $readmemh("test", DualPortedMemory.memory); -end - endmodule - -bind DualPortedMemory BindsTo_0_DualPortedMemory BindsTo_0_DualPortedMemory_Inst(.*); \ No newline at end of file From 1245fb5eec6761827c80eecc3bb20680172a0e42 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 1 May 2019 20:28:06 -0700 Subject: [PATCH 30/57] Delete firrtl_black_box_resource_files.f --- firrtl_black_box_resource_files.f | 1 - 1 file changed, 1 deletion(-) delete mode 100644 firrtl_black_box_resource_files.f diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f deleted file mode 100644 index 900ea4d4..00000000 --- a/firrtl_black_box_resource_files.f +++ /dev/null @@ -1 +0,0 @@ -/riscv/Top.DualPortedMemory.memory.v \ No newline at end of file From b749de03569264c9ebc37ba1cab0e203315375c7 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 14 May 2019 18:41:04 -0700 Subject: [PATCH 31/57] removed useless headers in csr, rebuilt binaries for testing --- src/main/scala/components/csr.scala | 10 +- src/main/scala/testing/InstTests.scala | 208 ++++----- src/test/resources/risc-v/Makefile | 2 +- "src/test/resources/risc-v/\\" | 619 +++++++++++++++++++++++++ src/test/resources/risc-v/add0 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/add1 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/add2 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/addfwd | Bin 4592 -> 4784 bytes src/test/resources/risc-v/addi1 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/addi2 | Bin 4560 -> 4752 bytes src/test/resources/risc-v/and | Bin 4552 -> 4748 bytes src/test/resources/risc-v/andi | Bin 4556 -> 4748 bytes src/test/resources/risc-v/auipc0 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/auipc1 | Bin 4560 -> 4752 bytes src/test/resources/risc-v/auipc2 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/auipc3 | Bin 4560 -> 4752 bytes src/test/resources/risc-v/beq | Bin 4648 -> 4840 bytes src/test/resources/risc-v/bge | Bin 4648 -> 4840 bytes src/test/resources/risc-v/bgeu | Bin 4648 -> 4840 bytes src/test/resources/risc-v/blt | Bin 4648 -> 4840 bytes src/test/resources/risc-v/bltu | Bin 4648 -> 4840 bytes src/test/resources/risc-v/bne | Bin 4648 -> 4840 bytes src/test/resources/risc-v/csrrc | Bin 0 -> 4748 bytes src/test/resources/risc-v/csrrc.riscv | 12 + src/test/resources/risc-v/csrrci | Bin 0 -> 4748 bytes src/test/resources/risc-v/csrrci.riscv | 12 + src/test/resources/risc-v/csrrs | Bin 0 -> 4748 bytes src/test/resources/risc-v/csrrs.riscv | 12 + src/test/resources/risc-v/csrrsi | Bin 0 -> 4748 bytes src/test/resources/risc-v/csrrsi.riscv | 12 + src/test/resources/risc-v/csrrw | Bin 0 -> 4748 bytes src/test/resources/risc-v/csrrw.riscv | 12 + src/test/resources/risc-v/csrrwi | Bin 0 -> 4748 bytes src/test/resources/risc-v/csrrwi.riscv | 12 + src/test/resources/risc-v/divider | Bin 5740 -> 5932 bytes src/test/resources/risc-v/fibonacci | Bin 5672 -> 5864 bytes src/test/resources/risc-v/jal | Bin 4604 -> 4796 bytes src/test/resources/risc-v/jalr0 | Bin 4604 -> 4800 bytes src/test/resources/risc-v/jalr1 | Bin 4604 -> 4800 bytes src/test/resources/risc-v/lb | Bin 5620 -> 5812 bytes src/test/resources/risc-v/lb1 | Bin 5620 -> 5812 bytes src/test/resources/risc-v/lbu | Bin 5620 -> 5812 bytes src/test/resources/risc-v/lh | Bin 5620 -> 5812 bytes src/test/resources/risc-v/lh1 | Bin 5620 -> 5812 bytes src/test/resources/risc-v/lhu | Bin 5620 -> 5812 bytes src/test/resources/risc-v/lui0 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/lui1 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/lw1 | Bin 5620 -> 5812 bytes src/test/resources/risc-v/lwfwd | Bin 5620 -> 5816 bytes src/test/resources/risc-v/multiplier | Bin 5672 -> 5864 bytes src/test/resources/risc-v/naturalsum | Bin 5672 -> 5864 bytes src/test/resources/risc-v/oppsign | Bin 4560 -> 4756 bytes src/test/resources/risc-v/or | Bin 4552 -> 4744 bytes src/test/resources/risc-v/ori | Bin 4552 -> 4748 bytes src/test/resources/risc-v/power2 | Bin 4564 -> 4756 bytes src/test/resources/risc-v/rotR | Bin 4568 -> 4760 bytes src/test/resources/risc-v/sb | Bin 5620 -> 5812 bytes src/test/resources/risc-v/sh | Bin 5620 -> 5812 bytes src/test/resources/risc-v/sll | Bin 4552 -> 4748 bytes src/test/resources/risc-v/slli | Bin 4556 -> 4748 bytes src/test/resources/risc-v/slt | Bin 4552 -> 4748 bytes src/test/resources/risc-v/slt1 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/slti | Bin 4556 -> 4748 bytes src/test/resources/risc-v/sltiu | Bin 4556 -> 4748 bytes src/test/resources/risc-v/sltu | Bin 4556 -> 4748 bytes src/test/resources/risc-v/sltu1 | Bin 4556 -> 4748 bytes src/test/resources/risc-v/sort | Bin 5808 -> 6004 bytes src/test/resources/risc-v/sra | Bin 4552 -> 4748 bytes src/test/resources/risc-v/srai | Bin 4556 -> 4748 bytes src/test/resources/risc-v/srl | Bin 4552 -> 4748 bytes src/test/resources/risc-v/srli | Bin 4556 -> 4748 bytes src/test/resources/risc-v/sub | Bin 4552 -> 4748 bytes src/test/resources/risc-v/sw | Bin 5812 -> 5812 bytes src/test/resources/risc-v/sw.riscv | 1 - src/test/resources/risc-v/swapxor | Bin 4564 -> 4760 bytes src/test/resources/risc-v/test | Bin 5644 -> 5836 bytes src/test/resources/risc-v/xor | Bin 4552 -> 4748 bytes src/test/resources/risc-v/xori | Bin 4556 -> 4748 bytes src/test/scala/grading/Lab1Tests.scala | 2 + src/test/scala/grading/Lab2Tests.scala | 76 ++- 80 files changed, 877 insertions(+), 113 deletions(-) create mode 100644 "src/test/resources/risc-v/\\" create mode 100755 src/test/resources/risc-v/csrrc create mode 100644 src/test/resources/risc-v/csrrc.riscv create mode 100755 src/test/resources/risc-v/csrrci create mode 100644 src/test/resources/risc-v/csrrci.riscv create mode 100755 src/test/resources/risc-v/csrrs create mode 100644 src/test/resources/risc-v/csrrs.riscv create mode 100755 src/test/resources/risc-v/csrrsi create mode 100644 src/test/resources/risc-v/csrrsi.riscv create mode 100755 src/test/resources/risc-v/csrrw create mode 100644 src/test/resources/risc-v/csrrw.riscv create mode 100755 src/test/resources/risc-v/csrrwi create mode 100644 src/test/resources/risc-v/csrrwi.riscv diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index a353d112..b4417d26 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -5,8 +5,6 @@ package dinocpu import chisel3._ import collection.mutable.LinkedHashMap import chisel3.util._ -import chisel3.util.BitPat -import chisel3.util.experimental.BoringUtils import Util._ import scala.math._ @@ -221,6 +219,8 @@ object MCSRCmd{ val MPRV = 3 } + +//reorder bundles class CSRRegFileIO extends Bundle{ //val hartid = Input(UInt(32.W)) val rw = new Bundle { @@ -229,7 +229,7 @@ class CSRRegFileIO extends Bundle{ } val csr_stall = Output(Bool())//not needed in single cycle - val eret = Output(Bool())// + val eret = Output(Bool())// change ret names val decode = new Bundle { val inst = Input(UInt(32.W)) // @@ -241,8 +241,8 @@ class CSRRegFileIO extends Bundle{ val status = Output(new MStatus())//not needed in this design but useful if more ISA extensions val evec = Output(UInt(32.W)) // - val exception = Input(Bool()) // - val retire = Input(Bool()) // + val exception = Input(Bool()) // rename to illgl inst + val retire = Input(Bool()) // rename to retire inst val pc = Input(UInt(32.W)) // val time = Output(UInt(32.W))// } diff --git a/src/main/scala/testing/InstTests.scala b/src/main/scala/testing/InstTests.scala index d63bbbf6..dec66e85 100644 --- a/src/main/scala/testing/InstTests.scala +++ b/src/main/scala/testing/InstTests.scala @@ -32,85 +32,85 @@ object InstTests { val rtype = List[CPUTestCase]( CPUTestCase("add1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), CPUTestCase("add2", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 20 -> 5678), Map(0 -> 0, 10 -> 6912), Map(), Map()), CPUTestCase("add0", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 3456), Map(0 -> 0, 5 -> 1234, 6 -> 3456), Map(), Map()), CPUTestCase("or", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 5678), Map(7 -> 5886), Map(), Map()), CPUTestCase("sub", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 5678), Map(7 -> BigInt("FFFFEEA4", 16)), Map(), Map()), CPUTestCase("and", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 5678), Map(7 -> 1026), Map(), Map()), CPUTestCase("xor", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> 1234, 5 -> 5678), Map(5 -> 5678, 7 -> 1234, 6 -> 4860), Map(), Map()), CPUTestCase("slt", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> 1234, 5 -> 5678), Map(5 -> 5678, 7 -> 1234, 6 -> 1), Map(), Map()), CPUTestCase("slt1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> -1, 5 -> 1), Map(5 -> 1, 6 -> 1), Map(), Map()), CPUTestCase("sltu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> -1, 5 -> 1), Map(5 -> 1, 6 -> 0), Map(), Map()), CPUTestCase("sltu1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> 20, 5 -> 100), Map(5 -> 100, 6 -> 1), Map(), Map()), CPUTestCase("sll", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> 32, 5 -> 2), Map(7 -> 32, 5 -> 2, 6 -> 128), Map(), Map()), CPUTestCase("srl", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> 32, 5 -> 2), Map(7 -> 32, 5 -> 2, 6 -> 8), Map(), Map()), CPUTestCase("sra", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(7 -> twoscomp(-2), 5 -> 31), Map(5 -> 31, 6 -> twoscomp(-1)), Map(), Map()) @@ -119,49 +119,49 @@ object InstTests { val rtypeMultiCycle = List[CPUTestCase]( CPUTestCase("addfwd", Map("single-cycle" -> 10, "pipelined" -> 14), - Map(), Map()), + Map(), Map(), Map(5 -> 1, 10 -> 0), Map(5 -> 1, 10 -> 10), Map(), Map()), CPUTestCase("swapxor", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map()), + Map(), Map(), Map(7 -> 5678, 5 -> 1234), Map(5 -> 5678,7->1234), Map(), Map()), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map()), + Map(), Map(), Map(5 -> 512, 6->1), Map(7->1), Map(), Map(), "-512"), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6->1), Map(7->0), Map(), Map(), "-1234"), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map()), + Map(), Map(), Map(5 -> twoscomp(-65536), 6->1), Map(7->0), // This algorithm doesn't work for negative numbers Map(), Map(), "--65536"), CPUTestCase("oppsign", Map("single-cycle" -> 2, "pipelined" -> 7), - Map(), Map()), + Map(), Map(), Map(5 -> 512, 6->twoscomp(-1024),7->0), Map(7->1), Map(), Map(), "-true"), CPUTestCase("oppsign", Map("single-cycle" -> 2, "pipelined" -> 7), - Map(), Map()), + Map(), Map(), Map(5 -> 512, 6->1024,7->0), Map(7->0), Map(), Map(), "-false"), CPUTestCase("rotR", Map("single-cycle" -> 4, "pipelined" -> 8), - Map(), Map()), + Map(), Map(), Map(5 -> twoscomp(-1), 6->1, 7->32), Map(7->twoscomp(-1)), Map(), Map()) @@ -170,109 +170,109 @@ object InstTests { val itype = List[CPUTestCase]( CPUTestCase("addi1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(0 -> 0, 10 -> 17), Map(), Map()), CPUTestCase("slli", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1), Map(0 -> 0, 5 -> 1, 6 -> 128), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 1024), Map(0 -> 0, 5 -> 1024, 6 -> 8), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> twoscomp(-1024)), Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), Map(), Map(), "-negative"), CPUTestCase("srli", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 128), Map(0 -> 0, 5 -> 128, 6 -> 1), Map(), Map()), CPUTestCase("andi", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 200), Map(), Map()), CPUTestCase("ori", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 511), Map(), Map()), CPUTestCase("xori", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 311), Map(), Map()), CPUTestCase("slti", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1),6->1), Map(), Map()), CPUTestCase("sltiu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), - Map(), Map()) + Map(), Map()), CPUTestCase("csrrc", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), - Map(), Map()) + Map(), Map()), CPUTestCase("csrrci", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), - Map(), Map()) + Map(), Map()), CPUTestCase("csrrs", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), - Map(), Map()) + Map(), Map()), CPUTestCase("csrrsi", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), - Map(), Map()) + Map(), Map()), CPUTestCase("csrrw", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), - Map(), Map()) + Map(), Map()), CPUTestCase("csrrwi", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), - Map(), Map()) + Map(), Map()), CPUTestCase("ecall", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), - Map(), Map()) + Map(), Map()), CPUTestCase("ebreak", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(), Map(), Map()) @@ -281,7 +281,7 @@ object InstTests { val itypeMultiCycle = List[CPUTestCase]( CPUTestCase("addi2", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map()), + Map(), Map(), Map(), Map(0 -> 0, 10 -> 17, 11 -> 93), Map(), Map()) @@ -290,109 +290,109 @@ object InstTests { val branch = List[CPUTestCase]( CPUTestCase("beq", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-False"), CPUTestCase("beq", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-True"), CPUTestCase("bne", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("bne", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-True"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-False-equal"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-True"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), Map(), Map(), "-False-signed"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), Map(), Map(), "-True-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-False"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(), Map(), "-True"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), Map(), Map(), "-False-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), Map(), Map(), "-True-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-True-equal"), CPUTestCase("bltu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("bltu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(), Map(), "-True"), CPUTestCase("bgeu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(), Map(), "-False"), CPUTestCase("bgeu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(), Map(), "-True") @@ -414,61 +414,61 @@ object InstTests { val memory = List[CPUTestCase]( CPUTestCase("lw1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(5 -> BigInt("ffffffff", 16)), Map(), Map()), CPUTestCase("lb", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(5 -> BigInt("04", 16)), Map(), Map()), CPUTestCase("lh", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(5 -> BigInt("0304", 16)), Map(), Map()), CPUTestCase("lbu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(5 -> BigInt("f4", 16)), Map(), Map()), CPUTestCase("lhu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(5 -> BigInt("f3f4", 16)), Map(), Map()), CPUTestCase("lb1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(5 -> BigInt("fffffff4", 16)), Map(), Map()), CPUTestCase("lh1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(), Map(5 -> BigInt("fffff3f4", 16)), Map(), Map()), CPUTestCase("sw", Map("single-cycle" -> 6, "pipelined" -> 10), - Map(), Map()), + Map(), Map(), Map(5 -> 1234), Map(6 -> 1234), Map(), Map(0x100 -> 1234)), CPUTestCase("sb", Map("single-cycle" -> 6, "pipelined" -> 10), - Map(), Map()), + Map(), Map(), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffffff01", 16))), CPUTestCase("sh", Map("single-cycle" -> 6, "pipelined" -> 10), - Map(), Map()), + Map(), Map(), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffff0001", 16))) @@ -477,7 +477,7 @@ object InstTests { val memoryMultiCycle = List[CPUTestCase]( CPUTestCase("lwfwd", Map("single-cycle" -> 2, "pipelined" -> 7), - Map(), Map()), + Map(), Map(), Map(5 -> BigInt("ffffffff", 16), 10 -> 5), Map(5 -> 1, 10 -> 6), Map(), Map()), @@ -496,37 +496,37 @@ object InstTests { val utype = List[CPUTestCase]( CPUTestCase("auipc0", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc2", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map()), - Map(10 -> 1234), - Map(10 -> (17 << 12)), - Map(), Map()), - CPUTestCase("lui0", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc1", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map()), + Map(), Map(), Map(10 -> 1234), - Map(10 -> 4), + Map(10 -> (17 << 12)), Map(), Map()), CPUTestCase("auipc3", Map("single-cycle" -> 2, "pipelined" -> 6), + Map(), Map(), + Map(10 -> 1234), + Map(10 -> 4), Map(), Map()), + CPUTestCase("lui0", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()), CPUTestCase("lui1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map()), + Map(), Map(), Map(10 -> 1234), Map(10 -> 4096), Map(), Map()) @@ -535,13 +535,13 @@ object InstTests { val utypeMultiCycle = List[CPUTestCase]( CPUTestCase("auipc1", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map()), + Map(), Map(), Map(10 -> 1234), Map(10 -> 4), Map(), Map()), CPUTestCase("auipc3", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map()), + Map(), Map(), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()) @@ -550,19 +550,19 @@ object InstTests { val jump = List[CPUTestCase]( CPUTestCase("jal", Map("single-cycle" -> 2, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr0", Map("single-cycle" -> 2, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 10 -> 28), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr1", Map("single-cycle" -> 2, "pipelined" -> 9), - Map(), Map()), + Map(), Map(), Map(5 -> 1234, 10 -> 20), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -571,25 +571,25 @@ object InstTests { val smallApplications = List[CPUTestCase]( CPUTestCase("fibonacci", Map("single-cycle" -> 300, "pipelined" -> 1000), - Map(), Map()), + Map(), Map(), Map(6->11), Map(6->11,5->89), Map(), Map()), CPUTestCase("naturalsum", Map("single-cycle" -> 200, "pipelined" -> 500), - Map(), Map()), + Map(), Map(), Map(), Map(5->55), Map(), Map()), CPUTestCase("multiplier", Map("single-cycle" -> 1000, "pipelined" -> 1000), - Map(), Map()), + Map(), Map(), Map(5->23,6->20,8->0x1000), Map(5->23*20), Map(), Map()), CPUTestCase("divider", Map("single-cycle" -> 1000, "pipelined" -> 2000), - Map(), Map()), + Map(), Map(), Map(5->1260,6->30), Map(7->42), Map(), Map()) @@ -598,37 +598,37 @@ object InstTests { val fullApplications = List[CPUTestCase]( CPUTestCase("multiply.riscv", Map("single-cycle" -> 42342, "pipelined" -> 100000), - Map(), Map()), + Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("median.riscv", Map("single-cycle" -> 9433, "pipelined" -> 100000), - Map(), Map()), + Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("qsort.riscv", Map("single-cycle" -> 263290, "pipelined" -> 300000), - Map(), Map()), + Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("rsort.riscv", Map("single-cycle" -> 263290, "pipelined" -> 250000), - Map(), Map()), + Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("towers.riscv", Map("single-cycle" -> 12653, "pipelined" -> 100000), - Map(), Map()), + Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("vvadd.riscv", Map("single-cycle" -> 5484, "pipelined" -> 20000), - Map(), Map()), + Map(), Map(), Map(), Map(10->12345678), Map(), Map()) diff --git a/src/test/resources/risc-v/Makefile b/src/test/resources/risc-v/Makefile index 170b6280..157a74ee 100644 --- a/src/test/resources/risc-v/Makefile +++ b/src/test/resources/risc-v/Makefile @@ -1,5 +1,5 @@ -RISCV ?= /opt/riscv +RISCV ?= /home/nganjehl/riscv-gnu-toolchain RISCVBIN = $(RISCV)/bin SOURCES = $(wildcard *.riscv) diff --git "a/src/test/resources/risc-v/\\" "b/src/test/resources/risc-v/\\" new file mode 100644 index 00000000..71f4c040 --- /dev/null +++ "b/src/test/resources/risc-v/\\" @@ -0,0 +1,619 @@ +// Lists of different instruction test cases for use with different CPU models + +package dinocpu + +/** + * This object contains a set of lists of tests. Each list is a different set of + * instruction types and corresponds to a RISC-V program in resources/risc-v + * + * Each test case looks like: + * - binary to run in src/test/resources/risc-v + * - number of cycles to run for each CPU type + * - initial values for csr registers + * - final values to check for csr registers + * - initial values for registers + * - final values to check for registers + * - initial values for memory + * - final values to check for memory + * - extra name information + */ +object InstTests { + + val maxInt = BigInt("FFFFFFFF", 16) + + def twoscomp(v: BigInt) : BigInt = { + if (v < 0) { + return maxInt + v + 1 + } else { + return v + } + } + + val rtype = List[CPUTestCase]( + CPUTestCase("add1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1234), + Map(0 -> 0, 5 -> 1234, 6 -> 1234), + Map(), Map()), + CPUTestCase("add2", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1234, 20 -> 5678), + Map(0 -> 0, 10 -> 6912), + Map(), Map()), + CPUTestCase("add0", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1234, 6 -> 3456), + Map(0 -> 0, 5 -> 1234, 6 -> 3456), + Map(), Map()), + CPUTestCase("or", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1234, 6 -> 5678), + Map(7 -> 5886), + Map(), Map()), + CPUTestCase("sub", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1234, 6 -> 5678), + Map(7 -> BigInt("FFFFEEA4", 16)), + Map(), Map()), + CPUTestCase("and", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1234, 6 -> 5678), + Map(7 -> 1026), + Map(), Map()), + CPUTestCase("xor", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> 1234, 5 -> 5678), + Map(5 -> 5678, 7 -> 1234, 6 -> 4860), + Map(), Map()), + CPUTestCase("slt", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> 1234, 5 -> 5678), + Map(5 -> 5678, 7 -> 1234, 6 -> 1), + Map(), Map()), + CPUTestCase("slt1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> -1, 5 -> 1), + Map(5 -> 1, 6 -> 1), + Map(), Map()), + CPUTestCase("sltu", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> -1, 5 -> 1), + Map(5 -> 1, 6 -> 0), + Map(), Map()), + CPUTestCase("sltu1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> 20, 5 -> 100), + Map(5 -> 100, 6 -> 1), + Map(), Map()), + CPUTestCase("sll", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> 32, 5 -> 2), + Map(7 -> 32, 5 -> 2, 6 -> 128), + Map(), Map()), + CPUTestCase("srl", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> 32, 5 -> 2), + Map(7 -> 32, 5 -> 2, 6 -> 8), + Map(), Map()), + CPUTestCase("sra", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(7 -> twoscomp(-2), 5 -> 31), + Map(5 -> 31, 6 -> twoscomp(-1)), + Map(), Map()) + ) + + val rtypeMultiCycle = List[CPUTestCase]( + CPUTestCase("addfwd", + Map("single-cycle" -> 10, "five-cycle" -> 0, "pipelined" -> 14), + Map(), Map(), + Map(5 -> 1, 10 -> 0), + Map(5 -> 1, 10 -> 10), + Map(), Map()), + CPUTestCase("swapxor", + Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), + Map(), Map(), + Map(7 -> 5678, 5 -> 1234), + Map(5 -> 5678,7->1234), + Map(), Map()), + CPUTestCase("power2", + Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), + Map(), Map(), + Map(5 -> 512, 6->1), + Map(7->1), + Map(), Map(), "-512"), + CPUTestCase("power2", + Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), + Map(), Map(), + Map(5 -> 1234, 6->1), + Map(7->0), + Map(), Map(), "-1234"), + CPUTestCase("power2", + Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), + Map(), Map(), + Map(5 -> twoscomp(-65536), 6->1), + Map(7->0), // This algorithm doesn't work for negative numbers + Map(), Map(), "--65536"), + CPUTestCase("oppsign", + Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), + Map(), Map(), + Map(5 -> 512, 6->twoscomp(-1024),7->0), + Map(7->1), + Map(), Map(), "-true"), + CPUTestCase("oppsign", + Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), + Map(), Map(), + Map(5 -> 512, 6->1024,7->0), + Map(7->0), + Map(), Map(), "-false"), + CPUTestCase("rotR", + Map("single-cycle" -> 4, "five-cycle" -> 0, "pipelined" -> 8), + Map(), Map(), + Map(5 -> twoscomp(-1), 6->1, 7->32), + Map(7->twoscomp(-1)), + Map(), Map()) + ) + + val itype = List[CPUTestCase]( + CPUTestCase("addi1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(0 -> 0, 10 -> 17), + Map(), Map()), + CPUTestCase("slli", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1), + Map(0 -> 0, 5 -> 1, 6 -> 128), + Map(), Map()), + CPUTestCase("srai", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 1024), + Map(0 -> 0, 5 -> 1024, 6 -> 8), + Map(), Map()), + CPUTestCase("srai", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> twoscomp(-1024)), + Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), + Map(), Map(), "-negative"), + CPUTestCase("srli", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 128), + Map(0 -> 0, 5 -> 128, 6 -> 1), + Map(), Map()), + CPUTestCase("andi", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 456), + Map(0 -> 0, 5 -> 456, 6 -> 200), + Map(), Map()), + CPUTestCase("ori", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 456), + Map(0 -> 0, 5 -> 456, 6 -> 511), + Map(), Map()), + CPUTestCase("xori", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> 456), + Map(0 -> 0, 5 -> 456, 6 -> 311), + Map(), Map()), + CPUTestCase("slti", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> twoscomp(-1)), + Map(0 -> 0, 5 -> twoscomp(-1),6->1), + Map(), Map()), + CPUTestCase("sltiu", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(5 -> twoscomp(-1)), + Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), + Map(), Map()) + CPUTestCase("csrrc", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrci", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrs", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrsi", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrw", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + CPUTestCase("csrrwi", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + CPUTestCase("ecall", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + CPUTestCase("ebreak", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + ) + + val itypeMultiCycle = List[CPUTestCase]( + CPUTestCase("addi2", + Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 6), + Map(), Map(), + Map(), + Map(0 -> 0, 10 -> 17, 11 -> 93), + Map(), Map()) + ) + + val branch = List[CPUTestCase]( + CPUTestCase("beq", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(), Map(), "-False"), + CPUTestCase("beq", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(), Map(), "-True"), + CPUTestCase("bne", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(), Map(), "-False"), + CPUTestCase("bne", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(), Map(), "-True"), + CPUTestCase("blt", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), + Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> 5678), + Map(), Map(), "-False"), + CPUTestCase("blt", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(), Map(), "-False-equal"), + CPUTestCase("blt", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(), Map(), "-True"), + CPUTestCase("blt", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), + Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), + Map(), Map(), "-False-signed"), + CPUTestCase("blt", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), + Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), + Map(), Map(), "-True-signed"), + CPUTestCase("bge", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), + Map(), Map(), "-False"), + CPUTestCase("bge", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), + Map(5 -> 1235, 6 -> 1, 7 -> 9012, 28 -> 5678), + Map(), Map(), "-True"), + CPUTestCase("bge", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), + Map(5 -> 0, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), + Map(), Map(), "-False-signed"), + CPUTestCase("bge", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), + Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), + Map(), Map(), "-True-signed"), + CPUTestCase("bge", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), + Map(), Map(), "-True-equal"), + CPUTestCase("bltu", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), + Map(5 -> 0, 6 -> 1, 7 -> maxInt, 28 -> 5678), + Map(), Map(), "-False"), + CPUTestCase("bltu", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), + Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> maxInt), + Map(), Map(), "-True"), + CPUTestCase("bgeu", + Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), + Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> maxInt), + Map(), Map(), "-False"), + CPUTestCase("bgeu", + Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), + Map(5 -> 1235, 6 -> 1, 7 -> maxInt, 28 -> 5678), + Map(), Map(), "-True") + ) + + val memory = List[CPUTestCase]( + CPUTestCase("lw1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(5 -> BigInt("ffffffff", 16)), + Map(), Map()), + CPUTestCase("lb", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(5 -> BigInt("04", 16)), + Map(), Map()), + CPUTestCase("lh", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(5 -> BigInt("0304", 16)), + Map(), Map()), + CPUTestCase("lbu", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(5 -> BigInt("f4", 16)), + Map(), Map()), + CPUTestCase("lhu", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(5 -> BigInt("f3f4", 16)), + Map(), Map()), + CPUTestCase("lb1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(5 -> BigInt("fffffff4", 16)), + Map(), Map()), + CPUTestCase("lh1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(5 -> BigInt("fffff3f4", 16)), + Map(), Map()), + CPUTestCase("sw", + Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), + Map(), Map(), + Map(5 -> 1234), + Map(6 -> 1234), + Map(), Map(0x100 -> 1234)), + CPUTestCase("sb", + Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), + Map(), Map(), + Map(5 -> 1), + Map(6 -> 1), + Map(), Map(0x100 -> BigInt("ffffff01", 16))), + CPUTestCase("sh", + Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), + Map(), Map(), + Map(5 -> 1), + Map(6 -> 1), + Map(), Map(0x100 -> BigInt("ffff0001", 16))) + ) + + val memoryMultiCycle = List[CPUTestCase]( + CPUTestCase("lwfwd", + Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), + Map(), Map(), + Map(5 -> BigInt("ffffffff", 16), 10 -> 5), + Map(5 -> 1, 10 -> 6), + Map(), Map()) + ) + + val utype = List[CPUTestCase]( + CPUTestCase("auipc0", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(10 -> 1234), + Map(10 -> 0), + Map(), Map()), + CPUTestCase("auipc1", + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), Map(), + Map(10 -> 1234), + Map(10 -> 4), + Map(), Map()), + CPUTestCase("auipc2", + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), Map(), + Map(10 -> 1234), + Map(10 -> (17 << 12)), + Map(), Map()), + CPUTestCase("auipc3", + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), Map(), + Map(10 -> 1234), + Map(10 -> ((17 << 12) + 4)), + Map(), Map()), + CPUTestCase("lui0", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(10 -> 1234), + Map(10 -> 0), + Map(), Map()), + CPUTestCase("lui1", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(10 -> 1234), + Map(10 -> 4096), + Map(), Map()) + ) + + val jump = List[CPUTestCase]( + CPUTestCase("jal", + Map("single-cycle" -> 2, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234), + Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), + Map(), Map()), + CPUTestCase("jalr0", + Map("single-cycle" -> 2, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 10 -> 28), + Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), + Map(), Map()), + CPUTestCase("jalr1", + Map("single-cycle" -> 2, "five-cycle" -> 9, "pipelined" -> 9), + Map(), Map(), + Map(5 -> 1234, 10 -> 20), + Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), + Map(), Map()) + ) + + val smallApplications = List[CPUTestCase]( + CPUTestCase("fibonacci", + Map("single-cycle" -> 300, "five-cycle" -> 0, "pipelined" -> 1000), + Map(), Map(), + Map(6->11), + Map(6->11,5->89), + Map(), Map()), + CPUTestCase("naturalsum", + Map("single-cycle" -> 200, "five-cycle" -> 0, "pipelined" -> 500), + Map(), Map(), + Map(), + Map(5->55), + Map(), Map()), + CPUTestCase("multiplier", + Map("single-cycle" -> 1000, "five-cycle" -> 0, "pipelined" -> 1000), + Map(), Map(), + Map(5->23,6->20,8->0x1000), + Map(5->23*20), + Map(), Map()), + CPUTestCase("divider", + Map("single-cycle" -> 1000, "five-cycle" -> 0, "pipelined" -> 2000), + Map(), Map(), + Map(5->1260,6->30), + Map(7->42), + Map(), Map()) + ) + + val fullApplications = List[CPUTestCase]( + CPUTestCase("multiply.riscv", + Map("single-cycle" -> 42342, "five-cycle" -> 0, "pipelined" -> 100000), + Map(), Map(), + Map(), + Map(10->12345678), + Map(), Map()), + CPUTestCase("median.riscv", + Map("single-cycle" -> 9433, "five-cycle" -> 0, "pipelined" -> 100000), + Map(), Map(), + Map(), + Map(10->12345678), + Map(), Map()), + CPUTestCase("qsort.riscv", + Map("single-cycle" -> 263290, "five-cycle" -> 0, "pipelined" -> 300000), + Map(), Map(), + Map(), + Map(10->12345678), + Map(), Map()), + CPUTestCase("rsort.riscv", + Map("single-cycle" -> 263290, "five-cycle" -> 0, "pipelined" -> 250000), + Map(), Map(), + Map(), + Map(10->12345678), + Map(), Map()), + CPUTestCase("towers.riscv", + Map("single-cycle" -> 12653, "five-cycle" -> 0, "pipelined" -> 100000), + Map(), Map(), + Map(), + Map(10->12345678), + Map(), Map()), + CPUTestCase("vvadd.riscv", + Map("single-cycle" -> 5484, "five-cycle" -> 0, "pipelined" -> 20000), + Map(), Map(), + Map(), + Map(10->12345678), + Map(), Map()) + ) + + // Mapping from group name to list of tests + val tests = Map( + "rtype" -> rtype, + "rtypeMultiCycle" -> rtypeMultiCycle, + "itype" -> itype, + "itypeMultiCycle" -> itypeMultiCycle, + "branch" -> branch, + "memory" -> memory, + "memoryMultiCycle" -> memoryMultiCycle, + "utype" -> utype, + "jump" -> jump, + "smallApplications" -> smallApplications + ) + + // All of the tests + val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ + memory ++ memoryMultiCycle ++ utype ++ jump ++ smallApplications + + // Mapping from full name of test to test + val nameMap = (allTests ++ fullApplications).map(x => x.name() -> x).toMap +} diff --git a/src/test/resources/risc-v/add0 b/src/test/resources/risc-v/add0 index d53471e009316c86f3934f992b57e694aeb4b896..7785b2a23a0449eeae29e2d41438fe25f49896e4 100755 GIT binary patch delta 362 zcmX@3+@m@{L3oZJ0~nYvC@?TGXfUubux>Pd$}j0C2^22MEKV+CVB`lfS&PbyjWUf2 z3??SZ3o`?iA_Hayrpe|4s`U&!5K#e!kN*`wOcofQk--td1d{?l{RSWwlDrKX-vf;w zj>eBe<1-|tOkOP@ZxZa{7~&Z3tb#gUaw zzAT_8s0a3~USdf}QD#zUNow(AM!{fFMW8jz3=9Pz+dx1@8lvid=2eOPoDgh^yH*Ej_ delta 172 zcmeBCJ)=B9L6}950SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRZ=!6b;U z0AxuBKmPd$}j0C2^22MEKV+CVB`lfS&PbyjWUf2 z3??SZ3o`?iA_Hayrpe|4s`U&!5K#e!kN*`wOcofQk--td1d{?l{RSWwlDrKX-vf;w zj>eBe<1-|tOkOP@ZxZa{7~&Z3tb#gUaw zzAT_8s0a3~USdf}QD#zUNow(AM!{fFMW8jz3=9Pz+dx1@8lvid=2eOPoDgh^yH*Ej_ delta 172 zcmeBCJ)=B9L6}950SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRZ=!6b;U z0AxuBKmPd$}j0C2^22MEKV+CVB`lfS&PbyjWUf2 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a/src/test/resources/risc-v/srai b/src/test/resources/risc-v/srai index 77de1aac2b9b74636846228de6e997cf9145597f..aba76a2c763924c81a6cea53e85f4e9237286191 100755 GIT binary patch delta 362 zcmX@3+@m@{L3oZJ0~nYvC@?TGXfUubux>Pd$}j0C2^22MEKV+CVB`lfS&PbyjWUf2 z3??SZ3o`?iA_Hayrpe|4s`U&!5K#e!kN*`wOcofQk--td1d{?l{RSWwlDrKX-vf;w zj>eBe<1-W&Otb#gUaw zzAT_8s0a3~USdf}QD#zUNow(AM!{fFMW8jz3=9Pz+dx1@8lvid=2eOPoDgipCH;n)Q delta 172 zcmeBCJ)=B9L6}950SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRZ=!6b;U z0AxuBKm9d-GyTYZ0WEh&Nd_HfkWYWp`Wjpg%i{Eg!2Y@?}SeLDwl1IwzK zx0-Qtdh*LJm$U7G9V|m>$*I7{*9x|1Utq(7bt=}Zs$+kT%8Jt-oY^w{*73Dts&f6) zf*us~bwS@0G-#Fh6A+2i286gzCZSBkbP|tEqz=&udY!9|==KK}Lm^OigFy6$y|fOs z7TQQfHKe)<7PX_!HwJ(iPaX2%PreFMP?BXEpY-;WT z?qC*tGgNSZ{W8GRjWuv?#|g}C??bti^V>N0hMJJmj)yW@u!;xY%c6q2qA*j7_h^Nb LpSwe&^~2mZBlAYM delta 172 zcmeBCJ)t~7L6||10SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRN+!6b+; z4`fLQAmp{t_(ov<*HMJ1CX1@$H-X-qyMs4-bYNPrile*#b)GZ3>( aHWZR(T>%s^pByNp%z7WlQk={vBn$v&92lGc diff --git a/src/test/resources/risc-v/srli b/src/test/resources/risc-v/srli index 87b05f25c45a9587e01c4c2f1d369e77a8c3d0e6..30a5d305399df85ffd90d6e5edf6d017af6215fb 100755 GIT binary patch delta 362 zcmX@3+@m@{L3oZJ0~nYvC@?TGXfUubux>Pd$}j0C2^22MEKV+CVB`lfS&PbyjWUf2 z3??SZ3o`?iA_Hayrpe|4s`U&!5K#e!kN*`wOcofQk--td1d{?l{RSWwlDrKX-vf;w zj>eBe<1-W&Otb#gUaw zzAT_8s0a3~USdf}QD#zUNow(AM!{fFMW8jz3=9Pz+dx1@8lvid=2eOPoDgipCH;n)Q delta 172 zcmeBCJ)=B9L6}950SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRZ=!6b;U z0AxuBKm}Dw^i&075JRaA2yr(YD>)RCaXd0na)?g99bSf_)#;x1gh1Wu_eH1I zp4Uoip^Z%F=JHrHkVb-tMgxFAKRp*HMJ1CX1@$H-X-qyMs4-bYNPrile*#b)GZ3>( aHWZR(T>%s^pByNp%z7WlQk={vBn$v&92lGc diff --git a/src/test/resources/risc-v/sw b/src/test/resources/risc-v/sw index 4a12e983891160077c00550ebb56842279d81919..ee8e7f8550d9ffee090debde842add9e6f2bbe4d 100755 GIT binary patch delta 30 mcmdm@yG3__z-AVKKg<&gSSE>-FzReB6-j1f)R}x!^fmyfb_%Wl delta 31 ncmdm@yG3__0P|#~g3bT=|1wV!DPc6&Tq=^x$Y?P6rs!<|zHke) diff --git a/src/test/resources/risc-v/sw.riscv b/src/test/resources/risc-v/sw.riscv index 896bceb5..e62cbd8f 100644 --- a/src/test/resources/risc-v/sw.riscv +++ b/src/test/resources/risc-v/sw.riscv @@ -2,7 +2,6 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: - addi t0, x0, 7 sw t0, 0x400(zero) nop nop diff --git a/src/test/resources/risc-v/swapxor b/src/test/resources/risc-v/swapxor index a0dbb0374ae18e40842afa874e32fd5b9a96c120..58591543c63c92d869e5c477380674f5dd16b1e0 100755 GIT binary patch literal 4760 zcmeHLy-ve05I*-$LR6xN30Q()V2V)N5ec+PmN|1Mzp|qk@;Nxo@t6tv0AbV=4TcLsVeFH0wGw4~EeH%Ef zWzbUnq`)r<{JOwJfrEMy=`@jk0(>Nt2F~wBNhn4$tb}ZE}WM~ Y9WV1XXFv1I9WVDu6ta6<^t%6k1DYaDF#rGn delta 202 zcmbQCdPRAHf-sLD0~nYvC@?TGXfUucuxvDb%RezihMAdxadNhRs*{2QM2P@c0fY@A zL40K(tsnpq1M&6I_-0`KWF|p<&ZOev_~MepqLRs}f_f8^G$vmV)R1Ka$}>T}Ks1`oIz1_lA31?Fh-&S-ppka{Hj zacJ_Xlb4EEm;}2xhB(GMxw?D$#m6(m$2$cF$GiHufZ0jK#qq@@iA5zqab#tapNW_V z>VbWvmsnC#l$lgol3F}5QERe`Xn-il-OLOO1t9A|fJKCXL27cNs4}ktko5s5!V1Lf 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zcmeBCJ)=B9L6}950SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRZ=!6b;U z0AxuBKm 1), + Map(), Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), @@ -48,6 +49,7 @@ class Lab1Grader extends JUnitSuite { success = CPUTesterDriver(CPUTestCase("add2", Map("single-cycle" -> 1), + Map(), Map(), Map(5 -> 1234, 20 -> 5678), Map(0 -> 0, 10 -> 6912), Map(), Map()), diff --git a/src/test/scala/grading/Lab2Tests.scala b/src/test/scala/grading/Lab2Tests.scala index eb3a701a..dae07001 100644 --- a/src/test/scala/grading/Lab2Tests.scala +++ b/src/test/scala/grading/Lab2Tests.scala @@ -53,61 +53,85 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase](CPUTestCase("add1", Map("single-cycle" -> 1), + Map(), + Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), CPUTestCase("addi1", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(0 -> 0, 10 -> 17), Map(), Map()), CPUTestCase("addi2", Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 6), + Map(), + Map(), Map(), Map(0 -> 0, 10 -> 17, 11 -> 93), Map(), Map()), CPUTestCase("slli", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> 1), Map(0 -> 0, 5 -> 1, 6 -> 128), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> 1024), Map(0 -> 0, 5 -> 1024, 6 -> 8), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> twoscomp(-1024)), Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), Map(), Map(), "-negative"), CPUTestCase("srli", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> 128), Map(0 -> 0, 5 -> 128, 6 -> 1), Map(), Map()), CPUTestCase("andi", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 200), Map(), Map()), CPUTestCase("ori", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 511), Map(), Map()), CPUTestCase("xori", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 311), Map(), Map()), CPUTestCase("slti", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1),6->1), Map(), Map()), CPUTestCase("sltiu", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), Map(), Map()) @@ -142,11 +166,15 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("lw1", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(5 -> BigInt("ffffffff", 16)), Map(), Map()), CPUTestCase("lwfwd", Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), + Map(), + Map(), Map(5 -> BigInt("ffffffff", 16), 10 -> 5), Map(5 -> 1, 10 -> 6), Map(), Map()) @@ -179,31 +207,43 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("auipc0", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc1", Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(10 -> 1234), Map(10 -> 4), Map(), Map()), CPUTestCase("auipc2", Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(10 -> 1234), Map(10 -> (17 << 12)), Map(), Map()), CPUTestCase("auipc3", Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()), CPUTestCase("lui0", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("lui1", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(10 -> 1234), Map(10 -> 4096), Map(), Map()) @@ -239,6 +279,8 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("sw", Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), + Map(), + Map(), Map(5 -> 1234), Map(6 -> 1234), Map(), Map(0x100 -> 1234)) @@ -271,41 +313,57 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("lb", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(5 -> BigInt("04", 16)), Map(), Map()), CPUTestCase("lh", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(5 -> BigInt("0304", 16)), Map(), Map()), CPUTestCase("lbu", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(5 -> BigInt("f4", 16)), Map(), Map()), CPUTestCase("lhu", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(5 -> BigInt("f3f4", 16)), Map(), Map()), CPUTestCase("lb1", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(5 -> BigInt("fffffff4", 16)), Map(), Map()), CPUTestCase("lh1", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), + Map(), Map(), Map(5 -> BigInt("fffff3f4", 16)), Map(), Map()), CPUTestCase("sb", Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), + Map(), + Map(), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffffff01", 16))), CPUTestCase("sh", Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), + Map(), + Map(), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffff0001", 16))) @@ -364,6 +422,8 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("jal", Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -399,11 +459,15 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("jalr0", Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(5 -> 1234, 10 -> 28), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr1", Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(5 -> 1234, 10 -> 20), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -440,21 +504,29 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("fibonacci", Map("single-cycle" -> 300, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(6->11), Map(6->11,5->89), Map(), Map()), CPUTestCase("naturalsum", Map("single-cycle" -> 200, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(), Map(5->55), Map(), Map()), CPUTestCase("multiplier", - Map("single-cycle" -> 1000, "five-cycle" -> 6, "pipelined" -> 6), - Map(5->23,6->20), + Map("single-cycle" -> 1000, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), + Map(5->23,6->20), Map(5->23*20), Map(), Map()), CPUTestCase("divider", Map("single-cycle" -> 1000, "five-cycle" -> 6, "pipelined" -> 6), + Map(), + Map(), Map(5->1260,6->30), Map(7->42), Map(), Map()) From 08d41c1ff0566fbdfe9bedd2eec6232e47d6ede3 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 14 May 2019 18:43:55 -0700 Subject: [PATCH 32/57] resolved merge csr testing changes with old testing --- src/main/scala/testing/InstTests.scala | 107 ++++++++++++++----------- 1 file changed, 58 insertions(+), 49 deletions(-) diff --git a/src/main/scala/testing/InstTests.scala b/src/main/scala/testing/InstTests.scala index dec66e85..4ae85614 100644 --- a/src/main/scala/testing/InstTests.scala +++ b/src/main/scala/testing/InstTests.scala @@ -227,55 +227,7 @@ object InstTests { Map(), Map(), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), - Map(), Map()), - CPUTestCase("csrrc", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrci", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrs", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrsi", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrw", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrwi", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()), - CPUTestCase("ecall", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()), - CPUTestCase("ebreak", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) + Map(), Map()) ) val itypeMultiCycle = List[CPUTestCase]( @@ -567,6 +519,57 @@ object InstTests { Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) ) + + val csr = List[CPUTestCase]( + CPUTestCase("csrrc", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()), + CPUTestCase("csrrci", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()), + CPUTestCase("csrrs", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()), + CPUTestCase("csrrsi", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()), + CPUTestCase("csrrw", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()), + CPUTestCase("csrrwi", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()), + CPUTestCase("ecall", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()), + CPUTestCase("ebreak", + Map("single-cycle" -> 1, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), + Map(), Map()) + ) val smallApplications = List[CPUTestCase]( CPUTestCase("fibonacci", @@ -647,12 +650,18 @@ object InstTests { "utype" -> utype, "utypeMultiCycle" -> utypeMultiCycle, "jump" -> jump, + "csr" -> csr, "smallApplications" -> smallApplications ) // All of the tests +<<<<<<< HEAD val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ branchMultiCycle ++ memory ++ memoryMultiCycle ++ utype ++ utypeMultiCycle ++ jump ++ smallApplications +======= + val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ + memory ++ memoryMultiCycle ++ utype ++ jump ++ csr ++ smallApplications +>>>>>>> 5d9a896... addes seperate csr test category, still having argument mismatch errors // Mapping from full name of test to test val nameMap = (allTests ++ fullApplications).map(x => x.name() -> x).toMap From bda6e07d9a5e0c5515390593a16eca4897da43c8 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 14 May 2019 18:49:46 -0700 Subject: [PATCH 33/57] added csr debug to single cycle, added test for csrrc instruction --- src/main/scala/single-cycle/cpu.scala | 1 + src/main/scala/testing/InstTests.scala | 13 +++++-------- src/test/scala/labs/Lab2Test.scala | 1 + 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/src/main/scala/single-cycle/cpu.scala b/src/main/scala/single-cycle/cpu.scala index 1d61f544..1f2e4fa8 100644 --- a/src/main/scala/single-cycle/cpu.scala +++ b/src/main/scala/single-cycle/cpu.scala @@ -121,6 +121,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { val structures = List( (control, "control"), (registers, "registers"), + (csr, "csr"), (aluControl, "aluControl"), (alu, "alu"), (immGen, "immGen"), diff --git a/src/main/scala/testing/InstTests.scala b/src/main/scala/testing/InstTests.scala index 4ae85614..2df44caf 100644 --- a/src/main/scala/testing/InstTests.scala +++ b/src/main/scala/testing/InstTests.scala @@ -523,9 +523,10 @@ object InstTests { val csr = List[CPUTestCase]( CPUTestCase("csrrc", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), + Map( 0x300 -> 0x1888 ), + Map( 0x300 -> 0xffffe777 ), + Map( 6 -> 0xfffffffb), + Map( 6 -> 0xfffffffb), Map(), Map()), CPUTestCase("csrrci", Map("single-cycle" -> 1, "pipelined" -> 5), @@ -657,11 +658,7 @@ object InstTests { // All of the tests <<<<<<< HEAD val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ branchMultiCycle ++ - memory ++ memoryMultiCycle ++ utype ++ utypeMultiCycle ++ jump ++ smallApplications -======= - val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ - memory ++ memoryMultiCycle ++ utype ++ jump ++ csr ++ smallApplications ->>>>>>> 5d9a896... addes seperate csr test category, still having argument mismatch errors + memory ++ memoryMultiCycle ++ utype ++ utypeMultiCycle ++ jump ++ csr ++ smallApplications // Mapping from full name of test to test val nameMap = (allTests ++ fullApplications).map(x => x.name() -> x).toMap diff --git a/src/test/scala/labs/Lab2Test.scala b/src/test/scala/labs/Lab2Test.scala index 580ca77c..21590724 100644 --- a/src/test/scala/labs/Lab2Test.scala +++ b/src/test/scala/labs/Lab2Test.scala @@ -144,6 +144,7 @@ class SingleCycleStoreTesterLab2 extends CPUFlatSpec { */ class SingleCycleLoadStoreTesterLab2 extends CPUFlatSpec { +<<<<<<< HEAD val tests = InstTests.tests("memory") for (test <- tests) { "Single Cycle CPU" should s"run load/store instruction test ${test.binary}${test.extraName}" in { From bd6d38125555a47089489a7b69a6a24d891c79a5 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Fri, 10 May 2019 20:00:50 -0700 Subject: [PATCH 34/57] corrected csr to regfile wiring, enable mie by default --- Top.DualPortedMemory.memory.v | 20 +++++++++ firrtl_black_box_resource_files.f | 1 + src/main/scala/components/csr.scala | 58 +++++++++++++++++++------- src/main/scala/single-cycle/cpu.scala | 6 ++- src/test/resources/risc-v/csrrc | Bin 4748 -> 4752 bytes src/test/resources/risc-v/csrrc.riscv | 1 + stale_outputs_checked | 0 7 files changed, 68 insertions(+), 18 deletions(-) create mode 100644 Top.DualPortedMemory.memory.v create mode 100644 firrtl_black_box_resource_files.f create mode 100644 stale_outputs_checked diff --git a/Top.DualPortedMemory.memory.v b/Top.DualPortedMemory.memory.v new file mode 100644 index 00000000..a41466f6 --- /dev/null +++ b/Top.DualPortedMemory.memory.v @@ -0,0 +1,20 @@ +module BindsTo_0_DualPortedMemory( + input clock, + input reset, + input [31:0] io_imem_address, + output [31:0] io_imem_instruction, + input [31:0] io_dmem_address, + input [31:0] io_dmem_writedata, + input io_dmem_memread, + input io_dmem_memwrite, + input [1:0] io_dmem_maskmode, + input io_dmem_sext, + output [31:0] io_dmem_readdata +); + +initial begin + $readmemh("test", DualPortedMemory.memory); +end + endmodule + +bind DualPortedMemory BindsTo_0_DualPortedMemory BindsTo_0_DualPortedMemory_Inst(.*); \ No newline at end of file diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f new file mode 100644 index 00000000..900ea4d4 --- /dev/null +++ b/firrtl_black_box_resource_files.f @@ -0,0 +1 @@ +/riscv/Top.DualPortedMemory.memory.v \ No newline at end of file diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index b4417d26..8aaef9b7 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -238,7 +238,8 @@ class CSRRegFileIO extends Bundle{ val write_illegal = Output(Bool()) val system_illegal = Output(Bool()) } - + + val regwrite = Output(Bool()) val status = Output(new MStatus())//not needed in this design but useful if more ISA extensions val evec = Output(UInt(32.W)) // val exception = Input(Bool()) // rename to illgl inst @@ -254,6 +255,7 @@ class CSRRegFile extends Module{ val reset_mstatus = WireInit(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := MCSRCmd.MPRV//machine mode + reset_mstatus.mie := true.B//machine mode val reg_mstatus = RegInit(reset_mstatus) val reg_mepc = Reg(UInt(32.W)) @@ -303,29 +305,53 @@ class CSRRegFile extends Module{ read_mapping += MCSRs.minstreth -> 0.U //CSR DECODE - val cmd = if( io.decode.inst(6, 0) == ("b1110011".U) ) { - if( (io.decode.inst(19, 15) == ("b011".U)) || (io.decode.inst(19, 15) == ("b111".U)) ){ - MCSRCmd.clear //CSRRC{i} - }else if( (io.decode.inst(19, 15) == ("b010".U)) || (io.decode.inst(19, 15) == ("b110".U)) ){ - MCSRCmd.set //CSRRS{i} - }else if( (io.decode.inst(19, 15) == ("b001".U)) || (io.decode.inst(19, 15) == ("b101".U)) ){ - MCSRCmd.write //CSRRW{i} - }else if( (io.decode.inst(19, 15) == ("b000".U)) ) { - MCSRCmd.interrupt //ebreak, ecall + val cmd = WireInit(3.U(3.W)) + + when( io.decode.inst(6, 0) === ("b1110011".U)){ + switch(io.decode.inst(14, 12)){ + is("b011".U){ + cmd := MCSRCmd.clear + io.regwrite := true.B + } + is("b111".U){ + cmd := MCSRCmd.clear + io.regwrite := true.B + } + is("b010".U){ + cmd := MCSRCmd.set + io.regwrite := true.B + } + is("b110".U){ + cmd := MCSRCmd.set + io.regwrite := true.B + } + is("b001".U){ + cmd := MCSRCmd.write + io.regwrite := true.B + } + is("b101".U){ + cmd := MCSRCmd.write + io.regwrite := false.B + } + is("b000".U){ + cmd := MCSRCmd.interrupt + io.regwrite := false.B + } } - }else{ - MCSRCmd.nop + }.otherwise{ + cmd := MCSRCmd.nop + io.regwrite := false.B } val csr = io.decode.inst(MCSRCmd.MSB, MCSRCmd.LSB) - val system_insn = cmd == MCSRCmd.interrupt - val cpu_ren = cmd != MCSRCmd.nop && !system_insn + val system_insn = cmd === MCSRCmd.interrupt + val cpu_ren = cmd =/= MCSRCmd.nop && !system_insn val decoded_addr = read_mapping map { case (k, v) => k -> (csr === k) } val priv_sufficient = MCSRCmd.MPRV >= csr(9,8) val read_only = csr(11,10).andR - val cpu_wen = cpu_ren && cmd != MCSRCmd.read && priv_sufficient + val cpu_wen = cpu_ren && cmd =/= MCSRCmd.read && priv_sufficient val wen = cpu_wen && !read_only val wdata = readModifyWriteCSR(cmd.asInstanceOf[UInt], io.rw.rdata, io.rw.wdata) @@ -352,7 +378,7 @@ class CSRRegFile extends Module{ reg_mepc := io.pc // misaligned memory exceptions not supported... } - assert(PopCount(insn_ret :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") + //assert(PopCount(insn_ret :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") when (reg_time >= reg_mtimecmp) { reg_mip.mtix := true diff --git a/src/main/scala/single-cycle/cpu.scala b/src/main/scala/single-cycle/cpu.scala index 1f2e4fa8..554436e7 100644 --- a/src/main/scala/single-cycle/cpu.scala +++ b/src/main/scala/single-cycle/cpu.scala @@ -44,7 +44,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { registers.io.readreg2 := instruction(24,20) registers.io.writereg := instruction(11,7) - registers.io.wen := control.io.regwrite && (registers.io.writereg =/= 0.U) + registers.io.wen := (control.io.regwrite || csr.io.regwrite) && (registers.io.writereg =/= 0.U) aluControl.io.add := control.io.add aluControl.io.immediate := control.io.immediate @@ -83,7 +83,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { //WRITEBACK csr.io.decode.inst := instruction csr.io.decode.immid := imm - csr.io.rw.wdata := registers.io.readdata2 + csr.io.rw.wdata := registers.io.readdata1 csr.io.retire := true.B //mem is synchronous in this deisgn. no flushing as far as i'm aware @@ -98,6 +98,8 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { write_data := io.dmem.readdata } .elsewhen (control.io.toreg === 2.U) { write_data := pcPlusFour.io.result + } .elsewhen (control.io.toreg === 3.U) { + write_data := csr.io.rw.rdata } .otherwise { write_data := alu.io.result } diff --git a/src/test/resources/risc-v/csrrc b/src/test/resources/risc-v/csrrc index 70e16b78a4fc2af91a91272e7e64b4bb0cd2e425..ae8450446fea3927213f4ff6defba08a33a33a6d 100755 GIT binary patch delta 70 zcmeBCouE2FfpNh^MP*hQ1_lP1jh@^2S%jGj>L&?QFv@JM6o_YJl$m@}P#H-66;x-m Zn5-(K&d4#@S4f>TN05QRcrv4qFaU)*5W)Ze delta 81 zcmbQB+M_x_fpN}6MP*hA1_lO+jh@^2C$k7tFiLE$6^LhKl$d;1P#H)v3aK-iOx6UF WERzF;)Fm Date: Fri, 10 May 2019 20:05:46 -0700 Subject: [PATCH 35/57] added mret in InsTest --- src/main/scala/testing/InstTests.scala | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/main/scala/testing/InstTests.scala b/src/main/scala/testing/InstTests.scala index 2df44caf..71f077b7 100644 --- a/src/main/scala/testing/InstTests.scala +++ b/src/main/scala/testing/InstTests.scala @@ -569,7 +569,14 @@ object InstTests { Map(), Map(), Map(), Map(), + Map(), Map()), + CPUTestCase("mret", + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map(), Map(), + Map(), + Map(), Map(), Map()) + ) val smallApplications = List[CPUTestCase]( From 89098991d6df908ac2b335e069b683ff2d885d0f Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Fri, 10 May 2019 20:29:52 -0700 Subject: [PATCH 36/57] corrected csrrwi reg enable flag, addes all csrrx tests --- src/main/scala/components/csr.scala | 3 ++- src/test/resources/risc-v/csrrc | Bin 4752 -> 4756 bytes src/test/resources/risc-v/csrrc.riscv | 3 ++- src/test/resources/risc-v/csrrci | Bin 4748 -> 4752 bytes src/test/resources/risc-v/csrrci.riscv | 1 + src/test/resources/risc-v/csrrs | Bin 4748 -> 4756 bytes src/test/resources/risc-v/csrrs.riscv | 2 ++ src/test/resources/risc-v/csrrsi | Bin 4748 -> 4752 bytes src/test/resources/risc-v/csrrsi.riscv | 3 ++- src/test/resources/risc-v/csrrw | Bin 4748 -> 4756 bytes src/test/resources/risc-v/csrrw.riscv | 2 ++ src/test/resources/risc-v/csrrwi | Bin 4748 -> 4752 bytes src/test/resources/risc-v/csrrwi.riscv | 1 + 13 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 8aaef9b7..ea554d6c 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -256,6 +256,7 @@ class CSRRegFile extends Module{ val reset_mstatus = WireInit(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := MCSRCmd.MPRV//machine mode reset_mstatus.mie := true.B//machine mode + reset_mstatus.mie := true.B//machine mode val reg_mstatus = RegInit(reset_mstatus) val reg_mepc = Reg(UInt(32.W)) @@ -331,7 +332,7 @@ class CSRRegFile extends Module{ } is("b101".U){ cmd := MCSRCmd.write - io.regwrite := false.B + io.regwrite := true.B } is("b000".U){ cmd := MCSRCmd.interrupt diff --git a/src/test/resources/risc-v/csrrc b/src/test/resources/risc-v/csrrc index ae8450446fea3927213f4ff6defba08a33a33a6d..09586dbea884f3517335980bb04f64615964f162 100755 GIT binary patch delta 111 zcmbQBIz@GY0^^d2ips1C3=9kk8$EaO%YLZ;Y{YCJ4CJHZ%}fE4r3Dfh6*kuj#4|D~ lOuj3q3?vza)ER9iYXV80$$>)Z5(R<`48}n1Fu(|9000R45~KhC delta 104 zcmbQDIze@U0^@>-ips1q3=9l18$EaOOBU3BHexmq2J+GHWO;!^Mw!ix0`ZKDGLs() p0yPORFi1^q6cU~+BP76RF8O0{~Cs5!e6# delta 104 zcmbQB+M_x_fpN}6MP*hA1_lO+jh;LB#UAk+2m?82c(SxWBBR9ST7h^*Mv2LH1(ks$ eqmVkI$z)9+$uc=mNL?aRkb%J%s1*hnp$q`>)(@fp diff --git a/src/test/resources/risc-v/csrrsi.riscv b/src/test/resources/risc-v/csrrsi.riscv index da67d74d..b592ae70 100644 --- a/src/test/resources/risc-v/csrrsi.riscv +++ b/src/test/resources/risc-v/csrrsi.riscv @@ -2,11 +2,12 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: - csrrsi t0, mstatus, 0x1f + csrrsi t0, mstatus, 0x18 nop nop nop nop nop + add t0, x0, t0 _last: diff --git a/src/test/resources/risc-v/csrrw b/src/test/resources/risc-v/csrrw index b48a4ec3b4ac65758f529c05eb4defcbe27d1abf..6327126fefb710b56fb29937de88b220622a02f6 100755 GIT binary patch delta 78 zcmeBCouWEHfpN)1MP*h61_lO&jh@^2S%jHC@J|wuVBX9WFj-t6kx^lDr9eC*qr&8y hg33Vhub?`k&16*}bw-}azC!A(1%eC=#*-O^gaI3u61@Nb delta 102 zcmbQD+M_x_fpN}6MP*hA1_lO+jh@^2#Xk!%8wdk=Xn3-`Kq8~W=0<^dMn;Lr4+Vi* n1Q-~kCN~NRPnHo9U^JPmE2PfKBFMmy0v5{wie*f$6%q#k@~RWc diff --git a/src/test/resources/risc-v/csrrw.riscv b/src/test/resources/risc-v/csrrw.riscv index 2666481a..e4d7a0e8 100644 --- a/src/test/resources/risc-v/csrrw.riscv +++ b/src/test/resources/risc-v/csrrw.riscv @@ -2,6 +2,7 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: + addi t1, x0, 0xff csrrw t0, mstatus, t1 nop @@ -9,4 +10,5 @@ _start: nop nop nop + add t0, x0, t0 _last: diff --git a/src/test/resources/risc-v/csrrwi b/src/test/resources/risc-v/csrrwi index b8629172963279c962f1e0993b9b3659ade931a2..1df91787a586f31625713a037dae21db76d6263c 100755 GIT binary patch delta 70 zcmeBCouE2FfpNh^MP*hQ1_lP1jh^TEnKv^9OcobNWR%%lDG<-dC^Pw{pfZsBE2z$B ZF Date: Mon, 13 May 2019 15:52:36 -0700 Subject: [PATCH 37/57] added incomplete misaligned mem exception handeling --- src/main/scala/components/csr.scala | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index ea554d6c..99530059 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -378,6 +378,25 @@ class CSRRegFile extends Module{ io.evec := "h80000004".U reg_mepc := io.pc // misaligned memory exceptions not supported... } + + //MISALIGNED MEM ACCESS + /* + when (io.???) { //fetchexcept? + reg_mcause.interrupt := MCauses.misaligned_fetch & "h80000000".U + reg_mcause.exceptioncode := MCauses.misaligned_fetch & "h7fffffff".U + io.evec := "h80000004".U + reg_mepc := ??? + }.elsewhen (io.???){ ///loadexception? + reg_mcause.interrupt := MCauses.misaligned_load & "h80000000".U + reg_mcause.exceptioncode := MCauses.misaligned_load & "h7fffffff".U + io.evec := "h80000004".U + reg_mepc := ??? + }.elsewhen(io.???){ //storeexception? + reg_mcause.interrupt := MCauses.misaligned_store & "h80000000".U + reg_mcause.exceptioncode := MCauses.misaligned_store & "h7fffffff".U + io.evec := "h80000004".U + reg_mepc := ??? + }*/ //assert(PopCount(insn_ret :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") From 5d03a238d19a0adc7a34803a0a7ba69782fa3079 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Mon, 13 May 2019 18:21:26 -0700 Subject: [PATCH 38/57] csr and system calls finsihed and tested, fully working, commented code a bit --- src/main/scala/components/csr.scala | 191 ++++++++++--------------- src/main/scala/single-cycle/cpu.scala | 23 ++- src/test/resources/risc-v/Makefile | 2 +- src/test/resources/risc-v/csrrc.riscv | 2 - src/test/resources/risc-v/csrrci.riscv | 1 - src/test/resources/risc-v/csrrs.riscv | 2 - src/test/resources/risc-v/csrrsi.riscv | 3 +- src/test/resources/risc-v/csrrw.riscv | 2 - src/test/resources/risc-v/csrrwi.riscv | 3 +- src/test/resources/risc-v/ebreak.riscv | 12 ++ src/test/resources/risc-v/ecall.riscv | 12 ++ src/test/resources/risc-v/mret.riscv | 12 ++ 12 files changed, 121 insertions(+), 144 deletions(-) create mode 100644 src/test/resources/risc-v/ebreak.riscv create mode 100644 src/test/resources/risc-v/ecall.riscv create mode 100644 src/test/resources/risc-v/mret.riscv diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 99530059..f7648b70 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -25,23 +25,6 @@ object MCauses { val misaligned_store = 0x6 val store_access = 0x7 val machine_ecall = 0xb - val all = { - val res = collection.mutable.ArrayBuffer[Int]() - res += machine_soft_int - res += machine_timer_int - res += machine_ext_int - - res += misaligned_fetch - res += fetch_access - res += illegal_instruction - res += breakpoint - res += misaligned_load - res += load_access - res += misaligned_store - res += store_access - res += machine_ecall - res.toArray - } } object MCSRs { @@ -76,30 +59,6 @@ object MCSRs { val minstreth = 0xb82 //performance counter setup val mcounterinhibit = 0x320 - val all = { - val res = collection.mutable.ArrayBuffer[Int]() - res += mstatus - res += misa - res += medeleg - res += mideleg - res += mie - res += mtvec - res += mscratch - res += mepc - res += mcause - res += mtval - res += mip - res += mcycle - res += minstret - res += mcycleh - res += minstreth - res += mvendorid - res += marchid - res += mhartid - res += mimpid - res += mcounterinhibit - res.toArray - } } class MStatus extends Bundle{ @@ -218,71 +177,82 @@ object MCSRCmd{ val TRAPADDR = "h80000000".U val MPRV = 3 } - - -//reorder bundles -class CSRRegFileIO extends Bundle{ - //val hartid = Input(UInt(32.W)) - val rw = new Bundle { - val rdata = Output(UInt(32.W)) // - val wdata = Input(UInt(32.W)) // - } - - val csr_stall = Output(Bool())//not needed in single cycle - val eret = Output(Bool())// change ret names - val decode = new Bundle { +class CSRRegFile extends Module{ + //INIT CSR + val io = IO(new Bundle{ + val illegal_inst = Input(Bool())// + val retire_inst = Input(Bool())// + val pc = Input(UInt(32.W)) // + val read_data = Input(UInt(32.W)) // val inst = Input(UInt(32.W)) // val immid = Input(UInt(32.W)) // + val read_illegal = Output(Bool()) val write_illegal = Output(Bool()) val system_illegal = Output(Bool()) - } - - val regwrite = Output(Bool()) - val status = Output(new MStatus())//not needed in this design but useful if more ISA extensions - val evec = Output(UInt(32.W)) // - val exception = Input(Bool()) // rename to illgl inst - val retire = Input(Bool()) // rename to retire inst - val pc = Input(UInt(32.W)) // - val time = Output(UInt(32.W))// -} - -class CSRRegFile extends Module{ - //INIT CSR - val io = IO(new CSRRegFileIO) + val csr_stall = Output(Bool())//not needed in single cycle + val eret = Output(Bool())//return vector from a trap + val evec = Output(UInt(32.W)) //trap address + val write_data = Output(UInt(32.W)) // + val reg_write = Output(Bool())// + val status = Output(new MStatus())//not needed in this design but useful if more ISA extensions + val time = Output(UInt(32.W))// + }) io := DontCare val reset_mstatus = WireInit(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := MCSRCmd.MPRV//machine mode reset_mstatus.mie := true.B//machine mode - reset_mstatus.mie := true.B//machine mode + //contains info about system interrupts and privlidge mode val reg_mstatus = RegInit(reset_mstatus) + //exception program counter, set when exception raised val reg_mepc = Reg(UInt(32.W)) + //contains cause of exception val reg_mcause = RegInit(0.U.asTypeOf(new MCause())) + //register that can hold data to assist with exceptions/traps val reg_mtval = Reg(UInt(32.W)) + //scratch register for trap handler, useful for switching between mode memory spaces val reg_mscratch = Reg(UInt(32.W)) + //register used to set time for when timer interrupt should be raised val reg_mtimecmp = Reg(UInt(64.W)) + //register to indicate if trap handler should go directly to a specifc modes' trap handler + //rather than trap to machine mode then swap context to a less privileged mode. used to save + //performance, our implementation does not implement hardware to do this. val reg_medeleg = Reg(UInt(32.W)) + //indicates if we have a pending iterrupt for different interrupt types and modes val reg_mip = RegInit(0.U.asTypeOf(new MIx())) + //indicates which interrupts are enabled val reg_mie = RegInit(0.U.asTypeOf(new MIx())) + //used to halt cpu if WFI inst is seen, or can also just do nothing. This cpu doesn't + //implement WFI inst....yet val reg_wfi = RegInit(false.B) + //trap vector/address val reg_mtvec = RegInit(0.U.asTypeOf(new MTVec())) - + //current cpu time given in cycles val reg_time = WideCounter(64) - val reg_instret = WideCounter(64, io.retire) - + //number of instructions that have been completed + val reg_instret = WideCounter(64, io.retire_inst) + //performance counters, not implemented val reg_mcounterinhibit = RegInit(0.U.asTypeOf(new XCounterEnInhibit())) + //performance counter control val reg_mcounteren = RegInit(0.U.asTypeOf(new XCounterEnInhibit())) - + //machine status, contains interrupt bits, and priviledge mode val read_mstatus = io.status.asUInt() val isa_string = "I" - val reg_misa = RegInit((BigInt(0) | isa_string.map(x => 1 << (x - 'A')).reduce(_|_)).U.asTypeOf(new MISA())) + //takes user defined ISA string character by character and calculates ascii number for each, + //aligns the result to be a multiple of 2 then ors the results together to fit into MISA + //this tells the system what extensions are implemented + //val reg_misa = RegInit((BigInt(0) | isa_string.map(x => 1 << (x - 'A')).reduce(_|_)).U.asTypeOf(new MISA())) + //same as above but hardcoded for only I extension + val reg_misa = RegInit(16.U.asTypeOf(new MISA())) + //if we are a company we can hardcode our implementation info here val reg_mvendorid = RegInit(0.U.asTypeOf(new MVendorID())) - + //this hashmap associates CSR addresses to the actual register contents + //this is done to make decoding and working with csr's easier (avoid manual specification) val read_mapping = collection.mutable.LinkedHashMap[Int,Bits]( MCSRs.mcounterinhibit -> reg_mcounterinhibit.asUInt, MCSRs.mcycle -> reg_time, @@ -300,103 +270,88 @@ class CSRRegFile extends Module{ MCSRs.mtval -> reg_mtval, MCSRs.mcause -> reg_mcause.asUInt(), MCSRs.mhartid -> 0.U, - MCSRs.medeleg -> reg_medeleg) + MCSRs.medeleg -> reg_medeleg, + MCSRs.mcycleh -> 0.U, + MCSRs.minstreth -> 0.U + ) - read_mapping += MCSRs.mcycleh -> 0.U - read_mapping += MCSRs.minstreth -> 0.U - //CSR DECODE val cmd = WireInit(3.U(3.W)) - when( io.decode.inst(6, 0) === ("b1110011".U)){ - switch(io.decode.inst(14, 12)){ + when( io.inst(6, 0) === ("b1110011".U)){ + switch(io.inst(14, 12)){ is("b011".U){ cmd := MCSRCmd.clear - io.regwrite := true.B + io.reg_write := true.B } is("b111".U){ cmd := MCSRCmd.clear - io.regwrite := true.B + io.reg_write := true.B } is("b010".U){ cmd := MCSRCmd.set - io.regwrite := true.B + io.reg_write := true.B } is("b110".U){ cmd := MCSRCmd.set - io.regwrite := true.B + io.reg_write := true.B } is("b001".U){ cmd := MCSRCmd.write - io.regwrite := true.B + io.reg_write := true.B } is("b101".U){ cmd := MCSRCmd.write - io.regwrite := true.B + io.reg_write := true.B } is("b000".U){ cmd := MCSRCmd.interrupt - io.regwrite := false.B + io.reg_write := false.B } } }.otherwise{ cmd := MCSRCmd.nop - io.regwrite := false.B + io.reg_write := false.B } - val csr = io.decode.inst(MCSRCmd.MSB, MCSRCmd.LSB) + val csr = io.inst(MCSRCmd.MSB, MCSRCmd.LSB) val system_insn = cmd === MCSRCmd.interrupt val cpu_ren = cmd =/= MCSRCmd.nop && !system_insn - + //map is an infix operator on read_mapping. takes argument from decoded_addr() and applies it to + //read_mapping which provides a set if it exists then checks if the csr in the set corresponds to + //what the csr instruction specified. used for easier when statements below val decoded_addr = read_mapping map { case (k, v) => k -> (csr === k) } val priv_sufficient = MCSRCmd.MPRV >= csr(9,8) val read_only = csr(11,10).andR val cpu_wen = cpu_ren && cmd =/= MCSRCmd.read && priv_sufficient val wen = cpu_wen && !read_only - val wdata = readModifyWriteCSR(cmd.asInstanceOf[UInt], io.rw.rdata, io.rw.wdata) + val wdata = readModifyWriteCSR(cmd.asInstanceOf[UInt], io.write_data, Mux(io.inst(14),io.immid, io.read_data)) + //harware optimization? change this later? val opcode = 1.U << csr(2,0) val insn_call = system_insn && opcode(0) val insn_break = system_insn && opcode(1) val insn_ret = system_insn && opcode(2) && priv_sufficient + //wait for interrupt inst not implemented val insn_wfi = system_insn && opcode(5) && priv_sufficient private def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map( { case(k: Int, _: Bits) => csr === k }).reduce(_ || _) - io.decode.read_illegal := 3 < csr(9,8) || !decodeAny(read_mapping) - io.decode.write_illegal := csr(11,10).andR - io.decode.system_illegal := 3 < csr(9,8) + io.read_illegal := 3 < csr(9,8) || !decodeAny(read_mapping) + io.write_illegal := csr(11,10).andR + io.system_illegal := 3 < csr(9,8) io.status := reg_mstatus io.eret := insn_call || insn_break || insn_ret // ILLEGAL INSTR - when (io.exception) { + when (io.illegal_inst) { reg_mcause.interrupt := MCauses.illegal_instruction & "h80000000".U reg_mcause.exceptioncode := MCauses.illegal_instruction & "h7fffffff".U - io.evec := "h80000004".U + io.evec := "h80000000".U reg_mepc := io.pc // misaligned memory exceptions not supported... } - - //MISALIGNED MEM ACCESS - /* - when (io.???) { //fetchexcept? - reg_mcause.interrupt := MCauses.misaligned_fetch & "h80000000".U - reg_mcause.exceptioncode := MCauses.misaligned_fetch & "h7fffffff".U - io.evec := "h80000004".U - reg_mepc := ??? - }.elsewhen (io.???){ ///loadexception? - reg_mcause.interrupt := MCauses.misaligned_load & "h80000000".U - reg_mcause.exceptioncode := MCauses.misaligned_load & "h7fffffff".U - io.evec := "h80000004".U - reg_mepc := ??? - }.elsewhen(io.???){ //storeexception? - reg_mcause.interrupt := MCauses.misaligned_store & "h80000000".U - reg_mcause.exceptioncode := MCauses.misaligned_store & "h7fffffff".U - io.evec := "h80000004".U - reg_mepc := ??? - }*/ //assert(PopCount(insn_ret :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") @@ -420,7 +375,7 @@ class CSRRegFile extends Module{ //EBREAK when(insn_break){ - io.evec := "h80000004".U + io.evec := "h80000008".U reg_mcause.interrupt := MCauses.breakpoint & "h80000000".U reg_mcause.exceptioncode := MCauses.breakpoint & "h7fffffff".U } @@ -429,7 +384,7 @@ class CSRRegFile extends Module{ io.csr_stall := reg_wfi - io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) + io.write_data := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) when (wen) { //MISA IS FIXED IN THIS IMPLEMENATION diff --git a/src/main/scala/single-cycle/cpu.scala b/src/main/scala/single-cycle/cpu.scala index 554436e7..5a95dd1a 100644 --- a/src/main/scala/single-cycle/cpu.scala +++ b/src/main/scala/single-cycle/cpu.scala @@ -44,7 +44,7 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { registers.io.readreg2 := instruction(24,20) registers.io.writereg := instruction(11,7) - registers.io.wen := (control.io.regwrite || csr.io.regwrite) && (registers.io.writereg =/= 0.U) + registers.io.wen := (control.io.regwrite || csr.io.reg_write) && (registers.io.writereg =/= 0.U) aluControl.io.add := control.io.add aluControl.io.immediate := control.io.immediate @@ -55,6 +55,13 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { val imm = immGen.io.sextImm //ALU + csr.io.inst := instruction + csr.io.immid := imm + csr.io.read_data := registers.io.readdata1 + csr.io.retire_inst := true.B //mem is synchronous in this deisgn. no flushing as far as i'm aware + csr.io.illegal_inst := !control.io.validinst || csr.io.read_illegal || csr.io.write_illegal || csr.io.system_illegal //illegal inst exception? + csr.io.pc := pc + branchCtrl.io.branch := control.io.branch branchCtrl.io.funct3 := instruction(14,12) branchCtrl.io.inputx := registers.io.readdata1 @@ -81,25 +88,13 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends Module { io.dmem.sext := ~instruction(14) //WRITEBACK - csr.io.decode.inst := instruction - csr.io.decode.immid := imm - csr.io.rw.wdata := registers.io.readdata1 - - - csr.io.retire := true.B //mem is synchronous in this deisgn. no flushing as far as i'm aware - csr.io.exception := !control.io.validinst || csr.io.decode.read_illegal || - csr.io.decode.write_illegal || csr.io.decode.system_illegal //illegal inst exception? - csr.io.pc := pc - - - val write_data = Wire(UInt()) when (control.io.toreg === 1.U) { write_data := io.dmem.readdata } .elsewhen (control.io.toreg === 2.U) { write_data := pcPlusFour.io.result } .elsewhen (control.io.toreg === 3.U) { - write_data := csr.io.rw.rdata + write_data := csr.io.write_data } .otherwise { write_data := alu.io.result } diff --git a/src/test/resources/risc-v/Makefile b/src/test/resources/risc-v/Makefile index 157a74ee..170b6280 100644 --- a/src/test/resources/risc-v/Makefile +++ b/src/test/resources/risc-v/Makefile @@ -1,5 +1,5 @@ -RISCV ?= /home/nganjehl/riscv-gnu-toolchain +RISCV ?= /opt/riscv RISCVBIN = $(RISCV)/bin SOURCES = $(wildcard *.riscv) diff --git a/src/test/resources/risc-v/csrrc.riscv b/src/test/resources/risc-v/csrrc.riscv index 36dd8e2c..8d2d4eb3 100644 --- a/src/test/resources/risc-v/csrrc.riscv +++ b/src/test/resources/risc-v/csrrc.riscv @@ -2,7 +2,6 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: - addi t1, x0, 0x7ff #disable interrupt mie csrrc t0, mstatus, t1 nop @@ -10,5 +9,4 @@ _start: nop nop nop - add t0, x0, t0 # _last: diff --git a/src/test/resources/risc-v/csrrci.riscv b/src/test/resources/risc-v/csrrci.riscv index a75ab400..bdc85239 100644 --- a/src/test/resources/risc-v/csrrci.riscv +++ b/src/test/resources/risc-v/csrrci.riscv @@ -9,5 +9,4 @@ _start: nop nop nop - add t0, x0, t0 _last: diff --git a/src/test/resources/risc-v/csrrs.riscv b/src/test/resources/risc-v/csrrs.riscv index b4a9f0ca..2214b34a 100644 --- a/src/test/resources/risc-v/csrrs.riscv +++ b/src/test/resources/risc-v/csrrs.riscv @@ -2,7 +2,6 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: - addi t1, x0, 0x18 #set mpie to 1 and attempt to set spp (should stay false) csrrs t0, mstatus, t1 nop @@ -10,5 +9,4 @@ _start: nop nop nop - add t0, x0, t0 _last: diff --git a/src/test/resources/risc-v/csrrsi.riscv b/src/test/resources/risc-v/csrrsi.riscv index b592ae70..734abdd1 100644 --- a/src/test/resources/risc-v/csrrsi.riscv +++ b/src/test/resources/risc-v/csrrsi.riscv @@ -2,12 +2,11 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: - csrrsi t0, mstatus, 0x18 + csrrsi t0, mstatus, 0x7 #attempt to enable non m interrupts nop nop nop nop nop - add t0, x0, t0 _last: diff --git a/src/test/resources/risc-v/csrrw.riscv b/src/test/resources/risc-v/csrrw.riscv index e4d7a0e8..2666481a 100644 --- a/src/test/resources/risc-v/csrrw.riscv +++ b/src/test/resources/risc-v/csrrw.riscv @@ -2,7 +2,6 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: - addi t1, x0, 0xff csrrw t0, mstatus, t1 nop @@ -10,5 +9,4 @@ _start: nop nop nop - add t0, x0, t0 _last: diff --git a/src/test/resources/risc-v/csrrwi.riscv b/src/test/resources/risc-v/csrrwi.riscv index 6afa768c..447e36ce 100644 --- a/src/test/resources/risc-v/csrrwi.riscv +++ b/src/test/resources/risc-v/csrrwi.riscv @@ -2,12 +2,11 @@ .align 2 # Make sure we're aligned to 4 bytes .globl _start _start: - csrrwi t0, mstatus, 0x1f + csrrwi t0, mstatus, 0x17 nop nop nop nop nop - add t0, x0, t0 _last: diff --git a/src/test/resources/risc-v/ebreak.riscv b/src/test/resources/risc-v/ebreak.riscv new file mode 100644 index 00000000..96e89dcf --- /dev/null +++ b/src/test/resources/risc-v/ebreak.riscv @@ -0,0 +1,12 @@ +.text + .align 2 # Make sure we're aligned to 4 bytes + .globl _start +_start: + ebreak + + nop + nop + nop + nop + nop +_last: diff --git a/src/test/resources/risc-v/ecall.riscv b/src/test/resources/risc-v/ecall.riscv new file mode 100644 index 00000000..ab3b17dc --- /dev/null +++ b/src/test/resources/risc-v/ecall.riscv @@ -0,0 +1,12 @@ +.text + .align 2 # Make sure we're aligned to 4 bytes + .globl _start +_start: + ecall + + nop + nop + nop + nop + nop +_last: diff --git a/src/test/resources/risc-v/mret.riscv b/src/test/resources/risc-v/mret.riscv new file mode 100644 index 00000000..34810898 --- /dev/null +++ b/src/test/resources/risc-v/mret.riscv @@ -0,0 +1,12 @@ +.text + .align 2 # Make sure we're aligned to 4 bytes + .globl _start +_start: + mret + + nop + nop + nop + nop + nop +_last: From 28142a599ee022ec77c5552193f506af5d28b265 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 14 May 2019 17:25:10 -0700 Subject: [PATCH 39/57] unaligned mem access code wasn't push for some reason --- src/main/scala/components/csr.scala | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index f7648b70..17606f84 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -352,6 +352,26 @@ class CSRRegFile extends Module{ io.evec := "h80000000".U reg_mepc := io.pc // misaligned memory exceptions not supported... } + + //UNALIGNED MEM ACCESS + /* + when(io.???){ + reg_mcause.interrupt := MCauses.misaligned_fetch & "h80000000".U + reg_mcause.exceptioncode := MCauses.misaligned_fetch & "h7fffffff".U + io.evec := "h80000000".U + reg_mepc := + }.elsewhen(io.???){ + reg_mcause.interrupt := MCauses.misaligned_load & "h80000000".U + reg_mcause.exceptioncode := MCauses.misaligned_load & "h7fffffff".U + io.evec := "h80000000".U + reg_mepc := + }.elsewhen(io.???){ + reg_mcause.interrupt := MCauses.misaligned_store & "h80000000".U + reg_mcause.exceptioncode := MCauses.misaligned_store & "h7fffffff".U + io.evec := "h80000000".U + reg_mepc := + + }*/ //assert(PopCount(insn_ret :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") From 96582afc60c57c1edb60da72a7ba57fea1ee6265 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 14 May 2019 17:29:50 -0700 Subject: [PATCH 40/57] moved verilator testbench to different folder, deleted more verilog files, added syscall tests --- Top.DualPortedMemory.memory.v | 20 - firrtl_black_box_resource_files.f | 1 - src/{verilog => cpp}/testbench.cpp | 0 "src/test/resources/risc-v/\\" | 619 ----------------------------- src/test/resources/risc-v/csrrc | Bin 4756 -> 4748 bytes src/test/resources/risc-v/csrrci | Bin 4752 -> 4748 bytes src/test/resources/risc-v/csrrs | Bin 4756 -> 4748 bytes src/test/resources/risc-v/csrrsi | Bin 4752 -> 4748 bytes src/test/resources/risc-v/csrrw | Bin 4756 -> 4748 bytes src/test/resources/risc-v/csrrwi | Bin 4752 -> 4748 bytes src/test/resources/risc-v/ebreak | Bin 0 -> 4748 bytes src/test/resources/risc-v/ecall | Bin 0 -> 4748 bytes src/test/resources/risc-v/mret | Bin 0 -> 4748 bytes stale_outputs_checked | 0 14 files changed, 640 deletions(-) delete mode 100644 Top.DualPortedMemory.memory.v delete mode 100644 firrtl_black_box_resource_files.f rename src/{verilog => cpp}/testbench.cpp (100%) delete mode 100644 "src/test/resources/risc-v/\\" create mode 100755 src/test/resources/risc-v/ebreak create mode 100755 src/test/resources/risc-v/ecall create mode 100755 src/test/resources/risc-v/mret delete mode 100644 stale_outputs_checked diff --git a/Top.DualPortedMemory.memory.v b/Top.DualPortedMemory.memory.v deleted file mode 100644 index a41466f6..00000000 --- a/Top.DualPortedMemory.memory.v +++ /dev/null @@ -1,20 +0,0 @@ -module BindsTo_0_DualPortedMemory( - input clock, - input reset, - input [31:0] io_imem_address, - output [31:0] io_imem_instruction, - input [31:0] io_dmem_address, - input [31:0] io_dmem_writedata, - input io_dmem_memread, - input io_dmem_memwrite, - input [1:0] io_dmem_maskmode, - input io_dmem_sext, - output [31:0] io_dmem_readdata -); - -initial begin - $readmemh("test", DualPortedMemory.memory); -end - endmodule - -bind DualPortedMemory BindsTo_0_DualPortedMemory BindsTo_0_DualPortedMemory_Inst(.*); \ No newline at end of file diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f deleted file mode 100644 index 900ea4d4..00000000 --- a/firrtl_black_box_resource_files.f +++ /dev/null @@ -1 +0,0 @@ -/riscv/Top.DualPortedMemory.memory.v \ No newline at end of file diff --git a/src/verilog/testbench.cpp b/src/cpp/testbench.cpp similarity index 100% rename from src/verilog/testbench.cpp rename to src/cpp/testbench.cpp diff --git "a/src/test/resources/risc-v/\\" "b/src/test/resources/risc-v/\\" deleted file mode 100644 index 71f4c040..00000000 --- "a/src/test/resources/risc-v/\\" +++ /dev/null @@ -1,619 +0,0 @@ -// Lists of different instruction test cases for use with different CPU models - -package dinocpu - -/** - * This object contains a set of lists of tests. Each list is a different set of - * instruction types and corresponds to a RISC-V program in resources/risc-v - * - * Each test case looks like: - * - binary to run in src/test/resources/risc-v - * - number of cycles to run for each CPU type - * - initial values for csr registers - * - final values to check for csr registers - * - initial values for registers - * - final values to check for registers - * - initial values for memory - * - final values to check for memory - * - extra name information - */ -object InstTests { - - val maxInt = BigInt("FFFFFFFF", 16) - - def twoscomp(v: BigInt) : BigInt = { - if (v < 0) { - return maxInt + v + 1 - } else { - return v - } - } - - val rtype = List[CPUTestCase]( - CPUTestCase("add1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1234), - Map(0 -> 0, 5 -> 1234, 6 -> 1234), - Map(), Map()), - CPUTestCase("add2", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1234, 20 -> 5678), - Map(0 -> 0, 10 -> 6912), - Map(), Map()), - CPUTestCase("add0", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1234, 6 -> 3456), - Map(0 -> 0, 5 -> 1234, 6 -> 3456), - Map(), Map()), - CPUTestCase("or", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1234, 6 -> 5678), - Map(7 -> 5886), - Map(), Map()), - CPUTestCase("sub", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1234, 6 -> 5678), - Map(7 -> BigInt("FFFFEEA4", 16)), - Map(), Map()), - CPUTestCase("and", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1234, 6 -> 5678), - Map(7 -> 1026), - Map(), Map()), - CPUTestCase("xor", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> 1234, 5 -> 5678), - Map(5 -> 5678, 7 -> 1234, 6 -> 4860), - Map(), Map()), - CPUTestCase("slt", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> 1234, 5 -> 5678), - Map(5 -> 5678, 7 -> 1234, 6 -> 1), - Map(), Map()), - CPUTestCase("slt1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> -1, 5 -> 1), - Map(5 -> 1, 6 -> 1), - Map(), Map()), - CPUTestCase("sltu", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> -1, 5 -> 1), - Map(5 -> 1, 6 -> 0), - Map(), Map()), - CPUTestCase("sltu1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> 20, 5 -> 100), - Map(5 -> 100, 6 -> 1), - Map(), Map()), - CPUTestCase("sll", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> 32, 5 -> 2), - Map(7 -> 32, 5 -> 2, 6 -> 128), - Map(), Map()), - CPUTestCase("srl", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> 32, 5 -> 2), - Map(7 -> 32, 5 -> 2, 6 -> 8), - Map(), Map()), - CPUTestCase("sra", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(7 -> twoscomp(-2), 5 -> 31), - Map(5 -> 31, 6 -> twoscomp(-1)), - Map(), Map()) - ) - - val rtypeMultiCycle = List[CPUTestCase]( - CPUTestCase("addfwd", - Map("single-cycle" -> 10, "five-cycle" -> 0, "pipelined" -> 14), - Map(), Map(), - Map(5 -> 1, 10 -> 0), - Map(5 -> 1, 10 -> 10), - Map(), Map()), - CPUTestCase("swapxor", - Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), - Map(), Map(), - Map(7 -> 5678, 5 -> 1234), - Map(5 -> 5678,7->1234), - Map(), Map()), - CPUTestCase("power2", - Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), - Map(), Map(), - Map(5 -> 512, 6->1), - Map(7->1), - Map(), Map(), "-512"), - CPUTestCase("power2", - Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), - Map(), Map(), - Map(5 -> 1234, 6->1), - Map(7->0), - Map(), Map(), "-1234"), - CPUTestCase("power2", - Map("single-cycle" -> 3, "five-cycle" -> 0, "pipelined" -> 7), - Map(), Map(), - Map(5 -> twoscomp(-65536), 6->1), - Map(7->0), // This algorithm doesn't work for negative numbers - Map(), Map(), "--65536"), - CPUTestCase("oppsign", - Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), - Map(), Map(), - Map(5 -> 512, 6->twoscomp(-1024),7->0), - Map(7->1), - Map(), Map(), "-true"), - CPUTestCase("oppsign", - Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), - Map(), Map(), - Map(5 -> 512, 6->1024,7->0), - Map(7->0), - Map(), Map(), "-false"), - CPUTestCase("rotR", - Map("single-cycle" -> 4, "five-cycle" -> 0, "pipelined" -> 8), - Map(), Map(), - Map(5 -> twoscomp(-1), 6->1, 7->32), - Map(7->twoscomp(-1)), - Map(), Map()) - ) - - val itype = List[CPUTestCase]( - CPUTestCase("addi1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(0 -> 0, 10 -> 17), - Map(), Map()), - CPUTestCase("slli", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1), - Map(0 -> 0, 5 -> 1, 6 -> 128), - Map(), Map()), - CPUTestCase("srai", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 1024), - Map(0 -> 0, 5 -> 1024, 6 -> 8), - Map(), Map()), - CPUTestCase("srai", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> twoscomp(-1024)), - Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), - Map(), Map(), "-negative"), - CPUTestCase("srli", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 128), - Map(0 -> 0, 5 -> 128, 6 -> 1), - Map(), Map()), - CPUTestCase("andi", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 456), - Map(0 -> 0, 5 -> 456, 6 -> 200), - Map(), Map()), - CPUTestCase("ori", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 456), - Map(0 -> 0, 5 -> 456, 6 -> 511), - Map(), Map()), - CPUTestCase("xori", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> 456), - Map(0 -> 0, 5 -> 456, 6 -> 311), - Map(), Map()), - CPUTestCase("slti", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> twoscomp(-1)), - Map(0 -> 0, 5 -> twoscomp(-1),6->1), - Map(), Map()), - CPUTestCase("sltiu", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(5 -> twoscomp(-1)), - Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), - Map(), Map()) - CPUTestCase("csrrc", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - CPUTestCase("csrrci", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - CPUTestCase("csrrs", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - CPUTestCase("csrrsi", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - CPUTestCase("csrrw", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - CPUTestCase("csrrwi", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - CPUTestCase("ecall", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - CPUTestCase("ebreak", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(), - Map(), Map()) - ) - - val itypeMultiCycle = List[CPUTestCase]( - CPUTestCase("addi2", - Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 6), - Map(), Map(), - Map(), - Map(0 -> 0, 10 -> 17, 11 -> 93), - Map(), Map()) - ) - - val branch = List[CPUTestCase]( - CPUTestCase("beq", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(), Map(), "-False"), - CPUTestCase("beq", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(), Map(), "-True"), - CPUTestCase("bne", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(), Map(), "-False"), - CPUTestCase("bne", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(), Map(), "-True"), - CPUTestCase("blt", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), - Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> 5678), - Map(), Map(), "-False"), - CPUTestCase("blt", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(), Map(), "-False-equal"), - CPUTestCase("blt", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(), Map(), "-True"), - CPUTestCase("blt", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), - Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), - Map(), Map(), "-False-signed"), - CPUTestCase("blt", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), - Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), - Map(), Map(), "-True-signed"), - CPUTestCase("bge", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), - Map(), Map(), "-False"), - CPUTestCase("bge", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), - Map(5 -> 1235, 6 -> 1, 7 -> 9012, 28 -> 5678), - Map(), Map(), "-True"), - CPUTestCase("bge", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), - Map(5 -> 0, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), - Map(), Map(), "-False-signed"), - CPUTestCase("bge", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), - Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), - Map(), Map(), "-True-signed"), - CPUTestCase("bge", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), - Map(), Map(), "-True-equal"), - CPUTestCase("bltu", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), - Map(5 -> 0, 6 -> 1, 7 -> maxInt, 28 -> 5678), - Map(), Map(), "-False"), - CPUTestCase("bltu", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), - Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> maxInt), - Map(), Map(), "-True"), - CPUTestCase("bgeu", - Map("single-cycle" -> 3, "five-cycle" -> 7, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), - Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> maxInt), - Map(), Map(), "-False"), - CPUTestCase("bgeu", - Map("single-cycle" -> 3, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), - Map(5 -> 1235, 6 -> 1, 7 -> maxInt, 28 -> 5678), - Map(), Map(), "-True") - ) - - val memory = List[CPUTestCase]( - CPUTestCase("lw1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(5 -> BigInt("ffffffff", 16)), - Map(), Map()), - CPUTestCase("lb", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(5 -> BigInt("04", 16)), - Map(), Map()), - CPUTestCase("lh", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(5 -> BigInt("0304", 16)), - Map(), Map()), - CPUTestCase("lbu", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(5 -> BigInt("f4", 16)), - Map(), Map()), - CPUTestCase("lhu", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(5 -> BigInt("f3f4", 16)), - Map(), Map()), - CPUTestCase("lb1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(5 -> BigInt("fffffff4", 16)), - Map(), Map()), - CPUTestCase("lh1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(), - Map(5 -> BigInt("fffff3f4", 16)), - Map(), Map()), - CPUTestCase("sw", - Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), - Map(), Map(), - Map(5 -> 1234), - Map(6 -> 1234), - Map(), Map(0x100 -> 1234)), - CPUTestCase("sb", - Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), - Map(), Map(), - Map(5 -> 1), - Map(6 -> 1), - Map(), Map(0x100 -> BigInt("ffffff01", 16))), - CPUTestCase("sh", - Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), - Map(), Map(), - Map(5 -> 1), - Map(6 -> 1), - Map(), Map(0x100 -> BigInt("ffff0001", 16))) - ) - - val memoryMultiCycle = List[CPUTestCase]( - CPUTestCase("lwfwd", - Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), - Map(), Map(), - Map(5 -> BigInt("ffffffff", 16), 10 -> 5), - Map(5 -> 1, 10 -> 6), - Map(), Map()) - ) - - val utype = List[CPUTestCase]( - CPUTestCase("auipc0", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(10 -> 1234), - Map(10 -> 0), - Map(), Map()), - CPUTestCase("auipc1", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), Map(), - Map(10 -> 1234), - Map(10 -> 4), - Map(), Map()), - CPUTestCase("auipc2", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), Map(), - Map(10 -> 1234), - Map(10 -> (17 << 12)), - Map(), Map()), - CPUTestCase("auipc3", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), Map(), - Map(10 -> 1234), - Map(10 -> ((17 << 12) + 4)), - Map(), Map()), - CPUTestCase("lui0", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(10 -> 1234), - Map(10 -> 0), - Map(), Map()), - CPUTestCase("lui1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), - Map(10 -> 1234), - Map(10 -> 4096), - Map(), Map()) - ) - - val jump = List[CPUTestCase]( - CPUTestCase("jal", - Map("single-cycle" -> 2, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234), - Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), - Map(), Map()), - CPUTestCase("jalr0", - Map("single-cycle" -> 2, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 10 -> 28), - Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), - Map(), Map()), - CPUTestCase("jalr1", - Map("single-cycle" -> 2, "five-cycle" -> 9, "pipelined" -> 9), - Map(), Map(), - Map(5 -> 1234, 10 -> 20), - Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), - Map(), Map()) - ) - - val smallApplications = List[CPUTestCase]( - CPUTestCase("fibonacci", - Map("single-cycle" -> 300, "five-cycle" -> 0, "pipelined" -> 1000), - Map(), Map(), - Map(6->11), - Map(6->11,5->89), - Map(), Map()), - CPUTestCase("naturalsum", - Map("single-cycle" -> 200, "five-cycle" -> 0, "pipelined" -> 500), - Map(), Map(), - Map(), - Map(5->55), - Map(), Map()), - CPUTestCase("multiplier", - Map("single-cycle" -> 1000, "five-cycle" -> 0, "pipelined" -> 1000), - Map(), Map(), - Map(5->23,6->20,8->0x1000), - Map(5->23*20), - Map(), Map()), - CPUTestCase("divider", - Map("single-cycle" -> 1000, "five-cycle" -> 0, "pipelined" -> 2000), - Map(), Map(), - Map(5->1260,6->30), - Map(7->42), - Map(), Map()) - ) - - val fullApplications = List[CPUTestCase]( - CPUTestCase("multiply.riscv", - Map("single-cycle" -> 42342, "five-cycle" -> 0, "pipelined" -> 100000), - Map(), Map(), - Map(), - Map(10->12345678), - Map(), Map()), - CPUTestCase("median.riscv", - Map("single-cycle" -> 9433, "five-cycle" -> 0, "pipelined" -> 100000), - Map(), Map(), - Map(), - Map(10->12345678), - Map(), Map()), - CPUTestCase("qsort.riscv", - Map("single-cycle" -> 263290, "five-cycle" -> 0, "pipelined" -> 300000), - Map(), Map(), - Map(), - Map(10->12345678), - Map(), Map()), - CPUTestCase("rsort.riscv", - Map("single-cycle" -> 263290, "five-cycle" -> 0, "pipelined" -> 250000), - Map(), Map(), - Map(), - Map(10->12345678), - Map(), Map()), - CPUTestCase("towers.riscv", - Map("single-cycle" -> 12653, "five-cycle" -> 0, "pipelined" -> 100000), - Map(), Map(), - Map(), - Map(10->12345678), - Map(), Map()), - CPUTestCase("vvadd.riscv", - Map("single-cycle" -> 5484, "five-cycle" -> 0, "pipelined" -> 20000), - Map(), Map(), - Map(), - Map(10->12345678), - Map(), Map()) - ) - - // Mapping from group name to list of tests - val tests = Map( - "rtype" -> rtype, - "rtypeMultiCycle" -> rtypeMultiCycle, - "itype" -> itype, - "itypeMultiCycle" -> itypeMultiCycle, - "branch" -> branch, - "memory" -> memory, - "memoryMultiCycle" -> memoryMultiCycle, - "utype" -> utype, - "jump" -> jump, - "smallApplications" -> smallApplications - ) - - // All of the tests - val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ - memory ++ memoryMultiCycle ++ utype ++ jump ++ smallApplications - - // Mapping from full name of test to test - val nameMap = (allTests ++ fullApplications).map(x => x.name() -> x).toMap -} diff --git a/src/test/resources/risc-v/csrrc b/src/test/resources/risc-v/csrrc index 09586dbea884f3517335980bb04f64615964f162..70e16b78a4fc2af91a91272e7e64b4bb0cd2e425 100755 GIT binary patch delta 102 zcmbQD+M_x_fpN}6MP*hA1_lO+jh@^2#XlP{8wdk=Xn3-`Kq8~W=0<^dMn;Lr4+Vi* n1Q-~kCN~NRPnHo9U^JPmE2PfKBFMmy0v5{wie*f$6%q#k{E8Fm delta 78 zcmeBCouWEHfpN)1MP*h61_lO&jh@^2S%jHC)K3zSVBX9WFj-t6kx^lDr9eC*qr&8y hg33Vhub?`k&16*}bw-}azC!A(1%eC=#*-O^gaI8O0{~Cs5!e6# diff --git a/src/test/resources/risc-v/csrrw b/src/test/resources/risc-v/csrrw index 6327126fefb710b56fb29937de88b220622a02f6..b48a4ec3b4ac65758f529c05eb4defcbe27d1abf 100755 GIT binary patch delta 102 zcmbQD+M_x_fpN}6MP*hA1_lO+jh@^2#Xk!%8wdk=Xn3-`Kq8~W=0<^dMn;Lr4+Vi* n1Q-~kCN~NRPnHo9U^JPmE2PfKBFMmy0v5{wie*f$6%q#k@~RWc delta 78 zcmeBCouWEHfpN)1MP*h61_lO&jh@^2S%jHC@J|wuVBX9WFj-t6kx^lDr9eC*qr&8y hg33Vhub?`k&16*}bw-}azC!A(1%eC=#*-O^gaI3u61@Nb diff --git a/src/test/resources/risc-v/csrrwi b/src/test/resources/risc-v/csrrwi index 1df91787a586f31625713a037dae21db76d6263c..5fbc628c22ddd35431f26cdcad70a9c8377e00dc 100755 GIT binary patch delta 103 zcmbQB+M_x_fpN}6MP*hA1_lO+jh;LCMY#=xfowE9Sy~{GQDSqgKs+O(#N@kz%0QA) dNS)DSvL=vZnH(sjE|Dq7z+ep23ImK#1^}a*4!i&W delta 92 zcmeBCouE2FfpNh^MP*hQ1_lP1jh;LCCHW16foycVnJHkhxIiMK%;rjgct%E<$u|X+ gf#hF7bw-QHszU0F9Fu*8)LC-{85oQwGYSa<059Ybc>n+a diff --git a/src/test/resources/risc-v/ebreak b/src/test/resources/risc-v/ebreak new file mode 100755 index 0000000000000000000000000000000000000000..0b06c789f7a44e2ebfe515717e0b1a67757944e8 GIT binary patch literal 4748 zcmeI0ze)o^5XR^74-~-@o2ZS7h1DUK)IwsSD3T^NR_mTw^e`r2cMV$kB0iL_B0hl5 z+_IO;A!uha1Dl!eo4IBAb(z=xc6)|?8lzfWb&>i|w%nf-=%TTE4ao?bSm|s}!V{dhoVv+F%2*DcQB?$rtgVd=>El zbSBHDZ4mM1Wd@S@zS+s7{pB{V!`o{i1i0|v6P)W}@onFpbm0W+=g@%Ao;TeS04S2aJX z`TLreH4n*DWm%Mi%#=1DeliJtm_Nob_R-F!;rek0 zv*uf&0^;feEL~d*`;MH!Ofx7bd!@3sF7~~nB;>T?p^PPk5)*V NeRC{ys;>2WzX7JDMwkEq literal 0 HcmV?d00001 diff --git a/src/test/resources/risc-v/mret b/src/test/resources/risc-v/mret new file mode 100755 index 0000000000000000000000000000000000000000..9707950ab455ab6ac785b5c770f1e9a523ef2b8d GIT binary patch literal 4748 zcmeI0%}T>S5XUD?TNFeqUaDRyc<>ZT+oPA1)(?El zbSBHDX%O`0Wd=4g|CxW5<#(Ld{@s=5dElZ1pWsvnn{S79(t!r{FQ5t)JFmGv0P0xM zsZcA|C&|GCm;e)C0!)AjFaajO1egF5U;<2l3H(0+4UOgzKBIWTV{EEKk5=FvU|CVC zb}MNuo4-8S&$b8F=tF6%Q-+VP9URfVz=j9=RP0$*!+C?sveO=fwoJb@ye)l0ZhlFV zoW3dOhk|}AXqc(k1Pc&TsSOA*nJywZ70X33H?ca$&afBWhoalRz8wgGx;q?-{-BrE zk=8;Rsp!vbTRfIVf{5p1fIzQjMn;&8viZqXCVnvxq^tvJj7p+s6Ki_oALA5#w6m!? zKki^Qd^0p~hI1ca>1=iMoj8G+?x3JtN-O*6pzj?^LQFdz%GiQkJa}IgW!x2wGPSvn NR!Di@1RL!ieBUD%Mw9>m literal 0 HcmV?d00001 diff --git a/stale_outputs_checked b/stale_outputs_checked deleted file mode 100644 index e69de29b..00000000 From 352295a29a4b4fd3e52af7b5762f4693c3430dde Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 14 May 2019 17:35:22 -0700 Subject: [PATCH 41/57] reverted test binary to use original compiled versions --- src/test/resources/risc-v/add0 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/add1 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/add2 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/addfwd | Bin 4784 -> 4592 bytes src/test/resources/risc-v/addi1 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/addi2 | Bin 4752 -> 4560 bytes src/test/resources/risc-v/and | Bin 4748 -> 4552 bytes src/test/resources/risc-v/andi | Bin 4748 -> 4556 bytes src/test/resources/risc-v/auipc0 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/auipc1 | Bin 4752 -> 4560 bytes src/test/resources/risc-v/auipc2 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/auipc3 | Bin 4752 -> 4560 bytes src/test/resources/risc-v/beq | Bin 4840 -> 4648 bytes src/test/resources/risc-v/bge | Bin 4840 -> 4648 bytes src/test/resources/risc-v/bgeu | Bin 4840 -> 4648 bytes src/test/resources/risc-v/blt | Bin 4840 -> 4648 bytes src/test/resources/risc-v/bltu | Bin 4840 -> 4648 bytes src/test/resources/risc-v/bne | Bin 4840 -> 4648 bytes src/test/resources/risc-v/divider | Bin 5932 -> 5740 bytes src/test/resources/risc-v/fibonacci | Bin 5864 -> 5672 bytes src/test/resources/risc-v/jal | Bin 4796 -> 4604 bytes src/test/resources/risc-v/jalr0 | Bin 4800 -> 4604 bytes src/test/resources/risc-v/jalr1 | Bin 4800 -> 4604 bytes src/test/resources/risc-v/lb | Bin 5812 -> 5620 bytes src/test/resources/risc-v/lb1 | Bin 5812 -> 5620 bytes src/test/resources/risc-v/lbu | Bin 5812 -> 5620 bytes src/test/resources/risc-v/lh | Bin 5812 -> 5620 bytes src/test/resources/risc-v/lh1 | Bin 5812 -> 5620 bytes src/test/resources/risc-v/lhu | Bin 5812 -> 5620 bytes src/test/resources/risc-v/lui0 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/lui1 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/lw1 | Bin 5812 -> 5620 bytes src/test/resources/risc-v/lwfwd | Bin 5816 -> 5620 bytes src/test/resources/risc-v/multiplier | Bin 5864 -> 5672 bytes src/test/resources/risc-v/naturalsum | Bin 5864 -> 5672 bytes src/test/resources/risc-v/oppsign | Bin 4756 -> 4560 bytes src/test/resources/risc-v/or | Bin 4744 -> 4552 bytes src/test/resources/risc-v/ori | Bin 4748 -> 4552 bytes src/test/resources/risc-v/power2 | Bin 4756 -> 4564 bytes src/test/resources/risc-v/rotR | Bin 4760 -> 4568 bytes src/test/resources/risc-v/sb | Bin 5812 -> 5620 bytes src/test/resources/risc-v/sh | Bin 5812 -> 5620 bytes src/test/resources/risc-v/sll | Bin 4748 -> 4552 bytes src/test/resources/risc-v/slli | Bin 4748 -> 4556 bytes src/test/resources/risc-v/slt | Bin 4748 -> 4552 bytes src/test/resources/risc-v/slt1 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/slti | Bin 4748 -> 4556 bytes src/test/resources/risc-v/sltiu | Bin 4748 -> 4556 bytes src/test/resources/risc-v/sltu | Bin 4748 -> 4556 bytes src/test/resources/risc-v/sltu1 | Bin 4748 -> 4556 bytes src/test/resources/risc-v/sort | Bin 6004 -> 5808 bytes src/test/resources/risc-v/sra | Bin 4748 -> 4552 bytes src/test/resources/risc-v/srai | Bin 4748 -> 4556 bytes src/test/resources/risc-v/srl | Bin 4748 -> 4552 bytes src/test/resources/risc-v/srli | Bin 4748 -> 4556 bytes src/test/resources/risc-v/sub | Bin 4748 -> 4552 bytes src/test/resources/risc-v/sw | Bin 5812 -> 5812 bytes src/test/resources/risc-v/sw.riscv | 1 + src/test/resources/risc-v/swapxor | Bin 4760 -> 4564 bytes src/test/resources/risc-v/test | Bin 5836 -> 5644 bytes src/test/resources/risc-v/xor | Bin 4748 -> 4552 bytes src/test/resources/risc-v/xori | Bin 4748 -> 4556 bytes 62 files changed, 1 insertion(+) diff --git a/src/test/resources/risc-v/add0 b/src/test/resources/risc-v/add0 index 7785b2a23a0449eeae29e2d41438fe25f49896e4..d53471e009316c86f3934f992b57e694aeb4b896 100755 GIT binary patch delta 172 zcmeBCJ)=B9L6}950SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRZ=!6b;U z0AxuBKmPd$}j0C2^22MEKV+CVB`lfS&PbyjWUf2 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aHWZR(T>%s^pByNp%z7WlQk={vBn$v&92lGc literal 4748 zcmeI0&q~8U5XL9{CxT+dOVxu49y~>9d-GyTYZ0WEh&Nd_Hfo?YWp^$06J1?B^VtqRUZv)G! znzfp7b9(a2FPF3JfgLPEY00U;$JYwBXkTE%gLNv_tg2&wkIIVE9-P@S{nqidW2$of z(}Erp^mRes6g12e7IET&03F_Ah%C+KyqI-=VjTnvRk-3B&5Yc1=;Opl{BSXwa+5F%t6U`0yDQaIDqvG(%M4Eo_ud$1Rw6m$X z3%G+>@Xb)c0rtxPQ#aPYxg94kyS)$PQqFJV+&gMQPCFjTXu&ETd@qX%?ux=pE#9LQ MQhx3Zjn)ry-v@F=umAu6 diff --git a/src/test/resources/risc-v/xori b/src/test/resources/risc-v/xori index 396860922f85c9b034b5aae423c504258465b4b4..9970b919c31c6a83ea7945a3034911e94d0ee4e1 100755 GIT binary patch delta 172 zcmeBCJ)=B9L6}950SrtS6c`v8G#FSJST-6z<)3UKpfEW_K*dQy0wON}lvRZ=!6b;U z0AxuBKmPd$}j0C2^22MEKV+CVB`lfS&PbyjWUf2 z3??SZ3o`?iA_Hayrpe|4s`U&!5K#e!kN*`wOcofQk--td1d{?l{RSWwlDrKX-vf;w zj>eBe<1tb#gUaw zzAT_8s0a3~USdf}QD#zUNow(AM!{fFMW8jz3=9Pz+dx1@8lvid=2eOPoDgis&H;(`S From 2e5f72dd0da81779ed2e07ba2ece4a43b8d33c5c Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 14 May 2019 17:40:36 -0700 Subject: [PATCH 42/57] removed initializing registers through add instruction --- src/test/resources/risc-v/sw | Bin 5812 -> 5620 bytes src/test/resources/risc-v/sw.riscv | 1 - 2 files changed, 1 deletion(-) diff --git a/src/test/resources/risc-v/sw b/src/test/resources/risc-v/sw index 4a12e983891160077c00550ebb56842279d81919..2aef06ce26a4592ff64114ab77cfa4668c361c18 100755 GIT binary patch delta 207 zcmdm@`$c<#f-s9H0~nYvC@?TGXfUubux>Oy%fFdL;1Bb}0+vZ4EE5xDCfkUJOimCH z@zsGS29k^nJV25KL;!&R0~3QXgbC#{GROg0EG!T~kh~Te-*ECr5q-|2;^O$?lEk8t z$swX96O*(j9}yK{)R}x!)Oxawm;f(}2m`|ckVYV8og679&AJ3AVm6skOn7pSm;mc7 JAWt2{0{~*pAWHxM delta 399 zcmeyOy+wC|g76$s1~4#TP+(wW&|qL^VB2VXmY;btQ^Dr{{C}AziLgjIN&=M>Wfmuw zF);E2nXE-+#zvV&1qKrnfQ8}Xe>Nc304~JHzyoBnfCwNE z0Lse&X%-eR7szK~u!k_gqyW$~Jv4bMRK5~}8%QaV0imc07-A+*711{dc5w`GjCXQ% z_wYEUlZuPui%SxVN`T_X$|j!`F%i@QdtNWGq@*Y_sk9`ucrv4? zJ)^;7M^S50b)Z$u3=9Pz7k~hZ2m^!E Date: Wed, 15 May 2019 16:13:08 -0700 Subject: [PATCH 43/57] forgot to remove merge tag in lab2test --- src/test/scala/labs/Lab2Test.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/src/test/scala/labs/Lab2Test.scala b/src/test/scala/labs/Lab2Test.scala index 21590724..580ca77c 100644 --- a/src/test/scala/labs/Lab2Test.scala +++ b/src/test/scala/labs/Lab2Test.scala @@ -144,7 +144,6 @@ class SingleCycleStoreTesterLab2 extends CPUFlatSpec { */ class SingleCycleLoadStoreTesterLab2 extends CPUFlatSpec { -<<<<<<< HEAD val tests = InstTests.tests("memory") for (test <- tests) { "Single Cycle CPU" should s"run load/store instruction test ${test.binary}${test.extraName}" in { From 3167ed1e47b25fd8e9dfc4fbc80c7b0659826e4f Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 16:49:52 -0700 Subject: [PATCH 44/57] removed csr test params from lab2test grader, and fivecycle option --- src/test/scala/grading/Lab2Tests.scala | 140 +++++++------------------ 1 file changed, 35 insertions(+), 105 deletions(-) diff --git a/src/test/scala/grading/Lab2Tests.scala b/src/test/scala/grading/Lab2Tests.scala index dae07001..d4d02b38 100644 --- a/src/test/scala/grading/Lab2Tests.scala +++ b/src/test/scala/grading/Lab2Tests.scala @@ -53,85 +53,63 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase](CPUTestCase("add1", Map("single-cycle" -> 1), - Map(), - Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), CPUTestCase("addi1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(0 -> 0, 10 -> 17), Map(), Map()), CPUTestCase("addi2", - Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 6), Map(), Map(0 -> 0, 10 -> 17, 11 -> 93), Map(), Map()), CPUTestCase("slli", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> 1), Map(0 -> 0, 5 -> 1, 6 -> 128), Map(), Map()), CPUTestCase("srai", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> 1024), Map(0 -> 0, 5 -> 1024, 6 -> 8), Map(), Map()), CPUTestCase("srai", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> twoscomp(-1024)), Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), Map(), Map(), "-negative"), CPUTestCase("srli", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> 128), Map(0 -> 0, 5 -> 128, 6 -> 1), Map(), Map()), CPUTestCase("andi", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 200), Map(), Map()), CPUTestCase("ori", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 511), Map(), Map()), CPUTestCase("xori", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 311), Map(), Map()), CPUTestCase("slti", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1),6->1), Map(), Map()), CPUTestCase("sltiu", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), Map(), Map()) @@ -165,16 +143,12 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("lw1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(5 -> BigInt("ffffffff", 16)), Map(), Map()), CPUTestCase("lwfwd", - Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 7), Map(5 -> BigInt("ffffffff", 16), 10 -> 5), Map(5 -> 1, 10 -> 6), Map(), Map()) @@ -206,44 +180,32 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("auipc0", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc1", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 6), Map(10 -> 1234), Map(10 -> 4), Map(), Map()), CPUTestCase("auipc2", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 6), Map(10 -> 1234), Map(10 -> (17 << 12)), Map(), Map()), CPUTestCase("auipc3", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 6), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()), CPUTestCase("lui0", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("lui1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(10 -> 1234), Map(10 -> 4096), Map(), Map()) @@ -278,9 +240,7 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("sw", - Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), - Map(), - Map(), + Map("single-cycle" -> 6, "pipelined" -> 10), Map(5 -> 1234), Map(6 -> 1234), Map(), Map(0x100 -> 1234)) @@ -312,58 +272,42 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("lb", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(5 -> BigInt("04", 16)), Map(), Map()), CPUTestCase("lh", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(5 -> BigInt("0304", 16)), Map(), Map()), CPUTestCase("lbu", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(5 -> BigInt("f4", 16)), Map(), Map()), CPUTestCase("lhu", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(5 -> BigInt("f3f4", 16)), Map(), Map()), CPUTestCase("lb1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(5 -> BigInt("fffffff4", 16)), Map(), Map()), CPUTestCase("lh1", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), + Map("single-cycle" -> 1, "pipelined" -> 5), Map(), Map(5 -> BigInt("fffff3f4", 16)), Map(), Map()), CPUTestCase("sb", - Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), - Map(), - Map(), + Map("single-cycle" -> 6, "pipelined" -> 10), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffffff01", 16))), CPUTestCase("sh", - Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), - Map(), - Map(), + Map("single-cycle" -> 6, "pipelined" -> 10), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffff0001", 16))) @@ -421,9 +365,7 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("jal", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 6), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -458,16 +400,12 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("jalr0", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 6), Map(5 -> 1234, 10 -> 28), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr1", - Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 2, "pipelined" -> 6), Map(5 -> 1234, 10 -> 20), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -503,30 +441,22 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("fibonacci", - Map("single-cycle" -> 300, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 300, "pipelined" -> 6), Map(6->11), Map(6->11,5->89), Map(), Map()), CPUTestCase("naturalsum", - Map("single-cycle" -> 200, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 200, "pipelined" -> 6), Map(), Map(5->55), Map(), Map()), CPUTestCase("multiplier", - Map("single-cycle" -> 1000, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 1000, "pipelined" -> 6), Map(5->23,6->20), Map(5->23*20), Map(), Map()), CPUTestCase("divider", - Map("single-cycle" -> 1000, "five-cycle" -> 6, "pipelined" -> 6), - Map(), - Map(), + Map("single-cycle" -> 1000, "pipelined" -> 6), Map(5->1260,6->30), Map(7->42), Map(), Map()) From ebb25aa7af44919bce4ec23cece1c3b85c9bfd96 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 20:00:09 -0700 Subject: [PATCH 45/57] refactored csr to avoid using utils, restored helpers.scala --- src/main/scala/components/csr.scala | 198 ++++++++++++++------- src/main/scala/components/helpers.scala | 217 ------------------------ 2 files changed, 132 insertions(+), 283 deletions(-) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 17606f84..7b5d0bde 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -5,28 +5,63 @@ package dinocpu import chisel3._ import collection.mutable.LinkedHashMap import chisel3.util._ -import Util._ +//import Util._ import scala.math._ object MCauses { //with interrupt - val machine_soft_int = 0x80000003 - val machine_timer_int = 0x80000007 - val machine_ext_int = 0x8000000b + val machine_soft_int = "h80000003".U + val machine_timer_int = "h80000007".U + val machine_ext_int = "h8000000b".U //non interrupt - val misaligned_fetch = 0x0 - val fetch_access = 0x1 - val illegal_instruction = 0x2 - val breakpoint = 0x3 - val misaligned_load = 0x4 - val load_access = 0x5 - val misaligned_store = 0x6 - val store_access = 0x7 - val machine_ecall = 0xb + val misaligned_fetch = "h0".U + val fetch_access = "h1".U + val illegal_instruction = "h2".U + val breakpoint = "h3".U + val misaligned_load = "h4".U + val load_access = "h5".U + val misaligned_store = "h6".U + val store_access = "h7".U + val machine_ecall = "hb".U } +/* +object MCSRs { + //machine information registers + val mvendorid = "hf11".U //vendor id + val marchid = "hf12".U //architecture id + val mimpid = "hf13".U //implementation id + val mhartid = "hf14".U //hardware thread id + //machine trap setup + val mstatus = "h300".U //machine status reg + val misa = "h301".U //isa and extensions + val medeleg = "h302".U //machine exception delegation reg + val mideleg = "h303".U //machine interrupt delegation reg + val mie = "h304".U //machine iterrupt-enable reg + val mtvec = "h305".U //machine trap handler base address + val mcounteren = "h306".U //machine counter enable + + //machine trap handling + val mscratch = "h340".U //scratch reg for machine trap handlers + val mepc = "h341".U //machine exception program counter + val mcause = "h342".U //machine trap cause + val mtval = "h343".U //machine bad address or instruction + val mip = "h344".U //machine interrupt pending + + //machine memory protection + //DONT NEED + + //machine counter/timers + val mcycle = "hb00".U //machine cycle counter + val minstret = "hb02".U //machine instructions retured counter + val mcycleh = "hb80".U + val minstreth = "hb82".U + //performance counter setup + val mcounterinhibit = "h320".U +} +*/ object MCSRs { //machine information registers val mvendorid = 0xf11 //vendor id @@ -175,29 +210,29 @@ object MCSRCmd{ val MSB = 31 val LSB = 20 val TRAPADDR = "h80000000".U - val MPRV = 3 + val MPRV = 3.U } class CSRRegFile extends Module{ //INIT CSR val io = IO(new Bundle{ - val illegal_inst = Input(Bool())// - val retire_inst = Input(Bool())// - val pc = Input(UInt(32.W)) // - val read_data = Input(UInt(32.W)) // - val inst = Input(UInt(32.W)) // - val immid = Input(UInt(32.W)) // + val illegal_inst = Input(Bool())//an exception signal for a non existent instruction or bad fields + val retire_inst = Input(Bool())//asserted if a valid instruction has finished + val pc = Input(UInt(32.W)) //current program counter value + val read_data = Input(UInt(32.W))//data from reg file used in csr instructions + val inst = Input(UInt(32.W)) //full instruction used for decoding csrs internally + val immid = Input(UInt(32.W)) //sext immidiate for immidiate csr instructions - val read_illegal = Output(Bool()) - val write_illegal = Output(Bool()) - val system_illegal = Output(Bool()) - val csr_stall = Output(Bool())//not needed in single cycle + val read_illegal = Output(Bool())//an exception raised interally by a bad csr inst, used to raise illegal inst signal + val write_illegal = Output(Bool())//raised interally by a bad csr inst, used to raise illegal inst signal + val system_illegal = Output(Bool())//bad syscall instruction raised interally, used to raise illegal inst signal + val csr_stall = Output(Bool())//used in conjunction with wait for interrupt inst, not needed in single cycle val eret = Output(Bool())//return vector from a trap val evec = Output(UInt(32.W)) //trap address - val write_data = Output(UInt(32.W)) // - val reg_write = Output(Bool())// + val write_data = Output(UInt(32.W)) //previous csr reg state sent to GP registers + val reg_write = Output(Bool())//should we allow write_data to be written into GP registers? val status = Output(new MStatus())//not needed in this design but useful if more ISA extensions - val time = Output(UInt(32.W))// + val time = Output(UInt(32.W))//time of operation in cpu cycles }) io := DontCare @@ -255,8 +290,8 @@ class CSRRegFile extends Module{ //this is done to make decoding and working with csr's easier (avoid manual specification) val read_mapping = collection.mutable.LinkedHashMap[Int,Bits]( MCSRs.mcounterinhibit -> reg_mcounterinhibit.asUInt, - MCSRs.mcycle -> reg_time, - MCSRs.minstret -> reg_instret, + MCSRs.mcycle -> reg_time.value, + MCSRs.minstret -> reg_instret.value, MCSRs.mimpid -> 0.U, MCSRs.marchid -> 0.U, MCSRs.mvendorid -> 0.U, @@ -321,7 +356,7 @@ class CSRRegFile extends Module{ //map is an infix operator on read_mapping. takes argument from decoded_addr() and applies it to //read_mapping which provides a set if it exists then checks if the csr in the set corresponds to //what the csr instruction specified. used for easier when statements below - val decoded_addr = read_mapping map { case (k, v) => k -> (csr === k) } + val decoded_addr = read_mapping map { case (k, v) => k -> (csr === k.U) } val priv_sufficient = MCSRCmd.MPRV >= csr(9,8) val read_only = csr(11,10).andR val cpu_wen = cpu_ren && cmd =/= MCSRCmd.read && priv_sufficient @@ -336,10 +371,10 @@ class CSRRegFile extends Module{ //wait for interrupt inst not implemented val insn_wfi = system_insn && opcode(5) && priv_sufficient - private def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map( { case(k: Int, _: Bits) => csr === k }).reduce(_ || _) - io.read_illegal := 3 < csr(9,8) || !decodeAny(read_mapping) + private def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map( { case(k: Int, _: Bits) => csr === k.U }).reduce(_ || _) + io.read_illegal := 3.U < csr(9,8) || !decodeAny(read_mapping) io.write_illegal := csr(11,10).andR - io.system_illegal := 3 < csr(9,8) + io.system_illegal := 3.U < csr(9,8) io.status := reg_mstatus @@ -375,14 +410,14 @@ class CSRRegFile extends Module{ //assert(PopCount(insn_ret :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") - when (reg_time >= reg_mtimecmp) { - reg_mip.mtix := true + when (reg_time.value >= reg_mtimecmp) { + reg_mip.mtix := true.B } //MRET when (insn_ret && !csr(10)) { reg_mstatus.mie := reg_mstatus.mpie - reg_mstatus.mpie := true + reg_mstatus.mpie := true.B io.evec := reg_mepc } @@ -400,7 +435,7 @@ class CSRRegFile extends Module{ reg_mcause.exceptioncode := MCauses.breakpoint & "h7fffffff".U } - io.time := reg_time + io.time := reg_time.value io.csr_stall := reg_wfi @@ -427,18 +462,18 @@ class CSRRegFile extends Module{ reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie //unused bits in mstatus m-mode only specified by spec - reg_mstatus.spp := 0 - reg_mstatus.uie := 0 - reg_mstatus.upie := 0 - reg_mstatus.mprv := 0 - reg_mstatus.mxr := 0 - reg_mstatus.sum := 0 - reg_mstatus.tvm := 0 - reg_mstatus.tw := 0 - reg_mstatus.tsr := 0 - reg_mstatus.fs := 0 - reg_mstatus.xs := 0 - reg_mstatus.sd := 0 + reg_mstatus.spp := 0.U + reg_mstatus.uie := 0.U + reg_mstatus.upie := 0.U + reg_mstatus.mprv := 0.U + reg_mstatus.mxr := 0.U + reg_mstatus.sum := 0.U + reg_mstatus.tvm := 0.U + reg_mstatus.tw := 0.U + reg_mstatus.tsr := 0.U + reg_mstatus.fs := 0.U + reg_mstatus.xs := 0.U + reg_mstatus.sd := 0.U } //MTVEC IS FIXED IN THIS IMPLEMENTATION @@ -455,12 +490,12 @@ class CSRRegFile extends Module{ when (decoded_addr(MCSRs.mip)) { val new_mip = wdata.asTypeOf(new MIx()) reg_mip.msix := new_mip.msix - reg_mip.seix := 0 - reg_mip.ueix := 0 - reg_mip.stix := 0 - reg_mip.utix := 0 - reg_mip.ssix := 0 - reg_mip.usix := 0 + reg_mip.seix := 0.U + reg_mip.ueix := 0.U + reg_mip.stix := 0.U + reg_mip.utix := 0.U + reg_mip.ssix := 0.U + reg_mip.usix := 0.U } //MIE @@ -472,12 +507,12 @@ class CSRRegFile extends Module{ reg_mie.meix := new_mie.meix reg_mie.msix := new_mie.msix reg_mie.mtix := new_mie.mtix - reg_mip.seix := 0 - reg_mip.ueix := 0 - reg_mip.stix := 0 - reg_mip.utix := 0 - reg_mip.ssix := 0 - reg_mip.usix := 0 + reg_mip.seix := 0.U + reg_mip.ueix := 0.U + reg_mip.stix := 0.U + reg_mip.utix := 0.U + reg_mip.ssix := 0.U + reg_mip.usix := 0.U } //MCOUNTEREB IS FIXED IN THIS IMPLEMENTATION BECAUSE NO S | U MODE @@ -489,10 +524,10 @@ class CSRRegFile extends Module{ when (decoded_addr(MCSRs.mcounterinhibit)) { val new_mcounterinhibit = wdata.asTypeOf(new XCounterEnInhibit()) reg_mcounterinhibit := new_mcounterinhibit - if( reg_mcounterinhibit.cy == false.B) { + when( reg_mcounterinhibit.cy === false.B) { writeCounter(MCSRs.mcycle, reg_time, wdata) } - if( reg_mcounterinhibit.ir == false.B){ + when( reg_mcounterinhibit.ir === false.B){ writeCounter(MCSRs.minstret, reg_instret, wdata) } } @@ -519,9 +554,40 @@ class CSRRegFile extends Module{ } def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { val hi = lo + MCSRs.mcycleh - MCSRs.mcycle - when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } - when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } + when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.value.getWidth-33, 0), ctr.value(31, 0)) } + when (decoded_addr(lo)) { ctr := Cat(ctr.value(ctr.value.getWidth-1, 32), wdata) } } + def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = -(Mux(cmd.isOneOf(MCSRCmd.set, MCSRCmd.clear), rdata, 0.U) | wdata) & ~Mux(cmd === MCSRCmd.clear, wdata, 0.U) +(Mux(Seq(MCSRCmd.set, MCSRCmd.clear).map(cmd === _).reduce(_||_), rdata, 0.U) | wdata) & ~Mux(cmd === MCSRCmd.clear, wdata, 0.U) +} + +case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true) +{ + private val isWide = width > 2*inc.getWidth + private val smallWidth = if (isWide) inc.getWidth max log2Ceil(width) else width + private val small = if (reset) RegInit(0.asUInt(smallWidth.W)) else Reg(UInt(smallWidth.W)) + private val nextSmall = small +& inc + small := nextSmall + + private val large = if (isWide) { + val r = if (reset) RegInit(0.asUInt((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W)) + when (nextSmall(smallWidth)) { r := r + 1.U } + r + } else null + + val value = if (isWide) Cat(large, small) else small + lazy val carryOut = { + val lo = (small ^ nextSmall) >> 1 + if (!isWide) lo else { + val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1 + Cat(hi, lo) + } + } + + def := (x: UInt) = { + small := x + if (isWide) large := x >> smallWidth + } } + diff --git a/src/main/scala/components/helpers.scala b/src/main/scala/components/helpers.scala index 053b46e5..1818febd 100644 --- a/src/main/scala/components/helpers.scala +++ b/src/main/scala/components/helpers.scala @@ -4,223 +4,6 @@ package dinocpu import chisel3._ import chisel3.util._ -import scala.math._ -import scala.collection.mutable.ArrayBuffer - -object Util -{ - implicit def intToUInt(x: Int): UInt = x.U - implicit def intToBoolean(x: Int): Boolean = if (x != 0) true else false - implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0 - implicit def booleanToBool(x: Boolean): Bool = x.B - implicit def sextToConv(x: UInt) = new AnyRef { - def sextTo(n: Int): UInt = Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) - } - - implicit def wcToUInt(c: WideCounter): UInt = c.value - implicit class UIntIsOneOf(val x: UInt) extends AnyVal { - def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).reduce(_||_) - - def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) - } - - implicit class UIntToAugmentedUInt(val x: UInt) extends AnyVal { - def sextTo(n: Int): UInt = { - require(x.getWidth <= n) - if (x.getWidth == n) x - else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) - } - - def padTo(n: Int): UInt = { - require(x.getWidth <= n) - if (x.getWidth == n) x - else Cat(0.U((n - x.getWidth).W), x) - } - - def extract(hi: Int, lo: Int): UInt = { - if (hi == lo-1) 0.U - else x(hi, lo) - } - - def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds - } -} - - -//do two masks have at least 1 bit match? -object maskMatch -{ - def apply(msk1: UInt, msk2: UInt): Bool = - { - val br_match = (msk1 & msk2) =/= 0.U - return br_match - } -} - -//clear one-bit in the Mask as specified by the idx -object clearMaskBit -{ - def apply(msk: UInt, idx: UInt): UInt = - { - return (msk & ~(1.U << idx))(msk.getWidth-1, 0) - } -} - -//shift a register over by one bit -object PerformShiftRegister -{ - def apply(reg_val: Bits, new_bit: Bool): Bits = - { - reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt(), new_bit.asUInt()).asUInt() - reg_val - } -} - -object Split -{ - // is there a better way to do do this? - def apply(x: Bits, n0: Int) = { - val w = checkWidth(x, n0) - (x(w-1,n0), x(n0-1,0)) - } - def apply(x: Bits, n1: Int, n0: Int) = { - val w = checkWidth(x, n1, n0) - (x(w-1,n1), x(n1-1,n0), x(n0-1,0)) - } - def apply(x: Bits, n2: Int, n1: Int, n0: Int) = { - val w = checkWidth(x, n2, n1, n0) - (x(w-1,n2), x(n2-1,n1), x(n1-1,n0), x(n0-1,0)) - } - - private def checkWidth(x: Bits, n: Int*) = { - val w = x.getWidth - def decreasing(x: Seq[Int]): Boolean = - if (x.tail.isEmpty) true - else x.head > x.tail.head && decreasing(x.tail) - require(decreasing(w :: n.toList)) - w - } -} - - -// a counter that clock gates most of its MSBs using the LSB carry-out -case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true) -{ - private val isWide = width > 2*inc.getWidth - private val smallWidth = if (isWide) inc.getWidth max log2Ceil(width) else width - private val small = if (reset) RegInit(0.asUInt(smallWidth.W)) else Reg(UInt(smallWidth.W)) - private val nextSmall = small +& inc - small := nextSmall - - private val large = if (isWide) { - val r = if (reset) RegInit(0.asUInt((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W)) - when (nextSmall(smallWidth)) { r := r + 1.U } - r - } else null - - val value = if (isWide) Cat(large, small) else small - lazy val carryOut = { - val lo = (small ^ nextSmall) >> 1 - if (!isWide) lo else { - val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1 - Cat(hi, lo) - } - } - - def := (x: UInt) = { - small := x - if (isWide) large := x >> smallWidth - } -} - -// taken from rocket FPU -object RegEn -{ - def apply[T <: Data](data: T, en: Bool) = - { - val r = Reg(data) - when (en) { r := data } - r - } - def apply[T <: Bits](data: T, en: Bool, resetVal: T) = - { - val r = RegInit(resetVal) - when (en) { r := data } - r - } -} - -object Str -{ - def apply(s: String): UInt = { - var i = BigInt(0) - require(s.forall(validChar _)) - for (c <- s) - i = (i << 8) | c - i.asUInt((s.length*8).W) - } - def apply(x: Char): Bits = { - require(validChar(x)) - val lit = x.asUInt(8.W) - lit - } - def apply(x: UInt): Bits = apply(x, 10) - def apply(x: UInt, radix: Int): Bits = { - val rad = radix.U - val digs = digits(radix) - val w = x.getWidth - require(w > 0) - - var q = x - var s = digs(q % rad) - for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { - q = q / rad - s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digs(q % rad)), s) - } - s - } - def apply(x: SInt): Bits = apply(x, 10) - def apply(x: SInt, radix: Int): Bits = { - val neg = x < 0.S - val abs = Mux(neg, -x, x).asUInt() - if (radix != 10) { - Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) - } else { - val rad = radix.U - val digs = digits(radix) - val w = abs.getWidth - require(w > 0) - - var q = abs - var s = digs(q % rad) - var needSign = neg - for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { - q = q / rad - val placeSpace = q === 0.U - val space = Mux(needSign, Str('-'), Str(' ')) - needSign = needSign && !placeSpace - s = Cat(Mux(placeSpace, space, digs(q % rad)), s) - } - Cat(Mux(needSign, Str('-'), Str(' ')), s) - } - } - - def bigIntToString(x: BigInt): String = { - val s = new StringBuilder - var b = x - while (b != 0) { - s += (x & 0xFF).toChar - b = b >> 8 - } - s.toString - } - - private def digit(d: Int): Char = (if (d < 10) '0'+d else 'a'-10+d).toChar - private def digits(radix: Int): Vec[Bits] = - VecInit((0 until radix).map(i => Str(digit(i)))) - - private def validChar(x: Char) = x == (x & 0xFF) -} /** * A simple adder which takes two inputs and returns the sum * From 2c0af034bceb5774d4a8dbb3854d1a736133aee8 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 20:00:37 -0700 Subject: [PATCH 46/57] removed util header from csr --- src/main/scala/components/csr.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 7b5d0bde..9b6612cb 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -5,7 +5,6 @@ package dinocpu import chisel3._ import collection.mutable.LinkedHashMap import chisel3.util._ -//import Util._ import scala.math._ From dab43b157ef4f7627dc35d5ec18cb5331917a951 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 20:05:41 -0700 Subject: [PATCH 47/57] added comments for widecounter class, removed mcsr object using UInt as initialization --- src/main/scala/components/csr.scala | 41 +++++------------------------ 1 file changed, 6 insertions(+), 35 deletions(-) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 9b6612cb..0dd388ed 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -26,41 +26,6 @@ object MCauses { val machine_ecall = "hb".U } -/* -object MCSRs { - //machine information registers - val mvendorid = "hf11".U //vendor id - val marchid = "hf12".U //architecture id - val mimpid = "hf13".U //implementation id - val mhartid = "hf14".U //hardware thread id - //machine trap setup - val mstatus = "h300".U //machine status reg - val misa = "h301".U //isa and extensions - val medeleg = "h302".U //machine exception delegation reg - val mideleg = "h303".U //machine interrupt delegation reg - val mie = "h304".U //machine iterrupt-enable reg - val mtvec = "h305".U //machine trap handler base address - val mcounteren = "h306".U //machine counter enable - - //machine trap handling - val mscratch = "h340".U //scratch reg for machine trap handlers - val mepc = "h341".U //machine exception program counter - val mcause = "h342".U //machine trap cause - val mtval = "h343".U //machine bad address or instruction - val mip = "h344".U //machine interrupt pending - - //machine memory protection - //DONT NEED - - //machine counter/timers - val mcycle = "hb00".U //machine cycle counter - val minstret = "hb02".U //machine instructions retured counter - val mcycleh = "hb80".U - val minstreth = "hb82".U - //performance counter setup - val mcounterinhibit = "h320".U -} -*/ object MCSRs { //machine information registers val mvendorid = 0xf11 //vendor id @@ -551,16 +516,22 @@ class CSRRegFile extends Module{ when (decoded_addr(MCSRs.mtval)) { reg_mtval := wdata(32-1,0) } when (decoded_addr(MCSRs.medeleg)) { reg_medeleg := wdata(32-1,0) } } + + //takes counter data and data to write and modifies it 32 bits at a time def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { val hi = lo + MCSRs.mcycleh - MCSRs.mcycle when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.value.getWidth-33, 0), ctr.value(31, 0)) } when (decoded_addr(lo)) { ctr := Cat(ctr.value(ctr.value.getWidth-1, 32), wdata) } } + //takes in csr command and sees if it maps to any int the defined sequence and determines + //resulting csr data with bitwise operations def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = (Mux(Seq(MCSRCmd.set, MCSRCmd.clear).map(cmd === _).reduce(_||_), rdata, 0.U) | wdata) & ~Mux(cmd === MCSRCmd.clear, wdata, 0.U) } +//used for timers and performance counters. case class lets us use comparison +//operators on the content of the object rather than the reference to the object case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true) { private val isWide = width > 2*inc.getWidth From 731cf6718fd976ab09f8719cf96dd3e25113732f Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 20:10:33 -0700 Subject: [PATCH 48/57] Removed CSR from testing for time being until we find a good way of testing it --- src/main/scala/testing/CPUTesterDriver.scala | 30 +----- src/main/scala/testing/InstTests.scala | 100 +------------------ 2 files changed, 4 insertions(+), 126 deletions(-) diff --git a/src/main/scala/testing/CPUTesterDriver.scala b/src/main/scala/testing/CPUTesterDriver.scala index b3e1efbe..858955ad 100644 --- a/src/main/scala/testing/CPUTesterDriver.scala +++ b/src/main/scala/testing/CPUTesterDriver.scala @@ -59,12 +59,6 @@ class CPUTesterDriver(cpuType: String, simulator.reset(5) } - def initCSR(vals: Map[Int, BigInt]) { - for ((num, value) <- vals) { - simulator.poke(s"cpu.csr.read_mapping_$num", value) - } - } - def initRegs(vals: Map[Int, BigInt]) { for ((num, value) <- vals) { simulator.poke(s"cpu.registers.regs_$num", value) @@ -81,22 +75,6 @@ class CPUTesterDriver(cpuType: String, } } - def checkCSR(vals: Map[Int, BigInt]): Boolean = { - var success = true - for ((num, value) <- vals) { - try { - simulator.expect(s"cpu.csr.read_mapping_$num", value) - } catch { - case _: TreadleException => { - success = false - val real = simulator.peek(s"cpu.csr.read_mapping_$num") - println(s"CSR $num failed to match. Was $real. Should be $value") - } - } - } - success - } - def checkRegs(vals: Map[Int, BigInt]): Boolean = { var success = true for ((num, value) <- vals) { @@ -150,8 +128,6 @@ class CPUTesterDriver(cpuType: String, case class CPUTestCase( binary: String, cycles: Map[String, Int], - initCSR: Map[Int, BigInt], - checkCSR: Map[Int, BigInt], initRegs: Map[Int, BigInt], checkRegs: Map[Int, BigInt], initMem: Map[Int, BigInt], @@ -167,11 +143,9 @@ case class CPUTestCase( object CPUTesterDriver { def apply(testCase: CPUTestCase, cpuType: String, branchPredictor: String = ""): Boolean = { val driver = new CPUTesterDriver(cpuType, branchPredictor, testCase.binary, testCase.extraName) - driver.initCSR(testCase.initCSR) - driver.initRegs(testCase.initRegs) driver.initMemory(testCase.initMem) driver.run(testCase.cycles(cpuType)) - val success = driver.checkCSR(testCase.checkCSR) - success && driver.checkRegs(testCase.checkRegs) && driver.checkMemory(testCase.checkMem) + val success = driver.checkRegs(testCase.checkRegs) + success && driver.checkMemory(testCase.checkMem) } } diff --git a/src/main/scala/testing/InstTests.scala b/src/main/scala/testing/InstTests.scala index 71f077b7..a3f818fb 100644 --- a/src/main/scala/testing/InstTests.scala +++ b/src/main/scala/testing/InstTests.scala @@ -9,8 +9,6 @@ package dinocpu * Each test case looks like: * - binary to run in src/test/resources/risc-v * - number of cycles to run for each CPU type - * - initial values for csr registers - * - final values to check for csr registers * - initial values for registers * - final values to check for registers * - initial values for memory @@ -32,85 +30,71 @@ object InstTests { val rtype = List[CPUTestCase]( CPUTestCase("add1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), CPUTestCase("add2", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1234, 20 -> 5678), Map(0 -> 0, 10 -> 6912), Map(), Map()), CPUTestCase("add0", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1234, 6 -> 3456), Map(0 -> 0, 5 -> 1234, 6 -> 3456), Map(), Map()), CPUTestCase("or", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1234, 6 -> 5678), Map(7 -> 5886), Map(), Map()), CPUTestCase("sub", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1234, 6 -> 5678), Map(7 -> BigInt("FFFFEEA4", 16)), Map(), Map()), CPUTestCase("and", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1234, 6 -> 5678), Map(7 -> 1026), Map(), Map()), CPUTestCase("xor", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> 1234, 5 -> 5678), Map(5 -> 5678, 7 -> 1234, 6 -> 4860), Map(), Map()), CPUTestCase("slt", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> 1234, 5 -> 5678), Map(5 -> 5678, 7 -> 1234, 6 -> 1), Map(), Map()), CPUTestCase("slt1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> -1, 5 -> 1), Map(5 -> 1, 6 -> 1), Map(), Map()), CPUTestCase("sltu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> -1, 5 -> 1), Map(5 -> 1, 6 -> 0), Map(), Map()), CPUTestCase("sltu1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> 20, 5 -> 100), Map(5 -> 100, 6 -> 1), Map(), Map()), CPUTestCase("sll", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> 32, 5 -> 2), Map(7 -> 32, 5 -> 2, 6 -> 128), Map(), Map()), CPUTestCase("srl", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> 32, 5 -> 2), Map(7 -> 32, 5 -> 2, 6 -> 8), Map(), Map()), CPUTestCase("sra", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(7 -> twoscomp(-2), 5 -> 31), Map(5 -> 31, 6 -> twoscomp(-1)), Map(), Map()) @@ -119,49 +103,41 @@ object InstTests { val rtypeMultiCycle = List[CPUTestCase]( CPUTestCase("addfwd", Map("single-cycle" -> 10, "pipelined" -> 14), - Map(), Map(), Map(5 -> 1, 10 -> 0), Map(5 -> 1, 10 -> 10), Map(), Map()), CPUTestCase("swapxor", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map(), Map(7 -> 5678, 5 -> 1234), Map(5 -> 5678,7->1234), Map(), Map()), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map(), Map(5 -> 512, 6->1), Map(7->1), Map(), Map(), "-512"), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map(), Map(5 -> 1234, 6->1), Map(7->0), Map(), Map(), "-1234"), CPUTestCase("power2", Map("single-cycle" -> 3, "pipelined" -> 7), - Map(), Map(), Map(5 -> twoscomp(-65536), 6->1), Map(7->0), // This algorithm doesn't work for negative numbers Map(), Map(), "--65536"), CPUTestCase("oppsign", Map("single-cycle" -> 2, "pipelined" -> 7), - Map(), Map(), Map(5 -> 512, 6->twoscomp(-1024),7->0), Map(7->1), Map(), Map(), "-true"), CPUTestCase("oppsign", Map("single-cycle" -> 2, "pipelined" -> 7), - Map(), Map(), Map(5 -> 512, 6->1024,7->0), Map(7->0), Map(), Map(), "-false"), CPUTestCase("rotR", Map("single-cycle" -> 4, "pipelined" -> 8), - Map(), Map(), Map(5 -> twoscomp(-1), 6->1, 7->32), Map(7->twoscomp(-1)), Map(), Map()) @@ -170,61 +146,51 @@ object InstTests { val itype = List[CPUTestCase]( CPUTestCase("addi1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(0 -> 0, 10 -> 17), Map(), Map()), CPUTestCase("slli", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1), Map(0 -> 0, 5 -> 1, 6 -> 128), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 1024), Map(0 -> 0, 5 -> 1024, 6 -> 8), Map(), Map()), CPUTestCase("srai", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> twoscomp(-1024)), Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), Map(), Map(), "-negative"), CPUTestCase("srli", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 128), Map(0 -> 0, 5 -> 128, 6 -> 1), Map(), Map()), CPUTestCase("andi", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 200), Map(), Map()), CPUTestCase("ori", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 511), Map(), Map()), CPUTestCase("xori", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 311), Map(), Map()), CPUTestCase("slti", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1),6->1), Map(), Map()), CPUTestCase("sltiu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), Map(), Map()) @@ -233,7 +199,6 @@ object InstTests { val itypeMultiCycle = List[CPUTestCase]( CPUTestCase("addi2", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map(), Map(), Map(0 -> 0, 10 -> 17, 11 -> 93), Map(), Map()) @@ -242,109 +207,91 @@ object InstTests { val branch = List[CPUTestCase]( CPUTestCase("beq", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-False"), CPUTestCase("beq", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-True"), CPUTestCase("bne", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("bne", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-True"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-False-equal"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-True"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), Map(5 -> 0, 6 -> 1, 7 -> 9012, 28 -> twoscomp(-1)), Map(), Map(), "-False-signed"), CPUTestCase("blt", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-10000), 28 -> twoscomp(-1000)), Map(), Map(), "-True-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> 9012), Map(), Map(), "-False"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 9012, 28 -> 5678), Map(), Map(), "-True"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), Map(5 -> 0, 6 -> 1, 7 -> twoscomp(-1), 28 -> 9012), Map(), Map(), "-False-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), Map(5 -> 1235, 6 -> 1, 7 -> twoscomp(-1000), 28 -> twoscomp(-10000)), Map(), Map(), "-True-signed"), CPUTestCase("bge", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> 5678), Map(), Map(), "-True-equal"), CPUTestCase("bltu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(5 -> 0, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(), Map(), "-False"), CPUTestCase("bltu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(5 -> 1235, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(), Map(), "-True"), CPUTestCase("bgeu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(5 -> 0, 6 -> 1, 7 -> 5678, 28 -> maxInt), Map(), Map(), "-False"), CPUTestCase("bgeu", Map("single-cycle" -> 3, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(5 -> 1235, 6 -> 1, 7 -> maxInt, 28 -> 5678), Map(), Map(), "-True") @@ -366,61 +313,51 @@ object InstTests { val memory = List[CPUTestCase]( CPUTestCase("lw1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(5 -> BigInt("ffffffff", 16)), Map(), Map()), CPUTestCase("lb", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(5 -> BigInt("04", 16)), Map(), Map()), CPUTestCase("lh", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(5 -> BigInt("0304", 16)), Map(), Map()), CPUTestCase("lbu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(5 -> BigInt("f4", 16)), Map(), Map()), CPUTestCase("lhu", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(5 -> BigInt("f3f4", 16)), Map(), Map()), CPUTestCase("lb1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(5 -> BigInt("fffffff4", 16)), Map(), Map()), CPUTestCase("lh1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(5 -> BigInt("fffff3f4", 16)), Map(), Map()), CPUTestCase("sw", Map("single-cycle" -> 6, "pipelined" -> 10), - Map(), Map(), Map(5 -> 1234), Map(6 -> 1234), Map(), Map(0x100 -> 1234)), CPUTestCase("sb", Map("single-cycle" -> 6, "pipelined" -> 10), - Map(), Map(), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffffff01", 16))), CPUTestCase("sh", Map("single-cycle" -> 6, "pipelined" -> 10), - Map(), Map(), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffff0001", 16))) @@ -429,7 +366,6 @@ object InstTests { val memoryMultiCycle = List[CPUTestCase]( CPUTestCase("lwfwd", Map("single-cycle" -> 2, "pipelined" -> 7), - Map(), Map(), Map(5 -> BigInt("ffffffff", 16), 10 -> 5), Map(5 -> 1, 10 -> 6), Map(), Map()), @@ -448,37 +384,31 @@ object InstTests { val utype = List[CPUTestCase]( CPUTestCase("auipc0", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc2", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map(), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc1", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map(), Map(10 -> 1234), Map(10 -> (17 << 12)), Map(), Map()), CPUTestCase("auipc3", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map(), Map(10 -> 1234), Map(10 -> 4), Map(), Map()), CPUTestCase("lui0", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()), CPUTestCase("lui1", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(10 -> 1234), Map(10 -> 4096), Map(), Map()) @@ -487,13 +417,11 @@ object InstTests { val utypeMultiCycle = List[CPUTestCase]( CPUTestCase("auipc1", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map(), Map(10 -> 1234), Map(10 -> 4), Map(), Map()), CPUTestCase("auipc3", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(), Map(), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()) @@ -502,19 +430,16 @@ object InstTests { val jump = List[CPUTestCase]( CPUTestCase("jal", Map("single-cycle" -> 2, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr0", Map("single-cycle" -> 2, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 10 -> 28), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr1", Map("single-cycle" -> 2, "pipelined" -> 9), - Map(), Map(), Map(5 -> 1234, 10 -> 20), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -523,56 +448,46 @@ object InstTests { val csr = List[CPUTestCase]( CPUTestCase("csrrc", Map("single-cycle" -> 1, "pipelined" -> 5), - Map( 0x300 -> 0x1888 ), - Map( 0x300 -> 0xffffe777 ), - Map( 6 -> 0xfffffffb), - Map( 6 -> 0xfffffffb), + Map(), + Map(), Map(), Map()), CPUTestCase("csrrci", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()), CPUTestCase("csrrs", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()), CPUTestCase("csrrsi", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()), CPUTestCase("csrrw", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()), CPUTestCase("csrrwi", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()), CPUTestCase("ecall", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()), CPUTestCase("ebreak", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()), CPUTestCase("mret", Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), Map(), Map(), Map(), Map(), Map()) @@ -582,25 +497,21 @@ object InstTests { val smallApplications = List[CPUTestCase]( CPUTestCase("fibonacci", Map("single-cycle" -> 300, "pipelined" -> 1000), - Map(), Map(), Map(6->11), Map(6->11,5->89), Map(), Map()), CPUTestCase("naturalsum", Map("single-cycle" -> 200, "pipelined" -> 500), - Map(), Map(), Map(), Map(5->55), Map(), Map()), CPUTestCase("multiplier", Map("single-cycle" -> 1000, "pipelined" -> 1000), - Map(), Map(), Map(5->23,6->20,8->0x1000), Map(5->23*20), Map(), Map()), CPUTestCase("divider", Map("single-cycle" -> 1000, "pipelined" -> 2000), - Map(), Map(), Map(5->1260,6->30), Map(7->42), Map(), Map()) @@ -609,37 +520,31 @@ object InstTests { val fullApplications = List[CPUTestCase]( CPUTestCase("multiply.riscv", Map("single-cycle" -> 42342, "pipelined" -> 100000), - Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("median.riscv", Map("single-cycle" -> 9433, "pipelined" -> 100000), - Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("qsort.riscv", Map("single-cycle" -> 263290, "pipelined" -> 300000), - Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("rsort.riscv", Map("single-cycle" -> 263290, "pipelined" -> 250000), - Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("towers.riscv", Map("single-cycle" -> 12653, "pipelined" -> 100000), - Map(), Map(), Map(), Map(10->12345678), Map(), Map()), CPUTestCase("vvadd.riscv", Map("single-cycle" -> 5484, "pipelined" -> 20000), - Map(), Map(), Map(), Map(10->12345678), Map(), Map()) @@ -663,7 +568,6 @@ object InstTests { ) // All of the tests -<<<<<<< HEAD val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ branchMultiCycle ++ memory ++ memoryMultiCycle ++ utype ++ utypeMultiCycle ++ jump ++ csr ++ smallApplications From 059e4d4c718988d8594d17b265cc99ad8c8f048f Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 20:15:09 -0700 Subject: [PATCH 49/57] removed csr from grading tests --- src/test/scala/grading/Lab1Tests.scala | 2 -- src/test/scala/grading/Lab2Tests.scala | 2 -- 2 files changed, 4 deletions(-) diff --git a/src/test/scala/grading/Lab1Tests.scala b/src/test/scala/grading/Lab1Tests.scala index b013ae42..b18fb5ec 100644 --- a/src/test/scala/grading/Lab1Tests.scala +++ b/src/test/scala/grading/Lab1Tests.scala @@ -41,7 +41,6 @@ class Lab1Grader extends JUnitSuite { var success = CPUTesterDriver(CPUTestCase("add1", Map("single-cycle" -> 1), - Map(), Map(), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), @@ -49,7 +48,6 @@ class Lab1Grader extends JUnitSuite { success = CPUTesterDriver(CPUTestCase("add2", Map("single-cycle" -> 1), - Map(), Map(), Map(5 -> 1234, 20 -> 5678), Map(0 -> 0, 10 -> 6912), Map(), Map()), diff --git a/src/test/scala/grading/Lab2Tests.scala b/src/test/scala/grading/Lab2Tests.scala index d4d02b38..e14d3d18 100644 --- a/src/test/scala/grading/Lab2Tests.scala +++ b/src/test/scala/grading/Lab2Tests.scala @@ -93,8 +93,6 @@ class Lab2Grader extends JUnitSuite { Map(), Map()), CPUTestCase("ori", Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 511), Map(), Map()), From 10481e013591d3fb690c0a29fdaca0b7ae3658f2 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 20:29:28 -0700 Subject: [PATCH 50/57] corrected a missing line in CPUTesterDriver that initializes registers --- src/main/scala/testing/CPUTesterDriver.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/testing/CPUTesterDriver.scala b/src/main/scala/testing/CPUTesterDriver.scala index 858955ad..05338665 100644 --- a/src/main/scala/testing/CPUTesterDriver.scala +++ b/src/main/scala/testing/CPUTesterDriver.scala @@ -143,6 +143,7 @@ case class CPUTestCase( object CPUTesterDriver { def apply(testCase: CPUTestCase, cpuType: String, branchPredictor: String = ""): Boolean = { val driver = new CPUTesterDriver(cpuType, branchPredictor, testCase.binary, testCase.extraName) + driver.initRegs(testCase.initRegs) driver.initMemory(testCase.initMem) driver.run(testCase.cycles(cpuType)) val success = driver.checkRegs(testCase.checkRegs) From 4cbf05e6f5814c31d227bcf9f1e9607026c6b311 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Wed, 15 May 2019 21:20:36 -0700 Subject: [PATCH 51/57] fixed some tests failing --- src/main/scala/components/helpers.scala | 1 + src/main/scala/testing/InstTests.scala | 64 +--------------------- src/test/scala/grading/Lab2Tests.scala | 72 ++++++++++++------------- 3 files changed, 39 insertions(+), 98 deletions(-) diff --git a/src/main/scala/components/helpers.scala b/src/main/scala/components/helpers.scala index 1818febd..d0bbcd9d 100644 --- a/src/main/scala/components/helpers.scala +++ b/src/main/scala/components/helpers.scala @@ -4,6 +4,7 @@ package dinocpu import chisel3._ import chisel3.util._ + /** * A simple adder which takes two inputs and returns the sum * diff --git a/src/main/scala/testing/InstTests.scala b/src/main/scala/testing/InstTests.scala index a3f818fb..b265a169 100644 --- a/src/main/scala/testing/InstTests.scala +++ b/src/main/scala/testing/InstTests.scala @@ -389,23 +389,13 @@ object InstTests { Map(), Map()), CPUTestCase("auipc2", Map("single-cycle" -> 2, "pipelined" -> 6), - Map(10 -> 1234), - Map(10 -> 0), - Map(), Map()), - CPUTestCase("auipc1", - Map("single-cycle" -> 2, "pipelined" -> 6), Map(10 -> 1234), Map(10 -> (17 << 12)), Map(), Map()), - CPUTestCase("auipc3", - Map("single-cycle" -> 2, "pipelined" -> 6), - Map(10 -> 1234), - Map(10 -> 4), - Map(), Map()), CPUTestCase("lui0", Map("single-cycle" -> 1, "pipelined" -> 5), Map(10 -> 1234), - Map(10 -> ((17 << 12) + 4)), + Map(10 -> 0), Map(), Map()), CPUTestCase("lui1", Map("single-cycle" -> 1, "pipelined" -> 5), @@ -443,55 +433,6 @@ object InstTests { Map(5 -> 1234, 10 -> 20), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) - ) - - val csr = List[CPUTestCase]( - CPUTestCase("csrrc", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrci", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrs", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrsi", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrw", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("csrrwi", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("ecall", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("ebreak", - Map("single-cycle" -> 1, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()), - CPUTestCase("mret", - Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), - Map(), - Map(), - Map(), Map()) - ) val smallApplications = List[CPUTestCase]( @@ -563,13 +504,12 @@ object InstTests { "utype" -> utype, "utypeMultiCycle" -> utypeMultiCycle, "jump" -> jump, - "csr" -> csr, "smallApplications" -> smallApplications ) // All of the tests val allTests = rtype ++ rtypeMultiCycle ++ itype ++ itypeMultiCycle ++ branch ++ branchMultiCycle ++ - memory ++ memoryMultiCycle ++ utype ++ utypeMultiCycle ++ jump ++ csr ++ smallApplications + memory ++ memoryMultiCycle ++ utype ++ utypeMultiCycle ++ jump ++ smallApplications // Mapping from full name of test to test val nameMap = (allTests ++ fullApplications).map(x => x.name() -> x).toMap diff --git a/src/test/scala/grading/Lab2Tests.scala b/src/test/scala/grading/Lab2Tests.scala index e14d3d18..eb3a701a 100644 --- a/src/test/scala/grading/Lab2Tests.scala +++ b/src/test/scala/grading/Lab2Tests.scala @@ -57,57 +57,57 @@ class Lab2Grader extends JUnitSuite { Map(0 -> 0, 5 -> 1234, 6 -> 1234), Map(), Map()), CPUTestCase("addi1", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(0 -> 0, 10 -> 17), Map(), Map()), CPUTestCase("addi2", - Map("single-cycle" -> 2, "pipelined" -> 6), + Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 6), Map(), Map(0 -> 0, 10 -> 17, 11 -> 93), Map(), Map()), CPUTestCase("slli", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> 1), Map(0 -> 0, 5 -> 1, 6 -> 128), Map(), Map()), CPUTestCase("srai", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> 1024), Map(0 -> 0, 5 -> 1024, 6 -> 8), Map(), Map()), CPUTestCase("srai", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> twoscomp(-1024)), Map(0 -> 0, 5 -> twoscomp(-1024), 6 -> twoscomp(-8)), Map(), Map(), "-negative"), CPUTestCase("srli", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> 128), Map(0 -> 0, 5 -> 128, 6 -> 1), Map(), Map()), CPUTestCase("andi", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 200), Map(), Map()), CPUTestCase("ori", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 511), Map(), Map()), CPUTestCase("xori", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> 456), Map(0 -> 0, 5 -> 456, 6 -> 311), Map(), Map()), CPUTestCase("slti", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1),6->1), Map(), Map()), CPUTestCase("sltiu", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(5 -> twoscomp(-1)), Map(0 -> 0, 5 -> twoscomp(-1), 6 -> 0), Map(), Map()) @@ -141,12 +141,12 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("lw1", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(5 -> BigInt("ffffffff", 16)), Map(), Map()), CPUTestCase("lwfwd", - Map("single-cycle" -> 2, "pipelined" -> 7), + Map("single-cycle" -> 2, "five-cycle" -> 0, "pipelined" -> 7), Map(5 -> BigInt("ffffffff", 16), 10 -> 5), Map(5 -> 1, 10 -> 6), Map(), Map()) @@ -178,32 +178,32 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("auipc0", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("auipc1", - Map("single-cycle" -> 2, "pipelined" -> 6), + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), Map(10 -> 1234), Map(10 -> 4), Map(), Map()), CPUTestCase("auipc2", - Map("single-cycle" -> 2, "pipelined" -> 6), + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), Map(10 -> 1234), Map(10 -> (17 << 12)), Map(), Map()), CPUTestCase("auipc3", - Map("single-cycle" -> 2, "pipelined" -> 6), + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), Map(10 -> 1234), Map(10 -> ((17 << 12) + 4)), Map(), Map()), CPUTestCase("lui0", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(10 -> 1234), Map(10 -> 0), Map(), Map()), CPUTestCase("lui1", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(10 -> 1234), Map(10 -> 4096), Map(), Map()) @@ -238,7 +238,7 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("sw", - Map("single-cycle" -> 6, "pipelined" -> 10), + Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), Map(5 -> 1234), Map(6 -> 1234), Map(), Map(0x100 -> 1234)) @@ -270,42 +270,42 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("lb", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(5 -> BigInt("04", 16)), Map(), Map()), CPUTestCase("lh", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(5 -> BigInt("0304", 16)), Map(), Map()), CPUTestCase("lbu", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(5 -> BigInt("f4", 16)), Map(), Map()), CPUTestCase("lhu", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(5 -> BigInt("f3f4", 16)), Map(), Map()), CPUTestCase("lb1", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(5 -> BigInt("fffffff4", 16)), Map(), Map()), CPUTestCase("lh1", - Map("single-cycle" -> 1, "pipelined" -> 5), + Map("single-cycle" -> 1, "five-cycle" -> 5, "pipelined" -> 5), Map(), Map(5 -> BigInt("fffff3f4", 16)), Map(), Map()), CPUTestCase("sb", - Map("single-cycle" -> 6, "pipelined" -> 10), + Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffffff01", 16))), CPUTestCase("sh", - Map("single-cycle" -> 6, "pipelined" -> 10), + Map("single-cycle" -> 6, "five-cycle" -> 10, "pipelined" -> 10), Map(5 -> 1), Map(6 -> 1), Map(), Map(0x100 -> BigInt("ffff0001", 16))) @@ -363,7 +363,7 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("jal", - Map("single-cycle" -> 2, "pipelined" -> 6), + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), Map(5 -> 1234), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -398,12 +398,12 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("jalr0", - Map("single-cycle" -> 2, "pipelined" -> 6), + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), Map(5 -> 1234, 10 -> 28), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()), CPUTestCase("jalr1", - Map("single-cycle" -> 2, "pipelined" -> 6), + Map("single-cycle" -> 2, "five-cycle" -> 6, "pipelined" -> 6), Map(5 -> 1234, 10 -> 20), Map(0 -> 0, 5 -> 1234, 6 -> 1234, 1 -> 4), Map(), Map()) @@ -439,22 +439,22 @@ class Lab2Grader extends JUnitSuite { val tests = List[CPUTestCase]( CPUTestCase("fibonacci", - Map("single-cycle" -> 300, "pipelined" -> 6), + Map("single-cycle" -> 300, "five-cycle" -> 6, "pipelined" -> 6), Map(6->11), Map(6->11,5->89), Map(), Map()), CPUTestCase("naturalsum", - Map("single-cycle" -> 200, "pipelined" -> 6), + Map("single-cycle" -> 200, "five-cycle" -> 6, "pipelined" -> 6), Map(), Map(5->55), Map(), Map()), CPUTestCase("multiplier", - Map("single-cycle" -> 1000, "pipelined" -> 6), - Map(5->23,6->20), + Map("single-cycle" -> 1000, "five-cycle" -> 6, "pipelined" -> 6), + Map(5->23,6->20), Map(5->23*20), Map(), Map()), CPUTestCase("divider", - Map("single-cycle" -> 1000, "pipelined" -> 6), + Map("single-cycle" -> 1000, "five-cycle" -> 6, "pipelined" -> 6), Map(5->1260,6->30), Map(7->42), Map(), Map()) From 8e8afe48e8649bb217606a5f7111a0266ef99c28 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Thu, 16 May 2019 14:52:45 -0700 Subject: [PATCH 52/57] added comment to credit rocket chip for some implementation details --- src/main/scala/components/csr.scala | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 0dd388ed..798f0f0f 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -1,3 +1,7 @@ +/* The following code is based on https://github.com/freechipsproject/rocket-chip + * implementation of the csr unit + */ + /* Describes register file that maintains machine state */ package dinocpu From 08f734d47d632c982b16d594ba3aba61b5f5f855 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 21 May 2019 18:23:40 -0700 Subject: [PATCH 53/57] added support to write to mtvec register for better traps --- src/main/scala/components/csr.scala | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 798f0f0f..c9134b51 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -391,7 +391,7 @@ class CSRRegFile extends Module{ //ECALL when(insn_call){ - io.evec := "h80000004".U + io.evec := reg_mtvec.asUInt() reg_mcause.interrupt := MCauses.machine_ecall & "h80000000".U reg_mcause.exceptioncode := MCauses.machine_ecall & "h7fffffff".U } @@ -445,7 +445,11 @@ class CSRRegFile extends Module{ } //MTVEC IS FIXED IN THIS IMPLEMENTATION - + when (decoded_addr(MCSRs.mtvec)) { + val new_mtvec = wdata.asTypeOf(new MTVec()) + reg_mtvec.base := new_mtvec.base + reg_mtvec.mode := 0.U //direct trap mode only + } //MDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION //MIDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION From e1e98718d5acacc8d2d7da388de80d5ded747b65 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 21 May 2019 18:28:17 -0700 Subject: [PATCH 54/57] added support to write to mtvec register for better traps --- src/main/scala/components/csr.scala | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 798f0f0f..a2ca1c59 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -391,7 +391,7 @@ class CSRRegFile extends Module{ //ECALL when(insn_call){ - io.evec := "h80000004".U + io.evec := reg_mtvec.asUInt() reg_mcause.interrupt := MCauses.machine_ecall & "h80000000".U reg_mcause.exceptioncode := MCauses.machine_ecall & "h7fffffff".U } @@ -444,8 +444,15 @@ class CSRRegFile extends Module{ reg_mstatus.sd := 0.U } - //MTVEC IS FIXED IN THIS IMPLEMENTATION - + //MTVEC + /* write address to trap too + */ + when (decoded_addr(MCSRs.mtvec)) { + val new_mtvec = wdata.asTypeOf(new MTVec()) + reg_mtvec.base := new_mtvec.base + reg_mtvec.mode := 0.U//support direct addressing onl + } + //MDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION //MIDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION From 877f676bc8c3f3d6facd3ec98b55ac07c909bfa9 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Mon, 17 Jun 2019 19:39:41 -0700 Subject: [PATCH 55/57] Added fence instruction, and added support to write mtvec csr register --- src/main/scala/components/control.scala | 4 +++- src/main/scala/components/csr.scala | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/main/scala/components/control.scala b/src/main/scala/components/control.scala index d41bffab..88d3a599 100644 --- a/src/main/scala/components/control.scala +++ b/src/main/scala/components/control.scala @@ -61,7 +61,9 @@ class Control extends Module { // jalr BitPat("b1100111") -> List(true.B, false.B, false.B, 2.U, false.B, false.B, true.B, true.B, 0.U, 3.U), //csr - BitPat("b1110011") -> List(true.B, false.B, false.B, 3.U, false.B, false.B, false.B, false.B, 0.U, 0.U) + BitPat("b1110011") -> List(true.B, false.B, false.B, 3.U, false.B, false.B, false.B, false.B, 0.U, 0.U), + //fence + BitPat("b0001111") -> List(true.B, false.B, false.B, 4.U, false.B, false.B, false.B, false.B, 0.U, 0.U) ) // Array ) // ListLookup diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index c9134b51..4159a8f6 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -389,6 +389,7 @@ class CSRRegFile extends Module{ io.evec := reg_mepc } + //ECALL when(insn_call){ io.evec := reg_mtvec.asUInt() From bdcf521f68dee54fba0de8a62e09d6107c0dc744 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Tue, 21 May 2019 18:28:17 -0700 Subject: [PATCH 56/57] added support to write to mtvec register for better traps --- src/main/scala/components/csr.scala | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index 4159a8f6..6b9ae055 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -445,12 +445,24 @@ class CSRRegFile extends Module{ reg_mstatus.sd := 0.U } +<<<<<<< HEAD //MTVEC IS FIXED IN THIS IMPLEMENTATION when (decoded_addr(MCSRs.mtvec)) { val new_mtvec = wdata.asTypeOf(new MTVec()) reg_mtvec.base := new_mtvec.base reg_mtvec.mode := 0.U //direct trap mode only } +======= + //MTVEC + /* write address to trap too + */ + when (decoded_addr(MCSRs.mtvec)) { + val new_mtvec = wdata.asTypeOf(new MTVec()) + reg_mtvec.base := new_mtvec.base + reg_mtvec.mode := 0.U//support direct addressing onl + } + +>>>>>>> added support to write to mtvec register for better traps //MDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION //MIDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION From 3b9c7b4fb3789dd2ffa1e581812060e62ee2ce27 Mon Sep 17 00:00:00 2001 From: Nima Ganjehloo Date: Mon, 17 Jun 2019 20:05:35 -0700 Subject: [PATCH 57/57] Forgot to remove merge symbols --- src/main/scala/components/control.scala | 4 ---- src/main/scala/components/csr.scala | 19 ++----------------- 2 files changed, 2 insertions(+), 21 deletions(-) diff --git a/src/main/scala/components/control.scala b/src/main/scala/components/control.scala index a1639912..88d3a599 100644 --- a/src/main/scala/components/control.scala +++ b/src/main/scala/components/control.scala @@ -61,13 +61,9 @@ class Control extends Module { // jalr BitPat("b1100111") -> List(true.B, false.B, false.B, 2.U, false.B, false.B, true.B, true.B, 0.U, 3.U), //csr -<<<<<<< HEAD BitPat("b1110011") -> List(true.B, false.B, false.B, 3.U, false.B, false.B, false.B, false.B, 0.U, 0.U), //fence BitPat("b0001111") -> List(true.B, false.B, false.B, 4.U, false.B, false.B, false.B, false.B, 0.U, 0.U) -======= - BitPat("b1110011") -> List(true.B, false.B, false.B, 3.U, false.B, false.B, false.B, false.B, 0.U, 0.U) ->>>>>>> e1e98718d5acacc8d2d7da388de80d5ded747b65 ) // Array ) // ListLookup diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala index a897b9a2..eaa18c73 100644 --- a/src/main/scala/components/csr.scala +++ b/src/main/scala/components/csr.scala @@ -444,30 +444,15 @@ class CSRRegFile extends Module{ reg_mstatus.sd := 0.U } -<<<<<<< HEAD -<<<<<<< HEAD - //MTVEC IS FIXED IN THIS IMPLEMENTATION - when (decoded_addr(MCSRs.mtvec)) { - val new_mtvec = wdata.asTypeOf(new MTVec()) - reg_mtvec.base := new_mtvec.base - reg_mtvec.mode := 0.U //direct trap mode only - } -======= -======= ->>>>>>> e1e98718d5acacc8d2d7da388de80d5ded747b65 //MTVEC /* write address to trap too */ when (decoded_addr(MCSRs.mtvec)) { val new_mtvec = wdata.asTypeOf(new MTVec()) reg_mtvec.base := new_mtvec.base - reg_mtvec.mode := 0.U//support direct addressing onl + reg_mtvec.mode := 0.U //support direct addressing onl } - -<<<<<<< HEAD ->>>>>>> added support to write to mtvec register for better traps -======= ->>>>>>> e1e98718d5acacc8d2d7da388de80d5ded747b65 + //MDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION //MIDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION