diff --git a/src/main/scala/components/control.scala b/src/main/scala/components/control.scala
index d41bffab..88d3a599 100644
--- a/src/main/scala/components/control.scala
+++ b/src/main/scala/components/control.scala
@@ -61,7 +61,9 @@ class Control extends Module {
       // jalr
       BitPat("b1100111") -> List(true.B, false.B, false.B, 2.U,   false.B, false.B,  true.B,  true.B,     0.U,    3.U),
       //csr
-      BitPat("b1110011") -> List(true.B, false.B, false.B, 3.U,      false.B, false.B,  false.B, false.B,    0.U,    0.U)
+      BitPat("b1110011") -> List(true.B, false.B, false.B, 3.U,   false.B, false.B,  false.B, false.B,    0.U,    0.U),
+      //fence
+      BitPat("b0001111") -> List(true.B, false.B, false.B, 4.U,   false.B, false.B,  false.B, false.B,    0.U,    0.U)
       ) // Array
     ) // ListLookup
 
diff --git a/src/main/scala/components/csr.scala b/src/main/scala/components/csr.scala
index 798f0f0f..eaa18c73 100644
--- a/src/main/scala/components/csr.scala
+++ b/src/main/scala/components/csr.scala
@@ -391,7 +391,7 @@ class CSRRegFile extends Module{
 
   //ECALL
   when(insn_call){
-    io.evec := "h80000004".U
+    io.evec := reg_mtvec.asUInt()
     reg_mcause.interrupt := MCauses.machine_ecall & "h80000000".U
     reg_mcause.exceptioncode := MCauses.machine_ecall & "h7fffffff".U
   }
@@ -444,8 +444,15 @@ class CSRRegFile extends Module{
       reg_mstatus.sd := 0.U
     }
     
-    //MTVEC IS FIXED IN THIS IMPLEMENTATION
-
+    //MTVEC
+    /* write address to trap too
+     */
+    when (decoded_addr(MCSRs.mtvec)) {
+      val new_mtvec = wdata.asTypeOf(new MTVec())
+      reg_mtvec.base := new_mtvec.base
+      reg_mtvec.mode := 0.U //support direct addressing onl
+    }
+    
     //MDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION
     
     //MIDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION