Take for example a field:
module O = struct
type 'a t =
{
num_zeros : 'a With_valid.t [@bits num_bits]
}
[@@deriving hardcaml]
end
On RTL generation, we get:
"[Rtl_name.add_port_name] illegal port name" (name num_zeros$valid)
This seems wrong, as the With_valid.t interface can't be used when generating VHDL.
Take for example a field:
On RTL generation, we get:
"[Rtl_name.add_port_name] illegal port name" (name num_zeros$valid)This seems wrong, as the
With_valid.tinterface can't be used when generating VHDL.