TLB Misses

[andreas-abel]

To obtain measurements that are consistent with an "idealized execution", you map all memory addresses to the same cache set. While this eliminates cache misses, it does not prevent TLB misses.

An example is the 4881c4380800005b5d415c415d415e415f benchmark ("add rsp,0x838; pop rbx; pop rbp; pop r12; pop r13; pop r14; pop r15"). The difference between your measurements/Ithemal (~6 cycles) and IACA (3 cycles) is due to TLB misses.

[ychen306]

Thanks for filing this issue. You are correct. How did you detect the TLB misses? I tried using (PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) but got a counter of 0.

[andreas-abel]

I think the counter you mention measures only L2 TLB misses. I used the DTLB_LOAD_MISSES.STLB_HIT counter which counts loads that miss in the L1 TLB but hit in the L2 TLB.