Incorrect ground truths (2)

[andreas-abel]

The original issue (ithemal/Ithemal#54) was closed yesterday, however, the problem does not appear to be solved.

I've had a look at the 'ground truths' for Skylake (throughput/skl.csv).

Skylake can execute at most two instructions with memory operands per cycle (including LEA). Thus, any measurements that report a throughput smaller than 50 cycles for such instructions are obviously not accurate, and do not correspond to the real ground truth. Your file contains more than 20,000 such cases. More than 2,200 of them even report a throughput of less than 45 cycles (i.e., more than 10% off).

Moreover, Skylake can retire at most 4 instructions per cycle. Thus, any throughputs smaller than 25 cycles are incorrect. The file contains more than 2,000 such cases.

[ychen306]

Thanks for pointing out the error. We are investigating this issue. Basically there is some noise in our raw measurements, and we are trying to adjust for that in post-processing. We have updated the numbers in this branch. Please check it out.

Regarding the throughput lower-bounded by 25 cycles, does that hold for register-to-register moves?

[cod3monk]

register-to-register moves would bring the lower bound to 6 µOPs per cycle, at best, since they need to go through the front end before mov elimination and register renaming can happen. See https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Decoding and https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#.C2.B5OP_cache_.26_x86_tax

[andreas-abel]

On Ivy Bridge, Haswell, and Skylake, register-to-register moves are limited to 4 per cycle, see https://www.uops.info/table.html and https://www.agner.org/optimize/instruction_tables.pdf