errors - GLSL compilation and link errors will be reported to stderr.
Example: export MESA_GLSL=dump,nopt
diff --git a/include/GL/internal/dri_interface.h b/include/GL/internal/dri_interface.h
index f2e46f65f92..6d134e3a40f 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -1352,6 +1352,10 @@ struct __DRIdri2ExtensionRec {
#define __DRI_IMAGE_FOURCC_YVU422 0x36315659
#define __DRI_IMAGE_FOURCC_YVU444 0x34325659
+#define __DRI_IMAGE_FOURCC_P010 0x30313050
+#define __DRI_IMAGE_FOURCC_P012 0x32313050
+#define __DRI_IMAGE_FOURCC_P016 0x36313050
+
/**
* Queryable on images created by createImageFromNames.
*
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 7201562d824..b91abd7a3f9 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -171,6 +171,7 @@ CHIPSET(0x3185, glk_2x6, "Intel(R) UHD Graphics 600 (Geminilake 2x6)")
CHIPSET(0x3E90, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
CHIPSET(0x3E93, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
CHIPSET(0x3E99, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E9C, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
CHIPSET(0x3E91, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
CHIPSET(0x3E92, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
CHIPSET(0x3E96, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
@@ -203,6 +204,10 @@ CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
CHIPSET(0x8A50, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
CHIPSET(0x8A51, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
CHIPSET(0x8A52, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
+CHIPSET(0x8A56, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
+CHIPSET(0x8A57, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
+CHIPSET(0x8A58, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
+CHIPSET(0x8A59, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
CHIPSET(0x8A5A, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
CHIPSET(0x8A5B, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
CHIPSET(0x8A5C, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
diff --git a/meson.build b/meson.build
index d975b0dbf4b..5286b91c615 100644
--- a/meson.build
+++ b/meson.build
@@ -61,11 +61,11 @@ endif
dri_drivers_path = get_option('dri-drivers-path')
if dri_drivers_path == ''
- dri_drivers_path = join_paths(get_option('libdir'), 'dri')
+ dri_drivers_path = join_paths(get_option('prefix'), get_option('libdir'), 'dri')
endif
dri_search_path = get_option('dri-search-path')
if dri_search_path == ''
- dri_search_path = join_paths(get_option('prefix'), dri_drivers_path)
+ dri_search_path = dri_drivers_path
endif
with_gles1 = get_option('gles1')
@@ -608,7 +608,7 @@ with_gallium_xa = _xa != 'false'
d3d_drivers_path = get_option('d3d-drivers-path')
if d3d_drivers_path == ''
- d3d_drivers_path = join_paths(get_option('libdir'), 'd3d')
+ d3d_drivers_path = join_paths(get_option('prefix'), get_option('libdir'), 'd3d')
endif
with_gallium_st_nine = get_option('gallium-nine')
@@ -1213,6 +1213,7 @@ if _llvm != 'false'
with_gallium_opencl or _llvm == 'true'
),
static : not _shared_llvm,
+ method : 'config-tool',
)
with_llvm = dep_llvm.found()
endif
@@ -1387,12 +1388,14 @@ if with_platform_x11
dep_xshmfence = dependency('xshmfence', version : '>= 1.1')
endif
endif
- if with_glx == 'dri'
+ if with_glx == 'dri' or with_glx == 'gallium-xlib'
+ dep_glproto = dependency('glproto', version : '>= 1.4.14')
+ endif
+ if with_glx == 'dri'
if with_dri_platform == 'drm'
dep_dri2proto = dependency('dri2proto', version : '>= 2.8')
dep_xxf86vm = dependency('xxf86vm')
endif
- dep_glproto = dependency('glproto', version : '>= 1.4.14')
endif
if (with_egl or (
with_gallium_vdpau or with_gallium_xvmc or with_gallium_xa or
@@ -1400,7 +1403,7 @@ if with_platform_x11
dep_xcb_xfixes = dependency('xcb-xfixes')
endif
if with_xlib_lease
- dep_xcb_xrandr = dependency('xcb-randr', version : '>= 1.12')
+ dep_xcb_xrandr = dependency('xcb-randr')
dep_xlib_xrandr = dependency('xrandr', version : '>= 1.3')
endif
endif
diff --git a/scons/custom.py b/scons/custom.py
index 09946fa7324..8028990ef61 100644
--- a/scons/custom.py
+++ b/scons/custom.py
@@ -48,7 +48,12 @@
# a path directly. We want to support both, so we need to detect the SCons version,
# for which no API is provided by SCons 8-P
-scons_version = tuple(map(int, SCons.__version__.split('.')))
+# Scons version string has consistently been in this format:
+# MajorVersion.MinorVersion.Patch[.alpha/beta.yyyymmdd]
+# so this formula should cover all versions regardless of type
+# stable, alpha or beta.
+# For simplicity alpha and beta flags are removed.
+scons_version = tuple(map(int, SCons.__version__.split('.')[:3]))
def quietCommandLines(env):
# Quiet command lines
diff --git a/scons/gallium.py b/scons/gallium.py
index 963834a5fbc..61bbeb2399f 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -308,7 +308,20 @@ def generate(env):
if env.GetOption('num_jobs') <= 1:
env.SetOption('num_jobs', num_jobs())
- env.Decider('MD5-timestamp')
+ # Speed up dependency checking. See
+ # - https://github.com/SCons/scons/wiki/GoFastButton
+ # - https://bugs.freedesktop.org/show_bug.cgi?id=109443
+
+ # Scons version string has consistently been in this format:
+ # MajorVersion.MinorVersion.Patch[.alpha/beta.yyyymmdd]
+ # so this formula should cover all versions regardless of type
+ # stable, alpha or beta.
+ # For simplicity alpha and beta flags are removed.
+
+ scons_version = distutils.version.StrictVersion('.'.join(SCons.__version__.split('.')[:3]))
+ if scons_version < distutils.version.StrictVersion('3.0.2') or \
+ scons_version > distutils.version.StrictVersion('3.0.4'):
+ env.Decider('MD5-timestamp')
env.SetOption('max_drift', 60)
# C preprocessor options
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index fc8c6a09d2f..7ba13c24953 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -367,9 +367,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
info->has_ctx_priority = info->drm_minor >= 22;
- /* TODO: Enable this once the kernel handles it efficiently. */
- info->has_local_buffers = info->drm_minor >= 20 &&
- !info->has_dedicated_vram;
+ info->has_local_buffers = info->drm_minor >= 20;
info->kernel_flushes_hdp_before_ib = true;
info->htile_cmask_support_1d_tiling = true;
info->si_TA_CS_BC_BASE_ADDR_allowed = true;
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 768364b2dc6..3d7eb7b0421 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -905,6 +905,37 @@ ac_build_fs_interp(struct ac_llvm_context *ctx,
ctx->f32, args, 5, AC_FUNC_ATTR_READNONE);
}
+LLVMValueRef
+ac_build_fs_interp_f16(struct ac_llvm_context *ctx,
+ LLVMValueRef llvm_chan,
+ LLVMValueRef attr_number,
+ LLVMValueRef params,
+ LLVMValueRef i,
+ LLVMValueRef j)
+{
+ LLVMValueRef args[6];
+ LLVMValueRef p1;
+
+ args[0] = i;
+ args[1] = llvm_chan;
+ args[2] = attr_number;
+ args[3] = ctx->i1false;
+ args[4] = params;
+
+ p1 = ac_build_intrinsic(ctx, "llvm.amdgcn.interp.p1.f16",
+ ctx->f32, args, 5, AC_FUNC_ATTR_READNONE);
+
+ args[0] = p1;
+ args[1] = j;
+ args[2] = llvm_chan;
+ args[3] = attr_number;
+ args[4] = ctx->i1false;
+ args[5] = params;
+
+ return ac_build_intrinsic(ctx, "llvm.amdgcn.interp.p2.f16",
+ ctx->f16, args, 6, AC_FUNC_ATTR_READNONE);
+}
+
LLVMValueRef
ac_build_fs_interp_mov(struct ac_llvm_context *ctx,
LLVMValueRef parameter,
@@ -923,6 +954,14 @@ ac_build_fs_interp_mov(struct ac_llvm_context *ctx,
ctx->f32, args, 4, AC_FUNC_ATTR_READNONE);
}
+LLVMValueRef
+ac_build_gep_ptr(struct ac_llvm_context *ctx,
+ LLVMValueRef base_ptr,
+ LLVMValueRef index)
+{
+ return LLVMBuildGEP(ctx->builder, base_ptr, &index, 1, "");
+}
+
LLVMValueRef
ac_build_gep0(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr,
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index e47893bbbe6..370e7e9741c 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -216,6 +216,14 @@ ac_build_fs_interp(struct ac_llvm_context *ctx,
LLVMValueRef i,
LLVMValueRef j);
+LLVMValueRef
+ac_build_fs_interp_f16(struct ac_llvm_context *ctx,
+ LLVMValueRef llvm_chan,
+ LLVMValueRef attr_number,
+ LLVMValueRef params,
+ LLVMValueRef i,
+ LLVMValueRef j);
+
LLVMValueRef
ac_build_fs_interp_mov(struct ac_llvm_context *ctx,
LLVMValueRef parameter,
@@ -223,6 +231,11 @@ ac_build_fs_interp_mov(struct ac_llvm_context *ctx,
LLVMValueRef attr_number,
LLVMValueRef params);
+LLVMValueRef
+ac_build_gep_ptr(struct ac_llvm_context *ctx,
+ LLVMValueRef base_ptr,
+ LLVMValueRef index);
+
LLVMValueRef
ac_build_gep0(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr,
diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
index 69446863b95..6063411310b 100644
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -151,13 +151,14 @@ static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
LLVMTargetRef target = ac_get_llvm_target(triple);
snprintf(features, sizeof(features),
- "+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
+ "+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s%s",
HAVE_LLVM >= 0x0800 ? "" : ",+vgpr-spilling",
tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
- tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "");
-
+ tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "",
+ tm_options & AC_TM_NO_LOAD_STORE_OPT ? ",-load-store-opt" : "");
+
LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
target,
triple,
diff --git a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h
index 6d961c06f8a..ca00540da80 100644
--- a/src/amd/common/ac_llvm_util.h
+++ b/src/amd/common/ac_llvm_util.h
@@ -65,6 +65,7 @@ enum ac_target_machine_options {
AC_TM_CHECK_IR = (1 << 5),
AC_TM_ENABLE_GLOBAL_ISEL = (1 << 6),
AC_TM_CREATE_LOW_OPT = (1 << 7),
+ AC_TM_NO_LOAD_STORE_OPT = (1 << 8),
};
enum ac_float_mode {
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index efd3e260af1..a0815995b12 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1019,10 +1019,17 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
LLVMValueRef in[3];
for (unsigned chan = 0; chan < 3; chan++)
in[chan] = ac_llvm_extract_elem(&ctx->ac, src[0], chan);
- results[0] = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubetc",
+ results[0] = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubesc",
ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
- results[1] = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubesc",
+ results[1] = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubetc",
ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
+ LLVMValueRef ma = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubema",
+ ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
+ results[0] = ac_build_fdiv(&ctx->ac, results[0], ma);
+ results[1] = ac_build_fdiv(&ctx->ac, results[1], ma);
+ LLVMValueRef offset = LLVMConstReal(ctx->ac.f32, 0.5);
+ results[0] = LLVMBuildFAdd(ctx->ac.builder, results[0], offset, "");
+ results[1] = LLVMBuildFAdd(ctx->ac.builder, results[1], offset, "");
result = ac_build_gather_values(&ctx->ac, results, 2);
break;
}
@@ -1896,14 +1903,18 @@ static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
if (var) {
bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
var->data.mode == nir_var_shader_in;
- if (var->data.compact)
- stride = 1;
idx = var->data.driver_location;
comp = var->data.location_frac;
mode = var->data.mode;
get_deref_offset(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), vs_in, NULL, NULL,
&const_index, &indir_index);
+
+ if (var->data.compact) {
+ stride = 1;
+ const_index += comp;
+ comp = 0;
+ }
}
if (instr->dest.ssa.bit_size == 64)
@@ -2006,18 +2017,28 @@ static void
visit_store_var(struct ac_nir_context *ctx,
nir_intrinsic_instr *instr)
{
- nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
+ nir_deref_instr *deref = nir_instr_as_deref(instr->src[0].ssa->parent_instr);
+ nir_variable *var = nir_deref_instr_get_variable(deref);
LLVMValueRef temp_ptr, value;
- int idx = var->data.driver_location;
- unsigned comp = var->data.location_frac;
+ int idx = 0;
+ unsigned comp = 0;
LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[1]));
int writemask = instr->const_index[0];
LLVMValueRef indir_index;
unsigned const_index;
- get_deref_offset(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), false,
- NULL, NULL, &const_index, &indir_index);
+ if (var) {
+ get_deref_offset(ctx, deref, false,
+ NULL, NULL, &const_index, &indir_index);
+ idx = var->data.driver_location;
+ comp = var->data.location_frac;
+
+ if (var->data.compact) {
+ const_index += comp;
+ comp = 0;
+ }
+ }
if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
@@ -2030,7 +2051,7 @@ visit_store_var(struct ac_nir_context *ctx,
writemask = writemask << comp;
- switch (var->data.mode) {
+ switch (deref->mode) {
case nir_var_shader_out:
if (ctx->stage == MESA_SHADER_TESS_CTRL) {
@@ -2039,8 +2060,8 @@ visit_store_var(struct ac_nir_context *ctx,
unsigned const_index = 0;
const bool is_patch = var->data.patch;
- get_deref_offset(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr),
- false, NULL, is_patch ? NULL : &vertex_index,
+ get_deref_offset(ctx, deref, false, NULL,
+ is_patch ? NULL : &vertex_index,
&const_index, &indir_index);
ctx->abi->store_tcs_outputs(ctx->abi, var,
@@ -2107,7 +2128,7 @@ visit_store_var(struct ac_nir_context *ctx,
int writemask = instr->const_index[0];
LLVMValueRef address = get_src(ctx, instr->src[0]);
LLVMValueRef val = get_src(ctx, instr->src[1]);
- if (util_is_power_of_two_nonzero(writemask)) {
+ if (writemask == (1u << ac_get_llvm_num_components(val)) - 1) {
val = LLVMBuildBitCast(
ctx->ac.builder, val,
LLVMGetElementType(LLVMTypeOf(address)), "");
@@ -2338,10 +2359,12 @@ static void get_image_coords(struct ac_nir_context *ctx,
}
static LLVMValueRef get_image_buffer_descriptor(struct ac_nir_context *ctx,
- const nir_intrinsic_instr *instr, bool write)
+ const nir_intrinsic_instr *instr,
+ bool write, bool atomic)
{
LLVMValueRef rsrc = get_image_descriptor(ctx, instr, AC_DESC_BUFFER, write);
- if (ctx->abi->gfx9_stride_size_workaround) {
+ if (ctx->abi->gfx9_stride_size_workaround ||
+ (ctx->abi->gfx9_stride_size_workaround_for_atomic && atomic)) {
LLVMValueRef elem_count = LLVMBuildExtractElement(ctx->ac.builder, rsrc, LLVMConstInt(ctx->ac.i32, 2, 0), "");
LLVMValueRef stride = LLVMBuildExtractElement(ctx->ac.builder, rsrc, LLVMConstInt(ctx->ac.i32, 1, 0), "");
stride = LLVMBuildLShr(ctx->ac.builder, stride, LLVMConstInt(ctx->ac.i32, 16, 0), "");
@@ -2374,7 +2397,7 @@ static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
unsigned num_channels = util_last_bit(mask);
LLVMValueRef rsrc, vindex;
- rsrc = get_image_buffer_descriptor(ctx, instr, false);
+ rsrc = get_image_buffer_descriptor(ctx, instr, false, false);
vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[1]),
ctx->ac.i32_0, "");
@@ -2418,7 +2441,7 @@ static void visit_image_store(struct ac_nir_context *ctx,
if (dim == GLSL_SAMPLER_DIM_BUF) {
char name[48];
const char *types[] = { "f32", "v2f32", "v4f32" };
- LLVMValueRef rsrc = get_image_buffer_descriptor(ctx, instr, true);
+ LLVMValueRef rsrc = get_image_buffer_descriptor(ctx, instr, true, false);
LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[3]));
unsigned src_channels = ac_get_llvm_num_components(src);
@@ -2514,11 +2537,14 @@ static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
params[param_count++] = get_src(ctx, instr->src[3]);
if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
- params[param_count++] = get_image_buffer_descriptor(ctx, instr, true);
+ params[param_count++] = get_image_buffer_descriptor(ctx, instr, true, true);
params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[1]),
ctx->ac.i32_0, ""); /* vindex */
params[param_count++] = ctx->ac.i32_0; /* voffset */
- if (HAVE_LLVM >= 0x800) {
+ if (HAVE_LLVM >= 0x900) {
+ /* XXX: The new raw/struct atomic intrinsics are buggy
+ * with LLVM 8, see r358579.
+ */
params[param_count++] = ctx->ac.i32_0; /* soffset */
params[param_count++] = ctx->ac.i32_0; /* slc */
@@ -3079,7 +3105,8 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
ctx->abi->frag_pos[2],
ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
};
- result = ac_build_gather_values(&ctx->ac, values, 4);
+ result = ac_to_integer(&ctx->ac,
+ ac_build_gather_values(&ctx->ac, values, 4));
break;
}
case nir_intrinsic_load_front_face:
@@ -3818,6 +3845,73 @@ static void visit_jump(struct ac_llvm_context *ctx,
}
}
+static LLVMTypeRef
+glsl_base_to_llvm_type(struct ac_llvm_context *ac,
+ enum glsl_base_type type)
+{
+ switch (type) {
+ case GLSL_TYPE_INT:
+ case GLSL_TYPE_UINT:
+ case GLSL_TYPE_BOOL:
+ case GLSL_TYPE_SUBROUTINE:
+ return ac->i32;
+ case GLSL_TYPE_INT16:
+ case GLSL_TYPE_UINT16:
+ return ac->i16;
+ case GLSL_TYPE_FLOAT:
+ return ac->f32;
+ case GLSL_TYPE_FLOAT16:
+ return ac->f16;
+ case GLSL_TYPE_INT64:
+ case GLSL_TYPE_UINT64:
+ return ac->i64;
+ case GLSL_TYPE_DOUBLE:
+ return ac->f64;
+ default:
+ unreachable("unknown GLSL type");
+ }
+}
+
+static LLVMTypeRef
+glsl_to_llvm_type(struct ac_llvm_context *ac,
+ const struct glsl_type *type)
+{
+ if (glsl_type_is_scalar(type)) {
+ return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
+ }
+
+ if (glsl_type_is_vector(type)) {
+ return LLVMVectorType(
+ glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
+ glsl_get_vector_elements(type));
+ }
+
+ if (glsl_type_is_matrix(type)) {
+ return LLVMArrayType(
+ glsl_to_llvm_type(ac, glsl_get_column_type(type)),
+ glsl_get_matrix_columns(type));
+ }
+
+ if (glsl_type_is_array(type)) {
+ return LLVMArrayType(
+ glsl_to_llvm_type(ac, glsl_get_array_element(type)),
+ glsl_get_length(type));
+ }
+
+ assert(glsl_type_is_struct(type));
+
+ LLVMTypeRef member_types[glsl_get_length(type)];
+
+ for (unsigned i = 0; i < glsl_get_length(type); i++) {
+ member_types[i] =
+ glsl_to_llvm_type(ac,
+ glsl_get_struct_field(type, i));
+ }
+
+ return LLVMStructTypeInContext(ac->context, member_types,
+ glsl_get_length(type), false);
+}
+
static void visit_deref(struct ac_nir_context *ctx,
nir_deref_instr *instr)
{
@@ -3839,9 +3933,27 @@ static void visit_deref(struct ac_nir_context *ctx,
result = ac_build_gep0(&ctx->ac, get_src(ctx, instr->parent),
get_src(ctx, instr->arr.index));
break;
- case nir_deref_type_cast:
+ case nir_deref_type_ptr_as_array:
+ result = ac_build_gep_ptr(&ctx->ac, get_src(ctx, instr->parent),
+ get_src(ctx, instr->arr.index));
+ break;
+ case nir_deref_type_cast: {
result = get_src(ctx, instr->parent);
+
+ LLVMTypeRef pointee_type = glsl_to_llvm_type(&ctx->ac, instr->type);
+ LLVMTypeRef type = LLVMPointerType(pointee_type, AC_ADDR_SPACE_LDS);
+
+ if (LLVMTypeOf(result) != type) {
+ if (LLVMGetTypeKind(LLVMTypeOf(result)) == LLVMVectorTypeKind) {
+ result = LLVMBuildBitCast(ctx->ac.builder, result,
+ type, "");
+ } else {
+ result = LLVMBuildIntToPtr(ctx->ac.builder, result,
+ type, "");
+ }
+ }
break;
+ }
default:
unreachable("Unhandled deref_instr deref type");
}
@@ -3990,73 +4102,6 @@ ac_handle_shader_output_decl(struct ac_llvm_context *ctx,
}
}
-static LLVMTypeRef
-glsl_base_to_llvm_type(struct ac_llvm_context *ac,
- enum glsl_base_type type)
-{
- switch (type) {
- case GLSL_TYPE_INT:
- case GLSL_TYPE_UINT:
- case GLSL_TYPE_BOOL:
- case GLSL_TYPE_SUBROUTINE:
- return ac->i32;
- case GLSL_TYPE_INT16:
- case GLSL_TYPE_UINT16:
- return ac->i16;
- case GLSL_TYPE_FLOAT:
- return ac->f32;
- case GLSL_TYPE_FLOAT16:
- return ac->f16;
- case GLSL_TYPE_INT64:
- case GLSL_TYPE_UINT64:
- return ac->i64;
- case GLSL_TYPE_DOUBLE:
- return ac->f64;
- default:
- unreachable("unknown GLSL type");
- }
-}
-
-static LLVMTypeRef
-glsl_to_llvm_type(struct ac_llvm_context *ac,
- const struct glsl_type *type)
-{
- if (glsl_type_is_scalar(type)) {
- return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
- }
-
- if (glsl_type_is_vector(type)) {
- return LLVMVectorType(
- glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
- glsl_get_vector_elements(type));
- }
-
- if (glsl_type_is_matrix(type)) {
- return LLVMArrayType(
- glsl_to_llvm_type(ac, glsl_get_column_type(type)),
- glsl_get_matrix_columns(type));
- }
-
- if (glsl_type_is_array(type)) {
- return LLVMArrayType(
- glsl_to_llvm_type(ac, glsl_get_array_element(type)),
- glsl_get_length(type));
- }
-
- assert(glsl_type_is_struct(type));
-
- LLVMTypeRef member_types[glsl_get_length(type)];
-
- for (unsigned i = 0; i < glsl_get_length(type); i++) {
- member_types[i] =
- glsl_to_llvm_type(ac,
- glsl_get_struct_field(type, i));
- }
-
- return LLVMStructTypeInContext(ac->context, member_types,
- glsl_get_length(type), false);
-}
-
static void
setup_locals(struct ac_nir_context *ctx,
struct nir_function *func)
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index ee18e6c1923..9eb4d37257e 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -195,6 +195,7 @@ struct ac_shader_abi {
/* Whether to workaround GFX9 ignoring the stride for the buffer size if IDXEN=0
* and LLVM optimizes an indexed load with constant index to IDXEN=0. */
bool gfx9_stride_size_workaround;
+ bool gfx9_stride_size_workaround_for_atomic;
};
#endif /* AC_SHADER_ABI_H */
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 7f7f052986e..1271c3e73f2 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -301,7 +301,6 @@ radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
static VkResult
radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
{
-
cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
@@ -326,6 +325,8 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->record_result = VK_SUCCESS;
+ memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
+
for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
cmd_buffer->descriptors[i].dirty = 0;
cmd_buffer->descriptors[i].valid = 0;
@@ -338,14 +339,15 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
unsigned fence_offset, eop_bug_offset;
void *fence_ptr;
- radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0, &fence_offset,
+ radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
&fence_ptr);
+
cmd_buffer->gfx9_fence_va =
radv_buffer_get_va(cmd_buffer->upload.upload_bo);
cmd_buffer->gfx9_fence_va += fence_offset;
/* Allocate a buffer for the EOP bug on GFX9. */
- radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
+ radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
&eop_bug_offset, &fence_ptr);
cmd_buffer->gfx9_eop_bug_va =
radv_buffer_get_va(cmd_buffer->upload.upload_bo);
@@ -416,6 +418,8 @@ radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
unsigned *out_offset,
void **ptr)
{
+ assert(util_is_power_of_two_nonzero(alignment));
+
uint64_t offset = align(cmd_buffer->upload.offset, alignment);
if (offset + size > cmd_buffer->upload.size) {
if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
@@ -1255,7 +1259,7 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
++reg_count;
- radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
+ radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_PFP));
@@ -1279,7 +1283,7 @@ radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->tc_compat_zrange_offset;
- radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
+ radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_PFP));
@@ -1356,7 +1360,7 @@ radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
+ if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
@@ -1473,7 +1477,7 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
- radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
+ radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, cmd_buffer->state.predicating));
radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_PFP));
@@ -1518,14 +1522,13 @@ radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
+ if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
radeon_emit(cs, 2);
} else {
- /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
COPY_DATA_DST_SEL(COPY_DATA_REG) |
@@ -2155,6 +2158,7 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
ia_multi_vgt_param =
si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
draw_info->indirect,
+ !!draw_info->strmout_buffer,
draw_info->indirect ? 0 : draw_info->count);
if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
@@ -4404,10 +4408,15 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe
if (!radv_image_has_htile(image))
return;
- if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
- radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
- /* TODO: merge with the clear if applicable */
- radv_initialize_htile(cmd_buffer, image, range, 0);
+ if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
+ uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
+
+ if (radv_layout_is_htile_compressed(image, dst_layout,
+ dst_queue_mask)) {
+ clear_value = 0;
+ }
+
+ radv_initialize_htile(cmd_buffer, image, range, clear_value);
} else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
@@ -4837,8 +4846,11 @@ void radv_CmdBeginConditionalRenderingEXT(
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
bool draw_visible = true;
- uint64_t va;
+ uint64_t pred_value = 0;
+ uint64_t va, new_va;
+ unsigned pred_offset;
va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
@@ -4854,13 +4866,51 @@ void radv_CmdBeginConditionalRenderingEXT(
si_emit_cache_flush(cmd_buffer);
+ /* From the Vulkan spec 1.1.107:
+ *
+ * "If the 32-bit value at offset in buffer memory is zero, then the
+ * rendering commands are discarded, otherwise they are executed as
+ * normal. If the value of the predicate in buffer memory changes while
+ * conditional rendering is active, the rendering commands may be
+ * discarded in an implementation-dependent way. Some implementations
+ * may latch the value of the predicate upon beginning conditional
+ * rendering while others may read it before every rendering command."
+ *
+ * But, the AMD hardware treats the predicate as a 64-bit value which
+ * means we need a workaround in the driver. Luckily, it's not required
+ * to support if the value changes when predication is active.
+ *
+ * The workaround is as follows:
+ * 1) allocate a 64-value in the upload BO and initialize it to 0
+ * 2) copy the 32-bit predicate value to the upload BO
+ * 3) use the new allocated VA address for predication
+ *
+ * Based on the conditionalrender demo, it's faster to do the COPY_DATA
+ * in ME (+ sync PFP) instead of PFP.
+ */
+ radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
+
+ new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
+
+ radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
+ radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
+ COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
+ COPY_DATA_WR_CONFIRM);
+ radeon_emit(cs, va);
+ radeon_emit(cs, va >> 32);
+ radeon_emit(cs, new_va);
+ radeon_emit(cs, new_va >> 32);
+
+ radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
+ radeon_emit(cs, 0);
+
/* Enable predication for this command buffer. */
- si_emit_set_predication_state(cmd_buffer, draw_visible, va);
+ si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
cmd_buffer->state.predicating = true;
/* Store conditional rendering user info. */
cmd_buffer->state.predication_type = draw_visible;
- cmd_buffer->state.predication_va = va;
+ cmd_buffer->state.predication_va = new_va;
}
void radv_CmdEndConditionalRenderingEXT(
@@ -4904,7 +4954,7 @@ void radv_CmdBindTransformFeedbackBuffersEXT(
enabled_mask |= 1 << idx;
}
- cmd_buffer->state.streamout.enabled_mask = enabled_mask;
+ cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
}
diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index 01712bd22ce..ac93434b8bd 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -51,6 +51,7 @@ enum {
RADV_DEBUG_CHECKIR = 0x200000,
RADV_DEBUG_NOTHREADLLVM = 0x400000,
RADV_DEBUG_NOBINNING = 0x800000,
+ RADV_DEBUG_NO_LOAD_STORE_OPT = 0x1000000,
};
enum {
diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c
index cebe06aa078..68171b5d244 100644
--- a/src/amd/vulkan/radv_descriptor_set.c
+++ b/src/amd/vulkan/radv_descriptor_set.c
@@ -84,7 +84,9 @@ VkResult radv_CreateDescriptorSetLayout(
uint32_t immutable_sampler_count = 0;
for (uint32_t j = 0; j < pCreateInfo->bindingCount; j++) {
max_binding = MAX2(max_binding, pCreateInfo->pBindings[j].binding);
- if (pCreateInfo->pBindings[j].pImmutableSamplers)
+ if ((pCreateInfo->pBindings[j].descriptorType == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER ||
+ pCreateInfo->pBindings[j].descriptorType == VK_DESCRIPTOR_TYPE_SAMPLER) &&
+ pCreateInfo->pBindings[j].pImmutableSamplers)
immutable_sampler_count += pCreateInfo->pBindings[j].descriptorCount;
}
@@ -182,7 +184,9 @@ VkResult radv_CreateDescriptorSetLayout(
set_layout->has_variable_descriptors = true;
}
- if (binding->pImmutableSamplers) {
+ if ((binding->descriptorType == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER ||
+ binding->descriptorType == VK_DESCRIPTOR_TYPE_SAMPLER) &&
+ binding->pImmutableSamplers) {
set_layout->binding[b].immutable_samplers_offset = samplers_offset;
set_layout->binding[b].immutable_samplers_equal =
has_equal_immutable_samplers(binding->pImmutableSamplers, binding->descriptorCount);
@@ -965,9 +969,11 @@ void radv_update_descriptor_sets(
}
src_ptr += src_binding_layout->size / 4;
dst_ptr += dst_binding_layout->size / 4;
- dst_buffer_list[j] = src_buffer_list[j];
- ++src_buffer_list;
- ++dst_buffer_list;
+
+ if (src_binding_layout->type != VK_DESCRIPTOR_TYPE_SAMPLER) {
+ /* Sampler descriptors don't have a buffer list. */
+ dst_buffer_list[j] = src_buffer_list[j];
+ }
}
}
}
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 34d93b262f8..334c8bd4548 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -111,6 +111,7 @@ radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
+ case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
default: chip_string = "AMD RADV unknown"; break;
@@ -337,7 +338,7 @@ radv_physical_device_init(struct radv_physical_device *device,
device->rad_info.chip_class > GFX9)
fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
- radv_get_driver_uuid(&device->device_uuid);
+ radv_get_driver_uuid(&device->driver_uuid);
radv_get_device_uuid(&device->rad_info, &device->device_uuid);
if (device->rad_info.family == CHIP_STONEY ||
@@ -369,6 +370,11 @@ radv_physical_device_init(struct radv_physical_device *device,
device->dcc_msaa_allowed =
(device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
+ /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
+ device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
+ (device->rad_info.chip_class >= VI &&
+ device->rad_info.me_fw_feature >= 41);
+
radv_physical_device_init_mem_types(device);
radv_fill_device_extension_table(device, &device->supported_extensions);
@@ -460,6 +466,7 @@ static const struct debug_control radv_debug_options[] = {
{"checkir", RADV_DEBUG_CHECKIR},
{"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
{"nobinning", RADV_DEBUG_NOBINNING},
+ {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
{NULL, 0}
};
@@ -505,6 +512,13 @@ radv_handle_per_app_options(struct radv_instance *instance,
} else if (!strcmp(name, "DOOM_VFR")) {
/* Work around a Doom VFR game bug */
instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
+ } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
+ /* Workaround for a WaW hazard when LLVM moves/merges
+ * load/store memory operations.
+ * See https://reviews.llvm.org/D61313
+ */
+ if (HAVE_LLVM < 0x900)
+ instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
}
}
@@ -734,8 +748,7 @@ void radv_GetPhysicalDeviceFeatures(
.alphaToOne = true,
.multiViewport = true,
.samplerAnisotropy = true,
- .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
- pdevice->rad_info.family == CHIP_STONEY,
+ .textureCompressionETC2 = radv_device_supports_etc(pdevice),
.textureCompressionASTC_LDR = false,
.textureCompressionBC = true,
.occlusionQueryPrecise = true,
@@ -802,7 +815,7 @@ void radv_GetPhysicalDeviceFeatures2(
features->storageBuffer16BitAccess = enabled;
features->uniformAndStorageBuffer16BitAccess = enabled;
features->storagePushConstant16 = enabled;
- features->storageInputOutput16 = enabled;
+ features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
break;
}
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
@@ -998,7 +1011,7 @@ void radv_GetPhysicalDeviceProperties(
.maxCullDistances = 8,
.maxCombinedClipAndCullDistances = 8,
.discreteQueuePriorities = 2,
- .pointSizeRange = { 0.125, 255.875 },
+ .pointSizeRange = { 0.0, 8192.0 },
.lineWidthRange = { 0.0, 7.9921875 },
.pointSizeGranularity = (1.0 / 8.0),
.lineWidthGranularity = (1.0 / 128.0),
@@ -2790,7 +2803,7 @@ VkResult radv_QueueSubmit(
struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
struct radeon_winsys_ctx *ctx = queue->hw_ctx;
int ret;
- uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
+ uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
uint32_t scratch_size = 0;
uint32_t compute_scratch_size = 0;
uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
diff --git a/src/amd/vulkan/radv_extensions.py b/src/amd/vulkan/radv_extensions.py
index 1bf56943f25..187c0ba574d 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -100,7 +100,7 @@ def __init__(self, name, ext_version, enable):
Extension('VK_EXT_display_control', 1, 'VK_USE_PLATFORM_DISPLAY_KHR'),
Extension('VK_EXT_debug_report', 9, True),
Extension('VK_EXT_depth_range_unrestricted', 1, True),
- Extension('VK_EXT_descriptor_indexing', 2, True),
+ Extension('VK_EXT_descriptor_indexing', 2, False),
Extension('VK_EXT_discard_rectangles', 1, True),
Extension('VK_EXT_external_memory_dma_buf', 1, True),
Extension('VK_EXT_external_memory_host', 1, 'device->rad_info.has_userptr'),
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 499d94befeb..9c61e769ebd 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -595,6 +595,14 @@ static bool radv_is_filter_minmax_format_supported(VkFormat format)
}
}
+bool
+radv_device_supports_etc(struct radv_physical_device *physical_device)
+{
+ return physical_device->rad_info.family == CHIP_VEGA10 ||
+ physical_device->rad_info.family == CHIP_RAVEN ||
+ physical_device->rad_info.family == CHIP_STONEY;
+}
+
static void
radv_physical_device_get_format_properties(struct radv_physical_device *physical_device,
VkFormat format,
@@ -612,9 +620,7 @@ radv_physical_device_get_format_properties(struct radv_physical_device *physical
}
if (desc->layout == VK_FORMAT_LAYOUT_ETC &&
- physical_device->rad_info.family != CHIP_VEGA10 &&
- physical_device->rad_info.family != CHIP_RAVEN &&
- physical_device->rad_info.family != CHIP_STONEY) {
+ !radv_device_supports_etc(physical_device)) {
out_properties->linearTilingFeatures = linear;
out_properties->optimalTilingFeatures = tiled;
out_properties->bufferFeatures = buffer;
@@ -984,10 +990,22 @@ bool radv_format_pack_clear_color(VkFormat format,
assert(channel->size == 8);
v = util_format_linear_float_to_srgb_8unorm(value->float32[c]);
- } else if (channel->type == VK_FORMAT_TYPE_UNSIGNED) {
- v = MAX2(MIN2(value->float32[c], 1.0f), 0.0f) * ((1ULL << channel->size) - 1);
- } else {
- v = MAX2(MIN2(value->float32[c], 1.0f), -1.0f) * ((1ULL << (channel->size - 1)) - 1);
+ } else {
+ float f = MIN2(value->float32[c], 1.0f);
+
+ if (channel->type == VK_FORMAT_TYPE_UNSIGNED) {
+ f = MAX2(f, 0.0f) * ((1ULL << channel->size) - 1);
+ } else {
+ f = MAX2(f, -1.0f) * ((1ULL << (channel->size - 1)) - 1);
+ }
+
+ /* The hardware rounds before conversion. */
+ if (f > 0)
+ f += 0.5f;
+ else
+ f -= 0.5f;
+
+ v = (uint64_t)f;
}
} else if (channel->type == VK_FORMAT_TYPE_FLOAT) {
if (channel->size == 32) {
diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c
index ef690edb471..f3a8f6464b8 100644
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -849,54 +849,60 @@ build_pipeline(struct radv_device *device,
.subpass = 0,
};
- switch(aspect) {
- case VK_IMAGE_ASPECT_COLOR_BIT:
- vk_pipeline_info.pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
- .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
- .attachmentCount = 1,
- .pAttachments = (VkPipelineColorBlendAttachmentState []) {
- { .colorWriteMask =
- VK_COLOR_COMPONENT_A_BIT |
- VK_COLOR_COMPONENT_R_BIT |
- VK_COLOR_COMPONENT_G_BIT |
- VK_COLOR_COMPONENT_B_BIT },
+ VkPipelineColorBlendStateCreateInfo color_blend_info = {
+ .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
+ .attachmentCount = 1,
+ .pAttachments = (VkPipelineColorBlendAttachmentState []) {
+ {
+ .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
+ VK_COLOR_COMPONENT_R_BIT |
+ VK_COLOR_COMPONENT_G_BIT |
+ VK_COLOR_COMPONENT_B_BIT },
}
};
+
+ VkPipelineDepthStencilStateCreateInfo depth_info = {
+ .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
+ .depthTestEnable = true,
+ .depthWriteEnable = true,
+ .depthCompareOp = VK_COMPARE_OP_ALWAYS,
+ };
+
+ VkPipelineDepthStencilStateCreateInfo stencil_info = {
+ .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
+ .depthTestEnable = false,
+ .depthWriteEnable = false,
+ .stencilTestEnable = true,
+ .front = {
+ .failOp = VK_STENCIL_OP_REPLACE,
+ .passOp = VK_STENCIL_OP_REPLACE,
+ .depthFailOp = VK_STENCIL_OP_REPLACE,
+ .compareOp = VK_COMPARE_OP_ALWAYS,
+ .compareMask = 0xff,
+ .writeMask = 0xff,
+ .reference = 0
+ },
+ .back = {
+ .failOp = VK_STENCIL_OP_REPLACE,
+ .passOp = VK_STENCIL_OP_REPLACE,
+ .depthFailOp = VK_STENCIL_OP_REPLACE,
+ .compareOp = VK_COMPARE_OP_ALWAYS,
+ .compareMask = 0xff,
+ .writeMask = 0xff,
+ .reference = 0
+ },
+ .depthCompareOp = VK_COMPARE_OP_ALWAYS,
+ };
+
+ switch(aspect) {
+ case VK_IMAGE_ASPECT_COLOR_BIT:
+ vk_pipeline_info.pColorBlendState = &color_blend_info;
break;
case VK_IMAGE_ASPECT_DEPTH_BIT:
- vk_pipeline_info.pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
- .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
- .depthTestEnable = true,
- .depthWriteEnable = true,
- .depthCompareOp = VK_COMPARE_OP_ALWAYS,
- };
+ vk_pipeline_info.pDepthStencilState = &depth_info;
break;
case VK_IMAGE_ASPECT_STENCIL_BIT:
- vk_pipeline_info.pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
- .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
- .depthTestEnable = false,
- .depthWriteEnable = false,
- .stencilTestEnable = true,
- .front = {
- .failOp = VK_STENCIL_OP_REPLACE,
- .passOp = VK_STENCIL_OP_REPLACE,
- .depthFailOp = VK_STENCIL_OP_REPLACE,
- .compareOp = VK_COMPARE_OP_ALWAYS,
- .compareMask = 0xff,
- .writeMask = 0xff,
- .reference = 0
- },
- .back = {
- .failOp = VK_STENCIL_OP_REPLACE,
- .passOp = VK_STENCIL_OP_REPLACE,
- .depthFailOp = VK_STENCIL_OP_REPLACE,
- .compareOp = VK_COMPARE_OP_ALWAYS,
- .compareMask = 0xff,
- .writeMask = 0xff,
- .reference = 0
- },
- .depthCompareOp = VK_COMPARE_OP_ALWAYS,
- };
+ vk_pipeline_info.pDepthStencilState = &stencil_info;
break;
default:
unreachable("Unhandled aspect");
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 8805f0435e1..32af736fd8f 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -370,14 +370,29 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
const uint32_t subpass_att = clear_att->colorAttachment;
const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
- const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
- const uint32_t samples = iview->image->info.samples;
- const uint32_t samples_log2 = ffs(samples) - 1;
- unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
+ const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
+ uint32_t samples, samples_log2;
+ VkFormat format;
+ unsigned fs_key;
VkClearColorValue clear_value = clear_att->clearValue.color;
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
VkPipeline pipeline;
+ /* When a framebuffer is bound to the current command buffer, get the
+ * number of samples from it. Otherwise, get the number of samples from
+ * the render pass because it's likely a secondary command buffer.
+ */
+ if (iview) {
+ samples = iview->image->info.samples;
+ format = iview->vk_format;
+ } else {
+ samples = cmd_buffer->state.pass->attachments[pass_att].samples;
+ format = cmd_buffer->state.pass->attachments[pass_att].format;
+ }
+
+ samples_log2 = ffs(samples) - 1;
+ fs_key = radv_format_meta_fs_key(format);
+
if (fs_key == -1) {
radv_finishme("color clears incomplete");
return;
@@ -617,6 +632,9 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
const VkClearRect *clear_rect,
VkClearDepthStencilValue clear_value)
{
+ if (!iview)
+ return false;
+
uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index);
@@ -633,7 +651,7 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
iview->base_mip == 0 &&
iview->base_layer == 0 &&
radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
- !radv_image_extent_compare(iview->image, &iview->extent))
+ radv_image_extent_compare(iview->image, &iview->extent))
return true;
return false;
}
@@ -705,11 +723,22 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
VkImageAspectFlags aspects = clear_att->aspectMask;
- const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
- const uint32_t samples = iview->image->info.samples;
- const uint32_t samples_log2 = ffs(samples) - 1;
+ const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
+ uint32_t samples, samples_log2;
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
+ /* When a framebuffer is bound to the current command buffer, get the
+ * number of samples from it. Otherwise, get the number of samples from
+ * the render pass because it's likely a secondary command buffer.
+ */
+ if (iview) {
+ samples = iview->image->info.samples;
+ } else {
+ samples = cmd_buffer->state.pass->attachments[pass_att].samples;
+ }
+
+ samples_log2 = ffs(samples) - 1;
+
assert(pass_att != VK_ATTACHMENT_UNUSED);
if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
@@ -915,7 +944,11 @@ static bool
radv_image_view_can_fast_clear(struct radv_device *device,
const struct radv_image_view *iview)
{
- struct radv_image *image = iview->image;
+ struct radv_image *image;
+
+ if (!iview)
+ return false;
+ image = iview->image;
/* Only fast clear if the image itself can be fast cleared. */
if (!radv_image_can_fast_clear(device, image))
@@ -1523,7 +1556,7 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer,
const uint32_t subpass_att = clear_att->colorAttachment;
const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
- const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
+ const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
VkClearColorValue clear_value = clear_att->clearValue.color;
if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout,
@@ -1536,8 +1569,11 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer,
}
} else {
const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
+ if (pass_att == VK_ATTACHMENT_UNUSED)
+ return;
+
VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
- const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
+ const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
assert(aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index e80938527e5..00d65de8164 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -92,6 +92,7 @@ struct radv_shader_context {
gl_shader_stage stage;
LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
+ uint64_t float16_shaded_mask;
uint64_t input_mask;
uint64_t output_mask;
@@ -1441,7 +1442,7 @@ store_tcs_output(struct ac_shader_abi *abi,
{
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
const unsigned location = var->data.location;
- const unsigned component = var->data.location_frac;
+ unsigned component = var->data.location_frac;
const bool is_patch = var->data.patch;
const bool is_compact = var->data.compact;
LLVMValueRef dw_addr;
@@ -1459,10 +1460,14 @@ store_tcs_output(struct ac_shader_abi *abi,
}
param = shader_io_get_unique_index(location);
- if (location == VARYING_SLOT_CLIP_DIST0 &&
- is_compact && const_index > 3) {
- const_index -= 3;
- param++;
+ if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
+ const_index += component;
+ component = 0;
+
+ if (const_index >= 4) {
+ const_index -= 4;
+ param++;
+ }
}
if (!is_patch) {
@@ -1529,9 +1534,13 @@ load_tes_input(struct ac_shader_abi *abi,
LLVMValueRef result;
unsigned param = shader_io_get_unique_index(location);
- if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
- const_index -= 3;
- param++;
+ if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
+ const_index += component;
+ component = 0;
+ if (const_index >= 4) {
+ const_index -= 4;
+ param++;
+ }
}
buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
@@ -2018,10 +2027,32 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
- input = ac_build_buffer_load_format(&ctx->ac, t_list,
- buffer_index,
- ctx->ac.i32_0,
- num_channels, false, true);
+ if (ctx->options->key.vs.vertex_attribute_provided & (1u << attrib_index)) {
+ input = ac_build_buffer_load_format(&ctx->ac, t_list,
+ buffer_index,
+ ctx->ac.i32_0,
+ num_channels, false, true);
+ } else {
+ /* Per the Vulkan spec, it's invalid to consume vertex
+ * attributes that are not provided by the pipeline but
+ * some (invalid) apps appear to do that. Fill the
+ * input array with (eg. (0, 0, 0, 1)) to workaround
+ * the problem and to avoid possible GPU hangs.
+ */
+ LLVMValueRef chan[4];
+
+ /* The input_usage mask might be 0 if input variables
+ * are not removed by the compiler.
+ */
+ num_channels = CLAMP(num_channels, 1, 4);
+
+ for (unsigned i = 0; i < num_channels; i++) {
+ chan[i] = i == 3 ? ctx->ac.f32_1 : ctx->ac.f32_0;
+ chan[i] = ac_to_float(&ctx->ac, chan[i]);
+ }
+
+ input = ac_build_gather_values(&ctx->ac, chan, num_channels);
+ }
input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
@@ -2051,6 +2082,7 @@ static void interp_fs_input(struct radv_shader_context *ctx,
unsigned attr,
LLVMValueRef interp_param,
LLVMValueRef prim_mask,
+ bool float16,
LLVMValueRef result[4])
{
LLVMValueRef attr_number;
@@ -2083,7 +2115,12 @@ static void interp_fs_input(struct radv_shader_context *ctx,
for (chan = 0; chan < 4; chan++) {
LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
- if (interp) {
+ if (interp && float16) {
+ result[chan] = ac_build_fs_interp_f16(&ctx->ac,
+ llvm_chan,
+ attr_number,
+ prim_mask, i, j);
+ } else if (interp) {
result[chan] = ac_build_fs_interp(&ctx->ac,
llvm_chan,
attr_number,
@@ -2095,7 +2132,30 @@ static void interp_fs_input(struct radv_shader_context *ctx,
attr_number,
prim_mask);
result[chan] = LLVMBuildBitCast(ctx->ac.builder, result[chan], ctx->ac.i32, "");
- result[chan] = LLVMBuildTruncOrBitCast(ctx->ac.builder, result[chan], LLVMTypeOf(interp_param), "");
+ result[chan] = LLVMBuildTruncOrBitCast(ctx->ac.builder, result[chan], float16 ? ctx->ac.i16 : ctx->ac.i32, "");
+ }
+ }
+}
+
+static void mark_16bit_fs_input(struct radv_shader_context *ctx,
+ const struct glsl_type *type,
+ int location)
+{
+ if (glsl_type_is_scalar(type) || glsl_type_is_vector(type) || glsl_type_is_matrix(type)) {
+ unsigned attrib_count = glsl_count_attribute_slots(type, false);
+ if (glsl_type_is_16bit(type)) {
+ ctx->float16_shaded_mask |= ((1ull << attrib_count) - 1) << location;
+ }
+ } else if (glsl_type_is_array(type)) {
+ unsigned stride = glsl_count_attribute_slots(glsl_get_array_element(type), false);
+ for (unsigned i = 0; i < glsl_get_length(type); ++i) {
+ mark_16bit_fs_input(ctx, glsl_get_array_element(type), location + i * stride);
+ }
+ } else {
+ assert(glsl_type_is_struct(type));
+ for (unsigned i = 0; i < glsl_get_length(type); i++) {
+ mark_16bit_fs_input(ctx, glsl_get_struct_field(type, i), location);
+ location += glsl_count_attribute_slots(glsl_get_struct_field(type, i), false);
}
}
}
@@ -2110,9 +2170,20 @@ handle_fs_input_decl(struct radv_shader_context *ctx,
uint64_t mask;
variable->data.driver_location = idx * 4;
+
+
+ if (variable->data.compact) {
+ unsigned component_count = variable->data.location_frac +
+ glsl_get_length(variable->type);
+ attrib_count = (component_count + 3) / 4;
+ } else
+ mark_16bit_fs_input(ctx, variable->type, idx);
+
mask = ((1ull << attrib_count) - 1) << variable->data.location;
- if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
+ if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT ||
+ glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT16 ||
+ glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_STRUCT) {
unsigned interp_type;
if (variable->data.sample)
interp_type = INTERP_SAMPLE;
@@ -2123,22 +2194,12 @@ handle_fs_input_decl(struct radv_shader_context *ctx,
interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
}
- bool is_16bit = glsl_type_is_16bit(glsl_without_array(variable->type));
- LLVMTypeRef type = is_16bit ? ctx->ac.i16 : ctx->ac.i32;
if (interp == NULL)
- interp = LLVMGetUndef(type);
+ interp = LLVMGetUndef(ctx->ac.i32);
for (unsigned i = 0; i < attrib_count; ++i)
ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
- if (idx == VARYING_SLOT_CLIP_DIST0) {
- /* Do not account for the number of components inside the array
- * of clip/cull distances because this might wrongly set other
- * bits like primitive ID or layer.
- */
- mask = 1ull << VARYING_SLOT_CLIP_DIST0;
- }
-
ctx->input_mask |= mask;
}
@@ -2200,11 +2261,14 @@ handle_fs_inputs(struct radv_shader_context *ctx,
if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
interp_param = *inputs;
- interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
+ bool float16 = (ctx->float16_shaded_mask >> i) & 1;
+ interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask, float16,
inputs);
if (LLVMIsUndef(interp_param))
ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
+ if (float16)
+ ctx->shader_info->fs.float16_shaded_mask |= 1u << index;
if (i >= VARYING_SLOT_VAR0)
ctx->abi.fs_input_attr_indices[i - VARYING_SLOT_VAR0] = index;
++index;
@@ -2216,7 +2280,7 @@ handle_fs_inputs(struct radv_shader_context *ctx,
interp_param = *inputs;
interp_fs_input(ctx, index, interp_param,
- ctx->abi.prim_mask, inputs);
+ ctx->abi.prim_mask, false, inputs);
++index;
}
} else if (i == VARYING_SLOT_POS) {
@@ -2250,6 +2314,12 @@ scan_shader_output_decl(struct radv_shader_context *ctx,
if (stage == MESA_SHADER_TESS_CTRL)
return;
+ if (variable->data.compact) {
+ unsigned component_count = variable->data.location_frac +
+ glsl_get_length(variable->type);
+ attrib_count = (component_count + 3) / 4;
+ }
+
mask_attribs = ((1ull << attrib_count) - 1) << idx;
if (stage == MESA_SHADER_VERTEX ||
stage == MESA_SHADER_TESS_EVAL ||
@@ -2265,8 +2335,6 @@ scan_shader_output_decl(struct radv_shader_context *ctx,
ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
ctx->shader_info->tes.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
}
-
- mask_attribs = 1ull << idx;
}
}
@@ -2365,7 +2433,7 @@ si_llvm_init_export_args(struct radv_shader_context *ctx,
if (is_16bit) {
for (unsigned chan = 0; chan < 4; chan++)
values[chan] = LLVMBuildZExt(ctx->ac.builder,
- values[chan],
+ ac_to_integer(&ctx->ac, values[chan]),
ctx->ac.i32, "");
}
break;
@@ -2376,7 +2444,7 @@ si_llvm_init_export_args(struct radv_shader_context *ctx,
if (is_16bit) {
for (unsigned chan = 0; chan < 4; chan++)
values[chan] = LLVMBuildSExt(ctx->ac.builder,
- values[chan],
+ ac_to_integer(&ctx->ac, values[chan]),
ctx->ac.i32, "");
}
break;
@@ -2429,12 +2497,8 @@ si_llvm_init_export_args(struct radv_shader_context *ctx,
} else
memcpy(&args->out[0], values, sizeof(values[0]) * 4);
- for (unsigned i = 0; i < 4; ++i) {
- if (!(args->enabled_channels & (1 << i)))
- continue;
-
+ for (unsigned i = 0; i < 4; ++i)
args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
- }
}
static void
@@ -2615,51 +2679,41 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
sizeof(outinfo->vs_output_param_offset));
- if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
- unsigned output_usage_mask, length;
- LLVMValueRef slots[8];
- unsigned j;
-
- if (ctx->stage == MESA_SHADER_VERTEX &&
- !ctx->is_gs_copy_shader) {
- output_usage_mask =
- ctx->shader_info->info.vs.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
- } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
- output_usage_mask =
- ctx->shader_info->info.tes.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
- } else {
- assert(ctx->is_gs_copy_shader);
- output_usage_mask =
- ctx->shader_info->info.gs.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
- }
+ for(unsigned location = VARYING_SLOT_CLIP_DIST0; location <= VARYING_SLOT_CLIP_DIST1; ++location) {
+ if (ctx->output_mask & (1ull << location)) {
+ unsigned output_usage_mask, length;
+ LLVMValueRef slots[4];
+ unsigned j;
+
+ if (ctx->stage == MESA_SHADER_VERTEX &&
+ !ctx->is_gs_copy_shader) {
+ output_usage_mask =
+ ctx->shader_info->info.vs.output_usage_mask[location];
+ } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
+ output_usage_mask =
+ ctx->shader_info->info.tes.output_usage_mask[location];
+ } else {
+ assert(ctx->is_gs_copy_shader);
+ output_usage_mask =
+ ctx->shader_info->info.gs.output_usage_mask[location];
+ }
- length = util_last_bit(output_usage_mask);
+ length = util_last_bit(output_usage_mask);
- i = VARYING_SLOT_CLIP_DIST0;
- for (j = 0; j < length; j++)
- slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
+ for (j = 0; j < length; j++)
+ slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, location, j));
- for (i = length; i < 8; i++)
- slots[i] = LLVMGetUndef(ctx->ac.f32);
+ for (i = length; i < 4; i++)
+ slots[i] = LLVMGetUndef(ctx->ac.f32);
- if (length > 4) {
- target = V_008DFC_SQ_EXP_POS + 3;
- si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
+ target = V_008DFC_SQ_EXP_POS + 2 + (location - VARYING_SLOT_CLIP_DIST0);
+ si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
- &args, sizeof(args));
- }
+ &args, sizeof(args));
- target = V_008DFC_SQ_EXP_POS + 2;
- si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
- memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
- &args, sizeof(args));
-
- /* Export the clip/cull distances values to the next stage. */
- radv_export_param(ctx, param_count, &slots[0], 0xf);
- outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0] = param_count++;
- if (length > 4) {
- radv_export_param(ctx, param_count, &slots[4], 0xf);
- outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1] = param_count++;
+ /* Export the clip/cull distances values to the next stage. */
+ radv_export_param(ctx, param_count, &slots[0], 0xf);
+ outinfo->vs_output_param_offset[location] = param_count++;
}
}
@@ -2820,28 +2874,14 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
LLVMValueRef lds_base = NULL;
for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
- unsigned output_usage_mask;
int param_index;
- int length = 4;
if (!(ctx->output_mask & (1ull << i)))
continue;
- if (ctx->stage == MESA_SHADER_VERTEX) {
- output_usage_mask =
- ctx->shader_info->info.vs.output_usage_mask[i];
- } else {
- assert(ctx->stage == MESA_SHADER_TESS_EVAL);
- output_usage_mask =
- ctx->shader_info->info.tes.output_usage_mask[i];
- }
-
- if (i == VARYING_SLOT_CLIP_DIST0)
- length = util_last_bit(output_usage_mask);
-
param_index = shader_io_get_unique_index(i);
- max_output_written = MAX2(param_index + (length > 4), max_output_written);
+ max_output_written = MAX2(param_index, max_output_written);
}
outinfo->esgs_itemsize = (max_output_written + 1) * 16;
@@ -2862,7 +2902,6 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
unsigned output_usage_mask;
int param_index;
- int length = 4;
if (!(ctx->output_mask & (1ull << i)))
continue;
@@ -2876,9 +2915,6 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
ctx->shader_info->info.tes.output_usage_mask[i];
}
- if (i == VARYING_SLOT_CLIP_DIST0)
- length = util_last_bit(output_usage_mask);
-
param_index = shader_io_get_unique_index(i);
if (lds_base) {
@@ -2887,7 +2923,7 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
"");
}
- for (j = 0; j < length; j++) {
+ for (j = 0; j < 4; j++) {
if (!(output_usage_mask & (1 << j)))
continue;
@@ -2924,22 +2960,16 @@ handle_ls_outputs_post(struct radv_shader_context *ctx)
vertex_dw_stride, "");
for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
- unsigned output_usage_mask =
- ctx->shader_info->info.vs.output_usage_mask[i];
LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
- int length = 4;
if (!(ctx->output_mask & (1ull << i)))
continue;
- if (i == VARYING_SLOT_CLIP_DIST0)
- length = util_last_bit(output_usage_mask);
-
int param = shader_io_get_unique_index(i);
LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
LLVMConstInt(ctx->ac.i32, param * 4, false),
"");
- for (unsigned j = 0; j < length; j++) {
+ for (unsigned j = 0; j < 4; j++) {
LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
value = ac_to_integer(&ctx->ac, value);
value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
@@ -3467,10 +3497,17 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
ctx.abi.clamp_shadow_reference = false;
ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9 && HAVE_LLVM < 0x800;
+ /* Because the new raw/struct atomic intrinsics are buggy with LLVM 8,
+ * we fallback to the old intrinsics for atomic buffer image operations
+ * and thus we need to apply the indexing workaround...
+ */
+ ctx.abi.gfx9_stride_size_workaround_for_atomic = ctx.ac.chip_class == GFX9 && HAVE_LLVM < 0x900;
+
if (shader_count >= 2)
ac_init_exec_full_mask(&ctx.ac);
- if (ctx.ac.chip_class == GFX9 &&
+ if ((ctx.ac.family == CHIP_VEGA10 ||
+ ctx.ac.family == CHIP_RAVEN) &&
shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
ac_nir_fixup_ls_hs_input_vgprs(&ctx);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 138e153f9a4..2526000f56f 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -524,6 +524,14 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
col_format |= cf << (4 * i);
}
+ if (!col_format && blend->need_src_alpha & (1 << 0)) {
+ /* When a subpass doesn't have any color attachments, write the
+ * alpha channel of MRT0 when alpha coverage is enabled because
+ * the depth attachment needs it.
+ */
+ col_format |= V_028714_SPI_SHADER_32_ABGR;
+ }
+
/* If the i-th target format is set, all previous target formats must
* be non-zero to avoid hangs.
*/
@@ -689,6 +697,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
if (vkms && vkms->alphaToCoverageEnable) {
blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
+ blend.need_src_alpha |= 0x1;
}
blend.cb_target_mask = 0;
@@ -1436,11 +1445,13 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
- if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
+ if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
- typed_memcpy(dynamic->discard_rectangle.rectangles,
- discard_rectangle_info->pDiscardRectangles,
- discard_rectangle_info->discardRectangleCount);
+ if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
+ typed_memcpy(dynamic->discard_rectangle.rectangles,
+ discard_rectangle_info->pDiscardRectangles,
+ discard_rectangle_info->discardRectangleCount);
+ }
}
pipeline->dynamic_state.mask = states;
@@ -1913,6 +1924,8 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
}
key.vertex_alpha_adjust |= adjust << (2 * location);
}
+
+ key.vertex_attribute_provided |= 1 << location;
}
if (pCreateInfo->pTessellationState)
@@ -1941,6 +1954,7 @@ radv_fill_shader_keys(struct radv_shader_variant_key *keys,
{
keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
+ keys[MESA_SHADER_VERTEX].vs.vertex_attribute_provided = key->vertex_attribute_provided;
for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i)
keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
@@ -3079,13 +3093,17 @@ radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
}
-static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
+static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
{
uint32_t ps_input_cntl;
if (offset <= AC_EXP_PARAM_OFFSET_31) {
ps_input_cntl = S_028644_OFFSET(offset);
if (flat_shade)
ps_input_cntl |= S_028644_FLAT_SHADE(1);
+ if (float16) {
+ ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
+ S_028644_ATTR0_VALID(1);
+ }
} else {
/* The input is a DEFAULT_VAL constant. */
assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
@@ -3110,7 +3128,7 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
if (ps->info.info.ps.prim_id_input) {
unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
- ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
++ps_offset;
}
}
@@ -3120,9 +3138,9 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
ps->info.info.needs_multiview_view_index) {
unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
if (vs_offset != AC_EXP_PARAM_UNDEFINED)
- ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
else
- ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
+ ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
++ps_offset;
}
@@ -3138,14 +3156,14 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
- ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false);
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
++ps_offset;
}
vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
ps->info.info.ps.num_input_clips_culls > 4) {
- ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false);
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
++ps_offset;
}
}
@@ -3153,6 +3171,7 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
unsigned vs_offset;
bool flat_shade;
+ bool float16;
if (!(ps->info.fs.input_mask & (1u << i)))
continue;
@@ -3164,8 +3183,9 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
}
flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
+ float16 = !!(ps->info.fs.float16_shaded_mask & (1u << ps_offset));
- ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
+ ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
++ps_offset;
}
@@ -3192,11 +3212,11 @@ radv_compute_db_shader_control(const struct radv_device *device,
bool disable_rbplus = device->physical_device->has_rbplus &&
!device->physical_device->rbplus_allowed;
- /* Do not enable the gl_SampleMask fragment shader output if MSAA is
- * disabled.
+ /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
+ * but this appears to break Project Cars (DXVK). See
+ * https://bugs.freedesktop.org/show_bug.cgi?id=109401
*/
- bool mask_export_enable = ms->num_samples > 1 &&
- ps->info.info.ps.writes_sample_mask;
+ bool mask_export_enable = ps->info.info.ps.writes_sample_mask;
return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 85c18906f84..ea957ae6dab 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -306,6 +306,9 @@ struct radv_physical_device {
/* Whether DCC should be enabled for MSAA textures. */
bool dcc_msaa_allowed;
+ /* Whether LOAD_CONTEXT_REG packets are supported. */
+ bool has_load_ctx_reg_pkt;
+
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
*/
@@ -362,6 +365,7 @@ struct radv_pipeline_cache {
struct radv_pipeline_key {
uint32_t instance_rate_inputs;
uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_provided;
uint64_t vertex_alpha_adjust;
unsigned tess_input_vertices;
uint32_t col_format;
@@ -1144,6 +1148,7 @@ void si_write_scissors(struct radeon_cmdbuf *cs, int first,
const VkViewport *viewports, bool can_use_guardband);
uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
bool instanced_draw, bool indirect_draw,
+ bool count_from_stream_output,
uint32_t draw_vertex_count);
void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
enum chip_class chip_class,
@@ -1462,6 +1467,7 @@ bool radv_format_pack_clear_color(VkFormat format,
bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
bool radv_dcc_formats_compatible(VkFormat format1,
VkFormat format2);
+bool radv_device_supports_etc(struct radv_physical_device *physical_device);
struct radv_fmask_info {
uint64_t offset;
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 32cd9ae25e9..ec571e2f8c5 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -159,7 +159,7 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
NIR_PASS(progress, shader, nir_opt_if);
NIR_PASS(progress, shader, nir_opt_dead_cf);
NIR_PASS(progress, shader, nir_opt_cse);
- NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
+ NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true);
NIR_PASS(progress, shader, nir_opt_algebraic);
NIR_PASS(progress, shader, nir_opt_constant_folding);
NIR_PASS(progress, shader, nir_opt_undef);
@@ -222,6 +222,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
.lower_ubo_ssbo_access_to_offsets = true,
.caps = {
.descriptor_array_dynamic_indexing = true,
+ .descriptor_array_non_uniform_indexing = true,
+ .descriptor_indexing = true,
.device_group = true,
.draw_parameters = true,
.float64 = true,
@@ -610,6 +612,8 @@ shader_variant_create(struct radv_device *device,
tm_options |= AC_TM_SISCHED;
if (options->check_ir)
tm_options |= AC_TM_CHECK_IR;
+ if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
+ tm_options |= AC_TM_NO_LOAD_STORE_OPT;
thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
radv_init_llvm_once();
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 3652a811e80..f6f9dd2bbf1 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -66,6 +66,9 @@ struct radv_vs_variant_key {
uint32_t instance_rate_inputs;
uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+ /* Mask of vertex attributes that are provided by the pipeline. */
+ uint32_t vertex_attribute_provided;
+
/* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
* so we may need to fix it up. */
uint64_t alpha_adjust;
@@ -257,6 +260,7 @@ struct radv_shader_variant_info {
unsigned num_interp;
uint32_t input_mask;
uint32_t flat_shaded_mask;
+ uint32_t float16_shaded_mask;
bool can_discard;
bool early_fragment_test;
} fs;
@@ -401,6 +405,8 @@ static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
return 1;
if (slot == VARYING_SLOT_CLIP_DIST0)
return 2;
+ if (slot == VARYING_SLOT_CLIP_DIST1)
+ return 3;
/* 3 is reserved for clip dist as well */
if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
return 4 + (slot - VARYING_SLOT_VAR0);
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index 7e5a3789af2..fdc4f52086b 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -101,7 +101,7 @@ gather_intrinsic_load_deref_info(const nir_shader *nir,
case MESA_SHADER_VERTEX: {
nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
- if (var->data.mode == nir_var_shader_in) {
+ if (var && var->data.mode == nir_var_shader_in) {
unsigned idx = var->data.location;
uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
@@ -115,6 +115,15 @@ gather_intrinsic_load_deref_info(const nir_shader *nir,
}
}
+static uint32_t
+widen_writemask(uint32_t wrmask)
+{
+ uint32_t new_wrmask = 0;
+ for(unsigned i = 0; i < 4; i++)
+ new_wrmask |= (wrmask & (1 << i) ? 0x3 : 0x0) << (i * 2);
+ return new_wrmask;
+}
+
static void
set_output_usage_mask(const nir_shader *nir, const nir_intrinsic_instr *instr,
uint8_t *output_usage_mask)
@@ -122,25 +131,27 @@ set_output_usage_mask(const nir_shader *nir, const nir_intrinsic_instr *instr,
nir_deref_instr *deref_instr =
nir_instr_as_deref(instr->src[0].ssa->parent_instr);
nir_variable *var = nir_deref_instr_get_variable(deref_instr);
- unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
+ unsigned attrib_count = glsl_count_attribute_slots(deref_instr->type, false);
unsigned idx = var->data.location;
unsigned comp = var->data.location_frac;
unsigned const_offset = 0;
get_deref_offset(deref_instr, &const_offset);
- if (idx == VARYING_SLOT_CLIP_DIST0) {
- /* Special case for clip/cull distances because there are
- * combined into a single array that contains both.
- */
- output_usage_mask[idx] |= 1 << const_offset;
+ if (var->data.compact) {
+ assert(!glsl_type_is_64bit(deref_instr->type));
+ const_offset += comp;
+ output_usage_mask[idx + const_offset / 4] |= 1 << (const_offset % 4);
return;
}
- for (unsigned i = 0; i < attrib_count; i++) {
+ uint32_t wrmask = nir_intrinsic_write_mask(instr);
+ if (glsl_type_is_64bit(deref_instr->type))
+ wrmask = widen_writemask(wrmask);
+
+ for (unsigned i = 0; i < attrib_count; i++)
output_usage_mask[idx + i + const_offset] |=
- instr->const_index[0] << comp;
- }
+ ((wrmask >> (i * 4)) & 0xf) << comp;
}
static void
@@ -150,7 +161,7 @@ gather_intrinsic_store_deref_info(const nir_shader *nir,
{
nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
- if (var->data.mode == nir_var_shader_out) {
+ if (var && var->data.mode == nir_var_shader_out) {
unsigned idx = var->data.location;
switch (nir->info.stage) {
@@ -174,13 +185,9 @@ gather_intrinsic_store_deref_info(const nir_shader *nir,
type = glsl_get_array_element(var->type);
unsigned slots =
- var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
+ var->data.compact ? DIV_ROUND_UP(var->data.location_frac + glsl_get_length(type), 4)
: glsl_count_attribute_slots(type, false);
- if (idx == VARYING_SLOT_CLIP_DIST0)
- slots = (nir->info.clip_distance_array_size +
- nir->info.cull_distance_array_size > 4) ? 2 : 1;
-
mark_tess_output(info, var->data.patch, param, slots);
break;
}
@@ -374,7 +381,8 @@ gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
info->ps.layer_input = true;
break;
case VARYING_SLOT_CLIP_DIST0:
- info->ps.num_input_clips_culls = attrib_count;
+ case VARYING_SLOT_CLIP_DIST1:
+ info->ps.num_input_clips_culls += attrib_count;
break;
default:
break;
@@ -409,8 +417,8 @@ gather_info_output_decl_ls(const nir_shader *nir, const nir_variable *var,
int idx = var->data.location;
unsigned param = shader_io_get_unique_index(idx);
int num_slots = glsl_count_attribute_slots(var->type, false);
- if (idx == VARYING_SLOT_CLIP_DIST0)
- num_slots = (nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4) ? 2 : 1;
+ if (var->data.compact)
+ num_slots = DIV_ROUND_UP(var->data.location_frac + glsl_get_length(var->type), 4);
mark_ls_output(info, param, num_slots);
}
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index e75c6d127d6..e73c13762e5 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -561,6 +561,7 @@ radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
uint32_t
si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
bool instanced_draw, bool indirect_draw,
+ bool count_from_stream_output,
uint32_t draw_vertex_count)
{
enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
@@ -622,6 +623,12 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
(instanced_draw || indirect_draw))
partial_vs_wave = true;
+ /* Hardware requirement when drawing primitives from a stream
+ * output buffer.
+ */
+ if (count_from_stream_output)
+ wd_switch_on_eop = true;
+
/* If the WD switch is false, the IA switch must be false too. */
assert(wd_switch_on_eop || !ia_switch_on_eop);
}
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index d3b1e2cd4c6..49a86a72c31 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -543,7 +543,7 @@ static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs,
cs->handles[cs->num_buffers].bo_handle = bo;
cs->handles[cs->num_buffers].bo_priority = priority;
- hash = ((uintptr_t)bo >> 6) & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
+ hash = bo & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
cs->buffer_hash_table[hash] = cs->num_buffers;
++cs->num_buffers;
@@ -665,6 +665,7 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
assert(num < ws->num_buffers);
handles[num].bo_handle = bo->bo_handle;
handles[num].bo_priority = bo->priority;
+ num++;
}
r = amdgpu_bo_list_create_raw(ws->dev, ws->num_buffers,
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys_public.h b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys_public.h
index 854e216551f..709669b2a57 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys_public.h
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys_public.h
@@ -29,6 +29,13 @@
#ifndef RADV_AMDGPU_WINSYS_PUBLIC_H
#define RADV_AMDGPU_WINSYS_PUBLIC_H
+/* The number of IBs per submit isn't infinite, it depends on the ring type
+ * (ie. some initial setup needed for a submit) and the number of IBs (4 DW).
+ * This limit is arbitrary but should be safe for now. Ideally, we should get
+ * this limit from the KMD.
+*/
+#define RADV_MAX_IBS_PER_SUBMIT 192
+
struct radeon_winsys *radv_amdgpu_winsys_create(int fd, uint64_t debug_flags,
uint64_t perftest_flags);
diff --git a/src/broadcom/cle/v3d_packet_v33.xml b/src/broadcom/cle/v3d_packet_v33.xml
index 754461dc067..06e8ddad7ec 100644
--- a/src/broadcom/cle/v3d_packet_v33.xml
+++ b/src/broadcom/cle/v3d_packet_v33.xml
@@ -820,8 +820,8 @@
-
#endif /* HAVE_ANDROID_PLATFORM */
+#ifdef HAVE_GRALLOC1
+#include
+#endif
+
#include "eglconfig.h"
#include "eglcontext.h"
#include "egldevice.h"
@@ -238,7 +242,14 @@ struct dri2_egl_display
#endif
#ifdef HAVE_ANDROID_PLATFORM
- const gralloc_module_t *gralloc;
+ const hw_module_t *gralloc;
+ uint16_t gralloc_version;
+#ifdef HAVE_GRALLOC1
+ gralloc1_device_t *gralloc1_dvc;
+ GRALLOC1_PFN_LOCK_FLEX pfn_lockflex;
+ GRALLOC1_PFN_GET_FORMAT pfn_getFormat;
+ GRALLOC1_PFN_UNLOCK pfn_unlock;
+#endif
#endif
bool is_render_node;
diff --git a/src/egl/drivers/dri2/platform_android.c b/src/egl/drivers/dri2/platform_android.c
index 366a9ec14e9..a08723625fb 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -49,6 +49,8 @@
#define ALIGN(val, align) (((val) + (align) - 1) & ~((align) - 1))
+#define GRALLOC_DRM_GET_FORMAT 1
+
struct droid_yuv_format {
/* Lookup keys */
int native; /* HAL_PIXEL_FORMAT_ */
@@ -59,14 +61,26 @@ struct droid_yuv_format {
int fourcc; /* __DRI_IMAGE_FOURCC_ */
};
+/* This enumeration can be deleted if Android defined it in
+ * system/core/include/system/graphics.h
+ */
+enum {
+ HAL_PIXEL_FORMAT_NV12_Y_TILED_INTEL = 0x100,
+ HAL_PIXEL_FORMAT_NV12 = 0x10F,
+ HAL_PIXEL_FORMAT_P010_INTEL = 0x110
+};
+
/* The following table is used to look up a DRI image FourCC based
* on native format and information contained in android_ycbcr struct. */
static const struct droid_yuv_format droid_yuv_formats[] = {
/* Native format, YCrCb, Chroma step, DRI image FourCC */
{ HAL_PIXEL_FORMAT_YCbCr_420_888, 0, 2, __DRI_IMAGE_FOURCC_NV12 },
+ { HAL_PIXEL_FORMAT_P010_INTEL, 0, 4, __DRI_IMAGE_FOURCC_P010 },
{ HAL_PIXEL_FORMAT_YCbCr_420_888, 0, 1, __DRI_IMAGE_FOURCC_YUV420 },
{ HAL_PIXEL_FORMAT_YCbCr_420_888, 1, 1, __DRI_IMAGE_FOURCC_YVU420 },
{ HAL_PIXEL_FORMAT_YV12, 1, 1, __DRI_IMAGE_FOURCC_YVU420 },
+ { HAL_PIXEL_FORMAT_NV12, 0, 2, __DRI_IMAGE_FOURCC_NV12 },
+ { HAL_PIXEL_FORMAT_NV12_Y_TILED_INTEL, 0, 2, __DRI_IMAGE_FOURCC_NV12 },
/* HACK: See droid_create_image_from_prime_fd() and
* https://issuetracker.google.com/32077885. */
{ HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED, 0, 2, __DRI_IMAGE_FOURCC_NV12 },
@@ -249,6 +263,51 @@ droid_window_dequeue_buffer(struct dri2_egl_surface *dri2_surf)
return EGL_TRUE;
}
+static int
+droid_resolve_format(struct dri2_egl_display *dri2_dpy,
+ struct ANativeWindowBuffer *buf)
+{
+ int format = -1;
+ int ret;
+
+ if (buf->format != HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED)
+ return buf->format;
+#ifdef HAVE_GRALLOC1
+ if(dri2_dpy->gralloc_version == HARDWARE_MODULE_API_VERSION(1, 0)) {
+
+ if (!dri2_dpy->pfn_getFormat) {
+ _eglLog(_EGL_WARNING, "Gralloc does not support getFormat");
+ return -1;
+ }
+ ret = dri2_dpy->pfn_getFormat(dri2_dpy->gralloc1_dvc, buf->handle,
+ &format);
+ if (ret) {
+ _eglLog(_EGL_WARNING, "gralloc->getFormat failed: %d", ret);
+ return -1;
+ }
+ } else {
+#else
+ const gralloc_module_t *gralloc0;
+ gralloc0 = dri2_dpy->gralloc;
+
+ if (!gralloc0->perform) {
+ _eglLog(_EGL_WARNING, "gralloc->perform not supported");
+ return -1;
+ }
+ ret = gralloc0->perform(dri2_dpy->gralloc,
+ GRALLOC_DRM_GET_FORMAT,
+ buf->handle, &format);
+ if (ret){
+ _eglLog(_EGL_WARNING, "gralloc->perform failed with error: %d", ret);
+ return -1;
+ }
+#endif
+#ifdef HAVE_GRALLOC1
+ }
+#endif
+ return format;
+}
+
static EGLBoolean
droid_window_enqueue_buffer(_EGLDisplay *disp, struct dri2_egl_surface *dri2_surf)
{
@@ -463,7 +522,7 @@ droid_swap_interval(_EGLDriver *drv, _EGLDisplay *dpy,
struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
struct ANativeWindow *window = dri2_surf->window;
- if (window->setSwapInterval(window, interval))
+ if (window && window->setSwapInterval(window, interval))
return EGL_FALSE;
surf->SwapInterval = interval;
@@ -664,11 +723,18 @@ droid_query_buffer_age(_EGLDriver *drv,
{
struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surface);
+ /* To avoid blocking other EGL calls, release the display mutex before
+ * we enter droid_window_dequeue_buffer() and re-acquire the mutex upon
+ * return.
+ */
+ mtx_unlock(&disp->Mutex);
if (update_buffers(dri2_surf) < 0) {
_eglError(EGL_BAD_ALLOC, "droid_query_buffer_age");
+ mtx_lock(&disp->Mutex);
return -1;
}
+ mtx_lock(&disp->Mutex);
return dri2_surf->back ? dri2_surf->back->age : 0;
}
@@ -731,6 +797,31 @@ droid_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *draw)
return EGL_TRUE;
}
+static int get_ycbcr_from_flexlayout(struct android_flex_layout *outFlexLayout, struct android_ycbcr *ycbcr)
+{
+
+ for( int i = 0; i < outFlexLayout->num_planes; i++) {
+ switch(outFlexLayout->planes[i].component){
+ case FLEX_COMPONENT_Y:
+ ycbcr->y = outFlexLayout->planes[i].top_left;
+ ycbcr->ystride = outFlexLayout->planes[i].v_increment;
+ break;
+ case FLEX_COMPONENT_Cb:
+ ycbcr->cb = outFlexLayout->planes[i].top_left;
+ ycbcr->cstride = outFlexLayout->planes[i].v_increment;
+ break;
+ case FLEX_COMPONENT_Cr:
+ ycbcr->cr = outFlexLayout->planes[i].top_left;
+ ycbcr->chroma_step = outFlexLayout->planes[i].h_increment;
+ break;
+ default:
+ _eglLog(_EGL_WARNING,"unknown component 0x%x", __func__, outFlexLayout->planes[i].component);
+ break;
+ }
+ }
+ return 0;
+}
+
#if ANDROID_API_LEVEL >= 23
static EGLBoolean
droid_set_damage_region(_EGLDriver *drv,
@@ -774,30 +865,70 @@ droid_create_image_from_prime_fd_yuv(_EGLDisplay *disp, _EGLContext *ctx,
{
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
struct android_ycbcr ycbcr;
+#ifdef HAVE_GRALLOC1
+ struct android_flex_layout outFlexLayout;
+ gralloc1_rect_t accessRegion;
+#endif
size_t offsets[3];
size_t pitches[3];
int is_ycrcb;
int fourcc;
int ret;
- if (!dri2_dpy->gralloc->lock_ycbcr) {
- _eglLog(_EGL_WARNING, "Gralloc does not support lock_ycbcr");
+ int format = droid_resolve_format(dri2_dpy, buf);
+ if (format < 0) {
+ _eglError(EGL_BAD_PARAMETER, "eglCreateEGLImageKHR");
return NULL;
}
memset(&ycbcr, 0, sizeof(ycbcr));
- ret = dri2_dpy->gralloc->lock_ycbcr(dri2_dpy->gralloc, buf->handle,
- 0, 0, 0, 0, 0, &ycbcr);
- if (ret) {
- /* HACK: See droid_create_image_from_prime_fd() and
- * https://issuetracker.google.com/32077885.*/
- if (buf->format == HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED)
- return NULL;
-
- _eglLog(_EGL_WARNING, "gralloc->lock_ycbcr failed: %d", ret);
- return NULL;
- }
- dri2_dpy->gralloc->unlock(dri2_dpy->gralloc, buf->handle);
+#ifdef HAVE_GRALLOC1
+ if(dri2_dpy->gralloc_version == HARDWARE_MODULE_API_VERSION(1, 0)) {
+ if (!dri2_dpy->pfn_lockflex) {
+ _eglLog(_EGL_WARNING, "Gralloc does not support lockflex");
+ return NULL;
+ }
+
+ ret = dri2_dpy->pfn_lockflex(dri2_dpy->gralloc1_dvc, buf->handle,
+ 0, 0, &accessRegion, &outFlexLayout, -1);
+ if (ret) {
+ _eglLog(_EGL_WARNING, "gralloc->lockflex failed: %d", ret);
+ return NULL;
+ }
+ ret = get_ycbcr_from_flexlayout(&outFlexLayout, &ycbcr);
+ if (ret) {
+ _eglLog(_EGL_WARNING, "gralloc->lockflex failed: %d", ret);
+ return NULL;
+ }
+ int outReleaseFence = 0;
+ dri2_dpy->pfn_unlock(dri2_dpy->gralloc1_dvc, buf->handle, &outReleaseFence);
+ } else {
+#endif
+ const gralloc_module_t *gralloc0;
+ gralloc0 = dri2_dpy->gralloc;
+
+ if (!gralloc0->lock_ycbcr) {
+ _eglLog(_EGL_WARNING, "Gralloc does not support lock_ycbcr");
+ return NULL;
+ }
+
+ ret = gralloc0->lock_ycbcr(gralloc0, buf->handle,
+ 0, 0, 0, 0, 0, &ycbcr);
+
+ if (ret) {
+ /* HACK: See droid_create_image_from_prime_fd() and
+ * https://issuetracker.google.com/32077885.*/
+ if (buf->format == HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED)
+ return NULL;
+
+ _eglLog(_EGL_WARNING, "gralloc->lock_ycbcr failed: %d", ret);
+ return NULL;
+ }
+
+ gralloc0->unlock(dri2_dpy->gralloc, buf->handle);
+#ifdef HAVE_GRALLOC1
+ }
+#endif
/* When lock_ycbcr's usage argument contains no SW_READ/WRITE flags
* it will return the .y/.cb/.cr pointers based on a NULL pointer,
@@ -822,14 +953,15 @@ droid_create_image_from_prime_fd_yuv(_EGLDisplay *disp, _EGLContext *ctx,
/* .chroma_step is the byte distance between the same chroma channel
* values of subsequent pixels, assumed to be the same for Cb and Cr. */
- fourcc = get_fourcc_yuv(buf->format, is_ycrcb, ycbcr.chroma_step);
+ fourcc = get_fourcc_yuv(format, is_ycrcb, ycbcr.chroma_step);
if (fourcc == -1) {
_eglLog(_EGL_WARNING, "unsupported YUV format, native = %x, is_ycrcb = %d, chroma_step = %d",
- buf->format, is_ycrcb, ycbcr.chroma_step);
+ format, is_ycrcb, ycbcr.chroma_step);
return NULL;
}
- if (ycbcr.chroma_step == 2) {
+ /* FIXME? we should not rely on chroma_step */
+ if (ycbcr.chroma_step == 2 || ycbcr.chroma_step == 4) {
/* Semi-planar Y + CbCr or Y + CrCb format. */
const EGLint attr_list_2plane[] = {
EGL_WIDTH, buf->width,
@@ -871,9 +1003,16 @@ static _EGLImage *
droid_create_image_from_prime_fd(_EGLDisplay *disp, _EGLContext *ctx,
struct ANativeWindowBuffer *buf, int fd)
{
+ struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
unsigned int pitch;
- if (is_yuv(buf->format)) {
+ int format = droid_resolve_format(dri2_dpy, buf);
+ if (format < 0) {
+ _eglLog(_EGL_WARNING, "Could not resolve buffer format");
+ return NULL;
+ }
+
+ if (is_yuv(format)) {
_EGLImage *image;
image = droid_create_image_from_prime_fd_yuv(disp, ctx, buf, fd);
@@ -888,13 +1027,13 @@ droid_create_image_from_prime_fd(_EGLDisplay *disp, _EGLContext *ctx,
return image;
}
- const int fourcc = get_fourcc(buf->format);
+ const int fourcc = get_fourcc(format);
if (fourcc == -1) {
_eglError(EGL_BAD_PARAMETER, "eglCreateEGLImageKHR");
return NULL;
}
- pitch = buf->stride * get_format_bpp(buf->format);
+ pitch = buf->stride * get_format_bpp(format);
if (pitch == 0) {
_eglError(EGL_BAD_PARAMETER, "eglCreateEGLImageKHR");
return NULL;
@@ -1530,6 +1669,7 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *disp)
_EGLDevice *dev;
struct dri2_egl_display *dri2_dpy;
const char *err;
+ hw_device_t *device;
int ret;
/* Not supported yet */
@@ -1547,6 +1687,27 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *disp)
err = "DRI2: failed to get gralloc module";
goto cleanup;
}
+ dri2_dpy->gralloc_version = dri2_dpy->gralloc->module_api_version;
+#ifdef HAVE_GRALLOC1
+ if (dri2_dpy->gralloc_version == HARDWARE_MODULE_API_VERSION(1, 0)) {
+ ret = dri2_dpy->gralloc->methods->open(dri2_dpy->gralloc, GRALLOC_HARDWARE_MODULE_ID, &device);
+ if (ret) {
+ err = "Failed to open hw_device device";
+ goto cleanup;
+ } else {
+ dri2_dpy->gralloc1_dvc = (gralloc1_device_t *)device;
+
+ dri2_dpy->pfn_lockflex = (GRALLOC1_PFN_LOCK_FLEX)\
+ dri2_dpy->gralloc1_dvc->getFunction(dri2_dpy->gralloc1_dvc, GRALLOC1_FUNCTION_LOCK_FLEX);
+
+ dri2_dpy->pfn_getFormat = (GRALLOC1_PFN_GET_FORMAT)\
+ dri2_dpy->gralloc1_dvc->getFunction(dri2_dpy->gralloc1_dvc, GRALLOC1_FUNCTION_GET_FORMAT);
+
+ dri2_dpy->pfn_unlock = (GRALLOC1_PFN_UNLOCK)\
+ dri2_dpy->gralloc1_dvc->getFunction(dri2_dpy->gralloc1_dvc, GRALLOC1_FUNCTION_UNLOCK);
+ }
+ }
+#endif
disp->DriverData = (void *) dri2_dpy;
diff --git a/src/egl/drivers/dri2/platform_wayland.c b/src/egl/drivers/dri2/platform_wayland.c
index c3ca1b6f7bc..3025e34ba63 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -637,10 +637,8 @@ update_buffers(struct dri2_egl_surface *dri2_surf)
struct dri2_egl_display *dri2_dpy =
dri2_egl_display(dri2_surf->base.Resource.Display);
- if (dri2_surf->base.Width != dri2_surf->wl_win->attached_width ||
- dri2_surf->base.Height != dri2_surf->wl_win->attached_height) {
-
- dri2_wl_release_buffers(dri2_surf);
+ if (dri2_surf->base.Width != dri2_surf->wl_win->width ||
+ dri2_surf->base.Height != dri2_surf->wl_win->height) {
dri2_surf->base.Width = dri2_surf->wl_win->width;
dri2_surf->base.Height = dri2_surf->wl_win->height;
@@ -648,6 +646,11 @@ update_buffers(struct dri2_egl_surface *dri2_surf)
dri2_surf->dy = dri2_surf->wl_win->dy;
}
+ if (dri2_surf->base.Width != dri2_surf->wl_win->attached_width ||
+ dri2_surf->base.Height != dri2_surf->wl_win->attached_height) {
+ dri2_wl_release_buffers(dri2_surf);
+ }
+
if (get_back_bo(dri2_surf) < 0) {
_eglError(EGL_BAD_ALLOC, "failed to allocate color buffer");
return -1;
diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c
index 6b241a524ec..318a85a4f88 100644
--- a/src/egl/main/eglcontext.c
+++ b/src/egl/main/eglcontext.c
@@ -178,9 +178,12 @@ _eglParseContextAttribList(_EGLContext *ctx, _EGLDisplay *dpy,
* is supported for OpenGL contexts, and requesting a
* forward-compatible context for OpenGL versions less than 3.0
* will generate an error."
+ *
+ * Note: since the forward-compatible flag can be set more than one way,
+ * the OpenGL version check is performed once, below.
*/
if ((val & EGL_CONTEXT_OPENGL_FORWARD_COMPATIBLE_BIT_KHR) &&
- (api != EGL_OPENGL_API || ctx->ClientMajorVersion < 3)) {
+ api != EGL_OPENGL_API) {
err = EGL_BAD_ATTRIBUTE;
break;
}
diff --git a/src/egl/main/eglcurrent.c b/src/egl/main/eglcurrent.c
index 479f231fb8f..d20ec64e654 100644
--- a/src/egl/main/eglcurrent.c
+++ b/src/egl/main/eglcurrent.c
@@ -137,13 +137,37 @@ _eglDestroyThreadInfo(_EGLThreadInfo *t)
}
+/**
+ * Delete/free a _EGLThreadInfo object.
+ */
+static void
+_eglDestroyThreadInfoCallback(_EGLThreadInfo *t)
+{
+ /* If this callback is called on thread termination then try to also give a
+ * chance to cleanup to the client drivers. If called for module termination
+ * then just release the thread information as calling eglReleaseThread
+ * would result in a deadlock.
+ */
+ if (_egl_TSDInitialized) {
+ /* The callback handler has replaced the TLS entry, which is passed in as
+ * 't', with NULL. Restore it here so that the release thread finds it in
+ * the TLS entry.
+ */
+ _eglSetTSD(t);
+ eglReleaseThread();
+ } else {
+ _eglDestroyThreadInfo(t);
+ }
+}
+
+
/**
* Make sure TSD is initialized and return current value.
*/
static inline _EGLThreadInfo *
_eglCheckedGetTSD(void)
{
- if (_eglInitTSD(&_eglDestroyThreadInfo) != EGL_TRUE) {
+ if (_eglInitTSD(&_eglDestroyThreadInfoCallback) != EGL_TRUE) {
_eglLog(_EGL_FATAL, "failed to initialize \"current\" system");
return NULL;
}
diff --git a/src/egl/main/egldevice.c b/src/egl/main/egldevice.c
index 4878039be0e..c5c9a21273a 100644
--- a/src/egl/main/egldevice.c
+++ b/src/egl/main/egldevice.c
@@ -202,18 +202,6 @@ _eglDeviceSupports(_EGLDevice *dev, _EGLDeviceExtension ext)
};
}
-/* Ideally we'll have an extension which passes the render node,
- * instead of the card one + magic.
- *
- * Then we can move this in _eglQueryDeviceStringEXT below. Until then
- * keep it separate.
- */
-const char *
-_eglGetDRMDeviceRenderNode(_EGLDevice *dev)
-{
- return dev->device->nodes[DRM_NODE_RENDER];
-}
-
EGLBoolean
_eglQueryDeviceAttribEXT(_EGLDevice *dev, EGLint attribute,
EGLAttrib *value)
diff --git a/src/egl/main/egldevice.h b/src/egl/main/egldevice.h
index 83a47d5eacc..883f96f8e30 100644
--- a/src/egl/main/egldevice.h
+++ b/src/egl/main/egldevice.h
@@ -68,9 +68,6 @@ typedef enum _egl_device_extension _EGLDeviceExtension;
EGLBoolean
_eglDeviceSupports(_EGLDevice *dev, _EGLDeviceExtension ext);
-const char *
-_eglGetDRMDeviceRenderNode(_EGLDevice *dev);
-
EGLBoolean
_eglQueryDeviceAttribEXT(_EGLDevice *dev, EGLint attribute,
EGLAttrib *value);
diff --git a/src/egl/meson.build b/src/egl/meson.build
index a23cc36fc2b..b7ff09e9fed 100644
--- a/src/egl/meson.build
+++ b/src/egl/meson.build
@@ -93,10 +93,11 @@ if with_dri2
'drivers/dri2/egl_dri2.h',
'drivers/dri2/egl_dri2_fallbacks.h',
)
+ link_for_egl += [libloader, libxmlconfig]
+ incs_for_egl += inc_loader
if with_platform_x11
files_egl += files('drivers/dri2/platform_x11.c')
- incs_for_egl += inc_loader
if with_dri3
files_egl += files('drivers/dri2/platform_x11_dri3.c')
link_for_egl += libloader_dri3_helper
@@ -105,13 +106,12 @@ if with_dri2
endif
if with_platform_drm
files_egl += files('drivers/dri2/platform_drm.c')
- link_for_egl += [libloader, libgbm, libxmlconfig]
- incs_for_egl += [inc_loader, inc_gbm, include_directories('../gbm/main')]
+ link_for_egl += libgbm
+ incs_for_egl += [inc_gbm, include_directories('../gbm/main')]
deps_for_egl += dep_libdrm
endif
if with_platform_surfaceless
files_egl += files('drivers/dri2/platform_surfaceless.c')
- incs_for_egl += [inc_loader]
endif
if with_platform_wayland
deps_for_egl += [dep_wayland_client, dep_wayland_server, dep_wayland_egl_headers]
@@ -127,7 +127,6 @@ if with_dri2
if with_platform_android
deps_for_egl += dep_android
files_egl += files('drivers/dri2/platform_android.c')
- incs_for_egl += [inc_loader]
endif
elif with_platform_haiku
incs_for_egl += inc_haikugl
@@ -166,7 +165,7 @@ libegl = shared_library(
'-D_EGL_NATIVE_PLATFORM=_EGL_PLATFORM_@0@'.format(egl_native_platform.to_upper()),
],
include_directories : incs_for_egl,
- link_with : [link_for_egl, libloader, libxmlconfig, libglapi, libmesa_util],
+ link_with : [link_for_egl, libglapi, libmesa_util],
link_args : [ld_args_bsymbolic, ld_args_gc_sections],
dependencies : [deps_for_egl, dep_dl, dep_libdrm, dep_clock, dep_thread],
install : true,
diff --git a/src/freedreno/Makefile.am b/src/freedreno/Makefile.am
index 460fb87fb46..342f03d644c 100644
--- a/src/freedreno/Makefile.am
+++ b/src/freedreno/Makefile.am
@@ -45,6 +45,7 @@ TESTS =
BUILT_SOURCES =
CLEANFILES =
EXTRA_DIST = \
+ meson.build \
drm/meson.build \
ir3/ir3_nir_trig.py \
ir3/meson.build
diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index d9fcf798b3d..68926c9553b 100644
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -97,7 +97,7 @@ ir3_optimize_loop(nir_shader *s)
progress |= OPT(s, nir_opt_gcm, true);
else if (gcm == 2)
progress |= OPT(s, nir_opt_gcm, false);
- progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
+ progress |= OPT(s, nir_opt_peephole_select, 16, true);
progress |= OPT(s, nir_opt_intrinsics);
progress |= OPT(s, nir_opt_algebraic);
progress |= OPT(s, nir_opt_constant_folding);
diff --git a/src/gallium/auxiliary/Android.mk b/src/gallium/auxiliary/Android.mk
index 7618c6fcd93..fe976501451 100644
--- a/src/gallium/auxiliary/Android.mk
+++ b/src/gallium/auxiliary/Android.mk
@@ -32,8 +32,11 @@ LOCAL_SRC_FILES := \
$(C_SOURCES) \
$(NIR_SOURCES) \
$(RENDERONLY_SOURCES) \
- $(VL_STUB_SOURCES) \
- util/u_debug_stack_android.cpp
+ $(VL_STUB_SOURCES)
+
+ifeq ($(USE_LIBBACKTRACE),true)
+ LOCAL_SRC_FILES += util/u_debug_stack_android.cpp
+endif
LOCAL_C_INCLUDES := \
$(GALLIUM_TOP)/auxiliary/util \
diff --git a/src/gallium/auxiliary/draw/draw_context.c b/src/gallium/auxiliary/draw/draw_context.c
index 3fc096789c0..f8c69585e6a 100644
--- a/src/gallium/auxiliary/draw/draw_context.c
+++ b/src/gallium/auxiliary/draw/draw_context.c
@@ -950,6 +950,8 @@ draw_set_mapped_so_targets(struct draw_context *draw,
{
int i;
+ draw_do_flush( draw, DRAW_FLUSH_STATE_CHANGE );
+
for (i = 0; i < num_targets; i++)
draw->so.targets[i] = targets[i];
for (i = num_targets; i < PIPE_MAX_SO_BUFFERS; i++)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
index fcbdd5050fe..f307c26d4f7 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
@@ -556,11 +556,11 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
llvm::SmallVector MAttrs;
-#if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
-#if HAVE_LLVM >= 0x0400
- /* llvm-3.7+ implements sys::getHostCPUFeatures for x86,
- * which allows us to enable/disable code generation based
- * on the results of cpuid.
+#if HAVE_LLVM >= 0x0400 && (defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) || defined(PIPE_ARCH_ARM))
+ /* llvm-3.3+ implements sys::getHostCPUFeatures for Arm
+ * and llvm-3.7+ for x86, which allows us to enable/disable
+ * code generation based on the results of cpuid on these
+ * architectures.
*/
llvm::StringMap features;
llvm::sys::getHostCPUFeatures(features);
@@ -570,7 +570,7 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
++f) {
MAttrs.push_back(((*f).second ? "+" : "-") + (*f).first().str());
}
-#else
+#elif defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
/*
* We need to unset attributes because sometimes LLVM mistakenly assumes
* certain features are present given the processor name.
@@ -625,6 +625,12 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
MAttrs.push_back("-avx512vl");
#endif
#endif
+#if defined(PIPE_ARCH_ARM)
+ if (!util_cpu_caps.has_neon) {
+ MAttrs.push_back("-neon");
+ MAttrs.push_back("-crypto");
+ MAttrs.push_back("-vfp2");
+ }
#endif
#if defined(PIPE_ARCH_PPC)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index 0f5b3d9acb7..d6af1d84471 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -1108,7 +1108,7 @@ get_indirect_index(struct lp_build_tgsi_soa_context *bld,
* larger than the declared size but smaller than the buffer size.
*/
if (reg_file != TGSI_FILE_CONSTANT) {
- assert(index_limit > 0);
+ assert(index_limit >= 0);
max_index = lp_build_const_int_vec(bld->bld_base.base.gallivm,
uint_bld->type, index_limit);
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.h b/src/gallium/auxiliary/tgsi/tgsi_scan.h
index 64f2598a259..09eac4da95a 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.h
@@ -220,7 +220,9 @@ tgsi_is_bindless_image_file(unsigned file)
{
return file != TGSI_FILE_IMAGE &&
file != TGSI_FILE_MEMORY &&
- file != TGSI_FILE_BUFFER;
+ file != TGSI_FILE_BUFFER &&
+ file != TGSI_FILE_CONSTBUF &&
+ file != TGSI_FILE_HW_ATOMIC;
}
#ifdef __cplusplus
diff --git a/src/gallium/auxiliary/util/u_threaded_context.c b/src/gallium/auxiliary/util/u_threaded_context.c
index 8e3bceae18d..b596c322918 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.c
+++ b/src/gallium/auxiliary/util/u_threaded_context.c
@@ -1524,7 +1524,8 @@ tc_buffer_do_flush_region(struct threaded_context *tc,
if (ttrans->staging) {
struct pipe_box src_box;
- u_box_1d(ttrans->offset + box->x % tc->map_buffer_alignment,
+ u_box_1d(ttrans->offset + ttrans->b.box.x % tc->map_buffer_alignment +
+ (box->x - ttrans->b.box.x),
box->width, &src_box);
/* Copy the staging buffer into the original one. */
diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst
index eaf492ce8b0..b927d014179 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -487,6 +487,10 @@ The integer capabilities:
* ``PIPE_CAP_DEST_SURFACE_SRGB_CONTROL``: Indicates whether the drivers
supports switching the format between sRGB and linear for a surface that is
used as destination in draw and blit calls.
+* ``PIPE_CAP_MAX_VARYINGS``: The maximum number of fragment shader
+ varyings. This will generally correspond to
+ ``PIPE_SHADER_CAP_MAX_INPUTS`` for the fragment shader, but in some
+ cases may be a smaller number.
.. _pipe_capf:
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index fd320232528..35dcac1409b 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -360,6 +360,9 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
return 0;
+ case PIPE_CAP_MAX_VARYINGS:
+ return screen->specs.max_varyings;
+
case PIPE_CAP_PCI_GROUP:
case PIPE_CAP_PCI_BUS:
case PIPE_CAP_PCI_DEVICE:
diff --git a/src/gallium/drivers/freedreno/Makefile.am b/src/gallium/drivers/freedreno/Makefile.am
index fe409fa5f52..dbc15f40389 100644
--- a/src/gallium/drivers/freedreno/Makefile.am
+++ b/src/gallium/drivers/freedreno/Makefile.am
@@ -23,4 +23,6 @@ libfreedreno_la_SOURCES = \
$(a6xx_SOURCES) \
$(ir3_SOURCES)
-EXTRA_DIST = meson.build
+EXTRA_DIST = \
+ ir3/ir3_cmdline.c \
+ meson.build
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_draw.c b/src/gallium/drivers/freedreno/a2xx/fd2_draw.c
index 772127c7478..498c1eae1d7 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_draw.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_draw.c
@@ -339,7 +339,6 @@ clear_fast(struct fd_batch *batch, struct fd_ringbuffer *ring,
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_SCREEN_SCISSOR_BR));
OUT_RINGP(ring, patch_type, &batch->gmem_patches);
- OUT_RING(ring, 0);
OUT_PKT3(ring, CP_SET_CONSTANT, 4);
OUT_RING(ring, CP_REG(REG_A2XX_RB_SURFACE_INFO));
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
index 1c073e31739..692188ebd4e 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
@@ -59,6 +59,28 @@ static uint32_t fmt2swap(enum pipe_format format)
}
}
+static bool
+use_hw_binning(struct fd_batch *batch)
+{
+ struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+
+ /* we hardcoded a limit of 8 "pipes", we can increase this limit
+ * at the cost of a slightly larger command stream
+ * however very few cases will need more than 8
+ * gmem->num_vsc_pipes == 0 means empty batch (TODO: does it still happen?)
+ */
+ if (gmem->num_vsc_pipes > 8 || !gmem->num_vsc_pipes)
+ return false;
+
+ /* only a20x hw binning is implement
+ * a22x is more like a3xx, but perhaps the a20x works? (TODO)
+ */
+ if (!is_a20x(batch->ctx->screen))
+ return false;
+
+ return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
+}
+
/* transfer from gmem to system memory (ie. normal RAM) */
static void
@@ -272,7 +294,7 @@ fd2_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
y0 = ((float)tile->yoff) / ((float)pfb->height);
y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
- OUT_PKT3(ring, CP_MEM_WRITE, 9);
+ OUT_PKT3(ring, CP_MEM_WRITE, 7);
OUT_RELOC(ring, fd_resource(fd2_ctx->solid_vertexbuf)->bo, 36, 0, 0);
OUT_RING(ring, fui(x0));
OUT_RING(ring, fui(y0));
@@ -280,8 +302,6 @@ fd2_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
OUT_RING(ring, fui(y0));
OUT_RING(ring, fui(x0));
OUT_RING(ring, fui(y1));
- OUT_RING(ring, fui(x1));
- OUT_RING(ring, fui(y1));
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
@@ -492,18 +512,18 @@ fd2_emit_tile_init(struct fd_batch *batch)
/* note: 1 "line" is 512 bytes in both color/depth areas (1K total) */
switch (patch->val) {
case GMEM_PATCH_FASTCLEAR_COLOR:
- size = align(gmem->bin_w * gmem->bin_h * color_size, 0x4000);
+ size = align(gmem->bin_w * gmem->bin_h * color_size, 0x8000);
lines = size / 1024;
depth_base = size / 2;
break;
case GMEM_PATCH_FASTCLEAR_DEPTH:
- size = align(gmem->bin_w * gmem->bin_h * depth_size, 0x4000);
+ size = align(gmem->bin_w * gmem->bin_h * depth_size, 0x8000);
lines = size / 1024;
color_base = depth_base;
depth_base = depth_base + size / 2;
break;
case GMEM_PATCH_FASTCLEAR_COLOR_DEPTH:
- lines = align(gmem->bin_w * gmem->bin_h * color_size * 2, 0x4000) / 1024;
+ lines = align(gmem->bin_w * gmem->bin_h * color_size * 2, 0x8000) / 1024;
break;
case GMEM_PATCH_RESTORE_INFO:
patch->cs[0] = gmem->bin_w;
@@ -535,7 +555,7 @@ fd2_emit_tile_init(struct fd_batch *batch)
OUT_RING(ring, CP_REG(REG_A2XX_VGT_CURRENT_BIN_ID_MAX));
OUT_RING(ring, 0);
- if (is_a20x(ctx->screen) && fd_binning_enabled && gmem->num_vsc_pipes) {
+ if (use_hw_binning(batch)) {
/* patch out unneeded memory exports by changing EXEC CF to EXEC_END
*
* in the shader compiler, we guarantee that the shader ends with
@@ -694,7 +714,7 @@ fd2_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
OUT_RING(ring, fui(0.0f));
}
- if (is_a20x(ctx->screen) && fd_binning_enabled) {
+ if (use_hw_binning(batch)) {
struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_resource.c b/src/gallium/drivers/freedreno/a2xx/fd2_resource.c
index 1bd1f103ccd..2c813804689 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_resource.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_resource.c
@@ -55,6 +55,12 @@ fd2_setup_slices(struct fd_resource *rsc)
break;
}
+ /* mipmaps have power of two sizes in memory */
+ if (level) {
+ width = util_next_power_of_two(width);
+ height = util_next_power_of_two(height);
+ }
+
slice->pitch = width;
slice->offset = size;
diff --git a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c
index 5d92f86befc..b206911270a 100644
--- a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c
+++ b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c
@@ -74,7 +74,7 @@ ir2_optimize_loop(nir_shader *s)
progress |= OPT(s, nir_opt_dce);
progress |= OPT(s, nir_opt_cse);
/* progress |= OPT(s, nir_opt_gcm, true); */
- progress |= OPT(s, nir_opt_peephole_select, UINT_MAX, true, true);
+ progress |= OPT(s, nir_opt_peephole_select, UINT_MAX, true);
progress |= OPT(s, nir_opt_intrinsics);
progress |= OPT(s, nir_opt_algebraic);
progress |= OPT(s, nir_opt_constant_folding);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
index 460255f748a..c8719636182 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
@@ -438,7 +438,7 @@ emit_blit_texture(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(dfmt) |
A6XX_RB_2D_DST_INFO_TILE_MODE(dtile) |
A6XX_RB_2D_DST_INFO_COLOR_SWAP(dswap));
- OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
+ OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(dpitch));
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c b/src/gallium/drivers/freedreno/freedreno_resource.c
index ce8e4480be1..1879d2c60ed 100644
--- a/src/gallium/drivers/freedreno/freedreno_resource.c
+++ b/src/gallium/drivers/freedreno/freedreno_resource.c
@@ -853,7 +853,13 @@ fd_resource_create_with_modifiers(struct pipe_screen *pscreen,
enum pipe_format format = tmpl->format;
uint32_t size;
- if (screen->ro && (tmpl->bind & PIPE_BIND_SCANOUT)) {
+ /* when using kmsro, scanout buffers are allocated on the display device
+ * create_with_modifiers() doesn't give us usage flags, so we have to
+ * assume that all calls with modifiers are scanout-possible
+ */
+ if (screen->ro &&
+ ((tmpl->bind & PIPE_BIND_SCANOUT) ||
+ !(count == 1 && modifiers[0] == DRM_FORMAT_MOD_INVALID))) {
struct pipe_resource scanout_templat = *tmpl;
struct renderonly_scanout *scanout;
struct winsys_handle handle;
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index e596a4e8462..c3b08ab0e0f 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -317,6 +317,9 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_VIEWPORTS:
return 1;
+ case PIPE_CAP_MAX_VARYINGS:
+ return 16;
+
case PIPE_CAP_SHAREABLE_SHADERS:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
/* manage the variants for these ourself, to avoid breaking precompile: */
diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c
index a7b4a43c015..78707c66e62 100644
--- a/src/gallium/drivers/i915/i915_screen.c
+++ b/src/gallium/drivers/i915/i915_screen.c
@@ -402,6 +402,8 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
return 0;
case PIPE_CAP_ENDIANNESS:
return PIPE_ENDIAN_LITTLE;
+ case PIPE_CAP_MAX_VARYINGS:
+ return 10;
case PIPE_CAP_VENDOR_ID:
return 0x8086;
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c
index c95016a6cbe..b55b4a3c4fe 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -310,6 +310,8 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
return 1;
case PIPE_CAP_CLEAR_TEXTURE:
return 1;
+ case PIPE_CAP_MAX_VARYINGS:
+ return 32;
case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
diff --git a/src/gallium/drivers/nouveau/codegen/lib/gk104.asm b/src/gallium/drivers/nouveau/codegen/lib/gk104.asm
index cd65b547279..576da1bab60 100644
--- a/src/gallium/drivers/nouveau/codegen/lib/gk104.asm
+++ b/src/gallium/drivers/nouveau/codegen/lib/gk104.asm
@@ -543,6 +543,8 @@ $p2 suldgb b32 $r3 cg zero u8 g[$r4d] $r2 $p0
$p1 suldgb b32 $r3 cv zero u8 g[$r4d] $r2 $p0
long mov b32 $r3 0x3f800000
long nop
+sched 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+long nop
long ret
@@ -554,7 +556,144 @@ long ret
// SIZE: 9 * 8 bytes
//
gk104_rcp_f64:
- long nop
+ // Step 1: classify input according to exponent and value, and calculate
+ // result for 0/inf/nan. $r2 holds the exponent value, which starts at
+ // bit 52 (bit 20 of the upper half) and is 11 bits in length
+ ext u32 $r2 $r1 0xb14
+ add b32 $r3 $r2 0xffffffff
+ joinat #rcp_rejoin
+ // We want to check whether the exponent is 0 or 0x7ff (i.e. NaN, inf,
+ // denorm, or 0). Do this by substracting 1 from the exponent, which will
+ // mean that it's > 0x7fd in those cases when doing unsigned comparison
+ set $p0 0x1 gt u32 $r3 0x7fd
+ // $r3: 0 for norms, 0x36 for denorms, -1 for others
+ long mov b32 $r3 0x0
+ sched 0x2f 0x04 0x2d 0x2b 0x2f 0x28 0x28
+ join (not $p0) nop
+ // Process all special values: NaN, inf, denorm, 0
+ mov b32 $r3 0xffffffff
+ // A number is NaN if its abs value is greater than or unordered with inf
+ set $p0 0x1 gtu f64 abs $r0d 0x7ff0000000000000
+ (not $p0) bra #rcp_inf_or_denorm_or_zero
+ // NaN -> NaN, the next line sets the "quiet" bit of the result. This
+ // behavior is both seen on the CPU and the blob
+ join or b32 $r1 $r1 0x80000
+rcp_inf_or_denorm_or_zero:
+ and b32 $r4 $r1 0x7ff00000
+ // Other values with nonzero in exponent field should be inf
+ set $p0 0x1 eq s32 $r4 0x0
+ sched 0x2b 0x04 0x2f 0x2d 0x2b 0x2f 0x20
+ $p0 bra #rcp_denorm_or_zero
+ // +/-Inf -> +/-0
+ xor b32 $r1 $r1 0x7ff00000
+ join mov b32 $r0 0x0
+rcp_denorm_or_zero:
+ set $p0 0x1 gtu f64 abs $r0d 0x0
+ $p0 bra #rcp_denorm
+ // +/-0 -> +/-Inf
+ join or b32 $r1 $r1 0x7ff00000
+rcp_denorm:
+ // non-0 denorms: multiply with 2^54 (the 0x36 in $r3), join with norms
+ mul rn f64 $r0d $r0d 0x4350000000000000
+ sched 0x2f 0x28 0x2b 0x28 0x28 0x04 0x28
+ join mov b32 $r3 0x36
+rcp_rejoin:
+ // All numbers with -1 in $r3 have their result ready in $r0d, return them
+ // others need further calculation
+ set $p0 0x1 lt s32 $r3 0x0
+ $p0 bra #rcp_end
+ // Step 2: Before the real calculation goes on, renormalize the values to
+ // range [1, 2) by setting exponent field to 0x3ff (the exponent of 1)
+ // result in $r6d. The exponent will be recovered later.
+ ext u32 $r2 $r1 0xb14
+ and b32 $r7 $r1 0x800fffff
+ add b32 $r7 $r7 0x3ff00000
+ long mov b32 $r6 $r0
+ sched 0x2b 0x04 0x28 0x28 0x2a 0x2b 0x2e
+ // Step 3: Convert new value to float (no overflow will occur due to step
+ // 2), calculate rcp and do newton-raphson step once
+ cvt rz f32 $r5 f64 $r6d
+ long rcp f32 $r4 $r5
+ mov b32 $r0 0xbf800000
+ fma rn f32 $r5 $r4 $r5 $r0
+ fma rn f32 $r0 neg $r4 $r5 $r4
+ // Step 4: convert result $r0 back to double, do newton-raphson steps
+ cvt f64 $r0d f32 $r0
+ cvt f64 $r6d neg f64 $r6d
+ sched 0x2e 0x29 0x29 0x29 0x29 0x29 0x29
+ cvt f64 $r8d f32 0x3f800000
+ // 4 Newton-Raphson Steps, tmp in $r4d, result in $r0d
+ // The formula used here (and above) is:
+ // RCP_{n + 1} = 2 * RCP_{n} - x * RCP_{n} * RCP_{n}
+ // The following code uses 2 FMAs for each step, and it will basically
+ // looks like:
+ // tmp = -src * RCP_{n} + 1
+ // RCP_{n + 1} = RCP_{n} * tmp + RCP_{n}
+ fma rn f64 $r4d $r6d $r0d $r8d
+ fma rn f64 $r0d $r0d $r4d $r0d
+ fma rn f64 $r4d $r6d $r0d $r8d
+ fma rn f64 $r0d $r0d $r4d $r0d
+ fma rn f64 $r4d $r6d $r0d $r8d
+ fma rn f64 $r0d $r0d $r4d $r0d
+ sched 0x29 0x20 0x28 0x28 0x28 0x28 0x28
+ fma rn f64 $r4d $r6d $r0d $r8d
+ fma rn f64 $r0d $r0d $r4d $r0d
+ // Step 5: Exponent recovery and final processing
+ // The exponent is recovered by adding what we added to the exponent.
+ // Suppose we want to calculate rcp(x), but we have rcp(cx), then
+ // rcp(x) = c * rcp(cx)
+ // The delta in exponent comes from two sources:
+ // 1) The renormalization in step 2. The delta is:
+ // 0x3ff - $r2
+ // 2) (For the denorm input) The 2^54 we multiplied at rcp_denorm, stored
+ // in $r3
+ // These 2 sources are calculated in the first two lines below, and then
+ // added to the exponent extracted from the result above.
+ // Note that after processing, the new exponent may >= 0x7ff (inf)
+ // or <= 0 (denorm). Those cases will be handled respectively below
+ subr b32 $r2 $r2 0x3ff
+ long add b32 $r4 $r2 $r3
+ ext u32 $r3 $r1 0xb14
+ // New exponent in $r3
+ long add b32 $r3 $r3 $r4
+ add b32 $r2 $r3 0xffffffff
+ sched 0x28 0x2b 0x28 0x2b 0x28 0x28 0x2b
+ // (exponent-1) < 0x7fe (unsigned) means the result is in norm range
+ // (same logic as in step 1)
+ set $p0 0x1 lt u32 $r2 0x7fe
+ (not $p0) bra #rcp_result_inf_or_denorm
+ // Norms: convert exponents back and return
+ shl b32 $r4 $r4 clamp 0x14
+ long add b32 $r1 $r4 $r1
+ bra #rcp_end
+rcp_result_inf_or_denorm:
+ // New exponent >= 0x7ff means that result is inf
+ set $p0 0x1 ge s32 $r3 0x7ff
+ (not $p0) bra #rcp_result_denorm
+ sched 0x20 0x25 0x28 0x2b 0x23 0x25 0x2f
+ // Infinity
+ and b32 $r1 $r1 0x80000000
+ long mov b32 $r0 0x0
+ add b32 $r1 $r1 0x7ff00000
+ bra #rcp_end
+rcp_result_denorm:
+ // Denorm result comes from huge input. The greatest possible fp64, i.e.
+ // 0x7fefffffffffffff's rcp is 0x0004000000000000, 1/4 of the smallest
+ // normal value. Other rcp result should be greater than that. If we
+ // set the exponent field to 1, we can recover the result by multiplying
+ // it with 1/2 or 1/4. 1/2 is used if the "exponent" $r3 is 0, otherwise
+ // 1/4 ($r3 should be -1 then). This is quite tricky but greatly simplifies
+ // the logic here.
+ set $p0 0x1 ne u32 $r3 0x0
+ and b32 $r1 $r1 0x800fffff
+ // 0x3e800000: 1/4
+ $p0 cvt f64 $r6d f32 0x3e800000
+ sched 0x2f 0x28 0x2c 0x2e 0x2a 0x20 0x27
+ // 0x3f000000: 1/2
+ (not $p0) cvt f64 $r6d f32 0x3f000000
+ add b32 $r1 $r1 0x00100000
+ mul rn f64 $r0d $r0d $r6d
+rcp_end:
long ret
// RSQ F64: Newton Raphson rsqrt(x): r_{i+1} = r_i * (1.5 - 0.5 * x * r_i * r_i)
@@ -565,7 +704,67 @@ gk104_rcp_f64:
// SIZE: 14 * 8 bytes
//
gk104_rsq_f64:
- long nop
+ // Before getting initial result rsqrt64h, two special cases should be
+ // handled first.
+ // 1. NaN: set the highest bit in mantissa so it'll be surely recognized
+ // as NaN in rsqrt64h
+ set $p0 0x1 gtu f64 abs $r0d 0x7ff0000000000000
+ $p0 or b32 $r1 $r1 0x00080000
+ and b32 $r2 $r1 0x7fffffff
+ sched 0x27 0x20 0x28 0x2c 0x25 0x28 0x28
+ // 2. denorms and small normal values: using their original value will
+ // lose precision either at rsqrt64h or the first step in newton-raphson
+ // steps below. Take 2 as a threshold in exponent field, and multiply
+ // with 2^54 if the exponent is smaller or equal. (will multiply 2^27
+ // to recover in the end)
+ ext u32 $r3 $r1 0xb14
+ set $p1 0x1 le u32 $r3 0x2
+ long or b32 $r2 $r0 $r2
+ $p1 mul rn f64 $r0d $r0d 0x4350000000000000
+ rsqrt64h $r5 $r1
+ // rsqrt64h will give correct result for 0/inf/nan, the following logic
+ // checks whether the input is one of those (exponent is 0x7ff or all 0
+ // except for the sign bit)
+ set b32 $r6 ne u32 $r3 0x7ff
+ long and b32 $r2 $r2 $r6
+ sched 0x28 0x2b 0x20 0x27 0x28 0x2e 0x28
+ set $p0 0x1 ne u32 $r2 0x0
+ $p0 bra #rsq_norm
+ // For 0/inf/nan, make sure the sign bit agrees with input and return
+ and b32 $r1 $r1 0x80000000
+ long mov b32 $r0 0x0
+ long or b32 $r1 $r1 $r5
+ long ret
+rsq_norm:
+ // For others, do 4 Newton-Raphson steps with the formula:
+ // RSQ_{n + 1} = RSQ_{n} * (1.5 - 0.5 * x * RSQ_{n} * RSQ_{n})
+ // In the code below, each step is written as:
+ // tmp1 = 0.5 * x * RSQ_{n}
+ // tmp2 = -RSQ_{n} * tmp1 + 0.5
+ // RSQ_{n + 1} = RSQ_{n} * tmp2 + RSQ_{n}
+ long mov b32 $r4 0x0
+ sched 0x2f 0x29 0x29 0x29 0x29 0x29 0x29
+ // 0x3f000000: 1/2
+ cvt f64 $r8d f32 0x3f000000
+ mul rn f64 $r2d $r0d $r8d
+ mul rn f64 $r0d $r2d $r4d
+ fma rn f64 $r6d neg $r4d $r0d $r8d
+ fma rn f64 $r4d $r4d $r6d $r4d
+ mul rn f64 $r0d $r2d $r4d
+ fma rn f64 $r6d neg $r4d $r0d $r8d
+ sched 0x29 0x29 0x29 0x29 0x29 0x29 0x29
+ fma rn f64 $r4d $r4d $r6d $r4d
+ mul rn f64 $r0d $r2d $r4d
+ fma rn f64 $r6d neg $r4d $r0d $r8d
+ fma rn f64 $r4d $r4d $r6d $r4d
+ mul rn f64 $r0d $r2d $r4d
+ fma rn f64 $r6d neg $r4d $r0d $r8d
+ fma rn f64 $r4d $r4d $r6d $r4d
+ sched 0x29 0x20 0x28 0x2e 0x00 0x00 0x00
+ // Multiply 2^27 to result for small inputs to recover
+ $p1 mul rn f64 $r4d $r4d 0x41a0000000000000
+ long mov b32 $r1 $r5
+ long mov b32 $r0 $r4
long ret
//
diff --git a/src/gallium/drivers/nouveau/codegen/lib/gk104.asm.h b/src/gallium/drivers/nouveau/codegen/lib/gk104.asm.h
index 37998768efe..ed948dee471 100644
--- a/src/gallium/drivers/nouveau/codegen/lib/gk104.asm.h
+++ b/src/gallium/drivers/nouveau/codegen/lib/gk104.asm.h
@@ -481,12 +481,132 @@ uint64_t gk104_builtin_code[] = {
0xd40040000840c785,
0x18fe00000000dde2,
0x4000000000001de4,
- 0x9000000000001de7,
-/* 0x0f08: gk104_rcp_f64 */
+ 0x2000000000000007,
0x4000000000001de4,
0x9000000000001de7,
-/* 0x0f18: gk104_rsq_f64 */
- 0x4000000000001de4,
+/* 0x0f18: gk104_rcp_f64 */
+ 0x7000c02c50109c03,
+ 0x0bfffffffc20dc02,
+ 0x6000000280000007,
+ 0x1a0ec01ff431dc03,
+ 0x180000000000dde2,
+ 0x228282f2b2d042f7,
+ 0x40000000000021f4,
+ 0x1bfffffffc00dde2,
+ 0x1e0edffc0001dc81,
+ 0x40000000200021e7,
+ 0x3800200000105c52,
+/* 0x0f70: rcp_inf_or_denorm_or_zero */
+ 0x39ffc00000111c02,
+ 0x190e0000fc41dc23,
+ 0x2202f2b2d2f042b7,
+ 0x40000000400001e7,
+ 0x39ffc00000105c82,
+ 0x1800000000001df2,
+/* 0x0fa0: rcp_denorm_or_zero */
+ 0x1e0ec0000001dc81,
+ 0x40000000200001e7,
+ 0x39ffc00000105c52,
+/* 0x0fb8: rcp_denorm */
+ 0x5000d0d400001c01,
+ 0x2280428282b282f7,
+ 0x18000000d800ddf2,
+/* 0x0fd0: rcp_rejoin */
+ 0x188e0000fc31dc23,
+ 0x40000006000001e7,
+ 0x7000c02c50109c03,
+ 0x3a003ffffc11dc02,
+ 0x08ffc0000071dc02,
+ 0x2800000000019de4,
+ 0x22e2b2a2828042b7,
+ 0x1006000019a15c04,
+ 0xc800000010511c00,
+ 0x1afe000000001de2,
+ 0x3000000014415c00,
+ 0x3008000014401e00,
+ 0x1000000001301c04,
+ 0x1000000019b19d04,
+ 0x22929292929292e7,
+ 0x1000cfe001321c04,
+ 0x2010000000611c01,
+ 0x2000000010001c01,
+ 0x2010000000611c01,
+ 0x2000000010001c01,
+ 0x2010000000611c01,
+ 0x2000000010001c01,
+ 0x2282828282820297,
+ 0x2010000000611c01,
+ 0x2000000010001c01,
+ 0x0800000ffc209e02,
+ 0x480000000c211c03,
+ 0x7000c02c5010dc03,
+ 0x480000001030dc03,
+ 0x0bfffffffc309c02,
+ 0x22b28282b282b287,
+ 0x188ec01ff821dc03,
+ 0x40000000600021e7,
+ 0x6000c00050411c03,
+ 0x4800000004405c03,
+ 0x40000001c0001de7,
+/* 0x10f0: rcp_result_inf_or_denorm */
+ 0x1b0ec01ffc31dc23,
+ 0x40000000a00021e7,
+ 0x22f25232b2825207,
+ 0x3a00000000105c02,
+ 0x1800000000001de2,
+ 0x09ffc00000105c02,
+ 0x40000000e0001de7,
+/* 0x1128: rcp_result_denorm */
+ 0x1a8e0000fc31dc03,
+ 0x3a003ffffc105c02,
+ 0x1000cfa001318004,
+ 0x227202a2e2c282f7,
+ 0x1000cfc00131a004,
+ 0x0800400000105c02,
+ 0x5000000018001c01,
+/* 0x1160: rcp_end */
+ 0x9000000000001de7,
+/* 0x1168: gk104_rsq_f64 */
+ 0x1e0edffc0001dc81,
+ 0x3800200000104042,
+ 0x39fffffffc109c02,
+ 0x22828252c2820277,
+ 0x7000c02c5010dc03,
+ 0x198ec0000833dc03,
+ 0x6800000008009c43,
+ 0x5000d0d400000401,
+ 0xc80000001c115c00,
+ 0x128ec01ffc319c03,
+ 0x6800000018209c03,
+ 0x2282e2827202b287,
+ 0x1a8e0000fc21dc03,
+ 0x40000000800001e7,
+ 0x3a00000000105c02,
+ 0x1800000000001de2,
+ 0x6800000014105c43,
+ 0x9000000000001de7,
+/* 0x11f8: rsq_norm */
+ 0x1800000000011de2,
+ 0x22929292929292f7,
+ 0x1000cfc001321c04,
+ 0x5000000020009c01,
+ 0x5000000010201c01,
+ 0x2010000000419e01,
+ 0x2008000018411c01,
+ 0x5000000010201c01,
+ 0x2010000000419e01,
+ 0x2292929292929297,
+ 0x2008000018411c01,
+ 0x5000000010201c01,
+ 0x2010000000419e01,
+ 0x2008000018411c01,
+ 0x5000000010201c01,
+ 0x2010000000419e01,
+ 0x2008000018411c01,
+ 0x20000002e2820297,
+ 0x5000d06800410401,
+ 0x2800000014005de4,
+ 0x2800000010001de4,
0x9000000000001de7,
0xc800000003f01cc5,
0x2c00000100005c04,
@@ -495,7 +615,7 @@ uint64_t gk104_builtin_code[] = {
0x680100000c1fdc03,
0x4000000a60001c47,
0x180000004000dde2,
-/* 0x0f60: spill_cfstack */
+/* 0x12e0: spill_cfstack */
0x78000009c0000007,
0x0c0000000430dd02,
0x4003ffffa0001ca7,
@@ -543,14 +663,14 @@ uint64_t gk104_builtin_code[] = {
0x4000000100001ea7,
0x480100000c001c03,
0x0800000000105c42,
-/* 0x10d8: shared_loop */
+/* 0x1458: shared_loop */
0xc100000000309c85,
0x9400000500009c85,
0x0c00000010001d02,
0x0800000000105d42,
0x0c0000001030dd02,
0x4003ffff40001ca7,
-/* 0x1108: shared_done */
+/* 0x1488: shared_done */
0x2800406420001de4,
0x2800406430005de4,
0xe000000000001c45,
@@ -564,7 +684,7 @@ uint64_t gk104_builtin_code[] = {
0x480000000c209c03,
0x4801000008001c03,
0x0800000000105c42,
-/* 0x1170: search_cstack */
+/* 0x14f0: search_cstack */
0x280040646000dde4,
0x8400000020009f05,
0x190ec0002821dc03,
@@ -573,17 +693,17 @@ uint64_t gk104_builtin_code[] = {
0x0800000000105c42,
0x0c0000004030dd02,
0x00029dff0ffc5cbf,
-/* 0x11b0: entry_found */
+/* 0x1530: entry_found */
0x8400000000009f85,
0x2800406400001de4,
0x2800406410005de4,
0x9400000010009c85,
0x4000000000001df4,
-/* 0x11d8: end_exit */
+/* 0x1558: end_exit */
0x9800000003ffdcc5,
0xd000000000008007,
0xa000000000004007,
-/* 0x11f0: end_cont */
+/* 0x1570: end_cont */
0xd000000000008007,
0x3400c3fffc201c04,
0xc000000003f01ec5,
@@ -593,6 +713,6 @@ uint64_t gk104_builtin_code[] = {
uint64_t gk104_builtin_offsets[] = {
0x0000000000000000,
0x00000000000000f0,
- 0x0000000000000f08,
0x0000000000000f18,
+ 0x0000000000001168,
};
diff --git a/src/gallium/drivers/nouveau/codegen/lib/gk110.asm b/src/gallium/drivers/nouveau/codegen/lib/gk110.asm
index b9c05a04b9a..4047a565a9f 100644
--- a/src/gallium/drivers/nouveau/codegen/lib/gk110.asm
+++ b/src/gallium/drivers/nouveau/codegen/lib/gk110.asm
@@ -83,12 +83,229 @@ gk110_div_s32:
$p0 sub b32 $r1 $r1 $r2
$p0 add b32 $r0 $r0 0x1
$p3 cvt s32 $r0 neg s32 $r0
- sched 0x04 0x2e 0x04 0x28 0x04 0x20 0x2c
+ sched 0x04 0x2e 0x28 0x04 0x28 0x28 0x28
$p2 cvt s32 $r1 neg s32 $r1
ret
+// RCP F64
+//
+// INPUT: $r0d
+// OUTPUT: $r0d
+// CLOBBER: $r2 - $r9, $p0
+//
+// The core of RCP and RSQ implementation is Newton-Raphson step, which is
+// used to find successively better approximation from an imprecise initial
+// value (single precision rcp in RCP and rsqrt64h in RSQ).
+//
gk110_rcp_f64:
+ // Step 1: classify input according to exponent and value, and calculate
+ // result for 0/inf/nan. $r2 holds the exponent value, which starts at
+ // bit 52 (bit 20 of the upper half) and is 11 bits in length
+ ext u32 $r2 $r1 0xb14
+ add b32 $r3 $r2 0xffffffff
+ joinat #rcp_rejoin
+ // We want to check whether the exponent is 0 or 0x7ff (i.e. NaN, inf,
+ // denorm, or 0). Do this by substracting 1 from the exponent, which will
+ // mean that it's > 0x7fd in those cases when doing unsigned comparison
+ set b32 $p0 0x1 gt u32 $r3 0x7fd
+ // $r3: 0 for norms, 0x36 for denorms, -1 for others
+ mov b32 $r3 0x0
+ sched 0x2f 0x04 0x2d 0x2b 0x2f 0x28 0x28
+ join (not $p0) nop
+ // Process all special values: NaN, inf, denorm, 0
+ mov b32 $r3 0xffffffff
+ // A number is NaN if its abs value is greater than or unordered with inf
+ set $p0 0x1 gtu f64 abs $r0d 0x7ff0000000000000
+ (not $p0) bra #rcp_inf_or_denorm_or_zero
+ // NaN -> NaN, the next line sets the "quiet" bit of the result. This
+ // behavior is both seen on the CPU and the blob
+ join or b32 $r1 $r1 0x80000
+rcp_inf_or_denorm_or_zero:
+ and b32 $r4 $r1 0x7ff00000
+ // Other values with nonzero in exponent field should be inf
+ set b32 $p0 0x1 eq s32 $r4 0x0
+ sched 0x2b 0x04 0x2f 0x2d 0x2b 0x2f 0x20
+ $p0 bra #rcp_denorm_or_zero
+ // +/-Inf -> +/-0
+ xor b32 $r1 $r1 0x7ff00000
+ join mov b32 $r0 0x0
+rcp_denorm_or_zero:
+ set $p0 0x1 gtu f64 abs $r0d 0x0
+ $p0 bra #rcp_denorm
+ // +/-0 -> +/-Inf
+ join or b32 $r1 $r1 0x7ff00000
+rcp_denorm:
+ // non-0 denorms: multiply with 2^54 (the 0x36 in $r3), join with norms
+ mul rn f64 $r0d $r0d 0x4350000000000000
+ sched 0x2f 0x28 0x2b 0x28 0x28 0x04 0x28
+ join mov b32 $r3 0x36
+rcp_rejoin:
+ // All numbers with -1 in $r3 have their result ready in $r0d, return them
+ // others need further calculation
+ set b32 $p0 0x1 lt s32 $r3 0x0
+ $p0 bra #rcp_end
+ // Step 2: Before the real calculation goes on, renormalize the values to
+ // range [1, 2) by setting exponent field to 0x3ff (the exponent of 1)
+ // result in $r6d. The exponent will be recovered later.
+ ext u32 $r2 $r1 0xb14
+ and b32 $r7 $r1 0x800fffff
+ add b32 $r7 $r7 0x3ff00000
+ mov b32 $r6 $r0
+ sched 0x2b 0x04 0x28 0x28 0x2a 0x2b 0x2e
+ // Step 3: Convert new value to float (no overflow will occur due to step
+ // 2), calculate rcp and do newton-raphson step once
+ cvt rz f32 $r5 f64 $r6d
+ rcp f32 $r4 $r5
+ mov b32 $r0 0xbf800000
+ fma rn f32 $r5 $r4 $r5 $r0
+ fma rn f32 $r0 neg $r4 $r5 $r4
+ // Step 4: convert result $r0 back to double, do newton-raphson steps
+ cvt f64 $r0d f32 $r0
+ cvt f64 $r6d f64 neg $r6d
+ sched 0x2e 0x29 0x29 0x29 0x29 0x29 0x29
+ cvt f64 $r8d f32 0x3f800000
+ // 4 Newton-Raphson Steps, tmp in $r4d, result in $r0d
+ // The formula used here (and above) is:
+ // RCP_{n + 1} = 2 * RCP_{n} - x * RCP_{n} * RCP_{n}
+ // The following code uses 2 FMAs for each step, and it will basically
+ // looks like:
+ // tmp = -src * RCP_{n} + 1
+ // RCP_{n + 1} = RCP_{n} * tmp + RCP_{n}
+ fma rn f64 $r4d $r6d $r0d $r8d
+ fma rn f64 $r0d $r0d $r4d $r0d
+ fma rn f64 $r4d $r6d $r0d $r8d
+ fma rn f64 $r0d $r0d $r4d $r0d
+ fma rn f64 $r4d $r6d $r0d $r8d
+ fma rn f64 $r0d $r0d $r4d $r0d
+ sched 0x29 0x20 0x28 0x28 0x28 0x28 0x28
+ fma rn f64 $r4d $r6d $r0d $r8d
+ fma rn f64 $r0d $r0d $r4d $r0d
+ // Step 5: Exponent recovery and final processing
+ // The exponent is recovered by adding what we added to the exponent.
+ // Suppose we want to calculate rcp(x), but we have rcp(cx), then
+ // rcp(x) = c * rcp(cx)
+ // The delta in exponent comes from two sources:
+ // 1) The renormalization in step 2. The delta is:
+ // 0x3ff - $r2
+ // 2) (For the denorm input) The 2^54 we multiplied at rcp_denorm, stored
+ // in $r3
+ // These 2 sources are calculated in the first two lines below, and then
+ // added to the exponent extracted from the result above.
+ // Note that after processing, the new exponent may >= 0x7ff (inf)
+ // or <= 0 (denorm). Those cases will be handled respectively below
+ subr b32 $r2 $r2 0x3ff
+ add b32 $r4 $r2 $r3
+ ext u32 $r3 $r1 0xb14
+ // New exponent in $r3
+ add b32 $r3 $r3 $r4
+ add b32 $r2 $r3 0xffffffff
+ sched 0x28 0x2b 0x28 0x2b 0x28 0x28 0x2b
+ // (exponent-1) < 0x7fe (unsigned) means the result is in norm range
+ // (same logic as in step 1)
+ set b32 $p0 0x1 lt u32 $r2 0x7fe
+ (not $p0) bra #rcp_result_inf_or_denorm
+ // Norms: convert exponents back and return
+ shl b32 $r4 $r4 clamp 0x14
+ add b32 $r1 $r4 $r1
+ bra #rcp_end
+rcp_result_inf_or_denorm:
+ // New exponent >= 0x7ff means that result is inf
+ set b32 $p0 0x1 ge s32 $r3 0x7ff
+ (not $p0) bra #rcp_result_denorm
+ sched 0x20 0x25 0x28 0x2b 0x23 0x25 0x2f
+ // Infinity
+ and b32 $r1 $r1 0x80000000
+ mov b32 $r0 0x0
+ add b32 $r1 $r1 0x7ff00000
+ bra #rcp_end
+rcp_result_denorm:
+ // Denorm result comes from huge input. The greatest possible fp64, i.e.
+ // 0x7fefffffffffffff's rcp is 0x0004000000000000, 1/4 of the smallest
+ // normal value. Other rcp result should be greater than that. If we
+ // set the exponent field to 1, we can recover the result by multiplying
+ // it with 1/2 or 1/4. 1/2 is used if the "exponent" $r3 is 0, otherwise
+ // 1/4 ($r3 should be -1 then). This is quite tricky but greatly simplifies
+ // the logic here.
+ set b32 $p0 0x1 ne u32 $r3 0x0
+ and b32 $r1 $r1 0x800fffff
+ // 0x3e800000: 1/4
+ $p0 cvt f64 $r6d f32 0x3e800000
+ sched 0x2f 0x28 0x2c 0x2e 0x2a 0x20 0x27
+ // 0x3f000000: 1/2
+ (not $p0) cvt f64 $r6d f32 0x3f000000
+ add b32 $r1 $r1 0x00100000
+ mul rn f64 $r0d $r0d $r6d
+rcp_end:
+ ret
+
+// RSQ F64
+//
+// INPUT: $r0d
+// OUTPUT: $r0d
+// CLOBBER: $r2 - $r9, $p0 - $p1
+//
gk110_rsq_f64:
+ // Before getting initial result rsqrt64h, two special cases should be
+ // handled first.
+ // 1. NaN: set the highest bit in mantissa so it'll be surely recognized
+ // as NaN in rsqrt64h
+ set $p0 0x1 gtu f64 abs $r0d 0x7ff0000000000000
+ $p0 or b32 $r1 $r1 0x00080000
+ and b32 $r2 $r1 0x7fffffff
+ sched 0x27 0x20 0x28 0x2c 0x25 0x28 0x28
+ // 2. denorms and small normal values: using their original value will
+ // lose precision either at rsqrt64h or the first step in newton-raphson
+ // steps below. Take 2 as a threshold in exponent field, and multiply
+ // with 2^54 if the exponent is smaller or equal. (will multiply 2^27
+ // to recover in the end)
+ ext u32 $r3 $r1 0xb14
+ set b32 $p1 0x1 le u32 $r3 0x2
+ or b32 $r2 $r0 $r2
+ $p1 mul rn f64 $r0d $r0d 0x4350000000000000
+ rsqrt64h f32 $r5 $r1
+ // rsqrt64h will give correct result for 0/inf/nan, the following logic
+ // checks whether the input is one of those (exponent is 0x7ff or all 0
+ // except for the sign bit)
+ set b32 $r6 ne u32 $r3 0x7ff
+ and b32 $r2 $r2 $r6
+ sched 0x28 0x2b 0x20 0x27 0x28 0x2e 0x28
+ set b32 $p0 0x1 ne u32 $r2 0x0
+ $p0 bra #rsq_norm
+ // For 0/inf/nan, make sure the sign bit agrees with input and return
+ and b32 $r1 $r1 0x80000000
+ mov b32 $r0 0x0
+ or b32 $r1 $r1 $r5
+ ret
+rsq_norm:
+ // For others, do 4 Newton-Raphson steps with the formula:
+ // RSQ_{n + 1} = RSQ_{n} * (1.5 - 0.5 * x * RSQ_{n} * RSQ_{n})
+ // In the code below, each step is written as:
+ // tmp1 = 0.5 * x * RSQ_{n}
+ // tmp2 = -RSQ_{n} * tmp1 + 0.5
+ // RSQ_{n + 1} = RSQ_{n} * tmp2 + RSQ_{n}
+ mov b32 $r4 0x0
+ sched 0x2f 0x29 0x29 0x29 0x29 0x29 0x29
+ // 0x3f000000: 1/2
+ cvt f64 $r8d f32 0x3f000000
+ mul rn f64 $r2d $r0d $r8d
+ mul rn f64 $r0d $r2d $r4d
+ fma rn f64 $r6d neg $r4d $r0d $r8d
+ fma rn f64 $r4d $r4d $r6d $r4d
+ mul rn f64 $r0d $r2d $r4d
+ fma rn f64 $r6d neg $r4d $r0d $r8d
+ sched 0x29 0x29 0x29 0x29 0x29 0x29 0x29
+ fma rn f64 $r4d $r4d $r6d $r4d
+ mul rn f64 $r0d $r2d $r4d
+ fma rn f64 $r6d neg $r4d $r0d $r8d
+ fma rn f64 $r4d $r4d $r6d $r4d
+ mul rn f64 $r0d $r2d $r4d
+ fma rn f64 $r6d neg $r4d $r0d $r8d
+ fma rn f64 $r4d $r4d $r6d $r4d
+ sched 0x29 0x20 0x28 0x2e 0x00 0x00 0x00
+ // Multiply 2^27 to result for small inputs to recover
+ $p1 mul rn f64 $r4d $r4d 0x41a0000000000000
+ mov b32 $r1 $r5
+ mov b32 $r0 $r4
ret
.section #gk110_builtin_offsets
diff --git a/src/gallium/drivers/nouveau/codegen/lib/gk110.asm.h b/src/gallium/drivers/nouveau/codegen/lib/gk110.asm.h
index 8d00e2a2245..3d1523f2fdd 100644
--- a/src/gallium/drivers/nouveau/codegen/lib/gk110.asm.h
+++ b/src/gallium/drivers/nouveau/codegen/lib/gk110.asm.h
@@ -65,11 +65,132 @@ uint64_t gk110_builtin_code[] = {
0xe088000001000406,
0x4000000000800001,
0xe6010000000ce802,
- 0x08b08010a010b810,
+ 0x08a0a0a010a0b810,
0xe60100000088e806,
0x19000000001c003c,
/* 0x0218: gk110_rcp_f64 */
-/* 0x0218: gk110_rsq_f64 */
+ 0xc00000058a1c0409,
+ 0x407fffffff9c080d,
+ 0x1480000050000000,
+ 0xb3401c03fe9c0c1d,
+ 0xe4c03c007f9c000e,
+ 0x08a0a0bcacb410bc,
+ 0x8580000000603c02,
+ 0x747fffffff9fc00e,
+ 0xb4601fff801c021d,
+ 0x120000000420003c,
+ 0x21000400005c0404,
+/* 0x0270: rcp_inf_or_denorm_or_zero */
+ 0x203ff800001c0410,
+ 0xb3281c00001c101d,
+ 0x0880bcacb4bc10ac,
+ 0x120000000800003c,
+ 0x223ff800001c0404,
+ 0xe4c03c007fdc0002,
+/* 0x02a0: rcp_denorm_or_zero */
+ 0xb4601c00001c021d,
+ 0x120000000400003c,
+ 0x213ff800005c0404,
+/* 0x02b8: rcp_denorm */
+ 0xc400021a801c0001,
+ 0x08a010a0a0aca0bc,
+ 0x740000001b5fc00e,
+/* 0x02d0: rcp_rejoin */
+ 0xb3181c00001c0c1d,
+ 0x12000000c000003c,
+ 0xc00000058a1c0409,
+ 0x204007ffff9c041c,
+ 0x401ff800001c1c1d,
+ 0xe4c03c00001c001a,
+ 0x08b8aca8a0a010ac,
+ 0xe5400c00031c3816,
+ 0x84000000021c1412,
+ 0x745fc000001fc002,
+ 0xcc000000029c1016,
+ 0xcc081000029c1002,
+ 0xe5400000001c2c02,
+ 0xe5410000031c3c1a,
+ 0x08a4a4a4a4a4a4b8,
+ 0xc54001fc001c2c21,
+ 0xdb802000001c1812,
+ 0xdb800000021c0002,
+ 0xdb802000001c1812,
+ 0xdb800000021c0002,
+ 0xdb802000001c1812,
+ 0xdb800000021c0002,
+ 0x08a0a0a0a0a080a4,
+ 0xdb802000001c1812,
+ 0xdb800000021c0002,
+ 0x48000001ff9c0809,
+ 0xe0800000019c0812,
+ 0xc00000058a1c040d,
+ 0xe0800000021c0c0e,
+ 0x407fffffff9c0c09,
+ 0x08aca0a0aca0aca0,
+ 0xb3101c03ff1c081d,
+ 0x120000000c20003c,
+ 0xc24000000a1c1011,
+ 0xe0800000009c1006,
+ 0x12000000381c003c,
+/* 0x03f0: rcp_result_inf_or_denorm */
+ 0xb3681c03ff9c0c1d,
+ 0x120000001420003c,
+ 0x08bc948caca09480,
+ 0x20400000001c0404,
+ 0xe4c03c007f9c0002,
+ 0x403ff800001c0405,
+ 0x120000001c1c003c,
+/* 0x0428: rcp_result_denorm */
+ 0xb3501c00001c0c1d,
+ 0x204007ffff9c0404,
+ 0xc54001f400002c19,
+ 0x089c80a8b8b0a0bc,
+ 0xc54001f800202c19,
+ 0x40000800001c0405,
+ 0xe4000000031c0002,
+/* 0x0460: rcp_end */
+ 0x19000000001c003c,
+/* 0x0468: gk110_rsq_f64 */
+ 0xb4601fff801c021d,
+ 0x2100040000000404,
+ 0x203fffffff9c0408,
+ 0x08a0a094b0a0809c,
+ 0xc00000058a1c040d,
+ 0xb3301c00011c0c3d,
+ 0xe2001000011c000a,
+ 0xc400021a80040001,
+ 0x84000000039c0416,
+ 0xb2d01c03ff9c0c19,
+ 0xe2000000031c080a,
+ 0x08a0b8a09c80aca0,
+ 0xb3501c00001c081d,
+ 0x120000001000003c,
+ 0x20400000001c0404,
+ 0xe4c03c007f9c0002,
+ 0xe2001000029c0406,
+ 0x19000000001c003c,
+/* 0x04f8: rsq_norm */
+ 0xe4c03c007f9c0012,
+ 0x08a4a4a4a4a4a4bc,
+ 0xc54001f8001c2c21,
+ 0xe4000000041c000a,
+ 0xe4000000021c0802,
+ 0xdb882000001c101a,
+ 0xdb801000031c1012,
+ 0xe4000000021c0802,
+ 0xdb882000001c101a,
+ 0x08a4a4a4a4a4a4a4,
+ 0xdb801000031c1012,
+ 0xe4000000021c0802,
+ 0xdb882000001c101a,
+ 0xdb801000031c1012,
+ 0xe4000000021c0802,
+ 0xdb882000001c101a,
+ 0xdb801000031c1012,
+ 0x08000000b8a080a4,
+ 0xc400020d00041011,
+ 0xe4c03c00029c0006,
+ 0xe4c03c00021c0002,
0x19000000001c003c,
};
@@ -77,5 +198,5 @@ uint64_t gk110_builtin_offsets[] = {
0x0000000000000000,
0x00000000000000f0,
0x0000000000000218,
- 0x0000000000000218,
+ 0x0000000000000468,
};
diff --git a/src/gallium/drivers/nouveau/codegen/lib/gm107.asm b/src/gallium/drivers/nouveau/codegen/lib/gm107.asm
index 7ee5f8fc65b..faee0218d18 100644
--- a/src/gallium/drivers/nouveau/codegen/lib/gm107.asm
+++ b/src/gallium/drivers/nouveau/codegen/lib/gm107.asm
@@ -100,10 +100,253 @@ gm107_div_s32:
ret
nop 0
-// STUB
+// RCP F64
+//
+// INPUT: $r0d
+// OUTPUT: $r0d
+// CLOBBER: $r2 - $r9, $p0
+//
+// The core of RCP and RSQ implementation is Newton-Raphson step, which is
+// used to find successively better approximation from an imprecise initial
+// value (single precision rcp in RCP and rsqrt64h in RSQ).
+//
gm107_rcp_f64:
-gm107_rsq_f64:
+ // Step 1: classify input according to exponent and value, and calculate
+ // result for 0/inf/nan. $r2 holds the exponent value, which starts at
+ // bit 52 (bit 20 of the upper half) and is 11 bits in length
+ sched (st 0x0) (st 0x0) (st 0x0)
+ bfe u32 $r2 $r1 0xb14
+ iadd32i $r3 $r2 -1
+ ssy #rcp_rejoin
+ // We want to check whether the exponent is 0 or 0x7ff (i.e. NaN, inf,
+ // denorm, or 0). Do this by substracting 1 from the exponent, which will
+ // mean that it's > 0x7fd in those cases when doing unsigned comparison
+ sched (st 0x0) (st 0x0) (st 0x0)
+ isetp gt u32 and $p0 1 $r3 0x7fd 1
+ // $r3: 0 for norms, 0x36 for denorms, -1 for others
+ mov $r3 0x0 0xf
+ not $p0 sync
+ // Process all special values: NaN, inf, denorm, 0
+ sched (st 0x0) (st 0x0) (st 0x0)
+ mov32i $r3 0xffffffff 0xf
+ // A number is NaN if its abs value is greater than or unordered with inf
+ dsetp gtu and $p0 1 abs $r0 0x7ff0000000000000 1
+ not $p0 bra #rcp_inf_or_denorm_or_zero
+ // NaN -> NaN, the next line sets the "quiet" bit of the result. This
+ // behavior is both seen on the CPU and the blob
+ sched (st 0x0) (st 0x0) (st 0x0)
+ lop32i or $r1 $r1 0x80000
+ sync
+rcp_inf_or_denorm_or_zero:
+ lop32i and $r4 $r1 0x7ff00000
+ sched (st 0x0) (st 0x0) (st 0x0)
+ // Other values with nonzero in exponent field should be inf
+ isetp eq and $p0 1 $r4 0x0 1
+ $p0 bra #rcp_denorm_or_zero
+ // +/-Inf -> +/-0
+ lop32i xor $r1 $r1 0x7ff00000
+ sched (st 0x0) (st 0x0) (st 0x0)
+ mov $r0 0x0 0xf
+ sync
+rcp_denorm_or_zero:
+ dsetp gtu and $p0 1 abs $r0 0x0 1
+ sched (st 0x0) (st 0x0) (st 0x0)
+ $p0 bra #rcp_denorm
+ // +/-0 -> +/-Inf
+ lop32i or $r1 $r1 0x7ff00000
+ sync
+rcp_denorm:
+ // non-0 denorms: multiply with 2^54 (the 0x36 in $r3), join with norms
+ sched (st 0x0) (st 0x0) (st 0x0)
+ dmul $r0 $r0 0x4350000000000000
+ mov $r3 0x36 0xf
+ sync
+rcp_rejoin:
+ // All numbers with -1 in $r3 have their result ready in $r0d, return them
+ // others need further calculation
+ sched (st 0x0) (st 0x0) (st 0x0)
+ isetp lt and $p0 1 $r3 0x0 1
+ $p0 bra #rcp_end
+ // Step 2: Before the real calculation goes on, renormalize the values to
+ // range [1, 2) by setting exponent field to 0x3ff (the exponent of 1)
+ // result in $r6d. The exponent will be recovered later.
+ bfe u32 $r2 $r1 0xb14
+ sched (st 0x0) (st 0x0) (st 0x0)
+ lop32i and $r7 $r1 0x800fffff
+ iadd32i $r7 $r7 0x3ff00000
+ mov $r6 $r0 0xf
+ // Step 3: Convert new value to float (no overflow will occur due to step
+ // 2), calculate rcp and do newton-raphson step once
+ sched (st 0x0) (st 0x0) (st 0x0)
+ f2f ftz f64 f32 $r5 $r6
+ mufu rcp $r4 $r5
+ mov32i $r0 0xbf800000 0xf
+ sched (st 0x0) (st 0x0) (st 0x0)
+ ffma $r5 $r4 $r5 $r0
+ ffma $r0 $r5 neg $r4 $r4
+ // Step 4: convert result $r0 back to double, do newton-raphson steps
+ f2f f32 f64 $r0 $r0
+ sched (st 0x0) (st 0x0) (st 0x0)
+ f2f f64 f64 $r6 neg $r6
+ f2f f32 f64 $r8 0x3f800000
+ // 4 Newton-Raphson Steps, tmp in $r4d, result in $r0d
+ // The formula used here (and above) is:
+ // RCP_{n + 1} = 2 * RCP_{n} - x * RCP_{n} * RCP_{n}
+ // The following code uses 2 FMAs for each step, and it will basically
+ // looks like:
+ // tmp = -src * RCP_{n} + 1
+ // RCP_{n + 1} = RCP_{n} * tmp + RCP_{n}
+ dfma $r4 $r6 $r0 $r8
sched (st 0x0) (st 0x0) (st 0x0)
+ dfma $r0 $r0 $r4 $r0
+ dfma $r4 $r6 $r0 $r8
+ dfma $r0 $r0 $r4 $r0
+ sched (st 0x0) (st 0x0) (st 0x0)
+ dfma $r4 $r6 $r0 $r8
+ dfma $r0 $r0 $r4 $r0
+ dfma $r4 $r6 $r0 $r8
+ sched (st 0x0) (st 0x0) (st 0x0)
+ dfma $r0 $r0 $r4 $r0
+ // Step 5: Exponent recovery and final processing
+ // The exponent is recovered by adding what we added to the exponent.
+ // Suppose we want to calculate rcp(x), but we have rcp(cx), then
+ // rcp(x) = c * rcp(cx)
+ // The delta in exponent comes from two sources:
+ // 1) The renormalization in step 2. The delta is:
+ // 0x3ff - $r2
+ // 2) (For the denorm input) The 2^54 we multiplied at rcp_denorm, stored
+ // in $r3
+ // These 2 sources are calculated in the first two lines below, and then
+ // added to the exponent extracted from the result above.
+ // Note that after processing, the new exponent may >= 0x7ff (inf)
+ // or <= 0 (denorm). Those cases will be handled respectively below
+ iadd $r2 neg $r2 0x3ff
+ iadd $r4 $r2 $r3
+ sched (st 0x0) (st 0x0) (st 0x0)
+ bfe u32 $r3 $r1 0xb14
+ // New exponent in $r3
+ iadd $r3 $r3 $r4
+ iadd32i $r2 $r3 -1
+ // (exponent-1) < 0x7fe (unsigned) means the result is in norm range
+ // (same logic as in step 1)
+ sched (st 0x0) (st 0x0) (st 0x0)
+ isetp lt u32 and $p0 1 $r2 0x7fe 1
+ not $p0 bra #rcp_result_inf_or_denorm
+ // Norms: convert exponents back and return
+ shl $r4 $r4 0x14
+ sched (st 0x0) (st 0x0) (st 0x0)
+ iadd $r1 $r4 $r1
+ bra #rcp_end
+rcp_result_inf_or_denorm:
+ // New exponent >= 0x7ff means that result is inf
+ isetp ge and $p0 1 $r3 0x7ff 1
+ sched (st 0x0) (st 0x0) (st 0x0)
+ not $p0 bra #rcp_result_denorm
+ // Infinity
+ lop32i and $r1 $r1 0x80000000
+ mov $r0 0x0 0xf
+ sched (st 0x0) (st 0x0) (st 0x0)
+ iadd32i $r1 $r1 0x7ff00000
+ bra #rcp_end
+rcp_result_denorm:
+ // Denorm result comes from huge input. The greatest possible fp64, i.e.
+ // 0x7fefffffffffffff's rcp is 0x0004000000000000, 1/4 of the smallest
+ // normal value. Other rcp result should be greater than that. If we
+ // set the exponent field to 1, we can recover the result by multiplying
+ // it with 1/2 or 1/4. 1/2 is used if the "exponent" $r3 is 0, otherwise
+ // 1/4 ($r3 should be -1 then). This is quite tricky but greatly simplifies
+ // the logic here.
+ isetp ne u32 and $p0 1 $r3 0x0 1
+ sched (st 0x0) (st 0x0) (st 0x0)
+ lop32i and $r1 $r1 0x800fffff
+ // 0x3e800000: 1/4
+ $p0 f2f f32 f64 $r6 0x3e800000
+ // 0x3f000000: 1/2
+ not $p0 f2f f32 f64 $r6 0x3f000000
+ sched (st 0x0) (st 0x0) (st 0x0)
+ iadd32i $r1 $r1 0x00100000
+ dmul $r0 $r0 $r6
+rcp_end:
+ ret
+
+// RSQ F64
+//
+// INPUT: $r0d
+// OUTPUT: $r0d
+// CLOBBER: $r2 - $r9, $p0 - $p1
+//
+gm107_rsq_f64:
+ // Before getting initial result rsqrt64h, two special cases should be
+ // handled first.
+ // 1. NaN: set the highest bit in mantissa so it'll be surely recognized
+ // as NaN in rsqrt64h
+ sched (st 0xd wr 0x0 wt 0x3f) (st 0xd wt 0x1) (st 0xd)
+ dsetp gtu and $p0 1 abs $r0 0x7ff0000000000000 1
+ $p0 lop32i or $r1 $r1 0x00080000
+ lop32i and $r2 $r1 0x7fffffff
+ // 2. denorms and small normal values: using their original value will
+ // lose precision either at rsqrt64h or the first step in newton-raphson
+ // steps below. Take 2 as a threshold in exponent field, and multiply
+ // with 2^54 if the exponent is smaller or equal. (will multiply 2^27
+ // to recover in the end)
+ sched (st 0xd) (st 0xd) (st 0xd)
+ bfe u32 $r3 $r1 0xb14
+ isetp le u32 and $p1 1 $r3 0x2 1
+ lop or 1 $r2 $r0 $r2
+ sched (st 0xd wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xd)
+ $p1 dmul $r0 $r0 0x4350000000000000
+ mufu rsq64h $r5 $r1
+ // rsqrt64h will give correct result for 0/inf/nan, the following logic
+ // checks whether the input is one of those (exponent is 0x7ff or all 0
+ // except for the sign bit)
+ iset ne u32 and $r6 $r3 0x7ff 1
+ sched (st 0xd) (st 0xd) (st 0xd)
+ lop and 1 $r2 $r2 $r6
+ isetp ne u32 and $p0 1 $r2 0x0 1
+ $p0 bra #rsq_norm
+ // For 0/inf/nan, make sure the sign bit agrees with input and return
+ sched (st 0xd) (st 0xd) (st 0xd wt 0x1)
+ lop32i and $r1 $r1 0x80000000
+ mov $r0 0x0 0xf
+ lop or 1 $r1 $r1 $r5
+ sched (st 0xd) (st 0xf) (st 0xf)
+ ret
+ nop 0
+ nop 0
+rsq_norm:
+ // For others, do 4 Newton-Raphson steps with the formula:
+ // RSQ_{n + 1} = RSQ_{n} * (1.5 - 0.5 * x * RSQ_{n} * RSQ_{n})
+ // In the code below, each step is written as:
+ // tmp1 = 0.5 * x * RSQ_{n}
+ // tmp2 = -RSQ_{n} * tmp1 + 0.5
+ // RSQ_{n + 1} = RSQ_{n} * tmp2 + RSQ_{n}
+ sched (st 0xd) (st 0xd wr 0x1) (st 0xd wr 0x1 rd 0x0 wt 0x3)
+ mov $r4 0x0 0xf
+ // 0x3f000000: 1/2
+ f2f f32 f64 $r8 0x3f000000
+ dmul $r2 $r0 $r8
+ sched (st 0xd wr 0x0 wt 0x3) (st 0xd wr 0x0 wt 0x1) (st 0xd wr 0x0 wt 0x1)
+ dmul $r0 $r2 $r4
+ dfma $r6 $r0 neg $r4 $r8
+ dfma $r4 $r4 $r6 $r4
+ sched (st 0xd wr 0x0 wt 0x1) (st 0xd wr 0x0 wt 0x1) (st 0xd wr 0x0 wt 0x1)
+ dmul $r0 $r2 $r4
+ dfma $r6 $r0 neg $r4 $r8
+ dfma $r4 $r4 $r6 $r4
+ sched (st 0xd wr 0x0 wt 0x1) (st 0xd wr 0x0 wt 0x1) (st 0xd wr 0x0 wt 0x1)
+ dmul $r0 $r2 $r4
+ dfma $r6 $r0 neg $r4 $r8
+ dfma $r4 $r4 $r6 $r4
+ sched (st 0xd wr 0x0 wt 0x1) (st 0xd wr 0x0 wt 0x1) (st 0xd wr 0x0 wt 0x1)
+ dmul $r0 $r2 $r4
+ dfma $r6 $r0 neg $r4 $r8
+ dfma $r4 $r4 $r6 $r4
+ // Multiply 2^27 to result for small inputs to recover
+ sched (st 0xd wr 0x0 wt 0x1) (st 0xd wt 0x1) (st 0xd)
+ $p1 dmul $r4 $r4 0x41a0000000000000
+ mov $r1 $r5 0xf
+ mov $r0 $r4 0xf
+ sched (st 0xd) (st 0xf) (st 0xf)
ret
nop 0
nop 0
diff --git a/src/gallium/drivers/nouveau/codegen/lib/gm107.asm.h b/src/gallium/drivers/nouveau/codegen/lib/gm107.asm.h
index 65c93f7ae89..8eb27bbac99 100644
--- a/src/gallium/drivers/nouveau/codegen/lib/gm107.asm.h
+++ b/src/gallium/drivers/nouveau/codegen/lib/gm107.asm.h
@@ -82,8 +82,156 @@ uint64_t gm107_builtin_code[] = {
0xe32000000007000f,
0x50b0000000070f00,
/* 0x0280: gm107_rcp_f64 */
-/* 0x0280: gm107_rsq_f64 */
0x001f8000fc0007e0,
+ 0x38000000b1470102,
+ 0x1c0ffffffff70203,
+ 0xe29000000e000000,
+ 0x001f8000fc0007e0,
+ 0x366803807fd70307,
+ 0x5c9807800ff70003,
+ 0xf0f800000008000f,
+ 0x001f8000fc0007e0,
+ 0x010ffffffff7f003,
+ 0x368c03fff0070087,
+ 0xe24000000188000f,
+ 0x001f8000fc0007e0,
+ 0x0420008000070101,
+ 0xf0f800000007000f,
+/* 0x02f8: rcp_inf_or_denorm_or_zero */
+ 0x0407ff0000070104,
+ 0x001f8000fc0007e0,
+ 0x5b6503800ff70407,
+ 0xe24000000200000f,
+ 0x0447ff0000070101,
+ 0x001f8000fc0007e0,
+ 0x5c9807800ff70000,
+ 0xf0f800000007000f,
+/* 0x0338: rcp_denorm_or_zero */
+ 0x5b8c03800ff70087,
+ 0x001f8000fc0007e0,
+ 0xe24000000100000f,
+ 0x0427ff0000070101,
+ 0xf0f800000007000f,
+/* 0x0360: rcp_denorm */
+ 0x001f8000fc0007e0,
+ 0x3880004350070000,
+ 0x3898078003670003,
+ 0xf0f800000007000f,
+/* 0x0380: rcp_rejoin */
+ 0x001f8000fc0007e0,
+ 0x5b6303800ff70307,
+ 0xe24000001c00000f,
+ 0x38000000b1470102,
+ 0x001f8000fc0007e0,
+ 0x040800fffff70107,
+ 0x1c03ff0000070707,
+ 0x5c98078000070006,
+ 0x001f8000fc0007e0,
+ 0x5ca8100000670e05,
+ 0x5080000000470504,
+ 0x010bf8000007f000,
+ 0x001f8000fc0007e0,
+ 0x5980000000570405,
+ 0x5981020000470500,
+ 0x5ca8000000070b00,
+ 0x001f8000fc0007e0,
+ 0x5ca8200000670f06,
+ 0x38a8003f80070b08,
+ 0x5b70040000070604,
+ 0x001f8000fc0007e0,
+ 0x5b70000000470000,
+ 0x5b70040000070604,
+ 0x5b70000000470000,
+ 0x001f8000fc0007e0,
+ 0x5b70040000070604,
+ 0x5b70000000470000,
+ 0x5b70040000070604,
+ 0x001f8000fc0007e0,
+ 0x5b70000000470000,
+ 0x381200003ff70202,
+ 0x5c10000000370204,
+ 0x001f8000fc0007e0,
+ 0x38000000b1470103,
+ 0x5c10000000470303,
+ 0x1c0ffffffff70302,
+ 0x001f8000fc0007e0,
+ 0x366203807fe70207,
+ 0xe24000000208000f,
+ 0x3848000001470404,
+ 0x001f8000fc0007e0,
+ 0x5c10000000170401,
+ 0xe24000000807000f,
+/* 0x04d8: rcp_result_inf_or_denorm */
+ 0x366d03807ff70307,
+ 0x001f8000fc0007e0,
+ 0xe24000000288000f,
+ 0x0408000000070101,
+ 0x5c9807800ff70000,
+ 0x001f8000fc0007e0,
+ 0x1c07ff0000070101,
+ 0xe24000000407000f,
+/* 0x0518: rcp_result_denorm */
+ 0x5b6a03800ff70307,
+ 0x001f8000fc0007e0,
+ 0x040800fffff70101,
+ 0x38a8003e80000b06,
+ 0x38a8003f00080b06,
+ 0x001f8000fc0007e0,
+ 0x1c00010000070101,
+ 0x5c80000000670000,
+/* 0x0558: rcp_end */
+ 0xe32000000007000f,
+/* 0x0560: gm107_rsq_f64 */
+ 0x001fb401fda1ff0d,
+ 0x368c03fff0070087,
+ 0x0420008000000101,
+ 0x0407fffffff70102,
+ 0x001fb400fda007ed,
+ 0x38000000b1470103,
+ 0x366603800027030f,
+ 0x5c47020000270002,
+ 0x001fb401e1a0070d,
+ 0x3880004350010000,
+ 0x5080000000770105,
+ 0x365a03807ff70306,
+ 0x001fb400fda007ed,
+ 0x5c47000000670202,
+ 0x5b6a03800ff70207,
+ 0xe24000000400000f,
+ 0x003fb400fda007ed,
+ 0x0408000000070101,
+ 0x5c9807800ff70000,
+ 0x5c47020000570101,
+ 0x001fbc00fde007ed,
+ 0xe32000000007000f,
+ 0x50b0000000070f00,
+ 0x50b0000000070f00,
+/* 0x0620: rsq_norm */
+ 0x0060b400e5a007ed,
+ 0x5c9807800ff70004,
+ 0x38a8003f00070b08,
+ 0x5c80000000870002,
+ 0x003c3401e1a01f0d,
+ 0x5c80000000470200,
+ 0x5b71040000470006,
+ 0x5b70020000670404,
+ 0x003c3401e1a00f0d,
+ 0x5c80000000470200,
+ 0x5b71040000470006,
+ 0x5b70020000670404,
+ 0x003c3401e1a00f0d,
+ 0x5c80000000470200,
+ 0x5b71040000470006,
+ 0x5b70020000670404,
+ 0x003c3401e1a00f0d,
+ 0x5c80000000470200,
+ 0x5b71040000470006,
+ 0x5b70020000670404,
+ 0x001fb401fda00f0d,
+ 0x38800041a0010404,
+ 0x5c98078000570001,
+ 0x5c98078000470000,
+ 0x001fbc00fde007ed,
0xe32000000007000f,
0x50b0000000070f00,
0x50b0000000070f00,
@@ -93,5 +241,5 @@ uint64_t gm107_builtin_offsets[] = {
0x0000000000000000,
0x0000000000000120,
0x0000000000000280,
- 0x0000000000000280,
+ 0x0000000000000560,
};
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
index 49425b98b91..993d01c1e44 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
@@ -1119,6 +1119,7 @@ Program::Program(Type type, Target *arch)
binSize = 0;
maxGPR = -1;
+ fp64 = false;
main = new Function(this, "MAIN", ~0);
calls.insert(&main->call);
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 8085bb2f542..8d32a25ec23 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -1311,6 +1311,7 @@ class Program
uint32_t tlsSize; // size required for FILE_MEMORY_LOCAL
int maxGPR;
+ bool fp64;
MemoryPool mem_Instruction;
MemoryPool mem_CmpInstruction;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index afd7916a321..335e708c5cb 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -1087,6 +1087,8 @@ class Source
};
std::vector memoryFiles;
+ std::vector bufferAtomics;
+
private:
int inferSysValDirection(unsigned sn) const;
bool scanDeclaration(const struct tgsi_full_declaration *);
@@ -1137,6 +1139,7 @@ bool Source::scanSource()
//resources.resize(scan.file_max[TGSI_FILE_RESOURCE] + 1);
tempArrayId.resize(scan.file_max[TGSI_FILE_TEMPORARY] + 1);
memoryFiles.resize(scan.file_max[TGSI_FILE_MEMORY] + 1);
+ bufferAtomics.resize(scan.file_max[TGSI_FILE_BUFFER] + 1);
info->immd.bufSize = 0;
@@ -1483,11 +1486,14 @@ bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
tempArrayInfo.insert(std::make_pair(arrayId, std::make_pair(
first, last - first + 1)));
break;
+ case TGSI_FILE_BUFFER:
+ for (i = first; i <= last; ++i)
+ bufferAtomics[i] = decl->Declaration.Atomic;
+ break;
case TGSI_FILE_ADDRESS:
case TGSI_FILE_CONSTANT:
case TGSI_FILE_IMMEDIATE:
case TGSI_FILE_SAMPLER:
- case TGSI_FILE_BUFFER:
case TGSI_FILE_IMAGE:
break;
default:
@@ -2720,7 +2726,11 @@ Converter::handleLOAD(Value *dst0[4])
}
Instruction *ld = mkLoad(TYPE_U32, dst0[c], sym, off);
- ld->cache = tgsi.getCacheMode();
+ if (tgsi.getSrc(0).getFile() == TGSI_FILE_BUFFER &&
+ code->bufferAtomics[r])
+ ld->cache = nv50_ir::CACHE_CG;
+ else
+ ld->cache = tgsi.getCacheMode();
if (ind)
ld->setIndirect(0, 1, ind);
}
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 295497be2f9..346a98228bd 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -83,6 +83,38 @@ NVC0LegalizeSSA::handleDIV(Instruction *i)
delete_Instruction(prog, i);
}
+void
+NVC0LegalizeSSA::handleRCPRSQLib(Instruction *i, Value *src[])
+{
+ FlowInstruction *call;
+ Value *def[2];
+ int builtin;
+
+ def[0] = bld.mkMovToReg(0, src[0])->getDef(0);
+ def[1] = bld.mkMovToReg(1, src[1])->getDef(0);
+
+ if (i->op == OP_RCP)
+ builtin = NVC0_BUILTIN_RCP_F64;
+ else
+ builtin = NVC0_BUILTIN_RSQ_F64;
+
+ call = bld.mkFlow(OP_CALL, NULL, CC_ALWAYS, NULL);
+ def[0] = bld.getSSA();
+ def[1] = bld.getSSA();
+ bld.mkMovFromReg(def[0], 0);
+ bld.mkMovFromReg(def[1], 1);
+ bld.mkClobber(FILE_GPR, 0x3fc, 2);
+ bld.mkClobber(FILE_PREDICATE, i->op == OP_RSQ ? 0x3 : 0x1, 0);
+ bld.mkOp2(OP_MERGE, TYPE_U64, i->getDef(0), def[0], def[1]);
+
+ call->fixed = 1;
+ call->absolute = call->builtin = 1;
+ call->target.builtin = builtin;
+ delete_Instruction(prog, i);
+
+ prog->fp64 = true;
+}
+
void
NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
{
@@ -96,6 +128,12 @@ NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
Value *src[2], *dst[2], *def = i->getDef(0);
bld.mkSplit(src, 4, i->getSrc(0));
+ int chip = prog->getTarget()->getChipset();
+ if (chip >= NVISA_GK104_CHIPSET) {
+ handleRCPRSQLib(i, src);
+ return;
+ }
+
// 2. We don't care about the low 32 bits of the destination. Stick a 0 in.
dst[0] = bld.loadImm(NULL, 0);
dst[1] = bld.getSSA();
@@ -1063,22 +1101,6 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
}
}
- if (chipset >= NVISA_GK104_CHIPSET) {
- //
- // If TEX requires more than 4 sources, the 2nd register tuple must be
- // aligned to 4, even if it consists of just a single 4-byte register.
- //
- // XXX HACK: We insert 0 sources to avoid the 5 or 6 regs case.
- //
- int s = i->srcCount(0xff, true);
- if (s > 4 && s < 7) {
- if (i->srcExists(s)) // move potential predicate out of the way
- i->moveSources(s, 7 - s);
- while (s < 7)
- i->setSrc(s++, bld.loadImm(NULL, 0));
- }
- }
-
return true;
}
@@ -1887,7 +1909,8 @@ NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction *su)
su->op == OP_SULDB || su->op == OP_SUSTB || su->op == OP_SUREDB;
const int slot = su->tex.r;
const int dim = su->tex.target.getDim();
- const int arg = dim + (su->tex.target.isArray() || su->tex.target.isCube());
+ const bool array = su->tex.target.isArray() || su->tex.target.isCube();
+ const int arg = dim + array;
int c;
Value *zero = bld.mkImm(0);
Value *p1 = NULL;
@@ -1896,6 +1919,7 @@ NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction *su)
Value *bf, *eau, *off;
Value *addr, *pred;
Value *ind = su->getIndirectR();
+ Value *y, *z;
off = bld.getScratch(4);
bf = bld.getScratch(4);
@@ -1926,34 +1950,42 @@ NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction *su)
for (; c < 3; ++c)
src[c] = zero;
+ if (dim == 2 && !array) {
+ v = loadSuInfo32(ind, slot, NVC0_SU_INFO_UNK1C, su->tex.bindless);
+ src[2] = bld.mkOp2v(OP_SHR, TYPE_U32, bld.getSSA(),
+ v, bld.loadImm(NULL, 16));
+
+ v = loadSuInfo32(ind, slot, NVC0_SU_INFO_DIM(2), su->tex.bindless);
+ bld.mkOp3(OP_SUCLAMP, TYPE_S32, src[2], src[2], v, zero)
+ ->subOp = NV50_IR_SUBOP_SUCLAMP_SD(0, 2);
+ }
+
// set predicate output
if (su->tex.target == TEX_TARGET_BUFFER) {
src[0]->getInsn()->setFlagsDef(1, pred);
} else
- if (su->tex.target.isArray() || su->tex.target.isCube()) {
+ if (array) {
p1 = bld.getSSA(1, FILE_PREDICATE);
src[dim]->getInsn()->setFlagsDef(1, p1);
}
// calculate pixel offset
if (dim == 1) {
+ y = z = zero;
if (su->tex.target != TEX_TARGET_BUFFER)
bld.mkOp2(OP_AND, TYPE_U32, off, src[0], bld.loadImm(NULL, 0xffff));
- } else
- if (dim == 3) {
+ } else {
+ y = src[1];
+ z = src[2];
+
v = loadSuInfo32(ind, slot, NVC0_SU_INFO_UNK1C, su->tex.bindless);
bld.mkOp3(OP_MADSP, TYPE_U32, off, src[2], v, src[1])
- ->subOp = NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
+ ->subOp = NV50_IR_SUBOP_MADSP(4,4,8); // u16l u16l u16l
v = loadSuInfo32(ind, slot, NVC0_SU_INFO_PITCH, su->tex.bindless);
bld.mkOp3(OP_MADSP, TYPE_U32, off, off, v, src[0])
- ->subOp = NV50_IR_SUBOP_MADSP(0,2,8); // u32 u16l u16l
- } else {
- assert(dim == 2);
- v = loadSuInfo32(ind, slot, NVC0_SU_INFO_PITCH, su->tex.bindless);
- bld.mkOp3(OP_MADSP, TYPE_U32, off, src[1], v, src[0])
- ->subOp = (su->tex.target.isArray() || su->tex.target.isCube()) ?
- NV50_IR_SUBOP_MADSP_SD : NV50_IR_SUBOP_MADSP(4,2,8); // u16l u16l u16l
+ ->subOp = array ?
+ NV50_IR_SUBOP_MADSP_SD : NV50_IR_SUBOP_MADSP(0,2,8); // u32 u16l u16l
}
// calculate effective address part 1
@@ -1966,19 +1998,15 @@ NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction *su)
->subOp = NV50_IR_SUBOP_V1(7,6,8|2);
}
} else {
- Value *y = src[1];
- Value *z = src[2];
uint16_t subOp = 0;
switch (dim) {
case 1:
- y = zero;
- z = zero;
break;
case 2:
- z = off;
- if (!su->tex.target.isArray() && !su->tex.target.isCube()) {
- z = loadSuInfo32(ind, slot, NVC0_SU_INFO_UNK1C, su->tex.bindless);
+ if (array) {
+ z = off;
+ } else {
subOp = NV50_IR_SUBOP_SUBFM_3D;
}
break;
@@ -2001,7 +2029,7 @@ NVC0LoweringPass::processSurfaceCoordsNVE4(TexInstruction *su)
eau = bld.mkOp3v(OP_SUEAU, TYPE_U32, bld.getScratch(4), off, bf, v);
}
// add array layer offset
- if (su->tex.target.isArray() || su->tex.target.isCube()) {
+ if (array) {
v = loadSuInfo32(ind, slot, NVC0_SU_INFO_ARRAY, su->tex.bindless);
if (dim == 1)
bld.mkOp3(OP_MADSP, TYPE_U32, eau, src[1], v, eau)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
index e0f50ab0904..99809726602 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
@@ -62,6 +62,7 @@ class NVC0LegalizeSSA : public Pass
// we want to insert calls to the builtin library only after optimization
void handleDIV(Instruction *); // integer division, modulus
+ void handleRCPRSQLib(Instruction *, Value *[]);
void handleRCPRSQ(Instruction *); // double precision float recip/rsqrt
void handleFTZ(Instruction *);
void handleSET(CmpInstruction *);
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index f4379c137c5..f25bce00884 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -2341,9 +2341,19 @@ RegAlloc::InsertConstraintsPass::texConstraintGM107(TexInstruction *tex)
if (!tex->tex.target.isArray() && tex->tex.useOffsets)
s++;
}
- n = tex->srcCount(0xff) - s;
+ n = tex->srcCount(0xff, true) - s;
+ // TODO: Is this necessary? Perhaps just has to be aligned to the
+ // level that the first arg is, not necessarily to 4. This
+ // requirement has not been rigorously verified, as it has been on
+ // Kepler.
+ if (n > 0 && n < 3) {
+ if (tex->srcExists(n + s)) // move potential predicate out of the way
+ tex->moveSources(n + s, 3 - n);
+ while (n < 3)
+ tex->setSrc(s + n++, new_LValue(func, FILE_GPR));
+ }
} else {
- s = tex->srcCount(0xff);
+ s = tex->srcCount(0xff, true);
n = 0;
}
@@ -2366,14 +2376,18 @@ RegAlloc::InsertConstraintsPass::texConstraintNVE0(TexInstruction *tex)
} else
if (isTextureOp(tex->op)) {
int n = tex->srcCount(0xff, true);
- if (n > 4) {
- condenseSrcs(tex, 0, 3);
- if (n > 5) // NOTE: first call modified positions already
- condenseSrcs(tex, 4 - (4 - 1), n - 1 - (4 - 1));
- } else
- if (n > 1) {
- condenseSrcs(tex, 0, n - 1);
+ int s = n > 4 ? 4 : n;
+ if (n > 4 && n < 7) {
+ if (tex->srcExists(n)) // move potential predicate out of the way
+ tex->moveSources(n, 7 - n);
+
+ while (n < 7)
+ tex->setSrc(n++, new_LValue(func, FILE_GPR));
}
+ if (s > 1)
+ condenseSrcs(tex, 0, s - 1);
+ if (n > 4)
+ condenseSrcs(tex, 1, n - s);
}
}
@@ -2510,6 +2524,7 @@ RegAlloc::InsertConstraintsPass::insertConstraintMove(Instruction *cst, int s)
assert(cst->getSrc(s)->defs.size() == 1); // still SSA
Instruction *defi = cst->getSrc(s)->defs.front()->getInsn();
+
bool imm = defi->op == OP_MOV &&
defi->src(0).getFile() == FILE_IMMEDIATE;
bool load = defi->op == OP_LOAD &&
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
index 9193a01f189..5c6d0570ae2 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
@@ -399,6 +399,7 @@ Program::emitBinary(struct nv50_ir_prog_info *info)
}
}
}
+ info->io.fp64 |= fp64;
info->bin.relocData = emit->getRelocInfo();
info->bin.fixupData = emit->getFixupInfo();
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
index 2b69a8f6968..53551ebc037 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
@@ -79,6 +79,9 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return 2048;
case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
return 8 * 1024 * 1024;
+ case PIPE_CAP_MAX_VARYINGS:
+ return 8;
+
/* supported capabilities */
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_POINT_SPRITE:
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query.c b/src/gallium/drivers/nouveau/nv50/nv50_query.c
index e30380cd84d..13088ebb5fa 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_query.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_query.c
@@ -98,12 +98,10 @@ nv50_render_condition(struct pipe_context *pipe,
case PIPE_QUERY_OCCLUSION_COUNTER:
case PIPE_QUERY_OCCLUSION_PREDICATE:
case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
+ if (hq->state == NV50_HW_QUERY_STATE_READY)
+ wait = true;
if (likely(!condition)) {
- if (unlikely(hq->nesting))
- cond = wait ? NV50_3D_COND_MODE_NOT_EQUAL :
- NV50_3D_COND_MODE_ALWAYS;
- else
- cond = NV50_3D_COND_MODE_RES_NON_ZERO;
+ cond = wait ? NV50_3D_COND_MODE_NOT_EQUAL : NV50_3D_COND_MODE_ALWAYS;
} else {
cond = wait ? NV50_3D_COND_MODE_EQUAL : NV50_3D_COND_MODE_ALWAYS;
}
@@ -129,7 +127,7 @@ nv50_render_condition(struct pipe_context *pipe,
PUSH_SPACE(push, 9);
- if (wait) {
+ if (wait && hq->state != NV50_HW_QUERY_STATE_READY) {
BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
PUSH_DATA (push, 0);
}
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query_hw.c b/src/gallium/drivers/nouveau/nv50/nv50_query_hw.c
index ac3e409b2d5..4e74c462235 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_query_hw.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_query_hw.c
@@ -29,11 +29,6 @@
#include "nv50/nv50_query_hw_sm.h"
#include "nv_object.xml.h"
-#define NV50_HW_QUERY_STATE_READY 0
-#define NV50_HW_QUERY_STATE_ACTIVE 1
-#define NV50_HW_QUERY_STATE_ENDED 2
-#define NV50_HW_QUERY_STATE_FLUSHED 3
-
/* XXX: Nested queries, and simultaneous queries on multiple gallium contexts
* (since we use only a single GPU channel per screen) will not work properly.
*
@@ -158,8 +153,7 @@ nv50_hw_begin_query(struct nv50_context *nv50, struct nv50_query *q)
case PIPE_QUERY_OCCLUSION_COUNTER:
case PIPE_QUERY_OCCLUSION_PREDICATE:
case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
- hq->nesting = nv50->screen->num_occlusion_queries_active++;
- if (hq->nesting) {
+ if (nv50->screen->num_occlusion_queries_active++) {
nv50_hw_query_get(push, q, 0x10, 0x0100f002);
} else {
PUSH_SPACE(push, 4);
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query_hw.h b/src/gallium/drivers/nouveau/nv50/nv50_query_hw.h
index 82ec6bd2d96..a89a66cec4f 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_query_hw.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_query_hw.h
@@ -6,6 +6,11 @@
#include "nv50_query.h"
+#define NV50_HW_QUERY_STATE_READY 0
+#define NV50_HW_QUERY_STATE_ACTIVE 1
+#define NV50_HW_QUERY_STATE_ENDED 2
+#define NV50_HW_QUERY_STATE_FLUSHED 3
+
#define NVA0_HW_QUERY_STREAM_OUTPUT_BUFFER_OFFSET (PIPE_QUERY_TYPES + 0)
struct nv50_hw_query;
@@ -29,7 +34,6 @@ struct nv50_hw_query {
uint8_t state;
bool is64bit;
uint8_t rotate;
- int nesting; /* only used for occlusion queries */
struct nouveau_mm_allocation *mm;
struct nouveau_fence *fence;
};
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 0c53b22eb3c..8e65eaf50b1 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -156,6 +156,8 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return NV50_MAX_WINDOW_RECTANGLES;
case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
return 16 * 1024 * 1024;
+ case PIPE_CAP_MAX_VARYINGS:
+ return 15;
/* supported caps */
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
@@ -215,6 +217,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_CLOCK:
case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
+ case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
return 1;
case PIPE_CAP_SEAMLESS_CUBE_MAP:
return 1; /* class_3d >= NVA0_3D_CLASS; */
@@ -312,6 +315,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_ATOMFADD:
case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
+ case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
return 0;
case PIPE_CAP_VENDOR_ID:
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
index eb057bf2489..c1351062676 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
@@ -434,6 +434,7 @@ nvc0_video_buffer_create(struct pipe_context *pipe,
/* nvc0_push.c */
void nvc0_push_vbo(struct nvc0_context *, const struct pipe_draw_info *);
+void nvc0_push_vbo_indirect(struct nvc0_context *, const struct pipe_draw_info *);
/* nve4_compute.c */
void nve4_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
index 1a3e4e794c0..40af9936859 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
@@ -121,12 +121,10 @@ nvc0_render_condition(struct pipe_context *pipe,
case PIPE_QUERY_OCCLUSION_COUNTER:
case PIPE_QUERY_OCCLUSION_PREDICATE:
case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
+ if (hq->state == NVC0_HW_QUERY_STATE_READY)
+ wait = true;
if (likely(!condition)) {
- if (unlikely(hq->nesting))
- cond = wait ? NVC0_3D_COND_MODE_NOT_EQUAL :
- NVC0_3D_COND_MODE_ALWAYS;
- else
- cond = NVC0_3D_COND_MODE_RES_NON_ZERO;
+ cond = wait ? NVC0_3D_COND_MODE_NOT_EQUAL : NVC0_3D_COND_MODE_ALWAYS;
} else {
cond = wait ? NVC0_3D_COND_MODE_EQUAL : NVC0_3D_COND_MODE_ALWAYS;
}
@@ -151,7 +149,7 @@ nvc0_render_condition(struct pipe_context *pipe,
return;
}
- if (wait)
+ if (wait && hq->state != NVC0_HW_QUERY_STATE_READY)
nvc0_hw_query_fifo_wait(nvc0, q);
PUSH_SPACE(push, 10);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
index a420ed4ac0d..f6d5d0f5602 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
@@ -28,11 +28,6 @@
#include "nvc0/nvc0_query_hw_metric.h"
#include "nvc0/nvc0_query_hw_sm.h"
-#define NVC0_HW_QUERY_STATE_READY 0
-#define NVC0_HW_QUERY_STATE_ACTIVE 1
-#define NVC0_HW_QUERY_STATE_ENDED 2
-#define NVC0_HW_QUERY_STATE_FLUSHED 3
-
#define NVC0_HW_QUERY_ALLOC_SPACE 256
bool
@@ -158,14 +153,18 @@ nvc0_hw_begin_query(struct nvc0_context *nvc0, struct nvc0_query *q)
case PIPE_QUERY_OCCLUSION_COUNTER:
case PIPE_QUERY_OCCLUSION_PREDICATE:
case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
- hq->nesting = nvc0->screen->num_occlusion_queries_active++;
- if (hq->nesting) {
+ if (nvc0->screen->num_occlusion_queries_active++) {
nvc0_hw_query_get(push, q, 0x10, 0x0100f002);
} else {
PUSH_SPACE(push, 3);
BEGIN_NVC0(push, NVC0_3D(COUNTER_RESET), 1);
PUSH_DATA (push, NVC0_3D_COUNTER_RESET_SAMPLECNT);
IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 1);
+ /* Given that the counter is reset, the contents at 0x10 are
+ * equivalent to doing the query -- we would get hq->sequence as the
+ * payload and 0 as the reported value. This is already set up above
+ * as in the hq->rotate case.
+ */
}
break;
case PIPE_QUERY_PRIMITIVES_GENERATED:
@@ -199,6 +198,7 @@ nvc0_hw_begin_query(struct nvc0_context *nvc0, struct nvc0_query *q)
nvc0_hw_query_get(push, q, 0xc0 + 0x70, 0x0980a002); /* ROP, PIXELS */
nvc0_hw_query_get(push, q, 0xc0 + 0x80, 0x0d808002); /* TCP, LAUNCHES */
nvc0_hw_query_get(push, q, 0xc0 + 0x90, 0x0e809002); /* TEP, LAUNCHES */
+ ((uint64_t *)hq->data)[(12 + 10) * 2] = 0;
break;
default:
break;
@@ -271,6 +271,7 @@ nvc0_hw_end_query(struct nvc0_context *nvc0, struct nvc0_query *q)
nvc0_hw_query_get(push, q, 0x70, 0x0980a002); /* ROP, PIXELS */
nvc0_hw_query_get(push, q, 0x80, 0x0d808002); /* TCP, LAUNCHES */
nvc0_hw_query_get(push, q, 0x90, 0x0e809002); /* TEP, LAUNCHES */
+ ((uint64_t *)hq->data)[10 * 2] = 0;
break;
case PIPE_QUERY_TIMESTAMP_DISJOINT:
/* This query is not issued on GPU because disjoint is forced to false */
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.h b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.h
index 8225755d85e..5c8ad5eb2d0 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.h
@@ -6,6 +6,11 @@
#include "nvc0_query.h"
+#define NVC0_HW_QUERY_STATE_READY 0
+#define NVC0_HW_QUERY_STATE_ACTIVE 1
+#define NVC0_HW_QUERY_STATE_ENDED 2
+#define NVC0_HW_QUERY_STATE_FLUSHED 3
+
#define NVC0_HW_QUERY_TFB_BUFFER_OFFSET (PIPE_QUERY_TYPES + 0)
struct nvc0_hw_query;
@@ -29,7 +34,6 @@ struct nvc0_hw_query {
uint8_t state;
boolean is64bit;
uint8_t rotate;
- int nesting; /* only used for occlusion queries */
struct nouveau_mm_allocation *mm;
struct nouveau_fence *fence;
};
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 68b5869276a..553fe324bc7 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -182,6 +182,13 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return class_3d >= GM200_3D_CLASS ? 8 : 0;
case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
return 64 * 1024 * 1024;
+ case PIPE_CAP_MAX_VARYINGS:
+ /* NOTE: These only count our slots for GENERIC varyings.
+ * The address space may be larger, but the actual hard limit seems to be
+ * less than what the address space layout permits, so don't add TEXCOORD,
+ * COLOR, etc. here.
+ */
+ return 0x1f0 / 16;
/* supported caps */
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
@@ -266,6 +273,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
case PIPE_CAP_QUERY_SO_OVERFLOW:
+ case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
return 1;
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
@@ -336,6 +344,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_SURFACE_SAMPLE_COUNT:
case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
+ case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
return 0;
case PIPE_CAP_VENDOR_ID:
@@ -392,18 +401,6 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
return 16;
case PIPE_SHADER_CAP_MAX_INPUTS:
- if (shader == PIPE_SHADER_VERTEX)
- return 32;
- /* NOTE: These only count our slots for GENERIC varyings.
- * The address space may be larger, but the actual hard limit seems to be
- * less than what the address space layout permits, so don't add TEXCOORD,
- * COLOR, etc. here.
- */
- if (shader == PIPE_SHADER_FRAGMENT)
- return 0x1f0 / 16;
- /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
- * and excludes 0x60 per-patch inputs.
- */
return 0x200 / 16;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return 32;
@@ -1286,8 +1283,8 @@ nvc0_screen_create(struct nouveau_device *dev)
for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
PUSH_DATA (push, 1);
- PUSH_DATA (push, 8192 << 16);
- PUSH_DATA (push, 8192 << 16);
+ PUSH_DATA (push, 16384 << 16);
+ PUSH_DATA (push, 16384 << 16);
}
#define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index 04f0a0d55da..8820b5aac66 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
@@ -1051,21 +1051,13 @@ nve4_set_surface_info(struct nouveau_pushbuf *push,
} else {
struct nv50_miptree *mt = nv50_miptree(&res->base);
struct nv50_miptree_level *lvl = &mt->level[view->u.tex.level];
- const unsigned z = view->u.tex.first_layer;
-
- if (z) {
- if (mt->layout_3d) {
- address += nvc0_mt_zslice_offset(mt, view->u.tex.level, z);
- /* doesn't work if z passes z-tile boundary */
- if (depth > 1) {
- pipe_debug_message(&nvc0->base.debug, CONFORMANCE,
- "3D images are not really supported!");
- debug_printf("3D images are not really supported!\n");
- }
- } else {
- address += mt->layer_stride * z;
- }
+ unsigned z = view->u.tex.first_layer;
+
+ if (!mt->layout_3d) {
+ address += mt->layer_stride * z;
+ z = 0;
}
+
address += lvl->offset;
info[0] = address >> 8;
@@ -1080,7 +1072,8 @@ nve4_set_surface_info(struct nouveau_pushbuf *push,
info[6] = depth - 1;
info[6] |= (lvl->tile_mode & 0xf00) << 21;
info[6] |= NVC0_TILE_SHIFT_Z(lvl->tile_mode) << 22;
- info[7] = 0;
+ info[7] = mt->layout_3d ? 1 : 0;
+ info[7] |= z << 16;
info[14] = mt->ms_x;
info[15] = mt->ms_y;
}
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
index 3fbe7614e52..7d6be9382d1 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
@@ -1040,7 +1040,10 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
}
if (nvc0->state.vbo_mode) {
- nvc0_push_vbo(nvc0, info);
+ if (info->indirect)
+ nvc0_push_vbo_indirect(nvc0, info);
+ else
+ nvc0_push_vbo(nvc0, info);
goto cleanup;
}
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo_translate.c b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo_translate.c
index 256e20df2e4..4333fb26d23 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo_translate.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo_translate.c
@@ -466,6 +466,83 @@ nvc0_prim_gl(unsigned prim)
}
}
+typedef struct {
+ uint32_t count;
+ uint32_t primCount;
+ uint32_t first;
+ uint32_t baseInstance;
+} DrawArraysIndirectCommand;
+
+typedef struct {
+ uint32_t count;
+ uint32_t primCount;
+ uint32_t firstIndex;
+ int32_t baseVertex;
+ uint32_t baseInstance;
+} DrawElementsIndirectCommand;
+
+void
+nvc0_push_vbo_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
+{
+ /* The strategy here is to just read the commands from the indirect buffer
+ * and do the draws. This is suboptimal, but will only happen in the case
+ * that conversion is required for FIXED or DOUBLE inputs.
+ */
+ struct nvc0_screen *screen = nvc0->screen;
+ struct nouveau_pushbuf *push = nvc0->base.pushbuf;
+ struct nv04_resource *buf = nv04_resource(info->indirect->buffer);
+ struct nv04_resource *buf_count = nv04_resource(info->indirect->indirect_draw_count);
+ unsigned i;
+
+ unsigned draw_count = info->indirect->draw_count;
+ if (buf_count) {
+ uint32_t *count = nouveau_resource_map_offset(
+ &nvc0->base, buf_count, info->indirect->indirect_draw_count_offset,
+ NOUVEAU_BO_RD);
+ draw_count = *count;
+ }
+
+ uint8_t *buf_data = nouveau_resource_map_offset(
+ &nvc0->base, buf, info->indirect->offset, NOUVEAU_BO_RD);
+ struct pipe_draw_info single = *info;
+ single.indirect = NULL;
+ for (i = 0; i < draw_count; i++, buf_data += info->indirect->stride) {
+ if (info->index_size) {
+ DrawElementsIndirectCommand *cmd = (void *)buf_data;
+ single.start = info->start + cmd->firstIndex;
+ single.count = cmd->count;
+ single.start_instance = cmd->baseInstance;
+ single.instance_count = cmd->primCount;
+ single.index_bias = cmd->baseVertex;
+ } else {
+ DrawArraysIndirectCommand *cmd = (void *)buf_data;
+ single.start = cmd->first;
+ single.count = cmd->count;
+ single.start_instance = cmd->baseInstance;
+ single.instance_count = cmd->primCount;
+ }
+
+ if (nvc0->vertprog->vp.need_draw_parameters) {
+ PUSH_SPACE(push, 9);
+ BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
+ PUSH_DATA (push, NVC0_CB_AUX_SIZE);
+ PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(0));
+ PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(0));
+ BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 3);
+ PUSH_DATA (push, NVC0_CB_AUX_DRAW_INFO);
+ PUSH_DATA (push, single.index_bias);
+ PUSH_DATA (push, single.start_instance);
+ PUSH_DATA (push, single.drawid + i);
+ }
+
+ nvc0_push_vbo(nvc0, &single);
+ }
+
+ nouveau_resource_unmap(buf);
+ if (buf_count)
+ nouveau_resource_unmap(buf_count);
+}
+
void
nvc0_push_vbo(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
{
diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c
index 19d3a1bae30..be0b475e5ef 100644
--- a/src/gallium/drivers/r300/r300_screen.c
+++ b/src/gallium/drivers/r300/r300_screen.c
@@ -304,6 +304,9 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
return 2048;
+ case PIPE_CAP_MAX_VARYINGS:
+ return 10;
+
case PIPE_CAP_VENDOR_ID:
return 0x1002;
case PIPE_CAP_DEVICE_ID:
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index ade1a94ab32..41a878ab9d2 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -536,6 +536,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_TEXEL_OFFSET:
return 7;
+ case PIPE_CAP_MAX_VARYINGS:
+ return 32;
+
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
case PIPE_CAP_ENDIANNESS:
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index f86764f5220..96ffbf82927 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1837,18 +1837,17 @@ static void r600_emit_sampler_states(struct r600_context *rctx,
/* TEX_ARRAY_OVERRIDE must be set for array textures to disable
* filtering between layers.
- * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
*/
- if (rview) {
- enum pipe_texture_target target = rview->base.texture->target;
- if (target == PIPE_TEXTURE_1D_ARRAY ||
- target == PIPE_TEXTURE_2D_ARRAY) {
- rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
- texinfo->is_array_sampler[i] = true;
- } else {
- rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
- texinfo->is_array_sampler[i] = false;
- }
+ enum pipe_texture_target target = PIPE_BUFFER;
+ if (rview)
+ target = rview->base.texture->target;
+ if (target == PIPE_TEXTURE_1D_ARRAY ||
+ target == PIPE_TEXTURE_2D_ARRAY) {
+ rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
+ texinfo->is_array_sampler[i] = true;
+ } else {
+ rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
+ texinfo->is_array_sampler[i] = false;
}
radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index a4e6d9dc6b5..688cef90103 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -64,6 +64,7 @@ static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec,
memset(&result, 0, sizeof(result));
switch (pic->base.profile) {
case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
+ case PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE:
result.profile = RDECODE_H264_PROFILE_BASELINE;
break;
@@ -490,7 +491,7 @@ static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec,
assert(dec->base.max_references + 1 <= 16);
- for (i = 0 ; i < dec->base.max_references + 1 ; ++i) {
+ for (i = 0 ; i < 16 ; ++i) {
if (dec->render_pic_list[i] && dec->render_pic_list[i] == target) {
result.curr_pic_idx =
(uintptr_t)vl_video_buffer_get_associated_data(target, &dec->base);
diff --git a/src/gallium/drivers/radeonsi/Makefile.sources b/src/gallium/drivers/radeonsi/Makefile.sources
index 713629c6e87..3cdd0851a5c 100644
--- a/src/gallium/drivers/radeonsi/Makefile.sources
+++ b/src/gallium/drivers/radeonsi/Makefile.sources
@@ -14,6 +14,7 @@ C_SOURCES := \
si_compute_blit.c \
si_cp_dma.c \
si_debug.c \
+ si_debug_options.h \
si_descriptors.c \
si_dma.c \
si_dma_cs.c \
diff --git a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
index cbf3bb01fb3..000a300746e 100644
--- a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
+++ b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
@@ -11,5 +11,14 @@ DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
- DRI_CONF_RADEONSI_CLEAR_DB_CACHE_BEFORE_CLEAR("false")
+
+//= BEGIN VERBATIM
+#define OPT_BOOL(name, dflt, description) \
+ DRI_CONF_OPT_BEGIN_B(radeonsi_##name, #dflt) \
+ DRI_CONF_DESC(en, description) \
+ DRI_CONF_OPT_END
+
+#include "radeonsi/si_debug_options.h"
+//= END VERBATIM
+
DRI_CONF_SECTION_END
diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c
index 03c11cb7013..3845e56a4b3 100644
--- a/src/gallium/drivers/radeonsi/si_buffer.c
+++ b/src/gallium/drivers/radeonsi/si_buffer.c
@@ -521,10 +521,13 @@ static void si_buffer_do_flush_region(struct pipe_context *ctx,
struct si_resource *buf = si_resource(transfer->resource);
if (stransfer->staging) {
+ unsigned src_offset = stransfer->offset +
+ transfer->box.x % SI_MAP_BUFFER_ALIGNMENT +
+ (box->x - transfer->box.x);
+
/* Copy the staging buffer into the original one. */
si_copy_buffer((struct si_context*)ctx, transfer->resource,
- &stransfer->staging->b.b, box->x,
- stransfer->offset + box->x % SI_MAP_BUFFER_ALIGNMENT,
+ &stransfer->staging->b.b, box->x, src_offset,
box->width);
}
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 9026f61dc0a..ef25c79fa9c 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -272,7 +272,7 @@ void vi_dcc_clear_level(struct si_context *sctx,
}
si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
- &clear_value, 4, SI_COHERENCY_CB_META);
+ &clear_value, 4, SI_COHERENCY_CB_META, false);
}
/* Set the same micro tile mode as the destination of the last MSAA resolve.
@@ -505,7 +505,7 @@ static void si_do_fast_color_clear(struct si_context *sctx,
uint32_t clear_value = 0xCCCCCCCC;
si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
tex->cmask_offset, tex->surface.cmask_size,
- &clear_value, 4, SI_COHERENCY_CB_META);
+ &clear_value, 4, SI_COHERENCY_CB_META, false);
fmask_decompress_needed = true;
}
@@ -533,7 +533,7 @@ static void si_do_fast_color_clear(struct si_context *sctx,
uint32_t clear_value = 0;
si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
tex->cmask_offset, tex->surface.cmask_size,
- &clear_value, 4, SI_COHERENCY_CB_META);
+ &clear_value, 4, SI_COHERENCY_CB_META, false);
eliminate_needed = true;
}
@@ -647,7 +647,7 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
* This hack decreases back-to-back ClearDepth performance.
*/
if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
- sctx->screen->clear_db_cache_before_clear)
+ sctx->screen->options.clear_db_cache_before_clear)
sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
}
diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c
index 38c48c30be9..304296c4a52 100644
--- a/src/gallium/drivers/radeonsi/si_compute_blit.c
+++ b/src/gallium/drivers/radeonsi/si_compute_blit.c
@@ -177,7 +177,8 @@ static void si_compute_do_clear_or_copy(struct si_context *sctx,
void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
uint64_t offset, uint64_t size, uint32_t *clear_value,
- uint32_t clear_value_size, enum si_coherency coher)
+ uint32_t clear_value_size, enum si_coherency coher,
+ bool force_cpdma)
{
if (!size)
return;
@@ -241,7 +242,8 @@ void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
* about buffer placements.
*/
if (clear_value_size > 4 ||
- (clear_value_size == 4 &&
+ (!force_cpdma &&
+ clear_value_size == 4 &&
offset % 4 == 0 &&
(size > 32*1024 || sctx->chip_class <= VI))) {
si_compute_do_clear_or_copy(sctx, dst, offset, NULL, 0,
@@ -282,7 +284,7 @@ static void si_pipe_clear_buffer(struct pipe_context *ctx,
coher = SI_COHERENCY_SHADER;
si_clear_buffer((struct si_context*)ctx, dst, offset, size, (uint32_t*)clear_value,
- clear_value_size, coher);
+ clear_value_size, coher, false);
}
void si_copy_buffer(struct si_context *sctx,
diff --git a/src/gallium/drivers/radeonsi/si_debug_options.h b/src/gallium/drivers/radeonsi/si_debug_options.h
new file mode 100644
index 00000000000..165dba8baf5
--- /dev/null
+++ b/src/gallium/drivers/radeonsi/si_debug_options.h
@@ -0,0 +1,4 @@
+OPT_BOOL(clear_db_cache_before_clear, false, "Clear DB cache before fast depth clear")
+OPT_BOOL(enable_nir, false, "Enable NIR")
+
+#undef OPT_BOOL
diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index bb2d8c09eb1..ff25a976e77 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -208,7 +208,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
RADEON_SPARSE_PAGE_SIZE : 0;
case PIPE_CAP_PACKED_UNIFORMS:
- if (sscreen->debug_flags & DBG(NIR))
+ if (sscreen->options.enable_nir)
return 1;
return 0;
@@ -254,6 +254,9 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
return 30;
+ case PIPE_CAP_MAX_VARYINGS:
+ return 32;
+
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
return sscreen->info.chip_class <= VI ?
PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
@@ -420,11 +423,11 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
return SI_NUM_IMAGES;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
- if (sscreen->debug_flags & DBG(NIR))
+ if (sscreen->options.enable_nir)
return 0;
return 32;
case PIPE_SHADER_CAP_PREFERRED_IR:
- if (sscreen->debug_flags & DBG(NIR))
+ if (sscreen->options.enable_nir)
return PIPE_SHADER_IR_NIR;
return PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c
index 2da14f8868f..d55394f2cba 100644
--- a/src/gallium/drivers/radeonsi/si_perfcounter.c
+++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
@@ -1333,7 +1333,7 @@ void si_init_perfcounters(struct si_screen *screen)
for (i = 0; i < num_blocks; ++i) {
struct si_pc_block *block = &pc->blocks[i];
block->b = &blocks[i];
- block->num_instances = block->b->instances;
+ block->num_instances = MAX2(1, block->b->instances);
if (!strcmp(block->b->b->name, "CB") ||
!strcmp(block->b->b->name, "DB"))
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 41d395d7d3f..507ca65605f 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -61,7 +61,6 @@ static const struct debug_named_value debug_options[] = {
/* Shader compiler options (with no effect on the shader cache): */
{ "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
- { "nir", DBG(NIR), "Enable experimental NIR shaders" },
{ "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
{ "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
@@ -609,11 +608,14 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
si_begin_new_gfx_cs(sctx);
if (sctx->chip_class == CIK) {
- /* Clear the NULL constant buffer, because loads should return zeros. */
+ /* Clear the NULL constant buffer, because loads should return zeros.
+ * Note that this forces CP DMA to be used, because clover deadlocks
+ * for some reason when the compute codepath is used.
+ */
uint32_t clear_value = 0;
si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
sctx->null_const_buf.buffer->width0,
- &clear_value, 4, SI_COHERENCY_SHADER);
+ &clear_value, 4, SI_COHERENCY_SHADER, true);
}
return &sctx->b;
fail:
@@ -804,8 +806,7 @@ static void si_disk_cache_create(struct si_screen *sscreen)
#define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
DBG(SI_SCHED) | \
DBG(GISEL) | \
- DBG(UNSAFE_MATH) | \
- DBG(NIR))
+ DBG(UNSAFE_MATH))
uint64_t shader_debug_flags = sscreen->debug_flags &
ALL_FLAGS;
@@ -813,7 +814,11 @@ static void si_disk_cache_create(struct si_screen *sscreen)
* how 32-bit addresses are expanded to 64 bits.
*/
STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
- shader_debug_flags |= (uint64_t)sscreen->info.address32_hi << 32;
+ assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
+ shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
+
+ if (sscreen->options.enable_nir)
+ shader_debug_flags |= 1ull << 48;
sscreen->disk_shader_cache =
disk_cache_create(sscreen->info.name,
@@ -866,7 +871,6 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
sscreen->debug_flags |= DBG(SI_SCHED);
-
if (sscreen->debug_flags & DBG(INFO))
ac_print_gpu_info(&sscreen->info);
@@ -1013,8 +1017,16 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
sscreen->commutative_blend_add =
driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
- sscreen->clear_db_cache_before_clear =
- driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
+
+ {
+#define OPT_BOOL(name, dflt, description) \
+ sscreen->options.name = \
+ driQueryOptionb(config->options, "radeonsi_"#name);
+#include "si_debug_options.h"
+ }
+
+ sscreen->has_gfx9_scissor_bug = sscreen->info.family == CHIP_VEGA10 ||
+ sscreen->info.family == CHIP_RAVEN;
sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
sscreen->info.family <= CHIP_POLARIS12) ||
sscreen->info.family == CHIP_VEGA10 ||
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index eb3ba951dae..ea009622970 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -133,7 +133,6 @@ enum {
/* Shader compiler options (with no effect on the shader cache): */
DBG_CHECK_IR,
- DBG_NIR,
DBG_MONOLITHIC_SHADERS,
DBG_NO_OPT_VARIANT,
@@ -445,7 +444,7 @@ struct si_screen {
bool has_out_of_order_rast;
bool assume_no_z_fights;
bool commutative_blend_add;
- bool clear_db_cache_before_clear;
+ bool has_gfx9_scissor_bug;
bool has_msaa_sample_loc_bug;
bool has_ls_vgpr_init_bug;
bool has_dcc_constant_encode;
@@ -453,6 +452,11 @@ struct si_screen {
bool dfsm_allowed;
bool llvm_has_working_vgpr_indexing;
+ struct {
+#define OPT_BOOL(name, dflt, description) bool name:1;
+#include "si_debug_options.h"
+ } options;
+
/* Whether shaders are monolithic (1-part) or separate (3-part). */
bool use_monolithic_shaders;
bool record_llvm_ir;
@@ -1054,7 +1058,7 @@ struct si_context {
unsigned num_resident_handles;
uint64_t num_alloc_tex_transfer_bytes;
unsigned last_tex_ps_draw_ratio; /* for query */
- unsigned context_roll_counter;
+ unsigned context_roll;
/* Queries. */
/* Maintain the list of active queries for pausing between IBs. */
@@ -1168,7 +1172,8 @@ unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
enum si_cache_policy cache_policy);
void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
uint64_t offset, uint64_t size, uint32_t *clear_value,
- uint32_t clear_value_size, enum si_coherency coher);
+ uint32_t clear_value_size, enum si_coherency coher,
+ bool force_cpdma);
void si_copy_buffer(struct si_context *sctx,
struct pipe_resource *dst, struct pipe_resource *src,
uint64_t dst_offset, uint64_t src_offset, unsigned size);
diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c
index 266b9d3ce84..280eee3a280 100644
--- a/src/gallium/drivers/radeonsi/si_query.c
+++ b/src/gallium/drivers/radeonsi/si_query.c
@@ -549,11 +549,15 @@ void si_query_buffer_reset(struct si_context *sctx, struct si_query_buffer *buff
}
buffer->results_end = 0;
+ if (!buffer->buf)
+ return;
+
/* Discard even the oldest buffer if it can't be mapped without a stall. */
- if (buffer->buf &&
- (si_rings_is_buffer_referenced(sctx, buffer->buf->buf, RADEON_USAGE_READWRITE) ||
- !sctx->ws->buffer_wait(buffer->buf->buf, 0, RADEON_USAGE_READWRITE))) {
+ if (si_rings_is_buffer_referenced(sctx, buffer->buf->buf, RADEON_USAGE_READWRITE) ||
+ !sctx->ws->buffer_wait(buffer->buf->buf, 0, RADEON_USAGE_READWRITE)) {
si_resource_reference(&buffer->buf, NULL);
+ } else {
+ buffer->unprepared = true;
}
}
@@ -561,29 +565,31 @@ bool si_query_buffer_alloc(struct si_context *sctx, struct si_query_buffer *buff
bool (*prepare_buffer)(struct si_context *, struct si_query_buffer*),
unsigned size)
{
- if (buffer->buf && buffer->results_end + size >= buffer->buf->b.b.width0)
- return true;
+ bool unprepared = buffer->unprepared;
+ buffer->unprepared = false;
+
+ if (!buffer->buf || buffer->results_end + size > buffer->buf->b.b.width0) {
+ if (buffer->buf) {
+ struct si_query_buffer *qbuf = MALLOC_STRUCT(si_query_buffer);
+ memcpy(qbuf, buffer, sizeof(*qbuf));
+ buffer->previous = qbuf;
+ }
+ buffer->results_end = 0;
- if (buffer->buf) {
- struct si_query_buffer *qbuf = MALLOC_STRUCT(si_query_buffer);
- memcpy(qbuf, buffer, sizeof(*qbuf));
- buffer->previous = qbuf;
+ /* Queries are normally read by the CPU after
+ * being written by the gpu, hence staging is probably a good
+ * usage pattern.
+ */
+ struct si_screen *screen = sctx->screen;
+ unsigned buf_size = MAX2(size, screen->info.min_alloc_size);
+ buffer->buf = si_resource(
+ pipe_buffer_create(&screen->b, 0, PIPE_USAGE_STAGING, buf_size));
+ if (unlikely(!buffer->buf))
+ return false;
+ unprepared = true;
}
- buffer->results_end = 0;
-
- /* Queries are normally read by the CPU after
- * being written by the gpu, hence staging is probably a good
- * usage pattern.
- */
- struct si_screen *screen = sctx->screen;
- unsigned buf_size = MAX2(size, screen->info.min_alloc_size);
- buffer->buf = si_resource(
- pipe_buffer_create(&screen->b, 0, PIPE_USAGE_STAGING, buf_size));
- if (unlikely(!buffer->buf))
- return false;
-
- if (prepare_buffer) {
+ if (unprepared && prepare_buffer) {
if (unlikely(!prepare_buffer(sctx, buffer))) {
si_resource_reference(&buffer->buf, NULL);
return false;
diff --git a/src/gallium/drivers/radeonsi/si_query.h b/src/gallium/drivers/radeonsi/si_query.h
index aaf0bd03aca..c61af51d57c 100644
--- a/src/gallium/drivers/radeonsi/si_query.h
+++ b/src/gallium/drivers/radeonsi/si_query.h
@@ -177,12 +177,13 @@ struct si_query_hw_ops {
struct si_query_buffer {
/* The buffer where query results are stored. */
struct si_resource *buf;
- /* Offset of the next free result after current query data */
- unsigned results_end;
/* If a query buffer is full, a new buffer is created and the old one
* is put in here. When we calculate the result, we sum up the samples
* from all buffers. */
struct si_query_buffer *previous;
+ /* Offset of the next free result after current query data */
+ unsigned results_end;
+ bool unprepared;
};
void si_query_buffer_destroy(struct si_screen *sctx, struct si_query_buffer *buffer);
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 7554f5b9f8b..d7618b46eb0 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -834,7 +834,7 @@ si_lower_nir(struct si_shader_selector* sel)
NIR_PASS(progress, sel->nir, nir_opt_if);
NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
NIR_PASS(progress, sel->nir, nir_opt_cse);
- NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8, true, true);
+ NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8, true);
/* Needed for algebraic lowering */
NIR_PASS(progress, sel->nir, nir_opt_algebraic);
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 89d81c97e18..85103a614b1 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -256,7 +256,7 @@ static void si_emit_cb_render_state(struct si_context *sctx)
sx_blend_opt_control);
}
if (initial_cdw != cs->current.cdw)
- sctx->context_roll_counter++;
+ sctx->context_roll = true;
}
/*
@@ -792,7 +792,7 @@ static void si_emit_clip_regs(struct si_context *sctx)
S_028810_CLIP_DISABLE(window_space));
if (initial_cdw != sctx->gfx_cs->current.cdw)
- sctx->context_roll_counter++;
+ sctx->context_roll = true;
}
/*
@@ -1446,7 +1446,7 @@ static void si_emit_db_render_state(struct si_context *sctx)
SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
if (initial_cdw != sctx->gfx_cs->current.cdw)
- sctx->context_roll_counter++;
+ sctx->context_roll = true;
}
/*
@@ -3527,7 +3527,7 @@ static void si_emit_msaa_config(struct si_context *sctx)
SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
if (initial_cdw != cs->current.cdw) {
- sctx->context_roll_counter++;
+ sctx->context_roll = true;
/* GFX9: Flush DFSM when the AA mode changes. */
if (sctx->screen->dfsm_allowed) {
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index 767e789276a..344f45e7e43 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -224,7 +224,8 @@ static inline unsigned si_atoms_that_always_roll_context(void)
SI_ATOM_BIT(scissors) |
SI_ATOM_BIT(viewports) |
SI_ATOM_BIT(stencil_ref) |
- SI_ATOM_BIT(scratch_state));
+ SI_ATOM_BIT(scratch_state) |
+ SI_ATOM_BIT(window_rectangles));
}
struct si_shader_data {
diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
index 3516e561282..5c6c2e69b90 100644
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -321,7 +321,7 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF) |
S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
if (initial_cdw != sctx->gfx_cs->current.cdw)
- sctx->context_roll_counter++;
+ sctx->context_roll = true;
}
void si_emit_dpbb_state(struct si_context *sctx)
@@ -443,5 +443,5 @@ void si_emit_dpbb_state(struct si_context *sctx)
S_028060_PUNCHOUT_MODE(punchout_mode) |
S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
if (initial_cdw != sctx->gfx_cs->current.cdw)
- sctx->context_roll_counter++;
+ sctx->context_roll = true;
}
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index c7c02d20d15..7bf82b8b05b 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -66,7 +66,7 @@ static unsigned si_conv_pipe_prim(unsigned mode)
* The information about LDS and other non-compile-time parameters is then
* written to userdata SGPRs.
*/
-static bool si_emit_derived_tess_state(struct si_context *sctx,
+static void si_emit_derived_tess_state(struct si_context *sctx,
const struct pipe_draw_info *info,
unsigned *num_patches)
{
@@ -110,7 +110,7 @@ static bool si_emit_derived_tess_state(struct si_context *sctx,
(!has_primid_instancing_bug ||
(sctx->last_tess_uses_primid == tess_uses_primid))) {
*num_patches = sctx->last_num_patches;
- return false;
+ return;
}
sctx->last_ls = ls_current;
@@ -305,9 +305,8 @@ static bool si_emit_derived_tess_state(struct si_context *sctx,
ls_hs_config);
}
sctx->last_ls_hs_config = ls_hs_config;
- return true; /* true if the context rolls */
+ sctx->context_roll = true;
}
- return false;
}
static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
@@ -541,7 +540,7 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
}
/* rast_prim is the primitive type after GS. */
-static bool si_emit_rasterizer_prim_state(struct si_context *sctx)
+static void si_emit_rasterizer_prim_state(struct si_context *sctx)
{
struct radeon_cmdbuf *cs = sctx->gfx_cs;
enum pipe_prim_type rast_prim = sctx->current_rast_prim;
@@ -549,11 +548,11 @@ static bool si_emit_rasterizer_prim_state(struct si_context *sctx)
/* Skip this if not rendering lines. */
if (!util_prim_is_lines(rast_prim))
- return false;
+ return;
if (rast_prim == sctx->last_rast_prim &&
rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
- return false;
+ return;
/* For lines, reset the stipple pattern at each primitive. Otherwise,
* reset the stipple pattern at each packet (line strips, line loops).
@@ -564,7 +563,7 @@ static bool si_emit_rasterizer_prim_state(struct si_context *sctx)
sctx->last_rast_prim = rast_prim;
sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
- return true; /* true if the context rolls */
+ sctx->context_roll = true;
}
static void si_emit_vs_state(struct si_context *sctx,
@@ -659,6 +658,7 @@ static void si_emit_draw_registers(struct si_context *sctx,
radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
info->restart_index);
sctx->last_restart_index = info->restart_index;
+ sctx->context_roll = true;
}
}
@@ -896,6 +896,10 @@ static void si_emit_surface_sync(struct si_context *sctx,
radeon_emit(cs, 0); /* CP_COHER_BASE */
radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
}
+
+ /* ACQUIRE_MEM has an implicit context roll if the current context
+ * is busy. */
+ sctx->context_roll = true;
}
void si_emit_cache_flush(struct si_context *sctx)
@@ -1210,26 +1214,10 @@ static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_i
unsigned skip_atom_mask)
{
unsigned num_patches = 0;
- /* Vega10/Raven scissor bug workaround. When any context register is
- * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
- * registers must be written too.
- */
- bool handle_scissor_bug = (sctx->family == CHIP_VEGA10 || sctx->family == CHIP_RAVEN) &&
- !si_is_atom_dirty(sctx, &sctx->atoms.s.scissors);
- bool context_roll = false; /* set correctly for GFX9 only */
- context_roll |= si_emit_rasterizer_prim_state(sctx);
+ si_emit_rasterizer_prim_state(sctx);
if (sctx->tes_shader.cso)
- context_roll |= si_emit_derived_tess_state(sctx, info, &num_patches);
-
- if (handle_scissor_bug &&
- (info->count_from_stream_output ||
- sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
- sctx->dirty_states & si_states_that_always_roll_context() ||
- si_prim_restart_index_changed(sctx, info)))
- context_roll = true;
-
- sctx->context_roll_counter = 0;
+ si_emit_derived_tess_state(sctx, info, &num_patches);
/* Emit state atoms. */
unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
@@ -1252,12 +1240,6 @@ static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_i
}
sctx->dirty_states = 0;
- if (handle_scissor_bug &&
- (context_roll || sctx->context_roll_counter)) {
- sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
- sctx->atoms.s.scissors.emit(sctx);
- }
-
/* Emit draw states. */
si_emit_vs_state(sctx, info);
si_emit_draw_registers(sctx, info, num_patches);
@@ -1456,6 +1438,22 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
if (!si_upload_vertex_buffer_descriptors(sctx))
return;
+ /* Vega10/Raven scissor bug workaround. When any context register is
+ * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
+ * registers must be written too.
+ */
+ bool has_gfx9_scissor_bug = sctx->screen->has_gfx9_scissor_bug;
+ unsigned masked_atoms = 0;
+
+ if (has_gfx9_scissor_bug) {
+ masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
+
+ if (info->count_from_stream_output ||
+ sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
+ sctx->dirty_states & si_states_that_always_roll_context())
+ sctx->context_roll = true;
+ }
+
/* Use optimal packet order based on whether we need to sync the pipeline. */
if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
SI_CONTEXT_FLUSH_AND_INV_DB |
@@ -1466,8 +1464,6 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
* Then draw and prefetch at the end. This ensures that the time
* the CUs are idle is very short.
*/
- unsigned masked_atoms = 0;
-
if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
@@ -1481,6 +1477,13 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
sctx->atoms.s.render_cond.emit(sctx);
+
+ if (has_gfx9_scissor_bug &&
+ (sctx->context_roll ||
+ si_is_atom_dirty(sctx, &sctx->atoms.s.scissors))) {
+ sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+ sctx->atoms.s.scissors.emit(sctx);
+ }
sctx->dirty_atoms = 0;
si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
@@ -1505,7 +1508,16 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
if (!si_upload_graphics_shader_descriptors(sctx))
return;
- si_emit_all_states(sctx, info, 0);
+ si_emit_all_states(sctx, info, masked_atoms);
+
+ if (has_gfx9_scissor_bug &&
+ (sctx->context_roll ||
+ si_is_atom_dirty(sctx, &sctx->atoms.s.scissors))) {
+ sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+ sctx->atoms.s.scissors.emit(sctx);
+ }
+ sctx->dirty_atoms = 0;
+
si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
/* Prefetch the remaining shaders after the draw has been
@@ -1514,6 +1526,9 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
cik_emit_prefetch_L2(sctx, false);
}
+ /* Clear the context roll flag after the draw call. */
+ sctx->context_roll = false;
+
if (unlikely(sctx->current_saved_cs)) {
si_trace_emit(sctx);
si_log_draw_state(sctx, sctx->log);
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 9e052e1efce..e76bb49dff8 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -576,7 +576,7 @@ static void si_emit_shader_es(struct si_context *sctx)
shader->vgt_vertex_reuse_block_cntl);
if (initial_cdw != sctx->gfx_cs->current.cdw)
- sctx->context_roll_counter++;
+ sctx->context_roll = true;
}
static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
@@ -825,7 +825,7 @@ static void si_emit_shader_gs(struct si_context *sctx)
}
if (initial_cdw != sctx->gfx_cs->current.cdw)
- sctx->context_roll_counter++;
+ sctx->context_roll = true;
}
static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
@@ -1002,7 +1002,7 @@ static void si_emit_shader_vs(struct si_context *sctx)
shader->vgt_vertex_reuse_block_cntl);
if (initial_cdw != sctx->gfx_cs->current.cdw)
- sctx->context_roll_counter++;
+ sctx->context_roll = true;
}
/**
@@ -1194,7 +1194,7 @@ static void si_emit_shader_ps(struct si_context *sctx)
shader->ctx_reg.ps.cb_shader_mask);
if (initial_cdw != sctx->gfx_cs->current.cdw)
- sctx->context_roll_counter++;
+ sctx->context_roll = true;
}
static void si_shader_ps(struct si_shader *shader)
@@ -2869,7 +2869,7 @@ static void si_emit_spi_map(struct si_context *sctx)
sctx->tracked_regs.spi_ps_input_cntl, num_interp);
if (initial_cdw != sctx->gfx_cs->current.cdw)
- sctx->context_roll_counter++;
+ sctx->context_roll = true;
}
/**
diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c
index 2bf6862c89b..2a0a4bef9a2 100644
--- a/src/gallium/drivers/radeonsi/si_state_streamout.c
+++ b/src/gallium/drivers/radeonsi/si_state_streamout.c
@@ -303,6 +303,7 @@ void si_emit_streamout_end(struct si_context *sctx)
* buffer bound. This ensures that the primitives-emitted query
* won't increment. */
radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
+ sctx->context_roll = true;
t[i]->buf_filled_size_valid = true;
}
diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c
index dac90df1c4f..1ec69216841 100644
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -185,6 +185,16 @@ static void si_emit_guardband(struct si_context *ctx)
const unsigned hw_screen_offset_alignment =
ctx->chip_class >= VI ? 16 : MAX2(ctx->screen->se_tile_repeat, 16);
+ /* Indexed by quantization modes */
+ static int max_viewport_size[] = {65535, 16383, 4095};
+
+ /* Ensure that the whole viewport stays representable in
+ * absolute coordinates.
+ * See comment in si_set_viewport_states.
+ */
+ assert(vp_as_scissor.maxx <= max_viewport_size[vp_as_scissor.quant_mode] &&
+ vp_as_scissor.maxy <= max_viewport_size[vp_as_scissor.quant_mode]);
+
hw_screen_offset_x = CLAMP(hw_screen_offset_x, 0, MAX_PA_SU_HARDWARE_SCREEN_OFFSET);
hw_screen_offset_y = CLAMP(hw_screen_offset_y, 0, MAX_PA_SU_HARDWARE_SCREEN_OFFSET);
@@ -219,7 +229,6 @@ static void si_emit_guardband(struct si_context *ctx)
*
* The viewport range is [-max_viewport_size/2, max_viewport_size/2].
*/
- static unsigned max_viewport_size[] = {65535, 16383, 4095};
assert(vp_as_scissor.quant_mode < ARRAY_SIZE(max_viewport_size));
max_range = max_viewport_size[vp_as_scissor.quant_mode] / 2;
left = (-max_range - vp.translate[0]) / vp.scale[0];
@@ -274,7 +283,7 @@ static void si_emit_guardband(struct si_context *ctx)
S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH +
vp_as_scissor.quant_mode));
if (initial_cdw != ctx->gfx_cs->current.cdw)
- ctx->context_roll_counter++;
+ ctx->context_roll = true;
}
static void si_emit_scissors(struct si_context *ctx)
@@ -333,6 +342,8 @@ static void si_set_viewport_states(struct pipe_context *pctx,
unsigned h = scissor->maxy - scissor->miny;
unsigned max_extent = MAX2(w, h);
+ int max_corner = MAX2(scissor->maxx, scissor->maxy);
+
unsigned center_x = (scissor->maxx + scissor->minx) / 2;
unsigned center_y = (scissor->maxy + scissor->miny) / 2;
unsigned max_center = MAX2(center_x, center_y);
@@ -358,7 +369,22 @@ static void si_set_viewport_states(struct pipe_context *pctx,
if (ctx->family == CHIP_RAVEN)
max_extent = 16384; /* Use QUANT_MODE == 16_8. */
- if (max_extent <= 1024) /* 4K scanline area for guardband */
+ /* Another constraint is that all coordinates in the viewport
+ * are representable in fixed point with respect to the
+ * surface origin.
+ *
+ * It means that PA_SU_HARDWARE_SCREEN_OFFSET can't be given
+ * an offset that would make the upper corner of the viewport
+ * greater than the maximum representable number post
+ * quantization, ie 2^quant_bits.
+ *
+ * This does not matter for 14.10 and 16.8 formats since the
+ * offset is already limited at 8k, but it means we can't use
+ * 12.12 if we are drawing to some pixels outside the lower
+ * 4k x 4k of the render target.
+ */
+
+ if (max_extent <= 1024 && max_corner < 4096) /* 4K scanline area for guardband */
scissor->quant_mode = SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH;
else if (max_extent <= 4096) /* 16K scanline area for guardband */
scissor->quant_mode = SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH;
diff --git a/src/gallium/drivers/radeonsi/si_test_dma.c b/src/gallium/drivers/radeonsi/si_test_dma.c
index 90a2032cd80..7e396e671be 100644
--- a/src/gallium/drivers/radeonsi/si_test_dma.c
+++ b/src/gallium/drivers/radeonsi/si_test_dma.c
@@ -309,7 +309,7 @@ void si_test_dma(struct si_screen *sscreen)
/* clear dst pixels */
uint32_t zero = 0;
si_clear_buffer(sctx, dst, 0, sdst->surface.surf_size, &zero, 4,
- SI_COHERENCY_SHADER);
+ SI_COHERENCY_SHADER, false);
memset(dst_cpu.ptr, 0, dst_cpu.layer_stride * tdst.array_size);
/* preparation */
diff --git a/src/gallium/drivers/softpipe/sp_screen.c b/src/gallium/drivers/softpipe/sp_screen.c
index 44e48cc7ee4..6931b52dc9f 100644
--- a/src/gallium/drivers/softpipe/sp_screen.c
+++ b/src/gallium/drivers/softpipe/sp_screen.c
@@ -265,6 +265,8 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
return 1;
case PIPE_CAP_CLEAR_TEXTURE:
return 1;
+ case PIPE_CAP_MAX_VARYINGS:
+ return TGSI_EXEC_MAX_INPUT_ATTRIBS;
case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
diff --git a/src/gallium/drivers/softpipe/sp_setup.c b/src/gallium/drivers/softpipe/sp_setup.c
index ffe49260b9a..a91e4f588c8 100644
--- a/src/gallium/drivers/softpipe/sp_setup.c
+++ b/src/gallium/drivers/softpipe/sp_setup.c
@@ -390,17 +390,6 @@ setup_sort_vertices(struct setup_context *setup,
return FALSE;
}
-
- /* Prepare pixel offset for rasterisation:
- * - pixel center (0.5, 0.5) for GL, or
- * - assume (0.0, 0.0) for other APIs.
- */
- if (setup->softpipe->rasterizer->half_pixel_center) {
- setup->pixel_offset = 0.5f;
- } else {
- setup->pixel_offset = 0.0f;
- }
-
return TRUE;
}
@@ -1476,6 +1465,16 @@ sp_setup_prepare(struct setup_context *setup)
}
}
+ /* Prepare pixel offset for rasterisation:
+ * - pixel center (0.5, 0.5) for GL, or
+ * - assume (0.0, 0.0) for other APIs.
+ */
+ if (setup->softpipe->rasterizer->half_pixel_center) {
+ setup->pixel_offset = 0.5f;
+ } else {
+ setup->pixel_offset = 0.0f;
+ }
+
setup->max_layer = max_layer;
sp->quad.first->begin( sp->quad.first );
diff --git a/src/gallium/drivers/softpipe/sp_tile_cache.c b/src/gallium/drivers/softpipe/sp_tile_cache.c
index 351736ee421..998939bdf30 100644
--- a/src/gallium/drivers/softpipe/sp_tile_cache.c
+++ b/src/gallium/drivers/softpipe/sp_tile_cache.c
@@ -373,17 +373,18 @@ sp_tile_cache_flush_clear(struct softpipe_tile_cache *tc, int layer)
if (util_format_is_pure_uint(tc->surface->format)) {
pipe_put_tile_ui_format(pt, tc->transfer_map[layer],
x, y, TILE_SIZE, TILE_SIZE,
- pt->resource->format,
+ tc->surface->format,
(unsigned *) tc->tile->data.colorui128);
} else if (util_format_is_pure_sint(tc->surface->format)) {
pipe_put_tile_i_format(pt, tc->transfer_map[layer],
x, y, TILE_SIZE, TILE_SIZE,
- pt->resource->format,
+ tc->surface->format,
(int *) tc->tile->data.colori128);
} else {
- pipe_put_tile_rgba(pt, tc->transfer_map[layer],
- x, y, TILE_SIZE, TILE_SIZE,
- (float *) tc->tile->data.color);
+ pipe_put_tile_rgba_format(pt, tc->transfer_map[layer],
+ x, y, TILE_SIZE, TILE_SIZE,
+ tc->surface->format,
+ (float *) tc->tile->data.color);
}
}
numCleared++;
diff --git a/src/gallium/drivers/svga/Makefile.sources b/src/gallium/drivers/svga/Makefile.sources
index 72024cf60e1..229d2863c84 100644
--- a/src/gallium/drivers/svga/Makefile.sources
+++ b/src/gallium/drivers/svga/Makefile.sources
@@ -15,8 +15,6 @@ C_SOURCES := \
svga_hw_reg.h \
svga_link.c \
svga_link.h \
- svga_msg.c \
- svga_msg.h \
svga_mksstats.h \
svga_pipe_blend.c \
svga_pipe_blit.c \
diff --git a/src/gallium/drivers/svga/meson.build b/src/gallium/drivers/svga/meson.build
index 7981e2991f3..4d3207a9942 100644
--- a/src/gallium/drivers/svga/meson.build
+++ b/src/gallium/drivers/svga/meson.build
@@ -27,7 +27,6 @@ files_svga = files(
'svga_draw_elements.c',
'svga_format.c',
'svga_link.c',
- 'svga_msg.c',
'svga_pipe_blend.c',
'svga_pipe_blit.c',
'svga_pipe_clear.c',
diff --git a/src/gallium/drivers/svga/svga_cmd.c b/src/gallium/drivers/svga/svga_cmd.c
index 5557d208171..6577c839cf0 100644
--- a/src/gallium/drivers/svga/svga_cmd.c
+++ b/src/gallium/drivers/svga/svga_cmd.c
@@ -1693,7 +1693,7 @@ SVGA3D_BindGBSurface(struct svga_winsys_context *swc,
return PIPE_ERROR_OUT_OF_MEMORY;
swc->surface_relocation(swc, &cmd->sid, &cmd->mobid, surface,
- SVGA_RELOC_READ | SVGA_RELOC_INTERNAL);
+ SVGA_RELOC_READ);
swc->commit(swc);
diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c
index 95dde8b0897..f747ff78bcf 100644
--- a/src/gallium/drivers/svga/svga_screen.c
+++ b/src/gallium/drivers/svga/svga_screen.c
@@ -37,7 +37,6 @@
#include "svga_public.h"
#include "svga_context.h"
#include "svga_format.h"
-#include "svga_msg.h"
#include "svga_screen.h"
#include "svga_tgsi.h"
#include "svga_resource_texture.h"
@@ -350,6 +349,8 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
return sws->have_sm4_1 ? 1 : 0; /* only single-channel textures */
+ case PIPE_CAP_MAX_VARYINGS:
+ return sws->have_vgpu10 ? VGPU10_MAX_FS_INPUTS : 10;
/* Unsupported features */
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
@@ -889,17 +890,18 @@ svga_get_driver_query_info(struct pipe_screen *screen,
static void
init_logging(struct pipe_screen *screen)
{
+ struct svga_screen *svgascreen = svga_screen(screen);
static const char *log_prefix = "Mesa: ";
char host_log[1000];
/* Log Version to Host */
util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
- "%s%s", log_prefix, svga_get_name(screen));
- svga_host_log(host_log);
+ "%s%s\n", log_prefix, svga_get_name(screen));
+ svgascreen->sws->host_log(svgascreen->sws, host_log);
util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
"%s" PACKAGE_VERSION MESA_GIT_SHA1, log_prefix);
- svga_host_log(host_log);
+ svgascreen->sws->host_log(svgascreen->sws, host_log);
/* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
* line (program name and arguments).
@@ -908,13 +910,23 @@ init_logging(struct pipe_screen *screen)
char cmdline[1000];
if (os_get_command_line(cmdline, sizeof(cmdline))) {
util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
- "%s%s", log_prefix, cmdline);
- svga_host_log(host_log);
+ "%s%s\n", log_prefix, cmdline);
+ svgascreen->sws->host_log(svgascreen->sws, host_log);
}
}
}
+/**
+ * no-op logging function to use when SVGA_NO_LOGGING is set.
+ */
+static void
+nop_host_log(struct svga_winsys_screen *sws, const char *message)
+{
+ /* nothing */
+}
+
+
static void
svga_destroy_screen( struct pipe_screen *screen )
{
@@ -1132,7 +1144,11 @@ svga_screen_create(struct svga_winsys_screen *sws)
svga_screen_cache_init(svgascreen);
- init_logging(screen);
+ if (debug_get_bool_option("SVGA_NO_LOGGING", FALSE) == TRUE) {
+ svgascreen->sws->host_log = nop_host_log;
+ } else {
+ init_logging(screen);
+ }
return screen;
error2:
diff --git a/src/gallium/drivers/svga/svga_winsys.h b/src/gallium/drivers/svga/svga_winsys.h
index a067a7ba09d..14782e19a7d 100644
--- a/src/gallium/drivers/svga/svga_winsys.h
+++ b/src/gallium/drivers/svga/svga_winsys.h
@@ -753,6 +753,11 @@ struct svga_winsys_screen
void
(*stats_time_pop)();
+ /**
+ * Send a host log message
+ */
+ void
+ (*host_log)(struct svga_winsys_screen *sws, const char *message);
/** Have VGPU v10 hardware? */
boolean have_vgpu10;
diff --git a/src/gallium/drivers/swr/swr_screen.cpp b/src/gallium/drivers/swr/swr_screen.cpp
index de9008ddf6a..bee011e4abf 100644
--- a/src/gallium/drivers/swr/swr_screen.cpp
+++ b/src/gallium/drivers/swr/swr_screen.cpp
@@ -369,6 +369,8 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
return 32;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
return 1 << 27;
+ case PIPE_CAP_MAX_VARYINGS:
+ return 32;
case PIPE_CAP_VENDOR_ID:
return 0xFFFFFFFF;
@@ -844,7 +846,9 @@ swr_texture_layout(struct swr_screen *screen,
size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
res->swr.pitch * res->swr.numSamples;
- if (total_size > SWR_MAX_TEXTURE_SIZE)
+
+ // Let non-sampled textures (e.g. buffer objects) bypass the size limit
+ if (swr_resource_is_texture(&res->base) && total_size > SWR_MAX_TEXTURE_SIZE)
return false;
if (allocate) {
diff --git a/src/gallium/drivers/v3d/v3d_blit.c b/src/gallium/drivers/v3d/v3d_blit.c
index 2f36bdd46e3..d42e8fd0e69 100644
--- a/src/gallium/drivers/v3d/v3d_blit.c
+++ b/src/gallium/drivers/v3d/v3d_blit.c
@@ -491,7 +491,8 @@ v3d_tfu_blit(struct pipe_context *pctx, const struct pipe_blit_info *info)
if ((info->mask & PIPE_MASK_RGBA) == 0)
return false;
- if (info->dst.box.x != 0 ||
+ if (info->scissor_enable ||
+ info->dst.box.x != 0 ||
info->dst.box.y != 0 ||
info->dst.box.width != dst_width ||
info->dst.box.height != dst_height ||
diff --git a/src/gallium/drivers/v3d/v3d_resource.c b/src/gallium/drivers/v3d/v3d_resource.c
index 21c68942e14..84e86799d5e 100644
--- a/src/gallium/drivers/v3d/v3d_resource.c
+++ b/src/gallium/drivers/v3d/v3d_resource.c
@@ -780,7 +780,7 @@ v3d_resource_create_with_modifiers(struct pipe_screen *pscreen,
rsc->tiled = false;
} else {
fprintf(stderr, "Unsupported modifier requested\n");
- return NULL;
+ goto fail;
}
rsc->internal_format = prsc->format;
diff --git a/src/gallium/drivers/v3d/v3d_screen.c b/src/gallium/drivers/v3d/v3d_screen.c
index bed2c63a64d..17afeebb4fc 100644
--- a/src/gallium/drivers/v3d/v3d_screen.c
+++ b/src/gallium/drivers/v3d/v3d_screen.c
@@ -70,6 +70,7 @@ v3d_screen_destroy(struct pipe_screen *pscreen)
util_hash_table_destroy(screen->bo_handles);
v3d_bufmgr_destroy(pscreen);
slab_destroy_parent(&screen->transfer_pool);
+ free(screen->ro);
if (using_v3d_simulator)
v3d_simulator_destroy(screen);
@@ -177,11 +178,17 @@ v3d_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
return 4;
+ case PIPE_CAP_MAX_VARYINGS:
+ return V3D_MAX_FS_INPUTS / 4;
+
/* Texturing. */
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
- return V3D_MAX_MIP_LEVELS;
+ if (screen->devinfo.ver < 40)
+ return 12;
+ else
+ return V3D_MAX_MIP_LEVELS;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
return 2048;
diff --git a/src/gallium/drivers/v3d/v3dx_draw.c b/src/gallium/drivers/v3d/v3dx_draw.c
index 2700208e388..4b1b03b5db5 100644
--- a/src/gallium/drivers/v3d/v3dx_draw.c
+++ b/src/gallium/drivers/v3d/v3dx_draw.c
@@ -55,7 +55,28 @@ v3d_start_draw(struct v3d_context *v3d)
job->submit.bcl_start = job->bcl.bo->offset;
v3d_job_add_bo(job, job->bcl.bo);
- job->tile_alloc = v3d_bo_alloc(v3d->screen, 1024 * 1024, "tile_alloc");
+ /* The PTB will request the tile alloc initial size per tile at start
+ * of tile binning.
+ */
+ uint32_t tile_alloc_size = (job->draw_tiles_x *
+ job->draw_tiles_y) * 64;
+ /* The PTB allocates in aligned 4k chunks after the initial setup. */
+ tile_alloc_size = align(tile_alloc_size, 4096);
+
+ /* Include the first two chunk allocations that the PTB does so that
+ * we definitely clear the OOM condition before triggering one (the HW
+ * won't trigger OOM during the first allocations).
+ */
+ tile_alloc_size += 8192;
+
+ /* For performance, allocate some extra initial memory after the PTB's
+ * minimal allocations, so that we hopefully don't have to block the
+ * GPU on the kernel handling an OOM signal.
+ */
+ tile_alloc_size += 512 * 1024;
+
+ job->tile_alloc = v3d_bo_alloc(v3d->screen, tile_alloc_size,
+ "tile_alloc");
uint32_t tsda_per_tile_size = v3d->screen->devinfo.ver >= 40 ? 256 : 64;
job->tile_state = v3d_bo_alloc(v3d->screen,
job->draw_tiles_y *
@@ -203,8 +224,13 @@ v3d_emit_gl_shader_state(struct v3d_context *v3d,
* shader needs to write the Z value (even just discards).
*/
shader.fragment_shader_does_z_writes =
- (v3d->prog.fs->prog_data.fs->writes_z ||
- v3d->prog.fs->prog_data.fs->discard);
+ v3d->prog.fs->prog_data.fs->writes_z;
+ /* Set if the EZ test must be disabled (due to shader side
+ * effects and the early_z flag not being present in the
+ * shader).
+ */
+ shader.turn_off_early_z_test =
+ v3d->prog.fs->prog_data.fs->disable_ez;
shader.fragment_shader_uses_real_pixel_centre_w_in_addition_to_centroid_w2 =
v3d->prog.fs->prog_data.fs->uses_center_w;
diff --git a/src/gallium/drivers/v3d/v3dx_state.c b/src/gallium/drivers/v3d/v3dx_state.c
index f326b5379ba..eff6bcfca06 100644
--- a/src/gallium/drivers/v3d/v3dx_state.c
+++ b/src/gallium/drivers/v3d/v3dx_state.c
@@ -846,6 +846,9 @@ v3d_setup_texture_shader_state(struct V3DX(TEXTURE_SHADER_STATE) *tex,
prsc->target == PIPE_TEXTURE_1D_ARRAY) {
tex->image_height = tex->image_width >> 14;
}
+
+ tex->image_width &= (1 << 14) - 1;
+ tex->image_height &= (1 << 14) - 1;
#endif
if (prsc->target == PIPE_TEXTURE_3D) {
diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c
index 2d0a52bb5fb..8f1e561c444 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -1591,7 +1591,7 @@ vc4_optimize_nir(struct nir_shader *s)
NIR_PASS(progress, s, nir_opt_dce);
NIR_PASS(progress, s, nir_opt_dead_cf);
NIR_PASS(progress, s, nir_opt_cse);
- NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
+ NIR_PASS(progress, s, nir_opt_peephole_select, 8, true);
NIR_PASS(progress, s, nir_opt_algebraic);
NIR_PASS(progress, s, nir_opt_constant_folding);
NIR_PASS(progress, s, nir_opt_undef);
diff --git a/src/gallium/drivers/vc4/vc4_query.c b/src/gallium/drivers/vc4/vc4_query.c
index 6e4681e93cc..f08785f457f 100644
--- a/src/gallium/drivers/vc4/vc4_query.c
+++ b/src/gallium/drivers/vc4/vc4_query.c
@@ -132,7 +132,7 @@ vc4_create_batch_query(struct pipe_context *pctx, unsigned num_queries,
/* We can't mix HW and non-HW queries. */
if (nhwqueries && nhwqueries != num_queries)
- return NULL;
+ goto err_free_query;
if (!nhwqueries)
return (struct pipe_query *)query;
diff --git a/src/gallium/drivers/vc4/vc4_screen.c b/src/gallium/drivers/vc4/vc4_screen.c
index e7f7c82c271..acb4a1feb0d 100644
--- a/src/gallium/drivers/vc4/vc4_screen.c
+++ b/src/gallium/drivers/vc4/vc4_screen.c
@@ -178,6 +178,9 @@ vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
/* Note: Not supported in hardware, just faking it. */
return 5;
+ case PIPE_CAP_MAX_VARYINGS:
+ return 8;
+
case PIPE_CAP_VENDOR_ID:
return 0x14E4;
case PIPE_CAP_ACCELERATED:
diff --git a/src/gallium/drivers/virgl/virgl_context.c b/src/gallium/drivers/virgl/virgl_context.c
index 08f85f8574a..f9d8e231a13 100644
--- a/src/gallium/drivers/virgl/virgl_context.c
+++ b/src/gallium/drivers/virgl/virgl_context.c
@@ -765,7 +765,6 @@ static void virgl_flush_from_st(struct pipe_context *ctx,
enum pipe_flush_flags flags)
{
struct virgl_context *vctx = virgl_context(ctx);
- struct virgl_screen *rs = virgl_screen(ctx->screen);
if (flags & PIPE_FLUSH_FENCE_FD)
vctx->cbuf->needs_out_fence_fd = true;
diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c
index 42e0987e0c9..17fa5fc51cc 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -258,6 +258,10 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
return 1; /* TODO: need to introduce a hw-cap for this */
+ case PIPE_CAP_MAX_VARYINGS:
+ if (vscreen->caps.caps.v1.glsl_level < 150)
+ return vscreen->caps.caps.v2.max_vertex_attribs;
+ return 32;
case PIPE_CAP_TEXTURE_GATHER_SM5:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_FAKE_SW_MSAA:
diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h
index 867d0cb5d74..96e8fbed1be 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -856,6 +856,7 @@ enum pipe_cap
PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE,
PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND,
PIPE_CAP_DEST_SURFACE_SRGB_CONTROL,
+ PIPE_CAP_MAX_VARYINGS,
};
/**
diff --git a/src/gallium/include/pipe/p_video_enums.h b/src/gallium/include/pipe/p_video_enums.h
index b5b8b062285..adbe7858d0f 100644
--- a/src/gallium/include/pipe/p_video_enums.h
+++ b/src/gallium/include/pipe/p_video_enums.h
@@ -70,7 +70,8 @@ enum pipe_video_profile
PIPE_VIDEO_PROFILE_HEVC_MAIN_444,
PIPE_VIDEO_PROFILE_JPEG_BASELINE,
PIPE_VIDEO_PROFILE_VP9_PROFILE0,
- PIPE_VIDEO_PROFILE_VP9_PROFILE2
+ PIPE_VIDEO_PROFILE_VP9_PROFILE2,
+ PIPE_VIDEO_PROFILE_MAX
};
/* Video caps, can be different for each codec/profile */
diff --git a/src/gallium/state_trackers/dri/dri2.c b/src/gallium/state_trackers/dri/dri2.c
index ebbbabb6492..930d440a1e2 100644
--- a/src/gallium/state_trackers/dri/dri2.c
+++ b/src/gallium/state_trackers/dri/dri2.c
@@ -994,11 +994,6 @@ dri2_create_image_common(__DRIscreen *_screen,
if (!map)
return NULL;
- /* createImageWithModifiers doesn't supply usage, and we should not get
- * here with both modifiers and a usage flag.
- */
- assert(!(use && (modifiers != NULL)));
-
tex_usage = PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW;
if (use & __DRI_IMAGE_USE_SCANOUT)
@@ -1071,7 +1066,7 @@ dri2_create_image_with_modifiers(__DRIscreen *dri_screen,
void *loaderPrivate)
{
return dri2_create_image_common(dri_screen, width, height, format,
- 0 /* use */, modifiers, count,
+ __DRI_IMAGE_USE_SHARE, modifiers, count,
loaderPrivate);
}
diff --git a/src/gallium/state_trackers/glx/xlib/meson.build b/src/gallium/state_trackers/glx/xlib/meson.build
index f4ee75426bc..34b93c94cf2 100644
--- a/src/gallium/state_trackers/glx/xlib/meson.build
+++ b/src/gallium/state_trackers/glx/xlib/meson.build
@@ -23,5 +23,5 @@ libxlib = static_library(
files('glx_api.c', 'glx_getproc.c', 'glx_usefont.c', 'xm_api.c', 'xm_st.c'),
c_args : c_vis_args,
include_directories : [inc_common, inc_mapi, inc_mesa],
- dependencies : [dep_x11, dep_xext, dep_xcb],
+ dependencies : [dep_x11, dep_xext, dep_xcb, dep_glproto],
)
diff --git a/src/gallium/state_trackers/nine/nine_pipe.h b/src/gallium/state_trackers/nine/nine_pipe.h
index 7b68c09c47a..0595da5535a 100644
--- a/src/gallium/state_trackers/nine/nine_pipe.h
+++ b/src/gallium/state_trackers/nine/nine_pipe.h
@@ -377,6 +377,10 @@ d3dmultisample_type_check(struct pipe_screen *screen,
if (levels)
*levels = 1;
+ /* Ignores multisamplequality */
+ if (*multisample == D3DMULTISAMPLE_NONE)
+ return D3D_OK;
+
if (*multisample == D3DMULTISAMPLE_NONMASKABLE) {
if (depth_stencil_format(format))
bind = d3d9_get_pipe_depth_format_bindings(format);
diff --git a/src/gallium/state_trackers/nine/swapchain9.c b/src/gallium/state_trackers/nine/swapchain9.c
index 6c22be24c7c..8026ee16b7a 100644
--- a/src/gallium/state_trackers/nine/swapchain9.c
+++ b/src/gallium/state_trackers/nine/swapchain9.c
@@ -133,6 +133,13 @@ D3DWindowBuffer_release(struct NineSwapChain9 *This,
D3DWindowBuffer *present_handle)
{
int i;
+
+ /* IsBufferReleased API not available */
+ if (This->base.device->minor_version_num <= 2) {
+ ID3DPresent_DestroyD3DWindowBuffer(This->present, present_handle);
+ return;
+ }
+
/* Add it to the 'pending release' list */
for (i = 0; i < D3DPRESENT_BACK_BUFFERS_MAX_EX + 1; i++) {
if (!This->present_handles_pending_release[i]) {
@@ -750,9 +757,19 @@ present( struct NineSwapChain9 *This,
if (This->params.SwapEffect == D3DSWAPEFFECT_DISCARD)
handle_draw_cursor_and_hud(This, resource);
- ID3DPresent_GetWindowInfo(This->present, hDestWindowOverride, &target_width, &target_height, &target_depth);
+ hr = ID3DPresent_GetWindowInfo(This->present, hDestWindowOverride, &target_width, &target_height, &target_depth);
(void)target_depth;
+ /* Can happen with old Wine (presentation can still succeed),
+ * or at window destruction.
+ * Also disable for very old wine as D3DWindowBuffer_release
+ * cannot do the DestroyD3DWindowBuffer workaround. */
+ if (FAILED(hr) || target_width == 0 || target_height == 0 ||
+ This->base.device->minor_version_num <= 2) {
+ target_width = resource->width0;
+ target_height = resource->height0;
+ }
+
/* Switch to using presentation buffers on window resize.
* Note: Most apps should resize the d3d back buffers when
* a window resize is detected, which will result in a call to
diff --git a/src/gallium/state_trackers/va/context.c b/src/gallium/state_trackers/va/context.c
index 14e904ee490..47a5e7be230 100644
--- a/src/gallium/state_trackers/va/context.c
+++ b/src/gallium/state_trackers/va/context.c
@@ -175,7 +175,7 @@ VA_DRIVER_INIT_FUNC(VADriverContextP ctx)
ctx->version_minor = 1;
*ctx->vtable = vtable;
*ctx->vtable_vpp = vtable_vpp;
- ctx->max_profiles = PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH - PIPE_VIDEO_PROFILE_UNKNOWN;
+ ctx->max_profiles = PIPE_VIDEO_PROFILE_MAX - PIPE_VIDEO_PROFILE_UNKNOWN - 1;
ctx->max_entrypoints = 2;
ctx->max_attributes = 1;
ctx->max_image_formats = VL_VA_MAX_IMAGE_FORMATS;
diff --git a/src/gallium/state_trackers/va/picture_mpeg12.c b/src/gallium/state_trackers/va/picture_mpeg12.c
index 1e5a9c7428d..daf95f7403c 100644
--- a/src/gallium/state_trackers/va/picture_mpeg12.c
+++ b/src/gallium/state_trackers/va/picture_mpeg12.c
@@ -27,6 +27,19 @@
#include "va_private.h"
+const int reverse_inverse_zscan[] =
+{
+ /* Reverse inverse z scan pattern */
+ 0, 2, 3, 9, 10, 20, 21, 35,
+ 1, 4, 8, 11, 19, 22, 34, 36,
+ 5, 7, 12, 18, 23, 33, 37, 48,
+ 6, 13, 17, 24, 32, 38, 47, 49,
+ 14, 16, 25, 31, 39, 46, 50, 57,
+ 15, 26, 30, 40, 45, 51, 56, 58,
+ 27, 29, 41, 44, 52, 55, 59, 62,
+ 28, 42, 43, 53, 54, 60, 61, 63,
+};
+
void vlVaHandlePictureParameterBufferMPEG12(vlVaDriver *drv, vlVaContext *context, vlVaBuffer *buf)
{
VAPictureParameterBufferMPEG2 *mpeg2 = buf->data;
@@ -66,16 +79,29 @@ void vlVaHandlePictureParameterBufferMPEG12(vlVaDriver *drv, vlVaContext *contex
void vlVaHandleIQMatrixBufferMPEG12(vlVaContext *context, vlVaBuffer *buf)
{
VAIQMatrixBufferMPEG2 *mpeg2 = buf->data;
+ static uint8_t temp_intra_matrix[64];
+ static uint8_t temp_nonintra_matrix[64];
assert(buf->size >= sizeof(VAIQMatrixBufferMPEG2) && buf->num_elements == 1);
- if (mpeg2->load_intra_quantiser_matrix)
- context->desc.mpeg12.intra_matrix = mpeg2->intra_quantiser_matrix;
- else
+ if (mpeg2->load_intra_quantiser_matrix) {
+ /* The quantiser matrix that VAAPI provides has been applied
+ with inverse z-scan. However, what we expect in MPEG2
+ picture description is the original order. Therefore,
+ we need to reverse it back to its original order.
+ */
+ for (int i = 0; i < 64; i++)
+ temp_intra_matrix[i] =
+ mpeg2->intra_quantiser_matrix[reverse_inverse_zscan[i]];
+ context->desc.mpeg12.intra_matrix = temp_intra_matrix;
+ } else
context->desc.mpeg12.intra_matrix = NULL;
- if (mpeg2->load_non_intra_quantiser_matrix)
- context->desc.mpeg12.non_intra_matrix = mpeg2->non_intra_quantiser_matrix;
- else
+ if (mpeg2->load_non_intra_quantiser_matrix) {
+ for (int i = 0; i < 64; i++)
+ temp_nonintra_matrix[i] =
+ mpeg2->non_intra_quantiser_matrix[reverse_inverse_zscan[i]];
+ context->desc.mpeg12.non_intra_matrix = temp_nonintra_matrix;
+ } else
context->desc.mpeg12.non_intra_matrix = NULL;
}
diff --git a/src/gallium/state_trackers/va/picture_vp9.c b/src/gallium/state_trackers/va/picture_vp9.c
index c1ca54cd008..b5aca9a513c 100644
--- a/src/gallium/state_trackers/va/picture_vp9.c
+++ b/src/gallium/state_trackers/va/picture_vp9.c
@@ -28,6 +28,8 @@
#include "vl/vl_vlc.h"
#include "va_private.h"
+#define NUM_VP9_REFS 8
+
void vlVaHandlePictureParameterBufferVP9(vlVaDriver *drv, vlVaContext *context, vlVaBuffer *buf)
{
VADecPictureParameterBufferVP9 *vp9 = buf->data;
@@ -79,8 +81,11 @@ void vlVaHandlePictureParameterBufferVP9(vlVaDriver *drv, vlVaContext *context,
context->desc.vp9.picture_parameter.bit_depth = vp9->bit_depth;
- for (i = 0 ; i < 8 ; i++)
+ for (i = 0 ; i < NUM_VP9_REFS ; i++)
vlVaGetReferenceFrame(drv, vp9->reference_frames[i], &context->desc.vp9.ref[i]);
+
+ if (!context->decoder && !context->templat.max_references)
+ context->templat.max_references = NUM_VP9_REFS;
}
void vlVaHandleSliceParameterBufferVP9(vlVaContext *context, vlVaBuffer *buf)
diff --git a/src/gallium/state_trackers/xvmc/attributes.c b/src/gallium/state_trackers/xvmc/attributes.c
index 375705669b0..6e4d78a9a29 100644
--- a/src/gallium/state_trackers/xvmc/attributes.c
+++ b/src/gallium/state_trackers/xvmc/attributes.c
@@ -90,15 +90,15 @@ Status XvMCSetAttribute(Display *dpy, XvMCContext *context, Atom attribute, int
if (!attr)
return XvMCBadContext;
- if (strcmp(attr, XV_BRIGHTNESS))
+ if (strcmp(attr, XV_BRIGHTNESS) == 0)
context_priv->procamp.brightness = value / 1000.0f;
- else if (strcmp(attr, XV_CONTRAST))
+ else if (strcmp(attr, XV_CONTRAST) == 0)
context_priv->procamp.contrast = value / 1000.0f + 1.0f;
- else if (strcmp(attr, XV_SATURATION))
+ else if (strcmp(attr, XV_SATURATION) == 0)
context_priv->procamp.saturation = value / 1000.0f + 1.0f;
- else if (strcmp(attr, XV_HUE))
+ else if (strcmp(attr, XV_HUE) == 0)
context_priv->procamp.hue = value / 1000.0f;
- else if (strcmp(attr, XV_COLORSPACE))
+ else if (strcmp(attr, XV_COLORSPACE) == 0)
context_priv->color_standard = value ?
VL_CSC_COLOR_STANDARD_BT_601 :
VL_CSC_COLOR_STANDARD_BT_709;
@@ -134,15 +134,15 @@ Status XvMCGetAttribute(Display *dpy, XvMCContext *context, Atom attribute, int
if (!attr)
return XvMCBadContext;
- if (strcmp(attr, XV_BRIGHTNESS))
+ if (strcmp(attr, XV_BRIGHTNESS) == 0)
*value = context_priv->procamp.brightness * 1000;
- else if (strcmp(attr, XV_CONTRAST))
+ else if (strcmp(attr, XV_CONTRAST) == 0)
*value = context_priv->procamp.contrast * 1000 - 1000;
- else if (strcmp(attr, XV_SATURATION))
+ else if (strcmp(attr, XV_SATURATION) == 0)
*value = context_priv->procamp.saturation * 1000 + 1000;
- else if (strcmp(attr, XV_HUE))
+ else if (strcmp(attr, XV_HUE) == 0)
*value = context_priv->procamp.hue * 1000;
- else if (strcmp(attr, XV_COLORSPACE))
+ else if (strcmp(attr, XV_COLORSPACE) == 0)
*value = context_priv->color_standard == VL_CSC_COLOR_STANDARD_BT_709;
else
return BadName;
diff --git a/src/gallium/state_trackers/xvmc/tests/xvmc_bench.c b/src/gallium/state_trackers/xvmc/tests/xvmc_bench.c
index 3cd23173c7c..dbd705639f6 100644
--- a/src/gallium/state_trackers/xvmc/tests/xvmc_bench.c
+++ b/src/gallium/state_trackers/xvmc/tests/xvmc_bench.c
@@ -123,11 +123,11 @@ void ParseArgs(int argc, char **argv, struct Config *config)
while (token && !fail)
{
- if (strcmp(token, "i"))
+ if (strcmp(token, "i") == 0)
config->mb_types |= MB_TYPE_I;
- else if (strcmp(token, "p"))
+ else if (strcmp(token, "p") == 0)
config->mb_types |= MB_TYPE_P;
- else if (strcmp(token, "b"))
+ else if (strcmp(token, "b") == 0)
config->mb_types |= MB_TYPE_B;
else
fail = 1;
diff --git a/src/gallium/targets/d3dadapter9/meson.build b/src/gallium/targets/d3dadapter9/meson.build
index bc72b1110a0..b3c31c5dc6d 100644
--- a/src/gallium/targets/d3dadapter9/meson.build
+++ b/src/gallium/targets/d3dadapter9/meson.build
@@ -68,5 +68,5 @@ pkg.generate(
description : 'Native D3D driver modules',
version : '.'.join(nine_version),
requires_private : 'libdrm >= ' + dep_libdrm.version(),
- variables : ['moduledir=${prefix}/@0@'.format(d3d_drivers_path)],
+ variables : ['moduledir=@0@'.format(d3d_drivers_path)],
)
diff --git a/src/gallium/targets/dri/Android.mk b/src/gallium/targets/dri/Android.mk
index 9c43fa1e8fd..6134251b5ca 100644
--- a/src/gallium/targets/dri/Android.mk
+++ b/src/gallium/targets/dri/Android.mk
@@ -40,12 +40,23 @@ LOCAL_LDFLAGS := \
-Wl,--undefined-version
LOCAL_SHARED_LIBRARIES := \
- libbacktrace \
libdl \
libglapi \
- libexpat \
libz
+# If Android version >=8 MESA should static link libexpat else should dynamic link
+ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0)
+LOCAL_STATIC_LIBRARIES := \
+ libexpat
+else
+LOCAL_SHARED_LIBRARIES += \
+ libexpat
+endif
+
+ifeq ($(USE_LIBBACKTRACE),true)
+ LOCAL_SHARED_LIBRARIES += libbacktrace
+endif
+
$(foreach d, $(MESA_BUILD_GALLIUM), $(eval LOCAL_CFLAGS += $(patsubst HAVE_%,-D%,$(d))))
# sort GALLIUM_LIBS to remove any duplicates
diff --git a/src/gallium/targets/dri/meson.build b/src/gallium/targets/dri/meson.build
index 68d226621b2..edd0c007e48 100644
--- a/src/gallium/targets/dri/meson.build
+++ b/src/gallium/targets/dri/meson.build
@@ -60,6 +60,10 @@ libgallium_dri = shared_library(
driver_tegra, driver_i915, driver_svga, driver_virgl,
driver_swr,
],
+ # Will be deleted during installation, see install_megadrivers.py
+ install : true,
+ install_dir : dri_drivers_path,
+ name_suffix : 'so',
)
foreach d : [[with_gallium_kmsro, 'pl111_dri.so'],
diff --git a/src/gallium/targets/omx/meson.build b/src/gallium/targets/omx/meson.build
index 6811e6ff904..7772ae47bb5 100644
--- a/src/gallium/targets/omx/meson.build
+++ b/src/gallium/targets/omx/meson.build
@@ -32,7 +32,7 @@ endif
libomx_gallium = shared_library(
'omx_mesa',
- 'target.c',
+ ['target.c', xmlpool_options_h],
c_args : c_vis_args,
cpp_args : cpp_vis_args,
link_args : [omx_link_args, ld_args_gc_sections],
diff --git a/src/gallium/targets/osmesa/meson.build b/src/gallium/targets/osmesa/meson.build
index b4ae8f4b6ec..e873e311aa0 100644
--- a/src/gallium/targets/osmesa/meson.build
+++ b/src/gallium/targets/osmesa/meson.build
@@ -43,9 +43,9 @@ libosmesa = shared_library(
inc_gallium_drivers,
],
link_depends : osmesa_link_deps,
- link_whole : [libosmesa_st],
+ link_whole : [libosmesa_st, libglapi_static],
link_with : [
- libmesa_gallium, libgallium, libglapi_static, libws_null, osmesa_link_with,
+ libmesa_gallium, libgallium, libws_null, osmesa_link_with,
],
dependencies : [
dep_selinux, dep_thread, dep_clock, dep_unwind,
diff --git a/src/gallium/targets/va/meson.build b/src/gallium/targets/va/meson.build
index ded689b464d..4bfb5cbab7a 100644
--- a/src/gallium/targets/va/meson.build
+++ b/src/gallium/targets/va/meson.build
@@ -33,7 +33,7 @@ endif
libva_gallium = shared_library(
'gallium_drv_video',
- 'target.c',
+ ['target.c', xmlpool_options_h],
c_args : c_vis_args,
cpp_args : cpp_vis_args,
link_args : [va_link_args, ld_args_gc_sections],
@@ -49,8 +49,10 @@ libva_gallium = shared_library(
dep_libdrm, dep_thread, driver_r600, driver_radeonsi, driver_nouveau,
],
link_depends : va_link_depends,
+ # Will be deleted during installation, see install_megadrivers.py
install : true,
install_dir : va_drivers_path,
+ name_suffix : 'so',
)
foreach d : [[with_gallium_r600, 'r600'],
diff --git a/src/gallium/targets/vdpau/meson.build b/src/gallium/targets/vdpau/meson.build
index 22e3f5ffdd8..48f01ffba6c 100644
--- a/src/gallium/targets/vdpau/meson.build
+++ b/src/gallium/targets/vdpau/meson.build
@@ -38,7 +38,7 @@ endif
libvdpau_gallium = shared_library(
'vdpau_gallium',
- 'target.c',
+ ['target.c', xmlpool_options_h],
c_args : c_vis_args,
cpp_args : cpp_vis_args,
link_args : [vdpau_link_args, ld_args_gc_sections],
@@ -55,6 +55,10 @@ libvdpau_gallium = shared_library(
],
link_depends : vdpau_link_depends,
soversion : '@0@.@1@.0'.format(VDPAU_MAJOR, VDPAU_MINOR),
+ # Will be deleted during installation, see install_megadrivers.py
+ install : true,
+ install_dir : vdpau_drivers_path,
+ name_suffix : 'so',
)
foreach d : [[with_gallium_r300, 'r300'],
[with_gallium_r600, 'r600'],
diff --git a/src/gallium/targets/xa/meson.build b/src/gallium/targets/xa/meson.build
index 733ef54ff85..582d5ef67f6 100644
--- a/src/gallium/targets/xa/meson.build
+++ b/src/gallium/targets/xa/meson.build
@@ -34,7 +34,7 @@ _xa_version = '.'.join(xa_version)
libxatracker = shared_library(
'xatracker',
- 'target.c',
+ ['target.c', xmlpool_options_h],
c_args : c_vis_args,
cpp_args : cpp_vis_args,
link_args : [xa_link_args, ld_args_gc_sections],
diff --git a/src/gallium/targets/xvmc/meson.build b/src/gallium/targets/xvmc/meson.build
index 0af5b6477ce..537275aab57 100644
--- a/src/gallium/targets/xvmc/meson.build
+++ b/src/gallium/targets/xvmc/meson.build
@@ -33,7 +33,7 @@ endif
libxvmc_gallium = shared_library(
'XvMCgallium',
- 'target.c',
+ ['target.c', xmlpool_options_h],
c_args : c_vis_args,
cpp_args : cpp_vis_args,
link_args : [xvmc_link_args, ld_args_gc_sections],
@@ -47,6 +47,10 @@ libxvmc_gallium = shared_library(
],
dependencies : [dep_thread, driver_r600, driver_nouveau],
link_depends : xvmc_link_depends,
+ # Will be deleted during installation, see install_megadrivers.py
+ install : true,
+ install_dir : xvmc_drivers_path,
+ name_suffix : 'so',
)
foreach d : [[with_gallium_r600, 'r600'], [with_gallium_nouveau, 'nouveau']]
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index b4e62acbae4..2e595e5a1b0 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -386,7 +386,8 @@ static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context *cs)
cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCE &&
cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD_ENC &&
cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_DEC &&
- cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_ENC;
+ cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_ENC &&
+ cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_JPEG;
}
static bool amdgpu_cs_has_chaining(struct amdgpu_cs *cs)
@@ -1219,8 +1220,6 @@ static void amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs *acs)
{
struct amdgpu_cs_context *cs = acs->csc;
- cs->num_fence_dependencies = 0;
-
amdgpu_add_fence_dependencies_bo_list(acs, cs->fence, cs->num_real_buffers, cs->real_buffers);
amdgpu_add_fence_dependencies_bo_list(acs, cs->fence, cs->num_slab_buffers, cs->slab_buffers);
amdgpu_add_fence_dependencies_bo_list(acs, cs->fence, cs->num_sparse_buffers, cs->sparse_buffers);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 79d2c1345ef..45e54b4791d 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -92,6 +92,10 @@ static bool do_winsys_init(struct amdgpu_winsys *ws,
if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
goto fail;
+ /* TODO: Enable this once the kernel handles it efficiently. */
+ if (ws->info.has_dedicated_vram)
+ ws->info.has_local_buffers = false;
+
handle_env_var_force_family(ws);
ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
diff --git a/src/gallium/winsys/svga/drm/Makefile.sources b/src/gallium/winsys/svga/drm/Makefile.sources
index f82b0097b5b..191f0b88b4a 100644
--- a/src/gallium/winsys/svga/drm/Makefile.sources
+++ b/src/gallium/winsys/svga/drm/Makefile.sources
@@ -8,6 +8,8 @@ C_SOURCES := \
vmw_fence.c \
vmw_fence.h \
vmwgfx_drm.h \
+ vmw_msg.c \
+ vmw_msg.h \
vmw_screen.c \
vmw_screen_dri.c \
vmw_screen.h \
diff --git a/src/gallium/winsys/svga/drm/meson.build b/src/gallium/winsys/svga/drm/meson.build
index 24f67aca9ec..55266ce1623 100644
--- a/src/gallium/winsys/svga/drm/meson.build
+++ b/src/gallium/winsys/svga/drm/meson.build
@@ -23,6 +23,7 @@ files_svgadrm = files(
'vmw_buffer.c',
'vmw_context.c',
'vmw_fence.c',
+ 'vmw_msg.c',
'vmw_screen.c',
'vmw_screen_dri.c',
'vmw_screen_ioctl.c',
diff --git a/src/gallium/drivers/svga/svga_msg.c b/src/gallium/winsys/svga/drm/vmw_msg.c
old mode 100755
new mode 100644
similarity index 93%
rename from src/gallium/drivers/svga/svga_msg.c
rename to src/gallium/winsys/svga/drm/vmw_msg.c
index 8b63132cb57..8cce2241f36
--- a/src/gallium/drivers/svga/svga_msg.c
+++ b/src/gallium/winsys/svga/drm/vmw_msg.c
@@ -29,7 +29,8 @@
#include "util/u_memory.h"
#include "util/u_string.h"
#include "pipe/p_defines.h"
-#include "svga_msg.h"
+#include "svga_winsys.h"
+#include "vmw_msg.h"
#define MESSAGE_STATUS_SUCCESS 0x0001
@@ -83,7 +84,7 @@
port_num, magic, \
ax, bx, cx, dx, si, di) \
({ \
- __asm__ volatile ("inl %%dx, %%eax;" : \
+ __asm__ volatile ("inl %%dx, %%eax;" : \
"=a"(ax), \
"=b"(bx), \
"=c"(cx), \
@@ -128,7 +129,7 @@ typedef uint64_t VMW_REG;
port_num, magic, bp, \
ax, bx, cx, dx, si, di) \
({ \
- __asm__ volatile ("push %%rbp;" \
+ __asm__ volatile ("push %%rbp;" \
"movq %12, %%rbp;" \
"rep outsb;" \
"pop %%rbp;" : \
@@ -152,7 +153,7 @@ typedef uint64_t VMW_REG;
port_num, magic, bp, \
ax, bx, cx, dx, si, di) \
({ \
- __asm__ volatile ("push %%rbp;" \
+ __asm__ volatile ("push %%rbp;" \
"movq %12, %%rbp;" \
"rep insb;" \
"pop %%rbp" : \
@@ -183,7 +184,7 @@ typedef uint32_t VMW_REG;
port_num, magic, bp, \
ax, bx, cx, dx, si, di) \
({ \
- __asm__ volatile ("push %%ebp;" \
+ __asm__ volatile ("push %%ebp;" \
"mov %12, %%ebp;" \
"rep outsb;" \
"pop %%ebp;" : \
@@ -208,7 +209,7 @@ typedef uint32_t VMW_REG;
port_num, magic, bp, \
ax, bx, cx, dx, si, di) \
({ \
- __asm__ volatile ("push %%ebp;" \
+ __asm__ volatile ("push %%ebp;" \
"mov %12, %%ebp;" \
"rep insb;" \
"pop %%ebp" : \
@@ -252,7 +253,7 @@ typedef uint32_t VMW_REG;
(void) in_cx; (void) bp; \
(void) ax; (void) bx; (void) cx; \
(void) dx; (void) si; (void) di;
-
+
#define VMW_PORT_HB_IN(cmd, in_cx, in_si, in_di, \
port_num, magic, bp, \
@@ -283,7 +284,7 @@ struct rpc_channel {
/**
- * svga_open_channel
+ * vmw_open_channel
*
* @channel: RPC channel
* @protocol:
@@ -291,7 +292,7 @@ struct rpc_channel {
* Returns: PIPE_OK on success, PIPE_ERROR otherwise
*/
static enum pipe_error
-svga_open_channel(struct rpc_channel *channel, unsigned protocol)
+vmw_open_channel(struct rpc_channel *channel, unsigned protocol)
{
VMW_REG ax = 0, bx = 0, cx = 0, dx = 0, si = 0, di = 0;
@@ -321,7 +322,7 @@ svga_open_channel(struct rpc_channel *channel, unsigned protocol)
* Returns: PIPE_OK on success, PIPE_ERROR otherwises
*/
static enum pipe_error
-svga_close_channel(struct rpc_channel *channel)
+vmw_close_channel(struct rpc_channel *channel)
{
VMW_REG ax = 0, bx = 0, cx = 0, dx = 0, si, di;
@@ -344,7 +345,7 @@ svga_close_channel(struct rpc_channel *channel)
/**
- * svga_send_msg: Sends a message to the host
+ * vmw_send_msg: Sends a message to the host
*
* @channel: RPC channel
* @logmsg: NULL terminated string
@@ -352,7 +353,7 @@ svga_close_channel(struct rpc_channel *channel)
* Returns: PIPE_OK on success
*/
static enum pipe_error
-svga_send_msg(struct rpc_channel *channel, const char *msg)
+vmw_send_msg(struct rpc_channel *channel, const char *msg)
{
VMW_REG ax = 0, bx = 0, cx = 0, dx = 0, si, di, bp;
size_t msg_len = strlen(msg);
@@ -406,46 +407,42 @@ svga_send_msg(struct rpc_channel *channel, const char *msg)
/**
- * svga_host_log: Sends a log message to the host
+ * vmw_svga_winsys_host_log: Sends a log message to the host
*
* @log: NULL terminated string
*
- * Returns: PIPE_OK on success
*/
-enum pipe_error
-svga_host_log(const char *log)
+void
+vmw_svga_winsys_host_log(struct svga_winsys_screen *sws, const char *log)
{
struct rpc_channel channel;
char *msg;
int msg_len;
- enum pipe_error ret = PIPE_OK;
#ifdef MSG_NOT_IMPLEMENTED
- return ret;
+ return;
#endif
if (!log)
- return ret;
+ return;
msg_len = strlen(log) + strlen("log ") + 1;
msg = CALLOC(1, msg_len);
if (msg == NULL) {
debug_printf("Cannot allocate memory for log message\n");
- return PIPE_ERROR_OUT_OF_MEMORY;
+ return;
}
util_sprintf(msg, "log %s", log);
- if (svga_open_channel(&channel, RPCI_PROTOCOL_NUM) ||
- svga_send_msg(&channel, msg) ||
- svga_close_channel(&channel)) {
+ if (vmw_open_channel(&channel, RPCI_PROTOCOL_NUM) ||
+ vmw_send_msg(&channel, msg) ||
+ vmw_close_channel(&channel)) {
debug_printf("Failed to send log\n");
-
- ret = PIPE_ERROR;
}
FREE(msg);
- return ret;
+ return;
}
diff --git a/src/gallium/drivers/svga/svga_msg.h b/src/gallium/winsys/svga/drm/vmw_msg.h
similarity index 89%
rename from src/gallium/drivers/svga/svga_msg.h
rename to src/gallium/winsys/svga/drm/vmw_msg.h
index 9132ba7e240..57057f23638 100644
--- a/src/gallium/drivers/svga/svga_msg.h
+++ b/src/gallium/winsys/svga/drm/vmw_msg.h
@@ -26,17 +26,16 @@
* Author:
* Sinclair Yeh
*/
-#ifndef _SVGA_MSG_H
-#define _SVGA_MSG_H
+#ifndef _VMW_MSG_H
+#define _VMW_MSG_H
/**
- * svga_host_log: Sends a log message to the host
+ * vmw_host_log: Sends a log message to the host
*
* @log: NULL terminated string
*
- * Returns: PIPE_OK on success
*/
-enum pipe_error svga_host_log(const char *log);
+void vmw_svga_winsys_host_log(struct svga_winsys_screen *sws, const char *log);
#endif
diff --git a/src/gallium/winsys/svga/drm/vmw_screen_svga.c b/src/gallium/winsys/svga/drm/vmw_screen_svga.c
index a6990414e20..cd3f21f6033 100644
--- a/src/gallium/winsys/svga/drm/vmw_screen_svga.c
+++ b/src/gallium/winsys/svga/drm/vmw_screen_svga.c
@@ -48,6 +48,7 @@
#include "vmw_surface.h"
#include "vmw_buffer.h"
#include "vmw_fence.h"
+#include "vmw_msg.h"
#include "vmw_shader.h"
#include "vmw_query.h"
#include "svga3d_surfacedefs.h"
@@ -509,6 +510,8 @@ vmw_winsys_screen_init_svga(struct vmw_winsys_screen *vws)
vws->base.stats_time_push = vmw_svga_winsys_stats_time_push;
vws->base.stats_time_pop = vmw_svga_winsys_stats_time_pop;
+ vws->base.host_log = vmw_svga_winsys_host_log;
+
return TRUE;
}
diff --git a/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c b/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c
index 8753139107c..a4c1d50453b 100644
--- a/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c
+++ b/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c
@@ -396,6 +396,7 @@ xlib_displaytarget_create(struct sw_winsys *winsys,
{
struct xlib_displaytarget *xlib_dt;
unsigned nblocksy, size;
+ int ignore;
xlib_dt = CALLOC_STRUCT(xlib_displaytarget);
if (!xlib_dt)
@@ -410,7 +411,8 @@ xlib_displaytarget_create(struct sw_winsys *winsys,
xlib_dt->stride = align(util_format_get_stride(format, width), alignment);
size = xlib_dt->stride * nblocksy;
- if (!debug_get_option_xlib_no_shm()) {
+ if (!debug_get_option_xlib_no_shm() &&
+ XQueryExtension(xlib_dt->display, "MIT-SHM", &ignore, &ignore, &ignore)) {
xlib_dt->data = alloc_shm(xlib_dt, size);
if (xlib_dt->data) {
xlib_dt->shm = True;
diff --git a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
index 26de8c702df..a2d232a539c 100644
--- a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
+++ b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
@@ -46,7 +46,7 @@
#define VIRGL_DRM_VERSION(major, minor) ((major) << 16 | (minor))
-#define VIRGL_DRM_VERSION_FENCE_FD VIRGL_DRM_VERSION(1, 0)
+#define VIRGL_DRM_VERSION_FENCE_FD VIRGL_DRM_VERSION(0, 1)
static inline boolean can_cache_resource(struct virgl_hw_res *res)
@@ -870,7 +870,7 @@ static int virgl_drm_get_version(int fd)
else if (version->version_major != 0)
ret = -EINVAL;
else
- ret = version->version_minor;
+ ret = VIRGL_DRM_VERSION(0, version->version_minor);
drmFreeVersion(version);
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index 298adc80ef1..d53fc87e21e 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -642,7 +642,6 @@ dri3_set_swap_interval(__GLXDRIdrawable *pdraw, int interval)
break;
}
- priv->swap_interval = interval;
loader_dri3_set_swap_interval(&priv->loader_drawable, interval);
return 0;
@@ -659,7 +658,7 @@ dri3_get_swap_interval(__GLXDRIdrawable *pdraw)
struct dri3_drawable *priv = (struct dri3_drawable *) pdraw;
- return priv->swap_interval;
+ return priv->loader_drawable.swap_interval;
}
static void
diff --git a/src/glx/dri3_priv.h b/src/glx/dri3_priv.h
index 1d3c03f9997..32a8d3f7e7d 100644
--- a/src/glx/dri3_priv.h
+++ b/src/glx/dri3_priv.h
@@ -117,7 +117,6 @@ struct dri3_context
struct dri3_drawable {
__GLXDRIdrawable base;
struct loader_dri3_drawable loader_drawable;
- int swap_interval;
/* LIBGL_SHOW_FPS support */
uint64_t previous_ust;
diff --git a/src/glx/drisw_glx.c b/src/glx/drisw_glx.c
index 00c7fa100ab..48c03ca42e0 100644
--- a/src/glx/drisw_glx.c
+++ b/src/glx/drisw_glx.c
@@ -147,6 +147,9 @@ XDestroyDrawable(struct drisw_drawable * pdp, Display * dpy, XID drawable)
if (pdp->ximage)
XDestroyImage(pdp->ximage);
+ if (pdp->shminfo.shmid > 0)
+ XShmDetach(dpy, &pdp->shminfo);
+
free(pdp->visinfo);
XFreeGC(dpy, pdp->gc);
diff --git a/src/intel/Android.common.mk b/src/intel/Android.common.mk
index 12cea6e5472..79d9f1284a0 100644
--- a/src/intel/Android.common.mk
+++ b/src/intel/Android.common.mk
@@ -38,7 +38,17 @@ LOCAL_C_INCLUDES := \
$(MESA_TOP)/src/mapi \
$(MESA_TOP)/src/mesa
-LOCAL_SHARED_LIBRARIES := libexpat libz
+LOCAL_SHARED_LIBRARIES := libz liblog
+
+# If Android version >=8 MESA should static link libexpat else should dynamic link
+ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0)
+LOCAL_STATIC_LIBRARIES := \
+ libexpat
+else
+LOCAL_SHARED_LIBRARIES += \
+ libexpat
+endif
+
LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_genxml
diff --git a/src/intel/Android.compiler.mk b/src/intel/Android.compiler.mk
index c2b01221dfc..41af7b20b9c 100644
--- a/src/intel/Android.compiler.mk
+++ b/src/intel/Android.compiler.mk
@@ -28,7 +28,7 @@
# ---------------------------------------
include $(CLEAR_VARS)
-
+LOCAL_CFLAGS += -Wno-error
LOCAL_MODULE := libmesa_intel_compiler
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
diff --git a/src/intel/Android.dev.mk b/src/intel/Android.dev.mk
index cd2ed66a176..3011ee232ed 100644
--- a/src/intel/Android.dev.mk
+++ b/src/intel/Android.dev.mk
@@ -33,5 +33,8 @@ LOCAL_C_INCLUDES := $(MESA_TOP)/include/drm-uapi
LOCAL_SRC_FILES := $(DEV_FILES)
+LOCAL_CFLAGS := \
+ -Wno-gnu-variable-sized-type-not-at-end
+
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk
index 7019c8cbc8f..73586803552 100644
--- a/src/intel/Android.vulkan.mk
+++ b/src/intel/Android.vulkan.mk
@@ -23,9 +23,10 @@ LOCAL_PATH := $(call my-dir)
include $(CLEAR_VARS)
include $(LOCAL_PATH)/Makefile.sources
-VK_ENTRYPOINTS_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/vulkan/anv_entrypoints_gen.py
-
-VK_EXTENSIONS_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/vulkan/anv_extensions_gen.py
+ANV_ENTRYPOINTS_GEN_SCRIPT := $(LOCAL_PATH)/vulkan/anv_entrypoints_gen.py
+ANV_EXTENSIONS_GEN_SCRIPT := $(LOCAL_PATH)/vulkan/anv_extensions_gen.py
+ANV_EXTENSIONS_SCRIPT := $(LOCAL_PATH)/vulkan/anv_extensions.py
+VULKAN_API_XML := $(MESA_TOP)/src/vulkan/registry/vk.xml
VULKAN_COMMON_INCLUDES := \
$(MESA_TOP)/include \
@@ -41,6 +42,18 @@ VULKAN_COMMON_INCLUDES := \
$(MESA_TOP)/src/compiler \
frameworks/native/vulkan/include
+ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0)
+VULKAN_COMMON_INCLUDES += \
+ frameworks/native/vulkan/include \
+ frameworks/native/libs/nativebase/include \
+ frameworks/native/libs/nativewindow/include \
+ frameworks/native/libs/arect/include
+
+VULKAN_COMMON_HEADER_LIBRARIES := \
+ libcutils_headers \
+ libhardware_headers
+endif
+
# libmesa_anv_entrypoints with header and dummy.c
#
# This static library is built to pull entrypoints header
@@ -59,16 +72,28 @@ LOCAL_C_INCLUDES := \
LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_entrypoints.h
LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/dummy.c
+LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_extensions.h
$(intermediates)/vulkan/dummy.c:
@mkdir -p $(dir $@)
@echo "Gen Dummy: $(PRIVATE_MODULE) <= $(notdir $(@))"
$(hide) touch $@
-$(intermediates)/vulkan/anv_entrypoints.h: $(intermediates)/vulkan/dummy.c
- $(VK_ENTRYPOINTS_SCRIPT) \
+$(intermediates)/vulkan/anv_entrypoints.h: $(intermediates)/vulkan/dummy.c \
+ $(ANV_ENTRYPOINTS_GEN_SCRIPT) \
+ $(ANV_EXTENSIONS_SCRIPT) \
+ $(VULKAN_API_XML)
+ $(MESA_PYTHON2) $(ANV_ENTRYPOINTS_GEN_SCRIPT) \
--outdir $(dir $@) \
- --xml $(MESA_TOP)/src/vulkan/registry/vk.xml
+ --xml $(VULKAN_API_XML)
+
+$(intermediates)/vulkan/anv_extensions.h: $(ANV_ENTRYPOINTS_GEN_SCRIPT) \
+ $(ANV_EXTENSIONS_SCRIPT) \
+ $(VULKAN_API_XML)
+ @mkdir -p $(dir $@)
+ $(MESA_PYTHON2) $(ANV_EXTENSIONS_GEN_SCRIPT) \
+ --xml $(VULKAN_API_XML) \
+ --out-h $@
LOCAL_EXPORT_C_INCLUDE_DIRS := \
$(intermediates)
@@ -107,6 +132,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES)
LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES)
+LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES)
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@@ -127,6 +153,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES)
LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES)
+LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES)
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@@ -147,6 +174,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES)
LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES)
+LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES)
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@@ -167,6 +195,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES)
LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES)
+LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES)
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@@ -187,6 +216,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES)
LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES)
+LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES)
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@@ -207,6 +237,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES)
LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES)
+LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES)
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@@ -218,7 +249,7 @@ include $(BUILD_STATIC_LIBRARY)
include $(CLEAR_VARS)
LOCAL_MODULE := libmesa_vulkan_common
LOCAL_MODULE_CLASS := STATIC_LIBRARIES
-
+LOCAL_CFLAGS += -Wno-error
intermediates := $(call local-generated-sources-dir)
LOCAL_SRC_FILES := $(VULKAN_FILES)
@@ -240,27 +271,25 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \
LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_entrypoints.c
LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_extensions.c
-LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_extensions.h
-$(intermediates)/vulkan/anv_entrypoints.c:
+$(intermediates)/vulkan/anv_entrypoints.c: $(ANV_ENTRYPOINTS_GEN_SCRIPT) \
+ $(ANV_EXTENSIONS_SCRIPT) \
+ $(VULKAN_API_XML)
@mkdir -p $(dir $@)
- $(VK_ENTRYPOINTS_SCRIPT) \
- --xml $(MESA_TOP)/src/vulkan/registry/vk.xml \
+ $(MESA_PYTHON2) $(ANV_ENTRYPOINTS_GEN_SCRIPT) \
+ --xml $(VULKAN_API_XML) \
--outdir $(dir $@)
-$(intermediates)/vulkan/anv_extensions.c:
+$(intermediates)/vulkan/anv_extensions.c: $(ANV_EXTENSIONS_GEN_SCRIPT) \
+ $(ANV_EXTENSIONS_SCRIPT) \
+ $(VULKAN_API_XML)
@mkdir -p $(dir $@)
- $(VK_EXTENSIONS_SCRIPT) \
- --xml $(MESA_TOP)/src/vulkan/registry/vk.xml \
+ $(MESA_PYTHON2) $(ANV_EXTENSIONS_GEN_SCRIPT) \
+ --xml $(VULKAN_API_XML) \
--out-c $@
-$(intermediates)/vulkan/anv_extensions.h:
- @mkdir -p $(dir $@)
- $(VK_EXTENSIONS_SCRIPT) \
- --xml $(MESA_TOP)/src/vulkan/registry/vk.xml \
- --out-h $@
-
LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES)
+LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES)
include $(MESA_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
@@ -310,6 +339,16 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \
libmesa_anv_entrypoints
LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES) libz libsync liblog
+LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES)
+
+# If Android version >=8 MESA should static link libexpat else should dynamic link
+ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0)
+LOCAL_STATIC_LIBRARIES := \
+ libexpat
+else
+ LOCAL_SHARED_LIBRARIES += \
+ libexpat
+endif
include $(MESA_COMMON_MK)
include $(BUILD_SHARED_LIBRARY)
diff --git a/src/intel/Makefile.isl.am b/src/intel/Makefile.isl.am
index a6733f3ba8e..dcb9d3ad6fc 100644
--- a/src/intel/Makefile.isl.am
+++ b/src/intel/Makefile.isl.am
@@ -33,12 +33,15 @@ ISL_GEN_LIBS = \
noinst_LTLIBRARIES += $(ISL_GEN_LIBS) \
isl/libisl.la \
- libisl_tiled_memcpy.la \
- libisl_tiled_memcpy_sse41.la
+ libisl_tiled_memcpy.la
isl_libisl_la_LIBADD = $(ISL_GEN_LIBS) \
- libisl_tiled_memcpy.la \
- libisl_tiled_memcpy_sse41.la
+ libisl_tiled_memcpy.la
+
+if SSE41_SUPPORTED
+isl_libisl_la_LIBADD += libisl_tiled_memcpy_sse41.la
+noinst_LTLIBRARIES += libisl_tiled_memcpy_sse41.la
+endif
isl_libisl_la_SOURCES = $(ISL_FILES) $(ISL_GENERATED_FILES)
diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
index b315f10a01a..cad0a57bc7f 100644
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -253,6 +253,7 @@ VULKAN_TESTS = \
vulkan/tests/block_pool_no_free \
vulkan/tests/state_pool_no_free \
vulkan/tests/state_pool_free_list_only \
+ vulkan/tests/state_pool_padding \
vulkan/tests/state_pool
VULKAN_TEST_LDADD = \
@@ -274,6 +275,10 @@ vulkan_tests_state_pool_free_list_only_CFLAGS = $(VULKAN_CFLAGS)
vulkan_tests_state_pool_free_list_only_CPPFLAGS = $(VULKAN_CPPFLAGS)
vulkan_tests_state_pool_free_list_only_LDADD = $(VULKAN_TEST_LDADD)
+vulkan_tests_state_pool_padding_CFLAGS = $(VULKAN_CFLAGS)
+vulkan_tests_state_pool_padding_CPPFLAGS = $(VULKAN_CPPFLAGS)
+vulkan_tests_state_pool_padding_LDADD = $(VULKAN_TEST_LDADD)
+
vulkan_tests_state_pool_CFLAGS = $(VULKAN_CFLAGS)
vulkan_tests_state_pool_CPPFLAGS = $(VULKAN_CPPFLAGS)
vulkan_tests_state_pool_LDADD = $(VULKAN_TEST_LDADD)
diff --git a/src/intel/blorp/meson.build b/src/intel/blorp/meson.build
index c1201b0aa16..ff68d255164 100644
--- a/src/intel/blorp/meson.build
+++ b/src/intel/blorp/meson.build
@@ -33,5 +33,5 @@ libblorp = static_library(
files_libblorp,
include_directories : [inc_common, inc_intel],
c_args : [c_vis_args, no_override_init_args],
- dependencies : idep_nir_headers,
+ dependencies : [idep_nir_headers, idep_genxml],
)
diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c
index a978f2f5818..8990d208207 100644
--- a/src/intel/common/gen_debug.c
+++ b/src/intel/common/gen_debug.c
@@ -85,6 +85,7 @@ static const struct debug_control debug_control[] = {
{ "nohiz", DEBUG_NO_HIZ },
{ "color", DEBUG_COLOR },
{ "reemit", DEBUG_REEMIT },
+ { "heur32", DEBUG_HEUR32 },
{ NULL, 0 }
};
diff --git a/src/intel/common/gen_debug.h b/src/intel/common/gen_debug.h
index 72d7ca20a39..c2ca2e2ebd6 100644
--- a/src/intel/common/gen_debug.h
+++ b/src/intel/common/gen_debug.h
@@ -83,6 +83,7 @@ extern uint64_t INTEL_DEBUG;
#define DEBUG_NO_HIZ (1ull << 39)
#define DEBUG_COLOR (1ull << 40)
#define DEBUG_REEMIT (1ull << 41)
+#define DEBUG_HEUR32 (1ull << 42)
/* These flags are not compatible with the disk shader cache */
#define DEBUG_DISK_CACHE_DISABLE_MASK DEBUG_SHADER_TIME
@@ -90,7 +91,7 @@ extern uint64_t INTEL_DEBUG;
/* These flags may affect program generation */
#define DEBUG_DISK_CACHE_MASK \
(DEBUG_NO16 | DEBUG_NO_DUAL_OBJECT_GS | DEBUG_NO8 | DEBUG_SPILL_FS | \
- DEBUG_SPILL_VEC4 | DEBUG_NO_COMPACTION | DEBUG_DO32)
+ DEBUG_SPILL_VEC4 | DEBUG_NO_COMPACTION | DEBUG_DO32 | DEBUG_HEUR32)
#ifdef HAVE_ANDROID_PLATFORM
#define LOG_TAG "INTEL-MESA"
diff --git a/src/intel/common/meson.build b/src/intel/common/meson.build
index 332e978b0ad..ec45962502e 100644
--- a/src/intel/common/meson.build
+++ b/src/intel/common/meson.build
@@ -43,5 +43,5 @@ libintel_common = static_library(
include_directories : [inc_common, inc_intel],
c_args : [c_vis_args, no_override_init_args],
link_with : [libisl],
- dependencies : [dep_expat, dep_libdrm, dep_thread],
+ dependencies : [dep_expat, dep_libdrm, dep_thread, idep_genxml],
)
diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index 61a4528d372..c294e5c3222 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -38,6 +38,15 @@ struct ra_regs;
struct nir_shader;
struct brw_program;
+struct brw_simd32_heuristics_control {
+ bool grouped_sends_check;
+ int max_grouped_sends;
+ bool inst_count_check;
+ float inst_count_ratio;
+ bool mrt_check;
+ int max_mrts;
+};
+
struct brw_compiler {
const struct gen_device_info *devinfo;
@@ -118,6 +127,8 @@ struct brw_compiler {
* whether nir_opt_large_constants will be run.
*/
bool supports_shader_constants;
+
+ struct brw_simd32_heuristics_control simd32_heuristics_control;
};
/**
@@ -196,6 +207,9 @@ struct brw_sampler_prog_key_data {
uint32_t yx_xuxv_image_mask;
uint32_t xy_uxvx_image_mask;
uint32_t ayuv_image_mask;
+
+ /* Scale factor for each texture. */
+ float scale_factors[32];
};
/**
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 8dd3b94fbd5..5b29292d6a0 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -251,6 +251,62 @@ fs_inst::is_send_from_grf() const
}
}
+bool
+fs_inst::is_control_source(unsigned arg) const
+{
+ switch (opcode) {
+ case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
+ case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
+ case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
+ return arg == 0;
+
+ case SHADER_OPCODE_BROADCAST:
+ case SHADER_OPCODE_SHUFFLE:
+ case SHADER_OPCODE_QUAD_SWIZZLE:
+ case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
+ case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
+ case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
+ case SHADER_OPCODE_IMAGE_SIZE:
+ case SHADER_OPCODE_GET_BUFFER_SIZE:
+ return arg == 1;
+
+ case SHADER_OPCODE_MOV_INDIRECT:
+ case SHADER_OPCODE_CLUSTER_BROADCAST:
+ case SHADER_OPCODE_TEX:
+ case FS_OPCODE_TXB:
+ case SHADER_OPCODE_TXD:
+ case SHADER_OPCODE_TXF:
+ case SHADER_OPCODE_TXF_LZ:
+ case SHADER_OPCODE_TXF_CMS:
+ case SHADER_OPCODE_TXF_CMS_W:
+ case SHADER_OPCODE_TXF_UMS:
+ case SHADER_OPCODE_TXF_MCS:
+ case SHADER_OPCODE_TXL:
+ case SHADER_OPCODE_TXL_LZ:
+ case SHADER_OPCODE_TXS:
+ case SHADER_OPCODE_LOD:
+ case SHADER_OPCODE_TG4:
+ case SHADER_OPCODE_TG4_OFFSET:
+ case SHADER_OPCODE_SAMPLEINFO:
+ case SHADER_OPCODE_UNTYPED_ATOMIC:
+ case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT:
+ case SHADER_OPCODE_UNTYPED_SURFACE_READ:
+ case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
+ case SHADER_OPCODE_BYTE_SCATTERED_READ:
+ case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
+ case SHADER_OPCODE_TYPED_ATOMIC:
+ case SHADER_OPCODE_TYPED_SURFACE_READ:
+ case SHADER_OPCODE_TYPED_SURFACE_WRITE:
+ return arg == 1 || arg == 2;
+
+ case SHADER_OPCODE_SEND:
+ return arg == 0 || arg == 1;
+
+ default:
+ return false;
+ }
+}
+
/**
* Returns true if this instruction's sources and destinations cannot
* safely be the same register.
@@ -3061,6 +3117,7 @@ fs_visitor::opt_peephole_csel()
if (csel_inst != NULL) {
progress = true;
+ csel_inst->saturate = inst->saturate;
inst->remove(block);
}
@@ -3899,18 +3956,22 @@ fs_visitor::lower_integer_multiplication()
bool needs_mov = false;
fs_reg orig_dst = inst->dst;
+
+ /* Get a new VGRF for the "low" 32x16-bit multiplication result if
+ * reusing the original destination is impossible due to hardware
+ * restrictions, source/destination overlap, or it being the null
+ * register.
+ */
fs_reg low = inst->dst;
if (orig_dst.is_null() || orig_dst.file == MRF ||
regions_overlap(inst->dst, inst->size_written,
inst->src[0], inst->size_read(0)) ||
regions_overlap(inst->dst, inst->size_written,
- inst->src[1], inst->size_read(1))) {
+ inst->src[1], inst->size_read(1)) ||
+ inst->dst.stride >= 4) {
needs_mov = true;
- /* Get a new VGRF but keep the same stride as inst->dst */
low = fs_reg(VGRF, alloc.allocate(regs_written(inst)),
inst->dst.type);
- low.stride = inst->dst.stride;
- low.offset = inst->dst.offset % REG_SIZE;
}
/* Get a new VGRF but keep the same stride as inst->dst */
@@ -7542,6 +7603,8 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
char **error_str)
{
const struct gen_device_info *devinfo = compiler->devinfo;
+ bool simd16_failed = false;
+ bool simd16_spilled = false;
shader = brw_nir_apply_sampler_key(shader, compiler, &key->tex, true);
brw_nir_lower_fs_inputs(shader, devinfo, key);
@@ -7608,10 +7671,12 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
shader_time_index16);
v16.import_uniforms(&v8);
if (!v16.run_fs(allow_spilling, use_rep_send)) {
+ simd16_failed = true;
compiler->shader_perf_log(log_data,
"SIMD16 shader failed to compile: %s",
v16.fail_msg);
} else {
+ simd16_spilled = v16.spilled_any_registers;
simd16_cfg = v16.cfg;
prog_data->dispatch_grf_start_reg_16 = v16.payload.num_regs;
prog_data->reg_blocks_16 = brw_register_blocks(v16.grf_used);
@@ -7619,9 +7684,17 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
}
/* Currently, the compiler only supports SIMD32 on SNB+ */
+ const brw_simd32_heuristics_control *ctrl = &compiler->simd32_heuristics_control;
+ uint64_t mrts = shader->info.outputs_written << FRAG_RESULT_DATA0;
+
if (v8.max_dispatch_width >= 32 && !use_rep_send &&
compiler->devinfo->gen >= 6 &&
- unlikely(INTEL_DEBUG & DEBUG_DO32)) {
+ (unlikely(INTEL_DEBUG & DEBUG_DO32) ||
+ (unlikely(INTEL_DEBUG & DEBUG_HEUR32) &&
+ !simd16_failed && !simd16_spilled &&
+ (!ctrl->mrt_check ||
+ (ctrl->mrt_check &&
+ u_count_bits64(&mrts) <= ctrl->max_mrts))))) {
/* Try a SIMD32 compile */
fs_visitor v32(compiler, log_data, mem_ctx, key,
&prog_data->base, prog, shader, 32,
@@ -7632,9 +7705,12 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
"SIMD32 shader failed to compile: %s",
v32.fail_msg);
} else {
- simd32_cfg = v32.cfg;
- prog_data->dispatch_grf_start_reg_32 = v32.payload.num_regs;
- prog_data->reg_blocks_32 = brw_register_blocks(v32.grf_used);
+ if (likely(!(INTEL_DEBUG & DEBUG_HEUR32)) ||
+ v32.run_heuristic(ctrl)) {
+ simd32_cfg = v32.cfg;
+ prog_data->dispatch_grf_start_reg_32 = v32.payload.num_regs;
+ prog_data->reg_blocks_32 = brw_register_blocks(v32.grf_used);
+ }
}
}
@@ -7713,13 +7789,49 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
}
if (simd32_cfg) {
- prog_data->dispatch_32 = true;
- prog_data->prog_offset_32 = g.generate_code(simd32_cfg, 32);
+ uint32_t offset = g.generate_code(simd32_cfg, 32);
+
+ if (unlikely(INTEL_DEBUG & DEBUG_DO32) ||
+ (unlikely(INTEL_DEBUG & DEBUG_HEUR32) &&
+ (!simd16_cfg ||
+ (simd16_cfg &&
+ (!ctrl->inst_count_check ||
+ (ctrl->inst_count_check &&
+ (float)g.get_inst_count(32) / (float)g.get_inst_count(16) <= ctrl->inst_count_ratio)))))) {
+ prog_data->dispatch_32 = true;
+ prog_data->prog_offset_32 = offset;
+ }
}
return g.get_assembly();
}
+bool
+fs_visitor::run_heuristic(const struct brw_simd32_heuristics_control *ctrl) {
+ int grouped_sends = 0;
+ int max_grouped_sends = 0;
+ bool pass = true;
+
+ foreach_block_and_inst(block, fs_inst, inst, cfg) {
+ if (inst->opcode >= SHADER_OPCODE_TEX && inst->opcode <= SHADER_OPCODE_SAMPLEINFO_LOGICAL) {
+ ++grouped_sends;
+ } else if (grouped_sends > 0) {
+ if (grouped_sends > max_grouped_sends) {
+ max_grouped_sends = grouped_sends;
+ }
+ grouped_sends = 0;
+ }
+ }
+
+ if (ctrl->grouped_sends_check) {
+ if (max_grouped_sends > ctrl->max_grouped_sends) {
+ pass = false;
+ }
+ }
+
+ return pass;
+}
+
fs_reg *
fs_visitor::emit_cs_work_group_id_setup()
{
diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index 5361b768003..72acf85581e 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -289,6 +289,8 @@ class fs_visitor : public backend_shader
void dump_instruction(backend_instruction *inst);
void dump_instruction(backend_instruction *inst, FILE *file);
+ bool run_heuristic(const struct brw_simd32_heuristics_control *ctrl);
+
const void *const key;
const struct brw_sampler_prog_key_data *key_tex;
@@ -400,6 +402,7 @@ class fs_generator
void enable_debug(const char *shader_name);
int generate_code(const cfg_t *cfg, int dispatch_width);
+ int get_inst_count(int dispatch_width);
const unsigned *get_assembly();
private:
@@ -495,6 +498,7 @@ class fs_generator
struct brw_stage_prog_data * const prog_data;
unsigned dispatch_width; /**< 8, 16 or 32 */
+ int inst_count[3]; /* for 8, 16 and 32 */
exec_list discard_halt_patches;
unsigned promoted_constants;
diff --git a/src/intel/compiler/brw_fs_cmod_propagation.cpp b/src/intel/compiler/brw_fs_cmod_propagation.cpp
index 5fb522f810f..b58730fbbe5 100644
--- a/src/intel/compiler/brw_fs_cmod_propagation.cpp
+++ b/src/intel/compiler/brw_fs_cmod_propagation.cpp
@@ -255,6 +255,13 @@ opt_cmod_propagation_local(const gen_device_info *devinfo, bblock_t *block)
if (inst->opcode == BRW_OPCODE_AND)
break;
+ /* Not safe to use inequality operators if the types are different
+ */
+ if (scan_inst->dst.type != inst->src[0].type &&
+ inst->conditional_mod != BRW_CONDITIONAL_Z &&
+ inst->conditional_mod != BRW_CONDITIONAL_NZ)
+ break;
+
/* Comparisons operate differently for ints and floats */
if (scan_inst->dst.type != inst->dst.type &&
(scan_inst->dst.type == BRW_REGISTER_TYPE_F ||
diff --git a/src/intel/compiler/brw_fs_copy_propagation.cpp b/src/intel/compiler/brw_fs_copy_propagation.cpp
index c23ce1ef426..bba7eb35830 100644
--- a/src/intel/compiler/brw_fs_copy_propagation.cpp
+++ b/src/intel/compiler/brw_fs_copy_propagation.cpp
@@ -32,9 +32,10 @@
* 12.5 (p356).
*/
-#define ACP_HASH_SIZE 16
+#define ACP_HASH_SIZE 64
#include "util/bitset.h"
+#include "util/u_math.h"
#include "brw_fs.h"
#include "brw_fs_live_variables.h"
#include "brw_cfg.h"
@@ -46,6 +47,7 @@ namespace { /* avoid conflict with opt_copy_propagation_elements */
struct acp_entry : public exec_node {
fs_reg dst;
fs_reg src;
+ unsigned global_idx;
uint8_t size_written;
uint8_t size_read;
enum opcode opcode;
@@ -142,6 +144,8 @@ fs_copy_prop_dataflow::fs_copy_prop_dataflow(void *mem_ctx, cfg_t *cfg,
foreach_in_list(acp_entry, entry, &out_acp[block->num][i]) {
acp[next_acp] = entry;
+ entry->global_idx = next_acp;
+
/* opt_copy_propagation_local populates out_acp with copies created
* in a block which are still live at the end of the block. This
* is exactly what we want in the COPY set.
@@ -167,21 +171,74 @@ void
fs_copy_prop_dataflow::setup_initial_values()
{
/* Initialize the COPY and KILL sets. */
- foreach_block (block, cfg) {
- foreach_inst_in_block(fs_inst, inst, block) {
- if (inst->dst.file != VGRF)
- continue;
+ {
+ /* Create a temporary table of ACP entries which we'll use for efficient
+ * look-up. Unfortunately, we have to do this in two steps because we
+ * have to match both sources and destinations and an ACP entry can only
+ * be in one list at a time.
+ *
+ * We choose to make the table size between num_acp/2 and num_acp/4 to
+ * try and trade off between the time it takes to initialize the table
+ * via exec_list constructors or make_empty() and the cost of
+ * collisions. In practice, it doesn't appear to matter too much what
+ * size we make the table as long as it's roughly the same order of
+ * magnitude as num_acp. We get most of the benefit of the table
+ * approach even if we use a table of size ACP_HASH_SIZE though a
+ * full-sized table is 1-2% faster in practice.
+ */
+ unsigned acp_table_size = util_next_power_of_two(num_acp) / 4;
+ acp_table_size = MAX2(acp_table_size, ACP_HASH_SIZE);
+ exec_list *acp_table = new exec_list[acp_table_size];
- /* Mark ACP entries which are killed by this instruction. */
- for (int i = 0; i < num_acp; i++) {
- if (regions_overlap(inst->dst, inst->size_written,
- acp[i]->dst, acp[i]->size_written) ||
- regions_overlap(inst->dst, inst->size_written,
- acp[i]->src, acp[i]->size_read)) {
- BITSET_SET(bd[block->num].kill, i);
+ /* First, get all the KILLs for instructions which overwrite ACP
+ * destinations.
+ */
+ for (int i = 0; i < num_acp; i++) {
+ unsigned idx = acp[i]->dst.nr & (acp_table_size - 1);
+ acp_table[idx].push_tail(acp[i]);
+ }
+
+ foreach_block (block, cfg) {
+ foreach_inst_in_block(fs_inst, inst, block) {
+ if (inst->dst.file != VGRF)
+ continue;
+
+ unsigned idx = inst->dst.nr & (acp_table_size - 1);
+ foreach_in_list(acp_entry, entry, &acp_table[idx]) {
+ if (regions_overlap(inst->dst, inst->size_written,
+ entry->dst, entry->size_written))
+ BITSET_SET(bd[block->num].kill, entry->global_idx);
}
}
}
+
+ /* Clear the table for the second pass */
+ for (unsigned i = 0; i < acp_table_size; i++)
+ acp_table[i].make_empty();
+
+ /* Next, get all the KILLs for instructions which overwrite ACP
+ * sources.
+ */
+ for (int i = 0; i < num_acp; i++) {
+ unsigned idx = acp[i]->src.nr & (acp_table_size - 1);
+ acp_table[idx].push_tail(acp[i]);
+ }
+
+ foreach_block (block, cfg) {
+ foreach_inst_in_block(fs_inst, inst, block) {
+ if (inst->dst.file != VGRF)
+ continue;
+
+ unsigned idx = inst->dst.nr & (acp_table_size - 1);
+ foreach_in_list(acp_entry, entry, &acp_table[idx]) {
+ if (regions_overlap(inst->dst, inst->size_written,
+ entry->src, entry->size_read))
+ BITSET_SET(bd[block->num].kill, entry->global_idx);
+ }
+ }
+ }
+
+ delete [] acp_table;
}
/* Populate the initial values for the livein and liveout sets. For the
@@ -904,6 +961,25 @@ fs_visitor::opt_copy_propagation()
foreach_block (block, cfg) {
progress = opt_copy_propagation_local(copy_prop_ctx, block,
out_acp[block->num]) || progress;
+
+ /* If the destination of an ACP entry exists only within this block,
+ * then there's no need to keep it for dataflow analysis. We can delete
+ * it from the out_acp table and avoid growing the bitsets any bigger
+ * than we absolutely have to.
+ *
+ * Because nothing in opt_copy_propagation_local touches the block
+ * start/end IPs and opt_copy_propagation_local is incapable of
+ * extending the live range of an ACP destination beyond the block,
+ * it's safe to use the liveness information in this way.
+ */
+ for (unsigned a = 0; a < ACP_HASH_SIZE; a++) {
+ foreach_in_list_safe(acp_entry, entry, &out_acp[block->num][a]) {
+ assert(entry->dst.file == VGRF);
+ if (block->start_ip <= virtual_grf_start[entry->dst.nr] &&
+ virtual_grf_end[entry->dst.nr] <= block->end_ip)
+ entry->remove();
+ }
+ }
}
/* Do dataflow analysis for those available copies. */
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index e3b68fa3165..82c2713a77f 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -90,9 +90,16 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
* different execution size when the number of components
* written to each destination GRF is not the same.
*/
- const unsigned width = MIN2(reg_width, phys_width);
- brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
- brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
+ if (reg->stride > 4) {
+ assert(reg != &inst->dst);
+ assert(reg->stride * type_sz(reg->type) <= REG_SIZE);
+ brw_reg = brw_vecn_reg(1, brw_file_from_reg(reg), reg->nr, 0);
+ brw_reg = stride(brw_reg, reg->stride, 1, 0);
+ } else {
+ const unsigned width = MIN2(reg_width, phys_width);
+ brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
+ brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
+ }
if (devinfo->gen == 7 && !devinfo->is_haswell) {
/* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
@@ -2093,6 +2100,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
break;
case SHADER_OPCODE_INTERLOCK:
+ assert(devinfo->gen >= 9);
/* The interlock is basically a memory fence issued via sendc */
brw_memory_fence(p, dst, BRW_OPCODE_SENDC);
break;
@@ -2289,6 +2297,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
fill_count, promoted_constants, before_size,
after_size);
+ inst_count[ffs(dispatch_width) - 4] = before_size / 16;
+
return start_offset;
}
@@ -2297,3 +2307,13 @@ fs_generator::get_assembly()
{
return brw_get_program(p, &prog_data->program_size);
}
+
+int
+fs_generator::get_inst_count(int dispatch_width)
+{
+ if (dispatch_width == 8 || dispatch_width == 16 || dispatch_width == 32) {
+ return inst_count[ffs(dispatch_width) - 4];
+ } else {
+ return 0;
+ }
+}
\ No newline at end of file
diff --git a/src/intel/compiler/brw_fs_lower_regioning.cpp b/src/intel/compiler/brw_fs_lower_regioning.cpp
index df50993dee6..c60d4700419 100644
--- a/src/intel/compiler/brw_fs_lower_regioning.cpp
+++ b/src/intel/compiler/brw_fs_lower_regioning.cpp
@@ -71,15 +71,33 @@ namespace {
!is_byte_raw_mov(inst)) {
return get_exec_type_size(inst);
} else {
- unsigned stride = inst->dst.stride * type_sz(inst->dst.type);
+ /* Calculate the maximum byte stride and the minimum/maximum type
+ * size across all source and destination operands we are required to
+ * lower.
+ */
+ unsigned max_stride = inst->dst.stride * type_sz(inst->dst.type);
+ unsigned min_size = type_sz(inst->dst.type);
+ unsigned max_size = type_sz(inst->dst.type);
for (unsigned i = 0; i < inst->sources; i++) {
- if (!is_uniform(inst->src[i]))
- stride = MAX2(stride, inst->src[i].stride *
- type_sz(inst->src[i].type));
+ if (!is_uniform(inst->src[i]) && !inst->is_control_source(i)) {
+ const unsigned size = type_sz(inst->src[i].type);
+ max_stride = MAX2(max_stride, inst->src[i].stride * size);
+ min_size = MIN2(min_size, size);
+ max_size = MAX2(max_size, size);
+ }
}
- return stride;
+ /* All operands involved in lowering need to fit in the calculated
+ * stride.
+ */
+ assert(max_size <= 4 * min_size);
+
+ /* Attempt to use the largest byte stride among all present operands,
+ * but never exceed a stride of 4 since that would lead to illegal
+ * destination regions during lowering.
+ */
+ return MIN2(max_stride, 4 * min_size);
}
}
@@ -92,7 +110,7 @@ namespace {
required_dst_byte_offset(const fs_inst *inst)
{
for (unsigned i = 0; i < inst->sources; i++) {
- if (!is_uniform(inst->src[i]))
+ if (!is_uniform(inst->src[i]) && !inst->is_control_source(i))
if (reg_offset(inst->src[i]) % REG_SIZE !=
reg_offset(inst->dst) % REG_SIZE)
return 0;
@@ -109,7 +127,7 @@ namespace {
has_invalid_src_region(const gen_device_info *devinfo, const fs_inst *inst,
unsigned i)
{
- if (is_unordered(inst)) {
+ if (is_unordered(inst) || inst->is_control_source(i)) {
return false;
} else {
const unsigned dst_byte_stride = inst->dst.stride * type_sz(inst->dst.type);
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index f16627b8a64..6f0d9731cfe 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -512,6 +512,15 @@ fs_visitor::optimize_extract_to_float(nir_alu_instr *instr,
src0->op != nir_op_extract_i8 && src0->op != nir_op_extract_i16)
return false;
+ /* If either opcode has source modifiers, bail.
+ *
+ * TODO: We can potentially handle source modifiers if both of the opcodes
+ * we're combining are signed integers.
+ */
+ if (instr->src[0].abs || instr->src[0].negate ||
+ src0->src[0].abs || src0->src[0].negate)
+ return false;
+
unsigned element = nir_src_as_uint(src0->src[1].src);
/* Element type to extract.*/
@@ -1484,16 +1493,25 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
* Use two instructions and a word or DWord intermediate integer type.
*/
if (nir_dest_bit_size(instr->dest.dest) == 64) {
- const brw_reg_type type = brw_int_type(2, instr->op == nir_op_extract_i8);
+ const brw_reg_type type = brw_int_type(1, instr->op == nir_op_extract_i8);
if (instr->op == nir_op_extract_i8) {
/* If we need to sign extend, extract to a word first */
fs_reg w_temp = bld.vgrf(BRW_REGISTER_TYPE_W);
bld.MOV(w_temp, subscript(op[0], type, byte));
bld.MOV(result, w_temp);
+ } else if (byte & 1) {
+ /* Extract the high byte from the word containing the desired byte
+ * offset.
+ */
+ bld.SHR(result,
+ subscript(op[0], BRW_REGISTER_TYPE_UW, byte / 2),
+ brw_imm_uw(8));
} else {
/* Otherwise use an AND with 0xff and a word type */
- bld.AND(result, subscript(op[0], type, byte / 2), brw_imm_uw(0xff));
+ bld.AND(result,
+ subscript(op[0], BRW_REGISTER_TYPE_UW, byte / 2),
+ brw_imm_uw(0xff));
}
} else {
const brw_reg_type type = brw_int_type(1, instr->op == nir_op_extract_i8);
diff --git a/src/intel/compiler/brw_fs_reg_allocate.cpp b/src/intel/compiler/brw_fs_reg_allocate.cpp
index 6961cb1caf4..6e18bdfe68a 100644
--- a/src/intel/compiler/brw_fs_reg_allocate.cpp
+++ b/src/intel/compiler/brw_fs_reg_allocate.cpp
@@ -591,7 +591,7 @@ fs_visitor::assign_regs(bool allow_spilling, bool spill_all)
*/
foreach_block_and_inst(block, fs_inst, inst, cfg) {
if (inst->dst.file == VGRF && inst->has_source_and_destination_hazard()) {
- for (unsigned i = 0; i < 3; i++) {
+ for (unsigned i = 0; i < inst->sources; i++) {
if (inst->src[i].file == VGRF) {
ra_add_node_interference(g, inst->dst.nr, inst->src[i].nr);
}
@@ -667,15 +667,14 @@ fs_visitor::assign_regs(bool allow_spilling, bool spill_all)
* messages adding a node interference to the grf127_send_hack_node.
* This node has a fixed asignment to grf127.
*
- * We don't apply it to SIMD16 because previous code avoids any register
- * overlap between sources and destination.
+ * We don't apply it to SIMD16 instructions because previous code avoids
+ * any register overlap between sources and destination.
*/
ra_set_node_reg(g, grf127_send_hack_node, 127);
- if (dispatch_width == 8) {
- foreach_block_and_inst(block, fs_inst, inst, cfg) {
- if (inst->is_send_from_grf() && inst->dst.file == VGRF)
- ra_add_node_interference(g, inst->dst.nr, grf127_send_hack_node);
- }
+ foreach_block_and_inst(block, fs_inst, inst, cfg) {
+ if (inst->exec_size < 16 && inst->is_send_from_grf() &&
+ inst->dst.file == VGRF)
+ ra_add_node_interference(g, inst->dst.nr, grf127_send_hack_node);
}
if (spilled_any_registers) {
@@ -711,14 +710,9 @@ fs_visitor::assign_regs(bool allow_spilling, bool spill_all)
if (inst->opcode == SHADER_OPCODE_SEND && inst->ex_mlen > 0 &&
inst->src[2].file == VGRF &&
inst->src[3].file == VGRF &&
- inst->src[2].nr != inst->src[3].nr) {
- for (unsigned i = 0; i < inst->mlen; i++) {
- for (unsigned j = 0; j < inst->ex_mlen; j++) {
- ra_add_node_interference(g, inst->src[2].nr + i,
- inst->src[3].nr + j);
- }
- }
- }
+ inst->src[2].nr != inst->src[3].nr)
+ ra_add_node_interference(g, inst->src[2].nr,
+ inst->src[3].nr);
}
}
diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h
index d05357e822e..c4427a658b0 100644
--- a/src/intel/compiler/brw_ir_fs.h
+++ b/src/intel/compiler/brw_ir_fs.h
@@ -357,6 +357,13 @@ class fs_inst : public backend_instruction {
bool can_change_types() const;
bool has_source_and_destination_hazard() const;
+ /**
+ * Return whether \p arg is a control source of a virtual instruction which
+ * shouldn't contribute to the execution type and usual regioning
+ * restriction calculations of arithmetic instructions.
+ */
+ bool is_control_source(unsigned arg) const;
+
/**
* Return the subset of flag registers read by the instruction as a bitset
* with byte granularity.
@@ -461,7 +468,8 @@ get_exec_type(const fs_inst *inst)
brw_reg_type exec_type = BRW_REGISTER_TYPE_B;
for (int i = 0; i < inst->sources; i++) {
- if (inst->src[i].file != BAD_FILE) {
+ if (inst->src[i].file != BAD_FILE &&
+ !inst->is_control_source(i)) {
const brw_reg_type t = get_exec_type(inst->src[i].type);
if (type_sz(t) > type_sz(exec_type))
exec_type = t;
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 9dbf06004a4..6b8f4d30c1a 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -590,9 +590,9 @@ brw_nir_optimize(nir_shader *nir, const struct brw_compiler *compiler,
const bool is_vec4_tessellation = !is_scalar &&
(nir->info.stage == MESA_SHADER_TESS_CTRL ||
nir->info.stage == MESA_SHADER_TESS_EVAL);
- OPT(nir_opt_peephole_select, 0, !is_vec4_tessellation, false);
- OPT(nir_opt_peephole_select, 1, !is_vec4_tessellation,
- compiler->devinfo->gen >= 6);
+ OPT(nir_opt_peephole_select, 0, !is_vec4_tessellation);
+ if (compiler->devinfo->gen >= 6)
+ OPT(nir_opt_peephole_select, 1, !is_vec4_tessellation);
OPT(nir_opt_intrinsics);
OPT(nir_opt_idiv_const, 32);
@@ -794,6 +794,17 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)
OPT(brw_nir_lower_mem_access_bit_sizes);
+ /* Lower array derefs of vectors for SSBO and UBO loads. For both UBOs and
+ * SSBOs, our back-end is capable of loading an entire vec4 at a time and
+ * we would like to take advantage of that whenever possible regardless of
+ * whether or not the app gives us full loads. This should allow the
+ * optimizer to combine UBO and SSBO load operations and save us some send
+ * messages.
+ */
+ OPT(nir_lower_array_deref_of_vec,
+ nir_var_mem_ubo | nir_var_mem_ssbo,
+ nir_lower_direct_array_deref_of_vec_load);
+
/* Get rid of split copies */
nir = brw_nir_optimize(nir, compiler, is_scalar, false);
@@ -842,6 +853,23 @@ brw_nir_link_shaders(const struct brw_compiler *compiler,
*producer = brw_nir_optimize(*producer, compiler, p_is_scalar, false);
*consumer = brw_nir_optimize(*consumer, compiler, c_is_scalar, false);
}
+
+ NIR_PASS_V(*producer, nir_lower_io_to_vector, nir_var_shader_out);
+ NIR_PASS_V(*consumer, nir_lower_io_to_vector, nir_var_shader_in);
+
+ if ((*producer)->info.stage != MESA_SHADER_TESS_CTRL) {
+ /* Calling lower_io_to_vector creates output variable writes with
+ * write-masks. On non-TCS outputs, the back-end can't handle it and we
+ * need to call nir_lower_io_to_temporaries to get rid of them. This,
+ * in turn, creates temporary variables and extra copy_deref intrinsics
+ * that we need to clean up.
+ */
+ NIR_PASS_V(*producer, nir_lower_io_to_temporaries,
+ nir_shader_get_entrypoint(*producer), true, false);
+ NIR_PASS_V(*producer, nir_lower_global_vars_to_local);
+ NIR_PASS_V(*producer, nir_split_var_copies);
+ NIR_PASS_V(*producer, nir_lower_var_copies);
+ }
}
/* Prepare the given shader for codegen
@@ -932,7 +960,9 @@ brw_nir_apply_sampler_key(nir_shader *nir,
bool is_scalar)
{
const struct gen_device_info *devinfo = compiler->devinfo;
- nir_lower_tex_options tex_options = { 0 };
+ nir_lower_tex_options tex_options = {
+ .lower_txd_clamp_if_sampler_index_not_lt_16 = true,
+ };
/* Iron Lake and prior require lowering of all rectangle textures */
if (devinfo->gen < 6)
@@ -964,6 +994,10 @@ brw_nir_apply_sampler_key(nir_shader *nir,
tex_options.lower_xy_uxvx_external = key_tex->xy_uxvx_image_mask;
tex_options.lower_ayuv_external = key_tex->ayuv_image_mask;
+ /* Setup array of scaling factors for each texture. */
+ memcpy(&tex_options.scale_factors, &key_tex->scale_factors,
+ sizeof(tex_options.scale_factors));
+
if (nir_lower_tex(nir, &tex_options)) {
nir_validate_shader(nir, "after nir_lower_tex");
nir = brw_nir_optimize(nir, compiler, is_scalar, false);
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 4489c682d01..785508f1e3f 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -1160,6 +1160,12 @@ vec4_instruction::can_reswizzle(const struct gen_device_info *devinfo,
if (devinfo->gen == 6 && is_math() && swizzle != BRW_SWIZZLE_XYZW)
return false;
+ /* If we write to the flag register changing the swizzle would change
+ * what channels are written to the flag register.
+ */
+ if (writes_flag())
+ return false;
+
/* We can't swizzle implicit accumulator access. We'd have to
* reswizzle the producer of the accumulator value in addition
* to the consumer (i.e. both MUL and MACH). Just skip this.
diff --git a/src/intel/compiler/brw_vec4_cmod_propagation.cpp b/src/intel/compiler/brw_vec4_cmod_propagation.cpp
index 760327d559d..a7a3bb8fb06 100644
--- a/src/intel/compiler/brw_vec4_cmod_propagation.cpp
+++ b/src/intel/compiler/brw_vec4_cmod_propagation.cpp
@@ -173,19 +173,19 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v)
/* Given a sequence like:
*
- * cmp.ge.f0(8) g21<1>.xF g20<4>.xF g18<4>.xF
+ * cmp.ge.f0(8) g21<1>.zF g20<4>.xF g18<4>.xF
* ...
- * cmp.nz.f0(8) null<1>D g21<4>.xD 0D
+ * cmp.nz.f0(8) null<1>D g21<4>.zD 0D
*
* Replace it with something like:
*
- * cmp.ge.f0(8) g22<1>F g20<4>.xF g18<4>.xF
- * mov(8) g21<1>.xF g22<1>.xxxxF
+ * cmp.ge.f0(8) g22<1>.zF g20<4>.xF g18<4>.xF
+ * mov(8) g21<1>.xF g22<1>.zzzzF
*
* The added MOV will most likely be removed later. In the
* worst case, it should be cheaper to schedule.
*/
- temp.swizzle = inst->src[0].swizzle;
+ temp.swizzle = brw_swizzle_for_mask(inst->dst.writemask);
temp.type = scan_inst->src[0].type;
vec4_instruction *mov = v->MOV(scan_inst->dst, temp);
diff --git a/src/intel/compiler/test_fs_cmod_propagation.cpp b/src/intel/compiler/test_fs_cmod_propagation.cpp
index 659fbb2d1bc..4215af1fb02 100644
--- a/src/intel/compiler/test_fs_cmod_propagation.cpp
+++ b/src/intel/compiler/test_fs_cmod_propagation.cpp
@@ -889,3 +889,35 @@ TEST_F(cmod_propagation_test, subtract_delete_compare_derp)
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode);
EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate);
}
+
+TEST_F(cmod_propagation_test, signed_unsigned_comparison_mismatch)
+{
+ const fs_builder &bld = v->bld;
+ fs_reg dest0 = v->vgrf(glsl_type::int_type);
+ fs_reg src0 = v->vgrf(glsl_type::int_type);
+ src0.type = BRW_REGISTER_TYPE_W;
+
+ bld.ASR(dest0, negate(src0), brw_imm_d(15));
+ bld.CMP(bld.null_reg_ud(), retype(dest0, BRW_REGISTER_TYPE_UD),
+ brw_imm_ud(0u), BRW_CONDITIONAL_LE);
+
+ /* = Before =
+ * 0: asr(8) dest:D -src0:W 15D
+ * 1: cmp.le.f0(8) null:UD dest:UD 0UD
+ *
+ * = After =
+ * (no changes)
+ */
+ v->calculate_cfg();
+ bblock_t *block0 = v->cfg->blocks[0];
+
+ EXPECT_EQ(0, block0->start_ip);
+ EXPECT_EQ(1, block0->end_ip);
+
+ EXPECT_FALSE(cmod_propagation(v));
+ EXPECT_EQ(0, block0->start_ip);
+ EXPECT_EQ(1, block0->end_ip);
+ EXPECT_EQ(BRW_OPCODE_ASR, instruction(block0, 0)->opcode);
+ EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode);
+ EXPECT_EQ(BRW_CONDITIONAL_LE, instruction(block0, 1)->conditional_mod);
+}
diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index 5dbd0607572..625ebc031dc 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -414,6 +414,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3 = {
.has_64bit_types = true, \
.supports_simd16_3src = true, \
.has_surface_tile_offset = true, \
+ .num_thread_per_eu = 7, \
.max_vs_threads = 504, \
.max_tcs_threads = 504, \
.max_tes_threads = 504, \
@@ -427,7 +428,6 @@ static const struct gen_device_info gen_device_info_bdw_gt1 = {
.num_slices = 1,
.num_subslices = { 2, },
.num_eu_per_subslice = 8,
- .num_thread_per_eu = 7,
.l3_banks = 2,
.max_cs_threads = 42,
.urb = {
@@ -452,7 +452,6 @@ static const struct gen_device_info gen_device_info_bdw_gt2 = {
.num_slices = 1,
.num_subslices = { 3, },
.num_eu_per_subslice = 8,
- .num_thread_per_eu = 7,
.l3_banks = 4,
.max_cs_threads = 56,
.urb = {
@@ -477,7 +476,6 @@ static const struct gen_device_info gen_device_info_bdw_gt3 = {
.num_slices = 2,
.num_subslices = { 3, 3, },
.num_eu_per_subslice = 8,
- .num_thread_per_eu = 7,
.l3_banks = 8,
.max_cs_threads = 56,
.urb = {
@@ -503,7 +501,6 @@ static const struct gen_device_info gen_device_info_chv = {
.num_slices = 1,
.num_subslices = { 2, },
.num_eu_per_subslice = 8,
- .num_thread_per_eu = 7,
.l3_banks = 2,
.max_vs_threads = 80,
.max_tcs_threads = 80,
@@ -609,8 +606,7 @@ static const struct gen_device_info gen_device_info_chv = {
#define GEN9_FEATURES \
GEN8_FEATURES, \
GEN9_HW_INFO, \
- .has_sample_with_hiz = true, \
- .num_thread_per_eu = 7
+ .has_sample_with_hiz = true
static const struct gen_device_info gen_device_info_skl_gt1 = {
GEN9_FEATURES, .gt = 1,
@@ -777,6 +773,7 @@ static const struct gen_device_info gen_device_info_cfl_gt1 = {
.num_subslices = { 2, },
.num_eu_per_subslice = 6,
.l3_banks = 2,
+ .urb.size = 192,
.simulator_id = 24,
};
static const struct gen_device_info gen_device_info_cfl_gt2 = {
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index 284633aedd4..4cb1f05ae25 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -2043,7 +2043,10 @@
+
+
-
+
-
+
+
+
+
+
@@ -229,6 +234,9 @@ TODO: document the other workarounds.
+
+
+
+
@@ -423,8 +434,17 @@ TODO: document the other workarounds.
+
+
+
+
+
+
diff --git a/src/util/Android.mk b/src/util/Android.mk
index 2d59e1ae15e..6d770ca9575 100644
--- a/src/util/Android.mk
+++ b/src/util/Android.mk
@@ -41,8 +41,14 @@ LOCAL_C_INCLUDES := \
$(MESA_TOP)/src/gallium/include \
$(MESA_TOP)/src/gallium/auxiliary
+# If Android version >=8 MESA should static link libexpat else should dynamic link
+ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0)
+LOCAL_STATIC_LIBRARIES := \
+ libexpat
+else
LOCAL_SHARED_LIBRARIES := \
libexpat
+endif
LOCAL_MODULE := libmesa_util
diff --git a/src/util/bitscan.h b/src/util/bitscan.h
index dc89ac93f28..cdfecafaf01 100644
--- a/src/util/bitscan.h
+++ b/src/util/bitscan.h
@@ -112,6 +112,31 @@ u_bit_scan64(uint64_t *mask)
return i;
}
+/* Count bits set in mask */
+static inline int
+u_count_bits(unsigned *mask)
+{
+ unsigned v = *mask;
+ int c;
+ v = v - ((v >> 1) & 0x55555555);
+ v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
+ v = (v + (v >> 4)) & 0xF0F0F0F;
+ c = (int)((v * 0x1010101) >> 24);
+ return c;
+}
+
+static inline int
+u_count_bits64(uint64_t *mask)
+{
+ uint64_t v = *mask;
+ int c;
+ v = v - ((v >> 1) & 0x5555555555555555ull);
+ v = (v & 0x3333333333333333ull) + ((v >> 2) & 0x3333333333333333ull);
+ v = (v + (v >> 4)) & 0xF0F0F0F0F0F0F0Full;
+ c = (int)((v * 0x101010101010101ull) >> 56);
+ return c;
+}
+
/* Determine if an unsigned value is a power of two.
*
* \note
diff --git a/src/util/bitset.h b/src/util/bitset.h
index 3b18abac793..7ccfffad45f 100644
--- a/src/util/bitset.h
+++ b/src/util/bitset.h
@@ -62,8 +62,8 @@
#define BITSET_SET(x, b) ((x)[BITSET_BITWORD(b)] |= BITSET_BIT(b))
#define BITSET_CLEAR(x, b) ((x)[BITSET_BITWORD(b)] &= ~BITSET_BIT(b))
-#define BITSET_MASK(b) ((b) == BITSET_WORDBITS ? ~0 : BITSET_BIT(b) - 1)
-#define BITSET_RANGE(b, e) (BITSET_MASK((e) + 1) & ~BITSET_MASK(b))
+#define BITSET_MASK(b) (((b) % BITSET_WORDBITS == 0) ? ~0 : BITSET_BIT(b) - 1)
+#define BITSET_RANGE(b, e) ((BITSET_MASK((e) + 1)) & ~(BITSET_BIT(b) - 1))
/* bit range operations
*/
diff --git a/src/util/merge_driinfo.py b/src/util/merge_driinfo.py
index e6ccca5e0f3..a09218a3902 100644
--- a/src/util/merge_driinfo.py
+++ b/src/util/merge_driinfo.py
@@ -52,6 +52,14 @@ def __init__(self, name, defaults):
self.defaults = defaults
+class Verbatim(object):
+ """
+ Represent a chunk of code that is copied into the result file verbatim.
+ """
+ def __init__(self):
+ self.string = ''
+
+
class Section(object):
"""
Represent a config section description as:
@@ -75,8 +83,29 @@ def parse_inputs(input_filenames):
section = None
linenum = 0
+ verbatim = None
for line in infile:
linenum += 1
+
+ if line.startswith('//= BEGIN VERBATIM'):
+ if verbatim is not None:
+ print('{}:{}: nested verbatim'
+ .format(input_filename, linenum))
+ success = False
+ continue
+ verbatim = Verbatim()
+
+ if verbatim is not None:
+ verbatim.string += line
+
+ if line.startswith('//= END VERBATIM'):
+ if section is None:
+ sections.append(verbatim)
+ else:
+ section.options.append(verbatim)
+ verbatim = None
+ continue
+
line = line.strip()
if not line:
continue
@@ -144,12 +173,17 @@ def merge_sections(section_list):
assert section.name == merged_section.name
for orig_option in section.options:
- for merged_option in merged_section.options:
- if orig_option.name == merged_option.name:
- merged_option.defaults = orig_option.defaults
- break
+ if isinstance(orig_option, Option):
+ for merged_option in merged_section.options:
+ if not isinstance(merged_option, Option):
+ continue
+ if orig_option.name == merged_option.name:
+ merged_option.defaults = orig_option.defaults
+ break
+ else:
+ merged_section.options.append(Option(orig_option.name, orig_option.defaults))
else:
- merged_section.options.append(Option(orig_option.name, orig_option.defaults))
+ merged_section.options.append(orig_option)
return merged_section
@@ -164,6 +198,10 @@ def merge_sections_lists(sections_lists):
for idx,sections in enumerate(sections_lists):
for base_section in sections:
+ if not isinstance(base_section, Section):
+ merged_sections.append(base_section)
+ continue
+
original_sections = [base_section]
for next_sections in sections_lists[idx+1:]:
for j,section in enumerate(next_sections):
@@ -201,15 +239,23 @@ def main(input_filenames):
DRI_CONF_BEGIN
% for section in sections:
+% if isinstance(section, Section):
DRI_CONF_SECTION_${section.name}
% for option in section.options:
+% if isinstance(option, Option):
DRI_CONF_${option.name}(${option.defaults})
+% else:
+${option.string}
+% endif
% endfor
DRI_CONF_SECTION_END
+% else:
+${section.string}
+% endif
% endfor
DRI_CONF_END""")
- print(driinfo_h_template.render(sections=merged_sections_list))
+ print(driinfo_h_template.render(sections=merged_sections_list, Section=Section, Option=Option))
return True
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index 80ddf0e203e..dd2b5c21760 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -338,12 +338,8 @@ DRI_CONF_OPT_BEGIN_B(radeonsi_commutative_blend_add, def) \
DRI_CONF_DESC(en,gettext("Commutative additive blending optimizations (may cause rendering errors)")) \
DRI_CONF_OPT_END
-#define DRI_CONF_RADEONSI_CLEAR_DB_CACHE_BEFORE_CLEAR(def) \
-DRI_CONF_OPT_BEGIN_B(radeonsi_clear_db_cache_before_clear, def) \
- DRI_CONF_DESC(en,"Clear DB cache before fast depth clear") \
-DRI_CONF_OPT_END
-
#define DRI_CONF_RADEONSI_ZERO_ALL_VRAM_ALLOCS(def) \
DRI_CONF_OPT_BEGIN_B(radeonsi_zerovram, def) \
DRI_CONF_DESC(en,"Zero all vram allocations") \
DRI_CONF_OPT_END
+
diff --git a/src/vulkan/Android.mk b/src/vulkan/Android.mk
index 6253f1c3be9..99dd3f56313 100644
--- a/src/vulkan/Android.mk
+++ b/src/vulkan/Android.mk
@@ -39,6 +39,14 @@ LOCAL_C_INCLUDES := \
$(MESA_TOP)/include/vulkan \
$(MESA_TOP)/src/vulkan/util
+ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0)
+LOCAL_C_INCLUDES += \
+ frameworks/native/libs/nativebase/include \
+ frameworks/native/libs/nativewindow/include \
+ frameworks/native/libs/arect/include
+LOCAL_HEADER_LIBRARIES += libcutils_headers libsystem_headers
+endif
+
LOCAL_GENERATED_SOURCES := $(addprefix $(intermediates)/, \
$(VULKAN_UTIL_GENERATED_FILES))
diff --git a/src/vulkan/wsi/wsi_common_display.c b/src/vulkan/wsi/wsi_common_display.c
index 20209b0cbd0..ccde1e0e679 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -960,8 +960,8 @@ static void
wsi_display_destroy_buffer(struct wsi_display *wsi,
uint32_t buffer)
{
- (void) drmIoctl(wsi->fd, DRM_IOCTL_MODE_DESTROY_DUMB,
- &((struct drm_mode_destroy_dumb) { .handle = buffer }));
+ (void) drmIoctl(wsi->fd, DRM_IOCTL_GEM_CLOSE,
+ &((struct drm_gem_close) { .handle = buffer }));
}
static VkResult
@@ -1798,6 +1798,30 @@ wsi_init_pthread_cond_monotonic(pthread_cond_t *cond)
return ret;
}
+
+/*
+ * Local version fo the libdrm helper. Added to avoid depending on bleeding
+ * edge version of the library.
+ */
+static int
+local_drmIsMaster(int fd)
+{
+ /* Detect master by attempting something that requires master.
+ *
+ * Authenticating magic tokens requires master and 0 is an
+ * internal kernel detail which we could use. Attempting this on
+ * a master fd would fail therefore fail with EINVAL because 0
+ * is invalid.
+ *
+ * A non-master fd will fail with EACCES, as the kernel checks
+ * for master before attempting to do anything else.
+ *
+ * Since we don't want to leak implementation details, use
+ * EACCES.
+ */
+ return drmAuthMagic(fd, 0) != -EACCES;
+}
+
VkResult
wsi_display_init_wsi(struct wsi_device *wsi_device,
const VkAllocationCallbacks *alloc,
@@ -1813,6 +1837,9 @@ wsi_display_init_wsi(struct wsi_device *wsi_device,
}
wsi->fd = display_fd;
+ if (wsi->fd != -1 && !local_drmIsMaster(wsi->fd))
+ wsi->fd = -1;
+
wsi->alloc = alloc;
list_inithead(&wsi->connectors);
diff --git a/src/vulkan/wsi/wsi_common_wayland.c b/src/vulkan/wsi/wsi_common_wayland.c
index c0132566ead..82139de31d9 100644
--- a/src/vulkan/wsi/wsi_common_wayland.c
+++ b/src/vulkan/wsi/wsi_common_wayland.c
@@ -701,9 +701,14 @@ wsi_wl_swapchain_acquire_next_image(struct wsi_swapchain *wsi_chain,
}
}
- /* This time we do a blocking dispatch because we can't go
- * anywhere until we get an event.
+ /* We now have to do a blocking dispatch, because all our images
+ * are in use and we cannot return one until the server does. However,
+ * if the client has requested non-blocking ANI, then we tell it up front
+ * that we have nothing to return.
*/
+ if (info->timeout == 0)
+ return VK_NOT_READY;
+
int ret = wl_display_roundtrip_queue(chain->display->wl_display,
chain->display->queue);
if (ret < 0)