From 2c9a8b02bc6d0fd19fdb434f76dd67a487a6e7af Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Tue, 1 Jun 2021 12:41:30 +0200 Subject: [PATCH] Optional BRAM-based register file on Altera --- altera_regs.v | 256 ++++++++++++++++++++++++++++++++++++++++++++++++++ fx68k.sv | 138 +++++++++++++++++++++++---- 2 files changed, 374 insertions(+), 20 deletions(-) create mode 100644 altera_regs.v diff --git a/altera_regs.v b/altera_regs.v new file mode 100644 index 0000000..c9d1de8 --- /dev/null +++ b/altera_regs.v @@ -0,0 +1,256 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: altera_regs.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module altera_regs ( + address_a, + address_b, + byteena_a, + byteena_b, + clock, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [4:0] address_a; + input [4:0] address_b; + input [1:0] byteena_a; + input [1:0] byteena_b; + input clock; + input [15:0] data_a; + input [15:0] data_b; + input wren_a; + input wren_b; + output [15:0] q_a; + output [15:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 [1:0] byteena_a; + tri1 [1:0] byteena_b; + tri1 clock; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] sub_wire1; + wire [15:0] q_a = sub_wire0[15:0]; + wire [15:0] q_b = sub_wire1[15:0]; + + altsyncram altsyncram_component ( + .byteena_a (byteena_a), + .clock0 (clock), + .wren_a (wren_a), + .address_b (address_b), + .byteena_b (byteena_b), + .data_b (data_b), + .wren_b (wren_b), + .address_a (address_a), + .data_a (data_a), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.byteena_reg_b = "CLOCK0", + altsyncram_component.byte_size = 8, + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK0", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 32, + altsyncram_component.numwords_b = 32, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 5, + altsyncram_component.widthad_b = 5, + altsyncram_component.width_a = 16, + altsyncram_component.width_b = 16, + altsyncram_component.width_byteena_a = 2, + altsyncram_component.width_byteena_b = 2, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "1" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "0" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: BYTEENA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "2" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: USED_PORT: address_a 0 0 5 0 INPUT NODEFVAL "address_a[4..0]" +// Retrieval info: USED_PORT: address_b 0 0 5 0 INPUT NODEFVAL "address_b[4..0]" +// Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC "byteena_a[1..0]" +// Retrieval info: USED_PORT: byteena_b 0 0 2 0 INPUT VCC "byteena_b[1..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]" +// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]" +// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]" +// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 5 0 address_a 0 0 5 0 +// Retrieval info: CONNECT: @address_b 0 0 5 0 address_b 0 0 5 0 +// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0 +// Retrieval info: CONNECT: @byteena_b 0 0 2 0 byteena_b 0 0 2 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0 +// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL altera_regs.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL altera_regs.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL altera_regs.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL altera_regs.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL altera_regs_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL altera_regs_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/fx68k.sv b/fx68k.sv index 2314685..9224633 100644 --- a/fx68k.sv +++ b/fx68k.sv @@ -16,6 +16,12 @@ Most systems don't need this. Note that these signals are not registered. */ +//`define FX68K_ALTERA_REGS +/* + Define FX68K_ALTERA_REGS to instantiate 2 BRAM blocks for the register file. Frees up ~2000 Logic Cells on Cyclone III. + Note: It's Altera specific, as it requires byte enables. +*/ + // Define this to run a self contained compilation test build // `define FX68K_TEST @@ -1169,11 +1175,64 @@ module excUnit( input s_clks Clks, localparam REG_USP = 15; localparam REG_SSP = 16; localparam REG_DT = 17; - + // Register file + reg [15:0] regs68L_x; + reg [15:0] regs68L_y; + reg [15:0] regs68H_x; + reg [15:0] regs68H_y; + +`ifdef FX68K_ALTERA_REGS + reg [15:0] regs68L_dx; + reg [15:0] regs68L_dy; + reg regs68L_we_x, regs68L_we_y; + reg regs68L_byte; + + altera_regs regs68L ( + .clock(!Clks.clk), + .address_a(actualRx), + .byteena_a({!regs68L_byte, 1'b1}), + .wren_a(regs68L_we_x), + .data_a(regs68L_dx), + .q_a(regs68L_x), + .address_b(actualRy), + .byteena_b({!regs68L_byte, 1'b1}), + .wren_b(regs68L_we_y), + .data_b(regs68L_dy), + .q_b(regs68L_y) + ); + + reg [15:0] regs68H_dx; + reg [15:0] regs68H_dy; + reg regs68H_we_x, regs68H_we_y; + + altera_regs regs68H ( + .clock(!Clks.clk), + .address_a(actualRx), + .byteena_a(2'b11), + .wren_a(regs68H_we_x), + .data_a(regs68H_dx), + .q_a(regs68H_x), + .address_b(actualRy), + .byteena_b(2'b11), + .wren_b(regs68H_we_y), + .data_b(regs68H_dy), + .q_b(regs68H_y) + ); + +`else + reg [15:0] regs68L[ 18]; reg [15:0] regs68H[ 18]; - + + always_comb begin + regs68L_x = regs68L[actualRx]; + regs68L_y = regs68L[actualRy]; + regs68H_x = regs68H[actualRx]; + regs68H_y = regs68H[actualRy]; + end +`endif // FX68K_ALTERA_REGS + // synthesis translate off /* It is bad practice to initialize simulation registers that the hardware doesn't. @@ -1331,8 +1390,8 @@ localparam REG_DT = 17; {dbhIdle, dblIdle, dbdIdle} = '0; unique case( 1'b1) - ryl2Dbd: dbdMux = regs68L[ actualRy]; - rxl2Dbd: dbdMux = regs68L[ actualRx]; + ryl2Dbd: dbdMux = regs68L_y; + rxl2Dbd: dbdMux = regs68L_x; Nanod.alue2Dbd: dbdMux = alue; Nanod.dbin2Dbd: dbdMux = dbin; Nanod.alu2Dbd: dbdMux = aluOut; @@ -1341,8 +1400,8 @@ localparam REG_DT = 17; endcase unique case( 1'b1) - rxl2Dbl: dblMux = regs68L[ actualRx]; - ryl2Dbl: dblMux = regs68L[ actualRy]; + rxl2Dbl: dblMux = regs68L_x; + ryl2Dbl: dblMux = regs68L_y; Nanod.ftu2Dbl: dblMux = ftu; Nanod.au2Db: dblMux = auReg[15:0]; Nanod.atl2Dbl: dblMux = Atl; @@ -1351,8 +1410,8 @@ localparam REG_DT = 17; endcase unique case( 1'b1) - Nanod.rxh2dbh: dbhMux = regs68H[ actualRx]; - Nanod.ryh2dbh: dbhMux = regs68H[ actualRy]; + Nanod.rxh2dbh: dbhMux = regs68H_x; + Nanod.ryh2dbh: dbhMux = regs68H_y; Nanod.au2Db: dbhMux = auReg[31:16]; Nanod.ath2Dbh: dbhMux = Ath; Pch2Dbh: dbhMux = PcH; @@ -1360,8 +1419,8 @@ localparam REG_DT = 17; endcase unique case( 1'b1) - ryl2Abd: abdMux = regs68L[ actualRy]; - rxl2Abd: abdMux = regs68L[ actualRx]; + ryl2Abd: abdMux = regs68L_y; + rxl2Abd: abdMux = regs68L_x; Nanod.dbin2Abd: abdMux = dbin; Nanod.alu2Abd: abdMux = aluOut; default: begin abdMux = 'X; abdIdle = 1'b1; end @@ -1369,8 +1428,8 @@ localparam REG_DT = 17; unique case( 1'b1) Pcl2Abl: ablMux = PcL; - rxl2Abl: ablMux = regs68L[ actualRx]; - ryl2Abl: ablMux = regs68L[ actualRy]; + rxl2Abl: ablMux = regs68L_x; + ryl2Abl: ablMux = regs68L_y; Nanod.ftu2Abl: ablMux = ftu; Nanod.au2Ab: ablMux = auReg[15:0]; Nanod.aob2Ab: ablMux = aob[15:0]; @@ -1380,8 +1439,8 @@ localparam REG_DT = 17; unique case( 1'b1) Pch2Abh: abhMux = PcH; - Nanod.rxh2abh: abhMux = regs68H[ actualRx]; - Nanod.ryh2abh: abhMux = regs68H[ actualRy]; + Nanod.rxh2abh: abhMux = regs68H_x; + Nanod.ryh2abh: abhMux = regs68H_y; Nanod.au2Ab: abhMux = auReg[31:16]; Nanod.aob2Ab: abhMux = aob[31:16]; Nanod.ath2Abh: abhMux = Ath; @@ -1518,8 +1577,47 @@ localparam REG_DT = 17; // Main A/D registers - always_ff @( posedge Clks.clk) begin - if( enT3) begin + always_ff @( posedge Clks.clk) begin +`ifdef FX68K_ALTERA_REGS + regs68L_byte <= 0; + { regs68L_we_x, regs68L_we_y } <= 0; + { regs68H_we_x, regs68H_we_y } <= 0; +`endif + + if( enT3) begin +`ifdef FX68K_ALTERA_REGS + if( Nanod.dbl2rxl | Nanod.abl2rxl) begin + regs68L_we_x <= 1; + if( ~rxIsAreg) begin + if( Nanod.dbl2rxl) regs68L_dx <= Dbd; + else if( abdIsByte) begin regs68L_dx[7:0] <= Abd[7:0]; regs68L_byte <= 1; end + else regs68L_dx <= Abd; + end + else + regs68L_dx <= Nanod.dbl2rxl ? Dbl : Abl; + end + if( Nanod.dbl2ryl | Nanod.abl2ryl) begin + regs68L_we_y <= 1; + if( ~ryIsAreg) begin + if( Nanod.dbl2ryl) regs68L_dy <= Dbd; + else if( abdIsByte) begin regs68L_dy[7:0] <= Abd[7:0]; regs68L_byte <= 1; end + else regs68L_dy <= Abd; + end + else + regs68L_dy <= Nanod.dbl2ryl ? Dbl : Abl; + end + // High registers are easier. Both A & D on the same buses, and not byte ops. + if( Nanod.dbh2rxh | Nanod.abh2rxh) begin + regs68H_dx <= Nanod.dbh2rxh ? Dbh : Abh; + regs68H_we_x <= 1; + end + if( Nanod.dbh2ryh | Nanod.abh2ryh) begin + regs68H_dy <= Nanod.dbh2ryh ? Dbh : Abh; + regs68H_we_y <= 1; + end + +`else + if( Nanod.dbl2rxl | Nanod.abl2rxl) begin if( ~rxIsAreg) begin if( Nanod.dbl2rxl) regs68L[ actualRx] <= Dbd; @@ -1529,7 +1627,7 @@ localparam REG_DT = 17; else regs68L[ actualRx] <= Nanod.dbl2rxl ? Dbl : Abl; end - + if( Nanod.dbl2ryl | Nanod.abl2ryl) begin if( ~ryIsAreg) begin if( Nanod.dbl2ryl) regs68L[ actualRy] <= Dbd; @@ -1539,14 +1637,14 @@ localparam REG_DT = 17; else regs68L[ actualRy] <= Nanod.dbl2ryl ? Dbl : Abl; end - + // High registers are easier. Both A & D on the same buses, and not byte ops. if( Nanod.dbh2rxh | Nanod.abh2rxh) regs68H[ actualRx] <= Nanod.dbh2rxh ? Dbh : Abh; if( Nanod.dbh2ryh | Nanod.abh2ryh) regs68H[ actualRy] <= Nanod.dbh2ryh ? Dbh : Abh; - - end +`endif // FX68K_ALTERA_REGS + end end // PC & AT