From 670983364016eb82ccdd5a603ca22d8530b14c8f Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Fri, 28 Aug 2020 18:46:14 +0200
Subject: [PATCH 01/16] Fixed some verilator warnings

---
 fx68k.sv     | 4776 +++++++++++++++++++++++++-------------------------
 fx68kAlu.sv  | 1611 ++++++++---------
 fx68k_pkg.sv |  160 ++
 uaddrPla.sv  | 3107 ++++++++++++++++----------------
 4 files changed, 4891 insertions(+), 4763 deletions(-)
 create mode 100644 fx68k_pkg.sv

diff --git a/fx68k.sv b/fx68k.sv
index 7510f6b..c5660ae 100644
--- a/fx68k.sv
+++ b/fx68k.sv
@@ -3,7 +3,7 @@
 //
 // M68000 cycle accurate, fully synchronous
 // Copyright (c) 2018 by Jorge Cwik
-// 
+//
 // TODO:
 // - Everything except bus retry already implemented.
 
@@ -12,903 +12,824 @@
 // Define this to run a self contained compilation test build
 // `define FX68K_TEST
 
-localparam CF = 0, VF = 1, ZF = 2, NF = 3, XF = 4, SF = 13;
-
-localparam UADDR_WIDTH = 10;
-localparam UROM_WIDTH = 17;
-localparam UROM_DEPTH = 1024;
-
-localparam NADDR_WIDTH = 9;
-localparam NANO_WIDTH = 68;
-localparam NANO_DEPTH = 336;
-
-localparam BSER1_NMA = 'h003;
-localparam RSTP0_NMA = 'h002;
-localparam HALT1_NMA = 'h001;
-localparam TRAC1_NMA = 'h1C0;
-localparam ITLX1_NMA = 'h1C4;
-
-localparam TVN_SPURIOUS = 12;
-localparam TVN_AUTOVEC = 13;
-localparam TVN_INTERRUPT = 15;
-
-localparam NANO_DOB_DBD = 2'b01;
-localparam NANO_DOB_ADB = 2'b10;
-localparam NANO_DOB_ALU = 2'b11;
-
-
-// Clocks, phases and resets
-typedef struct {
-	logic clk;
-	logic extReset;			// External sync reset on emulated system
-	logic pwrUp;			// Asserted together with reset on emulated system coldstart
-	logic enPhi1, enPhi2;	// Clock enables. Next cycle is PHI1 or PHI2
-} s_clks;
-
-// IRD decoded signals
-typedef struct {
-	logic isPcRel;
-	logic isTas;
-	logic implicitSp;
-	logic toCcr;
-	logic rxIsDt, ryIsDt;
-	logic rxIsUsp, rxIsMovem, movemPreDecr;
-	logic isByte;
-	logic isMovep;
-	logic [2:0] rx, ry;
-	logic rxIsAreg, ryIsAreg;
-	logic [15:0] ftuConst;
-	logic [5:0] macroTvn;
-	logic inhibitCcr;
-} s_irdecod;
-
-// Nano code decoded signals
-typedef struct {
-	logic permStart;
-	logic waitBusFinish;
-	logic isWrite;
-	logic busByte;
-	logic isRmc;
-	logic noLowByte, noHighByte;
-	
-	logic updTpend, clrTpend;
-	logic tvn2Ftu, const2Ftu;
-	logic ftu2Dbl, ftu2Abl;
-	logic abl2Pren, updPren;
-	logic inl2psw, ftu2Sr, sr2Ftu, ftu2Ccr, pswIToFtu;
-	logic ird2Ftu, ssw2Ftu;
-	logic initST;
-	logic Ir2Ird;
-	
-	logic auClkEn, noSpAlign;
-	logic [2:0] auCntrl;
-	logic todbin, toIrc;
-	logic dbl2Atl, abl2Atl, atl2Abl, atl2Dbl;
-	logic abh2Ath, dbh2Ath;
-	logic ath2Dbh, ath2Abh;
-	
-	logic db2Aob, ab2Aob, au2Aob;
-	logic aob2Ab, updSsw;
-	// logic adb2Dob, dbd2Dob, alu2Dob;
-	logic [1:0] dobCtrl;
-	
-	logic abh2reg, abl2reg;
-	logic reg2abl, reg2abh;
-	logic dbh2reg, dbl2reg;
-	logic reg2dbl, reg2dbh;
-	logic ssp, pchdbh, pcldbl, pclabl, pchabh;
-	
-	logic rxh2dbh, rxh2abh;
-	logic dbl2rxl, dbh2rxh;
-	logic rxl2db, rxl2ab;
-	logic abl2rxl, abh2rxh;
-	logic dbh2ryh, abh2ryh;
-	logic ryl2db, ryl2ab;
-	logic ryh2dbh, ryh2abh;
-	logic dbl2ryl, abl2ryl;
-	logic rz;
-	logic rxlDbl;
-	
-	logic [2:0] aluColumn;
-	logic [1:0] aluDctrl;
-	logic aluActrl;
-	logic aluInit, aluFinish;
-	logic abd2Dcr, dcr2Dbd;
-	logic dbd2Alue, alue2Dbd;
-	logic dbd2Alub, abd2Alub;
-	
-	logic alu2Dbd, alu2Abd;
-	logic au2Db, au2Ab, au2Pc;
-	logic dbin2Abd, dbin2Dbd;
-	logic extDbh, extAbh;
-	logic ablAbd, ablAbh;
-	logic dblDbd, dblDbh;
-	logic abdIsByte;
-} s_nanod;
-
-module fx68k(
-	input clk,
-	input HALTn,					// Used for single step only. Force high if not used
-	// input logic HALTn = 1'b1,			// Not all tools support default port values
-	
-	// These two signals don't need to be registered. They are not async reset.
-	input extReset,			// External sync reset on emulated system
-	input pwrUp,			// Asserted together with reset on emulated system coldstart	
-	input enPhi1, enPhi2,	// Clock enables. Next cycle is PHI1 or PHI2
-
-	output eRWn, output ASn, output LDSn, output UDSn,
-	output logic E, output VMAn,	
-	output FC0, output FC1, output FC2,
-	output BGn,
-	output oRESETn, output oHALTEDn,
-	input DTACKn, input VPAn,
-	input BERRn,
-	input BRn, BGACKn,
-	input IPL0n, input IPL1n, input IPL2n,
-	input [15:0] iEdb, output [15:0] oEdb,
-	output [23:1] eab
-	);
-	
-	// wire clock = Clks.clk;
-	s_clks Clks;
-	
-	assign Clks.clk = clk;	
-	assign Clks.extReset = extReset;
-	assign Clks.pwrUp = pwrUp;	
-	assign Clks.enPhi1 = enPhi1;
-	assign Clks.enPhi2 = enPhi2;
-	
-	wire wClk;
-	
-	// Internal sub clocks T1-T4
-	enum int unsigned { T0 = 0, T1, T2, T3, T4} tState;
-	wire enT1 = Clks.enPhi1 & (tState == T4) & ~wClk;
-	wire enT2 = Clks.enPhi2 & (tState == T1);
-	wire enT3 = Clks.enPhi1 & (tState == T2);
-	wire enT4 = Clks.enPhi2 & ((tState == T0) | (tState == T3));
-	
-	// T4 continues ticking during reset and group0 exception.
-	// We also need it to erase ucode output latched on T4.
-	always_ff @( posedge Clks.clk) begin
-		if( Clks.pwrUp)
-			tState <= T0;
-		else begin
-		case( tState)
-		T0: if( Clks.enPhi2) tState <= T4;
-		T1: if( Clks.enPhi2) tState <= T2;
-		T2: if( Clks.enPhi1) tState <= T3;
-		T3: if( Clks.enPhi2) tState <= T4;
-		T4: if( Clks.enPhi1) tState <= wClk ? T0 : T1;
-		endcase
-		end
-	end
-	
-	// The following signals are synchronized with 3 couplers, phi1-phi2-phi1.
-	// Will be valid internally one cycle later if changed at the rasing edge of the clock.
-	//
-	// DTACK, BERR
-		
-	// DTACK valid at S6 if changed at the rasing edge of S4 to avoid wait states.
-	// SNC (sncClkEn) is deasserted together (unless DTACK asserted too early).
-	//	
-	// We synchronize some signals half clock earlier. We compensate later
-	reg rDtack, rBerr;
-	reg [2:0] rIpl, iIpl;	
-	reg Vpai, BeI, Halti, BRi, BgackI, BeiDelay;
-	// reg rBR, rHALT;
-	wire BeDebounced = ~( BeI | BeiDelay);
-
-	always_ff @( posedge Clks.clk) begin
-		if( Clks.pwrUp) begin
-			rBerr <= 1'b0;
-			BeI <= 1'b0;
-		end
-		else if( Clks.enPhi2) begin
-			rDtack <= DTACKn;
-			rBerr <= BERRn;
-			rIpl <= ~{ IPL2n, IPL1n, IPL0n};
-			iIpl <= rIpl;
-			
-			// Needed for cycle accuracy but only if BR or HALT are asserted on the wrong edge of the clock			
-			// rBR <= BRn;
-			// rHALT <= HALTn;
-		end
-		else if( Clks.enPhi1) begin
-			Vpai <= VPAn;
-			BeI <= rBerr;
-			BeiDelay <= BeI;
-			BgackI <= BGACKn;
-			
-			BRi <= BRn;
-			Halti <= HALTn;
-			// BRi <= rBR;
-			// Halti <= rHALT;			
-		end	
-	end
-
-	// Instantiate micro and nano rom
-	logic [NANO_WIDTH-1:0] nanoLatch;
-	logic [NANO_WIDTH-1:0] nanoOutput;
-	logic [UROM_WIDTH-1:0] microLatch;
-	logic [UROM_WIDTH-1:0] microOutput;
-	
-	logic [UADDR_WIDTH-1:0] microAddr, nma; 
-	logic [NADDR_WIDTH-1:0] nanoAddr, orgAddr;
-	wire rstUrom;
-
-	// For the time being, address translation is done for nanorom only. 
-	microToNanoAddr microToNanoAddr( .uAddr( nma), .orgAddr);
-	
-	// Output of these modules will be updated at T2 at the latest (depending on clock division)
-	
-	nanoRom nanoRom( .clk( Clks.clk), .nanoAddr, .nanoOutput);
-	uRom uRom( .clk( Clks.clk), .microAddr, .microOutput);
-	
-	always_ff @( posedge Clks.clk) begin
-		// uaddr originally latched on T1, except bits 6 & 7, the conditional bits, on T2
-		// Seems we can latch whole address at either T1 or T2
-
-		// Originally it's invalid on hardware reset, and forced later when coming out of reset
-		if( Clks.pwrUp) begin
-			microAddr <= RSTP0_NMA;
-			nanoAddr <= RSTP0_NMA;
-		end
-		else if( enT1) begin
-			microAddr <= nma;
-			nanoAddr <= orgAddr;				// Register translated uaddr to naddr
-		end
-			
-		if( Clks.extReset) begin
-			microLatch <= '0;
-			nanoLatch <= '0;
-		end
-		else if( rstUrom) begin
-			// Originally reset these bits only. Not strictly needed like this.
-			// Can reset the whole register if it is important.
-			{ microLatch[16], microLatch[15], microLatch[0]} <= '0;
-			nanoLatch <= '0;
-		end
-		else if( enT3) begin
-			microLatch <= microOutput;
-			nanoLatch <= nanoOutput;
-		end
-					
-	end
-	
-
-	// Decoded nanocode signals
-	s_nanod Nanod;
-	// IRD decoded control signals
-	s_irdecod Irdecod;
-
-	//	
-	reg Tpend;
-	reg intPend;											// Interrupt pending
-	reg pswT, pswS;
-	reg [ 2:0] pswI;
-	wire [7:0] ccr;
-	
-	wire [15:0] psw = { pswT, 1'b0, pswS, 2'b00, pswI, ccr};
-
-	reg [15:0] ftu;
-	reg [15:0] Irc, Ir, Ird;
-	
-	wire [15:0] alue;
-	wire [15:0] Abl;
-	wire prenEmpty, au05z, dcr4, ze;
-	
-	wire [UADDR_WIDTH-1:0] a1, a2, a3;
-	wire isPriv, isIllegal, isLineA, isLineF;
-	
-
-	// IR & IRD forwarding
-	always_ff @( posedge Clks.clk) begin
-		if( enT1) begin
-			if( Nanod.Ir2Ird)
-				Ird <= Ir;
-			else if(microLatch[0])		// prevented by IR => IRD !
-				Ir <= Irc;
-		end
-	end
-	
-	wire [3:0] tvn;
-	wire waitBusCycle, busStarting;
-	wire BusRetry = 1'b0;
-	wire busAddrErr;
-	wire bciWrite;						// Last bus cycle was write
-	wire bgBlock, busAvail;
-	wire addrOe;
-
-	wire busIsByte = Nanod.busByte & (Irdecod.isByte | Irdecod.isMovep);
-	wire aob0;
-	
-	reg iStop;								// Internal signal for ending bus cycle
-	reg A0Err;								// Force bus/address error ucode
-	reg excRst;								// Signal reset exception to sequencer
-	reg BerrA;
-	reg Spuria, Avia;
-	wire Iac;
-	
-	reg rAddrErr, iBusErr, Err6591;
-	wire iAddrErr = rAddrErr & addrOe;		// To simulate async reset
-	wire enErrClk;
-
-	// Reset micro/nano latch after T4 of the current ublock.
-	assign rstUrom = Clks.enPhi1 & enErrClk;
-
-	uaddrDecode uaddrDecode( .opcode( Ir), .a1, .a2, .a3, .isPriv, .isIllegal, .isLineA, .isLineF, .lineBmap());
-
-	sequencer sequencer( .Clks, .enT3, .microLatch, .Ird,
-		.A0Err, .excRst, .BerrA, .busAddrErr, .Spuria, .Avia,
-		.Tpend, .intPend, .isIllegal, .isPriv, .isLineA, .isLineF,
-		.nma, .a1, .a2, .a3, .tvn,
-		.psw, .prenEmpty, .au05z, .dcr4, .ze, .alue01( alue[1:0]), .i11( Irc[ 11]) );
-
-	excUnit excUnit( .Clks, .Nanod, .Irdecod, .enT1, .enT2, .enT3, .enT4,
-		.Ird, .ftu, .iEdb, .pswS,
-		.prenEmpty, .au05z, .dcr4, .ze, .AblOut( Abl), .eab, .aob0, .Irc, .oEdb,
-		.alue, .ccr);
-
-	nDecoder3 nDecoder( .Clks, .Nanod, .Irdecod, .enT2, .enT4, .microLatch, .nanoLatch);
-	
-	irdDecode irdDecode( .ird( Ird), .Irdecod);
-	
-	busControl busControl( .Clks, .enT1, .enT4, .permStart( Nanod.permStart), .permStop( Nanod.waitBusFinish), .iStop,
-		.aob0, .isWrite( Nanod.isWrite), .isRmc( Nanod.isRmc), .isByte( busIsByte), .busAvail,
-		.bciWrite, .addrOe, .bgBlock, .waitBusCycle, .busStarting, .busAddrErr,
-		.rDtack, .BeDebounced, .Vpai,
-		.ASn, .LDSn, .UDSn, .eRWn);
-		
-	busArbiter busArbiter( .Clks, .BRi, .BgackI, .Halti, .bgBlock, .busAvail, .BGn);
-		
-		
-	// Output reset & halt control
-	wire [1:0] uFc = microLatch[ 16:15];
-	logic oReset, oHalted;
-	assign oRESETn = !oReset;
-	assign oHALTEDn = !oHalted;
-	
-	// FC without permStart is special, either reset or halt
-	always_ff @( posedge Clks.clk) begin
-		if( Clks.pwrUp) begin
-			oReset <= 1'b0;
-			oHalted <= 1'b0;
-		end
-		else if( enT1) begin
-			oReset <= (uFc == 2'b01) & !Nanod.permStart;
-			oHalted <= (uFc == 2'b10) & !Nanod.permStart;
-		end
-	end
-		
-	logic [2:0] rFC;
-	assign { FC2, FC1, FC0} = rFC;					// ~rFC;
-	assign Iac = {rFC == 3'b111};					// & Control output enable !!
-
-	always_ff @( posedge Clks.clk) begin
-		if( Clks.extReset)
-			rFC <= '0;
-		else if( enT1 & Nanod.permStart) begin		// S0 phase of bus cycle
-			rFC[2] <= pswS;
-			// If FC is type 'n' (0) at ucode, access type depends on PC relative mode		
-			// We don't care about RZ in this case. Those uinstructions with RZ don't start a bus cycle.
-			rFC[1] <= microLatch[ 16] | ( ~microLatch[ 15] & Irdecod.isPcRel);
-			rFC[0] <= microLatch[ 15] | ( ~microLatch[ 16] & ~Irdecod.isPcRel);
-		end
-	end
-	
-		
-	// IPL interface
-	reg [2:0] inl;							// Int level latch
-	reg updIll;
-	reg prevNmi;
-	
-	wire nmi = (iIpl == 3'b111);
-	wire iplStable = (iIpl == rIpl);
-	wire iplComp = iIpl > pswI;
-
-	always_ff @( posedge Clks.clk) begin
-		if( Clks.extReset) begin
-			intPend <= 1'b0;
-			prevNmi <= 1'b0;
-		end
-		else begin
-			if( Clks.enPhi2)
-				prevNmi <= nmi;
-				
-			// Originally async RS-Latch on PHI2, followed by a transparent latch on T2
-			// Tricky because they might change simultaneously
-			// Syncronous on PHI2 is equivalent as long as the output is read on T3!
-			
-			// Set on stable & NMI edge or compare
-			// Clear on: NMI Iack or (stable & !NMI & !Compare)
-
-			if( Clks.enPhi2) begin
-				if( iplStable & ((nmi & ~prevNmi) | iplComp) )
-					intPend <= 1'b1;
-				else if( ((inl == 3'b111) & Iac) | (iplStable & !nmi & !iplComp) )
-					intPend <= 1'b0;
-			end			
-		end
-		
-		if( Clks.extReset) begin
-			inl <= '1;
-			updIll <= 1'b0;
-		end
-		else if( enT4)
-			updIll <= microLatch[0];		// Update on any IRC->IR
-		else if( enT1 & updIll)
-			inl <= iIpl;					// Timing is correct.
-			
-		// Spurious interrupt, BERR on Interrupt Ack.
-		// Autovector interrupt. VPA on IACK.
-		// Timing is tight. Spuria is deasserted just after exception exception is recorded.
-		if( enT4) begin
-			Spuria <= ~BeiDelay & Iac;
-			Avia <= ~Vpai & Iac;
-		end
-			
-	end
-		
-	assign enErrClk = iAddrErr | iBusErr;
-	assign wClk = waitBusCycle | ~BeI | iAddrErr | Err6591;
-	
-	// E clock and counter, VMA
-	reg [3:0] eCntr;
-	reg rVma;
-	
-	assign VMAn = rVma;
-	
-	// Internal stop just one cycle before E falling edge
-	wire xVma = ~rVma & (eCntr == 8);
-	
-	always_ff @( posedge Clks.clk) begin
-		if( Clks.pwrUp) begin
-			E <= 1'b0;
-			eCntr <='0;
-			rVma <= 1'b1;
-		end
-		if( Clks.enPhi2) begin
-			if( eCntr == 9)
-				E <= 1'b0;
-			else if( eCntr == 5)
-				E <= 1'b1;
-
-			if( eCntr == 9)
-				eCntr <= '0;
-			else
-				eCntr <= eCntr + 1'b1;
-		end
-		
-		if( Clks.enPhi2 & addrOe & ~Vpai & (eCntr == 3))
-			rVma <= 1'b0;
-		else if( Clks.enPhi1 & eCntr == '0)
-			rVma <= 1'b1;
-	end
-		
-	always_ff @( posedge Clks.clk) begin
-	
-		// This timing is critical to stop the clock phases at the exact point on bus/addr error.
-		// Timing should be such that current ublock completes (up to T3 or T4).
-		// But T1 for the next ublock shouldn't happen. Next T1 only after resetting ucode and ncode latches.
-		
-		if( Clks.extReset)
-			rAddrErr <= 1'b0;
-		else if( Clks.enPhi1) begin
-			if( busAddrErr & addrOe)		// Not on T1 ?!
-				rAddrErr <= 1'b1;
-			else if( ~addrOe)				// Actually async reset!
-				rAddrErr <= 1'b0;
-		end
-		
-		if( Clks.extReset)
-			iBusErr <= 1'b0;
-		else if( Clks.enPhi1) begin
-			iBusErr <= ( BerrA & ~BeI & ~Iac & !BusRetry);
-		end
-
-		if( Clks.extReset)
-			BerrA <= 1'b0;
-		else if( Clks.enPhi2) begin
-			if( ~BeI & ~Iac & addrOe)
-				BerrA <= 1'b1;
-			// else if( BeI & addrOe)			// Bad, async reset since addrOe raising edge
-			else if( BeI & busStarting)			// So replaced with this that raises one cycle earlier
-				BerrA <= 1'b0;
-		end
-
-		// Signal reset exception to sequencer.
-		// Originally cleared on 1st T2 after permstart. Must keep it until TVN latched.
-		if( Clks.extReset)
-			excRst <= 1'b1;
-		else if( enT2 & Nanod.permStart)
-			excRst <= 1'b0;
-		
-		if( Clks.extReset)
-			A0Err <= 1'b1;								// A0 Reset
-		else if( enT3)									// Keep set until new urom words are being latched
-			A0Err <= 1'b0;
-		else if( Clks.enPhi1 & enErrClk & (busAddrErr | BerrA))		// Check bus error timing
-			A0Err <= 1'b1;
-		
-		if( Clks.extReset) begin
-			iStop <= 1'b0;
-			Err6591 <= 1'b0;
-		end
-		else if( Clks.enPhi1)
-			Err6591 <= enErrClk;
-		else if( Clks.enPhi2)
-			iStop <= xVma | (Vpai & (iAddrErr | ~rBerr));
-	end
-	
-	// PSW
-	logic irdToCcr_t4;
-	always_ff @( posedge Clks.clk) begin				
-		if( Clks.pwrUp) begin
-			Tpend <= 1'b0;
-			{pswT, pswS, pswI } <= '0;
-			irdToCcr_t4 <= '0;
-		end
-		
-		else if( enT4) begin
-			irdToCcr_t4 <= Irdecod.toCcr;
-		end
-		
-		else if( enT3) begin
-		
-			// UNIQUE IF !!	
-			if( Nanod.updTpend)
-				Tpend <= pswT;
-			else if( Nanod.clrTpend)
-				Tpend <= 1'b0;
-			
-			// UNIQUE IF !!	
-			if( Nanod.ftu2Sr & !irdToCcr_t4)
-				{pswT, pswS, pswI } <= { ftu[ 15], ftu[13], ftu[10:8]};
-			else begin
-				if( Nanod.initST) begin
-					pswS <= 1'b1;
-					pswT <= 1'b0;
-				end
-				if( Nanod.inl2psw)
-					pswI <= inl;
-			end
-				
-		end
-	end
-		
-	// FTU
-	reg [4:0] ssw;
-	reg [3:0] tvnLatch;
-	logic [15:0] tvnMux;
-	reg inExcept01;
-	
-	// Seems CPU has a buglet here.
-	// Flagging group 0 exceptions from TVN might not work because some bus cycles happen before TVN is updated.
-	// But doesn't matter because a group 0 exception inside another one will halt the CPU anyway and won't save the SSW.
-		
-	always_ff @( posedge Clks.clk) begin
-	
-		// Updated at the start of the exception ucode
-		if( Nanod.updSsw & enT3) begin
-			ssw <= { ~bciWrite, inExcept01, rFC};
-		end
-	
-		// Update TVN on T1 & IR=>IRD
-		if( enT1 & Nanod.Ir2Ird) begin
-			tvnLatch <= tvn;
-			inExcept01 <= (tvn != 1);
-		end
-			
-		if( Clks.pwrUp)
-			ftu <= '0;
-		else if( enT3) begin
-			unique case( 1'b1)
-			Nanod.tvn2Ftu:				ftu <= tvnMux;
-			
-			// 0 on unused bits seem to come from ftuConst PLA previously clearing FBUS
-			Nanod.sr2Ftu:				ftu <= {pswT, 1'b0, pswS, 2'b00, pswI, 3'b000, ccr[4:0] };
-			
-			Nanod.ird2Ftu:				ftu <= Ird;
-			Nanod.ssw2Ftu:				ftu[4:0] <= ssw;						// Undoc. Other bits must be preserved from IRD saved above!
-			Nanod.pswIToFtu:			ftu <= { 12'hFFF, pswI, 1'b0};			// Interrupt level shifted
-			Nanod.const2Ftu:			ftu <= Irdecod.ftuConst;
-			Nanod.abl2Pren:				ftu <= Abl;								// From ALU or datareg. Used for SR modify
-			default:					ftu <= ftu;
-			endcase
-		end
-	end
-	
-	always_comb begin
-		if( inExcept01) begin
-			// Unique IF !!!
-			if( tvnLatch == TVN_SPURIOUS)
-				tvnMux = {9'b0, 5'd24, 2'b00};
-			else if( tvnLatch == TVN_AUTOVEC)
-				tvnMux = {9'b0, 2'b11, pswI, 2'b00};				// Set TVN PLA decoder
-			else if( tvnLatch == TVN_INTERRUPT)
-				tvnMux = {6'b0, Ird[7:0], 2'b00};					// Interrupt vector was read and transferred to IRD
-			else
-				tvnMux = {10'b0, tvnLatch, 2'b00};
-		end
-		else
-			tvnMux = { 8'h0, Irdecod.macroTvn, 2'b00};
-	end
-				
+`ifdef _VLINT_
+`include "fx68k_pkg.sv"
+`include "uaddrPla.sv"
+`include "fx68kAlu.sv"
+`endif /* _VLINT_ */
+
+import fx68k_pkg::*;
+
+module fx68k
+(
+    input clk,
+    input HALTn,                    // Used for single step only. Force high if not used
+    // input logic HALTn = 1'b1,            // Not all tools support default port values
+
+    // These two signals don't need to be registered. They are not async reset.
+    input extReset,         // External sync reset on emulated system
+    input pwrUp,            // Asserted together with reset on emulated system coldstart
+    input enPhi1, enPhi2,   // Clock enables. Next cycle is PHI1 or PHI2
+
+    output eRWn, output ASn, output LDSn, output UDSn,
+    output logic E, output VMAn,
+    output FC0, output FC1, output FC2,
+    output BGn,
+    output oRESETn, output oHALTEDn,
+    input DTACKn, input VPAn,
+    input BERRn,
+    input BRn, BGACKn,
+    input IPL0n, input IPL1n, input IPL2n,
+    input [15:0] iEdb, output [15:0] oEdb,
+    output [23:1] eab
+);
+
+    s_clks Clks;
+
+    assign Clks.clk = clk;
+    assign Clks.extReset = extReset;
+    assign Clks.pwrUp    = pwrUp;
+    assign Clks.enPhi1   = enPhi1;
+    assign Clks.enPhi2   = enPhi2;
+
+    wire wClk;
+
+    // Internal sub clocks T1-T4
+    enum int unsigned { T0 = 0, T1, T2, T3, T4} tState;
+    wire enT1 = Clks.enPhi1 & (tState == T4) & ~wClk;
+    wire enT2 = Clks.enPhi2 & (tState == T1);
+    wire enT3 = Clks.enPhi1 & (tState == T2);
+    wire enT4 = Clks.enPhi2 & ((tState == T0) | (tState == T3));
+
+    // T4 continues ticking during reset and group0 exception.
+    // We also need it to erase ucode output latched on T4.
+    always_ff @( posedge Clks.clk) begin
+
+        if (Clks.pwrUp) begin
+            tState <= T0;
+        end
+        else begin
+            case (tState)
+                T0: if (Clks.enPhi2) tState <= T4;
+                T1: if (Clks.enPhi2) tState <= T2;
+                T2: if (Clks.enPhi1) tState <= T3;
+                T3: if (Clks.enPhi2) tState <= T4;
+                T4: if (Clks.enPhi1) tState <= wClk ? T0 : T1;
+            endcase
+        end
+    end
+
+    // The following signals are synchronized with 3 couplers, phi1-phi2-phi1.
+    // Will be valid internally one cycle later if changed at the rasing edge of the clock.
+    //
+    // DTACK, BERR
+
+    // DTACK valid at S6 if changed at the rasing edge of S4 to avoid wait states.
+    // SNC (sncClkEn) is deasserted together (unless DTACK asserted too early).
+    //
+    // We synchronize some signals half clock earlier. We compensate later
+    reg rDtack, rBerr;
+    reg [2:0] rIpl, iIpl;
+    reg Vpai, BeI, Halti, BRi, BgackI, BeiDelay;
+    // reg rBR, rHALT;
+    wire BeDebounced = ~( BeI | BeiDelay);
+
+    always_ff @( posedge Clks.clk) begin
+
+        if (Clks.pwrUp) begin
+            rBerr    <= 1'b0;
+            BeI      <= 1'b0;
+        end
+        else if (Clks.enPhi2) begin
+            rDtack   <= DTACKn;
+            rBerr    <= BERRn;
+            rIpl     <= ~{ IPL2n, IPL1n, IPL0n};
+            iIpl     <= rIpl;
+
+            // Needed for cycle accuracy but only if BR or HALT are asserted on the wrong edge of the clock
+            // rBR <= BRn;
+            // rHALT <= HALTn;
+        end
+        else if (Clks.enPhi1) begin
+            Vpai     <= VPAn;
+            BeI      <= rBerr;
+            BeiDelay <= BeI;
+            BgackI   <= BGACKn;
+
+            BRi      <= BRn;
+            Halti    <= HALTn;
+            // BRi <= rBR;
+            // Halti <= rHALT;
+        end
+    end
+
+    // Instantiate micro and nano rom
+    logic  [NANO_WIDTH-1:0] nanoLatch;
+    logic  [NANO_WIDTH-1:0] nanoOutput;
+    logic  [UROM_WIDTH-1:0] microLatch;
+    logic  [UROM_WIDTH-1:0] microOutput;
+
+    logic [UADDR_WIDTH-1:0] microAddr, nma;
+    logic [NADDR_WIDTH-1:0] nanoAddr, orgAddr;
+    wire rstUrom;
+
+    // For the time being, address translation is done for nanorom only.
+    microToNanoAddr microToNanoAddr( .uAddr( nma), .orgAddr);
+
+    // Output of these modules will be updated at T2 at the latest (depending on clock division)
+
+    nanoRom nanoRom( .clk( Clks.clk), .nanoAddr, .nanoOutput);
+    uRom uRom( .clk( Clks.clk), .microAddr, .microOutput);
+
+    always_ff @( posedge Clks.clk) begin
+        // uaddr originally latched on T1, except bits 6 & 7, the conditional bits, on T2
+        // Seems we can latch whole address at either T1 or T2
+
+        // Originally it's invalid on hardware reset, and forced later when coming out of reset
+        if (Clks.pwrUp) begin
+            microAddr <= RSTP0_NMA[UADDR_WIDTH-1:0];
+            nanoAddr  <= RSTP0_NMA[NADDR_WIDTH-1:0];
+        end
+        else if (enT1) begin
+            microAddr <= nma;
+            nanoAddr  <= orgAddr;                // Register translated uaddr to naddr
+        end
+
+        if (Clks.extReset) begin
+            microLatch <= {UROM_WIDTH{1'b0}};
+            nanoLatch  <= {NANO_WIDTH{1'b0}};
+        end
+        else if (rstUrom) begin
+            // Originally reset these bits only. Not strictly needed like this.
+            // Can reset the whole register if it is important.
+            microLatch[16] <= 1'b0;
+            microLatch[15] <= 1'b0;
+            microLatch[0]  <= 1'b0;
+            nanoLatch      <= {NANO_WIDTH{1'b0}};
+        end
+        else if (enT3) begin
+            microLatch <= microOutput;
+            nanoLatch  <= nanoOutput;
+        end
+    end
+
+
+    // Decoded nanocode signals
+    s_nanod Nanod;
+    // IRD decoded control signals
+    s_irdecod Irdecod;
+
+    //
+    reg         Tpend;
+    reg         intPend; // Interrupt pending
+    reg         pswT;
+    reg         pswS;
+    reg   [2:0] pswI;
+    wire  [7:0] ccr;
+
+    wire [15:0] psw = { pswT, 1'b0, pswS, 2'b00, pswI, ccr };
+
+    reg  [15:0] ftu;
+    reg  [15:0] Irc, Ir, Ird;
+
+    wire [15:0] alue;
+    wire [15:0] Abl;
+    wire prenEmpty, au05z, dcr4, ze;
+
+    wire [UADDR_WIDTH-1:0] a1, a2, a3;
+    wire isPriv, isIllegal, isLineA, isLineF;
+
+
+    // IR & IRD forwarding
+    always_ff @( posedge Clks.clk) begin
+        if (enT1) begin
+            if (Nanod.Ir2Ird)
+                Ird <= Ir;
+            else if(microLatch[0])      // prevented by IR => IRD !
+                Ir <= Irc;
+        end
+    end
+
+    wire [3:0] tvn;
+    wire waitBusCycle, busStarting;
+    wire BusRetry = 1'b0;
+    wire busAddrErr;
+    wire bciWrite;                      // Last bus cycle was write
+    wire bgBlock, busAvail;
+    wire addrOe;
+
+    wire busIsByte = Nanod.busByte & (Irdecod.isByte | Irdecod.isMovep);
+    wire aob0;
+
+    reg iStop;                              // Internal signal for ending bus cycle
+    reg A0Err;                              // Force bus/address error ucode
+    reg excRst;                             // Signal reset exception to sequencer
+    reg BerrA;
+    reg Spuria, Avia;
+    wire Iac;
+
+    reg rAddrErr, iBusErr, Err6591;
+    wire iAddrErr = rAddrErr & addrOe;      // To simulate async reset
+    wire enErrClk;
+
+    // Reset micro/nano latch after T4 of the current ublock.
+    assign rstUrom = Clks.enPhi1 & enErrClk;
+
+    uaddrDecode uaddrDecode( .opcode( Ir), .a1, .a2, .a3, .isPriv, .isIllegal, .isLineA, .isLineF, .lineBmap());
+
+    sequencer sequencer( .Clks, .enT3, .microLatch, .Ird,
+        .A0Err, .excRst, .BerrA, .busAddrErr, .Spuria, .Avia,
+        .Tpend, .intPend, .isIllegal, .isPriv, .isLineA, .isLineF,
+        .nma, .a1, .a2, .a3, .tvn,
+        .psw, .prenEmpty, .au05z, .dcr4, .ze, .alue01( alue[1:0]), .i11( Irc[ 11]) );
+
+    excUnit excUnit( .Clks, .Nanod, .Irdecod, .enT1, .enT2, .enT3, .enT4,
+        .Ird, .ftu, .iEdb, .pswS,
+        .prenEmpty, .au05z, .dcr4, .ze, .AblOut( Abl), .eab, .aob0, .Irc, .oEdb,
+        .alue, .ccr);
+
+    nDecoder3 nDecoder( .Clks, .Nanod, .Irdecod, .enT2, .enT4, .microLatch, .nanoLatch);
+
+    irdDecode irdDecode( .ird( Ird), .Irdecod);
+
+    busControl busControl( .Clks, .enT1, .enT4, .permStart( Nanod.permStart), .permStop( Nanod.waitBusFinish), .iStop,
+        .aob0, .isWrite( Nanod.isWrite), .isRmc( Nanod.isRmc), .isByte( busIsByte), .busAvail,
+        .bciWrite, .addrOe, .bgBlock, .waitBusCycle, .busStarting, .busAddrErr,
+        .rDtack, .BeDebounced, .Vpai,
+        .ASn, .LDSn, .UDSn, .eRWn);
+
+    busArbiter busArbiter( .Clks, .BRi, .BgackI, .Halti, .bgBlock, .busAvail, .BGn);
+
+
+    // Output reset & halt control
+    wire [1:0] uFc = microLatch[ 16:15];
+    logic oReset, oHalted;
+    assign oRESETn = !oReset;
+    assign oHALTEDn = !oHalted;
+
+    // FC without permStart is special, either reset or halt
+    always_ff @( posedge Clks.clk) begin
+
+        if (Clks.pwrUp) begin
+            oReset  <= 1'b0;
+            oHalted <= 1'b0;
+        end
+        else if (enT1) begin
+            oReset  <= (uFc == 2'b01) ? ~Nanod.permStart : 1'b0;
+            oHalted <= (uFc == 2'b10) ? ~Nanod.permStart : 1'b0;
+        end
+    end
+
+    logic [2:0] rFC;
+    assign { FC2, FC1, FC0} = rFC;                  // ~rFC;
+    assign Iac = {rFC == 3'b111};                   // & Control output enable !!
+
+    always_ff @( posedge Clks.clk) begin
+
+        if (Clks.extReset) begin
+            rFC <= 3'b000;
+        end
+        else if (enT1 & Nanod.permStart) begin      // S0 phase of bus cycle
+            rFC[2] <= pswS;
+            // If FC is type 'n' (0) at ucode, access type depends on PC relative mode
+            // We don't care about RZ in this case. Those uinstructions with RZ don't start a bus cycle.
+            rFC[1] <= microLatch[ 16] | ( ~microLatch[ 15] &  Irdecod.isPcRel);
+            rFC[0] <= microLatch[ 15] | ( ~microLatch[ 16] & ~Irdecod.isPcRel);
+        end
+    end
+
+
+    // IPL interface
+    reg [2:0] inl;                          // Int level latch
+    reg updIll;
+    reg prevNmi;
+
+    wire nmi = (iIpl == 3'b111);
+    wire iplStable = (iIpl == rIpl);
+    wire iplComp = iIpl > pswI;
+
+    always_ff @( posedge Clks.clk) begin
+
+        if (Clks.extReset) begin
+            intPend <= 1'b0;
+            prevNmi <= 1'b0;
+        end
+        else begin
+            if (Clks.enPhi2) begin
+                prevNmi <= nmi;
+            end
+
+            // Originally async RS-Latch on PHI2, followed by a transparent latch on T2
+            // Tricky because they might change simultaneously
+            // Syncronous on PHI2 is equivalent as long as the output is read on T3!
+
+            // Set on stable & NMI edge or compare
+            // Clear on: NMI Iack or (stable & !NMI & !Compare)
+
+            if (Clks.enPhi2) begin
+                if (iplStable & ((nmi & ~prevNmi) | iplComp)) begin
+                    intPend <= 1'b1;
+                end
+                else if (((inl == 3'b111) & Iac) | (iplStable & !nmi & !iplComp)) begin
+                    intPend <= 1'b0;
+                end
+            end
+        end
+
+        if (Clks.extReset) begin
+            inl    <= '1;
+            updIll <= 1'b0;
+        end
+        else if (enT4)
+            updIll <= microLatch[0];        // Update on any IRC->IR
+        else if (enT1 & updIll)
+            inl <= iIpl;                    // Timing is correct.
+
+        // Spurious interrupt, BERR on Interrupt Ack.
+        // Autovector interrupt. VPA on IACK.
+        // Timing is tight. Spuria is deasserted just after exception exception is recorded.
+        if (enT4) begin
+            Spuria <= ~BeiDelay & Iac;
+            Avia   <= ~Vpai & Iac;
+        end
+
+    end
+
+    assign enErrClk = iAddrErr | iBusErr;
+    assign wClk = waitBusCycle | ~BeI | iAddrErr | Err6591;
+
+    // E clock and counter, VMA
+    reg [3:0] eCntr;
+    reg rVma;
+
+    assign VMAn = rVma;
+
+    // Internal stop just one cycle before E falling edge
+    wire xVma = ~rVma & (eCntr == 8);
+
+    always_ff @( posedge Clks.clk) begin
+
+        if (Clks.pwrUp) begin
+            E     <= 1'b0;
+            eCntr <= 4'd0;
+            rVma  <= 1'b1;
+        end
+        if (Clks.enPhi2) begin
+            if (eCntr == 4'd9)
+                E <= 1'b0;
+            else if (eCntr == 4'd5)
+                E <= 1'b1;
+
+            if (eCntr == 4'd9)
+                eCntr <= 4'd0;
+            else
+                eCntr <= eCntr + 4'd1;
+        end
+
+        if (Clks.enPhi2 & addrOe & ~Vpai & (eCntr == 4'd3))
+            rVma <= 1'b0;
+        else if (Clks.enPhi1 & eCntr == 4'd0)
+            rVma <= 1'b1;
+    end
+
+    always_ff @( posedge Clks.clk) begin
+
+        // This timing is critical to stop the clock phases at the exact point on bus/addr error.
+        // Timing should be such that current ublock completes (up to T3 or T4).
+        // But T1 for the next ublock shouldn't happen. Next T1 only after resetting ucode and ncode latches.
+
+        if (Clks.extReset)
+            rAddrErr <= 1'b0;
+        else if (Clks.enPhi1) begin
+            if (busAddrErr & addrOe)        // Not on T1 ?!
+                rAddrErr <= 1'b1;
+            else if (~addrOe)               // Actually async reset!
+                rAddrErr <= 1'b0;
+        end
+
+        if (Clks.extReset)
+            iBusErr <= 1'b0;
+        else if (Clks.enPhi1) begin
+            iBusErr <= ( BerrA & ~BeI & ~Iac & !BusRetry);
+        end
+
+        if (Clks.extReset)
+            BerrA <= 1'b0;
+        else if (Clks.enPhi2) begin
+            if (~BeI & ~Iac & addrOe)
+                BerrA <= 1'b1;
+            // else if (BeI & addrOe)           // Bad, async reset since addrOe raising edge
+            else if (BeI & busStarting)         // So replaced with this that raises one cycle earlier
+                BerrA <= 1'b0;
+        end
+
+        // Signal reset exception to sequencer.
+        // Originally cleared on 1st T2 after permstart. Must keep it until TVN latched.
+        if (Clks.extReset)
+            excRst <= 1'b1;
+        else if (enT2 & Nanod.permStart)
+            excRst <= 1'b0;
+
+        if (Clks.extReset)
+            A0Err <= 1'b1;                              // A0 Reset
+        else if (enT3)                                  // Keep set until new urom words are being latched
+            A0Err <= 1'b0;
+        else if (Clks.enPhi1 & enErrClk & (busAddrErr | BerrA))     // Check bus error timing
+            A0Err <= 1'b1;
+
+        if (Clks.extReset) begin
+            iStop <= 1'b0;
+            Err6591 <= 1'b0;
+        end
+        else if (Clks.enPhi1)
+            Err6591 <= enErrClk;
+        else if (Clks.enPhi2)
+            iStop <= xVma | (Vpai & (iAddrErr | ~rBerr));
+    end
+
+    // PSW
+    logic irdToCcr_t4;
+    always_ff @( posedge Clks.clk) begin
+
+        if (Clks.pwrUp) begin
+            Tpend <= 1'b0;
+            { pswT, pswS, pswI } <= 5'b0_0_000;
+            irdToCcr_t4 <= '0;
+        end
+
+        else if (enT4) begin
+            irdToCcr_t4 <= Irdecod.toCcr;
+        end
+
+        else if (enT3) begin
+
+            // UNIQUE IF !!
+            if (Nanod.updTpend)
+                Tpend <= pswT;
+            else if (Nanod.clrTpend)
+                Tpend <= 1'b0;
+
+            // UNIQUE IF !!
+            if (Nanod.ftu2Sr & !irdToCcr_t4) begin
+                { pswT, pswS, pswI } <= { ftu[15], ftu[13], ftu[10:8]};
+            end
+            else begin
+                if (Nanod.initST) begin
+                    pswS <= 1'b1;
+                    pswT <= 1'b0;
+                end
+                if (Nanod.inl2psw) begin
+                    pswI <= inl;
+                end
+            end
+        end
+    end
+
+    // FTU
+    reg    [4:0] ssw;
+    reg    [3:0] tvnLatch;
+    logic [15:0] tvnMux;
+    reg          inExcept01;
+
+    // Seems CPU has a buglet here.
+    // Flagging group 0 exceptions from TVN might not work because some bus cycles happen before TVN is updated.
+    // But doesn't matter because a group 0 exception inside another one will halt the CPU anyway and won't save the SSW.
+
+    always_ff @( posedge Clks.clk) begin
+
+        // Updated at the start of the exception ucode
+        if (Nanod.updSsw & enT3) begin
+            ssw <= { ~bciWrite, inExcept01, rFC};
+        end
+
+        // Update TVN on T1 & IR=>IRD
+        if (enT1 & Nanod.Ir2Ird) begin
+            tvnLatch <= tvn;
+            inExcept01 <= (tvn != 4'h1);
+        end
+
+        if (Clks.pwrUp) begin
+            ftu <= 16'h0000;
+        end
+        else if (enT3) begin
+            unique case (1'b1)
+            Nanod.tvn2Ftu:              ftu <= tvnMux;
+
+            // 0 on unused bits seem to come from ftuConst PLA previously clearing FBUS
+            Nanod.sr2Ftu:               ftu <= {pswT, 1'b0, pswS, 2'b00, pswI, 3'b000, ccr[4:0] };
+
+            Nanod.ird2Ftu:              ftu <= Ird;
+            Nanod.ssw2Ftu:              ftu[4:0] <= ssw;                        // Undoc. Other bits must be preserved from IRD saved above!
+            Nanod.pswIToFtu:            ftu <= { 12'hFFF, pswI, 1'b0};          // Interrupt level shifted
+            Nanod.const2Ftu:            ftu <= Irdecod.ftuConst;
+            Nanod.abl2Pren:             ftu <= Abl;                             // From ALU or datareg. Used for SR modify
+            default:                    ftu <= ftu;
+            endcase
+        end
+    end
+
+    always_comb begin
+
+        if (inExcept01) begin
+            // Unique IF !!!
+            if (tvnLatch == TVN_SPURIOUS)
+                tvnMux = { 9'b0, 5'd24, 2'b0 };
+            else if (tvnLatch == TVN_AUTOVEC)
+                tvnMux = { 9'b0, 2'b11, pswI, 2'b0 };                // Set TVN PLA decoder
+            else if (tvnLatch == TVN_INTERRUPT)
+                tvnMux = { 6'b0, Ird[7:0], 2'b0 };                   // Interrupt vector was read and transferred to IRD
+            else
+                tvnMux = { 10'b0, tvnLatch, 2'b0 };
+        end
+        else begin
+            tvnMux = { 8'h0, Irdecod.macroTvn, 2'b0 };
+        end
+    end
+
 endmodule
 
 // Nanorom (plus) decoder for die nanocode
-module nDecoder3( input s_clks Clks, input s_irdecod Irdecod, output s_nanod Nanod,
-	input enT2, enT4,
-	input [UROM_WIDTH-1:0] microLatch,
-	input [NANO_WIDTH-1:0] nanoLatch);
-
-localparam NANO_IR2IRD = 67;
-localparam NANO_TOIRC = 66;
-localparam NANO_ALU_COL = 63;		// ALU operator column order is 63-64-65 !
-localparam NANO_ALU_FI = 61;	// ALU finish-init 62-61
-localparam NANO_TODBIN = 60;
-localparam NANO_ALUE = 57;			// 57-59 shared with DCR control
-localparam NANO_DCR = 57;			// 57-59 shared with ALUE control
-localparam NANO_DOBCTRL_1 = 56;		// Input to control and permwrite
-localparam NANO_LOWBYTE = 55;		// Used by MOVEP
-localparam NANO_HIGHBYTE = 54;
-localparam NANO_DOBCTRL_0 = 53;		// Input to control and permwrite
-localparam NANO_ALU_DCTRL = 51;	// 52-51 databus input mux control
-localparam NANO_ALU_ACTRL = 50;	// addrbus input mux control
-localparam NANO_DBD2ALUB = 49;
-localparam NANO_ABD2ALUB = 48;
-localparam NANO_DBIN2DBD = 47;
-localparam NANO_DBIN2ABD = 46;
-localparam NANO_ALU2ABD = 45;
-localparam NANO_ALU2DBD = 44;
-localparam NANO_RZ = 43;
-localparam NANO_BUSBYTE = 42;		// If *both* this set and instruction is byte sized, then bus cycle is byte sized.
-localparam NANO_PCLABL = 41;
-localparam NANO_RXL_DBL = 40;		// Switches RXL/RYL on DBL/ABL buses
-localparam NANO_PCLDBL = 39;
-localparam NANO_ABDHRECHARGE = 38;
-localparam NANO_REG2ABL = 37;		// register to ABL
-localparam NANO_ABL2REG = 36;		// ABL to register
-localparam NANO_ABLABD = 35;
-localparam NANO_DBLDBD = 34;
-localparam NANO_DBL2REG = 33;		// DBL to register
-localparam NANO_REG2DBL = 32;		// register to DBL
-localparam NANO_ATLCTRL = 29;		// 31-29
-localparam NANO_FTUCONTROL = 25;
-localparam NANO_SSP = 24;
-localparam NANO_RXH_DBH = 22;		// Switches RXH/RYH on DBH/ABH buses
-localparam NANO_AUOUT = 20;			// 21-20
-localparam NANO_AUCLKEN = 19;
-localparam NANO_AUCTRL = 16;		// 18-16
-localparam NANO_DBLDBH = 15;
-localparam NANO_ABLABH = 14;
-localparam NANO_EXT_ABH = 13;
-localparam NANO_EXT_DBH = 12;
-localparam NANO_ATHCTRL = 9;		// 11-9
-localparam NANO_REG2ABH = 8;		// register to ABH
-localparam NANO_ABH2REG = 7;		// ABH to register
-localparam NANO_REG2DBH = 6;		// register to DBH
-localparam NANO_DBH2REG = 5;		// DBH to register
-localparam NANO_AOBCTRL = 3;		// 4-3
-localparam NANO_PCH = 0;			// 1-0 PchDbh PchAbh
-localparam NANO_NO_SP_ALGN = 0;		// Same bits as above when both set
-
-localparam NANO_FTU_UPDTPEND = 1;		// Also loads FTU constant according to IRD !
-localparam NANO_FTU_INIT_ST = 15;		// Set S, clear T (but not TPEND)
-localparam NANO_FTU_CLRTPEND = 14;
-localparam NANO_FTU_TVN = 13;
-localparam NANO_FTU_ABL2PREN = 12;		// ABL => FTU & ABL => PREN. Both transfers enabled, but only one will be used depending on uroutine.
-localparam NANO_FTU_SSW = 11;
-localparam NANO_FTU_RSTPREN = 10;
-localparam NANO_FTU_IRD = 9;
-localparam NANO_FTU_2ABL = 8;
-localparam NANO_FTU_RDSR = 7;
-localparam NANO_FTU_INL = 6;
-localparam NANO_FTU_PSWI = 5;		// Read Int Mask into FTU
-localparam NANO_FTU_DBL = 4;
-localparam NANO_FTU_2SR = 2;
-localparam NANO_FTU_CONST = 1;
-
-	reg [3:0] ftuCtrl;	
-	
-	logic [2:0] athCtrl, atlCtrl;
-	assign athCtrl = nanoLatch[ NANO_ATHCTRL+2: NANO_ATHCTRL];
-	assign atlCtrl = nanoLatch[ NANO_ATLCTRL+2: NANO_ATLCTRL];
-	wire [1:0] aobCtrl = nanoLatch[ NANO_AOBCTRL+1:NANO_AOBCTRL];
-	wire [1:0] dobCtrl = {nanoLatch[ NANO_DOBCTRL_1], nanoLatch[NANO_DOBCTRL_0]};
-	
-	always_ff @( posedge Clks.clk) begin
-		if( enT4) begin
-			// Reverse order!
-			ftuCtrl <= { nanoLatch[ NANO_FTUCONTROL+0], nanoLatch[ NANO_FTUCONTROL+1], nanoLatch[ NANO_FTUCONTROL+2], nanoLatch[ NANO_FTUCONTROL+3]} ;
-				
-			Nanod.auClkEn <= !nanoLatch[ NANO_AUCLKEN];
-			Nanod.auCntrl <= nanoLatch[ NANO_AUCTRL+2 : NANO_AUCTRL+0];
-			Nanod.noSpAlign <= (nanoLatch[ NANO_NO_SP_ALGN + 1:NANO_NO_SP_ALGN] == 2'b11);			
-			Nanod.extDbh <= nanoLatch[ NANO_EXT_DBH];
-			Nanod.extAbh <= nanoLatch[ NANO_EXT_ABH];
-			Nanod.todbin <= nanoLatch[ NANO_TODBIN];
-			Nanod.toIrc <=  nanoLatch[ NANO_TOIRC];
-			
-			// ablAbd is disabled on byte transfers (adbhCharge plus irdIsByte). Not sure the combination makes much sense.
-			// It happens in a few cases but I don't see anything enabled on abL (or abH) section anyway.
-			
-			Nanod.ablAbd <= nanoLatch[ NANO_ABLABD];
-			Nanod.ablAbh <= nanoLatch[ NANO_ABLABH];
-			Nanod.dblDbd <= nanoLatch[ NANO_DBLDBD];
-			Nanod.dblDbh <= nanoLatch[ NANO_DBLDBH];
-			
-			Nanod.dbl2Atl <= (atlCtrl == 3'b010);
-			Nanod.atl2Dbl <= (atlCtrl == 3'b011);
-			Nanod.abl2Atl <= (atlCtrl == 3'b100);
-			Nanod.atl2Abl <= (atlCtrl == 3'b101);
-
-			Nanod.aob2Ab <= (athCtrl == 3'b101);		// Used on BSER1 only
-			
-			Nanod.abh2Ath <= (athCtrl == 3'b001) | (athCtrl == 3'b101);
-			Nanod.dbh2Ath <= (athCtrl == 3'b100);
-			Nanod.ath2Dbh <= (athCtrl == 3'b110);
-			Nanod.ath2Abh <= (athCtrl == 3'b011);			
-
-			Nanod.alu2Dbd <= nanoLatch[ NANO_ALU2DBD];
-			Nanod.alu2Abd <= nanoLatch[ NANO_ALU2ABD];
-			
-			Nanod.abd2Dcr <= (nanoLatch[ NANO_DCR+1:NANO_DCR] == 2'b11);
-			Nanod.dcr2Dbd <= (nanoLatch[ NANO_DCR+2:NANO_DCR+1] == 2'b11);
-			Nanod.dbd2Alue <= (nanoLatch[ NANO_ALUE+2:NANO_ALUE+1] == 2'b10);
-			Nanod.alue2Dbd <= (nanoLatch[ NANO_ALUE+1:NANO_ALUE] == 2'b01);
-
-			Nanod.dbd2Alub <= nanoLatch[ NANO_DBD2ALUB];
-			Nanod.abd2Alub <= nanoLatch[ NANO_ABD2ALUB];			
-			
-			// Originally not latched. We better should because we transfer one cycle later, T3 instead of T1.
-			Nanod.dobCtrl <= dobCtrl;
-			// Nanod.adb2Dob <= (dobCtrl == 2'b10);			Nanod.dbd2Dob <= (dobCtrl == 2'b01);			Nanod.alu2Dob <= (dobCtrl == 2'b11);
-							
-		end
-	end
-	
-	// Update SSW at the start of Bus/Addr error ucode
-	assign Nanod.updSsw = Nanod.aob2Ab;
-
-	assign Nanod.updTpend = (ftuCtrl == NANO_FTU_UPDTPEND);
-	assign Nanod.clrTpend = (ftuCtrl == NANO_FTU_CLRTPEND);
-	assign Nanod.tvn2Ftu = (ftuCtrl == NANO_FTU_TVN);
-	assign Nanod.const2Ftu = (ftuCtrl == NANO_FTU_CONST);
-	assign Nanod.ftu2Dbl = (ftuCtrl == NANO_FTU_DBL) | ( ftuCtrl == NANO_FTU_INL);	
-	assign Nanod.ftu2Abl = (ftuCtrl == NANO_FTU_2ABL);	
-	assign Nanod.inl2psw = (ftuCtrl == NANO_FTU_INL);
-	assign Nanod.pswIToFtu = (ftuCtrl == NANO_FTU_PSWI);
-	assign Nanod.ftu2Sr = (ftuCtrl == NANO_FTU_2SR);
-	assign Nanod.sr2Ftu = (ftuCtrl == NANO_FTU_RDSR);
-	assign Nanod.ird2Ftu = (ftuCtrl == NANO_FTU_IRD);		// Used on bus/addr error
-	assign Nanod.ssw2Ftu = (ftuCtrl == NANO_FTU_SSW);
-	assign Nanod.initST = (ftuCtrl == NANO_FTU_INL) | (ftuCtrl == NANO_FTU_CLRTPEND) | (ftuCtrl == NANO_FTU_INIT_ST);
-	assign Nanod.abl2Pren = (ftuCtrl == NANO_FTU_ABL2PREN);
-	assign Nanod.updPren = (ftuCtrl == NANO_FTU_RSTPREN);
-	
-	assign Nanod.Ir2Ird = nanoLatch[ NANO_IR2IRD];
-
-	// ALU control better latched later after combining with IRD decoding
-		
-	assign Nanod.aluDctrl = nanoLatch[ NANO_ALU_DCTRL+1 : NANO_ALU_DCTRL];
-	assign Nanod.aluActrl = nanoLatch[ NANO_ALU_ACTRL];
-	assign Nanod.aluColumn = { nanoLatch[ NANO_ALU_COL], nanoLatch[ NANO_ALU_COL+1], nanoLatch[ NANO_ALU_COL+2]};
-	wire [1:0] aluFinInit = nanoLatch[ NANO_ALU_FI+1:NANO_ALU_FI];
-	assign Nanod.aluFinish = (aluFinInit == 2'b10);
-	assign Nanod.aluInit = (aluFinInit == 2'b01);
-
-	// FTU 2 CCR encoded as both ALU Init and ALU Finish set.
-	// In theory this encoding allows writes to CCR without writing to SR
-	// But FTU 2 CCR and to SR are both set together at nanorom.
-	assign Nanod.ftu2Ccr = ( aluFinInit == 2'b11);
-
-	assign Nanod.abdIsByte = nanoLatch[ NANO_ABDHRECHARGE];
-	
-	// Not being latched on T4 creates non unique case warning!
-	assign Nanod.au2Db = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b01);
-	assign Nanod.au2Ab = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b10);
-	assign Nanod.au2Pc = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b11);
-	
-	assign Nanod.db2Aob = (aobCtrl == 2'b10);
-	assign Nanod.ab2Aob = (aobCtrl == 2'b01);
-	assign Nanod.au2Aob = (aobCtrl == 2'b11);
-	
-	assign Nanod.dbin2Abd = nanoLatch[ NANO_DBIN2ABD];
-	assign Nanod.dbin2Dbd = nanoLatch[ NANO_DBIN2DBD];
-	
-	assign Nanod.permStart = (| aobCtrl);
-	assign Nanod.isWrite  = ( | dobCtrl);
-	assign Nanod.waitBusFinish = nanoLatch[ NANO_TOIRC] | nanoLatch[ NANO_TODBIN] | Nanod.isWrite;
-	assign Nanod.busByte = nanoLatch[ NANO_BUSBYTE];
-	
-	assign Nanod.noLowByte = nanoLatch[ NANO_LOWBYTE];
-	assign Nanod.noHighByte = nanoLatch[ NANO_HIGHBYTE];	
-			
-	// Not registered. Register at T4 after combining
-	// Might be better to remove all those and combine here instead of at execution unit !!
-	assign Nanod.abl2reg = nanoLatch[ NANO_ABL2REG];
-	assign Nanod.abh2reg = nanoLatch[ NANO_ABH2REG];
-	assign Nanod.dbl2reg = nanoLatch[ NANO_DBL2REG];
-	assign Nanod.dbh2reg = nanoLatch[ NANO_DBH2REG];
-	assign Nanod.reg2dbl = nanoLatch[ NANO_REG2DBL];
-	assign Nanod.reg2dbh = nanoLatch[ NANO_REG2DBH];
-	assign Nanod.reg2abl = nanoLatch[ NANO_REG2ABL];
-	assign Nanod.reg2abh = nanoLatch[ NANO_REG2ABH];
-	
-	assign Nanod.ssp = nanoLatch[ NANO_SSP];
-	
-	assign Nanod.rz = nanoLatch[ NANO_RZ];
-	
-	// Actually DTL can't happen on PC relative mode. See IR decoder.
-	
-	wire dtldbd = 1'b0;
-	wire dthdbh = 1'b0;
-	wire dtlabd = 1'b0;
-	wire dthabh = 1'b0;
-	
-	wire dblSpecial = Nanod.pcldbl | dtldbd;
-	wire dbhSpecial = Nanod.pchdbh | dthdbh;
-	wire ablSpecial = Nanod.pclabl | dtlabd;
-	wire abhSpecial = Nanod.pchabh | dthabh;
-			
-	//
-	// Combine with IRD decoding
-	// Careful that IRD is updated only on T1! All output depending on IRD must be latched on T4!
-	//
-	
-	// PC used instead of RY on PC relative instuctions
-	
-	assign Nanod.rxlDbl = nanoLatch[ NANO_RXL_DBL];
-	wire isPcRel = Irdecod.isPcRel & !Nanod.rz;
-	wire pcRelDbl = isPcRel & !nanoLatch[ NANO_RXL_DBL];
-	wire pcRelDbh = isPcRel & !nanoLatch[ NANO_RXH_DBH];
-	wire pcRelAbl = isPcRel & nanoLatch[ NANO_RXL_DBL];
-	wire pcRelAbh = isPcRel & nanoLatch[ NANO_RXH_DBH];
-	
-	assign Nanod.pcldbl = nanoLatch[ NANO_PCLDBL] | pcRelDbl;
-	assign Nanod.pchdbh = (nanoLatch[ NANO_PCH+1:NANO_PCH] == 2'b01) | pcRelDbh;
-	
-	assign Nanod.pclabl = nanoLatch[ NANO_PCLABL] | pcRelAbl;
-	assign Nanod.pchabh = (nanoLatch[ NANO_PCH+1:NANO_PCH] == 2'b10) | pcRelAbh;
-
-	// Might be better not to register these signals to allow latching RX/RY mux earlier!
-	// But then must latch Irdecod.isPcRel on T3!
-
-	always_ff @( posedge Clks.clk) begin
-		if( enT4) begin
-			Nanod.rxl2db <= Nanod.reg2dbl & !dblSpecial & nanoLatch[ NANO_RXL_DBL];
-			Nanod.rxl2ab <= Nanod.reg2abl & !ablSpecial & !nanoLatch[ NANO_RXL_DBL];
-			
-			Nanod.dbl2rxl <= Nanod.dbl2reg & !dblSpecial & nanoLatch[ NANO_RXL_DBL];	
-			Nanod.abl2rxl <= Nanod.abl2reg & !ablSpecial & !nanoLatch[ NANO_RXL_DBL];	
-
-			Nanod.rxh2dbh <= Nanod.reg2dbh & !dbhSpecial & nanoLatch[ NANO_RXH_DBH];			
-			Nanod.rxh2abh <= Nanod.reg2abh & !abhSpecial & !nanoLatch[ NANO_RXH_DBH];			
-				
-			Nanod.dbh2rxh <= Nanod.dbh2reg & !dbhSpecial & nanoLatch[ NANO_RXH_DBH];
-			Nanod.abh2rxh <= Nanod.abh2reg & !abhSpecial & !nanoLatch[ NANO_RXH_DBH];	
-
-			Nanod.dbh2ryh <= Nanod.dbh2reg & !dbhSpecial & !nanoLatch[ NANO_RXH_DBH];
-			Nanod.abh2ryh <= Nanod.abh2reg & !abhSpecial & nanoLatch[ NANO_RXH_DBH];	
-
-			Nanod.dbl2ryl <= Nanod.dbl2reg & !dblSpecial & !nanoLatch[ NANO_RXL_DBL];	
-			Nanod.abl2ryl <= Nanod.abl2reg & !ablSpecial & nanoLatch[ NANO_RXL_DBL];	
-
-			Nanod.ryl2db <= Nanod.reg2dbl & !dblSpecial & !nanoLatch[ NANO_RXL_DBL];
-			Nanod.ryl2ab <= Nanod.reg2abl & !ablSpecial & nanoLatch[ NANO_RXL_DBL];
-
-			Nanod.ryh2dbh <= Nanod.reg2dbh & !dbhSpecial & !nanoLatch[ NANO_RXH_DBH];			
-			Nanod.ryh2abh <= Nanod.reg2abh & !abhSpecial & nanoLatch[ NANO_RXH_DBH];					
-		end
-		
-		// Originally isTas only delayed on T2 (and seems only a late mask rev fix)
-		// Better latch the combination on T4
-		if( enT4)
-			Nanod.isRmc <= Irdecod.isTas & nanoLatch[ NANO_BUSBYTE];
-	end
-			
-	
+module nDecoder3
+(
+    input                   s_clks Clks,
+    input                   enT2,
+    input                   enT4,
+    input  [UROM_WIDTH-1:0] microLatch,
+    input  [NANO_WIDTH-1:0] nanoLatch,
+    input                   s_irdecod Irdecod,
+    output                  s_nanod Nanod
+);
+
+localparam
+    NANO_IR2IRD       = 67,
+    NANO_TOIRC        = 66,
+    NANO_ALU_COL      = 63, // ALU operator column order is 63-64-65 !
+    NANO_ALU_FI       = 61, // ALU finish-init 62-61
+    NANO_TODBIN       = 60,
+    NANO_ALUE         = 57, // 57-59 shared with DCR control
+    NANO_DCR          = 57, // 57-59 shared with ALUE control
+    NANO_DOBCTRL_1    = 56, // Input to control and permwrite
+    NANO_LOWBYTE      = 55, // Used by MOVEP
+    NANO_HIGHBYTE     = 54,
+    NANO_DOBCTRL_0    = 53, // Input to control and permwrite
+    NANO_ALU_DCTRL    = 51, // 52-51 databus input mux control
+    NANO_ALU_ACTRL    = 50, // addrbus input mux control
+    NANO_DBD2ALUB     = 49,
+    NANO_ABD2ALUB     = 48,
+    NANO_DBIN2DBD     = 47,
+    NANO_DBIN2ABD     = 46,
+    NANO_ALU2ABD      = 45,
+    NANO_ALU2DBD      = 44,
+    NANO_RZ           = 43,
+    NANO_BUSBYTE      = 42, // If *both* this set and instruction is byte sized, then bus cycle is byte sized.
+    NANO_PCLABL       = 41,
+    NANO_RXL_DBL      = 40, // Switches RXL/RYL on DBL/ABL buses
+    NANO_PCLDBL       = 39,
+    NANO_ABDHRECHARGE = 38,
+    NANO_REG2ABL      = 37, // register to ABL
+    NANO_ABL2REG      = 36, // ABL to register
+    NANO_ABLABD       = 35,
+    NANO_DBLDBD       = 34,
+    NANO_DBL2REG      = 33, // DBL to register
+    NANO_REG2DBL      = 32, // register to DBL
+    NANO_ATLCTRL      = 29, // 31-29
+    NANO_FTUCONTROL   = 25,
+    NANO_SSP          = 24,
+    NANO_RXH_DBH      = 22, // Switches RXH/RYH on DBH/ABH buses
+    NANO_AUOUT        = 20, // 21-20
+    NANO_AUCLKEN      = 19,
+    NANO_AUCTRL       = 16, // 18-16
+    NANO_DBLDBH       = 15,
+    NANO_ABLABH       = 14,
+    NANO_EXT_ABH      = 13,
+    NANO_EXT_DBH      = 12,
+    NANO_ATHCTRL      = 9,  // 11-9
+    NANO_REG2ABH      = 8,  // register to ABH
+    NANO_ABH2REG      = 7,  // ABH to register
+    NANO_REG2DBH      = 6,  // register to DBH
+    NANO_DBH2REG      = 5,  // DBH to register
+    NANO_AOBCTRL      = 3,  // 4-3
+    NANO_PCH          = 0,  // 1-0 PchDbh PchAbh
+    NANO_NO_SP_ALGN   = 0;  // Same bits as above when both set
+
+// Reverse order!
+localparam [3:0]
+    NANO_FTU_UPDTPEND = 4'b1000, // Also loads FTU constant according to IRD !
+    NANO_FTU_INIT_ST  = 4'b1111, // Set S, clear T (but not TPEND)
+    NANO_FTU_CLRTPEND = 4'b0111,
+    NANO_FTU_TVN      = 4'b1011,
+    NANO_FTU_ABL2PREN = 4'b0011, // ABL => FTU & ABL => PREN. Both transfers enabled, but only one will be used depending on uroutine.
+    NANO_FTU_SSW      = 4'b1101,
+    NANO_FTU_RSTPREN  = 4'b0101,
+    NANO_FTU_IRD      = 4'b1001,
+    NANO_FTU_2ABL     = 4'b0001,
+    NANO_FTU_RDSR     = 4'b1110,
+    NANO_FTU_INL      = 4'b0110,
+    NANO_FTU_PSWI     = 4'b1010, // Read Int Mask into FTU
+    NANO_FTU_DBL      = 4'b0010,
+    NANO_FTU_2SR      = 4'b0100,
+    NANO_FTU_CONST    = 4'b1000;
+
+    reg [3:0] ftuCtrl;
+
+    wire [2:0] athCtrl = nanoLatch[NANO_ATHCTRL +: 3];
+    wire [2:0] atlCtrl = nanoLatch[NANO_ATLCTRL +: 3];
+    wire [1:0] aobCtrl = nanoLatch[NANO_AOBCTRL +: 2];
+    wire [1:0] dobCtrl = { nanoLatch[ NANO_DOBCTRL_1], nanoLatch[NANO_DOBCTRL_0] };
+
+    always_ff @( posedge Clks.clk) begin
+
+        if (enT4) begin
+
+            ftuCtrl         <= nanoLatch[NANO_FTUCONTROL +: 4];
+
+            Nanod.auClkEn   <= ~nanoLatch[NANO_AUCLKEN];
+            Nanod.auCntrl   <= nanoLatch[NANO_AUCTRL +: 3];
+            Nanod.noSpAlign <= &nanoLatch[NANO_NO_SP_ALGN +: 2];
+            Nanod.extDbh    <= nanoLatch[NANO_EXT_DBH];
+            Nanod.extAbh    <= nanoLatch[NANO_EXT_ABH];
+            Nanod.todbin    <= nanoLatch[NANO_TODBIN];
+            Nanod.toIrc     <= nanoLatch[NANO_TOIRC];
+
+            // ablAbd is disabled on byte transfers (adbhCharge plus irdIsByte). Not sure the combination makes much sense.
+            // It happens in a few cases but I don't see anything enabled on abL (or abH) section anyway.
+
+            Nanod.ablAbd  <= nanoLatch[NANO_ABLABD];
+            Nanod.ablAbh  <= nanoLatch[NANO_ABLABH];
+            Nanod.dblDbd  <= nanoLatch[NANO_DBLDBD];
+            Nanod.dblDbh  <= nanoLatch[NANO_DBLDBH];
+
+            Nanod.dbl2Atl <= (atlCtrl[2:0] == 3'b010) ? 1'b1 : 1'b0;
+            Nanod.atl2Dbl <= (atlCtrl[2:0] == 3'b011) ? 1'b1 : 1'b0;
+            Nanod.abl2Atl <= (atlCtrl[2:0] == 3'b100) ? 1'b1 : 1'b0;
+            Nanod.atl2Abl <= (atlCtrl[2:0] == 3'b101) ? 1'b1 : 1'b0;
+
+            Nanod.aob2Ab  <= (athCtrl[2:0] == 3'b101) ? 1'b1 : 1'b0; // Used on BSER1 only
+
+            Nanod.abh2Ath <= (athCtrl[1:0] == 2'b01 ) ? 1'b1 : 1'b0;
+            Nanod.dbh2Ath <= (athCtrl[2:0] == 3'b100) ? 1'b1 : 1'b0;
+            Nanod.ath2Dbh <= (athCtrl[2:0] == 3'b110) ? 1'b1 : 1'b0;
+            Nanod.ath2Abh <= (athCtrl[2:0] == 3'b011) ? 1'b1 : 1'b0;
+
+            Nanod.alu2Dbd <= nanoLatch[NANO_ALU2DBD];
+            Nanod.alu2Abd <= nanoLatch[NANO_ALU2ABD];
+
+            Nanod.abd2Dcr <= (nanoLatch[ NANO_DCR+1:NANO_DCR] == 2'b11);
+            Nanod.dcr2Dbd <= (nanoLatch[ NANO_DCR+2:NANO_DCR+1] == 2'b11);
+            Nanod.dbd2Alue <= (nanoLatch[ NANO_ALUE+2:NANO_ALUE+1] == 2'b10);
+            Nanod.alue2Dbd <= (nanoLatch[ NANO_ALUE+1:NANO_ALUE] == 2'b01);
+
+            Nanod.dbd2Alub <= nanoLatch[ NANO_DBD2ALUB];
+            Nanod.abd2Alub <= nanoLatch[ NANO_ABD2ALUB];
+
+            // Originally not latched. We better should because we transfer one cycle later, T3 instead of T1.
+            Nanod.dobCtrl <= dobCtrl;
+            // Nanod.adb2Dob <= (dobCtrl == 2'b10);
+            // Nanod.dbd2Dob <= (dobCtrl == 2'b01);
+            // Nanod.alu2Dob <= (dobCtrl == 2'b11);
+
+            // Might be better not to register these signals to allow latching RX/RY mux earlier!
+            // But then must latch Irdecod.isPcRel on T3!
+
+            Nanod.rxl2db <= Nanod.reg2dbl & !dblSpecial & nanoLatch[ NANO_RXL_DBL];
+            Nanod.rxl2ab <= Nanod.reg2abl & !ablSpecial & !nanoLatch[ NANO_RXL_DBL];
+
+            Nanod.dbl2rxl <= Nanod.dbl2reg & !dblSpecial & nanoLatch[ NANO_RXL_DBL];
+            Nanod.abl2rxl <= Nanod.abl2reg & !ablSpecial & !nanoLatch[ NANO_RXL_DBL];
+
+            Nanod.rxh2dbh <= Nanod.reg2dbh & !dbhSpecial & nanoLatch[ NANO_RXH_DBH];
+            Nanod.rxh2abh <= Nanod.reg2abh & !abhSpecial & !nanoLatch[ NANO_RXH_DBH];
+
+            Nanod.dbh2rxh <= Nanod.dbh2reg & !dbhSpecial & nanoLatch[ NANO_RXH_DBH];
+            Nanod.abh2rxh <= Nanod.abh2reg & !abhSpecial & !nanoLatch[ NANO_RXH_DBH];
+
+            Nanod.dbh2ryh <= Nanod.dbh2reg & !dbhSpecial & !nanoLatch[ NANO_RXH_DBH];
+            Nanod.abh2ryh <= Nanod.abh2reg & !abhSpecial & nanoLatch[ NANO_RXH_DBH];
+
+            Nanod.dbl2ryl <= Nanod.dbl2reg & !dblSpecial & !nanoLatch[ NANO_RXL_DBL];
+            Nanod.abl2ryl <= Nanod.abl2reg & !ablSpecial & nanoLatch[ NANO_RXL_DBL];
+
+            Nanod.ryl2db <= Nanod.reg2dbl & !dblSpecial & !nanoLatch[ NANO_RXL_DBL];
+            Nanod.ryl2ab <= Nanod.reg2abl & !ablSpecial & nanoLatch[ NANO_RXL_DBL];
+
+            Nanod.ryh2dbh <= Nanod.reg2dbh & !dbhSpecial & !nanoLatch[ NANO_RXH_DBH];
+            Nanod.ryh2abh <= Nanod.reg2abh & !abhSpecial & nanoLatch[ NANO_RXH_DBH];
+
+            // Originally isTas only delayed on T2 (and seems only a late mask rev fix)
+            // Better latch the combination on T4
+            Nanod.isRmc <= Irdecod.isTas & nanoLatch[ NANO_BUSBYTE];
+        end
+    end
+
+    // Update SSW at the start of Bus/Addr error ucode
+    assign Nanod.updSsw    = Nanod.aob2Ab;
+
+    assign Nanod.updTpend  = (ftuCtrl == NANO_FTU_UPDTPEND);
+    assign Nanod.clrTpend  = (ftuCtrl == NANO_FTU_CLRTPEND);
+    assign Nanod.tvn2Ftu   = (ftuCtrl == NANO_FTU_TVN);
+    assign Nanod.const2Ftu = (ftuCtrl == NANO_FTU_CONST);
+    assign Nanod.ftu2Dbl   = (ftuCtrl == NANO_FTU_DBL) | ( ftuCtrl == NANO_FTU_INL);
+    assign Nanod.ftu2Abl   = (ftuCtrl == NANO_FTU_2ABL);
+    assign Nanod.inl2psw   = (ftuCtrl == NANO_FTU_INL);
+    assign Nanod.pswIToFtu = (ftuCtrl == NANO_FTU_PSWI);
+    assign Nanod.ftu2Sr    = (ftuCtrl == NANO_FTU_2SR);
+    assign Nanod.sr2Ftu    = (ftuCtrl == NANO_FTU_RDSR);
+    assign Nanod.ird2Ftu   = (ftuCtrl == NANO_FTU_IRD);       // Used on bus/addr error
+    assign Nanod.ssw2Ftu   = (ftuCtrl == NANO_FTU_SSW);
+    assign Nanod.initST    = (ftuCtrl == NANO_FTU_INL) | (ftuCtrl == NANO_FTU_CLRTPEND) | (ftuCtrl == NANO_FTU_INIT_ST);
+    assign Nanod.abl2Pren  = (ftuCtrl == NANO_FTU_ABL2PREN);
+    assign Nanod.updPren   = (ftuCtrl == NANO_FTU_RSTPREN);
+
+    assign Nanod.Ir2Ird    = nanoLatch[ NANO_IR2IRD];
+
+    // ALU control better latched later after combining with IRD decoding
+
+    wire [1:0] aluFinInit  = nanoLatch[NANO_ALU_FI +: 2];
+
+    assign Nanod.aluDctrl  = nanoLatch[NANO_ALU_DCTRL +: 2];
+    assign Nanod.aluActrl  = nanoLatch[NANO_ALU_ACTRL];
+    assign Nanod.aluColumn = { nanoLatch[ NANO_ALU_COL], nanoLatch[ NANO_ALU_COL+1], nanoLatch[ NANO_ALU_COL+2]};
+    assign Nanod.aluFinish = (aluFinInit == 2'b10) ? 1'b1 : 1'b0;
+    assign Nanod.aluInit   = (aluFinInit == 2'b01) ? 1'b1 : 1'b0;
+
+    // FTU 2 CCR encoded as both ALU Init and ALU Finish set.
+    // In theory this encoding allows writes to CCR without writing to SR
+    // But FTU 2 CCR and to SR are both set together at nanorom.
+    assign Nanod.ftu2Ccr   = (aluFinInit == 2'b11) ? 1'b1 : 1'b0;
+
+    assign Nanod.abdIsByte = nanoLatch[ NANO_ABDHRECHARGE];
+
+    // Not being latched on T4 creates non unique case warning!
+    assign Nanod.au2Db = (nanoLatch[ NANO_AUOUT +: 2] == 2'b01) ? 1'b1 : 1'b0;
+    assign Nanod.au2Ab = (nanoLatch[ NANO_AUOUT +: 2] == 2'b10) ? 1'b1 : 1'b0;
+    assign Nanod.au2Pc = (nanoLatch[ NANO_AUOUT +: 2] == 2'b11) ? 1'b1 : 1'b0;
+
+    assign Nanod.db2Aob = (aobCtrl == 2'b10) ? 1'b1 : 1'b0;
+    assign Nanod.ab2Aob = (aobCtrl == 2'b01) ? 1'b1 : 1'b0;
+    assign Nanod.au2Aob = (aobCtrl == 2'b11) ? 1'b1 : 1'b0;
+
+    assign Nanod.dbin2Abd = nanoLatch[ NANO_DBIN2ABD];
+    assign Nanod.dbin2Dbd = nanoLatch[ NANO_DBIN2DBD];
+
+    assign Nanod.permStart     = (aobCtrl != 2'b00) ? 1'b1 : 1'b0;
+    assign Nanod.isWrite       = nanoLatch[NANO_DOBCTRL_1]
+                               | nanoLatch[NANO_DOBCTRL_0];
+    assign Nanod.waitBusFinish = nanoLatch[NANO_DOBCTRL_1]
+                               | nanoLatch[NANO_DOBCTRL_0]
+                               | nanoLatch[NANO_TOIRC]
+                               | nanoLatch[NANO_TODBIN];
+    assign Nanod.busByte       = nanoLatch[NANO_BUSBYTE];
+
+    assign Nanod.noLowByte     = nanoLatch[NANO_LOWBYTE];
+    assign Nanod.noHighByte    = nanoLatch[NANO_HIGHBYTE];
+
+    // Not registered. Register at T4 after combining
+    // Might be better to remove all those and combine here instead of at execution unit !!
+    assign Nanod.abl2reg = nanoLatch[ NANO_ABL2REG];
+    assign Nanod.abh2reg = nanoLatch[ NANO_ABH2REG];
+    assign Nanod.dbl2reg = nanoLatch[ NANO_DBL2REG];
+    assign Nanod.dbh2reg = nanoLatch[ NANO_DBH2REG];
+    assign Nanod.reg2dbl = nanoLatch[ NANO_REG2DBL];
+    assign Nanod.reg2dbh = nanoLatch[ NANO_REG2DBH];
+    assign Nanod.reg2abl = nanoLatch[ NANO_REG2ABL];
+    assign Nanod.reg2abh = nanoLatch[ NANO_REG2ABH];
+
+    assign Nanod.ssp = nanoLatch[ NANO_SSP];
+
+    assign Nanod.rz = nanoLatch[ NANO_RZ];
+
+    // Actually DTL can't happen on PC relative mode. See IR decoder.
+
+    wire dtldbd = 1'b0;
+    wire dthdbh = 1'b0;
+    wire dtlabd = 1'b0;
+    wire dthabh = 1'b0;
+
+    wire dblSpecial = Nanod.pcldbl | dtldbd;
+    wire dbhSpecial = Nanod.pchdbh | dthdbh;
+    wire ablSpecial = Nanod.pclabl | dtlabd;
+    wire abhSpecial = Nanod.pchabh | dthabh;
+
+    //
+    // Combine with IRD decoding
+    // Careful that IRD is updated only on T1! All output depending on IRD must be latched on T4!
+    //
+
+    // PC used instead of RY on PC relative instuctions
+
+    assign Nanod.rxlDbl = nanoLatch[ NANO_RXL_DBL];
+    wire isPcRel  = Irdecod.isPcRel & ~nanoLatch[NANO_RZ];
+    wire pcRelDbl = isPcRel & ~nanoLatch[NANO_RXL_DBL];
+    wire pcRelDbh = isPcRel & ~nanoLatch[NANO_RXH_DBH];
+    wire pcRelAbl = isPcRel &  nanoLatch[NANO_RXL_DBL];
+    wire pcRelAbh = isPcRel &  nanoLatch[NANO_RXH_DBH];
+
+    assign Nanod.pcldbl = nanoLatch[ NANO_PCLDBL] | pcRelDbl;
+    assign Nanod.pchdbh = (nanoLatch[NANO_PCH +: 2] == 2'b01) ? 1'b1 : pcRelDbh;
+
+    assign Nanod.pclabl = nanoLatch[ NANO_PCLABL] | pcRelAbl;
+    assign Nanod.pchabh = (nanoLatch[NANO_PCH +: 2] == 2'b10) ? 1'b1 : pcRelAbh;
+
 endmodule
 
 //
@@ -917,207 +838,210 @@ endmodule
 // IRD updated on T1, while ncode still executing. To avoid using the next IRD,
 // decoded signals must be registered on T3, or T4 before using them.
 //
-module irdDecode( input [15:0] ird,
-			output s_irdecod Irdecod);
-
-	wire [3:0] line = ird[15:12];
-	logic [15:0] lineOnehot;
-
-	// This can be registered and pipelined from the IR decoder !
-	onehotEncoder4 irdLines( line, lineOnehot);
-	
-	wire isRegShift = (lineOnehot['he]) & (ird[7:6] != 2'b11);
-	wire isDynShift = isRegShift & ird[5];
-					
-	assign Irdecod.isPcRel = (& ird[ 5:3]) & ~isDynShift & !ird[2] & ird[1];		
-	assign Irdecod.isTas = lineOnehot[4] & (ird[11:6] == 6'b101011);
-	
-	assign Irdecod.rx = ird[11:9];
-	assign Irdecod.ry = ird[ 2:0];
-
-	wire isPreDecr = (ird[ 5:3] == 3'b100);
-	wire eaAreg = (ird[5:3] == 3'b001);
-		
-	// rx is A or D
-	// movem
-	always_comb begin
-		unique case( 1'b1)
-		lineOnehot[1],
-		lineOnehot[2],
-		lineOnehot[3]:
-					// MOVE: RX always Areg except if dest mode is Dn 000
-					Irdecod.rxIsAreg = (| ird[8:6]);
-
-		lineOnehot[4]:		Irdecod.rxIsAreg = (& ird[8:6]);		// not CHK (LEA)
-
-		lineOnehot['h8]:	Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7];	// SBCD
-		lineOnehot['hc]:	Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7];	// ABCD/EXG An,An				
-		
-		lineOnehot['h9],
-		lineOnehot['hb],
-		lineOnehot['hd]:	Irdecod.rxIsAreg =
-							(ird[7] & ird[6]) |								// SUBA/CMPA/ADDA
-							(eaAreg & ird[8] & (ird[7:6] != 2'b11));		// SUBX/CMPM/ADDX		
-		default:
-				Irdecod.rxIsAreg = Irdecod.implicitSp;
-		endcase
-	end	
-
-	// RX is movem
-	always_comb begin
-		Irdecod.rxIsMovem = lineOnehot[4] & ~ird[8] & ~Irdecod.implicitSp;
-	end
-	assign Irdecod.movemPreDecr = Irdecod.rxIsMovem & isPreDecr;
-	
-	// RX is DT.
-	// but SSP explicit or pc explicit has higher priority!
-	// addq/subq (scc & dbcc also, but don't use rx)
-	// Immediate including static bit
-	assign Irdecod.rxIsDt = lineOnehot[5] | (lineOnehot[0] & ~ird[8]);
-	
-	// RX is USP
-	assign Irdecod.rxIsUsp = lineOnehot[4] & (ird[ 11:4] == 8'he6);
-	
-	// RY is DT
-	// rz or PC explicit has higher priority
-	
-	wire eaImmOrAbs = (ird[5:3] == 3'b111) & ~ird[1];
-	assign Irdecod.ryIsDt = eaImmOrAbs & ~isRegShift;
-		
-	// RY is Address register
-	always_comb begin
-		logic eaIsAreg;
-		
-		// On most cases RY is Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL)
-		eaIsAreg = (ird[5:3] != 3'b000) & (ird[5:3] != 3'b111);
-		
-		unique case( 1'b1)
-				// MOVE: RY always Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL)
-				// Most lines, including misc line 4, also.
-		default:		Irdecod.ryIsAreg = eaIsAreg;
-
-		lineOnehot[5]:	// DBcc is an exception
-						Irdecod.ryIsAreg = eaIsAreg & (ird[7:3] != 5'b11001);
-
-		lineOnehot[6],
-		lineOnehot[7]:	Irdecod.ryIsAreg = 1'b0;
-
-		lineOnehot['he]:
-						Irdecod.ryIsAreg = ~isRegShift;
-		endcase
-	end	
-
-	// Byte sized instruction
-		
-	// Original implementation sets this for some instructions that aren't really byte size
-	// but doesn't matter because they don't have a byte transfer enabled at nanocode, such as MOVEQ
-		
-	wire xIsScc = (ird[7:6] == 2'b11) & (ird[5:3] != 3'b001); 
-	wire xStaticMem = (ird[11:8] == 4'b1000) & (ird[5:4] == 2'b00);		// Static bit to mem
-	always_comb begin
-		unique case( 1'b1)
-		lineOnehot[0]:
-				Irdecod.isByte = 
-				( ird[8] & (ird[5:4] != 2'b00)					) |	// Dynamic bit to mem
-				( (ird[11:8] == 4'b1000) & (ird[5:4] != 2'b00)	) |	// Static bit to mem
-				( (ird[8:7] == 2'b10) & (ird[5:3] == 3'b001)	) |	// Movep from mem only! For byte mux
-				( (ird[8:6] == 3'b000) & !xStaticMem );				// Immediate byte
-								
-		lineOnehot[1]:			Irdecod.isByte = 1'b1;		// MOVE.B
-	
-		
-		lineOnehot[4]:			Irdecod.isByte = (ird[7:6] == 2'b00) | Irdecod.isTas;		
-		lineOnehot[5]:			Irdecod.isByte = (ird[7:6] == 2'b00) | xIsScc;
-		
-		lineOnehot[8],
-		lineOnehot[9],
-		lineOnehot['hb],
-		lineOnehot['hc],
-		lineOnehot['hd],
-		lineOnehot['he]:		Irdecod.isByte = (ird[7:6] == 2'b00);
-		
-		default:				Irdecod.isByte = 1'b0;
-		endcase
-	end	
-	
-	// Need it for special byte size. Bus is byte, but whole register word is modified.
-	assign Irdecod.isMovep = lineOnehot[0] & ird[8] & eaAreg;
-	
-	
-	// rxIsSP implicit use of RX for actual SP transfer
-	//
-	// This logic is simple and will include some instructions that don't actually reference SP.
-	// But doesn't matter as long as they don't perform any RX transfer.
-	
-	always_comb begin
-		unique case( 1'b1)
-		lineOnehot[6]:		Irdecod.implicitSp = (ird[11:8] == 4'b0001);		// BSR
-		lineOnehot[4]:
-			// Misc like RTS, JSR, etc
-			Irdecod.implicitSp = (ird[11:8] == 4'b1110) | (ird[11:6] == 6'b1000_01);
-		default:			Irdecod.implicitSp = 1'b0;
-		endcase
-	end
-	
-	// Modify CCR (and not SR)
-	// Probably overkill !! Only needs to distinguish SR vs CCR
-	// RTR, MOVE to CCR, xxxI to CCR
-	assign Irdecod.toCcr =	( lineOnehot[4] & ((ird[11:0] == 12'he77) | (ird[11:6] == 6'b010011)) ) |
-							( lineOnehot[0] & (ird[8:6] == 3'b000));
-	
-	// FTU constants
-	// This should not be latched on T3/T4. Latch on T2 or not at all. FTU needs it on next T3.
-	// Note: Reset instruction gets constant from ALU not from FTU!
-	logic [15:0] ftuConst;
-	wire [3:0] zero28 = (ird[11:9] == 0) ? 4'h8 : { 1'b0, ird[11:9]};		// xltate 0,1-7 into 8,1-7
-
-	always_comb begin
-		unique case( 1'b1)
-		lineOnehot[6],														// Bcc short
-		lineOnehot[7]:		ftuConst = { { 8{ ird[ 7]}}, ird[ 7:0] };		// MOVEQ
-		
-		lineOnehot['h5],													// addq/subq/static shift double check this
-		lineOnehot['he]:	ftuConst = { 12'b0, zero28};
-		
-		// MULU/MULS DIVU/DIVS
-		lineOnehot['h8],
-		lineOnehot['hc]:	ftuConst = 16'h0f;
-
-		lineOnehot[4]:		ftuConst = 16'h80;								// TAS
-
-		default:			ftuConst = '0;
-		endcase	
-	end	
-	assign Irdecod.ftuConst = ftuConst;
-	
-	//
-	// TRAP Vector # for group 2 exceptions
-	//
-	
-	always_comb begin
-		if( lineOnehot[4]) begin
-			case ( ird[6:5])
-			2'b00,2'b01:	Irdecod.macroTvn = 6;					// CHK
-			2'b11:			Irdecod.macroTvn = 7;					// TRAPV
-			2'b10:			Irdecod.macroTvn = {2'b10, ird[3:0]};	// TRAP
-			endcase
-		end
-		else
-							Irdecod.macroTvn = 5;					// Division by zero
-	end
-	
-	
-	wire eaAdir = (ird[ 5:3] == 3'b001);
-	wire size11 = ird[7] & ird[6];
-	
-	// Opcodes variants that don't affect flags
-	// ADDA/SUBA ADDQ/SUBQ MOVEA
-
-	assign Irdecod.inhibitCcr =
-		( (lineOnehot[9] | lineOnehot['hd]) & size11) |				// ADDA/SUBA
-		( lineOnehot[5] & eaAdir) |									// ADDQ/SUBQ to An (originally checks for line[4] as well !?)
-		( (lineOnehot[2] | lineOnehot[3]) & ird[8:6] == 3'b001);	// MOVEA
-		
+module irdDecode
+(
+    input [15:0] ird,
+    output s_irdecod Irdecod
+);
+
+    wire [3:0] line = ird[15:12];
+    logic [15:0] lineOnehot;
+
+    // This can be registered and pipelined from the IR decoder !
+    onehotEncoder4 irdLines( line, lineOnehot);
+
+    wire isRegShift = (lineOnehot['he]) & (ird[7:6] != 2'b11);
+    wire isDynShift = isRegShift & ird[5];
+
+    assign Irdecod.isPcRel = (& ird[ 5:3]) & ~isDynShift & !ird[2] & ird[1];
+    assign Irdecod.isTas = lineOnehot[4] & (ird[11:6] == 6'b101011);
+
+    assign Irdecod.rx = ird[11:9];
+    assign Irdecod.ry = ird[ 2:0];
+
+    wire isPreDecr = (ird[ 5:3] == 3'b100);
+    wire eaAreg = (ird[5:3] == 3'b001);
+
+    // rx is A or D
+    // movem
+    always_comb begin
+        unique case (1'b1)
+        lineOnehot[1],
+        lineOnehot[2],
+        lineOnehot[3]:
+                    // MOVE: RX always Areg except if dest mode is Dn 000
+                    Irdecod.rxIsAreg = (| ird[8:6]);
+
+        lineOnehot[4]:      Irdecod.rxIsAreg = (& ird[8:6]);        // not CHK (LEA)
+
+        lineOnehot['h8]:    Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7];   // SBCD
+        lineOnehot['hc]:    Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7];   // ABCD/EXG An,An
+
+        lineOnehot['h9],
+        lineOnehot['hb],
+        lineOnehot['hd]:    Irdecod.rxIsAreg =
+                            (ird[7] & ird[6]) |                             // SUBA/CMPA/ADDA
+                            (eaAreg & ird[8] & (ird[7:6] != 2'b11));        // SUBX/CMPM/ADDX
+        default:
+                Irdecod.rxIsAreg = Irdecod.implicitSp;
+        endcase
+    end
+
+    // RX is movem
+    always_comb begin
+        Irdecod.rxIsMovem = lineOnehot[4] & ~ird[8] & ~Irdecod.implicitSp;
+    end
+    assign Irdecod.movemPreDecr = Irdecod.rxIsMovem & isPreDecr;
+
+    // RX is DT.
+    // but SSP explicit or pc explicit has higher priority!
+    // addq/subq (scc & dbcc also, but don't use rx)
+    // Immediate including static bit
+    assign Irdecod.rxIsDt = lineOnehot[5] | (lineOnehot[0] & ~ird[8]);
+
+    // RX is USP
+    assign Irdecod.rxIsUsp = lineOnehot[4] & (ird[ 11:4] == 8'he6);
+
+    // RY is DT
+    // rz or PC explicit has higher priority
+
+    wire eaImmOrAbs = (ird[5:3] == 3'b111) & ~ird[1];
+    assign Irdecod.ryIsDt = eaImmOrAbs & ~isRegShift;
+
+    // RY is Address register
+    always_comb begin
+        logic eaIsAreg;
+
+        // On most cases RY is Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL)
+        eaIsAreg = (ird[5:3] != 3'b000) & (ird[5:3] != 3'b111);
+
+        unique case (1'b1)
+                // MOVE: RY always Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL)
+                // Most lines, including misc line 4, also.
+        default:        Irdecod.ryIsAreg = eaIsAreg;
+
+        lineOnehot[5]:  // DBcc is an exception
+                        Irdecod.ryIsAreg = eaIsAreg & (ird[7:3] != 5'b11001);
+
+        lineOnehot[6],
+        lineOnehot[7]:  Irdecod.ryIsAreg = 1'b0;
+
+        lineOnehot['he]:
+                        Irdecod.ryIsAreg = ~isRegShift;
+        endcase
+    end
+
+    // Byte sized instruction
+
+    // Original implementation sets this for some instructions that aren't really byte size
+    // but doesn't matter because they don't have a byte transfer enabled at nanocode, such as MOVEQ
+
+    wire xIsScc = (ird[7:6] == 2'b11) & (ird[5:3] != 3'b001);
+    wire xStaticMem = (ird[11:8] == 4'b1000) & (ird[5:4] == 2'b00);     // Static bit to mem
+    always_comb begin
+        unique case (1'b1)
+        lineOnehot[0]:
+                Irdecod.isByte =
+                ( ird[8] & (ird[5:4] != 2'b00)                  ) | // Dynamic bit to mem
+                ( (ird[11:8] == 4'b1000) & (ird[5:4] != 2'b00)  ) | // Static bit to mem
+                ( (ird[8:7] == 2'b10) & (ird[5:3] == 3'b001)    ) | // Movep from mem only! For byte mux
+                ( (ird[8:6] == 3'b000) & !xStaticMem );             // Immediate byte
+
+        lineOnehot[1]:          Irdecod.isByte = 1'b1;      // MOVE.B
+
+
+        lineOnehot[4]:          Irdecod.isByte = (ird[7:6] == 2'b00) | Irdecod.isTas;
+        lineOnehot[5]:          Irdecod.isByte = (ird[7:6] == 2'b00) | xIsScc;
+
+        lineOnehot[8],
+        lineOnehot[9],
+        lineOnehot['hb],
+        lineOnehot['hc],
+        lineOnehot['hd],
+        lineOnehot['he]:        Irdecod.isByte = (ird[7:6] == 2'b00);
+
+        default:                Irdecod.isByte = 1'b0;
+        endcase
+    end
+
+    // Need it for special byte size. Bus is byte, but whole register word is modified.
+    assign Irdecod.isMovep = lineOnehot[0] & ird[8] & eaAreg;
+
+
+    // rxIsSP implicit use of RX for actual SP transfer
+    //
+    // This logic is simple and will include some instructions that don't actually reference SP.
+    // But doesn't matter as long as they don't perform any RX transfer.
+
+    always_comb begin
+        unique case (1'b1)
+        lineOnehot[6]:      Irdecod.implicitSp = (ird[11:8] == 4'b0001);        // BSR
+        lineOnehot[4]:
+            // Misc like RTS, JSR, etc
+            Irdecod.implicitSp = (ird[11:8] == 4'b1110) | (ird[11:6] == 6'b1000_01);
+        default:            Irdecod.implicitSp = 1'b0;
+        endcase
+    end
+
+    // Modify CCR (and not SR)
+    // Probably overkill !! Only needs to distinguish SR vs CCR
+    // RTR, MOVE to CCR, xxxI to CCR
+    assign Irdecod.toCcr =  ( lineOnehot[4] & ((ird[11:0] == 12'he77) | (ird[11:6] == 6'b010011)) ) |
+                            ( lineOnehot[0] & (ird[8:6] == 3'b000));
+
+    // FTU constants
+    // This should not be latched on T3/T4. Latch on T2 or not at all. FTU needs it on next T3.
+    // Note: Reset instruction gets constant from ALU not from FTU!
+    logic [15:0] ftuConst;
+    wire [3:0] zero28 = (ird[11:9] == 0) ? 4'h8 : { 1'b0, ird[11:9]};       // xltate 0,1-7 into 8,1-7
+
+    always_comb begin
+        unique case (1'b1)
+        lineOnehot[6],                                                      // Bcc short
+        lineOnehot[7]:      ftuConst = { { 8{ ird[ 7]}}, ird[ 7:0] };       // MOVEQ
+
+        lineOnehot['h5],                                                    // addq/subq/static shift double check this
+        lineOnehot['he]:    ftuConst = { 12'b0, zero28};
+
+        // MULU/MULS DIVU/DIVS
+        lineOnehot['h8],
+        lineOnehot['hc]:    ftuConst = 16'h0f;
+
+        lineOnehot[4]:      ftuConst = 16'h80;                              // TAS
+
+        default:            ftuConst = '0;
+        endcase
+    end
+    assign Irdecod.ftuConst = ftuConst;
+
+    //
+    // TRAP Vector # for group 2 exceptions
+    //
+
+    always_comb begin
+        if (lineOnehot[4]) begin
+            case ( ird[6:5])
+            2'b00,2'b01:    Irdecod.macroTvn = 6;                   // CHK
+            2'b11:          Irdecod.macroTvn = 7;                   // TRAPV
+            2'b10:          Irdecod.macroTvn = {2'b10, ird[3:0]};   // TRAP
+            endcase
+        end
+        else
+                            Irdecod.macroTvn = 5;                   // Division by zero
+    end
+
+
+    wire eaAdir = (ird[ 5:3] == 3'b001);
+    wire size11 = ird[7] & ird[6];
+
+    // Opcodes variants that don't affect flags
+    // ADDA/SUBA ADDQ/SUBQ MOVEA
+
+    assign Irdecod.inhibitCcr =
+        ( (lineOnehot[9] | lineOnehot['hd]) & size11) |             // ADDA/SUBA
+        ( lineOnehot[5] & eaAdir) |                                 // ADDQ/SUBQ to An (originally checks for line[4] as well !?)
+        ( (lineOnehot[2] | lineOnehot[3]) & ird[8:6] == 3'b001);    // MOVEA
+
 endmodule
 
 /*
@@ -1129,548 +1053,558 @@ endmodule
 
 */
 
-module excUnit( input s_clks Clks,
-	input enT1, enT2, enT3, enT4,
-	input s_nanod Nanod, input s_irdecod Irdecod,
-	input [15:0] Ird,			// ALU row (and others) decoder needs it	
-	input pswS,
-	input [15:0] ftu,
-	input [15:0] iEdb,
-	
-	output logic [7:0] ccr,
-	output [15:0] alue,
-	
-	output prenEmpty, au05z,
-	output logic dcr4, ze,
-	output logic aob0,
-	output [15:0] AblOut,
-	output logic [15:0] Irc,
-	output logic [15:0] oEdb,
-	output logic [23:1] eab);
-
-localparam REG_USP = 15;
-localparam REG_SSP = 16;
-localparam REG_DT = 17;
-
-	// Register file
-	reg [15:0] regs68L[ 18];
-	reg [15:0] regs68H[ 18];
-
-// synthesis translate off
-	/*
-		It is bad practice to initialize simulation registers that the hardware doesn't.
-		There is risk that simulation would be different than the real hardware. But in this case is the other way around.
-		Some ROM uses something like sub.l An,An at powerup which clears the register
-		Simulator power ups the registers with 'X, as they are really undetermined at the real hardware.
-		But the simulator doesn't realize (it can't) that the same value is substracting from itself,
-		and that the result should be zero even when it's 'X - 'X.
-	*/
-	
-	initial begin
-		for( int i = 0; i < 18; i++) begin
-			regs68L[i] <= '0;
-			regs68H[i] <= '0;
-		end
-	end
-	
-	// For simulation display only
-	wire [31:0] SSP = { regs68H[REG_SSP], regs68L[REG_SSP]};
-	
-// synthesis translate on
-	
-
-	wire [15:0] aluOut;
-	wire [15:0] dbin;
-	logic [15:0] dcrOutput;
-
-	reg [15:0] PcL, PcH;
-
-	reg [31:0] auReg, aob;
-
-	reg [15:0] Ath, Atl;
-
-	// Bus execution
-	reg [15:0] Dbl, Dbh;
-	reg [15:0] Abh, Abl;
-	reg [15:0] Abd, Dbd;
-	
-	assign AblOut = Abl;
-	assign au05z = (~| auReg[5:0]);
-	
-	logic [15:0] dblMux, dbhMux;
-	logic [15:0] abhMux, ablMux;
-	logic [15:0] abdMux, dbdMux;
-	
-	logic abdIsByte;
-		
-	logic Pcl2Dbl, Pch2Dbh;
-	logic Pcl2Abl, Pch2Abh;
-	
-	
-	// RX RY muxes	
-	// RX and RY actual registers
-	logic [4:0] actualRx, actualRy;
-	logic [3:0] movemRx;
-	logic byteNotSpAlign;			// Byte instruction and no sp word align
-	
-	// IRD decoded signals must be latched. See comments on decoder
-	// But nanostore decoding can't be latched before T4.
-	//
-	// If we need this earlier we can register IRD decode on T3 and use nano async
-
-	logic [4:0] rxMux, ryMux;
-	logic [3:0] rxReg, ryReg;
-	logic rxIsSp, ryIsSp;
-	logic rxIsAreg, ryIsAreg;
-	
-	always_comb begin
-	
-		// Unique IF !!
-		if( Nanod.ssp) begin
-			rxMux = REG_SSP;
-			rxIsSp = 1'b1;
-			rxReg = 1'bX;
-		end
-		else if( Irdecod.rxIsUsp) begin
-			rxMux = REG_USP;
-			rxIsSp = 1'b1;
-			rxReg = 1'bX;
-		end
-		else if( Irdecod.rxIsDt & !Irdecod.implicitSp) begin
-			rxMux = REG_DT;
-			rxIsSp = 1'b0;
-			rxReg = 1'bX;
-		end
-		else begin
-			if( Irdecod.implicitSp)
-				rxReg = 15;
-			else if( Irdecod.rxIsMovem)
-				rxReg = movemRx;
-			else
-				rxReg = { Irdecod.rxIsAreg, Irdecod.rx};
-				
-			if( (& rxReg)) begin
-				rxMux = pswS ? REG_SSP : 15;
-				rxIsSp = 1'b1;
-			end
-			else begin
-				rxMux = { 1'b0, rxReg};
-				rxIsSp = 1'b0;
-			end
-		end
-
-		// RZ has higher priority!		
-		if( Irdecod.ryIsDt & !Nanod.rz) begin
-			ryMux = REG_DT;
-			ryIsSp = 1'b0;
-			ryReg = 'X;
-		end
-		else begin
-			ryReg = Nanod.rz ? Irc[15:12] : {Irdecod.ryIsAreg, Irdecod.ry};
-			ryIsSp = (& ryReg);
-			if( ryIsSp & pswS)			// No implicit SP on RY
-				ryMux = REG_SSP;
-			else
-				ryMux = { 1'b0, ryReg};
-		end
-					
-	end	
-	
-	always_ff @( posedge Clks.clk) begin
-		if( enT4) begin
-			byteNotSpAlign <= Irdecod.isByte & ~(Nanod.rxlDbl ? rxIsSp : ryIsSp);
-				
-			actualRx <= rxMux;
-			actualRy <= ryMux;
-			
-			rxIsAreg <= rxIsSp | rxMux[3];
-			ryIsAreg <= ryIsSp | ryMux[3];			
-		end
-		
-		if( enT4)
-			abdIsByte <= Nanod.abdIsByte & Irdecod.isByte;
-	end
-			
-	// Set RX/RY low word to which bus segment is connected.
-		
-	wire ryl2Abl = Nanod.ryl2ab & (ryIsAreg | Nanod.ablAbd);
-	wire ryl2Abd = Nanod.ryl2ab & (~ryIsAreg | Nanod.ablAbd);
-	wire ryl2Dbl = Nanod.ryl2db & (ryIsAreg | Nanod.dblDbd);
-	wire ryl2Dbd = Nanod.ryl2db & (~ryIsAreg | Nanod.dblDbd);
-
-	wire rxl2Abl = Nanod.rxl2ab & (rxIsAreg | Nanod.ablAbd);
-	wire rxl2Abd = Nanod.rxl2ab & (~rxIsAreg | Nanod.ablAbd);
-	wire rxl2Dbl = Nanod.rxl2db & (rxIsAreg | Nanod.dblDbd);
-	wire rxl2Dbd = Nanod.rxl2db & (~rxIsAreg | Nanod.dblDbd);
-	
-	// Buses. Main mux
-	
-	logic abhIdle, ablIdle, abdIdle;
-	logic dbhIdle, dblIdle, dbdIdle;
-	
-	always_comb begin
-		{abhIdle, ablIdle, abdIdle} = '0;
-		{dbhIdle, dblIdle, dbdIdle} = '0;
-
-		unique case( 1'b1)
-		ryl2Dbd:				dbdMux = regs68L[ actualRy];
-		rxl2Dbd:				dbdMux = regs68L[ actualRx];
-		Nanod.alue2Dbd:			dbdMux = alue;
-		Nanod.dbin2Dbd:			dbdMux = dbin;
-		Nanod.alu2Dbd:			dbdMux = aluOut;
-		Nanod.dcr2Dbd:			dbdMux = dcrOutput;
-		default: begin			dbdMux = 'X;	dbdIdle = 1'b1;				end
-		endcase
-	
-		unique case( 1'b1)
-		rxl2Dbl:				dblMux = regs68L[ actualRx];
-		ryl2Dbl:				dblMux = regs68L[ actualRy];
-		Nanod.ftu2Dbl:			dblMux = ftu;
-		Nanod.au2Db:			dblMux = auReg[15:0];
-		Nanod.atl2Dbl:			dblMux = Atl;
-		Pcl2Dbl:				dblMux = PcL;
-		default: begin			dblMux = 'X;	dblIdle = 1'b1;				end
-		endcase
-			
-		unique case( 1'b1)
-		Nanod.rxh2dbh:			dbhMux = regs68H[ actualRx];
-		Nanod.ryh2dbh:			dbhMux = regs68H[ actualRy];
-		Nanod.au2Db:			dbhMux = auReg[31:16];
-		Nanod.ath2Dbh:			dbhMux = Ath;
-		Pch2Dbh:				dbhMux = PcH;
-		default: begin			dbhMux = 'X;	dbhIdle = 1'b1;				end
-		endcase
-
-		unique case( 1'b1)
-		ryl2Abd:				abdMux = regs68L[ actualRy];
-		rxl2Abd:				abdMux = regs68L[ actualRx];
-		Nanod.dbin2Abd:			abdMux = dbin;
-		Nanod.alu2Abd:			abdMux = aluOut;
-		default: begin			abdMux = 'X;	abdIdle = 1'b1;				end
-		endcase
-
-		unique case( 1'b1)
-		Pcl2Abl:				ablMux = PcL;
-		rxl2Abl:				ablMux = regs68L[ actualRx];
-		ryl2Abl:				ablMux = regs68L[ actualRy];
-		Nanod.ftu2Abl:			ablMux = ftu;
-		Nanod.au2Ab:			ablMux = auReg[15:0];
-		Nanod.aob2Ab:			ablMux = aob[15:0];
-		Nanod.atl2Abl:			ablMux = Atl;
-		default: begin			ablMux = 'X;	ablIdle = 1'b1;				end
-		endcase
-			
-		unique case( 1'b1)		
-		Pch2Abh:				abhMux = PcH;
-		Nanod.rxh2abh:			abhMux = regs68H[ actualRx];
-		Nanod.ryh2abh:			abhMux = regs68H[ actualRy];
-		Nanod.au2Ab:			abhMux = auReg[31:16];
-		Nanod.aob2Ab:			abhMux = aob[31:16];
-		Nanod.ath2Abh:			abhMux = Ath;
-		default: begin			abhMux = 'X;	abhIdle = 1'b1;				end
-		endcase
-			
-	end
-	
-	// Source starts driving the bus on T1. Bus holds data until end of T3. Destination latches at T3.
-
-	// These registers store the first level mux, without bus interconnections.
-	// Even when this uses almost to 100 registers, it saves a lot of comb muxing and it is much faster.
-	reg [15:0] preAbh, preAbl, preAbd;
-	reg [15:0] preDbh, preDbl, preDbd;
-	
-	always_ff @( posedge Clks.clk) begin
-
-		// Register first level mux at T1		
-		if( enT1) begin
-			{preAbh, preAbl, preAbd} <= { abhMux, ablMux, abdMux};
-			{preDbh, preDbl, preDbd} <= { dbhMux, dblMux, dbdMux};			
-		end
-		
-		// Process bus interconnection at T2. Many combinations only used on DIV
-		// We use a simple method. If a specific bus segment is not driven we know that it should get data from a neighbour segment.
-		// In some cases this is not true and the segment is really idle without any destination. But then it doesn't matter.
-		
-		if( enT2) begin
-			if( Nanod.extAbh)
-				Abh <= { 16{ ablIdle ? preAbd[ 15] : preAbl[ 15] }};
-			else if( abhIdle)
-				Abh <= ablIdle ? preAbd : preAbl;
-			else
-				Abh <= preAbh;
-
-			if( ~ablIdle)
-				Abl <= preAbl;
-			else
-				Abl <= Nanod.ablAbh ? preAbh : preAbd;
-
-			Abd <= ~abdIdle ? preAbd : ablIdle ? preAbh : preAbl;
-
-			if( Nanod.extDbh)
-				Dbh <= { 16{ dblIdle ? preDbd[ 15] : preDbl[ 15] }};
-			else if( dbhIdle)
-				Dbh <= dblIdle ? preDbd : preDbl;
-			else
-				Dbh <= preDbh;
-
-			if( ~dblIdle)
-				Dbl <= preDbl;
-			else
-				Dbl <= Nanod.dblDbh ? preDbh : preDbd;
-
-			Dbd <= ~dbdIdle ? preDbd: dblIdle ? preDbh : preDbl;
-			
-			/*
-			Dbl <= dblMux;			Dbh <= dbhMux;
-			Abd <= abdMux;			Dbd <= dbdMux;
-			Abh <= abhMux;			Abl <= ablMux; */
-		end
-	end
-
-	// AOB
-	//
-	// Originally change on T1. We do on T2, only then the output is enabled anyway.
-	//
-	// AOB[0] is used for address error. But even when raises on T1, seems not actually used until T2 or possibly T3.
-	// It is used on T1 when deasserted at the BSER exception ucode. Probably deassertion timing is not critical. 
-	// But in that case (at BSER), AOB is loaded from AU, so we can safely transfer on T1.
-
-	// We need to take directly from first level muxes that are updated and T1
-			
-	wire au2Aob = Nanod.au2Aob | (Nanod.au2Db & Nanod.db2Aob);
-	
-	always_ff @( posedge Clks.clk) begin
-		// UNIQUE IF !
-		
-		if( enT1 & au2Aob)		// From AU we do can on T1
-			aob <= auReg;
-		else if( enT2) begin
-			if( Nanod.db2Aob)
-				aob <= { preDbh, ~dblIdle ? preDbl : preDbd};
-			else if( Nanod.ab2Aob)
-				aob <= { preAbh, ~ablIdle ? preAbl : preAbd};
-		end
-	end
-
-	assign eab = aob[23:1];
-	assign aob0 = aob[0];
-				
-	// AU
-	logic [31:0] auInpMux;
-
-	// `ifdef ALW_COMB_BUG
-	// Old Modelsim bug. Doesn't update ouput always. Need excplicit sensitivity list !?
-	// always @( Nanod.auCntrl) begin
-	
-	always_comb begin
-		unique case( Nanod.auCntrl)
-		3'b000:		auInpMux = 0;
-		3'b001:		auInpMux = byteNotSpAlign | Nanod.noSpAlign ? 1 : 2;		// +1/+2
-		3'b010:		auInpMux = -4;
-		3'b011:		auInpMux = { Abh, Abl};
-		3'b100:		auInpMux = 2;
-		3'b101:		auInpMux = 4;
-		3'b110:		auInpMux = -2;
-		3'b111:		auInpMux = byteNotSpAlign | Nanod.noSpAlign ? -1 : -2;	// -1/-2
-		default:	auInpMux = 'X;
-		endcase
-	end
-
-	// Simulation problem
-	// Sometimes (like in MULM1) DBH is not set. AU is used in these cases just as a 6 bits counter testing if bits 5-0 are zero.
-	// But when adding something like 32'hXXXX0000, the simulator (incorrectly) will set *all the 32 bits* of the result as X.
-
-// synthesis translate_off 
-	`define SIMULBUGX32 1
-	wire [16:0] aulow = Dbl + auInpMux[15:0];
-	wire [31:0] auResult = {Dbh + auInpMux[31:16] + aulow[16], aulow[15:0]};
+module excUnit
+(
+    input s_clks Clks,
+    input enT1, enT2, enT3, enT4,
+    input s_nanod Nanod,
+    input s_irdecod Irdecod,
+    input [15:0] Ird,           // ALU row (and others) decoder needs it
+    input pswS,
+    input [15:0] ftu,
+    input [15:0] iEdb,
+
+    output logic [7:0] ccr,
+    output [15:0] alue,
+
+    output prenEmpty, au05z,
+    output logic dcr4, ze,
+    output logic aob0,
+    output [15:0] AblOut,
+    output logic [15:0] Irc,
+    output logic [15:0] oEdb,
+    output logic [23:1] eab
+);
+
+localparam
+    REG_USP = 15,
+    REG_SSP = 16,
+    REG_DT  = 17;
+
+    // Register file
+    reg [15:0] regs68L[0:17];
+    reg [15:0] regs68H[0:17];
+
+`ifdef verilator3
+
+    /*
+        It is bad practice to initialize simulation registers that the hardware doesn't.
+        There is risk that simulation would be different than the real hardware. But in this case is the other way around.
+        Some ROM uses something like sub.l An,An at powerup which clears the register
+        Simulator power ups the registers with 'X, as they are really undetermined at the real hardware.
+        But the simulator doesn't realize (it can't) that the same value is substracting from itself,
+        and that the result should be zero even when it's 'X - 'X.
+    */
+
+    initial begin
+        for( int i = 0; i < 18; i++) begin
+            regs68L[i] = 16'h0000;
+            regs68H[i] = 16'h0000;
+        end
+    end
+
+    // For simulation display only
+    wire [31:0] SSP = { regs68H[REG_SSP], regs68L[REG_SSP]};
+
+`endif
+
+
+    wire [15:0] aluOut;
+    wire [15:0] dbin;
+    logic [15:0] dcrOutput;
+
+    reg [15:0] PcL, PcH;
+
+    reg [31:0] auReg, aob;
+
+    reg [15:0] Ath, Atl;
+
+    // Bus execution
+    reg [15:0] Dbl, Dbh;
+    reg [15:0] Abh, Abl;
+    reg [15:0] Abd, Dbd;
+
+    assign AblOut = Abl;
+    assign au05z = (~| auReg[5:0]);
+
+    logic [15:0] dblMux, dbhMux;
+    logic [15:0] abhMux, ablMux;
+    logic [15:0] abdMux, dbdMux;
+
+    logic abdIsByte;
+
+    logic Pcl2Dbl, Pch2Dbh;
+    logic Pcl2Abl, Pch2Abh;
+
+
+    // RX RY muxes
+    // RX and RY actual registers
+    logic [4:0] actualRx, actualRy;
+    logic [3:0] movemRx;
+    logic byteNotSpAlign;           // Byte instruction and no sp word align
+
+    // IRD decoded signals must be latched. See comments on decoder
+    // But nanostore decoding can't be latched before T4.
+    //
+    // If we need this earlier we can register IRD decode on T3 and use nano async
+
+    logic [4:0] rxMux, ryMux;
+    logic [3:0] rxReg, ryReg;
+    logic rxIsSp, ryIsSp;
+    logic rxIsAreg, ryIsAreg;
+
+    always_comb begin
+
+        // Unique IF !!
+        if (Nanod.ssp) begin
+            rxMux  = REG_SSP[4:0];
+            rxIsSp = 1'b1;
+            rxReg  = 4'hX;
+        end
+        else if (Irdecod.rxIsUsp) begin
+            rxMux  = REG_USP[4:0];
+            rxIsSp = 1'b1;
+            rxReg  = 4'hX;
+        end
+        else if (Irdecod.rxIsDt & !Irdecod.implicitSp) begin
+            rxMux  = REG_DT[4:0];
+            rxIsSp = 1'b0;
+            rxReg  = 4'hX;
+        end
+        else begin
+            if (Irdecod.implicitSp)
+                rxReg = REG_USP[3:0];
+            else if (Irdecod.rxIsMovem)
+                rxReg = movemRx;
+            else
+                rxReg = { Irdecod.rxIsAreg, Irdecod.rx};
+
+            if (&rxReg) begin
+                rxMux  = pswS ? REG_SSP[4:0] : REG_USP[4:0];
+                rxIsSp = 1'b1;
+            end
+            else begin
+                rxMux  = { 1'b0, rxReg};
+                rxIsSp = 1'b0;
+            end
+        end
+
+        // RZ has higher priority!
+        if (Irdecod.ryIsDt & !Nanod.rz) begin
+            ryMux  = REG_DT[4:0];
+            ryIsSp = 1'b0;
+            ryReg  = 4'hX;
+        end
+        else begin
+            ryReg = Nanod.rz ? Irc[15:12] : {Irdecod.ryIsAreg, Irdecod.ry};
+            ryIsSp = (& ryReg);
+            if (ryIsSp & pswS)          // No implicit SP on RY
+                ryMux = REG_SSP[4:0];
+            else
+                ryMux = { 1'b0, ryReg};
+        end
+
+    end
+
+    always_ff @( posedge Clks.clk) begin
+    
+        if (enT4) begin
+            byteNotSpAlign <= Irdecod.isByte & ~(Nanod.rxlDbl ? rxIsSp : ryIsSp);
+
+            actualRx <= rxMux;
+            actualRy <= ryMux;
+
+            rxIsAreg <= rxIsSp | rxMux[3];
+            ryIsAreg <= ryIsSp | ryMux[3];
+
+            abdIsByte <= Nanod.abdIsByte & Irdecod.isByte;
+        end
+    end
+
+    // Set RX/RY low word to which bus segment is connected.
+
+    wire ryl2Abl = Nanod.ryl2ab & ( ryIsAreg | Nanod.ablAbd);
+    wire ryl2Abd = Nanod.ryl2ab & (~ryIsAreg | Nanod.ablAbd);
+    wire ryl2Dbl = Nanod.ryl2db & ( ryIsAreg | Nanod.dblDbd);
+    wire ryl2Dbd = Nanod.ryl2db & (~ryIsAreg | Nanod.dblDbd);
+
+    wire rxl2Abl = Nanod.rxl2ab & ( rxIsAreg | Nanod.ablAbd);
+    wire rxl2Abd = Nanod.rxl2ab & (~rxIsAreg | Nanod.ablAbd);
+    wire rxl2Dbl = Nanod.rxl2db & ( rxIsAreg | Nanod.dblDbd);
+    wire rxl2Dbd = Nanod.rxl2db & (~rxIsAreg | Nanod.dblDbd);
+
+    // Buses. Main mux
+
+    logic abhIdle, ablIdle, abdIdle;
+    logic dbhIdle, dblIdle, dbdIdle;
+
+    always_comb begin
+        {abhIdle, ablIdle, abdIdle} = 3'b000;
+        {dbhIdle, dblIdle, dbdIdle} = 3'b000;
+
+        unique case (1'b1)
+        ryl2Dbd:                dbdMux = regs68L[ actualRy];
+        rxl2Dbd:                dbdMux = regs68L[ actualRx];
+        Nanod.alue2Dbd:         dbdMux = alue;
+        Nanod.dbin2Dbd:         dbdMux = dbin;
+        Nanod.alu2Dbd:          dbdMux = aluOut;
+        Nanod.dcr2Dbd:          dbdMux = dcrOutput;
+        default: begin          dbdMux = 'X;    dbdIdle = 1'b1;             end
+        endcase
+
+        unique case (1'b1)
+        rxl2Dbl:                dblMux = regs68L[ actualRx];
+        ryl2Dbl:                dblMux = regs68L[ actualRy];
+        Nanod.ftu2Dbl:          dblMux = ftu;
+        Nanod.au2Db:            dblMux = auReg[15:0];
+        Nanod.atl2Dbl:          dblMux = Atl;
+        Pcl2Dbl:                dblMux = PcL;
+        default: begin          dblMux = 'X;    dblIdle = 1'b1;             end
+        endcase
+
+        unique case (1'b1)
+        Nanod.rxh2dbh:          dbhMux = regs68H[ actualRx];
+        Nanod.ryh2dbh:          dbhMux = regs68H[ actualRy];
+        Nanod.au2Db:            dbhMux = auReg[31:16];
+        Nanod.ath2Dbh:          dbhMux = Ath;
+        Pch2Dbh:                dbhMux = PcH;
+        default: begin          dbhMux = 'X;    dbhIdle = 1'b1;             end
+        endcase
+
+        unique case (1'b1)
+        ryl2Abd:                abdMux = regs68L[ actualRy];
+        rxl2Abd:                abdMux = regs68L[ actualRx];
+        Nanod.dbin2Abd:         abdMux = dbin;
+        Nanod.alu2Abd:          abdMux = aluOut;
+        default: begin          abdMux = 'X;    abdIdle = 1'b1;             end
+        endcase
+
+        unique case (1'b1)
+        Pcl2Abl:                ablMux = PcL;
+        rxl2Abl:                ablMux = regs68L[ actualRx];
+        ryl2Abl:                ablMux = regs68L[ actualRy];
+        Nanod.ftu2Abl:          ablMux = ftu;
+        Nanod.au2Ab:            ablMux = auReg[15:0];
+        Nanod.aob2Ab:           ablMux = aob[15:0];
+        Nanod.atl2Abl:          ablMux = Atl;
+        default: begin          ablMux = 'X;    ablIdle = 1'b1;             end
+        endcase
+
+        unique case (1'b1)
+        Pch2Abh:                abhMux = PcH;
+        Nanod.rxh2abh:          abhMux = regs68H[ actualRx];
+        Nanod.ryh2abh:          abhMux = regs68H[ actualRy];
+        Nanod.au2Ab:            abhMux = auReg[31:16];
+        Nanod.aob2Ab:           abhMux = aob[31:16];
+        Nanod.ath2Abh:          abhMux = Ath;
+        default: begin          abhMux = 'X;    abhIdle = 1'b1;             end
+        endcase
+
+    end
+
+    // Source starts driving the bus on T1. Bus holds data until end of T3. Destination latches at T3.
+
+    // These registers store the first level mux, without bus interconnections.
+    // Even when this uses almost to 100 registers, it saves a lot of comb muxing and it is much faster.
+    reg [15:0] preAbh, preAbl, preAbd;
+    reg [15:0] preDbh, preDbl, preDbd;
+
+    always_ff @( posedge Clks.clk) begin
+
+        // Register first level mux at T1
+        if (enT1) begin
+            {preAbh, preAbl, preAbd} <= { abhMux, ablMux, abdMux};
+            {preDbh, preDbl, preDbd} <= { dbhMux, dblMux, dbdMux};
+        end
+
+        // Process bus interconnection at T2. Many combinations only used on DIV
+        // We use a simple method. If a specific bus segment is not driven we know that it should get data from a neighbour segment.
+        // In some cases this is not true and the segment is really idle without any destination. But then it doesn't matter.
+
+        if (enT2) begin
+            if (Nanod.extAbh)
+                Abh <= { 16{ ablIdle ? preAbd[ 15] : preAbl[ 15] }};
+            else if (abhIdle)
+                Abh <= ablIdle ? preAbd : preAbl;
+            else
+                Abh <= preAbh;
+
+            if (~ablIdle)
+                Abl <= preAbl;
+            else
+                Abl <= Nanod.ablAbh ? preAbh : preAbd;
+
+            Abd <= ~abdIdle ? preAbd : ablIdle ? preAbh : preAbl;
+
+            if (Nanod.extDbh)
+                Dbh <= { 16{ dblIdle ? preDbd[ 15] : preDbl[ 15] }};
+            else if (dbhIdle)
+                Dbh <= dblIdle ? preDbd : preDbl;
+            else
+                Dbh <= preDbh;
+
+            if (~dblIdle)
+                Dbl <= preDbl;
+            else
+                Dbl <= Nanod.dblDbh ? preDbh : preDbd;
+
+            Dbd <= ~dbdIdle ? preDbd: dblIdle ? preDbh : preDbl;
+
+            /*
+            Dbl <= dblMux;
+            Dbh <= dbhMux;
+            Abd <= abdMux;
+            Dbd <= dbdMux;
+            Abh <= abhMux;
+            Abl <= ablMux;
+            */
+        end
+    end
+
+    // AOB
+    //
+    // Originally change on T1. We do on T2, only then the output is enabled anyway.
+    //
+    // AOB[0] is used for address error. But even when raises on T1, seems not actually used until T2 or possibly T3.
+    // It is used on T1 when deasserted at the BSER exception ucode. Probably deassertion timing is not critical.
+    // But in that case (at BSER), AOB is loaded from AU, so we can safely transfer on T1.
+
+    // We need to take directly from first level muxes that are updated and T1
+
+    wire au2Aob = Nanod.au2Aob | (Nanod.au2Db & Nanod.db2Aob);
+
+    always_ff @( posedge Clks.clk) begin
+        // UNIQUE IF !
+
+        if (enT1 & au2Aob)      // From AU we do can on T1
+            aob <= auReg;
+        else if (enT2) begin
+            if (Nanod.db2Aob)
+                aob <= { preDbh, ~dblIdle ? preDbl : preDbd};
+            else if (Nanod.ab2Aob)
+                aob <= { preAbh, ~ablIdle ? preAbl : preAbd};
+        end
+    end
+
+    assign eab = aob[23:1];
+    assign aob0 = aob[0];
+
+    // AU
+    logic [31:0] auInpMux;
+
+    // `ifdef ALW_COMB_BUG
+    // Old Modelsim bug. Doesn't update ouput always. Need excplicit sensitivity list !?
+    // always @( Nanod.auCntrl) begin
+
+    always_comb begin
+        unique case (Nanod.auCntrl)
+            3'b000:  auInpMux = 32'h00000000;
+            3'b001:  auInpMux = byteNotSpAlign | Nanod.noSpAlign ? 32'h00000001 : 32'h00000002; // +1/+2
+            3'b010:  auInpMux = 32'hFFFFFFFC;
+            3'b011:  auInpMux = { Abh, Abl};
+            3'b100:  auInpMux = 32'h00000002;
+            3'b101:  auInpMux = 32'h00000004;
+            3'b110:  auInpMux = 32'hFFFFFFFE;
+            3'b111:  auInpMux = byteNotSpAlign | Nanod.noSpAlign ? 32'hFFFFFFFF : 32'hFFFFFFFE; // -1/-2
+            default: auInpMux = 32'h00000000;
+        endcase
+    end
+
+    // Simulation problem
+    // Sometimes (like in MULM1) DBH is not set. AU is used in these cases just as a 6 bits counter testing if bits 5-0 are zero.
+    // But when adding something like 32'hXXXX0000, the simulator (incorrectly) will set *all the 32 bits* of the result as X.
+
+// synthesis translate_off
+    `define SIMULBUGX32 1
+    wire [16:0] aulow = Dbl + auInpMux[15:0];
+    wire [31:0] auResult = {Dbh + auInpMux[31:16] + {15'b0, aulow[16]}, aulow[15:0]};
 // synthesis translate_on
 
-	always_ff @( posedge Clks.clk) begin
-		if( Clks.pwrUp)
-			auReg <= '0;
-		else if( enT3 & Nanod.auClkEn)
-			`ifdef SIMULBUGX32
-				auReg <= auResult;
-			`else
-				auReg <= { Dbh, Dbl } + auInpMux;
-			`endif
-	end
-	
-	
-	// Main A/D registers
-	
-	always_ff @( posedge Clks.clk) begin
-		if( enT3) begin
-			if( Nanod.dbl2rxl | Nanod.abl2rxl) begin
-				if( ~rxIsAreg) begin
-					if( Nanod.dbl2rxl)			regs68L[ actualRx] <= Dbd;
-					else if( abdIsByte)			regs68L[ actualRx][7:0] <= Abd[7:0];
-					else						regs68L[ actualRx] <= Abd;
-				end
-				else
-					regs68L[ actualRx] <= Nanod.dbl2rxl ? Dbl : Abl;
-			end
-				
-			if( Nanod.dbl2ryl | Nanod.abl2ryl) begin
-				if( ~ryIsAreg) begin
-					if( Nanod.dbl2ryl)			regs68L[ actualRy] <= Dbd;
-					else if( abdIsByte)			regs68L[ actualRy][7:0] <= Abd[7:0];
-					else						regs68L[ actualRy] <= Abd;				
-				end
-				else
-					regs68L[ actualRy] <= Nanod.dbl2ryl ? Dbl : Abl;
-			end
-			
-			// High registers are easier. Both A & D on the same buses, and not byte ops.
-			if( Nanod.dbh2rxh | Nanod.abh2rxh)
-				regs68H[ actualRx] <= Nanod.dbh2rxh ? Dbh : Abh;
-			if( Nanod.dbh2ryh | Nanod.abh2ryh)
-				regs68H[ actualRy] <= Nanod.dbh2ryh ? Dbh : Abh;
-				
-		end	
-	end
-		
-	// PC & AT
-	reg dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl;
-		
-	always_ff @( posedge Clks.clk) begin
-		if( Clks.extReset) begin
-			{ dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl } <= '0;
-			
-			Pcl2Dbl <= 1'b0;
-			Pch2Dbh <= 1'b0;
-			Pcl2Abl <= 1'b0;
-			Pch2Abh <= 1'b0;
-		end
-		else if( enT4) begin				// Must latch on T4 !
-			dbl2Pcl <= Nanod.dbl2reg & Nanod.pcldbl;
-			dbh2Pch <= Nanod.dbh2reg & Nanod.pchdbh;
-			abh2Pch <= Nanod.abh2reg & Nanod.pchabh;
-			abl2Pcl <= Nanod.abl2reg & Nanod.pclabl;
-			
-			Pcl2Dbl <= Nanod.reg2dbl & Nanod.pcldbl;
-			Pch2Dbh <= Nanod.reg2dbh & Nanod.pchdbh;
-			Pcl2Abl <= Nanod.reg2abl & Nanod.pclabl;
-			Pch2Abh <= Nanod.reg2abh & Nanod.pchabh;
-		end
-		
-		// Unique IF !!!
-		if( enT1 & Nanod.au2Pc)
-			PcL <= auReg[15:0];
-		else if( enT3) begin
-			if( dbl2Pcl)
-				PcL <= Dbl;
-			else if( abl2Pcl)
-				PcL <= Abl;
-		end
-			
-		// Unique IF !!!
-		if( enT1 & Nanod.au2Pc)
-			PcH <= auReg[31:16];
-		else if( enT3) begin
-			if( dbh2Pch)
-				PcH <= Dbh;
-			else if( abh2Pch)
-				PcH <= Abh;
-		end
-
-		// Unique IF !!!
-		if( enT3) begin
-			if( Nanod.dbl2Atl)
-				Atl <= Dbl;
-			else if( Nanod.abl2Atl)
-				Atl <= Abl;
-		end
-
-		// Unique IF !!!
-		if( enT3) begin
-			if( Nanod.abh2Ath)
-				Ath <= Abh;
-			else if( Nanod.dbh2Ath)
-				Ath <= Dbh;
-		end
-
-	end
-
-	// Movem reg mask priority encoder
-	
-	wire rmIdle;
-	logic [3:0] prHbit;
-	logic [15:0] prenLatch;
-	
-	// Invert reg order for predecrement mode
-	assign prenEmpty = (~| prenLatch);	
-	pren rmPren( .mask( prenLatch), .hbit (prHbit));
-
-	always_ff @( posedge Clks.clk) begin
-		// Cheating: PREN always loaded from DBIN
-		// Must be on T1 to branch earlier if reg mask is empty!
-		if( enT1 & Nanod.abl2Pren)
-			prenLatch <= dbin;
-		else if( enT3 & Nanod.updPren) begin
-			prenLatch [prHbit] <= 1'b0;
-			movemRx <= Irdecod.movemPreDecr ? ~prHbit : prHbit;
-		end
-	end
-	
-	// DCR
-	wire [15:0] dcrCode;
-
-	wire [3:0] dcrInput = abdIsByte ? { 1'b0, Abd[ 2:0]} : Abd[ 3:0];
-	onehotEncoder4 dcrDecoder( .bin( dcrInput), .bitMap( dcrCode));
-	
-	always_ff @( posedge Clks.clk) begin
-		if( Clks.pwrUp)
-			dcr4 <= '0;
-		else if( enT3 & Nanod.abd2Dcr) begin
-			dcrOutput <= dcrCode;
-			dcr4 <= Abd[4];
-		end
-	end
-	
-	// ALUB
-	reg [15:0] alub;
-	
-	always_ff @( posedge Clks.clk) begin
-		if( enT3) begin
-			// UNIQUE IF !!
-			if( Nanod.dbd2Alub)
-				alub <= Dbd;
-			else if( Nanod.abd2Alub)
-				alub <= Abd;				// abdIsByte affects this !!??
-		end
-	end
-	
-	wire alueClkEn = enT3 & Nanod.dbd2Alue;
-
-	// DOB/DBIN/IRC
-	
-	logic [15:0] dobInput;
-	wire dobIdle = (~| Nanod.dobCtrl);
-	
-	always_comb begin
-		unique case (Nanod.dobCtrl)
-		NANO_DOB_ADB:		dobInput = Abd;
-		NANO_DOB_DBD:		dobInput = Dbd;
-		NANO_DOB_ALU:		dobInput = aluOut;
-		default:			dobInput = 'X;
-		endcase
-	end
-
-	dataIo dataIo( .Clks, .enT1, .enT2, .enT3, .enT4, .Nanod, .Irdecod,
-			.iEdb, .dobIdle, .dobInput, .aob0,
-			.Irc, .dbin, .oEdb);
-
-	fx68kAlu alu(
-		.clk( Clks.clk), .pwrUp( Clks.pwrUp), .enT1, .enT3, .enT4,
-		.ird( Ird),
-		.aluColumn( Nanod.aluColumn), .aluAddrCtrl( Nanod.aluActrl),
-		.init( Nanod.aluInit), .finish( Nanod.aluFinish), .aluIsByte( Irdecod.isByte),
-		.ftu2Ccr( Nanod.ftu2Ccr),
-		.alub, .ftu, .alueClkEn, .alue,
-		.aluDataCtrl( Nanod.aluDctrl), .iDataBus( Dbd), .iAddrBus(Abd),
-		.ze, .aluOut, .ccr);
+    always_ff @( posedge Clks.clk) begin
+        if (Clks.pwrUp)
+            auReg <= '0;
+        else if (enT3 & Nanod.auClkEn)
+            `ifdef SIMULBUGX32
+                auReg <= auResult;
+            `else
+                auReg <= { Dbh, Dbl } + auInpMux;
+            `endif
+    end
+
+
+    // Main A/D registers
+
+    always_ff @( posedge Clks.clk) begin
+        if (enT3) begin
+            if (Nanod.dbl2rxl | Nanod.abl2rxl) begin
+                if (~rxIsAreg) begin
+                    if (Nanod.dbl2rxl)          regs68L[ actualRx] <= Dbd;
+                    else if (abdIsByte)         regs68L[ actualRx][7:0] <= Abd[7:0];
+                    else                        regs68L[ actualRx] <= Abd;
+                end
+                else
+                    regs68L[ actualRx] <= Nanod.dbl2rxl ? Dbl : Abl;
+            end
+
+            if (Nanod.dbl2ryl | Nanod.abl2ryl) begin
+                if (~ryIsAreg) begin
+                    if (Nanod.dbl2ryl)          regs68L[ actualRy] <= Dbd;
+                    else if (abdIsByte)         regs68L[ actualRy][7:0] <= Abd[7:0];
+                    else                        regs68L[ actualRy] <= Abd;
+                end
+                else
+                    regs68L[ actualRy] <= Nanod.dbl2ryl ? Dbl : Abl;
+            end
+
+            // High registers are easier. Both A & D on the same buses, and not byte ops.
+            if (Nanod.dbh2rxh | Nanod.abh2rxh)
+                regs68H[ actualRx] <= Nanod.dbh2rxh ? Dbh : Abh;
+            if (Nanod.dbh2ryh | Nanod.abh2ryh)
+                regs68H[ actualRy] <= Nanod.dbh2ryh ? Dbh : Abh;
+
+        end
+    end
+
+    // PC & AT
+    reg dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl;
+
+    always_ff @( posedge Clks.clk) begin
+        if (Clks.extReset) begin
+            { dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl } <= '0;
+
+            Pcl2Dbl <= 1'b0;
+            Pch2Dbh <= 1'b0;
+            Pcl2Abl <= 1'b0;
+            Pch2Abh <= 1'b0;
+        end
+        else if (enT4) begin                // Must latch on T4 !
+            dbl2Pcl <= Nanod.dbl2reg & Nanod.pcldbl;
+            dbh2Pch <= Nanod.dbh2reg & Nanod.pchdbh;
+            abh2Pch <= Nanod.abh2reg & Nanod.pchabh;
+            abl2Pcl <= Nanod.abl2reg & Nanod.pclabl;
+
+            Pcl2Dbl <= Nanod.reg2dbl & Nanod.pcldbl;
+            Pch2Dbh <= Nanod.reg2dbh & Nanod.pchdbh;
+            Pcl2Abl <= Nanod.reg2abl & Nanod.pclabl;
+            Pch2Abh <= Nanod.reg2abh & Nanod.pchabh;
+        end
+
+        // Unique IF !!!
+        if (enT1 & Nanod.au2Pc)
+            PcL <= auReg[15:0];
+        else if (enT3) begin
+            if (dbl2Pcl)
+                PcL <= Dbl;
+            else if (abl2Pcl)
+                PcL <= Abl;
+        end
+
+        // Unique IF !!!
+        if (enT1 & Nanod.au2Pc)
+            PcH <= auReg[31:16];
+        else if (enT3) begin
+            if (dbh2Pch)
+                PcH <= Dbh;
+            else if (abh2Pch)
+                PcH <= Abh;
+        end
+
+        // Unique IF !!!
+        if (enT3) begin
+            if (Nanod.dbl2Atl)
+                Atl <= Dbl;
+            else if (Nanod.abl2Atl)
+                Atl <= Abl;
+        end
+
+        // Unique IF !!!
+        if (enT3) begin
+            if (Nanod.abh2Ath)
+                Ath <= Abh;
+            else if (Nanod.dbh2Ath)
+                Ath <= Dbh;
+        end
+
+    end
+
+    // Movem reg mask priority encoder
+
+    wire         rmIdle;
+    logic  [3:0] prHbit;
+    logic [15:0] prenLatch;
+
+    // Invert reg order for predecrement mode
+    assign prenEmpty = (~| prenLatch);
+    pren rmPren( .mask( prenLatch), .hbit (prHbit));
+
+    always_ff @( posedge Clks.clk) begin
+        // Cheating: PREN always loaded from DBIN
+        // Must be on T1 to branch earlier if reg mask is empty!
+        if (enT1 & Nanod.abl2Pren)
+            prenLatch <= dbin;
+        else if (enT3 & Nanod.updPren) begin
+            prenLatch [prHbit] <= 1'b0;
+            movemRx <= Irdecod.movemPreDecr ? ~prHbit : prHbit;
+        end
+    end
+
+    // DCR
+    wire [15:0] dcrCode;
+
+    wire [3:0] dcrInput = abdIsByte ? { 1'b0, Abd[ 2:0]} : Abd[ 3:0];
+    onehotEncoder4 dcrDecoder( .bin( dcrInput), .bitMap( dcrCode));
+
+    always_ff @( posedge Clks.clk) begin
+        if (Clks.pwrUp)
+            dcr4 <= '0;
+        else if (enT3 & Nanod.abd2Dcr) begin
+            dcrOutput <= dcrCode;
+            dcr4 <= Abd[4];
+        end
+    end
+
+    // ALUB
+    reg [15:0] alub;
+
+    always_ff @( posedge Clks.clk) begin
+        if (enT3) begin
+            // UNIQUE IF !!
+            if (Nanod.dbd2Alub)
+                alub <= Dbd;
+            else if (Nanod.abd2Alub)
+                alub <= Abd;                // abdIsByte affects this !!??
+        end
+    end
+
+    wire alueClkEn = enT3 & Nanod.dbd2Alue;
+
+    // DOB/DBIN/IRC
+
+    logic [15:0] dobInput;
+    wire dobIdle = (~| Nanod.dobCtrl);
+
+    always_comb begin
+        unique case (Nanod.dobCtrl)
+        NANO_DOB_ADB:       dobInput = Abd;
+        NANO_DOB_DBD:       dobInput = Dbd;
+        NANO_DOB_ALU:       dobInput = aluOut;
+        default:            dobInput = 'X;
+        endcase
+    end
+
+    dataIo dataIo( .Clks, .enT1, .enT2, .enT3, .enT4, .Nanod, .Irdecod,
+            .iEdb, .dobIdle, .dobInput, .aob0,
+            .Irc, .dbin, .oEdb);
+
+    fx68kAlu alu(
+        .clk( Clks.clk), .pwrUp( Clks.pwrUp), .enT1, .enT3, .enT4,
+        .ird( Ird),
+        .aluColumn( Nanod.aluColumn), .aluAddrCtrl( Nanod.aluActrl),
+        .init( Nanod.aluInit), .finish( Nanod.aluFinish), .aluIsByte( Irdecod.isByte),
+        .ftu2Ccr( Nanod.ftu2Ccr),
+        .alub, .ftu, .alueClkEn, .alue,
+        .aluDataCtrl( Nanod.aluDctrl), .iDataBus( Dbd), .iAddrBus(Abd),
+        .ze, .aluOut, .ccr);
 
 endmodule
 
@@ -1684,91 +1618,91 @@ endmodule
 // We capture directly from the external data bus to the internal registers (IRC & DBIN) on PHI2, starting the external S7 phase, at a T4 internal period.
 
 module dataIo( input s_clks Clks,
-	input enT1, enT2, enT3, enT4,
-	input s_nanod Nanod, input s_irdecod Irdecod,
-	input [15:0] iEdb,
-	input aob0,
-
-	input dobIdle,
-	input [15:0] dobInput,
-	
-	output logic [15:0] Irc,	
-	output logic [15:0] dbin,
-	output logic [15:0] oEdb
-	);
-
-	reg [15:0] dob;
-	
-	// DBIN/IRC
-	
-	// Timing is different than any other register. We can latch only on the next T4 (bus phase S7).
-	// We need to register all control signals correctly because the next ublock will already be started.
-	// Can't latch control on T4 because if there are wait states there might be multiple T4 before we latch.
-	
-	reg xToDbin, xToIrc;
-	reg dbinNoLow, dbinNoHigh;
-	reg byteMux, isByte_T4;
-	
-	always_ff @( posedge Clks.clk) begin
-	
-		// Byte mux control. Can't latch at T1. AOB might be not ready yet.
-		// Must latch IRD decode at T1 (or T4). Then combine and latch only at T3.
-
-		// Can't latch at T3, a new IRD might be loaded already at T1.	
-		// Ok to latch at T4 if combination latched then at T3
-		if( enT4)
-			isByte_T4 <= Irdecod.isByte;	// Includes MOVEP from mem, we could OR it here
-
-		if( enT3) begin
-			dbinNoHigh <= Nanod.noHighByte;
-			dbinNoLow <= Nanod.noLowByte;
-			byteMux <= Nanod.busByte & isByte_T4 & ~aob0;
-		end
-		
-		if( enT1) begin
-			// If on wait states, we continue latching until next T1
-			xToDbin <= 1'b0;
-			xToIrc <= 1'b0;			
-		end
-		else if( enT3) begin
-			xToDbin <= Nanod.todbin;
-			xToIrc <= Nanod.toIrc;
-		end
-
-		// Capture on T4 of the next ucycle
-		// If there are wait states, we keep capturing every PHI2 until the next T1
-		
-		if( xToIrc & Clks.enPhi2)
-			Irc <= iEdb;
-		if( xToDbin & Clks.enPhi2) begin
-			// Original connects both halves of EDB.
-			if( ~dbinNoLow)
-				dbin[ 7:0] <= byteMux ? iEdb[ 15:8] : iEdb[7:0];
-			if( ~dbinNoHigh)
-				dbin[ 15:8] <= ~byteMux & dbinNoLow ? iEdb[ 7:0] : iEdb[ 15:8];
-		end
-	end
-	
-	// DOB
-	logic byteCycle;	
-	
-	always_ff @( posedge Clks.clk) begin
-		// Originaly on T1. Transfer to internal EDB also on T1 (stays enabled upto the next T1). But only on T4 (S3) output enables.
-		// It is safe to do on T3, then, but control signals if derived from IRD must be registered.
-		// Originally control signals are not registered.
-		
-		// Wait states don't affect DOB operation that is done at the start of the bus cycle. 
-
-		if( enT4)
-			byteCycle <= Nanod.busByte & Irdecod.isByte;		// busIsByte but not MOVEP
-		
-		// Originally byte low/high interconnect is done at EDB, not at DOB.
-		if( enT3 & ~dobIdle) begin
-			dob[7:0] <= Nanod.noLowByte ? dobInput[15:8] : dobInput[ 7:0];
-			dob[15:8] <= (byteCycle | Nanod.noHighByte) ? dobInput[ 7:0] : dobInput[15:8];
-		end
-	end
-	assign oEdb = dob;
+    input enT1, enT2, enT3, enT4,
+    input s_nanod Nanod, input s_irdecod Irdecod,
+    input [15:0] iEdb,
+    input aob0,
+
+    input dobIdle,
+    input [15:0] dobInput,
+
+    output logic [15:0] Irc,
+    output logic [15:0] dbin,
+    output logic [15:0] oEdb
+    );
+
+    reg [15:0] dob;
+
+    // DBIN/IRC
+
+    // Timing is different than any other register. We can latch only on the next T4 (bus phase S7).
+    // We need to register all control signals correctly because the next ublock will already be started.
+    // Can't latch control on T4 because if there are wait states there might be multiple T4 before we latch.
+
+    reg xToDbin, xToIrc;
+    reg dbinNoLow, dbinNoHigh;
+    reg byteMux, isByte_T4;
+
+    always_ff @( posedge Clks.clk) begin
+
+        // Byte mux control. Can't latch at T1. AOB might be not ready yet.
+        // Must latch IRD decode at T1 (or T4). Then combine and latch only at T3.
+
+        // Can't latch at T3, a new IRD might be loaded already at T1.
+        // Ok to latch at T4 if combination latched then at T3
+        if (enT4)
+            isByte_T4 <= Irdecod.isByte;    // Includes MOVEP from mem, we could OR it here
+
+        if (enT3) begin
+            dbinNoHigh <= Nanod.noHighByte;
+            dbinNoLow <= Nanod.noLowByte;
+            byteMux <= Nanod.busByte & isByte_T4 & ~aob0;
+        end
+
+        if (enT1) begin
+            // If on wait states, we continue latching until next T1
+            xToDbin <= 1'b0;
+            xToIrc  <= 1'b0;
+        end
+        else if (enT3) begin
+            xToDbin <= Nanod.todbin;
+            xToIrc  <= Nanod.toIrc;
+        end
+
+        // Capture on T4 of the next ucycle
+        // If there are wait states, we keep capturing every PHI2 until the next T1
+
+        if (xToIrc & Clks.enPhi2)
+            Irc <= iEdb;
+        if (xToDbin & Clks.enPhi2) begin
+            // Original connects both halves of EDB.
+            if (~dbinNoLow)
+                dbin[ 7:0] <= byteMux ? iEdb[ 15:8] : iEdb[7:0];
+            if (~dbinNoHigh)
+                dbin[ 15:8] <= ~byteMux & dbinNoLow ? iEdb[ 7:0] : iEdb[ 15:8];
+        end
+    end
+
+    // DOB
+    logic byteCycle;
+
+    always_ff @( posedge Clks.clk) begin
+        // Originaly on T1. Transfer to internal EDB also on T1 (stays enabled upto the next T1). But only on T4 (S3) output enables.
+        // It is safe to do on T3, then, but control signals if derived from IRD must be registered.
+        // Originally control signals are not registered.
+
+        // Wait states don't affect DOB operation that is done at the start of the bus cycle.
+
+        if (enT4)
+            byteCycle <= Nanod.busByte & Irdecod.isByte;        // busIsByte but not MOVEP
+
+        // Originally byte low/high interconnect is done at EDB, not at DOB.
+        if (enT3 & ~dobIdle) begin
+            dob[7:0] <= Nanod.noLowByte ? dobInput[15:8] : dobInput[ 7:0];
+            dob[15:8] <= (byteCycle | Nanod.noHighByte) ? dobInput[ 7:0] : dobInput[15:8];
+        end
+    end
+    assign oEdb = dob;
 
 endmodule
 
@@ -1781,112 +1715,107 @@ endmodule
 // IR updated at the least one microinstruction earlier.
 // Just need to configure the timing analizer correctly.
 
-module uaddrDecode( 
-	input [15:0] opcode,
-	output [UADDR_WIDTH-1:0] a1, a2, a3,
-	output logic isPriv, isIllegal, isLineA, isLineF,
-	output [15:0] lineBmap);
-	
-	wire [3:0] line = opcode[15:12];
-	logic [3:0] eaCol, movEa;
-
-	onehotEncoder4 irLineDecod( line, lineBmap);
-	
-	assign isLineA = lineBmap[ 'hA];
-	assign isLineF = lineBmap[ 'hF];
-	
-	pla_lined pla_lined( .movEa( movEa), .col( eaCol),
-		.opcode( opcode), .lineBmap( lineBmap),
-		.palIll( isIllegal), .plaA1( a1), .plaA2( a2), .plaA3( a3) );
-	
-	// ea decoding   
-	assign eaCol = eaDecode( opcode[ 5:0]);
-	assign movEa = eaDecode( {opcode[ 8:6], opcode[ 11:9]} );
-
-	// EA decode
-	function [3:0] eaDecode;
-	input [5:0] eaBits;
-	begin
-	unique case( eaBits[ 5:3])
-	3'b111:
-		case( eaBits[ 2:0])
-		3'b000:   eaDecode = 7;            // Absolute short
-		3'b001:   eaDecode = 8;            // Absolute long
-		3'b010:   eaDecode = 9;            // PC displacement
-		3'b011:   eaDecode = 10;           // PC offset
-		3'b100:   eaDecode = 11;           // Immediate
-		default:  eaDecode = 12;           // Invalid
-		endcase
-         
-	default:   eaDecode = eaBits[5:3];      // Register based EAs
-	endcase
-	end
-	endfunction
-	
-	
-	/*
-	Privileged instructions:
-
-	ANDI/EORI/ORI SR
-	MOVE to SR
-	MOVE to/from USP
-	RESET
-	RTE
-	STOP
-	*/
-	
-	always_comb begin
-		unique case( lineBmap)
-           
-		// ori/andi/eori SR      
-		'h01:   isPriv = ((opcode & 16'hf5ff) == 16'h007c);
-      
-		'h10:
-			begin
-			// No priority !!!
-				if( (opcode & 16'hffc0) == 16'h46c0)        // move to sr
-					isPriv = 1'b1;
-				
-				else if( (opcode & 16'hfff0) == 16'h4e60)   // move usp
-					isPriv = 1'b1;
-		
-				else if(	opcode == 16'h4e70 ||			// reset
-							opcode == 16'h4e73 ||			// rte
-							opcode == 16'h4e72)				// stop
-					isPriv = 1'b1;
-				else
-					isPriv = 1'b0;
-			end
-         
-		default:   isPriv = 1'b0;
-		endcase
-	end
-
-	
+module uaddrDecode
+(
+    input [15:0] opcode,
+    output [UADDR_WIDTH-1:0] a1, a2, a3,
+    output logic isPriv, isIllegal, isLineA, isLineF,
+    output [15:0] lineBmap
+);
+
+    wire [3:0] line = opcode[15:12];
+    logic [3:0] eaCol, movEa;
+
+    onehotEncoder4 irLineDecod( line, lineBmap);
+
+    assign isLineA = lineBmap[ 'hA];
+    assign isLineF = lineBmap[ 'hF];
+
+    uaddrPla U_uaddrPla
+    (
+        .movEa    (movEa),
+        .col      (eaCol),
+        .opcode   (opcode),
+        .lineBmap (lineBmap),
+        .palIll   (isIllegal),
+        .plaA1    (a1),
+        .plaA2    (a2),
+        .plaA3    (a3)
+    );
+
+    // ea decoding
+    assign eaCol = eaDecode( opcode[ 5:0]);
+    assign movEa = eaDecode( {opcode[ 8:6], opcode[ 11:9]} );
+
+    /*
+    Privileged instructions:
+
+    ANDI/EORI/ORI SR
+    MOVE to SR
+    MOVE to/from USP
+    RESET
+    STOP
+    RTE
+    */
+
+    always_comb begin
+        unique case (lineBmap)
+
+        // ori/andi/eori SR
+        'h01:   isPriv = ((opcode & 16'hf5ff) == 16'h007c);
+
+        'h10:
+            begin
+            // No priority !!!
+                if ((opcode & 16'hffc0) == 16'h46c0)        // move to sr
+                    isPriv = 1'b1;
+
+                else if ((opcode & 16'hfff0) == 16'h4e60)   // move usp
+                    isPriv = 1'b1;
+
+                else if (   opcode == 16'h4e70 ||           // reset
+                            opcode == 16'h4e73 ||           // rte
+                            opcode == 16'h4e72)             // stop
+                    isPriv = 1'b1;
+                else
+                    isPriv = 1'b0;
+            end
+
+        default:   isPriv = 1'b0;
+        endcase
+    end
+
+
 endmodule
 
 // bin to one-hot, 4 bits to 16-bit bitmap
-module onehotEncoder4( input [3:0] bin, output reg [15:0] bitMap);
-	always_comb begin
-	case( bin)
-		'b0000:   bitMap = 16'h0001;
-		'b0001:   bitMap = 16'h0002;
-		'b0010:   bitMap = 16'h0004;
-		'b0011:   bitMap = 16'h0008;
-		'b0100:   bitMap = 16'h0010;
-		'b0101:   bitMap = 16'h0020;
-		'b0110:   bitMap = 16'h0040;
-		'b0111:   bitMap = 16'h0080;
-		'b1000:   bitMap = 16'h0100;
-		'b1001:   bitMap = 16'h0200;
-		'b1010:   bitMap = 16'h0400;
-		'b1011:   bitMap = 16'h0800;
-		'b1100:   bitMap = 16'h1000;
-		'b1101:   bitMap = 16'h2000;
-		'b1110:   bitMap = 16'h4000;
-		'b1111:   bitMap = 16'h8000;
-	endcase
-	end
+module onehotEncoder4
+(
+    input       [3:0] bin,
+    output reg [15:0] bitMap
+);
+
+    always_comb begin
+        case (bin)
+            4'h0:   bitMap = 16'b0000000000000001;
+            4'h1:   bitMap = 16'b0000000000000010;
+            4'h2:   bitMap = 16'b0000000000000100;
+            4'h3:   bitMap = 16'b0000000000001000;
+            4'h4:   bitMap = 16'b0000000000010000;
+            4'h5:   bitMap = 16'b0000000000100000;
+            4'h6:   bitMap = 16'b0000000001000000;
+            4'h7:   bitMap = 16'b0000000010000000;
+            4'h8:   bitMap = 16'b0000000100000000;
+            4'h9:   bitMap = 16'b0000001000000000;
+            4'hA:   bitMap = 16'b0000010000000000;
+            4'hB:   bitMap = 16'b0000100000000000;
+            4'hC:   bitMap = 16'b0001000000000000;
+            4'hD:   bitMap = 16'b0010000000000000;
+            4'hE:   bitMap = 16'b0100000000000000;
+            4'hF:   bitMap = 16'b1000000000000000;
+        endcase
+    end
+
 endmodule
 
 // priority encoder
@@ -1900,14 +1829,14 @@ module pren( mask, hbit);
    input [size-1:0] mask;
    output reg [outbits-1:0] hbit;
    // output reg idle;
-   
+
    always @( mask) begin
       integer i;
       hbit = 0;
       // idle = 1;
       for( i = size-1; i >= 0; i = i - 1) begin
-          if( mask[ i]) begin
-             hbit = i;
+          if (mask[i]) begin
+             hbit = i[outbits-1:0];
              // idle = 0;
          end
       end
@@ -1918,239 +1847,239 @@ endmodule
 // Microcode sequencer
 
 module sequencer( input s_clks Clks, input enT3,
-	input [UROM_WIDTH-1:0] microLatch,
-	input A0Err, BerrA, busAddrErr, Spuria, Avia,
-	input Tpend, intPend, isIllegal, isPriv, excRst, isLineA, isLineF,
-	input [15:0] psw,
-	input prenEmpty, au05z, dcr4, ze, i11,
-	input [1:0] alue01,
-	input [15:0] Ird,
-	input [UADDR_WIDTH-1:0] a1, a2, a3,
-	output logic [3:0] tvn,
-	output logic [UADDR_WIDTH-1:0] nma);
-	
-	logic [UADDR_WIDTH-1:0] uNma;
-	logic [UADDR_WIDTH-1:0] grp1Nma;	
-	logic [1:0] c0c1;
-	reg a0Rst;
-	wire A0Sel;
-	wire inGrp0Exc;
-	
-	// assign nma = Clks.extReset ? RSTP0_NMA : (A0Err ? BSER1_NMA : uNma);
-	// assign nma = A0Err ? (a0Rst ? RSTP0_NMA : BSER1_NMA) : uNma;
-	
+    input [UROM_WIDTH-1:0] microLatch,
+    input A0Err, BerrA, busAddrErr, Spuria, Avia,
+    input Tpend, intPend, isIllegal, isPriv, excRst, isLineA, isLineF,
+    input [15:0] psw,
+    input prenEmpty, au05z, dcr4, ze, i11,
+    input [1:0] alue01,
+    input [15:0] Ird,
+    input [UADDR_WIDTH-1:0] a1, a2, a3,
+    output logic [3:0] tvn,
+    output logic [UADDR_WIDTH-1:0] nma);
+
+    logic [UADDR_WIDTH-1:0] uNma;
+    logic [UADDR_WIDTH-1:0] grp1Nma;
+    logic [1:0] c0c1;
+    reg a0Rst;
+    wire A0Sel;
+    wire inGrp0Exc;
+
+    // assign nma = Clks.extReset ? RSTP0_NMA : (A0Err ? BSER1_NMA : uNma);
+    // assign nma = A0Err ? (a0Rst ? RSTP0_NMA : BSER1_NMA) : uNma;
+
     // word type I: 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
     // NMA :        .. .. 09 08 01 00 05 04 03 02 07 06 .. .. .. .. ..
-	
-	wire [UADDR_WIDTH-1:0] dbNma = { microLatch[ 14:13], microLatch[ 6:5], microLatch[ 10:7], microLatch[ 12:11]};
-
-	// Group 0 exception.
-	// Separated block from regular NMA. Otherwise simulation might depend on order of assigments.
-	always_comb begin
-		if( A0Err) begin
-			if( a0Rst)					// Reset
-				nma = RSTP0_NMA;
-			else if( inGrp0Exc)			// Double fault
-				nma = HALT1_NMA;
-			else						// Bus or address error
-				nma = BSER1_NMA;
-		end
-		else
-			nma = uNma;
-	end
-
-	always_comb begin
-		// Format II (conditional) or I (direct branch)
-		if( microLatch[1])
-			uNma = { microLatch[ 14:13], c0c1, microLatch[ 10:7], microLatch[ 12:11]};		
-		else
-			case( microLatch[ 3:2])
-			0:   uNma = dbNma;   // DB
-			1:   uNma = A0Sel ? grp1Nma : a1;
-			2:   uNma = a2;
-			3:   uNma = a3;
-			endcase			
-	end
-
-	// Format II, conditional, NMA decoding
-	wire [1:0] enl = { Ird[6], prenEmpty};		// Updated on T3
-	
-	wire [1:0] ms0 = { Ird[8], alue01[0]};
-	wire [3:0] m01 = { au05z, Ird[8], alue01};
-	wire [1:0] nz1 = { psw[ NF], psw[ ZF]};
-	wire [1:0] nv  = { psw[ NF], psw[ VF]};
-	
-	logic ccTest;
-	wire [4:0] cbc = microLatch[ 6:2];			// CBC bits
-	
-	always_comb begin
-		unique case( cbc)
-		'h0:    c0c1 = {i11, i11};						// W/L offset EA, from IRC
-
-		'h1:    c0c1 = (au05z) ? 2'b01 : 2'b11;			// Updated on T3
-		'h11:   c0c1 = (au05z) ? 2'b00 : 2'b11;
-
-		'h02:   c0c1 = { 1'b0, ~psw[ CF]};				// C used in DIV
-		'h12:   c0c1 = { 1'b1, ~psw[ CF]};
-
-		'h03:   c0c1 = {psw[ ZF], psw[ ZF]};			// Z used in DIVU
-		
-		'h04:											// nz1, used in DIVS
-			case( nz1)
+
+    wire [UADDR_WIDTH-1:0] dbNma = { microLatch[ 14:13], microLatch[ 6:5], microLatch[ 10:7], microLatch[ 12:11]};
+
+    // Group 0 exception.
+    // Separated block from regular NMA. Otherwise simulation might depend on order of assigments.
+    always_comb begin
+        if (A0Err) begin
+            if (a0Rst)                  // Reset
+                nma = RSTP0_NMA[UADDR_WIDTH-1:0];
+            else if (inGrp0Exc)         // Double fault
+                nma = HALT1_NMA[UADDR_WIDTH-1:0];
+            else                        // Bus or address error
+                nma = BSER1_NMA[UADDR_WIDTH-1:0];
+        end
+        else
+            nma = uNma;
+    end
+
+    always_comb begin
+        // Format II (conditional) or I (direct branch)
+        if (microLatch[1])
+            uNma = { microLatch[ 14:13], c0c1, microLatch[ 10:7], microLatch[ 12:11]};
+        else
+            case (microLatch[ 3:2])
+            0:   uNma = dbNma;   // DB
+            1:   uNma = A0Sel ? grp1Nma : a1;
+            2:   uNma = a2;
+            3:   uNma = a3;
+            endcase
+    end
+
+    // Format II, conditional, NMA decoding
+    wire [1:0] enl = { Ird[6], prenEmpty};      // Updated on T3
+
+    wire [1:0] ms0 = { Ird[8], alue01[0]};
+    wire [3:0] m01 = { au05z, Ird[8], alue01};
+    wire [1:0] nz1 = { psw[ NF], psw[ ZF]};
+    wire [1:0] nv  = { psw[ NF], psw[ VF]};
+
+    logic ccTest;
+    wire [4:0] cbc = microLatch[ 6:2];          // CBC bits
+
+    always_comb begin
+        unique case (cbc)
+        'h0:    c0c1 = {i11, i11};                      // W/L offset EA, from IRC
+
+        'h1:    c0c1 = (au05z) ? 2'b01 : 2'b11;         // Updated on T3
+        'h11:   c0c1 = (au05z) ? 2'b00 : 2'b11;
+
+        'h02:   c0c1 = { 1'b0, ~psw[ CF]};              // C used in DIV
+        'h12:   c0c1 = { 1'b1, ~psw[ CF]};
+
+        'h03:   c0c1 = {psw[ ZF], psw[ ZF]};            // Z used in DIVU
+
+        'h04:                                           // nz1, used in DIVS
+            case (nz1)
                'b00:         c0c1 = 2'b10;
                'b10:         c0c1 = 2'b01;
                'b01,'b11:    c0c1 = 2'b11;
-            endcase		
-
-		'h05:   c0c1 = {psw[ NF], 1'b1};				// N used in CHK and DIV
-		'h15:   c0c1 = {1'b1, psw[ NF]};
-		
-		// nz2, used in DIVS (same combination as nz1)
-		'h06:   c0c1 = { ~nz1[1] & ~nz1[0], 1'b1};
-		
-		'h07:											// ms0 used in MUL
-		case( ms0)
-		 'b10, 'b00: c0c1 = 2'b11;
-		 'b01: c0c1 = 2'b01;
-		 'b11: c0c1 = 2'b10;
-		endcase		
-		
-		'h08:											// m01 used in MUL
-		case( m01)
-		'b0000,'b0001,'b0100,'b0111:  c0c1 = 2'b11;
-		'b0010,'b0011,'b0101:         c0c1 = 2'b01;
-		'b0110:                       c0c1 = 2'b10;
-		default:                      c0c1 = 2'b00;
-		endcase
-
-		// Conditional		
-		'h09:   c0c1 = (ccTest) ? 2'b11 : 2'b01;
-		'h19:   c0c1 = (ccTest) ? 2'b11 : 2'b10;
-		
-		// DCR bit 4 (high or low word)
-		'h0c:   c0c1 = dcr4 ? 2'b01: 2'b11;
-		'h1c:   c0c1 = dcr4 ? 2'b10: 2'b11;		
-		
-		// DBcc done
-		'h0a:   c0c1 = ze ? 2'b11 : 2'b00;
-		
-		// nv, used in CHK
-		'h0b:   c0c1 = (nv == 2'b00) ? 2'b00 : 2'b11;
-		
-		// V, used in trapv
-		'h0d:   c0c1 = { ~psw[ VF], ~psw[VF]};		
-		
-		// enl, combination of pren idle and word/long on IRD
-		'h0e,'h1e:
-			case( enl)
-			2'b00:	c0c1 = 'b10;
-			2'b10:	c0c1 = 'b11;
-			// 'hx1 result 00/01 depending on condition 0e/1e
-			2'b01,2'b11:
-					c0c1 = { 1'b0, microLatch[ 6]};
-			endcase
-			
-		default: 				c0c1 = 'X;
-		endcase
-	end
-	
-	// CCR conditional
-	always_comb begin
-		unique case( Ird[ 11:8])		
-		'h0: ccTest = 1'b1;						// T
-		'h1: ccTest = 1'b0;						// F
-		'h2: ccTest = ~psw[ CF] & ~psw[ ZF];	// HI
-		'h3: ccTest = psw[ CF] | psw[ZF];		// LS
-		'h4: ccTest = ~psw[ CF];				// CC (HS)
-		'h5: ccTest = psw[ CF];					// CS (LO)
-		'h6: ccTest = ~psw[ ZF];				// NE
-		'h7: ccTest = psw[ ZF];					// EQ
-		'h8: ccTest = ~psw[ VF];				// VC
-		'h9: ccTest = psw[ VF];					// VS
-		'ha: ccTest = ~psw[ NF];				// PL
-		'hb: ccTest = psw[ NF];					// MI
-		'hc: ccTest = (psw[ NF] & psw[ VF]) | (~psw[ NF] & ~psw[ VF]);				// GE
-		'hd: ccTest = (psw[ NF] & ~psw[ VF]) | (~psw[ NF] & psw[ VF]);				// LT
-		'he: ccTest = (psw[ NF] & psw[ VF] & ~psw[ ZF]) |
-				 (~psw[ NF] & ~psw[ VF] & ~psw[ ZF]);								// GT
-		'hf: ccTest = psw[ ZF] | (psw[ NF] & ~psw[VF]) | (~psw[ NF] & psw[VF]);		// LE
-		endcase
-	end
-	
-	// Exception logic
-	logic rTrace, rInterrupt;
-	logic rIllegal, rPriv, rLineA, rLineF;
-	logic rExcRst, rExcAdrErr, rExcBusErr;
-	logic rSpurious, rAutovec;
-	wire grp1LatchEn, grp0LatchEn;
-			
-	// Originally control signals latched on T4. Then exception latches updated on T3
-	assign grp1LatchEn = microLatch[0] & (microLatch[1] | !microLatch[4]);
-	assign grp0LatchEn = microLatch[4] & !microLatch[1];
-	
-	assign inGrp0Exc = rExcRst | rExcBusErr | rExcAdrErr;
-	
-	always_ff @( posedge Clks.clk) begin
-		if( grp0LatchEn & enT3) begin
-			rExcRst <= excRst;
-			rExcBusErr <= BerrA;
-			rExcAdrErr <= busAddrErr;
-			rSpurious <= Spuria;
-			rAutovec <= Avia;
-		end
-		
-		// Update group 1 exception latches
-		// Inputs from IR decoder updated on T1 as soon as IR loaded
-		// Trace pending updated on T3 at the start of the instruction
-		// Interrupt pending on T2
-		if( grp1LatchEn & enT3) begin
-			rTrace <= Tpend;
-			rInterrupt <= intPend;
-			rIllegal <= isIllegal & ~isLineA & ~isLineF;
-			rLineA <= isLineA;
-			rLineF <= isLineF;
-			rPriv <= isPriv & !psw[ SF];
-		end
-	end
-
-	// exception priority
-	always_comb begin
-		grp1Nma = TRAC1_NMA;
-		if( rExcRst)
-			tvn = '0;							// Might need to change that to signal in exception
-		else if( rExcBusErr | rExcAdrErr)
-			tvn = { 1'b1, rExcAdrErr};
-			
-		// Seudo group 0 exceptions. Just for updating TVN
-		else if( rSpurious | rAutovec)
-			tvn = rSpurious ? TVN_SPURIOUS : TVN_AUTOVEC;
-		
-		else if( rTrace)
-			tvn = 9;
-		else if( rInterrupt) begin
-			tvn = TVN_INTERRUPT;
-			grp1Nma = ITLX1_NMA;
-		end
-		else begin
-			unique case( 1'b1)					// Can't happen more than one of these
-			rIllegal:			tvn = 4;
-			rPriv:				tvn = 8;
-			rLineA:				tvn = 10;
-			rLineF:				tvn = 11;
-			default:			tvn = 1;		// Signal no group 0/1 exception
-			endcase
-		end
-	end
-	
-	assign A0Sel = rIllegal | rLineF | rLineA | rPriv | rTrace | rInterrupt;
-	
-	always_ff @( posedge Clks.clk) begin
-		if( Clks.extReset)
-			a0Rst <= 1'b1;
-		else if( enT3)
-			a0Rst <= 1'b0;
-	end
-	
+            endcase
+
+        'h05:   c0c1 = {psw[ NF], 1'b1};                // N used in CHK and DIV
+        'h15:   c0c1 = {1'b1, psw[ NF]};
+
+        // nz2, used in DIVS (same combination as nz1)
+        'h06:   c0c1 = { ~nz1[1] & ~nz1[0], 1'b1};
+
+        'h07:                                           // ms0 used in MUL
+        case (ms0)
+         'b10, 'b00: c0c1 = 2'b11;
+         'b01: c0c1 = 2'b01;
+         'b11: c0c1 = 2'b10;
+        endcase
+
+        'h08:                                           // m01 used in MUL
+        case (m01)
+        'b0000,'b0001,'b0100,'b0111:  c0c1 = 2'b11;
+        'b0010,'b0011,'b0101:         c0c1 = 2'b01;
+        'b0110:                       c0c1 = 2'b10;
+        default:                      c0c1 = 2'b00;
+        endcase
+
+        // Conditional
+        'h09:   c0c1 = (ccTest) ? 2'b11 : 2'b01;
+        'h19:   c0c1 = (ccTest) ? 2'b11 : 2'b10;
+
+        // DCR bit 4 (high or low word)
+        'h0c:   c0c1 = dcr4 ? 2'b01: 2'b11;
+        'h1c:   c0c1 = dcr4 ? 2'b10: 2'b11;
+
+        // DBcc done
+        'h0a:   c0c1 = ze ? 2'b11 : 2'b00;
+
+        // nv, used in CHK
+        'h0b:   c0c1 = (nv == 2'b00) ? 2'b00 : 2'b11;
+
+        // V, used in trapv
+        'h0d:   c0c1 = { ~psw[ VF], ~psw[VF]};
+
+        // enl, combination of pren idle and word/long on IRD
+        'h0e,'h1e:
+            case (enl)
+            2'b00:  c0c1 = 'b10;
+            2'b10:  c0c1 = 'b11;
+            // 'hx1 result 00/01 depending on condition 0e/1e
+            2'b01,2'b11:
+                    c0c1 = { 1'b0, microLatch[ 6]};
+            endcase
+
+        default:                c0c1 = 'X;
+        endcase
+    end
+
+    // CCR conditional
+    always_comb begin
+        unique case (Ird[ 11:8])
+        'h0: ccTest = 1'b1;                     // T
+        'h1: ccTest = 1'b0;                     // F
+        'h2: ccTest = ~psw[ CF] & ~psw[ ZF];    // HI
+        'h3: ccTest = psw[ CF] | psw[ZF];       // LS
+        'h4: ccTest = ~psw[ CF];                // CC (HS)
+        'h5: ccTest = psw[ CF];                 // CS (LO)
+        'h6: ccTest = ~psw[ ZF];                // NE
+        'h7: ccTest = psw[ ZF];                 // EQ
+        'h8: ccTest = ~psw[ VF];                // VC
+        'h9: ccTest = psw[ VF];                 // VS
+        'ha: ccTest = ~psw[ NF];                // PL
+        'hb: ccTest = psw[ NF];                 // MI
+        'hc: ccTest = (psw[ NF] & psw[ VF]) | (~psw[ NF] & ~psw[ VF]);              // GE
+        'hd: ccTest = (psw[ NF] & ~psw[ VF]) | (~psw[ NF] & psw[ VF]);              // LT
+        'he: ccTest = (psw[ NF] & psw[ VF] & ~psw[ ZF]) |
+                 (~psw[ NF] & ~psw[ VF] & ~psw[ ZF]);                               // GT
+        'hf: ccTest = psw[ ZF] | (psw[ NF] & ~psw[VF]) | (~psw[ NF] & psw[VF]);     // LE
+        endcase
+    end
+
+    // Exception logic
+    logic rTrace, rInterrupt;
+    logic rIllegal, rPriv, rLineA, rLineF;
+    logic rExcRst, rExcAdrErr, rExcBusErr;
+    logic rSpurious, rAutovec;
+    wire grp1LatchEn, grp0LatchEn;
+
+    // Originally control signals latched on T4. Then exception latches updated on T3
+    assign grp1LatchEn = microLatch[0] & (microLatch[1] | !microLatch[4]);
+    assign grp0LatchEn = microLatch[4] & !microLatch[1];
+
+    assign inGrp0Exc = rExcRst | rExcBusErr | rExcAdrErr;
+
+    always_ff @( posedge Clks.clk) begin
+        if (grp0LatchEn & enT3) begin
+            rExcRst <= excRst;
+            rExcBusErr <= BerrA;
+            rExcAdrErr <= busAddrErr;
+            rSpurious <= Spuria;
+            rAutovec <= Avia;
+        end
+
+        // Update group 1 exception latches
+        // Inputs from IR decoder updated on T1 as soon as IR loaded
+        // Trace pending updated on T3 at the start of the instruction
+        // Interrupt pending on T2
+        if (grp1LatchEn & enT3) begin
+            rTrace <= Tpend;
+            rInterrupt <= intPend;
+            rIllegal <= isIllegal & ~isLineA & ~isLineF;
+            rLineA <= isLineA;
+            rLineF <= isLineF;
+            rPriv <= isPriv & !psw[ SF];
+        end
+    end
+
+    // exception priority
+    always_comb begin
+        grp1Nma = TRAC1_NMA[UADDR_WIDTH-1:0];
+        if (rExcRst)
+            tvn = 4'h0;                         // Might need to change that to signal in exception
+        else if (rExcBusErr | rExcAdrErr)
+            tvn = { 3'b001, rExcAdrErr};
+
+        // Seudo group 0 exceptions. Just for updating TVN
+        else if (rSpurious | rAutovec)
+            tvn = rSpurious ? TVN_SPURIOUS : TVN_AUTOVEC;
+
+        else if (rTrace)
+            tvn = 4'h9;
+        else if (rInterrupt) begin
+            tvn = TVN_INTERRUPT;
+            grp1Nma = ITLX1_NMA[UADDR_WIDTH-1:0];
+        end
+        else begin
+            unique case (1'b1)                  // Can't happen more than one of these
+            rIllegal:           tvn = 4'h4;
+            rPriv:              tvn = 4'h8;
+            rLineA:             tvn = 4'hA;
+            rLineF:             tvn = 4'hB;
+            default:            tvn = 4'h1;     // Signal no group 0/1 exception
+            endcase
+        end
+    end
+
+    assign A0Sel = rIllegal | rLineF | rLineA | rPriv | rTrace | rInterrupt;
+
+    always_ff @( posedge Clks.clk) begin
+        if (Clks.extReset)
+            a0Rst <= 1'b1;
+        else if (enT3)
+            a0Rst <= 1'b0;
+    end
+
 endmodule
 
 
@@ -2158,286 +2087,293 @@ endmodule
 // DMA/BUS Arbitration
 //
 
-module busArbiter( input s_clks Clks,
-		input BRi, BgackI, Halti, bgBlock,
-		output busAvail,
-		output logic BGn);
-		
-	enum int unsigned { DRESET = 0, DIDLE, D1, D_BR, D_BA, D_BRA, D3, D2} dmaPhase, next;
-
-	always_comb begin
-		case(dmaPhase)
-		DRESET:	next = DIDLE;
-		DIDLE:	begin
-				if( bgBlock)
-					next = DIDLE;
-				else if( ~BgackI)
-					next = D_BA;
-				else if( ~BRi)
-					next = D1;
-				else
-					next = DIDLE;
-				end
-
-		D_BA:	begin							// Loop while only BGACK asserted, BG negated here
-				if( ~BRi & !bgBlock)
-					next = D3;
-				else if( ~BgackI & !bgBlock)
-					next = D_BA;
-				else
-					next = DIDLE;
-				end
-				
-		D1:		next = D_BR;							// Loop while only BR asserted
-		D_BR:	next = ~BRi & BgackI ? D_BR : D_BA;		// No direct path to IDLE !
-		
-		D3:		next = D_BRA;
-		D_BRA:	begin						// Loop while both BR and BGACK asserted
-				case( {BgackI, BRi} )
-				2'b11:	next = DIDLE;		// Both deasserted
-				2'b10:	next = D_BR;		// BR asserted only
-				2'b01:	next = D2;			// BGACK asserted only
-				2'b00:	next = D_BRA;		// Stay here while both asserted
-				endcase
-				end
-				
-		// Might loop here if both deasserted, should normally don't arrive here anyway?
-		// D2:		next = (BgackI & BRi) | bgBlock ? D2: D_BA;
-
-		D2:		next = D_BA;
-		
-		default:	next = DIDLE;			// Should not reach here normally		
-		endcase
-	end
-		
-	logic granting;
-	always_comb begin
-		unique case( next)
-		D1, D3, D_BR, D_BRA:	granting = 1'b1;
-		default:				granting = 1'b0;
-		endcase
-	end
-	
-	reg rGranted;
-	assign busAvail = Halti & BRi & BgackI & ~rGranted;
-		
-	always_ff @( posedge Clks.clk) begin
-		if( Clks.extReset) begin
-			dmaPhase <= DRESET;
-			rGranted <= 1'b0;
-		end
-		else if( Clks.enPhi2) begin
-			dmaPhase <= next;
-			// Internal signal changed on PHI2
-			rGranted <= granting;
-		end
-
-		// External Output changed on PHI1
-		if( Clks.extReset)
-			BGn <= 1'b1;
-		else if( Clks.enPhi1)
-			BGn <= ~rGranted;
-		
-	end
-			
+module busArbiter
+(
+    input s_clks Clks,
+    input BRi, BgackI, Halti, bgBlock,
+    output busAvail,
+    output logic BGn
+);
+
+    enum int unsigned { DRESET = 0, DIDLE, D1, D_BR, D_BA, D_BRA, D3, D2} dmaPhase, next;
+
+    always_comb begin
+        case(dmaPhase)
+        DRESET: next = DIDLE;
+        DIDLE:  begin
+                if (bgBlock)
+                    next = DIDLE;
+                else if (~BgackI)
+                    next = D_BA;
+                else if (~BRi)
+                    next = D1;
+                else
+                    next = DIDLE;
+                end
+
+        D_BA:   begin                           // Loop while only BGACK asserted, BG negated here
+                if (~BRi & !bgBlock)
+                    next = D3;
+                else if (~BgackI & !bgBlock)
+                    next = D_BA;
+                else
+                    next = DIDLE;
+                end
+
+        D1:     next = D_BR;                            // Loop while only BR asserted
+        D_BR:   next = ~BRi & BgackI ? D_BR : D_BA;     // No direct path to IDLE !
+
+        D3:     next = D_BRA;
+        D_BRA:  begin                       // Loop while both BR and BGACK asserted
+                case ({BgackI, BRi} )
+                2'b11:  next = DIDLE;       // Both deasserted
+                2'b10:  next = D_BR;        // BR asserted only
+                2'b01:  next = D2;          // BGACK asserted only
+                2'b00:  next = D_BRA;       // Stay here while both asserted
+                endcase
+                end
+
+        // Might loop here if both deasserted, should normally don't arrive here anyway?
+        // D2:      next = (BgackI & BRi) | bgBlock ? D2: D_BA;
+
+        D2:     next = D_BA;
+
+        default:    next = DIDLE;           // Should not reach here normally
+        endcase
+    end
+
+    logic granting;
+    always_comb begin
+        unique case (next)
+        D1, D3, D_BR, D_BRA:    granting = 1'b1;
+        default:                granting = 1'b0;
+        endcase
+    end
+
+    reg rGranted;
+    assign busAvail = Halti & BRi & BgackI & ~rGranted;
+
+    always_ff @( posedge Clks.clk) begin
+
+        if (Clks.extReset) begin
+            dmaPhase <= DRESET;
+            rGranted <= 1'b0;
+        end
+        else if (Clks.enPhi2) begin
+            dmaPhase <= next;
+            // Internal signal changed on PHI2
+            rGranted <= granting;
+        end
+
+        // External Output changed on PHI1
+        if (Clks.extReset)
+            BGn <= 1'b1;
+        else if (Clks.enPhi1)
+            BGn <= ~rGranted;
+
+    end
+
 endmodule
 
 module busControl( input s_clks Clks, input enT1, input enT4,
-		input permStart, permStop, iStop,
-		input aob0,
-		input isWrite, isByte, isRmc,
-		input busAvail,
-		output bgBlock,
-		output busAddrErr,
-		output waitBusCycle,
-		output busStarting,			// Asserted during S0
-		output logic addrOe,		// Asserted from S1 to the end, whole bus cycle except S0
-		output bciWrite,			// Used for SSW on bus/addr error
-		
-		input rDtack, BeDebounced, Vpai,
-		output ASn, output LDSn, output UDSn, eRWn);
-
-	reg rAS, rLDS, rUDS, rRWn;
-	assign ASn = rAS;
-	assign LDSn = rLDS;
-	assign UDSn = rUDS;
-	assign eRWn = rRWn;
-
-	reg dataOe;
-		
-	reg bcPend;
-	reg isWriteReg, bciByte, isRmcReg, wendReg;
-	assign bciWrite = isWriteReg;
-	reg addrOeDelay;
-	reg isByteT4;
-
-	wire canStart, busEnd;
-	wire bcComplete, bcReset;
-	
-	wire isRcmReset = bcComplete & bcReset & isRmcReg;
-	
-	assign busAddrErr = aob0 & ~bciByte;
-	
-	// Bus retry not really supported.
-	// It's BERR and HALT and not address error, and not read-modify cycle.
-	wire busRetry = ~busAddrErr & 1'b0;
-	
-	enum int unsigned { SRESET = 0, SIDLE, S0, S2, S4, S6, SRMC_RES} busPhase, next;
-
-	always_ff @( posedge Clks.clk) begin
-		if( Clks.extReset)
-			busPhase <= SRESET;
-		else if( Clks.enPhi1)
-			busPhase <= next;
-	end
-	
-	always_comb begin
-		case( busPhase)
-		SRESET:		next = SIDLE;
-		SRMC_RES:	next = SIDLE;			// Single cycle special state when read phase of RMC reset
-		S0:			next = S2;
-		S2:			next = S4;
-		S4:			next = busEnd ? S6 : S4;
-		S6:			next = isRcmReset ? SRMC_RES : (canStart ? S0 : SIDLE);
-		SIDLE:		next = canStart ? S0 : SIDLE;
-		default:	next = SIDLE;
-		endcase
-	end	
-	
-	// Idle phase of RMC bus cycle. Might be better to just add a new state
-	wire rmcIdle = (busPhase == SIDLE) & ~ASn & isRmcReg;
-		
-	assign canStart = (busAvail | rmcIdle) & (bcPend | permStart) & !busRetry & !bcReset;
-		
-	wire busEnding = (next == SIDLE) | (next == S0);
-	
-	assign busStarting = (busPhase == S0);
-		
-	// term signal (DTACK, BERR, VPA, adress error)
-	assign busEnd = ~rDtack | iStop;
-				
-	// bcComplete asserted on raising edge of S6 (together with SNC).
-	assign bcComplete = (busPhase == S6);
-	
-	// Clear bus info latch on completion (regular or aborted) and no bus retry (and not PHI1).
-	// bciClear asserted half clock later on PHI2, and bci latches cleared async concurrently
-	wire bciClear = bcComplete & ~busRetry;
-	
-	// Reset on reset or (berr & berrDelay & (not halt or rmc) & not 6800 & in bus cycle) (and not PHI1)
-	assign bcReset = Clks.extReset | (addrOeDelay & BeDebounced & Vpai);
-		
-	// Enable uclock only on S6 (S8 on Bus Error) or not bciPermStop
-	assign waitBusCycle = wendReg & !bcComplete;
-	
-	// Block Bus Grant when starting new bus cycle. But No need if AS already asserted (read phase of RMC)
-	// Except that when that RMC phase aborted on bus error, it's asserted one cycle later!
-	assign bgBlock = ((busPhase == S0) & ASn) | (busPhase == SRMC_RES);
-	
-	always_ff @( posedge Clks.clk) begin
-		if( Clks.extReset) begin
-			addrOe <= 1'b0;
-		end
-		else if( Clks.enPhi2 & ( busPhase == S0))			// From S1, whole bus cycle except S0
-				addrOe <= 1'b1;
-		else if( Clks.enPhi1 & (busPhase == SRMC_RES))
-			addrOe <= 1'b0;
-		else if( Clks.enPhi1 & ~isRmcReg & busEnding)
-			addrOe <= 1'b0;
-			
-		if( Clks.enPhi1)
-			addrOeDelay <= addrOe;
-		
-		if( Clks.extReset) begin
-			rAS <= 1'b1;
-			rUDS <= 1'b1;
-			rLDS <= 1'b1;
-			rRWn <= 1'b1;
-			dataOe <= '0;
-		end
-		else begin
-
-			if( Clks.enPhi2 & isWriteReg & (busPhase == S2))
-				dataOe <= 1'b1;
-			else if( Clks.enPhi1 & (busEnding | (busPhase == SIDLE)) )
-				dataOe <= 1'b0;
-						
-			if( Clks.enPhi1 & busEnding)
-				rRWn <= 1'b1;
-			else if( Clks.enPhi1 & isWriteReg) begin
-				// Unlike LDS/UDS Asserted even in address error
-				if( (busPhase == S0) & isWriteReg)
-					rRWn <= 1'b0;
-			end
-
-			// AS. Actually follows addrOe half cycle later!
-			if( Clks.enPhi1 & (busPhase == S0))
-				rAS <= 1'b0;
-			else if( Clks.enPhi2 & (busPhase == SRMC_RES))		// Bus error on read phase of RMC. Deasserted one cycle later
-				rAS <= 1'b1;			
-			else if( Clks.enPhi2 & bcComplete & ~SRMC_RES)
-				if( ~isRmcReg)									// Keep AS asserted on the IDLE phase of RMC
-					rAS <= 1'b1;
-			
-			if( Clks.enPhi1 & (busPhase == S0)) begin
-				if( ~isWriteReg & !busAddrErr) begin
-					rUDS <= ~(~bciByte | ~aob0);
-					rLDS <= ~(~bciByte | aob0);
-				end
-			end
-			else if( Clks.enPhi1 & isWriteReg & (busPhase == S2) & !busAddrErr) begin
-					rUDS <= ~(~bciByte | ~aob0);
-					rLDS <= ~(~bciByte | aob0);
-			end		
-			else if( Clks.enPhi2 & bcComplete) begin
-				rUDS <= 1'b1;
-				rLDS <= 1'b1;
-			end
-			
-		end
-		
-	end
-	
-	// Bus cycle info latch. Needed because uinstr might change if the bus is busy and we must wait.
-	// Note that urom advances even on wait states. It waits *after* updating urom and nanorom latches.
-	// Even without wait states, ublocks of type ir (init reading) will not wait for bus completion.
-	// Originally latched on (permStart AND T1).
-	
-	// Bus cycle info latch: isRead, isByte, read-modify-cycle, and permStart (bus cycle pending). Some previously latched on T4?
-	// permStop also latched, but unconditionally on T1
-	
-	// Might make more sense to register this outside this module
-	always_ff @( posedge Clks.clk) begin
-		if( enT4) begin
-			isByteT4 <= isByte;
-		end
-	end
-	
-	// Bus Cycle Info Latch
-	always_ff @( posedge Clks.clk) begin
-		if( Clks.pwrUp) begin
-			bcPend <= 1'b0;
-			wendReg <= 1'b0;	
-			isWriteReg <= 1'b0;
-			bciByte <= 1'b0;
-			isRmcReg <= 1'b0;		
-		end
-		
-		else if( Clks.enPhi2 & (bciClear | bcReset)) begin
-			bcPend <= 1'b0;
-			wendReg <= 1'b0;
-		end
-		else begin
-			if( enT1 & permStart) begin
-				isWriteReg <= isWrite;
-				bciByte <= isByteT4;
-				isRmcReg <= isRmc & ~isWrite;	// We need special case the end of the read phase only.
-				bcPend <= 1'b1;
-			end
-			if( enT1)
-				wendReg <= permStop;
-		end
-	end
-			
+        input permStart, permStop, iStop,
+        input aob0,
+        input isWrite, isByte, isRmc,
+        input busAvail,
+        output bgBlock,
+        output busAddrErr,
+        output waitBusCycle,
+        output busStarting,         // Asserted during S0
+        output logic addrOe,        // Asserted from S1 to the end, whole bus cycle except S0
+        output bciWrite,            // Used for SSW on bus/addr error
+
+        input rDtack, BeDebounced, Vpai,
+        output ASn, output LDSn, output UDSn, eRWn);
+
+    reg rAS, rLDS, rUDS, rRWn;
+    assign ASn = rAS;
+    assign LDSn = rLDS;
+    assign UDSn = rUDS;
+    assign eRWn = rRWn;
+
+    reg dataOe;
+
+    reg bcPend;
+    reg isWriteReg, bciByte, isRmcReg, wendReg;
+    assign bciWrite = isWriteReg;
+    reg addrOeDelay;
+    reg isByteT4;
+
+    wire canStart, busEnd;
+    wire bcComplete, bcReset;
+
+    wire isRcmReset = bcComplete & bcReset & isRmcReg;
+
+    assign busAddrErr = aob0 & ~bciByte;
+
+    // Bus retry not really supported.
+    // It's BERR and HALT and not address error, and not read-modify cycle.
+    wire busRetry = ~busAddrErr & 1'b0;
+
+    enum int unsigned { SRESET = 0, SIDLE, S0, S2, S4, S6, SRMC_RES} busPhase, next;
+
+    always_ff @( posedge Clks.clk) begin
+        if (Clks.extReset)
+            busPhase <= SRESET;
+        else if (Clks.enPhi1)
+            busPhase <= next;
+    end
+
+    always_comb begin
+        case (busPhase)
+            SRESET:   next = SIDLE;
+            SRMC_RES: next = SIDLE;           // Single cycle special state when read phase of RMC reset
+            S0:       next = S2;
+            S2:       next = S4;
+            S4:       next = busEnd ? S6 : S4;
+            S6:       next = isRcmReset ? SRMC_RES : (canStart ? S0 : SIDLE);
+            SIDLE:    next = canStart ? S0 : SIDLE;
+            default:  next = SIDLE;
+        endcase
+    end
+
+    // Idle phase of RMC bus cycle. Might be better to just add a new state
+    wire rmcIdle = (busPhase == SIDLE) & ~ASn & isRmcReg;
+
+    assign canStart = (busAvail | rmcIdle) & (bcPend | permStart) & !busRetry & !bcReset;
+
+    wire busEnding = (next == SIDLE) | (next == S0);
+
+    assign busStarting = (busPhase == S0);
+
+    // term signal (DTACK, BERR, VPA, adress error)
+    assign busEnd = ~rDtack | iStop;
+
+    // bcComplete asserted on raising edge of S6 (together with SNC).
+    assign bcComplete = (busPhase == S6);
+
+    // Clear bus info latch on completion (regular or aborted) and no bus retry (and not PHI1).
+    // bciClear asserted half clock later on PHI2, and bci latches cleared async concurrently
+    wire bciClear = bcComplete & ~busRetry;
+
+    // Reset on reset or (berr & berrDelay & (not halt or rmc) & not 6800 & in bus cycle) (and not PHI1)
+    assign bcReset = Clks.extReset | (addrOeDelay & BeDebounced & Vpai);
+
+    // Enable uclock only on S6 (S8 on Bus Error) or not bciPermStop
+    assign waitBusCycle = wendReg & !bcComplete;
+
+    // Block Bus Grant when starting new bus cycle. But No need if AS already asserted (read phase of RMC)
+    // Except that when that RMC phase aborted on bus error, it's asserted one cycle later!
+    assign bgBlock = ((busPhase == S0) & ASn) | (busPhase == SRMC_RES);
+
+    always_ff @( posedge Clks.clk) begin
+        if (Clks.extReset) begin
+            addrOe <= 1'b0;
+        end
+        // S0 (enPHi2, S0) -> S1 (enPhi1, S0)
+        else if (Clks.enPhi2 & ( busPhase == S0))           // From S1, whole bus cycle except S0
+            addrOe <= 1'b1;
+        else if (Clks.enPhi1 & (busPhase == SRMC_RES))
+            addrOe <= 1'b0;
+        else if (Clks.enPhi1 & ~isRmcReg & busEnding)
+            addrOe <= 1'b0;
+
+        if (Clks.enPhi1)
+            addrOeDelay <= addrOe;
+
+        if (Clks.extReset) begin
+            rAS    <= 1'b1;
+            rUDS   <= 1'b1;
+            rLDS   <= 1'b1;
+            rRWn   <= 1'b1;
+            dataOe <= 1'b0;
+        end
+        else begin
+
+            if (Clks.enPhi2 & isWriteReg & (busPhase == S2))
+                dataOe <= 1'b1;
+            else if (Clks.enPhi1 & (busEnding | (busPhase == SIDLE)) )
+                dataOe <= 1'b0;
+
+            if (Clks.enPhi1 & busEnding)
+                rRWn <= 1'b1;
+            else if (Clks.enPhi1 & isWriteReg) begin
+                // Unlike LDS/UDS Asserted even in address error
+                if ((busPhase == S0) & isWriteReg)
+                    rRWn <= 1'b0;
+            end
+
+            // AS. Actually follows addrOe half cycle later!
+            // S1 (enPhi1, S0) -> S2 (enPHi2, S2)
+            if (Clks.enPhi1 & (busPhase == S0))
+                rAS <= 1'b0;
+            else if (Clks.enPhi2 & (busPhase == SRMC_RES))      // Bus error on read phase of RMC. Deasserted one cycle later
+                rAS <= 1'b1;
+            //else if (Clks.enPhi2 & bcComplete & ~SRMC_RES) ???
+            else if (Clks.enPhi2 & bcComplete)
+                if (~isRmcReg)                                  // Keep AS asserted on the IDLE phase of RMC
+                    rAS <= 1'b1;
+
+            if (Clks.enPhi1 & (busPhase == S0)) begin
+                if (~isWriteReg & !busAddrErr) begin
+                    rUDS <= ~(~bciByte | ~aob0);
+                    rLDS <= ~(~bciByte |  aob0);
+                end
+            end
+            else if (Clks.enPhi1 & isWriteReg & (busPhase == S2) & !busAddrErr) begin
+                rUDS <= ~(~bciByte | ~aob0);
+                rLDS <= ~(~bciByte |  aob0);
+            end
+            else if (Clks.enPhi2 & bcComplete) begin
+                rUDS <= 1'b1;
+                rLDS <= 1'b1;
+            end
+        end
+    end
+
+    // Bus cycle info latch. Needed because uinstr might change if the bus is busy and we must wait.
+    // Note that urom advances even on wait states. It waits *after* updating urom and nanorom latches.
+    // Even without wait states, ublocks of type ir (init reading) will not wait for bus completion.
+    // Originally latched on (permStart AND T1).
+
+    // Bus cycle info latch: isRead, isByte, read-modify-cycle, and permStart (bus cycle pending). Some previously latched on T4?
+    // permStop also latched, but unconditionally on T1
+
+    // Might make more sense to register this outside this module
+    always_ff @( posedge Clks.clk) begin
+
+        if (enT4) begin
+            isByteT4 <= isByte;
+        end
+    end
+
+    // Bus Cycle Info Latch
+    always_ff @( posedge Clks.clk) begin
+
+        if (Clks.pwrUp) begin
+            bcPend     <= 1'b0;
+            wendReg    <= 1'b0;
+            isWriteReg <= 1'b0;
+            bciByte    <= 1'b0;
+            isRmcReg   <= 1'b0;
+        end
+        else if (Clks.enPhi2 & (bciClear | bcReset)) begin
+            bcPend     <= 1'b0;
+            wendReg    <= 1'b0;
+        end
+        else begin
+            if (enT1 & permStart) begin
+                isWriteReg <= isWrite;
+                bciByte    <= isByteT4;
+                isRmcReg   <= isRmc & ~isWrite;   // We need special case the end of the read phase only.
+                bcPend     <= 1'b1;
+            end
+            if (enT1) begin
+                wendReg    <= permStop;
+            end
+        end
+    end
+
 endmodule
 
 //
@@ -2448,40 +2384,58 @@ endmodule
 // Might be more efficient to use vendor specific features such as clock enable.
 //
 
-module uRom( input clk, input [UADDR_WIDTH-1:0] microAddr, output logic [UROM_WIDTH-1:0] microOutput);
-	reg [UROM_WIDTH-1:0] uRam[ UROM_DEPTH];		
-	initial begin
-		$readmemb("microrom.mem", uRam);
-	end
-	
-	always_ff @( posedge clk) 
-		microOutput <= uRam[ microAddr];
+module uRom
+(
+    input                          clk,
+    input        [UADDR_WIDTH-1:0] microAddr,
+    output logic  [UROM_WIDTH-1:0] microOutput
+);
+
+    reg [UROM_WIDTH-1:0] uRam[0:UROM_DEPTH-1];
+
+    initial begin
+        $readmemb("microrom.mem", uRam);
+    end
+
+    always_ff @(posedge clk) begin
+        microOutput <= uRam[microAddr];
+    end
+
 endmodule
 
 
-module nanoRom( input clk, input [NADDR_WIDTH-1:0] nanoAddr, output logic [NANO_WIDTH-1:0] nanoOutput);
-	reg [NANO_WIDTH-1:0] nRam[ NANO_DEPTH];		
-	initial begin
-		$readmemb("nanorom.mem", nRam);
-	end
-	
-	always_ff @( posedge clk) 
-		nanoOutput <= nRam[ nanoAddr];
+module nanoRom
+(
+    input                         clk,
+    input       [NADDR_WIDTH-1:0] nanoAddr,
+    output logic [NANO_WIDTH-1:0] nanoOutput
+);
+
+    reg [NANO_WIDTH-1:0] nRam[0:NANO_DEPTH-1];
+
+    initial begin
+        $readmemb("nanorom.mem", nRam);
+    end
+
+    always_ff @(posedge clk) begin
+        nanoOutput <= nRam[nanoAddr];
+    end
+
 endmodule
 
 // Translate uaddr to nanoaddr
 module microToNanoAddr(
-	input [UADDR_WIDTH-1:0] uAddr,
-	output [NADDR_WIDTH-1:0] orgAddr);
+    input [UADDR_WIDTH-1:0] uAddr,
+    output [NADDR_WIDTH-1:0] orgAddr);
 
-	wire [UADDR_WIDTH-1:2] baseAddr = uAddr[UADDR_WIDTH-1:2];
-	logic [NADDR_WIDTH-1:2] orgBase;
-	assign orgAddr = { orgBase, uAddr[1:0]};
+    wire [UADDR_WIDTH-1:2] baseAddr = uAddr[UADDR_WIDTH-1:2];
+    logic [NADDR_WIDTH-1:2] orgBase;
+    assign orgAddr = { orgBase, uAddr[1:0]};
 
-	always @( baseAddr)
-	begin
-		// nano ROM (136 addresses)
-		case( baseAddr)
+    always @( baseAddr)
+    begin
+        // nano ROM (136 addresses)
+        case (baseAddr)
 
 'h00: orgBase = 7'h0 ;
 'h01: orgBase = 7'h1 ;
@@ -2620,10 +2574,10 @@ module microToNanoAddr(
 'hFA: orgBase = 7'h53 ;
 'hFB: orgBase = 7'h53 ;
 
-			default:
-				orgBase = 'X;
-		endcase
-	end
+            default:
+                orgBase = 'X;
+        endcase
+    end
 
 endmodule
 
@@ -2632,56 +2586,56 @@ endmodule
 //
 
 `ifdef FX68K_TEST
-module fx68kTop( input clk32, 
-	input extReset,
-	// input pwrUp,
-
-	input DTACKn, input VPAn,
-	input BERRn,
-	input BRn, BGACKn,
-	input IPL0n, input IPL1n, input IPL2n,
-	input [15:0] iEdb,
-	
-	output [15:0] oEdb,
-	output eRWn, output ASn, output LDSn, output UDSn,
-	output logic E, output VMAn,	
-	output FC0, output FC1, output FC2,
-	output BGn,
-	output oRESETn, output oHALTEDn,
-	output [23:1] eab
-	);
-
-	// Clock must be at least twice the desired frequency. A 32 MHz clock means a maximum 16 MHz effective frequency.
-	// In this example we divide the clock by 4. Resulting on an effective processor running at 8 MHz.
-	
-	reg [1:0] clkDivisor = '0;
-	always @( posedge clk32) begin
-		clkDivisor <= clkDivisor + 1'b1;
-	end
-		
-	/*
-	These two signals must be a single cycle pulse. They don't need to be registered.
-	Same signal can't be asserted twice in a row. Other than that there are no restrictions.
-	There can be any number of cycles, or none, even variable non constant cycles, between each pulse.
-	*/
-	
-	wire enPhi1 = (clkDivisor == 2'b11);
-	wire enPhi2 = (clkDivisor == 2'b01);
-		
-		
-	fx68k fx68k( .clk( clk32),
-		.extReset, .pwrUp( extReset), .enPhi1, .enPhi2,
-	
-		.DTACKn, .VPAn, .BERRn, .BRn, .BGACKn,
-		.IPL0n, .IPL1n, .IPL2n,
-		.iEdb,
-		
-		.oEdb,
-		.eRWn, .ASn, .LDSn, .UDSn,
-		.E, .VMAn,	
-		.FC0, .FC1, .FC2,
-		.BGn,
-		.oRESETn, .oHALTEDn, .eab);
+module fx68kTop( input clk32,
+    input extReset,
+    // input pwrUp,
+
+    input DTACKn, input VPAn,
+    input BERRn,
+    input BRn, BGACKn,
+    input IPL0n, input IPL1n, input IPL2n,
+    input [15:0] iEdb,
+
+    output [15:0] oEdb,
+    output eRWn, output ASn, output LDSn, output UDSn,
+    output logic E, output VMAn,
+    output FC0, output FC1, output FC2,
+    output BGn,
+    output oRESETn, output oHALTEDn,
+    output [23:1] eab
+    );
+
+    // Clock must be at least twice the desired frequency. A 32 MHz clock means a maximum 16 MHz effective frequency.
+    // In this example we divide the clock by 4. Resulting on an effective processor running at 8 MHz.
+
+    reg [1:0] clkDivisor = '0;
+    always @( posedge clk32) begin
+        clkDivisor <= clkDivisor + 1'b1;
+    end
+
+    /*
+    These two signals must be a single cycle pulse. They don't need to be registered.
+    Same signal can't be asserted twice in a row. Other than that there are no restrictions.
+    There can be any number of cycles, or none, even variable non constant cycles, between each pulse.
+    */
+
+    wire enPhi1 = (clkDivisor == 2'b11);
+    wire enPhi2 = (clkDivisor == 2'b01);
+
+
+    fx68k fx68k( .clk( clk32),
+        .extReset, .pwrUp( extReset), .enPhi1, .enPhi2,
+
+        .DTACKn, .VPAn, .BERRn, .BRn, .BGACKn,
+        .IPL0n, .IPL1n, .IPL2n,
+        .iEdb,
+
+        .oEdb,
+        .eRWn, .ASn, .LDSn, .UDSn,
+        .E, .VMAn,
+        .FC0, .FC1, .FC2,
+        .BGn,
+        .oRESETn, .oHALTEDn, .eab);
 
 endmodule
 `endif
diff --git a/fx68kAlu.sv b/fx68kAlu.sv
index 189f6ac..1fcd090 100644
--- a/fx68kAlu.sv
+++ b/fx68kAlu.sv
@@ -12,606 +12,616 @@
 localparam MASK_NBITS = 5;
 
 localparam
-		OP_AND = 1,
-		OP_SUB = 2, OP_SUBX = 3, OP_ADD = 4,
-		OP_EXT = 5, OP_SBCD = 6, OP_SUB0 = 7,
-		OP_OR = 8, OP_EOR = 9,
-		OP_SUBC = 10, OP_ADDC = 11, OP_ADDX = 12,
-		OP_ASL = 13,
-		OP_ASR = 14,
-		OP_LSL = 15,
-		OP_LSR = 16,
-		OP_ROL = 17,
-		OP_ROR = 18,
-		OP_ROXL = 19,
-		OP_ROXR = 20,
-		OP_SLAA = 21,
-		OP_ABCD = 22;
+        OP_AND = 1,
+        OP_SUB = 2, OP_SUBX = 3, OP_ADD = 4,
+        OP_EXT = 5, OP_SBCD = 6, OP_SUB0 = 7,
+        OP_OR = 8, OP_EOR = 9,
+        OP_SUBC = 10, OP_ADDC = 11, OP_ADDX = 12,
+        OP_ASL = 13,
+        OP_ASR = 14,
+        OP_LSL = 15,
+        OP_LSR = 16,
+        OP_ROL = 17,
+        OP_ROR = 18,
+        OP_ROXL = 19,
+        OP_ROXR = 20,
+        OP_SLAA = 21,
+        OP_ABCD = 22;
 
 module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
-	input [15:0] ird,
-	input [2:0] aluColumn,
-	input [1:0] aluDataCtrl,
-	input aluAddrCtrl, alueClkEn, ftu2Ccr, init, finish, aluIsByte,
-	input [15:0] ftu,
-	input [15:0] alub,
-	input [15:0] iDataBus, input [15:0] iAddrBus,
-	output ze,
-	output reg [15:0] alue,
-	output reg [7:0] ccr,
-	output [15:0] aluOut);
-
-
-`define ALU_ROW_01		16'h0002
-`define ALU_ROW_02		16'h0004
-`define ALU_ROW_03		16'h0008
-`define ALU_ROW_04		16'h0010
-`define ALU_ROW_05		16'h0020
-`define ALU_ROW_06		16'h0040
-`define ALU_ROW_07		16'h0080
-`define ALU_ROW_08		16'h0100
-`define ALU_ROW_09		16'h0200
-`define ALU_ROW_10		16'h0400
-`define ALU_ROW_11		16'h0800
-`define ALU_ROW_12		16'h1000
-`define ALU_ROW_13		16'h2000
-`define ALU_ROW_14		16'h4000
-`define ALU_ROW_15		16'h8000
-	
-	
-	// Bit positions for flags in CCR
-	localparam CF = 0, VF = 1, ZF = 2, NF = 3, XF = 4;
-
-	reg [15:0] aluLatch;
-	reg [4:0] pswCcr;
-	reg [4:0] ccrCore;
-	
-	logic [15:0] result;
-	logic [4:0] ccrTemp;
-	reg coreH;		// half carry latch
-
-	logic [15:0] subResult;
-	logic subHcarry;
-	logic subCout, subOv;
-
-	assign aluOut = aluLatch;
-	assign ze = ~ccrCore[ ZF];		// Check polarity !!!
-
-	//
-	// Control
-	//	Signals derived from IRD *must* be registered on either T3 or T4
-	//  Signals derived from nano rom can be registered on T4.
-
-	reg [15:0] row;
-	reg isArX;									// Don't set Z
-	reg noCcrEn;
-	reg isByte;
-	
-	reg [4:0] ccrMask;
-	reg [4:0] oper;
-	
-	logic [15:0] aOperand, dOperand;
-	wire isCorf = ( aluDataCtrl == 2'b10);
-
-	wire [15:0] cRow;
-	wire cIsArX;
-	wire cNoCcrEn;
-	rowDecoder rowDecoder( .ird( ird), .row( cRow), .noCcrEn( cNoCcrEn), .isArX( cIsArX));
-	
-	// Get Operation & CCR Mask from row/col
-	// Registering them on T4 increase performance. But slowest part seems to be corf !
-	wire [4:0] cMask;
-	wire [4:0] aluOp;
-
-	aluGetOp aluGetOp( .row, .col( aluColumn), .isCorf, .aluOp);	
-	ccrTable ccrTable( .col( aluColumn), .row( row), .finish, .ccrMask( cMask));
-
-	// Inefficient, uCode could help !
-	wire shftIsMul = row[7];
-	wire shftIsDiv = row[1];
-
-	wire [31:0] shftResult;
-	reg [7:0] bcdLatch;
-	reg bcdCarry, bcdOverf;
-		
-	reg isLong;
-	reg rIrd8;
-	logic isShift;
-	logic shftCin, shftRight, addCin;
-	
-	// Register some decoded signals	
-	always_ff @( posedge clk) begin
-		if( enT3) begin
-			row <= cRow;
-			isArX <= cIsArX;
-			noCcrEn <= cNoCcrEn;
-			rIrd8 <= ird[8];
-			isByte <= aluIsByte;
-		end
-		
-		if( enT4) begin
-			// Decode if long shift
-			// MUL and DIV are long (but special !)
-			isLong <= (ird[7] & ~ird[6]) | shftIsMul | shftIsDiv;			
-			
-			ccrMask <= cMask;
-			oper <= aluOp;
-		end
-	end
-	
-	
-	always_comb begin
-		// Dest (addr) operand source
-		// If aluCsr (depends on column/row) addrbus is shifted !!
-		aOperand = (aluAddrCtrl ? alub : iAddrBus);
-		
-		// Second (data,source) operand mux
-		case( aluDataCtrl)
-			2'b00:				dOperand = iDataBus;
-			2'b01:				dOperand = 'h0000;
-			2'b11:				dOperand = 'hffff;
-			// 2'b10:				dOperand = bcdResult;
-			2'b10:				dOperand = 'X;
-		endcase
-	end
-	
-	// Execution
-	   
-	// shift operand MSB. Input in ASR/ROL. Carry in right.
-	// Can't be registered because uses bus operands that aren't available early !
-	wire shftMsb = isLong ? alue[15] : (isByte ? aOperand[7] : aOperand[15]);
-	   
-	aluShifter shifter( .data( { alue, aOperand}),
-		.swapWords( shftIsMul | shftIsDiv),
-		.cin( shftCin), .dir( shftRight), .isByte( isByte), .isLong( isLong),
-		.result( shftResult));
-				
-	wire [7:0] bcdResult;
-	wire bcdC, bcdV;
-	aluCorf aluCorf( .binResult( aluLatch[7:0]), .hCarry( coreH),
-		.bAdd( (oper != OP_SBCD) ), .cin( pswCcr[ XF]),
-		.bcdResult( bcdResult), .dC( bcdC), .ov( bcdV));
-
-	// BCD adjust is among the slowest processing on ALU !
-	// Precompute and register BCD result on T1
-	// We don't need to wait for execution buses because corf is always added to ALU previous result
-	always_ff @( posedge clk)
-		if( enT1) begin
-			bcdLatch <= bcdResult;
-			bcdCarry <= bcdC;
-			bcdOverf <= bcdV;
-		end
-		
-	// Adder carry in selector
-	always_comb
-	begin
-		case( oper)
-			OP_ADD, OP_SUB:   addCin = 1'b0;
-			OP_SUB0:          addCin = 1'b1;			// NOT = 0 - op - 1
-			OP_ADDC,OP_SUBC:  addCin = ccrCore[ CF];
-			OP_ADDX,OP_SUBX:  addCin = pswCcr[ XF];
-			default: addCin = 1'bX;
-		endcase
-	end
-   	
-	// Shifter carry in and direction selector
-	always_comb begin
-		case( oper)
-		OP_LSL, OP_ASL, OP_ROL, OP_ROXL, OP_SLAA:   shftRight = 1'b0;
-		OP_LSR, OP_ASR, OP_ROR, OP_ROXR:            shftRight = 1'b1;
-		default:									shftRight = 1'bX;
-		endcase
-		
-		case( oper)
-		OP_LSR,
-		OP_ASL,
-		OP_LSL:		shftCin = 1'b0;
-		OP_ROL,
-		OP_ASR:		shftCin = shftMsb;
-		OP_ROR:		shftCin = aOperand[0];
-		OP_ROXL,
-		OP_ROXR:
-			if( shftIsMul)
-				shftCin = rIrd8 ? pswCcr[NF] ^ pswCcr[VF] : pswCcr[ CF];
-			else
-				shftCin = pswCcr[ XF];
-				
-		OP_SLAA:	shftCin = aluColumn[1];   // col4 -> 0, col 6-> 1
-		default:	shftCin = 'X;
-		endcase
-	end
-	
-	// ALU operation selector
-	always_comb begin	      
-
-		// sub is DATA - ADDR	    
-		mySubber( aOperand, dOperand, addCin,
-			(oper == OP_ADD) | (oper == OP_ADDC) | (oper == OP_ADDX),
-			isByte, subResult, subCout, subOv);
-			
-		isShift = 1'b0;
-		case( oper)
-		OP_AND: result = aOperand & dOperand;
-		OP_OR:  result = aOperand | dOperand;
-		OP_EOR: result = aOperand ^ dOperand;
-		
-		OP_EXT: result = { {8{aOperand[7]}}, aOperand[7:0]};
-		
-		OP_SLAA,
-		OP_ASL, OP_ASR,
-		OP_LSL, OP_LSR,
-		OP_ROL, OP_ROR,
-		OP_ROXL, OP_ROXR:
-			begin
-				result = shftResult[15:0];
-				isShift = 1'b1;
-			end
-			
-		OP_ADD,
-		OP_ADDC,
-		OP_ADDX,
-		OP_SUB,
-		OP_SUBC,
-		OP_SUB0,
-		OP_SUBX:	result = subResult;
-		
-		OP_ABCD,
-		OP_SBCD:	result = { 8'hXX, bcdLatch};
-
-		default:	result = 'X;
-		endcase	   
-	end
-	
-	task mySubber;
-		input [15:0] inpa, inpb;
-		input cin, bAdd, isByte;
-		output reg [15:0] result;
-		output cout, ov;
-
-		// Not very efficient!
-		logic [16:0] rtemp;
-		logic rm,sm,dm,tsm;
-
-		begin
-			if( isByte)
-			begin
-				rtemp = bAdd ? { 1'b0, inpb[7:0]} + { 1'b0, inpa[7:0]} + cin:
-								{ 1'b0, inpb[7:0] } - { 1'b0, inpa[7:0]} - cin;
-				result = { {8{ rtemp[7]}}, rtemp[7:0]};
-				cout = rtemp[8];
-			end
-			else begin
-				rtemp = bAdd ? { 1'b0, inpb } + { 1'b0, inpa} + cin:
-								{ 1'b0, inpb } - { 1'b0, inpa} - cin;
-				result = rtemp[ 15:0];
-				cout = rtemp[16];
-			end
-	        
-			rm  = isByte ? rtemp[7] : rtemp[15];
-			dm  = isByte ? inpb[ 7] : inpb[ 15];
-			tsm = isByte ? inpa[ 7] : inpa[ 15];
-			sm  = bAdd ? tsm : ~tsm;
-
-			ov = (sm & dm & ~rm) | (~sm & ~dm & rm);
-			
-			// Store half carry for bcd correction
-			subHcarry = inpa[4] ^ inpb[4] ^ rtemp[4];
-		
-		end
-	endtask
-	
-	
-	// CCR flags process
-	always_comb begin
-		
-		ccrTemp[XF] = pswCcr[XF];     ccrTemp[CF] = 0;     ccrTemp[VF] = 0;	
-
-		// Not on all operators
-		ccrTemp[ ZF] = isByte ? ~(| result[7:0]) : ~(| result);
-		ccrTemp[ NF] = isByte ? result[7] : result[15];
-
-		unique case( oper)
-		
-		OP_EXT:
-			// Division overflow.
-			if( aluColumn == 5) begin
-				ccrTemp[VF] = 1'b1;
-				ccrTemp[NF] = 1'b1;				ccrTemp[ ZF] = 1'b0;
-			end
-
-		OP_SUB0,				// used by NOT
-		OP_OR,
-		OP_EOR:
-			begin
-				ccrTemp[CF] = 0;      ccrTemp[VF] = 0;
-			end
-
-		OP_AND:
-			begin
-				// ROXL/ROXR indeed copy X to C in column 1 (OP_AND), executed before entering the loop.
-				// Needed when rotate count is zero, the ucode with the ROX operator never reached.
-				// 	C must be set to the value of X, X remains unaffected.
-				if( (aluColumn == 1) & (row[11] | row[8]))
-					ccrTemp[CF] = pswCcr[XF];
-				else
-					ccrTemp[CF] = 0;
-				ccrTemp[VF] = 0;
-			end
-			
-		// Assumes col 3 of DIV use C and not X !
-		// V will be set in other cols (2/3) of DIV
-		OP_SLAA:   ccrTemp[ CF] = aOperand[15];
-		
-		OP_LSL,OP_ROXL:
-			begin
-				ccrTemp[ CF] = shftMsb;
-				ccrTemp[ XF] = shftMsb;
-				ccrTemp[ VF] = 1'b0;
-			end
-			
-		OP_LSR,OP_ROXR:
-			begin
-				// 0 Needed for mul, or carry gets in high word
-				ccrTemp[ CF] = shftIsMul ? 1'b0 : aOperand[0];
-				ccrTemp[ XF] = aOperand[0];
-				// Not relevant for MUL, we clear it at mulm6 (1f) anyway.
-				// Not that MUL can never overlow!
-				ccrTemp[ VF] = 0;
-				// Z is checking here ALU (low result is actually in ALUE).
-				// But it is correct, see comment above.
-			end
-			
-		OP_ASL:
-			begin
-				ccrTemp[ XF] = shftMsb;			ccrTemp[ CF] = shftMsb;
-				// V set if msb changed on any shift.
-				// Otherwise clear previously on OP_AND (col 1i).
-				ccrTemp[ VF] = pswCcr[VF] | (shftMsb ^
-					(isLong ? alue[15-1] : (isByte ? aOperand[7-1] : aOperand[15-1])) );
-			end
-		OP_ASR:
-			begin
-				ccrTemp[ XF] = aOperand[0];		ccrTemp[ CF] = aOperand[0];
-				ccrTemp[ VF] = 0;
-			end
-      
-		// X not changed on ROL/ROR !
-		OP_ROL:		ccrTemp[ CF] = shftMsb;
-		OP_ROR:		ccrTemp[ CF] = aOperand[0];
-
-		OP_ADD,
-		OP_ADDC,
-		OP_ADDX,
-		OP_SUB,
-		OP_SUBC,
-		OP_SUBX:
-			begin
-				ccrTemp[ CF] = subCout;
-				ccrTemp[ XF] = subCout;
-				ccrTemp[ VF] = subOv;
-			end
-
-		OP_ABCD,
-		OP_SBCD:
-			begin
-				ccrTemp[ XF] = bcdCarry;
-				ccrTemp[ CF] = bcdCarry;
-				ccrTemp[ VF] = bcdOverf;
-			end
-		
-		endcase
-				
-	end
-	
-	// Core and psw latched at the same cycle
-	
-	// CCR filter
-	// CCR out mux for Z & C flags
-	// Z flag for 32-bit result
-	// Not described, but should be used also for instructions
-	//   that clear but not set Z (ADDX/SUBX/ABCD, etc)!
-	logic [4:0] ccrMasked;
-	always_comb begin
-		ccrMasked = (ccrTemp & ccrMask) | (pswCcr & ~ccrMask);
-		// if( finish | isCorf | isArX)		// No need to check specicially for isCorf as they always have the "finish" flag anyway
-		if( finish | isArX)
-			ccrMasked[ ZF] = ccrTemp[ ZF] & pswCcr[ ZF];
-	end
-		
-	always_ff @( posedge clk) begin
-		if( enT3) begin
-			// Update latches from ALU operators
-			if( (| aluColumn)) begin
-				aluLatch <= result;
-				
-				coreH <= subHcarry;
-			   
-				// Update CCR core
-				if( (| aluColumn))
-					ccrCore <= ccrTemp;		// Most bits not really used
-			end
-
-			if( alueClkEn)
-				alue <= iDataBus;
-			else if( isShift & (| aluColumn))
-				alue <= shftResult[31:16];
-		end
-				
-		// CCR
-		// Originally on T3-T4 edge pulse !!
-		// Might be possible to update on T4 (but not after T0) from partial result registered on T3, it will increase performance!
-		if( pwrUp)
-			pswCcr <= '0;
-		else if( enT3 & ftu2Ccr)
-			pswCcr <= ftu[4:0];	
-		else if( enT3 &	~noCcrEn & (finish | init))
-			pswCcr <= ccrMasked;
-	end
-	assign ccr = { 3'b0, pswCcr};	
-
-	      
+    input [15:0] ird,
+    input [2:0] aluColumn,
+    input [1:0] aluDataCtrl,
+    input aluAddrCtrl, alueClkEn, ftu2Ccr, init, finish, aluIsByte,
+    input [15:0] ftu,
+    input [15:0] alub,
+    input [15:0] iDataBus, input [15:0] iAddrBus,
+    output ze,
+    output reg [15:0] alue,
+    output reg [7:0] ccr,
+    output [15:0] aluOut);
+
+
+`define ALU_ROW_01      16'h0002
+`define ALU_ROW_02      16'h0004
+`define ALU_ROW_03      16'h0008
+`define ALU_ROW_04      16'h0010
+`define ALU_ROW_05      16'h0020
+`define ALU_ROW_06      16'h0040
+`define ALU_ROW_07      16'h0080
+`define ALU_ROW_08      16'h0100
+`define ALU_ROW_09      16'h0200
+`define ALU_ROW_10      16'h0400
+`define ALU_ROW_11      16'h0800
+`define ALU_ROW_12      16'h1000
+`define ALU_ROW_13      16'h2000
+`define ALU_ROW_14      16'h4000
+`define ALU_ROW_15      16'h8000
+
+
+    // Bit positions for flags in CCR
+    localparam CF = 0, VF = 1, ZF = 2, NF = 3, XF = 4;
+
+    reg [15:0] aluLatch;
+    reg [4:0] pswCcr;
+    reg [4:0] ccrCore;
+
+    logic [15:0] result;
+    logic [4:0] ccrTemp;
+    reg coreH;      // half carry latch
+
+    logic [15:0] subResult;
+    logic subHcarry;
+    logic subCout, subOv;
+
+    assign aluOut = aluLatch;
+    assign ze = ~ccrCore[ ZF];      // Check polarity !!!
+
+    //
+    // Control
+    //  Signals derived from IRD *must* be registered on either T3 or T4
+    //  Signals derived from nano rom can be registered on T4.
+
+    reg [15:0] row;
+    reg isArX;                                  // Don't set Z
+    reg noCcrEn;
+    reg isByte;
+
+    reg [4:0] ccrMask;
+    reg [4:0] oper;
+
+    logic [15:0] aOperand, dOperand;
+    wire isCorf = ( aluDataCtrl == 2'b10);
+
+    wire [15:0] cRow;
+    wire cIsArX;
+    wire cNoCcrEn;
+    rowDecoder rowDecoder( .ird( ird), .row( cRow), .noCcrEn( cNoCcrEn), .isArX( cIsArX));
+
+    // Get Operation & CCR Mask from row/col
+    // Registering them on T4 increase performance. But slowest part seems to be corf !
+    wire [4:0] cMask;
+    wire [4:0] aluOp;
+
+    aluGetOp aluGetOp( .row, .col( aluColumn), .isCorf, .aluOp);
+    ccrTable ccrTable( .col( aluColumn), .row( row), .finish, .ccrMask( cMask));
+
+    // Inefficient, uCode could help !
+    wire shftIsMul = row[7];
+    wire shftIsDiv = row[1];
+
+    wire [31:0] shftResult;
+    reg [7:0] bcdLatch;
+    reg bcdCarry, bcdOverf;
+
+    reg isLong;
+    reg rIrd8;
+    logic isShift;
+    logic shftCin, shftRight, addCin;
+
+    // Register some decoded signals
+    always_ff @( posedge clk) begin
+        if (enT3) begin
+            row     <= cRow;
+            isArX   <= cIsArX;
+            noCcrEn <= cNoCcrEn;
+            rIrd8   <= ird[8];
+            isByte  <= aluIsByte;
+        end
+
+        if (enT4) begin
+            // Decode if long shift
+            // MUL and DIV are long (but special !)
+            isLong   <= (ird[7] & ~ird[6]) | shftIsMul | shftIsDiv;
+
+            ccrMask  <= cMask;
+            oper     <= aluOp;
+        end
+    end
+
+
+    always_comb begin
+        // Dest (addr) operand source
+        // If aluCsr (depends on column/row) addrbus is shifted !!
+        aOperand = (aluAddrCtrl ? alub : iAddrBus);
+
+        // Second (data,source) operand mux
+        case (aluDataCtrl)
+            2'b00:              dOperand = iDataBus;
+            2'b01:              dOperand = 'h0000;
+            2'b11:              dOperand = 'hffff;
+            // 2'b10:               dOperand = bcdResult;
+            2'b10:              dOperand = 'X;
+        endcase
+    end
+
+    // Execution
+
+    // shift operand MSB. Input in ASR/ROL. Carry in right.
+    // Can't be registered because uses bus operands that aren't available early !
+    wire shftMsb = isLong ? alue[15] : (isByte ? aOperand[7] : aOperand[15]);
+
+    aluShifter shifter( .data( { alue, aOperand}),
+        .swapWords( shftIsMul | shftIsDiv),
+        .cin( shftCin), .dir( shftRight), .isByte( isByte), .isLong( isLong),
+        .result( shftResult));
+
+    wire [7:0] bcdResult;
+    wire bcdC, bcdV;
+    aluCorf aluCorf( .binResult( aluLatch[7:0]), .hCarry( coreH),
+        .bAdd( (oper != OP_SBCD) ), .cin( pswCcr[ XF]),
+        .bcdResult( bcdResult), .dC( bcdC), .ov( bcdV));
+
+    // BCD adjust is among the slowest processing on ALU !
+    // Precompute and register BCD result on T1
+    // We don't need to wait for execution buses because corf is always added to ALU previous result
+    always_ff @(posedge clk) begin
+    
+        if (enT1) begin
+            bcdLatch <= bcdResult;
+            bcdCarry <= bcdC;
+            bcdOverf <= bcdV;
+        end
+    end
+
+    // Adder carry in selector
+    always_comb
+    begin
+        case( oper)
+            OP_ADD, OP_SUB:   addCin = 1'b0;
+            OP_SUB0:          addCin = 1'b1;            // NOT = 0 - op - 1
+            OP_ADDC,OP_SUBC:  addCin = ccrCore[ CF];
+            OP_ADDX,OP_SUBX:  addCin = pswCcr[ XF];
+            default: addCin = 1'bX;
+        endcase
+    end
+
+    // Shifter carry in and direction selector
+    always_comb begin
+        case( oper)
+        OP_LSL, OP_ASL, OP_ROL, OP_ROXL, OP_SLAA:   shftRight = 1'b0;
+        OP_LSR, OP_ASR, OP_ROR, OP_ROXR:            shftRight = 1'b1;
+        default:                                    shftRight = 1'bX;
+        endcase
+
+        case( oper)
+        OP_LSR,
+        OP_ASL,
+        OP_LSL:     shftCin = 1'b0;
+        OP_ROL,
+        OP_ASR:     shftCin = shftMsb;
+        OP_ROR:     shftCin = aOperand[0];
+        OP_ROXL,
+        OP_ROXR:
+            if( shftIsMul)
+                shftCin = rIrd8 ? pswCcr[NF] ^ pswCcr[VF] : pswCcr[ CF];
+            else
+                shftCin = pswCcr[ XF];
+
+        OP_SLAA:    shftCin = aluColumn[1];   // col4 -> 0, col 6-> 1
+        default:    shftCin = 'X;
+        endcase
+    end
+
+    // ALU operation selector
+    always_comb begin
+
+        // sub is DATA - ADDR
+        mySubber( aOperand, dOperand, addCin,
+            (oper == OP_ADD) | (oper == OP_ADDC) | (oper == OP_ADDX),
+            isByte, subResult, subCout, subOv);
+
+        isShift = 1'b0;
+        case( oper)
+        OP_AND: result = aOperand & dOperand;
+        OP_OR:  result = aOperand | dOperand;
+        OP_EOR: result = aOperand ^ dOperand;
+
+        OP_EXT: result = { {8{aOperand[7]}}, aOperand[7:0]};
+
+        OP_SLAA,
+        OP_ASL, OP_ASR,
+        OP_LSL, OP_LSR,
+        OP_ROL, OP_ROR,
+        OP_ROXL, OP_ROXR:
+            begin
+                result = shftResult[15:0];
+                isShift = 1'b1;
+            end
+
+        OP_ADD,
+        OP_ADDC,
+        OP_ADDX,
+        OP_SUB,
+        OP_SUBC,
+        OP_SUB0,
+        OP_SUBX:    result = subResult;
+
+        OP_ABCD,
+        OP_SBCD:    result = { 8'hXX, bcdLatch};
+
+        default:    result = 'X;
+        endcase
+    end
+
+    task mySubber;
+        input [15:0] inpa, inpb;
+        input cin, bAdd, isByte;
+        output reg [15:0] result;
+        output cout, ov;
+
+        // Not very efficient!
+        logic [16:0] rtemp;
+        logic rm,sm,dm,tsm;
+
+        begin
+            if( isByte)
+            begin
+                rtemp = bAdd ? { 9'b0, inpb[7:0] } + { 9'b0, inpa[7:0] } + { 16'b0, cin }
+                             : { 9'b0, inpb[7:0] } - { 9'b0, inpa[7:0] } - { 16'b0, cin };
+                result = { {8{ rtemp[7]}}, rtemp[7:0]};
+                cout = rtemp[8];
+            end
+            else begin
+                rtemp = bAdd ? { 1'b0, inpb } + { 1'b0, inpa } + { 16'b0, cin }
+                             : { 1'b0, inpb } - { 1'b0, inpa } - { 16'b0, cin };
+                result = rtemp[ 15:0];
+                cout = rtemp[16];
+            end
+
+            rm  = isByte ? rtemp[7] : rtemp[15];
+            dm  = isByte ? inpb[ 7] : inpb[ 15];
+            tsm = isByte ? inpa[ 7] : inpa[ 15];
+            sm  = bAdd ? tsm : ~tsm;
+
+            ov = (sm & dm & ~rm) | (~sm & ~dm & rm);
+
+            // Store half carry for bcd correction
+            subHcarry = inpa[4] ^ inpb[4] ^ rtemp[4];
+
+        end
+    endtask
+
+
+    // CCR flags process
+    always_comb begin
+
+        ccrTemp[XF] = pswCcr[XF];     ccrTemp[CF] = 0;     ccrTemp[VF] = 0;
+
+        // Not on all operators
+        ccrTemp[ ZF] = isByte ? ~(| result[7:0]) : ~(| result);
+        ccrTemp[ NF] = isByte ? result[7] : result[15];
+
+        unique case( oper)
+
+        OP_EXT:
+            // Division overflow.
+            if( aluColumn == 5) begin
+                ccrTemp[VF] = 1'b1;
+                ccrTemp[NF] = 1'b1;             ccrTemp[ ZF] = 1'b0;
+            end
+
+        OP_SUB0,                // used by NOT
+        OP_OR,
+        OP_EOR:
+            begin
+                ccrTemp[CF] = 0;      ccrTemp[VF] = 0;
+            end
+
+        OP_AND:
+            begin
+                // ROXL/ROXR indeed copy X to C in column 1 (OP_AND), executed before entering the loop.
+                // Needed when rotate count is zero, the ucode with the ROX operator never reached.
+                //  C must be set to the value of X, X remains unaffected.
+                if( (aluColumn == 1) & (row[11] | row[8]))
+                    ccrTemp[CF] = pswCcr[XF];
+                else
+                    ccrTemp[CF] = 0;
+                ccrTemp[VF] = 0;
+            end
+
+        // Assumes col 3 of DIV use C and not X !
+        // V will be set in other cols (2/3) of DIV
+        OP_SLAA:   ccrTemp[ CF] = aOperand[15];
+
+        OP_LSL,OP_ROXL:
+            begin
+                ccrTemp[ CF] = shftMsb;
+                ccrTemp[ XF] = shftMsb;
+                ccrTemp[ VF] = 1'b0;
+            end
+
+        OP_LSR,OP_ROXR:
+            begin
+                // 0 Needed for mul, or carry gets in high word
+                ccrTemp[ CF] = shftIsMul ? 1'b0 : aOperand[0];
+                ccrTemp[ XF] = aOperand[0];
+                // Not relevant for MUL, we clear it at mulm6 (1f) anyway.
+                // Not that MUL can never overlow!
+                ccrTemp[ VF] = 0;
+                // Z is checking here ALU (low result is actually in ALUE).
+                // But it is correct, see comment above.
+            end
+
+        OP_ASL:
+            begin
+                ccrTemp[ XF] = shftMsb;         ccrTemp[ CF] = shftMsb;
+                // V set if msb changed on any shift.
+                // Otherwise clear previously on OP_AND (col 1i).
+                ccrTemp[ VF] = pswCcr[VF] | (shftMsb ^
+                    (isLong ? alue[15-1] : (isByte ? aOperand[7-1] : aOperand[15-1])) );
+            end
+        OP_ASR:
+            begin
+                ccrTemp[ XF] = aOperand[0];     ccrTemp[ CF] = aOperand[0];
+                ccrTemp[ VF] = 0;
+            end
+
+        // X not changed on ROL/ROR !
+        OP_ROL:     ccrTemp[ CF] = shftMsb;
+        OP_ROR:     ccrTemp[ CF] = aOperand[0];
+
+        OP_ADD,
+        OP_ADDC,
+        OP_ADDX,
+        OP_SUB,
+        OP_SUBC,
+        OP_SUBX:
+            begin
+                ccrTemp[ CF] = subCout;
+                ccrTemp[ XF] = subCout;
+                ccrTemp[ VF] = subOv;
+            end
+
+        OP_ABCD,
+        OP_SBCD:
+            begin
+                ccrTemp[ XF] = bcdCarry;
+                ccrTemp[ CF] = bcdCarry;
+                ccrTemp[ VF] = bcdOverf;
+            end
+
+        endcase
+
+    end
+
+    // Core and psw latched at the same cycle
+
+    // CCR filter
+    // CCR out mux for Z & C flags
+    // Z flag for 32-bit result
+    // Not described, but should be used also for instructions
+    //   that clear but not set Z (ADDX/SUBX/ABCD, etc)!
+    logic [4:0] ccrMasked;
+    always_comb begin
+        ccrMasked = (ccrTemp & ccrMask) | (pswCcr & ~ccrMask);
+        // if (finish | isCorf | isArX)     // No need to check specicially for isCorf as they always have the "finish" flag anyway
+        if (finish | isArX)
+            ccrMasked[ ZF] = ccrTemp[ ZF] & pswCcr[ ZF];
+    end
+
+    always_ff @(posedge clk) begin
+        if (enT3) begin
+            // Update latches from ALU operators
+            if ((| aluColumn)) begin
+                aluLatch <= result;
+
+                coreH <= subHcarry;
+
+                // Update CCR core
+                if ((| aluColumn))
+                    ccrCore <= ccrTemp;     // Most bits not really used
+            end
+
+            if (alueClkEn)
+                alue <= iDataBus;
+            else if (isShift & (| aluColumn))
+                alue <= shftResult[31:16];
+        end
+
+        // CCR
+        // Originally on T3-T4 edge pulse !!
+        // Might be possible to update on T4 (but not after T0) from partial result registered on T3, it will increase performance!
+        if (pwrUp)
+            pswCcr <= '0;
+        else if (enT3 & ftu2Ccr)
+            pswCcr <= ftu[4:0];
+        else if (enT3 & ~noCcrEn & (finish | init))
+            pswCcr <= ccrMasked;
+    end
+    assign ccr = { 3'b0, pswCcr};
+
 endmodule
 
 // add bcd correction factor
 // It would be more efficient to merge add/sub with main ALU !!!
-module aluCorf( input [7:0] binResult, input bAdd, input cin, input hCarry,
-	output [7:0] bcdResult, output dC, output logic ov);
-
-	reg [8:0] htemp;
-	reg [4:0] hNib;
-	
-	wire lowC  = hCarry | (bAdd ? gt9( binResult[ 3:0]) : 1'b0);
-	wire highC = cin	| (bAdd ? (gt9( htemp[7:4]) | htemp[8]) : 1'b0);
-		
-	always_comb begin
-		if( bAdd) begin
-			htemp = { 1'b0, binResult} + (lowC  ? 4'h6 : 4'h0);
-			hNib  = htemp[8:4] + (highC ? 4'h6 : 4'h0);
-			ov = hNib[3] & ~binResult[7];
-		end
-		else begin
-			htemp = { 1'b0, binResult} - (lowC  ? 4'h6 : 4'h0);
-			hNib  = htemp[8:4] - (highC ? 4'h6 : 4'h0);
-			ov = ~hNib[3] & binResult[7];
-		end
-	end
-
-	assign bcdResult = { hNib[ 3:0], htemp[3:0]};
-	assign dC = hNib[4] | cin;
-
-	// Nibble > 9
-	function gt9 (input [3:0] nib);
-	begin
-		gt9 = nib[3] & (nib[2] | nib[1]);
-	end
-	endfunction
+/* verilator lint_off UNOPTFLAT */
+module aluCorf
+(
+    input  [7:0] binResult,
+    input        bAdd,
+    input        cin,
+    input        hCarry,
+    output [7:0] bcdResult,
+    output       dC,
+    output logic ov
+);
+
+    reg [8:0] htemp;
+    reg [4:0] hNib;
+
+    wire lowC  = hCarry | (bAdd ? gt9(binResult[3:0]) : 1'b0);
+    wire highC = cin    | (bAdd ? (gt9(htemp[7:4]) | htemp[8]) : 1'b0);
+
+    always_comb begin
+        if (bAdd) begin
+            htemp = { 1'b0, binResult} + (lowC  ? 9'h6 : 9'h0);
+            hNib  = htemp[8:4] + (highC ? 5'h6 : 5'h0);
+            ov = hNib[3] & ~binResult[7];
+        end
+        else begin
+            htemp = { 1'b0, binResult} - (lowC  ? 9'h6 : 9'h0);
+            hNib  = htemp[8:4] - (highC ? 5'h6 : 5'h0);
+            ov = ~hNib[3] & binResult[7];
+        end
+    end
+
+    assign bcdResult = { hNib[ 3:0], htemp[3:0]};
+    assign dC = hNib[4] | cin;
+
+    // Nibble > 9
+    function gt9 (input [3:0] nib);
+    begin
+        gt9 = nib[3] & (nib[2] | nib[1]);
+    end
+    endfunction
 
 endmodule
-
+/* verilator lint_on UNOPTFLAT */
 
 module aluShifter( input [31:0] data,
-	input isByte, input isLong, swapWords,
-	input dir, input cin,
-	output logic [31:0] result);
-	// output reg cout
-
-	logic [31:0] tdata;         
-
-	// size mux, put cin in position if dir == right
-	always_comb begin
-		tdata = data;
-		if( isByte & dir)
-			tdata[8] = cin;
-		else if( !isLong & dir)
-			tdata[16] = cin;
-	end
-    
-	always_comb begin
-		// Reverse alu/alue position for MUL & DIV
-		// Result reversed again
-		if( swapWords & dir)
-			result = { tdata[0], tdata[31:17], cin, tdata[15:1]};
-		else if( swapWords)
-			result = { tdata[30:16], cin, tdata[14:0], tdata[31]};
-			
-		else if( dir)
-			result = { cin, tdata[31:1]};
-		else
-			result = { tdata[30:0], cin};
-	end
+    input isByte, input isLong, swapWords,
+    input dir, input cin,
+    output logic [31:0] result);
+    // output reg cout
+
+    logic [31:0] tdata;
+
+    // size mux, put cin in position if dir == right
+    always_comb begin
+        tdata = data;
+        if (isByte & dir)
+            tdata[8] = cin;
+        else if (!isLong & dir)
+            tdata[16] = cin;
+    end
+
+    always_comb begin
+        // Reverse alu/alue position for MUL & DIV
+        // Result reversed again
+        if (swapWords & dir)
+            result = { tdata[0], tdata[31:17], cin, tdata[15:1]};
+        else if (swapWords)
+            result = { tdata[30:16], cin, tdata[14:0], tdata[31]};
+
+        else if (dir)
+            result = { cin, tdata[31:1]};
+        else
+            result = { tdata[30:0], cin};
+    end
 
 endmodule
 
 
 // Get current OP from row & col
 module aluGetOp( input [15:0] row, input [2:0] col, input isCorf,
-	output logic [4:0] aluOp);
-	
-	always_comb begin
-		aluOp = 'X;
-		unique case( col)  
-		1:   aluOp = OP_AND;
-		5:   aluOp = OP_EXT;
-
-		default:
-			unique case( 1'b1)
-				row[1]:
-					unique case( col)
-					2: aluOp = OP_SUB;
-					3: aluOp = OP_SUBC;
-					4,6: aluOp = OP_SLAA;
-					endcase
-				
-				row[2]:
-					unique case( col)
-					2: aluOp = OP_ADD;
-					3: aluOp = OP_ADDC;
-					4: aluOp = OP_ASR;
-					endcase
-
-				row[3]:
-					unique case( col)
-					2: aluOp = OP_ADDX;
-					3: aluOp = isCorf ? OP_ABCD : OP_ADD;
-					4: aluOp = OP_ASL;
-					endcase
-                  
-				row[4]:
-					aluOp = ( col == 4) ? OP_LSL : OP_AND;
-				
-				row[5],
-				row[6]:
-					unique case( col)
-					2: aluOp = OP_SUB;
-					3: aluOp = OP_SUBC;
-					4: aluOp = OP_LSR;
-					endcase
-				
-				row[7]:					// MUL
-					unique case( col)
-					2: aluOp = OP_SUB;
-					3: aluOp = OP_ADD;
-					4: aluOp = OP_ROXR;
-					endcase
-               
-				row[8]:
-					// OP_AND For EXT.L
-					// But would be more efficient to change ucode and use column 1 instead of col3 at ublock extr1!				
-					unique case( col)
-					2: aluOp = OP_EXT;
-					3: aluOp = OP_AND;
-					4: aluOp = OP_ROXR;
-					endcase
-               
-				row[9]:
-					unique case( col)
-					2: aluOp = OP_SUBX;
-					3: aluOp = OP_SBCD;
-					4: aluOp = OP_ROL;
-					endcase
-
-				row[10]:
-					unique case( col)
-					2: aluOp = OP_SUBX;
-					3: aluOp = OP_SUBC;
-					4: aluOp = OP_ROR;
-					endcase
-                
-				row[11]:
-					unique case( col)
-					2: aluOp = OP_SUB0;
-					3: aluOp = OP_SUB0;
-					4: aluOp = OP_ROXL;
-					endcase
-                
-				row[12]:	aluOp = OP_ADDX;               
-				row[13]:	aluOp = OP_EOR;
-				row[14]:	aluOp = (col == 4) ? OP_EOR : OP_OR;
-				row[15]:	aluOp = (col == 3) ? OP_ADD : OP_OR;		// OP_ADD used by DBcc
-				
-			endcase         
-		endcase
-	end
+    output logic [4:0] aluOp);
+
+    always_comb begin
+        aluOp = 'X;
+        unique case (col)
+        1:   aluOp = OP_AND;
+        5:   aluOp = OP_EXT;
+
+        default:
+            unique case (1'b1)
+                row[1]:
+                    unique case (col)
+                    2: aluOp = OP_SUB;
+                    3: aluOp = OP_SUBC;
+                    4,6: aluOp = OP_SLAA;
+                    endcase
+
+                row[2]:
+                    unique case (col)
+                    2: aluOp = OP_ADD;
+                    3: aluOp = OP_ADDC;
+                    4: aluOp = OP_ASR;
+                    endcase
+
+                row[3]:
+                    unique case (col)
+                    2: aluOp = OP_ADDX;
+                    3: aluOp = isCorf ? OP_ABCD : OP_ADD;
+                    4: aluOp = OP_ASL;
+                    endcase
+
+                row[4]:
+                    aluOp = ( col == 4) ? OP_LSL : OP_AND;
+
+                row[5],
+                row[6]:
+                    unique case (col)
+                    2: aluOp = OP_SUB;
+                    3: aluOp = OP_SUBC;
+                    4: aluOp = OP_LSR;
+                    endcase
+
+                row[7]:                 // MUL
+                    unique case (col)
+                    2: aluOp = OP_SUB;
+                    3: aluOp = OP_ADD;
+                    4: aluOp = OP_ROXR;
+                    endcase
+
+                row[8]:
+                    // OP_AND For EXT.L
+                    // But would be more efficient to change ucode and use column 1 instead of col3 at ublock extr1!
+                    unique case (col)
+                    2: aluOp = OP_EXT;
+                    3: aluOp = OP_AND;
+                    4: aluOp = OP_ROXR;
+                    endcase
+
+                row[9]:
+                    unique case (col)
+                    2: aluOp = OP_SUBX;
+                    3: aluOp = OP_SBCD;
+                    4: aluOp = OP_ROL;
+                    endcase
+
+                row[10]:
+                    unique case (col)
+                    2: aluOp = OP_SUBX;
+                    3: aluOp = OP_SUBC;
+                    4: aluOp = OP_ROR;
+                    endcase
+
+                row[11]:
+                    unique case (col)
+                    2: aluOp = OP_SUB0;
+                    3: aluOp = OP_SUB0;
+                    4: aluOp = OP_ROXL;
+                    endcase
+
+                row[12]:    aluOp = OP_ADDX;
+                row[13]:    aluOp = OP_EOR;
+                row[14]:    aluOp = (col == 4) ? OP_EOR : OP_OR;
+                row[15]:    aluOp = (col == 3) ? OP_ADD : OP_OR;        // OP_ADD used by DBcc
+
+            endcase
+        endcase
+    end
 endmodule
 
 // Decodes IRD into ALU row (1-15)
@@ -621,219 +631,228 @@ endmodule
 // Many opcodes are not decoded because they either don't do any ALU op,
 // or use only columns 1 and 5 that are the same for all rows.
 
-module rowDecoder( input [15:0] ird,
-	output logic [15:0] row, output noCcrEn, output logic isArX);
-
-
-	// Addr or data register direct
-	wire eaRdir = (ird[ 5:4] == 2'b00);
-	// Addr register direct
-	wire eaAdir = (ird[ 5:3] == 3'b001);
-	wire size11 = ird[7] & ird[6];
-	
-	always_comb begin
-		case( ird[15:12])
-		'h4,
-		'h9,
-		'hd:
-			isArX = row[10] | row[12];
-		default:
-			isArX = 1'b0;
-		endcase
-	end
-
-	always_comb begin
-		unique case( ird[15:12])
-
-		'h4:  begin
-				if( ird[8])
-					row = `ALU_ROW_06;			// chk (or lea)
-				else case( ird[11:9])
-					'b000: row = `ALU_ROW_10;	// negx
-					'b001: row = `ALU_ROW_04;	// clr
-					'b010: row = `ALU_ROW_05;	// neg
-					'b011: row = `ALU_ROW_11;	// not
-					'b100: row = (ird[7]) ? `ALU_ROW_08 : `ALU_ROW_09;	// nbcd/swap/ext(or pea)
-					'b101: row = `ALU_ROW_15;	// tst & tas
-					default: row = 0;
-				endcase
-			end
-
-		'h0: begin
-				if( ird[8])                       // dynamic bit
-					row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13;
-				else case( ird[ 11:9])
-					'b000:   row = `ALU_ROW_14;	// ori
-					'b001:   row = `ALU_ROW_04;	// andi
-					'b010:   row = `ALU_ROW_05;	// subi
-					'b011:   row = `ALU_ROW_02;	// addi
-					'b100:   row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13;   // static bit
-					'b101:   row = `ALU_ROW_13;	// eori
-					'b110:   row = `ALU_ROW_06;	// cmpi
-					default: row = 0;
-					endcase
-				end
-				
-		// MOVE
-		// move.b originally also rows 5 & 15. Only because IRD bit 14 is not decoded.
-		// It's the same for move the operations performed by MOVE.B
-
-		'h1,'h2,'h3:   row = `ALU_ROW_02;
-		
-		'h5:
-			if( size11)										
-               row = `ALU_ROW_15;								// As originally and easier to decode
-			else
-				row = ird[8] ? `ALU_ROW_05 : `ALU_ROW_02;     // addq/subq
-		'h6:	row = 0;						//bcc/bra/bsr
-		'h7:	row = `ALU_ROW_02;				// moveq
-		'h8:
-			if( size11)						// div
-				row = `ALU_ROW_01;
-			else if( ird[8] & eaRdir)		// sbcd
-				row = `ALU_ROW_09;
-			else
-				row = `ALU_ROW_14;			// or
-		'h9:
-			if( ird[8] & ~size11 & eaRdir)
-				row = `ALU_ROW_10;			// subx
-			else
-				row = `ALU_ROW_05;			// sub/suba
-		'hb:
-			if( ird[8] & ~size11 & ~eaAdir)
-				row = `ALU_ROW_13;			// eor
-			else
-				row = `ALU_ROW_06;			// cmp/cmpa/cmpm
-		'hc:
-			if( size11)
-				row = `ALU_ROW_07;			// mul
-			else if( ird[8] & eaRdir)		// abcd
-				row = `ALU_ROW_03;
-			else
-				row = `ALU_ROW_04;			// and
-		'hd:
-			if( ird[8] & ~size11 & eaRdir)
-				row = `ALU_ROW_12;			// addx
-			else
-				row = `ALU_ROW_02;			// add/adda
-		'he:
-			begin
-				reg [1:0] stype;
-				
-				if( size11)					// memory shift/rotate
-					stype = ird[ 10:9];
-				else						// register shift/rotate
-					stype = ird[ 4:3];
-
-				case( {stype, ird[8]})
-				0: row = `ALU_ROW_02;	// ASR
-				1: row = `ALU_ROW_03;	// ASL
-				2: row = `ALU_ROW_05;	// LSR
-				3: row = `ALU_ROW_04;	// LSL
-				4: row = `ALU_ROW_08;	// ROXR
-				5: row = `ALU_ROW_11;	// ROXL
-				6: row = `ALU_ROW_10;	// ROR
-				7: row = `ALU_ROW_09;	// ROL
-				endcase
-			end
-			
-		default:	row = 0;
-		endcase
-	end
-   
-	// Decode opcodes that don't affect flags
-	// ADDA/SUBA ADDQ/SUBQ MOVEA
-
-	assign noCcrEn =
-		// ADDA/SUBA
-		( ird[15] & ~ird[13] & ird[12] & size11) |
-		// ADDQ/SUBQ to An
-		( (ird[15:12] == 4'h5) & eaAdir) |
-		// MOVEA
-		( (~ird[15] & ~ird[14] & ird[13]) & ird[8:6] == 3'b001);
-        
+module rowDecoder
+(
+    input [15:0] ird,
+    output logic [15:0] row,
+    output logic noCcrEn,
+    output logic isArX
+);
+
+
+    // Addr or data register direct
+    wire eaRdir = (ird[ 5:4] == 2'b00);
+    // Addr register direct
+    wire eaAdir = (ird[ 5:3] == 3'b001);
+    wire size11 = ird[7] & ird[6];
+
+    always_comb begin
+        case (ird[15:12])
+        'h4,
+        'h9,
+        'hd:
+            isArX = row[10] | row[12];
+        default:
+            isArX = 1'b0;
+        endcase
+    end
+
+    always_comb begin
+        unique case (ird[15:12])
+
+        'h4:  begin
+                if (ird[8])
+                    row = `ALU_ROW_06;          // chk (or lea)
+                else case (ird[11:9])
+                    'b000: row = `ALU_ROW_10;   // negx
+                    'b001: row = `ALU_ROW_04;   // clr
+                    'b010: row = `ALU_ROW_05;   // neg
+                    'b011: row = `ALU_ROW_11;   // not
+                    'b100: row = (ird[7]) ? `ALU_ROW_08 : `ALU_ROW_09;  // nbcd/swap/ext(or pea)
+                    'b101: row = `ALU_ROW_15;   // tst & tas
+                    default: row = 0;
+                endcase
+            end
+
+        'h0: begin
+                if (ird[8])                       // dynamic bit
+                    row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13;
+                else case (ird[ 11:9])
+                    'b000:   row = `ALU_ROW_14; // ori
+                    'b001:   row = `ALU_ROW_04; // andi
+                    'b010:   row = `ALU_ROW_05; // subi
+                    'b011:   row = `ALU_ROW_02; // addi
+                    'b100:   row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13;   // static bit
+                    'b101:   row = `ALU_ROW_13; // eori
+                    'b110:   row = `ALU_ROW_06; // cmpi
+                    default: row = 0;
+                    endcase
+                end
+
+        // MOVE
+        // move.b originally also rows 5 & 15. Only because IRD bit 14 is not decoded.
+        // It's the same for move the operations performed by MOVE.B
+
+        'h1,'h2,'h3:   row = `ALU_ROW_02;
+
+        'h5:
+            if (size11)
+               row = `ALU_ROW_15;                               // As originally and easier to decode
+            else
+                row = ird[8] ? `ALU_ROW_05 : `ALU_ROW_02;     // addq/subq
+        'h6:    row = 0;                        //bcc/bra/bsr
+        'h7:    row = `ALU_ROW_02;              // moveq
+        'h8:
+            if (size11)                     // div
+                row = `ALU_ROW_01;
+            else if (ird[8] & eaRdir)       // sbcd
+                row = `ALU_ROW_09;
+            else
+                row = `ALU_ROW_14;          // or
+        'h9:
+            if (ird[8] & ~size11 & eaRdir)
+                row = `ALU_ROW_10;          // subx
+            else
+                row = `ALU_ROW_05;          // sub/suba
+        'hb:
+            if (ird[8] & ~size11 & ~eaAdir)
+                row = `ALU_ROW_13;          // eor
+            else
+                row = `ALU_ROW_06;          // cmp/cmpa/cmpm
+        'hc:
+            if (size11)
+                row = `ALU_ROW_07;          // mul
+            else if (ird[8] & eaRdir)       // abcd
+                row = `ALU_ROW_03;
+            else
+                row = `ALU_ROW_04;          // and
+        'hd:
+            if (ird[8] & ~size11 & eaRdir)
+                row = `ALU_ROW_12;          // addx
+            else
+                row = `ALU_ROW_02;          // add/adda
+        'he:
+            begin
+                reg [1:0] stype;
+
+                if (size11)                 // memory shift/rotate
+                    stype = ird[ 10:9];
+                else                        // register shift/rotate
+                    stype = ird[ 4:3];
+
+                case ({stype, ird[8]})
+                0: row = `ALU_ROW_02;   // ASR
+                1: row = `ALU_ROW_03;   // ASL
+                2: row = `ALU_ROW_05;   // LSR
+                3: row = `ALU_ROW_04;   // LSL
+                4: row = `ALU_ROW_08;   // ROXR
+                5: row = `ALU_ROW_11;   // ROXL
+                6: row = `ALU_ROW_10;   // ROR
+                7: row = `ALU_ROW_09;   // ROL
+                endcase
+            end
+
+        default:    row = 0;
+        endcase
+    end
+
+    // Decode opcodes that don't affect flags
+    // ADDA/SUBA ADDQ/SUBQ MOVEA
+
+    assign noCcrEn =
+        // ADDA/SUBA
+        ( ird[15] & ~ird[13] & ird[12] & size11) |
+        // ADDQ/SUBQ to An
+        ( (ird[15:12] == 4'h5) & eaAdir) |
+        // MOVEA
+        ( (~ird[15] & ~ird[14] & ird[13]) & ird[8:6] == 3'b001);
+
 endmodule
 
 // Row/col CCR update table
-module ccrTable( 
-	input [2:0] col, input [15:0] row, input finish,
-	output logic [MASK_NBITS-1:0] ccrMask);
-    
-	localparam
-		KNZ00 = 5'b01111,   // ok coz operators clear them
-		KKZKK = 5'b00100,
-		KNZKK = 5'b01100,
-		KNZ10 = 5'b01111,	// Used by OP_EXT on divison overflow
-		KNZ0C = 5'b01111,	// Used by DIV. V should be 0, but it is ok:
-							// DIVU: ends with quotient - 0, so V & C always clear.
-							// DIVS: ends with 1i (AND), again, V & C always clear.
-
-		KNZVC	= 5'b01111,
-		XNKVC	= 5'b11011,	// Used by BCD instructions. Don't modify Z at all at the binary operation. Only at the BCD correction cycle
-		
-		CUPDALL = 5'b11111,
-		CUNUSED = 5'bxxxxx;
-    
-
-	logic [MASK_NBITS-1:0] ccrMask1;
-
-	always_comb begin
-		unique case( col)
-		1:			ccrMask = ccrMask1;
-		
-		2,3:
-			unique case( 1'b1)
-			row[1]:		ccrMask = KNZ0C;		// DIV, used as 3n in col3
-			
-			row[3],								// ABCD
-			row[9]:								// SBCD/NBCD
-						ccrMask = (col == 2) ? XNKVC : CUPDALL;
-			
-			row[2],
-			row[5],
-			row[10],							// SUBX/NEGX
-			row[12]:	ccrMask = CUPDALL;		// ADDX
-			
-			row[6],								// CMP
-			row[7],								// MUL		
-			row[11]:	ccrMask = KNZVC;		// NOT
-			row[4],
-			row[8],								// Not used in col 3
-			row[13],
-			row[14]:	ccrMask = KNZ00;
-			row[15]:	ccrMask = 5'b0;			// TAS/Scc, not used in col 3
-			// default:	ccrMask = CUNUSED;
-			endcase			
-			
-		4:
-			unique case( row)
-			// 1: DIV, only n (4n & 6n)
-			// 14: BCLR 4n
-			// 6,12,13,15	// not used
-			`ALU_ROW_02,
-			`ALU_ROW_03,							// ASL    (originally ANZVA)
-			`ALU_ROW_04,
-			`ALU_ROW_05:	ccrMask = CUPDALL;		// Shifts (originally ANZ0A)
-			
-			`ALU_ROW_07:	ccrMask = KNZ00;		// MUL (originally KNZ0A)
-			`ALU_ROW_09,
-			`ALU_ROW_10:	ccrMask = KNZ00;		// RO[lr] (originally KNZ0A)
-			`ALU_ROW_08,							// ROXR (originally ANZ0A)
-			`ALU_ROW_11:	ccrMask = CUPDALL;		// ROXL (originally ANZ0A)
-			default:	ccrMask = CUNUSED;
-			endcase
-		
-		5:			ccrMask = row[1] ? KNZ10 : 5'b0;
-		default:	ccrMask = CUNUSED;
-		endcase
-	end
-
-	// Column 1 (AND)      
-	always_comb begin
-		if( finish)
-			ccrMask1 = row[7] ? KNZ00 : KNZKK;
-		else
-			ccrMask1 = row[13] | row[14] ? KKZKK : KNZ00;
-	end
-    
+module ccrTable
+(
+    input  [2:0] col,
+    input [15:0] row,
+    input        finish,
+    output logic [MASK_NBITS-1:0] ccrMask
+);
+
+    localparam
+        KNZ00 = 5'b01111,   // ok coz operators clear them
+        KKZKK = 5'b00100,
+        KNZKK = 5'b01100,
+        KNZ10 = 5'b01111,   // Used by OP_EXT on divison overflow
+        KNZ0C = 5'b01111,   // Used by DIV. V should be 0, but it is ok:
+                            // DIVU: ends with quotient - 0, so V & C always clear.
+                            // DIVS: ends with 1i (AND), again, V & C always clear.
+
+        KNZVC   = 5'b01111,
+        XNKVC   = 5'b11011, // Used by BCD instructions. Don't modify Z at all at the binary operation. Only at the BCD correction cycle
+
+        CUPDALL = 5'b11111,
+        CUNUSED = 5'bxxxxx;
+
+
+    logic [MASK_NBITS-1:0] ccrMask1;
+
+    always_comb begin
+        unique case (col)
+        1:          ccrMask = ccrMask1;
+
+        2,3:
+            unique case (1'b1)
+            row[1]:     ccrMask = KNZ0C;        // DIV, used as 3n in col3
+
+            row[3],                             // ABCD
+            row[9]:                             // SBCD/NBCD
+                        ccrMask = (col == 2) ? XNKVC : CUPDALL;
+
+            row[2],
+            row[5],
+            row[10],                            // SUBX/NEGX
+            row[12]:    ccrMask = CUPDALL;      // ADDX
+
+            row[6],                             // CMP
+            row[7],                             // MUL
+            row[11]:    ccrMask = KNZVC;        // NOT
+            row[4],
+            row[8],                             // Not used in col 3
+            row[13],
+            row[14]:    ccrMask = KNZ00;
+            row[15]:    ccrMask = 5'b0;         // TAS/Scc, not used in col 3
+            // default: ccrMask = CUNUSED;
+            endcase
+
+        4:
+            unique case (row)
+            // 1: DIV, only n (4n & 6n)
+            // 14: BCLR 4n
+            // 6,12,13,15   // not used
+            `ALU_ROW_02,
+            `ALU_ROW_03,                            // ASL    (originally ANZVA)
+            `ALU_ROW_04,
+            `ALU_ROW_05:    ccrMask = CUPDALL;      // Shifts (originally ANZ0A)
+
+            `ALU_ROW_07:    ccrMask = KNZ00;        // MUL (originally KNZ0A)
+            `ALU_ROW_09,
+            `ALU_ROW_10:    ccrMask = KNZ00;        // RO[lr] (originally KNZ0A)
+            `ALU_ROW_08,                            // ROXR (originally ANZ0A)
+            `ALU_ROW_11:    ccrMask = CUPDALL;      // ROXL (originally ANZ0A)
+            default:    ccrMask = CUNUSED;
+            endcase
+
+        5:          ccrMask = row[1] ? KNZ10 : 5'b0;
+        default:    ccrMask = CUNUSED;
+        endcase
+    end
+
+    // Column 1 (AND)
+    always_comb begin
+        if (finish)
+            ccrMask1 = row[7] ? KNZ00 : KNZKK;
+        else
+            ccrMask1 = row[13] | row[14] ? KKZKK : KNZ00;
+    end
+
 endmodule
diff --git a/fx68k_pkg.sv b/fx68k_pkg.sv
new file mode 100644
index 0000000..52f6dae
--- /dev/null
+++ b/fx68k_pkg.sv
@@ -0,0 +1,160 @@
+`ifdef _FX68K_PKG_
+/* already included !! */
+`else
+`define _FX68K_PKG_
+
+package fx68k_pkg;
+
+localparam CF = 0, VF = 1, ZF = 2, NF = 3, XF = 4, SF = 13;
+
+localparam UADDR_WIDTH = 10;
+localparam UROM_WIDTH = 17;
+localparam UROM_DEPTH = 1024;
+
+localparam NADDR_WIDTH = 9;
+localparam NANO_WIDTH = 68;
+localparam NANO_DEPTH = 336;
+
+localparam
+    HALT1_NMA = 'h001,
+    RSTP0_NMA = 'h002,
+    BSER1_NMA = 'h003,
+    TRAC1_NMA = 'h1C0,
+    ITLX1_NMA = 'h1C4;
+
+localparam [3:0]
+    TVN_SPURIOUS  = 4'hC,
+    TVN_AUTOVEC   = 4'hD,
+    TVN_INTERRUPT = 4'hF;
+
+localparam NANO_DOB_DBD = 2'b01;
+localparam NANO_DOB_ADB = 2'b10;
+localparam NANO_DOB_ALU = 2'b11;
+
+localparam [3:0]
+    EA_Dn     = 4'h0, // Dn
+    EA_An     = 4'h1, // An
+    EA_Ind    = 4'h2, // (An)
+    EA_Post   = 4'h3, // (An)+
+    EA_Pre    = 4'h4, // -(An)
+    EA_Rel_An = 4'h5, // d16(An)
+    EA_Idx_An = 4'h6, // d8(An,Xn)
+    EA_Abs_W  = 4'h7, // xxxx.W
+    EA_Abs_L  = 4'h8, // xxxxxxxx.W
+    EA_Rel_PC = 4'h9, // d16(PC)
+    EA_Idx_PC = 4'hA, // d8(PC,Xn)
+    EA_Imm    = 4'hB, // #xx / #xxxx / #xxxxxxxx
+    EA_Inv    = 4'hC; // Invalid
+
+// Clocks, phases and resets
+typedef struct packed
+{
+	logic clk;
+	logic extReset;			// External sync reset on emulated system
+	logic pwrUp;			// Asserted together with reset on emulated system coldstart
+	logic enPhi1, enPhi2;	// Clock enables. Next cycle is PHI1 or PHI2
+} s_clks;
+
+// IRD decoded signals
+typedef struct packed
+{
+	logic isPcRel;
+	logic isTas;
+	logic implicitSp;
+	logic toCcr;
+	logic rxIsDt, ryIsDt;
+	logic rxIsUsp, rxIsMovem, movemPreDecr;
+	logic isByte;
+	logic isMovep;
+	logic [2:0] rx, ry;
+	logic rxIsAreg, ryIsAreg;
+	logic [15:0] ftuConst;
+	logic [5:0] macroTvn;
+	logic inhibitCcr;
+} s_irdecod;
+
+// Nano code decoded signals
+typedef struct packed
+{
+	logic permStart;
+	logic waitBusFinish;
+	logic isWrite;
+	logic busByte;
+	logic isRmc;
+	logic noLowByte, noHighByte;
+	
+	logic updTpend, clrTpend;
+	logic tvn2Ftu, const2Ftu;
+	logic ftu2Dbl, ftu2Abl;
+	logic abl2Pren, updPren;
+	logic inl2psw, ftu2Sr, sr2Ftu, ftu2Ccr, pswIToFtu;
+	logic ird2Ftu, ssw2Ftu;
+	logic initST;
+	logic Ir2Ird;
+	
+	logic auClkEn, noSpAlign;
+	logic [2:0] auCntrl;
+	logic todbin, toIrc;
+	logic dbl2Atl, abl2Atl, atl2Abl, atl2Dbl;
+	logic abh2Ath, dbh2Ath;
+	logic ath2Dbh, ath2Abh;
+	
+	logic db2Aob, ab2Aob, au2Aob;
+	logic aob2Ab, updSsw;
+	// logic adb2Dob, dbd2Dob, alu2Dob;
+	logic [1:0] dobCtrl;
+	
+	logic abh2reg, abl2reg;
+	logic reg2abl, reg2abh;
+	logic dbh2reg, dbl2reg;
+	logic reg2dbl, reg2dbh;
+	logic ssp, pchdbh, pcldbl, pclabl, pchabh;
+	
+	logic rxh2dbh, rxh2abh;
+	logic dbl2rxl, dbh2rxh;
+	logic rxl2db, rxl2ab;
+	logic abl2rxl, abh2rxh;
+	logic dbh2ryh, abh2ryh;
+	logic ryl2db, ryl2ab;
+	logic ryh2dbh, ryh2abh;
+	logic dbl2ryl, abl2ryl;
+	logic rz;
+	logic rxlDbl;
+	
+	logic [2:0] aluColumn;
+	logic [1:0] aluDctrl;
+	logic aluActrl;
+	logic aluInit, aluFinish;
+	logic abd2Dcr, dcr2Dbd;
+	logic dbd2Alue, alue2Dbd;
+	logic dbd2Alub, abd2Alub;
+	
+	logic alu2Dbd, alu2Abd;
+	logic au2Db, au2Ab, au2Pc;
+	logic dbin2Abd, dbin2Dbd;
+	logic extDbh, extAbh;
+	logic ablAbd, ablAbh;
+	logic dblDbd, dblDbh;
+	logic abdIsByte;
+} s_nanod;
+
+// EA decode
+function [3:0] eaDecode;
+    input [5:0] eaBits;
+    begin
+        unique casez (eaBits)
+            6'b111_000: eaDecode = EA_Abs_W;  // Absolute short
+            6'b111_001: eaDecode = EA_Abs_L;  // Absolute long
+            6'b111_010: eaDecode = EA_Rel_PC; // PC relative
+            6'b111_011: eaDecode = EA_Idx_PC; // PC indexed
+            6'b111_100: eaDecode = EA_Imm;    // Immediate
+            6'b111_101: eaDecode = EA_Inv;    // Invalid
+            6'b111_11?: eaDecode = EA_Inv;    // Invalid
+            default:    eaDecode = { 1'b0, eaBits[5:3] }; // Register based EAs
+        endcase
+    end
+endfunction
+
+endpackage
+
+`endif /* _FX68K_PKG_ */
diff --git a/uaddrPla.sv b/uaddrPla.sv
index e24e951..1c00f06 100644
--- a/uaddrPla.sv
+++ b/uaddrPla.sv
@@ -6,122 +6,117 @@
 
 `timescale 1 ns / 1 ns
 
-`define NMA_BITS   10
-
-`define SFTM1 'h3C7
-`define SRRW1 'h382
-`define SRIW1 'h381
-`define SRRL1 'h386
-`define SRIL1 'h385
-`define BSRI1 'h089
-`define BSRW1 'h0A9
-`define BBCI1 'h308
-`define BBCW1 'h068
-`define RLQL1 'h23B
-`define ADRW1 'h006
-`define PINW1 'h21C
-`define PDCW1 'h103
-`define ADSW1 'h1C2
-`define AIXW0 'h1E3
-`define ABWW1 'h00A
-`define ABLW1 'h1E2
-`define TRAP1 'h1D0
-`define LINK1 'h30B
-`define UNLK1 'h119
-`define LUSP1 'h2F5
-`define SUSP1 'h230
-`define TRPV1 'h06D
-`define RSET1 'h3A6
-`define B 'h363
-`define STOP1 'h3A2
-`define RTR1 'h12A
-`define RTS1 'h126
-
-
-module pla_lined(
-   input [3:0] movEa,
-   input [3:0] col,
+`ifdef _VLINT_
+`include "fx68k_pkg.sv"
+`endif /* _VLINT_ */
+
+import fx68k_pkg::*;
+
+module uaddrPla
+(
+    input                    [3:0] movEa,
+    input                    [3:0] col,
+    
+    input                   [15:0] opcode,
+    input                   [15:0] lineBmap,
+    
+    output                         palIll,
+    output logic [UADDR_WIDTH-1:0] plaA1,
+    output logic [UADDR_WIDTH-1:0] plaA2,
+    output logic [UADDR_WIDTH-1:0] plaA3
+);
 
-   input [15:0] opcode,
-   input [15:0] lineBmap,
+    wire [3:0] line  = opcode[15:12];
+    wire [2:0] row86 = opcode[8:6];
+    
+    logic            [15:0] arIll;
+    logic [UADDR_WIDTH-1:0] arA1[15:0];
+    logic [UADDR_WIDTH-1:0] arA23[15:0];
+    logic [UADDR_WIDTH-1:0] scA3;
+    
+    logic                   illMisc;
+    logic [UADDR_WIDTH-1:0] a1Misc;
    
-   output palIll,
-   output logic [`NMA_BITS-1:0] plaA1,
-   output logic [`NMA_BITS-1:0] plaA2,
-   output logic [`NMA_BITS-1:0] plaA3
-   );
-
-   wire [3:0] line = opcode[ 15:12];
-   wire [2:0] row86 = opcode[8:6];
-   
-   logic [15:0] arIll;
-   logic [`NMA_BITS-1:0] arA1[ 15:0];
-   logic [`NMA_BITS-1:0] arA23[ 15:0];
-   logic [`NMA_BITS-1:0] scA3;
-
-   logic illMisc;
-   logic [`NMA_BITS-1:0] a1Misc;
+    assign palIll = (| (arIll & lineBmap));
    
-   /*
-   reg [`NMA_BITS-1:0] lineMask[ 15:0];  
-   always_comb begin
-       integer i;
-       for( i = 0; i < 16; i = i + 1)
-         lineMask[i] = { 16{lineBmap[ i]}};
-   end
-   */
-
-   assign palIll = (| (arIll & lineBmap));
+    // Only line 0 has 3 subs
+    assign plaA1 = arA1[ line];
+    assign plaA2 = arA23[ line];
+    assign plaA3 = lineBmap[0] ? scA3 : arA23[ line];
    
-   // Only line 0 has 3 subs
-   assign plaA1 = arA1[ line];
-   assign plaA2 = arA23[ line];
-   assign plaA3 = lineBmap[0] ? scA3 : arA23[ line];
+`define SFTM1 10'h3C7
+`define SRRW1 10'h382
+`define SRIW1 10'h381
+`define SRRL1 10'h386
+`define SRIL1 10'h385
+`define BSRI1 10'h089
+`define BSRW1 10'h0A9
+`define BBCI1 10'h308
+`define BBCW1 10'h068
+`define RLQL1 10'h23B
+`define ADRW1 10'h006
+`define PINW1 10'h21C
+`define PDCW1 10'h103
+`define ADSW1 10'h1C2
+`define AIXW0 10'h1E3
+`define ABWW1 10'h00A
+`define ABLW1 10'h1E2
+`define TRAP1 10'h1D0
+`define LINK1 10'h30B
+`define UNLK1 10'h119
+`define LUSP1 10'h2F5
+`define SUSP1 10'h230
+`define TRPV1 10'h06D
+`define RSET1 10'h3A6
+`define B     10'h363
+`define STOP1 10'h3A2
+`define RTR1  10'h12A
+`define RTS1  10'h126
+`define UNDF  10'hXXX
    
-   
-   // Simple lines
-   always_comb begin
-      // Line 6: Branch
-      arIll[ 'h6] = 1'b0;
-      arA23[ 'h6] = 'X;
-      if( opcode[ 11:8] == 4'h1)
-         arA1[ 'h6] = (| opcode[7:0]) ? `BSRI1 : `BSRW1;
-      else
-         arA1[ 'h6] = (| opcode[7:0]) ? `BBCI1 : `BBCW1;
-                         
-      // Line 7: moveq
-      arIll[ 'h7] = opcode[ 8];
-      arA23[ 'h7] = 'X;
-      arA1[ 'h7] = `RLQL1;
-
-      // Line A & F      
-      arIll[ 'ha] = 1'b1;       arIll[ 'hf] = 1'b1;
-      arA1[ 'ha]  = 'X;         arA1[ 'hf]  = 'X;
-      arA23[ 'ha] = 'X;         arA23[ 'hf] = 'X;
-      
-   end   
+    // Simple lines
+    always_comb begin
+        // Line 6: Branch
+        arIll[ 'h6] = 1'b0;
+        arA23[ 'h6] = `UNDF;
+        if (opcode[ 11:8] == 4'b0001)
+            arA1[ 'h6] = (|opcode[7:0]) ? `BSRI1 : `BSRW1;
+        else
+            arA1[ 'h6] = (|opcode[7:0]) ? `BBCI1 : `BBCW1;
+        
+        // Line 7: moveq
+        arIll[ 'h7] = opcode[ 8];
+        arA23[ 'h7] = `UNDF;
+        arA1[ 'h7] = `RLQL1;
+        
+        // Line A & F      
+        arIll[ 'ha] = 1'b1;  arIll[ 'hf] = 1'b1;
+        arA1[ 'ha]  = `UNDF; arA1[ 'hf]  = `UNDF;
+        arA23[ 'ha] = `UNDF; arA23[ 'hf] = `UNDF;
+       
+    end   
 
    // Special lines
 
-   // Line e: shifts
+   // Line E: shifts
    always_comb begin
       if( ~opcode[11] & opcode[7] & opcode[6])
       begin
          arA23[ 'he] = `SFTM1;
          unique case( col)
-            2: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `ADRW1; end
-            3: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `PINW1; end
-            4: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `PDCW1; end
-            5: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `ADSW1; end
-            6: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `AIXW0; end
-            7: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `ABWW1; end
-            8: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `ABLW1; end
-            default: begin arIll[ 'he] = 1'b1; arA1[ 'he] = 'X; end
+            EA_Ind:    begin arIll[ 'he] = 1'b0; arA1[ 'he] = `ADRW1; end
+            EA_Post:   begin arIll[ 'he] = 1'b0; arA1[ 'he] = `PINW1; end
+            EA_Pre:    begin arIll[ 'he] = 1'b0; arA1[ 'he] = `PDCW1; end
+            EA_Rel_An: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `ADSW1; end
+            EA_Idx_An: begin arIll[ 'he] = 1'b0; arA1[ 'he] = `AIXW0; end
+            EA_Abs_W:  begin arIll[ 'he] = 1'b0; arA1[ 'he] = `ABWW1; end
+            EA_Abs_L:  begin arIll[ 'he] = 1'b0; arA1[ 'he] = `ABLW1; end
+            default:   begin arIll[ 'he] = 1'b1; arA1[ 'he] = `UNDF;  end
          endcase
       end
       else
       begin
-         arA23[ 'he] = 'X;
+         arA23[ 'he] = `UNDF;
          unique case( opcode[ 7:6])
          2'b00,
          2'b01: begin
@@ -132,7 +127,7 @@ module pla_lined(
                   arIll[ 'he] = 1'b0;
                   arA1[ 'he]  = opcode[ 5] ? `SRRL1 : `SRIL1;
               end
-         2'b11: begin arIll[ 'he] = 1'b1; arA1[ 'he]  = 'X; end
+         2'b11: begin arIll[ 'he] = 1'b1; arA1[ 'he]  = `UNDF; end
          endcase
       end
    end
@@ -157,10 +152,10 @@ module pla_lined(
          3'b011:   a1Misc = `RTR1;
          3'b111:   a1Misc = `RTR1;
          3'b101:   a1Misc = `RTS1;
-         default:  begin  illMisc = 1'b1; a1Misc = 'X; end
+         default:  begin  illMisc = 1'b1; a1Misc = `UNDF; end
          endcase
          
-      default:  begin  illMisc = 1'b1; a1Misc = 'X; end
+      default:  begin  illMisc = 1'b1; a1Misc = `UNDF; end
       endcase
    end
 
@@ -176,365 +171,365 @@ always_comb begin
 
 if( (opcode[11:6] & 'h1F) == 'h8) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1CC; scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1CC; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h37) == 'h0) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1CC; scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1CC; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h1F) == 'h9) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1CC; scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1CC; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h37) == 'h1) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1CC; scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1CC; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h1F) == 'hA) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h10C; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00B; scA3 = 'h29D; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00F; scA3 = 'h29D; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h179; scA3 = 'h29D; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1C6; scA3 = 'h29D; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E7; scA3 = 'h29D; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00E; scA3 = 'h29D; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E6; scA3 = 'h29D; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h10C; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00B; scA3 = 'h29D; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00F; scA3 = 'h29D; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h179; scA3 = 'h29D; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1C6; scA3 = 'h29D; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E7; scA3 = 'h29D; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00E; scA3 = 'h29D; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E6; scA3 = 'h29D; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h37) == 'h2) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h10C; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00B; scA3 = 'h29D; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00F; scA3 = 'h29D; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h179; scA3 = 'h29D; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1C6; scA3 = 'h29D; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E7; scA3 = 'h29D; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00E; scA3 = 'h29D; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E6; scA3 = 'h29D; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h10C; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00B; scA3 = 'h29D; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00F; scA3 = 'h29D; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h179; scA3 = 'h29D; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1C6; scA3 = 'h29D; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E7; scA3 = 'h29D; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00E; scA3 = 'h29D; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E6; scA3 = 'h29D; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h37) == 'h10) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h37) == 'h11) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h100; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h299; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h299; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h299; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h299; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h299; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h299; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h299; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h37) == 'h12) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h10C; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00B; scA3 = 'h29D; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00F; scA3 = 'h29D; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h179; scA3 = 'h29D; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1C6; scA3 = 'h29D; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E7; scA3 = 'h29D; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00E; scA3 = 'h29D; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E6; scA3 = 'h29D; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h10C; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00B; scA3 = 'h29D; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00F; scA3 = 'h29D; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h179; scA3 = 'h29D; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1C6; scA3 = 'h29D; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E7; scA3 = 'h29D; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00E; scA3 = 'h29D; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E6; scA3 = 'h29D; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h7) == 'h4) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E7; arA23[ 'h0] = 'X;  scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1D2; arA23[ 'h0] = 'X;  scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h006; arA23[ 'h0] = 'X;  scA3 = 'h215; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h21C; arA23[ 'h0] = 'X;  scA3 = 'h215; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h103; arA23[ 'h0] = 'X;  scA3 = 'h215; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = 'X;  scA3 = 'h215; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = 'X;  scA3 = 'h215; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h00A; arA23[ 'h0] = 'X;  scA3 = 'h215; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E2; arA23[ 'h0] = 'X;  scA3 = 'h215; end
-     9: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = 'X;  scA3 = 'h215; end
-    10: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = 'X;  scA3 = 'h215; end
-    11: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h0EA; arA23[ 'h0] = 'h0AB; scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E7; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1D2; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h006; arA23[ 'h0] = `UNDF; scA3 = 'h215; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h21C; arA23[ 'h0] = `UNDF; scA3 = 'h215; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h103; arA23[ 'h0] = `UNDF; scA3 = 'h215; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = `UNDF; scA3 = 'h215; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = `UNDF; scA3 = 'h215; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h00A; arA23[ 'h0] = `UNDF; scA3 = 'h215; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E2; arA23[ 'h0] = `UNDF; scA3 = 'h215; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = `UNDF; scA3 = 'h215; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = `UNDF; scA3 = 'h215; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h0EA; arA23[ 'h0] = 'h0AB; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h7) == 'h5) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3EF; arA23[ 'h0] = 'X;  scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1D6; arA23[ 'h0] = 'X;  scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h006; arA23[ 'h0] = 'X;  scA3 = 'h081; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h21C; arA23[ 'h0] = 'X;  scA3 = 'h081; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h103; arA23[ 'h0] = 'X;  scA3 = 'h081; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = 'X;  scA3 = 'h081; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = 'X;  scA3 = 'h081; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h00A; arA23[ 'h0] = 'X;  scA3 = 'h081; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E2; arA23[ 'h0] = 'X;  scA3 = 'h081; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3EF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1D6; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h006; arA23[ 'h0] = `UNDF; scA3 = 'h081; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h21C; arA23[ 'h0] = `UNDF; scA3 = 'h081; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h103; arA23[ 'h0] = `UNDF; scA3 = 'h081; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = `UNDF; scA3 = 'h081; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = `UNDF; scA3 = 'h081; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h00A; arA23[ 'h0] = `UNDF; scA3 = 'h081; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E2; arA23[ 'h0] = `UNDF; scA3 = 'h081; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h7) == 'h7) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3EF; arA23[ 'h0] = 'X;  scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1CE; arA23[ 'h0] = 'X;  scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h006; arA23[ 'h0] = 'X;  scA3 = 'h081; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h21C; arA23[ 'h0] = 'X;  scA3 = 'h081; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h103; arA23[ 'h0] = 'X;  scA3 = 'h081; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = 'X;  scA3 = 'h081; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = 'X;  scA3 = 'h081; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h00A; arA23[ 'h0] = 'X;  scA3 = 'h081; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E2; arA23[ 'h0] = 'X;  scA3 = 'h081; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3EF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1CE; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h006; arA23[ 'h0] = `UNDF; scA3 = 'h081; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h21C; arA23[ 'h0] = `UNDF; scA3 = 'h081; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h103; arA23[ 'h0] = `UNDF; scA3 = 'h081; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = `UNDF; scA3 = 'h081; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = `UNDF; scA3 = 'h081; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h00A; arA23[ 'h0] = `UNDF; scA3 = 'h081; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E2; arA23[ 'h0] = `UNDF; scA3 = 'h081; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h7) == 'h6) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3EB; arA23[ 'h0] = 'X;  scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1CA; arA23[ 'h0] = 'X;  scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h006; arA23[ 'h0] = 'X;  scA3 = 'h069; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h21C; arA23[ 'h0] = 'X;  scA3 = 'h069; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h103; arA23[ 'h0] = 'X;  scA3 = 'h069; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = 'X;  scA3 = 'h069; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = 'X;  scA3 = 'h069; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h00A; arA23[ 'h0] = 'X;  scA3 = 'h069; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E2; arA23[ 'h0] = 'X;  scA3 = 'h069; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3EB; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1CA; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h006; arA23[ 'h0] = `UNDF; scA3 = 'h069; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h21C; arA23[ 'h0] = `UNDF; scA3 = 'h069; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h103; arA23[ 'h0] = `UNDF; scA3 = 'h069; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1C2; arA23[ 'h0] = `UNDF; scA3 = 'h069; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E3; arA23[ 'h0] = `UNDF; scA3 = 'h069; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h00A; arA23[ 'h0] = `UNDF; scA3 = 'h069; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h1E2; arA23[ 'h0] = `UNDF; scA3 = 'h069; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h20) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h3E7; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h215; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h215; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h215; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h215; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h215; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h215; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h215; end
-     9: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h215; end
-    10: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h215; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h3E7; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h215; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h215; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h215; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h215; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h215; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h215; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h215; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h215; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h215; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h21) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h3EF; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h081; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h081; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h081; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h081; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h081; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h081; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h081; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h3EF; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h081; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h081; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h081; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h081; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h081; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h081; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h081; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h23) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h3EF; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h081; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h081; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h081; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h081; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h081; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h081; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h081; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h3EF; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h081; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h081; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h081; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h081; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h081; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h081; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h081; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h22) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h3EB; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h069; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h069; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h069; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h069; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h069; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h069; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h069; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h3EB; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h069; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h069; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h069; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h069; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h069; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h069; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h069; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h30) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h108; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h087; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h087; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h087; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h087; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h087; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h087; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h087; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h108; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h087; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h087; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h087; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h087; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h087; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h087; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h087; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h31) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h108; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h087; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h087; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h087; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h087; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h087; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h087; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h087; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h108; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h006; scA3 = 'h087; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h21C; scA3 = 'h087; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h103; scA3 = 'h087; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1C2; scA3 = 'h087; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E3; scA3 = 'h087; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h00A; scA3 = 'h087; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h2B9; arA23[ 'h0] = 'h1E2; scA3 = 'h087; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h32) begin
     unique case ( col)
-     0: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h104; scA3 = 'X; end
-     1: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-     2: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00B; scA3 = 'h08F; end
-     3: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00F; scA3 = 'h08F; end
-     4: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h179; scA3 = 'h08F; end
-     5: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1C6; scA3 = 'h08F; end
-     6: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E7; scA3 = 'h08F; end
-     7: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00E; scA3 = 'h08F; end
-     8: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E6; scA3 = 'h08F; end
-     9: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    10: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    11: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
-    default: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X;    scA3 = 'X; end
+    EA_Dn:     begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h104; scA3 = `UNDF; end
+    EA_An:     begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Ind:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00B; scA3 = 'h08F; end
+    EA_Post:   begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00F; scA3 = 'h08F; end
+    EA_Pre:    begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h179; scA3 = 'h08F; end
+    EA_Rel_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1C6; scA3 = 'h08F; end
+    EA_Idx_An: begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E7; scA3 = 'h08F; end
+    EA_Abs_W:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h00E; scA3 = 'h08F; end
+    EA_Abs_L:  begin arIll[ 'h0] = 1'b0; arA1[ 'h0] = 'h3E0; arA23[ 'h0] = 'h1E6; scA3 = 'h08F; end
+    EA_Rel_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    EA_Imm:    begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
+    default:   begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
     endcase
 end
 
-else begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = 'X   ; arA23[ 'h0] = 'X; scA3 = 'X; end
+else begin arIll[ 'h0] = 1'b1; arA1[ 'h0] = `UNDF; arA23[ 'h0] = `UNDF; scA3 = `UNDF; end
 
 end
 
@@ -546,351 +541,351 @@ always_comb begin
 
 if( (opcode[11:6] & 'h27) == 'h0) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h133; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h2B8; end
-     3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h2B8; end
-     4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h2B8; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h2B8; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h2B8; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h2B8; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h2B8; end
-     9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h133; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h2B8; end
+    EA_Post:   begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h2B8; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h2B8; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h2B8; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h2B8; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h2B8; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h2B8; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h27) == 'h1) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h133; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h2B8; end
-     3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h2B8; end
-     4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h2B8; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h2B8; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h2B8; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h2B8; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h2B8; end
-     9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h133; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h2B8; end
+    EA_Post:   begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h2B8; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h2B8; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h2B8; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h2B8; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h2B8; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h2B8; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h27) == 'h2) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h137; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00B; arA23[ 'h4] = 'h2BC; end
-     3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00F; arA23[ 'h4] = 'h2BC; end
-     4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h179; arA23[ 'h4] = 'h2BC; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C6; arA23[ 'h4] = 'h2BC; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E7; arA23[ 'h4] = 'h2BC; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00E; arA23[ 'h4] = 'h2BC; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E6; arA23[ 'h4] = 'h2BC; end
-     9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h137; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00B; arA23[ 'h4] = 'h2BC; end
+    EA_Post:   begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00F; arA23[ 'h4] = 'h2BC; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h179; arA23[ 'h4] = 'h2BC; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C6; arA23[ 'h4] = 'h2BC; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E7; arA23[ 'h4] = 'h2BC; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00E; arA23[ 'h4] = 'h2BC; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E6; arA23[ 'h4] = 'h2BC; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h3) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A5; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h3A1; end
-     3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h3A1; end
-     4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h3A1; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h3A1; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h3A1; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h3A1; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h3A1; end
-     9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A5; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h3A1; end
+    EA_Post:   begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h3A1; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h3A1; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h3A1; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h3A1; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h3A1; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h3A1; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h13) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h301; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h159; end
-     3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h159; end
-     4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h159; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h159; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h159; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h159; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h159; end
-     9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h159; end
-    10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h159; end
-    11: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h0EA; arA23[ 'h4] = 'h301; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h301; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h159; end
+    EA_Post:   begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h159; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h159; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h159; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h159; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h159; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h159; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h159; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h159; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h0EA; arA23[ 'h4] = 'h301; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h1B) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h301; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h159; end
-     3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h159; end
-     4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h159; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h159; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h159; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h159; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h159; end
-     9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h159; end
-    10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h159; end
-    11: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h0EA; arA23[ 'h4] = 'h301; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h301; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h159; end
+    EA_Post:   begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h159; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h159; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h159; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h159; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h159; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h159; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h159; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h159; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h0EA; arA23[ 'h4] = 'h301; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h20) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h13B; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h15C; end
-     3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h15C; end
-     4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h15C; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h15C; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h15C; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h15C; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h15C; end
-     9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h13B; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h15C; end
+    EA_Post:   begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h15C; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h15C; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h15C; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h15C; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h15C; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h15C; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h21) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h341; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h17C; arA23[ 'h4] = 'X; end
-     3: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     4: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h17D; arA23[ 'h4] = 'X; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FF; arA23[ 'h4] = 'X; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h178; arA23[ 'h4] = 'X; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FA; arA23[ 'h4] = 'X; end
-     9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h17D; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FF; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h341; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h17C; arA23[ 'h4] = `UNDF; end
+    EA_Post:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h17D; arA23[ 'h4] = `UNDF; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FF; arA23[ 'h4] = `UNDF; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h178; arA23[ 'h4] = `UNDF; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FA; arA23[ 'h4] = `UNDF; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h17D; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FF; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h22) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h133; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A0; arA23[ 'h4] = 'X; end
-     3: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A4; arA23[ 'h4] = 'X; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F1; arA23[ 'h4] = 'X; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h325; arA23[ 'h4] = 'X; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1ED; arA23[ 'h4] = 'X; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E5; arA23[ 'h4] = 'X; end
-     9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h133; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A0; arA23[ 'h4] = `UNDF; end
+    EA_Post:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A4; arA23[ 'h4] = `UNDF; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F1; arA23[ 'h4] = `UNDF; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h325; arA23[ 'h4] = `UNDF; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1ED; arA23[ 'h4] = `UNDF; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E5; arA23[ 'h4] = `UNDF; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h23) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h232; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A0; arA23[ 'h4] = 'X; end
-     3: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A4; arA23[ 'h4] = 'X; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F1; arA23[ 'h4] = 'X; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h325; arA23[ 'h4] = 'X; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1ED; arA23[ 'h4] = 'X; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E5; arA23[ 'h4] = 'X; end
-     9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h232; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A0; arA23[ 'h4] = `UNDF; end
+    EA_Post:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3A4; arA23[ 'h4] = `UNDF; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F1; arA23[ 'h4] = `UNDF; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h325; arA23[ 'h4] = `UNDF; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1ED; arA23[ 'h4] = `UNDF; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E5; arA23[ 'h4] = `UNDF; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h28) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h12D; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h3C3; end
-     3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h3C3; end
-     4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h3C3; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h3C3; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h3C3; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h3C3; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h3C3; end
-     9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h12D; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h3C3; end
+    EA_Post:   begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h3C3; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h3C3; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h3C3; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h3C3; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h3C3; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h3C3; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h29) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h12D; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h3C3; end
-     3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h3C3; end
-     4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h3C3; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h3C3; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h3C3; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h3C3; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h3C3; end
-     9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h12D; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h3C3; end
+    EA_Post:   begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h3C3; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h3C3; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h3C3; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h3C3; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h3C3; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h3C3; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h2A) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h125; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00B; arA23[ 'h4] = 'h3CB; end
-     3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00F; arA23[ 'h4] = 'h3CB; end
-     4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h179; arA23[ 'h4] = 'h3CB; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C6; arA23[ 'h4] = 'h3CB; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E7; arA23[ 'h4] = 'h3CB; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00E; arA23[ 'h4] = 'h3CB; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E6; arA23[ 'h4] = 'h3CB; end
-     9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h125; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00B; arA23[ 'h4] = 'h3CB; end
+    EA_Post:   begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00F; arA23[ 'h4] = 'h3CB; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h179; arA23[ 'h4] = 'h3CB; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C6; arA23[ 'h4] = 'h3CB; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E7; arA23[ 'h4] = 'h3CB; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00E; arA23[ 'h4] = 'h3CB; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E6; arA23[ 'h4] = 'h3CB; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h2B) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h345; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h343; end
-     3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h343; end
-     4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h343; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h343; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h343; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h343; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h343; end
-     9: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h345; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h343; end
+    EA_Post:   begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h343; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h343; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h343; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h343; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h343; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h343; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h3E) == 'h32) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h127; arA23[ 'h4] = 'X; end
-     3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h123; arA23[ 'h4] = 'X; end
-     4: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FD; arA23[ 'h4] = 'X; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F5; arA23[ 'h4] = 'X; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F9; arA23[ 'h4] = 'X; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E9; arA23[ 'h4] = 'X; end
-     9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FD; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F5; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h127; arA23[ 'h4] = `UNDF; end
+    EA_Post:   begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h123; arA23[ 'h4] = `UNDF; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FD; arA23[ 'h4] = `UNDF; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F5; arA23[ 'h4] = `UNDF; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F9; arA23[ 'h4] = `UNDF; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E9; arA23[ 'h4] = `UNDF; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FD; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F5; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h7) == 'h6) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h152; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h151; end
-     3: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h151; end
-     4: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h151; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h151; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h151; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h151; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h151; end
-     9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h151; end
-    10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h151; end
-    11: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h0EA; arA23[ 'h4] = 'h152; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h152; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h006; arA23[ 'h4] = 'h151; end
+    EA_Post:   begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h21C; arA23[ 'h4] = 'h151; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h103; arA23[ 'h4] = 'h151; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h151; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h151; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h00A; arA23[ 'h4] = 'h151; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E2; arA23[ 'h4] = 'h151; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1C2; arA23[ 'h4] = 'h151; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1E3; arA23[ 'h4] = 'h151; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h0EA; arA23[ 'h4] = 'h152; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( (opcode[11:6] & 'h7) == 'h7) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2F1; arA23[ 'h4] = 'X; end
-     3: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     4: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2F2; arA23[ 'h4] = 'X; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FB; arA23[ 'h4] = 'X; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h275; arA23[ 'h4] = 'X; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3E4; arA23[ 'h4] = 'X; end
-     9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2F2; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FB; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2F1; arA23[ 'h4] = `UNDF; end
+    EA_Post:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2F2; arA23[ 'h4] = `UNDF; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FB; arA23[ 'h4] = `UNDF; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h275; arA23[ 'h4] = `UNDF; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h3E4; arA23[ 'h4] = `UNDF; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2F2; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1FB; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h3A) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h273; arA23[ 'h4] = 'X; end
-     3: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     4: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2B0; arA23[ 'h4] = 'X; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F3; arA23[ 'h4] = 'X; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h293; arA23[ 'h4] = 'X; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F2; arA23[ 'h4] = 'X; end
-     9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2B0; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F3; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h273; arA23[ 'h4] = `UNDF; end
+    EA_Post:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2B0; arA23[ 'h4] = `UNDF; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F3; arA23[ 'h4] = `UNDF; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h293; arA23[ 'h4] = `UNDF; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F2; arA23[ 'h4] = `UNDF; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2B0; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F3; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h3B) begin
     unique case ( col)
-     0: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     1: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     2: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h255; arA23[ 'h4] = 'X; end
-     3: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     4: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-     5: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2B4; arA23[ 'h4] = 'X; end
-     6: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F7; arA23[ 'h4] = 'X; end
-     7: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h297; arA23[ 'h4] = 'X; end
-     8: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F6; arA23[ 'h4] = 'X; end
-     9: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2B4; arA23[ 'h4] = 'X; end
-    10: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F7; arA23[ 'h4] = 'X; end
-    11: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
-    default: begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+    EA_Dn:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_An:     begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h255; arA23[ 'h4] = `UNDF; end
+    EA_Post:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Pre:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    EA_Rel_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2B4; arA23[ 'h4] = `UNDF; end
+    EA_Idx_An: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F7; arA23[ 'h4] = `UNDF; end
+    EA_Abs_W:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h297; arA23[ 'h4] = `UNDF; end
+    EA_Abs_L:  begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F6; arA23[ 'h4] = `UNDF; end
+    EA_Rel_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h2B4; arA23[ 'h4] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h4] = 1'b0; arA1[ 'h4] = 'h1F7; arA23[ 'h4] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
+    default:   begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
     endcase
 end
 
 else if( opcode[11:6] == 'h39) begin
-     arIll[ 'h4] = illMisc; arA1[ 'h4] = a1Misc   ; arA23[ 'h4] = 'X;
+     arIll[ 'h4] = illMisc; arA1[ 'h4] = a1Misc   ; arA23[ 'h4] = `UNDF;
 end
 
-else begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = 'X   ; arA23[ 'h4] = 'X; end
+else begin arIll[ 'h4] = 1'b1; arA1[ 'h4] = `UNDF; arA23[ 'h4] = `UNDF; end
 
 end
 
@@ -903,140 +898,140 @@ unique case( movEa)
 
 0: // Row: 0
     unique case ( col)
-     0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h121; arA23[ 'h1] = 'X; end
-     1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
-     2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h29B; end
-     3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h29B; end
-     4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h29B; end
-     5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h29B; end
-     6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h29B; end
-     7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h29B; end
-     8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h29B; end
-     9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h29B; end
-    10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h29B; end
-    11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h121; end
-    default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
+    EA_Dn:     begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h121; arA23[ 'h1] = `UNDF; end
+    EA_An:     begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h29B; end
+    EA_Post:   begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h29B; end
+    EA_Pre:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h29B; end
+    EA_Rel_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h29B; end
+    EA_Idx_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h29B; end
+    EA_Abs_W:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h29B; end
+    EA_Abs_L:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h29B; end
+    EA_Rel_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h29B; end
+    EA_Idx_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h29B; end
+    EA_Imm:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h121; end
+    default:   begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
     endcase
 
 2: // Row: 2
     unique case ( col)
-     0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2FA; arA23[ 'h1] = 'X; end
-     1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
-     2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h3AB; end
-     3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h3AB; end
-     4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h3AB; end
-     5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h3AB; end
-     6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h3AB; end
-     7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h3AB; end
-     8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h3AB; end
-     9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h3AB; end
-    10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h3AB; end
-    11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2FA; end
-    default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
+    EA_Dn:     begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2FA; arA23[ 'h1] = `UNDF; end
+    EA_An:     begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h3AB; end
+    EA_Post:   begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h3AB; end
+    EA_Pre:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h3AB; end
+    EA_Rel_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h3AB; end
+    EA_Idx_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h3AB; end
+    EA_Abs_W:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h3AB; end
+    EA_Abs_L:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h3AB; end
+    EA_Rel_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h3AB; end
+    EA_Idx_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h3AB; end
+    EA_Imm:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2FA; end
+    default:   begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
     endcase
 
 3: // Row: 3
     unique case ( col)
-     0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2FE; arA23[ 'h1] = 'X; end
-     1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
-     2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h3AF; end
-     3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h3AF; end
-     4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h3AF; end
-     5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h3AF; end
-     6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h3AF; end
-     7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h3AF; end
-     8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h3AF; end
-     9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h3AF; end
-    10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h3AF; end
-    11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2FE; end
-    default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
+    EA_Dn:     begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2FE; arA23[ 'h1] = `UNDF; end
+    EA_An:     begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h3AF; end
+    EA_Post:   begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h3AF; end
+    EA_Pre:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h3AF; end
+    EA_Rel_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h3AF; end
+    EA_Idx_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h3AF; end
+    EA_Abs_W:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h3AF; end
+    EA_Abs_L:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h3AF; end
+    EA_Rel_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h3AF; end
+    EA_Idx_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h3AF; end
+    EA_Imm:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2FE; end
+    default:   begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
     endcase
 
 4: // Row: 4
     unique case ( col)
-     0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2F8; arA23[ 'h1] = 'X; end
-     1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
-     2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h38B; end
-     3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h38B; end
-     4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h38B; end
-     5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h38B; end
-     6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h38B; end
-     7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h38B; end
-     8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h38B; end
-     9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h38B; end
-    10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h38B; end
-    11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2F8; end
-    default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
+    EA_Dn:     begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2F8; arA23[ 'h1] = `UNDF; end
+    EA_An:     begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h38B; end
+    EA_Post:   begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h38B; end
+    EA_Pre:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h38B; end
+    EA_Rel_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h38B; end
+    EA_Idx_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h38B; end
+    EA_Abs_W:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h38B; end
+    EA_Abs_L:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h38B; end
+    EA_Rel_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h38B; end
+    EA_Idx_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h38B; end
+    EA_Imm:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2F8; end
+    default:   begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
     endcase
 
 5: // Row: 5
     unique case ( col)
-     0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2DA; arA23[ 'h1] = 'X; end
-     1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
-     2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h38A; end
-     3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h38A; end
-     4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h38A; end
-     5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h38A; end
-     6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h38A; end
-     7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h38A; end
-     8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h38A; end
-     9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h38A; end
-    10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h38A; end
-    11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2DA; end
-    default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
+    EA_Dn:     begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2DA; arA23[ 'h1] = `UNDF; end
+    EA_An:     begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h38A; end
+    EA_Post:   begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h38A; end
+    EA_Pre:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h38A; end
+    EA_Rel_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h38A; end
+    EA_Idx_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h38A; end
+    EA_Abs_W:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h38A; end
+    EA_Abs_L:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h38A; end
+    EA_Rel_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h38A; end
+    EA_Idx_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h38A; end
+    EA_Imm:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2DA; end
+    default:   begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
     endcase
 
 6: // Row: 6
     unique case ( col)
-     0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1EB; arA23[ 'h1] = 'X; end
-     1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
-     2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h298; end
-     3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h298; end
-     4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h298; end
-     5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h298; end
-     6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h298; end
-     7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h298; end
-     8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h298; end
-     9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h298; end
-    10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h298; end
-    11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h1EB; end
-    default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
+    EA_Dn:     begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1EB; arA23[ 'h1] = `UNDF; end
+    EA_An:     begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h298; end
+    EA_Post:   begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h298; end
+    EA_Pre:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h298; end
+    EA_Rel_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h298; end
+    EA_Idx_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h298; end
+    EA_Abs_W:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h298; end
+    EA_Abs_L:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h298; end
+    EA_Rel_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h298; end
+    EA_Idx_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h298; end
+    EA_Imm:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h1EB; end
+    default:   begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
     endcase
 
 7: // Row: 7
     unique case ( col)
-     0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2D9; arA23[ 'h1] = 'X; end
-     1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
-     2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h388; end
-     3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h388; end
-     4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h388; end
-     5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h388; end
-     6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h388; end
-     7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h388; end
-     8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h388; end
-     9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h388; end
-    10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h388; end
-    11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2D9; end
-    default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
+    EA_Dn:     begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h2D9; arA23[ 'h1] = `UNDF; end
+    EA_An:     begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h388; end
+    EA_Post:   begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h388; end
+    EA_Pre:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h388; end
+    EA_Rel_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h388; end
+    EA_Idx_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h388; end
+    EA_Abs_W:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h388; end
+    EA_Abs_L:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h388; end
+    EA_Rel_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h388; end
+    EA_Idx_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h388; end
+    EA_Imm:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h2D9; end
+    default:   begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
     endcase
 
 8: // Row: 8
     unique case ( col)
-     0: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1EA; arA23[ 'h1] = 'X; end
-     1: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
-     2: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h32B; end
-     3: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h32B; end
-     4: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h32B; end
-     5: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h32B; end
-     6: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h32B; end
-     7: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h32B; end
-     8: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h32B; end
-     9: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h32B; end
-    10: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h32B; end
-    11: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h1EA; end
-    default: begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
-    endcase
-default:  begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = 'X   ; arA23[ 'h1] = 'X; end
+    EA_Dn:     begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1EA; arA23[ 'h1] = `UNDF; end
+    EA_An:     begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h006; arA23[ 'h1] = 'h32B; end
+    EA_Post:   begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h21C; arA23[ 'h1] = 'h32B; end
+    EA_Pre:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h103; arA23[ 'h1] = 'h32B; end
+    EA_Rel_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h32B; end
+    EA_Idx_An: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h32B; end
+    EA_Abs_W:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h00A; arA23[ 'h1] = 'h32B; end
+    EA_Abs_L:  begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E2; arA23[ 'h1] = 'h32B; end
+    EA_Rel_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1C2; arA23[ 'h1] = 'h32B; end
+    EA_Idx_PC: begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h1E3; arA23[ 'h1] = 'h32B; end
+    EA_Imm:    begin arIll[ 'h1] = 1'b0; arA1[ 'h1] = 'h0EA; arA23[ 'h1] = 'h1EA; end
+    default:   begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
+    endcase
+default:  begin arIll[ 'h1] = 1'b1; arA1[ 'h1] = `UNDF; arA23[ 'h1] = `UNDF; end
 endcase
 
 //
@@ -1046,157 +1041,157 @@ unique case( movEa)
 
 0: // Row: 0
     unique case ( col)
-     0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h129; arA23[ 'h2] = 'X; end
-     1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h129; arA23[ 'h2] = 'X; end
-     2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h29F; end
-     3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h29F; end
-     4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h29F; end
-     5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29F; end
-     6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29F; end
-     7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h29F; end
-     8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h29F; end
-     9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29F; end
-    10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29F; end
-    11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h129; end
-    default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X   ; arA23[ 'h2] = 'X; end
+    EA_Dn:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h129; arA23[ 'h2] = `UNDF; end
+    EA_An:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h129; arA23[ 'h2] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h29F; end
+    EA_Post:   begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h29F; end
+    EA_Pre:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h29F; end
+    EA_Rel_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29F; end
+    EA_Idx_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29F; end
+    EA_Abs_W:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h29F; end
+    EA_Abs_L:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h29F; end
+    EA_Rel_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29F; end
+    EA_Idx_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29F; end
+    EA_Imm:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h129; end
+    default:   begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = `UNDF; arA23[ 'h2] = `UNDF; end
     endcase
 
 1: // Row: 1
     unique case ( col)
-     0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h129; arA23[ 'h2] = 'X; end
-     1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h129; arA23[ 'h2] = 'X; end
-     2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h29F; end
-     3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h29F; end
-     4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h29F; end
-     5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29F; end
-     6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29F; end
-     7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h29F; end
-     8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h29F; end
-     9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29F; end
-    10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29F; end
-    11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h129; end
-    default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X   ; arA23[ 'h2] = 'X; end
+    EA_Dn:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h129; arA23[ 'h2] = `UNDF; end
+    EA_An:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h129; arA23[ 'h2] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h29F; end
+    EA_Post:   begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h29F; end
+    EA_Pre:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h29F; end
+    EA_Rel_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29F; end
+    EA_Idx_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29F; end
+    EA_Abs_W:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h29F; end
+    EA_Abs_L:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h29F; end
+    EA_Rel_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29F; end
+    EA_Idx_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29F; end
+    EA_Imm:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h129; end
+    default:   begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = `UNDF; arA23[ 'h2] = `UNDF; end
     endcase
 
 2: // Row: 2
     unique case ( col)
-     0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2F9; arA23[ 'h2] = 'X; end
-     1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2F9; arA23[ 'h2] = 'X; end
-     2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h3A9; end
-     3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h3A9; end
-     4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h3A9; end
-     5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h3A9; end
-     6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h3A9; end
-     7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h3A9; end
-     8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h3A9; end
-     9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h3A9; end
-    10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h3A9; end
-    11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2F9; end
-    default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X   ; arA23[ 'h2] = 'X; end
+    EA_Dn:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2F9; arA23[ 'h2] = `UNDF; end
+    EA_An:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2F9; arA23[ 'h2] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h3A9; end
+    EA_Post:   begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h3A9; end
+    EA_Pre:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h3A9; end
+    EA_Rel_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h3A9; end
+    EA_Idx_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h3A9; end
+    EA_Abs_W:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h3A9; end
+    EA_Abs_L:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h3A9; end
+    EA_Rel_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h3A9; end
+    EA_Idx_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h3A9; end
+    EA_Imm:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2F9; end
+    default:   begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = `UNDF; arA23[ 'h2] = `UNDF; end
     endcase
 
 3: // Row: 3
     unique case ( col)
-     0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2FD; arA23[ 'h2] = 'X; end
-     1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2FD; arA23[ 'h2] = 'X; end
-     2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h3AD; end
-     3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h3AD; end
-     4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h3AD; end
-     5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h3AD; end
-     6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h3AD; end
-     7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h3AD; end
-     8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h3AD; end
-     9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h3AD; end
-    10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h3AD; end
-    11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2FD; end
-    default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X   ; arA23[ 'h2] = 'X; end
+    EA_Dn:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2FD; arA23[ 'h2] = `UNDF; end
+    EA_An:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2FD; arA23[ 'h2] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h3AD; end
+    EA_Post:   begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h3AD; end
+    EA_Pre:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h3AD; end
+    EA_Rel_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h3AD; end
+    EA_Idx_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h3AD; end
+    EA_Abs_W:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h3AD; end
+    EA_Abs_L:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h3AD; end
+    EA_Rel_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h3AD; end
+    EA_Idx_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h3AD; end
+    EA_Imm:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2FD; end
+    default:   begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = `UNDF; arA23[ 'h2] = `UNDF; end
     endcase
 
 4: // Row: 4
     unique case ( col)
-     0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2FC; arA23[ 'h2] = 'X; end
-     1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2FC; arA23[ 'h2] = 'X; end
-     2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h38F; end
-     3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h38F; end
-     4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h38F; end
-     5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38F; end
-     6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38F; end
-     7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h38F; end
-     8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h38F; end
-     9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38F; end
-    10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38F; end
-    11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2FC; end
-    default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X   ; arA23[ 'h2] = 'X; end
+    EA_Dn:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2FC; arA23[ 'h2] = `UNDF; end
+    EA_An:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2FC; arA23[ 'h2] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h38F; end
+    EA_Post:   begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h38F; end
+    EA_Pre:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h38F; end
+    EA_Rel_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38F; end
+    EA_Idx_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38F; end
+    EA_Abs_W:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h38F; end
+    EA_Abs_L:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h38F; end
+    EA_Rel_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38F; end
+    EA_Idx_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38F; end
+    EA_Imm:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2FC; end
+    default:   begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = `UNDF; arA23[ 'h2] = `UNDF; end
     endcase
 
 5: // Row: 5
     unique case ( col)
-     0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2DE; arA23[ 'h2] = 'X; end
-     1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2DE; arA23[ 'h2] = 'X; end
-     2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h38E; end
-     3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h38E; end
-     4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h38E; end
-     5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38E; end
-     6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38E; end
-     7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h38E; end
-     8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h38E; end
-     9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38E; end
-    10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38E; end
-    11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2DE; end
-    default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X   ; arA23[ 'h2] = 'X; end
+    EA_Dn:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2DE; arA23[ 'h2] = `UNDF; end
+    EA_An:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2DE; arA23[ 'h2] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h38E; end
+    EA_Post:   begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h38E; end
+    EA_Pre:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h38E; end
+    EA_Rel_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38E; end
+    EA_Idx_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38E; end
+    EA_Abs_W:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h38E; end
+    EA_Abs_L:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h38E; end
+    EA_Rel_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38E; end
+    EA_Idx_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38E; end
+    EA_Imm:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2DE; end
+    default:   begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = `UNDF; arA23[ 'h2] = `UNDF; end
     endcase
 
 6: // Row: 6
     unique case ( col)
-     0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1EF; arA23[ 'h2] = 'X; end
-     1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1EF; arA23[ 'h2] = 'X; end
-     2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h29C; end
-     3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h29C; end
-     4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h29C; end
-     5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29C; end
-     6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29C; end
-     7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h29C; end
-     8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h29C; end
-     9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29C; end
-    10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29C; end
-    11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h1EF; end
-    default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X   ; arA23[ 'h2] = 'X; end
+    EA_Dn:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1EF; arA23[ 'h2] = `UNDF; end
+    EA_An:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1EF; arA23[ 'h2] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h29C; end
+    EA_Post:   begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h29C; end
+    EA_Pre:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h29C; end
+    EA_Rel_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29C; end
+    EA_Idx_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29C; end
+    EA_Abs_W:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h29C; end
+    EA_Abs_L:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h29C; end
+    EA_Rel_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h29C; end
+    EA_Idx_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h29C; end
+    EA_Imm:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h1EF; end
+    default:   begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = `UNDF; arA23[ 'h2] = `UNDF; end
     endcase
 
 7: // Row: 7
     unique case ( col)
-     0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2DD; arA23[ 'h2] = 'X; end
-     1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2DD; arA23[ 'h2] = 'X; end
-     2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h38C; end
-     3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h38C; end
-     4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h38C; end
-     5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38C; end
-     6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38C; end
-     7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h38C; end
-     8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h38C; end
-     9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38C; end
-    10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38C; end
-    11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2DD; end
-    default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X   ; arA23[ 'h2] = 'X; end
+    EA_Dn:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2DD; arA23[ 'h2] = `UNDF; end
+    EA_An:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h2DD; arA23[ 'h2] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h38C; end
+    EA_Post:   begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h38C; end
+    EA_Pre:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h38C; end
+    EA_Rel_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38C; end
+    EA_Idx_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38C; end
+    EA_Abs_W:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h38C; end
+    EA_Abs_L:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h38C; end
+    EA_Rel_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h38C; end
+    EA_Idx_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h38C; end
+    EA_Imm:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h2DD; end
+    default:   begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = `UNDF; arA23[ 'h2] = `UNDF; end
     endcase
 
 8: // Row: 8
     unique case ( col)
-     0: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1EE; arA23[ 'h2] = 'X; end
-     1: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1EE; arA23[ 'h2] = 'X; end
-     2: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h30F; end
-     3: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h30F; end
-     4: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h30F; end
-     5: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h30F; end
-     6: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h30F; end
-     7: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h30F; end
-     8: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h30F; end
-     9: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h30F; end
-    10: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h30F; end
-    11: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h1EE; end
-    default: begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X   ; arA23[ 'h2] = 'X; end
-    endcase
-default:  begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = 'X   ; arA23[ 'h2] = 'X; end
+    EA_Dn:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1EE; arA23[ 'h2] = `UNDF; end
+    EA_An:     begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1EE; arA23[ 'h2] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00B; arA23[ 'h2] = 'h30F; end
+    EA_Post:   begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00F; arA23[ 'h2] = 'h30F; end
+    EA_Pre:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h179; arA23[ 'h2] = 'h30F; end
+    EA_Rel_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h30F; end
+    EA_Idx_An: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h30F; end
+    EA_Abs_W:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h00E; arA23[ 'h2] = 'h30F; end
+    EA_Abs_L:  begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E6; arA23[ 'h2] = 'h30F; end
+    EA_Rel_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1C6; arA23[ 'h2] = 'h30F; end
+    EA_Idx_PC: begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h1E7; arA23[ 'h2] = 'h30F; end
+    EA_Imm:    begin arIll[ 'h2] = 1'b0; arA1[ 'h2] = 'h0A7; arA23[ 'h2] = 'h1EE; end
+    default:   begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = `UNDF; arA23[ 'h2] = `UNDF; end
+    endcase
+default:  begin arIll[ 'h2] = 1'b1; arA1[ 'h2] = `UNDF; arA23[ 'h2] = `UNDF; end
 endcase
 
 //
@@ -1206,157 +1201,157 @@ unique case( movEa)
 
 0: // Row: 0
     unique case ( col)
-     0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h121; arA23[ 'h3] = 'X; end
-     1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h121; arA23[ 'h3] = 'X; end
-     2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h29B; end
-     3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h29B; end
-     4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h29B; end
-     5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h29B; end
-     6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h29B; end
-     7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h29B; end
-     8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h29B; end
-     9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h29B; end
-    10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h29B; end
-    11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h121; end
-    default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X   ; arA23[ 'h3] = 'X; end
+    EA_Dn:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h121; arA23[ 'h3] = `UNDF; end
+    EA_An:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h121; arA23[ 'h3] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h29B; end
+    EA_Post:   begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h29B; end
+    EA_Pre:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h29B; end
+    EA_Rel_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h29B; end
+    EA_Idx_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h29B; end
+    EA_Abs_W:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h29B; end
+    EA_Abs_L:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h29B; end
+    EA_Rel_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h29B; end
+    EA_Idx_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h29B; end
+    EA_Imm:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h121; end
+    default:   begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = `UNDF; arA23[ 'h3] = `UNDF; end
     endcase
 
 1: // Row: 1
     unique case ( col)
-     0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h279; arA23[ 'h3] = 'X; end
-     1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h279; arA23[ 'h3] = 'X; end
-     2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h158; end
-     3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h158; end
-     4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h158; end
-     5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h158; end
-     6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h158; end
-     7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h158; end
-     8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h158; end
-     9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h158; end
-    10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h158; end
-    11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h279; end
-    default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X   ; arA23[ 'h3] = 'X; end
+    EA_Dn:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h279; arA23[ 'h3] = `UNDF; end
+    EA_An:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h279; arA23[ 'h3] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h158; end
+    EA_Post:   begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h158; end
+    EA_Pre:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h158; end
+    EA_Rel_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h158; end
+    EA_Idx_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h158; end
+    EA_Abs_W:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h158; end
+    EA_Abs_L:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h158; end
+    EA_Rel_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h158; end
+    EA_Idx_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h158; end
+    EA_Imm:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h279; end
+    default:   begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = `UNDF; arA23[ 'h3] = `UNDF; end
     endcase
 
 2: // Row: 2
     unique case ( col)
-     0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2FA; arA23[ 'h3] = 'X; end
-     1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2FA; arA23[ 'h3] = 'X; end
-     2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h3AB; end
-     3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h3AB; end
-     4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h3AB; end
-     5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h3AB; end
-     6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h3AB; end
-     7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h3AB; end
-     8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h3AB; end
-     9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h3AB; end
-    10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h3AB; end
-    11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2FA; end
-    default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X   ; arA23[ 'h3] = 'X; end
+    EA_Dn:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2FA; arA23[ 'h3] = `UNDF; end
+    EA_An:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2FA; arA23[ 'h3] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h3AB; end
+    EA_Post:   begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h3AB; end
+    EA_Pre:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h3AB; end
+    EA_Rel_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h3AB; end
+    EA_Idx_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h3AB; end
+    EA_Abs_W:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h3AB; end
+    EA_Abs_L:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h3AB; end
+    EA_Rel_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h3AB; end
+    EA_Idx_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h3AB; end
+    EA_Imm:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2FA; end
+    default:   begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = `UNDF; arA23[ 'h3] = `UNDF; end
     endcase
 
 3: // Row: 3
     unique case ( col)
-     0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2FE; arA23[ 'h3] = 'X; end
-     1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2FE; arA23[ 'h3] = 'X; end
-     2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h3AF; end
-     3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h3AF; end
-     4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h3AF; end
-     5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h3AF; end
-     6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h3AF; end
-     7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h3AF; end
-     8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h3AF; end
-     9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h3AF; end
-    10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h3AF; end
-    11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2FE; end
-    default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X   ; arA23[ 'h3] = 'X; end
+    EA_Dn:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2FE; arA23[ 'h3] = `UNDF; end
+    EA_An:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2FE; arA23[ 'h3] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h3AF; end
+    EA_Post:   begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h3AF; end
+    EA_Pre:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h3AF; end
+    EA_Rel_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h3AF; end
+    EA_Idx_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h3AF; end
+    EA_Abs_W:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h3AF; end
+    EA_Abs_L:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h3AF; end
+    EA_Rel_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h3AF; end
+    EA_Idx_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h3AF; end
+    EA_Imm:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2FE; end
+    default:   begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = `UNDF; arA23[ 'h3] = `UNDF; end
     endcase
 
 4: // Row: 4
     unique case ( col)
-     0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2F8; arA23[ 'h3] = 'X; end
-     1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2F8; arA23[ 'h3] = 'X; end
-     2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h38B; end
-     3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h38B; end
-     4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h38B; end
-     5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h38B; end
-     6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h38B; end
-     7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h38B; end
-     8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h38B; end
-     9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h38B; end
-    10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h38B; end
-    11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2F8; end
-    default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X   ; arA23[ 'h3] = 'X; end
+    EA_Dn:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2F8; arA23[ 'h3] = `UNDF; end
+    EA_An:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2F8; arA23[ 'h3] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h38B; end
+    EA_Post:   begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h38B; end
+    EA_Pre:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h38B; end
+    EA_Rel_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h38B; end
+    EA_Idx_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h38B; end
+    EA_Abs_W:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h38B; end
+    EA_Abs_L:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h38B; end
+    EA_Rel_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h38B; end
+    EA_Idx_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h38B; end
+    EA_Imm:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2F8; end
+    default:   begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = `UNDF; arA23[ 'h3] = `UNDF; end
     endcase
 
 5: // Row: 5
     unique case ( col)
-     0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2DA; arA23[ 'h3] = 'X; end
-     1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2DA; arA23[ 'h3] = 'X; end
-     2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h38A; end
-     3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h38A; end
-     4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h38A; end
-     5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h38A; end
-     6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h38A; end
-     7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h38A; end
-     8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h38A; end
-     9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h38A; end
-    10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h38A; end
-    11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2DA; end
-    default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X   ; arA23[ 'h3] = 'X; end
+    EA_Dn:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2DA; arA23[ 'h3] = `UNDF; end
+    EA_An:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2DA; arA23[ 'h3] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h38A; end
+    EA_Post:   begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h38A; end
+    EA_Pre:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h38A; end
+    EA_Rel_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h38A; end
+    EA_Idx_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h38A; end
+    EA_Abs_W:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h38A; end
+    EA_Abs_L:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h38A; end
+    EA_Rel_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h38A; end
+    EA_Idx_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h38A; end
+    EA_Imm:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2DA; end
+    default:   begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = `UNDF; arA23[ 'h3] = `UNDF; end
     endcase
 
 6: // Row: 6
     unique case ( col)
-     0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1EB; arA23[ 'h3] = 'X; end
-     1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1EB; arA23[ 'h3] = 'X; end
-     2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h298; end
-     3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h298; end
-     4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h298; end
-     5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h298; end
-     6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h298; end
-     7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h298; end
-     8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h298; end
-     9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h298; end
-    10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h298; end
-    11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h1EB; end
-    default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X   ; arA23[ 'h3] = 'X; end
+    EA_Dn:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1EB; arA23[ 'h3] = `UNDF; end
+    EA_An:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1EB; arA23[ 'h3] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h298; end
+    EA_Post:   begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h298; end
+    EA_Pre:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h298; end
+    EA_Rel_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h298; end
+    EA_Idx_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h298; end
+    EA_Abs_W:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h298; end
+    EA_Abs_L:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h298; end
+    EA_Rel_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h298; end
+    EA_Idx_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h298; end
+    EA_Imm:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h1EB; end
+    default:   begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = `UNDF; arA23[ 'h3] = `UNDF; end
     endcase
 
 7: // Row: 7
     unique case ( col)
-     0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2D9; arA23[ 'h3] = 'X; end
-     1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2D9; arA23[ 'h3] = 'X; end
-     2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h388; end
-     3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h388; end
-     4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h388; end
-     5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h388; end
-     6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h388; end
-     7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h388; end
-     8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h388; end
-     9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h388; end
-    10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h388; end
-    11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2D9; end
-    default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X   ; arA23[ 'h3] = 'X; end
+    EA_Dn:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2D9; arA23[ 'h3] = `UNDF; end
+    EA_An:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h2D9; arA23[ 'h3] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h388; end
+    EA_Post:   begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h388; end
+    EA_Pre:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h388; end
+    EA_Rel_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h388; end
+    EA_Idx_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h388; end
+    EA_Abs_W:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h388; end
+    EA_Abs_L:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h388; end
+    EA_Rel_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h388; end
+    EA_Idx_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h388; end
+    EA_Imm:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h2D9; end
+    default:   begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = `UNDF; arA23[ 'h3] = `UNDF; end
     endcase
 
 8: // Row: 8
     unique case ( col)
-     0: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1EA; arA23[ 'h3] = 'X; end
-     1: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1EA; arA23[ 'h3] = 'X; end
-     2: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h32B; end
-     3: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h32B; end
-     4: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h32B; end
-     5: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h32B; end
-     6: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h32B; end
-     7: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h32B; end
-     8: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h32B; end
-     9: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h32B; end
-    10: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h32B; end
-    11: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h1EA; end
-    default: begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X   ; arA23[ 'h3] = 'X; end
-    endcase
-default:  begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = 'X   ; arA23[ 'h3] = 'X; end
+    EA_Dn:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1EA; arA23[ 'h3] = `UNDF; end
+    EA_An:     begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1EA; arA23[ 'h3] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h006; arA23[ 'h3] = 'h32B; end
+    EA_Post:   begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h21C; arA23[ 'h3] = 'h32B; end
+    EA_Pre:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h103; arA23[ 'h3] = 'h32B; end
+    EA_Rel_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h32B; end
+    EA_Idx_An: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h32B; end
+    EA_Abs_W:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h00A; arA23[ 'h3] = 'h32B; end
+    EA_Abs_L:  begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E2; arA23[ 'h3] = 'h32B; end
+    EA_Rel_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1C2; arA23[ 'h3] = 'h32B; end
+    EA_Idx_PC: begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h1E3; arA23[ 'h3] = 'h32B; end
+    EA_Imm:    begin arIll[ 'h3] = 1'b0; arA1[ 'h3] = 'h0EA; arA23[ 'h3] = 'h1EA; end
+    default:   begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = `UNDF; arA23[ 'h3] = `UNDF; end
+    endcase
+default:  begin arIll[ 'h3] = 1'b1; arA1[ 'h3] = `UNDF; arA23[ 'h3] = `UNDF; end
 endcase
 
 //
@@ -1366,114 +1361,114 @@ unique case( row86)
 
 3'b000: // Row: 0
     unique case ( col)
-     0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2D8; arA23[ 'h5] = 'X; end
-     1: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X   ; arA23[ 'h5] = 'X; end
-     2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h2F3; end
-     3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h2F3; end
-     4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h2F3; end
-     5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h2F3; end
-     6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h2F3; end
-     7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h2F3; end
-     8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h2F3; end
-    default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X   ; arA23[ 'h5] = 'X; end
+    EA_Dn:     begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2D8; arA23[ 'h5] = `UNDF; end
+    EA_An:     begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = `UNDF; arA23[ 'h5] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h2F3; end
+    EA_Post:   begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h2F3; end
+    EA_Pre:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h2F3; end
+    EA_Rel_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h2F3; end
+    EA_Idx_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h2F3; end
+    EA_Abs_W:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h2F3; end
+    EA_Abs_L:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h2F3; end
+    default:   begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = `UNDF; arA23[ 'h5] = `UNDF; end
     endcase
 
 3'b001: // Row: 1
     unique case ( col)
-     0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2D8; arA23[ 'h5] = 'X; end
-     1: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = 'X; end
-     2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h2F3; end
-     3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h2F3; end
-     4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h2F3; end
-     5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h2F3; end
-     6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h2F3; end
-     7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h2F3; end
-     8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h2F3; end
-    default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X   ; arA23[ 'h5] = 'X; end
+    EA_Dn:     begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2D8; arA23[ 'h5] = `UNDF; end
+    EA_An:     begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h2F3; end
+    EA_Post:   begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h2F3; end
+    EA_Pre:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h2F3; end
+    EA_Rel_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h2F3; end
+    EA_Idx_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h2F3; end
+    EA_Abs_W:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h2F3; end
+    EA_Abs_L:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h2F3; end
+    default:   begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = `UNDF; arA23[ 'h5] = `UNDF; end
     endcase
 
 3'b010: // Row: 2
     unique case ( col)
-     0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = 'X; end
-     1: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = 'X; end
-     2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00B; arA23[ 'h5] = 'h2F7; end
-     3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00F; arA23[ 'h5] = 'h2F7; end
-     4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h179; arA23[ 'h5] = 'h2F7; end
-     5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C6; arA23[ 'h5] = 'h2F7; end
-     6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E7; arA23[ 'h5] = 'h2F7; end
-     7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00E; arA23[ 'h5] = 'h2F7; end
-     8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E6; arA23[ 'h5] = 'h2F7; end
-    default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X   ; arA23[ 'h5] = 'X; end
+    EA_Dn:     begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = `UNDF; end
+    EA_An:     begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00B; arA23[ 'h5] = 'h2F7; end
+    EA_Post:   begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00F; arA23[ 'h5] = 'h2F7; end
+    EA_Pre:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h179; arA23[ 'h5] = 'h2F7; end
+    EA_Rel_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C6; arA23[ 'h5] = 'h2F7; end
+    EA_Idx_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E7; arA23[ 'h5] = 'h2F7; end
+    EA_Abs_W:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00E; arA23[ 'h5] = 'h2F7; end
+    EA_Abs_L:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E6; arA23[ 'h5] = 'h2F7; end
+    default:   begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = `UNDF; arA23[ 'h5] = `UNDF; end
     endcase
 
 3'b011: // Row: 3
     unique case ( col)
-     0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h384; arA23[ 'h5] = 'X; end
-     1: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h06C; arA23[ 'h5] = 'X; end
-     2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h380; end
-     3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h380; end
-     4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h380; end
-     5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h380; end
-     6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h380; end
-     7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h380; end
-     8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h380; end
-    default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X   ; arA23[ 'h5] = 'X; end
+    EA_Dn:     begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h384; arA23[ 'h5] = `UNDF; end
+    EA_An:     begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h06C; arA23[ 'h5] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h380; end
+    EA_Post:   begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h380; end
+    EA_Pre:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h380; end
+    EA_Rel_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h380; end
+    EA_Idx_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h380; end
+    EA_Abs_W:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h380; end
+    EA_Abs_L:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h380; end
+    default:   begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = `UNDF; arA23[ 'h5] = `UNDF; end
     endcase
 
 3'b100: // Row: 4
     unique case ( col)
-     0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2D8; arA23[ 'h5] = 'X; end
-     1: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X   ; arA23[ 'h5] = 'X; end
-     2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h2F3; end
-     3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h2F3; end
-     4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h2F3; end
-     5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h2F3; end
-     6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h2F3; end
-     7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h2F3; end
-     8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h2F3; end
-    default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X   ; arA23[ 'h5] = 'X; end
+    EA_Dn:     begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2D8; arA23[ 'h5] = `UNDF; end
+    EA_An:     begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = `UNDF; arA23[ 'h5] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h2F3; end
+    EA_Post:   begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h2F3; end
+    EA_Pre:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h2F3; end
+    EA_Rel_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h2F3; end
+    EA_Idx_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h2F3; end
+    EA_Abs_W:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h2F3; end
+    EA_Abs_L:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h2F3; end
+    default:   begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = `UNDF; arA23[ 'h5] = `UNDF; end
     endcase
 
 3'b101: // Row: 5
     unique case ( col)
-     0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2D8; arA23[ 'h5] = 'X; end
-     1: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = 'X; end
-     2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h2F3; end
-     3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h2F3; end
-     4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h2F3; end
-     5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h2F3; end
-     6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h2F3; end
-     7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h2F3; end
-     8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h2F3; end
-    default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X   ; arA23[ 'h5] = 'X; end
+    EA_Dn:     begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2D8; arA23[ 'h5] = `UNDF; end
+    EA_An:     begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h2F3; end
+    EA_Post:   begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h2F3; end
+    EA_Pre:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h2F3; end
+    EA_Rel_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h2F3; end
+    EA_Idx_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h2F3; end
+    EA_Abs_W:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h2F3; end
+    EA_Abs_L:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h2F3; end
+    default:   begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = `UNDF; arA23[ 'h5] = `UNDF; end
     endcase
 
 3'b110: // Row: 6
     unique case ( col)
-     0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = 'X; end
-     1: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = 'X; end
-     2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00B; arA23[ 'h5] = 'h2F7; end
-     3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00F; arA23[ 'h5] = 'h2F7; end
-     4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h179; arA23[ 'h5] = 'h2F7; end
-     5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C6; arA23[ 'h5] = 'h2F7; end
-     6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E7; arA23[ 'h5] = 'h2F7; end
-     7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00E; arA23[ 'h5] = 'h2F7; end
-     8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E6; arA23[ 'h5] = 'h2F7; end
-    default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X   ; arA23[ 'h5] = 'X; end
+    EA_Dn:     begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = `UNDF; end
+    EA_An:     begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h2DC; arA23[ 'h5] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00B; arA23[ 'h5] = 'h2F7; end
+    EA_Post:   begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00F; arA23[ 'h5] = 'h2F7; end
+    EA_Pre:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h179; arA23[ 'h5] = 'h2F7; end
+    EA_Rel_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C6; arA23[ 'h5] = 'h2F7; end
+    EA_Idx_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E7; arA23[ 'h5] = 'h2F7; end
+    EA_Abs_W:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00E; arA23[ 'h5] = 'h2F7; end
+    EA_Abs_L:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E6; arA23[ 'h5] = 'h2F7; end
+    default:   begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = `UNDF; arA23[ 'h5] = `UNDF; end
     endcase
 
 3'b111: // Row: 7
     unique case ( col)
-     0: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h384; arA23[ 'h5] = 'X; end
-     1: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h06C; arA23[ 'h5] = 'X; end
-     2: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h380; end
-     3: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h380; end
-     4: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h380; end
-     5: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h380; end
-     6: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h380; end
-     7: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h380; end
-     8: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h380; end
-    default: begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = 'X   ; arA23[ 'h5] = 'X; end
+    EA_Dn:     begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h384; arA23[ 'h5] = `UNDF; end
+    EA_An:     begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h06C; arA23[ 'h5] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h006; arA23[ 'h5] = 'h380; end
+    EA_Post:   begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h21C; arA23[ 'h5] = 'h380; end
+    EA_Pre:    begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h103; arA23[ 'h5] = 'h380; end
+    EA_Rel_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1C2; arA23[ 'h5] = 'h380; end
+    EA_Idx_An: begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E3; arA23[ 'h5] = 'h380; end
+    EA_Abs_W:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h00A; arA23[ 'h5] = 'h380; end
+    EA_Abs_L:  begin arIll[ 'h5] = 1'b0; arA1[ 'h5] = 'h1E2; arA23[ 'h5] = 'h380; end
+    default:   begin arIll[ 'h5] = 1'b1; arA1[ 'h5] = `UNDF; arA23[ 'h5] = `UNDF; end
     endcase
 endcase
 
@@ -1484,138 +1479,138 @@ unique case( row86)
 
 3'b000: // Row: 0
     unique case ( col)
-     0: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C1; arA23[ 'h8] = 'X; end
-     1: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-     2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h1C3; end
-     3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h1C3; end
-     4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h1C3; end
-     5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h1C3; end
-     6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h1C3; end
-     7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h1C3; end
-     8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h1C3; end
-     9: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h1C3; end
-    10: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h1C3; end
-    11: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0EA; arA23[ 'h8] = 'h1C1; end
-    default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
+    EA_Dn:     begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C1; arA23[ 'h8] = `UNDF; end
+    EA_An:     begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h1C3; end
+    EA_Post:   begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h1C3; end
+    EA_Pre:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h1C3; end
+    EA_Rel_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h1C3; end
+    EA_Idx_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h1C3; end
+    EA_Abs_W:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h1C3; end
+    EA_Abs_L:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h1C3; end
+    EA_Rel_PC: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h1C3; end
+    EA_Idx_PC: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h1C3; end
+    EA_Imm:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0EA; arA23[ 'h8] = 'h1C1; end
+    default:   begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
     endcase
 
 3'b001: // Row: 1
     unique case ( col)
-     0: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C1; arA23[ 'h8] = 'X; end
-     1: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-     2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h1C3; end
-     3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h1C3; end
-     4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h1C3; end
-     5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h1C3; end
-     6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h1C3; end
-     7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h1C3; end
-     8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h1C3; end
-     9: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h1C3; end
-    10: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h1C3; end
-    11: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0EA; arA23[ 'h8] = 'h1C1; end
-    default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
+    EA_Dn:     begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C1; arA23[ 'h8] = `UNDF; end
+    EA_An:     begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h1C3; end
+    EA_Post:   begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h1C3; end
+    EA_Pre:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h1C3; end
+    EA_Rel_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h1C3; end
+    EA_Idx_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h1C3; end
+    EA_Abs_W:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h1C3; end
+    EA_Abs_L:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h1C3; end
+    EA_Rel_PC: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h1C3; end
+    EA_Idx_PC: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h1C3; end
+    EA_Imm:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0EA; arA23[ 'h8] = 'h1C1; end
+    default:   begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
     endcase
 
 3'b010: // Row: 2
     unique case ( col)
-     0: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C5; arA23[ 'h8] = 'X; end
-     1: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-     2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00B; arA23[ 'h8] = 'h1CB; end
-     3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00F; arA23[ 'h8] = 'h1CB; end
-     4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h179; arA23[ 'h8] = 'h1CB; end
-     5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C6; arA23[ 'h8] = 'h1CB; end
-     6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E7; arA23[ 'h8] = 'h1CB; end
-     7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00E; arA23[ 'h8] = 'h1CB; end
-     8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E6; arA23[ 'h8] = 'h1CB; end
-     9: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C6; arA23[ 'h8] = 'h1CB; end
-    10: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E7; arA23[ 'h8] = 'h1CB; end
-    11: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0A7; arA23[ 'h8] = 'h1C5; end
-    default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
+    EA_Dn:     begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C5; arA23[ 'h8] = `UNDF; end
+    EA_An:     begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00B; arA23[ 'h8] = 'h1CB; end
+    EA_Post:   begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00F; arA23[ 'h8] = 'h1CB; end
+    EA_Pre:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h179; arA23[ 'h8] = 'h1CB; end
+    EA_Rel_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C6; arA23[ 'h8] = 'h1CB; end
+    EA_Idx_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E7; arA23[ 'h8] = 'h1CB; end
+    EA_Abs_W:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00E; arA23[ 'h8] = 'h1CB; end
+    EA_Abs_L:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E6; arA23[ 'h8] = 'h1CB; end
+    EA_Rel_PC: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C6; arA23[ 'h8] = 'h1CB; end
+    EA_Idx_PC: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E7; arA23[ 'h8] = 'h1CB; end
+    EA_Imm:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0A7; arA23[ 'h8] = 'h1C5; end
+    default:   begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
     endcase
 
 3'b011: // Row: 3
     unique case ( col)
-     0: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0A6; arA23[ 'h8] = 'X; end
-     1: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-     2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h0A4; end
-     3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h0A4; end
-     4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h0A4; end
-     5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h0A4; end
-     6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h0A4; end
-     7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h0A4; end
-     8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h0A4; end
-     9: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h0A4; end
-    10: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h0A4; end
-    11: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0EA; arA23[ 'h8] = 'h0A6; end
-    default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
+    EA_Dn:     begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0A6; arA23[ 'h8] = `UNDF; end
+    EA_An:     begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h0A4; end
+    EA_Post:   begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h0A4; end
+    EA_Pre:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h0A4; end
+    EA_Rel_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h0A4; end
+    EA_Idx_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h0A4; end
+    EA_Abs_W:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h0A4; end
+    EA_Abs_L:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h0A4; end
+    EA_Rel_PC: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h0A4; end
+    EA_Idx_PC: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h0A4; end
+    EA_Imm:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0EA; arA23[ 'h8] = 'h0A6; end
+    default:   begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
     endcase
 
 3'b100: // Row: 4
     unique case ( col)
-     0: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1CD; arA23[ 'h8] = 'X; end
-     1: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h107; arA23[ 'h8] = 'X; end
-     2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h299; end
-     3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h299; end
-     4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h299; end
-     5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h299; end
-     6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h299; end
-     7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h299; end
-     8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h299; end
-     9: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-    10: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-    11: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-    default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
+    EA_Dn:     begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1CD; arA23[ 'h8] = `UNDF; end
+    EA_An:     begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h107; arA23[ 'h8] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h299; end
+    EA_Post:   begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h299; end
+    EA_Pre:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h299; end
+    EA_Rel_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h299; end
+    EA_Idx_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h299; end
+    EA_Abs_W:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h299; end
+    EA_Abs_L:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h299; end
+    EA_Rel_PC: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    default:   begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
     endcase
 
 3'b101: // Row: 5
     unique case ( col)
-     0: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-     1: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-     2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h299; end
-     3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h299; end
-     4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h299; end
-     5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h299; end
-     6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h299; end
-     7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h299; end
-     8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h299; end
-     9: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-    10: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-    11: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-    default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
+    EA_Dn:     begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_An:     begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h299; end
+    EA_Post:   begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h299; end
+    EA_Pre:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h299; end
+    EA_Rel_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h299; end
+    EA_Idx_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h299; end
+    EA_Abs_W:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h299; end
+    EA_Abs_L:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h299; end
+    EA_Rel_PC: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    default:   begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
     endcase
 
 3'b110: // Row: 6
     unique case ( col)
-     0: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-     1: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-     2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00B; arA23[ 'h8] = 'h29D; end
-     3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00F; arA23[ 'h8] = 'h29D; end
-     4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h179; arA23[ 'h8] = 'h29D; end
-     5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C6; arA23[ 'h8] = 'h29D; end
-     6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E7; arA23[ 'h8] = 'h29D; end
-     7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00E; arA23[ 'h8] = 'h29D; end
-     8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E6; arA23[ 'h8] = 'h29D; end
-     9: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-    10: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-    11: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-    default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
+    EA_Dn:     begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_An:     begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00B; arA23[ 'h8] = 'h29D; end
+    EA_Post:   begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00F; arA23[ 'h8] = 'h29D; end
+    EA_Pre:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h179; arA23[ 'h8] = 'h29D; end
+    EA_Rel_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C6; arA23[ 'h8] = 'h29D; end
+    EA_Idx_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E7; arA23[ 'h8] = 'h29D; end
+    EA_Abs_W:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00E; arA23[ 'h8] = 'h29D; end
+    EA_Abs_L:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E6; arA23[ 'h8] = 'h29D; end
+    EA_Rel_PC: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    default:   begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
     endcase
 
 3'b111: // Row: 7
     unique case ( col)
-     0: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0AE; arA23[ 'h8] = 'X; end
-     1: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
-     2: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h0AC; end
-     3: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h0AC; end
-     4: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h0AC; end
-     5: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h0AC; end
-     6: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h0AC; end
-     7: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h0AC; end
-     8: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h0AC; end
-     9: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h0AC; end
-    10: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h0AC; end
-    11: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0EA; arA23[ 'h8] = 'h0AE; end
-    default: begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = 'X   ; arA23[ 'h8] = 'X; end
+    EA_Dn:     begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0AE; arA23[ 'h8] = `UNDF; end
+    EA_An:     begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h006; arA23[ 'h8] = 'h0AC; end
+    EA_Post:   begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h21C; arA23[ 'h8] = 'h0AC; end
+    EA_Pre:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h103; arA23[ 'h8] = 'h0AC; end
+    EA_Rel_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h0AC; end
+    EA_Idx_An: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h0AC; end
+    EA_Abs_W:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h00A; arA23[ 'h8] = 'h0AC; end
+    EA_Abs_L:  begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E2; arA23[ 'h8] = 'h0AC; end
+    EA_Rel_PC: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1C2; arA23[ 'h8] = 'h0AC; end
+    EA_Idx_PC: begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h1E3; arA23[ 'h8] = 'h0AC; end
+    EA_Imm:    begin arIll[ 'h8] = 1'b0; arA1[ 'h8] = 'h0EA; arA23[ 'h8] = 'h0AE; end
+    default:   begin arIll[ 'h8] = 1'b1; arA1[ 'h8] = `UNDF; arA23[ 'h8] = `UNDF; end
     endcase
 endcase
 
@@ -1626,138 +1621,138 @@ unique case( row86)
 
 3'b000: // Row: 0
     unique case ( col)
-     0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = 'X; end
-     1: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
-     2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h1C3; end
-     3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h1C3; end
-     4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h1C3; end
-     5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C3; end
-     6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C3; end
-     7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h1C3; end
-     8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h1C3; end
-     9: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C3; end
-    10: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C3; end
-    11: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0EA; arA23[ 'h9] = 'h1C1; end
-    default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
+    EA_Dn:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = `UNDF; end
+    EA_An:     begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h1C3; end
+    EA_Post:   begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h1C3; end
+    EA_Pre:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h1C3; end
+    EA_Rel_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C3; end
+    EA_Idx_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C3; end
+    EA_Abs_W:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h1C3; end
+    EA_Abs_L:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h1C3; end
+    EA_Rel_PC: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C3; end
+    EA_Idx_PC: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C3; end
+    EA_Imm:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0EA; arA23[ 'h9] = 'h1C1; end
+    default:   begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
     endcase
 
 3'b001: // Row: 1
     unique case ( col)
-     0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = 'X; end
-     1: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = 'X; end
-     2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h1C3; end
-     3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h1C3; end
-     4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h1C3; end
-     5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C3; end
-     6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C3; end
-     7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h1C3; end
-     8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h1C3; end
-     9: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C3; end
-    10: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C3; end
-    11: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0EA; arA23[ 'h9] = 'h1C1; end
-    default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
+    EA_Dn:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = `UNDF; end
+    EA_An:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h1C3; end
+    EA_Post:   begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h1C3; end
+    EA_Pre:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h1C3; end
+    EA_Rel_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C3; end
+    EA_Idx_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C3; end
+    EA_Abs_W:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h1C3; end
+    EA_Abs_L:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h1C3; end
+    EA_Rel_PC: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C3; end
+    EA_Idx_PC: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C3; end
+    EA_Imm:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0EA; arA23[ 'h9] = 'h1C1; end
+    default:   begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
     endcase
 
 3'b010: // Row: 2
     unique case ( col)
-     0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = 'X; end
-     1: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = 'X; end
-     2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00B; arA23[ 'h9] = 'h1CB; end
-     3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00F; arA23[ 'h9] = 'h1CB; end
-     4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h179; arA23[ 'h9] = 'h1CB; end
-     5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h1CB; end
-     6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h1CB; end
-     7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00E; arA23[ 'h9] = 'h1CB; end
-     8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E6; arA23[ 'h9] = 'h1CB; end
-     9: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h1CB; end
-    10: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h1CB; end
-    11: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0A7; arA23[ 'h9] = 'h1C5; end
-    default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
+    EA_Dn:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = `UNDF; end
+    EA_An:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00B; arA23[ 'h9] = 'h1CB; end
+    EA_Post:   begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00F; arA23[ 'h9] = 'h1CB; end
+    EA_Pre:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h179; arA23[ 'h9] = 'h1CB; end
+    EA_Rel_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h1CB; end
+    EA_Idx_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h1CB; end
+    EA_Abs_W:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00E; arA23[ 'h9] = 'h1CB; end
+    EA_Abs_L:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E6; arA23[ 'h9] = 'h1CB; end
+    EA_Rel_PC: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h1CB; end
+    EA_Idx_PC: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h1CB; end
+    EA_Imm:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0A7; arA23[ 'h9] = 'h1C5; end
+    default:   begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
     endcase
 
 3'b011: // Row: 3
     unique case ( col)
-     0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C9; arA23[ 'h9] = 'X; end
-     1: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C9; arA23[ 'h9] = 'X; end
-     2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h1C7; end
-     3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h1C7; end
-     4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h1C7; end
-     5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C7; end
-     6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C7; end
-     7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h1C7; end
-     8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h1C7; end
-     9: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C7; end
-    10: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C7; end
-    11: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0EA; arA23[ 'h9] = 'h1C9; end
-    default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
+    EA_Dn:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C9; arA23[ 'h9] = `UNDF; end
+    EA_An:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C9; arA23[ 'h9] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h1C7; end
+    EA_Post:   begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h1C7; end
+    EA_Pre:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h1C7; end
+    EA_Rel_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C7; end
+    EA_Idx_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C7; end
+    EA_Abs_W:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h1C7; end
+    EA_Abs_L:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h1C7; end
+    EA_Rel_PC: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h1C7; end
+    EA_Idx_PC: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h1C7; end
+    EA_Imm:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0EA; arA23[ 'h9] = 'h1C9; end
+    default:   begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
     endcase
 
 3'b100: // Row: 4
     unique case ( col)
-     0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = 'X; end
-     1: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h10F; arA23[ 'h9] = 'X; end
-     2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h299; end
-     3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h299; end
-     4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h299; end
-     5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h299; end
-     6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h299; end
-     7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h299; end
-     8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h299; end
-     9: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
-    10: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
-    11: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
-    default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
+    EA_Dn:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = `UNDF; end
+    EA_An:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h10F; arA23[ 'h9] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h299; end
+    EA_Post:   begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h299; end
+    EA_Pre:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h299; end
+    EA_Rel_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h299; end
+    EA_Idx_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h299; end
+    EA_Abs_W:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h299; end
+    EA_Abs_L:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h299; end
+    EA_Rel_PC: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
+    default:   begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
     endcase
 
 3'b101: // Row: 5
     unique case ( col)
-     0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = 'X; end
-     1: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h10F; arA23[ 'h9] = 'X; end
-     2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h299; end
-     3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h299; end
-     4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h299; end
-     5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h299; end
-     6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h299; end
-     7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h299; end
-     8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h299; end
-     9: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
-    10: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
-    11: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
-    default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
+    EA_Dn:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C1; arA23[ 'h9] = `UNDF; end
+    EA_An:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h10F; arA23[ 'h9] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h006; arA23[ 'h9] = 'h299; end
+    EA_Post:   begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h21C; arA23[ 'h9] = 'h299; end
+    EA_Pre:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h103; arA23[ 'h9] = 'h299; end
+    EA_Rel_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C2; arA23[ 'h9] = 'h299; end
+    EA_Idx_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E3; arA23[ 'h9] = 'h299; end
+    EA_Abs_W:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00A; arA23[ 'h9] = 'h299; end
+    EA_Abs_L:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E2; arA23[ 'h9] = 'h299; end
+    EA_Rel_PC: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
+    default:   begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
     endcase
 
 3'b110: // Row: 6
     unique case ( col)
-     0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = 'X; end
-     1: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h10B; arA23[ 'h9] = 'X; end
-     2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00B; arA23[ 'h9] = 'h29D; end
-     3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00F; arA23[ 'h9] = 'h29D; end
-     4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h179; arA23[ 'h9] = 'h29D; end
-     5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h29D; end
-     6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h29D; end
-     7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00E; arA23[ 'h9] = 'h29D; end
-     8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E6; arA23[ 'h9] = 'h29D; end
-     9: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
-    10: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
-    11: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
-    default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
+    EA_Dn:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = `UNDF; end
+    EA_An:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h10B; arA23[ 'h9] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00B; arA23[ 'h9] = 'h29D; end
+    EA_Post:   begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00F; arA23[ 'h9] = 'h29D; end
+    EA_Pre:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h179; arA23[ 'h9] = 'h29D; end
+    EA_Rel_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h29D; end
+    EA_Idx_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h29D; end
+    EA_Abs_W:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00E; arA23[ 'h9] = 'h29D; end
+    EA_Abs_L:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E6; arA23[ 'h9] = 'h29D; end
+    EA_Rel_PC: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
+    EA_Imm:    begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
+    default:   begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
     endcase
 
 3'b111: // Row: 7
     unique case ( col)
-     0: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = 'X; end
-     1: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = 'X; end
-     2: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00B; arA23[ 'h9] = 'h1CB; end
-     3: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00F; arA23[ 'h9] = 'h1CB; end
-     4: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h179; arA23[ 'h9] = 'h1CB; end
-     5: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h1CB; end
-     6: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h1CB; end
-     7: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00E; arA23[ 'h9] = 'h1CB; end
-     8: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E6; arA23[ 'h9] = 'h1CB; end
-     9: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h1CB; end
-    10: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h1CB; end
-    11: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0A7; arA23[ 'h9] = 'h1C5; end
-    default: begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = 'X   ; arA23[ 'h9] = 'X; end
+    EA_Dn:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = `UNDF; end
+    EA_An:     begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C5; arA23[ 'h9] = `UNDF; end
+    EA_Ind:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00B; arA23[ 'h9] = 'h1CB; end
+    EA_Post:   begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00F; arA23[ 'h9] = 'h1CB; end
+    EA_Pre:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h179; arA23[ 'h9] = 'h1CB; end
+    EA_Rel_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h1CB; end
+    EA_Idx_An: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h1CB; end
+    EA_Abs_W:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h00E; arA23[ 'h9] = 'h1CB; end
+    EA_Abs_L:  begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E6; arA23[ 'h9] = 'h1CB; end
+    EA_Rel_PC: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1C6; arA23[ 'h9] = 'h1CB; end
+    EA_Idx_PC: begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h1E7; arA23[ 'h9] = 'h1CB; end
+    EA_Imm:    begin arIll[ 'h9] = 1'b0; arA1[ 'h9] = 'h0A7; arA23[ 'h9] = 'h1C5; end
+    default:   begin arIll[ 'h9] = 1'b1; arA1[ 'h9] = `UNDF; arA23[ 'h9] = `UNDF; end
     endcase
 endcase
 
@@ -1768,138 +1763,138 @@ unique case( row86)
 
 3'b000: // Row: 0
     unique case ( col)
-     0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D1; arA23[ 'hb] = 'X; end
-     1: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
-     2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h1D3; end
-     3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h1D3; end
-     4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h1D3; end
-     5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1D3; end
-     6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1D3; end
-     7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h1D3; end
-     8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h1D3; end
-     9: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1D3; end
-    10: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1D3; end
-    11: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0EA; arA23[ 'hb] = 'h1D1; end
-    default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
+    EA_Dn:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D1; arA23[ 'hb] = `UNDF; end
+    EA_An:     begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h1D3; end
+    EA_Post:   begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h1D3; end
+    EA_Pre:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h1D3; end
+    EA_Rel_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1D3; end
+    EA_Idx_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1D3; end
+    EA_Abs_W:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h1D3; end
+    EA_Abs_L:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h1D3; end
+    EA_Rel_PC: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1D3; end
+    EA_Idx_PC: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1D3; end
+    EA_Imm:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0EA; arA23[ 'hb] = 'h1D1; end
+    default:   begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
     endcase
 
 3'b001: // Row: 1
     unique case ( col)
-     0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D1; arA23[ 'hb] = 'X; end
-     1: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D1; arA23[ 'hb] = 'X; end
-     2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h1D3; end
-     3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h1D3; end
-     4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h1D3; end
-     5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1D3; end
-     6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1D3; end
-     7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h1D3; end
-     8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h1D3; end
-     9: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1D3; end
-    10: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1D3; end
-    11: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0EA; arA23[ 'hb] = 'h1D1; end
-    default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
+    EA_Dn:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D1; arA23[ 'hb] = `UNDF; end
+    EA_An:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D1; arA23[ 'hb] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h1D3; end
+    EA_Post:   begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h1D3; end
+    EA_Pre:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h1D3; end
+    EA_Rel_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1D3; end
+    EA_Idx_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1D3; end
+    EA_Abs_W:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h1D3; end
+    EA_Abs_L:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h1D3; end
+    EA_Rel_PC: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1D3; end
+    EA_Idx_PC: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1D3; end
+    EA_Imm:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0EA; arA23[ 'hb] = 'h1D1; end
+    default:   begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
     endcase
 
 3'b010: // Row: 2
     unique case ( col)
-     0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D5; arA23[ 'hb] = 'X; end
-     1: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D5; arA23[ 'hb] = 'X; end
-     2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00B; arA23[ 'hb] = 'h1D7; end
-     3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00F; arA23[ 'hb] = 'h1D7; end
-     4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h179; arA23[ 'hb] = 'h1D7; end
-     5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h1D7; end
-     6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h1D7; end
-     7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00E; arA23[ 'hb] = 'h1D7; end
-     8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E6; arA23[ 'hb] = 'h1D7; end
-     9: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h1D7; end
-    10: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h1D7; end
-    11: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0A7; arA23[ 'hb] = 'h1D5; end
-    default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
+    EA_Dn:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D5; arA23[ 'hb] = `UNDF; end
+    EA_An:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D5; arA23[ 'hb] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00B; arA23[ 'hb] = 'h1D7; end
+    EA_Post:   begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00F; arA23[ 'hb] = 'h1D7; end
+    EA_Pre:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h179; arA23[ 'hb] = 'h1D7; end
+    EA_Rel_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h1D7; end
+    EA_Idx_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h1D7; end
+    EA_Abs_W:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00E; arA23[ 'hb] = 'h1D7; end
+    EA_Abs_L:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E6; arA23[ 'hb] = 'h1D7; end
+    EA_Rel_PC: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h1D7; end
+    EA_Idx_PC: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h1D7; end
+    EA_Imm:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0A7; arA23[ 'hb] = 'h1D5; end
+    default:   begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
     endcase
 
 3'b011: // Row: 3
     unique case ( col)
-     0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D9; arA23[ 'hb] = 'X; end
-     1: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D9; arA23[ 'hb] = 'X; end
-     2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h1CF; end
-     3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h1CF; end
-     4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h1CF; end
-     5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1CF; end
-     6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1CF; end
-     7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h1CF; end
-     8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h1CF; end
-     9: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1CF; end
-    10: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1CF; end
-    11: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0EA; arA23[ 'hb] = 'h1D9; end
-    default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
+    EA_Dn:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D9; arA23[ 'hb] = `UNDF; end
+    EA_An:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D9; arA23[ 'hb] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h1CF; end
+    EA_Post:   begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h1CF; end
+    EA_Pre:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h1CF; end
+    EA_Rel_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1CF; end
+    EA_Idx_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1CF; end
+    EA_Abs_W:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h1CF; end
+    EA_Abs_L:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h1CF; end
+    EA_Rel_PC: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h1CF; end
+    EA_Idx_PC: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h1CF; end
+    EA_Imm:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0EA; arA23[ 'hb] = 'h1D9; end
+    default:   begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
     endcase
 
 3'b100: // Row: 4
     unique case ( col)
-     0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h100; arA23[ 'hb] = 'X; end
-     1: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h06B; arA23[ 'hb] = 'X; end
-     2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h299; end
-     3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h299; end
-     4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h299; end
-     5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h299; end
-     6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h299; end
-     7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h299; end
-     8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h299; end
-     9: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
-    10: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
-    11: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
-    default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
+    EA_Dn:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h100; arA23[ 'hb] = `UNDF; end
+    EA_An:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h06B; arA23[ 'hb] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h299; end
+    EA_Post:   begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h299; end
+    EA_Pre:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h299; end
+    EA_Rel_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h299; end
+    EA_Idx_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h299; end
+    EA_Abs_W:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h299; end
+    EA_Abs_L:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h299; end
+    EA_Rel_PC: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
+    EA_Imm:    begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
+    default:   begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
     endcase
 
 3'b101: // Row: 5
     unique case ( col)
-     0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h100; arA23[ 'hb] = 'X; end
-     1: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h06B; arA23[ 'hb] = 'X; end
-     2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h299; end
-     3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h299; end
-     4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h299; end
-     5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h299; end
-     6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h299; end
-     7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h299; end
-     8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h299; end
-     9: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
-    10: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
-    11: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
-    default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
+    EA_Dn:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h100; arA23[ 'hb] = `UNDF; end
+    EA_An:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h06B; arA23[ 'hb] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h006; arA23[ 'hb] = 'h299; end
+    EA_Post:   begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h21C; arA23[ 'hb] = 'h299; end
+    EA_Pre:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h103; arA23[ 'hb] = 'h299; end
+    EA_Rel_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C2; arA23[ 'hb] = 'h299; end
+    EA_Idx_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E3; arA23[ 'hb] = 'h299; end
+    EA_Abs_W:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00A; arA23[ 'hb] = 'h299; end
+    EA_Abs_L:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E2; arA23[ 'hb] = 'h299; end
+    EA_Rel_PC: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
+    EA_Imm:    begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
+    default:   begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
     endcase
 
 3'b110: // Row: 6
     unique case ( col)
-     0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h10C; arA23[ 'hb] = 'X; end
-     1: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h06F; arA23[ 'hb] = 'X; end
-     2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00B; arA23[ 'hb] = 'h29D; end
-     3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00F; arA23[ 'hb] = 'h29D; end
-     4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h179; arA23[ 'hb] = 'h29D; end
-     5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h29D; end
-     6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h29D; end
-     7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00E; arA23[ 'hb] = 'h29D; end
-     8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E6; arA23[ 'hb] = 'h29D; end
-     9: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
-    10: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
-    11: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
-    default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
+    EA_Dn:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h10C; arA23[ 'hb] = `UNDF; end
+    EA_An:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h06F; arA23[ 'hb] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00B; arA23[ 'hb] = 'h29D; end
+    EA_Post:   begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00F; arA23[ 'hb] = 'h29D; end
+    EA_Pre:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h179; arA23[ 'hb] = 'h29D; end
+    EA_Rel_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h29D; end
+    EA_Idx_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h29D; end
+    EA_Abs_W:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00E; arA23[ 'hb] = 'h29D; end
+    EA_Abs_L:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E6; arA23[ 'hb] = 'h29D; end
+    EA_Rel_PC: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
+    EA_Imm:    begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
+    default:   begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
     endcase
 
 3'b111: // Row: 7
     unique case ( col)
-     0: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D5; arA23[ 'hb] = 'X; end
-     1: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D5; arA23[ 'hb] = 'X; end
-     2: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00B; arA23[ 'hb] = 'h1D7; end
-     3: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00F; arA23[ 'hb] = 'h1D7; end
-     4: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h179; arA23[ 'hb] = 'h1D7; end
-     5: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h1D7; end
-     6: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h1D7; end
-     7: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00E; arA23[ 'hb] = 'h1D7; end
-     8: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E6; arA23[ 'hb] = 'h1D7; end
-     9: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h1D7; end
-    10: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h1D7; end
-    11: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0A7; arA23[ 'hb] = 'h1D5; end
-    default: begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = 'X   ; arA23[ 'hb] = 'X; end
+    EA_Dn:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D5; arA23[ 'hb] = `UNDF; end
+    EA_An:     begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1D5; arA23[ 'hb] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00B; arA23[ 'hb] = 'h1D7; end
+    EA_Post:   begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00F; arA23[ 'hb] = 'h1D7; end
+    EA_Pre:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h179; arA23[ 'hb] = 'h1D7; end
+    EA_Rel_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h1D7; end
+    EA_Idx_An: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h1D7; end
+    EA_Abs_W:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h00E; arA23[ 'hb] = 'h1D7; end
+    EA_Abs_L:  begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E6; arA23[ 'hb] = 'h1D7; end
+    EA_Rel_PC: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1C6; arA23[ 'hb] = 'h1D7; end
+    EA_Idx_PC: begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h1E7; arA23[ 'hb] = 'h1D7; end
+    EA_Imm:    begin arIll[ 'hb] = 1'b0; arA1[ 'hb] = 'h0A7; arA23[ 'hb] = 'h1D5; end
+    default:   begin arIll[ 'hb] = 1'b1; arA1[ 'hb] = `UNDF; arA23[ 'hb] = `UNDF; end
     endcase
 endcase
 
@@ -1910,138 +1905,138 @@ unique case( row86)
 
 3'b000: // Row: 0
     unique case ( col)
-     0: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C1; arA23[ 'hc] = 'X; end
-     1: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-     2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h1C3; end
-     3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h1C3; end
-     4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h1C3; end
-     5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h1C3; end
-     6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h1C3; end
-     7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h1C3; end
-     8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h1C3; end
-     9: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h1C3; end
-    10: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h1C3; end
-    11: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0EA; arA23[ 'hc] = 'h1C1; end
-    default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
+    EA_Dn:     begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C1; arA23[ 'hc] = `UNDF; end
+    EA_An:     begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h1C3; end
+    EA_Post:   begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h1C3; end
+    EA_Pre:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h1C3; end
+    EA_Rel_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h1C3; end
+    EA_Idx_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h1C3; end
+    EA_Abs_W:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h1C3; end
+    EA_Abs_L:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h1C3; end
+    EA_Rel_PC: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h1C3; end
+    EA_Idx_PC: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h1C3; end
+    EA_Imm:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0EA; arA23[ 'hc] = 'h1C1; end
+    default:   begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
     endcase
 
 3'b001: // Row: 1
     unique case ( col)
-     0: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C1; arA23[ 'hc] = 'X; end
-     1: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-     2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h1C3; end
-     3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h1C3; end
-     4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h1C3; end
-     5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h1C3; end
-     6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h1C3; end
-     7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h1C3; end
-     8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h1C3; end
-     9: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h1C3; end
-    10: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h1C3; end
-    11: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0EA; arA23[ 'hc] = 'h1C1; end
-    default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
+    EA_Dn:     begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C1; arA23[ 'hc] = `UNDF; end
+    EA_An:     begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h1C3; end
+    EA_Post:   begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h1C3; end
+    EA_Pre:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h1C3; end
+    EA_Rel_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h1C3; end
+    EA_Idx_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h1C3; end
+    EA_Abs_W:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h1C3; end
+    EA_Abs_L:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h1C3; end
+    EA_Rel_PC: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h1C3; end
+    EA_Idx_PC: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h1C3; end
+    EA_Imm:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0EA; arA23[ 'hc] = 'h1C1; end
+    default:   begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
     endcase
 
 3'b010: // Row: 2
     unique case ( col)
-     0: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C5; arA23[ 'hc] = 'X; end
-     1: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-     2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00B; arA23[ 'hc] = 'h1CB; end
-     3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00F; arA23[ 'hc] = 'h1CB; end
-     4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h179; arA23[ 'hc] = 'h1CB; end
-     5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C6; arA23[ 'hc] = 'h1CB; end
-     6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E7; arA23[ 'hc] = 'h1CB; end
-     7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00E; arA23[ 'hc] = 'h1CB; end
-     8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E6; arA23[ 'hc] = 'h1CB; end
-     9: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C6; arA23[ 'hc] = 'h1CB; end
-    10: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E7; arA23[ 'hc] = 'h1CB; end
-    11: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0A7; arA23[ 'hc] = 'h1C5; end
-    default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
+    EA_Dn:     begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C5; arA23[ 'hc] = `UNDF; end
+    EA_An:     begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00B; arA23[ 'hc] = 'h1CB; end
+    EA_Post:   begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00F; arA23[ 'hc] = 'h1CB; end
+    EA_Pre:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h179; arA23[ 'hc] = 'h1CB; end
+    EA_Rel_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C6; arA23[ 'hc] = 'h1CB; end
+    EA_Idx_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E7; arA23[ 'hc] = 'h1CB; end
+    EA_Abs_W:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00E; arA23[ 'hc] = 'h1CB; end
+    EA_Abs_L:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E6; arA23[ 'hc] = 'h1CB; end
+    EA_Rel_PC: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C6; arA23[ 'hc] = 'h1CB; end
+    EA_Idx_PC: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E7; arA23[ 'hc] = 'h1CB; end
+    EA_Imm:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0A7; arA23[ 'hc] = 'h1C5; end
+    default:   begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
     endcase
 
 3'b011: // Row: 3
     unique case ( col)
-     0: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h15B; arA23[ 'hc] = 'X; end
-     1: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-     2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h15A; end
-     3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h15A; end
-     4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h15A; end
-     5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h15A; end
-     6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h15A; end
-     7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h15A; end
-     8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h15A; end
-     9: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h15A; end
-    10: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h15A; end
-    11: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0EA; arA23[ 'hc] = 'h15B; end
-    default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
+    EA_Dn:     begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h15B; arA23[ 'hc] = `UNDF; end
+    EA_An:     begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h15A; end
+    EA_Post:   begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h15A; end
+    EA_Pre:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h15A; end
+    EA_Rel_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h15A; end
+    EA_Idx_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h15A; end
+    EA_Abs_W:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h15A; end
+    EA_Abs_L:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h15A; end
+    EA_Rel_PC: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h15A; end
+    EA_Idx_PC: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h15A; end
+    EA_Imm:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0EA; arA23[ 'hc] = 'h15B; end
+    default:   begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
     endcase
 
 3'b100: // Row: 4
     unique case ( col)
-     0: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1CD; arA23[ 'hc] = 'X; end
-     1: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h107; arA23[ 'hc] = 'X; end
-     2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h299; end
-     3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h299; end
-     4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h299; end
-     5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h299; end
-     6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h299; end
-     7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h299; end
-     8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h299; end
-     9: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-    10: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-    11: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-    default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
+    EA_Dn:     begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1CD; arA23[ 'hc] = `UNDF; end
+    EA_An:     begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h107; arA23[ 'hc] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h299; end
+    EA_Post:   begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h299; end
+    EA_Pre:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h299; end
+    EA_Rel_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h299; end
+    EA_Idx_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h299; end
+    EA_Abs_W:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h299; end
+    EA_Abs_L:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h299; end
+    EA_Rel_PC: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    EA_Imm:    begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    default:   begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
     endcase
 
 3'b101: // Row: 5
     unique case ( col)
-     0: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h3E3; arA23[ 'hc] = 'X; end
-     1: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h3E3; arA23[ 'hc] = 'X; end
-     2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h299; end
-     3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h299; end
-     4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h299; end
-     5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h299; end
-     6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h299; end
-     7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h299; end
-     8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h299; end
-     9: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-    10: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-    11: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-    default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
+    EA_Dn:     begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h3E3; arA23[ 'hc] = `UNDF; end
+    EA_An:     begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h3E3; arA23[ 'hc] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h299; end
+    EA_Post:   begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h299; end
+    EA_Pre:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h299; end
+    EA_Rel_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h299; end
+    EA_Idx_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h299; end
+    EA_Abs_W:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h299; end
+    EA_Abs_L:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h299; end
+    EA_Rel_PC: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    EA_Imm:    begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    default:   begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
     endcase
 
 3'b110: // Row: 6
     unique case ( col)
-     0: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-     1: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h3E3; arA23[ 'hc] = 'X; end
-     2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00B; arA23[ 'hc] = 'h29D; end
-     3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00F; arA23[ 'hc] = 'h29D; end
-     4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h179; arA23[ 'hc] = 'h29D; end
-     5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C6; arA23[ 'hc] = 'h29D; end
-     6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E7; arA23[ 'hc] = 'h29D; end
-     7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00E; arA23[ 'hc] = 'h29D; end
-     8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E6; arA23[ 'hc] = 'h29D; end
-     9: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-    10: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-    11: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-    default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
+    EA_Dn:     begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    EA_An:     begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h3E3; arA23[ 'hc] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00B; arA23[ 'hc] = 'h29D; end
+    EA_Post:   begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00F; arA23[ 'hc] = 'h29D; end
+    EA_Pre:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h179; arA23[ 'hc] = 'h29D; end
+    EA_Rel_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C6; arA23[ 'hc] = 'h29D; end
+    EA_Idx_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E7; arA23[ 'hc] = 'h29D; end
+    EA_Abs_W:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00E; arA23[ 'hc] = 'h29D; end
+    EA_Abs_L:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E6; arA23[ 'hc] = 'h29D; end
+    EA_Rel_PC: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    EA_Imm:    begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    default:   begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
     endcase
 
 3'b111: // Row: 7
     unique case ( col)
-     0: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h15B; arA23[ 'hc] = 'X; end
-     1: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
-     2: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h15A; end
-     3: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h15A; end
-     4: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h15A; end
-     5: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h15A; end
-     6: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h15A; end
-     7: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h15A; end
-     8: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h15A; end
-     9: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h15A; end
-    10: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h15A; end
-    11: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0EA; arA23[ 'hc] = 'h15B; end
-    default: begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = 'X   ; arA23[ 'hc] = 'X; end
+    EA_Dn:     begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h15B; arA23[ 'hc] = `UNDF; end
+    EA_An:     begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h006; arA23[ 'hc] = 'h15A; end
+    EA_Post:   begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h21C; arA23[ 'hc] = 'h15A; end
+    EA_Pre:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h103; arA23[ 'hc] = 'h15A; end
+    EA_Rel_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h15A; end
+    EA_Idx_An: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h15A; end
+    EA_Abs_W:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h00A; arA23[ 'hc] = 'h15A; end
+    EA_Abs_L:  begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E2; arA23[ 'hc] = 'h15A; end
+    EA_Rel_PC: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1C2; arA23[ 'hc] = 'h15A; end
+    EA_Idx_PC: begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h1E3; arA23[ 'hc] = 'h15A; end
+    EA_Imm:    begin arIll[ 'hc] = 1'b0; arA1[ 'hc] = 'h0EA; arA23[ 'hc] = 'h15B; end
+    default:   begin arIll[ 'hc] = 1'b1; arA1[ 'hc] = `UNDF; arA23[ 'hc] = `UNDF; end
     endcase
 endcase
 
@@ -2052,138 +2047,138 @@ unique case( row86)
 
 3'b000: // Row: 0
     unique case ( col)
-     0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = 'X; end
-     1: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
-     2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h1C3; end
-     3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h1C3; end
-     4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h1C3; end
-     5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C3; end
-     6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C3; end
-     7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h1C3; end
-     8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h1C3; end
-     9: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C3; end
-    10: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C3; end
-    11: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0EA; arA23[ 'hd] = 'h1C1; end
-    default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
+    EA_Dn:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = `UNDF; end
+    EA_An:     begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h1C3; end
+    EA_Post:   begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h1C3; end
+    EA_Pre:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h1C3; end
+    EA_Rel_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C3; end
+    EA_Idx_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C3; end
+    EA_Abs_W:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h1C3; end
+    EA_Abs_L:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h1C3; end
+    EA_Rel_PC: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C3; end
+    EA_Idx_PC: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C3; end
+    EA_Imm:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0EA; arA23[ 'hd] = 'h1C1; end
+    default:   begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
     endcase
 
 3'b001: // Row: 1
     unique case ( col)
-     0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = 'X; end
-     1: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = 'X; end
-     2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h1C3; end
-     3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h1C3; end
-     4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h1C3; end
-     5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C3; end
-     6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C3; end
-     7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h1C3; end
-     8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h1C3; end
-     9: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C3; end
-    10: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C3; end
-    11: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0EA; arA23[ 'hd] = 'h1C1; end
-    default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
+    EA_Dn:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = `UNDF; end
+    EA_An:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h1C3; end
+    EA_Post:   begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h1C3; end
+    EA_Pre:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h1C3; end
+    EA_Rel_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C3; end
+    EA_Idx_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C3; end
+    EA_Abs_W:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h1C3; end
+    EA_Abs_L:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h1C3; end
+    EA_Rel_PC: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C3; end
+    EA_Idx_PC: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C3; end
+    EA_Imm:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0EA; arA23[ 'hd] = 'h1C1; end
+    default:   begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
     endcase
 
 3'b010: // Row: 2
     unique case ( col)
-     0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = 'X; end
-     1: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = 'X; end
-     2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00B; arA23[ 'hd] = 'h1CB; end
-     3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00F; arA23[ 'hd] = 'h1CB; end
-     4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h179; arA23[ 'hd] = 'h1CB; end
-     5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h1CB; end
-     6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h1CB; end
-     7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00E; arA23[ 'hd] = 'h1CB; end
-     8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E6; arA23[ 'hd] = 'h1CB; end
-     9: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h1CB; end
-    10: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h1CB; end
-    11: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0A7; arA23[ 'hd] = 'h1C5; end
-    default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
+    EA_Dn:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = `UNDF; end
+    EA_An:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00B; arA23[ 'hd] = 'h1CB; end
+    EA_Post:   begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00F; arA23[ 'hd] = 'h1CB; end
+    EA_Pre:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h179; arA23[ 'hd] = 'h1CB; end
+    EA_Rel_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h1CB; end
+    EA_Idx_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h1CB; end
+    EA_Abs_W:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00E; arA23[ 'hd] = 'h1CB; end
+    EA_Abs_L:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E6; arA23[ 'hd] = 'h1CB; end
+    EA_Rel_PC: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h1CB; end
+    EA_Idx_PC: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h1CB; end
+    EA_Imm:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0A7; arA23[ 'hd] = 'h1C5; end
+    default:   begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
     endcase
 
 3'b011: // Row: 3
     unique case ( col)
-     0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C9; arA23[ 'hd] = 'X; end
-     1: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C9; arA23[ 'hd] = 'X; end
-     2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h1C7; end
-     3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h1C7; end
-     4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h1C7; end
-     5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C7; end
-     6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C7; end
-     7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h1C7; end
-     8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h1C7; end
-     9: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C7; end
-    10: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C7; end
-    11: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0EA; arA23[ 'hd] = 'h1C9; end
-    default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
+    EA_Dn:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C9; arA23[ 'hd] = `UNDF; end
+    EA_An:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C9; arA23[ 'hd] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h1C7; end
+    EA_Post:   begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h1C7; end
+    EA_Pre:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h1C7; end
+    EA_Rel_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C7; end
+    EA_Idx_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C7; end
+    EA_Abs_W:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h1C7; end
+    EA_Abs_L:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h1C7; end
+    EA_Rel_PC: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h1C7; end
+    EA_Idx_PC: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h1C7; end
+    EA_Imm:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0EA; arA23[ 'hd] = 'h1C9; end
+    default:   begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
     endcase
 
 3'b100: // Row: 4
     unique case ( col)
-     0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = 'X; end
-     1: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h10F; arA23[ 'hd] = 'X; end
-     2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h299; end
-     3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h299; end
-     4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h299; end
-     5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h299; end
-     6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h299; end
-     7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h299; end
-     8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h299; end
-     9: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
-    10: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
-    11: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
-    default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
+    EA_Dn:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = `UNDF; end
+    EA_An:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h10F; arA23[ 'hd] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h299; end
+    EA_Post:   begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h299; end
+    EA_Pre:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h299; end
+    EA_Rel_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h299; end
+    EA_Idx_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h299; end
+    EA_Abs_W:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h299; end
+    EA_Abs_L:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h299; end
+    EA_Rel_PC: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
+    EA_Imm:    begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
+    default:   begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
     endcase
 
 3'b101: // Row: 5
     unique case ( col)
-     0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = 'X; end
-     1: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h10F; arA23[ 'hd] = 'X; end
-     2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h299; end
-     3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h299; end
-     4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h299; end
-     5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h299; end
-     6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h299; end
-     7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h299; end
-     8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h299; end
-     9: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
-    10: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
-    11: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
-    default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
+    EA_Dn:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C1; arA23[ 'hd] = `UNDF; end
+    EA_An:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h10F; arA23[ 'hd] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h006; arA23[ 'hd] = 'h299; end
+    EA_Post:   begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h21C; arA23[ 'hd] = 'h299; end
+    EA_Pre:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h103; arA23[ 'hd] = 'h299; end
+    EA_Rel_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C2; arA23[ 'hd] = 'h299; end
+    EA_Idx_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E3; arA23[ 'hd] = 'h299; end
+    EA_Abs_W:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00A; arA23[ 'hd] = 'h299; end
+    EA_Abs_L:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E2; arA23[ 'hd] = 'h299; end
+    EA_Rel_PC: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
+    EA_Imm:    begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
+    default:   begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
     endcase
 
 3'b110: // Row: 6
     unique case ( col)
-     0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = 'X; end
-     1: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h10B; arA23[ 'hd] = 'X; end
-     2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00B; arA23[ 'hd] = 'h29D; end
-     3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00F; arA23[ 'hd] = 'h29D; end
-     4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h179; arA23[ 'hd] = 'h29D; end
-     5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h29D; end
-     6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h29D; end
-     7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00E; arA23[ 'hd] = 'h29D; end
-     8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E6; arA23[ 'hd] = 'h29D; end
-     9: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
-    10: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
-    11: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
-    default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
+    EA_Dn:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = `UNDF; end
+    EA_An:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h10B; arA23[ 'hd] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00B; arA23[ 'hd] = 'h29D; end
+    EA_Post:   begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00F; arA23[ 'hd] = 'h29D; end
+    EA_Pre:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h179; arA23[ 'hd] = 'h29D; end
+    EA_Rel_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h29D; end
+    EA_Idx_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h29D; end
+    EA_Abs_W:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00E; arA23[ 'hd] = 'h29D; end
+    EA_Abs_L:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E6; arA23[ 'hd] = 'h29D; end
+    EA_Rel_PC: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
+    EA_Idx_PC: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
+    EA_Imm:    begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
+    default:   begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
     endcase
 
 3'b111: // Row: 7
     unique case ( col)
-     0: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = 'X; end
-     1: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = 'X; end
-     2: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00B; arA23[ 'hd] = 'h1CB; end
-     3: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00F; arA23[ 'hd] = 'h1CB; end
-     4: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h179; arA23[ 'hd] = 'h1CB; end
-     5: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h1CB; end
-     6: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h1CB; end
-     7: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00E; arA23[ 'hd] = 'h1CB; end
-     8: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E6; arA23[ 'hd] = 'h1CB; end
-     9: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h1CB; end
-    10: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h1CB; end
-    11: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0A7; arA23[ 'hd] = 'h1C5; end
-    default: begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = 'X   ; arA23[ 'hd] = 'X; end
+    EA_Dn:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = `UNDF; end
+    EA_An:     begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C5; arA23[ 'hd] = `UNDF; end
+    EA_Ind:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00B; arA23[ 'hd] = 'h1CB; end
+    EA_Post:   begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00F; arA23[ 'hd] = 'h1CB; end
+    EA_Pre:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h179; arA23[ 'hd] = 'h1CB; end
+    EA_Rel_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h1CB; end
+    EA_Idx_An: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h1CB; end
+    EA_Abs_W:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h00E; arA23[ 'hd] = 'h1CB; end
+    EA_Abs_L:  begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E6; arA23[ 'hd] = 'h1CB; end
+    EA_Rel_PC: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1C6; arA23[ 'hd] = 'h1CB; end
+    EA_Idx_PC: begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h1E7; arA23[ 'hd] = 'h1CB; end
+    EA_Imm:    begin arIll[ 'hd] = 1'b0; arA1[ 'hd] = 'h0A7; arA23[ 'hd] = 'h1C5; end
+    default:   begin arIll[ 'hd] = 1'b1; arA1[ 'hd] = `UNDF; arA23[ 'hd] = `UNDF; end
     endcase
 endcase
 end

From 5c87f895ff60dacef67cca6b82b5e35220f77005 Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Fri, 28 Aug 2020 19:19:43 +0200
Subject: [PATCH 02/16] Use a separate clock signal for verilator

---
 fx68k.sv     | 213 ++++++++++++++++++++++++++++++++-------------------
 fx68k_pkg.sv | 154 ++++++++++++++++++-------------------
 2 files changed, 212 insertions(+), 155 deletions(-)

diff --git a/fx68k.sv b/fx68k.sv
index c5660ae..742ab82 100644
--- a/fx68k.sv
+++ b/fx68k.sv
@@ -46,7 +46,7 @@ module fx68k
 
     s_clks Clks;
 
-    assign Clks.clk = clk;
+    //assign Clks.clk      = clk;
     assign Clks.extReset = extReset;
     assign Clks.pwrUp    = pwrUp;
     assign Clks.enPhi1   = enPhi1;
@@ -63,7 +63,7 @@ module fx68k
 
     // T4 continues ticking during reset and group0 exception.
     // We also need it to erase ucode output latched on T4.
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         if (Clks.pwrUp) begin
             tState <= T0;
@@ -94,7 +94,7 @@ module fx68k
     // reg rBR, rHALT;
     wire BeDebounced = ~( BeI | BeiDelay);
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         if (Clks.pwrUp) begin
             rBerr    <= 1'b0;
@@ -138,10 +138,10 @@ module fx68k
 
     // Output of these modules will be updated at T2 at the latest (depending on clock division)
 
-    nanoRom nanoRom( .clk( Clks.clk), .nanoAddr, .nanoOutput);
-    uRom uRom( .clk( Clks.clk), .microAddr, .microOutput);
+    nanoRom nanoRom( .clk(clk), .nanoAddr, .nanoOutput);
+    uRom uRom( .clk(clk), .microAddr, .microOutput);
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
         // uaddr originally latched on T1, except bits 6 & 7, the conditional bits, on T2
         // Seems we can latch whole address at either T1 or T2
 
@@ -201,7 +201,8 @@ module fx68k
 
 
     // IR & IRD forwarding
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
+
         if (enT1) begin
             if (Nanod.Ir2Ird)
                 Ird <= Ir;
@@ -237,38 +238,38 @@ module fx68k
 
     uaddrDecode uaddrDecode( .opcode( Ir), .a1, .a2, .a3, .isPriv, .isIllegal, .isLineA, .isLineF, .lineBmap());
 
-    sequencer sequencer( .Clks, .enT3, .microLatch, .Ird,
+    sequencer sequencer( .clk, .Clks, .enT3, .microLatch, .Ird,
         .A0Err, .excRst, .BerrA, .busAddrErr, .Spuria, .Avia,
         .Tpend, .intPend, .isIllegal, .isPriv, .isLineA, .isLineF,
         .nma, .a1, .a2, .a3, .tvn,
         .psw, .prenEmpty, .au05z, .dcr4, .ze, .alue01( alue[1:0]), .i11( Irc[ 11]) );
 
-    excUnit excUnit( .Clks, .Nanod, .Irdecod, .enT1, .enT2, .enT3, .enT4,
+    excUnit excUnit( .clk, .Clks, .Nanod, .Irdecod, .enT1, .enT2, .enT3, .enT4,
         .Ird, .ftu, .iEdb, .pswS,
         .prenEmpty, .au05z, .dcr4, .ze, .AblOut( Abl), .eab, .aob0, .Irc, .oEdb,
         .alue, .ccr);
 
-    nDecoder3 nDecoder( .Clks, .Nanod, .Irdecod, .enT2, .enT4, .microLatch, .nanoLatch);
+    nDecoder3 nDecoder( .clk, .Nanod, .Irdecod, .enT2, .enT4, .microLatch, .nanoLatch);
 
     irdDecode irdDecode( .ird( Ird), .Irdecod);
 
-    busControl busControl( .Clks, .enT1, .enT4, .permStart( Nanod.permStart), .permStop( Nanod.waitBusFinish), .iStop,
+    busControl busControl( .clk, .Clks, .enT1, .enT4, .permStart( Nanod.permStart), .permStop( Nanod.waitBusFinish), .iStop,
         .aob0, .isWrite( Nanod.isWrite), .isRmc( Nanod.isRmc), .isByte( busIsByte), .busAvail,
         .bciWrite, .addrOe, .bgBlock, .waitBusCycle, .busStarting, .busAddrErr,
         .rDtack, .BeDebounced, .Vpai,
         .ASn, .LDSn, .UDSn, .eRWn);
 
-    busArbiter busArbiter( .Clks, .BRi, .BgackI, .Halti, .bgBlock, .busAvail, .BGn);
+    busArbiter busArbiter( .clk, .Clks, .BRi, .BgackI, .Halti, .bgBlock, .busAvail, .BGn);
 
 
     // Output reset & halt control
-    wire [1:0] uFc = microLatch[ 16:15];
+    wire [1:0] uFc = microLatch[16:15];
     logic oReset, oHalted;
     assign oRESETn = !oReset;
     assign oHALTEDn = !oHalted;
 
     // FC without permStart is special, either reset or halt
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         if (Clks.pwrUp) begin
             oReset  <= 1'b0;
@@ -284,7 +285,7 @@ module fx68k
     assign { FC2, FC1, FC0} = rFC;                  // ~rFC;
     assign Iac = {rFC == 3'b111};                   // & Control output enable !!
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         if (Clks.extReset) begin
             rFC <= 3'b000;
@@ -308,7 +309,7 @@ module fx68k
     wire iplStable = (iIpl == rIpl);
     wire iplComp = iIpl > pswI;
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         if (Clks.extReset) begin
             intPend <= 1'b0;
@@ -367,7 +368,7 @@ module fx68k
     // Internal stop just one cycle before E falling edge
     wire xVma = ~rVma & (eCntr == 8);
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         if (Clks.pwrUp) begin
             E     <= 1'b0;
@@ -392,7 +393,7 @@ module fx68k
             rVma <= 1'b1;
     end
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         // This timing is critical to stop the clock phases at the exact point on bus/addr error.
         // Timing should be such that current ublock completes (up to T3 or T4).
@@ -449,7 +450,7 @@ module fx68k
 
     // PSW
     logic irdToCcr_t4;
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         if (Clks.pwrUp) begin
             Tpend <= 1'b0;
@@ -495,7 +496,7 @@ module fx68k
     // Flagging group 0 exceptions from TVN might not work because some bus cycles happen before TVN is updated.
     // But doesn't matter because a group 0 exception inside another one will halt the CPU anyway and won't save the SSW.
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         // Updated at the start of the exception ucode
         if (Nanod.updSsw & enT3) begin
@@ -551,7 +552,7 @@ endmodule
 // Nanorom (plus) decoder for die nanocode
 module nDecoder3
 (
-    input                   s_clks Clks,
+    input                   clk,
     input                   enT2,
     input                   enT4,
     input  [UROM_WIDTH-1:0] microLatch,
@@ -637,7 +638,7 @@ localparam [3:0]
     wire [1:0] aobCtrl = nanoLatch[NANO_AOBCTRL +: 2];
     wire [1:0] dobCtrl = { nanoLatch[ NANO_DOBCTRL_1], nanoLatch[NANO_DOBCTRL_0] };
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         if (enT4) begin
 
@@ -1055,6 +1056,7 @@ endmodule
 
 module excUnit
 (
+    input clk,
     input s_clks Clks,
     input enT1, enT2, enT3, enT4,
     input s_nanod Nanod,
@@ -1206,7 +1208,7 @@ localparam
 
     end
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
     
         if (enT4) begin
             byteNotSpAlign <= Irdecod.isByte & ~(Nanod.rxlDbl ? rxIsSp : ryIsSp);
@@ -1309,7 +1311,7 @@ localparam
     reg [15:0] preAbh, preAbl, preAbd;
     reg [15:0] preDbh, preDbl, preDbd;
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         // Register first level mux at T1
         if (enT1) begin
@@ -1373,7 +1375,7 @@ localparam
 
     wire au2Aob = Nanod.au2Aob | (Nanod.au2Db & Nanod.db2Aob);
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
         // UNIQUE IF !
 
         if (enT1 & au2Aob)      // From AU we do can on T1
@@ -1420,7 +1422,8 @@ localparam
     wire [31:0] auResult = {Dbh + auInpMux[31:16] + {15'b0, aulow[16]}, aulow[15:0]};
 // synthesis translate_on
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
+
         if (Clks.pwrUp)
             auReg <= '0;
         else if (enT3 & Nanod.auClkEn)
@@ -1434,7 +1437,8 @@ localparam
 
     // Main A/D registers
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
+
         if (enT3) begin
             if (Nanod.dbl2rxl | Nanod.abl2rxl) begin
                 if (~rxIsAreg) begin
@@ -1468,7 +1472,8 @@ localparam
     // PC & AT
     reg dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl;
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
+    
         if (Clks.extReset) begin
             { dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl } <= '0;
 
@@ -1537,7 +1542,8 @@ localparam
     assign prenEmpty = (~| prenLatch);
     pren rmPren( .mask( prenLatch), .hbit (prHbit));
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
+    
         // Cheating: PREN always loaded from DBIN
         // Must be on T1 to branch earlier if reg mask is empty!
         if (enT1 & Nanod.abl2Pren)
@@ -1554,7 +1560,8 @@ localparam
     wire [3:0] dcrInput = abdIsByte ? { 1'b0, Abd[ 2:0]} : Abd[ 3:0];
     onehotEncoder4 dcrDecoder( .bin( dcrInput), .bitMap( dcrCode));
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
+
         if (Clks.pwrUp)
             dcr4 <= '0;
         else if (enT3 & Nanod.abd2Dcr) begin
@@ -1566,7 +1573,8 @@ localparam
     // ALUB
     reg [15:0] alub;
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
+
         if (enT3) begin
             // UNIQUE IF !!
             if (Nanod.dbd2Alub)
@@ -1592,12 +1600,12 @@ localparam
         endcase
     end
 
-    dataIo dataIo( .Clks, .enT1, .enT2, .enT3, .enT4, .Nanod, .Irdecod,
+    dataIo dataIo( .clk, .Clks, .enT1, .enT2, .enT3, .enT4, .Nanod, .Irdecod,
             .iEdb, .dobIdle, .dobInput, .aob0,
             .Irc, .dbin, .oEdb);
 
     fx68kAlu alu(
-        .clk( Clks.clk), .pwrUp( Clks.pwrUp), .enT1, .enT3, .enT4,
+        .clk, .pwrUp( Clks.pwrUp), .enT1, .enT3, .enT4,
         .ird( Ird),
         .aluColumn( Nanod.aluColumn), .aluAddrCtrl( Nanod.aluActrl),
         .init( Nanod.aluInit), .finish( Nanod.aluFinish), .aluIsByte( Irdecod.isByte),
@@ -1617,19 +1625,26 @@ endmodule
 // Input is latched async at the EDB register.
 // We capture directly from the external data bus to the internal registers (IRC & DBIN) on PHI2, starting the external S7 phase, at a T4 internal period.
 
-module dataIo( input s_clks Clks,
-    input enT1, enT2, enT3, enT4,
-    input s_nanod Nanod, input s_irdecod Irdecod,
-    input [15:0] iEdb,
-    input aob0,
-
-    input dobIdle,
-    input [15:0] dobInput,
+module dataIo
+(
+    input               clk,
+    input        s_clks Clks,
+    input               enT1,
+    input               enT2,
+    input               enT3,
+    input               enT4,
+    input       s_nanod Nanod,
+    input     s_irdecod Irdecod,
+    input        [15:0] iEdb,
+    input               aob0,
+
+    input               dobIdle,
+    input        [15:0] dobInput,
 
     output logic [15:0] Irc,
     output logic [15:0] dbin,
     output logic [15:0] oEdb
-    );
+);
 
     reg [15:0] dob;
 
@@ -1643,7 +1658,7 @@ module dataIo( input s_clks Clks,
     reg dbinNoLow, dbinNoHigh;
     reg byteMux, isByte_T4;
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         // Byte mux control. Can't latch at T1. AOB might be not ready yet.
         // Must latch IRD decode at T1 (or T4). Then combine and latch only at T3.
@@ -1686,7 +1701,7 @@ module dataIo( input s_clks Clks,
     // DOB
     logic byteCycle;
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
         // Originaly on T1. Transfer to internal EDB also on T1 (stays enabled upto the next T1). But only on T4 (S3) output enables.
         // It is safe to do on T3, then, but control signals if derived from IRD must be registered.
         // Originally control signals are not registered.
@@ -1846,17 +1861,39 @@ endmodule
 
 // Microcode sequencer
 
-module sequencer( input s_clks Clks, input enT3,
-    input [UROM_WIDTH-1:0] microLatch,
-    input A0Err, BerrA, busAddrErr, Spuria, Avia,
-    input Tpend, intPend, isIllegal, isPriv, excRst, isLineA, isLineF,
-    input [15:0] psw,
-    input prenEmpty, au05z, dcr4, ze, i11,
-    input [1:0] alue01,
-    input [15:0] Ird,
-    input [UADDR_WIDTH-1:0] a1, a2, a3,
-    output logic [3:0] tvn,
-    output logic [UADDR_WIDTH-1:0] nma);
+module sequencer
+(
+    input                   clk,
+    input            s_clks Clks,
+    input                   enT3,
+    input  [UROM_WIDTH-1:0] microLatch,
+    input                   A0Err,
+    input                   BerrA,
+    input                   busAddrErr,
+    input                   Spuria,
+    input                   Avia,
+    input                   Tpend,
+    input                   intPend,
+    input                   isIllegal,
+    input                   isPriv,
+    input                   excRst,
+    input                   isLineA,
+    input                   isLineF,
+    input            [15:0] psw,
+    input                   prenEmpty,
+    input                   au05z,
+    input                   dcr4,
+    input                   ze,
+    input                   i11,
+    input             [1:0] alue01,
+    input            [15:0] Ird,
+    input [UADDR_WIDTH-1:0] a1,
+    input [UADDR_WIDTH-1:0] a2,
+    input [UADDR_WIDTH-1:0] a3,
+    
+    output logic             [3:0] tvn,
+    output logic [UADDR_WIDTH-1:0] nma
+);
 
     logic [UADDR_WIDTH-1:0] uNma;
     logic [UADDR_WIDTH-1:0] grp1Nma;
@@ -2019,7 +2056,7 @@ module sequencer( input s_clks Clks, input enT3,
 
     assign inGrp0Exc = rExcRst | rExcBusErr | rExcAdrErr;
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
         if (grp0LatchEn & enT3) begin
             rExcRst <= excRst;
             rExcBusErr <= BerrA;
@@ -2073,7 +2110,7 @@ module sequencer( input s_clks Clks, input enT3,
 
     assign A0Sel = rIllegal | rLineF | rLineA | rPriv | rTrace | rInterrupt;
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
         if (Clks.extReset)
             a0Rst <= 1'b1;
         else if (enT3)
@@ -2089,9 +2126,13 @@ endmodule
 
 module busArbiter
 (
+    input        clk,
     input s_clks Clks,
-    input BRi, BgackI, Halti, bgBlock,
-    output busAvail,
+    input        BRi,
+    input        BgackI,
+    input        Halti,
+    input        bgBlock,
+    output       busAvail,
     output logic BGn
 );
 
@@ -2153,7 +2194,7 @@ module busArbiter
     reg rGranted;
     assign busAvail = Halti & BRi & BgackI & ~rGranted;
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         if (Clks.extReset) begin
             dmaPhase <= DRESET;
@@ -2175,20 +2216,35 @@ module busArbiter
 
 endmodule
 
-module busControl( input s_clks Clks, input enT1, input enT4,
-        input permStart, permStop, iStop,
-        input aob0,
-        input isWrite, isByte, isRmc,
-        input busAvail,
-        output bgBlock,
-        output busAddrErr,
-        output waitBusCycle,
-        output busStarting,         // Asserted during S0
-        output logic addrOe,        // Asserted from S1 to the end, whole bus cycle except S0
-        output bciWrite,            // Used for SSW on bus/addr error
-
-        input rDtack, BeDebounced, Vpai,
-        output ASn, output LDSn, output UDSn, eRWn);
+module busControl
+(
+    input         clk,
+    input  s_clks Clks,
+    input         enT1,
+    input         enT4,
+    input         permStart,
+    input         permStop,
+    input         iStop,
+    input         aob0,
+    input         isWrite,
+    input         isByte,
+    input         isRmc,
+    input         busAvail,
+    output        bgBlock,
+    output        busAddrErr,
+    output        waitBusCycle,
+    output        busStarting,  // Asserted during S0
+    output logic  addrOe,       // Asserted from S1 to the end, whole bus cycle except S0
+    output        bciWrite,     // Used for SSW on bus/addr error
+
+    input         rDtack,
+    input         BeDebounced,
+    input         Vpai,
+    output        ASn,
+    output        LDSn,
+    output        UDSn,
+    output        eRWn
+);
 
     reg rAS, rLDS, rUDS, rRWn;
     assign ASn = rAS;
@@ -2217,7 +2273,7 @@ module busControl( input s_clks Clks, input enT1, input enT4,
 
     enum int unsigned { SRESET = 0, SIDLE, S0, S2, S4, S6, SRMC_RES} busPhase, next;
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
         if (Clks.extReset)
             busPhase <= SRESET;
         else if (Clks.enPhi1)
@@ -2266,7 +2322,8 @@ module busControl( input s_clks Clks, input enT1, input enT4,
     // Except that when that RMC phase aborted on bus error, it's asserted one cycle later!
     assign bgBlock = ((busPhase == S0) & ASn) | (busPhase == SRMC_RES);
 
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
+    
         if (Clks.extReset) begin
             addrOe <= 1'b0;
         end
@@ -2340,7 +2397,7 @@ module busControl( input s_clks Clks, input enT1, input enT4,
     // permStop also latched, but unconditionally on T1
 
     // Might make more sense to register this outside this module
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         if (enT4) begin
             isByteT4 <= isByte;
@@ -2348,7 +2405,7 @@ module busControl( input s_clks Clks, input enT1, input enT4,
     end
 
     // Bus Cycle Info Latch
-    always_ff @( posedge Clks.clk) begin
+    always_ff @(posedge clk) begin
 
         if (Clks.pwrUp) begin
             bcPend     <= 1'b0;
diff --git a/fx68k_pkg.sv b/fx68k_pkg.sv
index 52f6dae..a807bc2 100644
--- a/fx68k_pkg.sv
+++ b/fx68k_pkg.sv
@@ -49,93 +49,93 @@ localparam [3:0]
 // Clocks, phases and resets
 typedef struct packed
 {
-	logic clk;
-	logic extReset;			// External sync reset on emulated system
-	logic pwrUp;			// Asserted together with reset on emulated system coldstart
-	logic enPhi1, enPhi2;	// Clock enables. Next cycle is PHI1 or PHI2
+    //logic clk;
+    logic extReset;         // External sync reset on emulated system
+    logic pwrUp;            // Asserted together with reset on emulated system coldstart
+    logic enPhi1, enPhi2;   // Clock enables. Next cycle is PHI1 or PHI2
 } s_clks;
 
 // IRD decoded signals
 typedef struct packed
 {
-	logic isPcRel;
-	logic isTas;
-	logic implicitSp;
-	logic toCcr;
-	logic rxIsDt, ryIsDt;
-	logic rxIsUsp, rxIsMovem, movemPreDecr;
-	logic isByte;
-	logic isMovep;
-	logic [2:0] rx, ry;
-	logic rxIsAreg, ryIsAreg;
-	logic [15:0] ftuConst;
-	logic [5:0] macroTvn;
-	logic inhibitCcr;
+    logic isPcRel;
+    logic isTas;
+    logic implicitSp;
+    logic toCcr;
+    logic rxIsDt, ryIsDt;
+    logic rxIsUsp, rxIsMovem, movemPreDecr;
+    logic isByte;
+    logic isMovep;
+    logic [2:0] rx, ry;
+    logic rxIsAreg, ryIsAreg;
+    logic [15:0] ftuConst;
+    logic [5:0] macroTvn;
+    logic inhibitCcr;
 } s_irdecod;
 
 // Nano code decoded signals
 typedef struct packed
 {
-	logic permStart;
-	logic waitBusFinish;
-	logic isWrite;
-	logic busByte;
-	logic isRmc;
-	logic noLowByte, noHighByte;
-	
-	logic updTpend, clrTpend;
-	logic tvn2Ftu, const2Ftu;
-	logic ftu2Dbl, ftu2Abl;
-	logic abl2Pren, updPren;
-	logic inl2psw, ftu2Sr, sr2Ftu, ftu2Ccr, pswIToFtu;
-	logic ird2Ftu, ssw2Ftu;
-	logic initST;
-	logic Ir2Ird;
-	
-	logic auClkEn, noSpAlign;
-	logic [2:0] auCntrl;
-	logic todbin, toIrc;
-	logic dbl2Atl, abl2Atl, atl2Abl, atl2Dbl;
-	logic abh2Ath, dbh2Ath;
-	logic ath2Dbh, ath2Abh;
-	
-	logic db2Aob, ab2Aob, au2Aob;
-	logic aob2Ab, updSsw;
-	// logic adb2Dob, dbd2Dob, alu2Dob;
-	logic [1:0] dobCtrl;
-	
-	logic abh2reg, abl2reg;
-	logic reg2abl, reg2abh;
-	logic dbh2reg, dbl2reg;
-	logic reg2dbl, reg2dbh;
-	logic ssp, pchdbh, pcldbl, pclabl, pchabh;
-	
-	logic rxh2dbh, rxh2abh;
-	logic dbl2rxl, dbh2rxh;
-	logic rxl2db, rxl2ab;
-	logic abl2rxl, abh2rxh;
-	logic dbh2ryh, abh2ryh;
-	logic ryl2db, ryl2ab;
-	logic ryh2dbh, ryh2abh;
-	logic dbl2ryl, abl2ryl;
-	logic rz;
-	logic rxlDbl;
-	
-	logic [2:0] aluColumn;
-	logic [1:0] aluDctrl;
-	logic aluActrl;
-	logic aluInit, aluFinish;
-	logic abd2Dcr, dcr2Dbd;
-	logic dbd2Alue, alue2Dbd;
-	logic dbd2Alub, abd2Alub;
-	
-	logic alu2Dbd, alu2Abd;
-	logic au2Db, au2Ab, au2Pc;
-	logic dbin2Abd, dbin2Dbd;
-	logic extDbh, extAbh;
-	logic ablAbd, ablAbh;
-	logic dblDbd, dblDbh;
-	logic abdIsByte;
+    logic permStart;
+    logic waitBusFinish;
+    logic isWrite;
+    logic busByte;
+    logic isRmc;
+    logic noLowByte, noHighByte;
+    
+    logic updTpend, clrTpend;
+    logic tvn2Ftu, const2Ftu;
+    logic ftu2Dbl, ftu2Abl;
+    logic abl2Pren, updPren;
+    logic inl2psw, ftu2Sr, sr2Ftu, ftu2Ccr, pswIToFtu;
+    logic ird2Ftu, ssw2Ftu;
+    logic initST;
+    logic Ir2Ird;
+    
+    logic auClkEn, noSpAlign;
+    logic [2:0] auCntrl;
+    logic todbin, toIrc;
+    logic dbl2Atl, abl2Atl, atl2Abl, atl2Dbl;
+    logic abh2Ath, dbh2Ath;
+    logic ath2Dbh, ath2Abh;
+    
+    logic db2Aob, ab2Aob, au2Aob;
+    logic aob2Ab, updSsw;
+    // logic adb2Dob, dbd2Dob, alu2Dob;
+    logic [1:0] dobCtrl;
+    
+    logic abh2reg, abl2reg;
+    logic reg2abl, reg2abh;
+    logic dbh2reg, dbl2reg;
+    logic reg2dbl, reg2dbh;
+    logic ssp, pchdbh, pcldbl, pclabl, pchabh;
+    
+    logic rxh2dbh, rxh2abh;
+    logic dbl2rxl, dbh2rxh;
+    logic rxl2db, rxl2ab;
+    logic abl2rxl, abh2rxh;
+    logic dbh2ryh, abh2ryh;
+    logic ryl2db, ryl2ab;
+    logic ryh2dbh, ryh2abh;
+    logic dbl2ryl, abl2ryl;
+    logic rz;
+    logic rxlDbl;
+    
+    logic [2:0] aluColumn;
+    logic [1:0] aluDctrl;
+    logic aluActrl;
+    logic aluInit, aluFinish;
+    logic abd2Dcr, dcr2Dbd;
+    logic dbd2Alue, alue2Dbd;
+    logic dbd2Alub, abd2Alub;
+    
+    logic alu2Dbd, alu2Abd;
+    logic au2Db, au2Ab, au2Pc;
+    logic dbin2Abd, dbin2Dbd;
+    logic extDbh, extAbh;
+    logic ablAbd, ablAbh;
+    logic dblDbd, dblDbh;
+    logic abdIsByte;
 } s_nanod;
 
 // EA decode

From ddf753f54df988a99937a4922fd686c24d960a71 Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Fri, 28 Aug 2020 19:46:31 +0200
Subject: [PATCH 03/16] Fixed UNOPTFLAT verilator warning on Irdecod structure

---
 fx68k.sv | 175 +++++++++++++++++++++++++++++++++----------------------
 1 file changed, 104 insertions(+), 71 deletions(-)

diff --git a/fx68k.sv b/fx68k.sv
index 742ab82..49bb2e9 100644
--- a/fx68k.sv
+++ b/fx68k.sv
@@ -851,57 +851,66 @@ module irdDecode
     // This can be registered and pipelined from the IR decoder !
     onehotEncoder4 irdLines( line, lineOnehot);
 
-    wire isRegShift = (lineOnehot['he]) & (ird[7:6] != 2'b11);
+    reg  implicitSp;
+    
+    wire isRegShift = (lineOnehot[4'hE]) & (ird[7:6] != 2'b11);
     wire isDynShift = isRegShift & ird[5];
+    wire isTas      = (ird[11:6] == 6'b101011) ? lineOnehot[4'h4] : 1'b0;
 
     assign Irdecod.isPcRel = (& ird[ 5:3]) & ~isDynShift & !ird[2] & ird[1];
-    assign Irdecod.isTas = lineOnehot[4] & (ird[11:6] == 6'b101011);
+    assign Irdecod.isTas   = isTas;
 
     assign Irdecod.rx = ird[11:9];
     assign Irdecod.ry = ird[ 2:0];
 
-    wire isPreDecr = (ird[ 5:3] == 3'b100);
-    wire eaAreg = (ird[5:3] == 3'b001);
+    wire isPreDecr = (ird[5:3] == 3'b100) ? 1'b1 : 1'b0;
+    wire eaAreg    = (ird[5:3] == 3'b001) ? 1'b1 : 1'b0;
 
     // rx is A or D
     // movem
     always_comb begin
         unique case (1'b1)
-        lineOnehot[1],
-        lineOnehot[2],
-        lineOnehot[3]:
-                    // MOVE: RX always Areg except if dest mode is Dn 000
-                    Irdecod.rxIsAreg = (| ird[8:6]);
-
-        lineOnehot[4]:      Irdecod.rxIsAreg = (& ird[8:6]);        // not CHK (LEA)
-
-        lineOnehot['h8]:    Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7];   // SBCD
-        lineOnehot['hc]:    Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7];   // ABCD/EXG An,An
-
-        lineOnehot['h9],
-        lineOnehot['hb],
-        lineOnehot['hd]:    Irdecod.rxIsAreg =
-                            (ird[7] & ird[6]) |                             // SUBA/CMPA/ADDA
-                            (eaAreg & ird[8] & (ird[7:6] != 2'b11));        // SUBX/CMPM/ADDX
-        default:
-                Irdecod.rxIsAreg = Irdecod.implicitSp;
+            lineOnehot[4'h1],
+            lineOnehot[4'h2],
+            lineOnehot[4'h3]:
+                // MOVE: RX always Areg except if dest mode is Dn 000
+                Irdecod.rxIsAreg = (|ird[8:6]);
+
+            lineOnehot[4'h4]:
+                // not CHK (LEA)
+                Irdecod.rxIsAreg = (&ird[8:6]);
+
+            lineOnehot[4'h8]:
+                // SBCD
+                Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7];
+                
+            lineOnehot[4'hC]:
+                // ABCD/EXG An,An
+                Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7];
+
+            lineOnehot[4'h9],
+            lineOnehot[4'hB],
+            lineOnehot[4'hD]:
+                Irdecod.rxIsAreg =
+                    (ird[7] & ird[6]) |                      // SUBA/CMPA/ADDA
+                    (eaAreg & ird[8] & (ird[7:6] != 2'b11)); // SUBX/CMPM/ADDX
+            default:
+                Irdecod.rxIsAreg = implicitSp;
         endcase
     end
 
     // RX is movem
-    always_comb begin
-        Irdecod.rxIsMovem = lineOnehot[4] & ~ird[8] & ~Irdecod.implicitSp;
-    end
-    assign Irdecod.movemPreDecr = Irdecod.rxIsMovem & isPreDecr;
+    assign Irdecod.rxIsMovem    = lineOnehot[4'h4] & ~ird[8] & ~implicitSp;
+    assign Irdecod.movemPreDecr = lineOnehot[4'h4] & ~ird[8] & ~implicitSp & isPreDecr;
 
     // RX is DT.
     // but SSP explicit or pc explicit has higher priority!
     // addq/subq (scc & dbcc also, but don't use rx)
     // Immediate including static bit
-    assign Irdecod.rxIsDt = lineOnehot[5] | (lineOnehot[0] & ~ird[8]);
+    assign Irdecod.rxIsDt = lineOnehot[4'h5] | (lineOnehot[4'h0] & ~ird[8]);
 
     // RX is USP
-    assign Irdecod.rxIsUsp = lineOnehot[4] & (ird[ 11:4] == 8'he6);
+    assign Irdecod.rxIsUsp = lineOnehot[4'h4] & (ird[11:4] == 8'hE6);
 
     // RY is DT
     // rz or PC explicit has higher priority
@@ -917,18 +926,21 @@ module irdDecode
         eaIsAreg = (ird[5:3] != 3'b000) & (ird[5:3] != 3'b111);
 
         unique case (1'b1)
-                // MOVE: RY always Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL)
-                // Most lines, including misc line 4, also.
-        default:        Irdecod.ryIsAreg = eaIsAreg;
+            // MOVE: RY always Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL)
+            // Most lines, including misc line 4, also.
+            default:
+                Irdecod.ryIsAreg = eaIsAreg;
 
-        lineOnehot[5]:  // DBcc is an exception
-                        Irdecod.ryIsAreg = eaIsAreg & (ird[7:3] != 5'b11001);
+            lineOnehot[4'h5]:
+                // DBcc is an exception
+                Irdecod.ryIsAreg = eaIsAreg & (ird[7:3] != 5'b11001);
 
-        lineOnehot[6],
-        lineOnehot[7]:  Irdecod.ryIsAreg = 1'b0;
+            lineOnehot[4'h6],
+            lineOnehot[4'h7]:
+                Irdecod.ryIsAreg = 1'b0;
 
-        lineOnehot['he]:
-                        Irdecod.ryIsAreg = ~isRegShift;
+            lineOnehot[4'hE]:
+                Irdecod.ryIsAreg = ~isRegShift;
         endcase
     end
 
@@ -941,32 +953,38 @@ module irdDecode
     wire xStaticMem = (ird[11:8] == 4'b1000) & (ird[5:4] == 2'b00);     // Static bit to mem
     always_comb begin
         unique case (1'b1)
-        lineOnehot[0]:
+            lineOnehot[4'h0]:
                 Irdecod.isByte =
                 ( ird[8] & (ird[5:4] != 2'b00)                  ) | // Dynamic bit to mem
                 ( (ird[11:8] == 4'b1000) & (ird[5:4] != 2'b00)  ) | // Static bit to mem
                 ( (ird[8:7] == 2'b10) & (ird[5:3] == 3'b001)    ) | // Movep from mem only! For byte mux
                 ( (ird[8:6] == 3'b000) & !xStaticMem );             // Immediate byte
 
-        lineOnehot[1]:          Irdecod.isByte = 1'b1;      // MOVE.B
+            lineOnehot[4'h1]:
+                Irdecod.isByte = 1'b1;      // MOVE.B
+
 
+            lineOnehot[4'h4]:
+                Irdecod.isByte = (ird[7:6] == 2'b00) | isTas;
 
-        lineOnehot[4]:          Irdecod.isByte = (ird[7:6] == 2'b00) | Irdecod.isTas;
-        lineOnehot[5]:          Irdecod.isByte = (ird[7:6] == 2'b00) | xIsScc;
+            lineOnehot[4'h5]:
+                Irdecod.isByte = (ird[7:6] == 2'b00) | xIsScc;
 
-        lineOnehot[8],
-        lineOnehot[9],
-        lineOnehot['hb],
-        lineOnehot['hc],
-        lineOnehot['hd],
-        lineOnehot['he]:        Irdecod.isByte = (ird[7:6] == 2'b00);
+            lineOnehot[4'h8],
+            lineOnehot[4'h9],
+            lineOnehot[4'hB],
+            lineOnehot[4'hC],
+            lineOnehot[4'hD],
+            lineOnehot[4'hE]:
+                Irdecod.isByte = (ird[7:6] == 2'b00);
 
-        default:                Irdecod.isByte = 1'b0;
+            default:
+                Irdecod.isByte = 1'b0;
         endcase
     end
 
     // Need it for special byte size. Bus is byte, but whole register word is modified.
-    assign Irdecod.isMovep = lineOnehot[0] & ird[8] & eaAreg;
+    assign Irdecod.isMovep = lineOnehot[4'h0] & ird[8] & eaAreg;
 
 
     // rxIsSP implicit use of RX for actual SP transfer
@@ -976,13 +994,17 @@ module irdDecode
 
     always_comb begin
         unique case (1'b1)
-        lineOnehot[6]:      Irdecod.implicitSp = (ird[11:8] == 4'b0001);        // BSR
-        lineOnehot[4]:
-            // Misc like RTS, JSR, etc
-            Irdecod.implicitSp = (ird[11:8] == 4'b1110) | (ird[11:6] == 6'b1000_01);
-        default:            Irdecod.implicitSp = 1'b0;
+            lineOnehot[6]:
+                // BSR
+                implicitSp = (ird[11:8] == 4'b0001);
+            lineOnehot[4]:
+                // Misc like RTS, JSR, etc
+                implicitSp = (ird[11:8] == 4'b1110) | (ird[11:6] == 6'b1000_01);
+            default:
+                implicitSp = 1'b0;
         endcase
     end
+    assign Irdecod.implicitSp = implicitSp;
 
     // Modify CCR (and not SR)
     // Probably overkill !! Only needs to distinguish SR vs CCR
@@ -998,19 +1020,25 @@ module irdDecode
 
     always_comb begin
         unique case (1'b1)
-        lineOnehot[6],                                                      // Bcc short
-        lineOnehot[7]:      ftuConst = { { 8{ ird[ 7]}}, ird[ 7:0] };       // MOVEQ
-
-        lineOnehot['h5],                                                    // addq/subq/static shift double check this
-        lineOnehot['he]:    ftuConst = { 12'b0, zero28};
+            lineOnehot[4'h6], // Bcc short
+            lineOnehot[4'h7]: // MOVEQ
+                ftuConst = { {8{ird[7]}}, ird[7:0] };
+
+            // ADDQ/SUBQ/static shift double check this
+            lineOnehot[4'h5],
+            lineOnehot[4'hE]:
+                ftuConst = { 12'h000, zero28};
 
-        // MULU/MULS DIVU/DIVS
-        lineOnehot['h8],
-        lineOnehot['hc]:    ftuConst = 16'h0f;
+            // MULU/MULS DIVU/DIVS
+            lineOnehot[4'h8],
+            lineOnehot[4'hC]:
+                ftuConst = 16'h000F;
 
-        lineOnehot[4]:      ftuConst = 16'h80;                              // TAS
+            lineOnehot[4]: // TAS
+                ftuConst = 16'h8000;
 
-        default:            ftuConst = '0;
+            default:
+                ftuConst = 16'h0000;
         endcase
     end
     assign Irdecod.ftuConst = ftuConst;
@@ -1020,15 +1048,20 @@ module irdDecode
     //
 
     always_comb begin
-        if (lineOnehot[4]) begin
-            case ( ird[6:5])
-            2'b00,2'b01:    Irdecod.macroTvn = 6;                   // CHK
-            2'b11:          Irdecod.macroTvn = 7;                   // TRAPV
-            2'b10:          Irdecod.macroTvn = {2'b10, ird[3:0]};   // TRAP
+        if (lineOnehot[4'h4]) begin
+            case (ird[6:5])
+                2'b00,
+                2'b01:
+                    Irdecod.macroTvn = 6'h6;                // CHK
+                2'b11:
+                    Irdecod.macroTvn = 6'h7;                // TRAPV
+                2'b10:
+                    Irdecod.macroTvn = { 2'b10, ird[3:0] }; // TRAP
             endcase
         end
-        else
-                            Irdecod.macroTvn = 5;                   // Division by zero
+        else begin
+            Irdecod.macroTvn = 6'h5; // Division by zero
+        end
     end
 
 

From 83d7dfe0e13937c51266bc56008fd64ad6e4fa31 Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Fri, 28 Aug 2020 20:52:37 +0200
Subject: [PATCH 04/16] Fixed UNOPTFLAT verilator warning on Nanod structure

---
 fx68k.sv     | 554 +++++++++++++++++++++++++++------------------------
 fx68k_pkg.sv | 208 ++++++++++++-------
 2 files changed, 425 insertions(+), 337 deletions(-)

diff --git a/fx68k.sv b/fx68k.sv
index 49bb2e9..562aa9e 100644
--- a/fx68k.sv
+++ b/fx68k.sv
@@ -175,7 +175,8 @@ module fx68k
 
 
     // Decoded nanocode signals
-    s_nanod Nanod;
+    s_nanod_r Nanod_r;
+    s_nanod_w Nanod_w;
     // IRD decoded control signals
     s_irdecod Irdecod;
 
@@ -204,10 +205,13 @@ module fx68k
     always_ff @(posedge clk) begin
 
         if (enT1) begin
-            if (Nanod.Ir2Ird)
+            if (Nanod_w.Ir2Ird) begin
                 Ird <= Ir;
-            else if(microLatch[0])      // prevented by IR => IRD !
+            end
+            else if(microLatch[0]) begin
+                // prevented by IR => IRD !
                 Ir <= Irc;
+            end
         end
     end
 
@@ -219,7 +223,7 @@ module fx68k
     wire bgBlock, busAvail;
     wire addrOe;
 
-    wire busIsByte = Nanod.busByte & (Irdecod.isByte | Irdecod.isMovep);
+    wire busIsByte = Nanod_w.busByte & (Irdecod.isByte | Irdecod.isMovep);
     wire aob0;
 
     reg iStop;                              // Internal signal for ending bus cycle
@@ -236,7 +240,11 @@ module fx68k
     // Reset micro/nano latch after T4 of the current ublock.
     assign rstUrom = Clks.enPhi1 & enErrClk;
 
-    uaddrDecode uaddrDecode( .opcode( Ir), .a1, .a2, .a3, .isPriv, .isIllegal, .isLineA, .isLineF, .lineBmap());
+    uaddrDecode U_uaddrDecode
+    (
+        .opcode (Ir),
+        .a1, .a2, .a3, .isPriv, .isIllegal, .isLineA, .isLineF, .lineBmap()
+    );
 
     sequencer sequencer( .clk, .Clks, .enT3, .microLatch, .Ird,
         .A0Err, .excRst, .BerrA, .busAddrErr, .Spuria, .Avia,
@@ -244,17 +252,17 @@ module fx68k
         .nma, .a1, .a2, .a3, .tvn,
         .psw, .prenEmpty, .au05z, .dcr4, .ze, .alue01( alue[1:0]), .i11( Irc[ 11]) );
 
-    excUnit excUnit( .clk, .Clks, .Nanod, .Irdecod, .enT1, .enT2, .enT3, .enT4,
+    excUnit excUnit( .clk, .Clks, .Nanod_r, .Nanod_w, .Irdecod, .enT1, .enT2, .enT3, .enT4,
         .Ird, .ftu, .iEdb, .pswS,
         .prenEmpty, .au05z, .dcr4, .ze, .AblOut( Abl), .eab, .aob0, .Irc, .oEdb,
         .alue, .ccr);
 
-    nDecoder3 nDecoder( .clk, .Nanod, .Irdecod, .enT2, .enT4, .microLatch, .nanoLatch);
+    nDecoder3 nDecoder( .clk, .Nanod_r, .Nanod_w, .Irdecod, .enT2, .enT4, .microLatch, .nanoLatch);
 
     irdDecode irdDecode( .ird( Ird), .Irdecod);
 
-    busControl busControl( .clk, .Clks, .enT1, .enT4, .permStart( Nanod.permStart), .permStop( Nanod.waitBusFinish), .iStop,
-        .aob0, .isWrite( Nanod.isWrite), .isRmc( Nanod.isRmc), .isByte( busIsByte), .busAvail,
+    busControl busControl( .clk, .Clks, .enT1, .enT4, .permStart(Nanod_w.permStart), .permStop(Nanod_w.waitBusFinish), .iStop,
+        .aob0, .isWrite(Nanod_w.isWrite), .isRmc(Nanod_r.isRmc), .isByte(busIsByte), .busAvail,
         .bciWrite, .addrOe, .bgBlock, .waitBusCycle, .busStarting, .busAddrErr,
         .rDtack, .BeDebounced, .Vpai,
         .ASn, .LDSn, .UDSn, .eRWn);
@@ -276,8 +284,8 @@ module fx68k
             oHalted <= 1'b0;
         end
         else if (enT1) begin
-            oReset  <= (uFc == 2'b01) ? ~Nanod.permStart : 1'b0;
-            oHalted <= (uFc == 2'b10) ? ~Nanod.permStart : 1'b0;
+            oReset  <= (uFc == 2'b01) ? ~Nanod_w.permStart : 1'b0;
+            oHalted <= (uFc == 2'b10) ? ~Nanod_w.permStart : 1'b0;
         end
     end
 
@@ -290,7 +298,7 @@ module fx68k
         if (Clks.extReset) begin
             rFC <= 3'b000;
         end
-        else if (enT1 & Nanod.permStart) begin      // S0 phase of bus cycle
+        else if (enT1 & Nanod_w.permStart) begin      // S0 phase of bus cycle
             rFC[2] <= pswS;
             // If FC is type 'n' (0) at ucode, access type depends on PC relative mode
             // We don't care about RZ in this case. Those uinstructions with RZ don't start a bus cycle.
@@ -428,7 +436,7 @@ module fx68k
         // Originally cleared on 1st T2 after permstart. Must keep it until TVN latched.
         if (Clks.extReset)
             excRst <= 1'b1;
-        else if (enT2 & Nanod.permStart)
+        else if (enT2 & Nanod_w.permStart)
             excRst <= 1'b0;
 
         if (Clks.extReset)
@@ -465,21 +473,21 @@ module fx68k
         else if (enT3) begin
 
             // UNIQUE IF !!
-            if (Nanod.updTpend)
+            if (Nanod_w.updTpend)
                 Tpend <= pswT;
-            else if (Nanod.clrTpend)
+            else if (Nanod_w.clrTpend)
                 Tpend <= 1'b0;
 
             // UNIQUE IF !!
-            if (Nanod.ftu2Sr & !irdToCcr_t4) begin
+            if (Nanod_w.ftu2Sr & !irdToCcr_t4) begin
                 { pswT, pswS, pswI } <= { ftu[15], ftu[13], ftu[10:8]};
             end
             else begin
-                if (Nanod.initST) begin
+                if (Nanod_w.initST) begin
                     pswS <= 1'b1;
                     pswT <= 1'b0;
                 end
-                if (Nanod.inl2psw) begin
+                if (Nanod_w.inl2psw) begin
                     pswI <= inl;
                 end
             end
@@ -499,12 +507,12 @@ module fx68k
     always_ff @(posedge clk) begin
 
         // Updated at the start of the exception ucode
-        if (Nanod.updSsw & enT3) begin
+        if (Nanod_w.updSsw & enT3) begin
             ssw <= { ~bciWrite, inExcept01, rFC};
         end
 
         // Update TVN on T1 & IR=>IRD
-        if (enT1 & Nanod.Ir2Ird) begin
+        if (enT1 & Nanod_w.Ir2Ird) begin
             tvnLatch <= tvn;
             inExcept01 <= (tvn != 4'h1);
         end
@@ -514,17 +522,17 @@ module fx68k
         end
         else if (enT3) begin
             unique case (1'b1)
-            Nanod.tvn2Ftu:              ftu <= tvnMux;
+                Nanod_w.tvn2Ftu:   ftu <= tvnMux;
 
-            // 0 on unused bits seem to come from ftuConst PLA previously clearing FBUS
-            Nanod.sr2Ftu:               ftu <= {pswT, 1'b0, pswS, 2'b00, pswI, 3'b000, ccr[4:0] };
+                // 0 on unused bits seem to come from ftuConst PLA previously clearing FBUS
+                Nanod_w.sr2Ftu:    ftu <= {pswT, 1'b0, pswS, 2'b00, pswI, 3'b000, ccr[4:0] };
 
-            Nanod.ird2Ftu:              ftu <= Ird;
-            Nanod.ssw2Ftu:              ftu[4:0] <= ssw;                        // Undoc. Other bits must be preserved from IRD saved above!
-            Nanod.pswIToFtu:            ftu <= { 12'hFFF, pswI, 1'b0};          // Interrupt level shifted
-            Nanod.const2Ftu:            ftu <= Irdecod.ftuConst;
-            Nanod.abl2Pren:             ftu <= Abl;                             // From ALU or datareg. Used for SR modify
-            default:                    ftu <= ftu;
+                Nanod_w.ird2Ftu:   ftu <= Ird;
+                Nanod_w.ssw2Ftu:   ftu[4:0] <= ssw;                        // Undoc. Other bits must be preserved from IRD saved above!
+                Nanod_w.pswIToFtu: ftu <= { 12'hFFF, pswI, 1'b0};          // Interrupt level shifted
+                Nanod_w.const2Ftu: ftu <= Irdecod.ftuConst;
+                Nanod_w.abl2Pren:  ftu <= Abl;                             // From ALU or datareg. Used for SR modify
+                default:           ftu <= ftu;
             endcase
         end
     end
@@ -558,7 +566,8 @@ module nDecoder3
     input  [UROM_WIDTH-1:0] microLatch,
     input  [NANO_WIDTH-1:0] nanoLatch,
     input                   s_irdecod Irdecod,
-    output                  s_nanod Nanod
+    output                  s_nanod_r Nanod_r,
+    output                  s_nanod_w Nanod_w
 );
 
 localparam
@@ -642,162 +651,162 @@ localparam [3:0]
 
         if (enT4) begin
 
-            ftuCtrl         <= nanoLatch[NANO_FTUCONTROL +: 4];
+            ftuCtrl           <= nanoLatch[NANO_FTUCONTROL +: 4];
 
-            Nanod.auClkEn   <= ~nanoLatch[NANO_AUCLKEN];
-            Nanod.auCntrl   <= nanoLatch[NANO_AUCTRL +: 3];
-            Nanod.noSpAlign <= &nanoLatch[NANO_NO_SP_ALGN +: 2];
-            Nanod.extDbh    <= nanoLatch[NANO_EXT_DBH];
-            Nanod.extAbh    <= nanoLatch[NANO_EXT_ABH];
-            Nanod.todbin    <= nanoLatch[NANO_TODBIN];
-            Nanod.toIrc     <= nanoLatch[NANO_TOIRC];
+            Nanod_r.auClkEn   <= ~nanoLatch[NANO_AUCLKEN];
+            Nanod_r.auCntrl   <=  nanoLatch[NANO_AUCTRL +: 3];
+            Nanod_r.noSpAlign <= &nanoLatch[NANO_NO_SP_ALGN +: 2];
+            Nanod_r.extDbh    <=  nanoLatch[NANO_EXT_DBH];
+            Nanod_r.extAbh    <=  nanoLatch[NANO_EXT_ABH];
+            Nanod_r.todbin    <=  nanoLatch[NANO_TODBIN];
+            Nanod_r.toIrc     <=  nanoLatch[NANO_TOIRC];
 
             // ablAbd is disabled on byte transfers (adbhCharge plus irdIsByte). Not sure the combination makes much sense.
             // It happens in a few cases but I don't see anything enabled on abL (or abH) section anyway.
 
-            Nanod.ablAbd  <= nanoLatch[NANO_ABLABD];
-            Nanod.ablAbh  <= nanoLatch[NANO_ABLABH];
-            Nanod.dblDbd  <= nanoLatch[NANO_DBLDBD];
-            Nanod.dblDbh  <= nanoLatch[NANO_DBLDBH];
+            Nanod_r.ablAbd    <= nanoLatch[NANO_ABLABD];
+            Nanod_r.ablAbh    <= nanoLatch[NANO_ABLABH];
+            Nanod_r.dblDbd    <= nanoLatch[NANO_DBLDBD];
+            Nanod_r.dblDbh    <= nanoLatch[NANO_DBLDBH];
 
-            Nanod.dbl2Atl <= (atlCtrl[2:0] == 3'b010) ? 1'b1 : 1'b0;
-            Nanod.atl2Dbl <= (atlCtrl[2:0] == 3'b011) ? 1'b1 : 1'b0;
-            Nanod.abl2Atl <= (atlCtrl[2:0] == 3'b100) ? 1'b1 : 1'b0;
-            Nanod.atl2Abl <= (atlCtrl[2:0] == 3'b101) ? 1'b1 : 1'b0;
+            Nanod_r.dbl2Atl   <= (atlCtrl[2:0] == 3'b010) ? 1'b1 : 1'b0;
+            Nanod_r.atl2Dbl   <= (atlCtrl[2:0] == 3'b011) ? 1'b1 : 1'b0;
+            Nanod_r.abl2Atl   <= (atlCtrl[2:0] == 3'b100) ? 1'b1 : 1'b0;
+            Nanod_r.atl2Abl   <= (atlCtrl[2:0] == 3'b101) ? 1'b1 : 1'b0;
 
-            Nanod.aob2Ab  <= (athCtrl[2:0] == 3'b101) ? 1'b1 : 1'b0; // Used on BSER1 only
+            Nanod_r.aob2Ab    <= (athCtrl[2:0] == 3'b101) ? 1'b1 : 1'b0; // Used on BSER1 only
 
-            Nanod.abh2Ath <= (athCtrl[1:0] == 2'b01 ) ? 1'b1 : 1'b0;
-            Nanod.dbh2Ath <= (athCtrl[2:0] == 3'b100) ? 1'b1 : 1'b0;
-            Nanod.ath2Dbh <= (athCtrl[2:0] == 3'b110) ? 1'b1 : 1'b0;
-            Nanod.ath2Abh <= (athCtrl[2:0] == 3'b011) ? 1'b1 : 1'b0;
+            Nanod_r.abh2Ath   <= (athCtrl[1:0] == 2'b01 ) ? 1'b1 : 1'b0;
+            Nanod_r.dbh2Ath   <= (athCtrl[2:0] == 3'b100) ? 1'b1 : 1'b0;
+            Nanod_r.ath2Dbh   <= (athCtrl[2:0] == 3'b110) ? 1'b1 : 1'b0;
+            Nanod_r.ath2Abh   <= (athCtrl[2:0] == 3'b011) ? 1'b1 : 1'b0;
 
-            Nanod.alu2Dbd <= nanoLatch[NANO_ALU2DBD];
-            Nanod.alu2Abd <= nanoLatch[NANO_ALU2ABD];
+            Nanod_r.alu2Dbd   <= nanoLatch[NANO_ALU2DBD];
+            Nanod_r.alu2Abd   <= nanoLatch[NANO_ALU2ABD];
 
-            Nanod.abd2Dcr <= (nanoLatch[ NANO_DCR+1:NANO_DCR] == 2'b11);
-            Nanod.dcr2Dbd <= (nanoLatch[ NANO_DCR+2:NANO_DCR+1] == 2'b11);
-            Nanod.dbd2Alue <= (nanoLatch[ NANO_ALUE+2:NANO_ALUE+1] == 2'b10);
-            Nanod.alue2Dbd <= (nanoLatch[ NANO_ALUE+1:NANO_ALUE] == 2'b01);
+            Nanod_r.abd2Dcr   <= (nanoLatch[NANO_DCR+0 +: 2]  == 2'b11) ? 1'b1 : 1'b0;
+            Nanod_r.dcr2Dbd   <= (nanoLatch[NANO_DCR+1 +: 2]  == 2'b11) ? 1'b1 : 1'b0;
+            Nanod_r.dbd2Alue  <= (nanoLatch[NANO_ALUE+1 +: 2] == 2'b10) ? 1'b1 : 1'b0;
+            Nanod_r.alue2Dbd  <= (nanoLatch[NANO_ALUE+0 +: 2] == 2'b01) ? 1'b1 : 1'b0;
 
-            Nanod.dbd2Alub <= nanoLatch[ NANO_DBD2ALUB];
-            Nanod.abd2Alub <= nanoLatch[ NANO_ABD2ALUB];
+            Nanod_r.dbd2Alub  <= nanoLatch[NANO_DBD2ALUB];
+            Nanod_r.abd2Alub  <= nanoLatch[NANO_ABD2ALUB];
 
             // Originally not latched. We better should because we transfer one cycle later, T3 instead of T1.
-            Nanod.dobCtrl <= dobCtrl;
-            // Nanod.adb2Dob <= (dobCtrl == 2'b10);
-            // Nanod.dbd2Dob <= (dobCtrl == 2'b01);
-            // Nanod.alu2Dob <= (dobCtrl == 2'b11);
+            Nanod_r.dobCtrl   <= dobCtrl;
+            // Nanod_r.adb2Dob <= (dobCtrl == 2'b10);
+            // Nanod_r.dbd2Dob <= (dobCtrl == 2'b01);
+            // Nanod_r.alu2Dob <= (dobCtrl == 2'b11);
 
             // Might be better not to register these signals to allow latching RX/RY mux earlier!
             // But then must latch Irdecod.isPcRel on T3!
 
-            Nanod.rxl2db <= Nanod.reg2dbl & !dblSpecial & nanoLatch[ NANO_RXL_DBL];
-            Nanod.rxl2ab <= Nanod.reg2abl & !ablSpecial & !nanoLatch[ NANO_RXL_DBL];
+            Nanod_r.rxl2db  <= Nanod_w.reg2dbl & ~dblSpecial &  nanoLatch[NANO_RXL_DBL];
+            Nanod_r.rxl2ab  <= Nanod_w.reg2abl & ~ablSpecial & ~nanoLatch[NANO_RXL_DBL];
 
-            Nanod.dbl2rxl <= Nanod.dbl2reg & !dblSpecial & nanoLatch[ NANO_RXL_DBL];
-            Nanod.abl2rxl <= Nanod.abl2reg & !ablSpecial & !nanoLatch[ NANO_RXL_DBL];
+            Nanod_r.dbl2rxl <= Nanod_w.dbl2reg & ~dblSpecial &  nanoLatch[NANO_RXL_DBL];
+            Nanod_r.abl2rxl <= Nanod_w.abl2reg & ~ablSpecial & ~nanoLatch[NANO_RXL_DBL];
 
-            Nanod.rxh2dbh <= Nanod.reg2dbh & !dbhSpecial & nanoLatch[ NANO_RXH_DBH];
-            Nanod.rxh2abh <= Nanod.reg2abh & !abhSpecial & !nanoLatch[ NANO_RXH_DBH];
+            Nanod_r.rxh2dbh <= Nanod_w.reg2dbh & ~dbhSpecial &  nanoLatch[NANO_RXH_DBH];
+            Nanod_r.rxh2abh <= Nanod_w.reg2abh & ~abhSpecial & ~nanoLatch[NANO_RXH_DBH];
 
-            Nanod.dbh2rxh <= Nanod.dbh2reg & !dbhSpecial & nanoLatch[ NANO_RXH_DBH];
-            Nanod.abh2rxh <= Nanod.abh2reg & !abhSpecial & !nanoLatch[ NANO_RXH_DBH];
+            Nanod_r.dbh2rxh <= Nanod_w.dbh2reg & ~dbhSpecial &  nanoLatch[NANO_RXH_DBH];
+            Nanod_r.abh2rxh <= Nanod_w.abh2reg & ~abhSpecial & ~nanoLatch[NANO_RXH_DBH];
 
-            Nanod.dbh2ryh <= Nanod.dbh2reg & !dbhSpecial & !nanoLatch[ NANO_RXH_DBH];
-            Nanod.abh2ryh <= Nanod.abh2reg & !abhSpecial & nanoLatch[ NANO_RXH_DBH];
+            Nanod_r.dbh2ryh <= Nanod_w.dbh2reg & ~dbhSpecial & ~nanoLatch[NANO_RXH_DBH];
+            Nanod_r.abh2ryh <= Nanod_w.abh2reg & ~abhSpecial &  nanoLatch[NANO_RXH_DBH];
 
-            Nanod.dbl2ryl <= Nanod.dbl2reg & !dblSpecial & !nanoLatch[ NANO_RXL_DBL];
-            Nanod.abl2ryl <= Nanod.abl2reg & !ablSpecial & nanoLatch[ NANO_RXL_DBL];
+            Nanod_r.dbl2ryl <= Nanod_w.dbl2reg & ~dblSpecial & ~nanoLatch[NANO_RXL_DBL];
+            Nanod_r.abl2ryl <= Nanod_w.abl2reg & ~ablSpecial &  nanoLatch[NANO_RXL_DBL];
 
-            Nanod.ryl2db <= Nanod.reg2dbl & !dblSpecial & !nanoLatch[ NANO_RXL_DBL];
-            Nanod.ryl2ab <= Nanod.reg2abl & !ablSpecial & nanoLatch[ NANO_RXL_DBL];
+            Nanod_r.ryl2db  <= Nanod_w.reg2dbl & ~dblSpecial & ~nanoLatch[NANO_RXL_DBL];
+            Nanod_r.ryl2ab  <= Nanod_w.reg2abl & ~ablSpecial &  nanoLatch[NANO_RXL_DBL];
 
-            Nanod.ryh2dbh <= Nanod.reg2dbh & !dbhSpecial & !nanoLatch[ NANO_RXH_DBH];
-            Nanod.ryh2abh <= Nanod.reg2abh & !abhSpecial & nanoLatch[ NANO_RXH_DBH];
+            Nanod_r.ryh2dbh <= Nanod_w.reg2dbh & ~dbhSpecial & ~nanoLatch[NANO_RXH_DBH];
+            Nanod_r.ryh2abh <= Nanod_w.reg2abh & ~abhSpecial &  nanoLatch[NANO_RXH_DBH];
 
             // Originally isTas only delayed on T2 (and seems only a late mask rev fix)
             // Better latch the combination on T4
-            Nanod.isRmc <= Irdecod.isTas & nanoLatch[ NANO_BUSBYTE];
+            Nanod_r.isRmc   <= Irdecod.isTas & nanoLatch[NANO_BUSBYTE];
         end
     end
 
     // Update SSW at the start of Bus/Addr error ucode
-    assign Nanod.updSsw    = Nanod.aob2Ab;
-
-    assign Nanod.updTpend  = (ftuCtrl == NANO_FTU_UPDTPEND);
-    assign Nanod.clrTpend  = (ftuCtrl == NANO_FTU_CLRTPEND);
-    assign Nanod.tvn2Ftu   = (ftuCtrl == NANO_FTU_TVN);
-    assign Nanod.const2Ftu = (ftuCtrl == NANO_FTU_CONST);
-    assign Nanod.ftu2Dbl   = (ftuCtrl == NANO_FTU_DBL) | ( ftuCtrl == NANO_FTU_INL);
-    assign Nanod.ftu2Abl   = (ftuCtrl == NANO_FTU_2ABL);
-    assign Nanod.inl2psw   = (ftuCtrl == NANO_FTU_INL);
-    assign Nanod.pswIToFtu = (ftuCtrl == NANO_FTU_PSWI);
-    assign Nanod.ftu2Sr    = (ftuCtrl == NANO_FTU_2SR);
-    assign Nanod.sr2Ftu    = (ftuCtrl == NANO_FTU_RDSR);
-    assign Nanod.ird2Ftu   = (ftuCtrl == NANO_FTU_IRD);       // Used on bus/addr error
-    assign Nanod.ssw2Ftu   = (ftuCtrl == NANO_FTU_SSW);
-    assign Nanod.initST    = (ftuCtrl == NANO_FTU_INL) | (ftuCtrl == NANO_FTU_CLRTPEND) | (ftuCtrl == NANO_FTU_INIT_ST);
-    assign Nanod.abl2Pren  = (ftuCtrl == NANO_FTU_ABL2PREN);
-    assign Nanod.updPren   = (ftuCtrl == NANO_FTU_RSTPREN);
-
-    assign Nanod.Ir2Ird    = nanoLatch[ NANO_IR2IRD];
+    assign Nanod_w.updSsw    = Nanod_r.aob2Ab;
+
+    assign Nanod_w.updTpend  = (ftuCtrl == NANO_FTU_UPDTPEND);
+    assign Nanod_w.clrTpend  = (ftuCtrl == NANO_FTU_CLRTPEND);
+    assign Nanod_w.tvn2Ftu   = (ftuCtrl == NANO_FTU_TVN);
+    assign Nanod_w.const2Ftu = (ftuCtrl == NANO_FTU_CONST);
+    assign Nanod_w.ftu2Dbl   = (ftuCtrl == NANO_FTU_DBL) | ( ftuCtrl == NANO_FTU_INL);
+    assign Nanod_w.ftu2Abl   = (ftuCtrl == NANO_FTU_2ABL);
+    assign Nanod_w.inl2psw   = (ftuCtrl == NANO_FTU_INL);
+    assign Nanod_w.pswIToFtu = (ftuCtrl == NANO_FTU_PSWI);
+    assign Nanod_w.ftu2Sr    = (ftuCtrl == NANO_FTU_2SR);
+    assign Nanod_w.sr2Ftu    = (ftuCtrl == NANO_FTU_RDSR);
+    assign Nanod_w.ird2Ftu   = (ftuCtrl == NANO_FTU_IRD);       // Used on bus/addr error
+    assign Nanod_w.ssw2Ftu   = (ftuCtrl == NANO_FTU_SSW);
+    assign Nanod_w.initST    = (ftuCtrl == NANO_FTU_INL) | (ftuCtrl == NANO_FTU_CLRTPEND) | (ftuCtrl == NANO_FTU_INIT_ST);
+    assign Nanod_w.abl2Pren  = (ftuCtrl == NANO_FTU_ABL2PREN);
+    assign Nanod_w.updPren   = (ftuCtrl == NANO_FTU_RSTPREN);
+
+    assign Nanod_w.Ir2Ird    = nanoLatch[NANO_IR2IRD];
 
     // ALU control better latched later after combining with IRD decoding
 
-    wire [1:0] aluFinInit  = nanoLatch[NANO_ALU_FI +: 2];
+    wire [1:0] aluFinInit = nanoLatch[NANO_ALU_FI +: 2];
 
-    assign Nanod.aluDctrl  = nanoLatch[NANO_ALU_DCTRL +: 2];
-    assign Nanod.aluActrl  = nanoLatch[NANO_ALU_ACTRL];
-    assign Nanod.aluColumn = { nanoLatch[ NANO_ALU_COL], nanoLatch[ NANO_ALU_COL+1], nanoLatch[ NANO_ALU_COL+2]};
-    assign Nanod.aluFinish = (aluFinInit == 2'b10) ? 1'b1 : 1'b0;
-    assign Nanod.aluInit   = (aluFinInit == 2'b01) ? 1'b1 : 1'b0;
+    assign Nanod_w.aluDctrl      = nanoLatch[NANO_ALU_DCTRL +: 2];
+    assign Nanod_w.aluActrl      = nanoLatch[NANO_ALU_ACTRL];
+    assign Nanod_w.aluColumn     = { nanoLatch[ NANO_ALU_COL], nanoLatch[ NANO_ALU_COL+1], nanoLatch[ NANO_ALU_COL+2]};
+    assign Nanod_w.aluFinish     = (aluFinInit == 2'b10) ? 1'b1 : 1'b0;
+    assign Nanod_w.aluInit       = (aluFinInit == 2'b01) ? 1'b1 : 1'b0;
 
     // FTU 2 CCR encoded as both ALU Init and ALU Finish set.
     // In theory this encoding allows writes to CCR without writing to SR
     // But FTU 2 CCR and to SR are both set together at nanorom.
-    assign Nanod.ftu2Ccr   = (aluFinInit == 2'b11) ? 1'b1 : 1'b0;
+    assign Nanod_w.ftu2Ccr       = (aluFinInit == 2'b11) ? 1'b1 : 1'b0;
 
-    assign Nanod.abdIsByte = nanoLatch[ NANO_ABDHRECHARGE];
+    assign Nanod_w.abdIsByte     = nanoLatch[NANO_ABDHRECHARGE];
 
     // Not being latched on T4 creates non unique case warning!
-    assign Nanod.au2Db = (nanoLatch[ NANO_AUOUT +: 2] == 2'b01) ? 1'b1 : 1'b0;
-    assign Nanod.au2Ab = (nanoLatch[ NANO_AUOUT +: 2] == 2'b10) ? 1'b1 : 1'b0;
-    assign Nanod.au2Pc = (nanoLatch[ NANO_AUOUT +: 2] == 2'b11) ? 1'b1 : 1'b0;
-
-    assign Nanod.db2Aob = (aobCtrl == 2'b10) ? 1'b1 : 1'b0;
-    assign Nanod.ab2Aob = (aobCtrl == 2'b01) ? 1'b1 : 1'b0;
-    assign Nanod.au2Aob = (aobCtrl == 2'b11) ? 1'b1 : 1'b0;
-
-    assign Nanod.dbin2Abd = nanoLatch[ NANO_DBIN2ABD];
-    assign Nanod.dbin2Dbd = nanoLatch[ NANO_DBIN2DBD];
-
-    assign Nanod.permStart     = (aobCtrl != 2'b00) ? 1'b1 : 1'b0;
-    assign Nanod.isWrite       = nanoLatch[NANO_DOBCTRL_1]
-                               | nanoLatch[NANO_DOBCTRL_0];
-    assign Nanod.waitBusFinish = nanoLatch[NANO_DOBCTRL_1]
-                               | nanoLatch[NANO_DOBCTRL_0]
-                               | nanoLatch[NANO_TOIRC]
-                               | nanoLatch[NANO_TODBIN];
-    assign Nanod.busByte       = nanoLatch[NANO_BUSBYTE];
+    assign Nanod_w.au2Db         = (nanoLatch[NANO_AUOUT +: 2] == 2'b01) ? 1'b1 : 1'b0;
+    assign Nanod_w.au2Ab         = (nanoLatch[NANO_AUOUT +: 2] == 2'b10) ? 1'b1 : 1'b0;
+    assign Nanod_w.au2Pc         = (nanoLatch[NANO_AUOUT +: 2] == 2'b11) ? 1'b1 : 1'b0;
+
+    assign Nanod_w.db2Aob        = (aobCtrl == 2'b10) ? 1'b1 : 1'b0;
+    assign Nanod_w.ab2Aob        = (aobCtrl == 2'b01) ? 1'b1 : 1'b0;
+    assign Nanod_w.au2Aob        = (aobCtrl == 2'b11) ? 1'b1 : 1'b0;
+
+    assign Nanod_w.dbin2Abd      = nanoLatch[NANO_DBIN2ABD];
+    assign Nanod_w.dbin2Dbd      = nanoLatch[NANO_DBIN2DBD];
+
+    assign Nanod_w.permStart     = (aobCtrl != 2'b00) ? 1'b1 : 1'b0;
+    assign Nanod_w.isWrite       = nanoLatch[NANO_DOBCTRL_1]
+                                 | nanoLatch[NANO_DOBCTRL_0];
+    assign Nanod_w.waitBusFinish = nanoLatch[NANO_DOBCTRL_1]
+                                 | nanoLatch[NANO_DOBCTRL_0]
+                                 | nanoLatch[NANO_TOIRC]
+                                 | nanoLatch[NANO_TODBIN];
+    assign Nanod_w.busByte       = nanoLatch[NANO_BUSBYTE];
 
-    assign Nanod.noLowByte     = nanoLatch[NANO_LOWBYTE];
-    assign Nanod.noHighByte    = nanoLatch[NANO_HIGHBYTE];
+    assign Nanod_w.noLowByte     = nanoLatch[NANO_LOWBYTE];
+    assign Nanod_w.noHighByte    = nanoLatch[NANO_HIGHBYTE];
 
     // Not registered. Register at T4 after combining
     // Might be better to remove all those and combine here instead of at execution unit !!
-    assign Nanod.abl2reg = nanoLatch[ NANO_ABL2REG];
-    assign Nanod.abh2reg = nanoLatch[ NANO_ABH2REG];
-    assign Nanod.dbl2reg = nanoLatch[ NANO_DBL2REG];
-    assign Nanod.dbh2reg = nanoLatch[ NANO_DBH2REG];
-    assign Nanod.reg2dbl = nanoLatch[ NANO_REG2DBL];
-    assign Nanod.reg2dbh = nanoLatch[ NANO_REG2DBH];
-    assign Nanod.reg2abl = nanoLatch[ NANO_REG2ABL];
-    assign Nanod.reg2abh = nanoLatch[ NANO_REG2ABH];
+    assign Nanod_w.abl2reg       = nanoLatch[NANO_ABL2REG];
+    assign Nanod_w.abh2reg       = nanoLatch[NANO_ABH2REG];
+    assign Nanod_w.dbl2reg       = nanoLatch[NANO_DBL2REG];
+    assign Nanod_w.dbh2reg       = nanoLatch[NANO_DBH2REG];
+    assign Nanod_w.reg2dbl       = nanoLatch[NANO_REG2DBL];
+    assign Nanod_w.reg2dbh       = nanoLatch[NANO_REG2DBH];
+    assign Nanod_w.reg2abl       = nanoLatch[NANO_REG2ABL];
+    assign Nanod_w.reg2abh       = nanoLatch[NANO_REG2ABH];
 
-    assign Nanod.ssp = nanoLatch[ NANO_SSP];
+    assign Nanod_w.ssp           = nanoLatch[NANO_SSP];
 
-    assign Nanod.rz = nanoLatch[ NANO_RZ];
+    assign Nanod_w.rz            = nanoLatch[NANO_RZ];
 
     // Actually DTL can't happen on PC relative mode. See IR decoder.
 
@@ -806,10 +815,10 @@ localparam [3:0]
     wire dtlabd = 1'b0;
     wire dthabh = 1'b0;
 
-    wire dblSpecial = Nanod.pcldbl | dtldbd;
-    wire dbhSpecial = Nanod.pchdbh | dthdbh;
-    wire ablSpecial = Nanod.pclabl | dtlabd;
-    wire abhSpecial = Nanod.pchabh | dthabh;
+    wire dblSpecial = Nanod_w.pcldbl | dtldbd;
+    wire dbhSpecial = Nanod_w.pchdbh | dthdbh;
+    wire ablSpecial = Nanod_w.pclabl | dtlabd;
+    wire abhSpecial = Nanod_w.pchabh | dthabh;
 
     //
     // Combine with IRD decoding
@@ -818,18 +827,18 @@ localparam [3:0]
 
     // PC used instead of RY on PC relative instuctions
 
-    assign Nanod.rxlDbl = nanoLatch[ NANO_RXL_DBL];
+    assign Nanod_w.rxlDbl = nanoLatch[NANO_RXL_DBL];
     wire isPcRel  = Irdecod.isPcRel & ~nanoLatch[NANO_RZ];
     wire pcRelDbl = isPcRel & ~nanoLatch[NANO_RXL_DBL];
     wire pcRelDbh = isPcRel & ~nanoLatch[NANO_RXH_DBH];
     wire pcRelAbl = isPcRel &  nanoLatch[NANO_RXL_DBL];
     wire pcRelAbh = isPcRel &  nanoLatch[NANO_RXH_DBH];
 
-    assign Nanod.pcldbl = nanoLatch[ NANO_PCLDBL] | pcRelDbl;
-    assign Nanod.pchdbh = (nanoLatch[NANO_PCH +: 2] == 2'b01) ? 1'b1 : pcRelDbh;
+    assign Nanod_w.pcldbl = nanoLatch[NANO_PCLDBL] | pcRelDbl;
+    assign Nanod_w.pchdbh = (nanoLatch[NANO_PCH +: 2] == 2'b01) ? 1'b1 : pcRelDbh;
 
-    assign Nanod.pclabl = nanoLatch[ NANO_PCLABL] | pcRelAbl;
-    assign Nanod.pchabh = (nanoLatch[NANO_PCH +: 2] == 2'b10) ? 1'b1 : pcRelAbh;
+    assign Nanod_w.pclabl = nanoLatch[NANO_PCLABL] | pcRelAbl;
+    assign Nanod_w.pchabh = (nanoLatch[NANO_PCH +: 2] == 2'b10) ? 1'b1 : pcRelAbh;
 
 endmodule
 
@@ -1092,7 +1101,8 @@ module excUnit
     input clk,
     input s_clks Clks,
     input enT1, enT2, enT3, enT4,
-    input s_nanod Nanod,
+    input s_nanod_r Nanod_r,
+    input s_nanod_w Nanod_w,
     input s_irdecod Irdecod,
     input [15:0] Ird,           // ALU row (and others) decoder needs it
     input pswS,
@@ -1191,7 +1201,7 @@ localparam
     always_comb begin
 
         // Unique IF !!
-        if (Nanod.ssp) begin
+        if (Nanod_w.ssp) begin
             rxMux  = REG_SSP[4:0];
             rxIsSp = 1'b1;
             rxReg  = 4'hX;
@@ -1225,13 +1235,13 @@ localparam
         end
 
         // RZ has higher priority!
-        if (Irdecod.ryIsDt & !Nanod.rz) begin
+        if (Irdecod.ryIsDt & !Nanod_w.rz) begin
             ryMux  = REG_DT[4:0];
             ryIsSp = 1'b0;
             ryReg  = 4'hX;
         end
         else begin
-            ryReg = Nanod.rz ? Irc[15:12] : {Irdecod.ryIsAreg, Irdecod.ry};
+            ryReg = Nanod_w.rz ? Irc[15:12] : {Irdecod.ryIsAreg, Irdecod.ry};
             ryIsSp = (& ryReg);
             if (ryIsSp & pswS)          // No implicit SP on RY
                 ryMux = REG_SSP[4:0];
@@ -1244,7 +1254,7 @@ localparam
     always_ff @(posedge clk) begin
     
         if (enT4) begin
-            byteNotSpAlign <= Irdecod.isByte & ~(Nanod.rxlDbl ? rxIsSp : ryIsSp);
+            byteNotSpAlign <= Irdecod.isByte & ~(Nanod_w.rxlDbl ? rxIsSp : ryIsSp);
 
             actualRx <= rxMux;
             actualRy <= ryMux;
@@ -1252,21 +1262,21 @@ localparam
             rxIsAreg <= rxIsSp | rxMux[3];
             ryIsAreg <= ryIsSp | ryMux[3];
 
-            abdIsByte <= Nanod.abdIsByte & Irdecod.isByte;
+            abdIsByte <= Nanod_w.abdIsByte & Irdecod.isByte;
         end
     end
 
     // Set RX/RY low word to which bus segment is connected.
 
-    wire ryl2Abl = Nanod.ryl2ab & ( ryIsAreg | Nanod.ablAbd);
-    wire ryl2Abd = Nanod.ryl2ab & (~ryIsAreg | Nanod.ablAbd);
-    wire ryl2Dbl = Nanod.ryl2db & ( ryIsAreg | Nanod.dblDbd);
-    wire ryl2Dbd = Nanod.ryl2db & (~ryIsAreg | Nanod.dblDbd);
+    wire ryl2Abl = Nanod_r.ryl2ab & ( ryIsAreg | Nanod_r.ablAbd);
+    wire ryl2Abd = Nanod_r.ryl2ab & (~ryIsAreg | Nanod_r.ablAbd);
+    wire ryl2Dbl = Nanod_r.ryl2db & ( ryIsAreg | Nanod_r.dblDbd);
+    wire ryl2Dbd = Nanod_r.ryl2db & (~ryIsAreg | Nanod_r.dblDbd);
 
-    wire rxl2Abl = Nanod.rxl2ab & ( rxIsAreg | Nanod.ablAbd);
-    wire rxl2Abd = Nanod.rxl2ab & (~rxIsAreg | Nanod.ablAbd);
-    wire rxl2Dbl = Nanod.rxl2db & ( rxIsAreg | Nanod.dblDbd);
-    wire rxl2Dbd = Nanod.rxl2db & (~rxIsAreg | Nanod.dblDbd);
+    wire rxl2Abl = Nanod_r.rxl2ab & ( rxIsAreg | Nanod_r.ablAbd);
+    wire rxl2Abd = Nanod_r.rxl2ab & (~rxIsAreg | Nanod_r.ablAbd);
+    wire rxl2Dbl = Nanod_r.rxl2db & ( rxIsAreg | Nanod_r.dblDbd);
+    wire rxl2Dbd = Nanod_r.rxl2db & (~rxIsAreg | Nanod_r.dblDbd);
 
     // Buses. Main mux
 
@@ -1278,60 +1288,60 @@ localparam
         {dbhIdle, dblIdle, dbdIdle} = 3'b000;
 
         unique case (1'b1)
-        ryl2Dbd:                dbdMux = regs68L[ actualRy];
-        rxl2Dbd:                dbdMux = regs68L[ actualRx];
-        Nanod.alue2Dbd:         dbdMux = alue;
-        Nanod.dbin2Dbd:         dbdMux = dbin;
-        Nanod.alu2Dbd:          dbdMux = aluOut;
-        Nanod.dcr2Dbd:          dbdMux = dcrOutput;
+        ryl2Dbd:                dbdMux = regs68L[actualRy];
+        rxl2Dbd:                dbdMux = regs68L[actualRx];
+        Nanod_r.alue2Dbd:       dbdMux = alue;
+        Nanod_w.dbin2Dbd:       dbdMux = dbin;
+        Nanod_r.alu2Dbd:        dbdMux = aluOut;
+        Nanod_r.dcr2Dbd:        dbdMux = dcrOutput;
         default: begin          dbdMux = 'X;    dbdIdle = 1'b1;             end
         endcase
 
         unique case (1'b1)
-        rxl2Dbl:                dblMux = regs68L[ actualRx];
-        ryl2Dbl:                dblMux = regs68L[ actualRy];
-        Nanod.ftu2Dbl:          dblMux = ftu;
-        Nanod.au2Db:            dblMux = auReg[15:0];
-        Nanod.atl2Dbl:          dblMux = Atl;
+        rxl2Dbl:                dblMux = regs68L[actualRx];
+        ryl2Dbl:                dblMux = regs68L[actualRy];
+        Nanod_w.ftu2Dbl:        dblMux = ftu;
+        Nanod_w.au2Db:          dblMux = auReg[15:0];
+        Nanod_r.atl2Dbl:        dblMux = Atl;
         Pcl2Dbl:                dblMux = PcL;
         default: begin          dblMux = 'X;    dblIdle = 1'b1;             end
         endcase
 
         unique case (1'b1)
-        Nanod.rxh2dbh:          dbhMux = regs68H[ actualRx];
-        Nanod.ryh2dbh:          dbhMux = regs68H[ actualRy];
-        Nanod.au2Db:            dbhMux = auReg[31:16];
-        Nanod.ath2Dbh:          dbhMux = Ath;
+        Nanod_r.rxh2dbh:        dbhMux = regs68H[actualRx];
+        Nanod_r.ryh2dbh:        dbhMux = regs68H[actualRy];
+        Nanod_w.au2Db:          dbhMux = auReg[31:16];
+        Nanod_r.ath2Dbh:        dbhMux = Ath;
         Pch2Dbh:                dbhMux = PcH;
         default: begin          dbhMux = 'X;    dbhIdle = 1'b1;             end
         endcase
 
         unique case (1'b1)
-        ryl2Abd:                abdMux = regs68L[ actualRy];
-        rxl2Abd:                abdMux = regs68L[ actualRx];
-        Nanod.dbin2Abd:         abdMux = dbin;
-        Nanod.alu2Abd:          abdMux = aluOut;
+        ryl2Abd:                abdMux = regs68L[actualRy];
+        rxl2Abd:                abdMux = regs68L[actualRx];
+        Nanod_w.dbin2Abd:       abdMux = dbin;
+        Nanod_r.alu2Abd:        abdMux = aluOut;
         default: begin          abdMux = 'X;    abdIdle = 1'b1;             end
         endcase
 
         unique case (1'b1)
         Pcl2Abl:                ablMux = PcL;
-        rxl2Abl:                ablMux = regs68L[ actualRx];
-        ryl2Abl:                ablMux = regs68L[ actualRy];
-        Nanod.ftu2Abl:          ablMux = ftu;
-        Nanod.au2Ab:            ablMux = auReg[15:0];
-        Nanod.aob2Ab:           ablMux = aob[15:0];
-        Nanod.atl2Abl:          ablMux = Atl;
+        rxl2Abl:                ablMux = regs68L[actualRx];
+        ryl2Abl:                ablMux = regs68L[actualRy];
+        Nanod_w.ftu2Abl:        ablMux = ftu;
+        Nanod_w.au2Ab:          ablMux = auReg[15:0];
+        Nanod_r.aob2Ab:         ablMux = aob[15:0];
+        Nanod_r.atl2Abl:        ablMux = Atl;
         default: begin          ablMux = 'X;    ablIdle = 1'b1;             end
         endcase
 
         unique case (1'b1)
         Pch2Abh:                abhMux = PcH;
-        Nanod.rxh2abh:          abhMux = regs68H[ actualRx];
-        Nanod.ryh2abh:          abhMux = regs68H[ actualRy];
-        Nanod.au2Ab:            abhMux = auReg[31:16];
-        Nanod.aob2Ab:           abhMux = aob[31:16];
-        Nanod.ath2Abh:          abhMux = Ath;
+        Nanod_r.rxh2abh:        abhMux = regs68H[actualRx];
+        Nanod_r.ryh2abh:        abhMux = regs68H[actualRy];
+        Nanod_w.au2Ab:          abhMux = auReg[31:16];
+        Nanod_r.aob2Ab:         abhMux = aob[31:16];
+        Nanod_r.ath2Abh:        abhMux = Ath;
         default: begin          abhMux = 'X;    abhIdle = 1'b1;             end
         endcase
 
@@ -1357,8 +1367,8 @@ localparam
         // In some cases this is not true and the segment is really idle without any destination. But then it doesn't matter.
 
         if (enT2) begin
-            if (Nanod.extAbh)
-                Abh <= { 16{ ablIdle ? preAbd[ 15] : preAbl[ 15] }};
+            if (Nanod_r.extAbh)
+                Abh <= { 16{ ablIdle ? preAbd[15] : preAbl[15] }};
             else if (abhIdle)
                 Abh <= ablIdle ? preAbd : preAbl;
             else
@@ -1367,12 +1377,12 @@ localparam
             if (~ablIdle)
                 Abl <= preAbl;
             else
-                Abl <= Nanod.ablAbh ? preAbh : preAbd;
+                Abl <= Nanod_r.ablAbh ? preAbh : preAbd;
 
             Abd <= ~abdIdle ? preAbd : ablIdle ? preAbh : preAbl;
 
-            if (Nanod.extDbh)
-                Dbh <= { 16{ dblIdle ? preDbd[ 15] : preDbl[ 15] }};
+            if (Nanod_r.extDbh)
+                Dbh <= { 16{ dblIdle ? preDbd[15] : preDbl[15] }};
             else if (dbhIdle)
                 Dbh <= dblIdle ? preDbd : preDbl;
             else
@@ -1381,7 +1391,7 @@ localparam
             if (~dblIdle)
                 Dbl <= preDbl;
             else
-                Dbl <= Nanod.dblDbh ? preDbh : preDbd;
+                Dbl <= Nanod_r.dblDbh ? preDbh : preDbd;
 
             Dbd <= ~dbdIdle ? preDbd: dblIdle ? preDbh : preDbl;
 
@@ -1406,7 +1416,7 @@ localparam
 
     // We need to take directly from first level muxes that are updated and T1
 
-    wire au2Aob = Nanod.au2Aob | (Nanod.au2Db & Nanod.db2Aob);
+    wire au2Aob = Nanod_w.au2Aob | (Nanod_w.au2Db & Nanod_w.db2Aob);
 
     always_ff @(posedge clk) begin
         // UNIQUE IF !
@@ -1414,9 +1424,9 @@ localparam
         if (enT1 & au2Aob)      // From AU we do can on T1
             aob <= auReg;
         else if (enT2) begin
-            if (Nanod.db2Aob)
+            if (Nanod_w.db2Aob)
                 aob <= { preDbh, ~dblIdle ? preDbl : preDbd};
-            else if (Nanod.ab2Aob)
+            else if (Nanod_w.ab2Aob)
                 aob <= { preAbh, ~ablIdle ? preAbl : preAbd};
         end
     end
@@ -1429,18 +1439,18 @@ localparam
 
     // `ifdef ALW_COMB_BUG
     // Old Modelsim bug. Doesn't update ouput always. Need excplicit sensitivity list !?
-    // always @( Nanod.auCntrl) begin
+    // always @( Nanod_r.auCntrl) begin
 
     always_comb begin
-        unique case (Nanod.auCntrl)
+        unique case (Nanod_r.auCntrl)
             3'b000:  auInpMux = 32'h00000000;
-            3'b001:  auInpMux = byteNotSpAlign | Nanod.noSpAlign ? 32'h00000001 : 32'h00000002; // +1/+2
+            3'b001:  auInpMux = byteNotSpAlign | Nanod_r.noSpAlign ? 32'h00000001 : 32'h00000002; // +1/+2
             3'b010:  auInpMux = 32'hFFFFFFFC;
             3'b011:  auInpMux = { Abh, Abl};
             3'b100:  auInpMux = 32'h00000002;
             3'b101:  auInpMux = 32'h00000004;
             3'b110:  auInpMux = 32'hFFFFFFFE;
-            3'b111:  auInpMux = byteNotSpAlign | Nanod.noSpAlign ? 32'hFFFFFFFF : 32'hFFFFFFFE; // -1/-2
+            3'b111:  auInpMux = byteNotSpAlign | Nanod_r.noSpAlign ? 32'hFFFFFFFF : 32'hFFFFFFFE; // -1/-2
             default: auInpMux = 32'h00000000;
         endcase
     end
@@ -1459,7 +1469,7 @@ localparam
 
         if (Clks.pwrUp)
             auReg <= '0;
-        else if (enT3 & Nanod.auClkEn)
+        else if (enT3 & Nanod_r.auClkEn)
             `ifdef SIMULBUGX32
                 auReg <= auResult;
             `else
@@ -1473,31 +1483,31 @@ localparam
     always_ff @(posedge clk) begin
 
         if (enT3) begin
-            if (Nanod.dbl2rxl | Nanod.abl2rxl) begin
+            if (Nanod_r.dbl2rxl | Nanod_r.abl2rxl) begin
                 if (~rxIsAreg) begin
-                    if (Nanod.dbl2rxl)          regs68L[ actualRx] <= Dbd;
-                    else if (abdIsByte)         regs68L[ actualRx][7:0] <= Abd[7:0];
-                    else                        regs68L[ actualRx] <= Abd;
+                    if (Nanod_r.dbl2rxl)        regs68L[actualRx] <= Dbd;
+                    else if (abdIsByte)         regs68L[actualRx][7:0] <= Abd[7:0];
+                    else                        regs68L[actualRx] <= Abd;
                 end
                 else
-                    regs68L[ actualRx] <= Nanod.dbl2rxl ? Dbl : Abl;
+                    regs68L[actualRx] <= Nanod_r.dbl2rxl ? Dbl : Abl;
             end
 
-            if (Nanod.dbl2ryl | Nanod.abl2ryl) begin
+            if (Nanod_r.dbl2ryl | Nanod_r.abl2ryl) begin
                 if (~ryIsAreg) begin
-                    if (Nanod.dbl2ryl)          regs68L[ actualRy] <= Dbd;
-                    else if (abdIsByte)         regs68L[ actualRy][7:0] <= Abd[7:0];
-                    else                        regs68L[ actualRy] <= Abd;
+                    if (Nanod_r.dbl2ryl)        regs68L[actualRy] <= Dbd;
+                    else if (abdIsByte)         regs68L[actualRy][7:0] <= Abd[7:0];
+                    else                        regs68L[actualRy] <= Abd;
                 end
                 else
-                    regs68L[ actualRy] <= Nanod.dbl2ryl ? Dbl : Abl;
+                    regs68L[actualRy] <= Nanod_r.dbl2ryl ? Dbl : Abl;
             end
 
             // High registers are easier. Both A & D on the same buses, and not byte ops.
-            if (Nanod.dbh2rxh | Nanod.abh2rxh)
-                regs68H[ actualRx] <= Nanod.dbh2rxh ? Dbh : Abh;
-            if (Nanod.dbh2ryh | Nanod.abh2ryh)
-                regs68H[ actualRy] <= Nanod.dbh2ryh ? Dbh : Abh;
+            if (Nanod_r.dbh2rxh | Nanod_r.abh2rxh)
+                regs68H[actualRx] <= Nanod_r.dbh2rxh ? Dbh : Abh;
+            if (Nanod_r.dbh2ryh | Nanod_r.abh2ryh)
+                regs68H[actualRy] <= Nanod_r.dbh2ryh ? Dbh : Abh;
 
         end
     end
@@ -1516,19 +1526,19 @@ localparam
             Pch2Abh <= 1'b0;
         end
         else if (enT4) begin                // Must latch on T4 !
-            dbl2Pcl <= Nanod.dbl2reg & Nanod.pcldbl;
-            dbh2Pch <= Nanod.dbh2reg & Nanod.pchdbh;
-            abh2Pch <= Nanod.abh2reg & Nanod.pchabh;
-            abl2Pcl <= Nanod.abl2reg & Nanod.pclabl;
+            dbl2Pcl <= Nanod_w.dbl2reg & Nanod_w.pcldbl;
+            dbh2Pch <= Nanod_w.dbh2reg & Nanod_w.pchdbh;
+            abh2Pch <= Nanod_w.abh2reg & Nanod_w.pchabh;
+            abl2Pcl <= Nanod_w.abl2reg & Nanod_w.pclabl;
 
-            Pcl2Dbl <= Nanod.reg2dbl & Nanod.pcldbl;
-            Pch2Dbh <= Nanod.reg2dbh & Nanod.pchdbh;
-            Pcl2Abl <= Nanod.reg2abl & Nanod.pclabl;
-            Pch2Abh <= Nanod.reg2abh & Nanod.pchabh;
+            Pcl2Dbl <= Nanod_w.reg2dbl & Nanod_w.pcldbl;
+            Pch2Dbh <= Nanod_w.reg2dbh & Nanod_w.pchdbh;
+            Pcl2Abl <= Nanod_w.reg2abl & Nanod_w.pclabl;
+            Pch2Abh <= Nanod_w.reg2abh & Nanod_w.pchabh;
         end
 
         // Unique IF !!!
-        if (enT1 & Nanod.au2Pc)
+        if (enT1 & Nanod_w.au2Pc)
             PcL <= auReg[15:0];
         else if (enT3) begin
             if (dbl2Pcl)
@@ -1538,7 +1548,7 @@ localparam
         end
 
         // Unique IF !!!
-        if (enT1 & Nanod.au2Pc)
+        if (enT1 & Nanod_w.au2Pc)
             PcH <= auReg[31:16];
         else if (enT3) begin
             if (dbh2Pch)
@@ -1549,17 +1559,17 @@ localparam
 
         // Unique IF !!!
         if (enT3) begin
-            if (Nanod.dbl2Atl)
+            if (Nanod_r.dbl2Atl)
                 Atl <= Dbl;
-            else if (Nanod.abl2Atl)
+            else if (Nanod_r.abl2Atl)
                 Atl <= Abl;
         end
 
         // Unique IF !!!
         if (enT3) begin
-            if (Nanod.abh2Ath)
+            if (Nanod_r.abh2Ath)
                 Ath <= Abh;
-            else if (Nanod.dbh2Ath)
+            else if (Nanod_r.dbh2Ath)
                 Ath <= Dbh;
         end
 
@@ -1579,9 +1589,9 @@ localparam
     
         // Cheating: PREN always loaded from DBIN
         // Must be on T1 to branch earlier if reg mask is empty!
-        if (enT1 & Nanod.abl2Pren)
+        if (enT1 & Nanod_w.abl2Pren)
             prenLatch <= dbin;
-        else if (enT3 & Nanod.updPren) begin
+        else if (enT3 & Nanod_w.updPren) begin
             prenLatch [prHbit] <= 1'b0;
             movemRx <= Irdecod.movemPreDecr ? ~prHbit : prHbit;
         end
@@ -1597,7 +1607,7 @@ localparam
 
         if (Clks.pwrUp)
             dcr4 <= '0;
-        else if (enT3 & Nanod.abd2Dcr) begin
+        else if (enT3 & Nanod_r.abd2Dcr) begin
             dcrOutput <= dcrCode;
             dcr4 <= Abd[4];
         end
@@ -1610,22 +1620,22 @@ localparam
 
         if (enT3) begin
             // UNIQUE IF !!
-            if (Nanod.dbd2Alub)
+            if (Nanod_r.dbd2Alub)
                 alub <= Dbd;
-            else if (Nanod.abd2Alub)
+            else if (Nanod_r.abd2Alub)
                 alub <= Abd;                // abdIsByte affects this !!??
         end
     end
 
-    wire alueClkEn = enT3 & Nanod.dbd2Alue;
+    wire alueClkEn = enT3 & Nanod_r.dbd2Alue;
 
     // DOB/DBIN/IRC
 
     logic [15:0] dobInput;
-    wire dobIdle = (~| Nanod.dobCtrl);
+    wire dobIdle = (~| Nanod_r.dobCtrl);
 
     always_comb begin
-        unique case (Nanod.dobCtrl)
+        unique case (Nanod_r.dobCtrl)
         NANO_DOB_ADB:       dobInput = Abd;
         NANO_DOB_DBD:       dobInput = Dbd;
         NANO_DOB_ALU:       dobInput = aluOut;
@@ -1633,19 +1643,29 @@ localparam
         endcase
     end
 
-    dataIo dataIo( .clk, .Clks, .enT1, .enT2, .enT3, .enT4, .Nanod, .Irdecod,
-            .iEdb, .dobIdle, .dobInput, .aob0,
-            .Irc, .dbin, .oEdb);
+    dataIo U_dataIo
+    (
+        .clk, .Clks, .enT1, .enT2, .enT3, .enT4,
+        .Nanod_r, .Nanod_w, .Irdecod,
+        .iEdb, .dobIdle, .dobInput, .aob0,
+        .Irc, .dbin, .oEdb
+    );
 
-    fx68kAlu alu(
+    fx68kAlu U_fx68kAlu
+    (
         .clk, .pwrUp( Clks.pwrUp), .enT1, .enT3, .enT4,
-        .ird( Ird),
-        .aluColumn( Nanod.aluColumn), .aluAddrCtrl( Nanod.aluActrl),
-        .init( Nanod.aluInit), .finish( Nanod.aluFinish), .aluIsByte( Irdecod.isByte),
-        .ftu2Ccr( Nanod.ftu2Ccr),
+        .ird         (Ird),
+        .aluColumn   (Nanod_w.aluColumn),
+        .aluDataCtrl (Nanod_w.aluDctrl),
+        .aluAddrCtrl (Nanod_w.aluActrl),
+        .ftu2Ccr     (Nanod_w.ftu2Ccr),
+        .init        (Nanod_w.aluInit),
+        .finish      (Nanod_w.aluFinish),
+        .aluIsByte   (Irdecod.isByte),
         .alub, .ftu, .alueClkEn, .alue,
-        .aluDataCtrl( Nanod.aluDctrl), .iDataBus( Dbd), .iAddrBus(Abd),
-        .ze, .aluOut, .ccr);
+        .iDataBus( Dbd), .iAddrBus(Abd),
+        .ze, .aluOut, .ccr
+    );
 
 endmodule
 
@@ -1666,7 +1686,8 @@ module dataIo
     input               enT2,
     input               enT3,
     input               enT4,
-    input       s_nanod Nanod,
+    input     s_nanod_r Nanod_r,
+    input     s_nanod_w Nanod_w,
     input     s_irdecod Irdecod,
     input        [15:0] iEdb,
     input               aob0,
@@ -1702,9 +1723,9 @@ module dataIo
             isByte_T4 <= Irdecod.isByte;    // Includes MOVEP from mem, we could OR it here
 
         if (enT3) begin
-            dbinNoHigh <= Nanod.noHighByte;
-            dbinNoLow <= Nanod.noLowByte;
-            byteMux <= Nanod.busByte & isByte_T4 & ~aob0;
+            dbinNoHigh <= Nanod_w.noHighByte;
+            dbinNoLow  <= Nanod_w.noLowByte;
+            byteMux    <= Nanod_w.busByte & isByte_T4 & ~aob0;
         end
 
         if (enT1) begin
@@ -1713,8 +1734,8 @@ module dataIo
             xToIrc  <= 1'b0;
         end
         else if (enT3) begin
-            xToDbin <= Nanod.todbin;
-            xToIrc  <= Nanod.toIrc;
+            xToDbin <= Nanod_r.todbin;
+            xToIrc  <= Nanod_r.toIrc;
         end
 
         // Capture on T4 of the next ucycle
@@ -1742,12 +1763,12 @@ module dataIo
         // Wait states don't affect DOB operation that is done at the start of the bus cycle.
 
         if (enT4)
-            byteCycle <= Nanod.busByte & Irdecod.isByte;        // busIsByte but not MOVEP
+            byteCycle <= Nanod_w.busByte & Irdecod.isByte;        // busIsByte but not MOVEP
 
         // Originally byte low/high interconnect is done at EDB, not at DOB.
         if (enT3 & ~dobIdle) begin
-            dob[7:0] <= Nanod.noLowByte ? dobInput[15:8] : dobInput[ 7:0];
-            dob[15:8] <= (byteCycle | Nanod.noHighByte) ? dobInput[ 7:0] : dobInput[15:8];
+            dob[7:0] <= Nanod_w.noLowByte ? dobInput[15:8] : dobInput[ 7:0];
+            dob[15:8] <= (byteCycle | Nanod_w.noHighByte) ? dobInput[ 7:0] : dobInput[15:8];
         end
     end
     assign oEdb = dob;
@@ -1765,10 +1786,15 @@ endmodule
 
 module uaddrDecode
 (
-    input [15:0] opcode,
-    output [UADDR_WIDTH-1:0] a1, a2, a3,
-    output logic isPriv, isIllegal, isLineA, isLineF,
-    output [15:0] lineBmap
+    input             [15:0] opcode,
+    output [UADDR_WIDTH-1:0] a1,
+    output [UADDR_WIDTH-1:0] a2,
+    output [UADDR_WIDTH-1:0] a3,
+    output logic             isPriv,
+    output logic             isIllegal,
+    output logic             isLineA,
+    output logic             isLineF,
+    output            [15:0] lineBmap
 );
 
     wire [3:0] line = opcode[15:12];
diff --git a/fx68k_pkg.sv b/fx68k_pkg.sv
index a807bc2..91369f3 100644
--- a/fx68k_pkg.sv
+++ b/fx68k_pkg.sv
@@ -58,85 +58,147 @@ typedef struct packed
 // IRD decoded signals
 typedef struct packed
 {
-    logic isPcRel;
-    logic isTas;
-    logic implicitSp;
-    logic toCcr;
-    logic rxIsDt, ryIsDt;
-    logic rxIsUsp, rxIsMovem, movemPreDecr;
-    logic isByte;
-    logic isMovep;
-    logic [2:0] rx, ry;
-    logic rxIsAreg, ryIsAreg;
+    logic        isPcRel;
+    logic        isTas;
+    logic        implicitSp;
+    logic        toCcr;
+    logic        rxIsDt;
+    logic        ryIsDt;
+    logic        rxIsUsp;
+    logic        rxIsMovem;
+    logic        movemPreDecr;
+    logic        isByte;
+    logic        isMovep;
+    logic  [2:0] rx;
+    logic  [2:0] ry;
+    logic        rxIsAreg;
+    logic        ryIsAreg;
     logic [15:0] ftuConst;
-    logic [5:0] macroTvn;
-    logic inhibitCcr;
+    logic  [5:0] macroTvn;
+    logic        inhibitCcr;
 } s_irdecod;
 
 // Nano code decoded signals
 typedef struct packed
 {
-    logic permStart;
-    logic waitBusFinish;
-    logic isWrite;
-    logic busByte;
-    logic isRmc;
-    logic noLowByte, noHighByte;
-    
-    logic updTpend, clrTpend;
-    logic tvn2Ftu, const2Ftu;
-    logic ftu2Dbl, ftu2Abl;
-    logic abl2Pren, updPren;
-    logic inl2psw, ftu2Sr, sr2Ftu, ftu2Ccr, pswIToFtu;
-    logic ird2Ftu, ssw2Ftu;
-    logic initST;
-    logic Ir2Ird;
-    
-    logic auClkEn, noSpAlign;
-    logic [2:0] auCntrl;
-    logic todbin, toIrc;
-    logic dbl2Atl, abl2Atl, atl2Abl, atl2Dbl;
-    logic abh2Ath, dbh2Ath;
-    logic ath2Dbh, ath2Abh;
-    
-    logic db2Aob, ab2Aob, au2Aob;
-    logic aob2Ab, updSsw;
-    // logic adb2Dob, dbd2Dob, alu2Dob;
-    logic [1:0] dobCtrl;
-    
-    logic abh2reg, abl2reg;
-    logic reg2abl, reg2abh;
-    logic dbh2reg, dbl2reg;
-    logic reg2dbl, reg2dbh;
-    logic ssp, pchdbh, pcldbl, pclabl, pchabh;
-    
-    logic rxh2dbh, rxh2abh;
-    logic dbl2rxl, dbh2rxh;
-    logic rxl2db, rxl2ab;
-    logic abl2rxl, abh2rxh;
-    logic dbh2ryh, abh2ryh;
-    logic ryl2db, ryl2ab;
-    logic ryh2dbh, ryh2abh;
-    logic dbl2ryl, abl2ryl;
-    logic rz;
-    logic rxlDbl;
-    
-    logic [2:0] aluColumn;
-    logic [1:0] aluDctrl;
-    logic aluActrl;
-    logic aluInit, aluFinish;
-    logic abd2Dcr, dcr2Dbd;
-    logic dbd2Alue, alue2Dbd;
-    logic dbd2Alub, abd2Alub;
-    
-    logic alu2Dbd, alu2Abd;
-    logic au2Db, au2Ab, au2Pc;
-    logic dbin2Abd, dbin2Dbd;
-    logic extDbh, extAbh;
-    logic ablAbd, ablAbh;
-    logic dblDbd, dblDbh;
-    logic abdIsByte;
-} s_nanod;
+    logic       isRmc;         // r
+
+    logic       auClkEn;       // r
+    logic       noSpAlign;     // r
+    logic [2:0] auCntrl;       // r
+    logic       todbin;        // r
+    logic       toIrc;         // r
+    logic       dbl2Atl;       // r
+    logic       abl2Atl;       // r
+    logic       atl2Abl;       // r
+    logic       atl2Dbl;       // r
+    logic       abh2Ath;       // r
+    logic       dbh2Ath;       // r
+    logic       ath2Dbh;       // r
+    logic       ath2Abh;       // r
+
+    logic       aob2Ab;        // r
+    // logic adb2Dob;             // r
+    // logic dbd2Dob;             // r
+    // logic alu2Dob;             // r
+    logic [1:0] dobCtrl;       // r
+
+    logic       rxh2dbh;       // r
+    logic       rxh2abh;       // r
+    logic       dbl2rxl;       // r
+    logic       dbh2rxh;       // r
+    logic       rxl2db;        // r
+    logic       rxl2ab;        // r
+    logic       abl2rxl;       // r
+    logic       abh2rxh;       // r
+    logic       dbh2ryh;       // r
+    logic       abh2ryh;       // r
+    logic       ryl2db;        // r
+    logic       ryl2ab;        // r
+    logic       ryh2dbh;       // r
+    logic       ryh2abh;       // r
+    logic       dbl2ryl;       // r
+    logic       abl2ryl;       // r
+
+    logic       abd2Dcr;       // r
+    logic       dcr2Dbd;       // r
+    logic       dbd2Alue;      // r
+    logic       alue2Dbd;      // r
+    logic       dbd2Alub;      // r
+    logic       abd2Alub;      // r
+
+    logic       alu2Dbd;       // r
+    logic       alu2Abd;       // r
+    logic       extDbh;        // r
+    logic       extAbh;        // r
+    logic       ablAbd;        // r
+    logic       ablAbh;        // r
+    logic       dblDbd;        // r
+    logic       dblDbh;        // r
+} s_nanod_r;
+
+typedef struct packed
+{
+    logic       permStart;     // w
+    logic       waitBusFinish; // w
+    logic       isWrite;       // w
+    logic       busByte;       // w
+    logic       noLowByte;     // w
+    logic       noHighByte;    // w
+
+    logic       updTpend;      // w
+    logic       clrTpend;      // w
+    logic       tvn2Ftu;       // w
+    logic       const2Ftu;     // w
+    logic       ftu2Dbl;       // w
+    logic       ftu2Abl;       // w
+    logic       abl2Pren;      // w
+    logic       updPren;       // w
+    logic       inl2psw;       // w
+    logic       ftu2Sr;        // w
+    logic       sr2Ftu;        // w
+    logic       ftu2Ccr;       // w
+    logic       pswIToFtu;     // w
+    logic       ird2Ftu;       // w
+    logic       ssw2Ftu;       // w
+    logic       initST;        // w
+    logic       Ir2Ird;        // w
+
+    logic       db2Aob;        // w
+    logic       ab2Aob;        // w
+    logic       au2Aob;        // w
+    logic       updSsw;        // w
+
+    logic       abh2reg;       // w
+    logic       abl2reg;       // w
+    logic       reg2abl;       // w
+    logic       reg2abh;       // w
+    logic       dbh2reg;       // w
+    logic       dbl2reg;       // w
+    logic       reg2dbl;       // w
+    logic       reg2dbh;       // w
+    logic       ssp;           // w
+    logic       pchdbh;        // w
+    logic       pcldbl;        // w
+    logic       pclabl;        // w
+    logic       pchabh;        // w
+
+    logic       rz;            // w
+    logic       rxlDbl;        // w
+
+    logic [2:0] aluColumn;     // w
+    logic [1:0] aluDctrl;      // w
+    logic       aluActrl;      // w
+    logic       aluInit;       // w
+    logic       aluFinish;     // w
+
+    logic       au2Db;         // w
+    logic       au2Ab;         // w
+    logic       au2Pc;         // w
+    logic       dbin2Abd;      // w
+    logic       dbin2Dbd;      // w
+    logic       abdIsByte;     // w
+} s_nanod_w;
 
 // EA decode
 function [3:0] eaDecode;

From b2ee11c67f803bd9b30a9e77ce18665be463158a Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Fri, 28 Aug 2020 20:55:22 +0200
Subject: [PATCH 05/16] Increase address bus width to 32 bits

---
 fx68k.sv | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/fx68k.sv b/fx68k.sv
index 562aa9e..94b89a6 100644
--- a/fx68k.sv
+++ b/fx68k.sv
@@ -41,7 +41,7 @@ module fx68k
     input BRn, BGACKn,
     input IPL0n, input IPL1n, input IPL2n,
     input [15:0] iEdb, output [15:0] oEdb,
-    output [23:1] eab
+    output [31:1] eab
 );
 
     s_clks Clks;
@@ -1118,7 +1118,7 @@ module excUnit
     output [15:0] AblOut,
     output logic [15:0] Irc,
     output logic [15:0] oEdb,
-    output logic [23:1] eab
+    output logic [31:1] eab
 );
 
 localparam
@@ -1431,7 +1431,7 @@ localparam
         end
     end
 
-    assign eab = aob[23:1];
+    assign eab = aob[31:1];
     assign aob0 = aob[0];
 
     // AU
@@ -2718,7 +2718,7 @@ module fx68kTop( input clk32,
     output FC0, output FC1, output FC2,
     output BGn,
     output oRESETn, output oHALTEDn,
-    output [23:1] eab
+    output [31:1] eab
     );
 
     // Clock must be at least twice the desired frequency. A 32 MHz clock means a maximum 16 MHz effective frequency.

From d04a8b37a5d2c50face37e3182005777ac76220a Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Sat, 29 Aug 2020 00:27:03 +0200
Subject: [PATCH 06/16] ALU optimization by re-ordering ALU opcodes

---
 fx68kAlu.sv | 335 ++++++++++++++++++++++++++++++----------------------
 1 file changed, 193 insertions(+), 142 deletions(-)

diff --git a/fx68kAlu.sv b/fx68kAlu.sv
index 1fcd090..cfad24f 100644
--- a/fx68kAlu.sv
+++ b/fx68kAlu.sv
@@ -11,22 +11,36 @@
 
 localparam MASK_NBITS = 5;
 
-localparam
-        OP_AND = 1,
-        OP_SUB = 2, OP_SUBX = 3, OP_ADD = 4,
-        OP_EXT = 5, OP_SBCD = 6, OP_SUB0 = 7,
-        OP_OR = 8, OP_EOR = 9,
-        OP_SUBC = 10, OP_ADDC = 11, OP_ADDX = 12,
-        OP_ASL = 13,
-        OP_ASR = 14,
-        OP_LSL = 15,
-        OP_LSR = 16,
-        OP_ROL = 17,
-        OP_ROR = 18,
-        OP_ROXL = 19,
-        OP_ROXR = 20,
-        OP_SLAA = 21,
-        OP_ABCD = 22;
+localparam [4:0]
+    // 5'b000xx : BCD
+    OP_0    = 5'd0, // Not used
+    OP_1    = 5'd1, // Not used
+    OP_ABCD = 5'd2,
+    OP_SBCD = 5'd3,
+    // 5'b001xx : Logic
+    OP_OR   = 5'd4,
+    OP_EOR  = 5'd5,
+    OP_AND  = 5'd6,
+    OP_EXT  = 5'd7,
+    // 5'b01xxx : Adder
+    OP_ADD0 = 5'd8, // Not used
+    OP_SUB0 = 5'd9,
+    OP_ADD  = 5'd10,
+    OP_SUB  = 5'd11,
+    OP_ADDC = 5'd12,
+    OP_SUBC = 5'd13,
+    OP_ADDX = 5'd14,
+    OP_SUBX = 5'd15,
+    // 5'b1xxxx : Shifter
+    OP_ASL  = 5'd16,
+    OP_ASR  = 5'd17,
+    OP_LSL  = 5'd18,
+    OP_LSR  = 5'd19,
+    OP_ROL  = 5'd20,
+    OP_ROR  = 5'd21,
+    OP_ROXL = 5'd22,
+    OP_ROXR = 5'd23,
+    OP_SLAA = 5'd24;
 
 module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     input [15:0] ird,
@@ -120,7 +134,8 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     logic shftCin, shftRight, addCin;
 
     // Register some decoded signals
-    always_ff @( posedge clk) begin
+    always_ff @( posedge clk) begin
+    
         if (enT3) begin
             row     <= cRow;
             isArX   <= cIsArX;
@@ -168,9 +183,16 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
 
     wire [7:0] bcdResult;
     wire bcdC, bcdV;
-    aluCorf aluCorf( .binResult( aluLatch[7:0]), .hCarry( coreH),
-        .bAdd( (oper != OP_SBCD) ), .cin( pswCcr[ XF]),
-        .bcdResult( bcdResult), .dC( bcdC), .ov( bcdV));
+    aluCorf aluCorf
+    (
+        .binResult (aluLatch[7:0]),
+        .hCarry    (coreH),
+        .bAdd      (~oper[0]),
+        .cin       (pswCcr[XF]),
+        .bcdResult (bcdResult),
+        .dC        (bcdC),
+        .ov        (bcdV)
+    );
 
     // BCD adjust is among the slowest processing on ALU !
     // Precompute and register BCD result on T1
@@ -185,41 +207,37 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     end
 
     // Adder carry in selector
-    always_comb
-    begin
-        case( oper)
-            OP_ADD, OP_SUB:   addCin = 1'b0;
-            OP_SUB0:          addCin = 1'b1;            // NOT = 0 - op - 1
-            OP_ADDC,OP_SUBC:  addCin = ccrCore[ CF];
-            OP_ADDX,OP_SUBX:  addCin = pswCcr[ XF];
-            default: addCin = 1'bX;
+    always_comb begin
+        case (oper[2:0])
+            OP_ADD0[2:0], OP_SUB0[2:0]: addCin = 1'b1;            // NOT = 0 - op - 1
+            OP_ADD[2:0],  OP_SUB[2:0]:  addCin = 1'b0;
+            OP_ADDC[2:0], OP_SUBC[2:0]: addCin = ccrCore[CF];
+            OP_ADDX[2:0], OP_SUBX[2:0]: addCin = pswCcr[XF];
         endcase
     end
 
     // Shifter carry in and direction selector
     always_comb begin
-        case( oper)
-        OP_LSL, OP_ASL, OP_ROL, OP_ROXL, OP_SLAA:   shftRight = 1'b0;
-        OP_LSR, OP_ASR, OP_ROR, OP_ROXR:            shftRight = 1'b1;
-        default:                                    shftRight = 1'bX;
-        endcase
-
-        case( oper)
-        OP_LSR,
-        OP_ASL,
-        OP_LSL:     shftCin = 1'b0;
-        OP_ROL,
-        OP_ASR:     shftCin = shftMsb;
-        OP_ROR:     shftCin = aOperand[0];
-        OP_ROXL,
-        OP_ROXR:
-            if( shftIsMul)
-                shftCin = rIrd8 ? pswCcr[NF] ^ pswCcr[VF] : pswCcr[ CF];
-            else
-                shftCin = pswCcr[ XF];
-
-        OP_SLAA:    shftCin = aluColumn[1];   // col4 -> 0, col 6-> 1
-        default:    shftCin = 'X;
+        shftRight = oper[0];
+
+        case (oper[3:0])
+            OP_LSR[3:0],
+            OP_ASL[3:0],
+            OP_LSL[3:0]:
+                shftCin = 1'b0;
+            OP_ROL[3:0],
+            OP_ASR[3:0]:
+                shftCin = shftMsb;
+            OP_ROR[3:0]:
+                shftCin = aOperand[0];
+            OP_ROXL[3:0],
+            OP_ROXR[3:0]:
+                if (shftIsMul)
+                    shftCin = rIrd8 ? pswCcr[NF] ^ pswCcr[VF] : pswCcr[ CF];
+                else
+                    shftCin = pswCcr[ XF];
+            default: // OP_SLAA
+                shftCin = aluColumn[1];   // col4 -> 0, col 6-> 1
         endcase
     end
 
@@ -227,40 +245,50 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     always_comb begin
 
         // sub is DATA - ADDR
-        mySubber( aOperand, dOperand, addCin,
-            (oper == OP_ADD) | (oper == OP_ADDC) | (oper == OP_ADDX),
+        mySubber( aOperand, dOperand, addCin, ~oper[0],
             isByte, subResult, subCout, subOv);
 
-        isShift = 1'b0;
-        case( oper)
-        OP_AND: result = aOperand & dOperand;
-        OP_OR:  result = aOperand | dOperand;
-        OP_EOR: result = aOperand ^ dOperand;
-
-        OP_EXT: result = { {8{aOperand[7]}}, aOperand[7:0]};
-
-        OP_SLAA,
-        OP_ASL, OP_ASR,
-        OP_LSL, OP_LSR,
-        OP_ROL, OP_ROR,
-        OP_ROXL, OP_ROXR:
+        isShift = oper[4];
+        
+        case (oper)
+            OP_0, // not used
+            OP_1, // not used
+            OP_ABCD,
+            OP_SBCD:
+            begin
+                result = { 8'h00, bcdLatch };
+            end
+            
+            OP_OR:  result = aOperand | dOperand;
+            OP_EOR: result = aOperand ^ dOperand;
+            OP_AND: result = aOperand & dOperand;
+            OP_EXT: result = { {8{aOperand[7]}}, aOperand[7:0] };
+
+            OP_ADD0, // Not used
+            OP_SUB0,
+            OP_ADD,
+            OP_SUB,
+            OP_ADDC,
+            OP_SUBC,
+            OP_ADDX,
+            OP_SUBX:
+            begin
+                result = subResult;
+            end
+            
+            //OP_ASL,
+            //OP_ASR,
+            //OP_LSL,
+            //OP_LSR,
+            //OP_ROL,
+            //OP_ROR,
+            //OP_ROXL,
+            //OP_ROXR,
+            //OP_SLAA:
+            default:
             begin
                 result = shftResult[15:0];
-                isShift = 1'b1;
             end
-
-        OP_ADD,
-        OP_ADDC,
-        OP_ADDX,
-        OP_SUB,
-        OP_SUBC,
-        OP_SUB0,
-        OP_SUBX:    result = subResult;
-
-        OP_ABCD,
-        OP_SBCD:    result = { 8'hXX, bcdLatch};
-
-        default:    result = 'X;
         endcase
     end
 
@@ -306,103 +334,126 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     // CCR flags process
     always_comb begin
 
-        ccrTemp[XF] = pswCcr[XF];     ccrTemp[CF] = 0;     ccrTemp[VF] = 0;
+        ccrTemp[XF] = pswCcr[XF];
+        ccrTemp[CF] = 1'b0;
+        ccrTemp[VF] = 1'b0;
 
         // Not on all operators
-        ccrTemp[ ZF] = isByte ? ~(| result[7:0]) : ~(| result);
-        ccrTemp[ NF] = isByte ? result[7] : result[15];
-
-        unique case( oper)
-
-        OP_EXT:
-            // Division overflow.
-            if( aluColumn == 5) begin
-                ccrTemp[VF] = 1'b1;
-                ccrTemp[NF] = 1'b1;             ccrTemp[ ZF] = 1'b0;
+        ccrTemp[ZF] = isByte ? ~(|result[7:0]) : ~(|result);
+        ccrTemp[NF] = isByte ? result[7] : result[15];
+
+        unique case (oper)
+            OP_0, // not used
+            OP_1, // not used
+            OP_ABCD,
+            OP_SBCD:
+            begin
+                ccrTemp[XF] = bcdCarry;
+                ccrTemp[CF] = bcdCarry;
+                ccrTemp[VF] = bcdOverf;
             end
-
-        OP_SUB0,                // used by NOT
-        OP_OR,
-        OP_EOR:
+
+            OP_SUB0, // used by NOT
+            OP_ADD0, // not used
+            OP_OR,
+            OP_EOR:
             begin
-                ccrTemp[CF] = 0;      ccrTemp[VF] = 0;
+                ccrTemp[CF] = 1'b0;
+                ccrTemp[VF] = 1'b0;
             end
 
-        OP_AND:
+            OP_AND:
             begin
                 // ROXL/ROXR indeed copy X to C in column 1 (OP_AND), executed before entering the loop.
                 // Needed when rotate count is zero, the ucode with the ROX operator never reached.
                 //  C must be set to the value of X, X remains unaffected.
-                if( (aluColumn == 1) & (row[11] | row[8]))
+                if ((aluColumn == 1) & (row[11] | row[8])) begin
                     ccrTemp[CF] = pswCcr[XF];
-                else
-                    ccrTemp[CF] = 0;
-                ccrTemp[VF] = 0;
+                end
+                else begin
+                    ccrTemp[CF] = 1'b0;
+                end
+                ccrTemp[VF] = 1'b0;
             end
 
-        // Assumes col 3 of DIV use C and not X !
-        // V will be set in other cols (2/3) of DIV
-        OP_SLAA:   ccrTemp[ CF] = aOperand[15];
+            OP_EXT:
+            begin
+                // Division overflow.
+                if (aluColumn == 5) begin
+                    ccrTemp[VF] = 1'b1;
+                    ccrTemp[NF] = 1'b1;
+                    ccrTemp[ZF] = 1'b0;
+                end
+            end
 
-        OP_LSL,OP_ROXL:
-            begin
-                ccrTemp[ CF] = shftMsb;
-                ccrTemp[ XF] = shftMsb;
-                ccrTemp[ VF] = 1'b0;
+            OP_ADD,
+            OP_ADDC,
+            OP_ADDX,
+            OP_SUB,
+            OP_SUBC,
+            OP_SUBX:
+            begin
+                ccrTemp[CF] = subCout;
+                ccrTemp[XF] = subCout;
+                ccrTemp[VF] = subOv;
             end
 
-        OP_LSR,OP_ROXR:
-            begin
+            OP_LSL,
+            OP_ROXL:
+            begin
+                ccrTemp[CF] = shftMsb;
+                ccrTemp[XF] = shftMsb;
+                ccrTemp[VF] = 1'b0;
+            end
+
+            OP_LSR,
+            OP_ROXR:
+            begin
                 // 0 Needed for mul, or carry gets in high word
-                ccrTemp[ CF] = shftIsMul ? 1'b0 : aOperand[0];
-                ccrTemp[ XF] = aOperand[0];
+                ccrTemp[CF] = shftIsMul ? 1'b0 : aOperand[0];
+                ccrTemp[XF] = aOperand[0];
                 // Not relevant for MUL, we clear it at mulm6 (1f) anyway.
                 // Not that MUL can never overlow!
-                ccrTemp[ VF] = 0;
+                ccrTemp[VF] = 1'b0;
                 // Z is checking here ALU (low result is actually in ALUE).
                 // But it is correct, see comment above.
             end
 
-        OP_ASL:
+            OP_ASL:
             begin
-                ccrTemp[ XF] = shftMsb;         ccrTemp[ CF] = shftMsb;
+                ccrTemp[XF] = shftMsb;
+                ccrTemp[CF] = shftMsb;
                 // V set if msb changed on any shift.
                 // Otherwise clear previously on OP_AND (col 1i).
-                ccrTemp[ VF] = pswCcr[VF] | (shftMsb ^
+                ccrTemp[VF] = pswCcr[VF] | (shftMsb ^
                     (isLong ? alue[15-1] : (isByte ? aOperand[7-1] : aOperand[15-1])) );
             end
-        OP_ASR:
-            begin
-                ccrTemp[ XF] = aOperand[0];     ccrTemp[ CF] = aOperand[0];
-                ccrTemp[ VF] = 0;
-            end
-
-        // X not changed on ROL/ROR !
-        OP_ROL:     ccrTemp[ CF] = shftMsb;
-        OP_ROR:     ccrTemp[ CF] = aOperand[0];
-
-        OP_ADD,
-        OP_ADDC,
-        OP_ADDX,
-        OP_SUB,
-        OP_SUBC,
-        OP_SUBX:
-            begin
-                ccrTemp[ CF] = subCout;
-                ccrTemp[ XF] = subCout;
-                ccrTemp[ VF] = subOv;
+            
+            OP_ASR:
+            begin
+                ccrTemp[XF] = aOperand[0];
+                ccrTemp[CF] = aOperand[0];
+                ccrTemp[VF] = 1'b0;
             end
 
-        OP_ABCD,
-        OP_SBCD:
+            // X not changed on ROL/ROR !
+            OP_ROL:
             begin
-                ccrTemp[ XF] = bcdCarry;
-                ccrTemp[ CF] = bcdCarry;
-                ccrTemp[ VF] = bcdOverf;
+                ccrTemp[CF] = shftMsb;
             end
 
-        endcase
+            OP_ROR:
+            begin
+                ccrTemp[CF] = aOperand[0];
+            end
 
+            // Assumes col 3 of DIV use C and not X !
+            // V will be set in other cols (2/3) of DIV
+            default: // OP_SLAA
+            begin
+                ccrTemp[CF] = aOperand[15];
+            end
+        endcase
     end
 
     // Core and psw latched at the same cycle

From b32f1c5924d53757c4cdd04ab106034a907adbd0 Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Sat, 29 Aug 2020 00:45:35 +0200
Subject: [PATCH 07/16] Stupid typo fix for TAS instruction

---
 fx68k.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fx68k.sv b/fx68k.sv
index 94b89a6..9fd2d77 100644
--- a/fx68k.sv
+++ b/fx68k.sv
@@ -1043,8 +1043,8 @@ module irdDecode
             lineOnehot[4'hC]:
                 ftuConst = 16'h000F;
 
-            lineOnehot[4]: // TAS
-                ftuConst = 16'h8000;
+            lineOnehot[4'h4]: // TAS
+                ftuConst = 16'h0080;
 
             default:
                 ftuConst = 16'h0000;

From f2be6ec25b431376bf7ee438a86b131e70b1a517 Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Sat, 29 Aug 2020 00:46:23 +0200
Subject: [PATCH 08/16] ALU optimization by re-writing the adder

---
 fx68kAlu.sv | 35 ++++++++++++++++++-----------------
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/fx68kAlu.sv b/fx68kAlu.sv
index cfad24f..bfaf2b6 100644
--- a/fx68kAlu.sv
+++ b/fx68kAlu.sv
@@ -209,10 +209,14 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     // Adder carry in selector
     always_comb begin
         case (oper[2:0])
-            OP_ADD0[2:0], OP_SUB0[2:0]: addCin = 1'b1;            // NOT = 0 - op - 1
-            OP_ADD[2:0],  OP_SUB[2:0]:  addCin = 1'b0;
-            OP_ADDC[2:0], OP_SUBC[2:0]: addCin = ccrCore[CF];
-            OP_ADDX[2:0], OP_SUBX[2:0]: addCin = pswCcr[XF];
+            OP_ADD0[2:0]: addCin = 1'b1; // Not used
+            OP_SUB0[2:0]: addCin = 1'b0; // NOT = 0 + ~op
+            OP_ADD[2:0]:  addCin = 1'b0;
+            OP_SUB[2:0]:  addCin = 1'b1;
+            OP_ADDC[2:0]: addCin =  ccrCore[CF];
+            OP_SUBC[2:0]: addCin = ~ccrCore[CF];
+            OP_ADDX[2:0]: addCin =  pswCcr[XF];
+            OP_SUBX[2:0]: addCin = ~pswCcr[XF];
         endcase
     end
 
@@ -299,25 +303,23 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
         output cout, ov;
 
         // Not very efficient!
-        logic [16:0] rtemp;
+        logic [17:0] rtemp;
         logic rm,sm,dm,tsm;
 
         begin
-            if( isByte)
+            rtemp = { 1'b0, inpb, cin }
+                  + { 1'b0, inpa ^ {16{~bAdd}}, cin };
+            if (isByte)
             begin
-                rtemp = bAdd ? { 9'b0, inpb[7:0] } + { 9'b0, inpa[7:0] } + { 16'b0, cin }
-                             : { 9'b0, inpb[7:0] } - { 9'b0, inpa[7:0] } - { 16'b0, cin };
-                result = { {8{ rtemp[7]}}, rtemp[7:0]};
-                cout = rtemp[8];
+                result = { {8{ rtemp[8]}}, rtemp[8:1] };
+                cout   = rtemp[9];
             end
             else begin
-                rtemp = bAdd ? { 1'b0, inpb } + { 1'b0, inpa } + { 16'b0, cin }
-                             : { 1'b0, inpb } - { 1'b0, inpa } - { 16'b0, cin };
-                result = rtemp[ 15:0];
-                cout = rtemp[16];
+                result = rtemp[16:1];
+                cout   = rtemp[17];
             end
 
-            rm  = isByte ? rtemp[7] : rtemp[15];
+            rm  = isByte ? rtemp[8] : rtemp[16];
             dm  = isByte ? inpb[ 7] : inpb[ 15];
             tsm = isByte ? inpa[ 7] : inpa[ 15];
             sm  = bAdd ? tsm : ~tsm;
@@ -325,8 +327,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
             ov = (sm & dm & ~rm) | (~sm & ~dm & rm);
 
             // Store half carry for bcd correction
-            subHcarry = inpa[4] ^ inpb[4] ^ rtemp[4];
-
+            subHcarry = inpa[4] ^ inpb[4] ^ rtemp[5];
         end
     endtask
 

From dde38897a968f45c217e3e827fc6c760e26296a4 Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Sat, 29 Aug 2020 13:25:52 +0200
Subject: [PATCH 09/16] Use one-hot encoding instead of enum on tState signal

---
 fx68k.sv | 73 ++++++++++++++++++++++++++++++++++++++++++++++----------
 1 file changed, 61 insertions(+), 12 deletions(-)

diff --git a/fx68k.sv b/fx68k.sv
index 9fd2d77..5b10d10 100644
--- a/fx68k.sv
+++ b/fx68k.sv
@@ -55,30 +55,79 @@ module fx68k
     wire wClk;
 
     // Internal sub clocks T1-T4
-    enum int unsigned { T0 = 0, T1, T2, T3, T4} tState;
-    wire enT1 = Clks.enPhi1 & (tState == T4) & ~wClk;
-    wire enT2 = Clks.enPhi2 & (tState == T1);
-    wire enT3 = Clks.enPhi1 & (tState == T2);
-    wire enT4 = Clks.enPhi2 & ((tState == T0) | (tState == T3));
+    localparam
+        T0 = 0,
+        T1 = 1,
+        T2 = 2,
+        T3 = 3,
+        T4 = 4;
+    reg [4:0] tState;
 
     // T4 continues ticking during reset and group0 exception.
     // We also need it to erase ucode output latched on T4.
     always_ff @(posedge clk) begin
 
         if (Clks.pwrUp) begin
-            tState <= T0;
+            tState <= 5'b00001; // T0
         end
         else begin
-            case (tState)
-                T0: if (Clks.enPhi2) tState <= T4;
-                T1: if (Clks.enPhi2) tState <= T2;
-                T2: if (Clks.enPhi1) tState <= T3;
-                T3: if (Clks.enPhi2) tState <= T4;
-                T4: if (Clks.enPhi1) tState <= wClk ? T0 : T1;
+            tState <= 5'b00000;
+            case (1'b1)
+                tState[T0]:
+                begin
+                    if (Clks.enPhi2) begin
+                        tState[T4] <= 1'b1;
+                    end
+                    else begin
+                        tState[T0] <= 1'b1;
+                    end
+                end
+                tState[T1]:
+                begin
+                    if (Clks.enPhi2) begin
+                        tState[T2] <= 1'b1;
+                    end
+                    else begin
+                        tState[T1] <= 1'b1;
+                    end
+                end
+                tState[T2]:
+                begin
+                    if (Clks.enPhi1) begin
+                        tState[T3] <= 1'b1;
+                    end
+                    else begin
+                        tState[T2] <= 1'b1;
+                    end
+                end
+                tState[T3]:
+                begin
+                    if (Clks.enPhi2) begin
+                        tState[T4] <= 1'b1;
+                    end
+                    else begin
+                        tState[T3] <= 1'b1;
+                    end
+                end
+                tState[T4]:
+                begin
+                    if (Clks.enPhi1) begin
+                        tState[T0] <= wClk;
+                        tState[T1] <= ~wClk;
+                    end
+                    else begin
+                        tState[T4] <= 1'b1;
+                    end
+                end
             endcase
         end
     end
 
+    wire enT1 = Clks.enPhi1 & tState[T4] & ~wClk;
+    wire enT2 = Clks.enPhi2 & tState[T1];
+    wire enT3 = Clks.enPhi1 & tState[T2];
+    wire enT4 = Clks.enPhi2 & (tState[T0] | tState[T3]);
+
     // The following signals are synchronized with 3 couplers, phi1-phi2-phi1.
     // Will be valid internally one cycle later if changed at the rasing edge of the clock.
     //

From 03fd7f765b24b871532562824855917fa52dccd2 Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Sat, 29 Aug 2020 16:18:18 +0200
Subject: [PATCH 10/16] Added E clock falling / rising edge signals

Some code clean up
---
 fx68k.sv | 165 +++++++++++++++++++++++++++++++++++--------------------
 1 file changed, 106 insertions(+), 59 deletions(-)

diff --git a/fx68k.sv b/fx68k.sv
index 5b10d10..3799f8d 100644
--- a/fx68k.sv
+++ b/fx68k.sv
@@ -22,25 +22,44 @@ import fx68k_pkg::*;
 
 module fx68k
 (
-    input clk,
-    input HALTn,                    // Used for single step only. Force high if not used
-    // input logic HALTn = 1'b1,            // Not all tools support default port values
-
+    input         clk,      // Master clock
+    input         enPhi1,   // Clock enable : next cycle is PHI1 (clock rising edge)
+    input         enPhi2,   // Clock enable : next cycle is PHI2 (clock falling edge)
+    
+    input         HALTn,    // Used for single step only. Force high if not used
     // These two signals don't need to be registered. They are not async reset.
-    input extReset,         // External sync reset on emulated system
-    input pwrUp,            // Asserted together with reset on emulated system coldstart
-    input enPhi1, enPhi2,   // Clock enables. Next cycle is PHI1 or PHI2
-
-    output eRWn, output ASn, output LDSn, output UDSn,
-    output logic E, output VMAn,
-    output FC0, output FC1, output FC2,
-    output BGn,
-    output oRESETn, output oHALTEDn,
-    input DTACKn, input VPAn,
-    input BERRn,
-    input BRn, BGACKn,
-    input IPL0n, input IPL1n, input IPL2n,
-    input [15:0] iEdb, output [15:0] oEdb,
+    input         extReset, // External sync reset on emulated system
+    input         pwrUp,    // Asserted together with reset on emulated system coldstart
+    output        oRESETn,
+    output        oHALTEDn,
+    // 6800 peripheral access
+    output logic  E,        // E clock
+    output        E_rise,   // E clock rising edge
+    output        E_fall,   // E clock falling edge
+    input         VPAn,     // Valid peripheral address
+    output        VMAn,     // Valid memory address
+    // Control signals
+    output        ASn,      // Address strobe
+    output        eRWn,     // Read (1) / Write (0)
+    output        LDSn,     // Lower data strobe
+    output        UDSn,     // Upper data strobe
+    output        FC2,      // Function code
+    output        FC1,
+    output        FC0,
+    input         DTACKn,   // Data acknowledge
+    input         BERRn,    // Bus error
+    // Bus cycles stealing
+    input         BRn,      // Bus request
+    output        BGn,      // Bus granted
+    input         BGACKn,   // Bus granted acknowledge
+    // Interrupts requests
+    input         IPL2n,    // Interrupt level
+    input         IPL1n,
+    input         IPL0n,
+    // Data bus
+    input  [15:0] iEdb,
+    output [15:0] oEdb,
+    // Address bus
     output [31:1] eab
 );
 
@@ -418,7 +437,7 @@ module fx68k
 
     // E clock and counter, VMA
     reg [3:0] eCntr;
-    reg rVma;
+    reg       rVma;
 
     assign VMAn = rVma;
 
@@ -432,17 +451,14 @@ module fx68k
             eCntr <= 4'd0;
             rVma  <= 1'b1;
         end
+        
+        // Cycles counter
         if (Clks.enPhi2) begin
-            if (eCntr == 4'd9)
-                E <= 1'b0;
-            else if (eCntr == 4'd5)
-                E <= 1'b1;
-
-            if (eCntr == 4'd9)
-                eCntr <= 4'd0;
-            else
-                eCntr <= eCntr + 4'd1;
+            eCntr <= (eCntr == 4'd9) ? 4'd0 : eCntr + 4'd1;
         end
+        
+        // E clock generation
+        E <= (E | E_rise) & ~E_fall;
 
         if (Clks.enPhi2 & addrOe & ~Vpai & (eCntr == 4'd3))
             rVma <= 1'b0;
@@ -450,6 +466,9 @@ module fx68k
             rVma <= 1'b1;
     end
 
+    assign E_rise = (eCntr == 4'd5) ? Clks.enPhi2 : 1'b0;
+    assign E_fall = (eCntr == 4'd9) ? Clks.enPhi2 : 1'b0;
+
     always_ff @(posedge clk) begin
 
         // This timing is critical to stop the clock phases at the exact point on bus/addr error.
@@ -1480,7 +1499,7 @@ localparam
         end
     end
 
-    assign eab = aob[31:1];
+    assign eab  = aob[31:1];
     assign aob0 = aob[0];
 
     // AU
@@ -2751,31 +2770,48 @@ endmodule
 //
 
 `ifdef FX68K_TEST
-module fx68kTop( input clk32,
-    input extReset,
-    // input pwrUp,
-
-    input DTACKn, input VPAn,
-    input BERRn,
-    input BRn, BGACKn,
-    input IPL0n, input IPL1n, input IPL2n,
-    input [15:0] iEdb,
-
+module fx68kTop
+(
+    input         clk32,
+    input         extReset,
+    output        oRESETn,
+    output        oHALTEDn,
+    //
+    output        E,
+    output        E_rise,
+    output        E_fall,
+    input         VPAn,
+    output        VMAn,
+    //
+    output        ASn,
+    output        eRWn,
+    output        LDSn,
+    output        UDSn,
+    output        FC2,
+    output        FC1,
+    output        FC0,
+    input         DTACKn,
+    input         BERRn,
+    //
+    input         BRn,
+    output        BGn,
+    input         BGACKn,
+    //
+    input         IPL2n,
+    input         IPL1n,
+    input         IPL0n,
+    //
+    input  [15:0] iEdb,
     output [15:0] oEdb,
-    output eRWn, output ASn, output LDSn, output UDSn,
-    output logic E, output VMAn,
-    output FC0, output FC1, output FC2,
-    output BGn,
-    output oRESETn, output oHALTEDn,
     output [31:1] eab
-    );
+);
 
     // Clock must be at least twice the desired frequency. A 32 MHz clock means a maximum 16 MHz effective frequency.
     // In this example we divide the clock by 4. Resulting on an effective processor running at 8 MHz.
 
-    reg [1:0] clkDivisor = '0;
+    reg [1:0] clkDivisor = 2'd0;
     always @( posedge clk32) begin
-        clkDivisor <= clkDivisor + 1'b1;
+        clkDivisor <= clkDivisor + 2'd1;
     end
 
     /*
@@ -2784,23 +2820,34 @@ module fx68kTop( input clk32,
     There can be any number of cycles, or none, even variable non constant cycles, between each pulse.
     */
 
-    wire enPhi1 = (clkDivisor == 2'b11);
-    wire enPhi2 = (clkDivisor == 2'b01);
-
+    wire enPhi1 = (clkDivisor == 2'd3) ? 1'b1 : 1'b0;
+    wire enPhi2 = (clkDivisor == 2'd1) ? 1'b1 : 1'b0;
 
-    fx68k fx68k( .clk( clk32),
-        .extReset, .pwrUp( extReset), .enPhi1, .enPhi2,
 
-        .DTACKn, .VPAn, .BERRn, .BRn, .BGACKn,
+    fx68k fx68k
+    (
+        .clk (clk32),
+        .enPhi1,
+        .enPhi2,
+        
+        .extReset,
+        .pwrUp (extReset),
+        .oRESETn, .oHALTEDn,
+
+        .E, .E_rise, .E_fall,
+        .VPAn, .VMAn,
+        
+        .ASn, .eRWn, .LDSn, .UDSn,
+        .FC2, .FC1, .FC0,
+        .DTACKn, .BERRn,
+        
+        .BRn, .BGn, .BGACKn,
         .IPL0n, .IPL1n, .IPL2n,
+        
         .iEdb,
-
         .oEdb,
-        .eRWn, .ASn, .LDSn, .UDSn,
-        .E, .VMAn,
-        .FC0, .FC1, .FC2,
-        .BGn,
-        .oRESETn, .oHALTEDn, .eab);
+        .eab
+    );
 
 endmodule
 `endif

From 07584a4f2f8825a4ba21cfd2011f41e4a995f002 Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Sat, 29 Aug 2020 17:26:00 +0200
Subject: [PATCH 11/16] Added IR pre-decoding to improve timings

---
 fx68k.sv | 263 ++++++++++++++++++++++++++++---------------------------
 1 file changed, 132 insertions(+), 131 deletions(-)

diff --git a/fx68k.sv b/fx68k.sv
index 3799f8d..6617554 100644
--- a/fx68k.sv
+++ b/fx68k.sv
@@ -259,7 +259,17 @@ module fx68k
     wire [15:0] psw = { pswT, 1'b0, pswS, 2'b00, pswI, ccr };
 
     reg  [15:0] ftu;
-    reg  [15:0] Irc, Ir, Ird;
+    
+    reg  [15:0] Irc;
+    wire [15:0] IrcL;
+    
+    reg  [15:0] Ir;
+    reg  [15:0] IrL;
+    reg   [3:0] IrEA1;
+    reg   [3:0] IrEA2;
+    
+    reg  [15:0] Ird;
+    reg  [15:0] IrdL;
 
     wire [15:0] alue;
     wire [15:0] Abl;
@@ -268,17 +278,25 @@ module fx68k
     wire [UADDR_WIDTH-1:0] a1, a2, a3;
     wire isPriv, isIllegal, isLineA, isLineF;
 
+    onehotEncoder4 ircLineDecod(Irc[15:12], IrcL);
 
     // IR & IRD forwarding
+    // and some IR pre-decoding
     always_ff @(posedge clk) begin
 
         if (enT1) begin
             if (Nanod_w.Ir2Ird) begin
-                Ird <= Ir;
+                Ird   <= Ir;
+                IrdL  <= IrL;
             end
-            else if(microLatch[0]) begin
+            else if (microLatch[0]) begin
                 // prevented by IR => IRD !
-                Ir <= Irc;
+                Ir    <= Irc;
+                // Instruction groups pre-decoding
+                IrL   <= IrcL;
+                // Effective address pre-decoding
+                IrEA1 <= eaDecode(Irc[5:0]);
+                IrEA2 <= eaDecode({ Irc[8:6], Irc[11:9] });
             end
         end
     end
@@ -311,7 +329,10 @@ module fx68k
     uaddrDecode U_uaddrDecode
     (
         .opcode (Ir),
-        .a1, .a2, .a3, .isPriv, .isIllegal, .isLineA, .isLineF, .lineBmap()
+        .opline (IrL),
+        .ea1    (IrEA1),
+        .ea2    (IrEA2),
+        .a1, .a2, .a3, .isPriv, .isIllegal, .isLineA, .isLineF
     );
 
     sequencer sequencer( .clk, .Clks, .enT3, .microLatch, .Ird,
@@ -327,7 +348,7 @@ module fx68k
 
     nDecoder3 nDecoder( .clk, .Nanod_r, .Nanod_w, .Irdecod, .enT2, .enT4, .microLatch, .nanoLatch);
 
-    irdDecode irdDecode( .ird( Ird), .Irdecod);
+    irdDecode irdDecode( .Ird, .IrdL, .Irdecod);
 
     busControl busControl( .clk, .Clks, .enT1, .enT4, .permStart(Nanod_w.permStart), .permStop(Nanod_w.waitBusFinish), .iStop,
         .aob0, .isWrite(Nanod_w.isWrite), .isRmc(Nanod_r.isRmc), .isByte(busIsByte), .busAvail,
@@ -918,81 +939,75 @@ endmodule
 //
 module irdDecode
 (
-    input [15:0] ird,
+    input     [15:0] Ird,
+    input     [15:0] IrdL,
     output s_irdecod Irdecod
 );
 
-    wire [3:0] line = ird[15:12];
-    logic [15:0] lineOnehot;
-
-    // This can be registered and pipelined from the IR decoder !
-    onehotEncoder4 irdLines( line, lineOnehot);
-
     reg  implicitSp;
-    
-    wire isRegShift = (lineOnehot[4'hE]) & (ird[7:6] != 2'b11);
-    wire isDynShift = isRegShift & ird[5];
-    wire isTas      = (ird[11:6] == 6'b101011) ? lineOnehot[4'h4] : 1'b0;
+    wire isRegShift = (IrdL[4'hE]) & (Ird[7:6] != 2'b11);
+    wire isDynShift = isRegShift & Ird[5];
+    wire isTas      = (Ird[11:6] == 6'b101011) ? IrdL[4'h4] : 1'b0;
 
-    assign Irdecod.isPcRel = (& ird[ 5:3]) & ~isDynShift & !ird[2] & ird[1];
+    assign Irdecod.isPcRel = (&Ird[5:3]) & ~isDynShift & !Ird[2] & Ird[1];
     assign Irdecod.isTas   = isTas;
 
-    assign Irdecod.rx = ird[11:9];
-    assign Irdecod.ry = ird[ 2:0];
+    assign Irdecod.rx = Ird[11:9];
+    assign Irdecod.ry = Ird[ 2:0];
 
-    wire isPreDecr = (ird[5:3] == 3'b100) ? 1'b1 : 1'b0;
-    wire eaAreg    = (ird[5:3] == 3'b001) ? 1'b1 : 1'b0;
+    wire isPreDecr = (Ird[5:3] == 3'b100) ? 1'b1 : 1'b0;
+    wire eaAreg    = (Ird[5:3] == 3'b001) ? 1'b1 : 1'b0;
 
     // rx is A or D
     // movem
     always_comb begin
         unique case (1'b1)
-            lineOnehot[4'h1],
-            lineOnehot[4'h2],
-            lineOnehot[4'h3]:
+            IrdL[4'h1],
+            IrdL[4'h2],
+            IrdL[4'h3]:
                 // MOVE: RX always Areg except if dest mode is Dn 000
-                Irdecod.rxIsAreg = (|ird[8:6]);
+                Irdecod.rxIsAreg = (|Ird[8:6]);
 
-            lineOnehot[4'h4]:
+            IrdL[4'h4]:
                 // not CHK (LEA)
-                Irdecod.rxIsAreg = (&ird[8:6]);
+                Irdecod.rxIsAreg = (&Ird[8:6]);
 
-            lineOnehot[4'h8]:
+            IrdL[4'h8]:
                 // SBCD
-                Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7];
-                
-            lineOnehot[4'hC]:
+                Irdecod.rxIsAreg = eaAreg & Ird[8] & ~Ird[7];
+
+            IrdL[4'hC]:
                 // ABCD/EXG An,An
-                Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7];
+                Irdecod.rxIsAreg = eaAreg & Ird[8] & ~Ird[7];
 
-            lineOnehot[4'h9],
-            lineOnehot[4'hB],
-            lineOnehot[4'hD]:
+            IrdL[4'h9],
+            IrdL[4'hB],
+            IrdL[4'hD]:
                 Irdecod.rxIsAreg =
-                    (ird[7] & ird[6]) |                      // SUBA/CMPA/ADDA
-                    (eaAreg & ird[8] & (ird[7:6] != 2'b11)); // SUBX/CMPM/ADDX
+                    (Ird[7] & Ird[6]) |                      // SUBA/CMPA/ADDA
+                    (eaAreg & Ird[8] & (Ird[7:6] != 2'b11)); // SUBX/CMPM/ADDX
             default:
                 Irdecod.rxIsAreg = implicitSp;
         endcase
     end
 
     // RX is movem
-    assign Irdecod.rxIsMovem    = lineOnehot[4'h4] & ~ird[8] & ~implicitSp;
-    assign Irdecod.movemPreDecr = lineOnehot[4'h4] & ~ird[8] & ~implicitSp & isPreDecr;
+    assign Irdecod.rxIsMovem    = IrdL[4'h4] & ~Ird[8] & ~implicitSp;
+    assign Irdecod.movemPreDecr = IrdL[4'h4] & ~Ird[8] & ~implicitSp & isPreDecr;
 
     // RX is DT.
     // but SSP explicit or pc explicit has higher priority!
     // addq/subq (scc & dbcc also, but don't use rx)
     // Immediate including static bit
-    assign Irdecod.rxIsDt = lineOnehot[4'h5] | (lineOnehot[4'h0] & ~ird[8]);
+    assign Irdecod.rxIsDt = IrdL[4'h5] | (IrdL[4'h0] & ~Ird[8]);
 
-    // RX is USP
-    assign Irdecod.rxIsUsp = lineOnehot[4'h4] & (ird[11:4] == 8'hE6);
+    // RX is USP (16'h4E6x)
+    assign Irdecod.rxIsUsp = IrdL[4'h4] & (Ird[11:4] == 8'hE6);
 
     // RY is DT
     // rz or PC explicit has higher priority
 
-    wire eaImmOrAbs = (ird[5:3] == 3'b111) & ~ird[1];
+    wire eaImmOrAbs = (Ird[5:3] == 3'b111) & ~Ird[1];
     assign Irdecod.ryIsDt = eaImmOrAbs & ~isRegShift;
 
     // RY is Address register
@@ -1000,7 +1015,7 @@ module irdDecode
         logic eaIsAreg;
 
         // On most cases RY is Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL)
-        eaIsAreg = (ird[5:3] != 3'b000) & (ird[5:3] != 3'b111);
+        eaIsAreg = (Ird[5:3] != 3'b000) & (Ird[5:3] != 3'b111);
 
         unique case (1'b1)
             // MOVE: RY always Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL)
@@ -1008,15 +1023,15 @@ module irdDecode
             default:
                 Irdecod.ryIsAreg = eaIsAreg;
 
-            lineOnehot[4'h5]:
+            IrdL[4'h5]:
                 // DBcc is an exception
-                Irdecod.ryIsAreg = eaIsAreg & (ird[7:3] != 5'b11001);
+                Irdecod.ryIsAreg = eaIsAreg & (Ird[7:3] != 5'b11001);
 
-            lineOnehot[4'h6],
-            lineOnehot[4'h7]:
+            IrdL[4'h6],
+            IrdL[4'h7]:
                 Irdecod.ryIsAreg = 1'b0;
 
-            lineOnehot[4'hE]:
+            IrdL[4'hE]:
                 Irdecod.ryIsAreg = ~isRegShift;
         endcase
     end
@@ -1026,34 +1041,34 @@ module irdDecode
     // Original implementation sets this for some instructions that aren't really byte size
     // but doesn't matter because they don't have a byte transfer enabled at nanocode, such as MOVEQ
 
-    wire xIsScc = (ird[7:6] == 2'b11) & (ird[5:3] != 3'b001);
-    wire xStaticMem = (ird[11:8] == 4'b1000) & (ird[5:4] == 2'b00);     // Static bit to mem
+    wire xIsScc = (Ird[7:6] == 2'b11) & (Ird[5:3] != 3'b001);
+    wire xStaticMem = (Ird[11:8] == 4'b1000) & (Ird[5:4] == 2'b00);     // Static bit to mem
     always_comb begin
         unique case (1'b1)
-            lineOnehot[4'h0]:
+            IrdL[4'h0]:
                 Irdecod.isByte =
-                ( ird[8] & (ird[5:4] != 2'b00)                  ) | // Dynamic bit to mem
-                ( (ird[11:8] == 4'b1000) & (ird[5:4] != 2'b00)  ) | // Static bit to mem
-                ( (ird[8:7] == 2'b10) & (ird[5:3] == 3'b001)    ) | // Movep from mem only! For byte mux
-                ( (ird[8:6] == 3'b000) & !xStaticMem );             // Immediate byte
+                ( Ird[8] & (Ird[5:4] != 2'b00)                  ) | // Dynamic bit to mem
+                ( (Ird[11:8] == 4'b1000) & (Ird[5:4] != 2'b00)  ) | // Static bit to mem
+                ( (Ird[8:7] == 2'b10) & (Ird[5:3] == 3'b001)    ) | // Movep from mem only! For byte mux
+                ( (Ird[8:6] == 3'b000) & !xStaticMem );             // Immediate byte
 
-            lineOnehot[4'h1]:
+            IrdL[4'h1]:
                 Irdecod.isByte = 1'b1;      // MOVE.B
 
 
-            lineOnehot[4'h4]:
-                Irdecod.isByte = (ird[7:6] == 2'b00) | isTas;
+            IrdL[4'h4]:
+                Irdecod.isByte = (Ird[7:6] == 2'b00) ? 1'b1 : isTas;
 
-            lineOnehot[4'h5]:
-                Irdecod.isByte = (ird[7:6] == 2'b00) | xIsScc;
+            IrdL[4'h5]:
+                Irdecod.isByte = (Ird[7:6] == 2'b00) ? 1'b1 : xIsScc;
 
-            lineOnehot[4'h8],
-            lineOnehot[4'h9],
-            lineOnehot[4'hB],
-            lineOnehot[4'hC],
-            lineOnehot[4'hD],
-            lineOnehot[4'hE]:
-                Irdecod.isByte = (ird[7:6] == 2'b00);
+            IrdL[4'h8],
+            IrdL[4'h9],
+            IrdL[4'hB],
+            IrdL[4'hC],
+            IrdL[4'hD],
+            IrdL[4'hE]:
+                Irdecod.isByte = (Ird[7:6] == 2'b00) ? 1'b1 : 1'b0;
 
             default:
                 Irdecod.isByte = 1'b0;
@@ -1061,7 +1076,7 @@ module irdDecode
     end
 
     // Need it for special byte size. Bus is byte, but whole register word is modified.
-    assign Irdecod.isMovep = lineOnehot[4'h0] & ird[8] & eaAreg;
+    assign Irdecod.isMovep = IrdL[4'h0] & Ird[8] & eaAreg;
 
 
     // rxIsSP implicit use of RX for actual SP transfer
@@ -1071,12 +1086,12 @@ module irdDecode
 
     always_comb begin
         unique case (1'b1)
-            lineOnehot[6]:
+            IrdL[4'h6]:
                 // BSR
-                implicitSp = (ird[11:8] == 4'b0001);
-            lineOnehot[4]:
+                implicitSp = (Ird[11:8] == 4'b0001) ? 1'b1 : 1'b0;
+            IrdL[4'h4]:
                 // Misc like RTS, JSR, etc
-                implicitSp = (ird[11:8] == 4'b1110) | (ird[11:6] == 6'b1000_01);
+                implicitSp = (Ird[11:8] == 4'b1110) | (Ird[11:6] == 6'b1000_01);
             default:
                 implicitSp = 1'b0;
         endcase
@@ -1086,32 +1101,33 @@ module irdDecode
     // Modify CCR (and not SR)
     // Probably overkill !! Only needs to distinguish SR vs CCR
     // RTR, MOVE to CCR, xxxI to CCR
-    assign Irdecod.toCcr =  ( lineOnehot[4] & ((ird[11:0] == 12'he77) | (ird[11:6] == 6'b010011)) ) |
-                            ( lineOnehot[0] & (ird[8:6] == 3'b000));
+    assign Irdecod.toCcr =  ( IrdL[4'h4] & ((Ird[11:0] == 12'he77) | (Ird[11:6] == 6'b010011)) ) |
+                            ( IrdL[4'h0] & (Ird[8:6] == 3'b000));
 
     // FTU constants
     // This should not be latched on T3/T4. Latch on T2 or not at all. FTU needs it on next T3.
     // Note: Reset instruction gets constant from ALU not from FTU!
     logic [15:0] ftuConst;
-    wire [3:0] zero28 = (ird[11:9] == 0) ? 4'h8 : { 1'b0, ird[11:9]};       // xltate 0,1-7 into 8,1-7
+    wire [3:0] zero28 = (Ird[11:9] == 0) ? 4'h8 : { 1'b0, Ird[11:9]};       // xltate 0,1-7 into 8,1-7
 
     always_comb begin
         unique case (1'b1)
-            lineOnehot[4'h6], // Bcc short
-            lineOnehot[4'h7]: // MOVEQ
-                ftuConst = { {8{ird[7]}}, ird[7:0] };
+            IrdL[4'h6], // Bcc short
+            IrdL[4'h7]: // MOVEQ
+                ftuConst = { {8{Ird[7]}}, Ird[7:0] };
 
             // ADDQ/SUBQ/static shift double check this
-            lineOnehot[4'h5],
-            lineOnehot[4'hE]:
+            IrdL[4'h5],
+            IrdL[4'hE]:
                 ftuConst = { 12'h000, zero28};
 
             // MULU/MULS DIVU/DIVS
-            lineOnehot[4'h8],
-            lineOnehot[4'hC]:
+            IrdL[4'h8],
+            IrdL[4'hC]:
                 ftuConst = 16'h000F;
-
-            lineOnehot[4'h4]: // TAS
+
+            // TAS
+            IrdL[4'h4]:
                 ftuConst = 16'h0080;
 
             default:
@@ -1125,15 +1141,15 @@ module irdDecode
     //
 
     always_comb begin
-        if (lineOnehot[4'h4]) begin
-            case (ird[6:5])
+        if (IrdL[4'h4]) begin
+            case (Ird[6:5])
                 2'b00,
                 2'b01:
                     Irdecod.macroTvn = 6'h6;                // CHK
                 2'b11:
                     Irdecod.macroTvn = 6'h7;                // TRAPV
                 2'b10:
-                    Irdecod.macroTvn = { 2'b10, ird[3:0] }; // TRAP
+                    Irdecod.macroTvn = { 2'b10, Ird[3:0] }; // TRAP
             endcase
         end
         else begin
@@ -1142,16 +1158,16 @@ module irdDecode
     end
 
 
-    wire eaAdir = (ird[ 5:3] == 3'b001);
-    wire size11 = ird[7] & ird[6];
+    wire eaAdir = (Ird[ 5:3] == 3'b001);
+    wire size11 = Ird[7] & Ird[6];
 
     // Opcodes variants that don't affect flags
     // ADDA/SUBA ADDQ/SUBQ MOVEA
 
     assign Irdecod.inhibitCcr =
-        ( (lineOnehot[9] | lineOnehot['hd]) & size11) |             // ADDA/SUBA
-        ( lineOnehot[5] & eaAdir) |                                 // ADDQ/SUBQ to An (originally checks for line[4] as well !?)
-        ( (lineOnehot[2] | lineOnehot[3]) & ird[8:6] == 3'b001);    // MOVEA
+        ( (IrdL[4'h9] | IrdL[4'hD]) & size11) |            // ADDA/SUBA
+        ( IrdL[4'h5] & eaAdir) |                           // ADDQ/SUBQ to An (originally checks for line[4] as well !?)
+        ( (IrdL[4'h2] | IrdL[4'h3]) & Ird[8:6] == 3'b001); // MOVEA
 
 endmodule
 
@@ -1855,40 +1871,30 @@ endmodule
 module uaddrDecode
 (
     input             [15:0] opcode,
+    input             [15:0] opline,
+    input              [3:0] ea1,
+    input              [3:0] ea2,
     output [UADDR_WIDTH-1:0] a1,
     output [UADDR_WIDTH-1:0] a2,
     output [UADDR_WIDTH-1:0] a3,
     output logic             isPriv,
     output logic             isIllegal,
     output logic             isLineA,
-    output logic             isLineF,
-    output            [15:0] lineBmap
+    output logic             isLineF
 );
 
-    wire [3:0] line = opcode[15:12];
-    logic [3:0] eaCol, movEa;
-
-    onehotEncoder4 irLineDecod( line, lineBmap);
-
-    assign isLineA = lineBmap[ 'hA];
-    assign isLineF = lineBmap[ 'hF];
-
     uaddrPla U_uaddrPla
     (
-        .movEa    (movEa),
-        .col      (eaCol),
+        .movEa    (ea2),
+        .col      (ea1),
         .opcode   (opcode),
-        .lineBmap (lineBmap),
+        .lineBmap (opline),
         .palIll   (isIllegal),
         .plaA1    (a1),
         .plaA2    (a2),
         .plaA3    (a3)
     );
 
-    // ea decoding
-    assign eaCol = eaDecode( opcode[ 5:0]);
-    assign movEa = eaDecode( {opcode[ 8:6], opcode[ 11:9]} );
-
     /*
     Privileged instructions:
 
@@ -1901,32 +1907,27 @@ module uaddrDecode
     */
 
     always_comb begin
-        unique case (lineBmap)
+        unique case (1'b1)
 
-        // ori/andi/eori SR
-        'h01:   isPriv = ((opcode & 16'hf5ff) == 16'h007c);
-
-        'h10:
-            begin
-            // No priority !!!
-                if ((opcode & 16'hffc0) == 16'h46c0)        // move to sr
-                    isPriv = 1'b1;
+            // ANDI/EORI/ORI SR
+            opline[0]:
+                isPriv = ((opcode[11:0] & 12'h5FF) == 12'h07C) ? 1'b1 : 1'b0;
 
-                else if ((opcode & 16'hfff0) == 16'h4e60)   // move usp
-                    isPriv = 1'b1;
+            opline[4]:
+                isPriv = ((opcode[11:0] & 12'hFC0) == 12'h6C0) // MOVE to SR
+                      || ((opcode[11:0] & 12'hFF0) == 12'hE60) // MOVE to/from USP
+                      || ((opcode[11:0] & 12'hFFF) == 12'hE70) // RESET
+                      || ((opcode[11:0] & 12'hFFF) == 12'hE72) // STOP
+                      || ((opcode[11:0] & 12'hFFF) == 12'hE73) // RTE
+                      ? 1'b1 : 1'b0;
 
-                else if (   opcode == 16'h4e70 ||           // reset
-                            opcode == 16'h4e73 ||           // rte
-                            opcode == 16'h4e72)             // stop
-                    isPriv = 1'b1;
-                else
-                    isPriv = 1'b0;
-            end
-
-        default:   isPriv = 1'b0;
+            default:
+                isPriv = 1'b0;
         endcase
     end
 
+    assign isLineA = opline[4'hA];
+    assign isLineF = opline[4'hF];
 
 endmodule
 

From 320730179bfebbb35ea58301dcab61ed9678e641 Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Sat, 29 Aug 2020 17:38:50 +0200
Subject: [PATCH 12/16] Added a separate latch for BCD operation

Some renaming : Subber => Adder
---
 fx68kAlu.sv | 36 +++++++++++++++++++-----------------
 1 file changed, 19 insertions(+), 17 deletions(-)

diff --git a/fx68kAlu.sv b/fx68kAlu.sv
index bfaf2b6..07b6d81 100644
--- a/fx68kAlu.sv
+++ b/fx68kAlu.sv
@@ -77,6 +77,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     localparam CF = 0, VF = 1, ZF = 2, NF = 3, XF = 4;
 
     reg [15:0] aluLatch;
+    reg  [7:0] addLatch;
     reg [4:0] pswCcr;
     reg [4:0] ccrCore;
 
@@ -84,9 +85,9 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     logic [4:0] ccrTemp;
     reg coreH;      // half carry latch
 
-    logic [15:0] subResult;
-    logic subHcarry;
-    logic subCout, subOv;
+    logic [15:0] addResult;
+    logic addHcarry;
+    logic addCout, addOv;
 
     assign aluOut = aluLatch;
     assign ze = ~ccrCore[ ZF];      // Check polarity !!!
@@ -134,7 +135,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     logic shftCin, shftRight, addCin;
 
     // Register some decoded signals
-    always_ff @( posedge clk) begin
+    always_ff @(posedge clk) begin
     
         if (enT3) begin
             row     <= cRow;
@@ -185,7 +186,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     wire bcdC, bcdV;
     aluCorf aluCorf
     (
-        .binResult (aluLatch[7:0]),
+        .binResult (addLatch),
         .hCarry    (coreH),
         .bAdd      (~oper[0]),
         .cin       (pswCcr[XF]),
@@ -249,8 +250,8 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     always_comb begin
 
         // sub is DATA - ADDR
-        mySubber( aOperand, dOperand, addCin, ~oper[0],
-            isByte, subResult, subCout, subOv);
+        myAdder( aOperand, dOperand, addCin, ~oper[0],
+            isByte, addResult, addCout, addOv);
 
         isShift = oper[4];
         
@@ -277,7 +278,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
             OP_ADDX,
             OP_SUBX:
             begin
-                result = subResult;
+                result = addResult;
             end
             
             //OP_ASL,
@@ -296,9 +297,9 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
         endcase
     end
 
-    task mySubber;
+    task myAdder;
         input [15:0] inpa, inpb;
-        input cin, bAdd, isByte;
+        input cin, bSub, isByte;
         output reg [15:0] result;
         output cout, ov;
 
@@ -308,7 +309,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
 
         begin
             rtemp = { 1'b0, inpb, cin }
-                  + { 1'b0, inpa ^ {16{~bAdd}}, cin };
+                  + { 1'b0, inpa ^ {16{bSub}}, cin };
             if (isByte)
             begin
                 result = { {8{ rtemp[8]}}, rtemp[8:1] };
@@ -322,12 +323,12 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
             rm  = isByte ? rtemp[8] : rtemp[16];
             dm  = isByte ? inpb[ 7] : inpb[ 15];
             tsm = isByte ? inpa[ 7] : inpa[ 15];
-            sm  = bAdd ? tsm : ~tsm;
+            sm  = bSub ? ~tsm : tsm;
 
             ov = (sm & dm & ~rm) | (~sm & ~dm & rm);
 
             // Store half carry for bcd correction
-            subHcarry = inpa[4] ^ inpb[4] ^ rtemp[5];
+            addHcarry = inpa[4] ^ inpb[4] ^ rtemp[5];
         end
     endtask
 
@@ -394,9 +395,9 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
             OP_SUBC,
             OP_SUBX:
             begin
-                ccrTemp[CF] = subCout;
-                ccrTemp[XF] = subCout;
-                ccrTemp[VF] = subOv;
+                ccrTemp[CF] = addCout;
+                ccrTemp[XF] = addCout;
+                ccrTemp[VF] = addOv;
             end
 
             OP_LSL,
@@ -477,8 +478,9 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
             // Update latches from ALU operators
             if ((| aluColumn)) begin
                 aluLatch <= result;
+                addLatch <= addResult[7:0];
 
-                coreH <= subHcarry;
+                coreH <= addHcarry;
 
                 // Update CCR core
                 if ((| aluColumn))

From babe2905d9e74fe1fe233e43cbcb03b66b04fc5b Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Mon, 31 Aug 2020 00:08:16 +0200
Subject: [PATCH 13/16] Fixed dumb error in Adder logic

---
 fx68kAlu.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fx68kAlu.sv b/fx68kAlu.sv
index 07b6d81..d846158 100644
--- a/fx68kAlu.sv
+++ b/fx68kAlu.sv
@@ -250,7 +250,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     always_comb begin
 
         // sub is DATA - ADDR
-        myAdder( aOperand, dOperand, addCin, ~oper[0],
+        myAdder( aOperand, dOperand, addCin, oper[0],
             isByte, addResult, addCout, addOv);
 
         isShift = oper[4];

From c5d838cc04d1393f0ceeb723e6efc0b1cb38304a Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Mon, 31 Aug 2020 14:53:02 +0200
Subject: [PATCH 14/16] Lot of signals renaming and 68k registers read/write
 improvement

---
 fx68k.sv     | 1342 +++++++++++++++++++++++++++-----------------------
 fx68kAlu.sv  |  132 ++---
 fx68k_pkg.sv |   40 +-
 uaddrPla.sv  |    4 +-
 4 files changed, 819 insertions(+), 699 deletions(-)

diff --git a/fx68k.sv b/fx68k.sv
index 6617554..304861d 100644
--- a/fx68k.sv
+++ b/fx68k.sv
@@ -192,61 +192,82 @@ module fx68k
     end
 
     // Instantiate micro and nano rom
-    logic  [NANO_WIDTH-1:0] nanoLatch;
-    logic  [NANO_WIDTH-1:0] nanoOutput;
-    logic  [UROM_WIDTH-1:0] microLatch;
-    logic  [UROM_WIDTH-1:0] microOutput;
-
-    logic [UADDR_WIDTH-1:0] microAddr, nma;
-    logic [NADDR_WIDTH-1:0] nanoAddr, orgAddr;
-    wire rstUrom;
+    reg  [NANO_WIDTH-1:0] rNanoLatch_t3;
+    wire [NANO_WIDTH-1:0] wNanoOutput;
+    reg  [UROM_WIDTH-1:0] rMicroLatch_t3;
+    wire [UROM_WIDTH-1:0] wMicroOutput;
+
+    reg  [UADDR_WIDTH-1:0] rMicroAddr_t1;
+    wire [UADDR_WIDTH-1:0] wMicroAddr;
+    reg  [NADDR_WIDTH-1:0] rNanoAddr_t1;
+    wire [NADDR_WIDTH-1:0] wNanoAddr;
+    
+    // Reset micro/nano latch after T4 of the current ublock.
+    wire                   wRstUrom = Clks.enPhi1 & enErrClk;
 
     // For the time being, address translation is done for nanorom only.
-    microToNanoAddr microToNanoAddr( .uAddr( nma), .orgAddr);
+    microToNanoAddr microToNanoAddr
+    (
+        .uAddr   (wMicroAddr),
+        .orgAddr (wNanoAddr)
+    );
 
     // Output of these modules will be updated at T2 at the latest (depending on clock division)
-
-    nanoRom nanoRom( .clk(clk), .nanoAddr, .nanoOutput);
-    uRom uRom( .clk(clk), .microAddr, .microOutput);
+    nanoRom U_nanoRom
+    (
+        .clk         (clk),
+        .nanoAddr    (rNanoAddr_t1),
+        .nanoOutput  (wNanoOutput)
+    );
+    
+    uRom U_microRom
+    (
+        .clk         (clk),
+        .microAddr   (rMicroAddr_t1),
+        .microOutput (wMicroOutput)
+    );
 
-    always_ff @(posedge clk) begin
+    always_ff @(posedge clk) begin : ROM_ADDR_T1
         // uaddr originally latched on T1, except bits 6 & 7, the conditional bits, on T2
         // Seems we can latch whole address at either T1 or T2
 
         // Originally it's invalid on hardware reset, and forced later when coming out of reset
         if (Clks.pwrUp) begin
-            microAddr <= RSTP0_NMA[UADDR_WIDTH-1:0];
-            nanoAddr  <= RSTP0_NMA[NADDR_WIDTH-1:0];
+            rMicroAddr_t1 <= RSTP0_NMA[UADDR_WIDTH-1:0];
+            rNanoAddr_t1  <= RSTP0_NMA[NADDR_WIDTH-1:0];
         end
         else if (enT1) begin
-            microAddr <= nma;
-            nanoAddr  <= orgAddr;                // Register translated uaddr to naddr
+            rMicroAddr_t1 <= wMicroAddr;
+            rNanoAddr_t1  <= wNanoAddr;                // Register translated uaddr to naddr
         end
+    end
 
+    always_ff @(posedge clk) begin : ROM_DATA_T3
+    
         if (Clks.extReset) begin
-            microLatch <= {UROM_WIDTH{1'b0}};
-            nanoLatch  <= {NANO_WIDTH{1'b0}};
+            rMicroLatch_t3 <= {UROM_WIDTH{1'b0}};
+            rNanoLatch_t3  <= {NANO_WIDTH{1'b0}};
         end
-        else if (rstUrom) begin
+        else if (wRstUrom) begin
             // Originally reset these bits only. Not strictly needed like this.
             // Can reset the whole register if it is important.
-            microLatch[16] <= 1'b0;
-            microLatch[15] <= 1'b0;
-            microLatch[0]  <= 1'b0;
-            nanoLatch      <= {NANO_WIDTH{1'b0}};
+            rMicroLatch_t3[16] <= 1'b0;
+            rMicroLatch_t3[15] <= 1'b0;
+            rMicroLatch_t3[0]  <= 1'b0;
+            rNanoLatch_t3      <= {NANO_WIDTH{1'b0}};
         end
         else if (enT3) begin
-            microLatch <= microOutput;
-            nanoLatch  <= nanoOutput;
+            rMicroLatch_t3 <= wMicroOutput;
+            rNanoLatch_t3  <= wNanoOutput;
         end
     end
 
 
     // Decoded nanocode signals
-    s_nanod_r Nanod_r;
-    s_nanod_w Nanod_w;
+    s_nanod_r wNanoDec_t4;
+    s_nanod_w wNanoDec_t3;
     // IRD decoded control signals
-    s_irdecod Irdecod;
+    s_irdecod wIrdDecode_t1;
 
     //
     reg         Tpend;
@@ -258,48 +279,66 @@ module fx68k
 
     wire [15:0] psw = { pswT, 1'b0, pswS, 2'b00, pswI, ccr };
 
-    reg  [15:0] ftu;
+    reg  [15:0] rFtu_t3;
     
-    reg  [15:0] Irc;
-    wire [15:0] IrcL;
+    wire [15:0] wIrc_t4;
+    wire [15:0] wIrcL_t4;
     
-    reg  [15:0] Ir;
-    reg  [15:0] IrL;
-    reg   [3:0] IrEA1;
-    reg   [3:0] IrEA2;
+    reg  [15:0] rIr_t1;
+    reg  [15:0] rIrL_t1;
+    reg   [3:0] rIrEA1_t1;
+    reg   [3:0] rIrEA2_t1;
     
-    reg  [15:0] Ird;
-    reg  [15:0] IrdL;
+    reg  [15:0] rIrd_t1;
+    reg  [15:0] rIrdL_t1;
 
     wire [15:0] alue;
-    wire [15:0] Abl;
+    wire [15:0] wAbl_t2;
     wire prenEmpty, au05z, dcr4, ze;
 
-    wire [UADDR_WIDTH-1:0] a1, a2, a3;
-    wire isPriv, isIllegal, isLineA, isLineF;
-
-    onehotEncoder4 ircLineDecod(Irc[15:12], IrcL);
+    onehotEncoder4 U_IrcLine_T4(wIrc_t4[15:12], wIrcL_t4);
 
     // IR & IRD forwarding
     // and some IR pre-decoding
-    always_ff @(posedge clk) begin
+    always_ff @(posedge clk) begin : IR_IRD_T1
 
         if (enT1) begin
-            if (Nanod_w.Ir2Ird) begin
-                Ird   <= Ir;
-                IrdL  <= IrL;
+            if (wNanoDec_t3.Ir2Ird) begin
+                rIrd_t1   <= rIr_t1;
+                rIrdL_t1  <= rIrL_t1;
             end
-            else if (microLatch[0]) begin
+            else if (rMicroLatch_t3[0]) begin
                 // prevented by IR => IRD !
-                Ir    <= Irc;
+                rIr_t1    <= wIrc_t4;
                 // Instruction groups pre-decoding
-                IrL   <= IrcL;
+                rIrL_t1   <= wIrcL_t4;
                 // Effective address pre-decoding
-                IrEA1 <= eaDecode(Irc[5:0]);
-                IrEA2 <= eaDecode({ Irc[8:6], Irc[11:9] });
+                rIrEA1_t1 <= eaDecode(wIrc_t4[5:0]);
+                rIrEA2_t1 <= eaDecode({ wIrc_t4[8:6], wIrc_t4[11:9] });
             end
         end
     end
+    
+    wire [UADDR_WIDTH-1:0] wPlaA1_t1;
+    wire [UADDR_WIDTH-1:0] wPlaA2_t1;
+    wire [UADDR_WIDTH-1:0] wPlaA3_t1;
+    wire                   wIsPriv_t1;
+    wire                   wIsIllegal_t1;
+    wire                   wIsLineA_t1 = rIrL_t1[4'hA];
+    wire                   wIsLineF_t1 = rIrL_t1[4'hF];
+
+    uaddrDecode U_uaddrDecode_T1
+    (
+        .iOpCode_t1    (rIr_t1),
+        .iOpLine_t1    (rIrL_t1),
+        .iEA1_t1       (rIrEA1_t1),
+        .iEA2_t1       (rIrEA2_t1),
+        .oPlaA1_t1     (wPlaA1_t1),
+        .oPlaA2_t1     (wPlaA2_t1),
+        .oPlaA3_t1     (wPlaA3_t1),
+        .oIsPriv_t1    (wIsPriv_t1),
+        .oIsIllegal_t1 (wIsIllegal_t1)
+    );
 
     wire [3:0] tvn;
     wire waitBusCycle, busStarting;
@@ -309,7 +348,7 @@ module fx68k
     wire bgBlock, busAvail;
     wire addrOe;
 
-    wire busIsByte = Nanod_w.busByte & (Irdecod.isByte | Irdecod.isMovep);
+    wire busIsByte = wNanoDec_t3.busByte & (wIrdDecode_t1.isByte | wIrdDecode_t1.isMovep);
     wire aob0;
 
     reg iStop;                              // Internal signal for ending bus cycle
@@ -323,35 +362,65 @@ module fx68k
     wire iAddrErr = rAddrErr & addrOe;      // To simulate async reset
     wire enErrClk;
 
-    // Reset micro/nano latch after T4 of the current ublock.
-    assign rstUrom = Clks.enPhi1 & enErrClk;
-
-    uaddrDecode U_uaddrDecode
+    sequencer sequencer
     (
-        .opcode (Ir),
-        .opline (IrL),
-        .ea1    (IrEA1),
-        .ea2    (IrEA2),
-        .a1, .a2, .a3, .isPriv, .isIllegal, .isLineA, .isLineF
+        .clk,
+        .Clks,
+        .enT3,
+        .iMicroLatch_t3 (rMicroLatch_t3),
+        .Ird        (rIrd_t1),
+        .A0Err, .excRst, .BerrA, .busAddrErr, .Spuria, .Avia,
+        .Tpend, .intPend,
+        .isIllegal (wIsIllegal_t1),
+        .isPriv    (wIsPriv_t1),
+        .isLineA   (wIsLineA_t1),
+        .isLineF   (wIsLineF_t1),
+        .nma       (wMicroAddr),
+        .a1        (wPlaA1_t1),
+        .a2        (wPlaA2_t1),
+        .a3        (wPlaA3_t1),
+        .tvn,
+        .psw, .prenEmpty, .au05z, .dcr4, .ze, .alue01( alue[1:0]), .i11(wIrc_t4[11])
     );
 
-    sequencer sequencer( .clk, .Clks, .enT3, .microLatch, .Ird,
-        .A0Err, .excRst, .BerrA, .busAddrErr, .Spuria, .Avia,
-        .Tpend, .intPend, .isIllegal, .isPriv, .isLineA, .isLineF,
-        .nma, .a1, .a2, .a3, .tvn,
-        .psw, .prenEmpty, .au05z, .dcr4, .ze, .alue01( alue[1:0]), .i11( Irc[ 11]) );
-
-    excUnit excUnit( .clk, .Clks, .Nanod_r, .Nanod_w, .Irdecod, .enT1, .enT2, .enT3, .enT4,
-        .Ird, .ftu, .iEdb, .pswS,
-        .prenEmpty, .au05z, .dcr4, .ze, .AblOut( Abl), .eab, .aob0, .Irc, .oEdb,
+    excUnit excUnit
+    (
+        .clk,
+        .Clks,
+        .enT1, .enT2, .enT3, .enT4,
+        .iNanoDec_t4 (wNanoDec_t4),
+        .iNanoDec_t3 (wNanoDec_t3),
+        .Irdecod     (wIrdDecode_t1),
+        .Ird         (rIrd_t1),
+        .iFtu_t3     (rFtu_t3), 
+        .iEdb, .pswS,
+        .prenEmpty, .au05z, .dcr4, .ze,
+        .oAbl_t2     (wAbl_t2),
+        .eab, .aob0,
+        .oIrc_t4 (wIrc_t4),
+        .oEdb,
         .alue, .ccr);
 
-    nDecoder3 nDecoder( .clk, .Nanod_r, .Nanod_w, .Irdecod, .enT2, .enT4, .microLatch, .nanoLatch);
+    nDecoder3 nDecoder
+    (
+        .clk,
+        .enT2,
+        .enT4,
+        .iNanoLatch_t3 (rNanoLatch_t3),
+        .iIrdDecode_t1 (wIrdDecode_t1),
+        .oNanoDec_t4   (wNanoDec_t4),
+        .oNanoDec_t3   (wNanoDec_t3)
+    );
 
-    irdDecode irdDecode( .Ird, .IrdL, .Irdecod);
+    irdDecode U_irdDecode_T1
+    (
+        .iIrd_t1       (rIrd_t1),
+        .iIrdL_t1      (rIrdL_t1),
+        .oIrdDecode_t1 (wIrdDecode_t1)
+    );
 
-    busControl busControl( .clk, .Clks, .enT1, .enT4, .permStart(Nanod_w.permStart), .permStop(Nanod_w.waitBusFinish), .iStop,
-        .aob0, .isWrite(Nanod_w.isWrite), .isRmc(Nanod_r.isRmc), .isByte(busIsByte), .busAvail,
+    busControl busControl( .clk, .Clks, .enT1, .enT4, .permStart(wNanoDec_t3.permStart), .permStop(wNanoDec_t3.waitBusFinish), .iStop,
+        .aob0, .isWrite(wNanoDec_t3.isWrite), .isRmc(wNanoDec_t4.isRmc), .isByte(busIsByte), .busAvail,
         .bciWrite, .addrOe, .bgBlock, .waitBusCycle, .busStarting, .busAddrErr,
         .rDtack, .BeDebounced, .Vpai,
         .ASn, .LDSn, .UDSn, .eRWn);
@@ -360,7 +429,7 @@ module fx68k
 
 
     // Output reset & halt control
-    wire [1:0] uFc = microLatch[16:15];
+    wire [1:0] uFc = rMicroLatch_t3[16:15];
     logic oReset, oHalted;
     assign oRESETn = !oReset;
     assign oHALTEDn = !oHalted;
@@ -373,8 +442,8 @@ module fx68k
             oHalted <= 1'b0;
         end
         else if (enT1) begin
-            oReset  <= (uFc == 2'b01) ? ~Nanod_w.permStart : 1'b0;
-            oHalted <= (uFc == 2'b10) ? ~Nanod_w.permStart : 1'b0;
+            oReset  <= (uFc == 2'b01) ? ~wNanoDec_t3.permStart : 1'b0;
+            oHalted <= (uFc == 2'b10) ? ~wNanoDec_t3.permStart : 1'b0;
         end
     end
 
@@ -387,12 +456,12 @@ module fx68k
         if (Clks.extReset) begin
             rFC <= 3'b000;
         end
-        else if (enT1 & Nanod_w.permStart) begin      // S0 phase of bus cycle
+        else if (enT1 & wNanoDec_t3.permStart) begin      // S0 phase of bus cycle
             rFC[2] <= pswS;
             // If FC is type 'n' (0) at ucode, access type depends on PC relative mode
             // We don't care about RZ in this case. Those uinstructions with RZ don't start a bus cycle.
-            rFC[1] <= microLatch[ 16] | ( ~microLatch[ 15] &  Irdecod.isPcRel);
-            rFC[0] <= microLatch[ 15] | ( ~microLatch[ 16] & ~Irdecod.isPcRel);
+            rFC[1] <= rMicroLatch_t3[ 16] | ( ~rMicroLatch_t3[ 15] &  wIrdDecode_t1.isPcRel);
+            rFC[0] <= rMicroLatch_t3[ 15] | ( ~rMicroLatch_t3[ 16] & ~wIrdDecode_t1.isPcRel);
         end
     end
 
@@ -439,7 +508,7 @@ module fx68k
             updIll <= 1'b0;
         end
         else if (enT4)
-            updIll <= microLatch[0];        // Update on any IRC->IR
+            updIll <= rMicroLatch_t3[0];        // Update on any IRC->IR
         else if (enT1 & updIll)
             inl <= iIpl;                    // Timing is correct.
 
@@ -525,7 +594,7 @@ module fx68k
         // Originally cleared on 1st T2 after permstart. Must keep it until TVN latched.
         if (Clks.extReset)
             excRst <= 1'b1;
-        else if (enT2 & Nanod_w.permStart)
+        else if (enT2 & wNanoDec_t3.permStart)
             excRst <= 1'b0;
 
         if (Clks.extReset)
@@ -556,27 +625,27 @@ module fx68k
         end
 
         else if (enT4) begin
-            irdToCcr_t4 <= Irdecod.toCcr;
+            irdToCcr_t4 <= wIrdDecode_t1.toCcr;
         end
 
         else if (enT3) begin
 
             // UNIQUE IF !!
-            if (Nanod_w.updTpend)
+            if (wNanoDec_t4.updTpend)
                 Tpend <= pswT;
-            else if (Nanod_w.clrTpend)
+            else if (wNanoDec_t4.clrTpend)
                 Tpend <= 1'b0;
 
             // UNIQUE IF !!
-            if (Nanod_w.ftu2Sr & !irdToCcr_t4) begin
-                { pswT, pswS, pswI } <= { ftu[15], ftu[13], ftu[10:8]};
+            if (wNanoDec_t4.ftu2Sr & !irdToCcr_t4) begin
+                { pswT, pswS, pswI } <= { rFtu_t3[15], rFtu_t3[13], rFtu_t3[10:8]};
             end
             else begin
-                if (Nanod_w.initST) begin
+                if (wNanoDec_t4.initST) begin
                     pswS <= 1'b1;
                     pswT <= 1'b0;
                 end
-                if (Nanod_w.inl2psw) begin
+                if (wNanoDec_t4.inl2psw) begin
                     pswI <= inl;
                 end
             end
@@ -596,32 +665,32 @@ module fx68k
     always_ff @(posedge clk) begin
 
         // Updated at the start of the exception ucode
-        if (Nanod_w.updSsw & enT3) begin
+        if (wNanoDec_t3.updSsw & enT3) begin
             ssw <= { ~bciWrite, inExcept01, rFC};
         end
 
         // Update TVN on T1 & IR=>IRD
-        if (enT1 & Nanod_w.Ir2Ird) begin
+        if (enT1 & wNanoDec_t3.Ir2Ird) begin
             tvnLatch <= tvn;
             inExcept01 <= (tvn != 4'h1);
         end
 
         if (Clks.pwrUp) begin
-            ftu <= 16'h0000;
+            rFtu_t3 <= 16'h0000;
         end
         else if (enT3) begin
             unique case (1'b1)
-                Nanod_w.tvn2Ftu:   ftu <= tvnMux;
+                wNanoDec_t4.tvn2Ftu:   rFtu_t3 <= tvnMux;
 
                 // 0 on unused bits seem to come from ftuConst PLA previously clearing FBUS
-                Nanod_w.sr2Ftu:    ftu <= {pswT, 1'b0, pswS, 2'b00, pswI, 3'b000, ccr[4:0] };
-
-                Nanod_w.ird2Ftu:   ftu <= Ird;
-                Nanod_w.ssw2Ftu:   ftu[4:0] <= ssw;                        // Undoc. Other bits must be preserved from IRD saved above!
-                Nanod_w.pswIToFtu: ftu <= { 12'hFFF, pswI, 1'b0};          // Interrupt level shifted
-                Nanod_w.const2Ftu: ftu <= Irdecod.ftuConst;
-                Nanod_w.abl2Pren:  ftu <= Abl;                             // From ALU or datareg. Used for SR modify
-                default:           ftu <= ftu;
+                wNanoDec_t4.sr2Ftu:    rFtu_t3 <= {pswT, 1'b0, pswS, 2'b00, pswI, 3'b000, ccr[4:0] };
+
+                wNanoDec_t4.ird2Ftu:   rFtu_t3 <= rIrd_t1;
+                wNanoDec_t4.ssw2Ftu:   rFtu_t3[4:0] <= ssw;               // Undoc. Other bits must be preserved from IRD saved above!
+                wNanoDec_t4.pswIToFtu: rFtu_t3 <= { 12'hFFF, pswI, 1'b0}; // Interrupt level shifted
+                wNanoDec_t4.const2Ftu: rFtu_t3 <= wIrdDecode_t1.ftuConst;
+                wNanoDec_t4.abl2Pren:  rFtu_t3 <= wAbl_t2;                    // From ALU or datareg. Used for SR modify
+                default:               rFtu_t3 <= rFtu_t3;
             endcase
         end
     end
@@ -635,12 +704,12 @@ module fx68k
             else if (tvnLatch == TVN_AUTOVEC)
                 tvnMux = { 9'b0, 2'b11, pswI, 2'b0 };                // Set TVN PLA decoder
             else if (tvnLatch == TVN_INTERRUPT)
-                tvnMux = { 6'b0, Ird[7:0], 2'b0 };                   // Interrupt vector was read and transferred to IRD
+                tvnMux = { 6'b0, rIrd_t1[7:0], 2'b0 };               // Interrupt vector was read and transferred to IRD
             else
                 tvnMux = { 10'b0, tvnLatch, 2'b0 };
         end
         else begin
-            tvnMux = { 8'h0, Irdecod.macroTvn, 2'b0 };
+            tvnMux = { 8'h0, wIrdDecode_t1.macroTvn, 2'b0 };
         end
     end
 
@@ -652,11 +721,10 @@ module nDecoder3
     input                   clk,
     input                   enT2,
     input                   enT4,
-    input  [UROM_WIDTH-1:0] microLatch,
-    input  [NANO_WIDTH-1:0] nanoLatch,
-    input                   s_irdecod Irdecod,
-    output                  s_nanod_r Nanod_r,
-    output                  s_nanod_w Nanod_w
+    input  [NANO_WIDTH-1:0] iNanoLatch_t3,
+    input         s_irdecod iIrdDecode_t1,
+    output        s_nanod_r oNanoDec_t4,
+    output        s_nanod_w oNanoDec_t3
 );
 
 localparam
@@ -729,173 +797,178 @@ localparam [3:0]
     NANO_FTU_2SR      = 4'b0100,
     NANO_FTU_CONST    = 4'b1000;
 
-    reg [3:0] ftuCtrl;
-
-    wire [2:0] athCtrl = nanoLatch[NANO_ATHCTRL +: 3];
-    wire [2:0] atlCtrl = nanoLatch[NANO_ATLCTRL +: 3];
-    wire [1:0] aobCtrl = nanoLatch[NANO_AOBCTRL +: 2];
-    wire [1:0] dobCtrl = { nanoLatch[ NANO_DOBCTRL_1], nanoLatch[NANO_DOBCTRL_0] };
+    wire [3:0] ftuCtrl = iNanoLatch_t3[NANO_FTUCONTROL +: 4];
+    wire [2:0] athCtrl = iNanoLatch_t3[NANO_ATHCTRL +: 3];
+    wire [2:0] atlCtrl = iNanoLatch_t3[NANO_ATLCTRL +: 3];
+    wire [1:0] aobCtrl = iNanoLatch_t3[NANO_AOBCTRL +: 2];
+    wire [1:0] dobCtrl = { iNanoLatch_t3[NANO_DOBCTRL_1], iNanoLatch_t3[NANO_DOBCTRL_0] };
 
     always_ff @(posedge clk) begin
 
         if (enT4) begin
 
-            ftuCtrl           <= nanoLatch[NANO_FTUCONTROL +: 4];
-
-            Nanod_r.auClkEn   <= ~nanoLatch[NANO_AUCLKEN];
-            Nanod_r.auCntrl   <=  nanoLatch[NANO_AUCTRL +: 3];
-            Nanod_r.noSpAlign <= &nanoLatch[NANO_NO_SP_ALGN +: 2];
-            Nanod_r.extDbh    <=  nanoLatch[NANO_EXT_DBH];
-            Nanod_r.extAbh    <=  nanoLatch[NANO_EXT_ABH];
-            Nanod_r.todbin    <=  nanoLatch[NANO_TODBIN];
-            Nanod_r.toIrc     <=  nanoLatch[NANO_TOIRC];
+            oNanoDec_t4.updTpend  <= (ftuCtrl == NANO_FTU_UPDTPEND) ? 1'b1 : 1'b0;
+            oNanoDec_t4.clrTpend  <= (ftuCtrl == NANO_FTU_CLRTPEND) ? 1'b1 : 1'b0;
+            oNanoDec_t4.tvn2Ftu   <= (ftuCtrl == NANO_FTU_TVN)      ? 1'b1 : 1'b0;
+            oNanoDec_t4.const2Ftu <= (ftuCtrl == NANO_FTU_CONST)    ? 1'b1 : 1'b0;
+            oNanoDec_t4.ftu2Dbl   <= (ftuCtrl == NANO_FTU_DBL)
+                              || (ftuCtrl == NANO_FTU_INL)      ? 1'b1 : 1'b0;
+            oNanoDec_t4.ftu2Abl   <= (ftuCtrl == NANO_FTU_2ABL)     ? 1'b1 : 1'b0;
+            oNanoDec_t4.abl2Pren  <= (ftuCtrl == NANO_FTU_ABL2PREN) ? 1'b1 : 1'b0;
+            oNanoDec_t4.updPren   <= (ftuCtrl == NANO_FTU_RSTPREN)  ? 1'b1 : 1'b0;
+            oNanoDec_t4.inl2psw   <= (ftuCtrl == NANO_FTU_INL)      ? 1'b1 : 1'b0;
+            oNanoDec_t4.ftu2Sr    <= (ftuCtrl == NANO_FTU_2SR)      ? 1'b1 : 1'b0;
+            oNanoDec_t4.sr2Ftu    <= (ftuCtrl == NANO_FTU_RDSR)     ? 1'b1 : 1'b0;
+            oNanoDec_t4.pswIToFtu <= (ftuCtrl == NANO_FTU_PSWI)     ? 1'b1 : 1'b0;
+            oNanoDec_t4.ird2Ftu   <= (ftuCtrl == NANO_FTU_IRD)      ? 1'b1 : 1'b0; // Used on bus/addr error
+            oNanoDec_t4.ssw2Ftu   <= (ftuCtrl == NANO_FTU_SSW)      ? 1'b1 : 1'b0;
+            oNanoDec_t4.initST    <= (ftuCtrl == NANO_FTU_INL)
+                              || (ftuCtrl == NANO_FTU_CLRTPEND)
+                              || (ftuCtrl == NANO_FTU_INIT_ST)  ? 1'b1 : 1'b0;
+
+            oNanoDec_t4.auClkEn   <= ~iNanoLatch_t3[NANO_AUCLKEN];
+            oNanoDec_t4.auCntrl   <=  iNanoLatch_t3[NANO_AUCTRL +: 3];
+            oNanoDec_t4.noSpAlign <= &iNanoLatch_t3[NANO_NO_SP_ALGN +: 2];
+            oNanoDec_t4.extDbh    <=  iNanoLatch_t3[NANO_EXT_DBH];
+            oNanoDec_t4.extAbh    <=  iNanoLatch_t3[NANO_EXT_ABH];
+            oNanoDec_t4.todbin    <=  iNanoLatch_t3[NANO_TODBIN];
+            oNanoDec_t4.toIrc     <=  iNanoLatch_t3[NANO_TOIRC];
 
             // ablAbd is disabled on byte transfers (adbhCharge plus irdIsByte). Not sure the combination makes much sense.
             // It happens in a few cases but I don't see anything enabled on abL (or abH) section anyway.
 
-            Nanod_r.ablAbd    <= nanoLatch[NANO_ABLABD];
-            Nanod_r.ablAbh    <= nanoLatch[NANO_ABLABH];
-            Nanod_r.dblDbd    <= nanoLatch[NANO_DBLDBD];
-            Nanod_r.dblDbh    <= nanoLatch[NANO_DBLDBH];
+            oNanoDec_t4.ablAbd    <= iNanoLatch_t3[NANO_ABLABD];
+            oNanoDec_t4.ablAbh    <= iNanoLatch_t3[NANO_ABLABH];
+            oNanoDec_t4.dblDbd    <= iNanoLatch_t3[NANO_DBLDBD];
+            oNanoDec_t4.dblDbh    <= iNanoLatch_t3[NANO_DBLDBH];
 
-            Nanod_r.dbl2Atl   <= (atlCtrl[2:0] == 3'b010) ? 1'b1 : 1'b0;
-            Nanod_r.atl2Dbl   <= (atlCtrl[2:0] == 3'b011) ? 1'b1 : 1'b0;
-            Nanod_r.abl2Atl   <= (atlCtrl[2:0] == 3'b100) ? 1'b1 : 1'b0;
-            Nanod_r.atl2Abl   <= (atlCtrl[2:0] == 3'b101) ? 1'b1 : 1'b0;
+            oNanoDec_t4.dbl2Atl   <= (atlCtrl[2:0] == 3'b010) ? 1'b1 : 1'b0;
+            oNanoDec_t4.atl2Dbl   <= (atlCtrl[2:0] == 3'b011) ? 1'b1 : 1'b0;
+            oNanoDec_t4.abl2Atl   <= (atlCtrl[2:0] == 3'b100) ? 1'b1 : 1'b0;
+            oNanoDec_t4.atl2Abl   <= (atlCtrl[2:0] == 3'b101) ? 1'b1 : 1'b0;
 
-            Nanod_r.aob2Ab    <= (athCtrl[2:0] == 3'b101) ? 1'b1 : 1'b0; // Used on BSER1 only
+            oNanoDec_t4.aob2Ab    <= (athCtrl[2:0] == 3'b101) ? 1'b1 : 1'b0; // Used on BSER1 only
 
-            Nanod_r.abh2Ath   <= (athCtrl[1:0] == 2'b01 ) ? 1'b1 : 1'b0;
-            Nanod_r.dbh2Ath   <= (athCtrl[2:0] == 3'b100) ? 1'b1 : 1'b0;
-            Nanod_r.ath2Dbh   <= (athCtrl[2:0] == 3'b110) ? 1'b1 : 1'b0;
-            Nanod_r.ath2Abh   <= (athCtrl[2:0] == 3'b011) ? 1'b1 : 1'b0;
+            oNanoDec_t4.abh2Ath   <= (athCtrl[1:0] == 2'b01 ) ? 1'b1 : 1'b0;
+            oNanoDec_t4.dbh2Ath   <= (athCtrl[2:0] == 3'b100) ? 1'b1 : 1'b0;
+            oNanoDec_t4.ath2Dbh   <= (athCtrl[2:0] == 3'b110) ? 1'b1 : 1'b0;
+            oNanoDec_t4.ath2Abh   <= (athCtrl[2:0] == 3'b011) ? 1'b1 : 1'b0;
 
-            Nanod_r.alu2Dbd   <= nanoLatch[NANO_ALU2DBD];
-            Nanod_r.alu2Abd   <= nanoLatch[NANO_ALU2ABD];
+            oNanoDec_t4.alu2Dbd   <= iNanoLatch_t3[NANO_ALU2DBD];
+            oNanoDec_t4.alu2Abd   <= iNanoLatch_t3[NANO_ALU2ABD];
+            oNanoDec_t4.dbin2Dbd  <= iNanoLatch_t3[NANO_DBIN2DBD];
+            oNanoDec_t4.dbin2Abd  <= iNanoLatch_t3[NANO_DBIN2ABD];
+            oNanoDec_t4.au2Db     <= oNanoDec_t3.au2Db;
+            oNanoDec_t4.au2Ab     <= oNanoDec_t3.au2Ab;
 
-            Nanod_r.abd2Dcr   <= (nanoLatch[NANO_DCR+0 +: 2]  == 2'b11) ? 1'b1 : 1'b0;
-            Nanod_r.dcr2Dbd   <= (nanoLatch[NANO_DCR+1 +: 2]  == 2'b11) ? 1'b1 : 1'b0;
-            Nanod_r.dbd2Alue  <= (nanoLatch[NANO_ALUE+1 +: 2] == 2'b10) ? 1'b1 : 1'b0;
-            Nanod_r.alue2Dbd  <= (nanoLatch[NANO_ALUE+0 +: 2] == 2'b01) ? 1'b1 : 1'b0;
+            oNanoDec_t4.abd2Dcr   <= (iNanoLatch_t3[NANO_DCR+0 +: 2]  == 2'b11) ? 1'b1 : 1'b0;
+            oNanoDec_t4.dcr2Dbd   <= (iNanoLatch_t3[NANO_DCR+1 +: 2]  == 2'b11) ? 1'b1 : 1'b0;
+            oNanoDec_t4.dbd2Alue  <= (iNanoLatch_t3[NANO_ALUE+1 +: 2] == 2'b10) ? 1'b1 : 1'b0;
+            oNanoDec_t4.alue2Dbd  <= (iNanoLatch_t3[NANO_ALUE+0 +: 2] == 2'b01) ? 1'b1 : 1'b0;
 
-            Nanod_r.dbd2Alub  <= nanoLatch[NANO_DBD2ALUB];
-            Nanod_r.abd2Alub  <= nanoLatch[NANO_ABD2ALUB];
+            oNanoDec_t4.dbd2Alub  <= iNanoLatch_t3[NANO_DBD2ALUB];
+            oNanoDec_t4.abd2Alub  <= iNanoLatch_t3[NANO_ABD2ALUB];
 
             // Originally not latched. We better should because we transfer one cycle later, T3 instead of T1.
-            Nanod_r.dobCtrl   <= dobCtrl;
-            // Nanod_r.adb2Dob <= (dobCtrl == 2'b10);
-            // Nanod_r.dbd2Dob <= (dobCtrl == 2'b01);
-            // Nanod_r.alu2Dob <= (dobCtrl == 2'b11);
+            oNanoDec_t4.dobCtrl   <= dobCtrl;
+            // oNanoDec_t4.adb2Dob <= (dobCtrl == 2'b10);
+            // oNanoDec_t4.dbd2Dob <= (dobCtrl == 2'b01);
+            // oNanoDec_t4.alu2Dob <= (dobCtrl == 2'b11);
 
             // Might be better not to register these signals to allow latching RX/RY mux earlier!
-            // But then must latch Irdecod.isPcRel on T3!
+            // But then must latch iIrdDecode_t1.isPcRel on T3!
 
-            Nanod_r.rxl2db  <= Nanod_w.reg2dbl & ~dblSpecial &  nanoLatch[NANO_RXL_DBL];
-            Nanod_r.rxl2ab  <= Nanod_w.reg2abl & ~ablSpecial & ~nanoLatch[NANO_RXL_DBL];
+            oNanoDec_t4.rxl2db  <= oNanoDec_t3.reg2dbl & ~dblSpecial &  iNanoLatch_t3[NANO_RXL_DBL];
+            oNanoDec_t4.rxl2ab  <= oNanoDec_t3.reg2abl & ~ablSpecial & ~iNanoLatch_t3[NANO_RXL_DBL];
 
-            Nanod_r.dbl2rxl <= Nanod_w.dbl2reg & ~dblSpecial &  nanoLatch[NANO_RXL_DBL];
-            Nanod_r.abl2rxl <= Nanod_w.abl2reg & ~ablSpecial & ~nanoLatch[NANO_RXL_DBL];
+            oNanoDec_t4.dbl2rxl <= oNanoDec_t3.dbl2reg & ~dblSpecial &  iNanoLatch_t3[NANO_RXL_DBL];
+            oNanoDec_t4.abl2rxl <= oNanoDec_t3.abl2reg & ~ablSpecial & ~iNanoLatch_t3[NANO_RXL_DBL];
 
-            Nanod_r.rxh2dbh <= Nanod_w.reg2dbh & ~dbhSpecial &  nanoLatch[NANO_RXH_DBH];
-            Nanod_r.rxh2abh <= Nanod_w.reg2abh & ~abhSpecial & ~nanoLatch[NANO_RXH_DBH];
+            oNanoDec_t4.rxh2dbh <= oNanoDec_t3.reg2dbh & ~dbhSpecial &  iNanoLatch_t3[NANO_RXH_DBH];
+            oNanoDec_t4.rxh2abh <= oNanoDec_t3.reg2abh & ~abhSpecial & ~iNanoLatch_t3[NANO_RXH_DBH];
 
-            Nanod_r.dbh2rxh <= Nanod_w.dbh2reg & ~dbhSpecial &  nanoLatch[NANO_RXH_DBH];
-            Nanod_r.abh2rxh <= Nanod_w.abh2reg & ~abhSpecial & ~nanoLatch[NANO_RXH_DBH];
+            oNanoDec_t4.dbh2rxh <= oNanoDec_t3.dbh2reg & ~dbhSpecial &  iNanoLatch_t3[NANO_RXH_DBH];
+            oNanoDec_t4.abh2rxh <= oNanoDec_t3.abh2reg & ~abhSpecial & ~iNanoLatch_t3[NANO_RXH_DBH];
 
-            Nanod_r.dbh2ryh <= Nanod_w.dbh2reg & ~dbhSpecial & ~nanoLatch[NANO_RXH_DBH];
-            Nanod_r.abh2ryh <= Nanod_w.abh2reg & ~abhSpecial &  nanoLatch[NANO_RXH_DBH];
+            oNanoDec_t4.dbh2ryh <= oNanoDec_t3.dbh2reg & ~dbhSpecial & ~iNanoLatch_t3[NANO_RXH_DBH];
+            oNanoDec_t4.abh2ryh <= oNanoDec_t3.abh2reg & ~abhSpecial &  iNanoLatch_t3[NANO_RXH_DBH];
 
-            Nanod_r.dbl2ryl <= Nanod_w.dbl2reg & ~dblSpecial & ~nanoLatch[NANO_RXL_DBL];
-            Nanod_r.abl2ryl <= Nanod_w.abl2reg & ~ablSpecial &  nanoLatch[NANO_RXL_DBL];
+            oNanoDec_t4.dbl2ryl <= oNanoDec_t3.dbl2reg & ~dblSpecial & ~iNanoLatch_t3[NANO_RXL_DBL];
+            oNanoDec_t4.abl2ryl <= oNanoDec_t3.abl2reg & ~ablSpecial &  iNanoLatch_t3[NANO_RXL_DBL];
 
-            Nanod_r.ryl2db  <= Nanod_w.reg2dbl & ~dblSpecial & ~nanoLatch[NANO_RXL_DBL];
-            Nanod_r.ryl2ab  <= Nanod_w.reg2abl & ~ablSpecial &  nanoLatch[NANO_RXL_DBL];
+            oNanoDec_t4.ryl2db  <= oNanoDec_t3.reg2dbl & ~dblSpecial & ~iNanoLatch_t3[NANO_RXL_DBL];
+            oNanoDec_t4.ryl2ab  <= oNanoDec_t3.reg2abl & ~ablSpecial &  iNanoLatch_t3[NANO_RXL_DBL];
 
-            Nanod_r.ryh2dbh <= Nanod_w.reg2dbh & ~dbhSpecial & ~nanoLatch[NANO_RXH_DBH];
-            Nanod_r.ryh2abh <= Nanod_w.reg2abh & ~abhSpecial &  nanoLatch[NANO_RXH_DBH];
+            oNanoDec_t4.ryh2dbh <= oNanoDec_t3.reg2dbh & ~dbhSpecial & ~iNanoLatch_t3[NANO_RXH_DBH];
+            oNanoDec_t4.ryh2abh <= oNanoDec_t3.reg2abh & ~abhSpecial &  iNanoLatch_t3[NANO_RXH_DBH];
 
             // Originally isTas only delayed on T2 (and seems only a late mask rev fix)
             // Better latch the combination on T4
-            Nanod_r.isRmc   <= Irdecod.isTas & nanoLatch[NANO_BUSBYTE];
+            oNanoDec_t4.isRmc   <= iIrdDecode_t1.isTas & iNanoLatch_t3[NANO_BUSBYTE];
         end
     end
 
     // Update SSW at the start of Bus/Addr error ucode
-    assign Nanod_w.updSsw    = Nanod_r.aob2Ab;
-
-    assign Nanod_w.updTpend  = (ftuCtrl == NANO_FTU_UPDTPEND);
-    assign Nanod_w.clrTpend  = (ftuCtrl == NANO_FTU_CLRTPEND);
-    assign Nanod_w.tvn2Ftu   = (ftuCtrl == NANO_FTU_TVN);
-    assign Nanod_w.const2Ftu = (ftuCtrl == NANO_FTU_CONST);
-    assign Nanod_w.ftu2Dbl   = (ftuCtrl == NANO_FTU_DBL) | ( ftuCtrl == NANO_FTU_INL);
-    assign Nanod_w.ftu2Abl   = (ftuCtrl == NANO_FTU_2ABL);
-    assign Nanod_w.inl2psw   = (ftuCtrl == NANO_FTU_INL);
-    assign Nanod_w.pswIToFtu = (ftuCtrl == NANO_FTU_PSWI);
-    assign Nanod_w.ftu2Sr    = (ftuCtrl == NANO_FTU_2SR);
-    assign Nanod_w.sr2Ftu    = (ftuCtrl == NANO_FTU_RDSR);
-    assign Nanod_w.ird2Ftu   = (ftuCtrl == NANO_FTU_IRD);       // Used on bus/addr error
-    assign Nanod_w.ssw2Ftu   = (ftuCtrl == NANO_FTU_SSW);
-    assign Nanod_w.initST    = (ftuCtrl == NANO_FTU_INL) | (ftuCtrl == NANO_FTU_CLRTPEND) | (ftuCtrl == NANO_FTU_INIT_ST);
-    assign Nanod_w.abl2Pren  = (ftuCtrl == NANO_FTU_ABL2PREN);
-    assign Nanod_w.updPren   = (ftuCtrl == NANO_FTU_RSTPREN);
-
-    assign Nanod_w.Ir2Ird    = nanoLatch[NANO_IR2IRD];
+    assign oNanoDec_t3.updSsw    = oNanoDec_t4.aob2Ab;
+
+
+    assign oNanoDec_t3.Ir2Ird    = iNanoLatch_t3[NANO_IR2IRD];
 
     // ALU control better latched later after combining with IRD decoding
 
-    wire [1:0] aluFinInit = nanoLatch[NANO_ALU_FI +: 2];
+    wire [1:0] aluFinInit = iNanoLatch_t3[NANO_ALU_FI +: 2];
 
-    assign Nanod_w.aluDctrl      = nanoLatch[NANO_ALU_DCTRL +: 2];
-    assign Nanod_w.aluActrl      = nanoLatch[NANO_ALU_ACTRL];
-    assign Nanod_w.aluColumn     = { nanoLatch[ NANO_ALU_COL], nanoLatch[ NANO_ALU_COL+1], nanoLatch[ NANO_ALU_COL+2]};
-    assign Nanod_w.aluFinish     = (aluFinInit == 2'b10) ? 1'b1 : 1'b0;
-    assign Nanod_w.aluInit       = (aluFinInit == 2'b01) ? 1'b1 : 1'b0;
+    assign oNanoDec_t3.aluDctrl      = iNanoLatch_t3[NANO_ALU_DCTRL +: 2];
+    assign oNanoDec_t3.aluActrl      = iNanoLatch_t3[NANO_ALU_ACTRL];
+    assign oNanoDec_t3.aluColumn     = { iNanoLatch_t3[ NANO_ALU_COL], iNanoLatch_t3[ NANO_ALU_COL+1], iNanoLatch_t3[ NANO_ALU_COL+2]};
+    assign oNanoDec_t3.aluFinish     = (aluFinInit == 2'b10) ? 1'b1 : 1'b0;
+    assign oNanoDec_t3.aluInit       = (aluFinInit == 2'b01) ? 1'b1 : 1'b0;
 
     // FTU 2 CCR encoded as both ALU Init and ALU Finish set.
     // In theory this encoding allows writes to CCR without writing to SR
     // But FTU 2 CCR and to SR are both set together at nanorom.
-    assign Nanod_w.ftu2Ccr       = (aluFinInit == 2'b11) ? 1'b1 : 1'b0;
+    assign oNanoDec_t3.ftu2Ccr       = (aluFinInit == 2'b11) ? 1'b1 : 1'b0;
 
-    assign Nanod_w.abdIsByte     = nanoLatch[NANO_ABDHRECHARGE];
+    assign oNanoDec_t3.abdIsByte     = iNanoLatch_t3[NANO_ABDHRECHARGE];
 
     // Not being latched on T4 creates non unique case warning!
-    assign Nanod_w.au2Db         = (nanoLatch[NANO_AUOUT +: 2] == 2'b01) ? 1'b1 : 1'b0;
-    assign Nanod_w.au2Ab         = (nanoLatch[NANO_AUOUT +: 2] == 2'b10) ? 1'b1 : 1'b0;
-    assign Nanod_w.au2Pc         = (nanoLatch[NANO_AUOUT +: 2] == 2'b11) ? 1'b1 : 1'b0;
+    assign oNanoDec_t3.au2Db         = (iNanoLatch_t3[NANO_AUOUT +: 2] == 2'b01) ? 1'b1 : 1'b0;
+    assign oNanoDec_t3.au2Ab         = (iNanoLatch_t3[NANO_AUOUT +: 2] == 2'b10) ? 1'b1 : 1'b0;
+    assign oNanoDec_t3.au2Pc         = (iNanoLatch_t3[NANO_AUOUT +: 2] == 2'b11) ? 1'b1 : 1'b0;
 
-    assign Nanod_w.db2Aob        = (aobCtrl == 2'b10) ? 1'b1 : 1'b0;
-    assign Nanod_w.ab2Aob        = (aobCtrl == 2'b01) ? 1'b1 : 1'b0;
-    assign Nanod_w.au2Aob        = (aobCtrl == 2'b11) ? 1'b1 : 1'b0;
+    assign oNanoDec_t3.db2Aob        = (aobCtrl == 2'b10) ? 1'b1 : 1'b0;
+    assign oNanoDec_t3.ab2Aob        = (aobCtrl == 2'b01) ? 1'b1 : 1'b0;
+    assign oNanoDec_t3.au2Aob        = (aobCtrl == 2'b11) ? 1'b1 : 1'b0;
 
-    assign Nanod_w.dbin2Abd      = nanoLatch[NANO_DBIN2ABD];
-    assign Nanod_w.dbin2Dbd      = nanoLatch[NANO_DBIN2DBD];
+    //assign oNanoDec_t3.dbin2Abd      = iNanoLatch_t3[NANO_DBIN2ABD];
+    //assign oNanoDec_t3.dbin2Dbd      = iNanoLatch_t3[NANO_DBIN2DBD];
 
-    assign Nanod_w.permStart     = (aobCtrl != 2'b00) ? 1'b1 : 1'b0;
-    assign Nanod_w.isWrite       = nanoLatch[NANO_DOBCTRL_1]
-                                 | nanoLatch[NANO_DOBCTRL_0];
-    assign Nanod_w.waitBusFinish = nanoLatch[NANO_DOBCTRL_1]
-                                 | nanoLatch[NANO_DOBCTRL_0]
-                                 | nanoLatch[NANO_TOIRC]
-                                 | nanoLatch[NANO_TODBIN];
-    assign Nanod_w.busByte       = nanoLatch[NANO_BUSBYTE];
+    assign oNanoDec_t3.permStart     = (aobCtrl != 2'b00) ? 1'b1 : 1'b0;
+    assign oNanoDec_t3.isWrite       = iNanoLatch_t3[NANO_DOBCTRL_1]
+                                 | iNanoLatch_t3[NANO_DOBCTRL_0];
+    assign oNanoDec_t3.waitBusFinish = iNanoLatch_t3[NANO_DOBCTRL_1]
+                                 | iNanoLatch_t3[NANO_DOBCTRL_0]
+                                 | iNanoLatch_t3[NANO_TOIRC]
+                                 | iNanoLatch_t3[NANO_TODBIN];
+    assign oNanoDec_t3.busByte       = iNanoLatch_t3[NANO_BUSBYTE];
 
-    assign Nanod_w.noLowByte     = nanoLatch[NANO_LOWBYTE];
-    assign Nanod_w.noHighByte    = nanoLatch[NANO_HIGHBYTE];
+    assign oNanoDec_t3.noLowByte     = iNanoLatch_t3[NANO_LOWBYTE];
+    assign oNanoDec_t3.noHighByte    = iNanoLatch_t3[NANO_HIGHBYTE];
 
     // Not registered. Register at T4 after combining
     // Might be better to remove all those and combine here instead of at execution unit !!
-    assign Nanod_w.abl2reg       = nanoLatch[NANO_ABL2REG];
-    assign Nanod_w.abh2reg       = nanoLatch[NANO_ABH2REG];
-    assign Nanod_w.dbl2reg       = nanoLatch[NANO_DBL2REG];
-    assign Nanod_w.dbh2reg       = nanoLatch[NANO_DBH2REG];
-    assign Nanod_w.reg2dbl       = nanoLatch[NANO_REG2DBL];
-    assign Nanod_w.reg2dbh       = nanoLatch[NANO_REG2DBH];
-    assign Nanod_w.reg2abl       = nanoLatch[NANO_REG2ABL];
-    assign Nanod_w.reg2abh       = nanoLatch[NANO_REG2ABH];
+    assign oNanoDec_t3.abl2reg       = iNanoLatch_t3[NANO_ABL2REG];
+    assign oNanoDec_t3.abh2reg       = iNanoLatch_t3[NANO_ABH2REG];
+    assign oNanoDec_t3.dbl2reg       = iNanoLatch_t3[NANO_DBL2REG];
+    assign oNanoDec_t3.dbh2reg       = iNanoLatch_t3[NANO_DBH2REG];
+    assign oNanoDec_t3.reg2dbl       = iNanoLatch_t3[NANO_REG2DBL];
+    assign oNanoDec_t3.reg2dbh       = iNanoLatch_t3[NANO_REG2DBH];
+    assign oNanoDec_t3.reg2abl       = iNanoLatch_t3[NANO_REG2ABL];
+    assign oNanoDec_t3.reg2abh       = iNanoLatch_t3[NANO_REG2ABH];
 
-    assign Nanod_w.ssp           = nanoLatch[NANO_SSP];
+    assign oNanoDec_t3.ssp           = iNanoLatch_t3[NANO_SSP];
 
-    assign Nanod_w.rz            = nanoLatch[NANO_RZ];
+    assign oNanoDec_t3.rz            = iNanoLatch_t3[NANO_RZ];
 
     // Actually DTL can't happen on PC relative mode. See IR decoder.
 
@@ -904,10 +977,10 @@ localparam [3:0]
     wire dtlabd = 1'b0;
     wire dthabh = 1'b0;
 
-    wire dblSpecial = Nanod_w.pcldbl | dtldbd;
-    wire dbhSpecial = Nanod_w.pchdbh | dthdbh;
-    wire ablSpecial = Nanod_w.pclabl | dtlabd;
-    wire abhSpecial = Nanod_w.pchabh | dthabh;
+    wire dblSpecial = oNanoDec_t3.pcldbl | dtldbd;
+    wire dbhSpecial = oNanoDec_t3.pchdbh | dthdbh;
+    wire ablSpecial = oNanoDec_t3.pclabl | dtlabd;
+    wire abhSpecial = oNanoDec_t3.pchabh | dthabh;
 
     //
     // Combine with IRD decoding
@@ -916,18 +989,18 @@ localparam [3:0]
 
     // PC used instead of RY on PC relative instuctions
 
-    assign Nanod_w.rxlDbl = nanoLatch[NANO_RXL_DBL];
-    wire isPcRel  = Irdecod.isPcRel & ~nanoLatch[NANO_RZ];
-    wire pcRelDbl = isPcRel & ~nanoLatch[NANO_RXL_DBL];
-    wire pcRelDbh = isPcRel & ~nanoLatch[NANO_RXH_DBH];
-    wire pcRelAbl = isPcRel &  nanoLatch[NANO_RXL_DBL];
-    wire pcRelAbh = isPcRel &  nanoLatch[NANO_RXH_DBH];
+    assign oNanoDec_t3.rxlDbl = iNanoLatch_t3[NANO_RXL_DBL];
+    wire isPcRel  = iIrdDecode_t1.isPcRel & ~iNanoLatch_t3[NANO_RZ];
+    wire pcRelDbl = isPcRel & ~iNanoLatch_t3[NANO_RXL_DBL];
+    wire pcRelDbh = isPcRel & ~iNanoLatch_t3[NANO_RXH_DBH];
+    wire pcRelAbl = isPcRel &  iNanoLatch_t3[NANO_RXL_DBL];
+    wire pcRelAbh = isPcRel &  iNanoLatch_t3[NANO_RXH_DBH];
 
-    assign Nanod_w.pcldbl = nanoLatch[NANO_PCLDBL] | pcRelDbl;
-    assign Nanod_w.pchdbh = (nanoLatch[NANO_PCH +: 2] == 2'b01) ? 1'b1 : pcRelDbh;
+    assign oNanoDec_t3.pcldbl = iNanoLatch_t3[NANO_PCLDBL] | pcRelDbl;
+    assign oNanoDec_t3.pchdbh = (iNanoLatch_t3[NANO_PCH +: 2] == 2'b01) ? 1'b1 : pcRelDbh;
 
-    assign Nanod_w.pclabl = nanoLatch[NANO_PCLABL] | pcRelAbl;
-    assign Nanod_w.pchabh = (nanoLatch[NANO_PCH +: 2] == 2'b10) ? 1'b1 : pcRelAbh;
+    assign oNanoDec_t3.pclabl = iNanoLatch_t3[NANO_PCLABL] | pcRelAbl;
+    assign oNanoDec_t3.pchabh = (iNanoLatch_t3[NANO_PCH +: 2] == 2'b10) ? 1'b1 : pcRelAbh;
 
 endmodule
 
@@ -939,100 +1012,100 @@ endmodule
 //
 module irdDecode
 (
-    input     [15:0] Ird,
-    input     [15:0] IrdL,
-    output s_irdecod Irdecod
+    input     [15:0] iIrd_t1,
+    input     [15:0] iIrdL_t1,
+    output s_irdecod oIrdDecode_t1
 );
 
     reg  implicitSp;
-    wire isRegShift = (IrdL[4'hE]) & (Ird[7:6] != 2'b11);
-    wire isDynShift = isRegShift & Ird[5];
-    wire isTas      = (Ird[11:6] == 6'b101011) ? IrdL[4'h4] : 1'b0;
+    wire isRegShift = (iIrdL_t1[4'hE]) & (iIrd_t1[7:6] != 2'b11);
+    wire isDynShift = isRegShift & iIrd_t1[5];
+    wire isTas      = (iIrd_t1[11:6] == 6'b101011) ? iIrdL_t1[4'h4] : 1'b0;
 
-    assign Irdecod.isPcRel = (&Ird[5:3]) & ~isDynShift & !Ird[2] & Ird[1];
-    assign Irdecod.isTas   = isTas;
+    assign oIrdDecode_t1.isPcRel = (&iIrd_t1[5:3]) & ~isDynShift & !iIrd_t1[2] & iIrd_t1[1];
+    assign oIrdDecode_t1.isTas   = isTas;
 
-    assign Irdecod.rx = Ird[11:9];
-    assign Irdecod.ry = Ird[ 2:0];
+    assign oIrdDecode_t1.rx = iIrd_t1[11:9];
+    assign oIrdDecode_t1.ry = iIrd_t1[ 2:0];
 
-    wire isPreDecr = (Ird[5:3] == 3'b100) ? 1'b1 : 1'b0;
-    wire eaAreg    = (Ird[5:3] == 3'b001) ? 1'b1 : 1'b0;
+    wire isPreDecr = (iIrd_t1[5:3] == 3'b100) ? 1'b1 : 1'b0;
+    wire eaAreg    = (iIrd_t1[5:3] == 3'b001) ? 1'b1 : 1'b0;
 
     // rx is A or D
     // movem
     always_comb begin
         unique case (1'b1)
-            IrdL[4'h1],
-            IrdL[4'h2],
-            IrdL[4'h3]:
+            iIrdL_t1[4'h1],
+            iIrdL_t1[4'h2],
+            iIrdL_t1[4'h3]:
                 // MOVE: RX always Areg except if dest mode is Dn 000
-                Irdecod.rxIsAreg = (|Ird[8:6]);
+                oIrdDecode_t1.rxIsAreg = (|iIrd_t1[8:6]);
 
-            IrdL[4'h4]:
+            iIrdL_t1[4'h4]:
                 // not CHK (LEA)
-                Irdecod.rxIsAreg = (&Ird[8:6]);
+                oIrdDecode_t1.rxIsAreg = (&iIrd_t1[8:6]);
 
-            IrdL[4'h8]:
+            iIrdL_t1[4'h8]:
                 // SBCD
-                Irdecod.rxIsAreg = eaAreg & Ird[8] & ~Ird[7];
+                oIrdDecode_t1.rxIsAreg = eaAreg & iIrd_t1[8] & ~iIrd_t1[7];
 
-            IrdL[4'hC]:
+            iIrdL_t1[4'hC]:
                 // ABCD/EXG An,An
-                Irdecod.rxIsAreg = eaAreg & Ird[8] & ~Ird[7];
-
-            IrdL[4'h9],
-            IrdL[4'hB],
-            IrdL[4'hD]:
-                Irdecod.rxIsAreg =
-                    (Ird[7] & Ird[6]) |                      // SUBA/CMPA/ADDA
-                    (eaAreg & Ird[8] & (Ird[7:6] != 2'b11)); // SUBX/CMPM/ADDX
+                oIrdDecode_t1.rxIsAreg = eaAreg & iIrd_t1[8] & ~iIrd_t1[7];
+
+            iIrdL_t1[4'h9],
+            iIrdL_t1[4'hB],
+            iIrdL_t1[4'hD]:
+                oIrdDecode_t1.rxIsAreg =
+                    (iIrd_t1[7] & iIrd_t1[6]) |                      // SUBA/CMPA/ADDA
+                    (eaAreg & iIrd_t1[8] & (iIrd_t1[7:6] != 2'b11)); // SUBX/CMPM/ADDX
             default:
-                Irdecod.rxIsAreg = implicitSp;
+                oIrdDecode_t1.rxIsAreg = implicitSp;
         endcase
     end
 
     // RX is movem
-    assign Irdecod.rxIsMovem    = IrdL[4'h4] & ~Ird[8] & ~implicitSp;
-    assign Irdecod.movemPreDecr = IrdL[4'h4] & ~Ird[8] & ~implicitSp & isPreDecr;
+    assign oIrdDecode_t1.rxIsMovem    = iIrdL_t1[4'h4] & ~iIrd_t1[8] & ~implicitSp;
+    assign oIrdDecode_t1.movemPreDecr = iIrdL_t1[4'h4] & ~iIrd_t1[8] & ~implicitSp & isPreDecr;
 
     // RX is DT.
     // but SSP explicit or pc explicit has higher priority!
     // addq/subq (scc & dbcc also, but don't use rx)
     // Immediate including static bit
-    assign Irdecod.rxIsDt = IrdL[4'h5] | (IrdL[4'h0] & ~Ird[8]);
+    assign oIrdDecode_t1.rxIsDt = iIrdL_t1[4'h5] | (iIrdL_t1[4'h0] & ~iIrd_t1[8]);
 
     // RX is USP (16'h4E6x)
-    assign Irdecod.rxIsUsp = IrdL[4'h4] & (Ird[11:4] == 8'hE6);
+    assign oIrdDecode_t1.rxIsUsp = iIrdL_t1[4'h4] & (iIrd_t1[11:4] == 8'hE6);
 
     // RY is DT
     // rz or PC explicit has higher priority
 
-    wire eaImmOrAbs = (Ird[5:3] == 3'b111) & ~Ird[1];
-    assign Irdecod.ryIsDt = eaImmOrAbs & ~isRegShift;
+    wire eaImmOrAbs = (iIrd_t1[5:3] == 3'b111) & ~iIrd_t1[1];
+    assign oIrdDecode_t1.ryIsDt = eaImmOrAbs & ~isRegShift;
 
     // RY is Address register
     always_comb begin
         logic eaIsAreg;
 
         // On most cases RY is Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL)
-        eaIsAreg = (Ird[5:3] != 3'b000) & (Ird[5:3] != 3'b111);
+        eaIsAreg = (iIrd_t1[5:3] != 3'b000) & (iIrd_t1[5:3] != 3'b111);
 
         unique case (1'b1)
             // MOVE: RY always Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL)
             // Most lines, including misc line 4, also.
             default:
-                Irdecod.ryIsAreg = eaIsAreg;
+                oIrdDecode_t1.ryIsAreg = eaIsAreg;
 
-            IrdL[4'h5]:
+            iIrdL_t1[4'h5]:
                 // DBcc is an exception
-                Irdecod.ryIsAreg = eaIsAreg & (Ird[7:3] != 5'b11001);
+                oIrdDecode_t1.ryIsAreg = eaIsAreg & (iIrd_t1[7:3] != 5'b11001);
 
-            IrdL[4'h6],
-            IrdL[4'h7]:
-                Irdecod.ryIsAreg = 1'b0;
+            iIrdL_t1[4'h6],
+            iIrdL_t1[4'h7]:
+                oIrdDecode_t1.ryIsAreg = 1'b0;
 
-            IrdL[4'hE]:
-                Irdecod.ryIsAreg = ~isRegShift;
+            iIrdL_t1[4'hE]:
+                oIrdDecode_t1.ryIsAreg = ~isRegShift;
         endcase
     end
 
@@ -1041,42 +1114,42 @@ module irdDecode
     // Original implementation sets this for some instructions that aren't really byte size
     // but doesn't matter because they don't have a byte transfer enabled at nanocode, such as MOVEQ
 
-    wire xIsScc = (Ird[7:6] == 2'b11) & (Ird[5:3] != 3'b001);
-    wire xStaticMem = (Ird[11:8] == 4'b1000) & (Ird[5:4] == 2'b00);     // Static bit to mem
+    wire xIsScc     = (iIrd_t1[7:6] == 2'b11) & (iIrd_t1[5:3] != 3'b001);
+    wire xStaticMem = (iIrd_t1[11:8] == 4'b1000) & (iIrd_t1[5:4] == 2'b00);     // Static bit to mem
     always_comb begin
         unique case (1'b1)
-            IrdL[4'h0]:
-                Irdecod.isByte =
-                ( Ird[8] & (Ird[5:4] != 2'b00)                  ) | // Dynamic bit to mem
-                ( (Ird[11:8] == 4'b1000) & (Ird[5:4] != 2'b00)  ) | // Static bit to mem
-                ( (Ird[8:7] == 2'b10) & (Ird[5:3] == 3'b001)    ) | // Movep from mem only! For byte mux
-                ( (Ird[8:6] == 3'b000) & !xStaticMem );             // Immediate byte
+            iIrdL_t1[4'h0]:
+                oIrdDecode_t1.isByte =
+                ( iIrd_t1[8] & (iIrd_t1[5:4] != 2'b00)                  ) | // Dynamic bit to mem
+                ( (iIrd_t1[11:8] == 4'b1000) & (iIrd_t1[5:4] != 2'b00)  ) | // Static bit to mem
+                ( (iIrd_t1[8:7] == 2'b10) & (iIrd_t1[5:3] == 3'b001)    ) | // Movep from mem only! For byte mux
+                ( (iIrd_t1[8:6] == 3'b000) & !xStaticMem );             // Immediate byte
 
-            IrdL[4'h1]:
-                Irdecod.isByte = 1'b1;      // MOVE.B
+            iIrdL_t1[4'h1]:
+                oIrdDecode_t1.isByte = 1'b1;      // MOVE.B
 
 
-            IrdL[4'h4]:
-                Irdecod.isByte = (Ird[7:6] == 2'b00) ? 1'b1 : isTas;
+            iIrdL_t1[4'h4]:
+                oIrdDecode_t1.isByte = (iIrd_t1[7:6] == 2'b00) ? 1'b1 : isTas;
 
-            IrdL[4'h5]:
-                Irdecod.isByte = (Ird[7:6] == 2'b00) ? 1'b1 : xIsScc;
+            iIrdL_t1[4'h5]:
+                oIrdDecode_t1.isByte = (iIrd_t1[7:6] == 2'b00) ? 1'b1 : xIsScc;
 
-            IrdL[4'h8],
-            IrdL[4'h9],
-            IrdL[4'hB],
-            IrdL[4'hC],
-            IrdL[4'hD],
-            IrdL[4'hE]:
-                Irdecod.isByte = (Ird[7:6] == 2'b00) ? 1'b1 : 1'b0;
+            iIrdL_t1[4'h8],
+            iIrdL_t1[4'h9],
+            iIrdL_t1[4'hB],
+            iIrdL_t1[4'hC],
+            iIrdL_t1[4'hD],
+            iIrdL_t1[4'hE]:
+                oIrdDecode_t1.isByte = (iIrd_t1[7:6] == 2'b00) ? 1'b1 : 1'b0;
 
             default:
-                Irdecod.isByte = 1'b0;
+                oIrdDecode_t1.isByte = 1'b0;
         endcase
     end
 
     // Need it for special byte size. Bus is byte, but whole register word is modified.
-    assign Irdecod.isMovep = IrdL[4'h0] & Ird[8] & eaAreg;
+    assign oIrdDecode_t1.isMovep = iIrdL_t1[4'h0] & iIrd_t1[8] & eaAreg;
 
 
     // rxIsSP implicit use of RX for actual SP transfer
@@ -1086,88 +1159,88 @@ module irdDecode
 
     always_comb begin
         unique case (1'b1)
-            IrdL[4'h6]:
+            iIrdL_t1[4'h6]:
                 // BSR
-                implicitSp = (Ird[11:8] == 4'b0001) ? 1'b1 : 1'b0;
-            IrdL[4'h4]:
+                implicitSp = (iIrd_t1[11:8] == 4'b0001) ? 1'b1 : 1'b0;
+            iIrdL_t1[4'h4]:
                 // Misc like RTS, JSR, etc
-                implicitSp = (Ird[11:8] == 4'b1110) | (Ird[11:6] == 6'b1000_01);
+                implicitSp = (iIrd_t1[11:8] == 4'b1110) | (iIrd_t1[11:6] == 6'b1000_01);
             default:
                 implicitSp = 1'b0;
         endcase
     end
-    assign Irdecod.implicitSp = implicitSp;
+    assign oIrdDecode_t1.implicitSp = implicitSp;
 
     // Modify CCR (and not SR)
     // Probably overkill !! Only needs to distinguish SR vs CCR
     // RTR, MOVE to CCR, xxxI to CCR
-    assign Irdecod.toCcr =  ( IrdL[4'h4] & ((Ird[11:0] == 12'he77) | (Ird[11:6] == 6'b010011)) ) |
-                            ( IrdL[4'h0] & (Ird[8:6] == 3'b000));
+    assign oIrdDecode_t1.toCcr =  ( iIrdL_t1[4'h4] & ((iIrd_t1[11:0] == 12'he77) | (iIrd_t1[11:6] == 6'b010011)) ) |
+                            ( iIrdL_t1[4'h0] & (iIrd_t1[8:6] == 3'b000));
 
     // FTU constants
     // This should not be latched on T3/T4. Latch on T2 or not at all. FTU needs it on next T3.
     // Note: Reset instruction gets constant from ALU not from FTU!
     logic [15:0] ftuConst;
-    wire [3:0] zero28 = (Ird[11:9] == 0) ? 4'h8 : { 1'b0, Ird[11:9]};       // xltate 0,1-7 into 8,1-7
+    wire [3:0] zero28 = (iIrd_t1[11:9] == 0) ? 4'h8 : { 1'b0, iIrd_t1[11:9]};       // xltate 0,1-7 into 8,1-7
 
     always_comb begin
         unique case (1'b1)
-            IrdL[4'h6], // Bcc short
-            IrdL[4'h7]: // MOVEQ
-                ftuConst = { {8{Ird[7]}}, Ird[7:0] };
+            iIrdL_t1[4'h6], // Bcc short
+            iIrdL_t1[4'h7]: // MOVEQ
+                ftuConst = { {8{iIrd_t1[7]}}, iIrd_t1[7:0] };
 
             // ADDQ/SUBQ/static shift double check this
-            IrdL[4'h5],
-            IrdL[4'hE]:
+            iIrdL_t1[4'h5],
+            iIrdL_t1[4'hE]:
                 ftuConst = { 12'h000, zero28};
 
             // MULU/MULS DIVU/DIVS
-            IrdL[4'h8],
-            IrdL[4'hC]:
+            iIrdL_t1[4'h8],
+            iIrdL_t1[4'hC]:
                 ftuConst = 16'h000F;
 
             // TAS
-            IrdL[4'h4]:
+            iIrdL_t1[4'h4]:
                 ftuConst = 16'h0080;
 
             default:
                 ftuConst = 16'h0000;
         endcase
     end
-    assign Irdecod.ftuConst = ftuConst;
+    assign oIrdDecode_t1.ftuConst = ftuConst;
 
     //
     // TRAP Vector # for group 2 exceptions
     //
 
     always_comb begin
-        if (IrdL[4'h4]) begin
-            case (Ird[6:5])
+        if (iIrdL_t1[4'h4]) begin
+            case (iIrd_t1[6:5])
                 2'b00,
                 2'b01:
-                    Irdecod.macroTvn = 6'h6;                // CHK
+                    oIrdDecode_t1.macroTvn = 6'h6;                // CHK
                 2'b11:
-                    Irdecod.macroTvn = 6'h7;                // TRAPV
+                    oIrdDecode_t1.macroTvn = 6'h7;                // TRAPV
                 2'b10:
-                    Irdecod.macroTvn = { 2'b10, Ird[3:0] }; // TRAP
+                    oIrdDecode_t1.macroTvn = { 2'b10, iIrd_t1[3:0] }; // TRAP
             endcase
         end
         else begin
-            Irdecod.macroTvn = 6'h5; // Division by zero
+            oIrdDecode_t1.macroTvn = 6'h5; // Division by zero
         end
     end
 
 
-    wire eaAdir = (Ird[ 5:3] == 3'b001);
-    wire size11 = Ird[7] & Ird[6];
+    wire eaAdir = (iIrd_t1[ 5:3] == 3'b001);
+    wire size11 = iIrd_t1[7] & iIrd_t1[6];
 
     // Opcodes variants that don't affect flags
     // ADDA/SUBA ADDQ/SUBQ MOVEA
 
-    assign Irdecod.inhibitCcr =
-        ( (IrdL[4'h9] | IrdL[4'hD]) & size11) |            // ADDA/SUBA
-        ( IrdL[4'h5] & eaAdir) |                           // ADDQ/SUBQ to An (originally checks for line[4] as well !?)
-        ( (IrdL[4'h2] | IrdL[4'h3]) & Ird[8:6] == 3'b001); // MOVEA
+    assign oIrdDecode_t1.inhibitCcr =
+        ( (iIrdL_t1[4'h9] | iIrdL_t1[4'hD]) & size11) |            // ADDA/SUBA
+        ( iIrdL_t1[4'h5] & eaAdir) |                           // ADDQ/SUBQ to An (originally checks for line[4] as well !?)
+        ( (iIrdL_t1[4'h2] | iIrdL_t1[4'h3]) & iIrd_t1[8:6] == 3'b001); // MOVEA
 
 endmodule
 
@@ -1185,12 +1258,12 @@ module excUnit
     input clk,
     input s_clks Clks,
     input enT1, enT2, enT3, enT4,
-    input s_nanod_r Nanod_r,
-    input s_nanod_w Nanod_w,
+    input s_nanod_r iNanoDec_t4,
+    input s_nanod_w iNanoDec_t3,
     input s_irdecod Irdecod,
     input [15:0] Ird,           // ALU row (and others) decoder needs it
     input pswS,
-    input [15:0] ftu,
+    input [15:0] iFtu_t3,
     input [15:0] iEdb,
 
     output logic [7:0] ccr,
@@ -1199,8 +1272,8 @@ module excUnit
     output prenEmpty, au05z,
     output logic dcr4, ze,
     output logic aob0,
-    output [15:0] AblOut,
-    output logic [15:0] Irc,
+    output [15:0] oAbl_t2,
+    output logic [15:0] oIrc_t4,
     output logic [15:0] oEdb,
     output logic [31:1] eab
 );
@@ -1239,36 +1312,26 @@ localparam
 
 
     wire [15:0] aluOut;
-    wire [15:0] dbin;
+    wire [15:0] wDbin_t4;
     logic [15:0] dcrOutput;
 
     reg [15:0] PcL, PcH;
 
-    reg [31:0] auReg, aob;
+    reg [31:0] rAuReg_t3, aob;
 
-    reg [15:0] Ath, Atl;
+    reg [15:0] rAth_t3;
+    reg [15:0] rAtl_t3;
 
     // Bus execution
-    reg [15:0] Dbl, Dbh;
-    reg [15:0] Abh, Abl;
-    reg [15:0] Abd, Dbd;
-
-    assign AblOut = Abl;
-    assign au05z = (~| auReg[5:0]);
-
-    logic [15:0] dblMux, dbhMux;
-    logic [15:0] abhMux, ablMux;
-    logic [15:0] abdMux, dbdMux;
-
-    logic abdIsByte;
-
-    logic Pcl2Dbl, Pch2Dbh;
-    logic Pcl2Abl, Pch2Abh;
+    reg [15:0] rDbl_t2, rDbh_t2;
+    reg [15:0] rAbh_t2, rAbl_t2;
+    reg [15:0] rAbd_t2, rDbd_t2;
 
+    assign oAbl_t2 = rAbl_t2;
+    assign au05z = (~| rAuReg_t3[5:0]);
 
     // RX RY muxes
     // RX and RY actual registers
-    logic [4:0] actualRx, actualRy;
     logic [3:0] movemRx;
     logic byteNotSpAlign;           // Byte instruction and no sp word align
 
@@ -1280,12 +1343,11 @@ localparam
     logic [4:0] rxMux, ryMux;
     logic [3:0] rxReg, ryReg;
     logic rxIsSp, ryIsSp;
-    logic rxIsAreg, ryIsAreg;
 
     always_comb begin
 
         // Unique IF !!
-        if (Nanod_w.ssp) begin
+        if (iNanoDec_t3.ssp) begin
             rxMux  = REG_SSP[4:0];
             rxIsSp = 1'b1;
             rxReg  = 4'hX;
@@ -1319,13 +1381,13 @@ localparam
         end
 
         // RZ has higher priority!
-        if (Irdecod.ryIsDt & !Nanod_w.rz) begin
+        if (Irdecod.ryIsDt & !iNanoDec_t3.rz) begin
             ryMux  = REG_DT[4:0];
             ryIsSp = 1'b0;
             ryReg  = 4'hX;
         end
         else begin
-            ryReg = Nanod_w.rz ? Irc[15:12] : {Irdecod.ryIsAreg, Irdecod.ry};
+            ryReg = iNanoDec_t3.rz ? oIrc_t4[15:12] : {Irdecod.ryIsAreg, Irdecod.ry};
             ryIsSp = (& ryReg);
             if (ryIsSp & pswS)          // No implicit SP on RY
                 ryMux = REG_SSP[4:0];
@@ -1335,98 +1397,114 @@ localparam
 
     end
 
+    reg [4:0] rActualRx_t4;
+    reg [4:0] rActualRy_t4;
+    reg       rRxIsAreg_t4;
+    reg       rRyIsAreg_t4;
+    
+    reg       rAbdIsByte_t4;
+
     always_ff @(posedge clk) begin
     
         if (enT4) begin
-            byteNotSpAlign <= Irdecod.isByte & ~(Nanod_w.rxlDbl ? rxIsSp : ryIsSp);
+            byteNotSpAlign <= Irdecod.isByte & ~(iNanoDec_t3.rxlDbl ? rxIsSp : ryIsSp);
 
-            actualRx <= rxMux;
-            actualRy <= ryMux;
+            rActualRx_t4 <= rxMux;
+            rActualRy_t4 <= ryMux;
 
-            rxIsAreg <= rxIsSp | rxMux[3];
-            ryIsAreg <= ryIsSp | ryMux[3];
+            rRxIsAreg_t4 <= rxIsSp | rxMux[3];
+            rRyIsAreg_t4 <= ryIsSp | ryMux[3];
 
-            abdIsByte <= Nanod_w.abdIsByte & Irdecod.isByte;
+            rAbdIsByte_t4 <= iNanoDec_t3.abdIsByte & Irdecod.isByte;
         end
     end
 
     // Set RX/RY low word to which bus segment is connected.
 
-    wire ryl2Abl = Nanod_r.ryl2ab & ( ryIsAreg | Nanod_r.ablAbd);
-    wire ryl2Abd = Nanod_r.ryl2ab & (~ryIsAreg | Nanod_r.ablAbd);
-    wire ryl2Dbl = Nanod_r.ryl2db & ( ryIsAreg | Nanod_r.dblDbd);
-    wire ryl2Dbd = Nanod_r.ryl2db & (~ryIsAreg | Nanod_r.dblDbd);
+    wire wRyl2Abl_t4 = iNanoDec_t4.ryl2ab & ( rRyIsAreg_t4 | iNanoDec_t4.ablAbd);
+    wire wRyl2Abd_t4 = iNanoDec_t4.ryl2ab & (~rRyIsAreg_t4 | iNanoDec_t4.ablAbd);
+    wire wRyl2Dbl_t4 = iNanoDec_t4.ryl2db & ( rRyIsAreg_t4 | iNanoDec_t4.dblDbd);
+    wire wRyl2Dbd_t4 = iNanoDec_t4.ryl2db & (~rRyIsAreg_t4 | iNanoDec_t4.dblDbd);
 
-    wire rxl2Abl = Nanod_r.rxl2ab & ( rxIsAreg | Nanod_r.ablAbd);
-    wire rxl2Abd = Nanod_r.rxl2ab & (~rxIsAreg | Nanod_r.ablAbd);
-    wire rxl2Dbl = Nanod_r.rxl2db & ( rxIsAreg | Nanod_r.dblDbd);
-    wire rxl2Dbd = Nanod_r.rxl2db & (~rxIsAreg | Nanod_r.dblDbd);
+    wire wRxl2Abl_t4 = iNanoDec_t4.rxl2ab & ( rRxIsAreg_t4 | iNanoDec_t4.ablAbd);
+    wire wRxl2Abd_t4 = iNanoDec_t4.rxl2ab & (~rRxIsAreg_t4 | iNanoDec_t4.ablAbd);
+    wire wRxl2Dbl_t4 = iNanoDec_t4.rxl2db & ( rRxIsAreg_t4 | iNanoDec_t4.dblDbd);
+    wire wRxl2Dbd_t4 = iNanoDec_t4.rxl2db & (~rRxIsAreg_t4 | iNanoDec_t4.dblDbd);
 
     // Buses. Main mux
 
-    logic abhIdle, ablIdle, abdIdle;
-    logic dbhIdle, dblIdle, dbdIdle;
-
-    always_comb begin
-        {abhIdle, ablIdle, abdIdle} = 3'b000;
-        {dbhIdle, dblIdle, dbdIdle} = 3'b000;
-
+    
+    logic        wDbdIdle_t4;
+    logic [15:0] wDbdMux_t4;
+    logic        wDblIdle_t4;
+    logic [15:0] wDblMux_t4;
+    logic        wDbhIdle_t4;
+    logic [15:0] wDbhMux_t4;
+    
+    logic        wAbdIdle_t4;
+    logic [15:0] wAbdMux_t4;
+    logic        wAblIdle_t4;
+    logic [15:0] wAblMux_t4;
+    logic        wAbhIdle_t4;
+    logic [15:0] wAbhMux_t4;
+
+    always_comb begin : BUS_MUXES_T4
         unique case (1'b1)
-        ryl2Dbd:                dbdMux = regs68L[actualRy];
-        rxl2Dbd:                dbdMux = regs68L[actualRx];
-        Nanod_r.alue2Dbd:       dbdMux = alue;
-        Nanod_w.dbin2Dbd:       dbdMux = dbin;
-        Nanod_r.alu2Dbd:        dbdMux = aluOut;
-        Nanod_r.dcr2Dbd:        dbdMux = dcrOutput;
-        default: begin          dbdMux = 'X;    dbdIdle = 1'b1;             end
+            wRyl2Dbd_t4:          { wDbdIdle_t4, wDbdMux_t4 } = { 1'b0, regs68L[rActualRy_t4] };
+            wRxl2Dbd_t4:          { wDbdIdle_t4, wDbdMux_t4 } = { 1'b0, regs68L[rActualRx_t4] };
+            iNanoDec_t4.alue2Dbd: { wDbdIdle_t4, wDbdMux_t4 } = { 1'b0, alue };
+            iNanoDec_t4.dbin2Dbd: { wDbdIdle_t4, wDbdMux_t4 } = { 1'b0, wDbin_t4 };
+            iNanoDec_t4.alu2Dbd:  { wDbdIdle_t4, wDbdMux_t4 } = { 1'b0, aluOut };
+            iNanoDec_t4.dcr2Dbd:  { wDbdIdle_t4, wDbdMux_t4 } = { 1'b0, dcrOutput };
+            default:              { wDbdIdle_t4, wDbdMux_t4 } = { 1'b1, 16'h0000 };
         endcase
 
         unique case (1'b1)
-        rxl2Dbl:                dblMux = regs68L[actualRx];
-        ryl2Dbl:                dblMux = regs68L[actualRy];
-        Nanod_w.ftu2Dbl:        dblMux = ftu;
-        Nanod_w.au2Db:          dblMux = auReg[15:0];
-        Nanod_r.atl2Dbl:        dblMux = Atl;
-        Pcl2Dbl:                dblMux = PcL;
-        default: begin          dblMux = 'X;    dblIdle = 1'b1;             end
+            wRxl2Dbl_t4:          { wDblIdle_t4, wDblMux_t4 } = { 1'b0, regs68L[rActualRx_t4] };
+            wRyl2Dbl_t4:          { wDblIdle_t4, wDblMux_t4 } = { 1'b0, regs68L[rActualRy_t4] };
+            iNanoDec_t4.ftu2Dbl:  { wDblIdle_t4, wDblMux_t4 } = { 1'b0, iFtu_t3 };
+            iNanoDec_t4.au2Db:    { wDblIdle_t4, wDblMux_t4 } = { 1'b0, rAuReg_t3[15:0] };
+            iNanoDec_t4.atl2Dbl:  { wDblIdle_t4, wDblMux_t4 } = { 1'b0, rAtl_t3 };
+            rPcl2Dbl_t4:          { wDblIdle_t4, wDblMux_t4 } = { 1'b0, PcL };
+            default:              { wDblIdle_t4, wDblMux_t4 } = { 1'b1, 16'h0000 };
         endcase
 
         unique case (1'b1)
-        Nanod_r.rxh2dbh:        dbhMux = regs68H[actualRx];
-        Nanod_r.ryh2dbh:        dbhMux = regs68H[actualRy];
-        Nanod_w.au2Db:          dbhMux = auReg[31:16];
-        Nanod_r.ath2Dbh:        dbhMux = Ath;
-        Pch2Dbh:                dbhMux = PcH;
-        default: begin          dbhMux = 'X;    dbhIdle = 1'b1;             end
+            iNanoDec_t4.rxh2dbh:  { wDbhIdle_t4, wDbhMux_t4 } = { 1'b0, regs68H[rActualRx_t4] };
+            iNanoDec_t4.ryh2dbh:  { wDbhIdle_t4, wDbhMux_t4 } = { 1'b0, regs68H[rActualRy_t4] };
+            iNanoDec_t4.au2Db:    { wDbhIdle_t4, wDbhMux_t4 } = { 1'b0, rAuReg_t3[31:16] };
+            iNanoDec_t4.ath2Dbh:  { wDbhIdle_t4, wDbhMux_t4 } = { 1'b0, rAth_t3 };
+            rPch2Dbh_t4:          { wDbhIdle_t4, wDbhMux_t4 } = { 1'b0, PcH };
+            default:              { wDbhIdle_t4, wDbhMux_t4 } = { 1'b1, 16'h0000 };
         endcase
 
         unique case (1'b1)
-        ryl2Abd:                abdMux = regs68L[actualRy];
-        rxl2Abd:                abdMux = regs68L[actualRx];
-        Nanod_w.dbin2Abd:       abdMux = dbin;
-        Nanod_r.alu2Abd:        abdMux = aluOut;
-        default: begin          abdMux = 'X;    abdIdle = 1'b1;             end
+            wRyl2Abd_t4:          { wAbdIdle_t4, wAbdMux_t4 } = { 1'b0, regs68L[rActualRy_t4] };
+            wRxl2Abd_t4:          { wAbdIdle_t4, wAbdMux_t4 } = { 1'b0, regs68L[rActualRx_t4] };
+            iNanoDec_t4.dbin2Abd: { wAbdIdle_t4, wAbdMux_t4 } = { 1'b0, wDbin_t4 };
+            iNanoDec_t4.alu2Abd:  { wAbdIdle_t4, wAbdMux_t4 } = { 1'b0, aluOut };
+            default:              { wAbdIdle_t4, wAbdMux_t4 } = { 1'b1, 16'h0000 };
         endcase
 
         unique case (1'b1)
-        Pcl2Abl:                ablMux = PcL;
-        rxl2Abl:                ablMux = regs68L[actualRx];
-        ryl2Abl:                ablMux = regs68L[actualRy];
-        Nanod_w.ftu2Abl:        ablMux = ftu;
-        Nanod_w.au2Ab:          ablMux = auReg[15:0];
-        Nanod_r.aob2Ab:         ablMux = aob[15:0];
-        Nanod_r.atl2Abl:        ablMux = Atl;
-        default: begin          ablMux = 'X;    ablIdle = 1'b1;             end
+            rPcl2Abl_t4:          { wAblIdle_t4, wAblMux_t4 } = { 1'b0, PcL };
+            wRxl2Abl_t4:          { wAblIdle_t4, wAblMux_t4 } = { 1'b0, regs68L[rActualRx_t4] };
+            wRyl2Abl_t4:          { wAblIdle_t4, wAblMux_t4 } = { 1'b0, regs68L[rActualRy_t4] };
+            iNanoDec_t4.ftu2Abl:  { wAblIdle_t4, wAblMux_t4 } = { 1'b0, iFtu_t3 };
+            iNanoDec_t4.au2Ab:    { wAblIdle_t4, wAblMux_t4 } = { 1'b0, rAuReg_t3[15:0] };
+            iNanoDec_t4.aob2Ab:   { wAblIdle_t4, wAblMux_t4 } = { 1'b0, aob[15:0] };
+            iNanoDec_t4.atl2Abl:  { wAblIdle_t4, wAblMux_t4 } = { 1'b0, rAtl_t3 };
+            default:              { wAblIdle_t4, wAblMux_t4 } = { 1'b1, 16'h0000 };
         endcase
 
         unique case (1'b1)
-        Pch2Abh:                abhMux = PcH;
-        Nanod_r.rxh2abh:        abhMux = regs68H[actualRx];
-        Nanod_r.ryh2abh:        abhMux = regs68H[actualRy];
-        Nanod_w.au2Ab:          abhMux = auReg[31:16];
-        Nanod_r.aob2Ab:         abhMux = aob[31:16];
-        Nanod_r.ath2Abh:        abhMux = Ath;
-        default: begin          abhMux = 'X;    abhIdle = 1'b1;             end
+            rPch2Abh_t4:          { wAbhIdle_t4, wAbhMux_t4 } = { 1'b0, PcH };
+            iNanoDec_t4.rxh2abh:  { wAbhIdle_t4, wAbhMux_t4 } = { 1'b0, regs68H[rActualRx_t4] };
+            iNanoDec_t4.ryh2abh:  { wAbhIdle_t4, wAbhMux_t4 } = { 1'b0, regs68H[rActualRy_t4] };
+            iNanoDec_t4.au2Ab:    { wAbhIdle_t4, wAbhMux_t4 } = { 1'b0, rAuReg_t3[31:16] };
+            iNanoDec_t4.aob2Ab:   { wAbhIdle_t4, wAbhMux_t4 } = { 1'b0, aob[31:16] };
+            iNanoDec_t4.ath2Abh:  { wAbhIdle_t4, wAbhMux_t4 } = { 1'b0, rAth_t3 };
+            default:              { wAbhIdle_t4, wAbhMux_t4 } = { 1'b1, 16'h0000 };
         endcase
 
     end
@@ -1442,8 +1520,8 @@ localparam
 
         // Register first level mux at T1
         if (enT1) begin
-            {preAbh, preAbl, preAbd} <= { abhMux, ablMux, abdMux};
-            {preDbh, preDbl, preDbd} <= { dbhMux, dblMux, dbdMux};
+            {preAbh, preAbl, preAbd} <= { wAbhMux_t4, wAblMux_t4, wAbdMux_t4};
+            {preDbh, preDbl, preDbd} <= { wDbhMux_t4, wDblMux_t4, wDbdMux_t4};
         end
 
         // Process bus interconnection at T2. Many combinations only used on DIV
@@ -1451,41 +1529,41 @@ localparam
         // In some cases this is not true and the segment is really idle without any destination. But then it doesn't matter.
 
         if (enT2) begin
-            if (Nanod_r.extAbh)
-                Abh <= { 16{ ablIdle ? preAbd[15] : preAbl[15] }};
-            else if (abhIdle)
-                Abh <= ablIdle ? preAbd : preAbl;
+            if (iNanoDec_t4.extAbh)
+                rAbh_t2 <= { 16{ wAblIdle_t4 ? preAbd[15] : preAbl[15] }};
+            else if (wAbhIdle_t4)
+                rAbh_t2 <= wAblIdle_t4 ? preAbd : preAbl;
             else
-                Abh <= preAbh;
+                rAbh_t2 <= preAbh;
 
-            if (~ablIdle)
-                Abl <= preAbl;
+            if (~wAblIdle_t4)
+                rAbl_t2 <= preAbl;
             else
-                Abl <= Nanod_r.ablAbh ? preAbh : preAbd;
+                rAbl_t2 <= iNanoDec_t4.ablAbh ? preAbh : preAbd;
 
-            Abd <= ~abdIdle ? preAbd : ablIdle ? preAbh : preAbl;
+            rAbd_t2 <= ~wAbdIdle_t4 ? preAbd : wAblIdle_t4 ? preAbh : preAbl;
 
-            if (Nanod_r.extDbh)
-                Dbh <= { 16{ dblIdle ? preDbd[15] : preDbl[15] }};
-            else if (dbhIdle)
-                Dbh <= dblIdle ? preDbd : preDbl;
+            if (iNanoDec_t4.extDbh)
+                rDbh_t2 <= { 16{ wDblIdle_t4 ? preDbd[15] : preDbl[15] }};
+            else if (wDbhIdle_t4)
+                rDbh_t2 <= wDblIdle_t4 ? preDbd : preDbl;
             else
-                Dbh <= preDbh;
+                rDbh_t2 <= preDbh;
 
-            if (~dblIdle)
-                Dbl <= preDbl;
+            if (~wDblIdle_t4)
+                rDbl_t2 <= preDbl;
             else
-                Dbl <= Nanod_r.dblDbh ? preDbh : preDbd;
+                rDbl_t2 <= iNanoDec_t4.dblDbh ? preDbh : preDbd;
 
-            Dbd <= ~dbdIdle ? preDbd: dblIdle ? preDbh : preDbl;
+            rDbd_t2 <= ~wDbdIdle_t4 ? preDbd: wDblIdle_t4 ? preDbh : preDbl;
 
             /*
-            Dbl <= dblMux;
-            Dbh <= dbhMux;
-            Abd <= abdMux;
-            Dbd <= dbdMux;
-            Abh <= abhMux;
-            Abl <= ablMux;
+            rDbl_t2 <= wDblMux_t4;
+            rDbh_t2 <= wDbhMux_t4;
+            rAbd_t2 <= wAbdMux_t4;
+            rDbd_t2 <= wDbdMux_t4;
+            rAbh_t2 <= wAbhMux_t4;
+            rAbl_t2 <= wAblMux_t4;
             */
         end
     end
@@ -1500,18 +1578,18 @@ localparam
 
     // We need to take directly from first level muxes that are updated and T1
 
-    wire au2Aob = Nanod_w.au2Aob | (Nanod_w.au2Db & Nanod_w.db2Aob);
+    wire au2Aob = iNanoDec_t3.au2Aob | (iNanoDec_t3.au2Db & iNanoDec_t3.db2Aob);
 
     always_ff @(posedge clk) begin
         // UNIQUE IF !
 
         if (enT1 & au2Aob)      // From AU we do can on T1
-            aob <= auReg;
+            aob <= rAuReg_t3;
         else if (enT2) begin
-            if (Nanod_w.db2Aob)
-                aob <= { preDbh, ~dblIdle ? preDbl : preDbd};
-            else if (Nanod_w.ab2Aob)
-                aob <= { preAbh, ~ablIdle ? preAbl : preAbd};
+            if (iNanoDec_t3.db2Aob)
+                aob <= { preDbh, ~wDblIdle_t4 ? preDbl : preDbd};
+            else if (iNanoDec_t3.ab2Aob)
+                aob <= { preAbh, ~wAblIdle_t4 ? preAbl : preAbd};
         end
     end
 
@@ -1523,18 +1601,18 @@ localparam
 
     // `ifdef ALW_COMB_BUG
     // Old Modelsim bug. Doesn't update ouput always. Need excplicit sensitivity list !?
-    // always @( Nanod_r.auCntrl) begin
+    // always @( iNanoDec_t4.auCntrl) begin
 
     always_comb begin
-        unique case (Nanod_r.auCntrl)
+        unique case (iNanoDec_t4.auCntrl)
             3'b000:  auInpMux = 32'h00000000;
-            3'b001:  auInpMux = byteNotSpAlign | Nanod_r.noSpAlign ? 32'h00000001 : 32'h00000002; // +1/+2
+            3'b001:  auInpMux = byteNotSpAlign | iNanoDec_t4.noSpAlign ? 32'h00000001 : 32'h00000002; // +1/+2
             3'b010:  auInpMux = 32'hFFFFFFFC;
-            3'b011:  auInpMux = { Abh, Abl};
+            3'b011:  auInpMux = { rAbh_t2, rAbl_t2};
             3'b100:  auInpMux = 32'h00000002;
             3'b101:  auInpMux = 32'h00000004;
             3'b110:  auInpMux = 32'hFFFFFFFE;
-            3'b111:  auInpMux = byteNotSpAlign | Nanod_r.noSpAlign ? 32'hFFFFFFFF : 32'hFFFFFFFE; // -1/-2
+            3'b111:  auInpMux = byteNotSpAlign | iNanoDec_t4.noSpAlign ? 32'hFFFFFFFF : 32'hFFFFFFFE; // -1/-2
             default: auInpMux = 32'h00000000;
         endcase
     end
@@ -1545,116 +1623,131 @@ localparam
 
 // synthesis translate_off
     `define SIMULBUGX32 1
-    wire [16:0] aulow = Dbl + auInpMux[15:0];
-    wire [31:0] auResult = {Dbh + auInpMux[31:16] + {15'b0, aulow[16]}, aulow[15:0]};
+    wire [16:0] aulow = rDbl_t2 + auInpMux[15:0];
+    wire [31:0] auResult = {rDbh_t2 + auInpMux[31:16] + {15'b0, aulow[16]}, aulow[15:0]};
 // synthesis translate_on
 
     always_ff @(posedge clk) begin
 
         if (Clks.pwrUp)
-            auReg <= '0;
-        else if (enT3 & Nanod_r.auClkEn)
+            rAuReg_t3 <= 32'h00000000;
+        else if (enT3 & iNanoDec_t4.auClkEn)
             `ifdef SIMULBUGX32
-                auReg <= auResult;
+                rAuReg_t3 <= auResult;
             `else
-                auReg <= { Dbh, Dbl } + auInpMux;
+                rAuReg_t3 <= { rDbh_t2, rDbl_t2 } + auInpMux;
             `endif
     end
 
 
     // Main A/D registers
+    
+    wire [15:0] wRxh_t2 = (iNanoDec_t4.dbh2rxh) ? rDbh_t2 : rAbh_t2;
+    wire [15:0] wRxl_t2 = (rRyIsAreg_t4)
+                        ? ((iNanoDec_t4.dbl2rxl) ? rDbl_t2 : rAbl_t2)
+                        : ((iNanoDec_t4.dbl2rxl) ? rDbd_t2 : rAbd_t2);
+    
+    wire [15:0] wRyh_t2 = (iNanoDec_t4.dbh2ryh) ? rDbh_t2 : rAbh_t2;
+    wire [15:0] wRyl_t2 = (rRyIsAreg_t4)
+                        ? ((iNanoDec_t4.dbl2ryl) ? rDbl_t2 : rAbl_t2)
+                        : ((iNanoDec_t4.dbl2ryl) ? rDbd_t2 : rAbd_t2);
+
+    always_ff @(posedge clk) begin : REGS_WRITE_T3
+        reg [2:0] vRxWEna;
+        reg [2:0] vRyWEna;
+        
+        vRxWEna[2] <= iNanoDec_t4.dbh2rxh | iNanoDec_t4.abh2rxh;
+        vRxWEna[1] <= iNanoDec_t4.dbl2rxl | iNanoDec_t4.abl2rxl & (~rAbdIsByte_t4 | rRxIsAreg_t4);
+        vRxWEna[0] <= iNanoDec_t4.dbl2rxl | iNanoDec_t4.abl2rxl;
 
-    always_ff @(posedge clk) begin
-
+        vRyWEna[2] <= iNanoDec_t4.dbh2ryh | iNanoDec_t4.abh2ryh;
+        vRyWEna[1] <= iNanoDec_t4.dbl2ryl | iNanoDec_t4.abl2ryl & (~rAbdIsByte_t4 | rRyIsAreg_t4);
+        vRyWEna[0] <= iNanoDec_t4.dbl2ryl | iNanoDec_t4.abl2ryl;
+        
         if (enT3) begin
-            if (Nanod_r.dbl2rxl | Nanod_r.abl2rxl) begin
-                if (~rxIsAreg) begin
-                    if (Nanod_r.dbl2rxl)        regs68L[actualRx] <= Dbd;
-                    else if (abdIsByte)         regs68L[actualRx][7:0] <= Abd[7:0];
-                    else                        regs68L[actualRx] <= Abd;
-                end
-                else
-                    regs68L[actualRx] <= Nanod_r.dbl2rxl ? Dbl : Abl;
-            end
-
-            if (Nanod_r.dbl2ryl | Nanod_r.abl2ryl) begin
-                if (~ryIsAreg) begin
-                    if (Nanod_r.dbl2ryl)        regs68L[actualRy] <= Dbd;
-                    else if (abdIsByte)         regs68L[actualRy][7:0] <= Abd[7:0];
-                    else                        regs68L[actualRy] <= Abd;
-                end
-                else
-                    regs68L[actualRy] <= Nanod_r.dbl2ryl ? Dbl : Abl;
-            end
-
-            // High registers are easier. Both A & D on the same buses, and not byte ops.
-            if (Nanod_r.dbh2rxh | Nanod_r.abh2rxh)
-                regs68H[actualRx] <= Nanod_r.dbh2rxh ? Dbh : Abh;
-            if (Nanod_r.dbh2ryh | Nanod_r.abh2ryh)
-                regs68H[actualRy] <= Nanod_r.dbh2ryh ? Dbh : Abh;
-
+            if (vRxWEna[2]) regs68H[rActualRx_t4][15:0] <= wRxh_t2[15:0];
+            if (vRxWEna[1]) regs68L[rActualRx_t4][15:8] <= wRxl_t2[15:8];
+            if (vRxWEna[0]) regs68L[rActualRx_t4][ 7:0] <= wRxl_t2[ 7:0];
+            
+            if (vRyWEna[2]) regs68H[rActualRy_t4][15:0] <= wRyh_t2[15:0];
+            if (vRyWEna[1]) regs68L[rActualRy_t4][15:8] <= wRyl_t2[15:8];
+            if (vRyWEna[0]) regs68L[rActualRy_t4][ 7:0] <= wRyl_t2[ 7:0];
+            `ifdef verilator3
+            if ((|vRxWEna) & (|vRyWEna)) $display("68k regs : concurrent write !!");
+            `endif
         end
     end
 
     // PC & AT
-    reg dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl;
-
+    reg  rDbl2Pcl_t4;
+    reg  rDbh2Pch_t4;
+    reg  rAbh2Pch_t4;
+    reg  rAbl2Pcl_t4;
+
+    reg  rPcl2Dbl_t4;
+    reg  rPch2Dbh_t4;
+    reg  rPcl2Abl_t4;
+    reg  rPch2Abh_t4;
+    
     always_ff @(posedge clk) begin
     
         if (Clks.extReset) begin
-            { dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl } <= '0;
+            rDbl2Pcl_t4 <= 1'b0;
+            rDbh2Pch_t4 <= 1'b0;
+            rAbl2Pcl_t4 <= 1'b0;
+            rAbh2Pch_t4 <= 1'b0;
 
-            Pcl2Dbl <= 1'b0;
-            Pch2Dbh <= 1'b0;
-            Pcl2Abl <= 1'b0;
-            Pch2Abh <= 1'b0;
+            rPcl2Dbl_t4 <= 1'b0;
+            rPch2Dbh_t4 <= 1'b0;
+            rPcl2Abl_t4 <= 1'b0;
+            rPch2Abh_t4 <= 1'b0;
         end
-        else if (enT4) begin                // Must latch on T4 !
-            dbl2Pcl <= Nanod_w.dbl2reg & Nanod_w.pcldbl;
-            dbh2Pch <= Nanod_w.dbh2reg & Nanod_w.pchdbh;
-            abh2Pch <= Nanod_w.abh2reg & Nanod_w.pchabh;
-            abl2Pcl <= Nanod_w.abl2reg & Nanod_w.pclabl;
+        else if (enT4) begin // Must latch on T4 !
+            rDbl2Pcl_t4 <= iNanoDec_t3.dbl2reg & iNanoDec_t3.pcldbl;
+            rDbh2Pch_t4 <= iNanoDec_t3.dbh2reg & iNanoDec_t3.pchdbh;
+            rAbh2Pch_t4 <= iNanoDec_t3.abh2reg & iNanoDec_t3.pchabh;
+            rAbl2Pcl_t4 <= iNanoDec_t3.abl2reg & iNanoDec_t3.pclabl;
 
-            Pcl2Dbl <= Nanod_w.reg2dbl & Nanod_w.pcldbl;
-            Pch2Dbh <= Nanod_w.reg2dbh & Nanod_w.pchdbh;
-            Pcl2Abl <= Nanod_w.reg2abl & Nanod_w.pclabl;
-            Pch2Abh <= Nanod_w.reg2abh & Nanod_w.pchabh;
+            rPcl2Dbl_t4 <= iNanoDec_t3.reg2dbl & iNanoDec_t3.pcldbl;
+            rPch2Dbh_t4 <= iNanoDec_t3.reg2dbh & iNanoDec_t3.pchdbh;
+            rPcl2Abl_t4 <= iNanoDec_t3.reg2abl & iNanoDec_t3.pclabl;
+            rPch2Abh_t4 <= iNanoDec_t3.reg2abh & iNanoDec_t3.pchabh;
         end
 
         // Unique IF !!!
-        if (enT1 & Nanod_w.au2Pc)
-            PcL <= auReg[15:0];
+        if (enT1 & iNanoDec_t3.au2Pc)
+            PcL <= rAuReg_t3[15:0];
         else if (enT3) begin
-            if (dbl2Pcl)
-                PcL <= Dbl;
-            else if (abl2Pcl)
-                PcL <= Abl;
+            if (rDbl2Pcl_t4)
+                PcL <= rDbl_t2;
+            else if (rAbl2Pcl_t4)
+                PcL <= rAbl_t2;
         end
 
         // Unique IF !!!
-        if (enT1 & Nanod_w.au2Pc)
-            PcH <= auReg[31:16];
+        if (enT1 & iNanoDec_t3.au2Pc)
+            PcH <= rAuReg_t3[31:16];
         else if (enT3) begin
-            if (dbh2Pch)
-                PcH <= Dbh;
-            else if (abh2Pch)
-                PcH <= Abh;
+            if (rDbh2Pch_t4)
+                PcH <= rDbh_t2;
+            else if (rAbh2Pch_t4)
+                PcH <= rAbh_t2;
         end
 
         // Unique IF !!!
         if (enT3) begin
-            if (Nanod_r.dbl2Atl)
-                Atl <= Dbl;
-            else if (Nanod_r.abl2Atl)
-                Atl <= Abl;
+            if (iNanoDec_t4.dbl2Atl)
+                rAtl_t3 <= rDbl_t2;
+            else if (iNanoDec_t4.abl2Atl)
+                rAtl_t3 <= rAbl_t2;
         end
 
         // Unique IF !!!
         if (enT3) begin
-            if (Nanod_r.abh2Ath)
-                Ath <= Abh;
-            else if (Nanod_r.dbh2Ath)
-                Ath <= Dbh;
+            if (iNanoDec_t4.abh2Ath)
+                rAth_t3 <= rAbh_t2;
+            else if (iNanoDec_t4.dbh2Ath)
+                rAth_t3 <= rDbh_t2;
         end
 
     end
@@ -1673,9 +1766,9 @@ localparam
     
         // Cheating: PREN always loaded from DBIN
         // Must be on T1 to branch earlier if reg mask is empty!
-        if (enT1 & Nanod_w.abl2Pren)
-            prenLatch <= dbin;
-        else if (enT3 & Nanod_w.updPren) begin
+        if (enT1 & iNanoDec_t4.abl2Pren)
+            prenLatch <= wDbin_t4;
+        else if (enT3 & iNanoDec_t4.updPren) begin
             prenLatch [prHbit] <= 1'b0;
             movemRx <= Irdecod.movemPreDecr ? ~prHbit : prHbit;
         end
@@ -1684,44 +1777,44 @@ localparam
     // DCR
     wire [15:0] dcrCode;
 
-    wire [3:0] dcrInput = abdIsByte ? { 1'b0, Abd[ 2:0]} : Abd[ 3:0];
+    wire [3:0] dcrInput = rAbdIsByte_t4 ? { 1'b0, rAbd_t2[ 2:0]} : rAbd_t2[ 3:0];
     onehotEncoder4 dcrDecoder( .bin( dcrInput), .bitMap( dcrCode));
 
     always_ff @(posedge clk) begin
 
         if (Clks.pwrUp)
             dcr4 <= '0;
-        else if (enT3 & Nanod_r.abd2Dcr) begin
+        else if (enT3 & iNanoDec_t4.abd2Dcr) begin
             dcrOutput <= dcrCode;
-            dcr4 <= Abd[4];
+            dcr4 <= rAbd_t2[4];
         end
     end
 
     // ALUB
-    reg [15:0] alub;
+    reg [15:0] rAlub_t3;
 
     always_ff @(posedge clk) begin
 
         if (enT3) begin
             // UNIQUE IF !!
-            if (Nanod_r.dbd2Alub)
-                alub <= Dbd;
-            else if (Nanod_r.abd2Alub)
-                alub <= Abd;                // abdIsByte affects this !!??
+            if (iNanoDec_t4.dbd2Alub)
+                rAlub_t3 <= rDbd_t2;
+            else if (iNanoDec_t4.abd2Alub)
+                rAlub_t3 <= rAbd_t2;                // rAbdIsByte_t4 affects this !!??
         end
     end
 
-    wire alueClkEn = enT3 & Nanod_r.dbd2Alue;
+    wire alueClkEn = enT3 & iNanoDec_t4.dbd2Alue;
 
     // DOB/DBIN/IRC
 
     logic [15:0] dobInput;
-    wire dobIdle = (~| Nanod_r.dobCtrl);
+    wire dobIdle = (~| iNanoDec_t4.dobCtrl);
 
     always_comb begin
-        unique case (Nanod_r.dobCtrl)
-        NANO_DOB_ADB:       dobInput = Abd;
-        NANO_DOB_DBD:       dobInput = Dbd;
+        unique case (iNanoDec_t4.dobCtrl)
+        NANO_DOB_ADB:       dobInput = rAbd_t2;
+        NANO_DOB_DBD:       dobInput = rDbd_t2;
         NANO_DOB_ALU:       dobInput = aluOut;
         default:            dobInput = 'X;
         endcase
@@ -1730,25 +1823,35 @@ localparam
     dataIo U_dataIo
     (
         .clk, .Clks, .enT1, .enT2, .enT3, .enT4,
-        .Nanod_r, .Nanod_w, .Irdecod,
+        .iNanoDec_t4 (iNanoDec_t4),
+        .iNanoDec_t3 (iNanoDec_t3),
+        .Irdecod,
         .iEdb, .dobIdle, .dobInput, .aob0,
-        .Irc, .dbin, .oEdb
+        .oIrc_t4     (oIrc_t4),
+        .oDbin_t4    (wDbin_t4),
+        .oEdb
     );
 
     fx68kAlu U_fx68kAlu
     (
         .clk, .pwrUp( Clks.pwrUp), .enT1, .enT3, .enT4,
         .ird         (Ird),
-        .aluColumn   (Nanod_w.aluColumn),
-        .aluDataCtrl (Nanod_w.aluDctrl),
-        .aluAddrCtrl (Nanod_w.aluActrl),
-        .ftu2Ccr     (Nanod_w.ftu2Ccr),
-        .init        (Nanod_w.aluInit),
-        .finish      (Nanod_w.aluFinish),
+        .aluColumn   (iNanoDec_t3.aluColumn),
+        .aluDataCtrl (iNanoDec_t3.aluDctrl),
+        .aluAddrCtrl (iNanoDec_t3.aluActrl),
+        .ftu2Ccr     (iNanoDec_t3.ftu2Ccr),
+        .init        (iNanoDec_t3.aluInit),
+        .finish      (iNanoDec_t3.aluFinish),
         .aluIsByte   (Irdecod.isByte),
-        .alub, .ftu, .alueClkEn, .alue,
-        .iDataBus( Dbd), .iAddrBus(Abd),
-        .ze, .aluOut, .ccr
+        .alub        (rAlub_t3),
+        .ftu         (iFtu_t3), 
+        .alueClkEn,
+        .iDataBus    (rDbd_t2),
+        .iAddrBus    (rAbd_t2),
+        .ze          (ze),
+        .alue        (alue),
+        .oAluOut     (aluOut),
+        .oCcr        (ccr)
     );
 
 endmodule
@@ -1770,8 +1873,8 @@ module dataIo
     input               enT2,
     input               enT3,
     input               enT4,
-    input     s_nanod_r Nanod_r,
-    input     s_nanod_w Nanod_w,
+    input     s_nanod_r iNanoDec_t4,
+    input     s_nanod_w iNanoDec_t3,
     input     s_irdecod Irdecod,
     input        [15:0] iEdb,
     input               aob0,
@@ -1779,8 +1882,8 @@ module dataIo
     input               dobIdle,
     input        [15:0] dobInput,
 
-    output logic [15:0] Irc,
-    output logic [15:0] dbin,
+    output       [15:0] oIrc_t4,
+    output       [15:0] oDbin_t4,
     output logic [15:0] oEdb
 );
 
@@ -1795,6 +1898,11 @@ module dataIo
     reg xToDbin, xToIrc;
     reg dbinNoLow, dbinNoHigh;
     reg byteMux, isByte_T4;
+    
+    // Instruction register (IRC)
+    reg [15:0] rIrc_t4;
+    // Data register (DBIN)
+    reg [15:0] rDbin_t4;
 
     always_ff @(posedge clk) begin
 
@@ -1807,9 +1915,9 @@ module dataIo
             isByte_T4 <= Irdecod.isByte;    // Includes MOVEP from mem, we could OR it here
 
         if (enT3) begin
-            dbinNoHigh <= Nanod_w.noHighByte;
-            dbinNoLow  <= Nanod_w.noLowByte;
-            byteMux    <= Nanod_w.busByte & isByte_T4 & ~aob0;
+            dbinNoHigh <= iNanoDec_t3.noHighByte;
+            dbinNoLow  <= iNanoDec_t3.noLowByte;
+            byteMux    <= iNanoDec_t3.busByte & isByte_T4 & ~aob0;
         end
 
         if (enT1) begin
@@ -1818,23 +1926,26 @@ module dataIo
             xToIrc  <= 1'b0;
         end
         else if (enT3) begin
-            xToDbin <= Nanod_r.todbin;
-            xToIrc  <= Nanod_r.toIrc;
+            xToDbin <= iNanoDec_t4.todbin;
+            xToIrc  <= iNanoDec_t4.toIrc;
         end
 
         // Capture on T4 of the next ucycle
         // If there are wait states, we keep capturing every PHI2 until the next T1
 
         if (xToIrc & Clks.enPhi2)
-            Irc <= iEdb;
+            rIrc_t4 <= iEdb;
         if (xToDbin & Clks.enPhi2) begin
             // Original connects both halves of EDB.
             if (~dbinNoLow)
-                dbin[ 7:0] <= byteMux ? iEdb[ 15:8] : iEdb[7:0];
+                rDbin_t4[ 7:0] <= byteMux ? iEdb[ 15:8] : iEdb[7:0];
             if (~dbinNoHigh)
-                dbin[ 15:8] <= ~byteMux & dbinNoLow ? iEdb[ 7:0] : iEdb[ 15:8];
+                rDbin_t4[15:8] <= ~byteMux & dbinNoLow ? iEdb[ 7:0] : iEdb[ 15:8];
         end
     end
+    
+    assign oIrc_t4  = rIrc_t4;
+    assign oDbin_t4 = rDbin_t4;
 
     // DOB
     logic byteCycle;
@@ -1847,12 +1958,12 @@ module dataIo
         // Wait states don't affect DOB operation that is done at the start of the bus cycle.
 
         if (enT4)
-            byteCycle <= Nanod_w.busByte & Irdecod.isByte;        // busIsByte but not MOVEP
+            byteCycle <= iNanoDec_t3.busByte & Irdecod.isByte;        // busIsByte but not MOVEP
 
         // Originally byte low/high interconnect is done at EDB, not at DOB.
         if (enT3 & ~dobIdle) begin
-            dob[7:0] <= Nanod_w.noLowByte ? dobInput[15:8] : dobInput[ 7:0];
-            dob[15:8] <= (byteCycle | Nanod_w.noHighByte) ? dobInput[ 7:0] : dobInput[15:8];
+            dob[7:0] <= iNanoDec_t3.noLowByte ? dobInput[15:8] : dobInput[ 7:0];
+            dob[15:8] <= (byteCycle | iNanoDec_t3.noHighByte) ? dobInput[ 7:0] : dobInput[15:8];
         end
     end
     assign oEdb = dob;
@@ -1870,29 +1981,27 @@ endmodule
 
 module uaddrDecode
 (
-    input             [15:0] opcode,
-    input             [15:0] opline,
-    input              [3:0] ea1,
-    input              [3:0] ea2,
-    output [UADDR_WIDTH-1:0] a1,
-    output [UADDR_WIDTH-1:0] a2,
-    output [UADDR_WIDTH-1:0] a3,
-    output logic             isPriv,
-    output logic             isIllegal,
-    output logic             isLineA,
-    output logic             isLineF
+    input             [15:0] iOpCode_t1,
+    input             [15:0] iOpLine_t1,
+    input              [3:0] iEA1_t1,
+    input              [3:0] iEA2_t1,
+    output [UADDR_WIDTH-1:0] oPlaA1_t1,
+    output [UADDR_WIDTH-1:0] oPlaA2_t1,
+    output [UADDR_WIDTH-1:0] oPlaA3_t1,
+    output logic             oIsPriv_t1,
+    output logic             oIsIllegal_t1
 );
 
     uaddrPla U_uaddrPla
     (
-        .movEa    (ea2),
-        .col      (ea1),
-        .opcode   (opcode),
-        .lineBmap (opline),
-        .palIll   (isIllegal),
-        .plaA1    (a1),
-        .plaA2    (a2),
-        .plaA3    (a3)
+        .movEa    (iEA2_t1),
+        .col      (iEA1_t1),
+        .opcode   (iOpCode_t1),
+        .lineBmap (iOpLine_t1),
+        .plaIll   (oIsIllegal_t1),
+        .plaA1    (oPlaA1_t1),
+        .plaA2    (oPlaA2_t1),
+        .plaA3    (oPlaA3_t1)
     );
 
     /*
@@ -1905,30 +2014,27 @@ module uaddrDecode
     STOP
     RTE
     */
-
+    
     always_comb begin
         unique case (1'b1)
 
             // ANDI/EORI/ORI SR
-            opline[0]:
-                isPriv = ((opcode[11:0] & 12'h5FF) == 12'h07C) ? 1'b1 : 1'b0;
+            iOpLine_t1[0]:
+                oIsPriv_t1 = ((iOpCode_t1[11:0] & 12'h5FF) == 12'h07C) ? 1'b1 : 1'b0;
 
-            opline[4]:
-                isPriv = ((opcode[11:0] & 12'hFC0) == 12'h6C0) // MOVE to SR
-                      || ((opcode[11:0] & 12'hFF0) == 12'hE60) // MOVE to/from USP
-                      || ((opcode[11:0] & 12'hFFF) == 12'hE70) // RESET
-                      || ((opcode[11:0] & 12'hFFF) == 12'hE72) // STOP
-                      || ((opcode[11:0] & 12'hFFF) == 12'hE73) // RTE
-                      ? 1'b1 : 1'b0;
+            iOpLine_t1[4]:
+                oIsPriv_t1 = ((iOpCode_t1[11:0] & 12'hFC0) == 12'h6C0) // MOVE to SR
+                          || ((iOpCode_t1[11:0] & 12'hFF0) == 12'hE60) // MOVE to/from USP
+                          || ((iOpCode_t1[11:0] & 12'hFFF) == 12'hE70) // RESET
+                          || ((iOpCode_t1[11:0] & 12'hFFF) == 12'hE72) // STOP
+                          || ((iOpCode_t1[11:0] & 12'hFFF) == 12'hE73) // RTE
+                          ? 1'b1 : 1'b0;
 
             default:
-                isPriv = 1'b0;
+                oIsPriv_t1 = 1'b0;
         endcase
     end
 
-    assign isLineA = opline[4'hA];
-    assign isLineF = opline[4'hF];
-
 endmodule
 
 // bin to one-hot, 4 bits to 16-bit bitmap
@@ -1994,7 +2100,7 @@ module sequencer
     input                   clk,
     input            s_clks Clks,
     input                   enT3,
-    input  [UROM_WIDTH-1:0] microLatch,
+    input  [UROM_WIDTH-1:0] iMicroLatch_t3,
     input                   A0Err,
     input                   BerrA,
     input                   busAddrErr,
@@ -2036,7 +2142,7 @@ module sequencer
     // word type I: 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
     // NMA :        .. .. 09 08 01 00 05 04 03 02 07 06 .. .. .. .. ..
 
-    wire [UADDR_WIDTH-1:0] dbNma = { microLatch[ 14:13], microLatch[ 6:5], microLatch[ 10:7], microLatch[ 12:11]};
+    wire [UADDR_WIDTH-1:0] dbNma = { iMicroLatch_t3[ 14:13], iMicroLatch_t3[ 6:5], iMicroLatch_t3[ 10:7], iMicroLatch_t3[ 12:11]};
 
     // Group 0 exception.
     // Separated block from regular NMA. Otherwise simulation might depend on order of assigments.
@@ -2055,10 +2161,10 @@ module sequencer
 
     always_comb begin
         // Format II (conditional) or I (direct branch)
-        if (microLatch[1])
-            uNma = { microLatch[ 14:13], c0c1, microLatch[ 10:7], microLatch[ 12:11]};
+        if (iMicroLatch_t3[1])
+            uNma = { iMicroLatch_t3[ 14:13], c0c1, iMicroLatch_t3[ 10:7], iMicroLatch_t3[ 12:11]};
         else
-            case (microLatch[ 3:2])
+            case (iMicroLatch_t3[ 3:2])
             0:   uNma = dbNma;   // DB
             1:   uNma = A0Sel ? grp1Nma : a1;
             2:   uNma = a2;
@@ -2075,7 +2181,7 @@ module sequencer
     wire [1:0] nv  = { psw[ NF], psw[ VF]};
 
     logic ccTest;
-    wire [4:0] cbc = microLatch[ 6:2];          // CBC bits
+    wire [4:0] cbc = iMicroLatch_t3[ 6:2];          // CBC bits
 
     always_comb begin
         unique case (cbc)
@@ -2141,7 +2247,7 @@ module sequencer
             2'b10:  c0c1 = 'b11;
             // 'hx1 result 00/01 depending on condition 0e/1e
             2'b01,2'b11:
-                    c0c1 = { 1'b0, microLatch[ 6]};
+                    c0c1 = { 1'b0, iMicroLatch_t3[ 6]};
             endcase
 
         default:                c0c1 = 'X;
@@ -2179,8 +2285,8 @@ module sequencer
     wire grp1LatchEn, grp0LatchEn;
 
     // Originally control signals latched on T4. Then exception latches updated on T3
-    assign grp1LatchEn = microLatch[0] & (microLatch[1] | !microLatch[4]);
-    assign grp0LatchEn = microLatch[4] & !microLatch[1];
+    assign grp1LatchEn = iMicroLatch_t3[0] & (iMicroLatch_t3[1] | !iMicroLatch_t3[4]);
+    assign grp0LatchEn = iMicroLatch_t3[4] & !iMicroLatch_t3[1];
 
     assign inGrp0Exc = rExcRst | rExcBusErr | rExcAdrErr;
 
@@ -2198,12 +2304,12 @@ module sequencer
         // Trace pending updated on T3 at the start of the instruction
         // Interrupt pending on T2
         if (grp1LatchEn & enT3) begin
-            rTrace <= Tpend;
+            rTrace     <= Tpend;
             rInterrupt <= intPend;
-            rIllegal <= isIllegal & ~isLineA & ~isLineF;
-            rLineA <= isLineA;
-            rLineF <= isLineF;
-            rPriv <= isPriv & !psw[ SF];
+            rIllegal   <= isIllegal & ~isLineA & ~isLineF;
+            rLineA     <= isLineA;
+            rLineF     <= isLineF;
+            rPriv      <= isPriv & ~psw[SF];
         end
     end
 
diff --git a/fx68kAlu.sv b/fx68kAlu.sv
index d846158..520c6b0 100644
--- a/fx68kAlu.sv
+++ b/fx68kAlu.sv
@@ -52,8 +52,9 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     input [15:0] iDataBus, input [15:0] iAddrBus,
     output ze,
     output reg [15:0] alue,
-    output reg [7:0] ccr,
-    output [15:0] aluOut);
+    output     [15:0] oAluOut,
+    output      [7:0] oCcr
+);
 
 
 `define ALU_ROW_01      16'h0002
@@ -76,10 +77,15 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     // Bit positions for flags in CCR
     localparam CF = 0, VF = 1, ZF = 2, NF = 3, XF = 4;
 
-    reg [15:0] aluLatch;
-    reg  [7:0] addLatch;
-    reg [4:0] pswCcr;
-    reg [4:0] ccrCore;
+    // ALU result latch
+    reg [15:0] rAluLatch_t3;
+    // Adder result latch for BCD
+    reg  [7:0] rAddLatch_t3;
+    // Half carry latch for BCD
+    reg        rAddHCarry_t3;
+    
+    reg  [4:0] rPswCcr_t3;
+    reg  [4:0] rCcrCore_t3;
 
     logic [15:0] result;
     logic [4:0] ccrTemp;
@@ -89,8 +95,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     logic addHcarry;
     logic addCout, addOv;
 
-    assign aluOut = aluLatch;
-    assign ze = ~ccrCore[ ZF];      // Check polarity !!!
+    assign ze = ~rCcrCore_t3[ZF];      // Check polarity !!!
 
     //
     // Control
@@ -126,8 +131,6 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     wire shftIsDiv = row[1];
 
     wire [31:0] shftResult;
-    reg [7:0] bcdLatch;
-    reg bcdCarry, bcdOverf;
 
     reg isLong;
     reg rIrd8;
@@ -157,17 +160,18 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
 
 
     always_comb begin
+
         // Dest (addr) operand source
         // If aluCsr (depends on column/row) addrbus is shifted !!
-        aOperand = (aluAddrCtrl ? alub : iAddrBus);
-
+        aOperand = (aluAddrCtrl) ? alub : iAddrBus;
+        
         // Second (data,source) operand mux
         case (aluDataCtrl)
             2'b00:              dOperand = iDataBus;
-            2'b01:              dOperand = 'h0000;
-            2'b11:              dOperand = 'hffff;
+            2'b01:              dOperand = 16'h0000;
+            2'b11:              dOperand = 16'hFFFF;
             // 2'b10:               dOperand = bcdResult;
-            2'b10:              dOperand = 'X;
+            2'b10:              dOperand = 16'hXXXX;
         endcase
     end
 
@@ -182,28 +186,34 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
         .cin( shftCin), .dir( shftRight), .isByte( isByte), .isLong( isLong),
         .result( shftResult));
 
-    wire [7:0] bcdResult;
-    wire bcdC, bcdV;
+    wire [7:0] wBcdResult_t3;
+    wire       wBcdCarry_t3;
+    wire       wBcdOverf_t3;
+    
     aluCorf aluCorf
     (
-        .binResult (addLatch),
-        .hCarry    (coreH),
+        .binResult (rAddLatch_t3),
+        .hCarry    (rAddHCarry_t3),
         .bAdd      (~oper[0]),
-        .cin       (pswCcr[XF]),
-        .bcdResult (bcdResult),
-        .dC        (bcdC),
-        .ov        (bcdV)
+        .cin       (rPswCcr_t3[XF]),
+        .bcdResult (wBcdResult_t3),
+        .dC        (wBcdCarry_t3),
+        .ov        (wBcdOverf_t3)
     );
 
+    reg [7:0] rBcdResult_t1;
+    reg       rBcdCarry_t1;
+    reg       rBcdOverf_t1;
+    
     // BCD adjust is among the slowest processing on ALU !
     // Precompute and register BCD result on T1
     // We don't need to wait for execution buses because corf is always added to ALU previous result
-    always_ff @(posedge clk) begin
+    always_ff @(posedge clk) begin : BCD_RESULT_T1
     
         if (enT1) begin
-            bcdLatch <= bcdResult;
-            bcdCarry <= bcdC;
-            bcdOverf <= bcdV;
+            rBcdResult_t1 <= wBcdResult_t3;
+            rBcdCarry_t1  <= wBcdCarry_t3;
+            rBcdOverf_t1  <= wBcdOverf_t3;
         end
     end
 
@@ -214,10 +224,10 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
             OP_SUB0[2:0]: addCin = 1'b0; // NOT = 0 + ~op
             OP_ADD[2:0]:  addCin = 1'b0;
             OP_SUB[2:0]:  addCin = 1'b1;
-            OP_ADDC[2:0]: addCin =  ccrCore[CF];
-            OP_SUBC[2:0]: addCin = ~ccrCore[CF];
-            OP_ADDX[2:0]: addCin =  pswCcr[XF];
-            OP_SUBX[2:0]: addCin = ~pswCcr[XF];
+            OP_ADDC[2:0]: addCin =  rCcrCore_t3[CF];
+            OP_SUBC[2:0]: addCin = ~rCcrCore_t3[CF];
+            OP_ADDX[2:0]: addCin =  rPswCcr_t3[XF];
+            OP_SUBX[2:0]: addCin = ~rPswCcr_t3[XF];
         endcase
     end
 
@@ -238,9 +248,9 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
             OP_ROXL[3:0],
             OP_ROXR[3:0]:
                 if (shftIsMul)
-                    shftCin = rIrd8 ? pswCcr[NF] ^ pswCcr[VF] : pswCcr[ CF];
+                    shftCin = rIrd8 ? rPswCcr_t3[NF] ^ rPswCcr_t3[VF] : rPswCcr_t3[ CF];
                 else
-                    shftCin = pswCcr[ XF];
+                    shftCin = rPswCcr_t3[ XF];
             default: // OP_SLAA
                 shftCin = aluColumn[1];   // col4 -> 0, col 6-> 1
         endcase
@@ -261,7 +271,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
             OP_ABCD,
             OP_SBCD:
             begin
-                result = { 8'h00, bcdLatch };
+                result = { 8'h00, rBcdResult_t1 };
             end
             
             OP_OR:  result = aOperand | dOperand;
@@ -336,7 +346,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     // CCR flags process
     always_comb begin
 
-        ccrTemp[XF] = pswCcr[XF];
+        ccrTemp[XF] = rPswCcr_t3[XF];
         ccrTemp[CF] = 1'b0;
         ccrTemp[VF] = 1'b0;
 
@@ -350,9 +360,9 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
             OP_ABCD,
             OP_SBCD:
             begin
-                ccrTemp[XF] = bcdCarry;
-                ccrTemp[CF] = bcdCarry;
-                ccrTemp[VF] = bcdOverf;
+                ccrTemp[XF] = rBcdCarry_t1;
+                ccrTemp[CF] = rBcdCarry_t1;
+                ccrTemp[VF] = rBcdOverf_t1;
             end
 
             OP_SUB0, // used by NOT
@@ -370,7 +380,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
                 // Needed when rotate count is zero, the ucode with the ROX operator never reached.
                 //  C must be set to the value of X, X remains unaffected.
                 if ((aluColumn == 1) & (row[11] | row[8])) begin
-                    ccrTemp[CF] = pswCcr[XF];
+                    ccrTemp[CF] = rPswCcr_t3[XF];
                 end
                 else begin
                     ccrTemp[CF] = 1'b0;
@@ -427,7 +437,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
                 ccrTemp[CF] = shftMsb;
                 // V set if msb changed on any shift.
                 // Otherwise clear previously on OP_AND (col 1i).
-                ccrTemp[VF] = pswCcr[VF] | (shftMsb ^
+                ccrTemp[VF] = rPswCcr_t3[VF] | (shftMsb ^
                     (isLong ? alue[15-1] : (isByte ? aOperand[7-1] : aOperand[15-1])) );
             end
             
@@ -467,29 +477,28 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
     //   that clear but not set Z (ADDX/SUBX/ABCD, etc)!
     logic [4:0] ccrMasked;
     always_comb begin
-        ccrMasked = (ccrTemp & ccrMask) | (pswCcr & ~ccrMask);
+        ccrMasked = (ccrTemp & ccrMask) | (rPswCcr_t3 & ~ccrMask);
         // if (finish | isCorf | isArX)     // No need to check specicially for isCorf as they always have the "finish" flag anyway
         if (finish | isArX)
-            ccrMasked[ ZF] = ccrTemp[ ZF] & pswCcr[ ZF];
+            ccrMasked[ZF] = ccrTemp[ZF] & rPswCcr_t3[ZF];
     end
 
     always_ff @(posedge clk) begin
         if (enT3) begin
             // Update latches from ALU operators
-            if ((| aluColumn)) begin
-                aluLatch <= result;
-                addLatch <= addResult[7:0];
+            if (|aluColumn) begin
+                rAluLatch_t3  <= result;
+                rAddLatch_t3  <= addResult[7:0];
 
-                coreH <= addHcarry;
+                rAddHCarry_t3 <= addHcarry;
 
                 // Update CCR core
-                if ((| aluColumn))
-                    ccrCore <= ccrTemp;     // Most bits not really used
+                rCcrCore_t3   <= ccrTemp; // Most bits not really used
             end
 
             if (alueClkEn)
                 alue <= iDataBus;
-            else if (isShift & (| aluColumn))
+            else if (isShift & (|aluColumn))
                 alue <= shftResult[31:16];
         end
 
@@ -497,13 +506,15 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
         // Originally on T3-T4 edge pulse !!
         // Might be possible to update on T4 (but not after T0) from partial result registered on T3, it will increase performance!
         if (pwrUp)
-            pswCcr <= '0;
+            rPswCcr_t3 <= 5'b00000;
         else if (enT3 & ftu2Ccr)
-            pswCcr <= ftu[4:0];
+            rPswCcr_t3 <= ftu[4:0];
         else if (enT3 & ~noCcrEn & (finish | init))
-            pswCcr <= ccrMasked;
+            rPswCcr_t3 <= ccrMasked;
     end
-    assign ccr = { 3'b0, pswCcr};
+    
+    assign oAluOut = rAluLatch_t3;
+    assign oCcr    = { 3'b0, rPswCcr_t3 };
 
 endmodule
 
@@ -573,15 +584,12 @@ module aluShifter( input [31:0] data,
     always_comb begin
         // Reverse alu/alue position for MUL & DIV
         // Result reversed again
-        if (swapWords & dir)
-            result = { tdata[0], tdata[31:17], cin, tdata[15:1]};
-        else if (swapWords)
-            result = { tdata[30:16], cin, tdata[14:0], tdata[31]};
-
-        else if (dir)
-            result = { cin, tdata[31:1]};
-        else
-            result = { tdata[30:0], cin};
+        case ({ swapWords, dir })
+            2'b11 : result = { tdata[0], tdata[31:17], cin, tdata[15:1] };
+            2'b10 : result = { tdata[30:16], cin, tdata[14:0], tdata[31] };
+            2'b01 : result = { cin, tdata[31:1] };
+            2'b00 : result = { tdata[30:0], cin };
+        endcase
     end
 
 endmodule
diff --git a/fx68k_pkg.sv b/fx68k_pkg.sv
index 91369f3..748ad9c 100644
--- a/fx68k_pkg.sv
+++ b/fx68k_pkg.sv
@@ -83,6 +83,22 @@ typedef struct packed
 {
     logic       isRmc;         // r
 
+    logic       updTpend;      // r
+    logic       clrTpend;      // r
+    logic       tvn2Ftu;       // r
+    logic       const2Ftu;     // r
+    logic       ftu2Dbl;       // r
+    logic       ftu2Abl;       // r
+    logic       abl2Pren;      // r
+    logic       updPren;       // r
+    logic       inl2psw;       // r
+    logic       ftu2Sr;        // r
+    logic       sr2Ftu;        // r
+    logic       pswIToFtu;     // r
+    logic       ird2Ftu;       // r
+    logic       ssw2Ftu;       // r
+    logic       initST;        // r
+    
     logic       auClkEn;       // r
     logic       noSpAlign;     // r
     logic [2:0] auCntrl;       // r
@@ -129,6 +145,11 @@ typedef struct packed
 
     logic       alu2Dbd;       // r
     logic       alu2Abd;       // r
+    logic       dbin2Dbd;      // r
+    logic       dbin2Abd;      // r
+    logic       au2Db;         // r
+    logic       au2Ab;         // r
+    
     logic       extDbh;        // r
     logic       extAbh;        // r
     logic       ablAbd;        // r
@@ -146,22 +167,7 @@ typedef struct packed
     logic       noLowByte;     // w
     logic       noHighByte;    // w
 
-    logic       updTpend;      // w
-    logic       clrTpend;      // w
-    logic       tvn2Ftu;       // w
-    logic       const2Ftu;     // w
-    logic       ftu2Dbl;       // w
-    logic       ftu2Abl;       // w
-    logic       abl2Pren;      // w
-    logic       updPren;       // w
-    logic       inl2psw;       // w
-    logic       ftu2Sr;        // w
-    logic       sr2Ftu;        // w
     logic       ftu2Ccr;       // w
-    logic       pswIToFtu;     // w
-    logic       ird2Ftu;       // w
-    logic       ssw2Ftu;       // w
-    logic       initST;        // w
     logic       Ir2Ird;        // w
 
     logic       db2Aob;        // w
@@ -195,8 +201,8 @@ typedef struct packed
     logic       au2Db;         // w
     logic       au2Ab;         // w
     logic       au2Pc;         // w
-    logic       dbin2Abd;      // w
-    logic       dbin2Dbd;      // w
+    //logic       dbin2Abd;      // w
+    //logic       dbin2Dbd;      // w
     logic       abdIsByte;     // w
 } s_nanod_w;
 
diff --git a/uaddrPla.sv b/uaddrPla.sv
index 1c00f06..2b4eca9 100644
--- a/uaddrPla.sv
+++ b/uaddrPla.sv
@@ -20,7 +20,7 @@ module uaddrPla
     input                   [15:0] opcode,
     input                   [15:0] lineBmap,
     
-    output                         palIll,
+    output                         plaIll,
     output logic [UADDR_WIDTH-1:0] plaA1,
     output logic [UADDR_WIDTH-1:0] plaA2,
     output logic [UADDR_WIDTH-1:0] plaA3
@@ -37,7 +37,7 @@ module uaddrPla
     logic                   illMisc;
     logic [UADDR_WIDTH-1:0] a1Misc;
    
-    assign palIll = (| (arIll & lineBmap));
+    assign plaIll = (| (arIll & lineBmap));
    
     // Only line 0 has 3 subs
     assign plaA1 = arA1[ line];

From 1bf00e9e10a6969a4ffc446b215020bc92c7f6fd Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Mon, 31 Aug 2020 19:49:14 +0200
Subject: [PATCH 15/16] 68k registers uses now two M4k memory blocks : new core
 size is 3200 LEs !!

---
 fx68k.sv | 475 +++++++++++++++++++++++++++++++++++++++++++------------
 1 file changed, 374 insertions(+), 101 deletions(-)

diff --git a/fx68k.sv b/fx68k.sv
index 304861d..4552d07 100644
--- a/fx68k.sv
+++ b/fx68k.sv
@@ -388,11 +388,11 @@ module fx68k
         .clk,
         .Clks,
         .enT1, .enT2, .enT3, .enT4,
-        .iNanoDec_t4 (wNanoDec_t4),
-        .iNanoDec_t3 (wNanoDec_t3),
-        .Irdecod     (wIrdDecode_t1),
-        .Ird         (rIrd_t1),
-        .iFtu_t3     (rFtu_t3), 
+        .iNanoDec_t4   (wNanoDec_t4),
+        .iNanoDec_t3   (wNanoDec_t3),
+        .iIrdDecode_t1 (wIrdDecode_t1),
+        .Ird           (rIrd_t1),
+        .iFtu_t3       (rFtu_t3), 
         .iEdb, .pswS,
         .prenEmpty, .au05z, .dcr4, .ze,
         .oAbl_t2     (wAbl_t2),
@@ -1260,7 +1260,7 @@ module excUnit
     input enT1, enT2, enT3, enT4,
     input s_nanod_r iNanoDec_t4,
     input s_nanod_w iNanoDec_t3,
-    input s_irdecod Irdecod,
+    input s_irdecod iIrdDecode_t1,
     input [15:0] Ird,           // ALU row (and others) decoder needs it
     input pswS,
     input [15:0] iFtu_t3,
@@ -1332,7 +1332,9 @@ localparam
 
     // RX RY muxes
     // RX and RY actual registers
-    logic [3:0] movemRx;
+    reg  [3:0] rMovemRx_t3;
+    reg        rRxIsMovem_t3;
+    reg        rMovemRxIsSp_t3;
     logic byteNotSpAlign;           // Byte instruction and no sp word align
 
     // IRD decoded signals must be latched. See comments on decoder
@@ -1340,82 +1342,110 @@ localparam
     //
     // If we need this earlier we can register IRD decode on T3 and use nano async
 
-    logic [4:0] rxMux, ryMux;
-    logic [3:0] rxReg, ryReg;
-    logic rxIsSp, ryIsSp;
+    reg   [4:0] rRxMux_t3;
+    reg         rRxIsSp_t3;
 
-    always_comb begin
+    reg   [4:0] rRyMux_t3;
+    reg         rRyIsSp_t3;
+    
+    // Pre-computation for wRxMux_t3 and wRyMux_t3
+    always_ff @(posedge clk) begin
+        reg [3:0] vTmp;
+    
+        if (enT3) begin
+            if (iIrdDecode_t1.rxIsUsp) begin
+                rRxMux_t3  <= REG_USP[4:0];
+                rRxIsSp_t3 <= 1'b1;
+            end
+            else if (iIrdDecode_t1.implicitSp) begin
+                rRxMux_t3  <= (pswS) ? REG_SSP[4:0] : REG_USP[4:0];
+                rRxIsSp_t3 <= 1'b1;
+            end
+            else if (iIrdDecode_t1.rxIsDt) begin
+                rRxMux_t3  <= REG_DT[4:0];
+                rRxIsSp_t3 <= 1'b0;
+            end
+            else if (!iIrdDecode_t1.rxIsMovem) begin
+                vTmp = { iIrdDecode_t1.rxIsAreg, iIrdDecode_t1.rx};
+                if (&vTmp) begin
+                    rRxMux_t3  <= (pswS) ? REG_SSP[4:0] : { 1'b0, vTmp };
+                    rRxIsSp_t3 <= 1'b1;
+                end
+                else begin
+                    rRxMux_t3  <= { 1'b0, vTmp };
+                    rRxIsSp_t3 <= 1'b0;
+                end
+            end
+            
+            if (iIrdDecode_t1.ryIsDt) begin
+                rRyMux_t3  <= REG_DT[4:0];
+                rRyIsSp_t3 <= 1'b0;
+            end
+            else begin
+                vTmp = { iIrdDecode_t1.ryIsAreg, iIrdDecode_t1.ry };
+                if (&vTmp) begin
+                    rRyMux_t3  <= (pswS) ? REG_SSP[4:0] : { 1'b0, vTmp };
+                    rRyIsSp_t3 <= 1'b1;
+                end
+                else begin
+                    rRyMux_t3  <= { 1'b0, vTmp };
+                    rRyIsSp_t3 <= 1'b0;
+                end
+            end
+        end
+    end
+    
+    logic [4:0] wRxMux_t3;
+    logic       wRxIsSp_t3;
+
+    logic [4:0] wRyMux_t3;
+    logic       wRyIsSp_t3;
 
-        // Unique IF !!
+    always_comb begin : RX_IDX_T3
         if (iNanoDec_t3.ssp) begin
-            rxMux  = REG_SSP[4:0];
-            rxIsSp = 1'b1;
-            rxReg  = 4'hX;
+            wRxMux_t3  = REG_SSP[4:0];
+            wRxIsSp_t3 = 1'b1;
         end
-        else if (Irdecod.rxIsUsp) begin
-            rxMux  = REG_USP[4:0];
-            rxIsSp = 1'b1;
-            rxReg  = 4'hX;
-        end
-        else if (Irdecod.rxIsDt & !Irdecod.implicitSp) begin
-            rxMux  = REG_DT[4:0];
-            rxIsSp = 1'b0;
-            rxReg  = 4'hX;
+        else if (rRxIsMovem_t3) begin
+            wRxMux_t3  = (pswS & rMovemRxIsSp_t3) ? REG_SSP[4:0] : { 1'b0, rMovemRx_t3 };
+            wRxIsSp_t3 = rMovemRxIsSp_t3;
         end
         else begin
-            if (Irdecod.implicitSp)
-                rxReg = REG_USP[3:0];
-            else if (Irdecod.rxIsMovem)
-                rxReg = movemRx;
-            else
-                rxReg = { Irdecod.rxIsAreg, Irdecod.rx};
-
-            if (&rxReg) begin
-                rxMux  = pswS ? REG_SSP[4:0] : REG_USP[4:0];
-                rxIsSp = 1'b1;
-            end
-            else begin
-                rxMux  = { 1'b0, rxReg};
-                rxIsSp = 1'b0;
-            end
+            wRxMux_t3  = rRxMux_t3;
+            wRxIsSp_t3 = rRxIsSp_t3;
         end
+    end
 
-        // RZ has higher priority!
-        if (Irdecod.ryIsDt & !iNanoDec_t3.rz) begin
-            ryMux  = REG_DT[4:0];
-            ryIsSp = 1'b0;
-            ryReg  = 4'hX;
+    always_comb begin : RY_IDX_T3
+        if (iNanoDec_t3.rz) begin
+            wRyIsSp_t3 = &oIrc_t4[15:12];
+            if (wRyIsSp_t3 & pswS)
+                wRyMux_t3 = REG_SSP[4:0];
+            else
+                wRyMux_t3 = { 1'b0, oIrc_t4[15:12] };
         end
         else begin
-            ryReg = iNanoDec_t3.rz ? oIrc_t4[15:12] : {Irdecod.ryIsAreg, Irdecod.ry};
-            ryIsSp = (& ryReg);
-            if (ryIsSp & pswS)          // No implicit SP on RY
-                ryMux = REG_SSP[4:0];
-            else
-                ryMux = { 1'b0, ryReg};
+            wRyMux_t3  = rRyMux_t3;
+            wRyIsSp_t3 = rRyIsSp_t3;
         end
-
     end
 
-    reg [4:0] rActualRx_t4;
-    reg [4:0] rActualRy_t4;
-    reg       rRxIsAreg_t4;
-    reg       rRyIsAreg_t4;
+    wire [31:0] wRx_t4;
+    wire [31:0] wRy_t4;
+    reg         rRxIsAreg_t4;
+    reg         rRyIsAreg_t4;
     
-    reg       rAbdIsByte_t4;
+    reg         rAbdIsByte_t4;
 
     always_ff @(posedge clk) begin
     
         if (enT4) begin
-            byteNotSpAlign <= Irdecod.isByte & ~(iNanoDec_t3.rxlDbl ? rxIsSp : ryIsSp);
+            byteNotSpAlign <= iIrdDecode_t1.isByte & ~(iNanoDec_t3.rxlDbl ? wRxIsSp_t3 : wRyIsSp_t3);
 
-            rActualRx_t4 <= rxMux;
-            rActualRy_t4 <= ryMux;
+            rRxIsAreg_t4 <= wRxIsSp_t3 | wRxMux_t3[3];
+            rRyIsAreg_t4 <= wRyIsSp_t3 | wRyMux_t3[3];
 
-            rRxIsAreg_t4 <= rxIsSp | rxMux[3];
-            rRyIsAreg_t4 <= ryIsSp | ryMux[3];
-
-            rAbdIsByte_t4 <= iNanoDec_t3.abdIsByte & Irdecod.isByte;
+            rAbdIsByte_t4 <= iNanoDec_t3.abdIsByte & iIrdDecode_t1.isByte;
         end
     end
 
@@ -1450,8 +1480,8 @@ localparam
 
     always_comb begin : BUS_MUXES_T4
         unique case (1'b1)
-            wRyl2Dbd_t4:          { wDbdIdle_t4, wDbdMux_t4 } = { 1'b0, regs68L[rActualRy_t4] };
-            wRxl2Dbd_t4:          { wDbdIdle_t4, wDbdMux_t4 } = { 1'b0, regs68L[rActualRx_t4] };
+            wRxl2Dbd_t4:          { wDbdIdle_t4, wDbdMux_t4 } = { 1'b0, wRx_t4[15:0] };
+            wRyl2Dbd_t4:          { wDbdIdle_t4, wDbdMux_t4 } = { 1'b0, wRy_t4[15:0] };
             iNanoDec_t4.alue2Dbd: { wDbdIdle_t4, wDbdMux_t4 } = { 1'b0, alue };
             iNanoDec_t4.dbin2Dbd: { wDbdIdle_t4, wDbdMux_t4 } = { 1'b0, wDbin_t4 };
             iNanoDec_t4.alu2Dbd:  { wDbdIdle_t4, wDbdMux_t4 } = { 1'b0, aluOut };
@@ -1460,8 +1490,8 @@ localparam
         endcase
 
         unique case (1'b1)
-            wRxl2Dbl_t4:          { wDblIdle_t4, wDblMux_t4 } = { 1'b0, regs68L[rActualRx_t4] };
-            wRyl2Dbl_t4:          { wDblIdle_t4, wDblMux_t4 } = { 1'b0, regs68L[rActualRy_t4] };
+            wRxl2Dbl_t4:          { wDblIdle_t4, wDblMux_t4 } = { 1'b0, wRx_t4[15:0] };
+            wRyl2Dbl_t4:          { wDblIdle_t4, wDblMux_t4 } = { 1'b0, wRy_t4[15:0] };
             iNanoDec_t4.ftu2Dbl:  { wDblIdle_t4, wDblMux_t4 } = { 1'b0, iFtu_t3 };
             iNanoDec_t4.au2Db:    { wDblIdle_t4, wDblMux_t4 } = { 1'b0, rAuReg_t3[15:0] };
             iNanoDec_t4.atl2Dbl:  { wDblIdle_t4, wDblMux_t4 } = { 1'b0, rAtl_t3 };
@@ -1470,8 +1500,8 @@ localparam
         endcase
 
         unique case (1'b1)
-            iNanoDec_t4.rxh2dbh:  { wDbhIdle_t4, wDbhMux_t4 } = { 1'b0, regs68H[rActualRx_t4] };
-            iNanoDec_t4.ryh2dbh:  { wDbhIdle_t4, wDbhMux_t4 } = { 1'b0, regs68H[rActualRy_t4] };
+            iNanoDec_t4.rxh2dbh:  { wDbhIdle_t4, wDbhMux_t4 } = { 1'b0, wRx_t4[31:16] };
+            iNanoDec_t4.ryh2dbh:  { wDbhIdle_t4, wDbhMux_t4 } = { 1'b0, wRy_t4[31:16] };
             iNanoDec_t4.au2Db:    { wDbhIdle_t4, wDbhMux_t4 } = { 1'b0, rAuReg_t3[31:16] };
             iNanoDec_t4.ath2Dbh:  { wDbhIdle_t4, wDbhMux_t4 } = { 1'b0, rAth_t3 };
             rPch2Dbh_t4:          { wDbhIdle_t4, wDbhMux_t4 } = { 1'b0, PcH };
@@ -1479,8 +1509,8 @@ localparam
         endcase
 
         unique case (1'b1)
-            wRyl2Abd_t4:          { wAbdIdle_t4, wAbdMux_t4 } = { 1'b0, regs68L[rActualRy_t4] };
-            wRxl2Abd_t4:          { wAbdIdle_t4, wAbdMux_t4 } = { 1'b0, regs68L[rActualRx_t4] };
+            wRxl2Abd_t4:          { wAbdIdle_t4, wAbdMux_t4 } = { 1'b0, wRx_t4[15:0] };
+            wRyl2Abd_t4:          { wAbdIdle_t4, wAbdMux_t4 } = { 1'b0, wRy_t4[15:0] };
             iNanoDec_t4.dbin2Abd: { wAbdIdle_t4, wAbdMux_t4 } = { 1'b0, wDbin_t4 };
             iNanoDec_t4.alu2Abd:  { wAbdIdle_t4, wAbdMux_t4 } = { 1'b0, aluOut };
             default:              { wAbdIdle_t4, wAbdMux_t4 } = { 1'b1, 16'h0000 };
@@ -1488,8 +1518,8 @@ localparam
 
         unique case (1'b1)
             rPcl2Abl_t4:          { wAblIdle_t4, wAblMux_t4 } = { 1'b0, PcL };
-            wRxl2Abl_t4:          { wAblIdle_t4, wAblMux_t4 } = { 1'b0, regs68L[rActualRx_t4] };
-            wRyl2Abl_t4:          { wAblIdle_t4, wAblMux_t4 } = { 1'b0, regs68L[rActualRy_t4] };
+            wRxl2Abl_t4:          { wAblIdle_t4, wAblMux_t4 } = { 1'b0, wRx_t4[15:0] };
+            wRyl2Abl_t4:          { wAblIdle_t4, wAblMux_t4 } = { 1'b0, wRy_t4[15:0] };
             iNanoDec_t4.ftu2Abl:  { wAblIdle_t4, wAblMux_t4 } = { 1'b0, iFtu_t3 };
             iNanoDec_t4.au2Ab:    { wAblIdle_t4, wAblMux_t4 } = { 1'b0, rAuReg_t3[15:0] };
             iNanoDec_t4.aob2Ab:   { wAblIdle_t4, wAblMux_t4 } = { 1'b0, aob[15:0] };
@@ -1499,8 +1529,8 @@ localparam
 
         unique case (1'b1)
             rPch2Abh_t4:          { wAbhIdle_t4, wAbhMux_t4 } = { 1'b0, PcH };
-            iNanoDec_t4.rxh2abh:  { wAbhIdle_t4, wAbhMux_t4 } = { 1'b0, regs68H[rActualRx_t4] };
-            iNanoDec_t4.ryh2abh:  { wAbhIdle_t4, wAbhMux_t4 } = { 1'b0, regs68H[rActualRy_t4] };
+            iNanoDec_t4.rxh2abh:  { wAbhIdle_t4, wAbhMux_t4 } = { 1'b0, wRx_t4[31:16] };
+            iNanoDec_t4.ryh2abh:  { wAbhIdle_t4, wAbhMux_t4 } = { 1'b0, wRy_t4[31:16] };
             iNanoDec_t4.au2Ab:    { wAbhIdle_t4, wAbhMux_t4 } = { 1'b0, rAuReg_t3[31:16] };
             iNanoDec_t4.aob2Ab:   { wAbhIdle_t4, wAbhMux_t4 } = { 1'b0, aob[31:16] };
             iNanoDec_t4.ath2Abh:  { wAbhIdle_t4, wAbhMux_t4 } = { 1'b0, rAth_t3 };
@@ -1652,31 +1682,42 @@ localparam
                         ? ((iNanoDec_t4.dbl2ryl) ? rDbl_t2 : rAbl_t2)
                         : ((iNanoDec_t4.dbl2ryl) ? rDbd_t2 : rAbd_t2);
 
-    always_ff @(posedge clk) begin : REGS_WRITE_T3
-        reg [2:0] vRxWEna;
-        reg [2:0] vRyWEna;
+    reg   [3:0] rRxWEna_t2;
+    reg   [3:0] rRyWEna_t2;
         
-        vRxWEna[2] <= iNanoDec_t4.dbh2rxh | iNanoDec_t4.abh2rxh;
-        vRxWEna[1] <= iNanoDec_t4.dbl2rxl | iNanoDec_t4.abl2rxl & (~rAbdIsByte_t4 | rRxIsAreg_t4);
-        vRxWEna[0] <= iNanoDec_t4.dbl2rxl | iNanoDec_t4.abl2rxl;
-
-        vRyWEna[2] <= iNanoDec_t4.dbh2ryh | iNanoDec_t4.abh2ryh;
-        vRyWEna[1] <= iNanoDec_t4.dbl2ryl | iNanoDec_t4.abl2ryl & (~rAbdIsByte_t4 | rRyIsAreg_t4);
-        vRyWEna[0] <= iNanoDec_t4.dbl2ryl | iNanoDec_t4.abl2ryl;
+    always_ff @(posedge clk) begin : REGS_WRENA_T2
         
-        if (enT3) begin
-            if (vRxWEna[2]) regs68H[rActualRx_t4][15:0] <= wRxh_t2[15:0];
-            if (vRxWEna[1]) regs68L[rActualRx_t4][15:8] <= wRxl_t2[15:8];
-            if (vRxWEna[0]) regs68L[rActualRx_t4][ 7:0] <= wRxl_t2[ 7:0];
+        if (enT2) begin
+            rRxWEna_t2[3] <= iNanoDec_t4.dbh2rxh | iNanoDec_t4.abh2rxh;
+            rRxWEna_t2[2] <= iNanoDec_t4.dbh2rxh | iNanoDec_t4.abh2rxh;
+            rRxWEna_t2[1] <= iNanoDec_t4.dbl2rxl | iNanoDec_t4.abl2rxl & (~rAbdIsByte_t4 | rRxIsAreg_t4);
+            rRxWEna_t2[0] <= iNanoDec_t4.dbl2rxl | iNanoDec_t4.abl2rxl;
             
-            if (vRyWEna[2]) regs68H[rActualRy_t4][15:0] <= wRyh_t2[15:0];
-            if (vRyWEna[1]) regs68L[rActualRy_t4][15:8] <= wRyl_t2[15:8];
-            if (vRyWEna[0]) regs68L[rActualRy_t4][ 7:0] <= wRyl_t2[ 7:0];
-            `ifdef verilator3
-            if ((|vRxWEna) & (|vRyWEna)) $display("68k regs : concurrent write !!");
-            `endif
+            rRyWEna_t2[3] <= iNanoDec_t4.dbh2ryh | iNanoDec_t4.abh2ryh;
+            rRyWEna_t2[2] <= iNanoDec_t4.dbh2ryh | iNanoDec_t4.abh2ryh;
+            rRyWEna_t2[1] <= iNanoDec_t4.dbl2ryl | iNanoDec_t4.abl2ryl & (~rAbdIsByte_t4 | rRyIsAreg_t4);
+            rRyWEna_t2[0] <= iNanoDec_t4.dbl2ryl | iNanoDec_t4.abl2ryl;
         end
     end
+    
+    
+    fx68kRegs U_fx68kRegs
+    (
+        .clk        (clk),
+        .clk_ena    (enT3 | enT4),
+        
+        .iRxAddr    (wRxMux_t3),
+        .iRxWrEna   (enT3),
+        .iRxByteEna (rRxWEna_t2),
+        .iRxWrData  ({ wRxh_t2[15:0], wRxl_t2[15:0] }),
+        .oRxRdData  (wRx_t4),
+        
+        .iRyAddr    (wRyMux_t3),
+        .iRyWrEna   (enT3),
+        .iRyByteEna (rRyWEna_t2),
+        .iRyWrData  ({ wRyh_t2[15:0], wRyl_t2[15:0] }),
+        .oRyRdData  (wRy_t4)
+    );
 
     // PC & AT
     reg  rDbl2Pcl_t4;
@@ -1770,7 +1811,12 @@ localparam
             prenLatch <= wDbin_t4;
         else if (enT3 & iNanoDec_t4.updPren) begin
             prenLatch [prHbit] <= 1'b0;
-            movemRx <= Irdecod.movemPreDecr ? ~prHbit : prHbit;
+            rMovemRx_t3     <= prHbit ^ {4{iIrdDecode_t1.movemPreDecr}};
+            rMovemRxIsSp_t3 <= (prHbit == {4{~iIrdDecode_t1.movemPreDecr}}) ? 1'b1 : 1'b0;
+        end
+        
+        if (enT3) begin
+            rRxIsMovem_t3 <= iIrdDecode_t1.rxIsMovem;
         end
     end
 
@@ -1825,7 +1871,7 @@ localparam
         .clk, .Clks, .enT1, .enT2, .enT3, .enT4,
         .iNanoDec_t4 (iNanoDec_t4),
         .iNanoDec_t3 (iNanoDec_t3),
-        .Irdecod,
+        .iIsByte_t1  (iIrdDecode_t1.isByte),
         .iEdb, .dobIdle, .dobInput, .aob0,
         .oIrc_t4     (oIrc_t4),
         .oDbin_t4    (wDbin_t4),
@@ -1842,7 +1888,7 @@ localparam
         .ftu2Ccr     (iNanoDec_t3.ftu2Ccr),
         .init        (iNanoDec_t3.aluInit),
         .finish      (iNanoDec_t3.aluFinish),
-        .aluIsByte   (Irdecod.isByte),
+        .aluIsByte   (iIrdDecode_t1.isByte),
         .alub        (rAlub_t3),
         .ftu         (iFtu_t3), 
         .alueClkEn,
@@ -1856,6 +1902,139 @@ localparam
 
 endmodule
 
+module fx68kRegs
+(
+    input         clk,
+    input         clk_ena,
+    
+    input   [4:0] iRxAddr,
+    input         iRxWrEna,
+    input   [3:0] iRxByteEna,
+    input  [31:0] iRxWrData,
+    output [31:0] oRxRdData,
+    
+    input   [4:0] iRyAddr,
+    input         iRyWrEna,
+    input   [3:0] iRyByteEna,
+    input  [31:0] iRyWrData,
+    output [31:0] oRyRdData
+);
+
+`ifdef verilator3
+
+    // Inferred block RAM
+    reg [31:0] rRam [0:31];
+    
+    always_ff @(posedge clk) begin : RX_WRITE
+    
+        if (clk_ena & iRxWrEna) begin
+            if (iRxByteEna[3]) rRam[iRxAddr][31:24] <= iRxWrData[31:24];
+            if (iRxByteEna[2]) rRam[iRxAddr][23:16] <= iRxWrData[23:16];
+            if (iRxByteEna[1]) rRam[iRxAddr][15: 8] <= iRxWrData[15: 8];
+            if (iRxByteEna[0]) rRam[iRxAddr][ 7: 0] <= iRxWrData[ 7: 0];
+        end
+    end
+    
+    reg [31:0] rRxRdData;
+    
+    always_ff @(posedge clk) begin : RX_READ
+    
+        if (clk_ena) begin
+            rRxRdData <= rRam[iRxAddr];
+        end
+    end
+    
+    assign oRxRdData = rRxRdData;
+
+    always_ff @(posedge clk) begin : RY_WRITE
+    
+        if (clk_ena & iRyWrEna) begin
+            if (iRyByteEna[3]) rRam[iRyAddr][31:24] <= iRyWrData[31:24];
+            if (iRyByteEna[2]) rRam[iRyAddr][23:16] <= iRyWrData[23:16];
+            if (iRyByteEna[1]) rRam[iRyAddr][15: 8] <= iRyWrData[15: 8];
+            if (iRyByteEna[0]) rRam[iRyAddr][ 7: 0] <= iRyWrData[ 7: 0];
+        end
+    end
+
+    reg [31:0] rRyRdData;
+    
+    always_ff @(posedge clk) begin : RY_READ
+    
+        if (clk_ena) begin
+            rRyRdData <= rRam[iRyAddr];
+        end
+    end
+    
+    assign oRyRdData = rRyRdData;
+
+`else
+
+    altsyncram U_altsyncram
+    (
+        // Clock & reset
+        .aclr0          (1'b0),
+        .aclr1          (1'b0),
+        .clock0         (clk),
+        .clock1         (1'b1),
+        .clocken0       (clk_ena),
+        .clocken1       (1'b1),
+        .clocken2       (1'b1),
+        .clocken3       (1'b1),
+        // Rx port
+        .rden_a         (1'b1),
+        .wren_a         (iRxWrEna),
+        .byteena_a      (iRxByteEna),
+        .address_a      (iRxAddr),
+        .addressstall_a (1'b0),
+        .data_a         (iRxWrData),
+        .q_a            (oRxRdData),
+        // Ry port
+        .rden_b         (1'b1),
+        .wren_b         (iRyWrEna),
+        .byteena_b      (iRyByteEna),
+        .address_b      (iRyAddr),
+        .addressstall_b (1'b0),
+        .data_b         (iRyWrData),
+        .q_b            (oRyRdData),
+        .eccstatus      ()
+    );
+	defparam
+        U_altsyncram.address_aclr_a            = "NONE",
+        U_altsyncram.address_aclr_b            = "NONE",
+        U_altsyncram.address_reg_b             = "CLOCK0",
+        U_altsyncram.byteena_aclr_a            = "NONE",
+        U_altsyncram.byteena_aclr_b            = "NONE",
+        U_altsyncram.byteena_reg_b             = "CLOCK0",
+        U_altsyncram.byte_size                 = 8,
+        U_altsyncram.indata_aclr_a             = "NONE",
+        U_altsyncram.indata_aclr_b             = "NONE",
+        U_altsyncram.indata_reg_b              = "CLOCK0",
+        U_altsyncram.intended_device_family    = "Stratix",
+        U_altsyncram.lpm_type                  = "altsyncram",
+        U_altsyncram.numwords_a                = 32,
+        U_altsyncram.numwords_b                = 32,
+        U_altsyncram.operation_mode            = "BIDIR_DUAL_PORT",
+        U_altsyncram.outdata_aclr_a            = "NONE",
+        U_altsyncram.outdata_aclr_b            = "NONE",
+        U_altsyncram.outdata_reg_a             = "UNREGISTERED",
+        U_altsyncram.outdata_reg_b             = "UNREGISTERED",
+        U_altsyncram.power_up_uninitialized    = "FALSE",
+        U_altsyncram.ram_block_type            = "M4K",
+        U_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+        U_altsyncram.widthad_a                 = 5,
+        U_altsyncram.widthad_b                 = 5,
+        U_altsyncram.width_a                   = 32,
+        U_altsyncram.width_b                   = 32,
+        U_altsyncram.width_byteena_a           = 4,
+        U_altsyncram.width_byteena_b           = 4,
+        U_altsyncram.wrcontrol_aclr_a          = "NONE",
+        U_altsyncram.wrcontrol_aclr_b          = "NONE",
+        U_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK0";
+        
+`endif
+
+endmodule
+
 //
 // Data bus I/O
 // At a separate module because it is a bit complicated and the timing is special.
@@ -1875,7 +2054,7 @@ module dataIo
     input               enT4,
     input     s_nanod_r iNanoDec_t4,
     input     s_nanod_w iNanoDec_t3,
-    input     s_irdecod Irdecod,
+    input               iIsByte_t1,
     input        [15:0] iEdb,
     input               aob0,
 
@@ -1912,7 +2091,7 @@ module dataIo
         // Can't latch at T3, a new IRD might be loaded already at T1.
         // Ok to latch at T4 if combination latched then at T3
         if (enT4)
-            isByte_T4 <= Irdecod.isByte;    // Includes MOVEP from mem, we could OR it here
+            isByte_T4 <= iIsByte_t1;    // Includes MOVEP from mem, we could OR it here
 
         if (enT3) begin
             dbinNoHigh <= iNanoDec_t3.noHighByte;
@@ -1958,7 +2137,7 @@ module dataIo
         // Wait states don't affect DOB operation that is done at the start of the bus cycle.
 
         if (enT4)
-            byteCycle <= iNanoDec_t3.busByte & Irdecod.isByte;        // busIsByte but not MOVEP
+            byteCycle <= iNanoDec_t3.busByte & iIsByte_t1;        // busIsByte but not MOVEP
 
         // Originally byte low/high interconnect is done at EDB, not at DOB.
         if (enT3 & ~dobIdle) begin
@@ -2682,6 +2861,8 @@ module uRom
     output logic  [UROM_WIDTH-1:0] microOutput
 );
 
+`ifdef verilator3
+
     reg [UROM_WIDTH-1:0] uRam[0:UROM_DEPTH-1];
 
     initial begin
@@ -2692,6 +2873,51 @@ module uRom
         microOutput <= uRam[microAddr];
     end
 
+`else
+
+    altsyncram U_altsyncram
+    (
+        .clock0         (clk),
+        .address_a      (microAddr),
+        .q_a            (microOutput),
+        .aclr0          (1'b0),
+        .aclr1          (1'b0),
+        .address_b      (1'b1),
+        .addressstall_a (1'b0),
+        .addressstall_b (1'b0),
+        .byteena_a      (1'b1),
+        .byteena_b      (1'b1),
+        .clock1         (1'b1),
+        .clocken0       (1'b1),
+        .clocken1       (1'b1),
+        .clocken2       (1'b1),
+        .clocken3       (1'b1),
+        .data_a         ({UROM_WIDTH{1'b1}}),
+        .data_b         (1'b1),
+        .eccstatus      (),
+        .q_b            (),
+        .rden_a         (1'b1),
+        .rden_b         (1'b1),
+        .wren_a         (1'b0),
+        .wren_b         (1'b0)
+    );
+    defparam
+        U_altsyncram.address_aclr_a         = "NONE",
+        //U_altsyncram.clock_enable_input_a   = "BYPASS",
+        //U_altsyncram.clock_enable_output_a  = "BYPASS",
+        U_altsyncram.init_file              = "microrom.mif",
+        U_altsyncram.intended_device_family = "Stratix",
+        U_altsyncram.lpm_type               = "altsyncram",
+        U_altsyncram.numwords_a             = (1 << UADDR_WIDTH),
+        U_altsyncram.operation_mode         = "ROM",
+        U_altsyncram.outdata_aclr_a         = "NONE",
+        U_altsyncram.outdata_reg_a          = "UNREGISTERED",
+        U_altsyncram.widthad_a              = UADDR_WIDTH,
+        U_altsyncram.width_a                = UROM_WIDTH,
+        U_altsyncram.width_byteena_a        = 1;
+        
+`endif
+
 endmodule
 
 
@@ -2702,6 +2928,8 @@ module nanoRom
     output logic [NANO_WIDTH-1:0] nanoOutput
 );
 
+`ifdef verilator3
+
     reg [NANO_WIDTH-1:0] nRam[0:NANO_DEPTH-1];
 
     initial begin
@@ -2712,6 +2940,51 @@ module nanoRom
         nanoOutput <= nRam[nanoAddr];
     end
 
+`else
+
+    altsyncram U_altsyncram
+    (
+        .clock0         (clk),
+        .address_a      (nanoAddr),
+        .q_a            (nanoOutput),
+        .aclr0          (1'b0),
+        .aclr1          (1'b0),
+        .address_b      (1'b1),
+        .addressstall_a (1'b0),
+        .addressstall_b (1'b0),
+        .byteena_a      (1'b1),
+        .byteena_b      (1'b1),
+        .clock1         (1'b1),
+        .clocken0       (1'b1),
+        .clocken1       (1'b1),
+        .clocken2       (1'b1),
+        .clocken3       (1'b1),
+        .data_a         ({NANO_WIDTH{1'b1}}),
+        .data_b         (1'b1),
+        .eccstatus      (),
+        .q_b            (),
+        .rden_a         (1'b1),
+        .rden_b         (1'b1),
+        .wren_a         (1'b0),
+        .wren_b         (1'b0)
+    );
+    defparam
+        U_altsyncram.address_aclr_a         = "NONE",
+        //U_altsyncram.clock_enable_input_a   = "BYPASS",
+        //U_altsyncram.clock_enable_output_a  = "BYPASS",
+        U_altsyncram.init_file              = "nanorom.mif",
+        U_altsyncram.intended_device_family = "Stratix",
+        U_altsyncram.lpm_type               = "altsyncram",
+        U_altsyncram.numwords_a             = (1 << NADDR_WIDTH),
+        U_altsyncram.operation_mode         = "ROM",
+        U_altsyncram.outdata_aclr_a         = "NONE",
+        U_altsyncram.outdata_reg_a          = "UNREGISTERED",
+        U_altsyncram.widthad_a              = NADDR_WIDTH,
+        U_altsyncram.width_a                = NANO_WIDTH,
+        U_altsyncram.width_byteena_a        = 1;
+        
+`endif
+
 endmodule
 
 // Translate uaddr to nanoaddr

From 26c90eb590d7ae55bee59a4a2b614636f776c123 Mon Sep 17 00:00:00 2001
From: frederic <requin_frederic2@yahoo.fr>
Date: Wed, 2 Sep 2020 18:18:49 +0200
Subject: [PATCH 16/16] Created generic and Altera block RAM/ROM for registers
 and microcode

---
 bram/fx68kRegs_altera.sv  |   88 ++++
 bram/fx68kRegs_generic.sv |   97 ++++
 bram/fx68kRom_altera.sv   |   64 +++
 bram/fx68kRom_generic.sv  |   68 +++
 fx68k.sv                  |  549 +++++++-------------
 microrom.mif              | 1030 +++++++++++++++++++++++++++++++++++++
 nanorom.mif               |  342 ++++++++++++
 7 files changed, 1864 insertions(+), 374 deletions(-)
 create mode 100644 bram/fx68kRegs_altera.sv
 create mode 100644 bram/fx68kRegs_generic.sv
 create mode 100644 bram/fx68kRom_altera.sv
 create mode 100644 bram/fx68kRom_generic.sv
 create mode 100644 microrom.mif
 create mode 100644 nanorom.mif

diff --git a/bram/fx68kRegs_altera.sv b/bram/fx68kRegs_altera.sv
new file mode 100644
index 0000000..aeff65c
--- /dev/null
+++ b/bram/fx68kRegs_altera.sv
@@ -0,0 +1,88 @@
+module fx68kRegs
+#(
+    parameter FPGA_DEVICE = "Stratix",
+    parameter BRAM_TYPE   = "M4K"
+)
+(
+    input         clk,
+    input         clk_ena,
+    
+    input   [4:0] address_a,
+    input         wren_a,
+    input   [3:0] byteena_a,
+    input  [31:0] data_a,
+    output [31:0] q_a,
+    
+    input   [4:0] address_b,
+    input         wren_b,
+    input   [3:0] byteena_b,
+    input  [31:0] data_b,
+    output [31:0] q_b
+);
+
+    altsyncram
+    #(
+        .address_aclr_a   ("NONE"),
+        .address_aclr_b   ("NONE"),
+        .address_reg_b    ("CLOCK0"),
+        .byteena_aclr_a   ("NONE"),
+        .byteena_aclr_b   ("NONE"),
+        .byteena_reg_b    ("CLOCK0"),
+        .byte_size        (8),
+        .indata_aclr_a    ("NONE"),
+        .indata_aclr_b    ("NONE"),
+        .indata_reg_b     ("CLOCK0"),
+        .intended_device_family (FPGA_DEVICE),
+        .lpm_type         ("altsyncram"),
+        .numwords_a       (32),
+        .numwords_b       (32),
+        .operation_mode   ("BIDIR_DUAL_PORT"),
+        .outdata_aclr_a   ("NONE"),
+        .outdata_aclr_b   ("NONE"),
+        .outdata_reg_a    ("UNREGISTERED"),
+        .outdata_reg_b    ("UNREGISTERED"),
+        .power_up_uninitialized ("FALSE"),
+        .ram_block_type   (BRAM_TYPE),
+        .read_during_write_mode_mixed_ports ("DONT_CARE"),
+        .widthad_a        (5),
+        .widthad_b        (5),
+        .width_a          (32),
+        .width_b          (32),
+        .width_byteena_a  (4),
+        .width_byteena_b  (4),
+        .wrcontrol_aclr_a ("NONE"),
+        .wrcontrol_aclr_b ("NONE"),
+        .wrcontrol_wraddress_reg_b ("CLOCK0")
+    )
+    U_altsyncram
+    (
+        // Clock & reset
+        .aclr0            (1'b0),
+        .aclr1            (1'b0),
+        .clock0           (clk),
+        .clock1           (1'b1),
+        .clocken0         (clk_ena),
+        .clocken1         (1'b1),
+        .clocken2         (1'b1),
+        .clocken3         (1'b1),
+        // Port A
+        .rden_a           (1'b1),
+        .wren_a           (wren_a),
+        .byteena_a        (byteena_a),
+        .address_a        (address_a),
+        .addressstall_a   (1'b0),
+        .data_a           (data_a),
+        .q_a              (q_a),
+        // Port B
+        .rden_b           (1'b1),
+        .wren_b           (wren_b),
+        .byteena_b        (byteena_b),
+        .address_b        (address_b),
+        .addressstall_b   (1'b0),
+        .data_b           (data_b),
+        .q_b              (q_b),
+        
+        .eccstatus        ()
+    );
+
+endmodule
diff --git a/bram/fx68kRegs_generic.sv b/bram/fx68kRegs_generic.sv
new file mode 100644
index 0000000..4ccd43b
--- /dev/null
+++ b/bram/fx68kRegs_generic.sv
@@ -0,0 +1,97 @@
+module fx68kRegs
+(
+    input         clk,
+    input         clk_ena,
+    
+    input   [4:0] address_a,
+    input         wren_a,
+    input   [3:0] byteena_a,
+    input  [31:0] data_a,
+    output [31:0] q_a,
+    
+    input   [4:0] address_b,
+    input         wren_b,
+    input   [3:0] byteena_b,
+    input  [31:0] data_b,
+    output [31:0] q_b
+);
+
+//=============================================================================
+// Inferred blocks RAM
+//=============================================================================
+
+    logic [15:0] ram_L [0:31];
+    logic [ 7:0] ram_W [0:31];
+    logic [ 7:0] ram_B [0:31];
+
+//=============================================================================
+// Port A access
+//=============================================================================
+    
+    reg [31:0] r_q_a;
+    
+    always_ff @(posedge clk) begin : PORT_A
+    
+        if (clk_ena) begin
+            if (byteena_a[2] & wren_a) begin
+                ram_L[address_a] <= data_a[31:16];
+                r_q_a[31:16] <= data_a[31:16];
+            end
+            else begin
+                r_q_a[31:16] <= ram_L[address_a];
+            end
+            if (byteena_a[1] & wren_a) begin
+                ram_W[address_a] <= data_a[15: 8];
+                r_q_a[15: 8] <= data_a[15: 8];
+            end
+            else begin
+                r_q_a[15: 8] <= ram_W[address_a];
+            end
+            if (byteena_a[0] & wren_a) begin
+                ram_B[address_a] <= data_a[ 7: 0];
+                r_q_a[ 7: 0] <= data_a[ 7: 0];
+            end
+            else begin
+                r_q_a[ 7: 0] <= ram_B[address_a];
+            end
+        end
+    end
+    
+    assign q_a = r_q_a;
+
+//=============================================================================
+// Port B access
+//=============================================================================
+
+    reg [31:0] r_q_b;
+    
+    always_ff @(posedge clk) begin : PORT_B
+    
+        if (clk_ena) begin
+            if (byteena_b[2] & wren_b) begin
+                ram_L[address_b] <= data_b[31:16];
+                r_q_b[31:16] <= data_b[31:16];
+            end
+            else begin
+                r_q_b[31:16] <= ram_L[address_b];
+            end
+            if (byteena_b[1] & wren_b) begin
+                ram_W[address_b] <= data_b[15: 8];
+                r_q_b[15: 8] <= data_b[15: 8];
+            end
+            else begin
+                r_q_b[15: 8] <= ram_W[address_b];
+            end
+            if (byteena_b[0] & wren_b) begin
+                ram_B[address_b] <= data_b[ 7: 0];
+                r_q_b[ 7: 0] <= data_b[ 7: 0];
+            end
+            else begin
+                r_q_b[ 7: 0] <= ram_B[address_b];
+            end
+        end
+    end
+
+    assign q_b = r_q_b;
+
+endmodule
diff --git a/bram/fx68kRom_altera.sv b/bram/fx68kRom_altera.sv
new file mode 100644
index 0000000..f62e030
--- /dev/null
+++ b/bram/fx68kRom_altera.sv
@@ -0,0 +1,64 @@
+module fx68kRom
+#(
+    parameter bit     OUTPUT_REG  = 1,
+    parameter integer ADDR_WIDTH  = 10,
+    parameter integer DATA_WIDTH  = 32,
+    parameter         INIT_FILE   = "NONE",
+    parameter         FPGA_DEVICE = "Stratix",
+    parameter         BRAM_TYPE   = "M4K"
+)
+(
+    input                   rst,
+    input                   clk,
+    input                   clk_ena,
+    input  [ADDR_WIDTH-1:0] addr,
+    output [DATA_WIDTH-1:0] q
+);
+
+    altsyncram
+    #(
+        .address_aclr_a  ("NONE"),
+        .init_file       (INIT_FILE),
+        .intended_device_family (FPGA_DEVICE),
+        .lpm_hint        ("ENABLE_RUNTIME_MOD=NO"),
+        .lpm_type        ("altsyncram"),
+        .numwords_a      (1 << ADDR_WIDTH),
+        .operation_mode  ("ROM"),
+        .outdata_aclr_a  ((OUTPUT_REG) ? "CLEAR1" : "NONE"),
+        .outdata_reg_a   ((OUTPUT_REG) ? "CLOCK1" : "UNREGISTERED"),
+        .ram_block_type  (BRAM_TYPE),
+        .widthad_a       (ADDR_WIDTH),
+        .width_a         (DATA_WIDTH),
+        .width_byteena_a (1)
+    )
+    U_altsyncram
+    (
+        .aclr0           (1'b0),
+        .aclr1           ((OUTPUT_REG) ? rst : 1'b0),
+        .clock0          (clk),
+        .clock1          ((OUTPUT_REG) ? clk : 1'b1),
+        .clocken0        (1'b1),
+        .clocken1        ((OUTPUT_REG) ? clk_ena : 1'b1),
+        .clocken2        (1'b1),
+        .clocken3        (1'b1),
+        
+        .address_a       (addr),
+        .addressstall_a  (1'b0),
+        .rden_a          (1'b1),
+        .wren_a          (1'b0),
+        .byteena_a       (1'b1),
+        .data_a          ({DATA_WIDTH{1'b1}}),
+        .q_a             (q),
+        
+        .address_b       (1'b1),
+        .addressstall_b  (1'b0),
+        .rden_b          (1'b1),
+        .wren_b          (1'b0),
+        .byteena_b       (1'b1),
+        .data_b          (1'b1),
+        .q_b             (/* open */),
+        
+        .eccstatus       (/* open */)
+    );
+    
+endmodule
diff --git a/bram/fx68kRom_generic.sv b/bram/fx68kRom_generic.sv
new file mode 100644
index 0000000..f0059bd
--- /dev/null
+++ b/bram/fx68kRom_generic.sv
@@ -0,0 +1,68 @@
+module fx68kRom
+#(
+    parameter bit     OUTPUT_REG = 1,
+    parameter integer ADDR_WIDTH = 10,
+    parameter integer DATA_WIDTH = 32,
+    parameter string  INIT_FILE  = "NONE"
+)
+(
+    input                   rst,
+    input                   clk,
+    input                   clk_ena,
+    input  [ADDR_WIDTH-1:0] addr,
+    output [DATA_WIDTH-1:0] q
+);
+
+//=============================================================================
+// Inferred ROM block
+//=============================================================================
+
+    logic [DATA_WIDTH-1:0] rom [0:(1 << ADDR_WIDTH)-1];
+
+//=============================================================================
+// ROM content
+//=============================================================================
+
+    initial begin : ROM_INIT
+        integer i;
+        
+        if (INIT_FILE == "NONE") begin
+            for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1) begin
+                rom[i] = {DATA_WIDTH{1'b0}};
+            end
+        end
+        else begin
+            $readmemb(INIT_FILE, rom);
+        end
+    end
+    
+//=============================================================================
+// ROM read
+//=============================================================================
+
+    reg [DATA_WIDTH-1:0] r_rom_q_p0;
+    
+    always_ff @(posedge clk) begin : ROM_READ_P0
+    
+        r_rom_q_p0 <= rom[addr];
+    end
+    
+//=============================================================================
+// Asynchronous reset on registered output
+//=============================================================================
+
+    reg [DATA_WIDTH-1:0] r_rom_q_p1;
+    
+    always_ff @(posedge rst or posedge clk) begin : OUTPUT_REG_P1
+    
+        if (rst) begin
+            r_rom_q_p1 <= {DATA_WIDTH{1'b0}};
+        end
+        else if (clk_ena) begin
+            r_rom_q_p1 <= r_rom_q_p0;
+        end
+    end
+    
+    assign q = (OUTPUT_REG) ? r_rom_q_p1 : r_rom_q_p0;
+    
+endmodule
diff --git a/fx68k.sv b/fx68k.sv
index 4552d07..332d33b 100644
--- a/fx68k.sv
+++ b/fx68k.sv
@@ -8,15 +8,78 @@
 // - Everything except bus retry already implemented.
 
 `timescale 1 ns / 1 ns
+
+//`define _FX68K_FPGA_STRATIX_
+//`define _FX68K_FPGA_STRATIX_II_
+//`define _FX68K_FPGA_STRATIX_III_
+//`define _FX68K_FPGA_CYCLONE_
+//`define _FX68K_FPGA_CYCLONE_II_
+//`define _FX68K_FPGA_CYCLONE_III_
+//`define _FX68K_FPGA_CYCLONE_IV_
+//`define _FX68K_FPGA_CYCLONE_V_
+
+`ifdef _VLINT_
+
+    `include "fx68k_pkg.sv"
+    `include "uaddrPla.sv"
+    `include "fx68kAlu.sv"
+    `include "bram/fx68kRom_generic.sv"
+    `include "bram/fx68kRegs_generic.sv"
+    
+`else /* _VLINT_ */
+
+    `ifdef _FX68K_FPGA_STRATIX_
+    `define _FX68K_FPGA_VENDOR_ALTERA_
+    `define _FX68K_FPGA_DEVICE_ "Stratix"
+    `define _FX68K_BRAM_TYPE_   "M4K"
+    `endif /* _FX68K_FPGA_STRATIX_ */
+    
+    `ifdef _FX68K_FPGA_STRATIX_II_
+    `define _FX68K_FPGA_VENDOR_ALTERA_
+    `define _FX68K_FPGA_DEVICE_ "Stratix II"
+    `define _FX68K_BRAM_TYPE_   "M4K"
+    `endif /* _FX68K_FPGA_STRATIX_II_ */
+    
+    `ifdef _FX68K_FPGA_STRATIX_III_
+    `define _FX68K_FPGA_VENDOR_ALTERA_
+    `define _FX68K_FPGA_DEVICE_ "Stratix III"
+    `define _FX68K_BRAM_TYPE_   "M9K"
+    `endif /* _FX68K_FPGA_STRATIX_III_ */
+    
+    `ifdef _FX68K_FPGA_CYCLONE_
+    `define _FX68K_FPGA_VENDOR_ALTERA_
+    `define _FX68K_FPGA_DEVICE_ "Cyclone"
+    `define _FX68K_BRAM_TYPE_   "M4K"
+    `endif /* _FX68K_FPGA_CYCLONE_ */
+    
+    `ifdef _FX68K_FPGA_CYCLONE_II_
+    `define _FX68K_FPGA_VENDOR_ALTERA_
+    `define _FX68K_FPGA_DEVICE_ "Cyclone II"
+    `define _FX68K_BRAM_TYPE_   "M4K"
+    `endif /* _FX68K_FPGA_CYCLONE_II_ */
+    
+    `ifdef _FX68K_FPGA_CYCLONE_III_
+    `define _FX68K_FPGA_VENDOR_ALTERA_
+    `define _FX68K_FPGA_DEVICE_ "Cyclone III"
+    `define _FX68K_BRAM_TYPE_   "M9K"
+    `endif /* _FX68K_FPGA_CYCLONE_III_ */
+    
+    `ifdef _FX68K_FPGA_CYCLONE_IV_
+    `define _FX68K_FPGA_VENDOR_ALTERA_
+    `define _FX68K_FPGA_DEVICE_ "Cyclone IV"
+    `define _FX68K_BRAM_TYPE_   "M9K"
+    `endif /* _FX68K_FPGA_CYCLONE_IV_ */
+    
+    `ifdef _FX68K_FPGA_CYCLONE_V_
+    `define _FX68K_FPGA_VENDOR_ALTERA_
+    `define _FX68K_FPGA_DEVICE_ "Cyclone V"
+    `define _FX68K_BRAM_TYPE_   "M10K"
+    `endif /* _FX68K_FPGA_CYCLONE_V_ */
+
+`endif /* _VLINT_ */
 
 // Define this to run a self contained compilation test build
 // `define FX68K_TEST
-
-`ifdef _VLINT_
-`include "fx68k_pkg.sv"
-`include "uaddrPla.sv"
-`include "fx68kAlu.sv"
-`endif /* _VLINT_ */
 
 import fx68k_pkg::*;
 
@@ -192,19 +255,14 @@ module fx68k
     end
 
     // Instantiate micro and nano rom
-    reg  [NANO_WIDTH-1:0] rNanoLatch_t3;
-    wire [NANO_WIDTH-1:0] wNanoOutput;
-    reg  [UROM_WIDTH-1:0] rMicroLatch_t3;
-    wire [UROM_WIDTH-1:0] wMicroOutput;
+    wire  [NANO_WIDTH-1:0] wNanoLatch_t3;
+    wire  [UROM_WIDTH-1:0] wMicroLatch_t3;
 
     reg  [UADDR_WIDTH-1:0] rMicroAddr_t1;
     wire [UADDR_WIDTH-1:0] wMicroAddr;
     reg  [NADDR_WIDTH-1:0] rNanoAddr_t1;
     wire [NADDR_WIDTH-1:0] wNanoAddr;
     
-    // Reset micro/nano latch after T4 of the current ublock.
-    wire                   wRstUrom = Clks.enPhi1 & enErrClk;
-
     // For the time being, address translation is done for nanorom only.
     microToNanoAddr microToNanoAddr
     (
@@ -212,21 +270,6 @@ module fx68k
         .orgAddr (wNanoAddr)
     );
 
-    // Output of these modules will be updated at T2 at the latest (depending on clock division)
-    nanoRom U_nanoRom
-    (
-        .clk         (clk),
-        .nanoAddr    (rNanoAddr_t1),
-        .nanoOutput  (wNanoOutput)
-    );
-    
-    uRom U_microRom
-    (
-        .clk         (clk),
-        .microAddr   (rMicroAddr_t1),
-        .microOutput (wMicroOutput)
-    );
-
     always_ff @(posedge clk) begin : ROM_ADDR_T1
         // uaddr originally latched on T1, except bits 6 & 7, the conditional bits, on T2
         // Seems we can latch whole address at either T1 or T2
@@ -237,31 +280,58 @@ module fx68k
             rNanoAddr_t1  <= RSTP0_NMA[NADDR_WIDTH-1:0];
         end
         else if (enT1) begin
-            rMicroAddr_t1 <= wMicroAddr;
-            rNanoAddr_t1  <= wNanoAddr;                // Register translated uaddr to naddr
-        end
-    end
-
-    always_ff @(posedge clk) begin : ROM_DATA_T3
-    
-        if (Clks.extReset) begin
-            rMicroLatch_t3 <= {UROM_WIDTH{1'b0}};
-            rNanoLatch_t3  <= {NANO_WIDTH{1'b0}};
-        end
-        else if (wRstUrom) begin
-            // Originally reset these bits only. Not strictly needed like this.
-            // Can reset the whole register if it is important.
-            rMicroLatch_t3[16] <= 1'b0;
-            rMicroLatch_t3[15] <= 1'b0;
-            rMicroLatch_t3[0]  <= 1'b0;
-            rNanoLatch_t3      <= {NANO_WIDTH{1'b0}};
-        end
-        else if (enT3) begin
-            rMicroLatch_t3 <= wMicroOutput;
-            rNanoLatch_t3  <= wNanoOutput;
-        end
+            rMicroAddr_t1 <= wMicroAddr;
+            rNanoAddr_t1  <= wNanoAddr;                // Register translated uaddr to naddr
+        end
     end
 
+    // Reset micro/nano latch after T4 of the current ublock.
+    wire wRstUrom = Clks.extReset | Clks.enPhi1 & enErrClk;
+
+    // Output of these modules will be updated at T3
+    fx68kRom
+    #(
+       .OUTPUT_REG  (1),
+       .ADDR_WIDTH  (NADDR_WIDTH),
+       .DATA_WIDTH  (NANO_WIDTH),
+`ifdef _FX68K_FPGA_VENDOR_ALTERA_
+       .INIT_FILE   ("nanorom.mif"),
+       .FPGA_DEVICE (`_FX68K_FPGA_DEVICE_),
+       .BRAM_TYPE   (`_FX68K_BRAM_TYPE_)
+`else
+       .INIT_FILE   ("nanorom.mem")
+`endif
+    )
+    U_nanoRom_t3
+    (
+        .rst        (wRstUrom),
+        .clk        (clk),
+        .clk_ena    (enT3), // ROM output available at T3
+        .addr       (rNanoAddr_t1),
+        .q          (wNanoLatch_t3)
+    );
+    
+    fx68kRom
+    #(
+       .OUTPUT_REG  (1),
+       .ADDR_WIDTH  (UADDR_WIDTH),
+       .DATA_WIDTH  (UROM_WIDTH),
+`ifdef _FX68K_FPGA_VENDOR_ALTERA_
+       .INIT_FILE   ("microrom.mif"),
+       .FPGA_DEVICE (`_FX68K_FPGA_DEVICE_),
+       .BRAM_TYPE   (`_FX68K_BRAM_TYPE_)
+`else
+       .INIT_FILE   ("microrom.mem")
+`endif
+    )
+    U_microRom_t3
+    (
+        .rst        (wRstUrom),
+        .clk        (clk),
+        .clk_ena    (enT3), // ROM output available at T3
+        .addr       (rMicroAddr_t1),
+        .q          (wMicroLatch_t3)
+    );
 
     // Decoded nanocode signals
     s_nanod_r wNanoDec_t4;
@@ -307,7 +377,7 @@ module fx68k
                 rIrd_t1   <= rIr_t1;
                 rIrdL_t1  <= rIrL_t1;
             end
-            else if (rMicroLatch_t3[0]) begin
+            else if (wMicroLatch_t3[0]) begin
                 // prevented by IR => IRD !
                 rIr_t1    <= wIrc_t4;
                 // Instruction groups pre-decoding
@@ -367,7 +437,7 @@ module fx68k
         .clk,
         .Clks,
         .enT3,
-        .iMicroLatch_t3 (rMicroLatch_t3),
+        .iMicroLatch_t3 (wMicroLatch_t3),
         .Ird        (rIrd_t1),
         .A0Err, .excRst, .BerrA, .busAddrErr, .Spuria, .Avia,
         .Tpend, .intPend,
@@ -406,7 +476,7 @@ module fx68k
         .clk,
         .enT2,
         .enT4,
-        .iNanoLatch_t3 (rNanoLatch_t3),
+        .iNanoLatch_t3 (wNanoLatch_t3),
         .iIrdDecode_t1 (wIrdDecode_t1),
         .oNanoDec_t4   (wNanoDec_t4),
         .oNanoDec_t3   (wNanoDec_t3)
@@ -429,7 +499,7 @@ module fx68k
 
 
     // Output reset & halt control
-    wire [1:0] uFc = rMicroLatch_t3[16:15];
+    wire [1:0] uFc = wMicroLatch_t3[16:15];
     logic oReset, oHalted;
     assign oRESETn = !oReset;
     assign oHALTEDn = !oHalted;
@@ -460,8 +530,8 @@ module fx68k
             rFC[2] <= pswS;
             // If FC is type 'n' (0) at ucode, access type depends on PC relative mode
             // We don't care about RZ in this case. Those uinstructions with RZ don't start a bus cycle.
-            rFC[1] <= rMicroLatch_t3[ 16] | ( ~rMicroLatch_t3[ 15] &  wIrdDecode_t1.isPcRel);
-            rFC[0] <= rMicroLatch_t3[ 15] | ( ~rMicroLatch_t3[ 16] & ~wIrdDecode_t1.isPcRel);
+            rFC[1] <= wMicroLatch_t3[ 16] | ( ~wMicroLatch_t3[ 15] &  wIrdDecode_t1.isPcRel);
+            rFC[0] <= wMicroLatch_t3[ 15] | ( ~wMicroLatch_t3[ 16] & ~wIrdDecode_t1.isPcRel);
         end
     end
 
@@ -508,7 +578,7 @@ module fx68k
             updIll <= 1'b0;
         end
         else if (enT4)
-            updIll <= rMicroLatch_t3[0];        // Update on any IRC->IR
+            updIll <= wMicroLatch_t3[0];        // Update on any IRC->IR
         else if (enT1 & updIll)
             inl <= iIpl;                    // Timing is correct.
 
@@ -812,7 +882,7 @@ localparam [3:0]
             oNanoDec_t4.tvn2Ftu   <= (ftuCtrl == NANO_FTU_TVN)      ? 1'b1 : 1'b0;
             oNanoDec_t4.const2Ftu <= (ftuCtrl == NANO_FTU_CONST)    ? 1'b1 : 1'b0;
             oNanoDec_t4.ftu2Dbl   <= (ftuCtrl == NANO_FTU_DBL)
-                              || (ftuCtrl == NANO_FTU_INL)      ? 1'b1 : 1'b0;
+                                  || (ftuCtrl == NANO_FTU_INL)      ? 1'b1 : 1'b0;
             oNanoDec_t4.ftu2Abl   <= (ftuCtrl == NANO_FTU_2ABL)     ? 1'b1 : 1'b0;
             oNanoDec_t4.abl2Pren  <= (ftuCtrl == NANO_FTU_ABL2PREN) ? 1'b1 : 1'b0;
             oNanoDec_t4.updPren   <= (ftuCtrl == NANO_FTU_RSTPREN)  ? 1'b1 : 1'b0;
@@ -823,8 +893,8 @@ localparam [3:0]
             oNanoDec_t4.ird2Ftu   <= (ftuCtrl == NANO_FTU_IRD)      ? 1'b1 : 1'b0; // Used on bus/addr error
             oNanoDec_t4.ssw2Ftu   <= (ftuCtrl == NANO_FTU_SSW)      ? 1'b1 : 1'b0;
             oNanoDec_t4.initST    <= (ftuCtrl == NANO_FTU_INL)
-                              || (ftuCtrl == NANO_FTU_CLRTPEND)
-                              || (ftuCtrl == NANO_FTU_INIT_ST)  ? 1'b1 : 1'b0;
+                                  || (ftuCtrl == NANO_FTU_CLRTPEND)
+                                  || (ftuCtrl == NANO_FTU_INIT_ST)  ? 1'b1 : 1'b0;
 
             oNanoDec_t4.auClkEn   <= ~iNanoLatch_t3[NANO_AUCLKEN];
             oNanoDec_t4.auCntrl   <=  iNanoLatch_t3[NANO_AUCTRL +: 3];
@@ -945,11 +1015,11 @@ localparam [3:0]
 
     assign oNanoDec_t3.permStart     = (aobCtrl != 2'b00) ? 1'b1 : 1'b0;
     assign oNanoDec_t3.isWrite       = iNanoLatch_t3[NANO_DOBCTRL_1]
-                                 | iNanoLatch_t3[NANO_DOBCTRL_0];
+                                     | iNanoLatch_t3[NANO_DOBCTRL_0];
     assign oNanoDec_t3.waitBusFinish = iNanoLatch_t3[NANO_DOBCTRL_1]
-                                 | iNanoLatch_t3[NANO_DOBCTRL_0]
-                                 | iNanoLatch_t3[NANO_TOIRC]
-                                 | iNanoLatch_t3[NANO_TODBIN];
+                                     | iNanoLatch_t3[NANO_DOBCTRL_0]
+                                     | iNanoLatch_t3[NANO_TOIRC]
+                                     | iNanoLatch_t3[NANO_TODBIN];
     assign oNanoDec_t3.busByte       = iNanoLatch_t3[NANO_BUSBYTE];
 
     assign oNanoDec_t3.noLowByte     = iNanoLatch_t3[NANO_LOWBYTE];
@@ -1238,8 +1308,8 @@ module irdDecode
     // ADDA/SUBA ADDQ/SUBQ MOVEA
 
     assign oIrdDecode_t1.inhibitCcr =
-        ( (iIrdL_t1[4'h9] | iIrdL_t1[4'hD]) & size11) |            // ADDA/SUBA
-        ( iIrdL_t1[4'h5] & eaAdir) |                           // ADDQ/SUBQ to An (originally checks for line[4] as well !?)
+        ( (iIrdL_t1[4'h9] | iIrdL_t1[4'hD]) & size11) |                // ADDA/SUBA
+        ( iIrdL_t1[4'h5] & eaAdir) |                                   // ADDQ/SUBQ to An (originally checks for line[4] as well !?)
         ( (iIrdL_t1[4'h2] | iIrdL_t1[4'h3]) & iIrd_t1[8:6] == 3'b001); // MOVEA
 
 endmodule
@@ -1283,31 +1353,27 @@ localparam
     REG_SSP = 16,
     REG_DT  = 17;
 
-    // Register file
-    reg [15:0] regs68L[0:17];
-    reg [15:0] regs68H[0:17];
-
 `ifdef verilator3
-
-    /*
-        It is bad practice to initialize simulation registers that the hardware doesn't.
-        There is risk that simulation would be different than the real hardware. But in this case is the other way around.
-        Some ROM uses something like sub.l An,An at powerup which clears the register
-        Simulator power ups the registers with 'X, as they are really undetermined at the real hardware.
-        But the simulator doesn't realize (it can't) that the same value is substracting from itself,
-        and that the result should be zero even when it's 'X - 'X.
-    */
-
-    initial begin
-        for( int i = 0; i < 18; i++) begin
-            regs68L[i] = 16'h0000;
-            regs68H[i] = 16'h0000;
-        end
-    end
-
     // For simulation display only
-    wire [31:0] SSP = { regs68H[REG_SSP], regs68L[REG_SSP]};
-
+    wire [31:0] dbg_D0 =  { U_fx68kRegs.ram_L[0],       U_fx68kRegs.ram_W[0],       U_fx68kRegs.ram_B[0]       };
+    wire [31:0] dbg_D1 =  { U_fx68kRegs.ram_L[1],       U_fx68kRegs.ram_W[1],       U_fx68kRegs.ram_B[1]       };
+    wire [31:0] dbg_D2 =  { U_fx68kRegs.ram_L[2],       U_fx68kRegs.ram_W[2],       U_fx68kRegs.ram_B[2]       };
+    wire [31:0] dbg_D3 =  { U_fx68kRegs.ram_L[3],       U_fx68kRegs.ram_W[3],       U_fx68kRegs.ram_B[3]       };
+    wire [31:0] dbg_D4 =  { U_fx68kRegs.ram_L[4],       U_fx68kRegs.ram_W[4],       U_fx68kRegs.ram_B[4]       };
+    wire [31:0] dbg_D5 =  { U_fx68kRegs.ram_L[5],       U_fx68kRegs.ram_W[5],       U_fx68kRegs.ram_B[5]       };
+    wire [31:0] dbg_D6 =  { U_fx68kRegs.ram_L[6],       U_fx68kRegs.ram_W[6],       U_fx68kRegs.ram_B[6]       };
+    wire [31:0] dbg_D7 =  { U_fx68kRegs.ram_L[7],       U_fx68kRegs.ram_W[7],       U_fx68kRegs.ram_B[7]       };
+    wire [31:0] dbg_A0 =  { U_fx68kRegs.ram_L[8],       U_fx68kRegs.ram_W[8],       U_fx68kRegs.ram_B[8]       };
+    wire [31:0] dbg_A1 =  { U_fx68kRegs.ram_L[9],       U_fx68kRegs.ram_W[9],       U_fx68kRegs.ram_B[9]       };
+    wire [31:0] dbg_A2 =  { U_fx68kRegs.ram_L[10],      U_fx68kRegs.ram_W[10],      U_fx68kRegs.ram_B[10]      };
+    wire [31:0] dbg_A3 =  { U_fx68kRegs.ram_L[11],      U_fx68kRegs.ram_W[11],      U_fx68kRegs.ram_B[11]      };
+    wire [31:0] dbg_A4 =  { U_fx68kRegs.ram_L[12],      U_fx68kRegs.ram_W[12],      U_fx68kRegs.ram_B[12]      };
+    wire [31:0] dbg_A5 =  { U_fx68kRegs.ram_L[13],      U_fx68kRegs.ram_W[13],      U_fx68kRegs.ram_B[13]      };
+    wire [31:0] dbg_A6 =  { U_fx68kRegs.ram_L[14],      U_fx68kRegs.ram_W[14],      U_fx68kRegs.ram_B[14]      };
+    wire [31:0] dbg_USP = { U_fx68kRegs.ram_L[REG_USP], U_fx68kRegs.ram_W[REG_USP], U_fx68kRegs.ram_B[REG_USP] };
+    wire [31:0] dbg_SSP = { U_fx68kRegs.ram_L[REG_SSP], U_fx68kRegs.ram_W[REG_SSP], U_fx68kRegs.ram_B[REG_SSP] };
+    wire [31:0] dbg_DT  = { U_fx68kRegs.ram_L[REG_DT],  U_fx68kRegs.ram_W[REG_DT],  U_fx68kRegs.ram_B[REG_DT]  };
+    wire [31:0] dbg_PC =  { PcH, PcL };
 `endif
 
 
@@ -1700,23 +1766,30 @@ localparam
         end
     end
     
-    
-    fx68kRegs U_fx68kRegs
+    // Registers file
+    fx68kRegs
+`ifdef _FX68K_FPGA_VENDOR_ALTERA_
+    #(
+       .FPGA_DEVICE (`_FX68K_FPGA_DEVICE_),
+       .BRAM_TYPE   (`_FX68K_BRAM_TYPE_)
+    )
+`endif
+    U_fx68kRegs
     (
         .clk        (clk),
         .clk_ena    (enT3 | enT4),
         
-        .iRxAddr    (wRxMux_t3),
-        .iRxWrEna   (enT3),
-        .iRxByteEna (rRxWEna_t2),
-        .iRxWrData  ({ wRxh_t2[15:0], wRxl_t2[15:0] }),
-        .oRxRdData  (wRx_t4),
+        .address_a  (wRxMux_t3),
+        .wren_a     (enT3),
+        .byteena_a  (rRxWEna_t2),
+        .data_a     ({ wRxh_t2[15:0], wRxl_t2[15:0] }),
+        .q_a        (wRx_t4),
         
-        .iRyAddr    (wRyMux_t3),
-        .iRyWrEna   (enT3),
-        .iRyByteEna (rRyWEna_t2),
-        .iRyWrData  ({ wRyh_t2[15:0], wRyl_t2[15:0] }),
-        .oRyRdData  (wRy_t4)
+        .address_b  (wRyMux_t3),
+        .wren_b     (enT3),
+        .byteena_b  (rRyWEna_t2),
+        .data_b     ({ wRyh_t2[15:0], wRyl_t2[15:0] }),
+        .q_b        (wRy_t4)
     );
 
     // PC & AT
@@ -1902,138 +1975,6 @@ localparam
 
 endmodule
 
-module fx68kRegs
-(
-    input         clk,
-    input         clk_ena,
-    
-    input   [4:0] iRxAddr,
-    input         iRxWrEna,
-    input   [3:0] iRxByteEna,
-    input  [31:0] iRxWrData,
-    output [31:0] oRxRdData,
-    
-    input   [4:0] iRyAddr,
-    input         iRyWrEna,
-    input   [3:0] iRyByteEna,
-    input  [31:0] iRyWrData,
-    output [31:0] oRyRdData
-);
-
-`ifdef verilator3
-
-    // Inferred block RAM
-    reg [31:0] rRam [0:31];
-    
-    always_ff @(posedge clk) begin : RX_WRITE
-    
-        if (clk_ena & iRxWrEna) begin
-            if (iRxByteEna[3]) rRam[iRxAddr][31:24] <= iRxWrData[31:24];
-            if (iRxByteEna[2]) rRam[iRxAddr][23:16] <= iRxWrData[23:16];
-            if (iRxByteEna[1]) rRam[iRxAddr][15: 8] <= iRxWrData[15: 8];
-            if (iRxByteEna[0]) rRam[iRxAddr][ 7: 0] <= iRxWrData[ 7: 0];
-        end
-    end
-    
-    reg [31:0] rRxRdData;
-    
-    always_ff @(posedge clk) begin : RX_READ
-    
-        if (clk_ena) begin
-            rRxRdData <= rRam[iRxAddr];
-        end
-    end
-    
-    assign oRxRdData = rRxRdData;
-
-    always_ff @(posedge clk) begin : RY_WRITE
-    
-        if (clk_ena & iRyWrEna) begin
-            if (iRyByteEna[3]) rRam[iRyAddr][31:24] <= iRyWrData[31:24];
-            if (iRyByteEna[2]) rRam[iRyAddr][23:16] <= iRyWrData[23:16];
-            if (iRyByteEna[1]) rRam[iRyAddr][15: 8] <= iRyWrData[15: 8];
-            if (iRyByteEna[0]) rRam[iRyAddr][ 7: 0] <= iRyWrData[ 7: 0];
-        end
-    end
-
-    reg [31:0] rRyRdData;
-    
-    always_ff @(posedge clk) begin : RY_READ
-    
-        if (clk_ena) begin
-            rRyRdData <= rRam[iRyAddr];
-        end
-    end
-    
-    assign oRyRdData = rRyRdData;
-
-`else
-
-    altsyncram U_altsyncram
-    (
-        // Clock & reset
-        .aclr0          (1'b0),
-        .aclr1          (1'b0),
-        .clock0         (clk),
-        .clock1         (1'b1),
-        .clocken0       (clk_ena),
-        .clocken1       (1'b1),
-        .clocken2       (1'b1),
-        .clocken3       (1'b1),
-        // Rx port
-        .rden_a         (1'b1),
-        .wren_a         (iRxWrEna),
-        .byteena_a      (iRxByteEna),
-        .address_a      (iRxAddr),
-        .addressstall_a (1'b0),
-        .data_a         (iRxWrData),
-        .q_a            (oRxRdData),
-        // Ry port
-        .rden_b         (1'b1),
-        .wren_b         (iRyWrEna),
-        .byteena_b      (iRyByteEna),
-        .address_b      (iRyAddr),
-        .addressstall_b (1'b0),
-        .data_b         (iRyWrData),
-        .q_b            (oRyRdData),
-        .eccstatus      ()
-    );
-	defparam
-        U_altsyncram.address_aclr_a            = "NONE",
-        U_altsyncram.address_aclr_b            = "NONE",
-        U_altsyncram.address_reg_b             = "CLOCK0",
-        U_altsyncram.byteena_aclr_a            = "NONE",
-        U_altsyncram.byteena_aclr_b            = "NONE",
-        U_altsyncram.byteena_reg_b             = "CLOCK0",
-        U_altsyncram.byte_size                 = 8,
-        U_altsyncram.indata_aclr_a             = "NONE",
-        U_altsyncram.indata_aclr_b             = "NONE",
-        U_altsyncram.indata_reg_b              = "CLOCK0",
-        U_altsyncram.intended_device_family    = "Stratix",
-        U_altsyncram.lpm_type                  = "altsyncram",
-        U_altsyncram.numwords_a                = 32,
-        U_altsyncram.numwords_b                = 32,
-        U_altsyncram.operation_mode            = "BIDIR_DUAL_PORT",
-        U_altsyncram.outdata_aclr_a            = "NONE",
-        U_altsyncram.outdata_aclr_b            = "NONE",
-        U_altsyncram.outdata_reg_a             = "UNREGISTERED",
-        U_altsyncram.outdata_reg_b             = "UNREGISTERED",
-        U_altsyncram.power_up_uninitialized    = "FALSE",
-        U_altsyncram.ram_block_type            = "M4K",
-        U_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
-        U_altsyncram.widthad_a                 = 5,
-        U_altsyncram.widthad_b                 = 5,
-        U_altsyncram.width_a                   = 32,
-        U_altsyncram.width_b                   = 32,
-        U_altsyncram.width_byteena_a           = 4,
-        U_altsyncram.width_byteena_b           = 4,
-        U_altsyncram.wrcontrol_aclr_a          = "NONE",
-        U_altsyncram.wrcontrol_aclr_b          = "NONE",
-        U_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK0";
-        
-`endif
-
-endmodule
 
 //
 // Data bus I/O
@@ -2846,146 +2787,6 @@ module busControl
 
 endmodule
 
-//
-// microrom and nanorom instantiation
-//
-// There is bit of wasting of resources here. An extra registering pipeline happens that is not needed.
-// This is just for the purpose of helping inferring block RAM using pure generic code. Inferring RAM is important for performance.
-// Might be more efficient to use vendor specific features such as clock enable.
-//
-
-module uRom
-(
-    input                          clk,
-    input        [UADDR_WIDTH-1:0] microAddr,
-    output logic  [UROM_WIDTH-1:0] microOutput
-);
-
-`ifdef verilator3
-
-    reg [UROM_WIDTH-1:0] uRam[0:UROM_DEPTH-1];
-
-    initial begin
-        $readmemb("microrom.mem", uRam);
-    end
-
-    always_ff @(posedge clk) begin
-        microOutput <= uRam[microAddr];
-    end
-
-`else
-
-    altsyncram U_altsyncram
-    (
-        .clock0         (clk),
-        .address_a      (microAddr),
-        .q_a            (microOutput),
-        .aclr0          (1'b0),
-        .aclr1          (1'b0),
-        .address_b      (1'b1),
-        .addressstall_a (1'b0),
-        .addressstall_b (1'b0),
-        .byteena_a      (1'b1),
-        .byteena_b      (1'b1),
-        .clock1         (1'b1),
-        .clocken0       (1'b1),
-        .clocken1       (1'b1),
-        .clocken2       (1'b1),
-        .clocken3       (1'b1),
-        .data_a         ({UROM_WIDTH{1'b1}}),
-        .data_b         (1'b1),
-        .eccstatus      (),
-        .q_b            (),
-        .rden_a         (1'b1),
-        .rden_b         (1'b1),
-        .wren_a         (1'b0),
-        .wren_b         (1'b0)
-    );
-    defparam
-        U_altsyncram.address_aclr_a         = "NONE",
-        //U_altsyncram.clock_enable_input_a   = "BYPASS",
-        //U_altsyncram.clock_enable_output_a  = "BYPASS",
-        U_altsyncram.init_file              = "microrom.mif",
-        U_altsyncram.intended_device_family = "Stratix",
-        U_altsyncram.lpm_type               = "altsyncram",
-        U_altsyncram.numwords_a             = (1 << UADDR_WIDTH),
-        U_altsyncram.operation_mode         = "ROM",
-        U_altsyncram.outdata_aclr_a         = "NONE",
-        U_altsyncram.outdata_reg_a          = "UNREGISTERED",
-        U_altsyncram.widthad_a              = UADDR_WIDTH,
-        U_altsyncram.width_a                = UROM_WIDTH,
-        U_altsyncram.width_byteena_a        = 1;
-        
-`endif
-
-endmodule
-
-
-module nanoRom
-(
-    input                         clk,
-    input       [NADDR_WIDTH-1:0] nanoAddr,
-    output logic [NANO_WIDTH-1:0] nanoOutput
-);
-
-`ifdef verilator3
-
-    reg [NANO_WIDTH-1:0] nRam[0:NANO_DEPTH-1];
-
-    initial begin
-        $readmemb("nanorom.mem", nRam);
-    end
-
-    always_ff @(posedge clk) begin
-        nanoOutput <= nRam[nanoAddr];
-    end
-
-`else
-
-    altsyncram U_altsyncram
-    (
-        .clock0         (clk),
-        .address_a      (nanoAddr),
-        .q_a            (nanoOutput),
-        .aclr0          (1'b0),
-        .aclr1          (1'b0),
-        .address_b      (1'b1),
-        .addressstall_a (1'b0),
-        .addressstall_b (1'b0),
-        .byteena_a      (1'b1),
-        .byteena_b      (1'b1),
-        .clock1         (1'b1),
-        .clocken0       (1'b1),
-        .clocken1       (1'b1),
-        .clocken2       (1'b1),
-        .clocken3       (1'b1),
-        .data_a         ({NANO_WIDTH{1'b1}}),
-        .data_b         (1'b1),
-        .eccstatus      (),
-        .q_b            (),
-        .rden_a         (1'b1),
-        .rden_b         (1'b1),
-        .wren_a         (1'b0),
-        .wren_b         (1'b0)
-    );
-    defparam
-        U_altsyncram.address_aclr_a         = "NONE",
-        //U_altsyncram.clock_enable_input_a   = "BYPASS",
-        //U_altsyncram.clock_enable_output_a  = "BYPASS",
-        U_altsyncram.init_file              = "nanorom.mif",
-        U_altsyncram.intended_device_family = "Stratix",
-        U_altsyncram.lpm_type               = "altsyncram",
-        U_altsyncram.numwords_a             = (1 << NADDR_WIDTH),
-        U_altsyncram.operation_mode         = "ROM",
-        U_altsyncram.outdata_aclr_a         = "NONE",
-        U_altsyncram.outdata_reg_a          = "UNREGISTERED",
-        U_altsyncram.widthad_a              = NADDR_WIDTH,
-        U_altsyncram.width_a                = NANO_WIDTH,
-        U_altsyncram.width_byteena_a        = 1;
-        
-`endif
-
-endmodule
 
 // Translate uaddr to nanoaddr
 module microToNanoAddr(
diff --git a/microrom.mif b/microrom.mif
new file mode 100644
index 0000000..a4033b9
--- /dev/null
+++ b/microrom.mif
@@ -0,0 +1,1030 @@
+WIDTH=17;
+DEPTH=1024;
+ADDRESS_RADIX=UNS;
+DATA_RADIX=BIN;
+CONTENT BEGIN
+    0      : 10010000101100000;
+    1      : 10000100000000000;
+    2      : 00101001011010000;
+    3      : 00111110011000000;
+    4      : 01000000000001100;
+    5      : 01000000000001100;
+    6      : 01000010010000000;
+    7      : 10001100011100000;
+    8      : 01000100010000000;
+    9      : 10000000010000000;
+    10     : 10000000010000000;
+    11     : 01000100010000000;
+    12     : 00001010010000000;
+    13     : 10000000100000000;
+    14     : 10000000100000000;
+    15     : 01101001100000000;
+    16     : 00000000000000000;
+    17     : 00000000000000000;
+    18     : 00000000000000000;
+    19     : 00000000000000000;
+    20     : 00000000000000000;
+    21     : 00000000000000000;
+    22     : 00000000000000000;
+    23     : 00000000000000000;
+    24     : 00000000000000000;
+    25     : 00000000000000000;
+    26     : 00000000000000000;
+    27     : 00000000000000000;
+    28     : 00000000000000000;
+    29     : 00000000000000000;
+    30     : 00000000000000000;
+    31     : 00000000000000000;
+    32     : 00000000000000100;
+    33     : 00001010110000000;
+    34     : 00111000001100000;
+    35     : 00100101001001010;
+    36     : 00000000000001100;
+    37     : 10110000110100001;
+    38     : 00000000000001100;
+    39     : 00001110100000000;
+    40     : 00110100101000000;
+    41     : 00100011010100000;
+    42     : 00000010010000000;
+    43     : 10000110000000010;
+    44     : 00111110110000000;
+    45     : 00000100011100000;
+    46     : 00101111010100000;
+    47     : 10010011100000010;
+    48     : 00000000000000000;
+    49     : 00000000000000000;
+    50     : 00000000000000000;
+    51     : 00000000000000000;
+    52     : 00000000000000000;
+    53     : 00000000000000000;
+    54     : 00000000000000000;
+    55     : 00000000000000000;
+    56     : 00000000000000000;
+    57     : 00000000000000000;
+    58     : 00000000000000000;
+    59     : 00000000000000000;
+    60     : 00000000000000000;
+    61     : 00000000000000000;
+    62     : 00000000000000000;
+    63     : 00000000000000000;
+    64     : 10011101000000000;
+    65     : 00000100110010110;
+    66     : 00101001010000000;
+    67     : 10110000110100001;
+    68     : 00000000000000100;
+    69     : 00111110000100000;
+    70     : 10010111010100000;
+    71     : 01000110000100000;
+    72     : 01010111100000000;
+    73     : 10001010010011010;
+    74     : 01000110010100001;
+    75     : 00000110010111010;
+    76     : 01001100010100000;
+    77     : 10001010010010111;
+    78     : 01000000000100001;
+    79     : 00110100111000000;
+    80     : 00000000000000000;
+    81     : 00000000000000000;
+    82     : 00000000000000000;
+    83     : 00000000000000000;
+    84     : 00000000000000000;
+    85     : 00000000000000000;
+    86     : 00000000000000000;
+    87     : 00000000000000000;
+    88     : 00000000000000000;
+    89     : 00000000000000000;
+    90     : 00000000000000000;
+    91     : 00000000000000000;
+    92     : 00000000000000000;
+    93     : 00000000000000000;
+    94     : 00000000000000000;
+    95     : 00000000000000000;
+    96     : 00000010001100000;
+    97     : 01001010000100001;
+    98     : 10110100111000000;
+    99     : 00011011010100000;
+    100    : 10000000000000100;
+    101    : 10110100111000000;
+    102    : 00000000000000100;
+    103    : 00001000001000000;
+    104    : 00000100011100110;
+    105    : 10001110010100001;
+    106    : 00000000011110010;
+    107    : 01001000011000000;
+    108    : 00001000010100110;
+    109    : 10001010000110111;
+    110    : 00000000111110010;
+    111    : 01001000111000000;
+    112    : 00000000000000000;
+    113    : 00000000000000000;
+    114    : 00000000000000000;
+    115    : 00000000000000000;
+    116    : 00000000000000000;
+    117    : 00000000000000000;
+    118    : 00000000000000000;
+    119    : 00000000000000000;
+    120    : 00000000000000000;
+    121    : 00000000000000000;
+    122    : 00000000000000000;
+    123    : 00000000000000000;
+    124    : 00000000000000000;
+    125    : 00000000000000000;
+    126    : 00000000000000000;
+    127    : 00000000000000000;
+    128    : 10101001000000001;
+    129    : 10001000001000001;
+    130    : 01000000000000100;
+    131    : 01001100001111010;
+    132    : 00000110001000000;
+    133    : 00010110001100000;
+    134    : 00011010000000000;
+    135    : 10110000110100001;
+    136    : 01111000001100000;
+    137    : 00011000000000000;
+    138    : 00000100100100001;
+    139    : 00000000000000100;
+    140    : 00000000101100000;
+    141    : 00000000000000100;
+    142    : 00010001010100000;
+    143    : 10010111000100001;
+    144    : 00000000000000000;
+    145    : 00000000000000000;
+    146    : 00000000000000000;
+    147    : 00000000000000000;
+    148    : 00000000000000000;
+    149    : 00000000000000000;
+    150    : 00000000000000000;
+    151    : 00000000000000000;
+    152    : 00000000000000000;
+    153    : 00000000000000000;
+    154    : 00000000000000000;
+    155    : 00000000000000000;
+    156    : 00000000000000000;
+    157    : 00000000000000000;
+    158    : 00000000000000000;
+    159    : 00000000000000000;
+    160    : 00000010001100000;
+    161    : 00000000000000100;
+    162    : 01111000011100000;
+    163    : 00011011010100000;
+    164    : 00101101000000000;
+    165    : 01000110010111010;
+    166    : 00101101000000000;
+    167    : 10001010101100000;
+    168    : 01010110001100000;
+    169    : 00011000110000000;
+    170    : 01010110001100000;
+    171    : 10001110011100001;
+    172    : 00000100101100000;
+    173    : 01000110010111010;
+    174    : 00000100101100000;
+    175    : 10001010111100000;
+    176    : 00000000000000000;
+    177    : 00000000000000000;
+    178    : 00000000000000000;
+    179    : 00000000000000000;
+    180    : 00000000000000000;
+    181    : 00000000000000000;
+    182    : 00000000000000000;
+    183    : 00000000000000000;
+    184    : 00000000000000000;
+    185    : 00000000000000000;
+    186    : 00000000000000000;
+    187    : 00000000000000000;
+    188    : 00000000000000000;
+    189    : 00000000000000000;
+    190    : 00000000000000000;
+    191    : 00000000000000000;
+    192    : 10101001000000001;
+    193    : 00001000101010110;
+    194    : 00011111010100000;
+    195    : 01101101110000000;
+    196    : 00000000000000100;
+    197    : 10111110000100000;
+    198    : 00000100011100000;
+    199    : 10001100101000001;
+    200    : 00000110001000000;
+    201    : 00001110000010010;
+    202    : 00100101000010110;
+    203    : 00101101000100000;
+    204    : 00000000011100000;
+    205    : 00001000111100000;
+    206    : 00100101000011010;
+    207    : 00110100111000000;
+    208    : 00000000000000000;
+    209    : 00000000000000000;
+    210    : 00000000000000000;
+    211    : 00000000000000000;
+    212    : 00000000000000000;
+    213    : 00000000000000000;
+    214    : 00000000000000000;
+    215    : 00000000000000000;
+    216    : 00000000000000000;
+    217    : 00000000000000000;
+    218    : 00000000000000000;
+    219    : 00000000000000000;
+    220    : 00000000000000000;
+    221    : 00000000000000000;
+    222    : 00000000000000000;
+    223    : 00000000000000000;
+    224    : 00000010000100010;
+    225    : 00001010110000000;
+    226    : 00000000000000100;
+    227    : 00101101010000000;
+    228    : 01010001010000000;
+    229    : 01000110111000000;
+    230    : 00000000000000100;
+    231    : 00000000010110010;
+    232    : 00110100101000000;
+    233    : 00100011010100000;
+    234    : 10000000000001000;
+    235    : 01101011010000000;
+    236    : 00111110110000000;
+    237    : 00000100011100000;
+    238    : 10010101000000000;
+    239    : 01111110010100000;
+    240    : 00000000000000000;
+    241    : 00000000000000000;
+    242    : 00000000000000000;
+    243    : 00000000000000000;
+    244    : 00000000000000000;
+    245    : 00000000000000000;
+    246    : 00000000000000000;
+    247    : 00000000000000000;
+    248    : 00000000000000000;
+    249    : 00000000000000000;
+    250    : 00000000000000000;
+    251    : 00000000000000000;
+    252    : 00000000000000000;
+    253    : 00000000000000000;
+    254    : 00000000000000000;
+    255    : 00000000000000000;
+    256    : 10001100101000001;
+    257    : 10000010100000010;
+    258    : 01000010101000000;
+    259    : 00011111100100000;
+    260    : 10100111100000001;
+    261    : 10010010110000010;
+    262    : 01110100111000000;
+    263    : 00010111010000000;
+    264    : 10101011100000001;
+    265    : 10010010100000010;
+    266    : 01110000100100000;
+    267    : 00000000100100000;
+    268    : 10100101100100001;
+    269    : 10000010110000010;
+    270    : 01001010101000000;
+    271    : 00010111000000000;
+    272    : 00010001000010110;
+    273    : 01110010100111010;
+    274    : 10110100010000000;
+    275    : 00110100111000000;
+    276    : 01000010010000110;
+    277    : 01110010110111011;
+    278    : 01111100000000000;
+    279    : 00101101000100000;
+    280    : 00101001001010001;
+    281    : 01011011111100000;
+    282    : 01101111011000000;
+    283    : 00100011100000000;
+    284    : 00111110000110000;
+    285    : 00000000000000000;
+    286    : 10101111011000000;
+    287    : 00000000000000000;
+    288    : 00001010100000000;
+    289    : 10101011100100001;
+    290    : 01010011000100001;
+    291    : 10010101010000000;
+    292    : 00000000110000000;
+    293    : 10111010000100001;
+    294    : 01011001010000000;
+    295    : 10010101000000000;
+    296    : 00101101101100000;
+    297    : 10100011100100001;
+    298    : 01011110100000000;
+    299    : 01110100011100000;
+    300    : 00101011111000000;
+    301    : 10110000110100001;
+    302    : 01010101010100001;
+    303    : 00000000000000000;
+    304    : 00111000100000000;
+    305    : 01011011000000000;
+    306    : 00001000100100000;
+    307    : 10001100101000001;
+    308    : 00100001100000000;
+    309    : 01011011010000000;
+    310    : 00001000110100000;
+    311    : 10011001110100001;
+    312    : 00000110010111010;
+    313    : 01011011100000000;
+    314    : 00000000110100000;
+    315    : 10011101010000001;
+    316    : 00000000000000000;
+    317    : 00000000000000000;
+    318    : 00000000000000000;
+    319    : 00000000000000000;
+    320    : 00000000000000000;
+    321    : 00000000000000000;
+    322    : 00000000000000000;
+    323    : 00000000000000000;
+    324    : 00000000000000000;
+    325    : 00000000000000000;
+    326    : 00000000000000000;
+    327    : 00000000000000000;
+    328    : 00000000000000000;
+    329    : 00000000000000000;
+    330    : 00000000000000000;
+    331    : 00000000000000000;
+    332    : 00000000000000000;
+    333    : 00000000000000000;
+    334    : 00000000000000000;
+    335    : 00000000000000000;
+    336    : 10110000110100001;
+    337    : 00011101000100000;
+    338    : 00011101000100000;
+    339    : 00010001000101110;
+    340    : 01011010110000000;
+    341    : 01011001010100000;
+    342    : 10011101010100000;
+    343    : 00000000000000100;
+    344    : 10110000110100001;
+    345    : 00110110000000000;
+    346    : 10110000011100001;
+    347    : 10110000011100001;
+    348    : 10011101000000001;
+    349    : 01110100111000000;
+    350    : 00101101100100000;
+    351    : 10011000100000000;
+    352    : 00000000000000000;
+    353    : 00000000000000000;
+    354    : 00000000000000000;
+    355    : 00000000000000000;
+    356    : 00000000000000000;
+    357    : 00000000000000000;
+    358    : 00000000000000000;
+    359    : 00000000000000000;
+    360    : 00000000000000000;
+    361    : 00000000000000000;
+    362    : 00000000000000000;
+    363    : 00000000000000000;
+    364    : 00000000000000000;
+    365    : 00000000000000000;
+    366    : 00000000000000000;
+    367    : 00000000000000000;
+    368    : 10000000000000100;
+    369    : 00000000000000100;
+    370    : 00000100111000000;
+    371    : 00000100111000000;
+    372    : 00000100111000000;
+    373    : 00001100010101010;
+    374    : 00001000000010110;
+    375    : 00101001010000000;
+    376    : 10011000100000000;
+    377    : 00011011100100000;
+    378    : 01000100010000000;
+    379    : 01000000000001100;
+    380    : 10011000010000001;
+    381    : 10011011110100000;
+    382    : 10011111110100001;
+    383    : 00011000010000000;
+    384    : 00000000000000000;
+    385    : 00000000000000000;
+    386    : 00000000000000000;
+    387    : 00000000000000000;
+    388    : 00000000000000000;
+    389    : 00000000000000000;
+    390    : 00000000000000000;
+    391    : 00000000000000000;
+    392    : 00000000000000000;
+    393    : 00000000000000000;
+    394    : 00000000000000000;
+    395    : 00000000000000000;
+    396    : 00000000000000000;
+    397    : 00000000000000000;
+    398    : 00000000000000000;
+    399    : 00000000000000000;
+    400    : 00000000000000000;
+    401    : 00000000000000000;
+    402    : 00000000000000000;
+    403    : 00000000000000000;
+    404    : 00000000000000000;
+    405    : 00000000000000000;
+    406    : 00000000000000000;
+    407    : 00000000000000000;
+    408    : 00000000000000000;
+    409    : 00000000000000000;
+    410    : 00000000000000000;
+    411    : 00000000000000000;
+    412    : 00000000000000000;
+    413    : 00000000000000000;
+    414    : 00000000000000000;
+    415    : 00000000000000000;
+    416    : 00000000000000000;
+    417    : 00000000000000000;
+    418    : 00000000000000000;
+    419    : 00000000000000000;
+    420    : 00000000000000000;
+    421    : 00000000000000000;
+    422    : 00000000000000000;
+    423    : 00000000000000000;
+    424    : 00000000000000000;
+    425    : 00000000000000000;
+    426    : 00000000000000000;
+    427    : 00000000000000000;
+    428    : 00000000000000000;
+    429    : 00000000000000000;
+    430    : 00000000000000000;
+    431    : 00000000000000000;
+    432    : 00000000000000000;
+    433    : 00000000000000000;
+    434    : 00000000000000000;
+    435    : 00000000000000000;
+    436    : 00000000000000000;
+    437    : 00000000000000000;
+    438    : 00000000000000000;
+    439    : 00000000000000000;
+    440    : 00000000000000000;
+    441    : 00000000000000000;
+    442    : 00000000000000000;
+    443    : 00000000000000000;
+    444    : 00000000000000000;
+    445    : 00000000000000000;
+    446    : 00000000000000000;
+    447    : 00000000000000000;
+    448    : 00111110001000000;
+    449    : 10101011100100001;
+    450    : 10001010100000000;
+    451    : 10101011100100001;
+    452    : 00100011010000000;
+    453    : 10110000001100001;
+    454    : 10000000110000000;
+    455    : 10110000101100001;
+    456    : 00000000000000000;
+    457    : 10110000101100001;
+    458    : 10110110110100000;
+    459    : 10100001110100001;
+    460    : 00111100010000000;
+    461    : 10011101100000001;
+    462    : 10111110100100000;
+    463    : 10010011010100001;
+    464    : 00111100010100000;
+    465    : 10101011100000001;
+    466    : 10101001101000000;
+    467    : 10101011100000001;
+    468    : 00000000000000000;
+    469    : 10011111000100001;
+    470    : 10101001111000000;
+    471    : 10011011000100001;
+    472    : 00000000000000000;
+    473    : 10010011010100001;
+    474    : 00000000000000000;
+    475    : 00000000000000000;
+    476    : 00000000000000000;
+    477    : 00000000000000000;
+    478    : 00000000000000000;
+    479    : 00000000000000000;
+    480    : 00001010100000000;
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+    964    : 00000010000011110;
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+    987    : 00000000000000000;
+    988    : 00000000000000000;
+    989    : 00000000000000000;
+    990    : 00000000000000000;
+    991    : 00000000000000000;
+    992    : 10100111101000000;
+    993    : 00000000000000000;
+    994    : 10010010000000010;
+    995    : 10100111000000001;
+    996    : 10100111111000000;
+    997    : 00000000000000000;
+    998    : 10010010010000010;
+    999    : 10001110011100001;
+    1000   : 00100011001100000;
+    1001   : 00100001001001010;
+    1002   : 10010011000000010;
+    1003   : 10001010110100001;
+    1004   : 01100011011100000;
+    1005   : 00100001011001010;
+    1006   : 10010011010000010;
+    1007   : 10001010100100001;
+    1008   : 00000000000000000;
+    1009   : 00000000000000000;
+    1010   : 00000000000000000;
+    1011   : 00000000000000000;
+    1012   : 00000000000000000;
+    1013   : 00000000000000000;
+    1014   : 00000000000000000;
+    1015   : 00000000000000000;
+    1016   : 00000000000000000;
+    1017   : 00000000000000000;
+    1018   : 00000000000000000;
+    1019   : 00000000000000000;
+    1020   : 00000000000000000;
+    1021   : 00000000000000000;
+    1022   : 00000000000000000;
+    1023   : 00000000000000000;
+END;
diff --git a/nanorom.mif b/nanorom.mif
new file mode 100644
index 0000000..cb7f611
--- /dev/null
+++ b/nanorom.mif
@@ -0,0 +1,342 @@
+WIDTH=68;
+DEPTH=336;
+ADDRESS_RADIX=UNS;
+DATA_RADIX=BIN;
+CONTENT BEGIN
+    0      : 00000000000000000000000000000000000000000000000010000000000000000000;
+    1      : 00000000000000000000000000000000000000000000000010000000000000000000;
+    2      : 00000000000000000000000000000000000000000000000010000000000000000000;
+    3      : 00000000000000000000000000001000000110011100000000000000101001000001;
+    4      : 00100001000000011000010001001000000110100000000001000000011001001001;
+    5      : 00000001100000000010100000001000000110000000001001000000001001001001;
+    6      : 00100000000000011000010001000000000101000000000010000000100001010000;
+    7      : 11000001000000000000000000001000000100010000000001000000000001010001;
+    8      : 00100001000000011000010000000000000000000000000101000000000000010000;
+    9      : 01000001011000000000100000000110010001000000001100000000110100011000;
+    10     : 01000001011000000000100000000110010001000000001100000001100100011000;
+    11     : 00100001000000011000010000000000000100000000000001000000000001010000;
+    12     : 10100100001000011000001000010000101001110000000001000100110010100001;
+    13     : 01000000000000000000000010000000010100000000001000110001000000000000;
+    14     : 00100001000000011000000000110010100100011111010001100000000001000000;
+    15     : 00100010000000011000000000000000100010000100000000010100000100000011;
+    16     : 00000001011000000000000001000110000000000000000010000000000100000000;
+    17     : 00000000000000000000000000001000000100000000000001000000000001010001;
+    18     : 00000001100000000010100000001000000110000000001001010000001001001001;
+    19     : 00101000000000001000010000000000000000000000000010000000000000000000;
+    20     : 01100010000000011000010010000000010100000000001000110001000000000000;
+    21     : 00000000000000000000000010010010100000000000000100110010000000000000;
+    22     : 00100000000000011000010001001000000110000000001001010000001001001001;
+    23     : 00000000000000000000001000000000100100000000000000110010000001011000;
+    24     : 00010010000000000100100000001000000100000000000010000000000001010001;
+    25     : 00100010000000011100000000000000000001100000000010001000100000000000;
+    26     : 00010010000000000100000000000000010001100000000010000000000000000000;
+    27     : 00000000000000000000000000011001100110100000010001000000011011010001;
+    28     : 10100010110000000000000000000000100000010000010010000100000100000000;
+    29     : 10000000000000000000000000001000000100010000000001000000000001000001;
+    30     : 00100000000000011001000000011010000110000000001001000000001001001001;
+    31     : 00010011000000000000101000010000001001000000010101000000100000110000;
+    32     : 00000001000000000001010000000000000000000000000101100000000000010000;
+    33     : 00100010000000011000001000001000100110000000000001000000000001010001;
+    34     : 00000001000000000010100001010000001001000000010110000000100000110000;
+    35     : 01000001000000000000000000000000000001101010001100000000110000000000;
+    36     : 00110100000000000100000100000000000000000000000010000000000000000000;
+    37     : 00000000000100100000100000000000010000000000000000000001000000011000;
+    38     : 01110101000000000100100000100010000001100000000000000000110100001010;
+    39     : 00100010000000011010000100000000100010000100000000010100000100000011;
+    40     : 11000001000000000000000000001000000100010000000001000000000001010001;
+    41     : 01010011000000000100100000100010000001100000000000000000110100001010;
+    42     : 11000001000000000000000000001001100110110000000001000000011011000001;
+    43     : 01001001110000000000001000001000001000000000000101000000000000100001;
+    44     : 00000000000000000000100000100010010000000000000000110001000100000010;
+    45     : 00010000110000000001010000000000000000011100000010000000000000011000;
+    46     : 01010001110000000001000000011010100100000000000001000000000001000001;
+    47     : 00000000000000000000000001000000000100000000001100010000000001010000;
+    48     : 00001000000000011001001000001000000110100000000001000100000011010001;
+    49     : 01010001110000000001010000001000001000000000000101000000000000110001;
+    50     : 10100010110100100100000001000000000001110000000010000000110000010000;
+    51     : 00000000000100000000000000000010100001001010000101100000100000010000;
+    52     : 00010000110000000001000000000000100000000000010010000100000100000000;
+    53     : 10000000000000000000000000001000000100010000000001000000000001000001;
+    54     : 00000001000000000000000001000000001001000000000101000000100000100000;
+    55     : 00010010000000000000100000001010101000000000000101000000000000110001;
+    56     : 10100000000100111000000000100001100010111010000101100000011010010010;
+    57     : 00100000000000011000000000110010100110000000010000100000001101000010;
+    58     : 00010010000000001100000000000000000000000000000010000000000000000000;
+    59     : 11000001000000000000001000011101100100010000000001000000000001000001;
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