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<!--
This Source Code Form is subject to the terms of the Mozilla Public
License, v. 2.0. If a copy of the MPL was not distributed with this
file, You can obtain one at http://mozilla.org/MPL/2.0/.
-->
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8" />
<title>PCIe Configuration Space Viewer</title>
<style>
* {
box-sizing: border-box;
}
body {
margin: 0;
font-family: system-ui, -apple-system, BlinkMacSystemFont, "Segoe UI", sans-serif;
font-size: 13px;
color: #222;
}
.app {
display: flex;
flex-direction: column;
height: 100vh;
}
/* ---------- TOP: structures list ---------- */
.top-list {
flex: 0 0 40%;
border-bottom: 1px solid #ccc;
overflow-y: auto;
background: #f8fafc;
}
table {
width: 100%;
border-collapse: collapse;
}
thead {
position: sticky;
top: 0;
background: #e2edf7;
z-index: 1;
}
th,
td {
padding: 6px 8px;
border-bottom: 1px solid #e5e7eb;
text-align: left;
}
tr.struct-row {
cursor: pointer;
}
tr.struct-row:nth-child(even) td {
background: #f9fcff;
}
tr.struct-row.selected td {
background: #d1e3ff;
}
.id-col {
width: 80px;
}
.type-col {
width: 70px;
}
/* ---------- BOTTOM: bitfield + bit detail ---------- */
.bottom {
flex: 1 1 auto;
display: flex;
min-height: 0;
}
.bottom-left,
.bottom-right {
flex: 1;
overflow-y: auto;
padding: 8px;
}
.bottom-left {
border-right: 1px solid #e5e7eb;
background: #fafafa;
}
.section-title {
font-weight: 600;
margin: 0 0 6px;
font-size: 14px;
}
.section-subtitle {
margin: 0 0 10px;
font-size: 12px;
color: #555;
}
/* bitfield “map” (Bottom-Left) - Flexbox Layout */
.struct-container {
display: flex;
flex-direction: column;
background: #fff;
font-size: 11px;
border: 1px solid #ccc;
}
.struct-row-flex {
display: flex;
border-bottom: 1px solid #ccc;
height: 24px;
/* Fixed height for consistency */
}
.struct-row-flex:last-child {
border-bottom: none;
}
.struct-content-flex {
flex: 1;
/* Takes remaining space */
display: flex;
}
.struct-field-flex {
display: flex;
align-items: center;
justify-content: center;
border-right: 1px solid #7f7f7f;
overflow: hidden;
white-space: nowrap;
text-overflow: ellipsis;
cursor: pointer;
background: #fff;
box-sizing: border-box;
/* Include border in width */
padding: 0 4px;
}
.struct-field-flex:last-child {
border-right: none;
/* Last field in content area doesn't need right border */
}
.struct-field-flex:hover {
background: #e0f2fe;
}
.struct-field-flex.selected {
background: #a3d3a3;
border-color: #555;
}
.struct-offset-flex {
width: 40px;
/* Fixed width */
display: flex;
align-items: center;
justify-content: center;
background: #f0f0f0;
border-left: 1px solid #ccc;
font-weight: bold;
color: #333;
flex-shrink: 0;
/* Prevent shrinking */
}
/* bit detail (Bottom-Right) */
.detail-header {
display: flex;
align-items: baseline;
gap: 10px;
margin-bottom: 10px;
border-bottom: 1px solid #eee;
padding-bottom: 5px;
}
.detail-title {
font-size: 16px;
font-weight: bold;
}
.detail-subtitle {
font-size: 14px;
color: #666;
}
/* Visual Bit Bar */
.bit-bar-container {
margin-bottom: 15px;
font-family: monospace;
font-size: 10px;
}
.bit-numbers {
display: flex;
justify-content: space-between;
margin-bottom: 2px;
padding: 0 2px;
color: #555;
}
.bit-bar {
display: flex;
border: 1px solid #999;
height: 14px;
}
.bit-box {
flex: 1;
border-right: 1px solid #ccc;
background: #eee;
/* Default/Reserved */
}
.bit-box:last-child {
border-right: none;
}
.bit-box.active {
background: #fff;
/* Defined bits */
}
.bit-box.set {
background: #a3d3a3;
/* If we had values, but here just defined */
}
/* Description List */
.bit-list {
list-style: none;
padding: 0;
margin: 0;
}
.bit-list-item {
margin-bottom: 12px;
}
.bit-list-title {
font-size: 12px;
font-weight: bold;
color: #000;
}
.bit-list-desc {
font-size: 12px;
color: #333;
margin-left: 15px;
margin-top: 2px;
line-height: 1.4;
}
.bit-values-table {
margin-top: 4px;
margin-left: 15px;
border-collapse: collapse;
font-size: 11px;
width: auto;
}
.bit-values-table td {
border: none;
padding: 1px 6px 1px 0;
vertical-align: top;
color: #555;
background: transparent !important;
/* Override default table striping if any */
}
.bit-value-cell {
font-family: monospace;
font-weight: bold;
color: #444;
min-width: 20px;
}
.bit-meaning-cell {
color: #666;
}
/* simple top bar for future: config dump input等可以放這 */
.toolbar {
display: flex;
align-items: center;
gap: 8px;
padding: 4px 8px;
border-bottom: 1px solid #e5e7eb;
background: #f3f4f6;
font-size: 12px;
}
.toolbar input {
font-size: 12px;
padding: 3px 6px;
}
/* Splitters */
.splitter-horizontal {
height: 6px;
background: #e5e7eb;
cursor: row-resize;
flex: 0 0 auto;
display: flex;
align-items: center;
justify-content: center;
}
.splitter-horizontal::after {
content: "";
width: 30px;
height: 2px;
background: #bbb;
border-radius: 1px;
}
.splitter-horizontal:hover,
.splitter-horizontal.active {
background: #d1d5db;
}
.splitter-vertical {
width: 6px;
background: #e5e7eb;
cursor: col-resize;
flex: 0 0 auto;
display: flex;
align-items: center;
justify-content: center;
}
.splitter-vertical::after {
content: "";
height: 30px;
width: 2px;
background: #bbb;
border-radius: 1px;
}
.splitter-vertical:hover,
.splitter-vertical.active {
background: #d1d5db;
}
</style>
</head>
<body>
<div class="app">
<!-- optional toolbar: config dump / search can be added here later -->
<div class="toolbar">
<div style="font-weight:600;">PCIe Config Space Viewer</div>
<div style="margin-left:auto; font-size:11px; color:#4b5563;">
</div>
</div>
<!-- TOP: List of all Headers / Capabilities / Extended Capabilities -->
<div class="top-list" id="top-pane">
<table>
<thead>
<tr>
<th class="id-col">ID</th>
<th class="type-col">Type</th>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody id="structure-list-body">
<!-- JS render -->
</tbody>
</table>
</div>
<!-- Horizontal Splitter -->
<div class="splitter-horizontal" id="splitter-h"></div>
<!-- BOTTOM: Left = bitfield diagram, Right = bit description -->
<div class="bottom" id="bottom-pane">
<div class="bottom-left">
<div class="section-title" id="struct-title" style="background:#d1d5db; padding:4px; margin:0;">Structure</div>
<!-- Removed subtitle to match image style closer, or keep it minimal -->
<div style="padding:0;">
<div class="struct-container" id="bitfield-container">
<!-- JS render -->
</div>
</div>
<div class="placeholder" id="bitfield-placeholder" style="display:none; padding:8px;">
No bitfield layout defined.
</div>
</div>
<!-- Vertical Splitter -->
<div class="splitter-vertical" id="splitter-v"></div>
<div class="bottom-right" id="bottom-right-pane">
<div id="detail-container">
<!-- Header -->
<div class="detail-header">
<div class="detail-title" id="field-title">Select a register</div>
<div class="detail-subtitle" id="field-subtitle"></div>
</div>
<!-- Bit Bar -->
<div class="bit-bar-container" id="bit-bar-container" style="display:none;">
<div class="bit-numbers" id="bit-numbers"></div>
<div class="bit-bar" id="bit-bar"></div>
</div>
<!-- Description List -->
<ul class="bit-list" id="bit-list"></ul>
<div class="placeholder" id="bits-placeholder" style="display:none;">
No bit descriptions defined.
</div>
</div>
</div>
</div>
</div>
<script>
/**
* Note:
* - The structures here are just "templates + partial examples",
* you can follow this format to add other headers / capabilities / extended capabilities from the spec.
*
* Structure Explanation:
* - Each structure = One Header / Capability / Extended Capability.
* {
* id: "type0", // Custom ID, for JS use
* type: "Header|Cap|ExtCap",
* name: "Type 0 Header",
* description: "Brief description",
* rows: [ // For bottom-left bitfield diagram
* {
* offset: "00h",
* fields: [
* { id: "vendorid", label: "Vendor ID", range: "[15:0]" },
* ...
* ]
* },
* ...
* ],
* bitfields: { // For bottom-right bit detailed description
* status: {
* name: "Status",
* offset: "06h",
* range: "[31:16]",
* bits: [
* { range: "[3]", title: "Interrupt Status", description: "Placeholder text, please fill in according to the spec." },
* ...
* ]
* },
* ...
* }
* }
*/
const structures = [
/* =========================
* Type 0 / Type 1 Headers
* ========================= */
{
id: "type0",
type: "Header",
name: "Type 0 Header",
description: "First 64 bytes of configuration space for a non-bridge function.",
rows: [
{
offset: "00h",
fields: [
{ id: "vendorid", label: "Vendor ID", range: "[15:0]" },
{ id: "deviceid", label: "Device ID", range: "[31:16]" }
]
},
{
offset: "04h",
fields: [
{ id: "command", label: "Command", range: "[15:0]" },
{ id: "status", label: "Status", range: "[31:16]" }
]
},
{
offset: "08h",
fields: [
{ id: "revid", label: "Revision ID", range: "[7:0]" },
{ id: "classcode", label: "Class Code", range: "[31:8]" }
]
},
{
offset: "0Ch",
fields: [
{ id: "cacheline", label: "Cache Line Size", range: "[7:0]" },
{ id: "latency", label: "Latency Timer", range: "[15:8]" },
{ id: "hdrtype", label: "Header Type", range: "[23:16]" },
{ id: "bist", label: "BIST", range: "[31:24]" }
]
},
{
offset: "10h",
fields: [
{ id: "bar0", label: "Base Address Register 0", range: "[31:0]" }
]
},
{
offset: "14h",
fields: [
{ id: "bar1", label: "Base Address Register 1", range: "[31:0]" }
]
},
{
offset: "18h",
fields: [
{ id: "bar2", label: "Base Address Register 2", range: "[31:0]" }
]
},
{
offset: "1Ch",
fields: [
{ id: "bar3", label: "Base Address Register 3", range: "[31:0]" }
]
},
{
offset: "20h",
fields: [
{ id: "bar4", label: "Base Address Register 4", range: "[31:0]" }
]
},
{
offset: "24h",
fields: [
{ id: "bar5", label: "Base Address Register 5", range: "[31:0]" }
]
},
{
offset: "28h",
fields: [
{ id: "cardbus", label: "CardBus CIS Pointer", range: "[31:0]" }
]
},
{
offset: "2Ch",
fields: [
{ id: "subvendor", label: "Subsystem Vendor ID", range: "[15:0]" },
{ id: "subsysid", label: "Subsystem ID", range: "[31:16]" }
]
},
{
offset: "30h",
fields: [
{ id: "rombar", label: "Expansion ROM Base Address", range: "[31:0]" }
]
},
{
offset: "34h",
fields: [
{ id: "capptr", label: "Capabilities Pointer", range: "[7:0]" },
{ id: "reserved", label: "Reserved", range: "[31:8]" }
]
},
{
offset: "38h",
fields: [
{ id: "reserved2", label: "Reserved", range: "[31:0]" }
]
},
{
offset: "3Ch",
fields: [
{ id: "intline", label: "Interrupt Line", range: "[7:0]" },
{ id: "intpin", label: "Interrupt Pin", range: "[15:8]" },
{ id: "mingnt", label: "Min_Gnt", range: "[23:16]" },
{ id: "maxlat", label: "Max_Lat", range: "[31:24]" }
]
},
],
bitfields: {
command: {
name: "Command",
offset: "04h",
range: "[15:0]",
bits: [
{ range: "[0]", title: "I/O Space Enable", description: "Controls a Function's response to I/O Space accesses. When this bit is Clear, all received I/O accesses are caused to be handled as Unsupported Requests. When this bit is Set, the Function is enabled to decode the address and further process I/O Space accesses. For a Function with a Type 1 Configuration Space Header, this bit controls the response to I/O Space accesses received on its Primary Side. Default value of this bit is 0b. This bit is permitted to be hardwired to 0b if a Function does not support I/O Space accesses", values: { "0": "Disable", "1": "Enable" } },
{ range: "[1]", title: "Memory Space Enable", description: "\
Controls a Function's response to Memory Space accesses. When this bit is \
Clear, all received Memory Space accesses are caused to be handled as Unsupported Requests. When \
this bit is Set, the Function is enabled to decode the address and further process Memory Space\
accesses. For a Function with a Type 1 Configuration Space Header, this bit controls the response to\
Memory Space accesses received on its Primary Side.\
Default value of this bit is 0b.\
This bit is permitted to be hardwired to 0b if a Function does not support Memory Space accesses.", values: { "0": "Disable", "1": "Enable" } },
{ range: "[2]", title: "Bus Master Enable", description: "\
Controls the ability of a Function to issue Memory and I/O Read/Write Requests,\
and the ability of a Port to forward Memory and I/O Read/Write Requests in the Upstream direction\
When this bit is Set, the Function is allowed to issue Memory or I/O Requests.\
When this bit is Clear, the Function is not allowed to issue any Memory or I/O Requests.\
Note that as MSI/MSI-X interrupt Messages are in-band memory writes, setting the Bus Master\
Enable bit to 0b disables MSI/MSI-X interrupt Messages as well.\
Requests other than Memory or I/O Requests are not controlled by this bit.\
Default value of this bit is 0b.\
This bit is hardwired to 0b if a Function does not generate Memory or I/O Requests.", values: { "0": "Disable", "1": "Enable" } },
{ range: "[3]", title: "Special Cycle Enable", description: "\
This bit was originally described in the [PCI]. Its functionality does not apply to\
PCI Express and the bit must be hardwired to 0b." },
{ range: "[4]", title: "Memory Write and Invalidate", description: "\
This bit was originally described in the [PCI] and the [PCI-to-PCI-Bridge].\
Its functionality does not apply to PCI Express and the bit must be hardwired to 0b. For PCI Express to\
PCI/PCI-X Bridges, refer to the [PCIe-to-PCI-PCI-X-Bridge] for requirements for this register" },
{ range: "[5]", title: "VGA Palette Snoop", description: "RO for PCIe. Hardwired to 0." },
{ range: "[6]", title: "Parity Error Response", description: "Controls the Function’s response to parity errors.", values: { "0": "Disable", "1": "Enable" } },
{ range: "[7]", title: "IDSEL Stepping/Wait Cycle", description: "RO for PCIe. Hardwired to 0." },
{ range: "[8]", title: "SERR# Enable", description: "Controls the Enable for the SERR# driver.", values: { "0": "Disable", "1": "Enable" } },
{ range: "[9]", title: "Fast Back-to-Back Enable", description: "RO for PCIe. Hardwired to 0." },
{ range: "[10]", title: "Interrupt Disable", description: "Controls the ability of a Function to generate an INTx interrupt message.", values: { "0": "Enable INTx", "1": "Disable INTx" } },
{ range: "[15:11]", title: "Reserved", description: "Reserved." }
]
},
status: {
name: "Status",
offset: "06h",
range: "[15:0]",
bits: [
{ range: "[3]", title: "Interrupt Status", description: "Reflects the state of the interrupt in the function.", values: { "0": "Not Pending", "1": "Pending" } },
{ range: "[4]", title: "Capabilities List", description: "Indicates the presence of a Capabilities list.", values: { "0": "No", "1": "Yes" } },
{ range: "[5]", title: "66 MHz Capable", description: "RO for PCIe. Hardwired to 0." },
{ range: "[6]", title: "Reserved", description: "Reserved." },
{ range: "[7]", title: "Fast Back-to-Back Capable", description: "RO for PCIe. Hardwired to 0." },
{ range: "[8]", title: "Master Data Parity Error", description: "Set when the Function detects a parity error.", values: { "0": "Not Detected", "1": "Detected" } },
{ range: "[10:9]", title: "DEVSEL Timing", description: "RO for PCIe. Hardwired to 0." },
{ range: "[11]", title: "Signaled Target Abort", description: "Set when the Function completes a transaction with a Target Abort.", values: { "0": "Not Signaled", "1": "Signaled" } },
{ range: "[12]", title: "Received Target Abort", description: "Set when the Function receives a Target Abort.", values: { "0": "Not Received", "1": "Received" } },
{ range: "[13]", title: "Received Master Abort", description: "Set when the Function receives a Master Abort.", values: { "0": "Not Received", "1": "Received" } },
{ range: "[14]", title: "Signaled System Error", description: "Set when the Function signals SERR#.", values: { "0": "Not Signaled", "1": "Signaled" } },
{ range: "[15]", title: "Detected Parity Error", description: "Set when the Function detects a parity error.", values: { "0": "Not Detected", "1": "Detected" } }
]
},
revid: { name: "Revision ID", offset: "08h", range: "[7:0]", bits: [{ range: "[7:0]", title: "Revision ID", description: "Device specific revision identifier." }] },
classcode: { name: "Class Code", offset: "09h", range: "[23:0]", bits: [{ range: "[23:0]", title: "Class Code", description: "Identifies the general function of the device." }] },
cacheline: { name: "Cache Line Size", offset: "0Ch", range: "[7:0]", bits: [{ range: "[7:0]", title: "Cache Line Size", description: "Specifies the system cacheline size in 32-bit units." }] },
latency: { name: "Latency Timer", offset: "0Dh", range: "[7:0]", bits: [{ range: "[7:0]", title: "Latency Timer", description: "Not used in PCIe, hardwired to 0." }] },
hdrtype: { name: "Header Type", offset: "0Eh", range: "[7:0]", bits: [{ range: "[6:0]", title: "Header Layout", description: "Identifies the layout of the header (00h for Endpoint)." }, { range: "[7]", title: "Multi-Function Device", description: "Indicates if the device has multiple functions." }] },
bist: { name: "BIST", offset: "0Fh", range: "[7:0]", bits: [{ range: "[3:0]", title: "Completion Code", description: "Result of the BIST." }, { range: "[5:4]", title: "Reserved", description: "Reserved." }, { range: "[6]", title: "Start BIST", description: "Set to invoke BIST." }, { range: "[7]", title: "BIST Capable", description: "Indicates support for BIST." }] },
bar0: { name: "BAR0", offset: "10h", range: "[31:0]", bits: [{ range: "[0]", title: "Memory/IO", description: "0=Memory, 1=IO." }, { range: "[31:1]", title: "Base Address", description: "Base address." }] },
bar1: { name: "BAR1", offset: "14h", range: "[31:0]", bits: [{ range: "[31:0]", title: "Base Address", description: "Base address." }] },
bar2: { name: "BAR2", offset: "18h", range: "[31:0]", bits: [{ range: "[31:0]", title: "Base Address", description: "Base address." }] },
bar3: { name: "BAR3", offset: "1Ch", range: "[31:0]", bits: [{ range: "[31:0]", title: "Base Address", description: "Base address." }] },
bar4: { name: "BAR4", offset: "20h", range: "[31:0]", bits: [{ range: "[31:0]", title: "Base Address", description: "Base address." }] },
bar5: { name: "BAR5", offset: "24h", range: "[31:0]", bits: [{ range: "[31:0]", title: "Base Address", description: "Base address." }] },
cardbus: { name: "CardBus CIS Pointer", offset: "28h", range: "[31:0]", bits: [{ range: "[31:0]", title: "CardBus CIS Pointer", description: "Points to the CardBus CIS." }] },
subvendor: { name: "Subsystem Vendor ID", offset: "2Ch", range: "[15:0]", bits: [{ range: "[15:0]", title: "Subsystem Vendor ID", description: "Vendor ID of the add-in card." }] },
subsysid: { name: "Subsystem ID", offset: "2Eh", range: "[15:0]", bits: [{ range: "[15:0]", title: "Subsystem ID", description: "Device ID of the add-in card." }] },
rombar: { name: "Expansion ROM Base Address", offset: "30h", range: "[31:0]", bits: [{ range: "[0]", title: "Address Decode Enable", description: "Enables expansion ROM decoding." }, { range: "[31:11]", title: "Base Address", description: "Base address." }] },
capptr: { name: "Capabilities Pointer", offset: "34h", range: "[7:0]", bits: [{ range: "[7:0]", title: "Capabilities Pointer", description: "Points to the first capability in the list." }] },
intline: { name: "Interrupt Line", offset: "3Ch", range: "[7:0]", bits: [{ range: "[7:0]", title: "Interrupt Line", description: "System interrupt routing information." }] },
intpin: { name: "Interrupt Pin", offset: "3Dh", range: "[7:0]", bits: [{ range: "[7:0]", title: "Interrupt Pin", description: "Identifies the legacy interrupt pin used (1=INTA, etc.)." }] },
mingnt: { name: "Min_Gnt", offset: "3Eh", range: "[7:0]", bits: [{ range: "[7:0]", title: "Min_Gnt", description: "Length of burst period required." }] },
maxlat: { name: "Max_Lat", offset: "3Fh", range: "[7:0]", bits: [{ range: "[7:0]", title: "Max_Lat", description: "How often the device needs access to the bus." }] }
}
},
{
id: "type1",
type: "Header",
name: "Type 1 Header (Bridge)",
description: "Configuration header for PCI-to-PCI / PCIe-to-PCIe bridge functions.",
rows: [
{
offset: "00h",
fields: [
{ id: "vendorid", label: "Vendor ID", range: "[15:0]" },
{ id: "deviceid", label: "Device ID", range: "[31:16]" }
]
},
{
offset: "04h",
fields: [
{ id: "command", label: "Command", range: "[15:0]" },
{ id: "status", label: "Status", range: "[31:16]" }
]
},
{
offset: "08h",
fields: [
{ id: "revid", label: "Revision ID", range: "[7:0]" },
{ id: "classcode", label: "Class Code", range: "[31:8]" }
]
},
{
offset: "0Ch",
fields: [
{ id: "cacheline", label: "Cache Line Size", range: "[7:0]" },
{ id: "latency", label: "Latency Timer", range: "[15:8]" },
{ id: "hdrtype", label: "Header Type", range: "[23:16]" },
{ id: "bist", label: "BIST", range: "[31:24]" }
]
},
{
offset: "10h",
fields: [
{ id: "bar0", label: "Base Address Register 0", range: "[31:0]" }
]
},
{
offset: "14h",
fields: [
{ id: "bar1", label: "Base Address Register 1", range: "[31:0]" }
]
},
{
offset: "18h",
fields: [
{ id: "primary_bus", label: "Primary Bus", range: "[7:0]" },
{ id: "secondary_bus", label: "Secondary Bus", range: "[15:8]" },
{ id: "subordinate_bus", label: "Subordinate Bus", range: "[23:16]" },
{ id: "sec_latency", label: "Secondary Latency", range: "[31:24]" }
]
},
{
offset: "1Ch",
fields: [
{ id: "io_base", label: "I/O Base", range: "[7:0]" },
{ id: "io_limit", label: "I/O Limit", range: "[15:8]" },
{ id: "sec_status", label: "Secondary Status", range: "[31:16]" }
]
},
{
offset: "20h",
fields: [
{ id: "mem_base", label: "Memory Base", range: "[15:0]" },
{ id: "mem_limit", label: "Memory Limit", range: "[31:16]" }
]
},
{
offset: "24h",
fields: [
{ id: "pref_mem_base", label: "Prefetchable Memory Base", range: "[15:0]" },
{ id: "pref_mem_limit", label: "Prefetchable Memory Limit", range: "[31:16]" }
]
},
{
offset: "28h",
fields: [
{ id: "pref_base_upper", label: "Prefetchable Base Upper 32 Bits", range: "[31:0]" }
]
},
{
offset: "2Ch",
fields: [
{ id: "pref_limit_upper", label: "Prefetchable Limit Upper 32 Bits", range: "[31:0]" }
]
},
{
offset: "30h",
fields: [
{ id: "io_base_upper", label: "I/O Base Upper 16 Bits", range: "[15:0]" },
{ id: "io_limit_upper", label: "I/O Limit Upper 16 Bits", range: "[31:16]" }
]
},
{
offset: "34h",
fields: [
{ id: "capptr", label: "Capabilities Pointer", range: "[7:0]" },
{ id: "reserved", label: "Reserved", range: "[31:8]" }
]
},
{
offset: "38h",
fields: [
{ id: "rombar", label: "Expansion ROM Base Address", range: "[31:0]" }
]
},
{
offset: "3Ch",
fields: [
{ id: "intline", label: "Interrupt Line", range: "[7:0]" },
{ id: "intpin", label: "Interrupt Pin", range: "[15:8]" },
{ id: "bridgectl", label: "Bridge Control", range: "[31:16]" }
]
},
],
bitfields: {
command: {
name: "Command",
offset: "04h",
range: "[15:0]",
bits: [
{ range: "[0]", title: "I/O Space Enable", description: "Controls a Function’s response to I/O Space accesses.", values: { "0": "Disable", "1": "Enable" } },
{ range: "[1]", title: "Memory Space Enable", description: "Controls a Function’s response to Memory Space accesses.", values: { "0": "Disable", "1": "Enable" } },
{ range: "[2]", title: "Bus Master Enable", description: "Controls a Function’s ability to generate PCI accesses.", values: { "0": "Disable", "1": "Enable" } },
{ range: "[3]", title: "Special Cycle Enable", description: "RO for PCIe. Hardwired to 0." },
{ range: "[4]", title: "Memory Write and Invalidate", description: "RO for PCIe. Hardwired to 0." },
{ range: "[5]", title: "VGA Palette Snoop", description: "RO for PCIe. Hardwired to 0." },
{ range: "[6]", title: "Parity Error Response", description: "Controls the Function’s response to parity errors.", values: { "0": "Disable", "1": "Enable" } },
{ range: "[7]", title: "IDSEL Stepping/Wait Cycle", description: "RO for PCIe. Hardwired to 0." },
{ range: "[8]", title: "SERR# Enable", description: "Controls the Enable for the SERR# driver.", values: { "0": "Disable", "1": "Enable" } },
{ range: "[9]", title: "Fast Back-to-Back Enable", description: "RO for PCIe. Hardwired to 0." },
{ range: "[10]", title: "Interrupt Disable", description: "Controls the ability of a Function to generate an INTx interrupt message.", values: { "0": "Enable INTx", "1": "Disable INTx" } },
{ range: "[15:11]", title: "Reserved", description: "Reserved." }
]
},
status: {
name: "Status",
offset: "06h",
range: "[15:0]",
bits: [
{ range: "[3]", title: "Interrupt Status", description: "Reflects the state of the interrupt in the function.", values: { "0": "Not Pending", "1": "Pending" } },
{ range: "[4]", title: "Capabilities List", description: "Indicates the presence of a Capabilities list.", values: { "0": "No", "1": "Yes" } },
{ range: "[5]", title: "66 MHz Capable", description: "RO for PCIe. Hardwired to 0." },
{ range: "[6]", title: "Reserved", description: "Reserved." },
{ range: "[7]", title: "Fast Back-to-Back Capable", description: "RO for PCIe. Hardwired to 0." },
{ range: "[8]", title: "Master Data Parity Error", description: "Set when the Function detects a parity error.", values: { "0": "Not Detected", "1": "Detected" } },
{ range: "[10:9]", title: "DEVSEL Timing", description: "RO for PCIe. Hardwired to 0." },
{ range: "[11]", title: "Signaled Target Abort", description: "Set when the Function completes a transaction with a Target Abort.", values: { "0": "Not Signaled", "1": "Signaled" } },
{ range: "[12]", title: "Received Target Abort", description: "Set when the Function receives a Target Abort.", values: { "0": "Not Received", "1": "Received" } },
{ range: "[13]", title: "Received Master Abort", description: "Set when the Function receives a Master Abort.", values: { "0": "Not Received", "1": "Received" } },
{ range: "[14]", title: "Signaled System Error", description: "Set when the Function signals SERR#.", values: { "0": "Not Signaled", "1": "Signaled" } },
{ range: "[15]", title: "Detected Parity Error", description: "Set when the Function detects a parity error.", values: { "0": "Not Detected", "1": "Detected" } }
]
},
revid: { name: "Revision ID", offset: "08h", range: "[7:0]", bits: [{ range: "[7:0]", title: "Revision ID", description: "Device specific revision identifier." }] },
classcode: { name: "Class Code", offset: "09h", range: "[31:8]", bits: [{ range: "[31:8]", title: "Class Code", description: "Identifies the general function of the device." }] },
cacheline: { name: "Cache Line Size", offset: "0Ch", range: "[7:0]", bits: [{ range: "[7:0]", title: "Cache Line Size", description: "Specifies the system cacheline size in 32-bit units." }] },
latency: { name: "Latency Timer", offset: "0Dh", range: "[7:0]", bits: [{ range: "[7:0]", title: "Latency Timer", description: "Not used in PCIe, hardwired to 0." }] },
hdrtype: { name: "Header Type", offset: "0Eh", range: "[7:0]", bits: [{ range: "[6:0]", title: "Header Layout", description: "Identifies the layout of the header (01h for Bridge)." }, { range: "[7]", title: "Multi-Function Device", description: "Indicates if the device has multiple functions." }] },
bist: { name: "BIST", offset: "0Fh", range: "[7:0]", bits: [{ range: "[3:0]", title: "Completion Code", description: "Result of the BIST." }, { range: "[5:4]", title: "Reserved", description: "Reserved." }, { range: "[6]", title: "Start BIST", description: "Set to invoke BIST." }, { range: "[7]", title: "BIST Capable", description: "Indicates support for BIST." }] },
bar0: { name: "BAR0", offset: "10h", range: "[31:0]", bits: [{ range: "[0]", title: "Memory/IO", description: "0=Memory, 1=IO." }, { range: "[31:1]", title: "Base Address", description: "Base address." }] },
bar1: { name: "BAR1", offset: "14h", range: "[31:0]", bits: [{ range: "[31:0]", title: "Base Address", description: "Base address." }] },
primary_bus: { name: "Primary Bus", offset: "18h", range: "[7:0]", bits: [{ range: "[7:0]", title: "Primary Bus Number", description: "Bus number on the upstream side of the bridge." }] },
secondary_bus: { name: "Secondary Bus", offset: "19h", range: "[7:0]", bits: [{ range: "[7:0]", title: "Secondary Bus Number", description: "Bus number on the downstream side of the bridge." }] },
subordinate_bus: { name: "Subordinate Bus", offset: "1Ah", range: "[7:0]", bits: [{ range: "[7:0]", title: "Subordinate Bus Number", description: "Highest bus number downstream of the bridge." }] },
sec_latency: { name: "Secondary Latency Timer", offset: "1Bh", range: "[7:0]", bits: [{ range: "[7:0]", title: "Secondary Latency Timer", description: "Not used in PCIe, hardwired to 0." }] },
io_base: { name: "I/O Base", offset: "1Ch", range: "[7:0]", bits: [{ range: "[3:0]", title: "Addressing Capability", description: "01h=32-bit I/O." }, { range: "[7:4]", title: "I/O Base Address", description: "Upper 4 bits of the I/O base address." }] },
io_limit: { name: "I/O Limit", offset: "1Dh", range: "[7:0]", bits: [{ range: "[3:0]", title: "Addressing Capability", description: "01h=32-bit I/O." }, { range: "[7:4]", title: "I/O Limit Address", description: "Upper 4 bits of the I/O limit address." }] },
sec_status: { name: "Secondary Status", offset: "1Eh", range: "[15:0]", bits: [{ range: "[15:0]", title: "Secondary Status", description: "Status of the secondary interface." }] },
mem_base: { name: "Memory Base", offset: "20h", range: "[15:0]", bits: [{ range: "[3:0]", title: "Reserved", description: "Reserved." }, { range: "[15:4]", title: "Memory Base Address", description: "Upper 12 bits of the memory base address." }] },
mem_limit: { name: "Memory Limit", offset: "22h", range: "[15:0]", bits: [{ range: "[3:0]", title: "Reserved", description: "Reserved." }, { range: "[15:4]", title: "Memory Limit Address", description: "Upper 12 bits of the memory limit address." }] },
pref_mem_base: { name: "Prefetchable Memory Base", offset: "24h", range: "[15:0]", bits: [{ range: "[3:0]", title: "Addressing Capability", description: "0=32-bit, 1=64-bit." }, { range: "[15:4]", title: "Prefetchable Memory Base Address", description: "Upper 12 bits of the prefetchable memory base address." }] },
pref_mem_limit: { name: "Prefetchable Memory Limit", offset: "26h", range: "[15:0]", bits: [{ range: "[3:0]", title: "Addressing Capability", description: "0=32-bit, 1=64-bit." }, { range: "[15:4]", title: "Prefetchable Memory Limit Address", description: "Upper 12 bits of the prefetchable memory limit address." }] },
pref_base_upper: { name: "Prefetchable Base Upper 32 Bits", offset: "28h", range: "[31:0]", bits: [{ range: "[31:0]", title: "Base Address Upper", description: "Upper 32 bits of the prefetchable base address." }] },
pref_limit_upper: { name: "Prefetchable Limit Upper 32 Bits", offset: "2Ch", range: "[31:0]", bits: [{ range: "[31:0]", title: "Limit Address Upper", description: "Upper 32 bits of the prefetchable limit address." }] },
io_base_upper: { name: "I/O Base Upper 16 Bits", offset: "30h", range: "[15:0]", bits: [{ range: "[15:0]", title: "I/O Base Upper", description: "Upper 16 bits of the I/O base address." }] },
io_limit_upper: { name: "I/O Limit Upper 16 Bits", offset: "32h", range: "[15:0]", bits: [{ range: "[15:0]", title: "I/O Limit Upper", description: "Upper 16 bits of the I/O limit address." }] },
capptr: { name: "Capabilities Pointer", offset: "34h", range: "[7:0]", bits: [{ range: "[7:0]", title: "Capabilities Pointer", description: "Points to the first capability in the list." }] },
rombar: { name: "Expansion ROM Base Address", offset: "38h", range: "[31:0]", bits: [{ range: "[0]", title: "Address Decode Enable", description: "Enables expansion ROM decoding." }, { range: "[31:11]", title: "Base Address", description: "Base address." }] },
intline: { name: "Interrupt Line", offset: "3Ch", range: "[7:0]", bits: [{ range: "[7:0]", title: "Interrupt Line", description: "System interrupt routing information." }] },
intpin: { name: "Interrupt Pin", offset: "3Dh", range: "[7:0]", bits: [{ range: "[7:0]", title: "Interrupt Pin", description: "Identifies the legacy interrupt pin used (1=INTA, etc.)." }] },
bridgectl: {
name: "Bridge Control",
offset: "3Eh",
range: "[15:0]",
bits: [
{ range: "[0]", title: "Parity Error Response", description: "Controls the bridge’s response to parity errors on the secondary interface.", values: { "0": "Ignore", "1": "Report" } },
{ range: "[1]", title: "SERR# Enable", description: "Controls the forwarding of SERR#.", values: { "0": "Disable", "1": "Enable" } },
{ range: "[2]", title: "ISA Enable", description: "Modifies the response to I/O accesses.", values: { "0": "Disable", "1": "Enable" } },
{ range: "[3]", title: "VGA Enable", description: "Controls the routing of VGA addresses.", values: { "0": "Disable", "1": "Enable" } },
{ range: "[4]", title: "VGA 16-bit Decode", description: "Controls the decoding of VGA I/O addresses.", values: { "0": "10-bit", "1": "16-bit" } },
{ range: "[5]", title: "Master Abort Mode", description: "Controls the bridge’s behavior when a Master Abort occurs.", values: { "0": "Report", "1": "Ignore" } },
{ range: "[6]", title: "Secondary Bus Reset", description: "Forces a reset on the secondary bus.", values: { "0": "Clear", "1": "Set" } },
{ range: "[7]", title: "Fast Back-to-Back Enable", description: "RO for PCIe. Hardwired to 0." },
{ range: "[8]", title: "Primary Discard Timer", description: "Controls the primary discard timer." },
{ range: "[9]", title: "Secondary Discard Timer", description: "Controls the secondary discard timer." },
{ range: "[10]", title: "Discard Timer Status", description: "Status of the discard timer." },
{ range: "[11]", title: "Discard Timer SERR# Enable", description: "Controls SERR# generation for discard timer." },
{ range: "[15:12]", title: "Reserved", description: "Reserved." }
]
}
}
},
/* =========================
* PCI Power Management Cap
* ========================= */
{
id: "pm_cap",
type: "Cap",
name: "Power Management Capability (PM)",
description: "Legacy PCI-style Power Management capability structure.",
rows: [
{
offset: "00h",
fields: [
{ id: "capid", label: "Cap ID", range: "[7:0]" },
{ id: "nextptr", label: "Next Ptr", range: "[15:8]" },
{ id: "pmcap", label: "PM Capabilities", range: "[31:16]" }
]
},
{
offset: "04h",
fields: [
{ id: "pmcsr", label: "PM Control / Status", range: "[15:0]" },
{ id: "pm_bridge_ext", label: "Bridge Extensions", range: "[23:16]" },
{ id: "pm_data", label: "Data", range: "[31:24]" }
]
}
],
bitfields: {
capid: { name: "Capability ID", offset: "00h", range: "[7:0]", bits: [{ range: "[7:0]", title: "Capability ID", description: "ID = 01h for Power Management." }] },
nextptr: { name: "Next Item Pointer", offset: "01h", range: "[7:0]", bits: [{ range: "[7:0]", title: "Next Item Pointer", description: "Pointer to the next capability." }] },
pmcap: {
name: "PM Capabilities",
offset: "02h",
range: "[15:0]",
bits: [
{ range: "[2:0]", title: "Version", description: "PM Spec Version (011b = 1.2).", values: { "2": "1.1", "3": "1.2" } },
{ range: "[3]", title: "PME Clock", description: "Indicates if PME# generation requires a PCI clock.", values: { "0": "No", "1": "Yes" } },
{ range: "[4]", title: "Reserved", description: "Reserved." },
{ range: "[5]", title: "DSI", description: "Device Specific Initialization.", values: { "0": "No", "1": "Yes" } },
{ range: "[8:6]", title: "Aux_Current", description: "Auxiliary Current Requirements." },
{ range: "[9]", title: "D1 Support", description: "Supports D1 Power Management State.", values: { "0": "No", "1": "Yes" } },
{ range: "[10]", title: "D2 Support", description: "Supports D2 Power Management State.", values: { "0": "No", "1": "Yes" } },
{ range: "[15:11]", title: "PME Support", description: "Indicates PME# support in various power states." }
]
},
pmcsr: {
name: "PM Control / Status",
offset: "04h",
range: "[15:0]",
bits: [
{ range: "[1:0]", title: "Power State", description: "Current power state (00=D0, 01=D1, 10=D2, 11=D3).", values: { "0": "D0", "1": "D1", "2": "D2", "3": "D3hot" } },
{ range: "[2]", title: "Reserved", description: "Reserved." },
{ range: "[3]", title: "No Soft Reset", description: "Device transitions from D3hot to D0 without internal reset.", values: { "0": "Reset", "1": "No Reset" } },
{ range: "[7:4]", title: "Reserved", description: "Reserved." },
{ range: "[8]", title: "PME Enable", description: "Enables PME# generation.", values: { "0": "Disable", "1": "Enable" } },
{ range: "[12:9]", title: "Data Select", description: "Selects which data is reported in the Data register." },
{ range: "[14:13]", title: "Data Scale", description: "Scaling factor for the Data register.", values: { "0": "Unknown", "1": "0.1x", "2": "0.01x", "3": "0.001x" } },
{ range: "[15]", title: "PME Status", description: "Indicates if a PME event occurred.", values: { "0": "Not Asserted", "1": "Asserted" } }
]
},
pm_bridge_ext: { name: "PM Bridge Extensions", offset: "06h", range: "[7:0]", bits: [{ range: "[7:0]", title: "Bridge Extensions", description: "Bus Power/Clock Control Enable, B2/B3 support." }] },
pm_data: { name: "Data", offset: "07h", range: "[7:0]", bits: [{ range: "[7:0]", title: "Data", description: "Power consumption or heat dissipation data." }] }
}
},
/* =========================
* PCI Express Capability
* ========================= */
{
id: "pcie_cap",
type: "Cap",
name: "PCI Express Capability",
description: "Registers for PCI Express device, link, slot, and root capabilities / status.",
rows: [
{
offset: "00h",
fields: [
{ id: "capid", label: "Cap ID", range: "[7:0]" },
{ id: "nextptr", label: "Next Ptr", range: "[15:8]" },
{ id: "pcie_cap_reg", label: "PCIe Capabilities", range: "[31:16]" }
]
},
{
offset: "04h",
fields: [
{ id: "devcap", label: "Device Capabilities", range: "[31:0]" }
]
},
{
offset: "08h",
fields: [
{ id: "devctl", label: "Device Control", range: "[15:0]" },
{ id: "devsta", label: "Device Status", range: "[15:0]" }
]
},
{
offset: "0Ch",
fields: [
{ id: "linkcap", label: "Link Capabilities", range: "[31:0]" }
]
},
{
offset: "10h",
fields: [
{ id: "linkctl", label: "Link Control", range: "[15:0]" },
{ id: "linksta", label: "Link Status", range: "[15:0]" }
]
},
{
offset: "14h",
fields: [
{ id: "slotcap", label: "Slot Capabilities", range: "[31:0]" }
]
},
{
offset: "18h",
fields: [
{ id: "slotctl", label: "Slot Control", range: "[15:0]" },