From 0a208d09959e7b03a14a53689e04f953602cdf46 Mon Sep 17 00:00:00 2001 From: Tuyen Date: Mon, 13 Aug 2018 16:22:49 +0700 Subject: [PATCH 1/2] Add TrueSTUDIO project --- F4-Gyro-RTOS/.cproject | 318 ++++++++ F4-Gyro-RTOS/.project | 76 ++ ...lic.truestudio.debug.hardware_device.prefs | 11 + F4-Gyro-RTOS/.settings/language.settings.xml | 20 + .../org.eclipse.cdt.managedbuilder.core.prefs | 11 + .../Drivers/BSP/Components/ov2640/ov2640.su | 3 + .../Drivers/BSP/Components/s5k5cag/s5k5cag.su | 3 + .../Drivers/BSP/Components/ts3510/ts3510.su | 10 + .../Drivers/BSP/Components/wm8994/wm8994.su | 12 + .../STM32F4-Discovery/stm32f4_discovery.su | 18 + .../stm32f4_discovery_audio.su | 0 .../STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su | 25 + .../Src/stm32f4xx_hal_cortex.su | 18 + .../Src/stm32f4xx_hal_flash.su | 16 + .../Src/stm32f4xx_hal_gpio.su | 8 + .../Src/stm32f4xx_hal_i2c.su | 57 ++ .../Src/stm32f4xx_hal_i2c_ex.su | 0 .../Src/stm32f4xx_hal_i2s.su | 28 + .../Src/stm32f4xx_hal_i2s_ex.su | 10 + .../Src/stm32f4xx_hal_pcd.su | 32 + .../Src/stm32f4xx_hal_pcd_ex.su | 2 + .../Src/stm32f4xx_hal_pwr.su | 17 + .../Src/stm32f4xx_hal_pwr_ex.su | 6 + .../Src/stm32f4xx_hal_rcc_ex.su | 6 + .../Src/stm32f4xx_hal_spi.su | 54 ++ .../Src/stm32f4xx_hal_tim_ex.su | 37 + .../Src/stm32f4xx_ll_usb.su | 45 ++ .../Class/CDC/Src/usbd_cdc.su | 15 + .../Core/Src/usbd_core.su | 20 + .../Core/Src/usbd_ioreq.su | 7 + .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su | 53 ++ .../Third_Party/FreeRTOS/Source/croutine.su | 0 .../FreeRTOS/Source/event_groups.su | 9 + .../Third_Party/FreeRTOS/Source/list.su | 5 + .../Source/portable/GCC/ARM_CM4F/port.su | 13 + .../Third_Party/FreeRTOS/Source/queue.su | 21 + .../Third_Party/FreeRTOS/Source/tasks.su | 43 + .../Third_Party/FreeRTOS/Source/timers.su | 0 F4-Gyro-RTOS/Debug/Src/freertos.su | 0 F4-Gyro-RTOS/Debug/Src/main.su | 8 + F4-Gyro-RTOS/Debug/Src/stm32f4xx_hal_msp.su | 7 + .../Debug/Src/stm32f4xx_hal_timebase_TIM.su | 3 + F4-Gyro-RTOS/Debug/Src/stm32f4xx_it.su | 3 + F4-Gyro-RTOS/Debug/Src/system_stm32f4xx.su | 2 + F4-Gyro-RTOS/Debug/Src/usb_device.su | 1 + F4-Gyro-RTOS/Debug/Src/usbd_cdc_if.su | 5 + F4-Gyro-RTOS/Debug/Src/usbd_desc.su | 7 + F4-Gyro-RTOS/F4-Gyro-RTOS.elf.launch | 46 ++ .../Source/portable/GCC/ARM_CM4F/port.c | 763 ++++++++++++++++++ .../Source/portable/GCC/ARM_CM4F/portmacro.h | 284 +++++++ F4-Gyro-RTOS/STM32F407VG_FLASH.ld | 188 +++++ F4-Gyro-RTOS/startup/startup_stm32f407xx.s | 521 ++++++++++++ 52 files changed, 2867 insertions(+) create mode 100644 F4-Gyro-RTOS/.cproject create mode 100644 F4-Gyro-RTOS/.project create mode 100644 F4-Gyro-RTOS/.settings/com.atollic.truestudio.debug.hardware_device.prefs create mode 100644 F4-Gyro-RTOS/.settings/language.settings.xml create mode 100644 F4-Gyro-RTOS/.settings/org.eclipse.cdt.managedbuilder.core.prefs create mode 100644 F4-Gyro-RTOS/Debug/Drivers/BSP/Components/ov2640/ov2640.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/BSP/Components/s5k5cag/s5k5cag.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/BSP/Components/ts3510/ts3510.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/BSP/Components/wm8994/wm8994.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_audio.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.su create mode 100644 F4-Gyro-RTOS/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.su create mode 100644 F4-Gyro-RTOS/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.su create mode 100644 F4-Gyro-RTOS/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su create mode 100644 F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su create mode 100644 F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su create mode 100644 F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su create mode 100644 F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su create mode 100644 F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.su create mode 100644 F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su create mode 100644 F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su create mode 100644 F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su create mode 100644 F4-Gyro-RTOS/Debug/Src/freertos.su create mode 100644 F4-Gyro-RTOS/Debug/Src/main.su create mode 100644 F4-Gyro-RTOS/Debug/Src/stm32f4xx_hal_msp.su create mode 100644 F4-Gyro-RTOS/Debug/Src/stm32f4xx_hal_timebase_TIM.su create mode 100644 F4-Gyro-RTOS/Debug/Src/stm32f4xx_it.su create mode 100644 F4-Gyro-RTOS/Debug/Src/system_stm32f4xx.su create mode 100644 F4-Gyro-RTOS/Debug/Src/usb_device.su create mode 100644 F4-Gyro-RTOS/Debug/Src/usbd_cdc_if.su create mode 100644 F4-Gyro-RTOS/Debug/Src/usbd_desc.su create mode 100644 F4-Gyro-RTOS/F4-Gyro-RTOS.elf.launch create mode 100644 F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c create mode 100644 F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h create mode 100644 F4-Gyro-RTOS/STM32F407VG_FLASH.ld create mode 100644 F4-Gyro-RTOS/startup/startup_stm32f407xx.s diff --git a/F4-Gyro-RTOS/.cproject b/F4-Gyro-RTOS/.cproject new file mode 100644 index 0000000..ab000d3 --- /dev/null +++ b/F4-Gyro-RTOS/.cproject @@ -0,0 +1,318 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/F4-Gyro-RTOS/.project b/F4-Gyro-RTOS/.project new file mode 100644 index 0000000..faa95fe --- /dev/null +++ b/F4-Gyro-RTOS/.project @@ -0,0 +1,76 @@ + + + F4-Gyro-RTOS + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?children? + ?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\|| + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/STM32100B-EVAL/Debug} + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + + diff --git a/F4-Gyro-RTOS/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/F4-Gyro-RTOS/.settings/com.atollic.truestudio.debug.hardware_device.prefs new file mode 100644 index 0000000..f4a1b13 --- /dev/null +++ b/F4-Gyro-RTOS/.settings/com.atollic.truestudio.debug.hardware_device.prefs @@ -0,0 +1,11 @@ +BOARD=None +CODE_LOCATION=FLASH +ENDIAN=Little-endian +MCU=STM32F407VG +MCU_VENDOR=STMicroelectronics +MODEL=Lite +PROBE=ST-LINK +PROJECT_FORMAT_VERSION=2 +TARGET=ARM\u00AE +VERSION=4.1.0 +eclipse.preferences.version=1 diff --git a/F4-Gyro-RTOS/.settings/language.settings.xml b/F4-Gyro-RTOS/.settings/language.settings.xml new file mode 100644 index 0000000..eec129f --- /dev/null +++ b/F4-Gyro-RTOS/.settings/language.settings.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/F4-Gyro-RTOS/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/F4-Gyro-RTOS/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 0000000..66eb673 --- /dev/null +++ b/F4-Gyro-RTOS/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,11 @@ +eclipse.preferences.version=1 +environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/CPATH/delimiter=; +environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/CPATH/operation=remove +environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/C_INCLUDE_PATH/delimiter=; +environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/C_INCLUDE_PATH/operation=remove +environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/append=true +environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/appendContributed=true +environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/LIBRARY_PATH/delimiter=; +environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/LIBRARY_PATH/operation=remove +environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/append=true +environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/appendContributed=true diff --git a/F4-Gyro-RTOS/Debug/Drivers/BSP/Components/ov2640/ov2640.su b/F4-Gyro-RTOS/Debug/Drivers/BSP/Components/ov2640/ov2640.su new file mode 100644 index 0000000..f7de7af --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/BSP/Components/ov2640/ov2640.su @@ -0,0 +1,3 @@ +ov2640.c:1046:6:ov2640_Init 16 static +ov2640.c:1172:10:ov2640_ReadID 8 static +ov2640.c:1112:6:ov2640_Config 16 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/BSP/Components/s5k5cag/s5k5cag.su b/F4-Gyro-RTOS/Debug/Drivers/BSP/Components/s5k5cag/s5k5cag.su new file mode 100644 index 0000000..61f745c --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/BSP/Components/s5k5cag/s5k5cag.su @@ -0,0 +1,3 @@ +s5k5cag.c:3270:10:s5k5cag_ReadID 8 static +s5k5cag.c:3141:6:s5k5cag_Config 24 static +s5k5cag.c:3060:6:s5k5cag_Init 32 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/BSP/Components/ts3510/ts3510.su b/F4-Gyro-RTOS/Debug/Drivers/BSP/Components/ts3510/ts3510.su new file mode 100644 index 0000000..c228dc3 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/BSP/Components/ts3510/ts3510.su @@ -0,0 +1,10 @@ +ts3510.c:138:10:ts3510_ReadID 0 static +ts3510.c:227:9:ts3510_TS_ITStatus 0 static +ts3510.c:237:6:ts3510_TS_ClearIT 0 static +ts3510.c:116:6:ts3510_Init 0 static +ts3510.c:157:9:ts3510_TS_DetectTouch 24 static +ts3510.c:186:6:ts3510_TS_GetXY 32 static +ts3510.c:209:6:ts3510_TS_EnableIT 0 static +ts3510.c:218:6:ts3510_TS_DisableIT 0 static +ts3510.c:128:6:ts3510_Reset 0 static +ts3510.c:148:6:ts3510_TS_Start 0 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/BSP/Components/wm8994/wm8994.su b/F4-Gyro-RTOS/Debug/Drivers/BSP/Components/wm8994/wm8994.su new file mode 100644 index 0000000..b086969 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/BSP/Components/wm8994/wm8994.su @@ -0,0 +1,12 @@ +wm8994.c:850:10:wm8994_SetOutputMode 8 static +wm8994.c:937:10:wm8994_SetFrequency 8 static +wm8994.c:992:10:wm8994_Reset 8 static +wm8994.c:609:6:wm8994_DeInit 0 static +wm8994.c:620:10:wm8994_ReadID 8 static +wm8994.c:815:10:wm8994_SetMute 8 static +wm8994.c:634:10:wm8994_Play 0 static +wm8994.c:650:10:wm8994_Pause 16 static +wm8994.c:669:10:wm8994_Resume 0 static +wm8994.c:739:10:wm8994_SetVolume 24 static +wm8994.c:136:10:wm8994_Init 40 static +wm8994.c:693:10:wm8994_Stop 24 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery.su b/F4-Gyro-RTOS/Debug/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery.su new file mode 100644 index 0000000..17a2579 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery.su @@ -0,0 +1,18 @@ +stm32f4_discovery.c:309:13:SPIx_Init 40 static +stm32f4_discovery.c:338:16:SPIx_WriteRead 32 static +stm32f4_discovery.c:390:13:I2Cx_Init 48 static +stm32f4_discovery.c:156:10:BSP_GetVersion 0 static +stm32f4_discovery.c:170:6:BSP_LED_Init 56 static +stm32f4_discovery.c:197:6:BSP_LED_On 0 static +stm32f4_discovery.c:211:6:BSP_LED_Off 0 static +stm32f4_discovery.c:225:6:BSP_LED_Toggle 0 static +stm32f4_discovery.c:248:6:BSP_PB_Init 32 static +stm32f4_discovery.c:287:10:BSP_PB_GetState 8 static +stm32f4_discovery.c:508:6:ACCELERO_IO_Init 40 static +stm32f4_discovery.c:533:6:ACCELERO_IO_ITConfig 32 static +stm32f4_discovery.c:558:6:ACCELERO_IO_Write 16 static +stm32f4_discovery.c:592:6:ACCELERO_IO_Read 16 static +stm32f4_discovery.c:626:6:AUDIO_IO_Init 48 static +stm32f4_discovery.c:658:6:AUDIO_IO_DeInit 0 static +stm32f4_discovery.c:669:6:AUDIO_IO_Write 32 static +stm32f4_discovery.c:680:9:AUDIO_IO_Read 32 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_audio.su b/F4-Gyro-RTOS/Debug/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_audio.su new file mode 100644 index 0000000..e69de29 diff --git a/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su new file mode 100644 index 0000000..e6f321f --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su @@ -0,0 +1,25 @@ +stm32f4xx_hal.c:235:13:HAL_MspInit 0 static +stm32f4xx_hal.c:246:13:HAL_MspDeInit 0 static +stm32f4xx_hal.c:206:19:HAL_DeInit 8 static +stm32f4xx_hal.c:269:26:HAL_InitTick 16 static +stm32f4xx_hal.c:173:19:HAL_Init 8 static +stm32f4xx_hal.c:328:13:HAL_IncTick 0 static +stm32f4xx_hal.c:339:17:HAL_GetTick 0 static +stm32f4xx_hal.c:348:10:HAL_GetTickPrio 0 static +stm32f4xx_hal.c:357:19:HAL_SetTickFreq 8 static +stm32f4xx_hal.c:377:21:HAL_GetTickFreq 0 static +stm32f4xx_hal.c:393:13:HAL_Delay 16 static +stm32f4xx_hal.c:419:13:HAL_SuspendTick 0 static +stm32f4xx_hal.c:435:13:HAL_ResumeTick 0 static +stm32f4xx_hal.c:445:10:HAL_GetHalVersion 0 static +stm32f4xx_hal.c:454:10:HAL_GetREVID 0 static +stm32f4xx_hal.c:463:10:HAL_GetDEVID 0 static +stm32f4xx_hal.c:472:6:HAL_DBGMCU_EnableDBGSleepMode 0 static +stm32f4xx_hal.c:481:6:HAL_DBGMCU_DisableDBGSleepMode 0 static +stm32f4xx_hal.c:490:6:HAL_DBGMCU_EnableDBGStopMode 0 static +stm32f4xx_hal.c:499:6:HAL_DBGMCU_DisableDBGStopMode 0 static +stm32f4xx_hal.c:508:6:HAL_DBGMCU_EnableDBGStandbyMode 0 static +stm32f4xx_hal.c:517:6:HAL_DBGMCU_DisableDBGStandbyMode 0 static +stm32f4xx_hal.c:528:6:HAL_EnableCompensationCell 0 static +stm32f4xx_hal.c:539:6:HAL_DisableCompensationCell 0 static +stm32f4xx_hal.c:549:6:HAL_GetUID 0 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su new file mode 100644 index 0000000..a849056 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su @@ -0,0 +1,18 @@ +stm32f4xx_hal_cortex.c:159:6:HAL_NVIC_SetPriorityGrouping 0 static +stm32f4xx_hal_cortex.c:181:6:HAL_NVIC_SetPriority 12 static +stm32f4xx_hal_cortex.c:203:6:HAL_NVIC_EnableIRQ 0 static +stm32f4xx_hal_cortex.c:219:6:HAL_NVIC_DisableIRQ 0 static +stm32f4xx_hal_cortex.c:232:6:HAL_NVIC_SystemReset 0 static +stm32f4xx_hal_cortex.c:245:10:HAL_SYSTICK_Config 0 static +stm32f4xx_hal_cortex.c:274:6:HAL_MPU_Disable 0 static +stm32f4xx_hal_cortex.c:297:6:HAL_MPU_Enable 0 static +stm32f4xx_hal_cortex.c:316:6:HAL_MPU_ConfigRegion 8 static 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+stm32f4xx_hal_flash.c:656:13:FLASH_Program_Word 0 static +stm32f4xx_hal_flash.c:681:13:FLASH_Program_HalfWord 0 static +stm32f4xx_hal_flash.c:723:13:FLASH_SetErrorCode 0 static +stm32f4xx_hal_flash.c:230:19:HAL_FLASH_Program_IT 24 static +stm32f4xx_hal_flash.c:400:13:HAL_FLASH_EndOfOperationCallback 0 static +stm32f4xx_hal_flash.c:417:13:HAL_FLASH_OperationErrorCallback 0 static +stm32f4xx_hal_flash.c:277:6:HAL_FLASH_IRQHandler 16 static +stm32f4xx_hal_flash.c:449:19:HAL_FLASH_Unlock 0 static +stm32f4xx_hal_flash.c:473:19:HAL_FLASH_Lock 0 static +stm32f4xx_hal_flash.c:485:19:HAL_FLASH_OB_Unlock 0 static +stm32f4xx_hal_flash.c:505:19:HAL_FLASH_OB_Lock 0 static +stm32f4xx_hal_flash.c:554:10:HAL_FLASH_GetError 0 static +stm32f4xx_hal_flash.c:568:19:FLASH_WaitForLastOperation 24 static +stm32f4xx_hal_flash.c:172:19:HAL_FLASH_Program 24 static +stm32f4xx_hal_flash.c:517:19:HAL_FLASH_OB_Launch 0 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su new file mode 100644 index 0000000..5011c05 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su @@ -0,0 +1,8 @@ +stm32f4xx_hal_gpio.c:187:6:HAL_GPIO_Init 56 static +stm32f4xx_hal_gpio.c:312:6:HAL_GPIO_DeInit 36 static +stm32f4xx_hal_gpio.c:393:15:HAL_GPIO_ReadPin 0 static +stm32f4xx_hal_gpio.c:428:6:HAL_GPIO_WritePin 0 static +stm32f4xx_hal_gpio.c:451:6:HAL_GPIO_TogglePin 0 static +stm32f4xx_hal_gpio.c:470:19:HAL_GPIO_LockPin 8 static +stm32f4xx_hal_gpio.c:518:13:HAL_GPIO_EXTI_Callback 0 static +stm32f4xx_hal_gpio.c:503:6:HAL_GPIO_EXTI_IRQHandler 8 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su new file mode 100644 index 0000000..b2bac0d --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su @@ -0,0 +1,57 @@ +stm32f4xx_hal_i2c.c:5462:26:I2C_IsAcknowledgeFailed 0 static +stm32f4xx_hal_i2c.c:5264:26:I2C_WaitOnMasterAddressFlagUntilTimeout 32 static +stm32f4xx_hal_i2c.c:5230:26:I2C_WaitOnFlagUntilTimeout 32 static +stm32f4xx_hal_i2c.c:5312:26:I2C_WaitOnTXEFlagUntilTimeout 16 static +stm32f4xx_hal_i2c.c:4873:26:I2C_RequestMemoryWrite 40 static +stm32f4xx_hal_i2c.c:4963:26:I2C_RequestMemoryRead 40 static +stm32f4xx_hal_i2c.c:5420:26:I2C_WaitOnRXNEFlagUntilTimeout 16 static +stm32f4xx_hal_i2c.c:5349:26:I2C_WaitOnBTFFlagUntilTimeout 16 static +stm32f4xx_hal_i2c.c:472:14:HAL_I2C_MspInit 0 static +stm32f4xx_hal_i2c.c:354:19:HAL_I2C_Init 16 static +stm32f4xx_hal_i2c.c:487:14:HAL_I2C_MspDeInit 0 static +stm32f4xx_hal_i2c.c:436:19:HAL_I2C_DeInit 8 static +stm32f4xx_hal_i2c.c:575:19:HAL_I2C_Master_Transmit 40 static +stm32f4xx_hal_i2c.c:707:19:HAL_I2C_Master_Receive 64 static +stm32f4xx_hal_i2c.c:938:19:HAL_I2C_Slave_Transmit 40 static +stm32f4xx_hal_i2c.c:1067:19:HAL_I2C_Slave_Receive 40 static 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40 static +stm32f4xx_hal_i2c.c:2536:19:HAL_I2C_Mem_Read 56 static +stm32f4xx_hal_i2c.c:2769:19:HAL_I2C_Mem_Write_IT 32 static +stm32f4xx_hal_i2c.c:2854:19:HAL_I2C_Mem_Read_IT 32 static +stm32f4xx_hal_i2c.c:2944:19:HAL_I2C_Mem_Write_DMA 56 static +stm32f4xx_hal_i2c.c:3066:19:HAL_I2C_Mem_Read_DMA 56 static +stm32f4xx_hal_i2c.c:3228:19:HAL_I2C_IsDeviceReady 56 static +stm32f4xx_hal_i2c.c:3531:13:HAL_I2C_MasterTxCpltCallback 0 static +stm32f4xx_hal_i2c.c:3547:13:HAL_I2C_MasterRxCpltCallback 0 static +stm32f4xx_hal_i2c.c:3562:13:HAL_I2C_SlaveTxCpltCallback 0 static +stm32f4xx_hal_i2c.c:3578:13:HAL_I2C_SlaveRxCpltCallback 0 static +stm32f4xx_hal_i2c.c:3596:13:HAL_I2C_AddrCallback 0 static +stm32f4xx_hal_i2c.c:3614:13:HAL_I2C_ListenCpltCallback 0 static +stm32f4xx_hal_i2c.c:3630:13:HAL_I2C_MemTxCpltCallback 0 static +stm32f4xx_hal_i2c.c:3646:13:HAL_I2C_MemRxCpltCallback 0 static +stm32f4xx_hal_i2c.c:3662:13:HAL_I2C_ErrorCallback 0 static +stm32f4xx_hal_i2c.c:5154:13:I2C_DMAError 8 static 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b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.su @@ -0,0 +1,28 @@ +stm32f4xx_hal_i2s.c:1501:26:I2S_WaitFlagStateUntilTimeout.constprop 24 static +stm32f4xx_hal_i2s.c:440:14:HAL_I2S_MspInit 0 static +stm32f4xx_hal_i2s.c:455:14:HAL_I2S_MspDeInit 0 static +stm32f4xx_hal_i2s.c:412:19:HAL_I2S_DeInit 8 static +stm32f4xx_hal_i2s.c:728:19:HAL_I2S_Transmit_IT 0 static +stm32f4xx_hal_i2s.c:795:19:HAL_I2S_Receive_IT 0 static +stm32f4xx_hal_i2s.c:860:19:HAL_I2S_Transmit_DMA 16 static +stm32f4xx_hal_i2s.c:943:19:HAL_I2S_Receive_DMA 24 static +stm32f4xx_hal_i2s.c:1025:19:HAL_I2S_DMAPause 0 static +stm32f4xx_hal_i2s.c:1061:19:HAL_I2S_DMAResume 0 static +stm32f4xx_hal_i2s.c:1111:19:HAL_I2S_DMAStop 16 static +stm32f4xx_hal_i2s.c:1165:6:HAL_I2S_IRQHandler 0 static +stm32f4xx_hal_i2s.c:1177:14:HAL_I2S_TxHalfCpltCallback 0 static +stm32f4xx_hal_i2s.c:1323:13:I2S_DMATxHalfCplt 8 static +stm32f4xx_hal_i2s.c:1192:14:HAL_I2S_TxCpltCallback 0 static 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b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.su @@ -0,0 +1,10 @@ +stm32f4xx_hal_i2s_ex.c:1003:13:I2SEx_TxRxDMAError 0 static +stm32f4xx_hal_i2s_ex.c:1122:26:I2SEx_FullDuplexWaitFlagStateUntilTimeout.constprop 32 static +stm32f4xx_hal_i2s_ex.c:215:19:HAL_I2SEx_TransmitReceive 56 static +stm32f4xx_hal_i2s_ex.c:625:19:HAL_I2SEx_TransmitReceive_DMA 32 static +stm32f4xx_hal_i2s_ex.c:887:13:HAL_I2SEx_TxRxHalfCpltCallback 0 static +stm32f4xx_hal_i2s_ex.c:930:13:I2SEx_TxRxDMAHalfCplt 8 static +stm32f4xx_hal_i2s_ex.c:902:13:HAL_I2SEx_TxRxCpltCallback 0 static +stm32f4xx_hal_i2s_ex.c:469:19:HAL_I2SEx_TransmitReceive_IT 16 static +stm32f4xx_hal_i2s_ex.c:943:13:I2SEx_TxRxDMACplt 16 static +stm32f4xx_hal_i2s_ex.c:762:6:HAL_I2SEx_FullDuplex_IRQHandler 24 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su new file mode 100644 index 0000000..00595a3 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su @@ -0,0 +1,32 @@ +stm32f4xx_hal_pcd.c:248:13:HAL_PCD_MspInit 0 static +stm32f4xx_hal_pcd.c:137:19:HAL_PCD_Init 64 static +stm32f4xx_hal_pcd.c:262:13:HAL_PCD_MspDeInit 0 static +stm32f4xx_hal_pcd.c:295:19:HAL_PCD_Start 8 static +stm32f4xx_hal_pcd.c:309:19:HAL_PCD_Stop 8 static +stm32f4xx_hal_pcd.c:222:19:HAL_PCD_DeInit 8 static +stm32f4xx_hal_pcd.c:722:14:HAL_PCD_DataOutStageCallback 0 static +stm32f4xx_hal_pcd.c:738:14:HAL_PCD_DataInStageCallback 0 static +stm32f4xx_hal_pcd.c:752:14:HAL_PCD_SetupStageCallback 0 static +stm32f4xx_hal_pcd.c:766:14:HAL_PCD_SOFCallback 0 static +stm32f4xx_hal_pcd.c:780:14:HAL_PCD_ResetCallback 0 static +stm32f4xx_hal_pcd.c:794:14:HAL_PCD_SuspendCallback 0 static +stm32f4xx_hal_pcd.c:808:14:HAL_PCD_ResumeCallback 0 static +stm32f4xx_hal_pcd.c:823:14:HAL_PCD_ISOOUTIncompleteCallback 0 static +stm32f4xx_hal_pcd.c:839:14:HAL_PCD_ISOINIncompleteCallback 0 static +stm32f4xx_hal_pcd.c:854:14:HAL_PCD_ConnectCallback 0 static +stm32f4xx_hal_pcd.c:868:14:HAL_PCD_DisconnectCallback 0 static +stm32f4xx_hal_pcd.c:324:6:HAL_PCD_IRQHandler 64 static +stm32f4xx_hal_pcd.c:901:19:HAL_PCD_DevConnect 8 static +stm32f4xx_hal_pcd.c:914:19:HAL_PCD_DevDisconnect 8 static +stm32f4xx_hal_pcd.c:928:19:HAL_PCD_SetAddress 8 static +stm32f4xx_hal_pcd.c:943:19:HAL_PCD_EP_Open 16 static +stm32f4xx_hal_pcd.c:985:19:HAL_PCD_EP_Close 8 static +stm32f4xx_hal_pcd.c:1016:19:HAL_PCD_EP_Receive 16 static +stm32f4xx_hal_pcd.c:1052:10:HAL_PCD_EP_GetRxCount 0 static +stm32f4xx_hal_pcd.c:1064:19:HAL_PCD_EP_Transmit 16 static +stm32f4xx_hal_pcd.c:1100:19:HAL_PCD_EP_SetStall 16 static +stm32f4xx_hal_pcd.c:1135:19:HAL_PCD_EP_ClrStall 16 static +stm32f4xx_hal_pcd.c:1165:19:HAL_PCD_EP_Flush 8 static +stm32f4xx_hal_pcd.c:1188:19:HAL_PCD_ActivateRemoteWakeup 0 static +stm32f4xx_hal_pcd.c:1205:19:HAL_PCD_DeActivateRemoteWakeup 0 static +stm32f4xx_hal_pcd.c:1237:18:HAL_PCD_GetState 0 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su new file mode 100644 index 0000000..bc2e1f4 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su @@ -0,0 +1,2 @@ +stm32f4xx_hal_pcd_ex.c:89:19:HAL_PCDEx_SetTxFiFo 16 static +stm32f4xx_hal_pcd_ex.c:131:19:HAL_PCDEx_SetRxFiFo 0 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su new file mode 100644 index 0000000..2d53f8a --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su @@ -0,0 +1,17 @@ +stm32f4xx_hal_pwr.c:108:6:HAL_PWR_DeInit 0 static +stm32f4xx_hal_pwr.c:121:6:HAL_PWR_EnableBkUpAccess 0 static +stm32f4xx_hal_pwr.c:133:6:HAL_PWR_DisableBkUpAccess 0 static +stm32f4xx_hal_pwr.c:268:6:HAL_PWR_ConfigPVD 0 static +stm32f4xx_hal_pwr.c:311:6:HAL_PWR_EnablePVD 0 static +stm32f4xx_hal_pwr.c:320:6:HAL_PWR_DisablePVD 0 static +stm32f4xx_hal_pwr.c:334:6:HAL_PWR_EnableWakeUpPin 0 static +stm32f4xx_hal_pwr.c:352:6:HAL_PWR_DisableWakeUpPin 0 static +stm32f4xx_hal_pwr.c:381:6:HAL_PWR_EnterSLEEPMode 0 static +stm32f4xx_hal_pwr.c:424:6:HAL_PWR_EnterSTOPMode 0 static +stm32f4xx_hal_pwr.c:463:6:HAL_PWR_EnterSTANDBYMode 0 static +stm32f4xx_hal_pwr.c:501:13:HAL_PWR_PVDCallback 0 static +stm32f4xx_hal_pwr.c:484:6:HAL_PWR_PVD_IRQHandler 8 static +stm32f4xx_hal_pwr.c:516:6:HAL_PWR_EnableSleepOnExit 0 static +stm32f4xx_hal_pwr.c:528:6:HAL_PWR_DisableSleepOnExit 0 static +stm32f4xx_hal_pwr.c:540:6:HAL_PWR_EnableSEVOnPend 0 static +stm32f4xx_hal_pwr.c:552:6:HAL_PWR_DisableSEVOnPend 0 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su new file mode 100644 index 0000000..9ace054 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su @@ -0,0 +1,6 @@ +stm32f4xx_hal_pwr_ex.c:159:19:HAL_PWREx_EnableBkUpReg 16 static +stm32f4xx_hal_pwr_ex.c:183:19:HAL_PWREx_DisableBkUpReg 16 static +stm32f4xx_hal_pwr_ex.c:207:6:HAL_PWREx_EnableFlashPowerDown 0 static +stm32f4xx_hal_pwr_ex.c:216:6:HAL_PWREx_DisableFlashPowerDown 0 static +stm32f4xx_hal_pwr_ex.c:229:10:HAL_PWREx_GetVoltageRange 0 static +stm32f4xx_hal_pwr_ex.c:250:19:HAL_PWREx_ControlVoltageScaling 24 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su new file mode 100644 index 0000000..6262a7a --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su @@ -0,0 +1,6 @@ +stm32f4xx_hal_rcc_ex.c:2519:19:HAL_RCCEx_PeriphCLKConfig 32 static +stm32f4xx_hal_rcc_ex.c:2647:6:HAL_RCCEx_GetPeriphCLKConfig 0 static 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static +stm32f4xx_hal_spi.c:2649:13:SPI_2linesRxISR_16BIT 4 static +stm32f4xx_hal_spi.c:2420:13:SPI_DMAError 8 static +stm32f4xx_hal_spi.c:2206:13:SPI_DMATransmitCplt 24 static +stm32f4xx_hal_spi.c:2250:13:SPI_DMAReceiveCplt 8 static +stm32f4xx_hal_spi.c:2317:13:SPI_DMATransmitReceiveCplt 16 static +stm32f4xx_hal_spi.c:1931:6:HAL_SPI_IRQHandler 32 static +stm32f4xx_hal_spi.c:2438:13:SPI_DMAAbortOnError 8 static +stm32f4xx_hal_spi.c:2134:13:HAL_SPI_AbortCpltCallback 0 static +stm32f4xx_hal_spi.c:1714:19:HAL_SPI_Abort_IT 24 static +stm32f4xx_hal_spi.c:2510:13:SPI_DMARxAbortCallback 16 static +stm32f4xx_hal_spi.c:2455:13:SPI_DMATxAbortCallback 16 static +stm32f4xx_hal_spi.c:2169:22:HAL_SPI_GetState 0 static +stm32f4xx_hal_spi.c:2181:10:HAL_SPI_GetError 0 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su new file mode 100644 index 0000000..dc25ec4 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su @@ -0,0 +1,37 @@ +stm32f4xx_hal_tim_ex.c:1853:13:TIM_CCxNChannelCmd 8 static +stm32f4xx_hal_tim_ex.c:258:13:HAL_TIMEx_HallSensor_MspInit 0 static +stm32f4xx_hal_tim_ex.c:157:19:HAL_TIMEx_HallSensor_Init 48 static +stm32f4xx_hal_tim_ex.c:273:13:HAL_TIMEx_HallSensor_MspDeInit 0 static +stm32f4xx_hal_tim_ex.c:230:19:HAL_TIMEx_HallSensor_DeInit 8 static +stm32f4xx_hal_tim_ex.c:288:19:HAL_TIMEx_HallSensor_Start 8 static +stm32f4xx_hal_tim_ex.c:310:19:HAL_TIMEx_HallSensor_Stop 8 static +stm32f4xx_hal_tim_ex.c:332:19:HAL_TIMEx_HallSensor_Start_IT 8 static +stm32f4xx_hal_tim_ex.c:357:19:HAL_TIMEx_HallSensor_Stop_IT 8 static +stm32f4xx_hal_tim_ex.c:384:19:HAL_TIMEx_HallSensor_Start_DMA 16 static +stm32f4xx_hal_tim_ex.c:432:19:HAL_TIMEx_HallSensor_Stop_DMA 8 static +stm32f4xx_hal_tim_ex.c:900:19:HAL_TIMEx_PWMN_Start 8 static +stm32f4xx_hal_tim_ex.c:487:19:HAL_TIMEx_OCN_Start 0 static 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static +stm32f4xx_ll_usb.c:149:19:USB_EnableGlobalInt 0 static +stm32f4xx_ll_usb.c:162:19:USB_DisableGlobalInt 0 static +stm32f4xx_ll_usb.c:178:19:USB_SetCurrentMode 8 static +stm32f4xx_ll_usb.c:203:19:USB_DevInit 24 static +stm32f4xx_ll_usb.c:349:19:USB_FlushTxFifo 0 static +stm32f4xx_ll_usb.c:373:19:USB_FlushRxFifo 0 static +stm32f4xx_ll_usb.c:403:19:USB_SetDevSpeed 0 static +stm32f4xx_ll_usb.c:418:9:USB_GetDevSpeed 0 static +stm32f4xx_ll_usb.c:445:19:USB_ActivateEndpoint 12 static +stm32f4xx_ll_usb.c:475:19:USB_ActivateDedicatedEndpoint 20 static +stm32f4xx_ll_usb.c:518:19:USB_DeactivateEndpoint 0 static +stm32f4xx_ll_usb.c:589:19:USB_DeactivateDedicatedEndpoint 16 static +stm32f4xx_ll_usb.c:665:19:USB_EPStartXfer 32 static +stm32f4xx_ll_usb.c:787:19:USB_EP0StartXfer 16 static +stm32f4xx_ll_usb.c:877:19:USB_WritePacket 8 static +stm32f4xx_ll_usb.c:905:7:USB_ReadPacket 0 static +stm32f4xx_ll_usb.c:924:19:USB_EPSetStall 0 static +stm32f4xx_ll_usb.c:952:19:USB_EPClearStall 0 static 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static +stm32f4xx_ll_usb.c:1396:10:USB_GetHostSpeed 8 static +stm32f4xx_ll_usb.c:1409:10:USB_GetCurrentFrame 0 static +stm32f4xx_ll_usb.c:1438:19:USB_HC_Init 20 static +stm32f4xx_ll_usb.c:1543:19:USB_HC_StartXfer 48 static +stm32f4xx_ll_usb.c:1654:10:USB_HC_ReadInterrupt 16 static +stm32f4xx_ll_usb.c:1666:19:USB_HC_Halt 24 static +stm32f4xx_ll_usb.c:1727:19:USB_DoPing 24 static +stm32f4xx_ll_usb.c:1749:19:USB_StopHost 32 static diff --git a/F4-Gyro-RTOS/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.su b/F4-Gyro-RTOS/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.su new file mode 100644 index 0000000..ee7e821 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.su @@ -0,0 +1,15 @@ +usbd_cdc.c:664:17:USBD_CDC_DataIn 0 static +usbd_cdc.c:718:17:USBD_CDC_EP0_RxReady 8 static +usbd_cdc.c:740:18:USBD_CDC_GetFSCfgDesc 0 static +usbd_cdc.c:753:18:USBD_CDC_GetHSCfgDesc 0 static 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b/F4-Gyro-RTOS/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su new file mode 100644 index 0000000..c0258dc --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su @@ -0,0 +1,7 @@ +usbd_ioreq.c:95:21:USBD_CtlSendData 8 static +usbd_ioreq.c:117:21:USBD_CtlContinueSendData 8 static +usbd_ioreq.c:135:21:USBD_CtlPrepareRx 8 static +usbd_ioreq.c:160:21:USBD_CtlContinueRx 8 static +usbd_ioreq.c:177:21:USBD_CtlSendStatus 8 static +usbd_ioreq.c:195:21:USBD_CtlReceiveStatus 8 static +usbd_ioreq.c:217:11:USBD_GetRxCount 8 static diff --git a/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su new file mode 100644 index 0000000..a2cdeeb --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su @@ -0,0 +1,53 @@ +cmsis_os.c:193:10:osKernelStart 8 static +cmsis_os.c:208:9:osKernelRunning 8 static +cmsis_os.c:227:10:osKernelSysTick 0 static +cmsis_os.c:245:12:osThreadCreate 32 static +cmsis_os.c:283:12:osThreadGetId 0 static +cmsis_os.c:298:10:osThreadTerminate 8 static +cmsis_os.c:313:10:osThreadYield 0 static +cmsis_os.c:327:10:osThreadSetPriority 8 static +cmsis_os.c:343:12:osThreadGetPriority 8 static +cmsis_os.c:365:10:osDelay 8 static +cmsis_os.c:400:11:osTimerCreate 0 static +cmsis_os.c:447:10:osTimerStart 0 static +cmsis_os.c:486:10:osTimerStop 0 static +cmsis_os.c:515:10:osTimerDelete 0 static +cmsis_os.c:545:9:osSignalSet 24 static +cmsis_os.c:586:9:osSignalWait 32 static +cmsis_os.c:640:11:osMutexCreate 0 static +cmsis_os.c:669:10:osMutexWait 16 static +cmsis_os.c:755:15:osSemaphoreCreate 8 static +cmsis_os.c:822:9:osSemaphoreWait 16 static +cmsis_os.c:862:10:osSemaphoreRelease 16 static +cmsis_os.c:709:10:osMutexRelease 0 static +cmsis_os.c:926:10:osPoolCreate 24 static +cmsis_os.c:979:7:osPoolAlloc 16 static +cmsis_os.c:1023:7:osPoolCAlloc 8 static +cmsis_os.c:1042:10:osPoolFree 0 static +cmsis_os.c:1086:14:osMessageCreate 0 static +cmsis_os.c:1113:10:osMessagePut 24 static +cmsis_os.c:1145:9:osMessageGet 40 static +cmsis_os.c:1214:11:osMailCreate 32 static +cmsis_os.c:1260:7:osMailAlloc 0 static +cmsis_os.c:1282:7:osMailCAlloc 16 static +cmsis_os.c:1303:10:osMailPut 24 static +cmsis_os.c:1336:9:osMailGet 40 static +cmsis_os.c:1392:10:osMailFree 0 static +cmsis_os.c:1408:6:osSystickHandler 8 static +cmsis_os.c:1478:10:osThreadSuspend 8 static +cmsis_os.c:1494:10:osThreadResume 8 static +cmsis_os.c:1518:10:osThreadSuspendAll 8 static +cmsis_os.c:1529:10:osThreadResumeAll 8 static +cmsis_os.c:1546:10:osDelayUntil 0 static +cmsis_os.c:1566:10:osAbortDelay 0 static +cmsis_os.c:1587:10:osThreadList 0 static +cmsis_os.c:1601:9:osMessagePeek 32 static +cmsis_os.c:1642:10:osMessageWaiting 0 static +cmsis_os.c:1658:10:osMessageAvailableSpace 0 static +cmsis_os.c:1668:10:osMessageDelete 8 static +cmsis_os.c:889:10:osSemaphoreDelete 0 static +cmsis_os.c:733:10:osMutexDelete 0 static +cmsis_os.c:1684:11:osRecursiveMutexCreate 0 static +cmsis_os.c:1710:10:osRecursiveMutexRelease 0 static +cmsis_os.c:1731:10:osRecursiveMutexWait 0 static +cmsis_os.c:1770:10:osSemaphoreGetCount 0 static diff --git a/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su new file mode 100644 index 0000000..e69de29 diff --git a/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su new file mode 100644 index 0000000..83ea901 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su @@ -0,0 +1,9 @@ +event_groups.c:174:21:xEventGroupCreate 8 static +event_groups.c:324:13:xEventGroupWaitBits 32 static +event_groups.c:472:13:xEventGroupClearBits 16 static +event_groups.c:514:13:xEventGroupGetBitsFromISR 0 static +event_groups.c:530:13:xEventGroupSetBits 24 static +event_groups.c:208:13:xEventGroupSync 24 static +event_groups.c:624:6:vEventGroupDelete 16 static +event_groups.c:668:6:vEventGroupSetBitsCallback 0 static +event_groups.c:676:6:vEventGroupClearBitsCallback 0 static diff --git a/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su new file mode 100644 index 0000000..f197ed0 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su @@ -0,0 +1,5 @@ +list.c:79:6:vListInitialise 0 static +list.c:104:6:vListInitialiseItem 0 static +list.c:116:6:vListInsertEnd 0 static +list.c:145:6:vListInsert 12 static +list.c:212:13:uxListRemove 0 static diff --git a/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.su b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.su new file mode 100644 index 0000000..bf682e3 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.su @@ -0,0 +1,13 @@ +port.c:259:13:prvTaskExitError 0 static +port.c:292:13:prvPortStartFirstTask 0 static +port.c:689:13:vPortEnableVFP 0 static +port.c:229:14:pxPortInitialiseStack 0 static +port.c:273:6:SVC_Handler 0 static +port.c:399:6:vPortEndScheduler 0 static +port.c:407:6:vPortEnterCritical 0 static +port.c:424:6:vPortExitCritical 0 static +port.c:435:6:PendSV_Handler 0 static +port.c:493:6:xPortSysTickHandler 8 static +port.c:671:30:vPortSetupTimerInterrupt 0 static +port.c:312:12:xPortStartScheduler 16 static +port.c:705:7:vPortValidateInterruptPriority 0 static diff --git a/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su new file mode 100644 index 0000000..852c3dc --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su @@ -0,0 +1,21 @@ +queue.c:1697:19:prvCopyDataToQueue 16 static +queue.c:1776:13:prvCopyDataFromQueue 4 static +queue.c:1794:13:prvUnlockQueue 16 static +queue.c:279:12:xQueueGenericReset 16 static +queue.c:386:16:xQueueGenericCreate 16 static +queue.c:723:12:xQueueGenericSend 48 static +queue.c:506:16:xQueueCreateMutex 8 static +queue.c:921:12:xQueueGenericSendFromISR 32 static +queue.c:1072:12:xQueueGiveFromISR 16 static +queue.c:1237:12:xQueueGenericReceive 48 static +queue.c:1434:12:xQueueReceiveFromISR 32 static +queue.c:1525:12:xQueuePeekFromISR 24 static +queue.c:1579:13:uxQueueMessagesWaiting 8 static +queue.c:1595:13:uxQueueSpacesAvailable 16 static +queue.c:1613:13:uxQueueMessagesWaitingFromISR 0 static +queue.c:1935:12:xQueueIsQueueEmptyFromISR 0 static +queue.c:1974:12:xQueueIsQueueFullFromISR 0 static +queue.c:2269:7:vQueueAddToRegistry 12 static +queue.c:2298:14:pcQueueGetName 0 static +queue.c:2326:7:vQueueUnregisterQueue 8 static +queue.c:1625:6:vQueueDelete 8 static diff --git a/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su new file mode 100644 index 0000000..62ce6c9 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su @@ -0,0 +1,43 @@ +tasks.c:3635:13:prvResetNextTaskUnblockTime 0 static +tasks.c:4692:13:prvAddCurrentTaskToDelayedList 24 static +tasks.c:3007:6:vTaskSetTimeOutState.part.5 0 static +tasks.c:1656:20:prvTaskIsTaskSuspended 8 static +tasks.c:676:13:xTaskCreate 40 static +tasks.c:1048:7:vTaskDelete 16 static +tasks.c:1340:14:uxTaskPriorityGet 8 static +tasks.c:1362:14:uxTaskPriorityGetFromISR 8 static +tasks.c:1402:7:vTaskPrioritySet 24 static +tasks.c:1702:7:vTaskResume 16 static +tasks.c:1756:13:xTaskResumeFromISR 24 static +tasks.c:1826:6:vTaskStartScheduler 16 static +tasks.c:1933:6:vTaskEndScheduler 0 static +tasks.c:1944:6:vTaskSuspendAll 0 static +tasks.c:2127:12:xTaskGetTickCount 0 static +tasks.c:2142:12:xTaskGetTickCountFromISR 8 static +tasks.c:2173:13:uxTaskGetNumberOfTasks 0 static +tasks.c:2181:7:pcTaskGetName 0 static +tasks.c:2499:12:xTaskIncrementTick 40 static +tasks.c:2017:12:xTaskResumeAll 32 static +tasks.c:1224:7:vTaskDelay 8 static +tasks.c:3131:8:prvIdleTask 8 static +tasks.c:2761:6:vTaskSwitchContext 8 static +tasks.c:1566:7:vTaskSuspend 16 static +tasks.c:2820:6:vTaskPlaceOnEventList 8 static +tasks.c:2837:6:vTaskPlaceOnUnorderedEventList 8 static +tasks.c:2894:12:xTaskRemoveFromEventList 16 static +tasks.c:2962:12:xTaskRemoveFromUnorderedEventList 16 static +tasks.c:3007:6:vTaskSetTimeOutState 8 static +tasks.c:3015:12:xTaskCheckForTimeOut 16 static +tasks.c:3076:6:vTaskMissedYield 0 static +tasks.c:3661:15:xTaskGetCurrentTaskHandle 0 static +tasks.c:3678:13:xTaskGetSchedulerState 0 static +tasks.c:3706:7:vTaskPriorityInherit 24 static +tasks.c:3772:13:xTaskPriorityDisinherit 24 static +tasks.c:4162:12:uxTaskResetEventItemValue 0 static +tasks.c:4178:8:pvTaskIncrementMutexHeldCount 0 static +tasks.c:4195:11:ulTaskNotifyTake 16 static +tasks.c:4263:13:xTaskNotifyWait 24 static +tasks.c:4343:13:xTaskGenericNotify 24 static +tasks.c:4449:13:xTaskGenericNotifyFromISR 32 static +tasks.c:4573:7:vTaskNotifyGiveFromISR 24 static +tasks.c:4662:13:xTaskNotifyStateClear 8 static diff --git a/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su new file mode 100644 index 0000000..e69de29 diff --git a/F4-Gyro-RTOS/Debug/Src/freertos.su b/F4-Gyro-RTOS/Debug/Src/freertos.su new file mode 100644 index 0000000..e69de29 diff --git a/F4-Gyro-RTOS/Debug/Src/main.su b/F4-Gyro-RTOS/Debug/Src/main.su new file mode 100644 index 0000000..d78abc5 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Src/main.su @@ -0,0 +1,8 @@ +main.c:191:6:SystemClock_Config 112 static +main.c:108:5:main 88 static +main.c:408:6:GYRO_Task 32 static +main.c:523:6:StartTask02 8 static +main.c:485:6:USB_Task 192 static +main.c:505:6:StartTask01 8 static +main.c:546:6:HAL_TIM_PeriodElapsedCallback 0 static +main.c:566:6:_Error_Handler 0 static diff --git a/F4-Gyro-RTOS/Debug/Src/stm32f4xx_hal_msp.su b/F4-Gyro-RTOS/Debug/Src/stm32f4xx_hal_msp.su new file mode 100644 index 0000000..48c5ec8 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Src/stm32f4xx_hal_msp.su @@ -0,0 +1,7 @@ +stm32f4xx_hal_msp.c:59:6:HAL_MspInit 16 static +stm32f4xx_hal_msp.c:91:6:HAL_I2C_MspInit 32 static +stm32f4xx_hal_msp.c:121:6:HAL_I2C_MspDeInit 0 static +stm32f4xx_hal_msp.c:145:6:HAL_I2S_MspInit 40 static +stm32f4xx_hal_msp.c:184:6:HAL_I2S_MspDeInit 8 static +stm32f4xx_hal_msp.c:212:6:HAL_SPI_MspInit 32 static +stm32f4xx_hal_msp.c:243:6:HAL_SPI_MspDeInit 0 static diff --git a/F4-Gyro-RTOS/Debug/Src/stm32f4xx_hal_timebase_TIM.su b/F4-Gyro-RTOS/Debug/Src/stm32f4xx_hal_timebase_TIM.su new file mode 100644 index 0000000..c310097 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Src/stm32f4xx_hal_timebase_TIM.su @@ -0,0 +1,3 @@ +stm32f4xx_hal_timebase_TIM.c:78:19:HAL_InitTick 48 static +stm32f4xx_hal_timebase_TIM.c:132:6:HAL_SuspendTick 0 static +stm32f4xx_hal_timebase_TIM.c:144:6:HAL_ResumeTick 0 static diff --git a/F4-Gyro-RTOS/Debug/Src/stm32f4xx_it.su b/F4-Gyro-RTOS/Debug/Src/stm32f4xx_it.su new file mode 100644 index 0000000..5e1d8df --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Src/stm32f4xx_it.su @@ -0,0 +1,3 @@ +stm32f4xx_it.c:55:6:SysTick_Handler 0 static +stm32f4xx_it.c:76:6:TIM6_DAC_IRQHandler 0 static +stm32f4xx_it.c:90:6:OTG_FS_IRQHandler 0 static diff --git a/F4-Gyro-RTOS/Debug/Src/system_stm32f4xx.su b/F4-Gyro-RTOS/Debug/Src/system_stm32f4xx.su new file mode 100644 index 0000000..0757a3e --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Src/system_stm32f4xx.su @@ -0,0 +1,2 @@ +system_stm32f4xx.c:166:6:SystemInit 0 static +system_stm32f4xx.c:239:6:SystemCoreClockUpdate 8 static diff --git a/F4-Gyro-RTOS/Debug/Src/usb_device.su b/F4-Gyro-RTOS/Debug/Src/usb_device.su new file mode 100644 index 0000000..f10dfa5 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Src/usb_device.su @@ -0,0 +1 @@ +usb_device.c:93:6:MX_USB_DEVICE_Init 8 static diff --git a/F4-Gyro-RTOS/Debug/Src/usbd_cdc_if.su b/F4-Gyro-RTOS/Debug/Src/usbd_cdc_if.su new file mode 100644 index 0000000..40f27d5 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Src/usbd_cdc_if.su @@ -0,0 +1,5 @@ +usbd_cdc_if.c:197:15:CDC_DeInit_FS 0 static +usbd_cdc_if.c:211:15:CDC_Control_FS 0 static +usbd_cdc_if.c:291:15:CDC_Receive_FS 8 static +usbd_cdc_if.c:183:15:CDC_Init_FS 8 static +usbd_cdc_if.c:311:9:CDC_Transmit_FS 8 static diff --git a/F4-Gyro-RTOS/Debug/Src/usbd_desc.su b/F4-Gyro-RTOS/Debug/Src/usbd_desc.su new file mode 100644 index 0000000..9c401b3 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Src/usbd_desc.su @@ -0,0 +1,7 @@ +usbd_desc.c:273:11:USBD_FS_DeviceDescriptor 0 static +usbd_desc.c:285:11:USBD_FS_LangIDStrDescriptor 0 static +usbd_desc.c:316:11:USBD_FS_ManufacturerStrDescriptor 8 static +usbd_desc.c:297:11:USBD_FS_ProductStrDescriptor 8 static +usbd_desc.c:328:11:USBD_FS_SerialStrDescriptor 8 static +usbd_desc.c:347:11:USBD_FS_ConfigStrDescriptor 8 static +usbd_desc.c:366:11:USBD_FS_InterfaceStrDescriptor 8 static diff --git a/F4-Gyro-RTOS/F4-Gyro-RTOS.elf.launch b/F4-Gyro-RTOS/F4-Gyro-RTOS.elf.launch new file mode 100644 index 0000000..279f38f --- /dev/null +++ b/F4-Gyro-RTOS/F4-Gyro-RTOS.elf.launch @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c b/F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c new file mode 100644 index 0000000..d5feca9 --- /dev/null +++ b/F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c @@ -0,0 +1,763 @@ +/* + FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM CM4F port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __VFP_FP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + /* The way the SysTick is clocked is not modified in case it is not the same + as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 +r0p1 port. */ +#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXEC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* For strict compliance with the Cortex-M spec the task start address should +have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have +occurred while the SysTick counter is stopped during tickless idle +calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* Let the user override the pre-loading of the initial LR with the address of +prvTaskExitError() in case it messes up unwinding of the stack in the +debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* Each task maintains its own interrupt status in the critical nesting +variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__ (( naked )); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ) __attribute__ (( naked )); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvPortStartFirstTask( void ) __attribute__ (( naked )); + +/* + * Function to enable the VFP. + */ +static void vPortEnableVFP( void ) __attribute__ (( naked )); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* + * The number of SysTick increments that make up one tick period. + */ +#if configUSE_TICKLESS_IDLE == 1 + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if configUSE_TICKLESS_IDLE == 1 + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if configUSE_TICKLESS_IDLE == 1 + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXEC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + __asm volatile ( + " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */ + " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " msr psp, r0 \n" /* Restore the task stack pointer. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); +} +/*-----------------------------------------------------------*/ + +static void prvPortStartFirstTask( void ) +{ + __asm volatile( + " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc 0 \n" /* System call to start first task. */ + " nop \n" + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* This port can be used on all revisions of the Cortex-M7 core other than + the r0p1 parts. r0p1 parts should use the port from the + /source/portable/GCC/ARM_CM7/r0p1 directory. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + + #if( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + functions can be called. ISR safe functions are those that end in + "FromISR". FreeRTOS maintains separate thread and ISR API functions to + ensure interrupt entry is as fast and simple as possible. + + Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + /* Shift the priority group value back to its position within the AIRCR + register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* conifgASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; + portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + exit error function to prevent compiler warnings about a static function + not being called in the case that the application writer overrides this + functionality by defining configTASK_RETURN_ADDRESS. */ + prvTaskExitError(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " mrs r0, psp \n" + " isb \n" + " \n" + " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" + " \n" + " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */ + " \n" + " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */ + " \n" + " stmdb sp!, {r3} \n" + " mov r0, %0 \n" + " msr basepri, r0 \n" + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " ldmia sp!, {r3} \n" + " \n" + " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " ldr r0, [r1] \n" + " \n" + " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */ + " \n" + " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" + " \n" + " msr psp, r0 \n" + " isb \n" + " \n" + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */ + #if WORKAROUND_PMU_CM001 == 1 + " push { r14 } \n" + " pop { pc } \n" + #endif + #endif + " \n" + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + executes all interrupts must be unmasked. There is therefore no need to + save and then restore the interrupt mask value as its value is already + known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + is accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + tick periods. -1 is used because this code will execute part way + through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + method as that will mask interrupts that should exit sleep mode. */ + __asm volatile( "cpsid i" ); + __asm volatile( "dsb" ); + __asm volatile( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + above. */ + __asm volatile( "cpsie i" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + set its parameter to 0 to indicate that its implementation contains + its own wait for interrupt or wait for event instruction, and so wfi + should not be executed again. However, the original expected idle + time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( &xModifiableIdleTime ); + if( xModifiableIdleTime > 0 ) + { + __asm volatile( "dsb" ); + __asm volatile( "wfi" ); + __asm volatile( "isb" ); + } + configPOST_SLEEP_PROCESSING( &xExpectedIdleTime ); + + /* Stop SysTick. Again, the time the SysTick is stopped for is + accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG; + portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT ); + + /* Re-enable interrupts - see comments above the cpsid instruction() + above. */ + __asm volatile( "cpsie i" ); + + if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt has already executed, and the SysTick + count reloaded with ulReloadValue. Reset the + portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + underflowed because the post sleep hook did something + that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* The tick interrupt handler will already have pended the tick + processing in the kernel. As the pending tick will be + processed as soon as this function exits, the tick value + maintained by the tick is stepped forward by one less than the + time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + Work out how long the sleep lasted rounded to complete tick + periods (not the ulReload value which accounted for part + ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + value. The critical section is used to ensure the tick interrupt + can only execute once in the case that the reload register is near + zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portENTER_CRITICAL(); + { + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + portEXIT_CRITICAL(); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if configUSE_TICKLESS_IDLE == 1 + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP( void ) +{ + __asm volatile + ( + " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */ + " ldr r1, [r0] \n" + " \n" + " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ + " str r1, [r0] \n" + " bx r14 " + ); +} +/*-----------------------------------------------------------*/ + +#if( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + an interrupt that has been assigned a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + function. ISR safe FreeRTOS API functions must *only* be called + from interrupts that have been assigned a priority at or below + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Numerically low interrupt priority numbers represent logically high + interrupt priorities, therefore the priority of the interrupt must + be set to a value equal to or numerically *higher* than + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Interrupts that use the FreeRTOS API must not be left at their + default priority of zero as that is the highest possible priority, + which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + and therefore also guaranteed to be invalid. + + FreeRTOS maintains separate thread and ISR API functions to ensure + interrupt entry is as fast and simple as possible. + + The following links provide detailed information: + http://www.freertos.org/RTOS-Cortex-M3-M4.html + http://www.freertos.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + that define each interrupt's priority to be split between bits that + define the interrupt's pre-emption priority bits and bits that define + the interrupt's sub-priority. For simplicity all bits must be defined + to be pre-emption priority bits. The following assertion will fail if + this is not the case (if some bits represent a sub-priority). + + If the application only uses CMSIS libraries for interrupt + configuration then the correct setting can be achieved on all Cortex-M + devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + scheduler. Note however that some vendor specific peripheral libraries + assume a non-zero priority group setting, in which cases using a value + of zero will result in unpredicable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ + + diff --git a/F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h b/F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h new file mode 100644 index 0000000..d44fc92 --- /dev/null +++ b/F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h @@ -0,0 +1,284 @@ +/* + FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +#define portYIELD() \ +{ \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + within the specified behaviour for the architecture. */ \ + __asm volatile( "dsb" ); \ + __asm volatile( "isb" ); \ +} + +#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD() +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI(0) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not necessary for to use this port. They are defined so the common demo files +(which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + return ucReturn; + } + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__(( always_inline)) +#endif + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ +uint32_t ulCurrentInterrupt; +BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ +uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n" \ + " msr basepri, %0 \n" \ + " isb \n" \ + " dsb \n" \ + :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ +uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n" \ + " mov %1, %2 \n" \ + " msr basepri, %1 \n" \ + " isb \n" \ + " dsb \n" \ + :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + + /* This return will not be reached but is necessary to prevent compiler + warnings. */ + return ulOriginalBASEPRI; +} +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + ( + " msr basepri, %0 " :: "r" ( ulNewMaskValue ) + ); +} +/*-----------------------------------------------------------*/ + + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/F4-Gyro-RTOS/STM32F407VG_FLASH.ld b/F4-Gyro-RTOS/STM32F407VG_FLASH.ld new file mode 100644 index 0000000..2799d12 --- /dev/null +++ b/F4-Gyro-RTOS/STM32F407VG_FLASH.ld @@ -0,0 +1,188 @@ +/* +***************************************************************************** +** + +** File : stm32_flash.ld +** +** Abstract : Linker script for STM32F407VG Device with +** 1024KByte FLASH, 128KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Environment : Atollic TrueSTUDIO(R) +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Atollic AB. +** You may use this file as-is or modify it according to the needs of your +** project. This file may only be built (assembled or compiled and linked) +** using the Atollic TrueSTUDIO(R) product. The use of this file together +** with other tools than Atollic TrueSTUDIO(R) is not permitted. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + _siccmram = LOADADDR(.ccmram); + + /* CCM-RAM section + * + * IMPORTANT NOTE! + * If initialized variables will be placed in this section, + * the startup code needs to be modified to copy the init-values. + */ + .ccmram : + { + . = ALIGN(4); + _sccmram = .; /* create a global symbol at ccmram start */ + *(.ccmram) + *(.ccmram*) + + . = ALIGN(4); + _eccmram = .; /* create a global symbol at ccmram end */ + } >CCMRAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/F4-Gyro-RTOS/startup/startup_stm32f407xx.s b/F4-Gyro-RTOS/startup/startup_stm32f407xx.s new file mode 100644 index 0000000..aeeeb22 --- /dev/null +++ b/F4-Gyro-RTOS/startup/startup_stm32f407xx.s @@ -0,0 +1,521 @@ +/** + ****************************************************************************** + * @file startup_stm32f407xx.s + * @author MCD Application Team + * @brief STM32F407xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ From 14e2683d84251fc125e4e6b844bc0dcb8ea0d5e6 Mon Sep 17 00:00:00 2001 From: Tuyen Date: Mon, 13 Aug 2018 16:49:36 +0700 Subject: [PATCH 2/2] Add TrueSTUDIO project --- F4-Gyro-RTOS/.cproject | 18 +- F4-Gyro-RTOS/.cproject.bak | 318 + F4-Gyro-RTOS/.mxproject | 11 +- F4-Gyro-RTOS/.project.bak | 76 + F4-Gyro-RTOS/.settings/language.settings.xml | 2 +- .../org.eclipse.cdt.codan.core.prefs | 71 + .../Debug/Drivers/BSP/Components/.gitignore | 16 + .../stm32f4_discovery_accelerometer.su | 6 + .../Src/stm32f4xx_hal_dma.su | 13 + .../Src/stm32f4xx_hal_dma_ex.su | 3 + .../Src/stm32f4xx_hal_flash_ex.su | 7 + .../Src/stm32f4xx_hal_flash_ramfunc.su | 0 .../Src/stm32f4xx_hal_rcc.su | 14 + .../Src/stm32f4xx_hal_tim.su | 99 + F4-Gyro-RTOS/Debug/F4-Gyro-RTOS.hex | 1793 ++ F4-Gyro-RTOS/Debug/F4-Gyro-RTOS.list | 17931 ++++++++++++++++ F4-Gyro-RTOS/Debug/F4-Gyro-RTOS.map | 4568 ++++ .../Core/Src/usbd_ctlreq.su | 7 + .../FreeRTOS/Source/portable/.gitignore | 2 + F4-Gyro-RTOS/Debug/Src/main.su | 14 +- F4-Gyro-RTOS/Debug/Src/usbd_cdc_if.su | 10 +- F4-Gyro-RTOS/Debug/Src/usbd_conf.su | 28 + .../stm32f4_discovery_audio.c | 1140 - .../stm32f4_discovery_audio.h | 274 - F4-Gyro-RTOS/F4-Gyro-RTOS.elf.launch | 2 +- F4-Gyro-RTOS/F4-Gyro-RTOS.ioc | 6 +- .../Class/CDC/Inc/usbd_cdc.h | 2 +- .../Source/portable/RVDS/ARM_CM4F/port.c | 791 - .../Source/portable/RVDS/ARM_CM4F/portmacro.h | 294 - F4-Gyro-RTOS/Src/main.c | 52 +- 30 files changed, 25017 insertions(+), 2551 deletions(-) create mode 100644 F4-Gyro-RTOS/.cproject.bak create mode 100644 F4-Gyro-RTOS/.project.bak create mode 100644 F4-Gyro-RTOS/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 F4-Gyro-RTOS/Debug/Drivers/BSP/Components/.gitignore create mode 100644 F4-Gyro-RTOS/Debug/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_accelerometer.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su create mode 100644 F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su create mode 100644 F4-Gyro-RTOS/Debug/F4-Gyro-RTOS.hex create mode 100644 F4-Gyro-RTOS/Debug/F4-Gyro-RTOS.list create mode 100644 F4-Gyro-RTOS/Debug/F4-Gyro-RTOS.map create mode 100644 F4-Gyro-RTOS/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su create mode 100644 F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/.gitignore create mode 100644 F4-Gyro-RTOS/Debug/Src/usbd_conf.su delete mode 100644 F4-Gyro-RTOS/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_audio.c delete mode 100644 F4-Gyro-RTOS/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_audio.h delete mode 100644 F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c delete mode 100644 F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h diff --git a/F4-Gyro-RTOS/.cproject b/F4-Gyro-RTOS/.cproject index ab000d3..a2899af 100644 --- a/F4-Gyro-RTOS/.cproject +++ b/F4-Gyro-RTOS/.cproject @@ -15,9 +15,9 @@ - @@ -143,9 +143,9 @@ - @@ -261,8 +261,8 @@ - + diff --git a/F4-Gyro-RTOS/.cproject.bak b/F4-Gyro-RTOS/.cproject.bak new file mode 100644 index 0000000..ab000d3 --- /dev/null +++ b/F4-Gyro-RTOS/.cproject.bak @@ -0,0 +1,318 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/F4-Gyro-RTOS/.mxproject b/F4-Gyro-RTOS/.mxproject index fe3d22c..350615e 100644 --- a/F4-Gyro-RTOS/.mxproject +++ b/F4-Gyro-RTOS/.mxproject @@ -1,13 +1,18 @@ [PreviousGenFiles] -HeaderPath=C:/Users/VuSon/Desktop/STM32F0_Workshop 2016/STM32F0 DK Exercises/FreeRTOS-STM32F4-Tutorial/F4-Gyro-RTOS/Inc +HeaderPath=C:/Users/Administrator/Desktop/node_red/FreeRTOS-STM32F4-Tutorial/F4-Gyro-RTOS/Inc HeaderFiles=FreeRTOSConfig.h;usb_device.h;usbd_conf.h;usbd_desc.h;usbd_cdc_if.h;stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; -SourcePath=C:/Users/VuSon/Desktop/STM32F0_Workshop 2016/STM32F0 DK Exercises/FreeRTOS-STM32F4-Tutorial/F4-Gyro-RTOS/Src +SourcePath=C:/Users/Administrator/Desktop/node_red/FreeRTOS-STM32F4-Tutorial/F4-Gyro-RTOS/Src SourceFiles=freertos.c;usb_device.c;usbd_conf.c;usbd_desc.c;usbd_cdc_if.c;stm32f4xx_it.c;stm32f4xx_hal_msp.c;stm32f4xx_hal_timebase_TIM.c;main.c; [PreviousLibFiles] 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/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; 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[PreviousUsedKeilFiles] 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HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F;..\Middlewares\ST\STM32_USB_Device_Library\Core\Inc;..\Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Inc;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Middlewares\Third_Party\FreeRTOS\Source\include;..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS;..\Drivers\CMSIS\Include;..\Inc; +[PreviousUsedTStudioFiles] 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+HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F;..\Middlewares\ST\STM32_USB_Device_Library\Core\Inc;..\Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Inc;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Middlewares\Third_Party\FreeRTOS\Source\include;..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS;..\Drivers\CMSIS\Include;..\Inc; +CDefines=__weak:__attribute__((weak));__packed:__attribute__((__packed__)); + diff --git a/F4-Gyro-RTOS/.project.bak b/F4-Gyro-RTOS/.project.bak new file mode 100644 index 0000000..faa95fe --- /dev/null +++ b/F4-Gyro-RTOS/.project.bak @@ -0,0 +1,76 @@ + + + F4-Gyro-RTOS + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?children? + ?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\|| + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/STM32100B-EVAL/Debug} + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + + diff --git a/F4-Gyro-RTOS/.settings/language.settings.xml b/F4-Gyro-RTOS/.settings/language.settings.xml index eec129f..2f1410c 100644 --- a/F4-Gyro-RTOS/.settings/language.settings.xml +++ b/F4-Gyro-RTOS/.settings/language.settings.xml @@ -4,7 +4,7 @@ - + diff --git a/F4-Gyro-RTOS/.settings/org.eclipse.cdt.codan.core.prefs b/F4-Gyro-RTOS/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..b5248c6 --- /dev/null +++ b/F4-Gyro-RTOS/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,71 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue=Error +org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"} +org.eclipse.cdt.codan.checkers.nocommentinside=-Error +org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"} +org.eclipse.cdt.codan.checkers.nolinecomment=-Error +org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"} +org.eclipse.cdt.codan.checkers.noreturn=Error +org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"} +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous 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b/F4-Gyro-RTOS/Debug/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_accelerometer.su @@ -0,0 +1,6 @@ +stm32f4_discovery_accelerometer.c:98:9:BSP_ACCELERO_Init 16 static +stm32f4_discovery_accelerometer.c:181:9:BSP_ACCELERO_ReadID 0 static +stm32f4_discovery_accelerometer.c:195:6:BSP_ACCELERO_Reset 0 static +stm32f4_discovery_accelerometer.c:206:6:BSP_ACCELERO_Click_ITConfig 0 static +stm32f4_discovery_accelerometer.c:217:6:BSP_ACCELERO_Click_ITClear 0 static +stm32f4_discovery_accelerometer.c:230:6:BSP_ACCELERO_GetXYZ 16 static diff --git a/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su new file mode 100644 index 0000000..e61ef79 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su @@ -0,0 +1,13 @@ +stm32f4xx_hal_dma.c:1193:17:DMA_CalcBaseAndBitshift 0 static +stm32f4xx_hal_dma.c:187:19:HAL_DMA_Init 16 static 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a/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su new file mode 100644 index 0000000..e69de29 diff --git a/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su new file mode 100644 index 0000000..b3d4b63 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su @@ -0,0 +1,14 @@ +stm32f4xx_hal_rcc.c:218:26:HAL_RCC_DeInit 0 static +stm32f4xx_hal_rcc.c:237:26:HAL_RCC_OscConfig 32 static +stm32f4xx_hal_rcc.c:765:6:HAL_RCC_MCOConfig 48 static +stm32f4xx_hal_rcc.c:831:6:HAL_RCC_EnableCSS 0 static +stm32f4xx_hal_rcc.c:840:6:HAL_RCC_DisableCSS 0 static +stm32f4xx_hal_rcc.c:875:17:HAL_RCC_GetSysClockFreq 8 static +stm32f4xx_hal_rcc.c:581:19:HAL_RCC_ClockConfig 24 static +stm32f4xx_hal_rcc.c:931:10:HAL_RCC_GetHCLKFreq 0 static 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+:106F50000000000000000000000000000000000031 +:106F60000000000000000000000000000000000021 +:106F70000000000000000000000000000000000011 +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000000F1 +:046FA00000000000ED +:04000005080061F995 +:00000001FF diff --git a/F4-Gyro-RTOS/Debug/F4-Gyro-RTOS.list b/F4-Gyro-RTOS/Debug/F4-Gyro-RTOS.list new file mode 100644 index 0000000..fcf220f --- /dev/null +++ b/F4-Gyro-RTOS/Debug/F4-Gyro-RTOS.list @@ -0,0 +1,17931 @@ + +F4-Gyro-RTOS.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 00000188 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 000069c4 08000190 08000190 00010190 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 000001fc 08006b54 08006b54 00016b54 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM 00000008 08006d50 08006d50 00016d50 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .init_array 00000004 08006d58 08006d58 00016d58 2**2 + CONTENTS, ALLOC, LOAD, DATA + 5 .fini_array 00000004 08006d5c 08006d5c 00016d5c 2**2 + CONTENTS, ALLOC, LOAD, DATA + 6 .data 00000244 20000000 08006d60 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .ccmram 00000000 10000000 10000000 00020244 2**0 + CONTENTS + 8 .bss 000047b0 20000244 20000244 00020244 2**2 + ALLOC + 9 ._user_heap_stack 00000600 200049f4 200049f4 00020244 2**0 + ALLOC + 10 .ARM.attributes 00000030 00000000 00000000 00020244 2**0 + CONTENTS, READONLY + 11 .debug_info 000364eb 00000000 00000000 00020274 2**0 + CONTENTS, READONLY, DEBUGGING + 12 .debug_abbrev 00006b3e 00000000 00000000 0005675f 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_loc 000123cf 00000000 00000000 0005d29d 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_aranges 000017f0 00000000 00000000 0006f670 2**3 + CONTENTS, READONLY, DEBUGGING + 15 .debug_ranges 00001f38 00000000 00000000 00070e60 2**3 + CONTENTS, READONLY, DEBUGGING + 16 .debug_line 0000e8f8 00000000 00000000 00072d98 2**0 + CONTENTS, READONLY, DEBUGGING + 17 .debug_str 00008768 00000000 00000000 00081690 2**0 + CONTENTS, READONLY, DEBUGGING + 18 .comment 0000007c 00000000 00000000 00089df8 2**0 + CONTENTS, READONLY + 19 .debug_frame 00004a28 00000000 00000000 00089e74 2**2 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +08000190 <__do_global_dtors_aux>: + 8000190: b510 push {r4, lr} + 8000192: 4c05 ldr r4, [pc, #20] ; (80001a8 <__do_global_dtors_aux+0x18>) + 8000194: 7823 ldrb r3, [r4, #0] + 8000196: b933 cbnz r3, 80001a6 <__do_global_dtors_aux+0x16> + 8000198: 4b04 ldr r3, [pc, #16] ; (80001ac <__do_global_dtors_aux+0x1c>) + 800019a: b113 cbz r3, 80001a2 <__do_global_dtors_aux+0x12> + 800019c: 4804 ldr r0, [pc, #16] ; (80001b0 <__do_global_dtors_aux+0x20>) + 800019e: f3af 8000 nop.w + 80001a2: 2301 movs r3, #1 + 80001a4: 7023 strb r3, [r4, #0] + 80001a6: bd10 pop {r4, pc} + 80001a8: 20000244 .word 0x20000244 + 80001ac: 00000000 .word 0x00000000 + 80001b0: 08006b3c .word 0x08006b3c + +080001b4 : + 80001b4: b508 push {r3, lr} + 80001b6: 4b03 ldr r3, [pc, #12] ; (80001c4 ) + 80001b8: b11b cbz r3, 80001c2 + 80001ba: 4903 ldr r1, [pc, #12] ; (80001c8 ) + 80001bc: 4803 ldr r0, [pc, #12] ; (80001cc ) + 80001be: f3af 8000 nop.w + 80001c2: bd08 pop {r3, pc} + 80001c4: 00000000 .word 0x00000000 + 80001c8: 20000248 .word 0x20000248 + 80001cc: 08006b3c .word 0x08006b3c + +080001d0 : + 80001d0: 4603 mov r3, r0 + 80001d2: f813 2b01 ldrb.w r2, [r3], #1 + 80001d6: 2a00 cmp r2, #0 + 80001d8: d1fb bne.n 80001d2 + 80001da: 1a18 subs r0, r3, r0 + 80001dc: 3801 subs r0, #1 + 80001de: 4770 bx lr + +080001e0 : + 80001e0: f001 01ff and.w r1, r1, #255 ; 0xff + 80001e4: 2a10 cmp r2, #16 + 80001e6: db2b blt.n 8000240 + 80001e8: f010 0f07 tst.w r0, #7 + 80001ec: d008 beq.n 8000200 + 80001ee: f810 3b01 ldrb.w r3, [r0], #1 + 80001f2: 3a01 subs r2, #1 + 80001f4: 428b cmp r3, r1 + 80001f6: d02d beq.n 8000254 + 80001f8: f010 0f07 tst.w r0, #7 + 80001fc: b342 cbz r2, 8000250 + 80001fe: d1f6 bne.n 80001ee + 8000200: b4f0 push {r4, r5, r6, r7} + 8000202: ea41 2101 orr.w r1, r1, r1, lsl #8 + 8000206: ea41 4101 orr.w r1, r1, r1, lsl #16 + 800020a: f022 0407 bic.w r4, r2, #7 + 800020e: f07f 0700 mvns.w r7, #0 + 8000212: 2300 movs r3, #0 + 8000214: e8f0 5602 ldrd r5, r6, [r0], #8 + 8000218: 3c08 subs r4, #8 + 800021a: ea85 0501 eor.w r5, r5, r1 + 800021e: ea86 0601 eor.w r6, r6, r1 + 8000222: fa85 f547 uadd8 r5, r5, r7 + 8000226: faa3 f587 sel r5, r3, r7 + 800022a: fa86 f647 uadd8 r6, r6, r7 + 800022e: faa5 f687 sel r6, r5, r7 + 8000232: b98e cbnz r6, 8000258 + 8000234: d1ee bne.n 8000214 + 8000236: bcf0 pop {r4, r5, r6, r7} + 8000238: f001 01ff and.w r1, r1, #255 ; 0xff + 800023c: f002 0207 and.w r2, r2, #7 + 8000240: b132 cbz r2, 8000250 + 8000242: f810 3b01 ldrb.w r3, [r0], #1 + 8000246: 3a01 subs r2, #1 + 8000248: ea83 0301 eor.w r3, r3, r1 + 800024c: b113 cbz r3, 8000254 + 800024e: d1f8 bne.n 8000242 + 8000250: 2000 movs r0, #0 + 8000252: 4770 bx lr + 8000254: 3801 subs r0, #1 + 8000256: 4770 bx lr + 8000258: 2d00 cmp r5, #0 + 800025a: bf06 itte eq + 800025c: 4635 moveq r5, r6 + 800025e: 3803 subeq r0, #3 + 8000260: 3807 subne r0, #7 + 8000262: f015 0f01 tst.w r5, #1 + 8000266: d107 bne.n 8000278 + 8000268: 3001 adds r0, #1 + 800026a: f415 7f80 tst.w r5, #256 ; 0x100 + 800026e: bf02 ittt eq + 8000270: 3001 addeq r0, #1 + 8000272: f415 3fc0 tsteq.w r5, #98304 ; 0x18000 + 8000276: 3001 addeq r0, #1 + 8000278: bcf0 pop {r4, r5, r6, r7} + 800027a: 3801 subs r0, #1 + 800027c: 4770 bx lr + 800027e: bf00 nop + +08000280 <__aeabi_uldivmod>: + 8000280: b953 cbnz r3, 8000298 <__aeabi_uldivmod+0x18> + 8000282: b94a cbnz r2, 8000298 <__aeabi_uldivmod+0x18> + 8000284: 2900 cmp r1, #0 + 8000286: bf08 it eq + 8000288: 2800 cmpeq r0, #0 + 800028a: bf1c itt ne + 800028c: f04f 31ff movne.w r1, #4294967295 + 8000290: f04f 30ff movne.w r0, #4294967295 + 8000294: f000 b97a b.w 800058c <__aeabi_idiv0> + 8000298: f1ad 0c08 sub.w ip, sp, #8 + 800029c: e96d ce04 strd ip, lr, [sp, #-16]! + 80002a0: f000 f806 bl 80002b0 <__udivmoddi4> + 80002a4: f8dd e004 ldr.w lr, [sp, #4] + 80002a8: e9dd 2302 ldrd r2, r3, [sp, #8] + 80002ac: b004 add sp, #16 + 80002ae: 4770 bx lr + +080002b0 <__udivmoddi4>: + 80002b0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80002b4: 468c mov ip, r1 + 80002b6: 460d mov r5, r1 + 80002b8: 4604 mov r4, r0 + 80002ba: 9e08 ldr r6, [sp, #32] + 80002bc: 2b00 cmp r3, #0 + 80002be: d151 bne.n 8000364 <__udivmoddi4+0xb4> + 80002c0: 428a cmp r2, r1 + 80002c2: 4617 mov r7, r2 + 80002c4: d96d bls.n 80003a2 <__udivmoddi4+0xf2> + 80002c6: fab2 fe82 clz lr, r2 + 80002ca: f1be 0f00 cmp.w lr, #0 + 80002ce: d00b beq.n 80002e8 <__udivmoddi4+0x38> + 80002d0: f1ce 0c20 rsb ip, lr, #32 + 80002d4: fa01 f50e lsl.w r5, r1, lr + 80002d8: fa20 fc0c lsr.w ip, r0, ip + 80002dc: fa02 f70e lsl.w r7, r2, lr + 80002e0: ea4c 0c05 orr.w ip, ip, r5 + 80002e4: fa00 f40e lsl.w r4, r0, lr + 80002e8: ea4f 4a17 mov.w sl, r7, lsr #16 + 80002ec: 0c25 lsrs r5, r4, #16 + 80002ee: fbbc f8fa udiv r8, ip, sl + 80002f2: fa1f f987 uxth.w r9, r7 + 80002f6: fb0a cc18 mls ip, sl, r8, ip + 80002fa: ea45 450c orr.w r5, r5, ip, lsl #16 + 80002fe: fb08 f309 mul.w r3, r8, r9 + 8000302: 42ab cmp r3, r5 + 8000304: d90a bls.n 800031c <__udivmoddi4+0x6c> + 8000306: 19ed adds r5, r5, r7 + 8000308: f108 32ff add.w r2, r8, #4294967295 + 800030c: f080 8123 bcs.w 8000556 <__udivmoddi4+0x2a6> + 8000310: 42ab cmp r3, r5 + 8000312: f240 8120 bls.w 8000556 <__udivmoddi4+0x2a6> + 8000316: f1a8 0802 sub.w r8, r8, #2 + 800031a: 443d add r5, r7 + 800031c: 1aed subs r5, r5, r3 + 800031e: b2a4 uxth r4, r4 + 8000320: fbb5 f0fa udiv r0, r5, sl + 8000324: fb0a 5510 mls r5, sl, r0, r5 + 8000328: ea44 4405 orr.w r4, r4, r5, lsl #16 + 800032c: fb00 f909 mul.w r9, r0, r9 + 8000330: 45a1 cmp r9, r4 + 8000332: d909 bls.n 8000348 <__udivmoddi4+0x98> + 8000334: 19e4 adds r4, r4, r7 + 8000336: f100 33ff add.w r3, r0, #4294967295 + 800033a: f080 810a bcs.w 8000552 <__udivmoddi4+0x2a2> + 800033e: 45a1 cmp r9, r4 + 8000340: f240 8107 bls.w 8000552 <__udivmoddi4+0x2a2> + 8000344: 3802 subs r0, #2 + 8000346: 443c add r4, r7 + 8000348: eba4 0409 sub.w r4, r4, r9 + 800034c: ea40 4008 orr.w r0, r0, r8, lsl #16 + 8000350: 2100 movs r1, #0 + 8000352: 2e00 cmp r6, #0 + 8000354: d061 beq.n 800041a <__udivmoddi4+0x16a> + 8000356: fa24 f40e lsr.w r4, r4, lr + 800035a: 2300 movs r3, #0 + 800035c: 6034 str r4, [r6, #0] + 800035e: 6073 str r3, [r6, #4] + 8000360: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000364: 428b cmp r3, r1 + 8000366: d907 bls.n 8000378 <__udivmoddi4+0xc8> + 8000368: 2e00 cmp r6, #0 + 800036a: d054 beq.n 8000416 <__udivmoddi4+0x166> + 800036c: 2100 movs r1, #0 + 800036e: e886 0021 stmia.w r6, {r0, r5} + 8000372: 4608 mov r0, r1 + 8000374: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000378: fab3 f183 clz r1, r3 + 800037c: 2900 cmp r1, #0 + 800037e: f040 808e bne.w 800049e <__udivmoddi4+0x1ee> + 8000382: 42ab cmp r3, r5 + 8000384: d302 bcc.n 800038c <__udivmoddi4+0xdc> + 8000386: 4282 cmp r2, r0 + 8000388: f200 80fa bhi.w 8000580 <__udivmoddi4+0x2d0> + 800038c: 1a84 subs r4, r0, r2 + 800038e: eb65 0503 sbc.w r5, r5, r3 + 8000392: 2001 movs r0, #1 + 8000394: 46ac mov ip, r5 + 8000396: 2e00 cmp r6, #0 + 8000398: d03f beq.n 800041a <__udivmoddi4+0x16a> + 800039a: e886 1010 stmia.w r6, {r4, ip} + 800039e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 80003a2: b912 cbnz r2, 80003aa <__udivmoddi4+0xfa> + 80003a4: 2701 movs r7, #1 + 80003a6: fbb7 f7f2 udiv r7, r7, r2 + 80003aa: fab7 fe87 clz lr, r7 + 80003ae: f1be 0f00 cmp.w lr, #0 + 80003b2: d134 bne.n 800041e <__udivmoddi4+0x16e> + 80003b4: 1beb subs r3, r5, r7 + 80003b6: 0c3a lsrs r2, r7, #16 + 80003b8: fa1f fc87 uxth.w ip, r7 + 80003bc: 2101 movs r1, #1 + 80003be: fbb3 f8f2 udiv r8, r3, r2 + 80003c2: 0c25 lsrs r5, r4, #16 + 80003c4: fb02 3318 mls r3, r2, r8, r3 + 80003c8: ea45 4503 orr.w r5, r5, r3, lsl #16 + 80003cc: fb0c f308 mul.w r3, ip, r8 + 80003d0: 42ab cmp r3, r5 + 80003d2: d907 bls.n 80003e4 <__udivmoddi4+0x134> + 80003d4: 19ed adds r5, r5, r7 + 80003d6: f108 30ff add.w r0, r8, #4294967295 + 80003da: d202 bcs.n 80003e2 <__udivmoddi4+0x132> + 80003dc: 42ab cmp r3, r5 + 80003de: f200 80d1 bhi.w 8000584 <__udivmoddi4+0x2d4> + 80003e2: 4680 mov r8, r0 + 80003e4: 1aed subs r5, r5, r3 + 80003e6: b2a3 uxth r3, r4 + 80003e8: fbb5 f0f2 udiv r0, r5, r2 + 80003ec: fb02 5510 mls r5, r2, r0, r5 + 80003f0: ea43 4405 orr.w r4, r3, r5, lsl #16 + 80003f4: fb0c fc00 mul.w ip, ip, r0 + 80003f8: 45a4 cmp ip, r4 + 80003fa: d907 bls.n 800040c <__udivmoddi4+0x15c> + 80003fc: 19e4 adds r4, r4, r7 + 80003fe: f100 33ff add.w r3, r0, #4294967295 + 8000402: d202 bcs.n 800040a <__udivmoddi4+0x15a> + 8000404: 45a4 cmp ip, r4 + 8000406: f200 80b8 bhi.w 800057a <__udivmoddi4+0x2ca> + 800040a: 4618 mov r0, r3 + 800040c: eba4 040c sub.w r4, r4, ip + 8000410: ea40 4008 orr.w r0, r0, r8, lsl #16 + 8000414: e79d b.n 8000352 <__udivmoddi4+0xa2> + 8000416: 4631 mov r1, r6 + 8000418: 4630 mov r0, r6 + 800041a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800041e: f1ce 0420 rsb r4, lr, #32 + 8000422: fa05 f30e lsl.w r3, r5, lr + 8000426: fa07 f70e lsl.w r7, r7, lr + 800042a: fa20 f804 lsr.w r8, r0, r4 + 800042e: 0c3a lsrs r2, r7, #16 + 8000430: fa25 f404 lsr.w r4, r5, r4 + 8000434: ea48 0803 orr.w r8, r8, r3 + 8000438: fbb4 f1f2 udiv r1, r4, r2 + 800043c: ea4f 4518 mov.w r5, r8, lsr #16 + 8000440: fb02 4411 mls r4, r2, r1, r4 + 8000444: fa1f fc87 uxth.w ip, r7 + 8000448: ea45 4504 orr.w r5, r5, r4, lsl #16 + 800044c: fb01 f30c mul.w r3, r1, ip + 8000450: 42ab cmp r3, r5 + 8000452: fa00 f40e lsl.w r4, r0, lr + 8000456: d909 bls.n 800046c <__udivmoddi4+0x1bc> + 8000458: 19ed adds r5, r5, r7 + 800045a: f101 30ff add.w r0, r1, #4294967295 + 800045e: f080 808a bcs.w 8000576 <__udivmoddi4+0x2c6> + 8000462: 42ab cmp r3, r5 + 8000464: f240 8087 bls.w 8000576 <__udivmoddi4+0x2c6> + 8000468: 3902 subs r1, #2 + 800046a: 443d add r5, r7 + 800046c: 1aeb subs r3, r5, r3 + 800046e: fa1f f588 uxth.w r5, r8 + 8000472: fbb3 f0f2 udiv r0, r3, r2 + 8000476: fb02 3310 mls r3, r2, r0, r3 + 800047a: ea45 4503 orr.w r5, r5, r3, lsl #16 + 800047e: fb00 f30c mul.w r3, r0, ip + 8000482: 42ab cmp r3, r5 + 8000484: d907 bls.n 8000496 <__udivmoddi4+0x1e6> + 8000486: 19ed adds r5, r5, r7 + 8000488: f100 38ff add.w r8, r0, #4294967295 + 800048c: d26f bcs.n 800056e <__udivmoddi4+0x2be> + 800048e: 42ab cmp r3, r5 + 8000490: d96d bls.n 800056e <__udivmoddi4+0x2be> + 8000492: 3802 subs r0, #2 + 8000494: 443d add r5, r7 + 8000496: 1aeb subs r3, r5, r3 + 8000498: ea40 4101 orr.w r1, r0, r1, lsl #16 + 800049c: e78f b.n 80003be <__udivmoddi4+0x10e> + 800049e: f1c1 0720 rsb r7, r1, #32 + 80004a2: fa22 f807 lsr.w r8, r2, r7 + 80004a6: 408b lsls r3, r1 + 80004a8: fa05 f401 lsl.w r4, r5, r1 + 80004ac: ea48 0303 orr.w r3, r8, r3 + 80004b0: fa20 fe07 lsr.w lr, r0, r7 + 80004b4: ea4f 4c13 mov.w ip, r3, lsr #16 + 80004b8: 40fd lsrs r5, r7 + 80004ba: ea4e 0e04 orr.w lr, lr, r4 + 80004be: fbb5 f9fc udiv r9, r5, ip + 80004c2: ea4f 441e mov.w r4, lr, lsr #16 + 80004c6: fb0c 5519 mls r5, ip, r9, r5 + 80004ca: fa1f f883 uxth.w r8, r3 + 80004ce: ea44 4505 orr.w r5, r4, r5, lsl #16 + 80004d2: fb09 f408 mul.w r4, r9, r8 + 80004d6: 42ac cmp r4, r5 + 80004d8: fa02 f201 lsl.w r2, r2, r1 + 80004dc: fa00 fa01 lsl.w sl, r0, r1 + 80004e0: d908 bls.n 80004f4 <__udivmoddi4+0x244> + 80004e2: 18ed adds r5, r5, r3 + 80004e4: f109 30ff add.w r0, r9, #4294967295 + 80004e8: d243 bcs.n 8000572 <__udivmoddi4+0x2c2> + 80004ea: 42ac cmp r4, r5 + 80004ec: d941 bls.n 8000572 <__udivmoddi4+0x2c2> + 80004ee: f1a9 0902 sub.w r9, r9, #2 + 80004f2: 441d add r5, r3 + 80004f4: 1b2d subs r5, r5, r4 + 80004f6: fa1f fe8e uxth.w lr, lr + 80004fa: fbb5 f0fc udiv r0, r5, ip + 80004fe: fb0c 5510 mls r5, ip, r0, r5 + 8000502: ea4e 4405 orr.w r4, lr, r5, lsl #16 + 8000506: fb00 f808 mul.w r8, r0, r8 + 800050a: 45a0 cmp r8, r4 + 800050c: d907 bls.n 800051e <__udivmoddi4+0x26e> + 800050e: 18e4 adds r4, r4, r3 + 8000510: f100 35ff add.w r5, r0, #4294967295 + 8000514: d229 bcs.n 800056a <__udivmoddi4+0x2ba> + 8000516: 45a0 cmp r8, r4 + 8000518: d927 bls.n 800056a <__udivmoddi4+0x2ba> + 800051a: 3802 subs r0, #2 + 800051c: 441c add r4, r3 + 800051e: ea40 4009 orr.w r0, r0, r9, lsl #16 + 8000522: eba4 0408 sub.w r4, r4, r8 + 8000526: fba0 8902 umull r8, r9, r0, r2 + 800052a: 454c cmp r4, r9 + 800052c: 46c6 mov lr, r8 + 800052e: 464d mov r5, r9 + 8000530: d315 bcc.n 800055e <__udivmoddi4+0x2ae> + 8000532: d012 beq.n 800055a <__udivmoddi4+0x2aa> + 8000534: b156 cbz r6, 800054c <__udivmoddi4+0x29c> + 8000536: ebba 030e subs.w r3, sl, lr + 800053a: eb64 0405 sbc.w r4, r4, r5 + 800053e: fa04 f707 lsl.w r7, r4, r7 + 8000542: 40cb lsrs r3, r1 + 8000544: 431f orrs r7, r3 + 8000546: 40cc lsrs r4, r1 + 8000548: 6037 str r7, [r6, #0] + 800054a: 6074 str r4, [r6, #4] + 800054c: 2100 movs r1, #0 + 800054e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000552: 4618 mov r0, r3 + 8000554: e6f8 b.n 8000348 <__udivmoddi4+0x98> + 8000556: 4690 mov r8, r2 + 8000558: e6e0 b.n 800031c <__udivmoddi4+0x6c> + 800055a: 45c2 cmp sl, r8 + 800055c: d2ea bcs.n 8000534 <__udivmoddi4+0x284> + 800055e: ebb8 0e02 subs.w lr, r8, r2 + 8000562: eb69 0503 sbc.w r5, r9, r3 + 8000566: 3801 subs r0, #1 + 8000568: e7e4 b.n 8000534 <__udivmoddi4+0x284> + 800056a: 4628 mov r0, r5 + 800056c: e7d7 b.n 800051e <__udivmoddi4+0x26e> + 800056e: 4640 mov r0, r8 + 8000570: e791 b.n 8000496 <__udivmoddi4+0x1e6> + 8000572: 4681 mov r9, r0 + 8000574: e7be b.n 80004f4 <__udivmoddi4+0x244> + 8000576: 4601 mov r1, r0 + 8000578: e778 b.n 800046c <__udivmoddi4+0x1bc> + 800057a: 3802 subs r0, #2 + 800057c: 443c add r4, r7 + 800057e: e745 b.n 800040c <__udivmoddi4+0x15c> + 8000580: 4608 mov r0, r1 + 8000582: e708 b.n 8000396 <__udivmoddi4+0xe6> + 8000584: f1a8 0802 sub.w r8, r8, #2 + 8000588: 443d add r5, r7 + 800058a: e72b b.n 80003e4 <__udivmoddi4+0x134> + +0800058c <__aeabi_idiv0>: + 800058c: 4770 bx lr + 800058e: bf00 nop + +08000590 : + * @brief LIS302DL De-Initialization. + * @param None + * @retval None. + */ +void LIS302DL_DeInit(void) +{ + 8000590: 4770 bx lr + +08000592 : +{ + 8000592: b513 push {r0, r1, r4, lr} + uint8_t ctrl = 0x00; + 8000594: 2300 movs r3, #0 +{ + 8000596: 4604 mov r4, r0 + uint8_t ctrl = 0x00; + 8000598: f88d 3007 strb.w r3, [sp, #7] + ACCELERO_IO_Init(); + 800059c: f000 fa9a bl 8000ad4 + ctrl = (uint8_t) InitStruct; + 80005a0: a802 add r0, sp, #8 + ACCELERO_IO_Write(&ctrl, LIS302DL_CTRL_REG1_ADDR, 1); + 80005a2: 2201 movs r2, #1 + ctrl = (uint8_t) InitStruct; + 80005a4: f800 4d01 strb.w r4, [r0, #-1]! + ACCELERO_IO_Write(&ctrl, LIS302DL_CTRL_REG1_ADDR, 1); + 80005a8: 2120 movs r1, #32 + 80005aa: f000 fae1 bl 8000b70 +} + 80005ae: b002 add sp, #8 + 80005b0: bd10 pop {r4, pc} + +080005b2 : + * @brief Read LIS302DL device ID. + * @param None + * @retval The Device ID (two bytes). + */ +uint8_t LIS302DL_ReadID(void) +{ + 80005b2: b513 push {r0, r1, r4, lr} + uint8_t tmp = 0; + 80005b4: ac02 add r4, sp, #8 + 80005b6: 2300 movs r3, #0 + 80005b8: f804 3d01 strb.w r3, [r4, #-1]! + + /* Configure the low level interface */ + ACCELERO_IO_Init(); + 80005bc: f000 fa8a bl 8000ad4 + + /* Read WHO_AM_I register */ + ACCELERO_IO_Read(&tmp, LIS302DL_WHO_AM_I_ADDR, 1); + 80005c0: 4620 mov r0, r4 + 80005c2: 2201 movs r2, #1 + 80005c4: 210f movs r1, #15 + 80005c6: f000 faf5 bl 8000bb4 + + /* Return the ID */ + return (uint16_t)tmp; +} + 80005ca: f89d 0007 ldrb.w r0, [sp, #7] + 80005ce: b002 add sp, #8 + 80005d0: bd10 pop {r4, pc} + +080005d2 : + * @brief Set LIS302DL Internal High Pass Filter configuration. + * @param FilterStruct: contains data for filter config + * @retval None + */ +void LIS302DL_FilterConfig(uint8_t FilterStruct) +{ + 80005d2: b537 push {r0, r1, r2, r4, r5, lr} + uint8_t ctrl = 0x00; + 80005d4: ac02 add r4, sp, #8 + 80005d6: 2300 movs r3, #0 + 80005d8: f804 3d01 strb.w r3, [r4, #-1]! +{ + 80005dc: 4605 mov r5, r0 + + /* Read CTRL_REG2 register */ + ACCELERO_IO_Read(&ctrl, LIS302DL_CTRL_REG2_ADDR, 1); + 80005de: 2201 movs r2, #1 + 80005e0: 4620 mov r0, r4 + 80005e2: 2121 movs r1, #33 ; 0x21 + 80005e4: f000 fae6 bl 8000bb4 + + /* Clear high pass filter cut-off level, interrupt and data selection bits */ + ctrl &= (uint8_t)~(LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER | \ + 80005e8: f89d 3007 ldrb.w r3, [sp, #7] + 80005ec: f023 032f bic.w r3, r3, #47 ; 0x2f + LIS302DL_HIGHPASSFILTER_LEVEL_3 | \ + LIS302DL_HIGHPASSFILTERINTERRUPT_1_2); + + ctrl |= FilterStruct; + 80005f0: 431d orrs r5, r3 + + /* Write value to MEMS CTRL_REG2 register */ + ACCELERO_IO_Write(&ctrl, LIS302DL_CTRL_REG2_ADDR, 1); + 80005f2: 2201 movs r2, #1 + 80005f4: 2121 movs r1, #33 ; 0x21 + 80005f6: 4620 mov r0, r4 + ctrl |= FilterStruct; + 80005f8: f88d 5007 strb.w r5, [sp, #7] + ACCELERO_IO_Write(&ctrl, LIS302DL_CTRL_REG2_ADDR, 1); + 80005fc: f000 fab8 bl 8000b70 +} + 8000600: b003 add sp, #12 + 8000602: bd30 pop {r4, r5, pc} + +08000604 : + * @brief Clear LIS302DL click Interrupt + * @param None + * @retval None + */ +void LIS302DL_Click_IntClear(void) +{ + 8000604: b51f push {r0, r1, r2, r3, r4, lr} + uint8_t buffer[6], clickreg = 0; + 8000606: a804 add r0, sp, #16 + 8000608: 2300 movs r3, #0 + 800060a: f800 3d09 strb.w r3, [r0, #-9]! + + /* Read click and status registers if the available MEMS Accelerometer is LIS302DL */ + ACCELERO_IO_Read(&clickreg, LIS302DL_CLICK_SRC_REG_ADDR, 1); + 800060e: 2201 movs r2, #1 + 8000610: 2139 movs r1, #57 ; 0x39 + 8000612: f000 facf bl 8000bb4 + ACCELERO_IO_Read(buffer, LIS302DL_STATUS_REG_ADDR, 6); + 8000616: 2206 movs r2, #6 + 8000618: 2127 movs r1, #39 ; 0x27 + 800061a: a802 add r0, sp, #8 + 800061c: f000 faca bl 8000bb4 +} + 8000620: b005 add sp, #20 + 8000622: f85d fb04 ldr.w pc, [sp], #4 + +08000626 : + * @brief Reboot memory content of LIS302DL. + * @param None + * @retval None + */ +void LIS302DL_RebootCmd(void) +{ + 8000626: b507 push {r0, r1, r2, lr} + uint8_t tmpreg; + /* Read CTRL_REG2 register */ + ACCELERO_IO_Read(&tmpreg, LIS302DL_CTRL_REG2_ADDR, 1); + 8000628: 2201 movs r2, #1 + 800062a: f10d 0007 add.w r0, sp, #7 + 800062e: 2121 movs r1, #33 ; 0x21 + 8000630: f000 fac0 bl 8000bb4 + + /* Enable or Disable the reboot memory */ + tmpreg |= LIS302DL_BOOT_REBOOTMEMORY; + 8000634: f89d 3007 ldrb.w r3, [sp, #7] + + /* Write value to MEMS CTRL_REG2 register */ + ACCELERO_IO_Write(&tmpreg, LIS302DL_CTRL_REG2_ADDR, 1); + 8000638: 2201 movs r2, #1 + tmpreg |= LIS302DL_BOOT_REBOOTMEMORY; + 800063a: f043 0340 orr.w r3, r3, #64 ; 0x40 + ACCELERO_IO_Write(&tmpreg, LIS302DL_CTRL_REG2_ADDR, 1); + 800063e: 2121 movs r1, #33 ; 0x21 + 8000640: f10d 0007 add.w r0, sp, #7 + tmpreg |= LIS302DL_BOOT_REBOOTMEMORY; + 8000644: f88d 3007 strb.w r3, [sp, #7] + ACCELERO_IO_Write(&tmpreg, LIS302DL_CTRL_REG2_ADDR, 1); + 8000648: f000 fa92 bl 8000b70 +} + 800064c: b003 add sp, #12 + 800064e: f85d fb04 ldr.w pc, [sp], #4 + +08000652 : + * ACC[mg]=SENSITIVITY* (out_h*256+out_l)/16 (12 bit rappresentation) + * @param pfData: Data out pointer + * @retval None + */ +void LIS302DL_ReadACC(int16_t *pData) +{ + 8000652: b51f push {r0, r1, r2, r3, r4, lr} + 8000654: 4604 mov r4, r0 + int8_t buffer[6]; + int16_t pnRawData[3]; + uint8_t sensitivity = LIS302DL_SENSITIVITY_2_3G; + uint8_t crtl, i = 0x00; + + ACCELERO_IO_Read(&crtl, LIS302DL_CTRL_REG1_ADDR, 1); + 8000656: 2201 movs r2, #1 + 8000658: f10d 0007 add.w r0, sp, #7 + 800065c: 2120 movs r1, #32 + 800065e: f000 faa9 bl 8000bb4 + ACCELERO_IO_Read((uint8_t*)buffer, LIS302DL_OUT_X_ADDR, 6); + 8000662: a802 add r0, sp, #8 + 8000664: 2206 movs r2, #6 + 8000666: 2129 movs r1, #41 ; 0x29 + 8000668: f000 faa4 bl 8000bb4 + for(i=0; i<3; i++) + { + pnRawData[i] = buffer[2*i]; + } + + switch(crtl & LIS302DL_FULLSCALE_9_2) + 800066c: f89d 2007 ldrb.w r2, [sp, #7] + pnRawData[i] = buffer[2*i]; + 8000670: f99d 0008 ldrsb.w r0, [sp, #8] + 8000674: f99d 100a ldrsb.w r1, [sp, #10] + 8000678: f99d 300c ldrsb.w r3, [sp, #12] + switch(crtl & LIS302DL_FULLSCALE_9_2) + 800067c: f002 0220 and.w r2, r2, #32 + 8000680: 2a20 cmp r2, #32 + } + + /* Obtain the mg value for the three axis */ + for(i=0; i<3; i++) + { + pData[i]=(pnRawData[i] * sensitivity); + 8000682: bf0c ite eq + 8000684: 2248 moveq r2, #72 ; 0x48 + 8000686: 2212 movne r2, #18 + 8000688: fb10 f002 smulbb r0, r0, r2 + 800068c: fb11 f102 smulbb r1, r1, r2 + 8000690: fb13 f302 smulbb r3, r3, r2 + 8000694: 8020 strh r0, [r4, #0] + 8000696: 8061 strh r1, [r4, #2] + 8000698: 80a3 strh r3, [r4, #4] + } +} + 800069a: b004 add sp, #16 + 800069c: bd10 pop {r4, pc} + +0800069e : +{ + 800069e: b537 push {r0, r1, r2, r4, r5, lr} + uint8_t ctrl = 0x00; + 80006a0: ac02 add r4, sp, #8 + 80006a2: 2300 movs r3, #0 + 80006a4: f804 3d01 strb.w r3, [r4, #-1]! +{ + 80006a8: 4605 mov r5, r0 + ACCELERO_IO_Read(&ctrl, LIS302DL_CLICK_CFG_REG_ADDR, 1); + 80006aa: 2201 movs r2, #1 + 80006ac: 4620 mov r0, r4 + 80006ae: 2138 movs r1, #56 ; 0x38 + 80006b0: f000 fa80 bl 8000bb4 + ctrl = (uint8_t)(LIS302DL_IntConfigStruct->Latch_Request| \ + 80006b4: 786a ldrb r2, [r5, #1] + 80006b6: 782b ldrb r3, [r5, #0] + 80006b8: 4313 orrs r3, r2 + 80006ba: 78aa ldrb r2, [r5, #2] + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_CFG_REG_ADDR, 1); + 80006bc: 2138 movs r1, #56 ; 0x38 + ctrl = (uint8_t)(LIS302DL_IntConfigStruct->Latch_Request| \ + 80006be: 4313 orrs r3, r2 + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_CFG_REG_ADDR, 1); + 80006c0: 4620 mov r0, r4 + 80006c2: 2201 movs r2, #1 + ctrl = (uint8_t)(LIS302DL_IntConfigStruct->Latch_Request| \ + 80006c4: f88d 3007 strb.w r3, [sp, #7] + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_CFG_REG_ADDR, 1); + 80006c8: f000 fa52 bl 8000b70 +} + 80006cc: b003 add sp, #12 + 80006ce: bd30 pop {r4, r5, pc} + +080006d0 : +{ + 80006d0: b573 push {r0, r1, r4, r5, r6, lr} + uint8_t ctrl = 0x00; + 80006d2: 2300 movs r3, #0 + 80006d4: f88d 3003 strb.w r3, [sp, #3] + ACCELERO_IO_ITConfig(); + 80006d8: f000 fa22 bl 8000b20 + LIS302DL_InterruptStruct.Latch_Request = LIS302DL_INTERRUPTREQUEST_LATCHED; + 80006dc: 2340 movs r3, #64 ; 0x40 + ctrl = 0x3F; + 80006de: ac02 add r4, sp, #8 + LIS302DL_InterruptStruct.Latch_Request = LIS302DL_INTERRUPTREQUEST_LATCHED; + 80006e0: f88d 3004 strb.w r3, [sp, #4] + LIS302DL_InterruptStruct.SingleClick_Axes = LIS302DL_CLICKINTERRUPT_Z_ENABLE; + 80006e4: 2310 movs r3, #16 + 80006e6: f88d 3005 strb.w r3, [sp, #5] + LIS302DL_InterruptConfig(&LIS302DL_InterruptStruct); + 80006ea: a801 add r0, sp, #4 + LIS302DL_InterruptStruct.DoubleClick_Axes = LIS302DL_DOUBLECLICKINTERRUPT_Z_ENABLE; + 80006ec: 2320 movs r3, #32 + ctrl = 0x3F; + 80006ee: 253f movs r5, #63 ; 0x3f + LIS302DL_InterruptStruct.DoubleClick_Axes = LIS302DL_DOUBLECLICKINTERRUPT_Z_ENABLE; + 80006f0: f88d 3006 strb.w r3, [sp, #6] + LIS302DL_InterruptConfig(&LIS302DL_InterruptStruct); + 80006f4: f7ff ffd3 bl 800069e + ctrl = 0x3F; + 80006f8: f804 5d05 strb.w r5, [r4, #-5]! + ACCELERO_IO_Write(&ctrl, LIS302DL_CTRL_REG3_ADDR, 1); + 80006fc: 2201 movs r2, #1 + 80006fe: 4620 mov r0, r4 + 8000700: 2122 movs r1, #34 ; 0x22 + 8000702: f000 fa35 bl 8000b70 + ctrl = 0x50; + 8000706: 2350 movs r3, #80 ; 0x50 + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_CFG_REG_ADDR, 1); + 8000708: 4620 mov r0, r4 + 800070a: 2201 movs r2, #1 + 800070c: 2138 movs r1, #56 ; 0x38 + ctrl = 0x50; + 800070e: f88d 3003 strb.w r3, [sp, #3] + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_CFG_REG_ADDR, 1); + 8000712: f000 fa2d bl 8000b70 + ctrl = 0xAA; + 8000716: 23aa movs r3, #170 ; 0xaa + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_THSY_X_REG_ADDR, 1); + 8000718: 4620 mov r0, r4 + 800071a: 2201 movs r2, #1 + 800071c: 213b movs r1, #59 ; 0x3b + ctrl = 0xAA; + 800071e: f88d 3003 strb.w r3, [sp, #3] + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_THSY_X_REG_ADDR, 1); + 8000722: f000 fa25 bl 8000b70 + ctrl = 0x0A; + 8000726: 230a movs r3, #10 + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_THSZ_REG_ADDR, 1); + 8000728: 4620 mov r0, r4 + 800072a: 2201 movs r2, #1 + 800072c: 213c movs r1, #60 ; 0x3c + ctrl = 0x0A; + 800072e: f88d 3003 strb.w r3, [sp, #3] + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_THSZ_REG_ADDR, 1); + 8000732: f000 fa1d bl 8000b70 + ctrl = 0x4C; + 8000736: 234c movs r3, #76 ; 0x4c + ACCELERO_IO_Write(&ctrl, LIS302DL_FF_WU_CFG1_REG_ADDR, 1); + 8000738: 4620 mov r0, r4 + 800073a: 2201 movs r2, #1 + 800073c: 2130 movs r1, #48 ; 0x30 + ctrl = 0x4C; + 800073e: f88d 3003 strb.w r3, [sp, #3] + ACCELERO_IO_Write(&ctrl, LIS302DL_FF_WU_CFG1_REG_ADDR, 1); + 8000742: f000 fa15 bl 8000b70 + ctrl = 0x03; + 8000746: 2303 movs r3, #3 + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_TIMELIMIT_REG_ADDR, 1); + 8000748: 4620 mov r0, r4 + 800074a: 2201 movs r2, #1 + 800074c: 213d movs r1, #61 ; 0x3d + ctrl = 0x03; + 800074e: f88d 3003 strb.w r3, [sp, #3] + ctrl = 0x7F; + 8000752: 267f movs r6, #127 ; 0x7f + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_TIMELIMIT_REG_ADDR, 1); + 8000754: f000 fa0c bl 8000b70 + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_LATENCY_REG_ADDR, 1); + 8000758: 4620 mov r0, r4 + 800075a: 2201 movs r2, #1 + 800075c: 213e movs r1, #62 ; 0x3e + ctrl = 0x7F; + 800075e: f88d 6003 strb.w r6, [sp, #3] + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_LATENCY_REG_ADDR, 1); + 8000762: f000 fa05 bl 8000b70 + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_WINDOW_REG_ADDR, 1); + 8000766: 2201 movs r2, #1 + 8000768: 4629 mov r1, r5 + 800076a: 4620 mov r0, r4 + ctrl = 0x7F; + 800076c: f88d 6003 strb.w r6, [sp, #3] + ACCELERO_IO_Write(&ctrl, LIS302DL_CLICK_WINDOW_REG_ADDR, 1); + 8000770: f000 f9fe bl 8000b70 +} + 8000774: b002 add sp, #8 + 8000776: bd70 pop {r4, r5, r6, pc} + +08000778 : + * @brief LIS3DSH De-Initialization. + * @param None + * @retval None. + */ +void LIS3DSH_DeInit(void) +{ + 8000778: 4770 bx lr + +0800077a : +{ + 800077a: b537 push {r0, r1, r2, r4, r5, lr} + ctrl = (uint8_t) (InitStruct); + 800077c: ac02 add r4, sp, #8 + uint8_t ctrl = 0x00; + 800077e: 2300 movs r3, #0 +{ + 8000780: 4605 mov r5, r0 + uint8_t ctrl = 0x00; + 8000782: f88d 3007 strb.w r3, [sp, #7] + ACCELERO_IO_Init(); + 8000786: f000 f9a5 bl 8000ad4 + ctrl = (uint8_t) (InitStruct); + 800078a: f804 5d01 strb.w r5, [r4, #-1]! + ACCELERO_IO_Write(&ctrl, LIS3DSH_CTRL_REG4_ADDR, 1); + 800078e: 2201 movs r2, #1 + 8000790: 4620 mov r0, r4 + 8000792: 2120 movs r1, #32 + 8000794: f000 f9ec bl 8000b70 + ctrl = (uint8_t) (InitStruct >> 8); + 8000798: 0a2d lsrs r5, r5, #8 + ACCELERO_IO_Write(&ctrl, LIS3DSH_CTRL_REG5_ADDR, 1); + 800079a: 2201 movs r2, #1 + 800079c: 2124 movs r1, #36 ; 0x24 + 800079e: 4620 mov r0, r4 + ctrl = (uint8_t) (InitStruct >> 8); + 80007a0: f88d 5007 strb.w r5, [sp, #7] + ACCELERO_IO_Write(&ctrl, LIS3DSH_CTRL_REG5_ADDR, 1); + 80007a4: f000 f9e4 bl 8000b70 +} + 80007a8: b003 add sp, #12 + 80007aa: bd30 pop {r4, r5, pc} + +080007ac : + * @brief Read LIS3DSH device ID. + * @param None + * @retval The Device ID (two bytes). + */ +uint8_t LIS3DSH_ReadID(void) +{ + 80007ac: b513 push {r0, r1, r4, lr} + uint8_t tmp = 0; + 80007ae: ac02 add r4, sp, #8 + 80007b0: 2300 movs r3, #0 + 80007b2: f804 3d01 strb.w r3, [r4, #-1]! + + /* Configure the low level interface */ + ACCELERO_IO_Init(); + 80007b6: f000 f98d bl 8000ad4 + + /* Read WHO_AM_I register */ + ACCELERO_IO_Read(&tmp, LIS3DSH_WHO_AM_I_ADDR, 1); + 80007ba: 4620 mov r0, r4 + 80007bc: 2201 movs r2, #1 + 80007be: 210f movs r1, #15 + 80007c0: f000 f9f8 bl 8000bb4 + + /* Return the ID */ + return (uint16_t)tmp; +} + 80007c4: f89d 0007 ldrb.w r0, [sp, #7] + 80007c8: b002 add sp, #8 + 80007ca: bd10 pop {r4, pc} + +080007cc : + * @brief Reboot memory content of LIS3DSH. + * @param None + * @retval None + */ +void LIS3DSH_RebootCmd(void) +{ + 80007cc: b507 push {r0, r1, r2, lr} + uint8_t tmpreg; + /* Read CTRL_REG6 register */ + ACCELERO_IO_Read(&tmpreg, LIS3DSH_CTRL_REG6_ADDR, 1); + 80007ce: 2201 movs r2, #1 + 80007d0: f10d 0007 add.w r0, sp, #7 + 80007d4: 2125 movs r1, #37 ; 0x25 + 80007d6: f000 f9ed bl 8000bb4 + + /* Enable or Disable the reboot memory */ + tmpreg |= LIS3DSH_BOOT_FORCED; + 80007da: f89d 3007 ldrb.w r3, [sp, #7] + + /* Write value to MEMS CTRL_REG6 register */ + ACCELERO_IO_Write(&tmpreg, LIS3DSH_CTRL_REG6_ADDR, 1); + 80007de: 2201 movs r2, #1 + tmpreg |= LIS3DSH_BOOT_FORCED; + 80007e0: f063 037f orn r3, r3, #127 ; 0x7f + ACCELERO_IO_Write(&tmpreg, LIS3DSH_CTRL_REG6_ADDR, 1); + 80007e4: 2125 movs r1, #37 ; 0x25 + 80007e6: f10d 0007 add.w r0, sp, #7 + tmpreg |= LIS3DSH_BOOT_FORCED; + 80007ea: f88d 3007 strb.w r3, [sp, #7] + ACCELERO_IO_Write(&tmpreg, LIS3DSH_CTRL_REG6_ADDR, 1); + 80007ee: f000 f9bf bl 8000b70 +} + 80007f2: b003 add sp, #12 + 80007f4: f85d fb04 ldr.w pc, [sp], #4 + +080007f8 : + * ACC[mg]=SENSITIVITY* (out_h*256+out_l)/16 (12 bit representation). + * @param pointer on floating buffer. + * @retval None + */ +void LIS3DSH_ReadACC(int16_t *pData) +{ + 80007f8: b530 push {r4, r5, lr} + 80007fa: b085 sub sp, #20 + int8_t buffer[6]; + uint8_t crtl, i = 0x00; + float sensitivity = LIS3DSH_SENSITIVITY_0_06G; + float valueinfloat = 0; + + ACCELERO_IO_Read(&crtl, LIS3DSH_CTRL_REG5_ADDR, 1); + 80007fc: 2201 movs r2, #1 + 80007fe: 2124 movs r1, #36 ; 0x24 +{ + 8000800: 4605 mov r5, r0 + ACCELERO_IO_Read((uint8_t*)&buffer[0], LIS3DSH_OUT_X_L_ADDR, 1); + 8000802: ac02 add r4, sp, #8 + ACCELERO_IO_Read(&crtl, LIS3DSH_CTRL_REG5_ADDR, 1); + 8000804: f10d 0007 add.w r0, sp, #7 + 8000808: f000 f9d4 bl 8000bb4 + ACCELERO_IO_Read((uint8_t*)&buffer[0], LIS3DSH_OUT_X_L_ADDR, 1); + 800080c: 2201 movs r2, #1 + 800080e: 2128 movs r1, #40 ; 0x28 + 8000810: 4620 mov r0, r4 + 8000812: f000 f9cf bl 8000bb4 + ACCELERO_IO_Read((uint8_t*)&buffer[1], LIS3DSH_OUT_X_H_ADDR, 1); + 8000816: 2201 movs r2, #1 + 8000818: 2129 movs r1, #41 ; 0x29 + 800081a: f10d 0009 add.w r0, sp, #9 + 800081e: f000 f9c9 bl 8000bb4 + ACCELERO_IO_Read((uint8_t*)&buffer[2], LIS3DSH_OUT_Y_L_ADDR, 1); + 8000822: 2201 movs r2, #1 + 8000824: 212a movs r1, #42 ; 0x2a + 8000826: f10d 000a add.w r0, sp, #10 + 800082a: f000 f9c3 bl 8000bb4 + ACCELERO_IO_Read((uint8_t*)&buffer[3], LIS3DSH_OUT_Y_H_ADDR, 1); + 800082e: 2201 movs r2, #1 + 8000830: 212b movs r1, #43 ; 0x2b + 8000832: f10d 000b add.w r0, sp, #11 + 8000836: f000 f9bd bl 8000bb4 + ACCELERO_IO_Read((uint8_t*)&buffer[4], LIS3DSH_OUT_Z_L_ADDR, 1); + 800083a: 2201 movs r2, #1 + 800083c: 212c movs r1, #44 ; 0x2c + 800083e: a803 add r0, sp, #12 + 8000840: f000 f9b8 bl 8000bb4 + ACCELERO_IO_Read((uint8_t*)&buffer[5], LIS3DSH_OUT_Z_H_ADDR, 1); + 8000844: 2201 movs r2, #1 + 8000846: 212d movs r1, #45 ; 0x2d + 8000848: f10d 000d add.w r0, sp, #13 + 800084c: f000 f9b2 bl 8000bb4 + 8000850: f89d 3007 ldrb.w r3, [sp, #7] + 8000854: f003 0338 and.w r3, r3, #56 ; 0x38 + 8000858: 3b08 subs r3, #8 + 800085a: b2db uxtb r3, r3 + 800085c: 2b18 cmp r3, #24 + 800085e: bf97 itett ls + 8000860: 4a0e ldrls r2, [pc, #56] ; (800089c ) + + switch(crtl & LIS3DSH__FULLSCALE_SELECTION) + 8000862: ed9f 7a0f vldrhi s14, [pc, #60] ; 80008a0 + 8000866: eb02 0383 addls.w r3, r2, r3, lsl #2 + 800086a: ed93 7a00 vldrls s14, [r3] + 800086e: 2200 movs r2, #0 + } + + /* Obtain the mg value for the three axis */ + for(i=0; i<3; i++) + { + valueinfloat = ((buffer[2*i+1] << 8) + buffer[2*i]) * sensitivity; + 8000870: 18a3 adds r3, r4, r2 + 8000872: f993 1001 ldrsb.w r1, [r3, #1] + 8000876: 56a3 ldrsb r3, [r4, r2] + 8000878: eb03 2301 add.w r3, r3, r1, lsl #8 + 800087c: ee07 3a90 vmov s15, r3 + 8000880: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8000884: ee67 7a87 vmul.f32 s15, s15, s14 + pData[i] = (int16_t)valueinfloat; + 8000888: eefd 7ae7 vcvt.s32.f32 s15, s15 + 800088c: ee17 3a90 vmov r3, s15 + 8000890: 52ab strh r3, [r5, r2] + 8000892: 3202 adds r2, #2 + for(i=0; i<3; i++) + 8000894: 2a06 cmp r2, #6 + 8000896: d1eb bne.n 8000870 + } +} + 8000898: b005 add sp, #20 + 800089a: bd30 pop {r4, r5, pc} + 800089c: 08006bfc .word 0x08006bfc + 80008a0: 3d75c28f .word 0x3d75c28f + +080008a4 : +{ + 80008a4: b537 push {r0, r1, r2, r4, r5, lr} + ctrl = (uint8_t)(LIS3DSH_IntConfigStruct->Interrupt_Selection_Enable | \ + 80008a6: 7802 ldrb r2, [r0, #0] + 80008a8: 7843 ldrb r3, [r0, #1] + 80008aa: 4313 orrs r3, r2 + 80008ac: 7882 ldrb r2, [r0, #2] + 80008ae: ad02 add r5, sp, #8 + 80008b0: 4313 orrs r3, r2 + 80008b2: f805 3d01 strb.w r3, [r5, #-1]! +{ + 80008b6: 4604 mov r4, r0 + ACCELERO_IO_Write(&ctrl, LIS3DSH_CTRL_REG3_ADDR, 1); + 80008b8: 2201 movs r2, #1 + 80008ba: 4628 mov r0, r5 + 80008bc: 2123 movs r1, #35 ; 0x23 + 80008be: f000 f957 bl 8000b70 + ctrl = (uint8_t)(LIS3DSH_IntConfigStruct->State_Machine1_Enable | \ + 80008c2: 7922 ldrb r2, [r4, #4] + 80008c4: 78e3 ldrb r3, [r4, #3] + ACCELERO_IO_Write(&ctrl, LIS3DSH_CTRL_REG1_ADDR, 1); + 80008c6: 4628 mov r0, r5 + ctrl = (uint8_t)(LIS3DSH_IntConfigStruct->State_Machine1_Enable | \ + 80008c8: 4313 orrs r3, r2 + ACCELERO_IO_Write(&ctrl, LIS3DSH_CTRL_REG1_ADDR, 1); + 80008ca: 2121 movs r1, #33 ; 0x21 + 80008cc: 2201 movs r2, #1 + ctrl = (uint8_t)(LIS3DSH_IntConfigStruct->State_Machine1_Enable | \ + 80008ce: f88d 3007 strb.w r3, [sp, #7] + ACCELERO_IO_Write(&ctrl, LIS3DSH_CTRL_REG1_ADDR, 1); + 80008d2: f000 f94d bl 8000b70 + ctrl = (uint8_t)(LIS3DSH_IntConfigStruct->State_Machine2_Enable | \ + 80008d6: 79a2 ldrb r2, [r4, #6] + 80008d8: 7963 ldrb r3, [r4, #5] + ACCELERO_IO_Write(&ctrl, LIS3DSH_CTRL_REG2_ADDR, 1); + 80008da: 2122 movs r1, #34 ; 0x22 + ctrl = (uint8_t)(LIS3DSH_IntConfigStruct->State_Machine2_Enable | \ + 80008dc: 4313 orrs r3, r2 + ACCELERO_IO_Write(&ctrl, LIS3DSH_CTRL_REG2_ADDR, 1); + 80008de: 4628 mov r0, r5 + 80008e0: 2201 movs r2, #1 + ctrl = (uint8_t)(LIS3DSH_IntConfigStruct->State_Machine2_Enable | \ + 80008e2: f88d 3007 strb.w r3, [sp, #7] + ACCELERO_IO_Write(&ctrl, LIS3DSH_CTRL_REG2_ADDR, 1); + 80008e6: f000 f943 bl 8000b70 +} + 80008ea: b003 add sp, #12 + 80008ec: bd30 pop {r4, r5, pc} + +080008ee : +{ + 80008ee: b530 push {r4, r5, lr} + 80008f0: b085 sub sp, #20 + uint8_t ctrl = 0x00; + 80008f2: 2400 movs r4, #0 + LIS3DSH_InterruptStruct.State_Machine2_Enable = LIS3DSH_SM_ENABLE; + 80008f4: 2501 movs r5, #1 + uint8_t ctrl = 0x00; + 80008f6: f88d 4007 strb.w r4, [sp, #7] + ACCELERO_IO_ITConfig(); + 80008fa: f000 f911 bl 8000b20 + LIS3DSH_InterruptStruct.Interrupt_Selection_Enable = LIS3DSH_INTERRUPT_2_ENABLE; + 80008fe: f88d 4009 strb.w r4, [sp, #9] + LIS3DSH_InterruptStruct.Interrupt_Request = LIS3DSH_INTERRUPT_REQUEST_LATCHED; + 8000902: f88d 4008 strb.w r4, [sp, #8] + LIS3DSH_InterruptStruct.Interrupt_Signal = LIS3DSH_INTERRUPT_SIGNAL_HIGH; + 8000906: 2340 movs r3, #64 ; 0x40 + LIS3DSH_InterruptStruct.State_Machine1_Enable = LIS3DSH_SM_DISABLE; + 8000908: f88d 400b strb.w r4, [sp, #11] + LIS3DSH_InterruptStruct.State_Machine2_Interrupt = LIS3DSH_SM_INT1; + 800090c: f88d 400e strb.w r4, [sp, #14] + LIS3DSH_InterruptConfig(&LIS3DSH_InterruptStruct); + 8000910: a802 add r0, sp, #8 + ctrl=0x03; + 8000912: ac04 add r4, sp, #16 + LIS3DSH_InterruptStruct.Interrupt_Signal = LIS3DSH_INTERRUPT_SIGNAL_HIGH; + 8000914: f88d 300a strb.w r3, [sp, #10] + LIS3DSH_InterruptStruct.State_Machine2_Enable = LIS3DSH_SM_ENABLE; + 8000918: f88d 500d strb.w r5, [sp, #13] + LIS3DSH_InterruptConfig(&LIS3DSH_InterruptStruct); + 800091c: f7ff ffc2 bl 80008a4 + ctrl=0x03; + 8000920: 2303 movs r3, #3 + 8000922: f804 3d09 strb.w r3, [r4, #-9]! + ACCELERO_IO_Write(&ctrl, LIS3DSH_TIM2_1_L_ADDR,1); + 8000926: 462a mov r2, r5 + 8000928: 4620 mov r0, r4 + 800092a: 2152 movs r1, #82 ; 0x52 + 800092c: f000 f920 bl 8000b70 + ctrl=0xC8; + 8000930: 23c8 movs r3, #200 ; 0xc8 + ACCELERO_IO_Write(&ctrl, LIS3DSH_TIM1_1_L_ADDR,1); + 8000932: 462a mov r2, r5 + 8000934: 4620 mov r0, r4 + 8000936: 2154 movs r1, #84 ; 0x54 + ctrl=0xC8; + 8000938: f88d 3007 strb.w r3, [sp, #7] + ACCELERO_IO_Write(&ctrl, LIS3DSH_TIM1_1_L_ADDR,1); + 800093c: f000 f918 bl 8000b70 + ctrl=0x45; + 8000940: 2345 movs r3, #69 ; 0x45 + ACCELERO_IO_Write(&ctrl, LIS3DSH_THRS2_1_ADDR,1); + 8000942: 462a mov r2, r5 + 8000944: 4620 mov r0, r4 + 8000946: 2156 movs r1, #86 ; 0x56 + ctrl=0x45; + 8000948: f88d 3007 strb.w r3, [sp, #7] + ACCELERO_IO_Write(&ctrl, LIS3DSH_THRS2_1_ADDR,1); + 800094c: f000 f910 bl 8000b70 + ctrl=0xFC; + 8000950: 23fc movs r3, #252 ; 0xfc + ACCELERO_IO_Write(&ctrl, LIS3DSH_MASK1_A_ADDR,1); + 8000952: 462a mov r2, r5 + 8000954: 4620 mov r0, r4 + 8000956: 215a movs r1, #90 ; 0x5a + ctrl=0xFC; + 8000958: f88d 3007 strb.w r3, [sp, #7] + ACCELERO_IO_Write(&ctrl, LIS3DSH_MASK1_A_ADDR,1); + 800095c: f000 f908 bl 8000b70 + ctrl=0xA1; + 8000960: 23a1 movs r3, #161 ; 0xa1 + ACCELERO_IO_Write(&ctrl, LIS3DSH_SETT1_ADDR,1); + 8000962: 462a mov r2, r5 + 8000964: 4620 mov r0, r4 + 8000966: 215b movs r1, #91 ; 0x5b + ctrl=0xA1; + 8000968: f88d 3007 strb.w r3, [sp, #7] + ACCELERO_IO_Write(&ctrl, LIS3DSH_SETT1_ADDR,1); + 800096c: f000 f900 bl 8000b70 + ACCELERO_IO_Write(&ctrl, LIS3DSH_PR1_ADDR,1); + 8000970: 462a mov r2, r5 + 8000972: 4620 mov r0, r4 + 8000974: 215c movs r1, #92 ; 0x5c + ctrl=0x01; + 8000976: f88d 5007 strb.w r5, [sp, #7] + ACCELERO_IO_Write(&ctrl, LIS3DSH_PR1_ADDR,1); + 800097a: f000 f8f9 bl 8000b70 + ACCELERO_IO_Write(&ctrl, LIS3DSH_SETT2_ADDR,1); + 800097e: 462a mov r2, r5 + 8000980: 4620 mov r0, r4 + 8000982: 217b movs r1, #123 ; 0x7b + 8000984: f000 f8f4 bl 8000b70 + ACCELERO_IO_Write(&ctrl, LIS3DSH_ST2_1_ADDR,1); + 8000988: 462a mov r2, r5 + 800098a: 4620 mov r0, r4 + 800098c: 2160 movs r1, #96 ; 0x60 + 800098e: f000 f8ef bl 8000b70 + ctrl=0x06; + 8000992: 2306 movs r3, #6 + ACCELERO_IO_Write(&ctrl, LIS3DSH_ST2_2_ADDR,1); + 8000994: 462a mov r2, r5 + 8000996: 4620 mov r0, r4 + 8000998: 2161 movs r1, #97 ; 0x61 + ctrl=0x06; + 800099a: f88d 3007 strb.w r3, [sp, #7] + ACCELERO_IO_Write(&ctrl, LIS3DSH_ST2_2_ADDR,1); + 800099e: f000 f8e7 bl 8000b70 + ctrl=0x28; + 80009a2: 2328 movs r3, #40 ; 0x28 + ACCELERO_IO_Write(&ctrl, LIS3DSH_ST2_3_ADDR,1); + 80009a4: 462a mov r2, r5 + 80009a6: 4620 mov r0, r4 + 80009a8: 2162 movs r1, #98 ; 0x62 + ctrl=0x28; + 80009aa: f88d 3007 strb.w r3, [sp, #7] + ACCELERO_IO_Write(&ctrl, LIS3DSH_ST2_3_ADDR,1); + 80009ae: f000 f8df bl 8000b70 + ctrl=0x11; + 80009b2: 2311 movs r3, #17 + ACCELERO_IO_Write(&ctrl, LIS3DSH_ST2_4_ADDR,1); + 80009b4: 462a mov r2, r5 + 80009b6: 2163 movs r1, #99 ; 0x63 + 80009b8: 4620 mov r0, r4 + ctrl=0x11; + 80009ba: f88d 3007 strb.w r3, [sp, #7] + ACCELERO_IO_Write(&ctrl, LIS3DSH_ST2_4_ADDR,1); + 80009be: f000 f8d7 bl 8000b70 +} + 80009c2: b005 add sp, #20 + 80009c4: bd30 pop {r4, r5, pc} + ... + +080009c8 : + +/** + * @brief SPIx Bus initialization + */ +static void SPIx_Init(void) +{ + 80009c8: b510 push {r4, lr} + if(HAL_SPI_GetState(&SpiHandle) == HAL_SPI_STATE_RESET) + 80009ca: 4c20 ldr r4, [pc, #128] ; (8000a4c ) +{ + 80009cc: b088 sub sp, #32 + if(HAL_SPI_GetState(&SpiHandle) == HAL_SPI_STATE_RESET) + 80009ce: 4620 mov r0, r4 + 80009d0: f001 ff7c bl 80028cc + 80009d4: 2800 cmp r0, #0 + 80009d6: d137 bne.n 8000a48 + { + /* SPI configuration -----------------------------------------------------*/ + SpiHandle.Instance = DISCOVERY_SPIx; + 80009d8: 4b1d ldr r3, [pc, #116] ; (8000a50 ) + 80009da: 6023 str r3, [r4, #0] + SpiHandle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; + 80009dc: 2318 movs r3, #24 + 80009de: 61e3 str r3, [r4, #28] + SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; + SpiHandle.Init.CLKPhase = SPI_PHASE_1EDGE; + SpiHandle.Init.CLKPolarity = SPI_POLARITY_LOW; + SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; + SpiHandle.Init.CRCPolynomial = 7; + 80009e0: 2307 movs r3, #7 + 80009e2: 62e3 str r3, [r4, #44] ; 0x2c + SpiHandle.Init.DataSize = SPI_DATASIZE_8BIT; + SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; + SpiHandle.Init.NSS = SPI_NSS_SOFT; + 80009e4: f44f 7300 mov.w r3, #512 ; 0x200 + 80009e8: 61a3 str r3, [r4, #24] + SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; + SpiHandle.Init.Mode = SPI_MODE_MASTER; + 80009ea: f44f 7382 mov.w r3, #260 ; 0x104 + 80009ee: 6063 str r3, [r4, #4] +static void SPIx_MspInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable the SPI peripheral */ + DISCOVERY_SPIx_CLK_ENABLE(); + 80009f0: 4b18 ldr r3, [pc, #96] ; (8000a54 ) + 80009f2: 9001 str r0, [sp, #4] + SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; + 80009f4: 60a0 str r0, [r4, #8] + SpiHandle.Init.CLKPhase = SPI_PHASE_1EDGE; + 80009f6: 6160 str r0, [r4, #20] + SpiHandle.Init.CLKPolarity = SPI_POLARITY_LOW; + 80009f8: 6120 str r0, [r4, #16] + SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; + 80009fa: 62a0 str r0, [r4, #40] ; 0x28 + SpiHandle.Init.DataSize = SPI_DATASIZE_8BIT; + 80009fc: 60e0 str r0, [r4, #12] + SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; + 80009fe: 6220 str r0, [r4, #32] + SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; + 8000a00: 6260 str r0, [r4, #36] ; 0x24 + DISCOVERY_SPIx_CLK_ENABLE(); + 8000a02: 6c5a ldr r2, [r3, #68] ; 0x44 + 8000a04: f442 5280 orr.w r2, r2, #4096 ; 0x1000 + 8000a08: 645a str r2, [r3, #68] ; 0x44 + 8000a0a: 6c5a ldr r2, [r3, #68] ; 0x44 + 8000a0c: f402 5280 and.w r2, r2, #4096 ; 0x1000 + 8000a10: 9201 str r2, [sp, #4] + 8000a12: 9a01 ldr r2, [sp, #4] + + /* Enable SCK, MOSI and MISO GPIO clocks */ + DISCOVERY_SPIx_GPIO_CLK_ENABLE(); + 8000a14: 9002 str r0, [sp, #8] + 8000a16: 6b1a ldr r2, [r3, #48] ; 0x30 + GPIO_InitStructure.Pin = (DISCOVERY_SPIx_SCK_PIN | DISCOVERY_SPIx_MISO_PIN | DISCOVERY_SPIx_MOSI_PIN); + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; + GPIO_InitStructure.Pull = GPIO_PULLDOWN; + GPIO_InitStructure.Speed = GPIO_SPEED_MEDIUM; + GPIO_InitStructure.Alternate = DISCOVERY_SPIx_AF; + HAL_GPIO_Init(DISCOVERY_SPIx_GPIO_PORT, &GPIO_InitStructure); + 8000a18: 480f ldr r0, [pc, #60] ; (8000a58 ) + DISCOVERY_SPIx_GPIO_CLK_ENABLE(); + 8000a1a: f042 0201 orr.w r2, r2, #1 + 8000a1e: 631a str r2, [r3, #48] ; 0x30 + 8000a20: 6b1b ldr r3, [r3, #48] ; 0x30 + 8000a22: f003 0301 and.w r3, r3, #1 + 8000a26: 9302 str r3, [sp, #8] + 8000a28: 9b02 ldr r3, [sp, #8] + GPIO_InitStructure.Pin = (DISCOVERY_SPIx_SCK_PIN | DISCOVERY_SPIx_MISO_PIN | DISCOVERY_SPIx_MOSI_PIN); + 8000a2a: 23e0 movs r3, #224 ; 0xe0 + 8000a2c: 9303 str r3, [sp, #12] + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; + 8000a2e: 2302 movs r3, #2 + 8000a30: 9304 str r3, [sp, #16] + GPIO_InitStructure.Pull = GPIO_PULLDOWN; + 8000a32: 9305 str r3, [sp, #20] + GPIO_InitStructure.Speed = GPIO_SPEED_MEDIUM; + 8000a34: 2301 movs r3, #1 + 8000a36: 9306 str r3, [sp, #24] + HAL_GPIO_Init(DISCOVERY_SPIx_GPIO_PORT, &GPIO_InitStructure); + 8000a38: a903 add r1, sp, #12 + GPIO_InitStructure.Alternate = DISCOVERY_SPIx_AF; + 8000a3a: 2305 movs r3, #5 + 8000a3c: 9307 str r3, [sp, #28] + HAL_GPIO_Init(DISCOVERY_SPIx_GPIO_PORT, &GPIO_InitStructure); + 8000a3e: f000 f9d5 bl 8000dec + HAL_SPI_Init(&SpiHandle); + 8000a42: 4620 mov r0, r4 + 8000a44: f001 fdf3 bl 800262e +} + 8000a48: b008 add sp, #32 + 8000a4a: bd10 pop {r4, pc} + 8000a4c: 20000260 .word 0x20000260 + 8000a50: 40013000 .word 0x40013000 + 8000a54: 40023800 .word 0x40023800 + 8000a58: 40020000 .word 0x40020000 + +08000a5c : +{ + 8000a5c: b57f push {r0, r1, r2, r3, r4, r5, r6, lr} + uint8_t receivedbyte = 0; + 8000a5e: aa06 add r2, sp, #24 + 8000a60: 2300 movs r3, #0 + 8000a62: f802 3d01 strb.w r3, [r2, #-1]! + if(HAL_SPI_TransmitReceive(&SpiHandle, (uint8_t*) &Byte, (uint8_t*) &receivedbyte, 1, SpixTimeout) != HAL_OK) + 8000a66: 4b0b ldr r3, [pc, #44] ; (8000a94 ) +{ + 8000a68: f88d 000f strb.w r0, [sp, #15] + if(HAL_SPI_TransmitReceive(&SpiHandle, (uint8_t*) &Byte, (uint8_t*) &receivedbyte, 1, SpixTimeout) != HAL_OK) + 8000a6c: 681b ldr r3, [r3, #0] + 8000a6e: 9300 str r3, [sp, #0] + 8000a70: f10d 010f add.w r1, sp, #15 + 8000a74: 2301 movs r3, #1 + 8000a76: 4808 ldr r0, [pc, #32] ; (8000a98 ) + 8000a78: f001 fe2c bl 80026d4 + 8000a7c: b120 cbz r0, 8000a88 + HAL_SPI_DeInit(&SpiHandle); + 8000a7e: 4806 ldr r0, [pc, #24] ; (8000a98 ) + 8000a80: f001 fe12 bl 80026a8 + SPIx_Init(); + 8000a84: f7ff ffa0 bl 80009c8 +} + 8000a88: f89d 0017 ldrb.w r0, [sp, #23] + 8000a8c: b007 add sp, #28 + 8000a8e: f85d fb04 ldr.w pc, [sp], #4 + 8000a92: bf00 nop + 8000a94: 20000078 .word 0x20000078 + 8000a98: 20000260 .word 0x20000260 + +08000a9c : + HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_SET); + 8000a9c: 4b04 ldr r3, [pc, #16] ; (8000ab0 ) + 8000a9e: f833 1010 ldrh.w r1, [r3, r0, lsl #1] + 8000aa2: 4b04 ldr r3, [pc, #16] ; (8000ab4 ) + 8000aa4: 2201 movs r2, #1 + 8000aa6: f853 0020 ldr.w r0, [r3, r0, lsl #2] + 8000aaa: f000 bb17 b.w 80010dc + 8000aae: bf00 nop + 8000ab0: 08006c60 .word 0x08006c60 + 8000ab4: 20000068 .word 0x20000068 + +08000ab8 : + HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_RESET); + 8000ab8: 4b04 ldr r3, [pc, #16] ; (8000acc ) + 8000aba: f833 1010 ldrh.w r1, [r3, r0, lsl #1] + 8000abe: 4b04 ldr r3, [pc, #16] ; (8000ad0 ) + 8000ac0: 2200 movs r2, #0 + 8000ac2: f853 0020 ldr.w r0, [r3, r0, lsl #2] + 8000ac6: f000 bb09 b.w 80010dc + 8000aca: bf00 nop + 8000acc: 08006c60 .word 0x08006c60 + 8000ad0: 20000068 .word 0x20000068 + +08000ad4 : + +/** + * @brief Configures the Accelerometer SPI interface. + */ +void ACCELERO_IO_Init(void) +{ + 8000ad4: b570 push {r4, r5, r6, lr} + 8000ad6: b086 sub sp, #24 + GPIO_InitTypeDef GPIO_InitStructure; + + /* Configure the Accelerometer Control pins --------------------------------*/ + /* Enable CS GPIO clock and configure GPIO pin for Accelerometer Chip select */ + ACCELERO_CS_GPIO_CLK_ENABLE(); + 8000ad8: 2100 movs r1, #0 + 8000ada: 4b0f ldr r3, [pc, #60] ; (8000b18 ) + 8000adc: 9100 str r1, [sp, #0] + 8000ade: 6b1a ldr r2, [r3, #48] ; 0x30 + /* Configure GPIO PIN for LIS Chip select */ + GPIO_InitStructure.Pin = ACCELERO_CS_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Speed = GPIO_SPEED_MEDIUM; + HAL_GPIO_Init(ACCELERO_CS_GPIO_PORT, &GPIO_InitStructure); + 8000ae0: 4d0e ldr r5, [pc, #56] ; (8000b1c ) + ACCELERO_CS_GPIO_CLK_ENABLE(); + 8000ae2: f042 0210 orr.w r2, r2, #16 + 8000ae6: 631a str r2, [r3, #48] ; 0x30 + 8000ae8: 6b1b ldr r3, [r3, #48] ; 0x30 + GPIO_InitStructure.Pull = GPIO_NOPULL; + 8000aea: 9103 str r1, [sp, #12] + ACCELERO_CS_GPIO_CLK_ENABLE(); + 8000aec: f003 0310 and.w r3, r3, #16 + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + 8000af0: 2401 movs r4, #1 + ACCELERO_CS_GPIO_CLK_ENABLE(); + 8000af2: 9300 str r3, [sp, #0] + GPIO_InitStructure.Pin = ACCELERO_CS_PIN; + 8000af4: 2608 movs r6, #8 + HAL_GPIO_Init(ACCELERO_CS_GPIO_PORT, &GPIO_InitStructure); + 8000af6: a901 add r1, sp, #4 + 8000af8: 4628 mov r0, r5 + ACCELERO_CS_GPIO_CLK_ENABLE(); + 8000afa: 9b00 ldr r3, [sp, #0] + GPIO_InitStructure.Pin = ACCELERO_CS_PIN; + 8000afc: 9601 str r6, [sp, #4] + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + 8000afe: 9402 str r4, [sp, #8] + GPIO_InitStructure.Speed = GPIO_SPEED_MEDIUM; + 8000b00: 9404 str r4, [sp, #16] + HAL_GPIO_Init(ACCELERO_CS_GPIO_PORT, &GPIO_InitStructure); + 8000b02: f000 f973 bl 8000dec + + /* Deselect: Chip Select high */ + ACCELERO_CS_HIGH(); + 8000b06: 4622 mov r2, r4 + 8000b08: 4631 mov r1, r6 + 8000b0a: 4628 mov r0, r5 + 8000b0c: f000 fae6 bl 80010dc + + SPIx_Init(); + 8000b10: f7ff ff5a bl 80009c8 +} + 8000b14: b006 add sp, #24 + 8000b16: bd70 pop {r4, r5, r6, pc} + 8000b18: 40023800 .word 0x40023800 + 8000b1c: 40021000 .word 0x40021000 + +08000b20 : +/** + * @brief Configures the Accelerometer INT2. + * EXTI0 is already used by user button so INT1 is not configured here. + */ +void ACCELERO_IO_ITConfig(void) +{ + 8000b20: b510 push {r4, lr} + 8000b22: b086 sub sp, #24 + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable INT2 GPIO clock and configure GPIO PINs to detect Interrupts */ + ACCELERO_INT_GPIO_CLK_ENABLE(); + 8000b24: 2400 movs r4, #0 + 8000b26: 4b0f ldr r3, [pc, #60] ; (8000b64 ) + 8000b28: 9400 str r4, [sp, #0] + 8000b2a: 6b1a ldr r2, [r3, #48] ; 0x30 + /* Configure GPIO PINs to detect Interrupts */ + GPIO_InitStructure.Pin = ACCELERO_INT2_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStructure.Speed = GPIO_SPEED_FAST; + GPIO_InitStructure.Pull = GPIO_NOPULL; + HAL_GPIO_Init(ACCELERO_INT_GPIO_PORT, &GPIO_InitStructure); + 8000b2c: 480e ldr r0, [pc, #56] ; (8000b68 ) + ACCELERO_INT_GPIO_CLK_ENABLE(); + 8000b2e: f042 0210 orr.w r2, r2, #16 + 8000b32: 631a str r2, [r3, #48] ; 0x30 + 8000b34: 6b1b ldr r3, [r3, #48] ; 0x30 + GPIO_InitStructure.Mode = GPIO_MODE_IT_RISING; + 8000b36: 4a0d ldr r2, [pc, #52] ; (8000b6c ) + 8000b38: 9202 str r2, [sp, #8] + ACCELERO_INT_GPIO_CLK_ENABLE(); + 8000b3a: f003 0310 and.w r3, r3, #16 + 8000b3e: 9300 str r3, [sp, #0] + 8000b40: 9b00 ldr r3, [sp, #0] + GPIO_InitStructure.Pull = GPIO_NOPULL; + 8000b42: 9403 str r4, [sp, #12] + GPIO_InitStructure.Pin = ACCELERO_INT2_PIN; + 8000b44: 2302 movs r3, #2 + HAL_GPIO_Init(ACCELERO_INT_GPIO_PORT, &GPIO_InitStructure); + 8000b46: a901 add r1, sp, #4 + GPIO_InitStructure.Pin = ACCELERO_INT2_PIN; + 8000b48: 9301 str r3, [sp, #4] + GPIO_InitStructure.Speed = GPIO_SPEED_FAST; + 8000b4a: 9304 str r3, [sp, #16] + HAL_GPIO_Init(ACCELERO_INT_GPIO_PORT, &GPIO_InitStructure); + 8000b4c: f000 f94e bl 8000dec + + /* Enable and set Accelerometer INT2 to the lowest priority */ + HAL_NVIC_SetPriority((IRQn_Type)ACCELERO_INT2_EXTI_IRQn, 0x0F, 0); + 8000b50: 4622 mov r2, r4 + 8000b52: 210f movs r1, #15 + 8000b54: 2007 movs r0, #7 + 8000b56: f000 f8e7 bl 8000d28 + HAL_NVIC_EnableIRQ((IRQn_Type)ACCELERO_INT2_EXTI_IRQn); + 8000b5a: 2007 movs r0, #7 + 8000b5c: f000 f918 bl 8000d90 +} + 8000b60: b006 add sp, #24 + 8000b62: bd10 pop {r4, pc} + 8000b64: 40023800 .word 0x40023800 + 8000b68: 40021000 .word 0x40021000 + 8000b6c: 10110000 .word 0x10110000 + +08000b70 : +{ + /* Configure the MS bit: + - When 0, the address will remain unchanged in multiple read/write commands. + - When 1, the address will be auto incremented in multiple read/write commands. + */ + if(NumByteToWrite > 0x01) + 8000b70: 2a01 cmp r2, #1 +{ + 8000b72: b570 push {r4, r5, r6, lr} + 8000b74: 460d mov r5, r1 + 8000b76: 4606 mov r6, r0 + { + WriteAddr |= (uint8_t)MULTIPLEBYTE_CMD; + 8000b78: bf88 it hi + 8000b7a: f041 0540 orrhi.w r5, r1, #64 ; 0x40 + } + /* Set chip select Low at the start of the transmission */ + ACCELERO_CS_LOW(); + 8000b7e: 480c ldr r0, [pc, #48] ; (8000bb0 ) +{ + 8000b80: 4614 mov r4, r2 + ACCELERO_CS_LOW(); + 8000b82: 2108 movs r1, #8 + 8000b84: 2200 movs r2, #0 + 8000b86: f000 faa9 bl 80010dc + + /* Send the Address of the indexed register */ + SPIx_WriteRead(WriteAddr); + 8000b8a: 4628 mov r0, r5 + 8000b8c: f7ff ff66 bl 8000a5c + + /* Send the data that will be written into the device (MSB First) */ + while(NumByteToWrite >= 0x01) + 8000b90: b934 cbnz r4, 8000ba0 + NumByteToWrite--; + pBuffer++; + } + + /* Set chip select High at the end of the transmission */ + ACCELERO_CS_HIGH(); + 8000b92: 2201 movs r2, #1 + 8000b94: 2108 movs r1, #8 + 8000b96: 4806 ldr r0, [pc, #24] ; (8000bb0 ) +} + 8000b98: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + ACCELERO_CS_HIGH(); + 8000b9c: f000 ba9e b.w 80010dc + SPIx_WriteRead(*pBuffer); + 8000ba0: f816 0b01 ldrb.w r0, [r6], #1 + NumByteToWrite--; + 8000ba4: 3c01 subs r4, #1 + SPIx_WriteRead(*pBuffer); + 8000ba6: f7ff ff59 bl 8000a5c + NumByteToWrite--; + 8000baa: b2a4 uxth r4, r4 + 8000bac: e7f0 b.n 8000b90 + 8000bae: bf00 nop + 8000bb0: 40021000 .word 0x40021000 + +08000bb4 : + * @param ReadAddr: Accelerometer's internal address to read from. + * @param NumByteToRead: number of bytes to read from the Accelerometer. + */ +void ACCELERO_IO_Read(uint8_t *pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead) +{ + if(NumByteToRead > 0x01) + 8000bb4: 2a01 cmp r2, #1 +{ + 8000bb6: b570 push {r4, r5, r6, lr} + { + ReadAddr |= (uint8_t)(READWRITE_CMD | MULTIPLEBYTE_CMD); + 8000bb8: bf8c ite hi + 8000bba: f041 05c0 orrhi.w r5, r1, #192 ; 0xc0 + } + else + { + ReadAddr |= (uint8_t)READWRITE_CMD; + 8000bbe: f041 0580 orrls.w r5, r1, #128 ; 0x80 +{ + 8000bc2: 4606 mov r6, r0 + 8000bc4: 4614 mov r4, r2 + } + /* Set chip select Low at the start of the transmission */ + ACCELERO_CS_LOW(); + 8000bc6: 480c ldr r0, [pc, #48] ; (8000bf8 ) + 8000bc8: 2200 movs r2, #0 + 8000bca: 2108 movs r1, #8 + 8000bcc: f000 fa86 bl 80010dc + + /* Send the Address of the indexed register */ + SPIx_WriteRead(ReadAddr); + 8000bd0: 4628 mov r0, r5 + 8000bd2: f7ff ff43 bl 8000a5c + + /* Receive the data that will be read from the device (MSB First) */ + while(NumByteToRead > 0x00) + 8000bd6: b934 cbnz r4, 8000be6 + NumByteToRead--; + pBuffer++; + } + + /* Set chip select High at the end of the transmission */ + ACCELERO_CS_HIGH(); + 8000bd8: 2201 movs r2, #1 + 8000bda: 2108 movs r1, #8 + 8000bdc: 4806 ldr r0, [pc, #24] ; (8000bf8 ) +} + 8000bde: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + ACCELERO_CS_HIGH(); + 8000be2: f000 ba7b b.w 80010dc + *pBuffer = SPIx_WriteRead(DUMMY_BYTE); + 8000be6: 2000 movs r0, #0 + 8000be8: f7ff ff38 bl 8000a5c + NumByteToRead--; + 8000bec: 3c01 subs r4, #1 + *pBuffer = SPIx_WriteRead(DUMMY_BYTE); + 8000bee: f806 0b01 strb.w r0, [r6], #1 + NumByteToRead--; + 8000bf2: b2a4 uxth r4, r4 + 8000bf4: e7ef b.n 8000bd6 + 8000bf6: bf00 nop + 8000bf8: 40021000 .word 0x40021000 + +08000bfc : +/** + * @brief Setx Accelerometer Initialization. + * @retval ACCELERO_OK if no problem during initialization + */ +uint8_t BSP_ACCELERO_Init(void) +{ + 8000bfc: b538 push {r3, r4, r5, lr} + uint16_t ctrl = 0x0000; + LIS302DL_InitTypeDef lis302dl_initstruct; + LIS302DL_FilterConfigTypeDef lis302dl_filter = {0,0,0}; + LIS3DSH_InitTypeDef l1s3dsh_InitStruct; + + if(Lis302dlDrv.ReadID() == I_AM_LIS302DL) + 8000bfe: 4c0e ldr r4, [pc, #56] ; (8000c38 ) + 8000c00: 68a3 ldr r3, [r4, #8] + 8000c02: 4798 blx r3 + 8000c04: 283b cmp r0, #59 ; 0x3b + 8000c06: d10a bne.n 8000c1e + { + /* Initialize the accelerometer driver structure */ + AcceleroDrv = &Lis302dlDrv; + 8000c08: 4d0c ldr r5, [pc, #48] ; (8000c3c ) + ctrl = (uint16_t) (lis302dl_initstruct.Output_DataRate | lis302dl_initstruct.Power_Mode | \ + lis302dl_initstruct.Full_Scale | lis302dl_initstruct.Self_Test | \ + lis302dl_initstruct.Axes_Enable); + + /* Configure the accelerometer main parameters */ + AcceleroDrv->Init(ctrl); + 8000c0a: 6823 ldr r3, [r4, #0] + AcceleroDrv = &Lis302dlDrv; + 8000c0c: 602c str r4, [r5, #0] + AcceleroDrv->Init(ctrl); + 8000c0e: 2047 movs r0, #71 ; 0x47 + 8000c10: 4798 blx r3 + ctrl = (uint8_t)(lis302dl_filter.HighPassFilter_Data_Selection | \ + lis302dl_filter.HighPassFilter_CutOff_Frequency | \ + lis302dl_filter.HighPassFilter_Interrupt); + + /* Configure the accelerometer LPF main parameters */ + AcceleroDrv->FilterConfig(ctrl); + 8000c12: 682b ldr r3, [r5, #0] + 8000c14: 202d movs r0, #45 ; 0x2d + 8000c16: 6a9b ldr r3, [r3, #40] ; 0x28 + 8000c18: 4798 blx r3 + l1s3dsh_InitStruct.Filter_BW) << 8); + + /* Configure the accelerometer main parameters */ + AcceleroDrv->Init(ctrl); + + ret = ACCELERO_OK; + 8000c1a: 2000 movs r0, #0 + 8000c1c: bd38 pop {r3, r4, r5, pc} + else if(Lis3dshDrv.ReadID() == I_AM_LIS3DSH) + 8000c1e: 4c08 ldr r4, [pc, #32] ; (8000c40 ) + 8000c20: 68a3 ldr r3, [r4, #8] + 8000c22: 4798 blx r3 + 8000c24: 283f cmp r0, #63 ; 0x3f + 8000c26: d105 bne.n 8000c34 + AcceleroDrv = &Lis3dshDrv; + 8000c28: 4b04 ldr r3, [pc, #16] ; (8000c3c ) + AcceleroDrv->Init(ctrl); + 8000c2a: 2067 movs r0, #103 ; 0x67 + AcceleroDrv = &Lis3dshDrv; + 8000c2c: 601c str r4, [r3, #0] + AcceleroDrv->Init(ctrl); + 8000c2e: 6823 ldr r3, [r4, #0] + 8000c30: 4798 blx r3 + 8000c32: e7f2 b.n 8000c1a + } + + else + { + ret = ACCELERO_ERROR; + 8000c34: 2001 movs r0, #1 + } + return ret; +} + 8000c36: bd38 pop {r3, r4, r5, pc} + 8000c38: 20000000 .word 0x20000000 + 8000c3c: 200002b8 .word 0x200002b8 + 8000c40: 20000034 .word 0x20000034 + +08000c44 : + * @brief Get XYZ axes acceleration. + * @param pDataXYZ: Pointer to 3 angular acceleration axes. + * pDataXYZ[0] = X axis, pDataXYZ[1] = Y axis, pDataXYZ[2] = Z axis + */ +void BSP_ACCELERO_GetXYZ(int16_t *pDataXYZ) +{ + 8000c44: b538 push {r3, r4, r5, lr} + float SwitchXY = 0; + + if(AcceleroDrv->GetXYZ != NULL) + 8000c46: 4d0d ldr r5, [pc, #52] ; (8000c7c ) + 8000c48: 682b ldr r3, [r5, #0] + 8000c4a: 6b1b ldr r3, [r3, #48] ; 0x30 +{ + 8000c4c: 4604 mov r4, r0 + if(AcceleroDrv->GetXYZ != NULL) + 8000c4e: b19b cbz r3, 8000c78 + { + AcceleroDrv->GetXYZ(pDataXYZ); + 8000c50: 4798 blx r3 + + /* Switch X and Y Axes in case of LIS302DL MEMS */ + if(AcceleroDrv == &Lis302dlDrv) + 8000c52: 682a ldr r2, [r5, #0] + 8000c54: 4b0a ldr r3, [pc, #40] ; (8000c80 ) + 8000c56: 429a cmp r2, r3 + 8000c58: d10e bne.n 8000c78 + { + SwitchXY = pDataXYZ[0]; + 8000c5a: f9b4 3000 ldrsh.w r3, [r4] + 8000c5e: ee07 3a90 vmov s15, r3 + 8000c62: eef8 7ae7 vcvt.f32.s32 s15, s15 + pDataXYZ[0] = pDataXYZ[1]; + 8000c66: 8863 ldrh r3, [r4, #2] + 8000c68: 8023 strh r3, [r4, #0] + /* Invert Y Axis to be compliant with LIS3DSH MEMS */ + pDataXYZ[1] = -SwitchXY; + 8000c6a: eef1 7a67 vneg.f32 s15, s15 + 8000c6e: eefd 7ae7 vcvt.s32.f32 s15, s15 + 8000c72: ee17 3a90 vmov r3, s15 + 8000c76: 8063 strh r3, [r4, #2] + 8000c78: bd38 pop {r3, r4, r5, pc} + 8000c7a: bf00 nop + 8000c7c: 200002b8 .word 0x200002b8 + 8000c80: 20000000 .word 0x20000000 + +08000c84 : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8000c84: b508 push {r3, lr} + /* Configure Flash prefetch, Instruction cache, Data cache */ +#if (INSTRUCTION_CACHE_ENABLE != 0U) + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + 8000c86: 4b0b ldr r3, [pc, #44] ; (8000cb4 ) + 8000c88: 681a ldr r2, [r3, #0] + 8000c8a: f442 7200 orr.w r2, r2, #512 ; 0x200 + 8000c8e: 601a str r2, [r3, #0] +#endif /* INSTRUCTION_CACHE_ENABLE */ + +#if (DATA_CACHE_ENABLE != 0U) + __HAL_FLASH_DATA_CACHE_ENABLE(); + 8000c90: 681a ldr r2, [r3, #0] + 8000c92: f442 6280 orr.w r2, r2, #1024 ; 0x400 + 8000c96: 601a str r2, [r3, #0] +#endif /* DATA_CACHE_ENABLE */ + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 8000c98: 681a ldr r2, [r3, #0] + 8000c9a: f442 7280 orr.w r2, r2, #256 ; 0x100 + 8000c9e: 601a str r2, [r3, #0] +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8000ca0: 2003 movs r0, #3 + 8000ca2: f000 f82f bl 8000d04 + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + 8000ca6: 2000 movs r0, #0 + 8000ca8: f004 fffe bl 8005ca8 + + /* Init the low level hardware */ + HAL_MspInit(); + 8000cac: f004 ff1e bl 8005aec + + /* Return function status */ + return HAL_OK; +} + 8000cb0: 2000 movs r0, #0 + 8000cb2: bd08 pop {r3, pc} + 8000cb4: 40023c00 .word 0x40023c00 + +08000cb8 : + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; + 8000cb8: 4a03 ldr r2, [pc, #12] ; (8000cc8 ) + 8000cba: 4b04 ldr r3, [pc, #16] ; (8000ccc ) + 8000cbc: 6811 ldr r1, [r2, #0] + 8000cbe: 781b ldrb r3, [r3, #0] + 8000cc0: 440b add r3, r1 + 8000cc2: 6013 str r3, [r2, #0] + 8000cc4: 4770 bx lr + 8000cc6: bf00 nop + 8000cc8: 20004014 .word 0x20004014 + 8000ccc: 2000007c .word 0x2000007c + +08000cd0 : + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; + 8000cd0: 4b01 ldr r3, [pc, #4] ; (8000cd8 ) + 8000cd2: 6818 ldr r0, [r3, #0] +} + 8000cd4: 4770 bx lr + 8000cd6: bf00 nop + 8000cd8: 20004014 .word 0x20004014 + +08000cdc : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 8000cdc: b538 push {r3, r4, r5, lr} + 8000cde: 4604 mov r4, r0 + uint32_t tickstart = HAL_GetTick(); + 8000ce0: f7ff fff6 bl 8000cd0 + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 8000ce4: 1c63 adds r3, r4, #1 + { + wait += (uint32_t)(uwTickFreq); + 8000ce6: bf1c itt ne + 8000ce8: 4b05 ldrne r3, [pc, #20] ; (8000d00 ) + 8000cea: 781b ldrbne r3, [r3, #0] + uint32_t tickstart = HAL_GetTick(); + 8000cec: 4605 mov r5, r0 + wait += (uint32_t)(uwTickFreq); + 8000cee: bf18 it ne + 8000cf0: 18e4 addne r4, r4, r3 + } + + while((HAL_GetTick() - tickstart) < wait) + 8000cf2: f7ff ffed bl 8000cd0 + 8000cf6: 1b40 subs r0, r0, r5 + 8000cf8: 4284 cmp r4, r0 + 8000cfa: d8fa bhi.n 8000cf2 + { + } +} + 8000cfc: bd38 pop {r3, r4, r5, pc} + 8000cfe: bf00 nop + 8000d00: 2000007c .word 0x2000007c + +08000d04 : +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8000d04: 4a07 ldr r2, [pc, #28] ; (8000d24 ) + 8000d06: 68d3 ldr r3, [r2, #12] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8000d08: f423 63e0 bic.w r3, r3, #1792 ; 0x700 + 8000d0c: 041b lsls r3, r3, #16 + 8000d0e: 0c1b lsrs r3, r3, #16 + 8000d10: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + 8000d14: 0200 lsls r0, r0, #8 + 8000d16: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8000d1a: f400 60e0 and.w r0, r0, #1792 ; 0x700 + reg_value = (reg_value | + 8000d1e: 4303 orrs r3, r0 + SCB->AIRCR = reg_value; + 8000d20: 60d3 str r3, [r2, #12] + 8000d22: 4770 bx lr + 8000d24: e000ed00 .word 0xe000ed00 + +08000d28 : + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8000d28: 4b17 ldr r3, [pc, #92] ; (8000d88 ) + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000d2a: b530 push {r4, r5, lr} + 8000d2c: 68dc ldr r4, [r3, #12] + 8000d2e: f3c4 2402 ubfx r4, r4, #8, #3 +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8000d32: f1c4 0307 rsb r3, r4, #7 + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8000d36: 1d25 adds r5, r4, #4 + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8000d38: 2b04 cmp r3, #4 + 8000d3a: bf28 it cs + 8000d3c: 2304 movcs r3, #4 + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8000d3e: 2d06 cmp r5, #6 + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000d40: f04f 0501 mov.w r5, #1 + 8000d44: fa05 f303 lsl.w r3, r5, r3 + 8000d48: f103 33ff add.w r3, r3, #4294967295 + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8000d4c: bf8c ite hi + 8000d4e: 3c03 subhi r4, #3 + 8000d50: 2400 movls r4, #0 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000d52: 4019 ands r1, r3 + 8000d54: 40a1 lsls r1, r4 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8000d56: fa05 f404 lsl.w r4, r5, r4 + 8000d5a: 3c01 subs r4, #1 + 8000d5c: 4022 ands r2, r4 + if ((int32_t)(IRQn) < 0) + 8000d5e: 2800 cmp r0, #0 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000d60: ea42 0201 orr.w r2, r2, r1 + 8000d64: ea4f 1202 mov.w r2, r2, lsl #4 + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000d68: bfaf iteee ge + 8000d6a: f100 4060 addge.w r0, r0, #3758096384 ; 0xe0000000 + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000d6e: f000 000f andlt.w r0, r0, #15 + 8000d72: 4b06 ldrlt r3, [pc, #24] ; (8000d8c ) + 8000d74: b2d2 uxtblt r2, r2 + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000d76: bfa5 ittet ge + 8000d78: f500 4061 addge.w r0, r0, #57600 ; 0xe100 + 8000d7c: b2d2 uxtbge r2, r2 + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000d7e: 541a strblt r2, [r3, r0] + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000d80: f880 2300 strbge.w r2, [r0, #768] ; 0x300 + 8000d84: bd30 pop {r4, r5, pc} + 8000d86: bf00 nop + 8000d88: e000ed00 .word 0xe000ed00 + 8000d8c: e000ed14 .word 0xe000ed14 + +08000d90 : + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + 8000d90: 0942 lsrs r2, r0, #5 + 8000d92: 2301 movs r3, #1 + 8000d94: f000 001f and.w r0, r0, #31 + 8000d98: fa03 f000 lsl.w r0, r3, r0 + 8000d9c: 4b01 ldr r3, [pc, #4] ; (8000da4 ) + 8000d9e: f843 0022 str.w r0, [r3, r2, lsl #2] + 8000da2: 4770 bx lr + 8000da4: e000e100 .word 0xe000e100 + +08000da8 : + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8000da8: 3801 subs r0, #1 + 8000daa: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000 + 8000dae: d20a bcs.n 8000dc6 + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8000db0: 4b06 ldr r3, [pc, #24] ; (8000dcc ) + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000db2: 4a07 ldr r2, [pc, #28] ; (8000dd0 ) + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8000db4: 6058 str r0, [r3, #4] + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000db6: 21f0 movs r1, #240 ; 0xf0 + 8000db8: f882 1023 strb.w r1, [r2, #35] ; 0x23 + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8000dbc: 2000 movs r0, #0 + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8000dbe: 2207 movs r2, #7 + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8000dc0: 6098 str r0, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8000dc2: 601a str r2, [r3, #0] + 8000dc4: 4770 bx lr + return (1UL); /* Reload value impossible */ + 8000dc6: 2001 movs r0, #1 + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} + 8000dc8: 4770 bx lr + 8000dca: bf00 nop + 8000dcc: e000e010 .word 0xe000e010 + 8000dd0: e000ed00 .word 0xe000ed00 + +08000dd4 : + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + 8000dd4: 4b04 ldr r3, [pc, #16] ; (8000de8 ) + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + 8000dd6: 681a ldr r2, [r3, #0] + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + 8000dd8: 2804 cmp r0, #4 + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + 8000dda: bf0c ite eq + 8000ddc: f042 0204 orreq.w r2, r2, #4 + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + 8000de0: f022 0204 bicne.w r2, r2, #4 + 8000de4: 601a str r2, [r3, #0] + 8000de6: 4770 bx lr + 8000de8: e000e010 .word 0xe000e010 + +08000dec : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8000dec: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8000df0: b085 sub sp, #20 + for(position = 0U; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = 0x01U << position; + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 8000df2: 680b ldr r3, [r1, #0] + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000df4: f8df 81ac ldr.w r8, [pc, #428] ; 8000fa4 + temp &= ~(0x0FU << (4U * (position & 0x03U))); + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + SYSCFG->EXTICR[position >> 2U] = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 8000df8: 4a68 ldr r2, [pc, #416] ; (8000f9c ) + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + 8000dfa: f8df 91ac ldr.w r9, [pc, #428] ; 8000fa8 + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 8000dfe: 9301 str r3, [sp, #4] + for(position = 0U; position < GPIO_NUMBER; position++) + 8000e00: 2300 movs r3, #0 + ioposition = 0x01U << position; + 8000e02: f04f 0e01 mov.w lr, #1 + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 8000e06: 9c01 ldr r4, [sp, #4] + ioposition = 0x01U << position; + 8000e08: fa0e fe03 lsl.w lr, lr, r3 + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 8000e0c: ea0e 0604 and.w r6, lr, r4 + if(iocurrent == ioposition) + 8000e10: 45b6 cmp lr, r6 + 8000e12: f040 80ae bne.w 8000f72 + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 8000e16: 684c ldr r4, [r1, #4] + 8000e18: f024 0710 bic.w r7, r4, #16 + 8000e1c: 2f02 cmp r7, #2 + 8000e1e: d116 bne.n 8000e4e + temp = GPIOx->AFR[position >> 3U]; + 8000e20: ea4f 0ad3 mov.w sl, r3, lsr #3 + 8000e24: eb00 0a8a add.w sl, r0, sl, lsl #2 + temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + 8000e28: f003 0b07 and.w fp, r3, #7 + temp = GPIOx->AFR[position >> 3U]; + 8000e2c: f8da 5020 ldr.w r5, [sl, #32] + temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + 8000e30: ea4f 0b8b mov.w fp, fp, lsl #2 + 8000e34: f04f 0c0f mov.w ip, #15 + 8000e38: fa0c fc0b lsl.w ip, ip, fp + 8000e3c: ea25 0c0c bic.w ip, r5, ip + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); + 8000e40: 690d ldr r5, [r1, #16] + 8000e42: fa05 f50b lsl.w r5, r5, fp + 8000e46: ea45 050c orr.w r5, r5, ip + GPIOx->AFR[position >> 3U] = temp; + 8000e4a: f8ca 5020 str.w r5, [sl, #32] + 8000e4e: ea4f 0a43 mov.w sl, r3, lsl #1 + temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); + 8000e52: 2503 movs r5, #3 + temp = GPIOx->MODER; + 8000e54: f8d0 b000 ldr.w fp, [r0] + temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); + 8000e58: fa05 f50a lsl.w r5, r5, sl + 8000e5c: 43ed mvns r5, r5 + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 8000e5e: f004 0c03 and.w ip, r4, #3 + temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); + 8000e62: ea0b 0b05 and.w fp, fp, r5 + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 8000e66: fa0c fc0a lsl.w ip, ip, sl + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 8000e6a: 3f01 subs r7, #1 + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 8000e6c: ea4c 0c0b orr.w ip, ip, fp + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 8000e70: 2f01 cmp r7, #1 + GPIOx->MODER = temp; + 8000e72: f8c0 c000 str.w ip, [r0] + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 8000e76: d811 bhi.n 8000e9c + temp = GPIOx->OSPEEDR; + 8000e78: 6887 ldr r7, [r0, #8] + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + 8000e7a: ea07 0b05 and.w fp, r7, r5 + temp |= (GPIO_Init->Speed << (position * 2U)); + 8000e7e: 68cf ldr r7, [r1, #12] + 8000e80: fa07 fc0a lsl.w ip, r7, sl + 8000e84: ea4c 070b orr.w r7, ip, fp + GPIOx->OSPEEDR = temp; + 8000e88: 6087 str r7, [r0, #8] + temp = GPIOx->OTYPER; + 8000e8a: 6847 ldr r7, [r0, #4] + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 8000e8c: ea27 0e0e bic.w lr, r7, lr + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + 8000e90: f3c4 1700 ubfx r7, r4, #4, #1 + 8000e94: 409f lsls r7, r3 + 8000e96: ea47 070e orr.w r7, r7, lr + GPIOx->OTYPER = temp; + 8000e9a: 6047 str r7, [r0, #4] + temp = GPIOx->PUPDR; + 8000e9c: 68c7 ldr r7, [r0, #12] + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); + 8000e9e: 403d ands r5, r7 + temp |= ((GPIO_Init->Pull) << (position * 2U)); + 8000ea0: 688f ldr r7, [r1, #8] + 8000ea2: fa07 f70a lsl.w r7, r7, sl + 8000ea6: 433d orrs r5, r7 + GPIOx->PUPDR = temp; + 8000ea8: 60c5 str r5, [r0, #12] + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + 8000eaa: 00e5 lsls r5, r4, #3 + 8000eac: d561 bpl.n 8000f72 + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000eae: f04f 0b00 mov.w fp, #0 + 8000eb2: f8cd b00c str.w fp, [sp, #12] + 8000eb6: f8d8 7044 ldr.w r7, [r8, #68] ; 0x44 + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + 8000eba: 4d39 ldr r5, [pc, #228] ; (8000fa0 ) + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000ebc: f447 4780 orr.w r7, r7, #16384 ; 0x4000 + 8000ec0: f8c8 7044 str.w r7, [r8, #68] ; 0x44 + 8000ec4: f8d8 7044 ldr.w r7, [r8, #68] ; 0x44 + 8000ec8: f407 4780 and.w r7, r7, #16384 ; 0x4000 + 8000ecc: 9703 str r7, [sp, #12] + 8000ece: 9f03 ldr r7, [sp, #12] + 8000ed0: f023 0703 bic.w r7, r3, #3 + 8000ed4: f107 4780 add.w r7, r7, #1073741824 ; 0x40000000 + 8000ed8: f507 379c add.w r7, r7, #79872 ; 0x13800 + temp &= ~(0x0FU << (4U * (position & 0x03U))); + 8000edc: f003 0c03 and.w ip, r3, #3 + temp = SYSCFG->EXTICR[position >> 2U]; + 8000ee0: f8d7 a008 ldr.w sl, [r7, #8] + temp &= ~(0x0FU << (4U * (position & 0x03U))); + 8000ee4: ea4f 0c8c mov.w ip, ip, lsl #2 + 8000ee8: f04f 0e0f mov.w lr, #15 + 8000eec: fa0e fe0c lsl.w lr, lr, ip + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + 8000ef0: 42a8 cmp r0, r5 + temp &= ~(0x0FU << (4U * (position & 0x03U))); + 8000ef2: ea2a 0e0e bic.w lr, sl, lr + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + 8000ef6: d043 beq.n 8000f80 + 8000ef8: f505 6580 add.w r5, r5, #1024 ; 0x400 + 8000efc: 42a8 cmp r0, r5 + 8000efe: d041 beq.n 8000f84 + 8000f00: f505 6580 add.w r5, r5, #1024 ; 0x400 + 8000f04: 42a8 cmp r0, r5 + 8000f06: d03f beq.n 8000f88 + 8000f08: f505 6580 add.w r5, r5, #1024 ; 0x400 + 8000f0c: 42a8 cmp r0, r5 + 8000f0e: d03d beq.n 8000f8c + 8000f10: f505 6580 add.w r5, r5, #1024 ; 0x400 + 8000f14: 42a8 cmp r0, r5 + 8000f16: d03b beq.n 8000f90 + 8000f18: 4548 cmp r0, r9 + 8000f1a: d03b beq.n 8000f94 + 8000f1c: f505 6500 add.w r5, r5, #2048 ; 0x800 + 8000f20: 42a8 cmp r0, r5 + 8000f22: d039 beq.n 8000f98 + 8000f24: f505 6580 add.w r5, r5, #1024 ; 0x400 + 8000f28: 42a8 cmp r0, r5 + 8000f2a: bf14 ite ne + 8000f2c: 2508 movne r5, #8 + 8000f2e: 2507 moveq r5, #7 + 8000f30: fa05 f50c lsl.w r5, r5, ip + 8000f34: ea45 050e orr.w r5, r5, lr + SYSCFG->EXTICR[position >> 2U] = temp; + 8000f38: 60bd str r5, [r7, #8] + temp = EXTI->IMR; + 8000f3a: 6815 ldr r5, [r2, #0] + temp &= ~((uint32_t)iocurrent); + 8000f3c: 43f7 mvns r7, r6 + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + 8000f3e: f414 3f80 tst.w r4, #65536 ; 0x10000 + temp &= ~((uint32_t)iocurrent); + 8000f42: bf0c ite eq + 8000f44: 403d andeq r5, r7 + { + temp |= iocurrent; + 8000f46: 4335 orrne r5, r6 + } + EXTI->IMR = temp; + 8000f48: 6015 str r5, [r2, #0] + + temp = EXTI->EMR; + 8000f4a: 6855 ldr r5, [r2, #4] + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 8000f4c: f414 3f00 tst.w r4, #131072 ; 0x20000 + temp &= ~((uint32_t)iocurrent); + 8000f50: bf0c ite eq + 8000f52: 403d andeq r5, r7 + { + temp |= iocurrent; + 8000f54: 4335 orrne r5, r6 + } + EXTI->EMR = temp; + 8000f56: 6055 str r5, [r2, #4] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 8000f58: 6895 ldr r5, [r2, #8] + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 8000f5a: f414 1f80 tst.w r4, #1048576 ; 0x100000 + temp &= ~((uint32_t)iocurrent); + 8000f5e: bf0c ite eq + 8000f60: 403d andeq r5, r7 + { + temp |= iocurrent; + 8000f62: 4335 orrne r5, r6 + } + EXTI->RTSR = temp; + 8000f64: 6095 str r5, [r2, #8] + + temp = EXTI->FTSR; + 8000f66: 68d5 ldr r5, [r2, #12] + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 8000f68: 02a4 lsls r4, r4, #10 + temp &= ~((uint32_t)iocurrent); + 8000f6a: bf54 ite pl + 8000f6c: 403d andpl r5, r7 + { + temp |= iocurrent; + 8000f6e: 4335 orrmi r5, r6 + } + EXTI->FTSR = temp; + 8000f70: 60d5 str r5, [r2, #12] + for(position = 0U; position < GPIO_NUMBER; position++) + 8000f72: 3301 adds r3, #1 + 8000f74: 2b10 cmp r3, #16 + 8000f76: f47f af44 bne.w 8000e02 + } + } + } +} + 8000f7a: b005 add sp, #20 + 8000f7c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + 8000f80: 465d mov r5, fp + 8000f82: e7d5 b.n 8000f30 + 8000f84: 2501 movs r5, #1 + 8000f86: e7d3 b.n 8000f30 + 8000f88: 2502 movs r5, #2 + 8000f8a: e7d1 b.n 8000f30 + 8000f8c: 2503 movs r5, #3 + 8000f8e: e7cf b.n 8000f30 + 8000f90: 2504 movs r5, #4 + 8000f92: e7cd b.n 8000f30 + 8000f94: 2505 movs r5, #5 + 8000f96: e7cb b.n 8000f30 + 8000f98: 2506 movs r5, #6 + 8000f9a: e7c9 b.n 8000f30 + 8000f9c: 40013c00 .word 0x40013c00 + 8000fa0: 40020000 .word 0x40020000 + 8000fa4: 40023800 .word 0x40023800 + 8000fa8: 40021400 .word 0x40021400 + +08000fac : + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + 8000fac: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + /* Configure the External Interrupt or event for the current IO */ + tmp = 0x0FU << (4U * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2U] &= ~tmp; + + /* Clear EXTI line configuration */ + EXTI->IMR &= ~((uint32_t)iocurrent); + 8000fb0: 4e46 ldr r6, [pc, #280] ; (80010cc ) + if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)))) + 8000fb2: f8df a120 ldr.w sl, [pc, #288] ; 80010d4 + 8000fb6: f8df b120 ldr.w fp, [pc, #288] ; 80010d8 + for(position = 0U; position < GPIO_NUMBER; position++) + 8000fba: 2400 movs r4, #0 + ioposition = 0x01U << position; + 8000fbc: f04f 0901 mov.w r9, #1 + 8000fc0: fa09 f204 lsl.w r2, r9, r4 + if(iocurrent == ioposition) + 8000fc4: ea32 0301 bics.w r3, r2, r1 + 8000fc8: d16c bne.n 80010a4 + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U)); + 8000fca: 2303 movs r3, #3 + 8000fcc: fa04 f509 lsl.w r5, r4, r9 + 8000fd0: 6807 ldr r7, [r0, #0] + 8000fd2: fa03 f505 lsl.w r5, r3, r5 + 8000fd6: 43ed mvns r5, r5 + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + 8000fd8: fa24 fc03 lsr.w ip, r4, r3 + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U)); + 8000fdc: 402f ands r7, r5 + 8000fde: eb00 0c8c add.w ip, r0, ip, lsl #2 + 8000fe2: 6007 str r7, [r0, #0] + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + 8000fe4: f004 0e07 and.w lr, r4, #7 + 8000fe8: f8dc 8020 ldr.w r8, [ip, #32] + 8000fec: 270f movs r7, #15 + 8000fee: ea4f 0e8e mov.w lr, lr, lsl #2 + 8000ff2: fa07 fe0e lsl.w lr, r7, lr + 8000ff6: ea28 0e0e bic.w lr, r8, lr + 8000ffa: f8cc e020 str.w lr, [ip, #32] + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + 8000ffe: f8d0 e008 ldr.w lr, [r0, #8] + 8001002: ea05 0e0e and.w lr, r5, lr + 8001006: f8c0 e008 str.w lr, [r0, #8] + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + 800100a: f8d0 e004 ldr.w lr, [r0, #4] + 800100e: 43d2 mvns r2, r2 + 8001010: ea02 0e0e and.w lr, r2, lr + 8001014: f8c0 e004 str.w lr, [r0, #4] + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); + 8001018: f8d0 e00c ldr.w lr, [r0, #12] + 800101c: ea05 050e and.w r5, r5, lr + 8001020: 60c5 str r5, [r0, #12] + 8001022: f024 0503 bic.w r5, r4, #3 + 8001026: f105 4580 add.w r5, r5, #1073741824 ; 0x40000000 + 800102a: f505 359c add.w r5, r5, #79872 ; 0x13800 + tmp &= (0x0FU << (4U * (position & 0x03U))); + 800102e: ea04 0e03 and.w lr, r4, r3 + if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)))) + 8001032: 4b27 ldr r3, [pc, #156] ; (80010d0 ) + tmp = SYSCFG->EXTICR[position >> 2U]; + 8001034: f8d5 c008 ldr.w ip, [r5, #8] + tmp &= (0x0FU << (4U * (position & 0x03U))); + 8001038: ea4f 0e8e mov.w lr, lr, lsl #2 + 800103c: fa07 f70e lsl.w r7, r7, lr + if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)))) + 8001040: 4298 cmp r0, r3 + tmp &= (0x0FU << (4U * (position & 0x03U))); + 8001042: ea0c 0c07 and.w ip, ip, r7 + if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)))) + 8001046: d032 beq.n 80010ae + 8001048: f503 6380 add.w r3, r3, #1024 ; 0x400 + 800104c: 4298 cmp r0, r3 + 800104e: d030 beq.n 80010b2 + 8001050: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8001054: 4298 cmp r0, r3 + 8001056: d02e beq.n 80010b6 + 8001058: f503 6380 add.w r3, r3, #1024 ; 0x400 + 800105c: 4298 cmp r0, r3 + 800105e: d02c beq.n 80010ba + 8001060: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8001064: 4298 cmp r0, r3 + 8001066: d02a beq.n 80010be + 8001068: f503 6380 add.w r3, r3, #1024 ; 0x400 + 800106c: 4298 cmp r0, r3 + 800106e: d028 beq.n 80010c2 + 8001070: 4550 cmp r0, sl + 8001072: d028 beq.n 80010c6 + 8001074: 4558 cmp r0, fp + 8001076: bf0c ite eq + 8001078: 2307 moveq r3, #7 + 800107a: 2308 movne r3, #8 + 800107c: fa03 f30e lsl.w r3, r3, lr + 8001080: 459c cmp ip, r3 + 8001082: d10f bne.n 80010a4 + SYSCFG->EXTICR[position >> 2U] &= ~tmp; + 8001084: 68ab ldr r3, [r5, #8] + 8001086: ea23 0707 bic.w r7, r3, r7 + 800108a: 60af str r7, [r5, #8] + EXTI->IMR &= ~((uint32_t)iocurrent); + 800108c: 6833 ldr r3, [r6, #0] + 800108e: 4013 ands r3, r2 + 8001090: 6033 str r3, [r6, #0] + EXTI->EMR &= ~((uint32_t)iocurrent); + 8001092: 6873 ldr r3, [r6, #4] + 8001094: 4013 ands r3, r2 + 8001096: 6073 str r3, [r6, #4] + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~((uint32_t)iocurrent); + 8001098: 68b3 ldr r3, [r6, #8] + 800109a: 4013 ands r3, r2 + 800109c: 60b3 str r3, [r6, #8] + EXTI->FTSR &= ~((uint32_t)iocurrent); + 800109e: 68f3 ldr r3, [r6, #12] + 80010a0: 401a ands r2, r3 + 80010a2: 60f2 str r2, [r6, #12] + for(position = 0U; position < GPIO_NUMBER; position++) + 80010a4: 3401 adds r4, #1 + 80010a6: 2c10 cmp r4, #16 + 80010a8: d188 bne.n 8000fbc + } + } + } +} + 80010aa: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)))) + 80010ae: 2300 movs r3, #0 + 80010b0: e7e4 b.n 800107c + 80010b2: 464b mov r3, r9 + 80010b4: e7e2 b.n 800107c + 80010b6: 2302 movs r3, #2 + 80010b8: e7e0 b.n 800107c + 80010ba: 2303 movs r3, #3 + 80010bc: e7de b.n 800107c + 80010be: 2304 movs r3, #4 + 80010c0: e7dc b.n 800107c + 80010c2: 2305 movs r3, #5 + 80010c4: e7da b.n 800107c + 80010c6: 2306 movs r3, #6 + 80010c8: e7d8 b.n 800107c + 80010ca: bf00 nop + 80010cc: 40013c00 .word 0x40013c00 + 80010d0: 40020000 .word 0x40020000 + 80010d4: 40021800 .word 0x40021800 + 80010d8: 40021c00 .word 0x40021c00 + +080010dc : +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + 80010dc: b10a cbz r2, 80010e2 + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; + 80010de: 6181 str r1, [r0, #24] + 80010e0: 4770 bx lr + 80010e2: 0409 lsls r1, r1, #16 + 80010e4: e7fb b.n 80010de + ... + +080010e8 : + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + 80010e8: b570 push {r4, r5, r6, lr} + uint32_t freqrange = 0U; + uint32_t pclk1 = 0U; + + /* Check the I2C handle allocation */ + if(hi2c == NULL) + 80010ea: 4604 mov r4, r0 + 80010ec: 2800 cmp r0, #0 + 80010ee: d062 beq.n 80011b6 + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if(hi2c->State == HAL_I2C_STATE_RESET) + 80010f0: f890 303d ldrb.w r3, [r0, #61] ; 0x3d + 80010f4: f003 02ff and.w r2, r3, #255 ; 0xff + 80010f8: b91b cbnz r3, 8001102 + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + 80010fa: f880 203c strb.w r2, [r0, #60] ; 0x3c + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_I2C_MspInit(hi2c); + 80010fe: f004 fd3d bl 8005b7c + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 8001102: 6822 ldr r2, [r4, #0] + /* Configure I2Cx: Frequency range */ + hi2c->Instance->CR2 = freqrange; + + /*---------------------------- I2Cx TRISE Configuration --------------------*/ + /* Configure I2Cx: Rise Time */ + hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed); + 8001104: 4e2d ldr r6, [pc, #180] ; (80011bc ) + freqrange = I2C_FREQRANGE(pclk1); + 8001106: 4d2e ldr r5, [pc, #184] ; (80011c0 ) + hi2c->State = HAL_I2C_STATE_BUSY; + 8001108: 2324 movs r3, #36 ; 0x24 + 800110a: f884 303d strb.w r3, [r4, #61] ; 0x3d + __HAL_I2C_DISABLE(hi2c); + 800110e: 6813 ldr r3, [r2, #0] + 8001110: f023 0301 bic.w r3, r3, #1 + 8001114: 6013 str r3, [r2, #0] + pclk1 = HAL_RCC_GetPCLK1Freq(); + 8001116: f001 f93f bl 8002398 + hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed); + 800111a: 6863 ldr r3, [r4, #4] + hi2c->Instance->CR2 = freqrange; + 800111c: 6822 ldr r2, [r4, #0] + freqrange = I2C_FREQRANGE(pclk1); + 800111e: fbb0 f5f5 udiv r5, r0, r5 + hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed); + 8001122: 42b3 cmp r3, r6 + 8001124: bf84 itt hi + 8001126: f44f 7196 movhi.w r1, #300 ; 0x12c + 800112a: 4369 mulhi r1, r5 + hi2c->Instance->CR2 = freqrange; + 800112c: 6055 str r5, [r2, #4] + hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed); + 800112e: bf91 iteee ls + 8001130: 1c69 addls r1, r5, #1 + 8001132: f44f 757a movhi.w r5, #1000 ; 0x3e8 + 8001136: fbb1 f1f5 udivhi r1, r1, r5 + 800113a: 3101 addhi r1, #1 + + /*---------------------------- I2Cx CCR Configuration ----------------------*/ + /* Configure I2Cx: Speed */ + hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle); + 800113c: 42b3 cmp r3, r6 + hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed); + 800113e: 6211 str r1, [r2, #32] + hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle); + 8001140: d821 bhi.n 8001186 + 8001142: 005b lsls r3, r3, #1 + 8001144: fbb0 f0f3 udiv r0, r0, r3 + 8001148: f3c0 030b ubfx r3, r0, #0, #12 + 800114c: 2b03 cmp r3, #3 + 800114e: bf98 it ls + 8001150: 2004 movls r0, #4 + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + 8001152: 6a21 ldr r1, [r4, #32] + 8001154: 69e3 ldr r3, [r4, #28] + hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle); + 8001156: 61d0 str r0, [r2, #28] + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + 8001158: 430b orrs r3, r1 + 800115a: 6013 str r3, [r2, #0] + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Configure I2Cx: Own Address1 and addressing mode */ + hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1); + 800115c: 68e1 ldr r1, [r4, #12] + 800115e: 6923 ldr r3, [r4, #16] + 8001160: 430b orrs r3, r1 + 8001162: 6093 str r3, [r2, #8] + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2); + 8001164: 69a1 ldr r1, [r4, #24] + 8001166: 6963 ldr r3, [r4, #20] + 8001168: 430b orrs r3, r1 + 800116a: 60d3 str r3, [r2, #12] + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + 800116c: 6813 ldr r3, [r2, #0] + 800116e: f043 0301 orr.w r3, r3, #1 + 8001172: 6013 str r3, [r2, #0] + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8001174: 2000 movs r0, #0 + hi2c->State = HAL_I2C_STATE_READY; + 8001176: 2320 movs r3, #32 + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8001178: 6420 str r0, [r4, #64] ; 0x40 + hi2c->State = HAL_I2C_STATE_READY; + 800117a: f884 303d strb.w r3, [r4, #61] ; 0x3d + hi2c->PreviousState = I2C_STATE_NONE; + 800117e: 6320 str r0, [r4, #48] ; 0x30 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8001180: f884 003e strb.w r0, [r4, #62] ; 0x3e + + return HAL_OK; + 8001184: bd70 pop {r4, r5, r6, pc} + hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle); + 8001186: 68a1 ldr r1, [r4, #8] + 8001188: b949 cbnz r1, 800119e + 800118a: eb03 0343 add.w r3, r3, r3, lsl #1 + 800118e: fbb0 f0f3 udiv r0, r0, r3 + 8001192: f3c0 030b ubfx r3, r0, #0, #12 + 8001196: b163 cbz r3, 80011b2 + 8001198: f440 4000 orr.w r0, r0, #32768 ; 0x8000 + 800119c: e7d9 b.n 8001152 + 800119e: 2119 movs r1, #25 + 80011a0: 434b muls r3, r1 + 80011a2: fbb0 f0f3 udiv r0, r0, r3 + 80011a6: f3c0 030b ubfx r3, r0, #0, #12 + 80011aa: b113 cbz r3, 80011b2 + 80011ac: f440 4040 orr.w r0, r0, #49152 ; 0xc000 + 80011b0: e7cf b.n 8001152 + 80011b2: 2001 movs r0, #1 + 80011b4: e7cd b.n 8001152 + return HAL_ERROR; + 80011b6: 2001 movs r0, #1 +} + 80011b8: bd70 pop {r4, r5, r6, pc} + 80011ba: bf00 nop + 80011bc: 000186a0 .word 0x000186a0 + 80011c0: 000f4240 .word 0x000f4240 + +080011c4 : + 80011c4: 4770 bx lr + +080011c6 : + 80011c6: 4770 bx lr + +080011c8 : + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ + __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) +{ + 80011c8: 4770 bx lr + ... + +080011cc : +{ + 80011cc: b570 push {r4, r5, r6, lr} + if(hi2s == NULL) + 80011ce: 4604 mov r4, r0 + 80011d0: 2800 cmp r0, #0 + 80011d2: d03f beq.n 8001254 + hi2s->State = HAL_I2S_STATE_BUSY; + 80011d4: 2502 movs r5, #2 + hi2s->IrqHandlerISR = I2S_IRQHandler; + 80011d6: 4b41 ldr r3, [pc, #260] ; (80012dc ) + hi2s->State = HAL_I2S_STATE_BUSY; + 80011d8: f880 5041 strb.w r5, [r0, #65] ; 0x41 + hi2s->IrqHandlerISR = I2S_IRQHandler; + 80011dc: 6343 str r3, [r0, #52] ; 0x34 + HAL_I2S_MspInit(hi2s); + 80011de: f004 fcf7 bl 8005bd0 + CLEAR_BIT(hi2s->Instance->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ + 80011e2: 6822 ldr r2, [r4, #0] + 80011e4: 69d3 ldr r3, [r2, #28] + 80011e6: f423 637b bic.w r3, r3, #4016 ; 0xfb0 + 80011ea: f023 030f bic.w r3, r3, #15 + 80011ee: 61d3 str r3, [r2, #28] + if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) + 80011f0: 6963 ldr r3, [r4, #20] + hi2s->Instance->I2SPR = 0x0002U; + 80011f2: 6215 str r5, [r2, #32] + if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) + 80011f4: 2b02 cmp r3, #2 + tmpreg = hi2s->Instance->I2SCFGR; + 80011f6: 69d5 ldr r5, [r2, #28] + if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) + 80011f8: d035 beq.n 8001266 + if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) + 80011fa: 68e3 ldr r3, [r4, #12] + packetlength = 16U; + 80011fc: 2b00 cmp r3, #0 + if(hi2s->Init.Standard <= I2S_STANDARD_LSB) + 80011fe: 68a3 ldr r3, [r4, #8] + packetlength = 16U; + 8001200: bf14 ite ne + 8001202: 2620 movne r6, #32 + 8001204: 2610 moveq r6, #16 + i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S); + 8001206: 2001 movs r0, #1 + if(hi2s->Init.Standard <= I2S_STANDARD_LSB) + 8001208: 2b20 cmp r3, #32 + packetlength = packetlength * 2U; + 800120a: bf98 it ls + 800120c: 0076 lslls r6, r6, #1 + i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S); + 800120e: f001 f989 bl 8002524 + if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) + 8001212: 6923 ldr r3, [r4, #16] + 8001214: 6961 ldr r1, [r4, #20] + 8001216: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 800121a: d11f bne.n 800125c + if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) + 800121c: 68e3 ldr r3, [r4, #12] + 800121e: 220a movs r2, #10 + 8001220: b1d3 cbz r3, 8001258 + tmp = (uint32_t)(((((i2sclk / (packetlength*4)) * 10) / hi2s->Init.AudioFreq)) + 5); + 8001222: 00b3 lsls r3, r6, #2 + tmp = (uint32_t)(((((i2sclk / (packetlength*8)) * 10) / hi2s->Init.AudioFreq)) + 5); + 8001224: fbb0 f3f3 udiv r3, r0, r3 + 8001228: 4353 muls r3, r2 + tmp = tmp / 10U; + 800122a: 220a movs r2, #10 + tmp = (uint32_t)(((((i2sclk / packetlength) *10 ) / hi2s->Init.AudioFreq)) + 5); + 800122c: fbb3 f3f1 udiv r3, r3, r1 + 8001230: 3305 adds r3, #5 + tmp = tmp / 10U; + 8001232: fbb3 f3f2 udiv r3, r3, r2 + i2sdiv = (uint16_t)((tmp - i2sodd) / 2U); + 8001236: f003 0201 and.w r2, r3, #1 + i2sodd = (uint32_t) (i2sodd << 8U); + 800123a: 0212 lsls r2, r2, #8 + 800123c: f3c3 034f ubfx r3, r3, #1, #16 + if((i2sdiv < 2U) || (i2sdiv > 0xFFU)) + 8001240: 1e99 subs r1, r3, #2 + 8001242: 29fd cmp r1, #253 ; 0xfd + 8001244: d911 bls.n 800126a + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER); + 8001246: 6c63 ldr r3, [r4, #68] ; 0x44 + 8001248: f043 0310 orr.w r3, r3, #16 + 800124c: 6463 str r3, [r4, #68] ; 0x44 + HAL_I2S_ErrorCallback(hi2s); + 800124e: 4620 mov r0, r4 + 8001250: f7ff ffba bl 80011c8 + return HAL_ERROR; + 8001254: 2001 movs r0, #1 +} + 8001256: bd70 pop {r4, r5, r6, pc} + tmp = (uint32_t)(((((i2sclk / (packetlength*8)) * 10) / hi2s->Init.AudioFreq)) + 5); + 8001258: 00f3 lsls r3, r6, #3 + 800125a: e7e3 b.n 8001224 + tmp = (uint32_t)(((((i2sclk / packetlength) *10 ) / hi2s->Init.AudioFreq)) + 5); + 800125c: 230a movs r3, #10 + 800125e: fbb0 f0f6 udiv r0, r0, r6 + 8001262: 4343 muls r3, r0 + 8001264: e7e1 b.n 800122a + uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 16U; + 8001266: 2200 movs r2, #0 + 8001268: e7ea b.n 8001240 + hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); + 800126a: 4313 orrs r3, r2 + 800126c: 6922 ldr r2, [r4, #16] + 800126e: 6820 ldr r0, [r4, #0] + tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \ + 8001270: 6866 ldr r6, [r4, #4] + hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); + 8001272: 4313 orrs r3, r2 + 8001274: 6203 str r3, [r0, #32] + (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \ + 8001276: 68e2 ldr r2, [r4, #12] + 8001278: 68a3 ldr r3, [r4, #8] + 800127a: 4313 orrs r3, r2 + (uint16_t)hi2s->Init.CPOL)))); + 800127c: 69a2 ldr r2, [r4, #24] + (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \ + 800127e: 4313 orrs r3, r2 + 8001280: b29b uxth r3, r3 + tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \ + 8001282: f446 6100 orr.w r1, r6, #2048 ; 0x800 + 8001286: 4319 orrs r1, r3 + if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) + 8001288: 6a22 ldr r2, [r4, #32] + tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \ + 800128a: b289 uxth r1, r1 + 800128c: 430d orrs r5, r1 + if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) + 800128e: 2a01 cmp r2, #1 + WRITE_REG(hi2s->Instance->I2SCFGR, tmpreg); + 8001290: 61c5 str r5, [r0, #28] + if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) + 8001292: d11c bne.n 80012ce + hi2s->IrqHandlerISR = HAL_I2SEx_FullDuplex_IRQHandler; + 8001294: 4a12 ldr r2, [pc, #72] ; (80012e0 ) + 8001296: 6362 str r2, [r4, #52] ; 0x34 + CLEAR_BIT(I2SxEXT(hi2s->Instance)->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ + 8001298: 4912 ldr r1, [pc, #72] ; (80012e4 ) + 800129a: 4a13 ldr r2, [pc, #76] ; (80012e8 ) + 800129c: 4288 cmp r0, r1 + 800129e: bf18 it ne + 80012a0: f04f 2240 movne.w r2, #1073758208 ; 0x40004000 + tmp = I2S_MODE_SLAVE_TX; + 80012a4: f436 7000 bics.w r0, r6, #512 ; 0x200 + CLEAR_BIT(I2SxEXT(hi2s->Instance)->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ + 80012a8: 69d1 ldr r1, [r2, #28] + 80012aa: f421 617b bic.w r1, r1, #4016 ; 0xfb0 + 80012ae: f021 010f bic.w r1, r1, #15 + 80012b2: 61d1 str r1, [r2, #28] + I2SxEXT(hi2s->Instance)->I2SPR = 2U; + 80012b4: f04f 0102 mov.w r1, #2 + 80012b8: 6211 str r1, [r2, #32] + tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR; + 80012ba: 69d1 ldr r1, [r2, #28] + tmp = I2S_MODE_SLAVE_TX; + 80012bc: bf0c ite eq + 80012be: f44f 7080 moveq.w r0, #256 ; 0x100 + 80012c2: 2000 movne r0, #0 + tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ + 80012c4: f443 6300 orr.w r3, r3, #2048 ; 0x800 + 80012c8: 4303 orrs r3, r0 + 80012ca: 430b orrs r3, r1 + WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR,tmpreg); + 80012cc: 61d3 str r3, [r2, #28] + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + 80012ce: 2000 movs r0, #0 + hi2s->State = HAL_I2S_STATE_READY; + 80012d0: 2301 movs r3, #1 + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + 80012d2: 6460 str r0, [r4, #68] ; 0x44 + hi2s->State = HAL_I2S_STATE_READY; + 80012d4: f884 3041 strb.w r3, [r4, #65] ; 0x41 + return HAL_OK; + 80012d8: bd70 pop {r4, r5, r6, pc} + 80012da: bf00 nop + 80012dc: 080012ed .word 0x080012ed + 80012e0: 080013f9 .word 0x080013f9 + 80012e4: 40003800 .word 0x40003800 + 80012e8: 40003400 .word 0x40003400 + +080012ec : + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s) +{ + 80012ec: b51f push {r0, r1, r2, r3, r4, lr} + __IO uint32_t i2ssr = hi2s->Instance->SR; + 80012ee: 6803 ldr r3, [r0, #0] + 80012f0: 689a ldr r2, [r3, #8] + 80012f2: 9201 str r2, [sp, #4] + + if(hi2s->State == HAL_I2S_STATE_BUSY_RX) + 80012f4: f890 2041 ldrb.w r2, [r0, #65] ; 0x41 + 80012f8: 2a04 cmp r2, #4 +{ + 80012fa: 4604 mov r4, r0 + if(hi2s->State == HAL_I2S_STATE_BUSY_RX) + 80012fc: d13a bne.n 8001374 + { + /* I2S in mode Receiver ------------------------------------------------*/ + if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) + 80012fe: 9a01 ldr r2, [sp, #4] + 8001300: 07d1 lsls r1, r2, #31 + 8001302: d519 bpl.n 8001338 + 8001304: 685a ldr r2, [r3, #4] + 8001306: 0652 lsls r2, r2, #25 + 8001308: d516 bpl.n 8001338 + (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; + 800130a: 6ac2 ldr r2, [r0, #44] ; 0x2c + 800130c: 1c91 adds r1, r2, #2 + 800130e: 62c1 str r1, [r0, #44] ; 0x2c + 8001310: 68d9 ldr r1, [r3, #12] + 8001312: 8011 strh r1, [r2, #0] + hi2s->RxXferCount--; + 8001314: 8e42 ldrh r2, [r0, #50] ; 0x32 + 8001316: 3a01 subs r2, #1 + 8001318: b292 uxth r2, r2 + 800131a: 8642 strh r2, [r0, #50] ; 0x32 + if(hi2s->RxXferCount == 0U) + 800131c: 8e42 ldrh r2, [r0, #50] ; 0x32 + 800131e: b292 uxth r2, r2 + 8001320: b952 cbnz r2, 8001338 + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 8001322: 685a ldr r2, [r3, #4] + 8001324: f022 0260 bic.w r2, r2, #96 ; 0x60 + 8001328: 0412 lsls r2, r2, #16 + 800132a: 0c12 lsrs r2, r2, #16 + 800132c: 605a str r2, [r3, #4] + hi2s->State = HAL_I2S_STATE_READY; + 800132e: 2301 movs r3, #1 + 8001330: f880 3041 strb.w r3, [r0, #65] ; 0x41 + HAL_I2S_RxCpltCallback(hi2s); + 8001334: f7ff ff47 bl 80011c6 + { + I2S_Receive_IT(hi2s); + } + + /* I2S Overrun error interrupt occured -------------------------------------*/ + if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) + 8001338: 9b01 ldr r3, [sp, #4] + 800133a: 0659 lsls r1, r3, #25 + 800133c: d51a bpl.n 8001374 + 800133e: 6823 ldr r3, [r4, #0] + 8001340: 685a ldr r2, [r3, #4] + 8001342: 0692 lsls r2, r2, #26 + 8001344: d516 bpl.n 8001374 + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 8001346: 685a ldr r2, [r3, #4] + 8001348: f022 0260 bic.w r2, r2, #96 ; 0x60 + 800134c: 0412 lsls r2, r2, #16 + 800134e: 0c12 lsrs r2, r2, #16 + 8001350: 605a str r2, [r3, #4] + + /* Clear Overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + 8001352: 2200 movs r2, #0 + 8001354: 9202 str r2, [sp, #8] + 8001356: 68da ldr r2, [r3, #12] + 8001358: 9202 str r2, [sp, #8] + 800135a: 689b ldr r3, [r3, #8] + 800135c: 9302 str r3, [sp, #8] + 800135e: 9b02 ldr r3, [sp, #8] + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + 8001360: 2301 movs r3, #1 + 8001362: f884 3041 strb.w r3, [r4, #65] ; 0x41 + + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR); + 8001366: 6c63 ldr r3, [r4, #68] ; 0x44 + 8001368: f043 0302 orr.w r3, r3, #2 + 800136c: 6463 str r3, [r4, #68] ; 0x44 + HAL_I2S_ErrorCallback(hi2s); + 800136e: 4620 mov r0, r4 + 8001370: f7ff ff2a bl 80011c8 + } + } + + if(hi2s->State == HAL_I2S_STATE_BUSY_TX) + 8001374: f894 3041 ldrb.w r3, [r4, #65] ; 0x41 + 8001378: 2b03 cmp r3, #3 + 800137a: d13a bne.n 80013f2 + { + /* I2S in mode Transmitter -----------------------------------------------*/ + if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) + 800137c: 9b01 ldr r3, [sp, #4] + 800137e: 079b lsls r3, r3, #30 + 8001380: d51b bpl.n 80013ba + 8001382: 6822 ldr r2, [r4, #0] + 8001384: 6853 ldr r3, [r2, #4] + 8001386: 0618 lsls r0, r3, #24 + 8001388: d517 bpl.n 80013ba + hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); + 800138a: 6a63 ldr r3, [r4, #36] ; 0x24 + 800138c: 1c99 adds r1, r3, #2 + 800138e: 881b ldrh r3, [r3, #0] + 8001390: 6261 str r1, [r4, #36] ; 0x24 + 8001392: 60d3 str r3, [r2, #12] + hi2s->TxXferCount--; + 8001394: 8d63 ldrh r3, [r4, #42] ; 0x2a + 8001396: 3b01 subs r3, #1 + 8001398: b29b uxth r3, r3 + 800139a: 8563 strh r3, [r4, #42] ; 0x2a + if(hi2s->TxXferCount == 0U) + 800139c: 8d63 ldrh r3, [r4, #42] ; 0x2a + 800139e: b29b uxth r3, r3 + 80013a0: b95b cbnz r3, 80013ba + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 80013a2: 6853 ldr r3, [r2, #4] + 80013a4: f023 03a0 bic.w r3, r3, #160 ; 0xa0 + 80013a8: 041b lsls r3, r3, #16 + 80013aa: 0c1b lsrs r3, r3, #16 + 80013ac: 6053 str r3, [r2, #4] + hi2s->State = HAL_I2S_STATE_READY; + 80013ae: 2301 movs r3, #1 + 80013b0: f884 3041 strb.w r3, [r4, #65] ; 0x41 + HAL_I2S_TxCpltCallback(hi2s); + 80013b4: 4620 mov r0, r4 + 80013b6: f7ff ff05 bl 80011c4 + { + I2S_Transmit_IT(hi2s); + } + + /* I2S Underrun error interrupt occurred --------------------------------*/ + if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) + 80013ba: 9b01 ldr r3, [sp, #4] + 80013bc: 0719 lsls r1, r3, #28 + 80013be: d518 bpl.n 80013f2 + 80013c0: 6823 ldr r3, [r4, #0] + 80013c2: 685a ldr r2, [r3, #4] + 80013c4: 0692 lsls r2, r2, #26 + 80013c6: d514 bpl.n 80013f2 + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 80013c8: 685a ldr r2, [r3, #4] + 80013ca: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 80013ce: 0412 lsls r2, r2, #16 + 80013d0: 0c12 lsrs r2, r2, #16 + 80013d2: 605a str r2, [r3, #4] + + /* Clear Underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + 80013d4: 2200 movs r2, #0 + 80013d6: 9203 str r2, [sp, #12] + 80013d8: 689b ldr r3, [r3, #8] + 80013da: 9303 str r3, [sp, #12] + 80013dc: 9b03 ldr r3, [sp, #12] + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + 80013de: 2301 movs r3, #1 + 80013e0: f884 3041 strb.w r3, [r4, #65] ; 0x41 + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + 80013e4: 6c63 ldr r3, [r4, #68] ; 0x44 + 80013e6: f043 0304 orr.w r3, r3, #4 + 80013ea: 6463 str r3, [r4, #68] ; 0x44 + HAL_I2S_ErrorCallback(hi2s); + 80013ec: 4620 mov r0, r4 + 80013ee: f7ff feeb bl 80011c8 + } + } +} + 80013f2: b004 add sp, #16 + 80013f4: bd10 pop {r4, pc} + +080013f6 : + * @brief Tx and Rx Transfer completed callback + * @param hi2s I2S handle + * @retval None + */ +__weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + 80013f6: 4770 bx lr + +080013f8 : +{ + 80013f8: b51f push {r0, r1, r2, r3, r4, lr} + __IO uint32_t i2ssr = hi2s->Instance->SR ; + 80013fa: 6803 ldr r3, [r0, #0] + __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR; + 80013fc: 4992 ldr r1, [pc, #584] ; (8001648 ) + __IO uint32_t i2ssr = hi2s->Instance->SR ; + 80013fe: 689a ldr r2, [r3, #8] + 8001400: 9200 str r2, [sp, #0] + __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR; + 8001402: 4a92 ldr r2, [pc, #584] ; (800164c ) + 8001404: 428b cmp r3, r1 + 8001406: bf18 it ne + 8001408: f04f 2240 movne.w r2, #1073758208 ; 0x40004000 +{ + 800140c: 4604 mov r4, r0 + __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR; + 800140e: 6891 ldr r1, [r2, #8] + 8001410: 9101 str r1, [sp, #4] + if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) + 8001412: 69d9 ldr r1, [r3, #28] + 8001414: f401 7140 and.w r1, r1, #768 ; 0x300 + 8001418: f5b1 7f00 cmp.w r1, #512 ; 0x200 + 800141c: d004 beq.n 8001428 + || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)) + 800141e: 69d9 ldr r1, [r3, #28] + 8001420: f411 7f40 tst.w r1, #768 ; 0x300 + 8001424: f040 8097 bne.w 8001556 + if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) + 8001428: 9a00 ldr r2, [sp, #0] + 800142a: 0792 lsls r2, r2, #30 + 800142c: d51d bpl.n 800146a + 800142e: 685a ldr r2, [r3, #4] + 8001430: 0610 lsls r0, r2, #24 + 8001432: d51a bpl.n 800146a +static void I2SEx_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed) +{ + if(i2sUsed == I2S_USE_I2S) + { + /* Write Data on DR register */ + hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); + 8001434: 6a62 ldr r2, [r4, #36] ; 0x24 + 8001436: 1c91 adds r1, r2, #2 + 8001438: 8812 ldrh r2, [r2, #0] + 800143a: 6261 str r1, [r4, #36] ; 0x24 + 800143c: 60da str r2, [r3, #12] + hi2s->TxXferCount--; + 800143e: 8d62 ldrh r2, [r4, #42] ; 0x2a + 8001440: 3a01 subs r2, #1 + 8001442: b292 uxth r2, r2 + 8001444: 8562 strh r2, [r4, #42] ; 0x2a + + if(hi2s->TxXferCount == 0U) + 8001446: 8d62 ldrh r2, [r4, #42] ; 0x2a + 8001448: b292 uxth r2, r2 + 800144a: b972 cbnz r2, 800146a + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 800144c: 685a ldr r2, [r3, #4] + 800144e: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 8001452: 0412 lsls r2, r2, #16 + 8001454: 0c12 lsrs r2, r2, #16 + 8001456: 605a str r2, [r3, #4] + + if(hi2s->RxXferCount == 0U) + 8001458: 8e63 ldrh r3, [r4, #50] ; 0x32 + 800145a: b29b uxth r3, r3 + 800145c: b92b cbnz r3, 800146a + { + hi2s->State = HAL_I2S_STATE_READY; + 800145e: 2301 movs r3, #1 + 8001460: f884 3041 strb.w r3, [r4, #65] ; 0x41 + HAL_I2SEx_TxRxCpltCallback(hi2s); + 8001464: 4620 mov r0, r4 + 8001466: f7ff ffc6 bl 80013f6 + if(((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) + 800146a: 9b01 ldr r3, [sp, #4] + 800146c: 07d9 lsls r1, r3, #31 + 800146e: d522 bpl.n 80014b6 + 8001470: 4a75 ldr r2, [pc, #468] ; (8001648 ) + 8001472: 6821 ldr r1, [r4, #0] + 8001474: 4b75 ldr r3, [pc, #468] ; (800164c ) + 8001476: 4291 cmp r1, r2 + 8001478: bf18 it ne + 800147a: f04f 2340 movne.w r3, #1073758208 ; 0x40004000 + 800147e: 685a ldr r2, [r3, #4] + 8001480: 0652 lsls r2, r2, #25 + 8001482: d518 bpl.n 80014b6 + } + } + else + { + /* Read Data from DR register */ + (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR; + 8001484: 6ae2 ldr r2, [r4, #44] ; 0x2c + 8001486: 1c91 adds r1, r2, #2 + 8001488: 62e1 str r1, [r4, #44] ; 0x2c + 800148a: 68d9 ldr r1, [r3, #12] + 800148c: 8011 strh r1, [r2, #0] + hi2s->RxXferCount--; + 800148e: 8e62 ldrh r2, [r4, #50] ; 0x32 + 8001490: 3a01 subs r2, #1 + 8001492: b292 uxth r2, r2 + 8001494: 8662 strh r2, [r4, #50] ; 0x32 + + if(hi2s->RxXferCount == 0U) + 8001496: 8e62 ldrh r2, [r4, #50] ; 0x32 + 8001498: b292 uxth r2, r2 + 800149a: b962 cbnz r2, 80014b6 + { + /* Disable I2Sext RXNE and ERR interrupt */ + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 800149c: 685a ldr r2, [r3, #4] + 800149e: f022 0260 bic.w r2, r2, #96 ; 0x60 + 80014a2: 605a str r2, [r3, #4] + + if(hi2s->TxXferCount == 0U) + 80014a4: 8d63 ldrh r3, [r4, #42] ; 0x2a + 80014a6: b29b uxth r3, r3 + 80014a8: b92b cbnz r3, 80014b6 + { + hi2s->State = HAL_I2S_STATE_READY; + 80014aa: 2301 movs r3, #1 + 80014ac: f884 3041 strb.w r3, [r4, #65] ; 0x41 + HAL_I2SEx_TxRxCpltCallback(hi2s); + 80014b0: 4620 mov r0, r4 + 80014b2: f7ff ffa0 bl 80013f6 + if(((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) + 80014b6: 9b01 ldr r3, [sp, #4] + 80014b8: 0658 lsls r0, r3, #25 + 80014ba: d524 bpl.n 8001506 + 80014bc: 4962 ldr r1, [pc, #392] ; (8001648 ) + 80014be: 6823 ldr r3, [r4, #0] + 80014c0: 4a62 ldr r2, [pc, #392] ; (800164c ) + 80014c2: 428b cmp r3, r1 + 80014c4: bf18 it ne + 80014c6: f04f 2240 movne.w r2, #1073758208 ; 0x40004000 + 80014ca: 6851 ldr r1, [r2, #4] + 80014cc: 0689 lsls r1, r1, #26 + 80014ce: d51a bpl.n 8001506 + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 80014d0: 6851 ldr r1, [r2, #4] + 80014d2: f021 0160 bic.w r1, r1, #96 ; 0x60 + 80014d6: 6051 str r1, [r2, #4] + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 80014d8: 685a ldr r2, [r3, #4] + 80014da: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 80014de: 0412 lsls r2, r2, #16 + 80014e0: 0c12 lsrs r2, r2, #16 + 80014e2: 605a str r2, [r3, #4] + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + 80014e4: 2200 movs r2, #0 + 80014e6: 9202 str r2, [sp, #8] + 80014e8: 68da ldr r2, [r3, #12] + 80014ea: 9202 str r2, [sp, #8] + 80014ec: 689b ldr r3, [r3, #8] + 80014ee: 9302 str r3, [sp, #8] + 80014f0: 9b02 ldr r3, [sp, #8] + hi2s->State = HAL_I2S_STATE_READY; + 80014f2: 2301 movs r3, #1 + 80014f4: f884 3041 strb.w r3, [r4, #65] ; 0x41 + SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR); + 80014f8: 6c63 ldr r3, [r4, #68] ; 0x44 + 80014fa: f043 0302 orr.w r3, r3, #2 + 80014fe: 6463 str r3, [r4, #68] ; 0x44 + HAL_I2S_ErrorCallback(hi2s); + 8001500: 4620 mov r0, r4 + 8001502: f7ff fe61 bl 80011c8 + if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) + 8001506: 9b00 ldr r3, [sp, #0] + 8001508: 071b lsls r3, r3, #28 + 800150a: d522 bpl.n 8001552 + 800150c: 6823 ldr r3, [r4, #0] + 800150e: 685a ldr r2, [r3, #4] + 8001510: 0690 lsls r0, r2, #26 + 8001512: d51e bpl.n 8001552 + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 8001514: 685a ldr r2, [r3, #4] + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 8001516: 494c ldr r1, [pc, #304] ; (8001648 ) + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 8001518: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 800151c: 0412 lsls r2, r2, #16 + 800151e: 0c12 lsrs r2, r2, #16 + 8001520: 605a str r2, [r3, #4] + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 8001522: 4a4a ldr r2, [pc, #296] ; (800164c ) + 8001524: 428b cmp r3, r1 + 8001526: bf18 it ne + 8001528: f04f 2240 movne.w r2, #1073758208 ; 0x40004000 + 800152c: 6851 ldr r1, [r2, #4] + 800152e: f021 0160 bic.w r1, r1, #96 ; 0x60 + 8001532: 6051 str r1, [r2, #4] + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + 8001534: 2200 movs r2, #0 + 8001536: 9203 str r2, [sp, #12] + 8001538: 689b ldr r3, [r3, #8] + 800153a: 9303 str r3, [sp, #12] + 800153c: 9b03 ldr r3, [sp, #12] + hi2s->State = HAL_I2S_STATE_READY; + 800153e: 2301 movs r3, #1 + 8001540: f884 3041 strb.w r3, [r4, #65] ; 0x41 + SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR); + 8001544: 6c63 ldr r3, [r4, #68] ; 0x44 + 8001546: f043 0304 orr.w r3, r3, #4 + 800154a: 6463 str r3, [r4, #68] ; 0x44 + HAL_I2S_ErrorCallback(hi2s); + 800154c: 4620 mov r0, r4 + 800154e: f7ff fe3b bl 80011c8 +} + 8001552: b004 add sp, #16 + 8001554: bd10 pop {r4, pc} + if(((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) + 8001556: 9b01 ldr r3, [sp, #4] + 8001558: 0799 lsls r1, r3, #30 + 800155a: d51a bpl.n 8001592 + 800155c: 6853 ldr r3, [r2, #4] + 800155e: 061b lsls r3, r3, #24 + 8001560: d517 bpl.n 8001592 + I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++); + 8001562: 6a43 ldr r3, [r0, #36] ; 0x24 + 8001564: 1c99 adds r1, r3, #2 + 8001566: 881b ldrh r3, [r3, #0] + 8001568: 6241 str r1, [r0, #36] ; 0x24 + 800156a: 60d3 str r3, [r2, #12] + hi2s->TxXferCount--; + 800156c: 8d43 ldrh r3, [r0, #42] ; 0x2a + 800156e: 3b01 subs r3, #1 + 8001570: b29b uxth r3, r3 + 8001572: 8543 strh r3, [r0, #42] ; 0x2a + if(hi2s->TxXferCount == 0U) + 8001574: 8d43 ldrh r3, [r0, #42] ; 0x2a + 8001576: b29b uxth r3, r3 + 8001578: b95b cbnz r3, 8001592 + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 800157a: 6853 ldr r3, [r2, #4] + 800157c: f023 03a0 bic.w r3, r3, #160 ; 0xa0 + 8001580: 6053 str r3, [r2, #4] + if(hi2s->RxXferCount == 0U) + 8001582: 8e43 ldrh r3, [r0, #50] ; 0x32 + 8001584: b29b uxth r3, r3 + 8001586: b923 cbnz r3, 8001592 + hi2s->State = HAL_I2S_STATE_READY; + 8001588: 2301 movs r3, #1 + 800158a: f880 3041 strb.w r3, [r0, #65] ; 0x41 + HAL_I2SEx_TxRxCpltCallback(hi2s); + 800158e: f7ff ff32 bl 80013f6 + if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) + 8001592: 9b00 ldr r3, [sp, #0] + 8001594: 07d8 lsls r0, r3, #31 + 8001596: d51e bpl.n 80015d6 + 8001598: 6822 ldr r2, [r4, #0] + 800159a: 6853 ldr r3, [r2, #4] + 800159c: 0659 lsls r1, r3, #25 + 800159e: d51a bpl.n 80015d6 + (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; + 80015a0: 6ae3 ldr r3, [r4, #44] ; 0x2c + 80015a2: 1c99 adds r1, r3, #2 + 80015a4: 62e1 str r1, [r4, #44] ; 0x2c + 80015a6: 68d1 ldr r1, [r2, #12] + 80015a8: 8019 strh r1, [r3, #0] + hi2s->RxXferCount--; + 80015aa: 8e63 ldrh r3, [r4, #50] ; 0x32 + 80015ac: 3b01 subs r3, #1 + 80015ae: b29b uxth r3, r3 + 80015b0: 8663 strh r3, [r4, #50] ; 0x32 + if(hi2s->RxXferCount == 0U) + 80015b2: 8e63 ldrh r3, [r4, #50] ; 0x32 + 80015b4: b29b uxth r3, r3 + 80015b6: b973 cbnz r3, 80015d6 + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 80015b8: 6853 ldr r3, [r2, #4] + 80015ba: f023 0360 bic.w r3, r3, #96 ; 0x60 + 80015be: 041b lsls r3, r3, #16 + 80015c0: 0c1b lsrs r3, r3, #16 + 80015c2: 6053 str r3, [r2, #4] + if(hi2s->TxXferCount == 0U) + 80015c4: 8d63 ldrh r3, [r4, #42] ; 0x2a + 80015c6: b29b uxth r3, r3 + 80015c8: b92b cbnz r3, 80015d6 + hi2s->State = HAL_I2S_STATE_READY; + 80015ca: 2301 movs r3, #1 + 80015cc: f884 3041 strb.w r3, [r4, #65] ; 0x41 + HAL_I2SEx_TxRxCpltCallback(hi2s); + 80015d0: 4620 mov r0, r4 + 80015d2: f7ff ff10 bl 80013f6 + if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) + 80015d6: 9b00 ldr r3, [sp, #0] + 80015d8: 065a lsls r2, r3, #25 + 80015da: d51d bpl.n 8001618 + 80015dc: 6822 ldr r2, [r4, #0] + 80015de: 6853 ldr r3, [r2, #4] + 80015e0: 069b lsls r3, r3, #26 + 80015e2: d519 bpl.n 8001618 + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 80015e4: 6853 ldr r3, [r2, #4] + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 80015e6: 4918 ldr r1, [pc, #96] ; (8001648 ) + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 80015e8: f023 0360 bic.w r3, r3, #96 ; 0x60 + 80015ec: 041b lsls r3, r3, #16 + 80015ee: 0c1b lsrs r3, r3, #16 + 80015f0: 6053 str r3, [r2, #4] + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 80015f2: 4b16 ldr r3, [pc, #88] ; (800164c ) + 80015f4: 428a cmp r2, r1 + 80015f6: bf18 it ne + 80015f8: f04f 2340 movne.w r3, #1073758208 ; 0x40004000 + HAL_I2S_ErrorCallback(hi2s); + 80015fc: 4620 mov r0, r4 + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 80015fe: 685a ldr r2, [r3, #4] + 8001600: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 8001604: 605a str r2, [r3, #4] + hi2s->State = HAL_I2S_STATE_READY; + 8001606: 2301 movs r3, #1 + 8001608: f884 3041 strb.w r3, [r4, #65] ; 0x41 + SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR); + 800160c: 6c63 ldr r3, [r4, #68] ; 0x44 + 800160e: f043 0302 orr.w r3, r3, #2 + 8001612: 6463 str r3, [r4, #68] ; 0x44 + HAL_I2S_ErrorCallback(hi2s); + 8001614: f7ff fdd8 bl 80011c8 + if(((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) + 8001618: 9b01 ldr r3, [sp, #4] + 800161a: 0718 lsls r0, r3, #28 + 800161c: d599 bpl.n 8001552 + 800161e: 490a ldr r1, [pc, #40] ; (8001648 ) + 8001620: 6822 ldr r2, [r4, #0] + 8001622: 4b0a ldr r3, [pc, #40] ; (800164c ) + 8001624: 428a cmp r2, r1 + 8001626: bf18 it ne + 8001628: f04f 2340 movne.w r3, #1073758208 ; 0x40004000 + 800162c: 6859 ldr r1, [r3, #4] + 800162e: 0689 lsls r1, r1, #26 + 8001630: d58f bpl.n 8001552 + __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + 8001632: 6859 ldr r1, [r3, #4] + 8001634: f021 01a0 bic.w r1, r1, #160 ; 0xa0 + 8001638: 6059 str r1, [r3, #4] + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + 800163a: 6853 ldr r3, [r2, #4] + 800163c: f023 0360 bic.w r3, r3, #96 ; 0x60 + 8001640: 041b lsls r3, r3, #16 + 8001642: 0c1b lsrs r3, r3, #16 + 8001644: 6053 str r3, [r2, #4] + 8001646: e77a b.n 800153e + 8001648: 40003800 .word 0x40003800 + 800164c: 40003400 .word 0x40003400 + +08001650 : + * parameters in the PCD_InitTypeDef and initialize the associated handle. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) +{ + 8001650: b5f0 push {r4, r5, r6, r7, lr} + uint32_t i = 0U; + + /* Check the PCD handle allocation */ + if(hpcd == NULL) + 8001652: 4606 mov r6, r0 +{ + 8001654: b08b sub sp, #44 ; 0x2c + if(hpcd == NULL) + 8001656: 2800 cmp r0, #0 + 8001658: d064 beq.n 8001724 + } + + /* Check the parameters */ + assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); + + hpcd->State = HAL_PCD_STATE_BUSY; + 800165a: 2303 movs r3, #3 + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); + + /* Disable the Interrupts */ + __HAL_PCD_DISABLE(hpcd); + 800165c: 4634 mov r4, r6 + hpcd->State = HAL_PCD_STATE_BUSY; + 800165e: f880 33b9 strb.w r3, [r0, #953] ; 0x3b9 + HAL_PCD_MspInit(hpcd); + 8001662: f004 fc19 bl 8005e98 + __HAL_PCD_DISABLE(hpcd); + 8001666: f854 0b10 ldr.w r0, [r4], #16 + 800166a: f001 faa5 bl 8002bb8 + + /*Init the Core (common init.) */ + USB_CoreInit(hpcd->Instance, hpcd->Init); + 800166e: cc0f ldmia r4!, {r0, r1, r2, r3} + 8001670: 466d mov r5, sp + 8001672: c50f stmia r5!, {r0, r1, r2, r3} + 8001674: cc0f ldmia r4!, {r0, r1, r2, r3} + 8001676: c50f stmia r5!, {r0, r1, r2, r3} + 8001678: e894 0003 ldmia.w r4, {r0, r1} + 800167c: e885 0003 stmia.w r5, {r0, r1} + 8001680: 1d37 adds r7, r6, #4 + 8001682: e897 000e ldmia.w r7, {r1, r2, r3} + 8001686: 6830 ldr r0, [r6, #0] + 8001688: f001 fa56 bl 8002b38 + + /* Force Device Mode*/ + USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE); + 800168c: 2100 movs r1, #0 + 800168e: 6830 ldr r0, [r6, #0] + 8001690: f001 fa98 bl 8002bc4 + + /* Init endpoints structures */ + for (i = 0U; i < 15U; i++) + 8001694: 2100 movs r1, #0 + 8001696: 4633 mov r3, r6 + USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE); + 8001698: 4632 mov r2, r6 + 800169a: f106 0410 add.w r4, r6, #16 + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1U; + 800169e: 2501 movs r5, #1 + hpcd->IN_ep[i].num = i; + hpcd->IN_ep[i].tx_fifo_num = i; + /* Control until ep is activated */ + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + 80016a0: 4608 mov r0, r1 + hpcd->IN_ep[i].num = i; + 80016a2: f882 1038 strb.w r1, [r2, #56] ; 0x38 + hpcd->IN_ep[i].tx_fifo_num = i; + 80016a6: 87d1 strh r1, [r2, #62] ; 0x3e + for (i = 0U; i < 15U; i++) + 80016a8: 3101 adds r1, #1 + 80016aa: 290f cmp r1, #15 + hpcd->IN_ep[i].is_in = 1U; + 80016ac: f882 5039 strb.w r5, [r2, #57] ; 0x39 + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + 80016b0: f882 003b strb.w r0, [r2, #59] ; 0x3b + hpcd->IN_ep[i].maxpacket = 0U; + 80016b4: 6410 str r0, [r2, #64] ; 0x40 + hpcd->IN_ep[i].xfer_buff = 0U; + 80016b6: 6450 str r0, [r2, #68] ; 0x44 + hpcd->IN_ep[i].xfer_len = 0U; + 80016b8: 64d0 str r0, [r2, #76] ; 0x4c + 80016ba: f102 021c add.w r2, r2, #28 + for (i = 0U; i < 15U; i++) + 80016be: d1f0 bne.n 80016a2 + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; + + hpcd->Instance->DIEPTXF[i] = 0U; + 80016c0: 2200 movs r2, #0 + 80016c2: f8d6 e000 ldr.w lr, [r6] + hpcd->OUT_ep[i].is_in = 0U; + 80016c6: 4611 mov r1, r2 + hpcd->Instance->DIEPTXF[i] = 0U; + 80016c8: f102 0040 add.w r0, r2, #64 ; 0x40 + hpcd->OUT_ep[i].num = i; + 80016cc: f883 21f8 strb.w r2, [r3, #504] ; 0x1f8 + hpcd->IN_ep[i].tx_fifo_num = i; + 80016d0: 87da strh r2, [r3, #62] ; 0x3e + hpcd->Instance->DIEPTXF[i] = 0U; + 80016d2: eb0e 0080 add.w r0, lr, r0, lsl #2 + for (i = 0U; i < 15U; i++) + 80016d6: 3201 adds r2, #1 + 80016d8: 2a0f cmp r2, #15 + hpcd->OUT_ep[i].is_in = 0U; + 80016da: f883 11f9 strb.w r1, [r3, #505] ; 0x1f9 + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + 80016de: f883 11fb strb.w r1, [r3, #507] ; 0x1fb + hpcd->OUT_ep[i].maxpacket = 0U; + 80016e2: f8c3 1200 str.w r1, [r3, #512] ; 0x200 + hpcd->OUT_ep[i].xfer_buff = 0U; + 80016e6: f8c3 1204 str.w r1, [r3, #516] ; 0x204 + hpcd->OUT_ep[i].xfer_len = 0U; + 80016ea: f8c3 120c str.w r1, [r3, #524] ; 0x20c + hpcd->Instance->DIEPTXF[i] = 0U; + 80016ee: 6041 str r1, [r0, #4] + 80016f0: f103 031c add.w r3, r3, #28 + for (i = 0U; i < 15U; i++) + 80016f4: d1e8 bne.n 80016c8 + } + + /* Init Device */ + USB_DevInit(hpcd->Instance, hpcd->Init); + 80016f6: cc0f ldmia r4!, {r0, r1, r2, r3} + 80016f8: 466d mov r5, sp + 80016fa: c50f stmia r5!, {r0, r1, r2, r3} + 80016fc: cc0f ldmia r4!, {r0, r1, r2, r3} + 80016fe: c50f stmia r5!, {r0, r1, r2, r3} + 8001700: e894 0003 ldmia.w r4, {r0, r1} + 8001704: e885 0003 stmia.w r5, {r0, r1} + 8001708: 4670 mov r0, lr + 800170a: e897 000e ldmia.w r7, {r1, r2, r3} + 800170e: f001 fa71 bl 8002bf4 + + hpcd->State= HAL_PCD_STATE_READY; + 8001712: 2301 movs r3, #1 + 8001714: f886 33b9 strb.w r3, [r6, #953] ; 0x3b9 + { + HAL_PCDEx_ActivateBCD(hpcd); + } +#endif /* USB_OTG_GCCFG_BCDEN */ + + USB_DevDisconnect (hpcd->Instance); + 8001718: 6830 ldr r0, [r6, #0] + 800171a: f001 fd8e bl 800323a + return HAL_OK; + 800171e: 2000 movs r0, #0 +} + 8001720: b00b add sp, #44 ; 0x2c + 8001722: bdf0 pop {r4, r5, r6, r7, pc} + return HAL_ERROR; + 8001724: 2001 movs r0, #1 + 8001726: e7fb b.n 8001720 + +08001728 : + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + 8001728: f890 33b8 ldrb.w r3, [r0, #952] ; 0x3b8 + 800172c: 2b01 cmp r3, #1 +{ + 800172e: b510 push {r4, lr} + 8001730: 4604 mov r4, r0 + __HAL_LOCK(hpcd); + 8001732: d00c beq.n 800174e + 8001734: 2301 movs r3, #1 + 8001736: f880 33b8 strb.w r3, [r0, #952] ; 0x3b8 + USB_DevConnect (hpcd->Instance); + 800173a: 6800 ldr r0, [r0, #0] + 800173c: f001 fd71 bl 8003222 + __HAL_PCD_ENABLE(hpcd); + 8001740: 6820 ldr r0, [r4, #0] + 8001742: f001 fa33 bl 8002bac + __HAL_UNLOCK(hpcd); + 8001746: 2000 movs r0, #0 + 8001748: f884 03b8 strb.w r0, [r4, #952] ; 0x3b8 + return HAL_OK; + 800174c: bd10 pop {r4, pc} + __HAL_LOCK(hpcd); + 800174e: 2002 movs r0, #2 +} + 8001750: bd10 pop {r4, pc} + ... + +08001754 : + * @brief Handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + 8001754: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 8001758: f8d0 9000 ldr.w r9, [r0] +{ + 800175c: b087 sub sp, #28 + 800175e: 4604 mov r4, r0 + uint32_t fifoemptymsk = 0U, temp = 0U; + USB_OTG_EPTypeDef *ep; + uint32_t hclk = 180000000U; + + /* ensure that we are in device mode */ + if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) + 8001760: 4648 mov r0, r9 + 8001762: f001 fda4 bl 80032ae + 8001766: 9002 str r0, [sp, #8] + 8001768: 2800 cmp r0, #0 + 800176a: f040 812e bne.w 80019ca + { + /* avoid spurious interrupt */ + if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) + 800176e: 6820 ldr r0, [r4, #0] + 8001770: f001 fd6f bl 8003252 + 8001774: 2800 cmp r0, #0 + 8001776: f000 8128 beq.w 80019ca + { + return; + } + + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) + 800177a: 6820 ldr r0, [r4, #0] + 800177c: f001 fd69 bl 8003252 + 8001780: 0785 lsls r5, r0, #30 + { + /* incorrect mode, acknowledge the interrupt */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); + 8001782: bf48 it mi + 8001784: 6822 ldrmi r2, [r4, #0] + } + + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) + 8001786: 6820 ldr r0, [r4, #0] + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); + 8001788: bf42 ittt mi + 800178a: 6953 ldrmi r3, [r2, #20] + 800178c: f003 0302 andmi.w r3, r3, #2 + 8001790: 6153 strmi r3, [r2, #20] + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) + 8001792: f001 fd5e bl 8003252 + 8001796: f410 2500 ands.w r5, r0, #524288 ; 0x80000 + 800179a: d00a beq.n 80017b2 + { + epnum = 0U; + + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); + 800179c: 6820 ldr r0, [r4, #0] + 800179e: f001 fd5c bl 800325a + 80017a2: f509 6630 add.w r6, r9, #2816 ; 0xb00 + 80017a6: 4607 mov r7, r0 + 80017a8: 46a2 mov sl, r4 + epnum = 0U; + 80017aa: 2500 movs r5, #0 + + while ( ep_intr ) + 80017ac: 2f00 cmp r7, #0 + 80017ae: f040 810f bne.w 80019d0 + epnum++; + ep_intr >>= 1U; + } + } + + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) + 80017b2: 6820 ldr r0, [r4, #0] + 80017b4: f001 fd4d bl 8003252 + 80017b8: 0341 lsls r1, r0, #13 + 80017ba: d50b bpl.n 80017d4 + { + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); + 80017bc: 6820 ldr r0, [r4, #0] + 80017be: f001 fd54 bl 800326a + 80017c2: 4626 mov r6, r4 + 80017c4: 9003 str r0, [sp, #12] + 80017c6: f509 6810 add.w r8, r9, #2304 ; 0x900 + + epnum = 0U; + 80017ca: 2500 movs r5, #0 + + while ( ep_intr ) + 80017cc: 9b03 ldr r3, [sp, #12] + 80017ce: 2b00 cmp r3, #0 + 80017d0: f040 813f bne.w 8001a52 + ep_intr >>= 1U; + } + } + + /* Handle Resume Interrupt */ + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) + 80017d4: 6820 ldr r0, [r4, #0] + 80017d6: f001 fd3c bl 8003252 + 80017da: 2800 cmp r0, #0 + 80017dc: da0d bge.n 80017fa + { + /* Clear the Remote Wake-up Signaling */ + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + 80017de: f8d9 3804 ldr.w r3, [r9, #2052] ; 0x804 + 80017e2: f023 0301 bic.w r3, r3, #1 + 80017e6: f8c9 3804 str.w r3, [r9, #2052] ; 0x804 + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); + } + else +#endif /* USB_OTG_GLPMCFG_LPMEN */ + { + HAL_PCD_ResumeCallback(hpcd); + 80017ea: 4620 mov r0, r4 + 80017ec: f004 fbde bl 8005fac + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); + 80017f0: 6822 ldr r2, [r4, #0] + 80017f2: 6953 ldr r3, [r2, #20] + 80017f4: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 + 80017f8: 6153 str r3, [r2, #20] + } + + /* Handle Suspend Interrupt */ + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) + 80017fa: 6820 ldr r0, [r4, #0] + 80017fc: f001 fd29 bl 8003252 + 8001800: 0506 lsls r6, r0, #20 + 8001802: d50b bpl.n 800181c + { + if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + 8001804: f8d9 3808 ldr.w r3, [r9, #2056] ; 0x808 + 8001808: 07d8 lsls r0, r3, #31 + 800180a: d502 bpl.n 8001812 + { + + HAL_PCD_SuspendCallback(hpcd); + 800180c: 4620 mov r0, r4 + 800180e: f004 fbb5 bl 8005f7c + } + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); + 8001812: 6822 ldr r2, [r4, #0] + 8001814: 6953 ldr r3, [r2, #20] + 8001816: f403 6300 and.w r3, r3, #2048 ; 0x800 + 800181a: 6153 str r3, [r2, #20] + } + } +#endif /* USB_OTG_GLPMCFG_LPMEN */ + + /* Handle Reset Interrupt */ + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) + 800181c: 6820 ldr r0, [r4, #0] + 800181e: f001 fd18 bl 8003252 + 8001822: 04c1 lsls r1, r0, #19 + 8001824: d537 bpl.n 8001896 + { + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + 8001826: f509 6600 add.w r6, r9, #2048 ; 0x800 + 800182a: 6873 ldr r3, [r6, #4] + USB_FlushTxFifo(hpcd->Instance , 0x10U); + 800182c: 6820 ldr r0, [r4, #0] + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + 800182e: f023 0301 bic.w r3, r3, #1 + 8001832: 6073 str r3, [r6, #4] + USB_FlushTxFifo(hpcd->Instance , 0x10U); + 8001834: 2110 movs r1, #16 + 8001836: f001 fa79 bl 8002d2c + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + 800183a: 6861 ldr r1, [r4, #4] + 800183c: f509 6310 add.w r3, r9, #2304 ; 0x900 + { + USBx_INEP(i)->DIEPINT = 0xFFU; + 8001840: 22ff movs r2, #255 ; 0xff + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + 8001842: 9802 ldr r0, [sp, #8] + 8001844: 4288 cmp r0, r1 + 8001846: f040 8192 bne.w 8001b6e + USBx_OUTEP(i)->DOEPINT = 0xFFU; + } + USBx_DEVICE->DAINT = 0xFFFFFFFFU; + 800184a: f04f 33ff mov.w r3, #4294967295 + 800184e: 61b3 str r3, [r6, #24] + USBx_DEVICE->DAINTMSK |= 0x10001U; + 8001850: 69f3 ldr r3, [r6, #28] + 8001852: f043 1301 orr.w r3, r3, #65537 ; 0x10001 + 8001856: 61f3 str r3, [r6, #28] + + if(hpcd->Init.use_dedicated_ep1) + 8001858: 6b23 ldr r3, [r4, #48] ; 0x30 + 800185a: 2b00 cmp r3, #0 + 800185c: f000 818f beq.w 8001b7e + { + USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); + 8001860: f8d6 3084 ldr.w r3, [r6, #132] ; 0x84 + 8001864: f043 030b orr.w r3, r3, #11 + 8001868: f8c6 3084 str.w r3, [r6, #132] ; 0x84 + USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); + 800186c: 6c73 ldr r3, [r6, #68] ; 0x44 + 800186e: f043 030b orr.w r3, r3, #11 + 8001872: 6473 str r3, [r6, #68] ; 0x44 +#endif /* USB_OTG_DOEPINT_OTEPSPR */ + USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); + } + + /* Set Default Address to 0 */ + USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; + 8001874: f8d9 3800 ldr.w r3, [r9, #2048] ; 0x800 + + /* setup EP0 to receive SETUP packets */ + USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + 8001878: 7c21 ldrb r1, [r4, #16] + 800187a: 6820 ldr r0, [r4, #0] + USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; + 800187c: f423 63fe bic.w r3, r3, #2032 ; 0x7f0 + 8001880: f8c9 3800 str.w r3, [r9, #2048] ; 0x800 + USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + 8001884: f504 726f add.w r2, r4, #956 ; 0x3bc + 8001888: f001 fd30 bl 80032ec + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); + 800188c: 6822 ldr r2, [r4, #0] + 800188e: 6953 ldr r3, [r2, #20] + 8001890: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8001894: 6153 str r3, [r2, #20] + } + + /* Handle Enumeration done Interrupt */ + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) + 8001896: 6820 ldr r0, [r4, #0] + 8001898: f001 fcdb bl 8003252 + 800189c: 0482 lsls r2, r0, #18 + 800189e: d51d bpl.n 80018dc + { + USB_ActivateSetup(hpcd->Instance); + 80018a0: 6820 ldr r0, [r4, #0] + 80018a2: f001 fd08 bl 80032b6 + hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + 80018a6: 6820 ldr r0, [r4, #0] + 80018a8: 68c3 ldr r3, [r0, #12] + 80018aa: f423 5370 bic.w r3, r3, #15360 ; 0x3c00 + 80018ae: 60c3 str r3, [r0, #12] + + if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH) + 80018b0: f001 fa65 bl 8002d7e + 80018b4: 2800 cmp r0, #0 + 80018b6: f040 816b bne.w 8001b90 + { + hpcd->Init.speed = USB_OTG_SPEED_HIGH; + hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ; + hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT); + 80018ba: 6822 ldr r2, [r4, #0] + hpcd->Init.speed = USB_OTG_SPEED_HIGH; + 80018bc: 60e0 str r0, [r4, #12] + hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ; + 80018be: f44f 7300 mov.w r3, #512 ; 0x200 + 80018c2: 6163 str r3, [r4, #20] + hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT); + 80018c4: 68d3 ldr r3, [r2, #12] + 80018c6: f443 5310 orr.w r3, r3, #9216 ; 0x2400 + 80018ca: 60d3 str r3, [r2, #12] + /* hclk Clock Range between 32-180 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0x6U << 10U) & USB_OTG_GUSBCFG_TRDT); + } + } + + HAL_PCD_ResetCallback(hpcd); + 80018cc: 4620 mov r0, r4 + 80018ce: f004 fb44 bl 8005f5a + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); + 80018d2: 6822 ldr r2, [r4, #0] + 80018d4: 6953 ldr r3, [r2, #20] + 80018d6: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 80018da: 6153 str r3, [r2, #20] + } + + /* Handle RxQLevel Interrupt */ + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + 80018dc: 6820 ldr r0, [r4, #0] + 80018de: f001 fcb8 bl 8003252 + 80018e2: 06c3 lsls r3, r0, #27 + 80018e4: d52b bpl.n 800193e + { + USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + 80018e6: 6822 ldr r2, [r4, #0] + 80018e8: 6993 ldr r3, [r2, #24] + 80018ea: f023 0310 bic.w r3, r3, #16 + 80018ee: 6193 str r3, [r2, #24] + + temp = USBx->GRXSTSP; + 80018f0: f8d9 6020 ldr.w r6, [r9, #32] + + ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; + + if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_DATA_UPDT) + 80018f4: f3c6 4343 ubfx r3, r6, #17, #4 + 80018f8: 2b02 cmp r3, #2 + ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; + 80018fa: f006 080f and.w r8, r6, #15 + if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_DATA_UPDT) + 80018fe: f040 81a8 bne.w 8001c52 + { + if((temp & USB_OTG_GRXSTSP_BCNT) != 0U) + 8001902: f647 73f0 movw r3, #32752 ; 0x7ff0 + 8001906: 421e tst r6, r3 + 8001908: d014 beq.n 8001934 + { + USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4U); + 800190a: 271c movs r7, #28 + 800190c: fb07 4708 mla r7, r7, r8, r4 + 8001910: f3c6 160a ubfx r6, r6, #4, #11 + 8001914: 4632 mov r2, r6 + 8001916: f8d7 1204 ldr.w r1, [r7, #516] ; 0x204 + 800191a: 4648 mov r0, r9 + 800191c: f001 fc2b bl 8003176 + ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U; + 8001920: f8d7 3204 ldr.w r3, [r7, #516] ; 0x204 + 8001924: 4433 add r3, r6 + 8001926: f8c7 3204 str.w r3, [r7, #516] ; 0x204 + } + } + else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_SETUP_UPDT) + { + USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U; + 800192a: f8d7 3210 ldr.w r3, [r7, #528] ; 0x210 + 800192e: 441e add r6, r3 + 8001930: f8c7 6210 str.w r6, [r7, #528] ; 0x210 + } + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + 8001934: 6822 ldr r2, [r4, #0] + 8001936: 6993 ldr r3, [r2, #24] + 8001938: f043 0310 orr.w r3, r3, #16 + 800193c: 6193 str r3, [r2, #24] + } + + /* Handle SOF Interrupt */ + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) + 800193e: 6820 ldr r0, [r4, #0] + 8001940: f001 fc87 bl 8003252 + 8001944: 0707 lsls r7, r0, #28 + 8001946: d507 bpl.n 8001958 + { + HAL_PCD_SOFCallback(hpcd); + 8001948: 4620 mov r0, r4 + 800194a: f004 fb02 bl 8005f52 + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); + 800194e: 6822 ldr r2, [r4, #0] + 8001950: 6953 ldr r3, [r2, #20] + 8001952: f003 0308 and.w r3, r3, #8 + 8001956: 6153 str r3, [r2, #20] + } + + /* Handle Incomplete ISO IN Interrupt */ + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) + 8001958: 6820 ldr r0, [r4, #0] + 800195a: f001 fc7a bl 8003252 + 800195e: 02c6 lsls r6, r0, #11 + 8001960: d508 bpl.n 8001974 + { + HAL_PCD_ISOINIncompleteCallback(hpcd, epnum); + 8001962: b2e9 uxtb r1, r5 + 8001964: 4620 mov r0, r4 + 8001966: f004 fb29 bl 8005fbc + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); + 800196a: 6822 ldr r2, [r4, #0] + 800196c: 6953 ldr r3, [r2, #20] + 800196e: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8001972: 6153 str r3, [r2, #20] + } + + /* Handle Incomplete ISO OUT Interrupt */ + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + 8001974: 6820 ldr r0, [r4, #0] + 8001976: f001 fc6c bl 8003252 + 800197a: 0280 lsls r0, r0, #10 + 800197c: d508 bpl.n 8001990 + { + HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum); + 800197e: b2e9 uxtb r1, r5 + 8001980: 4620 mov r0, r4 + 8001982: f004 fb17 bl 8005fb4 + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + 8001986: 6822 ldr r2, [r4, #0] + 8001988: 6953 ldr r3, [r2, #20] + 800198a: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 800198e: 6153 str r3, [r2, #20] + } + + /* Handle Connection event Interrupt */ + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) + 8001990: 6820 ldr r0, [r4, #0] + 8001992: f001 fc5e bl 8003252 + 8001996: 0041 lsls r1, r0, #1 + 8001998: d507 bpl.n 80019aa + { + HAL_PCD_ConnectCallback(hpcd); + 800199a: 4620 mov r0, r4 + 800199c: f004 fb12 bl 8005fc4 + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); + 80019a0: 6822 ldr r2, [r4, #0] + 80019a2: 6953 ldr r3, [r2, #20] + 80019a4: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 + 80019a8: 6153 str r3, [r2, #20] + } + + /* Handle Disconnection event Interrupt */ + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) + 80019aa: 6820 ldr r0, [r4, #0] + 80019ac: f001 fc51 bl 8003252 + 80019b0: 0742 lsls r2, r0, #29 + 80019b2: d50a bpl.n 80019ca + { + temp = hpcd->Instance->GOTGINT; + 80019b4: 6823 ldr r3, [r4, #0] + 80019b6: 685d ldr r5, [r3, #4] + + if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) + 80019b8: 076b lsls r3, r5, #29 + 80019ba: d502 bpl.n 80019c2 + { + HAL_PCD_DisconnectCallback(hpcd); + 80019bc: 4620 mov r0, r4 + 80019be: f004 fb05 bl 8005fcc + } + hpcd->Instance->GOTGINT |= temp; + 80019c2: 6823 ldr r3, [r4, #0] + 80019c4: 685a ldr r2, [r3, #4] + 80019c6: 4315 orrs r5, r2 + 80019c8: 605d str r5, [r3, #4] + } + } +} + 80019ca: b007 add sp, #28 + 80019cc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + if (ep_intr & 0x1U) + 80019d0: 07f8 lsls r0, r7, #31 + 80019d2: d538 bpl.n 8001a46 + epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum); + 80019d4: fa5f fb85 uxtb.w fp, r5 + 80019d8: 4659 mov r1, fp + 80019da: 6820 ldr r0, [r4, #0] + 80019dc: f001 fc4d bl 800327a + if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) + 80019e0: f010 0f01 tst.w r0, #1 + epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum); + 80019e4: 4680 mov r8, r0 + if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) + 80019e6: d021 beq.n 8001a2c + if(hpcd->Init.dma_enable == 1U) + 80019e8: 6921 ldr r1, [r4, #16] + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); + 80019ea: 2301 movs r3, #1 + if(hpcd->Init.dma_enable == 1U) + 80019ec: 4299 cmp r1, r3 + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); + 80019ee: 60b3 str r3, [r6, #8] + if(hpcd->Init.dma_enable == 1U) + 80019f0: d10c bne.n 8001a0c + hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); + 80019f2: 6931 ldr r1, [r6, #16] + 80019f4: f8da 0200 ldr.w r0, [sl, #512] ; 0x200 + 80019f8: f3c1 0112 ubfx r1, r1, #0, #19 + 80019fc: 1a41 subs r1, r0, r1 + 80019fe: f8ca 1210 str.w r1, [sl, #528] ; 0x210 + hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; + 8001a02: f8da 1204 ldr.w r1, [sl, #516] ; 0x204 + 8001a06: 4408 add r0, r1 + 8001a08: f8ca 0204 str.w r0, [sl, #516] ; 0x204 + HAL_PCD_DataOutStageCallback(hpcd, epnum); + 8001a0c: 4659 mov r1, fp + 8001a0e: 4620 mov r0, r4 + 8001a10: f004 fa8e bl 8005f30 + if(hpcd->Init.dma_enable == 1U) + 8001a14: 6921 ldr r1, [r4, #16] + 8001a16: 2901 cmp r1, #1 + 8001a18: d108 bne.n 8001a2c + if((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + 8001a1a: b93d cbnz r5, 8001a2c + 8001a1c: f8d4 220c ldr.w r2, [r4, #524] ; 0x20c + 8001a20: b922 cbnz r2, 8001a2c + USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + 8001a22: f504 726f add.w r2, r4, #956 ; 0x3bc + 8001a26: 6820 ldr r0, [r4, #0] + 8001a28: f001 fc60 bl 80032ec + if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) + 8001a2c: f018 0f08 tst.w r8, #8 + 8001a30: d004 beq.n 8001a3c + HAL_PCD_SetupStageCallback(hpcd); + 8001a32: 4620 mov r0, r4 + 8001a34: f004 fa76 bl 8005f24 + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); + 8001a38: 2308 movs r3, #8 + 8001a3a: 60b3 str r3, [r6, #8] + if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) + 8001a3c: f018 0f10 tst.w r8, #16 + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); + 8001a40: bf1c itt ne + 8001a42: 2310 movne r3, #16 + 8001a44: 60b3 strne r3, [r6, #8] + epnum++; + 8001a46: 3501 adds r5, #1 + ep_intr >>= 1U; + 8001a48: 087f lsrs r7, r7, #1 + 8001a4a: 3620 adds r6, #32 + 8001a4c: f10a 0a1c add.w sl, sl, #28 + 8001a50: e6ac b.n 80017ac + if (ep_intr & 0x1U) /* In ITR */ + 8001a52: 9b03 ldr r3, [sp, #12] + 8001a54: 07da lsls r2, r3, #31 + 8001a56: d558 bpl.n 8001b0a + epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum); + 8001a58: fa5f fb85 uxtb.w fp, r5 + 8001a5c: 4659 mov r1, fp + 8001a5e: 6820 ldr r0, [r4, #0] + 8001a60: f001 fc15 bl 800328e + if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + 8001a64: 07c3 lsls r3, r0, #31 + epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum); + 8001a66: 4607 mov r7, r0 + if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + 8001a68: d520 bpl.n 8001aac + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + 8001a6a: f8d9 3834 ldr.w r3, [r9, #2100] ; 0x834 + fifoemptymsk = 0x1U << epnum; + 8001a6e: 2101 movs r1, #1 + 8001a70: 40a9 lsls r1, r5 + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + 8001a72: ea23 0301 bic.w r3, r3, r1 + 8001a76: f8c9 3834 str.w r3, [r9, #2100] ; 0x834 + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); + 8001a7a: 2301 movs r3, #1 + 8001a7c: f8c8 3008 str.w r3, [r8, #8] + if (hpcd->Init.dma_enable == 1U) + 8001a80: 6923 ldr r3, [r4, #16] + 8001a82: 2b01 cmp r3, #1 + hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; + 8001a84: bf01 itttt eq + 8001a86: 6c73 ldreq r3, [r6, #68] ; 0x44 + 8001a88: 6c32 ldreq r2, [r6, #64] ; 0x40 + 8001a8a: 189b addeq r3, r3, r2 + 8001a8c: 6473 streq r3, [r6, #68] ; 0x44 + HAL_PCD_DataInStageCallback(hpcd, epnum); + 8001a8e: 4659 mov r1, fp + 8001a90: 4620 mov r0, r4 + 8001a92: f004 fa56 bl 8005f42 + if (hpcd->Init.dma_enable == 1U) + 8001a96: 6921 ldr r1, [r4, #16] + 8001a98: 2901 cmp r1, #1 + 8001a9a: d107 bne.n 8001aac + if((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) + 8001a9c: b935 cbnz r5, 8001aac + 8001a9e: 6ce3 ldr r3, [r4, #76] ; 0x4c + 8001aa0: b923 cbnz r3, 8001aac + USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + 8001aa2: f504 726f add.w r2, r4, #956 ; 0x3bc + 8001aa6: 6820 ldr r0, [r4, #0] + 8001aa8: f001 fc20 bl 80032ec + if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) + 8001aac: 0738 lsls r0, r7, #28 + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); + 8001aae: bf44 itt mi + 8001ab0: 2308 movmi r3, #8 + 8001ab2: f8c8 3008 strmi.w r3, [r8, #8] + if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) + 8001ab6: 06f9 lsls r1, r7, #27 + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); + 8001ab8: bf44 itt mi + 8001aba: 2310 movmi r3, #16 + 8001abc: f8c8 3008 strmi.w r3, [r8, #8] + if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) + 8001ac0: 067a lsls r2, r7, #25 + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); + 8001ac2: bf44 itt mi + 8001ac4: 2340 movmi r3, #64 ; 0x40 + 8001ac6: f8c8 3008 strmi.w r3, [r8, #8] + if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) + 8001aca: 07bb lsls r3, r7, #30 + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); + 8001acc: bf44 itt mi + 8001ace: 2302 movmi r3, #2 + 8001ad0: f8c8 3008 strmi.w r3, [r8, #8] + if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) + 8001ad4: 063f lsls r7, r7, #24 + 8001ad6: d518 bpl.n 8001b0a + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 8001ad8: 6823 ldr r3, [r4, #0] + 8001ada: 9304 str r3, [sp, #16] + int32_t len = 0U; + uint32_t len32b; + uint32_t fifoemptymsk = 0U; + + ep = &hpcd->IN_ep[epnum]; + len = ep->xfer_len - ep->xfer_count; + 8001adc: 6cf7 ldr r7, [r6, #76] ; 0x4c + 8001ade: 6d33 ldr r3, [r6, #80] ; 0x50 + 8001ae0: 1aff subs r7, r7, r3 + 8001ae2: 6c33 ldr r3, [r6, #64] ; 0x40 + 8001ae4: 429f cmp r7, r3 + 8001ae6: bf28 it cs + 8001ae8: 461f movcs r7, r3 + } + + + len32b = (len + 3U) / 4U; + + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b) && + 8001aea: 9b04 ldr r3, [sp, #16] + 8001aec: f503 6310 add.w r3, r3, #2304 ; 0x900 + len32b = (len + 3U) / 4U; + 8001af0: f107 0a03 add.w sl, r7, #3 + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b) && + 8001af4: eb03 1345 add.w r3, r3, r5, lsl #5 + len32b = (len + 3U) / 4U; + 8001af8: ea4f 0a9a mov.w sl, sl, lsr #2 + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b) && + 8001afc: 9305 str r3, [sp, #20] + 8001afe: 9b05 ldr r3, [sp, #20] + 8001b00: 699b ldr r3, [r3, #24] + 8001b02: b29b uxth r3, r3 + 8001b04: 4553 cmp r3, sl + 8001b06: d808 bhi.n 8001b1a + + ep->xfer_buff += len; + ep->xfer_count += len; + } + + if(len <= 0U) + 8001b08: b32f cbz r7, 8001b56 + ep_intr >>= 1U; + 8001b0a: 9b03 ldr r3, [sp, #12] + 8001b0c: 085b lsrs r3, r3, #1 + epnum++; + 8001b0e: 3501 adds r5, #1 + ep_intr >>= 1U; + 8001b10: 9303 str r3, [sp, #12] + 8001b12: 361c adds r6, #28 + 8001b14: f108 0820 add.w r8, r8, #32 + 8001b18: e658 b.n 80017cc + (ep->xfer_count < ep->xfer_len) && + 8001b1a: 6d32 ldr r2, [r6, #80] ; 0x50 + 8001b1c: 6cf3 ldr r3, [r6, #76] ; 0x4c + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b) && + 8001b1e: 4293 cmp r3, r2 + 8001b20: d9f2 bls.n 8001b08 + (ep->xfer_count < ep->xfer_len) && + 8001b22: 2b00 cmp r3, #0 + 8001b24: d0f0 beq.n 8001b08 + 8001b26: 6c37 ldr r7, [r6, #64] ; 0x40 + USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); + 8001b28: 9804 ldr r0, [sp, #16] + len = ep->xfer_len - ep->xfer_count; + 8001b2a: 1a9b subs r3, r3, r2 + 8001b2c: 429f cmp r7, r3 + 8001b2e: bf28 it cs + 8001b30: 461f movcs r7, r3 + USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); + 8001b32: 7c23 ldrb r3, [r4, #16] + 8001b34: 9300 str r3, [sp, #0] + 8001b36: 465a mov r2, fp + 8001b38: b2bb uxth r3, r7 + 8001b3a: 6c71 ldr r1, [r6, #68] ; 0x44 + 8001b3c: f001 fb07 bl 800314e + ep->xfer_buff += len; + 8001b40: 6c73 ldr r3, [r6, #68] ; 0x44 + 8001b42: 443b add r3, r7 + 8001b44: 6473 str r3, [r6, #68] ; 0x44 + ep->xfer_count += len; + 8001b46: 6d33 ldr r3, [r6, #80] ; 0x50 + len32b = (len + 3U) / 4U; + 8001b48: f107 0a03 add.w sl, r7, #3 + ep->xfer_count += len; + 8001b4c: 443b add r3, r7 + len32b = (len + 3U) / 4U; + 8001b4e: ea4f 0a9a mov.w sl, sl, lsr #2 + ep->xfer_count += len; + 8001b52: 6533 str r3, [r6, #80] ; 0x50 + 8001b54: e7d3 b.n 8001afe + { + fifoemptymsk = 0x1U << epnum; + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + 8001b56: 9b04 ldr r3, [sp, #16] + fifoemptymsk = 0x1U << epnum; + 8001b58: 2201 movs r2, #1 + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + 8001b5a: f503 6b00 add.w fp, r3, #2048 ; 0x800 + 8001b5e: f8d3 3834 ldr.w r3, [r3, #2100] ; 0x834 + fifoemptymsk = 0x1U << epnum; + 8001b62: 40aa lsls r2, r5 + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + 8001b64: ea23 0302 bic.w r3, r3, r2 + 8001b68: f8cb 3034 str.w r3, [fp, #52] ; 0x34 + 8001b6c: e7cd b.n 8001b0a + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + 8001b6e: 9802 ldr r0, [sp, #8] + USBx_INEP(i)->DIEPINT = 0xFFU; + 8001b70: 609a str r2, [r3, #8] + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + 8001b72: 3001 adds r0, #1 + USBx_OUTEP(i)->DOEPINT = 0xFFU; + 8001b74: f8c3 2208 str.w r2, [r3, #520] ; 0x208 + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + 8001b78: 9002 str r0, [sp, #8] + 8001b7a: 3320 adds r3, #32 + 8001b7c: e661 b.n 8001842 + USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); + 8001b7e: 6973 ldr r3, [r6, #20] + 8001b80: f043 030b orr.w r3, r3, #11 + 8001b84: 6173 str r3, [r6, #20] + USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); + 8001b86: 6933 ldr r3, [r6, #16] + 8001b88: f043 030b orr.w r3, r3, #11 + 8001b8c: 6133 str r3, [r6, #16] + 8001b8e: e671 b.n 8001874 + hpcd->Init.speed = USB_OTG_SPEED_FULL; + 8001b90: 2303 movs r3, #3 + 8001b92: 60e3 str r3, [r4, #12] + hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; + 8001b94: 2340 movs r3, #64 ; 0x40 + 8001b96: 6163 str r3, [r4, #20] + hclk = HAL_RCC_GetHCLKFreq(); + 8001b98: f000 fbf8 bl 800238c + if((hclk >= 14200000U)&&(hclk < 15000000U)) + 8001b9c: 4b34 ldr r3, [pc, #208] ; (8001c70 ) + 8001b9e: 4a35 ldr r2, [pc, #212] ; (8001c74 ) + 8001ba0: 4403 add r3, r0 + 8001ba2: 4293 cmp r3, r2 + 8001ba4: 6823 ldr r3, [r4, #0] + 8001ba6: d804 bhi.n 8001bb2 + hpcd->Instance->GUSBCFG |= (uint32_t)((0xFU << 10U) & USB_OTG_GUSBCFG_TRDT); + 8001ba8: 68da ldr r2, [r3, #12] + 8001baa: f442 5270 orr.w r2, r2, #15360 ; 0x3c00 + hpcd->Instance->GUSBCFG |= (uint32_t)((0x6U << 10U) & USB_OTG_GUSBCFG_TRDT); + 8001bae: 60da str r2, [r3, #12] + 8001bb0: e68c b.n 80018cc + else if((hclk >= 15000000U)&&(hclk < 16000000U)) + 8001bb2: 4a31 ldr r2, [pc, #196] ; (8001c78 ) + 8001bb4: 4931 ldr r1, [pc, #196] ; (8001c7c ) + 8001bb6: 4402 add r2, r0 + 8001bb8: 428a cmp r2, r1 + 8001bba: d803 bhi.n 8001bc4 + hpcd->Instance->GUSBCFG |= (uint32_t)((0xEU << 10U) & USB_OTG_GUSBCFG_TRDT); + 8001bbc: 68da ldr r2, [r3, #12] + 8001bbe: f442 5260 orr.w r2, r2, #14336 ; 0x3800 + 8001bc2: e7f4 b.n 8001bae + else if((hclk >= 16000000U)&&(hclk < 17200000U)) + 8001bc4: f5a0 0274 sub.w r2, r0, #15990784 ; 0xf40000 + 8001bc8: 492d ldr r1, [pc, #180] ; (8001c80 ) + 8001bca: f5a2 5210 sub.w r2, r2, #9216 ; 0x2400 + 8001bce: 428a cmp r2, r1 + 8001bd0: d803 bhi.n 8001bda + hpcd->Instance->GUSBCFG |= (uint32_t)((0xDU << 10U) & USB_OTG_GUSBCFG_TRDT); + 8001bd2: 68da ldr r2, [r3, #12] + 8001bd4: f442 5250 orr.w r2, r2, #13312 ; 0x3400 + 8001bd8: e7e9 b.n 8001bae + else if((hclk >= 17200000U)&&(hclk < 18500000U)) + 8001bda: f1a0 7283 sub.w r2, r0, #17170432 ; 0x1060000 + 8001bde: 4929 ldr r1, [pc, #164] ; (8001c84 ) + 8001be0: f5a2 42e7 sub.w r2, r2, #29568 ; 0x7380 + 8001be4: 428a cmp r2, r1 + 8001be6: d803 bhi.n 8001bf0 + hpcd->Instance->GUSBCFG |= (uint32_t)((0xCU << 10U) & USB_OTG_GUSBCFG_TRDT); + 8001be8: 68da ldr r2, [r3, #12] + 8001bea: f442 5240 orr.w r2, r2, #12288 ; 0x3000 + 8001bee: e7de b.n 8001bae + else if((hclk >= 18500000U)&&(hclk < 20000000U)) + 8001bf0: 4a25 ldr r2, [pc, #148] ; (8001c88 ) + 8001bf2: 4926 ldr r1, [pc, #152] ; (8001c8c ) + 8001bf4: 4402 add r2, r0 + 8001bf6: 428a cmp r2, r1 + 8001bf8: d803 bhi.n 8001c02 + hpcd->Instance->GUSBCFG |= (uint32_t)((0xBU << 10U) & USB_OTG_GUSBCFG_TRDT); + 8001bfa: 68da ldr r2, [r3, #12] + 8001bfc: f442 5230 orr.w r2, r2, #11264 ; 0x2c00 + 8001c00: e7d5 b.n 8001bae + else if((hclk >= 20000000U)&&(hclk < 21800000U)) + 8001c02: 4a23 ldr r2, [pc, #140] ; (8001c90 ) + 8001c04: 4923 ldr r1, [pc, #140] ; (8001c94 ) + 8001c06: 4402 add r2, r0 + 8001c08: 428a cmp r2, r1 + 8001c0a: d803 bhi.n 8001c14 + hpcd->Instance->GUSBCFG |= (uint32_t)((0xAU << 10U) & USB_OTG_GUSBCFG_TRDT); + 8001c0c: 68da ldr r2, [r3, #12] + 8001c0e: f442 5220 orr.w r2, r2, #10240 ; 0x2800 + 8001c12: e7cc b.n 8001bae + else if((hclk >= 21800000U)&&(hclk < 24000000U)) + 8001c14: 4a20 ldr r2, [pc, #128] ; (8001c98 ) + 8001c16: 4921 ldr r1, [pc, #132] ; (8001c9c ) + 8001c18: 4402 add r2, r0 + 8001c1a: 428a cmp r2, r1 + 8001c1c: d803 bhi.n 8001c26 + hpcd->Instance->GUSBCFG |= (uint32_t)((0x9U << 10U) & USB_OTG_GUSBCFG_TRDT); + 8001c1e: 68da ldr r2, [r3, #12] + 8001c20: f442 5210 orr.w r2, r2, #9216 ; 0x2400 + 8001c24: e7c3 b.n 8001bae + else if((hclk >= 24000000U)&&(hclk < 27700000U)) + 8001c26: f1a0 72b7 sub.w r2, r0, #23986176 ; 0x16e0000 + 8001c2a: 491d ldr r1, [pc, #116] ; (8001ca0 ) + 8001c2c: f5a2 5258 sub.w r2, r2, #13824 ; 0x3600 + 8001c30: 428a cmp r2, r1 + 8001c32: d803 bhi.n 8001c3c + hpcd->Instance->GUSBCFG |= (uint32_t)((0x8U << 10U) & USB_OTG_GUSBCFG_TRDT); + 8001c34: 68da ldr r2, [r3, #12] + 8001c36: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 8001c3a: e7b8 b.n 8001bae + else if((hclk >= 27700000U)&&(hclk < 32000000U)) + 8001c3c: 4a19 ldr r2, [pc, #100] ; (8001ca4 ) + 8001c3e: 491a ldr r1, [pc, #104] ; (8001ca8 ) + 8001c40: 4402 add r2, r0 + 8001c42: 428a cmp r2, r1 + hpcd->Instance->GUSBCFG |= (uint32_t)((0x7U << 10U) & USB_OTG_GUSBCFG_TRDT); + 8001c44: 68da ldr r2, [r3, #12] + 8001c46: bf94 ite ls + 8001c48: f442 52e0 orrls.w r2, r2, #7168 ; 0x1c00 + hpcd->Instance->GUSBCFG |= (uint32_t)((0x6U << 10U) & USB_OTG_GUSBCFG_TRDT); + 8001c4c: f442 52c0 orrhi.w r2, r2, #6144 ; 0x1800 + 8001c50: e7ad b.n 8001bae + else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_SETUP_UPDT) + 8001c52: 2b06 cmp r3, #6 + 8001c54: f47f ae6e bne.w 8001934 + USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + 8001c58: 2208 movs r2, #8 + 8001c5a: f504 716f add.w r1, r4, #956 ; 0x3bc + 8001c5e: 4648 mov r0, r9 + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U; + 8001c60: 271c movs r7, #28 + USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + 8001c62: f001 fa88 bl 8003176 + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U; + 8001c66: fb07 4708 mla r7, r7, r8, r4 + 8001c6a: f3c6 160a ubfx r6, r6, #4, #11 + 8001c6e: e65c b.n 800192a + 8001c70: ff275340 .word 0xff275340 + 8001c74: 000c34ff .word 0x000c34ff + 8001c78: ff1b1e40 .word 0xff1b1e40 + 8001c7c: 000f423f .word 0x000f423f + 8001c80: 00124f7f .word 0x00124f7f + 8001c84: 0013d61f .word 0x0013d61f + 8001c88: fee5b660 .word 0xfee5b660 + 8001c8c: 0016e35f .word 0x0016e35f + 8001c90: feced300 .word 0xfeced300 + 8001c94: 001b773f .word 0x001b773f + 8001c98: feb35bc0 .word 0xfeb35bc0 + 8001c9c: 002191bf .word 0x002191bf + 8001ca0: 0038751f .word 0x0038751f + 8001ca4: fe5954e0 .word 0xfe5954e0 + 8001ca8: 00419cdf .word 0x00419cdf + +08001cac : + __HAL_LOCK(hpcd); + 8001cac: f890 33b8 ldrb.w r3, [r0, #952] ; 0x3b8 + 8001cb0: 2b01 cmp r3, #1 +{ + 8001cb2: b510 push {r4, lr} + 8001cb4: 4604 mov r4, r0 + __HAL_LOCK(hpcd); + 8001cb6: d009 beq.n 8001ccc + 8001cb8: 2301 movs r3, #1 + 8001cba: f880 33b8 strb.w r3, [r0, #952] ; 0x3b8 + USB_SetDevAddress(hpcd->Instance, address); + 8001cbe: 6800 ldr r0, [r0, #0] + 8001cc0: f001 fa9f bl 8003202 + __HAL_UNLOCK(hpcd); + 8001cc4: 2000 movs r0, #0 + 8001cc6: f884 03b8 strb.w r0, [r4, #952] ; 0x3b8 + return HAL_OK; + 8001cca: bd10 pop {r4, pc} + __HAL_LOCK(hpcd); + 8001ccc: 2002 movs r0, #2 +} + 8001cce: bd10 pop {r4, pc} + +08001cd0 : +{ + 8001cd0: b570 push {r4, r5, r6, lr} + if ((ep_addr & 0x80) == 0x80) + 8001cd2: b24e sxtb r6, r1 + 8001cd4: 2e00 cmp r6, #0 +{ + 8001cd6: 4604 mov r4, r0 + 8001cd8: f04f 051c mov.w r5, #28 + 8001cdc: f001 007f and.w r0, r1, #127 ; 0x7f + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + 8001ce0: bfb5 itete lt + 8001ce2: fb05 4100 mlalt r1, r5, r0, r4 + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + 8001ce6: fb05 4101 mlage r1, r5, r1, r4 + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + 8001cea: 3138 addlt r1, #56 ; 0x38 + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + 8001cec: f501 71fc addge.w r1, r1, #504 ; 0x1f8 + ep->num = ep_addr & 0x7F; + 8001cf0: b2c0 uxtb r0, r0 + if (ep->is_in) + 8001cf2: 2e00 cmp r6, #0 + ep->tx_fifo_num = ep->num; + 8001cf4: bfb8 it lt + 8001cf6: 80c8 strhlt r0, [r1, #6] + if (ep_type == EP_TYPE_BULK ) + 8001cf8: 2b02 cmp r3, #2 + ep->type = ep_type; + 8001cfa: 70cb strb r3, [r1, #3] + ep->is_in = (0x80 & ep_addr) != 0; + 8001cfc: ea4f 75d6 mov.w r5, r6, lsr #31 + ep->data_pid_start = 0U; + 8001d00: bf04 itt eq + 8001d02: 2300 moveq r3, #0 + 8001d04: 710b strbeq r3, [r1, #4] + ep->num = ep_addr & 0x7F; + 8001d06: 7008 strb r0, [r1, #0] + ep->is_in = (0x80 & ep_addr) != 0; + 8001d08: 704d strb r5, [r1, #1] + __HAL_LOCK(hpcd); + 8001d0a: f894 33b8 ldrb.w r3, [r4, #952] ; 0x3b8 + ep->maxpacket = ep_mps; + 8001d0e: 608a str r2, [r1, #8] + __HAL_LOCK(hpcd); + 8001d10: 2b01 cmp r3, #1 + 8001d12: d009 beq.n 8001d28 + 8001d14: 2301 movs r3, #1 + 8001d16: f884 33b8 strb.w r3, [r4, #952] ; 0x3b8 + USB_ActivateEndpoint(hpcd->Instance , ep); + 8001d1a: 6820 ldr r0, [r4, #0] + 8001d1c: f001 f84a bl 8002db4 + __HAL_UNLOCK(hpcd); + 8001d20: 2000 movs r0, #0 + 8001d22: f884 03b8 strb.w r0, [r4, #952] ; 0x3b8 + return ret; + 8001d26: bd70 pop {r4, r5, r6, pc} + __HAL_LOCK(hpcd); + 8001d28: 2002 movs r0, #2 +} + 8001d2a: bd70 pop {r4, r5, r6, pc} + +08001d2c : + if ((ep_addr & 0x80) == 0x80) + 8001d2c: b24b sxtb r3, r1 + 8001d2e: 2b00 cmp r3, #0 +{ + 8001d30: b510 push {r4, lr} + 8001d32: f04f 021c mov.w r2, #28 + 8001d36: 4604 mov r4, r0 + 8001d38: f001 007f and.w r0, r1, #127 ; 0x7f + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + 8001d3c: bfb5 itete lt + 8001d3e: fb02 4100 mlalt r1, r2, r0, r4 + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + 8001d42: fb02 4101 mlage r1, r2, r1, r4 + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + 8001d46: 3138 addlt r1, #56 ; 0x38 + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + 8001d48: f501 71fc addge.w r1, r1, #504 ; 0x1f8 + ep->is_in = (0x80 & ep_addr) != 0; + 8001d4c: 0fdb lsrs r3, r3, #31 + ep->num = ep_addr & 0x7F; + 8001d4e: 7008 strb r0, [r1, #0] + ep->is_in = (0x80 & ep_addr) != 0; + 8001d50: 704b strb r3, [r1, #1] + __HAL_LOCK(hpcd); + 8001d52: f894 33b8 ldrb.w r3, [r4, #952] ; 0x3b8 + 8001d56: 2b01 cmp r3, #1 + 8001d58: d009 beq.n 8001d6e + 8001d5a: 2301 movs r3, #1 + 8001d5c: f884 33b8 strb.w r3, [r4, #952] ; 0x3b8 + USB_DeactivateEndpoint(hpcd->Instance , ep); + 8001d60: 6820 ldr r0, [r4, #0] + 8001d62: f001 f866 bl 8002e32 + __HAL_UNLOCK(hpcd); + 8001d66: 2000 movs r0, #0 + 8001d68: f884 03b8 strb.w r0, [r4, #952] ; 0x3b8 + return HAL_OK; + 8001d6c: bd10 pop {r4, pc} + __HAL_LOCK(hpcd); + 8001d6e: 2002 movs r0, #2 +} + 8001d70: bd10 pop {r4, pc} + +08001d72 : +{ + 8001d72: b538 push {r3, r4, r5, lr} + 8001d74: f001 057f and.w r5, r1, #127 ; 0x7f + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + 8001d78: 241c movs r4, #28 + 8001d7a: fb04 0105 mla r1, r4, r5, r0 + ep->xfer_buff = pBuf; + 8001d7e: fb04 0405 mla r4, r4, r5, r0 + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + 8001d82: f501 71fc add.w r1, r1, #504 ; 0x1f8 + ep->xfer_len = len; + 8001d86: f8c4 320c str.w r3, [r4, #524] ; 0x20c + ep->xfer_count = 0U; + 8001d8a: 2300 movs r3, #0 + ep->xfer_buff = pBuf; + 8001d8c: f8c4 2204 str.w r2, [r4, #516] ; 0x204 + ep->xfer_count = 0U; + 8001d90: f8c4 3210 str.w r3, [r4, #528] ; 0x210 + ep->is_in = 0U; + 8001d94: f884 31f9 strb.w r3, [r4, #505] ; 0x1f9 + ep->num = ep_addr & 0x7F; + 8001d98: f884 51f8 strb.w r5, [r4, #504] ; 0x1f8 + if (hpcd->Init.dma_enable == 1U) + 8001d9c: 6903 ldr r3, [r0, #16] + USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable); + 8001d9e: 6800 ldr r0, [r0, #0] + if (hpcd->Init.dma_enable == 1U) + 8001da0: 2b01 cmp r3, #1 + ep->dma_addr = (uint32_t)pBuf; + 8001da2: bf08 it eq + 8001da4: f8c4 2208 streq.w r2, [r4, #520] ; 0x208 + 8001da8: b2da uxtb r2, r3 + if ((ep_addr & 0x7F) == 0) + 8001daa: b91d cbnz r5, 8001db4 + USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable); + 8001dac: f001 f962 bl 8003074 +} + 8001db0: 2000 movs r0, #0 + 8001db2: bd38 pop {r3, r4, r5, pc} + USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable); + 8001db4: f001 f898 bl 8002ee8 + 8001db8: e7fa b.n 8001db0 + +08001dba : + return hpcd->OUT_ep[ep_addr & 0xF].xfer_count; + 8001dba: 231c movs r3, #28 + 8001dbc: f001 010f and.w r1, r1, #15 + 8001dc0: fb03 0101 mla r1, r3, r1, r0 +} + 8001dc4: f8b1 0210 ldrh.w r0, [r1, #528] ; 0x210 + 8001dc8: 4770 bx lr + +08001dca : +{ + 8001dca: b538 push {r3, r4, r5, lr} + 8001dcc: f001 057f and.w r5, r1, #127 ; 0x7f + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + 8001dd0: 241c movs r4, #28 + 8001dd2: fb04 0105 mla r1, r4, r5, r0 + ep->xfer_buff = pBuf; + 8001dd6: fb04 0405 mla r4, r4, r5, r0 + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + 8001dda: 3138 adds r1, #56 ; 0x38 + ep->xfer_len = len; + 8001ddc: 64e3 str r3, [r4, #76] ; 0x4c + ep->xfer_count = 0U; + 8001dde: 2300 movs r3, #0 + 8001de0: 6523 str r3, [r4, #80] ; 0x50 + ep->is_in = 1U; + 8001de2: 2301 movs r3, #1 + ep->xfer_buff = pBuf; + 8001de4: 6462 str r2, [r4, #68] ; 0x44 + ep->is_in = 1U; + 8001de6: f884 3039 strb.w r3, [r4, #57] ; 0x39 + ep->num = ep_addr & 0x7F; + 8001dea: f884 5038 strb.w r5, [r4, #56] ; 0x38 + if (hpcd->Init.dma_enable == 1U) + 8001dee: 6903 ldr r3, [r0, #16] + USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable); + 8001df0: 6800 ldr r0, [r0, #0] + if (hpcd->Init.dma_enable == 1U) + 8001df2: 2b01 cmp r3, #1 + ep->dma_addr = (uint32_t)pBuf; + 8001df4: bf08 it eq + 8001df6: 64a2 streq r2, [r4, #72] ; 0x48 + 8001df8: b2da uxtb r2, r3 + if ((ep_addr & 0x7F) == 0) + 8001dfa: b91d cbnz r5, 8001e04 + USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable); + 8001dfc: f001 f93a bl 8003074 +} + 8001e00: 2000 movs r0, #0 + 8001e02: bd38 pop {r3, r4, r5, pc} + USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable); + 8001e04: f001 f870 bl 8002ee8 + 8001e08: e7fa b.n 8001e00 + +08001e0a : +{ + 8001e0a: b538 push {r3, r4, r5, lr} + if ((0x80 & ep_addr) == 0x80) + 8001e0c: b24b sxtb r3, r1 + 8001e0e: 2b00 cmp r3, #0 + 8001e10: f001 057f and.w r5, r1, #127 ; 0x7f + 8001e14: f04f 021c mov.w r2, #28 + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + 8001e18: bfb5 itete lt + 8001e1a: fb02 0105 mlalt r1, r2, r5, r0 + ep = &hpcd->OUT_ep[ep_addr]; + 8001e1e: fb02 0101 mlage r1, r2, r1, r0 + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + 8001e22: 3138 addlt r1, #56 ; 0x38 + ep = &hpcd->OUT_ep[ep_addr]; + 8001e24: f501 71fc addge.w r1, r1, #504 ; 0x1f8 + ep->is_stall = 1U; + 8001e28: 2201 movs r2, #1 + ep->is_in = ((ep_addr & 0x80) == 0x80); + 8001e2a: 0fdb lsrs r3, r3, #31 + ep->num = ep_addr & 0x7F; + 8001e2c: b2ed uxtb r5, r5 + ep->is_stall = 1U; + 8001e2e: 708a strb r2, [r1, #2] + ep->num = ep_addr & 0x7F; + 8001e30: 700d strb r5, [r1, #0] + ep->is_in = ((ep_addr & 0x80) == 0x80); + 8001e32: 704b strb r3, [r1, #1] + __HAL_LOCK(hpcd); + 8001e34: f890 33b8 ldrb.w r3, [r0, #952] ; 0x3b8 + 8001e38: 4293 cmp r3, r2 +{ + 8001e3a: 4604 mov r4, r0 + __HAL_LOCK(hpcd); + 8001e3c: d00f beq.n 8001e5e + 8001e3e: f880 23b8 strb.w r2, [r0, #952] ; 0x3b8 + USB_EPSetStall(hpcd->Instance , ep); + 8001e42: 6800 ldr r0, [r0, #0] + 8001e44: f001 f9a5 bl 8003192 + if((ep_addr & 0x7F) == 0) + 8001e48: b92d cbnz r5, 8001e56 + USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + 8001e4a: f504 726f add.w r2, r4, #956 ; 0x3bc + 8001e4e: 7c21 ldrb r1, [r4, #16] + 8001e50: 6820 ldr r0, [r4, #0] + 8001e52: f001 fa4b bl 80032ec + __HAL_UNLOCK(hpcd); + 8001e56: 2000 movs r0, #0 + 8001e58: f884 03b8 strb.w r0, [r4, #952] ; 0x3b8 + return HAL_OK; + 8001e5c: bd38 pop {r3, r4, r5, pc} + __HAL_LOCK(hpcd); + 8001e5e: 2002 movs r0, #2 +} + 8001e60: bd38 pop {r3, r4, r5, pc} + +08001e62 : +{ + 8001e62: b538 push {r3, r4, r5, lr} + if ((0x80 & ep_addr) == 0x80) + 8001e64: b24b sxtb r3, r1 + 8001e66: 2b00 cmp r3, #0 +{ + 8001e68: 4605 mov r5, r0 + 8001e6a: f04f 021c mov.w r2, #28 + 8001e6e: f001 007f and.w r0, r1, #127 ; 0x7f + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + 8001e72: bfb5 itete lt + 8001e74: fb02 5100 mlalt r1, r2, r0, r5 + ep = &hpcd->OUT_ep[ep_addr]; + 8001e78: fb02 5101 mlage r1, r2, r1, r5 + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + 8001e7c: 3138 addlt r1, #56 ; 0x38 + ep = &hpcd->OUT_ep[ep_addr]; + 8001e7e: f501 71fc addge.w r1, r1, #504 ; 0x1f8 + ep->is_in = ((ep_addr & 0x80) == 0x80); + 8001e82: 0fdb lsrs r3, r3, #31 + ep->is_stall = 0U; + 8001e84: 2400 movs r4, #0 + 8001e86: 708c strb r4, [r1, #2] + ep->num = ep_addr & 0x7F; + 8001e88: 7008 strb r0, [r1, #0] + ep->is_in = ((ep_addr & 0x80) == 0x80); + 8001e8a: 704b strb r3, [r1, #1] + __HAL_LOCK(hpcd); + 8001e8c: f895 33b8 ldrb.w r3, [r5, #952] ; 0x3b8 + 8001e90: 2b01 cmp r3, #1 + 8001e92: d009 beq.n 8001ea8 + 8001e94: 2301 movs r3, #1 + 8001e96: f885 33b8 strb.w r3, [r5, #952] ; 0x3b8 + USB_EPClearStall(hpcd->Instance , ep); + 8001e9a: 6828 ldr r0, [r5, #0] + 8001e9c: f001 f998 bl 80031d0 + __HAL_UNLOCK(hpcd); + 8001ea0: f885 43b8 strb.w r4, [r5, #952] ; 0x3b8 + return HAL_OK; + 8001ea4: 4620 mov r0, r4 + 8001ea6: bd38 pop {r3, r4, r5, pc} + __HAL_LOCK(hpcd); + 8001ea8: 2002 movs r0, #2 +} + 8001eaa: bd38 pop {r3, r4, r5, pc} + +08001eac : + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + + Tx_Offset = hpcd->Instance->GRXFSIZ; + 8001eac: 6800 ldr r0, [r0, #0] +{ + 8001eae: b570 push {r4, r5, r6, lr} + Tx_Offset = hpcd->Instance->GRXFSIZ; + 8001eb0: 6a43 ldr r3, [r0, #36] ; 0x24 + + if(fifo == 0) + 8001eb2: b921 cbnz r1, 8001ebe + { + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset); + 8001eb4: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8001eb8: 6283 str r3, [r0, #40] ; 0x28 + /* Multiply Tx_Size by 2 to get higher performance */ + hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset); + } + + return HAL_OK; +} + 8001eba: 2000 movs r0, #0 + 8001ebc: bd70 pop {r4, r5, r6, pc} + Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U; + 8001ebe: 6a84 ldr r4, [r0, #40] ; 0x28 + for (i = 0; i < (fifo - 1); i++) + 8001ec0: 2500 movs r5, #0 + Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U; + 8001ec2: eb03 4314 add.w r3, r3, r4, lsr #16 + for (i = 0; i < (fifo - 1); i++) + 8001ec6: 1e4e subs r6, r1, #1 + 8001ec8: b2ec uxtb r4, r5 + 8001eca: 42b4 cmp r4, r6 + 8001ecc: f105 0501 add.w r5, r5, #1 + 8001ed0: db06 blt.n 8001ee0 + hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset); + 8001ed2: 313f adds r1, #63 ; 0x3f + 8001ed4: eb00 0081 add.w r0, r0, r1, lsl #2 + 8001ed8: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8001edc: 6043 str r3, [r0, #4] + 8001ede: e7ec b.n 8001eba + Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16U); + 8001ee0: 3440 adds r4, #64 ; 0x40 + 8001ee2: eb00 0484 add.w r4, r0, r4, lsl #2 + 8001ee6: 6864 ldr r4, [r4, #4] + 8001ee8: eb03 4314 add.w r3, r3, r4, lsr #16 + 8001eec: e7ec b.n 8001ec8 + +08001eee : + * @param size Size of Rx fifo + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) +{ + hpcd->Instance->GRXFSIZ = size; + 8001eee: 6803 ldr r3, [r0, #0] + + return HAL_OK; +} + 8001ef0: 2000 movs r0, #0 + hpcd->Instance->GRXFSIZ = size; + 8001ef2: 6259 str r1, [r3, #36] ; 0x24 +} + 8001ef4: 4770 bx lr + ... + +08001ef8 : + * supported by this API. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8001ef8: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} + uint32_t tickstart; + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + 8001efc: 4604 mov r4, r0 + 8001efe: b918 cbnz r0, 8001f08 + { + return HAL_ERROR; + 8001f00: 2001 movs r0, #1 + { + return HAL_ERROR; + } + } + return HAL_OK; +} + 8001f02: b002 add sp, #8 + 8001f04: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8001f08: 6803 ldr r3, [r0, #0] + 8001f0a: 07dd lsls r5, r3, #31 + 8001f0c: d410 bmi.n 8001f30 + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8001f0e: 6823 ldr r3, [r4, #0] + 8001f10: 0798 lsls r0, r3, #30 + 8001f12: d458 bmi.n 8001fc6 + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8001f14: 6823 ldr r3, [r4, #0] + 8001f16: 071a lsls r2, r3, #28 + 8001f18: f100 809a bmi.w 8002050 + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8001f1c: 6823 ldr r3, [r4, #0] + 8001f1e: 075b lsls r3, r3, #29 + 8001f20: f100 80b8 bmi.w 8002094 + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8001f24: 69a2 ldr r2, [r4, #24] + 8001f26: 2a00 cmp r2, #0 + 8001f28: f040 8119 bne.w 800215e + return HAL_OK; + 8001f2c: 2000 movs r0, #0 + 8001f2e: e7e8 b.n 8001f02 + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ + 8001f30: 4ba6 ldr r3, [pc, #664] ; (80021cc ) + 8001f32: 689a ldr r2, [r3, #8] + 8001f34: f002 020c and.w r2, r2, #12 + 8001f38: 2a04 cmp r2, #4 + 8001f3a: d007 beq.n 8001f4c + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + 8001f3c: 689a ldr r2, [r3, #8] + 8001f3e: f002 020c and.w r2, r2, #12 + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ + 8001f42: 2a08 cmp r2, #8 + 8001f44: d10a bne.n 8001f5c + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + 8001f46: 685b ldr r3, [r3, #4] + 8001f48: 0259 lsls r1, r3, #9 + 8001f4a: d507 bpl.n 8001f5c + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8001f4c: 4b9f ldr r3, [pc, #636] ; (80021cc ) + 8001f4e: 681b ldr r3, [r3, #0] + 8001f50: 039a lsls r2, r3, #14 + 8001f52: d5dc bpl.n 8001f0e + 8001f54: 6863 ldr r3, [r4, #4] + 8001f56: 2b00 cmp r3, #0 + 8001f58: d1d9 bne.n 8001f0e + 8001f5a: e7d1 b.n 8001f00 + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8001f5c: 6863 ldr r3, [r4, #4] + 8001f5e: 4d9b ldr r5, [pc, #620] ; (80021cc ) + 8001f60: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8001f64: d111 bne.n 8001f8a + 8001f66: 682b ldr r3, [r5, #0] + 8001f68: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8001f6c: 602b str r3, [r5, #0] + tickstart = HAL_GetTick(); + 8001f6e: f7fe feaf bl 8000cd0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8001f72: 4d96 ldr r5, [pc, #600] ; (80021cc ) + tickstart = HAL_GetTick(); + 8001f74: 4606 mov r6, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8001f76: 682b ldr r3, [r5, #0] + 8001f78: 039b lsls r3, r3, #14 + 8001f7a: d4c8 bmi.n 8001f0e + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8001f7c: f7fe fea8 bl 8000cd0 + 8001f80: 1b80 subs r0, r0, r6 + 8001f82: 2864 cmp r0, #100 ; 0x64 + 8001f84: d9f7 bls.n 8001f76 + return HAL_TIMEOUT; + 8001f86: 2003 movs r0, #3 + 8001f88: e7bb b.n 8001f02 + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8001f8a: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 8001f8e: d104 bne.n 8001f9a + 8001f90: 682b ldr r3, [r5, #0] + 8001f92: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 8001f96: 602b str r3, [r5, #0] + 8001f98: e7e5 b.n 8001f66 + 8001f9a: 682a ldr r2, [r5, #0] + 8001f9c: f422 3280 bic.w r2, r2, #65536 ; 0x10000 + 8001fa0: 602a str r2, [r5, #0] + 8001fa2: 682a ldr r2, [r5, #0] + 8001fa4: f422 2280 bic.w r2, r2, #262144 ; 0x40000 + 8001fa8: 602a str r2, [r5, #0] + if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) + 8001faa: 2b00 cmp r3, #0 + 8001fac: d1df bne.n 8001f6e + tickstart = HAL_GetTick(); + 8001fae: f7fe fe8f bl 8000cd0 + 8001fb2: 4606 mov r6, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8001fb4: 682b ldr r3, [r5, #0] + 8001fb6: 039f lsls r7, r3, #14 + 8001fb8: d5a9 bpl.n 8001f0e + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8001fba: f7fe fe89 bl 8000cd0 + 8001fbe: 1b80 subs r0, r0, r6 + 8001fc0: 2864 cmp r0, #100 ; 0x64 + 8001fc2: d9f7 bls.n 8001fb4 + 8001fc4: e7df b.n 8001f86 + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ + 8001fc6: 4b81 ldr r3, [pc, #516] ; (80021cc ) + 8001fc8: 689a ldr r2, [r3, #8] + 8001fca: f012 0f0c tst.w r2, #12 + 8001fce: d007 beq.n 8001fe0 + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + 8001fd0: 689a ldr r2, [r3, #8] + 8001fd2: f002 020c and.w r2, r2, #12 + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ + 8001fd6: 2a08 cmp r2, #8 + 8001fd8: d111 bne.n 8001ffe + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + 8001fda: 685b ldr r3, [r3, #4] + 8001fdc: 025e lsls r6, r3, #9 + 8001fde: d40e bmi.n 8001ffe + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001fe0: 4b7a ldr r3, [pc, #488] ; (80021cc ) + 8001fe2: 681a ldr r2, [r3, #0] + 8001fe4: 0795 lsls r5, r2, #30 + 8001fe6: d502 bpl.n 8001fee + 8001fe8: 68e2 ldr r2, [r4, #12] + 8001fea: 2a01 cmp r2, #1 + 8001fec: d188 bne.n 8001f00 + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8001fee: 681a ldr r2, [r3, #0] + 8001ff0: 6921 ldr r1, [r4, #16] + 8001ff2: f022 02f8 bic.w r2, r2, #248 ; 0xf8 + 8001ff6: ea42 02c1 orr.w r2, r2, r1, lsl #3 + 8001ffa: 601a str r2, [r3, #0] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001ffc: e78a b.n 8001f14 + if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + 8001ffe: 68e2 ldr r2, [r4, #12] + 8002000: 4b73 ldr r3, [pc, #460] ; (80021d0 ) + 8002002: b1b2 cbz r2, 8002032 + __HAL_RCC_HSI_ENABLE(); + 8002004: 2201 movs r2, #1 + 8002006: 601a str r2, [r3, #0] + tickstart = HAL_GetTick(); + 8002008: f7fe fe62 bl 8000cd0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 800200c: 4d6f ldr r5, [pc, #444] ; (80021cc ) + tickstart = HAL_GetTick(); + 800200e: 4606 mov r6, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8002010: 682b ldr r3, [r5, #0] + 8002012: 0798 lsls r0, r3, #30 + 8002014: d507 bpl.n 8002026 + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8002016: 682b ldr r3, [r5, #0] + 8002018: 6922 ldr r2, [r4, #16] + 800201a: f023 03f8 bic.w r3, r3, #248 ; 0xf8 + 800201e: ea43 03c2 orr.w r3, r3, r2, lsl #3 + 8002022: 602b str r3, [r5, #0] + 8002024: e776 b.n 8001f14 + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8002026: f7fe fe53 bl 8000cd0 + 800202a: 1b80 subs r0, r0, r6 + 800202c: 2802 cmp r0, #2 + 800202e: d9ef bls.n 8002010 + 8002030: e7a9 b.n 8001f86 + __HAL_RCC_HSI_DISABLE(); + 8002032: 601a str r2, [r3, #0] + tickstart = HAL_GetTick(); + 8002034: f7fe fe4c bl 8000cd0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 8002038: 4d64 ldr r5, [pc, #400] ; (80021cc ) + tickstart = HAL_GetTick(); + 800203a: 4606 mov r6, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 800203c: 682b ldr r3, [r5, #0] + 800203e: 0799 lsls r1, r3, #30 + 8002040: f57f af68 bpl.w 8001f14 + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8002044: f7fe fe44 bl 8000cd0 + 8002048: 1b80 subs r0, r0, r6 + 800204a: 2802 cmp r0, #2 + 800204c: d9f6 bls.n 800203c + 800204e: e79a b.n 8001f86 + if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + 8002050: 6962 ldr r2, [r4, #20] + 8002052: 4b60 ldr r3, [pc, #384] ; (80021d4 ) + 8002054: b17a cbz r2, 8002076 + __HAL_RCC_LSI_ENABLE(); + 8002056: 2201 movs r2, #1 + 8002058: 601a str r2, [r3, #0] + tickstart = HAL_GetTick(); + 800205a: f7fe fe39 bl 8000cd0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 800205e: 4d5b ldr r5, [pc, #364] ; (80021cc ) + tickstart = HAL_GetTick(); + 8002060: 4606 mov r6, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8002062: 6f6b ldr r3, [r5, #116] ; 0x74 + 8002064: 079f lsls r7, r3, #30 + 8002066: f53f af59 bmi.w 8001f1c + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 800206a: f7fe fe31 bl 8000cd0 + 800206e: 1b80 subs r0, r0, r6 + 8002070: 2802 cmp r0, #2 + 8002072: d9f6 bls.n 8002062 + 8002074: e787 b.n 8001f86 + __HAL_RCC_LSI_DISABLE(); + 8002076: 601a str r2, [r3, #0] + tickstart = HAL_GetTick(); + 8002078: f7fe fe2a bl 8000cd0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 800207c: 4d53 ldr r5, [pc, #332] ; (80021cc ) + tickstart = HAL_GetTick(); + 800207e: 4606 mov r6, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8002080: 6f6b ldr r3, [r5, #116] ; 0x74 + 8002082: 0798 lsls r0, r3, #30 + 8002084: f57f af4a bpl.w 8001f1c + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8002088: f7fe fe22 bl 8000cd0 + 800208c: 1b80 subs r0, r0, r6 + 800208e: 2802 cmp r0, #2 + 8002090: d9f6 bls.n 8002080 + 8002092: e778 b.n 8001f86 + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8002094: 4b4d ldr r3, [pc, #308] ; (80021cc ) + 8002096: 6c1a ldr r2, [r3, #64] ; 0x40 + 8002098: f012 5280 ands.w r2, r2, #268435456 ; 0x10000000 + 800209c: d128 bne.n 80020f0 + __HAL_RCC_PWR_CLK_ENABLE(); + 800209e: 9201 str r2, [sp, #4] + 80020a0: 6c1a ldr r2, [r3, #64] ; 0x40 + 80020a2: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 + 80020a6: 641a str r2, [r3, #64] ; 0x40 + 80020a8: 6c1b ldr r3, [r3, #64] ; 0x40 + 80020aa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80020ae: 9301 str r3, [sp, #4] + 80020b0: 9b01 ldr r3, [sp, #4] + pwrclkchanged = SET; + 80020b2: 2601 movs r6, #1 + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80020b4: 4d48 ldr r5, [pc, #288] ; (80021d8 ) + 80020b6: 682b ldr r3, [r5, #0] + 80020b8: 05d9 lsls r1, r3, #23 + 80020ba: d51b bpl.n 80020f4 + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 80020bc: 68a3 ldr r3, [r4, #8] + 80020be: 4d43 ldr r5, [pc, #268] ; (80021cc ) + 80020c0: 2b01 cmp r3, #1 + 80020c2: d127 bne.n 8002114 + 80020c4: 6f2b ldr r3, [r5, #112] ; 0x70 + 80020c6: f043 0301 orr.w r3, r3, #1 + 80020ca: 672b str r3, [r5, #112] ; 0x70 + tickstart = HAL_GetTick(); + 80020cc: f7fe fe00 bl 8000cd0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 80020d0: 4d3e ldr r5, [pc, #248] ; (80021cc ) + tickstart = HAL_GetTick(); + 80020d2: 4607 mov r7, r0 + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 80020d4: f241 3888 movw r8, #5000 ; 0x1388 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 80020d8: 6f2b ldr r3, [r5, #112] ; 0x70 + 80020da: 079b lsls r3, r3, #30 + 80020dc: d539 bpl.n 8002152 + if(pwrclkchanged == SET) + 80020de: 2e00 cmp r6, #0 + 80020e0: f43f af20 beq.w 8001f24 + __HAL_RCC_PWR_CLK_DISABLE(); + 80020e4: 4a39 ldr r2, [pc, #228] ; (80021cc ) + 80020e6: 6c13 ldr r3, [r2, #64] ; 0x40 + 80020e8: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 80020ec: 6413 str r3, [r2, #64] ; 0x40 + 80020ee: e719 b.n 8001f24 + FlagStatus pwrclkchanged = RESET; + 80020f0: 2600 movs r6, #0 + 80020f2: e7df b.n 80020b4 + SET_BIT(PWR->CR, PWR_CR_DBP); + 80020f4: 682b ldr r3, [r5, #0] + 80020f6: f443 7380 orr.w r3, r3, #256 ; 0x100 + 80020fa: 602b str r3, [r5, #0] + tickstart = HAL_GetTick(); + 80020fc: f7fe fde8 bl 8000cd0 + 8002100: 4607 mov r7, r0 + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8002102: 682b ldr r3, [r5, #0] + 8002104: 05da lsls r2, r3, #23 + 8002106: d4d9 bmi.n 80020bc + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8002108: f7fe fde2 bl 8000cd0 + 800210c: 1bc0 subs r0, r0, r7 + 800210e: 2802 cmp r0, #2 + 8002110: d9f7 bls.n 8002102 + 8002112: e738 b.n 8001f86 + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8002114: 2b05 cmp r3, #5 + 8002116: d104 bne.n 8002122 + 8002118: 6f2b ldr r3, [r5, #112] ; 0x70 + 800211a: f043 0304 orr.w r3, r3, #4 + 800211e: 672b str r3, [r5, #112] ; 0x70 + 8002120: e7d0 b.n 80020c4 + 8002122: 6f2a ldr r2, [r5, #112] ; 0x70 + 8002124: f022 0201 bic.w r2, r2, #1 + 8002128: 672a str r2, [r5, #112] ; 0x70 + 800212a: 6f2a ldr r2, [r5, #112] ; 0x70 + 800212c: f022 0204 bic.w r2, r2, #4 + 8002130: 672a str r2, [r5, #112] ; 0x70 + if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + 8002132: 2b00 cmp r3, #0 + 8002134: d1ca bne.n 80020cc + tickstart = HAL_GetTick(); + 8002136: f7fe fdcb bl 8000cd0 + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 800213a: f241 3888 movw r8, #5000 ; 0x1388 + tickstart = HAL_GetTick(); + 800213e: 4607 mov r7, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8002140: 6f2b ldr r3, [r5, #112] ; 0x70 + 8002142: 0798 lsls r0, r3, #30 + 8002144: d5cb bpl.n 80020de + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8002146: f7fe fdc3 bl 8000cd0 + 800214a: 1bc0 subs r0, r0, r7 + 800214c: 4540 cmp r0, r8 + 800214e: d9f7 bls.n 8002140 + 8002150: e719 b.n 8001f86 + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8002152: f7fe fdbd bl 8000cd0 + 8002156: 1bc0 subs r0, r0, r7 + 8002158: 4540 cmp r0, r8 + 800215a: d9bd bls.n 80020d8 + 800215c: e713 b.n 8001f86 + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + 800215e: 4d1b ldr r5, [pc, #108] ; (80021cc ) + 8002160: 68ab ldr r3, [r5, #8] + 8002162: f003 030c and.w r3, r3, #12 + 8002166: 2b08 cmp r3, #8 + 8002168: f43f aeca beq.w 8001f00 + 800216c: 4e1b ldr r6, [pc, #108] ; (80021dc ) + 800216e: 2300 movs r3, #0 + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 8002170: 2a02 cmp r2, #2 + __HAL_RCC_PLL_DISABLE(); + 8002172: 6033 str r3, [r6, #0] + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 8002174: d134 bne.n 80021e0 + tickstart = HAL_GetTick(); + 8002176: f7fe fdab bl 8000cd0 + 800217a: 4607 mov r7, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 800217c: 682b ldr r3, [r5, #0] + 800217e: 0199 lsls r1, r3, #6 + 8002180: d41e bmi.n 80021c0 + WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ + 8002182: 6a22 ldr r2, [r4, #32] + 8002184: 69e3 ldr r3, [r4, #28] + 8002186: 4313 orrs r3, r2 + 8002188: 6a62 ldr r2, [r4, #36] ; 0x24 + 800218a: ea43 1382 orr.w r3, r3, r2, lsl #6 + 800218e: 6ae2 ldr r2, [r4, #44] ; 0x2c + 8002190: ea43 6302 orr.w r3, r3, r2, lsl #24 + 8002194: 6aa2 ldr r2, [r4, #40] ; 0x28 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8002196: 4c0d ldr r4, [pc, #52] ; (80021cc ) + WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ + 8002198: 0852 lsrs r2, r2, #1 + 800219a: 3a01 subs r2, #1 + 800219c: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80021a0: 606b str r3, [r5, #4] + __HAL_RCC_PLL_ENABLE(); + 80021a2: 2301 movs r3, #1 + 80021a4: 6033 str r3, [r6, #0] + tickstart = HAL_GetTick(); + 80021a6: f7fe fd93 bl 8000cd0 + 80021aa: 4605 mov r5, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 80021ac: 6823 ldr r3, [r4, #0] + 80021ae: 019a lsls r2, r3, #6 + 80021b0: f53f aebc bmi.w 8001f2c + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 80021b4: f7fe fd8c bl 8000cd0 + 80021b8: 1b40 subs r0, r0, r5 + 80021ba: 2802 cmp r0, #2 + 80021bc: d9f6 bls.n 80021ac + 80021be: e6e2 b.n 8001f86 + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 80021c0: f7fe fd86 bl 8000cd0 + 80021c4: 1bc0 subs r0, r0, r7 + 80021c6: 2802 cmp r0, #2 + 80021c8: d9d8 bls.n 800217c + 80021ca: e6dc b.n 8001f86 + 80021cc: 40023800 .word 0x40023800 + 80021d0: 42470000 .word 0x42470000 + 80021d4: 42470e80 .word 0x42470e80 + 80021d8: 40007000 .word 0x40007000 + 80021dc: 42470060 .word 0x42470060 + tickstart = HAL_GetTick(); + 80021e0: f7fe fd76 bl 8000cd0 + 80021e4: 4604 mov r4, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 80021e6: 682b ldr r3, [r5, #0] + 80021e8: 019b lsls r3, r3, #6 + 80021ea: f57f ae9f bpl.w 8001f2c + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 80021ee: f7fe fd6f bl 8000cd0 + 80021f2: 1b00 subs r0, r0, r4 + 80021f4: 2802 cmp r0, #2 + 80021f6: d9f6 bls.n 80021e6 + 80021f8: e6c5 b.n 8001f86 + 80021fa: bf00 nop + +080021fc : +{ + uint32_t pllm = 0U, pllvco = 0U, pllp = 0U; + uint32_t sysclockfreq = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + 80021fc: 4913 ldr r1, [pc, #76] ; (800224c ) +{ + 80021fe: b508 push {r3, lr} + switch (RCC->CFGR & RCC_CFGR_SWS) + 8002200: 688b ldr r3, [r1, #8] + 8002202: f003 030c and.w r3, r3, #12 + 8002206: 2b04 cmp r3, #4 + 8002208: d003 beq.n 8002212 + 800220a: 2b08 cmp r3, #8 + 800220c: d003 beq.n 8002216 + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 800220e: 4810 ldr r0, [pc, #64] ; (8002250 ) + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} + 8002210: bd08 pop {r3, pc} + sysclockfreq = HSE_VALUE; + 8002212: 4810 ldr r0, [pc, #64] ; (8002254 ) + 8002214: bd08 pop {r3, pc} + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 8002216: 684a ldr r2, [r1, #4] + if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 8002218: 684b ldr r3, [r1, #4] + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 800221a: 6849 ldr r1, [r1, #4] + if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 800221c: f413 0380 ands.w r3, r3, #4194304 ; 0x400000 + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8002220: bf14 ite ne + 8002222: 480c ldrne r0, [pc, #48] ; (8002254 ) + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8002224: 480a ldreq r0, [pc, #40] ; (8002250 ) + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8002226: f3c1 1188 ubfx r1, r1, #6, #9 + 800222a: bf18 it ne + 800222c: 2300 movne r3, #0 + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 800222e: f002 023f and.w r2, r2, #63 ; 0x3f + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8002232: fba1 0100 umull r0, r1, r1, r0 + 8002236: f7fe f823 bl 8000280 <__aeabi_uldivmod> + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); + 800223a: 4b04 ldr r3, [pc, #16] ; (800224c ) + 800223c: 685b ldr r3, [r3, #4] + 800223e: f3c3 4301 ubfx r3, r3, #16, #2 + 8002242: 3301 adds r3, #1 + 8002244: 005b lsls r3, r3, #1 + sysclockfreq = pllvco/pllp; + 8002246: fbb0 f0f3 udiv r0, r0, r3 + 800224a: bd08 pop {r3, pc} + 800224c: 40023800 .word 0x40023800 + 8002250: 00f42400 .word 0x00f42400 + 8002254: 007a1200 .word 0x007a1200 + +08002258 : +{ + 8002258: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800225c: 460d mov r5, r1 + if(RCC_ClkInitStruct == NULL) + 800225e: 4604 mov r4, r0 + 8002260: b910 cbnz r0, 8002268 + return HAL_ERROR; + 8002262: 2001 movs r0, #1 + 8002264: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 8002268: 4b44 ldr r3, [pc, #272] ; (800237c ) + 800226a: 681a ldr r2, [r3, #0] + 800226c: f002 020f and.w r2, r2, #15 + 8002270: 428a cmp r2, r1 + 8002272: d328 bcc.n 80022c6 + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8002274: 6821 ldr r1, [r4, #0] + 8002276: 078f lsls r7, r1, #30 + 8002278: d42d bmi.n 80022d6 + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 800227a: 07c8 lsls r0, r1, #31 + 800227c: d440 bmi.n 8002300 + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 800227e: 4b3f ldr r3, [pc, #252] ; (800237c ) + 8002280: 681a ldr r2, [r3, #0] + 8002282: f002 020f and.w r2, r2, #15 + 8002286: 4295 cmp r5, r2 + 8002288: d366 bcc.n 8002358 + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 800228a: 6822 ldr r2, [r4, #0] + 800228c: 0751 lsls r1, r2, #29 + 800228e: d46c bmi.n 800236a + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8002290: 0713 lsls r3, r2, #28 + 8002292: d507 bpl.n 80022a4 + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 8002294: 4a3a ldr r2, [pc, #232] ; (8002380 ) + 8002296: 6921 ldr r1, [r4, #16] + 8002298: 6893 ldr r3, [r2, #8] + 800229a: f423 4360 bic.w r3, r3, #57344 ; 0xe000 + 800229e: ea43 03c1 orr.w r3, r3, r1, lsl #3 + 80022a2: 6093 str r3, [r2, #8] + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 80022a4: f7ff ffaa bl 80021fc + 80022a8: 4b35 ldr r3, [pc, #212] ; (8002380 ) + 80022aa: 4a36 ldr r2, [pc, #216] ; (8002384 ) + 80022ac: 689b ldr r3, [r3, #8] + 80022ae: f3c3 1303 ubfx r3, r3, #4, #4 + 80022b2: 5cd3 ldrb r3, [r2, r3] + 80022b4: 40d8 lsrs r0, r3 + 80022b6: 4b34 ldr r3, [pc, #208] ; (8002388 ) + 80022b8: 6018 str r0, [r3, #0] + HAL_InitTick (TICK_INT_PRIORITY); + 80022ba: 2000 movs r0, #0 + 80022bc: f003 fcf4 bl 8005ca8 + return HAL_OK; + 80022c0: 2000 movs r0, #0 + 80022c2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + __HAL_FLASH_SET_LATENCY(FLatency); + 80022c6: b2ca uxtb r2, r1 + 80022c8: 701a strb r2, [r3, #0] + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 80022ca: 681b ldr r3, [r3, #0] + 80022cc: f003 030f and.w r3, r3, #15 + 80022d0: 4299 cmp r1, r3 + 80022d2: d1c6 bne.n 8002262 + 80022d4: e7ce b.n 8002274 + 80022d6: 4b2a ldr r3, [pc, #168] ; (8002380 ) + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 80022d8: f011 0f04 tst.w r1, #4 + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + 80022dc: bf1e ittt ne + 80022de: 689a ldrne r2, [r3, #8] + 80022e0: f442 52e0 orrne.w r2, r2, #7168 ; 0x1c00 + 80022e4: 609a strne r2, [r3, #8] + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 80022e6: 070e lsls r6, r1, #28 + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + 80022e8: bf42 ittt mi + 80022ea: 689a ldrmi r2, [r3, #8] + 80022ec: f442 4260 orrmi.w r2, r2, #57344 ; 0xe000 + 80022f0: 609a strmi r2, [r3, #8] + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 80022f2: 689a ldr r2, [r3, #8] + 80022f4: 68a0 ldr r0, [r4, #8] + 80022f6: f022 02f0 bic.w r2, r2, #240 ; 0xf0 + 80022fa: 4302 orrs r2, r0 + 80022fc: 609a str r2, [r3, #8] + 80022fe: e7bc b.n 800227a + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8002300: 6862 ldr r2, [r4, #4] + 8002302: 4b1f ldr r3, [pc, #124] ; (8002380 ) + 8002304: 2a01 cmp r2, #1 + 8002306: d11d bne.n 8002344 + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8002308: 681b ldr r3, [r3, #0] + 800230a: f413 3f00 tst.w r3, #131072 ; 0x20000 + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 800230e: d0a8 beq.n 8002262 + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8002310: 4e1b ldr r6, [pc, #108] ; (8002380 ) + 8002312: 68b3 ldr r3, [r6, #8] + 8002314: f023 0303 bic.w r3, r3, #3 + 8002318: 4313 orrs r3, r2 + 800231a: 60b3 str r3, [r6, #8] + tickstart = HAL_GetTick(); + 800231c: f7fe fcd8 bl 8000cd0 + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 8002320: f241 3888 movw r8, #5000 ; 0x1388 + tickstart = HAL_GetTick(); + 8002324: 4607 mov r7, r0 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8002326: 68b3 ldr r3, [r6, #8] + 8002328: 6862 ldr r2, [r4, #4] + 800232a: f003 030c and.w r3, r3, #12 + 800232e: ebb3 0f82 cmp.w r3, r2, lsl #2 + 8002332: d0a4 beq.n 800227e + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 8002334: f7fe fccc bl 8000cd0 + 8002338: 1bc0 subs r0, r0, r7 + 800233a: 4540 cmp r0, r8 + 800233c: d9f3 bls.n 8002326 + return HAL_TIMEOUT; + 800233e: 2003 movs r0, #3 +} + 8002340: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || + 8002344: 1e91 subs r1, r2, #2 + 8002346: 2901 cmp r1, #1 + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8002348: 681b ldr r3, [r3, #0] + else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || + 800234a: d802 bhi.n 8002352 + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 800234c: f013 7f00 tst.w r3, #33554432 ; 0x2000000 + 8002350: e7dd b.n 800230e + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8002352: f013 0f02 tst.w r3, #2 + 8002356: e7da b.n 800230e + __HAL_FLASH_SET_LATENCY(FLatency); + 8002358: b2ea uxtb r2, r5 + 800235a: 701a strb r2, [r3, #0] + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 800235c: 681b ldr r3, [r3, #0] + 800235e: f003 030f and.w r3, r3, #15 + 8002362: 429d cmp r5, r3 + 8002364: f47f af7d bne.w 8002262 + 8002368: e78f b.n 800228a + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 800236a: 4905 ldr r1, [pc, #20] ; (8002380 ) + 800236c: 68e0 ldr r0, [r4, #12] + 800236e: 688b ldr r3, [r1, #8] + 8002370: f423 53e0 bic.w r3, r3, #7168 ; 0x1c00 + 8002374: 4303 orrs r3, r0 + 8002376: 608b str r3, [r1, #8] + 8002378: e78a b.n 8002290 + 800237a: bf00 nop + 800237c: 40023c00 .word 0x40023c00 + 8002380: 40023800 .word 0x40023800 + 8002384: 08006c9d .word 0x08006c9d + 8002388: 20000198 .word 0x20000198 + +0800238c : + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + 800238c: 4b01 ldr r3, [pc, #4] ; (8002394 ) + 800238e: 6818 ldr r0, [r3, #0] + 8002390: 4770 bx lr + 8002392: bf00 nop + 8002394: 20000198 .word 0x20000198 + +08002398 : + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); + 8002398: 4b04 ldr r3, [pc, #16] ; (80023ac ) + 800239a: 4a05 ldr r2, [pc, #20] ; (80023b0 ) + 800239c: 689b ldr r3, [r3, #8] + 800239e: f3c3 2382 ubfx r3, r3, #10, #3 + 80023a2: 5cd3 ldrb r3, [r2, r3] + 80023a4: 4a03 ldr r2, [pc, #12] ; (80023b4 ) + 80023a6: 6810 ldr r0, [r2, #0] +} + 80023a8: 40d8 lsrs r0, r3 + 80023aa: 4770 bx lr + 80023ac: 40023800 .word 0x40023800 + 80023b0: 08006cad .word 0x08006cad + 80023b4: 20000198 .word 0x20000198 + +080023b8 : + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + 80023b8: 230f movs r3, #15 + 80023ba: 6003 str r3, [r0, #0] + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + 80023bc: 4b0b ldr r3, [pc, #44] ; (80023ec ) + 80023be: 689a ldr r2, [r3, #8] + 80023c0: f002 0203 and.w r2, r2, #3 + 80023c4: 6042 str r2, [r0, #4] + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + 80023c6: 689a ldr r2, [r3, #8] + 80023c8: f002 02f0 and.w r2, r2, #240 ; 0xf0 + 80023cc: 6082 str r2, [r0, #8] + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + 80023ce: 689a ldr r2, [r3, #8] + 80023d0: f402 52e0 and.w r2, r2, #7168 ; 0x1c00 + 80023d4: 60c2 str r2, [r0, #12] + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); + 80023d6: 689b ldr r3, [r3, #8] + 80023d8: 08db lsrs r3, r3, #3 + 80023da: f403 53e0 and.w r3, r3, #7168 ; 0x1c00 + 80023de: 6103 str r3, [r0, #16] + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + 80023e0: 4b03 ldr r3, [pc, #12] ; (80023f0 ) + 80023e2: 681b ldr r3, [r3, #0] + 80023e4: f003 030f and.w r3, r3, #15 + 80023e8: 600b str r3, [r1, #0] + 80023ea: 4770 bx lr + 80023ec: 40023800 .word 0x40023800 + 80023f0: 40023c00 .word 0x40023c00 + +080023f4 : + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- I2S configuration ---------------------------*/ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + 80023f4: 6803 ldr r3, [r0, #0] + 80023f6: f013 0f05 tst.w r3, #5 +{ + 80023fa: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 80023fc: 4605 mov r5, r0 + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + 80023fe: d105 bne.n 800240c + } + } + } + + /*---------------------------- RTC configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + 8002400: 6828 ldr r0, [r5, #0] + 8002402: f010 0002 ands.w r0, r0, #2 + 8002406: d128 bne.n 800245a + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ + return HAL_OK; +} + 8002408: b003 add sp, #12 + 800240a: bdf0 pop {r4, r5, r6, r7, pc} + __HAL_RCC_PLLI2S_DISABLE(); + 800240c: 4c41 ldr r4, [pc, #260] ; (8002514 ) + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 800240e: 4e42 ldr r6, [pc, #264] ; (8002518 ) + __HAL_RCC_PLLI2S_DISABLE(); + 8002410: 2300 movs r3, #0 + 8002412: 6023 str r3, [r4, #0] + tickstart = HAL_GetTick(); + 8002414: f7fe fc5c bl 8000cd0 + 8002418: 4607 mov r7, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 800241a: 6833 ldr r3, [r6, #0] + 800241c: 011b lsls r3, r3, #4 + 800241e: d415 bmi.n 800244c + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); + 8002420: 68ab ldr r3, [r5, #8] + 8002422: 686a ldr r2, [r5, #4] + 8002424: 071b lsls r3, r3, #28 + 8002426: ea43 1382 orr.w r3, r3, r2, lsl #6 + 800242a: f8c6 3084 str.w r3, [r6, #132] ; 0x84 + __HAL_RCC_PLLI2S_ENABLE(); + 800242e: 2301 movs r3, #1 + 8002430: 6023 str r3, [r4, #0] + tickstart = HAL_GetTick(); + 8002432: f7fe fc4d bl 8000cd0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 8002436: 4c38 ldr r4, [pc, #224] ; (8002518 ) + tickstart = HAL_GetTick(); + 8002438: 4606 mov r6, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 800243a: 6823 ldr r3, [r4, #0] + 800243c: 0118 lsls r0, r3, #4 + 800243e: d4df bmi.n 8002400 + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + 8002440: f7fe fc46 bl 8000cd0 + 8002444: 1b80 subs r0, r0, r6 + 8002446: 2802 cmp r0, #2 + 8002448: d9f7 bls.n 800243a + 800244a: e004 b.n 8002456 + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + 800244c: f7fe fc40 bl 8000cd0 + 8002450: 1bc0 subs r0, r0, r7 + 8002452: 2802 cmp r0, #2 + 8002454: d9e1 bls.n 800241a + return HAL_TIMEOUT; + 8002456: 2003 movs r0, #3 + 8002458: e7d6 b.n 8002408 + __HAL_RCC_PWR_CLK_ENABLE(); + 800245a: 2300 movs r3, #0 + 800245c: 9301 str r3, [sp, #4] + 800245e: 4b2e ldr r3, [pc, #184] ; (8002518 ) + PWR->CR |= PWR_CR_DBP; + 8002460: 4c2e ldr r4, [pc, #184] ; (800251c ) + __HAL_RCC_PWR_CLK_ENABLE(); + 8002462: 6c1a ldr r2, [r3, #64] ; 0x40 + 8002464: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 + 8002468: 641a str r2, [r3, #64] ; 0x40 + 800246a: 6c1b ldr r3, [r3, #64] ; 0x40 + 800246c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002470: 9301 str r3, [sp, #4] + 8002472: 9b01 ldr r3, [sp, #4] + PWR->CR |= PWR_CR_DBP; + 8002474: 6823 ldr r3, [r4, #0] + 8002476: f443 7380 orr.w r3, r3, #256 ; 0x100 + 800247a: 6023 str r3, [r4, #0] + tickstart = HAL_GetTick(); + 800247c: f7fe fc28 bl 8000cd0 + 8002480: 4606 mov r6, r0 + while((PWR->CR & PWR_CR_DBP) == RESET) + 8002482: 6823 ldr r3, [r4, #0] + 8002484: 05d9 lsls r1, r3, #23 + 8002486: d51b bpl.n 80024c0 + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + 8002488: 4c23 ldr r4, [pc, #140] ; (8002518 ) + 800248a: 6f23 ldr r3, [r4, #112] ; 0x70 + if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + 800248c: f413 7340 ands.w r3, r3, #768 ; 0x300 + 8002490: d11c bne.n 80024cc + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 8002492: 68eb ldr r3, [r5, #12] + 8002494: f403 7240 and.w r2, r3, #768 ; 0x300 + 8002498: f5b2 7f40 cmp.w r2, #768 ; 0x300 + 800249c: 4a1e ldr r2, [pc, #120] ; (8002518 ) + 800249e: d134 bne.n 800250a + 80024a0: 6891 ldr r1, [r2, #8] + 80024a2: f023 4070 bic.w r0, r3, #4026531840 ; 0xf0000000 + 80024a6: f421 11f8 bic.w r1, r1, #2031616 ; 0x1f0000 + 80024aa: f420 7040 bic.w r0, r0, #768 ; 0x300 + 80024ae: 4301 orrs r1, r0 + 80024b0: 6091 str r1, [r2, #8] + 80024b2: 6f11 ldr r1, [r2, #112] ; 0x70 + 80024b4: f3c3 030b ubfx r3, r3, #0, #12 + 80024b8: 430b orrs r3, r1 + 80024ba: 6713 str r3, [r2, #112] ; 0x70 + return HAL_OK; + 80024bc: 2000 movs r0, #0 + 80024be: e7a3 b.n 8002408 + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + 80024c0: f7fe fc06 bl 8000cd0 + 80024c4: 1b80 subs r0, r0, r6 + 80024c6: 2802 cmp r0, #2 + 80024c8: d9db bls.n 8002482 + 80024ca: e7c4 b.n 8002456 + if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + 80024cc: 68ea ldr r2, [r5, #12] + 80024ce: f402 7240 and.w r2, r2, #768 ; 0x300 + 80024d2: 4293 cmp r3, r2 + 80024d4: d0dd beq.n 8002492 + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 80024d6: 6f23 ldr r3, [r4, #112] ; 0x70 + __HAL_RCC_BACKUPRESET_FORCE(); + 80024d8: 4a11 ldr r2, [pc, #68] ; (8002520 ) + 80024da: 2101 movs r1, #1 + 80024dc: 6011 str r1, [r2, #0] + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 80024de: f423 7340 bic.w r3, r3, #768 ; 0x300 + __HAL_RCC_BACKUPRESET_RELEASE(); + 80024e2: 2100 movs r1, #0 + 80024e4: 6011 str r1, [r2, #0] + RCC->BDCR = tmpreg1; + 80024e6: 6723 str r3, [r4, #112] ; 0x70 + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + 80024e8: 6f23 ldr r3, [r4, #112] ; 0x70 + 80024ea: 07da lsls r2, r3, #31 + 80024ec: d5d1 bpl.n 8002492 + tickstart = HAL_GetTick(); + 80024ee: f7fe fbef bl 8000cd0 + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 80024f2: f241 3788 movw r7, #5000 ; 0x1388 + tickstart = HAL_GetTick(); + 80024f6: 4606 mov r6, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 80024f8: 6f23 ldr r3, [r4, #112] ; 0x70 + 80024fa: 079b lsls r3, r3, #30 + 80024fc: d4c9 bmi.n 8002492 + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 80024fe: f7fe fbe7 bl 8000cd0 + 8002502: 1b80 subs r0, r0, r6 + 8002504: 42b8 cmp r0, r7 + 8002506: d9f7 bls.n 80024f8 + 8002508: e7a5 b.n 8002456 + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 800250a: 6891 ldr r1, [r2, #8] + 800250c: f421 11f8 bic.w r1, r1, #2031616 ; 0x1f0000 + 8002510: e7ce b.n 80024b0 + 8002512: bf00 nop + 8002514: 42470068 .word 0x42470068 + 8002518: 40023800 .word 0x40023800 + 800251c: 40007000 .word 0x40007000 + 8002520: 42470e40 .word 0x42470e40 + +08002524 : + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + 8002524: 2801 cmp r0, #1 + 8002526: d120 bne.n 800256a + { + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + 8002528: 4b11 ldr r3, [pc, #68] ; (8002570 ) + 800252a: 689a ldr r2, [r3, #8] + switch (srcclk) + 800252c: f412 0200 ands.w r2, r2, #8388608 ; 0x800000 + 8002530: d004 beq.n 800253c + 8002532: 2a01 cmp r2, #1 + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + 8002534: 480f ldr r0, [pc, #60] ; (8002574 ) + 8002536: bf18 it ne + 8002538: 2000 movne r0, #0 + 800253a: 4770 bx lr + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + 800253c: 685a ldr r2, [r3, #4] + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + 800253e: 490c ldr r1, [pc, #48] ; (8002570 ) + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + 8002540: 6858 ldr r0, [r3, #4] + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + 8002542: 0253 lsls r3, r2, #9 + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + 8002544: f8d1 2084 ldr.w r2, [r1, #132] ; 0x84 + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + 8002548: bf4c ite mi + 800254a: 4b0b ldrmi r3, [pc, #44] ; (8002578 ) + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + 800254c: 4b0b ldrpl r3, [pc, #44] ; (800257c ) + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + 800254e: f000 003f and.w r0, r0, #63 ; 0x3f + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + 8002552: fbb3 f3f0 udiv r3, r3, r0 + frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + 8002556: f8d1 0084 ldr.w r0, [r1, #132] ; 0x84 + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + 800255a: f3c2 1288 ubfx r2, r2, #6, #9 + 800255e: 4353 muls r3, r2 + frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + 8002560: f3c0 7002 ubfx r0, r0, #28, #3 + 8002564: fbb3 f0f0 udiv r0, r3, r0 + break; + 8002568: 4770 bx lr + uint32_t frequency = 0U; + 800256a: 2000 movs r0, #0 + } + break; + } + } + return frequency; +} + 800256c: 4770 bx lr + 800256e: bf00 nop + 8002570: 40023800 .word 0x40023800 + 8002574: 00bb8000 .word 0x00bb8000 + 8002578: 007a1200 .word 0x007a1200 + 800257c: 00f42400 .word 0x00f42400 + +08002580 : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart) +{ + 8002580: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8002584: 9e06 ldr r6, [sp, #24] + 8002586: 4604 mov r4, r0 + 8002588: 4688 mov r8, r1 + 800258a: 4617 mov r7, r2 + 800258c: 461d mov r5, r3 + while((((hspi->Instance->SR & Flag) == (Flag)) ? SET : RESET) != State) + 800258e: 6822 ldr r2, [r4, #0] + 8002590: 6893 ldr r3, [r2, #8] + 8002592: ea38 0303 bics.w r3, r8, r3 + 8002596: bf0c ite eq + 8002598: 2301 moveq r3, #1 + 800259a: 2300 movne r3, #0 + 800259c: 429f cmp r7, r3 + 800259e: d102 bne.n 80025a6 + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; + 80025a0: 2000 movs r0, #0 +} + 80025a2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + if(Timeout != HAL_MAX_DELAY) + 80025a6: 1c6b adds r3, r5, #1 + 80025a8: d0f2 beq.n 8002590 + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout)) + 80025aa: bb55 cbnz r5, 8002602 + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 80025ac: 6823 ldr r3, [r4, #0] + 80025ae: 685a ldr r2, [r3, #4] + 80025b0: f022 02e0 bic.w r2, r2, #224 ; 0xe0 + 80025b4: 605a str r2, [r3, #4] + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 80025b6: 6862 ldr r2, [r4, #4] + 80025b8: f5b2 7f82 cmp.w r2, #260 ; 0x104 + 80025bc: d10a bne.n 80025d4 + 80025be: 68a2 ldr r2, [r4, #8] + 80025c0: f5b2 4f00 cmp.w r2, #32768 ; 0x8000 + 80025c4: d002 beq.n 80025cc + 80025c6: f5b2 6f80 cmp.w r2, #1024 ; 0x400 + 80025ca: d103 bne.n 80025d4 + __HAL_SPI_DISABLE(hspi); + 80025cc: 681a ldr r2, [r3, #0] + 80025ce: f022 0240 bic.w r2, r2, #64 ; 0x40 + 80025d2: 601a str r2, [r3, #0] + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 80025d4: 6aa2 ldr r2, [r4, #40] ; 0x28 + 80025d6: f5b2 5f00 cmp.w r2, #8192 ; 0x2000 + 80025da: d109 bne.n 80025f0 + SPI_RESET_CRC(hspi); + 80025dc: 681a ldr r2, [r3, #0] + 80025de: f422 5200 bic.w r2, r2, #8192 ; 0x2000 + 80025e2: 0412 lsls r2, r2, #16 + 80025e4: 0c12 lsrs r2, r2, #16 + 80025e6: 601a str r2, [r3, #0] + 80025e8: 681a ldr r2, [r3, #0] + 80025ea: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 80025ee: 601a str r2, [r3, #0] + hspi->State= HAL_SPI_STATE_READY; + 80025f0: 2301 movs r3, #1 + 80025f2: f884 3051 strb.w r3, [r4, #81] ; 0x51 + __HAL_UNLOCK(hspi); + 80025f6: 2300 movs r3, #0 + 80025f8: f884 3050 strb.w r3, [r4, #80] ; 0x50 + 80025fc: 2003 movs r0, #3 + 80025fe: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout)) + 8002602: f7fe fb65 bl 8000cd0 + 8002606: 1b80 subs r0, r0, r6 + 8002608: 4285 cmp r5, r0 + 800260a: d8c0 bhi.n 800258e + 800260c: e7ce b.n 80025ac + +0800260e : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 800260e: b513 push {r0, r1, r4, lr} + /* Control the BSY flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 8002610: 460b mov r3, r1 + 8002612: 9200 str r2, [sp, #0] + 8002614: 2180 movs r1, #128 ; 0x80 + 8002616: 2200 movs r2, #0 +{ + 8002618: 4604 mov r4, r0 + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 800261a: f7ff ffb1 bl 8002580 + 800261e: b120 cbz r0, 800262a + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8002620: 6d63 ldr r3, [r4, #84] ; 0x54 + 8002622: f043 0320 orr.w r3, r3, #32 + 8002626: 6563 str r3, [r4, #84] ; 0x54 + return HAL_TIMEOUT; + 8002628: 2003 movs r0, #3 + } + return HAL_OK; +} + 800262a: b002 add sp, #8 + 800262c: bd10 pop {r4, pc} + +0800262e : +{ + 800262e: b510 push {r4, lr} + if(hspi == NULL) + 8002630: 4604 mov r4, r0 + 8002632: 2800 cmp r0, #0 + 8002634: d036 beq.n 80026a4 + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8002636: 2300 movs r3, #0 + 8002638: 6283 str r3, [r0, #40] ; 0x28 + if(hspi->State == HAL_SPI_STATE_RESET) + 800263a: f890 3051 ldrb.w r3, [r0, #81] ; 0x51 + 800263e: f003 02ff and.w r2, r3, #255 ; 0xff + 8002642: b91b cbnz r3, 800264c + hspi->Lock = HAL_UNLOCKED; + 8002644: f880 2050 strb.w r2, [r0, #80] ; 0x50 + HAL_SPI_MspInit(hspi); + 8002648: f003 faf4 bl 8005c34 + __HAL_SPI_DISABLE(hspi); + 800264c: 6821 ldr r1, [r4, #0] + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + 800264e: 68a0 ldr r0, [r4, #8] + 8002650: 69a2 ldr r2, [r4, #24] + hspi->State = HAL_SPI_STATE_BUSY; + 8002652: 2302 movs r3, #2 + 8002654: f884 3051 strb.w r3, [r4, #81] ; 0x51 + __HAL_SPI_DISABLE(hspi); + 8002658: 680b ldr r3, [r1, #0] + 800265a: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800265e: 600b str r3, [r1, #0] + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + 8002660: 6863 ldr r3, [r4, #4] + 8002662: 4303 orrs r3, r0 + 8002664: 68e0 ldr r0, [r4, #12] + 8002666: 4303 orrs r3, r0 + 8002668: 6920 ldr r0, [r4, #16] + 800266a: 4303 orrs r3, r0 + 800266c: 6960 ldr r0, [r4, #20] + 800266e: 4303 orrs r3, r0 + 8002670: 69e0 ldr r0, [r4, #28] + 8002672: 4303 orrs r3, r0 + 8002674: 6a20 ldr r0, [r4, #32] + 8002676: 4303 orrs r3, r0 + 8002678: 6aa0 ldr r0, [r4, #40] ; 0x28 + 800267a: 4303 orrs r3, r0 + 800267c: f402 7000 and.w r0, r2, #512 ; 0x200 + 8002680: 4303 orrs r3, r0 + 8002682: 600b str r3, [r1, #0] + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + 8002684: 0c12 lsrs r2, r2, #16 + 8002686: 6a63 ldr r3, [r4, #36] ; 0x24 + 8002688: f002 0204 and.w r2, r2, #4 + 800268c: 431a orrs r2, r3 + 800268e: 604a str r2, [r1, #4] + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 8002690: 69cb ldr r3, [r1, #28] + 8002692: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 8002696: 61cb str r3, [r1, #28] + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8002698: 2000 movs r0, #0 + hspi->State = HAL_SPI_STATE_READY; + 800269a: 2301 movs r3, #1 + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 800269c: 6560 str r0, [r4, #84] ; 0x54 + hspi->State = HAL_SPI_STATE_READY; + 800269e: f884 3051 strb.w r3, [r4, #81] ; 0x51 + return HAL_OK; + 80026a2: bd10 pop {r4, pc} + return HAL_ERROR; + 80026a4: 2001 movs r0, #1 +} + 80026a6: bd10 pop {r4, pc} + +080026a8 : +{ + 80026a8: b510 push {r4, lr} + if(hspi == NULL) + 80026aa: 4604 mov r4, r0 + 80026ac: b180 cbz r0, 80026d0 + __HAL_SPI_DISABLE(hspi); + 80026ae: 6802 ldr r2, [r0, #0] + hspi->State = HAL_SPI_STATE_BUSY; + 80026b0: 2302 movs r3, #2 + 80026b2: f880 3051 strb.w r3, [r0, #81] ; 0x51 + __HAL_SPI_DISABLE(hspi); + 80026b6: 6813 ldr r3, [r2, #0] + 80026b8: f023 0340 bic.w r3, r3, #64 ; 0x40 + 80026bc: 6013 str r3, [r2, #0] + HAL_SPI_MspDeInit(hspi); + 80026be: f003 fadf bl 8005c80 + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 80026c2: 2000 movs r0, #0 + 80026c4: 6560 str r0, [r4, #84] ; 0x54 + __HAL_UNLOCK(hspi); + 80026c6: f884 0050 strb.w r0, [r4, #80] ; 0x50 + hspi->State = HAL_SPI_STATE_RESET; + 80026ca: f884 0051 strb.w r0, [r4, #81] ; 0x51 + return HAL_OK; + 80026ce: bd10 pop {r4, pc} + return HAL_ERROR; + 80026d0: 2001 movs r0, #1 +} + 80026d2: bd10 pop {r4, pc} + +080026d4 : +{ + 80026d4: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 80026d8: 4699 mov r9, r3 + __HAL_LOCK(hspi); + 80026da: f890 3050 ldrb.w r3, [r0, #80] ; 0x50 +{ + 80026de: b085 sub sp, #20 + __HAL_LOCK(hspi); + 80026e0: 2b01 cmp r3, #1 +{ + 80026e2: 4604 mov r4, r0 + 80026e4: 460d mov r5, r1 + 80026e6: 4616 mov r6, r2 + 80026e8: 9f0c ldr r7, [sp, #48] ; 0x30 + __HAL_LOCK(hspi); + 80026ea: f000 80ed beq.w 80028c8 + 80026ee: 2301 movs r3, #1 + 80026f0: f880 3050 strb.w r3, [r0, #80] ; 0x50 + tickstart = HAL_GetTick(); + 80026f4: f7fe faec bl 8000cd0 + tmp = hspi->State; + 80026f8: f894 3051 ldrb.w r3, [r4, #81] ; 0x51 + tmp1 = hspi->Init.Mode; + 80026fc: 6861 ldr r1, [r4, #4] + tmp = hspi->State; + 80026fe: b2db uxtb r3, r3 + if(!((tmp == HAL_SPI_STATE_READY) || \ + 8002700: 2b01 cmp r3, #1 + tickstart = HAL_GetTick(); + 8002702: 4680 mov r8, r0 + if(!((tmp == HAL_SPI_STATE_READY) || \ + 8002704: d00a beq.n 800271c + 8002706: f5b1 7f82 cmp.w r1, #260 ; 0x104 + 800270a: f040 80db bne.w 80028c4 + ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) + 800270e: 68a2 ldr r2, [r4, #8] + 8002710: 2a00 cmp r2, #0 + 8002712: f040 80d7 bne.w 80028c4 + 8002716: 2b04 cmp r3, #4 + 8002718: f040 80d4 bne.w 80028c4 + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + 800271c: 2d00 cmp r5, #0 + 800271e: d04e beq.n 80027be + 8002720: 2e00 cmp r6, #0 + 8002722: d04c beq.n 80027be + 8002724: f1b9 0f00 cmp.w r9, #0 + 8002728: d049 beq.n 80027be + if(hspi->State == HAL_SPI_STATE_READY) + 800272a: f894 3051 ldrb.w r3, [r4, #81] ; 0x51 + hspi->pRxBuffPtr = (uint8_t *)pRxData; + 800272e: 63a6 str r6, [r4, #56] ; 0x38 + if(hspi->State == HAL_SPI_STATE_READY) + 8002730: 2b01 cmp r3, #1 + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + 8002732: bf04 itt eq + 8002734: 2305 moveq r3, #5 + 8002736: f884 3051 strbeq.w r3, [r4, #81] ; 0x51 + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 800273a: 2300 movs r3, #0 + 800273c: 6563 str r3, [r4, #84] ; 0x54 + hspi->RxISR = NULL; + 800273e: 6423 str r3, [r4, #64] ; 0x40 + hspi->TxISR = NULL; + 8002740: 6463 str r3, [r4, #68] ; 0x44 + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + 8002742: 6823 ldr r3, [r4, #0] + hspi->RxXferCount = Size; + 8002744: f8a4 903e strh.w r9, [r4, #62] ; 0x3e + hspi->TxXferCount = Size; + 8002748: f8a4 9036 strh.w r9, [r4, #54] ; 0x36 + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + 800274c: 681a ldr r2, [r3, #0] + hspi->RxXferSize = Size; + 800274e: f8a4 903c strh.w r9, [r4, #60] ; 0x3c + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + 8002752: 0650 lsls r0, r2, #25 + __HAL_SPI_ENABLE(hspi); + 8002754: bf58 it pl + 8002756: 681a ldrpl r2, [r3, #0] + hspi->pTxBuffPtr = (uint8_t *)pTxData; + 8002758: 6325 str r5, [r4, #48] ; 0x30 + __HAL_SPI_ENABLE(hspi); + 800275a: bf58 it pl + 800275c: f042 0240 orrpl.w r2, r2, #64 ; 0x40 + hspi->TxXferSize = Size; + 8002760: f8a4 9034 strh.w r9, [r4, #52] ; 0x34 + __HAL_SPI_ENABLE(hspi); + 8002764: bf58 it pl + 8002766: 601a strpl r2, [r3, #0] + if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + 8002768: 68e2 ldr r2, [r4, #12] + 800276a: f5b2 6f00 cmp.w r2, #2048 ; 0x800 + 800276e: d15d bne.n 800282c + if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + 8002770: b119 cbz r1, 800277a + 8002772: 8ee2 ldrh r2, [r4, #54] ; 0x36 + 8002774: b292 uxth r2, r2 + 8002776: 2a01 cmp r2, #1 + 8002778: d106 bne.n 8002788 + hspi->Instance->DR = *((uint16_t *)pTxData); + 800277a: f835 2b02 ldrh.w r2, [r5], #2 + 800277e: 60da str r2, [r3, #12] + hspi->TxXferCount--; + 8002780: 8ee3 ldrh r3, [r4, #54] ; 0x36 + 8002782: 3b01 subs r3, #1 + 8002784: b29b uxth r3, r3 + 8002786: 86e3 strh r3, [r4, #54] ; 0x36 + txallowed = 1U; + 8002788: f04f 0901 mov.w r9, #1 + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + 800278c: 8ee3 ldrh r3, [r4, #54] ; 0x36 + 800278e: b29b uxth r3, r3 + 8002790: b9bb cbnz r3, 80027c2 + 8002792: 8fe3 ldrh r3, [r4, #62] ; 0x3e + 8002794: b29b uxth r3, r3 + 8002796: b9a3 cbnz r3, 80027c2 + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK) + 8002798: f8cd 8000 str.w r8, [sp] + 800279c: 463b mov r3, r7 + 800279e: 2201 movs r2, #1 + 80027a0: 2102 movs r1, #2 + 80027a2: 4620 mov r0, r4 + 80027a4: f7ff feec bl 8002580 + 80027a8: 2800 cmp r0, #0 + 80027aa: d135 bne.n 8002818 + if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK) + 80027ac: 4642 mov r2, r8 + 80027ae: 4639 mov r1, r7 + 80027b0: 4620 mov r0, r4 + 80027b2: f7ff ff2c bl 800260e + 80027b6: 2800 cmp r0, #0 + 80027b8: d079 beq.n 80028ae + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 80027ba: 2320 movs r3, #32 + 80027bc: 6563 str r3, [r4, #84] ; 0x54 + errorcode = HAL_ERROR; + 80027be: 2001 movs r0, #1 + 80027c0: e02b b.n 800281a + if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) + 80027c2: f1b9 0f00 cmp.w r9, #0 + 80027c6: d00f beq.n 80027e8 + 80027c8: 8ee3 ldrh r3, [r4, #54] ; 0x36 + 80027ca: b29b uxth r3, r3 + 80027cc: b163 cbz r3, 80027e8 + 80027ce: 6823 ldr r3, [r4, #0] + 80027d0: 689a ldr r2, [r3, #8] + 80027d2: 0791 lsls r1, r2, #30 + 80027d4: d508 bpl.n 80027e8 + hspi->Instance->DR = *((uint16_t *)pTxData); + 80027d6: f835 2b02 ldrh.w r2, [r5], #2 + 80027da: 60da str r2, [r3, #12] + hspi->TxXferCount--; + 80027dc: 8ee3 ldrh r3, [r4, #54] ; 0x36 + 80027de: 3b01 subs r3, #1 + 80027e0: b29b uxth r3, r3 + 80027e2: 86e3 strh r3, [r4, #54] ; 0x36 + txallowed = 0U; + 80027e4: f04f 0900 mov.w r9, #0 + if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) + 80027e8: 8fe3 ldrh r3, [r4, #62] ; 0x3e + 80027ea: b29b uxth r3, r3 + 80027ec: b163 cbz r3, 8002808 + 80027ee: 6823 ldr r3, [r4, #0] + 80027f0: 689a ldr r2, [r3, #8] + 80027f2: 07d2 lsls r2, r2, #31 + 80027f4: d508 bpl.n 8002808 + *((uint16_t *)pRxData) = hspi->Instance->DR; + 80027f6: 68db ldr r3, [r3, #12] + 80027f8: f826 3b02 strh.w r3, [r6], #2 + hspi->RxXferCount--; + 80027fc: 8fe3 ldrh r3, [r4, #62] ; 0x3e + 80027fe: 3b01 subs r3, #1 + 8002800: b29b uxth r3, r3 + 8002802: 87e3 strh r3, [r4, #62] ; 0x3e + txallowed = 1U; + 8002804: f04f 0901 mov.w r9, #1 + if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) + 8002808: 1c78 adds r0, r7, #1 + 800280a: d0bf beq.n 800278c + 800280c: f7fe fa60 bl 8000cd0 + 8002810: eba0 0008 sub.w r0, r0, r8 + 8002814: 4287 cmp r7, r0 + 8002816: d8b9 bhi.n 800278c + errorcode = HAL_TIMEOUT; + 8002818: 2003 movs r0, #3 + hspi->State = HAL_SPI_STATE_READY; + 800281a: 2301 movs r3, #1 + 800281c: f884 3051 strb.w r3, [r4, #81] ; 0x51 + __HAL_UNLOCK(hspi); + 8002820: 2300 movs r3, #0 + 8002822: f884 3050 strb.w r3, [r4, #80] ; 0x50 +} + 8002826: b005 add sp, #20 + 8002828: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + 800282c: b119 cbz r1, 8002836 + 800282e: 8ee2 ldrh r2, [r4, #54] ; 0x36 + 8002830: b292 uxth r2, r2 + 8002832: 2a01 cmp r2, #1 + 8002834: d106 bne.n 8002844 + *((__IO uint8_t*)&hspi->Instance->DR) = (*pTxData); + 8002836: f815 2b01 ldrb.w r2, [r5], #1 + 800283a: 731a strb r2, [r3, #12] + hspi->TxXferCount--; + 800283c: 8ee3 ldrh r3, [r4, #54] ; 0x36 + 800283e: 3b01 subs r3, #1 + 8002840: b29b uxth r3, r3 + 8002842: 86e3 strh r3, [r4, #54] ; 0x36 + txallowed = 1U; + 8002844: f04f 0901 mov.w r9, #1 + while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + 8002848: 8ee3 ldrh r3, [r4, #54] ; 0x36 + 800284a: b29b uxth r3, r3 + 800284c: b91b cbnz r3, 8002856 + 800284e: 8fe3 ldrh r3, [r4, #62] ; 0x3e + 8002850: b29b uxth r3, r3 + 8002852: 2b00 cmp r3, #0 + 8002854: d0a0 beq.n 8002798 + if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) + 8002856: f1b9 0f00 cmp.w r9, #0 + 800285a: d00f beq.n 800287c + 800285c: 8ee3 ldrh r3, [r4, #54] ; 0x36 + 800285e: b29b uxth r3, r3 + 8002860: b163 cbz r3, 800287c + 8002862: 6823 ldr r3, [r4, #0] + 8002864: 689a ldr r2, [r3, #8] + 8002866: 0791 lsls r1, r2, #30 + 8002868: d508 bpl.n 800287c + *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++); + 800286a: 782a ldrb r2, [r5, #0] + 800286c: 731a strb r2, [r3, #12] + hspi->TxXferCount--; + 800286e: 8ee3 ldrh r3, [r4, #54] ; 0x36 + 8002870: 3b01 subs r3, #1 + 8002872: b29b uxth r3, r3 + 8002874: 86e3 strh r3, [r4, #54] ; 0x36 + *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++); + 8002876: 3501 adds r5, #1 + txallowed = 0U; + 8002878: f04f 0900 mov.w r9, #0 + if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) + 800287c: 8fe3 ldrh r3, [r4, #62] ; 0x3e + 800287e: b29b uxth r3, r3 + 8002880: b163 cbz r3, 800289c + 8002882: 6823 ldr r3, [r4, #0] + 8002884: 689a ldr r2, [r3, #8] + 8002886: 07d2 lsls r2, r2, #31 + 8002888: d508 bpl.n 800289c + (*(uint8_t *)pRxData++) = hspi->Instance->DR; + 800288a: 68db ldr r3, [r3, #12] + 800288c: 7033 strb r3, [r6, #0] + hspi->RxXferCount--; + 800288e: 8fe3 ldrh r3, [r4, #62] ; 0x3e + 8002890: 3b01 subs r3, #1 + 8002892: b29b uxth r3, r3 + 8002894: 87e3 strh r3, [r4, #62] ; 0x3e + (*(uint8_t *)pRxData++) = hspi->Instance->DR; + 8002896: 3601 adds r6, #1 + txallowed = 1U; + 8002898: f04f 0901 mov.w r9, #1 + if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) + 800289c: 1c7b adds r3, r7, #1 + 800289e: d0d3 beq.n 8002848 + 80028a0: f7fe fa16 bl 8000cd0 + 80028a4: eba0 0008 sub.w r0, r0, r8 + 80028a8: 4287 cmp r7, r0 + 80028aa: d8cd bhi.n 8002848 + 80028ac: e7b4 b.n 8002818 + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + 80028ae: 68a3 ldr r3, [r4, #8] + 80028b0: 2b00 cmp r3, #0 + 80028b2: d1b2 bne.n 800281a + __HAL_SPI_CLEAR_OVRFLAG(hspi); + 80028b4: 6823 ldr r3, [r4, #0] + 80028b6: 9003 str r0, [sp, #12] + 80028b8: 68da ldr r2, [r3, #12] + 80028ba: 9203 str r2, [sp, #12] + 80028bc: 689b ldr r3, [r3, #8] + 80028be: 9303 str r3, [sp, #12] + 80028c0: 9b03 ldr r3, [sp, #12] + 80028c2: e7aa b.n 800281a + errorcode = HAL_BUSY; + 80028c4: 2002 movs r0, #2 + 80028c6: e7a8 b.n 800281a + __HAL_LOCK(hspi); + 80028c8: 2002 movs r0, #2 + 80028ca: e7ac b.n 8002826 + +080028cc : + return hspi->State; + 80028cc: f890 0051 ldrb.w r0, [r0, #81] ; 0x51 +} + 80028d0: 4770 bx lr + +080028d2 : + 80028d2: 4770 bx lr + +080028d4 : +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + 80028d4: 6803 ldr r3, [r0, #0] + 80028d6: 68da ldr r2, [r3, #12] + 80028d8: f042 0201 orr.w r2, r2, #1 + 80028dc: 60da str r2, [r3, #12] + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + 80028de: 681a ldr r2, [r3, #0] + 80028e0: f042 0201 orr.w r2, r2, #1 + 80028e4: 601a str r2, [r3, #0] + + /* Return function status */ + return HAL_OK; +} + 80028e6: 2000 movs r0, #0 + 80028e8: 4770 bx lr + +080028ea : + 80028ea: 4770 bx lr + +080028ec : + 80028ec: 4770 bx lr + +080028ee : + 80028ee: 4770 bx lr + +080028f0 : + 80028f0: 4770 bx lr + +080028f2 : + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + 80028f2: 6803 ldr r3, [r0, #0] + 80028f4: 691a ldr r2, [r3, #16] + 80028f6: 0791 lsls r1, r2, #30 +{ + 80028f8: b510 push {r4, lr} + 80028fa: 4604 mov r4, r0 + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + 80028fc: d50e bpl.n 800291c + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) + 80028fe: 68da ldr r2, [r3, #12] + 8002900: 0792 lsls r2, r2, #30 + 8002902: d50b bpl.n 800291c + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + 8002904: f06f 0202 mvn.w r2, #2 + 8002908: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + 800290a: 699b ldr r3, [r3, #24] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 800290c: 2201 movs r2, #1 + if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + 800290e: 079b lsls r3, r3, #30 + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 8002910: 7602 strb r2, [r0, #24] + if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + 8002912: d077 beq.n 8002a04 + { + HAL_TIM_IC_CaptureCallback(htim); + 8002914: f7ff ffea bl 80028ec + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8002918: 2300 movs r3, #0 + 800291a: 7623 strb r3, [r4, #24] + } + } + } + /* Capture compare 2 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + 800291c: 6823 ldr r3, [r4, #0] + 800291e: 691a ldr r2, [r3, #16] + 8002920: 0750 lsls r0, r2, #29 + 8002922: d510 bpl.n 8002946 + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) + 8002924: 68da ldr r2, [r3, #12] + 8002926: 0751 lsls r1, r2, #29 + 8002928: d50d bpl.n 8002946 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + 800292a: f06f 0204 mvn.w r2, #4 + 800292e: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + 8002930: 699b ldr r3, [r3, #24] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 8002932: 2202 movs r2, #2 + if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + 8002934: f413 7f40 tst.w r3, #768 ; 0x300 + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 8002938: 7622 strb r2, [r4, #24] + { + HAL_TIM_IC_CaptureCallback(htim); + 800293a: 4620 mov r0, r4 + if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + 800293c: d068 beq.n 8002a10 + HAL_TIM_IC_CaptureCallback(htim); + 800293e: f7ff ffd5 bl 80028ec + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8002942: 2300 movs r3, #0 + 8002944: 7623 strb r3, [r4, #24] + } + } + /* Capture compare 3 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + 8002946: 6823 ldr r3, [r4, #0] + 8002948: 691a ldr r2, [r3, #16] + 800294a: 0712 lsls r2, r2, #28 + 800294c: d50f bpl.n 800296e + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) + 800294e: 68da ldr r2, [r3, #12] + 8002950: 0710 lsls r0, r2, #28 + 8002952: d50c bpl.n 800296e + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + 8002954: f06f 0208 mvn.w r2, #8 + 8002958: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + 800295a: 69db ldr r3, [r3, #28] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 800295c: 2204 movs r2, #4 + if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + 800295e: 0799 lsls r1, r3, #30 + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 8002960: 7622 strb r2, [r4, #24] + { + HAL_TIM_IC_CaptureCallback(htim); + 8002962: 4620 mov r0, r4 + if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + 8002964: d05a beq.n 8002a1c + HAL_TIM_IC_CaptureCallback(htim); + 8002966: f7ff ffc1 bl 80028ec + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 800296a: 2300 movs r3, #0 + 800296c: 7623 strb r3, [r4, #24] + } + } + /* Capture compare 4 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + 800296e: 6823 ldr r3, [r4, #0] + 8002970: 691a ldr r2, [r3, #16] + 8002972: 06d2 lsls r2, r2, #27 + 8002974: d510 bpl.n 8002998 + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) + 8002976: 68da ldr r2, [r3, #12] + 8002978: 06d0 lsls r0, r2, #27 + 800297a: d50d bpl.n 8002998 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + 800297c: f06f 0210 mvn.w r2, #16 + 8002980: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + 8002982: 69db ldr r3, [r3, #28] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 8002984: 2208 movs r2, #8 + if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + 8002986: f413 7f40 tst.w r3, #768 ; 0x300 + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 800298a: 7622 strb r2, [r4, #24] + { + HAL_TIM_IC_CaptureCallback(htim); + 800298c: 4620 mov r0, r4 + if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + 800298e: d04b beq.n 8002a28 + HAL_TIM_IC_CaptureCallback(htim); + 8002990: f7ff ffac bl 80028ec + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8002994: 2300 movs r3, #0 + 8002996: 7623 strb r3, [r4, #24] + } + } + /* TIM Update event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + 8002998: 6823 ldr r3, [r4, #0] + 800299a: 691a ldr r2, [r3, #16] + 800299c: 07d1 lsls r1, r2, #31 + 800299e: d508 bpl.n 80029b2 + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) + 80029a0: 68da ldr r2, [r3, #12] + 80029a2: 07d2 lsls r2, r2, #31 + 80029a4: d505 bpl.n 80029b2 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + 80029a6: f06f 0201 mvn.w r2, #1 + 80029aa: 611a str r2, [r3, #16] + HAL_TIM_PeriodElapsedCallback(htim); + 80029ac: 4620 mov r0, r4 + 80029ae: f003 f891 bl 8005ad4 + } + } + /* TIM Break input event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + 80029b2: 6823 ldr r3, [r4, #0] + 80029b4: 691a ldr r2, [r3, #16] + 80029b6: 0610 lsls r0, r2, #24 + 80029b8: d508 bpl.n 80029cc + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) + 80029ba: 68da ldr r2, [r3, #12] + 80029bc: 0611 lsls r1, r2, #24 + 80029be: d505 bpl.n 80029cc + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + 80029c0: f06f 0280 mvn.w r2, #128 ; 0x80 + 80029c4: 611a str r2, [r3, #16] + HAL_TIMEx_BreakCallback(htim); + 80029c6: 4620 mov r0, r4 + 80029c8: f000 f8b5 bl 8002b36 + } + } + /* TIM Trigger detection event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + 80029cc: 6823 ldr r3, [r4, #0] + 80029ce: 691a ldr r2, [r3, #16] + 80029d0: 0652 lsls r2, r2, #25 + 80029d2: d508 bpl.n 80029e6 + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) + 80029d4: 68da ldr r2, [r3, #12] + 80029d6: 0650 lsls r0, r2, #25 + 80029d8: d505 bpl.n 80029e6 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + 80029da: f06f 0240 mvn.w r2, #64 ; 0x40 + 80029de: 611a str r2, [r3, #16] + HAL_TIM_TriggerCallback(htim); + 80029e0: 4620 mov r0, r4 + 80029e2: f7ff ff85 bl 80028f0 + } + } + /* TIM commutation event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + 80029e6: 6823 ldr r3, [r4, #0] + 80029e8: 691a ldr r2, [r3, #16] + 80029ea: 0691 lsls r1, r2, #26 + 80029ec: d522 bpl.n 8002a34 + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) + 80029ee: 68da ldr r2, [r3, #12] + 80029f0: 0692 lsls r2, r2, #26 + 80029f2: d51f bpl.n 8002a34 + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + 80029f4: f06f 0220 mvn.w r2, #32 + HAL_TIMEx_CommutationCallback(htim); + 80029f8: 4620 mov r0, r4 + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + 80029fa: 611a str r2, [r3, #16] + } + } +} + 80029fc: e8bd 4010 ldmia.w sp!, {r4, lr} + HAL_TIMEx_CommutationCallback(htim); + 8002a00: f000 b898 b.w 8002b34 + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002a04: f7ff ff71 bl 80028ea + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002a08: 4620 mov r0, r4 + 8002a0a: f7ff ff70 bl 80028ee + 8002a0e: e783 b.n 8002918 + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002a10: f7ff ff6b bl 80028ea + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002a14: 4620 mov r0, r4 + 8002a16: f7ff ff6a bl 80028ee + 8002a1a: e792 b.n 8002942 + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002a1c: f7ff ff65 bl 80028ea + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002a20: 4620 mov r0, r4 + 8002a22: f7ff ff64 bl 80028ee + 8002a26: e7a0 b.n 800296a + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002a28: f7ff ff5f bl 80028ea + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002a2c: 4620 mov r0, r4 + 8002a2e: f7ff ff5e bl 80028ee + 8002a32: e7af b.n 8002994 + 8002a34: bd10 pop {r4, pc} + ... + +08002a38 : +{ + uint32_t tmpcr1 = 0U; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if(IS_TIM_CC3_INSTANCE(TIMx) != RESET) + 8002a38: 4a2e ldr r2, [pc, #184] ; (8002af4 ) + tmpcr1 = TIMx->CR1; + 8002a3a: 6803 ldr r3, [r0, #0] + if(IS_TIM_CC3_INSTANCE(TIMx) != RESET) + 8002a3c: 4290 cmp r0, r2 + 8002a3e: d012 beq.n 8002a66 + 8002a40: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000 + 8002a44: d00f beq.n 8002a66 + 8002a46: f5a2 427c sub.w r2, r2, #64512 ; 0xfc00 + 8002a4a: 4290 cmp r0, r2 + 8002a4c: d00b beq.n 8002a66 + 8002a4e: f502 6280 add.w r2, r2, #1024 ; 0x400 + 8002a52: 4290 cmp r0, r2 + 8002a54: d007 beq.n 8002a66 + 8002a56: f502 6280 add.w r2, r2, #1024 ; 0x400 + 8002a5a: 4290 cmp r0, r2 + 8002a5c: d003 beq.n 8002a66 + 8002a5e: f502 4278 add.w r2, r2, #63488 ; 0xf800 + 8002a62: 4290 cmp r0, r2 + 8002a64: d11d bne.n 8002aa2 + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + 8002a66: 684a ldr r2, [r1, #4] + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 8002a68: f023 0370 bic.w r3, r3, #112 ; 0x70 + tmpcr1 |= Structure->CounterMode; + 8002a6c: 4313 orrs r3, r2 + } + + if(IS_TIM_CC1_INSTANCE(TIMx) != RESET) + 8002a6e: 4a21 ldr r2, [pc, #132] ; (8002af4 ) + 8002a70: 4290 cmp r0, r2 + 8002a72: d104 bne.n 8002a7e + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 8002a74: 68ca ldr r2, [r1, #12] + tmpcr1 &= ~TIM_CR1_CKD; + 8002a76: f423 7340 bic.w r3, r3, #768 ; 0x300 + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 8002a7a: 4313 orrs r3, r2 + 8002a7c: e028 b.n 8002ad0 + if(IS_TIM_CC1_INSTANCE(TIMx) != RESET) + 8002a7e: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000 + 8002a82: d0f7 beq.n 8002a74 + 8002a84: 4a1c ldr r2, [pc, #112] ; (8002af8 ) + 8002a86: 4290 cmp r0, r2 + 8002a88: d0f4 beq.n 8002a74 + 8002a8a: f502 6280 add.w r2, r2, #1024 ; 0x400 + 8002a8e: 4290 cmp r0, r2 + 8002a90: d0f0 beq.n 8002a74 + 8002a92: f502 6280 add.w r2, r2, #1024 ; 0x400 + 8002a96: 4290 cmp r0, r2 + 8002a98: d0ec beq.n 8002a74 + 8002a9a: f502 4278 add.w r2, r2, #63488 ; 0xf800 + 8002a9e: 4290 cmp r0, r2 + 8002aa0: d0e8 beq.n 8002a74 + 8002aa2: 4a16 ldr r2, [pc, #88] ; (8002afc ) + 8002aa4: 4290 cmp r0, r2 + 8002aa6: d0e5 beq.n 8002a74 + 8002aa8: f502 6280 add.w r2, r2, #1024 ; 0x400 + 8002aac: 4290 cmp r0, r2 + 8002aae: d0e1 beq.n 8002a74 + 8002ab0: f502 6280 add.w r2, r2, #1024 ; 0x400 + 8002ab4: 4290 cmp r0, r2 + 8002ab6: d0dd beq.n 8002a74 + 8002ab8: f5a2 3298 sub.w r2, r2, #77824 ; 0x13000 + 8002abc: 4290 cmp r0, r2 + 8002abe: d0d9 beq.n 8002a74 + 8002ac0: f502 6280 add.w r2, r2, #1024 ; 0x400 + 8002ac4: 4290 cmp r0, r2 + 8002ac6: d0d5 beq.n 8002a74 + 8002ac8: f502 6280 add.w r2, r2, #1024 ; 0x400 + 8002acc: 4290 cmp r0, r2 + 8002ace: d0d1 beq.n 8002a74 + } + + TIMx->CR1 = tmpcr1; + 8002ad0: 6003 str r3, [r0, #0] + + /* Set the Auto-reload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 8002ad2: 688b ldr r3, [r1, #8] + 8002ad4: 62c3 str r3, [r0, #44] ; 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = (uint32_t)Structure->Prescaler; + 8002ad6: 680b ldr r3, [r1, #0] + 8002ad8: 6283 str r3, [r0, #40] ; 0x28 + + if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) + 8002ada: 4b06 ldr r3, [pc, #24] ; (8002af4 ) + 8002adc: 4298 cmp r0, r3 + 8002ade: d006 beq.n 8002aee + 8002ae0: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8002ae4: 4298 cmp r0, r3 + 8002ae6: d002 beq.n 8002aee + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter(only for TIM1 and TIM8) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 8002ae8: 2301 movs r3, #1 + 8002aea: 6143 str r3, [r0, #20] +} + 8002aec: 4770 bx lr + TIMx->RCR = Structure->RepetitionCounter; + 8002aee: 690b ldr r3, [r1, #16] + 8002af0: 6303 str r3, [r0, #48] ; 0x30 + 8002af2: e7f9 b.n 8002ae8 + 8002af4: 40010000 .word 0x40010000 + 8002af8: 40000400 .word 0x40000400 + 8002afc: 40014000 .word 0x40014000 + +08002b00 : +{ + 8002b00: b510 push {r4, lr} + if(htim == NULL) + 8002b02: 4604 mov r4, r0 + 8002b04: b1a0 cbz r0, 8002b30 + if(htim->State == HAL_TIM_STATE_RESET) + 8002b06: f890 3039 ldrb.w r3, [r0, #57] ; 0x39 + 8002b0a: f003 02ff and.w r2, r3, #255 ; 0xff + 8002b0e: b91b cbnz r3, 8002b18 + htim->Lock = HAL_UNLOCKED; + 8002b10: f880 2038 strb.w r2, [r0, #56] ; 0x38 + HAL_TIM_Base_MspInit(htim); + 8002b14: f7ff fedd bl 80028d2 + htim->State= HAL_TIM_STATE_BUSY; + 8002b18: 2302 movs r3, #2 + 8002b1a: f884 3039 strb.w r3, [r4, #57] ; 0x39 + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8002b1e: 6820 ldr r0, [r4, #0] + 8002b20: 1d21 adds r1, r4, #4 + 8002b22: f7ff ff89 bl 8002a38 + htim->State= HAL_TIM_STATE_READY; + 8002b26: 2301 movs r3, #1 + 8002b28: f884 3039 strb.w r3, [r4, #57] ; 0x39 + return HAL_OK; + 8002b2c: 2000 movs r0, #0 + 8002b2e: bd10 pop {r4, pc} + return HAL_ERROR; + 8002b30: 2001 movs r0, #1 +} + 8002b32: bd10 pop {r4, pc} + +08002b34 : + 8002b34: 4770 bx lr + +08002b36 : + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + 8002b36: 4770 bx lr + +08002b38 : + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + 8002b38: b084 sub sp, #16 + 8002b3a: b538 push {r3, r4, r5, lr} + 8002b3c: ad05 add r5, sp, #20 + 8002b3e: e885 000e stmia.w r5, {r1, r2, r3} + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + 8002b42: 9b0a ldr r3, [sp, #40] ; 0x28 + 8002b44: 2b01 cmp r3, #1 +{ + 8002b46: 4604 mov r4, r0 + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + 8002b48: d126 bne.n 8002b98 + { + + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + 8002b4a: 6b83 ldr r3, [r0, #56] ; 0x38 + 8002b4c: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8002b50: 6383 str r3, [r0, #56] ; 0x38 + + /* Init The ULPI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + 8002b52: 68c3 ldr r3, [r0, #12] + 8002b54: f423 0384 bic.w r3, r3, #4325376 ; 0x420000 + 8002b58: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8002b5c: 60c3 str r3, [r0, #12] + + /* Select vbus source */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + 8002b5e: 68c3 ldr r3, [r0, #12] + 8002b60: f423 1340 bic.w r3, r3, #3145728 ; 0x300000 + 8002b64: 60c3 str r3, [r0, #12] + if(cfg.use_external_vbus == 1U) + 8002b66: 9b11 ldr r3, [sp, #68] ; 0x44 + 8002b68: 2b01 cmp r3, #1 + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; + 8002b6a: bf02 ittt eq + 8002b6c: 68c3 ldreq r3, [r0, #12] + 8002b6e: f443 1380 orreq.w r3, r3, #1048576 ; 0x100000 + 8002b72: 60c3 streq r3, [r0, #12] + } + /* Reset after a PHY select */ + USB_CoreReset(USBx); + 8002b74: f000 fbde bl 8003334 + + /* Deactivate the power down*/ + USBx->GCCFG = USB_OTG_GCCFG_PWRDWN; + } + + if(cfg.dma_enable == ENABLE) + 8002b78: 9b08 ldr r3, [sp, #32] + 8002b7a: 2b01 cmp r3, #1 + 8002b7c: d107 bne.n 8002b8e + { + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; + 8002b7e: 68a3 ldr r3, [r4, #8] + 8002b80: f043 0306 orr.w r3, r3, #6 + 8002b84: 60a3 str r3, [r4, #8] + USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + 8002b86: 68a3 ldr r3, [r4, #8] + 8002b88: f043 0320 orr.w r3, r3, #32 + 8002b8c: 60a3 str r3, [r4, #8] + } + + return HAL_OK; +} + 8002b8e: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 8002b92: 2000 movs r0, #0 + 8002b94: b004 add sp, #16 + 8002b96: 4770 bx lr + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + 8002b98: 68c3 ldr r3, [r0, #12] + 8002b9a: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8002b9e: 60c3 str r3, [r0, #12] + USB_CoreReset(USBx); + 8002ba0: f000 fbc8 bl 8003334 + USBx->GCCFG = USB_OTG_GCCFG_PWRDWN; + 8002ba4: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8002ba8: 63a3 str r3, [r4, #56] ; 0x38 + 8002baa: e7e5 b.n 8002b78 + +08002bac : + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + 8002bac: 6883 ldr r3, [r0, #8] + 8002bae: f043 0301 orr.w r3, r3, #1 + 8002bb2: 6083 str r3, [r0, #8] + return HAL_OK; +} + 8002bb4: 2000 movs r0, #0 + 8002bb6: 4770 bx lr + +08002bb8 : + * @param USBx Selected device + * @retval HAL status +*/ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + 8002bb8: 6883 ldr r3, [r0, #8] + 8002bba: f023 0301 bic.w r3, r3, #1 + 8002bbe: 6083 str r3, [r0, #8] + return HAL_OK; +} + 8002bc0: 2000 movs r0, #0 + 8002bc2: 4770 bx lr + +08002bc4 : + * @arg USB_OTG_HOST_MODE: Host mode + * @arg USB_OTG_DRD_MODE: Dual Role Device mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode) +{ + 8002bc4: b508 push {r3, lr} + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + 8002bc6: 68c3 ldr r3, [r0, #12] + + if ( mode == USB_OTG_HOST_MODE) + 8002bc8: 2901 cmp r1, #1 + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + 8002bca: f023 43c0 bic.w r3, r3, #1610612736 ; 0x60000000 + 8002bce: 60c3 str r3, [r0, #12] + if ( mode == USB_OTG_HOST_MODE) + 8002bd0: d108 bne.n 8002be4 + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + 8002bd2: 68c3 ldr r3, [r0, #12] + 8002bd4: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 + 8002bd8: 60c3 str r3, [r0, #12] + } + else if ( mode == USB_OTG_DEVICE_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + } + HAL_Delay(50U); + 8002bda: 2032 movs r0, #50 ; 0x32 + 8002bdc: f7fe f87e bl 8000cdc + + return HAL_OK; +} + 8002be0: 2000 movs r0, #0 + 8002be2: bd08 pop {r3, pc} + else if ( mode == USB_OTG_DEVICE_MODE) + 8002be4: 2900 cmp r1, #0 + 8002be6: d1f8 bne.n 8002bda + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + 8002be8: 68c3 ldr r3, [r0, #12] + 8002bea: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 + 8002bee: 60c3 str r3, [r0, #12] + 8002bf0: e7f3 b.n 8002bda + ... + +08002bf4 : + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + 8002bf4: b084 sub sp, #16 + 8002bf6: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8002bfa: 4604 mov r4, r0 + 8002bfc: a807 add r0, sp, #28 + 8002bfe: e880 000e stmia.w r0, {r1, r2, r3} + 8002c02: 9e11 ldr r6, [sp, #68] ; 0x44 + 8002c04: 9f0a ldr r7, [sp, #40] ; 0x28 + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + } +#else + if (cfg.vbus_sensing_enable == 0U) + { + USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; + 8002c06: 6ba3 ldr r3, [r4, #56] ; 0x38 + 8002c08: 4688 mov r8, r1 + if (cfg.vbus_sensing_enable == 0U) + 8002c0a: b9a6 cbnz r6, 8002c36 + USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; + 8002c0c: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 + 8002c10: 63a3 str r3, [r4, #56] ; 0x38 + USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; + } +#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */ + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + 8002c12: 2300 movs r3, #0 + 8002c14: f8c4 3e00 str.w r3, [r4, #3584] ; 0xe00 + + /* Device mode configuration */ + USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; + 8002c18: f8d4 3800 ldr.w r3, [r4, #2048] ; 0x800 + 8002c1c: f8c4 3800 str.w r3, [r4, #2048] ; 0x800 + + if(cfg.phy_itface == USB_OTG_ULPI_PHY) + 8002c20: 9b0c ldr r3, [sp, #48] ; 0x30 + 8002c22: 2b01 cmp r3, #1 + USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; + 8002c24: f504 6500 add.w r5, r4, #2048 ; 0x800 + if(cfg.phy_itface == USB_OTG_ULPI_PHY) + 8002c28: d15e bne.n 8002ce8 + { + if(cfg.speed == USB_OTG_SPEED_HIGH) + 8002c2a: 9909 ldr r1, [sp, #36] ; 0x24 + 8002c2c: b939 cbnz r1, 8002c3e + } + } + else + { + /* Set Full speed phy */ + USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL); + 8002c2e: 4620 mov r0, r4 + 8002c30: f000 f89e bl 8002d70 + 8002c34: e007 b.n 8002c46 + USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; + 8002c36: f443 2300 orr.w r3, r3, #524288 ; 0x80000 + 8002c3a: 63a3 str r3, [r4, #56] ; 0x38 + 8002c3c: e7e9 b.n 8002c12 + USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL); + 8002c3e: 4619 mov r1, r3 + 8002c40: 4620 mov r0, r4 + 8002c42: f000 f895 bl 8002d70 + } + + /* Flush the FIFOs */ + USB_FlushTxFifo(USBx , 0x10U); /* all Tx FIFOs */ + 8002c46: 2110 movs r1, #16 + 8002c48: 4620 mov r0, r4 + 8002c4a: f000 f86f bl 8002d2c + USB_FlushRxFifo(USBx); + 8002c4e: 4620 mov r0, r4 + 8002c50: f000 f87e bl 8002d50 + + /* Clear all pending Device Interrupts */ + USBx_DEVICE->DIEPMSK = 0U; + 8002c54: 2300 movs r3, #0 + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINT = 0xFFFFFFFFU; + 8002c56: f04f 32ff mov.w r2, #4294967295 + USBx_DEVICE->DIEPMSK = 0U; + 8002c5a: 612b str r3, [r5, #16] + 8002c5c: 4619 mov r1, r3 + USBx_DEVICE->DOEPMSK = 0U; + 8002c5e: 616b str r3, [r5, #20] + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK); + 8002c60: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + USBx_DEVICE->DAINT = 0xFFFFFFFFU; + 8002c64: 61aa str r2, [r5, #24] + { + USBx_INEP(i)->DIEPCTL = 0U; + } + + USBx_INEP(i)->DIEPTSIZ = 0U; + USBx_INEP(i)->DIEPINT = 0xFFU; + 8002c66: f04f 0eff mov.w lr, #255 ; 0xff + USBx_DEVICE->DAINTMSK = 0U; + 8002c6a: 61eb str r3, [r5, #28] + 8002c6c: f504 6210 add.w r2, r4, #2304 ; 0x900 + for (i = 0U; i < cfg.dev_endpoints; i++) + 8002c70: 4543 cmp r3, r8 + 8002c72: d13b bne.n 8002cec + 8002c74: 2100 movs r1, #0 + 8002c76: f504 6230 add.w r2, r4, #2816 ; 0xb00 + 8002c7a: 4608 mov r0, r1 + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK); + 8002c7c: f04f 4e90 mov.w lr, #1207959552 ; 0x48000000 + { + USBx_OUTEP(i)->DOEPCTL = 0U; + } + + USBx_OUTEP(i)->DOEPTSIZ = 0U; + USBx_OUTEP(i)->DOEPINT = 0xFFU; + 8002c80: f04f 0cff mov.w ip, #255 ; 0xff + for (i = 0U; i < cfg.dev_endpoints; i++) + 8002c84: 428b cmp r3, r1 + 8002c86: d13e bne.n 8002d06 + } + + USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); + 8002c88: 692b ldr r3, [r5, #16] + + if (cfg.dma_enable == 1U) + 8002c8a: 2f01 cmp r7, #1 + USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); + 8002c8c: f423 7380 bic.w r3, r3, #256 ; 0x100 + 8002c90: 612b str r3, [r5, #16] + if (cfg.dma_enable == 1U) + 8002c92: d108 bne.n 8002ca6 + { + /*Set threshold parameters */ + USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6); + 8002c94: 4b23 ldr r3, [pc, #140] ; (8002d24 ) + 8002c96: 632b str r3, [r5, #48] ; 0x30 + USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN); + 8002c98: 6b2b ldr r3, [r5, #48] ; 0x30 + 8002c9a: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8002c9e: f043 0303 orr.w r3, r3, #3 + 8002ca2: 632b str r3, [r5, #48] ; 0x30 + + i= USBx_DEVICE->DTHRCTL; + 8002ca4: 6b2b ldr r3, [r5, #48] ; 0x30 + } + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + 8002ca6: 2300 movs r3, #0 + 8002ca8: 61a3 str r3, [r4, #24] + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xBFFFFFFFU; + 8002caa: f06f 4380 mvn.w r3, #1073741824 ; 0x40000000 + 8002cae: 6163 str r3, [r4, #20] + + /* Enable the common interrupts */ + if (cfg.dma_enable == DISABLE) + 8002cb0: b91f cbnz r7, 8002cba + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + 8002cb2: 69a3 ldr r3, [r4, #24] + 8002cb4: f043 0310 orr.w r3, r3, #16 + 8002cb8: 61a3 str r3, [r4, #24] + } + + /* Enable interrupts matching to the Device mode ONLY */ + USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\ + 8002cba: 69a2 ldr r2, [r4, #24] + 8002cbc: 4b1a ldr r3, [pc, #104] ; (8002d28 ) + 8002cbe: 4313 orrs r3, r2 + 8002cc0: 61a3 str r3, [r4, #24] + USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\ + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\ + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + + if(cfg.Sof_enable) + 8002cc2: 9b0d ldr r3, [sp, #52] ; 0x34 + 8002cc4: b11b cbz r3, 8002cce + { + USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; + 8002cc6: 69a3 ldr r3, [r4, #24] + 8002cc8: f043 0308 orr.w r3, r3, #8 + 8002ccc: 61a3 str r3, [r4, #24] + } + + if (cfg.vbus_sensing_enable == ENABLE) + 8002cce: 2e01 cmp r6, #1 + { + USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + 8002cd0: bf01 itttt eq + 8002cd2: 69a3 ldreq r3, [r4, #24] + 8002cd4: f043 4380 orreq.w r3, r3, #1073741824 ; 0x40000000 + 8002cd8: f043 0304 orreq.w r3, r3, #4 + 8002cdc: 61a3 streq r3, [r4, #24] + } + + return HAL_OK; +} + 8002cde: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 8002ce2: 2000 movs r0, #0 + 8002ce4: b004 add sp, #16 + 8002ce6: 4770 bx lr + USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL); + 8002ce8: 2103 movs r1, #3 + 8002cea: e7a0 b.n 8002c2e + if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + 8002cec: f8d2 c000 ldr.w ip, [r2] + 8002cf0: f1bc 0f00 cmp.w ip, #0 + USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK); + 8002cf4: bfb4 ite lt + 8002cf6: 6010 strlt r0, [r2, #0] + USBx_INEP(i)->DIEPCTL = 0U; + 8002cf8: 6011 strge r1, [r2, #0] + for (i = 0U; i < cfg.dev_endpoints; i++) + 8002cfa: 3301 adds r3, #1 + USBx_INEP(i)->DIEPTSIZ = 0U; + 8002cfc: 6111 str r1, [r2, #16] + USBx_INEP(i)->DIEPINT = 0xFFU; + 8002cfe: f8c2 e008 str.w lr, [r2, #8] + 8002d02: 3220 adds r2, #32 + 8002d04: e7b4 b.n 8002c70 + if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + 8002d06: f8d2 8000 ldr.w r8, [r2] + 8002d0a: f1b8 0f00 cmp.w r8, #0 + USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK); + 8002d0e: bfb4 ite lt + 8002d10: f8c2 e000 strlt.w lr, [r2] + USBx_OUTEP(i)->DOEPCTL = 0U; + 8002d14: 6010 strge r0, [r2, #0] + for (i = 0U; i < cfg.dev_endpoints; i++) + 8002d16: 3101 adds r1, #1 + USBx_OUTEP(i)->DOEPTSIZ = 0U; + 8002d18: 6110 str r0, [r2, #16] + USBx_OUTEP(i)->DOEPINT = 0xFFU; + 8002d1a: f8c2 c008 str.w ip, [r2, #8] + 8002d1e: 3220 adds r2, #32 + 8002d20: e7b0 b.n 8002c84 + 8002d22: bf00 nop + 8002d24: 00800100 .word 0x00800100 + 8002d28: 803c3800 .word 0x803c3800 + +08002d2c : + */ +HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) +{ + uint32_t count = 0; + + USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); + 8002d2c: 0189 lsls r1, r1, #6 + 8002d2e: f041 0120 orr.w r1, r1, #32 + 8002d32: 4a06 ldr r2, [pc, #24] ; (8002d4c ) + 8002d34: 6101 str r1, [r0, #16] + + do + { + if (++count > 200000) + 8002d36: 3a01 subs r2, #1 + 8002d38: d005 beq.n 8002d46 + { + return HAL_TIMEOUT; + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + 8002d3a: 6903 ldr r3, [r0, #16] + 8002d3c: f013 0320 ands.w r3, r3, #32 + 8002d40: d1f9 bne.n 8002d36 + + return HAL_OK; + 8002d42: 4618 mov r0, r3 + 8002d44: 4770 bx lr + return HAL_TIMEOUT; + 8002d46: 2003 movs r0, #3 +} + 8002d48: 4770 bx lr + 8002d4a: bf00 nop + 8002d4c: 00030d41 .word 0x00030d41 + +08002d50 : + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t count = 0; + + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + 8002d50: 2310 movs r3, #16 + 8002d52: 4a06 ldr r2, [pc, #24] ; (8002d6c ) + 8002d54: 6103 str r3, [r0, #16] + + do + { + if (++count > 200000) + 8002d56: 3a01 subs r2, #1 + 8002d58: d005 beq.n 8002d66 + { + return HAL_TIMEOUT; + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + 8002d5a: 6903 ldr r3, [r0, #16] + 8002d5c: f013 0310 ands.w r3, r3, #16 + 8002d60: d1f9 bne.n 8002d56 + + return HAL_OK; + 8002d62: 4618 mov r0, r3 + 8002d64: 4770 bx lr + return HAL_TIMEOUT; + 8002d66: 2003 movs r0, #3 +} + 8002d68: 4770 bx lr + 8002d6a: bf00 nop + 8002d6c: 00030d41 .word 0x00030d41 + +08002d70 : + * @arg USB_OTG_SPEED_LOW: Low speed mode + * @retval Hal status + */ +HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) +{ + USBx_DEVICE->DCFG |= speed; + 8002d70: f8d0 3800 ldr.w r3, [r0, #2048] ; 0x800 + 8002d74: 4319 orrs r1, r3 + 8002d76: f8c0 1800 str.w r1, [r0, #2048] ; 0x800 + return HAL_OK; +} + 8002d7a: 2000 movs r0, #0 + 8002d7c: 4770 bx lr + +08002d7e : + */ +uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) +{ + uint8_t speed = 0U; + + if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) + 8002d7e: f500 6200 add.w r2, r0, #2048 ; 0x800 + 8002d82: f8d0 0808 ldr.w r0, [r0, #2056] ; 0x808 + 8002d86: f010 0006 ands.w r0, r0, #6 + 8002d8a: d012 beq.n 8002db2 + { + speed = USB_OTG_SPEED_HIGH; + } + else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)|| + 8002d8c: 6893 ldr r3, [r2, #8] + 8002d8e: f003 0306 and.w r3, r3, #6 + 8002d92: 2b02 cmp r3, #2 + 8002d94: d00c beq.n 8002db0 + ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ)) + 8002d96: 6893 ldr r3, [r2, #8] + 8002d98: f003 0306 and.w r3, r3, #6 + else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)|| + 8002d9c: 2b06 cmp r3, #6 + 8002d9e: d007 beq.n 8002db0 + { + speed = USB_OTG_SPEED_FULL; + } + else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) + 8002da0: 6893 ldr r3, [r2, #8] + 8002da2: f003 0306 and.w r3, r3, #6 + 8002da6: 2b04 cmp r3, #4 + { + speed = USB_OTG_SPEED_LOW; + 8002da8: bf14 ite ne + 8002daa: 2000 movne r0, #0 + 8002dac: 2002 moveq r0, #2 + 8002dae: 4770 bx lr + speed = USB_OTG_SPEED_FULL; + 8002db0: 2003 movs r0, #3 + } + + return speed; +} + 8002db2: 4770 bx lr + +08002db4 : + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + 8002db4: b530 push {r4, r5, lr} + if (ep->is_in == 1U) + 8002db6: 784b ldrb r3, [r1, #1] + 8002db8: 780c ldrb r4, [r1, #0] + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))); + 8002dba: f8d0 581c ldr.w r5, [r0, #2076] ; 0x81c + 8002dbe: f500 6200 add.w r2, r0, #2048 ; 0x800 + if (ep->is_in == 1U) + 8002dc2: 2b01 cmp r3, #1 + 8002dc4: d11b bne.n 8002dfe + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))); + 8002dc6: 40a3 lsls r3, r4 + 8002dc8: b29b uxth r3, r3 + 8002dca: 432b orrs r3, r5 + + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) + 8002dcc: f500 6010 add.w r0, r0, #2304 ; 0x900 + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))); + 8002dd0: 61d3 str r3, [r2, #28] + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) + 8002dd2: eb00 1344 add.w r3, r0, r4, lsl #5 + 8002dd6: 681a ldr r2, [r3, #0] + 8002dd8: 0412 lsls r2, r2, #16 + 8002dda: d40e bmi.n 8002dfa + { + USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18U) |\ + 8002ddc: 688a ldr r2, [r1, #8] + 8002dde: 78c8 ldrb r0, [r1, #3] + 8002de0: 681d ldr r5, [r3, #0] + 8002de2: f3c2 020a ubfx r2, r2, #0, #11 + 8002de6: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 + 8002dea: f442 4200 orr.w r2, r2, #32768 ; 0x8000 + 8002dee: ea42 4080 orr.w r0, r2, r0, lsl #18 + 8002df2: ea40 5084 orr.w r0, r0, r4, lsl #22 + 8002df6: 4328 orrs r0, r5 + 8002df8: 6018 str r0, [r3, #0] + USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18U) |\ + (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP)); + } + } + return HAL_OK; +} + 8002dfa: 2000 movs r0, #0 + 8002dfc: bd30 pop {r4, r5, pc} + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U); + 8002dfe: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8002e02: 40a3 lsls r3, r4 + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + 8002e04: f500 6030 add.w r0, r0, #2816 ; 0xb00 + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U); + 8002e08: 432b orrs r3, r5 + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + 8002e0a: eb00 1044 add.w r0, r0, r4, lsl #5 + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U); + 8002e0e: 61d3 str r3, [r2, #28] + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + 8002e10: 6803 ldr r3, [r0, #0] + 8002e12: 041b lsls r3, r3, #16 + 8002e14: d4f1 bmi.n 8002dfa + USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18U) |\ + 8002e16: 688b ldr r3, [r1, #8] + 8002e18: 78c9 ldrb r1, [r1, #3] + 8002e1a: 6802 ldr r2, [r0, #0] + 8002e1c: f3c3 030a ubfx r3, r3, #0, #11 + 8002e20: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8002e24: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8002e28: ea43 4381 orr.w r3, r3, r1, lsl #18 + 8002e2c: 4313 orrs r3, r2 + 8002e2e: 6003 str r3, [r0, #0] + 8002e30: e7e3 b.n 8002dfa + +08002e32 : + 8002e32: f000 b801 b.w 8002e38 + ... + +08002e38 : + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + 8002e38: b570 push {r4, r5, r6, lr} + uint32_t count = 0U; + + /* Disable the IN endpoint */ + if (ep->is_in == 1U) + 8002e3a: 784b ldrb r3, [r1, #1] + 8002e3c: 2b01 cmp r3, #1 +{ + 8002e3e: 460e mov r6, r1 + 8002e40: 4605 mov r5, r0 + 8002e42: 7809 ldrb r1, [r1, #0] + 8002e44: f04f 0320 mov.w r3, #32 + if (ep->is_in == 1U) + 8002e48: d126 bne.n 8002e98 + { + USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_USBAEP; + 8002e4a: f500 6210 add.w r2, r0, #2304 ; 0x900 + 8002e4e: fb13 2301 smlabb r3, r3, r1, r2 + 8002e52: 681a ldr r2, [r3, #0] + 8002e54: f422 4200 bic.w r2, r2, #32768 ; 0x8000 + 8002e58: 601a str r2, [r3, #0] + + /* sets the NAK bit for the IN endpoint */ + USBx_INEP(ep->num)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + 8002e5a: f04f 6200 mov.w r2, #134217728 ; 0x8000000 + 8002e5e: 601a str r2, [r3, #0] + + /* Disable IN endpoint */ + USBx_INEP(ep->num)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS; + 8002e60: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8002e64: 601a str r2, [r3, #0] + 8002e66: 4a1f ldr r2, [pc, #124] ; (8002ee4 ) + + do + { + if (++count > 200000U) + 8002e68: 3a01 subs r2, #1 + 8002e6a: d101 bne.n 8002e70 + { + return HAL_TIMEOUT; + 8002e6c: 2003 movs r0, #3 + 8002e6e: bd70 pop {r4, r5, r6, pc} + } + } + + /*Wait for EPDISD endpoint disabled interrupt*/ + while ((USBx_INEP(ep->num)->DIEPINT & USB_OTG_DIEPCTL_EPDIS) == USB_OTG_DIEPCTL_EPDIS); + 8002e70: 689c ldr r4, [r3, #8] + 8002e72: f014 4480 ands.w r4, r4, #1073741824 ; 0x40000000 + 8002e76: d1f7 bne.n 8002e68 + + + /* Flush any data remaining in the TxFIFO */ + USB_FlushTxFifo(USBx , 0x10U); + 8002e78: 2110 movs r1, #16 + 8002e7a: 4628 mov r0, r5 + 8002e7c: f7ff ff56 bl 8002d2c + + /* Disable endpoint interrupts */ + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num)))); + 8002e80: 7831 ldrb r1, [r6, #0] + 8002e82: f8d5 281c ldr.w r2, [r5, #2076] ; 0x81c + 8002e86: 2301 movs r3, #1 + 8002e88: 408b lsls r3, r1 + 8002e8a: b29b uxth r3, r3 + 8002e8c: ea22 0303 bic.w r3, r2, r3 + 8002e90: f8c5 381c str.w r3, [r5, #2076] ; 0x81c + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; + + /* Disable endpoint interrupts */ + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U)); + } + return HAL_OK; + 8002e94: 4620 mov r0, r4 + 8002e96: bd70 pop {r4, r5, r6, pc} + USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + 8002e98: f500 6230 add.w r2, r0, #2816 ; 0xb00 + 8002e9c: fb13 2301 smlabb r3, r3, r1, r2 + 8002ea0: 681a ldr r2, [r3, #0] + 8002ea2: f422 4200 bic.w r2, r2, #32768 ; 0x8000 + 8002ea6: 601a str r2, [r3, #0] + USBx_OUTEP(ep->num)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + 8002ea8: f04f 6200 mov.w r2, #134217728 ; 0x8000000 + 8002eac: 601a str r2, [r3, #0] + USBx_OUTEP(ep->num)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS; + 8002eae: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8002eb2: 601a str r2, [r3, #0] + 8002eb4: 4a0b ldr r2, [pc, #44] ; (8002ee4 ) + if (++count > 200000U) + 8002eb6: 3a01 subs r2, #1 + 8002eb8: d0d8 beq.n 8002e6c + while ((USBx_OUTEP(ep->num)->DOEPINT & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS); + 8002eba: 6898 ldr r0, [r3, #8] + 8002ebc: f010 0010 ands.w r0, r0, #16 + 8002ec0: d1f9 bne.n 8002eb6 + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; + 8002ec2: f8d5 3804 ldr.w r3, [r5, #2052] ; 0x804 + 8002ec6: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8002eca: f8c5 3804 str.w r3, [r5, #2052] ; 0x804 + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U)); + 8002ece: f8d5 381c ldr.w r3, [r5, #2076] ; 0x81c + 8002ed2: f44f 3280 mov.w r2, #65536 ; 0x10000 + 8002ed6: 408a lsls r2, r1 + 8002ed8: ea23 0302 bic.w r3, r3, r2 + 8002edc: f8c5 381c str.w r3, [r5, #2076] ; 0x81c + +} + 8002ee0: bd70 pop {r4, r5, r6, pc} + 8002ee2: bf00 nop + 8002ee4: 00030d41 .word 0x00030d41 + +08002ee8 : + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) +{ + 8002ee8: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + uint16_t pktcnt = 0U; + + /* IN endpoint */ + if (ep->is_in == 1U) + 8002eea: 784b ldrb r3, [r1, #1] + 8002eec: 780c ldrb r4, [r1, #0] + 8002eee: 2b01 cmp r3, #1 + 8002ef0: 694b ldr r3, [r1, #20] + 8002ef2: d177 bne.n 8002fe4 + 8002ef4: 2620 movs r6, #32 + 8002ef6: f500 6510 add.w r5, r0, #2304 ; 0x900 + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 8002efa: fb16 5404 smlabb r4, r6, r4, r5 + 8002efe: 6926 ldr r6, [r4, #16] + if (ep->xfer_len == 0U) + 8002f00: 2b00 cmp r3, #0 + 8002f02: d138 bne.n 8002f76 + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 8002f04: f026 56ff bic.w r6, r6, #534773760 ; 0x1fe00000 + 8002f08: f426 16c0 bic.w r6, r6, #1572864 ; 0x180000 + 8002f0c: 6126 str r6, [r4, #16] + USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ; + 8002f0e: 6926 ldr r6, [r4, #16] + 8002f10: f446 2600 orr.w r6, r6, #524288 ; 0x80000 + 8002f14: 6126 str r6, [r4, #16] + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + 8002f16: 6926 ldr r6, [r4, #16] + 8002f18: 0cf6 lsrs r6, r6, #19 + 8002f1a: 04f6 lsls r6, r6, #19 + 8002f1c: 6126 str r6, [r4, #16] + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29U)); + } + } + + if (dma == 1U) + 8002f1e: 2a01 cmp r2, #1 + 8002f20: d150 bne.n 8002fc4 + { + USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr); + 8002f22: 780c ldrb r4, [r1, #0] + 8002f24: 690e ldr r6, [r1, #16] + 8002f26: eb05 1444 add.w r4, r5, r4, lsl #5 + 8002f2a: 6166 str r6, [r4, #20] + USBx_DEVICE->DIEPEMPMSK |= 1U << ep->num; + } + } + } + + if (ep->type == EP_TYPE_ISOC) + 8002f2c: 78ce ldrb r6, [r1, #3] + 8002f2e: 2e01 cmp r6, #1 + 8002f30: d10f bne.n 8002f52 + { + if ((USBx_DEVICE->DSTS & ( 1U << 8U )) == 0U) + 8002f32: f8d0 4808 ldr.w r4, [r0, #2056] ; 0x808 + 8002f36: 780f ldrb r7, [r1, #0] + 8002f38: f414 7f80 tst.w r4, #256 ; 0x100 + 8002f3c: f04f 0420 mov.w r4, #32 + { + USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + 8002f40: fb14 5407 smlabb r4, r4, r7, r5 + 8002f44: 6827 ldr r7, [r4, #0] + 8002f46: bf0c ite eq + 8002f48: f047 5700 orreq.w r7, r7, #536870912 ; 0x20000000 + } + else + { + USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + 8002f4c: f047 5780 orrne.w r7, r7, #268435456 ; 0x10000000 + 8002f50: 6027 str r7, [r4, #0] + } + } + + /* EP enable, IN data in FIFO */ + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + 8002f52: 780f ldrb r7, [r1, #0] + 8002f54: eb05 1547 add.w r5, r5, r7, lsl #5 + + if (ep->type == EP_TYPE_ISOC) + 8002f58: 2e01 cmp r6, #1 + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + 8002f5a: 682c ldr r4, [r5, #0] + 8002f5c: f044 4404 orr.w r4, r4, #2214592512 ; 0x84000000 + 8002f60: 602c str r4, [r5, #0] + if (ep->type == EP_TYPE_ISOC) + 8002f62: d105 bne.n 8002f70 + { + USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma); + 8002f64: 9200 str r2, [sp, #0] + 8002f66: b29b uxth r3, r3 + 8002f68: 463a mov r2, r7 + 8002f6a: 68c9 ldr r1, [r1, #12] + 8002f6c: f000 f8ef bl 800314e + } + /* EP enable */ + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + } + return HAL_OK; +} + 8002f70: 2000 movs r0, #0 + 8002f72: b003 add sp, #12 + 8002f74: bdf0 pop {r4, r5, r6, r7, pc} + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + 8002f76: 0cf6 lsrs r6, r6, #19 + 8002f78: 04f6 lsls r6, r6, #19 + 8002f7a: 6126 str r6, [r4, #16] + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 8002f7c: 6926 ldr r6, [r4, #16] + USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1U)/ ep->maxpacket) << 19U)) ; + 8002f7e: 688f ldr r7, [r1, #8] + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 8002f80: f026 56ff bic.w r6, r6, #534773760 ; 0x1fe00000 + 8002f84: f426 16c0 bic.w r6, r6, #1572864 ; 0x180000 + 8002f88: 6126 str r6, [r4, #16] + USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1U)/ ep->maxpacket) << 19U)) ; + 8002f8a: 19de adds r6, r3, r7 + 8002f8c: 3e01 subs r6, #1 + 8002f8e: fbb6 f7f7 udiv r7, r6, r7 + 8002f92: 4e37 ldr r6, [pc, #220] ; (8003070 ) + 8002f94: f8d4 e010 ldr.w lr, [r4, #16] + 8002f98: ea06 46c7 and.w r6, r6, r7, lsl #19 + 8002f9c: ea46 060e orr.w r6, r6, lr + 8002fa0: 6126 str r6, [r4, #16] + USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + 8002fa2: 6927 ldr r7, [r4, #16] + 8002fa4: f3c3 0612 ubfx r6, r3, #0, #19 + 8002fa8: 433e orrs r6, r7 + 8002faa: 6126 str r6, [r4, #16] + if (ep->type == EP_TYPE_ISOC) + 8002fac: 78ce ldrb r6, [r1, #3] + 8002fae: 2e01 cmp r6, #1 + 8002fb0: d15a bne.n 8003068 + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + 8002fb2: 6926 ldr r6, [r4, #16] + 8002fb4: f026 46c0 bic.w r6, r6, #1610612736 ; 0x60000000 + 8002fb8: 6126 str r6, [r4, #16] + USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29U)); + 8002fba: 6926 ldr r6, [r4, #16] + 8002fbc: f046 5600 orr.w r6, r6, #536870912 ; 0x20000000 + 8002fc0: 6126 str r6, [r4, #16] + 8002fc2: e7ac b.n 8002f1e + if (ep->type != EP_TYPE_ISOC) + 8002fc4: 78ce ldrb r6, [r1, #3] + 8002fc6: 2e01 cmp r6, #1 + 8002fc8: d0b3 beq.n 8002f32 + if (ep->xfer_len > 0U) + 8002fca: 2b00 cmp r3, #0 + 8002fcc: d0ae beq.n 8002f2c + USBx_DEVICE->DIEPEMPMSK |= 1U << ep->num; + 8002fce: f891 e000 ldrb.w lr, [r1] + 8002fd2: f8d0 7834 ldr.w r7, [r0, #2100] ; 0x834 + 8002fd6: 2401 movs r4, #1 + 8002fd8: fa04 f40e lsl.w r4, r4, lr + 8002fdc: 433c orrs r4, r7 + 8002fde: f8c0 4834 str.w r4, [r0, #2100] ; 0x834 + 8002fe2: e7a3 b.n 8002f2c + USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + 8002fe4: f500 6530 add.w r5, r0, #2816 ; 0xb00 + 8002fe8: eb05 1444 add.w r4, r5, r4, lsl #5 + 8002fec: 6925 ldr r5, [r4, #16] + 8002fee: 0ced lsrs r5, r5, #19 + 8002ff0: 04ed lsls r5, r5, #19 + 8002ff2: 6125 str r5, [r4, #16] + USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + 8002ff4: 6925 ldr r5, [r4, #16] + 8002ff6: f025 55ff bic.w r5, r5, #534773760 ; 0x1fe00000 + 8002ffa: f425 15c0 bic.w r5, r5, #1572864 ; 0x180000 + 8002ffe: 6125 str r5, [r4, #16] + 8003000: 688d ldr r5, [r1, #8] + if (ep->xfer_len == 0U) + 8003002: b9fb cbnz r3, 8003044 + USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + 8003004: 6923 ldr r3, [r4, #16] + 8003006: f3c5 0512 ubfx r5, r5, #0, #19 + 800300a: 431d orrs r5, r3 + 800300c: 6125 str r5, [r4, #16] + USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U)); + 800300e: 6923 ldr r3, [r4, #16] + 8003010: f443 2300 orr.w r3, r3, #524288 ; 0x80000 + 8003014: 6123 str r3, [r4, #16] + if (dma == 1U) + 8003016: 2a01 cmp r2, #1 + USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff; + 8003018: bf04 itt eq + 800301a: 68cb ldreq r3, [r1, #12] + 800301c: 6163 streq r3, [r4, #20] + if (ep->type == EP_TYPE_ISOC) + 800301e: 78cb ldrb r3, [r1, #3] + 8003020: 2b01 cmp r3, #1 + 8003022: d10a bne.n 800303a + if ((USBx_DEVICE->DSTS & ( 1U << 8U )) == 0U) + 8003024: f8d0 3808 ldr.w r3, [r0, #2056] ; 0x808 + 8003028: f413 7f80 tst.w r3, #256 ; 0x100 + USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + 800302c: 6823 ldr r3, [r4, #0] + 800302e: bf0c ite eq + 8003030: f043 5300 orreq.w r3, r3, #536870912 ; 0x20000000 + USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + 8003034: f043 5380 orrne.w r3, r3, #268435456 ; 0x10000000 + 8003038: 6023 str r3, [r4, #0] + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + 800303a: 6823 ldr r3, [r4, #0] + 800303c: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 + 8003040: 6023 str r3, [r4, #0] + return HAL_OK; + 8003042: e795 b.n 8002f70 + USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19U)); + 8003044: 4e0a ldr r6, [pc, #40] ; (8003070 ) + 8003046: 6927 ldr r7, [r4, #16] + pktcnt = (ep->xfer_len + ep->maxpacket -1U)/ ep->maxpacket; + 8003048: 442b add r3, r5 + 800304a: 3b01 subs r3, #1 + 800304c: fbb3 f3f5 udiv r3, r3, r5 + USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19U)); + 8003050: ea06 46c3 and.w r6, r6, r3, lsl #19 + 8003054: 433e orrs r6, r7 + 8003056: 6126 str r6, [r4, #16] + USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); + 8003058: b29b uxth r3, r3 + 800305a: 6926 ldr r6, [r4, #16] + 800305c: 435d muls r5, r3 + 800305e: f3c5 0512 ubfx r5, r5, #0, #19 + 8003062: 4335 orrs r5, r6 + 8003064: 6125 str r5, [r4, #16] + 8003066: e7d6 b.n 8003016 + if (dma == 1U) + 8003068: 2a01 cmp r2, #1 + 800306a: d1ae bne.n 8002fca + 800306c: e759 b.n 8002f22 + 800306e: bf00 nop + 8003070: 1ff80000 .word 0x1ff80000 + +08003074 : + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) +{ + /* IN endpoint */ + if (ep->is_in == 1U) + 8003074: 784b ldrb r3, [r1, #1] + 8003076: 2b01 cmp r3, #1 +{ + 8003078: b570 push {r4, r5, r6, lr} + 800307a: 780b ldrb r3, [r1, #0] + 800307c: 694d ldr r5, [r1, #20] + if (ep->is_in == 1U) + 800307e: d143 bne.n 8003108 + 8003080: 2420 movs r4, #32 + 8003082: f500 6610 add.w r6, r0, #2304 ; 0x900 + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 8003086: fb14 6303 smlabb r3, r4, r3, r6 + 800308a: 691c ldr r4, [r3, #16] + if (ep->xfer_len == 0U) + 800308c: b9cd cbnz r5, 80030c2 + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 800308e: f024 54ff bic.w r4, r4, #534773760 ; 0x1fe00000 + 8003092: f424 14c0 bic.w r4, r4, #1572864 ; 0x180000 + 8003096: 611c str r4, [r3, #16] + USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ; + 8003098: 691c ldr r4, [r3, #16] + 800309a: f444 2400 orr.w r4, r4, #524288 ; 0x80000 + 800309e: 611c str r4, [r3, #16] + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + 80030a0: 691c ldr r4, [r3, #16] + 80030a2: 0ce4 lsrs r4, r4, #19 + 80030a4: 04e4 lsls r4, r4, #19 + 80030a6: 611c str r4, [r3, #16] + USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + + } + + /* EP enable, IN data in FIFO */ + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + 80030a8: 780d ldrb r5, [r1, #0] + 80030aa: eb06 1345 add.w r3, r6, r5, lsl #5 + + if (dma == 1) + 80030ae: 2a01 cmp r2, #1 + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + 80030b0: 681c ldr r4, [r3, #0] + 80030b2: f044 4404 orr.w r4, r4, #2214592512 ; 0x84000000 + 80030b6: 601c str r4, [r3, #0] + if (dma == 1) + 80030b8: d11b bne.n 80030f2 + { + USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr); + 80030ba: 690a ldr r2, [r1, #16] + 80030bc: 615a str r2, [r3, #20] + + /* EP enable */ + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + } + return HAL_OK; +} + 80030be: 2000 movs r0, #0 + 80030c0: bd70 pop {r4, r5, r6, pc} + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + 80030c2: 0ce4 lsrs r4, r4, #19 + 80030c4: 04e4 lsls r4, r4, #19 + 80030c6: 611c str r4, [r3, #16] + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 80030c8: 691c ldr r4, [r3, #16] + 80030ca: f024 54ff bic.w r4, r4, #534773760 ; 0x1fe00000 + 80030ce: f424 14c0 bic.w r4, r4, #1572864 ; 0x180000 + 80030d2: 611c str r4, [r3, #16] + if(ep->xfer_len > ep->maxpacket) + 80030d4: 688c ldr r4, [r1, #8] + 80030d6: 42a5 cmp r5, r4 + ep->xfer_len = ep->maxpacket; + 80030d8: bf88 it hi + 80030da: 614c strhi r4, [r1, #20] + USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ; + 80030dc: 691c ldr r4, [r3, #16] + 80030de: f444 2400 orr.w r4, r4, #524288 ; 0x80000 + 80030e2: 611c str r4, [r3, #16] + USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + 80030e4: 694c ldr r4, [r1, #20] + 80030e6: 691d ldr r5, [r3, #16] + 80030e8: f3c4 0412 ubfx r4, r4, #0, #19 + 80030ec: 432c orrs r4, r5 + 80030ee: 611c str r4, [r3, #16] + 80030f0: e7da b.n 80030a8 + if (ep->xfer_len > 0U) + 80030f2: 694b ldr r3, [r1, #20] + 80030f4: 2b00 cmp r3, #0 + 80030f6: d0e2 beq.n 80030be + USBx_DEVICE->DIEPEMPMSK |= 1U << (ep->num); + 80030f8: f8d0 2834 ldr.w r2, [r0, #2100] ; 0x834 + 80030fc: 2301 movs r3, #1 + 80030fe: 40ab lsls r3, r5 + 8003100: 4313 orrs r3, r2 + 8003102: f8c0 3834 str.w r3, [r0, #2100] ; 0x834 + 8003106: e7da b.n 80030be + USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + 8003108: f500 6030 add.w r0, r0, #2816 ; 0xb00 + 800310c: eb00 1043 add.w r0, r0, r3, lsl #5 + 8003110: 6903 ldr r3, [r0, #16] + 8003112: 0cdb lsrs r3, r3, #19 + 8003114: 04db lsls r3, r3, #19 + 8003116: 6103 str r3, [r0, #16] + USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + 8003118: 6903 ldr r3, [r0, #16] + 800311a: f023 53ff bic.w r3, r3, #534773760 ; 0x1fe00000 + 800311e: f423 13c0 bic.w r3, r3, #1572864 ; 0x180000 + 8003122: 6103 str r3, [r0, #16] + 8003124: 688b ldr r3, [r1, #8] + if (ep->xfer_len > 0U) + 8003126: b105 cbz r5, 800312a + ep->xfer_len = ep->maxpacket; + 8003128: 614b str r3, [r1, #20] + USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U)); + 800312a: 6904 ldr r4, [r0, #16] + 800312c: f444 2400 orr.w r4, r4, #524288 ; 0x80000 + 8003130: 6104 str r4, [r0, #16] + USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); + 8003132: 6904 ldr r4, [r0, #16] + 8003134: f3c3 0312 ubfx r3, r3, #0, #19 + 8003138: 4323 orrs r3, r4 + if (dma == 1U) + 800313a: 2a01 cmp r2, #1 + USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); + 800313c: 6103 str r3, [r0, #16] + USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff); + 800313e: bf04 itt eq + 8003140: 68cb ldreq r3, [r1, #12] + 8003142: 6143 streq r3, [r0, #20] + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + 8003144: 6803 ldr r3, [r0, #0] + 8003146: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 + 800314a: 6003 str r3, [r0, #0] + 800314c: e7b7 b.n 80030be + +0800314e : + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) +{ + 800314e: b510 push {r4, lr} + 8003150: f89d 4008 ldrb.w r4, [sp, #8] + uint32_t count32b = 0U , i = 0U; + + if (dma == 0U) + 8003154: b94c cbnz r4, 800316a + { + count32b = (len + 3U) / 4U; + 8003156: 3303 adds r3, #3 + for (i = 0U; i < count32b; i++, src += 4U) + { + USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src); + 8003158: f500 5080 add.w r0, r0, #4096 ; 0x1000 + 800315c: f023 0303 bic.w r3, r3, #3 + 8003160: eb00 3202 add.w r2, r0, r2, lsl #12 + 8003164: 440b add r3, r1 + for (i = 0U; i < count32b; i++, src += 4U) + 8003166: 4299 cmp r1, r3 + 8003168: d101 bne.n 800316e + } + } + return HAL_OK; +} + 800316a: 2000 movs r0, #0 + 800316c: bd10 pop {r4, pc} + USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src); + 800316e: f851 0b04 ldr.w r0, [r1], #4 + 8003172: 6010 str r0, [r2, #0] + 8003174: e7f7 b.n 8003166 + +08003176 : + * @retval pointer to destination buffer + */ +void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +{ + uint32_t i=0U; + uint32_t count32b = (len + 3U) / 4U; + 8003176: 3203 adds r2, #3 + 8003178: f022 0203 bic.w r2, r2, #3 + 800317c: 440a add r2, r1 + + for ( i = 0U; i < count32b; i++, dest += 4U ) + { + *(__packed uint32_t *)dest = USBx_DFIFO(0U); + 800317e: f500 5080 add.w r0, r0, #4096 ; 0x1000 + for ( i = 0U; i < count32b; i++, dest += 4U ) + 8003182: 4291 cmp r1, r2 + 8003184: d101 bne.n 800318a + + } + return ((void *)dest); +} + 8003186: 4608 mov r0, r1 + 8003188: 4770 bx lr + *(__packed uint32_t *)dest = USBx_DFIFO(0U); + 800318a: 6803 ldr r3, [r0, #0] + 800318c: f841 3b04 str.w r3, [r1], #4 + 8003190: e7f7 b.n 8003182 + +08003192 : + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) +{ + if (ep->is_in == 1U) + 8003192: 784b ldrb r3, [r1, #1] + 8003194: 780a ldrb r2, [r1, #0] + 8003196: 2b01 cmp r3, #1 + 8003198: f04f 0320 mov.w r3, #32 + 800319c: d10b bne.n 80031b6 + { + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0U) + 800319e: f500 6010 add.w r0, r0, #2304 ; 0x900 + 80031a2: fb13 0002 smlabb r0, r3, r2, r0 + 80031a6: 6803 ldr r3, [r0, #0] + 80031a8: 2b00 cmp r3, #0 + 80031aa: db0b blt.n 80031c4 + } + else + { + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0U) + { + USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + 80031ac: 6803 ldr r3, [r0, #0] + 80031ae: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 + 80031b2: 6003 str r3, [r0, #0] + 80031b4: e006 b.n 80031c4 + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0U) + 80031b6: f500 6030 add.w r0, r0, #2816 ; 0xb00 + 80031ba: fb13 0002 smlabb r0, r3, r2, r0 + 80031be: 6803 ldr r3, [r0, #0] + 80031c0: 2b00 cmp r3, #0 + 80031c2: daf3 bge.n 80031ac + } + USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + 80031c4: 6803 ldr r3, [r0, #0] + 80031c6: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 + 80031ca: 6003 str r3, [r0, #0] + } + return HAL_OK; +} + 80031cc: 2000 movs r0, #0 + 80031ce: 4770 bx lr + +080031d0 : + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + if (ep->is_in == 1U) + 80031d0: 784b ldrb r3, [r1, #1] + 80031d2: 780a ldrb r2, [r1, #0] + 80031d4: 2b01 cmp r3, #1 + { + USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + 80031d6: bf0c ite eq + 80031d8: f500 6010 addeq.w r0, r0, #2304 ; 0x900 + USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + else + { + USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + 80031dc: f500 6030 addne.w r0, r0, #2816 ; 0xb00 + 80031e0: 2320 movs r3, #32 + 80031e2: fb13 0002 smlabb r0, r3, r2, r0 + 80031e6: 6803 ldr r3, [r0, #0] + 80031e8: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 + 80031ec: 6003 str r3, [r0, #0] + if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) + 80031ee: 78cb ldrb r3, [r1, #3] + 80031f0: 3b02 subs r3, #2 + 80031f2: 2b01 cmp r3, #1 + { + USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + 80031f4: bf9e ittt ls + 80031f6: 6803 ldrls r3, [r0, #0] + 80031f8: f043 5380 orrls.w r3, r3, #268435456 ; 0x10000000 + 80031fc: 6003 strls r3, [r0, #0] + } + } + return HAL_OK; +} + 80031fe: 2000 movs r0, #0 + 8003200: 4770 bx lr + +08003202 : + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address) +{ + USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD); + 8003202: f8d0 3800 ldr.w r3, [r0, #2048] ; 0x800 + 8003206: f423 63fe bic.w r3, r3, #2032 ; 0x7f0 + 800320a: f8c0 3800 str.w r3, [r0, #2048] ; 0x800 + USBx_DEVICE->DCFG |= (address << 4U) & USB_OTG_DCFG_DAD ; + 800320e: f8d0 3800 ldr.w r3, [r0, #2048] ; 0x800 + 8003212: 0109 lsls r1, r1, #4 + 8003214: f401 61fe and.w r1, r1, #2032 ; 0x7f0 + 8003218: 4319 orrs r1, r3 + 800321a: f8c0 1800 str.w r1, [r0, #2048] ; 0x800 + + return HAL_OK; +} + 800321e: 2000 movs r0, #0 + 8003220: 4770 bx lr + +08003222 : + * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) +{ + 8003222: b508 push {r3, lr} + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ; + 8003224: f8d0 3804 ldr.w r3, [r0, #2052] ; 0x804 + 8003228: f023 0302 bic.w r3, r3, #2 + 800322c: f8c0 3804 str.w r3, [r0, #2052] ; 0x804 + HAL_Delay(3U); + 8003230: 2003 movs r0, #3 + 8003232: f7fd fd53 bl 8000cdc + + return HAL_OK; +} + 8003236: 2000 movs r0, #0 + 8003238: bd08 pop {r3, pc} + +0800323a : + * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) +{ + 800323a: b508 push {r3, lr} + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ; + 800323c: f8d0 3804 ldr.w r3, [r0, #2052] ; 0x804 + 8003240: f043 0302 orr.w r3, r3, #2 + 8003244: f8c0 3804 str.w r3, [r0, #2052] ; 0x804 + HAL_Delay(3U); + 8003248: 2003 movs r0, #3 + 800324a: f7fd fd47 bl 8000cdc + + return HAL_OK; +} + 800324e: 2000 movs r0, #0 + 8003250: bd08 pop {r3, pc} + +08003252 : + */ +uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t v = 0U; + + v = USBx->GINTSTS; + 8003252: 6942 ldr r2, [r0, #20] + v &= USBx->GINTMSK; + 8003254: 6980 ldr r0, [r0, #24] + return v; +} + 8003256: 4010 ands r0, r2 + 8003258: 4770 bx lr + +0800325a : + * @retval HAL status + */ +uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t v; + v = USBx_DEVICE->DAINT; + 800325a: f8d0 3818 ldr.w r3, [r0, #2072] ; 0x818 + 800325e: f500 6000 add.w r0, r0, #2048 ; 0x800 + v &= USBx_DEVICE->DAINTMSK; + 8003262: 69c0 ldr r0, [r0, #28] + 8003264: 4018 ands r0, r3 + return ((v & 0xffff0000U) >> 16U); +} + 8003266: 0c00 lsrs r0, r0, #16 + 8003268: 4770 bx lr + +0800326a : + * @retval HAL status + */ +uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t v; + v = USBx_DEVICE->DAINT; + 800326a: f8d0 3818 ldr.w r3, [r0, #2072] ; 0x818 + 800326e: f500 6000 add.w r0, r0, #2048 ; 0x800 + v &= USBx_DEVICE->DAINTMSK; + 8003272: 69c0 ldr r0, [r0, #28] + 8003274: 4018 ands r0, r3 + return ((v & 0xFFFFU)); +} + 8003276: b280 uxth r0, r0 + 8003278: 4770 bx lr + +0800327a : + * @retval Device OUT EP Interrupt register + */ +uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) +{ + uint32_t v; + v = USBx_OUTEP(epnum)->DOEPINT; + 800327a: f500 6330 add.w r3, r0, #2816 ; 0xb00 + 800327e: eb03 1141 add.w r1, r3, r1, lsl #5 + v &= USBx_DEVICE->DOEPMSK; + 8003282: f500 6000 add.w r0, r0, #2048 ; 0x800 + v = USBx_OUTEP(epnum)->DOEPINT; + 8003286: 688a ldr r2, [r1, #8] + v &= USBx_DEVICE->DOEPMSK; + 8003288: 6940 ldr r0, [r0, #20] + return v; +} + 800328a: 4010 ands r0, r2 + 800328c: 4770 bx lr + +0800328e : + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) +{ + 800328e: b510 push {r4, lr} + uint32_t v, msk, emp; + + msk = USBx_DEVICE->DIEPMSK; + 8003290: f8d0 4810 ldr.w r4, [r0, #2064] ; 0x810 + emp = USBx_DEVICE->DIEPEMPMSK; + 8003294: f8d0 3834 ldr.w r3, [r0, #2100] ; 0x834 + msk |= ((emp >> epnum) & 0x1U) << 7U; + v = USBx_INEP(epnum)->DIEPINT & msk; + 8003298: eb00 1041 add.w r0, r0, r1, lsl #5 + msk |= ((emp >> epnum) & 0x1U) << 7U; + 800329c: 40cb lsrs r3, r1 + v = USBx_INEP(epnum)->DIEPINT & msk; + 800329e: f500 6010 add.w r0, r0, #2304 ; 0x900 + msk |= ((emp >> epnum) & 0x1U) << 7U; + 80032a2: 01db lsls r3, r3, #7 + v = USBx_INEP(epnum)->DIEPINT & msk; + 80032a4: 6880 ldr r0, [r0, #8] + msk |= ((emp >> epnum) & 0x1U) << 7U; + 80032a6: b2db uxtb r3, r3 + 80032a8: 4323 orrs r3, r4 + return v; +} + 80032aa: 4018 ands r0, r3 + 80032ac: bd10 pop {r4, pc} + +080032ae : + * 0 : Host + * 1 : Device + */ +uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) +{ + return ((USBx->GINTSTS ) & 0x1U); + 80032ae: 6940 ldr r0, [r0, #20] +} + 80032b0: f000 0001 and.w r0, r0, #1 + 80032b4: 4770 bx lr + +080032b6 : + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) +{ + /* Set the MPS of the IN EP based on the enumeration speed */ + USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; + 80032b6: f8d0 3900 ldr.w r3, [r0, #2304] ; 0x900 + 80032ba: f423 63ff bic.w r3, r3, #2040 ; 0x7f8 + 80032be: f023 0307 bic.w r3, r3, #7 + 80032c2: f8c0 3900 str.w r3, [r0, #2304] ; 0x900 + + if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) + 80032c6: f500 6300 add.w r3, r0, #2048 ; 0x800 + 80032ca: 689a ldr r2, [r3, #8] + 80032cc: f002 0206 and.w r2, r2, #6 + 80032d0: 2a04 cmp r2, #4 + { + USBx_INEP(0U)->DIEPCTL |= 3U; + 80032d2: bf02 ittt eq + 80032d4: f8d0 2900 ldreq.w r2, [r0, #2304] ; 0x900 + 80032d8: f042 0203 orreq.w r2, r2, #3 + 80032dc: f8c0 2900 streq.w r2, [r0, #2304] ; 0x900 + } + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; + 80032e0: 685a ldr r2, [r3, #4] + 80032e2: f442 7280 orr.w r2, r2, #256 ; 0x100 + 80032e6: 605a str r2, [r3, #4] + + return HAL_OK; +} + 80032e8: 2000 movs r0, #0 + 80032ea: 4770 bx lr + +080032ec : + * 1 : DMA feature used + * @param psetup pointer to setup packet + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) +{ + 80032ec: b510 push {r4, lr} + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + 80032ee: 2400 movs r4, #0 + 80032f0: f8c0 4b10 str.w r4, [r0, #2832] ; 0xb10 + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U)) ; + 80032f4: f8d0 4b10 ldr.w r4, [r0, #2832] ; 0xb10 + 80032f8: f444 2400 orr.w r4, r4, #524288 ; 0x80000 + 80032fc: f8c0 4b10 str.w r4, [r0, #2832] ; 0xb10 + USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + 8003300: f8d0 4b10 ldr.w r4, [r0, #2832] ; 0xb10 + 8003304: f044 0418 orr.w r4, r4, #24 + 8003308: f8c0 4b10 str.w r4, [r0, #2832] ; 0xb10 + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + 800330c: f8d0 4b10 ldr.w r4, [r0, #2832] ; 0xb10 + + if (dma == 1U) + 8003310: 2901 cmp r1, #1 + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + 8003312: f500 6330 add.w r3, r0, #2816 ; 0xb00 + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + 8003316: f044 44c0 orr.w r4, r4, #1610612736 ; 0x60000000 + { + USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; + /* EP enable */ + USBx_OUTEP(0U)->DOEPCTL = 0x80008000U; + 800331a: bf08 it eq + 800331c: f04f 2380 moveq.w r3, #2147516416 ; 0x80008000 + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + 8003320: f8c0 4b10 str.w r4, [r0, #2832] ; 0xb10 + USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; + 8003324: bf04 itt eq + 8003326: f8c0 2b14 streq.w r2, [r0, #2836] ; 0xb14 + USBx_OUTEP(0U)->DOEPCTL = 0x80008000U; + 800332a: f8c0 3b00 streq.w r3, [r0, #2816] ; 0xb00 + } + + return HAL_OK; +} + 800332e: 2000 movs r0, #0 + 8003330: bd10 pop {r4, pc} + ... + +08003334 : + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) +{ + 8003334: 4b0a ldr r3, [pc, #40] ; (8003360 ) + uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + if (++count > 200000U) + 8003336: 3b01 subs r3, #1 + 8003338: d101 bne.n 800333e + { + return HAL_TIMEOUT; + 800333a: 2003 movs r0, #3 + 800333c: 4770 bx lr + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + 800333e: 6902 ldr r2, [r0, #16] + 8003340: 2a00 cmp r2, #0 + 8003342: daf8 bge.n 8003336 + + /* Core Soft Reset */ + count = 0U; + USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + 8003344: 6903 ldr r3, [r0, #16] + 8003346: 4a06 ldr r2, [pc, #24] ; (8003360 ) + 8003348: f043 0301 orr.w r3, r3, #1 + 800334c: 6103 str r3, [r0, #16] + + do + { + if (++count > 200000U) + 800334e: 3a01 subs r2, #1 + 8003350: d0f3 beq.n 800333a + { + return HAL_TIMEOUT; + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + 8003352: 6903 ldr r3, [r0, #16] + 8003354: f013 0301 ands.w r3, r3, #1 + 8003358: d1f9 bne.n 800334e + + return HAL_OK; + 800335a: 4618 mov r0, r3 +} + 800335c: 4770 bx lr + 800335e: bf00 nop + 8003360: 00030d41 .word 0x00030d41 + +08003364 : + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + 8003364: f8d0 3218 ldr.w r3, [r0, #536] ; 0x218 + + if(pdev->pClassData != NULL) + 8003368: b11b cbz r3, 8003372 + { + + hcdc->TxState = 0; + 800336a: 2000 movs r0, #0 + 800336c: f8c3 0214 str.w r0, [r3, #532] ; 0x214 + + return USBD_OK; + 8003370: 4770 bx lr + } + else + { + return USBD_FAIL; + 8003372: 2002 movs r0, #2 + } +} + 8003374: 4770 bx lr + +08003376 : + */ +static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + if((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFF)) + 8003376: f8d0 321c ldr.w r3, [r0, #540] ; 0x21c +{ + 800337a: b510 push {r4, lr} + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + 800337c: f8d0 4218 ldr.w r4, [r0, #536] ; 0x218 + if((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFF)) + 8003380: b15b cbz r3, 800339a + 8003382: f894 0200 ldrb.w r0, [r4, #512] ; 0x200 + 8003386: 28ff cmp r0, #255 ; 0xff + 8003388: d007 beq.n 800339a + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, + 800338a: 689b ldr r3, [r3, #8] + 800338c: f894 2201 ldrb.w r2, [r4, #513] ; 0x201 + 8003390: 4621 mov r1, r4 + 8003392: 4798 blx r3 + (uint8_t *)hcdc->data, + hcdc->CmdLength); + hcdc->CmdOpCode = 0xFF; + 8003394: 23ff movs r3, #255 ; 0xff + 8003396: f884 3200 strb.w r3, [r4, #512] ; 0x200 + + } + return USBD_OK; +} + 800339a: 2000 movs r0, #0 + 800339c: bd10 pop {r4, pc} + ... + +080033a0 : + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) +{ + *length = sizeof (USBD_CDC_CfgFSDesc); + 80033a0: 2343 movs r3, #67 ; 0x43 + 80033a2: 8003 strh r3, [r0, #0] + return USBD_CDC_CfgFSDesc; +} + 80033a4: 4800 ldr r0, [pc, #0] ; (80033a8 ) + 80033a6: 4770 bx lr + 80033a8: 200000b8 .word 0x200000b8 + +080033ac : + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) +{ + *length = sizeof (USBD_CDC_CfgHSDesc); + 80033ac: 2343 movs r3, #67 ; 0x43 + 80033ae: 8003 strh r3, [r0, #0] + return USBD_CDC_CfgHSDesc; +} + 80033b0: 4800 ldr r0, [pc, #0] ; (80033b4 ) + 80033b2: 4770 bx lr + 80033b4: 200000fc .word 0x200000fc + +080033b8 : + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length) +{ + *length = sizeof (USBD_CDC_OtherSpeedCfgDesc); + 80033b8: 2343 movs r3, #67 ; 0x43 + 80033ba: 8003 strh r3, [r0, #0] + return USBD_CDC_OtherSpeedCfgDesc; +} + 80033bc: 4800 ldr r0, [pc, #0] ; (80033c0 ) + 80033be: 4770 bx lr + 80033c0: 2000014c .word 0x2000014c + +080033c4 : +* @param length : pointer data length +* @retval pointer to descriptor buffer +*/ +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length) +{ + *length = sizeof (USBD_CDC_DeviceQualifierDesc); + 80033c4: 230a movs r3, #10 + 80033c6: 8003 strh r3, [r0, #0] + return USBD_CDC_DeviceQualifierDesc; +} + 80033c8: 4800 ldr r0, [pc, #0] ; (80033cc ) + 80033ca: 4770 bx lr + 80033cc: 20000140 .word 0x20000140 + +080033d0 : +{ + 80033d0: b538 push {r3, r4, r5, lr} + 80033d2: 4605 mov r5, r0 + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + 80033d4: f8d0 4218 ldr.w r4, [r0, #536] ; 0x218 + hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum); + 80033d8: f002 feb6 bl 8006148 + if(pdev->pClassData != NULL) + 80033dc: f8d5 3218 ldr.w r3, [r5, #536] ; 0x218 + hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum); + 80033e0: f8c4 020c str.w r0, [r4, #524] ; 0x20c + if(pdev->pClassData != NULL) + 80033e4: b14b cbz r3, 80033fa + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); + 80033e6: f8d5 321c ldr.w r3, [r5, #540] ; 0x21c + 80033ea: f8d4 0204 ldr.w r0, [r4, #516] ; 0x204 + 80033ee: 68db ldr r3, [r3, #12] + 80033f0: f504 7103 add.w r1, r4, #524 ; 0x20c + 80033f4: 4798 blx r3 + return USBD_OK; + 80033f6: 2000 movs r0, #0 + 80033f8: bd38 pop {r3, r4, r5, pc} + return USBD_FAIL; + 80033fa: 2002 movs r0, #2 +} + 80033fc: bd38 pop {r3, r4, r5, pc} + ... + +08003400 : +{ + 8003400: b5f8 push {r3, r4, r5, r6, r7, lr} + switch (req->bmRequest & USB_REQ_TYPE_MASK) + 8003402: 780f ldrb r7, [r1, #0] + 8003404: f017 0360 ands.w r3, r7, #96 ; 0x60 +{ + 8003408: 4606 mov r6, r0 + 800340a: 460c mov r4, r1 + switch (req->bmRequest & USB_REQ_TYPE_MASK) + 800340c: d023 beq.n 8003456 + 800340e: 2b20 cmp r3, #32 + 8003410: d119 bne.n 8003446 + if (req->wLength) + 8003412: 88ca ldrh r2, [r1, #6] + 8003414: 784b ldrb r3, [r1, #1] + 8003416: b1c2 cbz r2, 800344a + if (req->bmRequest & 0x80) + 8003418: 0639 lsls r1, r7, #24 + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + 800341a: f8d0 5218 ldr.w r5, [r0, #536] ; 0x218 + if (req->bmRequest & 0x80) + 800341e: d50b bpl.n 8003438 + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + 8003420: f8d0 121c ldr.w r1, [r0, #540] ; 0x21c + 8003424: 4618 mov r0, r3 + 8003426: 688f ldr r7, [r1, #8] + 8003428: 4629 mov r1, r5 + 800342a: 47b8 blx r7 + USBD_CtlSendData (pdev, + 800342c: 88e2 ldrh r2, [r4, #6] + 800342e: 4629 mov r1, r5 + 8003430: 4630 mov r0, r6 + USBD_CtlSendData (pdev, + 8003432: f000 fb9a bl 8003b6a + break; + 8003436: e006 b.n 8003446 + hcdc->CmdOpCode = req->bRequest; + 8003438: f885 3200 strb.w r3, [r5, #512] ; 0x200 + hcdc->CmdLength = req->wLength; + 800343c: f885 2201 strb.w r2, [r5, #513] ; 0x201 + USBD_CtlPrepareRx (pdev, + 8003440: 4629 mov r1, r5 + 8003442: f000 fba7 bl 8003b94 +} + 8003446: 2000 movs r0, #0 + 8003448: bdf8 pop {r3, r4, r5, r6, r7, pc} + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + 800344a: f8d0 021c ldr.w r0, [r0, #540] ; 0x21c + 800344e: 6884 ldr r4, [r0, #8] + 8003450: 4618 mov r0, r3 + 8003452: 47a0 blx r4 + 8003454: e7f7 b.n 8003446 + switch (req->bRequest) + 8003456: 784b ldrb r3, [r1, #1] + 8003458: 2b0a cmp r3, #10 + 800345a: d1f4 bne.n 8003446 + USBD_CtlSendData (pdev, + 800345c: 2201 movs r2, #1 + 800345e: 4901 ldr r1, [pc, #4] ; (8003464 ) + 8003460: e7e7 b.n 8003432 + 8003462: bf00 nop + 8003464: 200002bc .word 0x200002bc + +08003468 : +{ + 8003468: b510 push {r4, lr} + USBD_LL_CloseEP(pdev, + 800346a: 2181 movs r1, #129 ; 0x81 +{ + 800346c: 4604 mov r4, r0 + USBD_LL_CloseEP(pdev, + 800346e: f002 fe03 bl 8006078 + USBD_LL_CloseEP(pdev, + 8003472: 2101 movs r1, #1 + 8003474: 4620 mov r0, r4 + 8003476: f002 fdff bl 8006078 + USBD_LL_CloseEP(pdev, + 800347a: 2182 movs r1, #130 ; 0x82 + 800347c: 4620 mov r0, r4 + 800347e: f002 fdfb bl 8006078 + if(pdev->pClassData != NULL) + 8003482: f8d4 3218 ldr.w r3, [r4, #536] ; 0x218 + 8003486: b153 cbz r3, 800349e + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); + 8003488: f8d4 321c ldr.w r3, [r4, #540] ; 0x21c + 800348c: 685b ldr r3, [r3, #4] + 800348e: 4798 blx r3 + USBD_free(pdev->pClassData); + 8003490: f8d4 0218 ldr.w r0, [r4, #536] ; 0x218 + 8003494: f002 ff06 bl 80062a4 + pdev->pClassData = NULL; + 8003498: 2300 movs r3, #0 + 800349a: f8c4 3218 str.w r3, [r4, #536] ; 0x218 +} + 800349e: 2000 movs r0, #0 + 80034a0: bd10 pop {r4, pc} + +080034a2 : +{ + 80034a2: b5f8 push {r3, r4, r5, r6, r7, lr} + if(pdev->dev_speed == USBD_SPEED_HIGH ) + 80034a4: 7c03 ldrb r3, [r0, #16] +{ + 80034a6: 4604 mov r4, r0 + if(pdev->dev_speed == USBD_SPEED_HIGH ) + 80034a8: bb7b cbnz r3, 800350a + USBD_LL_OpenEP(pdev, + 80034aa: f44f 7300 mov.w r3, #512 ; 0x200 + 80034ae: 2202 movs r2, #2 + 80034b0: 2181 movs r1, #129 ; 0x81 + 80034b2: f002 fdd1 bl 8006058 + USBD_LL_OpenEP(pdev, + 80034b6: f44f 7300 mov.w r3, #512 ; 0x200 + USBD_LL_OpenEP(pdev, + 80034ba: 2202 movs r2, #2 + 80034bc: 2101 movs r1, #1 + 80034be: 4620 mov r0, r4 + 80034c0: f002 fdca bl 8006058 + USBD_LL_OpenEP(pdev, + 80034c4: 2308 movs r3, #8 + 80034c6: 2203 movs r2, #3 + 80034c8: 2182 movs r1, #130 ; 0x82 + 80034ca: 4620 mov r0, r4 + 80034cc: f002 fdc4 bl 8006058 + pdev->pClassData = USBD_malloc(sizeof (USBD_CDC_HandleTypeDef)); + 80034d0: f44f 7007 mov.w r0, #540 ; 0x21c + 80034d4: f002 fede bl 8006294 + 80034d8: 4606 mov r6, r0 + 80034da: f8c4 0218 str.w r0, [r4, #536] ; 0x218 + if(pdev->pClassData == NULL) + 80034de: b320 cbz r0, 800352a + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); + 80034e0: f8d4 321c ldr.w r3, [r4, #540] ; 0x21c + 80034e4: 681b ldr r3, [r3, #0] + 80034e6: 4798 blx r3 + if(pdev->dev_speed == USBD_SPEED_HIGH ) + 80034e8: 7c27 ldrb r7, [r4, #16] + hcdc->TxState =0; + 80034ea: 2500 movs r5, #0 + 80034ec: f8c6 5214 str.w r5, [r6, #532] ; 0x214 + hcdc->RxState =0; + 80034f0: f8c6 5218 str.w r5, [r6, #536] ; 0x218 + if(pdev->dev_speed == USBD_SPEED_HIGH ) + 80034f4: b987 cbnz r7, 8003518 + USBD_LL_PrepareReceive(pdev, + 80034f6: f44f 7300 mov.w r3, #512 ; 0x200 + 80034fa: f8d6 2204 ldr.w r2, [r6, #516] ; 0x204 + 80034fe: 2101 movs r1, #1 + 8003500: 4620 mov r0, r4 + 8003502: f002 fe13 bl 800612c + uint8_t ret = 0; + 8003506: 4638 mov r0, r7 + 8003508: bdf8 pop {r3, r4, r5, r6, r7, pc} + USBD_LL_OpenEP(pdev, + 800350a: 2340 movs r3, #64 ; 0x40 + 800350c: 2202 movs r2, #2 + 800350e: 2181 movs r1, #129 ; 0x81 + 8003510: f002 fda2 bl 8006058 + USBD_LL_OpenEP(pdev, + 8003514: 2340 movs r3, #64 ; 0x40 + 8003516: e7d0 b.n 80034ba + USBD_LL_PrepareReceive(pdev, + 8003518: 2340 movs r3, #64 ; 0x40 + 800351a: f8d6 2204 ldr.w r2, [r6, #516] ; 0x204 + 800351e: 2101 movs r1, #1 + 8003520: 4620 mov r0, r4 + 8003522: f002 fe03 bl 800612c + uint8_t ret = 0; + 8003526: 4628 mov r0, r5 + 8003528: bdf8 pop {r3, r4, r5, r6, r7, pc} + ret = 1; + 800352a: 2001 movs r0, #1 +} + 800352c: bdf8 pop {r3, r4, r5, r6, r7, pc} + +0800352e : +uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops) +{ + uint8_t ret = USBD_FAIL; + + if(fops != NULL) + 800352e: b119 cbz r1, 8003538 + { + pdev->pUserData= fops; + 8003530: f8c0 121c str.w r1, [r0, #540] ; 0x21c + ret = USBD_OK; + 8003534: 2000 movs r0, #0 + 8003536: 4770 bx lr + uint8_t ret = USBD_FAIL; + 8003538: 2002 movs r0, #2 + } + + return ret; +} + 800353a: 4770 bx lr + +0800353c : + */ +uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, + uint8_t *pbuff, + uint16_t length) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + 800353c: f8d0 3218 ldr.w r3, [r0, #536] ; 0x218 + + hcdc->TxBuffer = pbuff; + hcdc->TxLength = length; + + return USBD_OK; +} + 8003540: 2000 movs r0, #0 + hcdc->TxBuffer = pbuff; + 8003542: f8c3 1208 str.w r1, [r3, #520] ; 0x208 + hcdc->TxLength = length; + 8003546: f8c3 2210 str.w r2, [r3, #528] ; 0x210 +} + 800354a: 4770 bx lr + +0800354c : +uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, + uint8_t *pbuff) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + hcdc->RxBuffer = pbuff; + 800354c: f8d0 3218 ldr.w r3, [r0, #536] ; 0x218 + + return USBD_OK; +} + 8003550: 2000 movs r0, #0 + hcdc->RxBuffer = pbuff; + 8003552: f8c3 1204 str.w r1, [r3, #516] ; 0x204 +} + 8003556: 4770 bx lr + +08003558 : + * @param epnum: endpoint number + * @retval status + */ +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + 8003558: f8d0 2218 ldr.w r2, [r0, #536] ; 0x218 +{ + 800355c: b510 push {r4, lr} + + if(pdev->pClassData != NULL) + 800355e: b172 cbz r2, 800357e + { + if(hcdc->TxState == 0) + 8003560: f8d2 4214 ldr.w r4, [r2, #532] ; 0x214 + 8003564: 2301 movs r3, #1 + 8003566: b964 cbnz r4, 8003582 + { + /* Tx Transfer in progress */ + hcdc->TxState = 1; + 8003568: f8c2 3214 str.w r3, [r2, #532] ; 0x214 + + /* Transmit next packet */ + USBD_LL_Transmit(pdev, + 800356c: 2181 movs r1, #129 ; 0x81 + 800356e: f8b2 3210 ldrh.w r3, [r2, #528] ; 0x210 + 8003572: f8d2 2208 ldr.w r2, [r2, #520] ; 0x208 + 8003576: f002 fdcb bl 8006110 + CDC_IN_EP, + hcdc->TxBuffer, + hcdc->TxLength); + + return USBD_OK; + 800357a: 4620 mov r0, r4 + 800357c: bd10 pop {r4, pc} + return USBD_BUSY; + } + } + else + { + return USBD_FAIL; + 800357e: 2002 movs r0, #2 + 8003580: bd10 pop {r4, pc} + return USBD_BUSY; + 8003582: 4618 mov r0, r3 + } +} + 8003584: bd10 pop {r4, pc} + +08003586 : + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + 8003586: f8d0 2218 ldr.w r2, [r0, #536] ; 0x218 +{ + 800358a: b510 push {r4, lr} + + /* Suspend or Resume USB Out process */ + if(pdev->pClassData != NULL) + 800358c: b162 cbz r2, 80035a8 + { + if(pdev->dev_speed == USBD_SPEED_HIGH ) + 800358e: 7c04 ldrb r4, [r0, #16] + 8003590: b944 cbnz r4, 80035a4 + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + 8003592: f44f 7300 mov.w r3, #512 ; 0x200 + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + 8003596: f8d2 2204 ldr.w r2, [r2, #516] ; 0x204 + 800359a: 2101 movs r1, #1 + 800359c: f002 fdc6 bl 800612c + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + return USBD_OK; + 80035a0: 2000 movs r0, #0 + 80035a2: bd10 pop {r4, pc} + USBD_LL_PrepareReceive(pdev, + 80035a4: 2340 movs r3, #64 ; 0x40 + 80035a6: e7f6 b.n 8003596 + } + else + { + return USBD_FAIL; + 80035a8: 2002 movs r0, #2 + } +} + 80035aa: bd10 pop {r4, pc} + +080035ac : +* @param pdesc: Descriptor structure address +* @param id: Low level core index +* @retval None +*/ +USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) +{ + 80035ac: b508 push {r3, lr} + /* Check whether the USB Host handle is valid */ + if(pdev == NULL) + 80035ae: b180 cbz r0, 80035d2 + USBD_ErrLog("Invalid Device handle"); + return USBD_FAIL; + } + + /* Unlink previous class*/ + if(pdev->pClass != NULL) + 80035b0: f8d0 3214 ldr.w r3, [r0, #532] ; 0x214 + 80035b4: b113 cbz r3, 80035bc + { + pdev->pClass = NULL; + 80035b6: 2300 movs r3, #0 + 80035b8: f8c0 3214 str.w r3, [r0, #532] ; 0x214 + } + + /* Assign USBD Descriptors */ + if(pdesc != NULL) + 80035bc: b109 cbz r1, 80035c2 + { + pdev->pDesc = pdesc; + 80035be: f8c0 1210 str.w r1, [r0, #528] ; 0x210 + } + + /* Set Device initial State */ + pdev->dev_state = USBD_STATE_DEFAULT; + 80035c2: 2301 movs r3, #1 + 80035c4: f880 31fc strb.w r3, [r0, #508] ; 0x1fc + pdev->id = id; + 80035c8: 7002 strb r2, [r0, #0] + /* Initialize low level driver */ + USBD_LL_Init(pdev); + 80035ca: f002 fd03 bl 8005fd4 + + return USBD_OK; + 80035ce: 2000 movs r0, #0 + 80035d0: bd08 pop {r3, pc} + return USBD_FAIL; + 80035d2: 2002 movs r0, #2 +} + 80035d4: bd08 pop {r3, pc} + +080035d6 : + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) +{ + USBD_StatusTypeDef status = USBD_OK; + if(pclass != 0) + 80035d6: b119 cbz r1, 80035e0 + { + /* link the class to the USB Device handle */ + pdev->pClass = pclass; + 80035d8: f8c0 1214 str.w r1, [r0, #532] ; 0x214 + status = USBD_OK; + 80035dc: 2000 movs r0, #0 + 80035de: 4770 bx lr + } + else + { + USBD_ErrLog("Invalid Class handle"); + status = USBD_FAIL; + 80035e0: 2002 movs r0, #2 + } + + return status; +} + 80035e2: 4770 bx lr + +080035e4 : + * Start the USB Device Core. + * @param pdev: Device Handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev) +{ + 80035e4: b508 push {r3, lr} + + /* Start the low level driver */ + USBD_LL_Start(pdev); + 80035e6: f002 fd29 bl 800603c + + return USBD_OK; +} + 80035ea: 2000 movs r0, #0 + 80035ec: bd08 pop {r3, pc} + +080035ee : +* @param cfgidx: configuration index +* @retval status +*/ + +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + 80035ee: b508 push {r3, lr} + USBD_StatusTypeDef ret = USBD_FAIL; + + if(pdev->pClass != NULL) + 80035f0: f8d0 3214 ldr.w r3, [r0, #532] ; 0x214 + 80035f4: b90b cbnz r3, 80035fa + USBD_StatusTypeDef ret = USBD_FAIL; + 80035f6: 2002 movs r0, #2 + 80035f8: bd08 pop {r3, pc} + { + /* Set configuration and Start the Class*/ + if(pdev->pClass->Init(pdev, cfgidx) == 0) + 80035fa: 681b ldr r3, [r3, #0] + 80035fc: 4798 blx r3 + 80035fe: 2800 cmp r0, #0 + 8003600: d1f9 bne.n 80035f6 + { + ret = USBD_OK; + } + } + return ret; +} + 8003602: bd08 pop {r3, pc} + +08003604 : +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status: USBD_StatusTypeDef +*/ +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + 8003604: b508 push {r3, lr} + /* Clear configuration and De-initialize the Class process*/ + pdev->pClass->DeInit(pdev, cfgidx); + 8003606: f8d0 3214 ldr.w r3, [r0, #532] ; 0x214 + 800360a: 685b ldr r3, [r3, #4] + 800360c: 4798 blx r3 + return USBD_OK; +} + 800360e: 2000 movs r0, #0 + 8003610: bd08 pop {r3, pc} + +08003612 : +* Handle the setup stage +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) +{ + 8003612: b538 push {r3, r4, r5, lr} + 8003614: 4604 mov r4, r0 + + USBD_ParseSetupRequest(&pdev->request, psetup); + 8003616: f500 7502 add.w r5, r0, #520 ; 0x208 + 800361a: 4628 mov r0, r5 + 800361c: f000 fa75 bl 8003b0a + + pdev->ep0_state = USBD_EP0_SETUP; + 8003620: 2301 movs r3, #1 + pdev->ep0_data_len = pdev->request.wLength; + + switch (pdev->request.bmRequest & 0x1F) + 8003622: f894 1208 ldrb.w r1, [r4, #520] ; 0x208 + pdev->ep0_state = USBD_EP0_SETUP; + 8003626: f8c4 31f4 str.w r3, [r4, #500] ; 0x1f4 + pdev->ep0_data_len = pdev->request.wLength; + 800362a: f8b4 320e ldrh.w r3, [r4, #526] ; 0x20e + 800362e: f8c4 31f8 str.w r3, [r4, #504] ; 0x1f8 + switch (pdev->request.bmRequest & 0x1F) + 8003632: f001 031f and.w r3, r1, #31 + 8003636: 2b01 cmp r3, #1 + 8003638: d00e beq.n 8003658 + 800363a: d307 bcc.n 800364c + 800363c: 2b02 cmp r3, #2 + 800363e: d010 beq.n 8003662 + case USB_REQ_RECIPIENT_ENDPOINT: + USBD_StdEPReq(pdev, &pdev->request); + break; + + default: + USBD_LL_StallEP(pdev , pdev->request.bmRequest & 0x80); + 8003640: f001 0180 and.w r1, r1, #128 ; 0x80 + 8003644: 4620 mov r0, r4 + 8003646: f002 fd25 bl 8006094 + break; + 800364a: e003 b.n 8003654 + USBD_StdDevReq (pdev, &pdev->request); + 800364c: 4629 mov r1, r5 + 800364e: 4620 mov r0, r4 + 8003650: f000 f8e6 bl 8003820 + } + return USBD_OK; +} + 8003654: 2000 movs r0, #0 + 8003656: bd38 pop {r3, r4, r5, pc} + USBD_StdItfReq(pdev, &pdev->request); + 8003658: 4629 mov r1, r5 + 800365a: 4620 mov r0, r4 + 800365c: f000 f9da bl 8003a14 + break; + 8003660: e7f8 b.n 8003654 + USBD_StdEPReq(pdev, &pdev->request); + 8003662: 4629 mov r1, r5 + 8003664: 4620 mov r0, r4 + 8003666: f000 f9ed bl 8003a44 + break; + 800366a: e7f3 b.n 8003654 + +0800366c : +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata) +{ + 800366c: b538 push {r3, r4, r5, lr} + 800366e: 4604 mov r4, r0 + 8003670: 4615 mov r5, r2 + USBD_EndpointTypeDef *pep; + + if(epnum == 0) + 8003672: bb11 cbnz r1, 80036ba + { + pep = &pdev->ep_out[0]; + + if ( pdev->ep0_state == USBD_EP0_DATA_OUT) + 8003674: f8d0 31f4 ldr.w r3, [r0, #500] ; 0x1f4 + 8003678: 2b03 cmp r3, #3 + 800367a: d10f bne.n 800369c + { + if(pep->rem_length > pep->maxpacket) + 800367c: f8d0 310c ldr.w r3, [r0, #268] ; 0x10c + 8003680: f8d0 2110 ldr.w r2, [r0, #272] ; 0x110 + 8003684: 4293 cmp r3, r2 + 8003686: d90b bls.n 80036a0 + { + pep->rem_length -= pep->maxpacket; + 8003688: 1a9b subs r3, r3, r2 + + USBD_CtlContinueRx (pdev, + pdata, + MIN(pep->rem_length ,pep->maxpacket)); + 800368a: 429a cmp r2, r3 + 800368c: bf28 it cs + 800368e: 461a movcs r2, r3 + pep->rem_length -= pep->maxpacket; + 8003690: f8c0 310c str.w r3, [r0, #268] ; 0x10c + USBD_CtlContinueRx (pdev, + 8003694: b292 uxth r2, r2 + 8003696: 4629 mov r1, r5 + 8003698: f000 fa8b bl 8003bb2 + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->DataOut(pdev, epnum); + } + return USBD_OK; +} + 800369c: 2000 movs r0, #0 + 800369e: bd38 pop {r3, r4, r5, pc} + if((pdev->pClass->EP0_RxReady != NULL)&& + 80036a0: f8d0 3214 ldr.w r3, [r0, #532] ; 0x214 + 80036a4: 691b ldr r3, [r3, #16] + 80036a6: b123 cbz r3, 80036b2 + 80036a8: f890 21fc ldrb.w r2, [r0, #508] ; 0x1fc + 80036ac: 2a03 cmp r2, #3 + 80036ae: d100 bne.n 80036b2 + pdev->pClass->EP0_RxReady(pdev); + 80036b0: 4798 blx r3 + USBD_CtlSendStatus(pdev); + 80036b2: 4620 mov r0, r4 + 80036b4: f000 fa85 bl 8003bc2 + 80036b8: e7f0 b.n 800369c + else if((pdev->pClass->DataOut != NULL)&& + 80036ba: f8d0 3214 ldr.w r3, [r0, #532] ; 0x214 + 80036be: 699b ldr r3, [r3, #24] + 80036c0: 2b00 cmp r3, #0 + 80036c2: d0eb beq.n 800369c + 80036c4: f890 21fc ldrb.w r2, [r0, #508] ; 0x1fc + 80036c8: 2a03 cmp r2, #3 + 80036ca: d1e7 bne.n 800369c + pdev->pClass->DataOut(pdev, epnum); + 80036cc: 4798 blx r3 + 80036ce: e7e5 b.n 800369c + +080036d0 : +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev ,uint8_t epnum, uint8_t *pdata) +{ + 80036d0: b570 push {r4, r5, r6, lr} + 80036d2: 4613 mov r3, r2 + 80036d4: 4604 mov r4, r0 + USBD_EndpointTypeDef *pep; + + if(epnum == 0) + 80036d6: 460e mov r6, r1 + 80036d8: 2900 cmp r1, #0 + 80036da: d13d bne.n 8003758 + { + pep = &pdev->ep_in[0]; + + if ( pdev->ep0_state == USBD_EP0_DATA_IN) + 80036dc: f8d0 21f4 ldr.w r2, [r0, #500] ; 0x1f4 + 80036e0: 2a02 cmp r2, #2 + 80036e2: d10f bne.n 8003704 + { + if(pep->rem_length > pep->maxpacket) + 80036e4: 69c5 ldr r5, [r0, #28] + 80036e6: 6a02 ldr r2, [r0, #32] + 80036e8: 4295 cmp r5, r2 + 80036ea: d914 bls.n 8003716 + { + pep->rem_length -= pep->maxpacket; + 80036ec: 1aaa subs r2, r5, r2 + 80036ee: 61c2 str r2, [r0, #28] + + USBD_CtlContinueSendData (pdev, + 80036f0: 4619 mov r1, r3 + 80036f2: b292 uxth r2, r2 + 80036f4: f000 fa46 bl 8003b84 + pdata, + pep->rem_length); + + /* Prepare endpoint for premature end of transfer */ + USBD_LL_PrepareReceive (pdev, + 80036f8: 4633 mov r3, r6 + + USBD_CtlContinueSendData(pdev , NULL, 0); + pdev->ep0_data_len = 0; + + /* Prepare endpoint for premature end of transfer */ + USBD_LL_PrepareReceive (pdev, + 80036fa: 461a mov r2, r3 + 80036fc: 4619 mov r1, r3 + 80036fe: 4620 mov r0, r4 + 8003700: f002 fd14 bl 800612c + } + USBD_CtlReceiveStatus(pdev); + } + } + } + if (pdev->dev_test_mode == 1) + 8003704: f894 3200 ldrb.w r3, [r4, #512] ; 0x200 + 8003708: 2b01 cmp r3, #1 + 800370a: d102 bne.n 8003712 + { + USBD_RunTestMode(pdev); + pdev->dev_test_mode = 0; + 800370c: 2300 movs r3, #0 + 800370e: f884 3200 strb.w r3, [r4, #512] ; 0x200 + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->DataIn(pdev, epnum); + } + return USBD_OK; +} + 8003712: 2000 movs r0, #0 + 8003714: bd70 pop {r4, r5, r6, pc} + if((pep->total_length % pep->maxpacket == 0) && + 8003716: 6983 ldr r3, [r0, #24] + 8003718: fbb3 f5f2 udiv r5, r3, r2 + 800371c: fb02 3515 mls r5, r2, r5, r3 + 8003720: b965 cbnz r5, 800373c + 8003722: 429a cmp r2, r3 + 8003724: d80a bhi.n 800373c + (pep->total_length >= pep->maxpacket) && + 8003726: f8d0 21f8 ldr.w r2, [r0, #504] ; 0x1f8 + 800372a: 4293 cmp r3, r2 + 800372c: d206 bcs.n 800373c + USBD_CtlContinueSendData(pdev , NULL, 0); + 800372e: 462a mov r2, r5 + 8003730: f000 fa28 bl 8003b84 + pdev->ep0_data_len = 0; + 8003734: f8c4 51f8 str.w r5, [r4, #504] ; 0x1f8 + USBD_LL_PrepareReceive (pdev, + 8003738: 462b mov r3, r5 + 800373a: e7de b.n 80036fa + if((pdev->pClass->EP0_TxSent != NULL)&& + 800373c: f8d4 3214 ldr.w r3, [r4, #532] ; 0x214 + 8003740: 68db ldr r3, [r3, #12] + 8003742: b12b cbz r3, 8003750 + 8003744: f894 21fc ldrb.w r2, [r4, #508] ; 0x1fc + 8003748: 2a03 cmp r2, #3 + 800374a: d101 bne.n 8003750 + pdev->pClass->EP0_TxSent(pdev); + 800374c: 4620 mov r0, r4 + 800374e: 4798 blx r3 + USBD_CtlReceiveStatus(pdev); + 8003750: 4620 mov r0, r4 + 8003752: f000 fa41 bl 8003bd8 + 8003756: e7d5 b.n 8003704 + else if((pdev->pClass->DataIn != NULL)&& + 8003758: f8d0 3214 ldr.w r3, [r0, #532] ; 0x214 + 800375c: 695b ldr r3, [r3, #20] + 800375e: 2b00 cmp r3, #0 + 8003760: d0d7 beq.n 8003712 + 8003762: f890 21fc ldrb.w r2, [r0, #508] ; 0x1fc + 8003766: 2a03 cmp r2, #3 + 8003768: d1d3 bne.n 8003712 + pdev->pClass->DataIn(pdev, epnum); + 800376a: 4798 blx r3 + 800376c: e7d1 b.n 8003712 + +0800376e : +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) +{ + 800376e: b538 push {r3, r4, r5, lr} + /* Open EP0 OUT */ + USBD_LL_OpenEP(pdev, + 8003770: 2200 movs r2, #0 +{ + 8003772: 4604 mov r4, r0 + USBD_LL_OpenEP(pdev, + 8003774: 4611 mov r1, r2 + 0x00, + USBD_EP_TYPE_CTRL, + USB_MAX_EP0_SIZE); + + pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; + 8003776: 2540 movs r5, #64 ; 0x40 + USBD_LL_OpenEP(pdev, + 8003778: 2340 movs r3, #64 ; 0x40 + 800377a: f002 fc6d bl 8006058 + + /* Open EP0 IN */ + USBD_LL_OpenEP(pdev, + 800377e: 462b mov r3, r5 + pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; + 8003780: f8c4 5110 str.w r5, [r4, #272] ; 0x110 + USBD_LL_OpenEP(pdev, + 8003784: 2200 movs r2, #0 + 8003786: 2180 movs r1, #128 ; 0x80 + 8003788: 4620 mov r0, r4 + 800378a: f002 fc65 bl 8006058 + USBD_EP_TYPE_CTRL, + USB_MAX_EP0_SIZE); + + pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; + /* Upon Reset call user call back */ + pdev->dev_state = USBD_STATE_DEFAULT; + 800378e: 2301 movs r3, #1 + 8003790: f884 31fc strb.w r3, [r4, #508] ; 0x1fc + + if (pdev->pClassData) + 8003794: f8d4 3218 ldr.w r3, [r4, #536] ; 0x218 + pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; + 8003798: 6225 str r5, [r4, #32] + if (pdev->pClassData) + 800379a: b12b cbz r3, 80037a8 + pdev->pClass->DeInit(pdev, pdev->dev_config); + 800379c: f8d4 3214 ldr.w r3, [r4, #532] ; 0x214 + 80037a0: 7921 ldrb r1, [r4, #4] + 80037a2: 685b ldr r3, [r3, #4] + 80037a4: 4620 mov r0, r4 + 80037a6: 4798 blx r3 + + + return USBD_OK; +} + 80037a8: 2000 movs r0, #0 + 80037aa: bd38 pop {r3, r4, r5, pc} + +080037ac : +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) +{ + pdev->dev_speed = speed; + 80037ac: 7401 strb r1, [r0, #16] + return USBD_OK; +} + 80037ae: 2000 movs r0, #0 + 80037b0: 4770 bx lr + +080037b2 : +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) +{ + pdev->dev_old_state = pdev->dev_state; + 80037b2: f890 31fc ldrb.w r3, [r0, #508] ; 0x1fc + 80037b6: f880 31fd strb.w r3, [r0, #509] ; 0x1fd + pdev->dev_state = USBD_STATE_SUSPENDED; + 80037ba: 2304 movs r3, #4 + 80037bc: f880 31fc strb.w r3, [r0, #508] ; 0x1fc + return USBD_OK; +} + 80037c0: 2000 movs r0, #0 + 80037c2: 4770 bx lr + +080037c4 : +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) +{ + pdev->dev_state = pdev->dev_old_state; + 80037c4: f890 31fd ldrb.w r3, [r0, #509] ; 0x1fd + 80037c8: f880 31fc strb.w r3, [r0, #508] ; 0x1fc + return USBD_OK; +} + 80037cc: 2000 movs r0, #0 + 80037ce: 4770 bx lr + +080037d0 : +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) +{ + 80037d0: b508 push {r3, lr} + if(pdev->dev_state == USBD_STATE_CONFIGURED) + 80037d2: f890 21fc ldrb.w r2, [r0, #508] ; 0x1fc + 80037d6: 2a03 cmp r2, #3 + 80037d8: d104 bne.n 80037e4 + { + if(pdev->pClass->SOF != NULL) + 80037da: f8d0 3214 ldr.w r3, [r0, #532] ; 0x214 + 80037de: 69db ldr r3, [r3, #28] + 80037e0: b103 cbz r3, 80037e4 + { + pdev->pClass->SOF(pdev); + 80037e2: 4798 blx r3 + } + } + return USBD_OK; +} + 80037e4: 2000 movs r0, #0 + 80037e6: bd08 pop {r3, pc} + +080037e8 : + 80037e8: 2000 movs r0, #0 + 80037ea: 4770 bx lr + +080037ec : +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + return USBD_OK; +} + 80037ec: 2000 movs r0, #0 + 80037ee: 4770 bx lr + +080037f0 : +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) +{ + return USBD_OK; +} + 80037f0: 2000 movs r0, #0 + 80037f2: 4770 bx lr + +080037f4 : +* Handle device disconnection event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) +{ + 80037f4: b508 push {r3, lr} + /* Free Class Resources */ + pdev->dev_state = USBD_STATE_DEFAULT; + 80037f6: 2201 movs r2, #1 + 80037f8: f880 21fc strb.w r2, [r0, #508] ; 0x1fc + pdev->pClass->DeInit(pdev, pdev->dev_config); + 80037fc: f8d0 2214 ldr.w r2, [r0, #532] ; 0x214 + 8003800: 7901 ldrb r1, [r0, #4] + 8003802: 6852 ldr r2, [r2, #4] + 8003804: 4790 blx r2 + + return USBD_OK; +} + 8003806: 2000 movs r0, #0 + 8003808: bd08 pop {r3, pc} + +0800380a : +* @param pdev: device instance +* @param req: usb request +* @retval None +*/ + +void USBD_CtlError( USBD_HandleTypeDef *pdev , + 800380a: b510 push {r4, lr} + USBD_SetupReqTypedef *req) +{ + USBD_LL_StallEP(pdev , 0x80); + 800380c: 2180 movs r1, #128 ; 0x80 +void USBD_CtlError( USBD_HandleTypeDef *pdev , + 800380e: 4604 mov r4, r0 + USBD_LL_StallEP(pdev , 0x80); + 8003810: f002 fc40 bl 8006094 + USBD_LL_StallEP(pdev , 0); + 8003814: 4620 mov r0, r4 + 8003816: 2100 movs r1, #0 +} + 8003818: e8bd 4010 ldmia.w sp!, {r4, lr} + USBD_LL_StallEP(pdev , 0); + 800381c: f002 bc3a b.w 8006094 + +08003820 : +{ + 8003820: b537 push {r0, r1, r2, r4, r5, lr} + switch (req->bRequest) + 8003822: 784b ldrb r3, [r1, #1] +{ + 8003824: 4604 mov r4, r0 + 8003826: 460d mov r5, r1 + switch (req->bRequest) + 8003828: 2b09 cmp r3, #9 + 800382a: d879 bhi.n 8003920 + 800382c: e8df f013 tbh [pc, r3, lsl #1] + 8003830: 00e500c9 .word 0x00e500c9 + 8003834: 00d90078 .word 0x00d90078 + 8003838: 006d0078 .word 0x006d0078 + 800383c: 0078000a .word 0x0078000a + 8003840: 008d00b9 .word 0x008d00b9 + switch (req->wValue >> 8) + 8003844: 884b ldrh r3, [r1, #2] + 8003846: 0a1a lsrs r2, r3, #8 + 8003848: 3a01 subs r2, #1 + 800384a: 2a06 cmp r2, #6 + 800384c: d868 bhi.n 8003920 + 800384e: e8df f002 tbb [pc, r2] + 8003852: 1c04 .short 0x1c04 + 8003854: 49676729 .word 0x49676729 + 8003858: 52 .byte 0x52 + 8003859: 00 .byte 0x00 + pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); + 800385a: f8d0 3210 ldr.w r3, [r0, #528] ; 0x210 + 800385e: 681b ldr r3, [r3, #0] + pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); + 8003860: 7c20 ldrb r0, [r4, #16] + 8003862: f10d 0106 add.w r1, sp, #6 + 8003866: 4798 blx r3 + if((len != 0)&& (req->wLength != 0)) + 8003868: f8bd 2006 ldrh.w r2, [sp, #6] + 800386c: 2a00 cmp r2, #0 + 800386e: d067 beq.n 8003940 + 8003870: 88eb ldrh r3, [r5, #6] + 8003872: 2b00 cmp r3, #0 + 8003874: d064 beq.n 8003940 + len = MIN(len , req->wLength); + 8003876: 429a cmp r2, r3 + 8003878: bf28 it cs + 800387a: 461a movcs r2, r3 + 800387c: f8ad 2006 strh.w r2, [sp, #6] + USBD_CtlSendData (pdev, + 8003880: 4601 mov r1, r0 + USBD_CtlSendData (pdev, + 8003882: 4620 mov r0, r4 + 8003884: f000 f971 bl 8003b6a + 8003888: e05a b.n 8003940 + if(pdev->dev_speed == USBD_SPEED_HIGH ) + 800388a: 7c02 ldrb r2, [r0, #16] + 800388c: f8d0 3214 ldr.w r3, [r0, #532] ; 0x214 + 8003890: b932 cbnz r2, 80038a0 + pbuf = (uint8_t *)pdev->pClass->GetHSConfigDescriptor(&len); + 8003892: 6a9b ldr r3, [r3, #40] ; 0x28 + pbuf = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(&len); + 8003894: f10d 0006 add.w r0, sp, #6 + 8003898: 4798 blx r3 + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 800389a: 2302 movs r3, #2 + pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + 800389c: 7043 strb r3, [r0, #1] + 800389e: e7e3 b.n 8003868 + pbuf = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(&len); + 80038a0: 6adb ldr r3, [r3, #44] ; 0x2c + 80038a2: e7f7 b.n 8003894 + switch ((uint8_t)(req->wValue)) + 80038a4: b2db uxtb r3, r3 + 80038a6: 2b05 cmp r3, #5 + 80038a8: d83a bhi.n 8003920 + 80038aa: e8df f003 tbb [pc, r3] + 80038ae: 0703 .short 0x0703 + 80038b0: 17130f0b .word 0x17130f0b + pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); + 80038b4: f8d0 3210 ldr.w r3, [r0, #528] ; 0x210 + 80038b8: 685b ldr r3, [r3, #4] + 80038ba: e7d1 b.n 8003860 + pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); + 80038bc: f8d0 3210 ldr.w r3, [r0, #528] ; 0x210 + 80038c0: 689b ldr r3, [r3, #8] + 80038c2: e7cd b.n 8003860 + pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); + 80038c4: f8d0 3210 ldr.w r3, [r0, #528] ; 0x210 + 80038c8: 68db ldr r3, [r3, #12] + 80038ca: e7c9 b.n 8003860 + pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); + 80038cc: f8d0 3210 ldr.w r3, [r0, #528] ; 0x210 + 80038d0: 691b ldr r3, [r3, #16] + 80038d2: e7c5 b.n 8003860 + pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); + 80038d4: f8d0 3210 ldr.w r3, [r0, #528] ; 0x210 + 80038d8: 695b ldr r3, [r3, #20] + 80038da: e7c1 b.n 8003860 + pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); + 80038dc: f8d0 3210 ldr.w r3, [r0, #528] ; 0x210 + 80038e0: 699b ldr r3, [r3, #24] + 80038e2: e7bd b.n 8003860 + if(pdev->dev_speed == USBD_SPEED_HIGH ) + 80038e4: 7c03 ldrb r3, [r0, #16] + 80038e6: b9db cbnz r3, 8003920 + pbuf = (uint8_t *)pdev->pClass->GetDeviceQualifierDescriptor(&len); + 80038e8: f8d0 3214 ldr.w r3, [r0, #532] ; 0x214 + 80038ec: f10d 0006 add.w r0, sp, #6 + 80038f0: 6b5b ldr r3, [r3, #52] ; 0x34 + 80038f2: 4798 blx r3 + 80038f4: e7b8 b.n 8003868 + if(pdev->dev_speed == USBD_SPEED_HIGH ) + 80038f6: 7c03 ldrb r3, [r0, #16] + 80038f8: b993 cbnz r3, 8003920 + pbuf = (uint8_t *)pdev->pClass->GetOtherSpeedConfigDescriptor(&len); + 80038fa: f8d0 3214 ldr.w r3, [r0, #532] ; 0x214 + 80038fe: f10d 0006 add.w r0, sp, #6 + 8003902: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003904: 4798 blx r3 + pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + 8003906: 2307 movs r3, #7 + 8003908: e7c8 b.n 800389c + if ((req->wIndex == 0) && (req->wLength == 0)) + 800390a: 888b ldrh r3, [r1, #4] + 800390c: b943 cbnz r3, 8003920 + 800390e: 88cb ldrh r3, [r1, #6] + 8003910: b933 cbnz r3, 8003920 + if (pdev->dev_state == USBD_STATE_CONFIGURED) + 8003912: f890 31fc ldrb.w r3, [r0, #508] ; 0x1fc + dev_addr = (uint8_t)(req->wValue) & 0x7F; + 8003916: 788d ldrb r5, [r1, #2] + if (pdev->dev_state == USBD_STATE_CONFIGURED) + 8003918: 2b03 cmp r3, #3 + dev_addr = (uint8_t)(req->wValue) & 0x7F; + 800391a: f005 057f and.w r5, r5, #127 ; 0x7f + if (pdev->dev_state == USBD_STATE_CONFIGURED) + 800391e: d103 bne.n 8003928 + USBD_CtlError(pdev , req); + 8003920: 4620 mov r0, r4 + 8003922: f7ff ff72 bl 800380a + break; + 8003926: e00b b.n 8003940 + pdev->dev_address = dev_addr; + 8003928: f880 51fe strb.w r5, [r0, #510] ; 0x1fe + USBD_LL_SetUSBAddress(pdev, dev_addr); + 800392c: 4629 mov r1, r5 + 800392e: f002 fbe1 bl 80060f4 + USBD_CtlSendStatus(pdev); + 8003932: 4620 mov r0, r4 + 8003934: f000 f945 bl 8003bc2 + if (dev_addr != 0) + 8003938: b12d cbz r5, 8003946 + pdev->dev_state = USBD_STATE_ADDRESSED; + 800393a: 2302 movs r3, #2 + pdev->dev_state = USBD_STATE_DEFAULT; + 800393c: f884 31fc strb.w r3, [r4, #508] ; 0x1fc +} + 8003940: 2000 movs r0, #0 + 8003942: b003 add sp, #12 + 8003944: bd30 pop {r4, r5, pc} + pdev->dev_state = USBD_STATE_DEFAULT; + 8003946: 2301 movs r3, #1 + 8003948: e7f8 b.n 800393c + cfgidx = (uint8_t)(req->wValue); + 800394a: 7889 ldrb r1, [r1, #2] + 800394c: 4d30 ldr r5, [pc, #192] ; (8003a10 ) + if (cfgidx > USBD_MAX_NUM_CONFIGURATION ) + 800394e: 2901 cmp r1, #1 + cfgidx = (uint8_t)(req->wValue); + 8003950: 7029 strb r1, [r5, #0] + if (cfgidx > USBD_MAX_NUM_CONFIGURATION ) + 8003952: d8e5 bhi.n 8003920 + switch (pdev->dev_state) + 8003954: f890 31fc ldrb.w r3, [r0, #508] ; 0x1fc + 8003958: 2b02 cmp r3, #2 + 800395a: d00c beq.n 8003976 + 800395c: 2b03 cmp r3, #3 + 800395e: d1df bne.n 8003920 + if (cfgidx == 0) + 8003960: b9b1 cbnz r1, 8003990 + pdev->dev_state = USBD_STATE_ADDRESSED; + 8003962: 2302 movs r3, #2 + 8003964: f880 31fc strb.w r3, [r0, #508] ; 0x1fc + pdev->dev_config = cfgidx; + 8003968: 6041 str r1, [r0, #4] + USBD_ClrClassConfig(pdev , cfgidx); + 800396a: f7ff fe4b bl 8003604 + USBD_CtlSendStatus(pdev); + 800396e: 4620 mov r0, r4 + 8003970: f000 f927 bl 8003bc2 + 8003974: e7e4 b.n 8003940 + if (cfgidx) + 8003976: 2900 cmp r1, #0 + 8003978: d0f9 beq.n 800396e + pdev->dev_config = cfgidx; + 800397a: 2101 movs r1, #1 + pdev->dev_state = USBD_STATE_CONFIGURED; + 800397c: 2303 movs r3, #3 + pdev->dev_config = cfgidx; + 800397e: 6041 str r1, [r0, #4] + pdev->dev_state = USBD_STATE_CONFIGURED; + 8003980: f880 31fc strb.w r3, [r0, #508] ; 0x1fc + if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL) + 8003984: 4620 mov r0, r4 + 8003986: f7ff fe32 bl 80035ee + 800398a: 2802 cmp r0, #2 + 800398c: d1ef bne.n 800396e + 800398e: e7c7 b.n 8003920 + else if (cfgidx != pdev->dev_config) + 8003990: 6841 ldr r1, [r0, #4] + 8003992: 2901 cmp r1, #1 + 8003994: d0eb beq.n 800396e + USBD_ClrClassConfig(pdev , pdev->dev_config); + 8003996: b2c9 uxtb r1, r1 + 8003998: f7ff fe34 bl 8003604 + pdev->dev_config = cfgidx; + 800399c: 7829 ldrb r1, [r5, #0] + 800399e: 6061 str r1, [r4, #4] + 80039a0: e7f0 b.n 8003984 + if (req->wLength != 1) + 80039a2: 88ca ldrh r2, [r1, #6] + 80039a4: 2a01 cmp r2, #1 + 80039a6: d1bb bne.n 8003920 + switch (pdev->dev_state ) + 80039a8: f890 31fc ldrb.w r3, [r0, #508] ; 0x1fc + 80039ac: 2b02 cmp r3, #2 + 80039ae: d003 beq.n 80039b8 + 80039b0: 2b03 cmp r3, #3 + 80039b2: d1b5 bne.n 8003920 + USBD_CtlSendData (pdev, + 80039b4: 1d01 adds r1, r0, #4 + 80039b6: e764 b.n 8003882 + pdev->dev_default_config = 0; + 80039b8: 4601 mov r1, r0 + 80039ba: 2300 movs r3, #0 + 80039bc: f841 3f08 str.w r3, [r1, #8]! + 80039c0: e75f b.n 8003882 + switch (pdev->dev_state) + 80039c2: f890 31fc ldrb.w r3, [r0, #508] ; 0x1fc + 80039c6: 3b02 subs r3, #2 + 80039c8: 2b01 cmp r3, #1 + 80039ca: d8a9 bhi.n 8003920 + pdev->dev_config_status = USB_CONFIG_SELF_POWERED; + 80039cc: 2301 movs r3, #1 + 80039ce: 60c3 str r3, [r0, #12] + if (pdev->dev_remote_wakeup) + 80039d0: f8d0 3204 ldr.w r3, [r0, #516] ; 0x204 + 80039d4: b10b cbz r3, 80039da + pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; + 80039d6: 2303 movs r3, #3 + 80039d8: 60c3 str r3, [r0, #12] + USBD_CtlSendData (pdev, + 80039da: 2202 movs r2, #2 + 80039dc: f104 010c add.w r1, r4, #12 + 80039e0: e74f b.n 8003882 + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + 80039e2: 884b ldrh r3, [r1, #2] + 80039e4: 2b01 cmp r3, #1 + 80039e6: d1ab bne.n 8003940 + pdev->dev_remote_wakeup = 0; + 80039e8: f8c4 3204 str.w r3, [r4, #516] ; 0x204 + pdev->pClass->Setup (pdev, req); + 80039ec: f8d4 3214 ldr.w r3, [r4, #532] ; 0x214 + 80039f0: 4629 mov r1, r5 + 80039f2: 689b ldr r3, [r3, #8] + 80039f4: 4620 mov r0, r4 + 80039f6: 4798 blx r3 + 80039f8: e7b9 b.n 800396e + switch (pdev->dev_state) + 80039fa: f890 31fc ldrb.w r3, [r0, #508] ; 0x1fc + 80039fe: 3b02 subs r3, #2 + 8003a00: 2b01 cmp r3, #1 + 8003a02: d88d bhi.n 8003920 + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + 8003a04: 884b ldrh r3, [r1, #2] + 8003a06: 2b01 cmp r3, #1 + 8003a08: d19a bne.n 8003940 + pdev->dev_remote_wakeup = 0; + 8003a0a: 2300 movs r3, #0 + 8003a0c: e7ec b.n 80039e8 + 8003a0e: bf00 nop + 8003a10: 200002bd .word 0x200002bd + +08003a14 : +{ + 8003a14: b538 push {r3, r4, r5, lr} + switch (pdev->dev_state) + 8003a16: f890 31fc ldrb.w r3, [r0, #508] ; 0x1fc + 8003a1a: 2b03 cmp r3, #3 +{ + 8003a1c: 4604 mov r4, r0 + 8003a1e: 460d mov r5, r1 + switch (pdev->dev_state) + 8003a20: d10d bne.n 8003a3e + if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) + 8003a22: 790b ldrb r3, [r1, #4] + 8003a24: 2b01 cmp r3, #1 + 8003a26: d80a bhi.n 8003a3e + pdev->pClass->Setup (pdev, req); + 8003a28: f8d0 3214 ldr.w r3, [r0, #532] ; 0x214 + 8003a2c: 689b ldr r3, [r3, #8] + 8003a2e: 4798 blx r3 + if((req->wLength == 0)&& (ret == USBD_OK)) + 8003a30: 88eb ldrh r3, [r5, #6] + 8003a32: b913 cbnz r3, 8003a3a + USBD_CtlSendStatus(pdev); + 8003a34: 4620 mov r0, r4 + 8003a36: f000 f8c4 bl 8003bc2 +} + 8003a3a: 2000 movs r0, #0 + 8003a3c: bd38 pop {r3, r4, r5, pc} + USBD_CtlError(pdev , req); + 8003a3e: f7ff fee4 bl 800380a + break; + 8003a42: e7fa b.n 8003a3a + +08003a44 : +{ + 8003a44: b570 push {r4, r5, r6, lr} + if ((req->bmRequest & 0x60) == 0x20) + 8003a46: 780a ldrb r2, [r1, #0] + ep_addr = LOBYTE(req->wIndex); + 8003a48: 888e ldrh r6, [r1, #4] + if ((req->bmRequest & 0x60) == 0x20) + 8003a4a: f002 0260 and.w r2, r2, #96 ; 0x60 + 8003a4e: 2a20 cmp r2, #32 +{ + 8003a50: 4604 mov r4, r0 + 8003a52: 460d mov r5, r1 + ep_addr = LOBYTE(req->wIndex); + 8003a54: b2f3 uxtb r3, r6 + if ((req->bmRequest & 0x60) == 0x20) + 8003a56: d105 bne.n 8003a64 + pdev->pClass->Setup (pdev, req); + 8003a58: f8d0 3214 ldr.w r3, [r0, #532] ; 0x214 + 8003a5c: 689b ldr r3, [r3, #8] + 8003a5e: 4798 blx r3 +} + 8003a60: 2000 movs r0, #0 + 8003a62: bd70 pop {r4, r5, r6, pc} + switch (req->bRequest) + 8003a64: 784a ldrb r2, [r1, #1] + 8003a66: 2a01 cmp r2, #1 + 8003a68: d01c beq.n 8003aa4 + 8003a6a: d32a bcc.n 8003ac2 + 8003a6c: 2a03 cmp r2, #3 + 8003a6e: d1f7 bne.n 8003a60 + switch (pdev->dev_state) + 8003a70: f890 21fc ldrb.w r2, [r0, #508] ; 0x1fc + 8003a74: 2a02 cmp r2, #2 + 8003a76: d040 beq.n 8003afa + 8003a78: 2a03 cmp r2, #3 + 8003a7a: d002 beq.n 8003a82 + USBD_CtlError(pdev , req); + 8003a7c: f7ff fec5 bl 800380a + break; + 8003a80: e7ee b.n 8003a60 + if (req->wValue == USB_FEATURE_EP_HALT) + 8003a82: 884a ldrh r2, [r1, #2] + 8003a84: b922 cbnz r2, 8003a90 + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + 8003a86: 065e lsls r6, r3, #25 + 8003a88: d002 beq.n 8003a90 + USBD_LL_StallEP(pdev , ep_addr); + 8003a8a: 4619 mov r1, r3 + 8003a8c: f002 fb02 bl 8006094 + pdev->pClass->Setup (pdev, req); + 8003a90: f8d4 3214 ldr.w r3, [r4, #532] ; 0x214 + 8003a94: 4629 mov r1, r5 + 8003a96: 689b ldr r3, [r3, #8] + 8003a98: 4620 mov r0, r4 + 8003a9a: 4798 blx r3 + USBD_CtlSendStatus(pdev); + 8003a9c: 4620 mov r0, r4 + 8003a9e: f000 f890 bl 8003bc2 + 8003aa2: e7dd b.n 8003a60 + switch (pdev->dev_state) + 8003aa4: f890 21fc ldrb.w r2, [r0, #508] ; 0x1fc + 8003aa8: 2a02 cmp r2, #2 + 8003aaa: d026 beq.n 8003afa + 8003aac: 2a03 cmp r2, #3 + 8003aae: d1e5 bne.n 8003a7c + if (req->wValue == USB_FEATURE_EP_HALT) + 8003ab0: 884a ldrh r2, [r1, #2] + 8003ab2: 2a00 cmp r2, #0 + 8003ab4: d1d4 bne.n 8003a60 + if ((ep_addr & 0x7F) != 0x00) + 8003ab6: 0659 lsls r1, r3, #25 + 8003ab8: d0f0 beq.n 8003a9c + USBD_LL_ClearStallEP(pdev , ep_addr); + 8003aba: 4619 mov r1, r3 + 8003abc: f002 faf8 bl 80060b0 + 8003ac0: e7e6 b.n 8003a90 + switch (pdev->dev_state) + 8003ac2: f890 21fc ldrb.w r2, [r0, #508] ; 0x1fc + 8003ac6: 2a02 cmp r2, #2 + 8003ac8: d017 beq.n 8003afa + 8003aca: 2a03 cmp r2, #3 + 8003acc: d1d6 bne.n 8003a7c + 8003ace: f003 057f and.w r5, r3, #127 ; 0x7f + pep = ((ep_addr & 0x80) == 0x80) ? &pdev->ep_in[ep_addr & 0x7F]:\ + 8003ad2: f016 0f80 tst.w r6, #128 ; 0x80 + 8003ad6: eb00 1505 add.w r5, r0, r5, lsl #4 + if(USBD_LL_IsStallEP(pdev, ep_addr)) + 8003ada: 4619 mov r1, r3 + pep = ((ep_addr & 0x80) == 0x80) ? &pdev->ep_in[ep_addr & 0x7F]:\ + 8003adc: bf14 ite ne + 8003ade: 3514 addne r5, #20 + 8003ae0: f505 7582 addeq.w r5, r5, #260 ; 0x104 + if(USBD_LL_IsStallEP(pdev, ep_addr)) + 8003ae4: f002 faf2 bl 80060cc + 8003ae8: b168 cbz r0, 8003b06 + pep->status = 0x0001; + 8003aea: 2301 movs r3, #1 + 8003aec: 602b str r3, [r5, #0] + USBD_CtlSendData (pdev, + 8003aee: 2202 movs r2, #2 + 8003af0: 4629 mov r1, r5 + 8003af2: 4620 mov r0, r4 + 8003af4: f000 f839 bl 8003b6a + break; + 8003af8: e7b2 b.n 8003a60 + if ((ep_addr & 0x7F) != 0x00) + 8003afa: 065a lsls r2, r3, #25 + 8003afc: d0b0 beq.n 8003a60 + USBD_LL_StallEP(pdev , ep_addr); + 8003afe: 4619 mov r1, r3 + 8003b00: f002 fac8 bl 8006094 + 8003b04: e7ac b.n 8003a60 + pep->status = 0x0000; + 8003b06: 6028 str r0, [r5, #0] + 8003b08: e7f1 b.n 8003aee + +08003b0a : + req->bmRequest = *(uint8_t *) (pdata); + 8003b0a: 780b ldrb r3, [r1, #0] + 8003b0c: 7003 strb r3, [r0, #0] + req->bRequest = *(uint8_t *) (pdata + 1); + 8003b0e: 784b ldrb r3, [r1, #1] + 8003b10: 7043 strb r3, [r0, #1] + req->wValue = SWAPBYTE (pdata + 2); + 8003b12: 78ca ldrb r2, [r1, #3] + 8003b14: 788b ldrb r3, [r1, #2] + 8003b16: eb03 2302 add.w r3, r3, r2, lsl #8 + 8003b1a: 8043 strh r3, [r0, #2] + req->wIndex = SWAPBYTE (pdata + 4); + 8003b1c: 794a ldrb r2, [r1, #5] + 8003b1e: 790b ldrb r3, [r1, #4] + 8003b20: eb03 2302 add.w r3, r3, r2, lsl #8 + 8003b24: 8083 strh r3, [r0, #4] + req->wLength = SWAPBYTE (pdata + 6); + 8003b26: 79ca ldrb r2, [r1, #7] + 8003b28: 798b ldrb r3, [r1, #6] + 8003b2a: eb03 2302 add.w r3, r3, r2, lsl #8 + 8003b2e: 80c3 strh r3, [r0, #6] + 8003b30: 4770 bx lr + +08003b32 : + * @param unicode : Formatted string buffer (unicode) + * @param len : descriptor length + * @retval None + */ +void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) +{ + 8003b32: b530 push {r4, r5, lr} + uint8_t idx = 0; + + if (desc != NULL) + 8003b34: b188 cbz r0, 8003b5a + 8003b36: 4605 mov r5, r0 + 8003b38: 1a2b subs r3, r5, r0 + */ +static uint8_t USBD_GetLen(uint8_t *buf) +{ + uint8_t len = 0; + + while (*buf != '\0') + 8003b3a: f815 4b01 ldrb.w r4, [r5], #1 + 8003b3e: b2db uxtb r3, r3 + 8003b40: 2c00 cmp r4, #0 + 8003b42: d1f9 bne.n 8003b38 + *len = USBD_GetLen(desc) * 2 + 2; + 8003b44: 005b lsls r3, r3, #1 + 8003b46: 3302 adds r3, #2 + 8003b48: 8013 strh r3, [r2, #0] + unicode[idx++] = *len; + 8003b4a: 700b strb r3, [r1, #0] + unicode[idx++] = USB_DESC_TYPE_STRING; + 8003b4c: 2303 movs r3, #3 + 8003b4e: 704b strb r3, [r1, #1] + 8003b50: 3801 subs r0, #1 + 8003b52: 2302 movs r3, #2 + while (*desc != '\0') + 8003b54: f810 5f01 ldrb.w r5, [r0, #1]! + 8003b58: b905 cbnz r5, 8003b5c + 8003b5a: bd30 pop {r4, r5, pc} + unicode[idx++] = *desc++; + 8003b5c: 1c5a adds r2, r3, #1 + 8003b5e: b2d2 uxtb r2, r2 + 8003b60: 54cd strb r5, [r1, r3] + unicode[idx++] = 0x00; + 8003b62: 3302 adds r3, #2 + 8003b64: b2db uxtb r3, r3 + 8003b66: 548c strb r4, [r1, r2] + 8003b68: e7f4 b.n 8003b54 + +08003b6a : +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + 8003b6a: b510 push {r4, lr} + 8003b6c: 4613 mov r3, r2 + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_IN; + 8003b6e: 2202 movs r2, #2 + 8003b70: f8c0 21f4 str.w r2, [r0, #500] ; 0x1f4 + pdev->ep_in[0].total_length = len; + 8003b74: 6183 str r3, [r0, #24] + pdev->ep_in[0].rem_length = len; + /* Start the transfer */ + USBD_LL_Transmit (pdev, 0x00, pbuf, len); + 8003b76: 460a mov r2, r1 + pdev->ep_in[0].rem_length = len; + 8003b78: 61c3 str r3, [r0, #28] + USBD_LL_Transmit (pdev, 0x00, pbuf, len); + 8003b7a: 2100 movs r1, #0 + 8003b7c: f002 fac8 bl 8006110 + + return USBD_OK; +} + 8003b80: 2000 movs r0, #0 + 8003b82: bd10 pop {r4, pc} + +08003b84 : +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + 8003b84: b508 push {r3, lr} + /* Start the next transfer */ + USBD_LL_Transmit (pdev, 0x00, pbuf, len); + 8003b86: 4613 mov r3, r2 + 8003b88: 460a mov r2, r1 + 8003b8a: 2100 movs r1, #0 + 8003b8c: f002 fac0 bl 8006110 + + return USBD_OK; +} + 8003b90: 2000 movs r0, #0 + 8003b92: bd08 pop {r3, pc} + +08003b94 : +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + 8003b94: b510 push {r4, lr} + 8003b96: 4613 mov r3, r2 + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_OUT; + 8003b98: 2203 movs r2, #3 + 8003b9a: f8c0 21f4 str.w r2, [r0, #500] ; 0x1f4 + pdev->ep_out[0].total_length = len; + 8003b9e: f8c0 3108 str.w r3, [r0, #264] ; 0x108 + pdev->ep_out[0].rem_length = len; + /* Start the transfer */ + USBD_LL_PrepareReceive (pdev, + 8003ba2: 460a mov r2, r1 + pdev->ep_out[0].rem_length = len; + 8003ba4: f8c0 310c str.w r3, [r0, #268] ; 0x10c + USBD_LL_PrepareReceive (pdev, + 8003ba8: 2100 movs r1, #0 + 8003baa: f002 fabf bl 800612c + 0, + pbuf, + len); + + return USBD_OK; +} + 8003bae: 2000 movs r0, #0 + 8003bb0: bd10 pop {r4, pc} + +08003bb2 : +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + 8003bb2: b508 push {r3, lr} + + USBD_LL_PrepareReceive (pdev, + 8003bb4: 4613 mov r3, r2 + 8003bb6: 460a mov r2, r1 + 8003bb8: 2100 movs r1, #0 + 8003bba: f002 fab7 bl 800612c + 0, + pbuf, + len); + return USBD_OK; +} + 8003bbe: 2000 movs r0, #0 + 8003bc0: bd08 pop {r3, pc} + +08003bc2 : +* send zero lzngth packet on the ctl pipe +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev) +{ + 8003bc2: b508 push {r3, lr} + + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_STATUS_IN; + 8003bc4: 2304 movs r3, #4 + 8003bc6: f8c0 31f4 str.w r3, [r0, #500] ; 0x1f4 + + /* Start the transfer */ + USBD_LL_Transmit (pdev, 0x00, NULL, 0); + 8003bca: 2300 movs r3, #0 + 8003bcc: 461a mov r2, r3 + 8003bce: 4619 mov r1, r3 + 8003bd0: f002 fa9e bl 8006110 + + return USBD_OK; +} + 8003bd4: 2000 movs r0, #0 + 8003bd6: bd08 pop {r3, pc} + +08003bd8 : +* receive zero lzngth packet on the ctl pipe +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev) +{ + 8003bd8: b508 push {r3, lr} + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_STATUS_OUT; + 8003bda: 2305 movs r3, #5 + 8003bdc: f8c0 31f4 str.w r3, [r0, #500] ; 0x1f4 + + /* Start the transfer */ + USBD_LL_PrepareReceive ( pdev, + 8003be0: 2300 movs r3, #0 + 8003be2: 461a mov r2, r3 + 8003be4: 4619 mov r1, r3 + 8003be6: f002 faa1 bl 800612c + 0, + NULL, + 0); + + return USBD_OK; +} + 8003bea: 2000 movs r0, #0 + 8003bec: bd08 pop {r3, pc} + +08003bee : +* @param argument pointer that is passed to the thread function as start argument. +* @retval status code that indicates the execution status of the function +* @note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +*/ +osStatus osKernelStart (void) +{ + 8003bee: b508 push {r3, lr} + vTaskStartScheduler(); + 8003bf0: f001 f898 bl 8004d24 + + return osOK; +} + 8003bf4: 2000 movs r0, #0 + 8003bf6: bd08 pop {r3, pc} + +08003bf8 : +* @param argument pointer that is passed to the thread function as start argument. +* @retval thread ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +*/ +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) +{ + 8003bf8: b530 push {r4, r5, lr} + + handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + thread_def->buffer, thread_def->controlblock); +#else + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + 8003bfa: f9b0 4008 ldrsh.w r4, [r0, #8] + 8003bfe: 8a02 ldrh r2, [r0, #16] +{ + 8003c00: 460b mov r3, r1 + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + 8003c02: e890 0022 ldmia.w r0, {r1, r5} +{ + 8003c06: b085 sub sp, #20 + if (priority != osPriorityError) { + 8003c08: 2c84 cmp r4, #132 ; 0x84 + fpriority += (priority - osPriorityIdle); + 8003c0a: bf14 ite ne + 8003c0c: 3403 addne r4, #3 + unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY; + 8003c0e: 2400 moveq r4, #0 + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + 8003c10: a803 add r0, sp, #12 + 8003c12: 9001 str r0, [sp, #4] + 8003c14: 9400 str r4, [sp, #0] + 8003c16: 4628 mov r0, r5 + 8003c18: f000 ffb4 bl 8004b84 + 8003c1c: 2801 cmp r0, #1 + &handle) != pdPASS) { + return NULL; + } +#endif + + return handle; + 8003c1e: bf0c ite eq + 8003c20: 9803 ldreq r0, [sp, #12] + return NULL; + 8003c22: 2000 movne r0, #0 +} + 8003c24: b005 add sp, #20 + 8003c26: bd30 pop {r4, r5, pc} + +08003c28 : +* @brief Wait for Timeout (Time Delay) +* @param millisec time delay value +* @retval status code that indicates the execution status of the function. +*/ +osStatus osDelay (uint32_t millisec) +{ + 8003c28: b508 push {r3, lr} +#if INCLUDE_vTaskDelay + TickType_t ticks = millisec / portTICK_PERIOD_MS; + + vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */ + 8003c2a: 2800 cmp r0, #0 + 8003c2c: bf08 it eq + 8003c2e: 2001 moveq r0, #1 + 8003c30: f001 f9c6 bl 8004fc0 +#else + (void) millisec; + + return osErrorResource; +#endif +} + 8003c34: 2000 movs r0, #0 + 8003c36: bd08 pop {r3, pc} + +08003c38 : +* @param signals specifies the signal flags of the thread that should be set. +* @retval previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +* @note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +*/ +int32_t osSignalSet (osThreadId thread_id, int32_t signal) +{ + 8003c38: b51f push {r0, r1, r2, r3, r4, lr} +#if( configUSE_TASK_NOTIFICATIONS == 1 ) + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + uint32_t ulPreviousNotificationValue = 0; + 8003c3a: ab04 add r3, sp, #16 + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + 8003c3c: 2200 movs r2, #0 + 8003c3e: 9202 str r2, [sp, #8] + uint32_t ulPreviousNotificationValue = 0; + 8003c40: f843 2d04 str.w r2, [r3, #-4]! + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 8003c44: f3ef 8205 mrs r2, IPSR + + if (inHandlerMode()) + 8003c48: b1ba cbz r2, 8003c7a + { + if(xTaskGenericNotifyFromISR( thread_id , (uint32_t)signal, eSetBits, &ulPreviousNotificationValue, &xHigherPriorityTaskWoken ) != pdPASS ) + 8003c4a: aa02 add r2, sp, #8 + 8003c4c: 9200 str r2, [sp, #0] + 8003c4e: 2201 movs r2, #1 + 8003c50: f001 fc5a bl 8005508 + 8003c54: 2801 cmp r0, #1 + 8003c56: d004 beq.n 8003c62 + return 0x80000000; + 8003c58: f04f 4000 mov.w r0, #2147483648 ; 0x80000000 + (void) thread_id; + (void) signal; + + return 0x80000000; /* Task Notification not supported */ +#endif +} + 8003c5c: b005 add sp, #20 + 8003c5e: f85d fb04 ldr.w pc, [sp], #4 + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + 8003c62: 9b02 ldr r3, [sp, #8] + 8003c64: b13b cbz r3, 8003c76 + 8003c66: 4b08 ldr r3, [pc, #32] ; (8003c88 ) + 8003c68: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8003c6c: 601a str r2, [r3, #0] + 8003c6e: f3bf 8f4f dsb sy + 8003c72: f3bf 8f6f isb sy + return ulPreviousNotificationValue; + 8003c76: 9803 ldr r0, [sp, #12] + 8003c78: e7f0 b.n 8003c5c + else if(xTaskGenericNotify( thread_id , (uint32_t)signal, eSetBits, &ulPreviousNotificationValue) != pdPASS ) + 8003c7a: 2201 movs r2, #1 + 8003c7c: f001 fbdc bl 8005438 + 8003c80: 2801 cmp r0, #1 + 8003c82: d0f8 beq.n 8003c76 + 8003c84: e7e8 b.n 8003c58 + 8003c86: bf00 nop + 8003c88: e000ed04 .word 0xe000ed04 + +08003c8c : +* @param millisec timeout value or 0 in case of no time-out. +* @retval event flag information or error code. +* @note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +*/ +osEvent osSignalWait (int32_t signals, uint32_t millisec) +{ + 8003c8c: b530 push {r4, r5, lr} + 8003c8e: b085 sub sp, #20 + +#if( configUSE_TASK_NOTIFICATIONS == 1 ) + + TickType_t ticks; + + ret.value.signals = 0; + 8003c90: 2300 movs r3, #0 +{ + 8003c92: 4604 mov r4, r0 + 8003c94: 4615 mov r5, r2 + ret.value.signals = 0; + 8003c96: 9302 str r3, [sp, #8] + 8003c98: f3ef 8005 mrs r0, IPSR + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) + 8003c9c: b110 cbz r0, 8003ca4 + { + ret.status = osErrorISR; /*Not allowed in ISR*/ + 8003c9e: 2382 movs r3, #130 ; 0x82 + } + else if(ret.value.signals < 0) + { + ret.status = osErrorValue; + } + else ret.status = osEventSignal; + 8003ca0: 9301 str r3, [sp, #4] + 8003ca2: e007 b.n 8003cb4 + if(xTaskNotifyWait( 0,(uint32_t) signals, (uint32_t *)&ret.value.signals, ticks) != pdTRUE) + 8003ca4: 4613 mov r3, r2 + 8003ca6: aa02 add r2, sp, #8 + 8003ca8: f001 fb80 bl 80053ac + 8003cac: 2801 cmp r0, #1 + 8003cae: d00b beq.n 8003cc8 + if(ticks == 0) ret.status = osOK; + 8003cb0: b945 cbnz r5, 8003cc4 + 8003cb2: 9501 str r5, [sp, #4] + (void) millisec; + + ret.status = osErrorOS; /* Task Notification not supported */ +#endif + + return ret; + 8003cb4: ab04 add r3, sp, #16 + 8003cb6: e913 0007 ldmdb r3, {r0, r1, r2} + 8003cba: e884 0007 stmia.w r4, {r0, r1, r2} +} + 8003cbe: 4620 mov r0, r4 + 8003cc0: b005 add sp, #20 + 8003cc2: bd30 pop {r4, r5, pc} + else ret.status = osEventTimeout; + 8003cc4: 2340 movs r3, #64 ; 0x40 + 8003cc6: e7eb b.n 8003ca0 + else if(ret.value.signals < 0) + 8003cc8: 9b02 ldr r3, [sp, #8] + 8003cca: 2b00 cmp r3, #0 + ret.status = osErrorValue; + 8003ccc: bfb4 ite lt + 8003cce: 2386 movlt r3, #134 ; 0x86 + else ret.status = osEventSignal; + 8003cd0: 2308 movge r3, #8 + 8003cd2: e7e5 b.n 8003ca0 + +08003cd4 : +* @param pool_def memory pool definition referenced with \ref osPool. +* @retval memory pool ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +*/ +osPoolId osPoolCreate (const osPoolDef_t *pool_def) +{ + 8003cd4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + osPoolId thePool; + int itemSize = 4 * ((pool_def->item_sz + 3) / 4); + 8003cd8: 6846 ldr r6, [r0, #4] +{ + 8003cda: 4607 mov r7, r0 + uint32_t i; + + /* First have to allocate memory for the pool control block. */ + thePool = pvPortMalloc(sizeof(os_pool_cb_t)); + 8003cdc: 2014 movs r0, #20 + 8003cde: f000 fb1b bl 8004318 + int itemSize = 4 * ((pool_def->item_sz + 3) / 4); + 8003ce2: 3603 adds r6, #3 + 8003ce4: f026 0603 bic.w r6, r6, #3 + + + if (thePool) { + 8003ce8: 4604 mov r4, r0 + 8003cea: b1a8 cbz r0, 8003d18 + thePool->pool_sz = pool_def->pool_sz; + 8003cec: 6838 ldr r0, [r7, #0] + 8003cee: 60a0 str r0, [r4, #8] + thePool->item_sz = itemSize; + thePool->currentIndex = 0; + 8003cf0: 2500 movs r5, #0 + thePool->item_sz = itemSize; + 8003cf2: 60e6 str r6, [r4, #12] + thePool->currentIndex = 0; + 8003cf4: 6125 str r5, [r4, #16] + + /* Memory for markers */ + thePool->markers = pvPortMalloc(pool_def->pool_sz); + 8003cf6: f000 fb0f bl 8004318 + 8003cfa: 4680 mov r8, r0 + 8003cfc: 6060 str r0, [r4, #4] + + if (thePool->markers) { + 8003cfe: b1d0 cbz r0, 8003d36 + /* Now allocate the pool itself. */ + thePool->pool = pvPortMalloc(pool_def->pool_sz * itemSize); + 8003d00: 6838 ldr r0, [r7, #0] + 8003d02: 4370 muls r0, r6 + 8003d04: f000 fb08 bl 8004318 + 8003d08: 4606 mov r6, r0 + 8003d0a: 6020 str r0, [r4, #0] + + if (thePool->pool) { + 8003d0c: b158 cbz r0, 8003d26 + 8003d0e: 462b mov r3, r5 + for (i = 0; i < pool_def->pool_sz; i++) { + thePool->markers[i] = 0; + 8003d10: 4629 mov r1, r5 + for (i = 0; i < pool_def->pool_sz; i++) { + 8003d12: 683a ldr r2, [r7, #0] + 8003d14: 4293 cmp r3, r2 + 8003d16: d302 bcc.n 8003d1e + return thePool; + +#else + return NULL; +#endif +} + 8003d18: 4620 mov r0, r4 + 8003d1a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + thePool->markers[i] = 0; + 8003d1e: 6862 ldr r2, [r4, #4] + 8003d20: 54d1 strb r1, [r2, r3] + for (i = 0; i < pool_def->pool_sz; i++) { + 8003d22: 3301 adds r3, #1 + 8003d24: e7f5 b.n 8003d12 + vPortFree(thePool->markers); + 8003d26: 6860 ldr r0, [r4, #4] + 8003d28: f000 fb84 bl 8004434 + vPortFree(thePool); + 8003d2c: 4620 mov r0, r4 + 8003d2e: f000 fb81 bl 8004434 + thePool = NULL; + 8003d32: 4634 mov r4, r6 + 8003d34: e7f0 b.n 8003d18 + vPortFree(thePool); + 8003d36: 4620 mov r0, r4 + 8003d38: f000 fb7c bl 8004434 + thePool = NULL; + 8003d3c: 4644 mov r4, r8 + return thePool; + 8003d3e: e7eb b.n 8003d18 + +08003d40 : +* @param pool_id memory pool ID obtain referenced with \ref osPoolCreate. +* @retval address of the allocated memory block or NULL in case of no memory available. +* @note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +*/ +void *osPoolAlloc (osPoolId pool_id) +{ + 8003d40: b570 push {r4, r5, r6, lr} + 8003d42: 4605 mov r5, r0 + 8003d44: f3ef 8405 mrs r4, IPSR + int dummy = 0; + void *p = NULL; + uint32_t i; + uint32_t index; + + if (inHandlerMode()) { + 8003d48: b17c cbz r4, 8003d6a + +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ +uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + 8003d4a: f3ef 8411 mrs r4, BASEPRI + 8003d4e: f04f 0350 mov.w r3, #80 ; 0x50 + 8003d52: f383 8811 msr BASEPRI, r3 + 8003d56: f3bf 8f6f isb sy + 8003d5a: f3bf 8f4f dsb sy + } + else { + vPortEnterCritical(); + } + + for (i = 0; i < pool_id->pool_sz; i++) { + 8003d5e: 68a9 ldr r1, [r5, #8] + 8003d60: 2200 movs r2, #0 + 8003d62: 428a cmp r2, r1 + 8003d64: d104 bne.n 8003d70 + void *p = NULL; + 8003d66: 2600 movs r6, #0 + 8003d68: e012 b.n 8003d90 + vPortEnterCritical(); + 8003d6a: f000 f97b bl 8004064 + 8003d6e: e7f6 b.n 8003d5e + index = pool_id->currentIndex + i; + 8003d70: 692b ldr r3, [r5, #16] + if (index >= pool_id->pool_sz) { + index = 0; + } + + if (pool_id->markers[index] == 0) { + 8003d72: 6868 ldr r0, [r5, #4] + index = pool_id->currentIndex + i; + 8003d74: 4413 add r3, r2 + index = 0; + 8003d76: 4299 cmp r1, r3 + 8003d78: bf98 it ls + 8003d7a: 2300 movls r3, #0 + if (pool_id->markers[index] == 0) { + 8003d7c: 18c6 adds r6, r0, r3 + 8003d7e: 5cc0 ldrb r0, [r0, r3] + 8003d80: b968 cbnz r0, 8003d9e + pool_id->markers[index] = 1; + 8003d82: 2201 movs r2, #1 + 8003d84: 7032 strb r2, [r6, #0] + p = (void *)((uint32_t)(pool_id->pool) + (index * pool_id->item_sz)); + 8003d86: 68ee ldr r6, [r5, #12] + 8003d88: 6828 ldr r0, [r5, #0] + pool_id->currentIndex = index; + 8003d8a: 612b str r3, [r5, #16] + p = (void *)((uint32_t)(pool_id->pool) + (index * pool_id->item_sz)); + 8003d8c: fb06 0603 mla r6, r6, r3, r0 + 8003d90: f3ef 8305 mrs r3, IPSR + break; + } + } + + if (inHandlerMode()) { + 8003d94: b12b cbz r3, 8003da2 +} +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + 8003d96: f384 8811 msr BASEPRI, r4 + else { + vPortExitCritical(); + } + + return p; +} + 8003d9a: 4630 mov r0, r6 + 8003d9c: bd70 pop {r4, r5, r6, pc} + for (i = 0; i < pool_id->pool_sz; i++) { + 8003d9e: 3201 adds r2, #1 + 8003da0: e7df b.n 8003d62 + vPortExitCritical(); + 8003da2: f000 f981 bl 80040a8 + return p; + 8003da6: e7f8 b.n 8003d9a + +08003da8 : +*/ +osStatus osPoolFree (osPoolId pool_id, void *block) +{ + uint32_t index; + + if (pool_id == NULL) { + 8003da8: b188 cbz r0, 8003dce + return osErrorParameter; + } + + if (block == NULL) { + 8003daa: b181 cbz r1, 8003dce + return osErrorParameter; + } + + if (block < pool_id->pool) { + 8003dac: 6803 ldr r3, [r0, #0] + 8003dae: 4299 cmp r1, r3 + 8003db0: d30d bcc.n 8003dce + return osErrorParameter; + } + + index = (uint32_t)block - (uint32_t)(pool_id->pool); + 8003db2: 1acb subs r3, r1, r3 + if (index % pool_id->item_sz) { + 8003db4: 68c1 ldr r1, [r0, #12] + 8003db6: fbb3 f2f1 udiv r2, r3, r1 + 8003dba: fb01 3112 mls r1, r1, r2, r3 + 8003dbe: b931 cbnz r1, 8003dce + return osErrorParameter; + } + index = index / pool_id->item_sz; + if (index >= pool_id->pool_sz) { + 8003dc0: 6883 ldr r3, [r0, #8] + 8003dc2: 429a cmp r2, r3 + 8003dc4: d203 bcs.n 8003dce + return osErrorParameter; + } + + pool_id->markers[index] = 0; + 8003dc6: 6843 ldr r3, [r0, #4] + + return osOK; + 8003dc8: 4608 mov r0, r1 + pool_id->markers[index] = 0; + 8003dca: 5499 strb r1, [r3, r2] + 8003dcc: 4770 bx lr + return osErrorParameter; + 8003dce: 2080 movs r0, #128 ; 0x80 +} + 8003dd0: 4770 bx lr + +08003dd2 : +* @param thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +* @retval mail queue ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +*/ +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) +{ + 8003dd2: b57f push {r0, r1, r2, r3, r4, r5, r6, lr} +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + (void) thread_id; + + osPoolDef_t pool_def = {queue_def->queue_sz, queue_def->item_sz, NULL}; + 8003dd4: 6803 ldr r3, [r0, #0] + + /* Create a mail queue control block */ + + *(queue_def->cb) = pvPortMalloc(sizeof(struct os_mailQ_cb)); + 8003dd6: 6884 ldr r4, [r0, #8] + osPoolDef_t pool_def = {queue_def->queue_sz, queue_def->item_sz, NULL}; + 8003dd8: 9301 str r3, [sp, #4] +{ + 8003dda: 4605 mov r5, r0 + osPoolDef_t pool_def = {queue_def->queue_sz, queue_def->item_sz, NULL}; + 8003ddc: 6843 ldr r3, [r0, #4] + 8003dde: 9302 str r3, [sp, #8] + 8003de0: 2600 movs r6, #0 + *(queue_def->cb) = pvPortMalloc(sizeof(struct os_mailQ_cb)); + 8003de2: 200c movs r0, #12 + osPoolDef_t pool_def = {queue_def->queue_sz, queue_def->item_sz, NULL}; + 8003de4: 9603 str r6, [sp, #12] + *(queue_def->cb) = pvPortMalloc(sizeof(struct os_mailQ_cb)); + 8003de6: f000 fa97 bl 8004318 + + if (*(queue_def->cb) == NULL) { + 8003dea: 68ab ldr r3, [r5, #8] + *(queue_def->cb) = pvPortMalloc(sizeof(struct os_mailQ_cb)); + 8003dec: 6020 str r0, [r4, #0] + if (*(queue_def->cb) == NULL) { + 8003dee: 681c ldr r4, [r3, #0] + 8003df0: b16c cbz r4, 8003e0e + return NULL; + } + (*(queue_def->cb))->queue_def = queue_def; + 8003df2: 6025 str r5, [r4, #0] + + /* Create a queue in FreeRTOS */ + (*(queue_def->cb))->handle = xQueueCreate(queue_def->queue_sz, sizeof(void *)); + 8003df4: 4632 mov r2, r6 + 8003df6: 2104 movs r1, #4 + 8003df8: 6828 ldr r0, [r5, #0] + 8003dfa: f000 fc13 bl 8004624 + + + if ((*(queue_def->cb))->handle == NULL) { + 8003dfe: 68ab ldr r3, [r5, #8] + (*(queue_def->cb))->handle = xQueueCreate(queue_def->queue_sz, sizeof(void *)); + 8003e00: 6060 str r0, [r4, #4] + if ((*(queue_def->cb))->handle == NULL) { + 8003e02: 681e ldr r6, [r3, #0] + 8003e04: 6874 ldr r4, [r6, #4] + 8003e06: b924 cbnz r4, 8003e12 + vPortFree(*(queue_def->cb)); + 8003e08: 4630 mov r0, r6 + + /* Create a mail pool */ + (*(queue_def->cb))->pool = osPoolCreate(&pool_def); + if ((*(queue_def->cb))->pool == NULL) { + //TODO: Delete queue. How to do it in FreeRTOS? + vPortFree(*(queue_def->cb)); + 8003e0a: f000 fb13 bl 8004434 + return NULL; + 8003e0e: 4620 mov r0, r4 + 8003e10: e008 b.n 8003e24 + (*(queue_def->cb))->pool = osPoolCreate(&pool_def); + 8003e12: a801 add r0, sp, #4 + 8003e14: f7ff ff5e bl 8003cd4 + if ((*(queue_def->cb))->pool == NULL) { + 8003e18: 68ab ldr r3, [r5, #8] + (*(queue_def->cb))->pool = osPoolCreate(&pool_def); + 8003e1a: 60b0 str r0, [r6, #8] + if ((*(queue_def->cb))->pool == NULL) { + 8003e1c: 6818 ldr r0, [r3, #0] + 8003e1e: 6884 ldr r4, [r0, #8] + 8003e20: 2c00 cmp r4, #0 + 8003e22: d0f2 beq.n 8003e0a + + return *(queue_def->cb); +#else + return NULL; +#endif +} + 8003e24: b004 add sp, #16 + 8003e26: bd70 pop {r4, r5, r6, pc} + +08003e28 : +{ + (void) millisec; + void *p; + + + if (queue_id == NULL) { + 8003e28: b110 cbz r0, 8003e30 + return NULL; + } + + p = osPoolAlloc(queue_id->pool); + 8003e2a: 6880 ldr r0, [r0, #8] + 8003e2c: f7ff bf88 b.w 8003d40 + + return p; +} + 8003e30: 4770 bx lr + ... + +08003e34 : +* @param mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMailPut (osMailQId queue_id, void *mail) +{ + 8003e34: b51f push {r0, r1, r2, r3, r4, lr} + 8003e36: 9101 str r1, [sp, #4] + portBASE_TYPE taskWoken; + + + if (queue_id == NULL) { + 8003e38: b318 cbz r0, 8003e82 + return osErrorParameter; + } + + taskWoken = pdFALSE; + 8003e3a: 2400 movs r4, #0 + 8003e3c: 9403 str r4, [sp, #12] + 8003e3e: f3ef 8305 mrs r3, IPSR + + if (inHandlerMode()) { + 8003e42: b1b3 cbz r3, 8003e72 + if (xQueueSendFromISR(queue_id->handle, &mail, &taskWoken) != pdTRUE) { + 8003e44: 4623 mov r3, r4 + 8003e46: aa03 add r2, sp, #12 + 8003e48: a901 add r1, sp, #4 + 8003e4a: 6840 ldr r0, [r0, #4] + 8003e4c: f000 fcc2 bl 80047d4 + 8003e50: 2801 cmp r0, #1 + 8003e52: d002 beq.n 8003e5a + return osErrorOS; + 8003e54: 20ff movs r0, #255 ; 0xff + return osErrorOS; + } + } + + return osOK; +} + 8003e56: b004 add sp, #16 + 8003e58: bd10 pop {r4, pc} + portEND_SWITCHING_ISR(taskWoken); + 8003e5a: 9b03 ldr r3, [sp, #12] + 8003e5c: b13b cbz r3, 8003e6e + 8003e5e: 4b0a ldr r3, [pc, #40] ; (8003e88 ) + 8003e60: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8003e64: 601a str r2, [r3, #0] + 8003e66: f3bf 8f4f dsb sy + 8003e6a: f3bf 8f6f isb sy + return osOK; + 8003e6e: 2000 movs r0, #0 + 8003e70: e7f1 b.n 8003e56 + if (xQueueSend(queue_id->handle, &mail, 0) != pdTRUE) { + 8003e72: 461a mov r2, r3 + 8003e74: a901 add r1, sp, #4 + 8003e76: 6840 ldr r0, [r0, #4] + 8003e78: f000 fbf6 bl 8004668 + 8003e7c: 2801 cmp r0, #1 + 8003e7e: d1e9 bne.n 8003e54 + 8003e80: e7f5 b.n 8003e6e + return osErrorParameter; + 8003e82: 2080 movs r0, #128 ; 0x80 + 8003e84: e7e7 b.n 8003e56 + 8003e86: bf00 nop + 8003e88: e000ed04 .word 0xe000ed04 + +08003e8c : +* @param millisec timeout value or 0 in case of no time-out +* @retval event that contains mail information or error code. +* @note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +*/ +osEvent osMailGet (osMailQId queue_id, uint32_t millisec) +{ + 8003e8c: b5f0 push {r4, r5, r6, r7, lr} + 8003e8e: b085 sub sp, #20 + 8003e90: 4604 mov r4, r0 + 8003e92: 4617 mov r7, r2 + 8003e94: 4608 mov r0, r1 + portBASE_TYPE taskWoken; + TickType_t ticks; + osEvent event; + + event.def.mail_id = queue_id; + 8003e96: 9103 str r1, [sp, #12] + 8003e98: ad01 add r5, sp, #4 + + if (queue_id == NULL) { + 8003e9a: b911 cbnz r1, 8003ea2 + event.status = osErrorParameter; + 8003e9c: 2380 movs r3, #128 ; 0x80 + if (xQueueReceive(queue_id->handle, &event.value.p, ticks) == pdTRUE) { + /* We have mail */ + event.status = osEventMail; + } + else { + event.status = (ticks == 0) ? osOK : osEventTimeout; + 8003e9e: 9301 str r3, [sp, #4] + 8003ea0: e019 b.n 8003ed6 + taskWoken = pdFALSE; + 8003ea2: 2600 movs r6, #0 + 8003ea4: 9600 str r6, [sp, #0] + 8003ea6: f3ef 8305 mrs r3, IPSR + if (inHandlerMode()) { + 8003eaa: b1db cbz r3, 8003ee4 + if (xQueueReceiveFromISR(queue_id->handle, &event.value.p, &taskWoken) == pdTRUE) { + 8003eac: 466a mov r2, sp + 8003eae: a902 add r1, sp, #8 + 8003eb0: 6840 ldr r0, [r0, #4] + 8003eb2: f000 fdb5 bl 8004a20 + 8003eb6: 2801 cmp r0, #1 + event.status = osEventMail; + 8003eb8: bf04 itt eq + 8003eba: 2320 moveq r3, #32 + 8003ebc: 9301 streq r3, [sp, #4] + portEND_SWITCHING_ISR(taskWoken); + 8003ebe: 9b00 ldr r3, [sp, #0] + event.status = osOK; + 8003ec0: bf18 it ne + 8003ec2: 9601 strne r6, [sp, #4] + portEND_SWITCHING_ISR(taskWoken); + 8003ec4: b13b cbz r3, 8003ed6 + 8003ec6: 4b0e ldr r3, [pc, #56] ; (8003f00 ) + 8003ec8: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8003ecc: 601a str r2, [r3, #0] + 8003ece: f3bf 8f4f dsb sy + 8003ed2: f3bf 8f6f isb sy + } + } + + return event; + 8003ed6: e895 0007 ldmia.w r5, {r0, r1, r2} + 8003eda: e884 0007 stmia.w r4, {r0, r1, r2} +} + 8003ede: 4620 mov r0, r4 + 8003ee0: b005 add sp, #20 + 8003ee2: bdf0 pop {r4, r5, r6, r7, pc} + if (xQueueReceive(queue_id->handle, &event.value.p, ticks) == pdTRUE) { + 8003ee4: a902 add r1, sp, #8 + 8003ee6: 6840 ldr r0, [r0, #4] + 8003ee8: f000 fcd6 bl 8004898 + 8003eec: 2801 cmp r0, #1 + 8003eee: d101 bne.n 8003ef4 + event.status = osEventMail; + 8003ef0: 2320 movs r3, #32 + 8003ef2: e7d4 b.n 8003e9e + event.status = (ticks == 0) ? osOK : osEventTimeout; + 8003ef4: 2f00 cmp r7, #0 + 8003ef6: bf0c ite eq + 8003ef8: 2300 moveq r3, #0 + 8003efa: 2340 movne r3, #64 ; 0x40 + 8003efc: e7cf b.n 8003e9e + 8003efe: bf00 nop + 8003f00: e000ed04 .word 0xe000ed04 + +08003f04 : +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMailFree (osMailQId queue_id, void *mail) +{ + if (queue_id == NULL) { + 8003f04: b110 cbz r0, 8003f0c + return osErrorParameter; + } + + return osPoolFree(queue_id->pool, mail); + 8003f06: 6880 ldr r0, [r0, #8] + 8003f08: f7ff bf4e b.w 8003da8 +} + 8003f0c: 2080 movs r0, #128 ; 0x80 + 8003f0e: 4770 bx lr + +08003f10 : +* @brief Handles the tick increment +* @param none. +* @retval none. +*/ +void osSystickHandler(void) +{ + 8003f10: b508 push {r3, lr} + +#if (INCLUDE_xTaskGetSchedulerState == 1 ) + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) + 8003f12: f001 f999 bl 8005248 + 8003f16: 2801 cmp r0, #1 + 8003f18: d003 beq.n 8003f22 +#endif /* INCLUDE_xTaskGetSchedulerState */ + xPortSysTickHandler(); +#if (INCLUDE_xTaskGetSchedulerState == 1 ) + } +#endif /* INCLUDE_xTaskGetSchedulerState */ +} + 8003f1a: e8bd 4008 ldmia.w sp!, {r3, lr} + xPortSysTickHandler(); + 8003f1e: f000 b909 b.w 8004134 + 8003f22: bd08 pop {r3, pc} + +08003f24 : +void vListInitialise( List_t * const pxList ) +{ + /* The list structure contains a list item which is used to mark the + end of the list. To initialise the list the list end is inserted + as the only list entry. */ + pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 8003f24: f100 0308 add.w r3, r0, #8 + 8003f28: 6043 str r3, [r0, #4] + + /* The list end value is the highest possible value in the list to + ensure it remains at the end of the list. */ + pxList->xListEnd.xItemValue = portMAX_DELAY; + 8003f2a: f04f 32ff mov.w r2, #4294967295 + + /* The list end next and previous pointers point to itself so we know + when the list is empty. */ + pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 8003f2e: 60c3 str r3, [r0, #12] + pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 8003f30: 6103 str r3, [r0, #16] + + pxList->uxNumberOfItems = ( UBaseType_t ) 0U; + 8003f32: 2300 movs r3, #0 + pxList->xListEnd.xItemValue = portMAX_DELAY; + 8003f34: 6082 str r2, [r0, #8] + pxList->uxNumberOfItems = ( UBaseType_t ) 0U; + 8003f36: 6003 str r3, [r0, #0] + 8003f38: 4770 bx lr + +08003f3a : +/*-----------------------------------------------------------*/ + +void vListInitialiseItem( ListItem_t * const pxItem ) +{ + /* Make sure the list item is not recorded as being on a list. */ + pxItem->pvContainer = NULL; + 8003f3a: 2300 movs r3, #0 + 8003f3c: 6103 str r3, [r0, #16] + 8003f3e: 4770 bx lr + +08003f40 : +} +/*-----------------------------------------------------------*/ + +void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) +{ +ListItem_t * const pxIndex = pxList->pxIndex; + 8003f40: 6843 ldr r3, [r0, #4] + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert a new list item into pxList, but rather than sort the list, + makes the new list item the last item to be removed by a call to + listGET_OWNER_OF_NEXT_ENTRY(). */ + pxNewListItem->pxNext = pxIndex; + 8003f42: 604b str r3, [r1, #4] + pxNewListItem->pxPrevious = pxIndex->pxPrevious; + 8003f44: 689a ldr r2, [r3, #8] + 8003f46: 608a str r2, [r1, #8] + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + pxIndex->pxPrevious->pxNext = pxNewListItem; + 8003f48: 689a ldr r2, [r3, #8] + 8003f4a: 6051 str r1, [r2, #4] + pxIndex->pxPrevious = pxNewListItem; + 8003f4c: 6099 str r1, [r3, #8] + + /* Remember which list the item is in. */ + pxNewListItem->pvContainer = ( void * ) pxList; + + ( pxList->uxNumberOfItems )++; + 8003f4e: 6803 ldr r3, [r0, #0] + pxNewListItem->pvContainer = ( void * ) pxList; + 8003f50: 6108 str r0, [r1, #16] + ( pxList->uxNumberOfItems )++; + 8003f52: 3301 adds r3, #1 + 8003f54: 6003 str r3, [r0, #0] + 8003f56: 4770 bx lr + +08003f58 : +/*-----------------------------------------------------------*/ + +void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) +{ +ListItem_t *pxIterator; +const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; + 8003f58: 680a ldr r2, [r1, #0] + new list item should be placed after it. This ensures that TCB's which are + stored in ready lists (all of which have the same xItemValue value) get a + share of the CPU. However, if the xItemValue is the same as the back marker + the iteration loop below will not end. Therefore the value is checked + first, and the algorithm slightly modified if necessary. */ + if( xValueOfInsertion == portMAX_DELAY ) + 8003f5a: 1c53 adds r3, r2, #1 +{ + 8003f5c: b530 push {r4, r5, lr} + if( xValueOfInsertion == portMAX_DELAY ) + 8003f5e: d10a bne.n 8003f76 + { + pxIterator = pxList->xListEnd.pxPrevious; + 8003f60: 6903 ldr r3, [r0, #16] + /* There is nothing to do here, just iterating to the wanted + insertion position. */ + } + } + + pxNewListItem->pxNext = pxIterator->pxNext; + 8003f62: 685a ldr r2, [r3, #4] + 8003f64: 604a str r2, [r1, #4] + pxNewListItem->pxNext->pxPrevious = pxNewListItem; + 8003f66: 6091 str r1, [r2, #8] + pxNewListItem->pxPrevious = pxIterator; + 8003f68: 608b str r3, [r1, #8] + pxIterator->pxNext = pxNewListItem; + 8003f6a: 6059 str r1, [r3, #4] + + /* Remember which list the item is in. This allows fast removal of the + item later. */ + pxNewListItem->pvContainer = ( void * ) pxList; + + ( pxList->uxNumberOfItems )++; + 8003f6c: 6803 ldr r3, [r0, #0] + pxNewListItem->pvContainer = ( void * ) pxList; + 8003f6e: 6108 str r0, [r1, #16] + ( pxList->uxNumberOfItems )++; + 8003f70: 3301 adds r3, #1 + 8003f72: 6003 str r3, [r0, #0] + 8003f74: bd30 pop {r4, r5, pc} + for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 8003f76: f100 0308 add.w r3, r0, #8 + 8003f7a: 685c ldr r4, [r3, #4] + 8003f7c: 6825 ldr r5, [r4, #0] + 8003f7e: 42aa cmp r2, r5 + 8003f80: d3ef bcc.n 8003f62 + 8003f82: 4623 mov r3, r4 + 8003f84: e7f9 b.n 8003f7a + +08003f86 : +{ +/* The list item knows which list it is in. Obtain the list from the list +item. */ +List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer; + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + 8003f86: 6841 ldr r1, [r0, #4] + 8003f88: 6882 ldr r2, [r0, #8] +List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer; + 8003f8a: 6903 ldr r3, [r0, #16] + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + 8003f8c: 608a str r2, [r1, #8] + pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; + 8003f8e: 6882 ldr r2, [r0, #8] + 8003f90: 6051 str r1, [r2, #4] + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + /* Make sure the index is left pointing to a valid item. */ + if( pxList->pxIndex == pxItemToRemove ) + 8003f92: 6859 ldr r1, [r3, #4] + 8003f94: 4288 cmp r0, r1 + { + pxList->pxIndex = pxItemToRemove->pxPrevious; + 8003f96: bf08 it eq + 8003f98: 605a streq r2, [r3, #4] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxItemToRemove->pvContainer = NULL; + 8003f9a: 2200 movs r2, #0 + 8003f9c: 6102 str r2, [r0, #16] + ( pxList->uxNumberOfItems )--; + 8003f9e: 6818 ldr r0, [r3, #0] + 8003fa0: 3801 subs r0, #1 + 8003fa2: 6018 str r0, [r3, #0] + + return pxList->uxNumberOfItems; +} + 8003fa4: 4770 bx lr + ... + +08003fa8 : + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + 8003fa8: 4b0a ldr r3, [pc, #40] ; (8003fd4 ) + 8003faa: 681b ldr r3, [r3, #0] + 8003fac: 3301 adds r3, #1 + 8003fae: d008 beq.n 8003fc2 + __asm volatile + 8003fb0: f04f 0350 mov.w r3, #80 ; 0x50 + 8003fb4: f383 8811 msr BASEPRI, r3 + 8003fb8: f3bf 8f6f isb sy + 8003fbc: f3bf 8f4f dsb sy + 8003fc0: e7fe b.n 8003fc0 + 8003fc2: f04f 0350 mov.w r3, #80 ; 0x50 + 8003fc6: f383 8811 msr BASEPRI, r3 + 8003fca: f3bf 8f6f isb sy + 8003fce: f3bf 8f4f dsb sy + 8003fd2: e7fe b.n 8003fd2 + 8003fd4: 20000190 .word 0x20000190 + +08003fd8 : +} +/*-----------------------------------------------------------*/ + +static void prvPortStartFirstTask( void ) +{ + __asm volatile( + 8003fd8: 4806 ldr r0, [pc, #24] ; (8003ff4 ) + 8003fda: 6800 ldr r0, [r0, #0] + 8003fdc: 6800 ldr r0, [r0, #0] + 8003fde: f380 8808 msr MSP, r0 + 8003fe2: b662 cpsie i + 8003fe4: b661 cpsie f + 8003fe6: f3bf 8f4f dsb sy + 8003fea: f3bf 8f6f isb sy + 8003fee: df00 svc 0 + 8003ff0: bf00 nop + 8003ff2: 0000 .short 0x0000 + 8003ff4: e000ed08 .word 0xe000ed08 + +08003ff8 : +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP( void ) +{ + __asm volatile + 8003ff8: f8df 000c ldr.w r0, [pc, #12] ; 8004008 + 8003ffc: 6801 ldr r1, [r0, #0] + 8003ffe: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 8004002: 6001 str r1, [r0, #0] + 8004004: 4770 bx lr + 8004006: 0000 .short 0x0000 + 8004008: e000ed88 .word 0xe000ed88 + +0800400c : + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + 800400c: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 8004010: f840 3c04 str.w r3, [r0, #-4] + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + 8004014: 4b07 ldr r3, [pc, #28] ; (8004034 ) + 8004016: f840 3c0c str.w r3, [r0, #-12] + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + 800401a: f021 0101 bic.w r1, r1, #1 + *pxTopOfStack = portINITIAL_EXEC_RETURN; + 800401e: f06f 0302 mvn.w r3, #2 + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + 8004022: f840 1c08 str.w r1, [r0, #-8] + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + 8004026: f840 2c20 str.w r2, [r0, #-32] + *pxTopOfStack = portINITIAL_EXEC_RETURN; + 800402a: f840 3c24 str.w r3, [r0, #-36] +} + 800402e: 3844 subs r0, #68 ; 0x44 + 8004030: 4770 bx lr + 8004032: bf00 nop + 8004034: 08003fa9 .word 0x08003fa9 + ... + +08004040 : + __asm volatile ( + 8004040: 4b07 ldr r3, [pc, #28] ; (8004060 ) + 8004042: 6819 ldr r1, [r3, #0] + 8004044: 6808 ldr r0, [r1, #0] + 8004046: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800404a: f380 8809 msr PSP, r0 + 800404e: f3bf 8f6f isb sy + 8004052: f04f 0000 mov.w r0, #0 + 8004056: f380 8811 msr BASEPRI, r0 + 800405a: 4770 bx lr + 800405c: f3af 8000 nop.w + +08004060 : + 8004060: 20003edc .word 0x20003edc + +08004064 : + 8004064: f04f 0350 mov.w r3, #80 ; 0x50 + 8004068: f383 8811 msr BASEPRI, r3 + 800406c: f3bf 8f6f isb sy + 8004070: f3bf 8f4f dsb sy + uxCriticalNesting++; + 8004074: 4a0a ldr r2, [pc, #40] ; (80040a0 ) + 8004076: 6813 ldr r3, [r2, #0] + 8004078: 3301 adds r3, #1 + if( uxCriticalNesting == 1 ) + 800407a: 2b01 cmp r3, #1 + uxCriticalNesting++; + 800407c: 6013 str r3, [r2, #0] + if( uxCriticalNesting == 1 ) + 800407e: d10d bne.n 800409c + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + 8004080: 4b08 ldr r3, [pc, #32] ; (80040a4 ) + 8004082: 681b ldr r3, [r3, #0] + 8004084: f013 0fff tst.w r3, #255 ; 0xff + 8004088: d008 beq.n 800409c + 800408a: f04f 0350 mov.w r3, #80 ; 0x50 + 800408e: f383 8811 msr BASEPRI, r3 + 8004092: f3bf 8f6f isb sy + 8004096: f3bf 8f4f dsb sy + 800409a: e7fe b.n 800409a + 800409c: 4770 bx lr + 800409e: bf00 nop + 80040a0: 20000190 .word 0x20000190 + 80040a4: e000ed04 .word 0xe000ed04 + +080040a8 : + configASSERT( uxCriticalNesting ); + 80040a8: 4a08 ldr r2, [pc, #32] ; (80040cc ) + 80040aa: 6813 ldr r3, [r2, #0] + 80040ac: b943 cbnz r3, 80040c0 + 80040ae: f04f 0350 mov.w r3, #80 ; 0x50 + 80040b2: f383 8811 msr BASEPRI, r3 + 80040b6: f3bf 8f6f isb sy + 80040ba: f3bf 8f4f dsb sy + 80040be: e7fe b.n 80040be + uxCriticalNesting--; + 80040c0: 3b01 subs r3, #1 + 80040c2: 6013 str r3, [r2, #0] + if( uxCriticalNesting == 0 ) + 80040c4: b90b cbnz r3, 80040ca + __asm volatile + 80040c6: f383 8811 msr BASEPRI, r3 + 80040ca: 4770 bx lr + 80040cc: 20000190 .word 0x20000190 + +080040d0 : + __asm volatile + 80040d0: f3ef 8009 mrs r0, PSP + 80040d4: f3bf 8f6f isb sy + 80040d8: 4b15 ldr r3, [pc, #84] ; (8004130 ) + 80040da: 681a ldr r2, [r3, #0] + 80040dc: f01e 0f10 tst.w lr, #16 + 80040e0: bf08 it eq + 80040e2: ed20 8a10 vstmdbeq r0!, {s16-s31} + 80040e6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80040ea: 6010 str r0, [r2, #0] + 80040ec: f84d 3d04 str.w r3, [sp, #-4]! + 80040f0: f04f 0050 mov.w r0, #80 ; 0x50 + 80040f4: f380 8811 msr BASEPRI, r0 + 80040f8: f3bf 8f4f dsb sy + 80040fc: f3bf 8f6f isb sy + 8004100: f000 ffbc bl 800507c + 8004104: f04f 0000 mov.w r0, #0 + 8004108: f380 8811 msr BASEPRI, r0 + 800410c: bc08 pop {r3} + 800410e: 6819 ldr r1, [r3, #0] + 8004110: 6808 ldr r0, [r1, #0] + 8004112: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8004116: f01e 0f10 tst.w lr, #16 + 800411a: bf08 it eq + 800411c: ecb0 8a10 vldmiaeq r0!, {s16-s31} + 8004120: f380 8809 msr PSP, r0 + 8004124: f3bf 8f6f isb sy + 8004128: 4770 bx lr + 800412a: bf00 nop + 800412c: f3af 8000 nop.w + +08004130 : + 8004130: 20003edc .word 0x20003edc + +08004134 : +{ + 8004134: b508 push {r3, lr} + __asm volatile + 8004136: f04f 0350 mov.w r3, #80 ; 0x50 + 800413a: f383 8811 msr BASEPRI, r3 + 800413e: f3bf 8f6f isb sy + 8004142: f3bf 8f4f dsb sy + if( xTaskIncrementTick() != pdFALSE ) + 8004146: f000 fe31 bl 8004dac + 800414a: b118 cbz r0, 8004154 + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + 800414c: 4b03 ldr r3, [pc, #12] ; (800415c ) + 800414e: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8004152: 601a str r2, [r3, #0] + __asm volatile + 8004154: 2300 movs r3, #0 + 8004156: f383 8811 msr BASEPRI, r3 + 800415a: bd08 pop {r3, pc} + 800415c: e000ed04 .word 0xe000ed04 + +08004160 : + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + 8004160: 4b06 ldr r3, [pc, #24] ; (800417c ) + 8004162: f44f 727a mov.w r2, #1000 ; 0x3e8 + 8004166: 681b ldr r3, [r3, #0] + 8004168: fbb3 f3f2 udiv r3, r3, r2 + 800416c: 4a04 ldr r2, [pc, #16] ; (8004180 ) + 800416e: 3b01 subs r3, #1 + 8004170: 6013 str r3, [r2, #0] + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); + 8004172: 4b04 ldr r3, [pc, #16] ; (8004184 ) + 8004174: 2207 movs r2, #7 + 8004176: 601a str r2, [r3, #0] + 8004178: 4770 bx lr + 800417a: bf00 nop + 800417c: 20000198 .word 0x20000198 + 8004180: e000e014 .word 0xe000e014 + 8004184: e000e010 .word 0xe000e010 + +08004188 : + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + 8004188: 4b31 ldr r3, [pc, #196] ; (8004250 ) + 800418a: 4a32 ldr r2, [pc, #200] ; (8004254 ) +{ + 800418c: b513 push {r0, r1, r4, lr} + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + 800418e: 6819 ldr r1, [r3, #0] + 8004190: 4291 cmp r1, r2 + 8004192: d108 bne.n 80041a6 + __asm volatile + 8004194: f04f 0350 mov.w r3, #80 ; 0x50 + 8004198: f383 8811 msr BASEPRI, r3 + 800419c: f3bf 8f6f isb sy + 80041a0: f3bf 8f4f dsb sy + 80041a4: e7fe b.n 80041a4 + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + 80041a6: 681a ldr r2, [r3, #0] + 80041a8: 4b2b ldr r3, [pc, #172] ; (8004258 ) + 80041aa: 429a cmp r2, r3 + 80041ac: d108 bne.n 80041c0 + 80041ae: f04f 0350 mov.w r3, #80 ; 0x50 + 80041b2: f383 8811 msr BASEPRI, r3 + 80041b6: f3bf 8f6f isb sy + 80041ba: f3bf 8f4f dsb sy + 80041be: e7fe b.n 80041be + ulOriginalPriority = *pucFirstUserPriorityRegister; + 80041c0: 4b26 ldr r3, [pc, #152] ; (800425c ) + 80041c2: 781a ldrb r2, [r3, #0] + 80041c4: b2d2 uxtb r2, r2 + 80041c6: 9201 str r2, [sp, #4] + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + 80041c8: 22ff movs r2, #255 ; 0xff + 80041ca: 701a strb r2, [r3, #0] + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + 80041cc: 781b ldrb r3, [r3, #0] + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + 80041ce: 4a24 ldr r2, [pc, #144] ; (8004260 ) + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + 80041d0: b2db uxtb r3, r3 + 80041d2: f88d 3003 strb.w r3, [sp, #3] + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + 80041d6: f89d 3003 ldrb.w r3, [sp, #3] + 80041da: f003 0350 and.w r3, r3, #80 ; 0x50 + 80041de: 7013 strb r3, [r2, #0] + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + 80041e0: 4b20 ldr r3, [pc, #128] ; (8004264 ) + 80041e2: 2207 movs r2, #7 + 80041e4: 601a str r2, [r3, #0] + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + 80041e6: 2100 movs r1, #0 + 80041e8: f89d 0003 ldrb.w r0, [sp, #3] + 80041ec: 0600 lsls r0, r0, #24 + 80041ee: f102 34ff add.w r4, r2, #4294967295 + 80041f2: d423 bmi.n 800423c + 80041f4: b101 cbz r1, 80041f8 + 80041f6: 601a str r2, [r3, #0] + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + 80041f8: 681a ldr r2, [r3, #0] + 80041fa: 0212 lsls r2, r2, #8 + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + 80041fc: f402 62e0 and.w r2, r2, #1792 ; 0x700 + 8004200: 601a str r2, [r3, #0] + *pucFirstUserPriorityRegister = ulOriginalPriority; + 8004202: 9b01 ldr r3, [sp, #4] + 8004204: 4a15 ldr r2, [pc, #84] ; (800425c ) + 8004206: b2db uxtb r3, r3 + 8004208: 7013 strb r3, [r2, #0] + portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; + 800420a: 4b17 ldr r3, [pc, #92] ; (8004268 ) + 800420c: 681a ldr r2, [r3, #0] + 800420e: f442 0270 orr.w r2, r2, #15728640 ; 0xf00000 + 8004212: 601a str r2, [r3, #0] + portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; + 8004214: 681a ldr r2, [r3, #0] + 8004216: f042 4270 orr.w r2, r2, #4026531840 ; 0xf0000000 + 800421a: 601a str r2, [r3, #0] + vPortSetupTimerInterrupt(); + 800421c: f7ff ffa0 bl 8004160 + uxCriticalNesting = 0; + 8004220: 4b12 ldr r3, [pc, #72] ; (800426c ) + 8004222: 2200 movs r2, #0 + 8004224: 601a str r2, [r3, #0] + vPortEnableVFP(); + 8004226: f7ff fee7 bl 8003ff8 + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + 800422a: 4a11 ldr r2, [pc, #68] ; (8004270 ) + 800422c: 6813 ldr r3, [r2, #0] + 800422e: f043 4340 orr.w r3, r3, #3221225472 ; 0xc0000000 + 8004232: 6013 str r3, [r2, #0] + prvPortStartFirstTask(); + 8004234: f7ff fed0 bl 8003fd8 + prvTaskExitError(); + 8004238: f7ff feb6 bl 8003fa8 + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + 800423c: f89d 2003 ldrb.w r2, [sp, #3] + 8004240: 0052 lsls r2, r2, #1 + 8004242: b2d2 uxtb r2, r2 + 8004244: f88d 2003 strb.w r2, [sp, #3] + 8004248: 2101 movs r1, #1 + 800424a: 4622 mov r2, r4 + 800424c: e7cc b.n 80041e8 + 800424e: bf00 nop + 8004250: e000ed00 .word 0xe000ed00 + 8004254: 410fc271 .word 0x410fc271 + 8004258: 410fc270 .word 0x410fc270 + 800425c: e000e400 .word 0xe000e400 + 8004260: 200002be .word 0x200002be + 8004264: 200002c0 .word 0x200002c0 + 8004268: e000ed20 .word 0xe000ed20 + 800426c: 20000190 .word 0x20000190 + 8004270: e000ef34 .word 0xe000ef34 + +08004274 : + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) ); + 8004274: f3ef 8305 mrs r3, IPSR + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + 8004278: 2b0f cmp r3, #15 + 800427a: d90e bls.n 800429a + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + 800427c: 4a10 ldr r2, [pc, #64] ; (80042c0 ) + 800427e: 5c9b ldrb r3, [r3, r2] + interrupt entry is as fast and simple as possible. + + The following links provide detailed information: + http://www.freertos.org/RTOS-Cortex-M3-M4.html + http://www.freertos.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + 8004280: 4a10 ldr r2, [pc, #64] ; (80042c4 ) + 8004282: 7812 ldrb r2, [r2, #0] + 8004284: 429a cmp r2, r3 + 8004286: d908 bls.n 800429a + 8004288: f04f 0350 mov.w r3, #80 ; 0x50 + 800428c: f383 8811 msr BASEPRI, r3 + 8004290: f3bf 8f6f isb sy + 8004294: f3bf 8f4f dsb sy + 8004298: e7fe b.n 8004298 + configuration then the correct setting can be achieved on all Cortex-M + devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + scheduler. Note however that some vendor specific peripheral libraries + assume a non-zero priority group setting, in which cases using a value + of zero will result in unpredicable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + 800429a: 4b0b ldr r3, [pc, #44] ; (80042c8 ) + 800429c: 4a0b ldr r2, [pc, #44] ; (80042cc ) + 800429e: 681b ldr r3, [r3, #0] + 80042a0: 6812 ldr r2, [r2, #0] + 80042a2: f403 63e0 and.w r3, r3, #1792 ; 0x700 + 80042a6: 4293 cmp r3, r2 + 80042a8: d908 bls.n 80042bc + 80042aa: f04f 0350 mov.w r3, #80 ; 0x50 + 80042ae: f383 8811 msr BASEPRI, r3 + 80042b2: f3bf 8f6f isb sy + 80042b6: f3bf 8f4f dsb sy + 80042ba: e7fe b.n 80042ba + 80042bc: 4770 bx lr + 80042be: bf00 nop + 80042c0: e000e3f0 .word 0xe000e3f0 + 80042c4: 200002be .word 0x200002be + 80042c8: e000ed0c .word 0xe000ed0c + 80042cc: 200002c0 .word 0x200002c0 + +080042d0 : + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) +{ + 80042d0: b510 push {r4, lr} +BlockLink_t *pxIterator; +uint8_t *puc; + + /* Iterate through the list until a block is found that has a higher address + than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + 80042d2: 4b0f ldr r3, [pc, #60] ; (8004310 ) + 80042d4: 681a ldr r2, [r3, #0] + 80042d6: 4282 cmp r2, r0 + 80042d8: d318 bcc.n 800430c + } + + /* Do the block being inserted, and the block it is being inserted after + make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + 80042da: 685c ldr r4, [r3, #4] + 80042dc: 1919 adds r1, r3, r4 + 80042de: 4288 cmp r0, r1 + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + 80042e0: bf01 itttt eq + 80042e2: 6841 ldreq r1, [r0, #4] + 80042e4: 4618 moveq r0, r3 + 80042e6: 1909 addeq r1, r1, r4 + 80042e8: 6059 streq r1, [r3, #4] + } + + /* Do the block being inserted, and the block it is being inserted before + make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + 80042ea: 6844 ldr r4, [r0, #4] + 80042ec: 1901 adds r1, r0, r4 + 80042ee: 428a cmp r2, r1 + 80042f0: d107 bne.n 8004302 + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + 80042f2: 4908 ldr r1, [pc, #32] ; (8004314 ) + 80042f4: 6809 ldr r1, [r1, #0] + 80042f6: 428a cmp r2, r1 + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + 80042f8: bf1f itttt ne + 80042fa: 6851 ldrne r1, [r2, #4] + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + 80042fc: 6812 ldrne r2, [r2, #0] + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + 80042fe: 1909 addne r1, r1, r4 + 8004300: 6041 strne r1, [r0, #4] + + /* If the block being inserted plugged a gab, so was merged with the block + before and the block after, then it's pxNextFreeBlock pointer will have + already been set, and should not be set here as that would make it point + to itself. */ + if( pxIterator != pxBlockToInsert ) + 8004302: 4298 cmp r0, r3 + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + 8004304: 6002 str r2, [r0, #0] + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + 8004306: bf18 it ne + 8004308: 6018 strne r0, [r3, #0] + 800430a: bd10 pop {r4, pc} + 800430c: 4613 mov r3, r2 + 800430e: e7e1 b.n 80042d4 + 8004310: 20003ed4 .word 0x20003ed4 + 8004314: 200002c4 .word 0x200002c4 + +08004318 : +{ + 8004318: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800431c: 4604 mov r4, r0 + vTaskSuspendAll(); + 800431e: f000 fd3d bl 8004d9c + if( pxEnd == NULL ) + 8004322: 493e ldr r1, [pc, #248] ; (800441c ) + 8004324: 4d3e ldr r5, [pc, #248] ; (8004420 ) + 8004326: 680b ldr r3, [r1, #0] + 8004328: bb0b cbnz r3, 800436e + uxAddress = ( size_t ) ucHeap; + 800432a: 4a3e ldr r2, [pc, #248] ; (8004424 ) + if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + 800432c: 0756 lsls r6, r2, #29 + uxAddress += ( portBYTE_ALIGNMENT - 1 ); + 800432e: bf1f itttt ne + 8004330: 1dd0 addne r0, r2, #7 + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + 8004332: f020 0007 bicne.w r0, r0, #7 + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + 8004336: f502 5370 addne.w r3, r2, #15360 ; 0x3c00 + 800433a: 1a1b subne r3, r3, r0 + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + 800433c: bf14 ite ne + 800433e: 4602 movne r2, r0 +size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; + 8004340: f44f 5370 moveq.w r3, #15360 ; 0x3c00 + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + 8004344: 4413 add r3, r2 + uxAddress -= xHeapStructSize; + 8004346: 3b08 subs r3, #8 + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + 8004348: f023 0307 bic.w r3, r3, #7 + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + 800434c: 4e36 ldr r6, [pc, #216] ; (8004428 ) + pxEnd = ( void * ) uxAddress; + 800434e: 600b str r3, [r1, #0] + xStart.xBlockSize = ( size_t ) 0; + 8004350: 2000 movs r0, #0 + 8004352: 6070 str r0, [r6, #4] + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + 8004354: 6032 str r2, [r6, #0] + pxEnd->xBlockSize = 0; + 8004356: 6058 str r0, [r3, #4] + pxEnd->pxNextFreeBlock = NULL; + 8004358: 6018 str r0, [r3, #0] + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + 800435a: 1a98 subs r0, r3, r2 + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + 800435c: 6013 str r3, [r2, #0] + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + 800435e: 4b33 ldr r3, [pc, #204] ; (800442c ) + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + 8004360: 6050 str r0, [r2, #4] + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + 8004362: 6018 str r0, [r3, #0] + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + 8004364: 4b32 ldr r3, [pc, #200] ; (8004430 ) + 8004366: 6018 str r0, [r3, #0] + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); + 8004368: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 + 800436c: 602b str r3, [r5, #0] + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + 800436e: 682f ldr r7, [r5, #0] + 8004370: 4227 tst r7, r4 + 8004372: d116 bne.n 80043a2 + if( xWantedSize > 0 ) + 8004374: 2c00 cmp r4, #0 + 8004376: d041 beq.n 80043fc + xWantedSize += xHeapStructSize; + 8004378: f104 0308 add.w r3, r4, #8 + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + 800437c: 0758 lsls r0, r3, #29 + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); + 800437e: bf1c itt ne + 8004380: f023 0307 bicne.w r3, r3, #7 + 8004384: 3308 addne r3, #8 + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + 8004386: b163 cbz r3, 80043a2 + 8004388: 4a29 ldr r2, [pc, #164] ; (8004430 ) + 800438a: 6816 ldr r6, [r2, #0] + 800438c: 42b3 cmp r3, r6 + 800438e: 4690 mov r8, r2 + 8004390: d807 bhi.n 80043a2 + pxBlock = xStart.pxNextFreeBlock; + 8004392: 4a25 ldr r2, [pc, #148] ; (8004428 ) + 8004394: 6815 ldr r5, [r2, #0] + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + 8004396: 6868 ldr r0, [r5, #4] + 8004398: 4283 cmp r3, r0 + 800439a: d804 bhi.n 80043a6 + if( pxBlock != pxEnd ) + 800439c: 6809 ldr r1, [r1, #0] + 800439e: 428d cmp r5, r1 + 80043a0: d107 bne.n 80043b2 +void *pvReturn = NULL; + 80043a2: 2400 movs r4, #0 + 80043a4: e02a b.n 80043fc + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + 80043a6: 682c ldr r4, [r5, #0] + 80043a8: 2c00 cmp r4, #0 + 80043aa: d0f7 beq.n 800439c + 80043ac: 462a mov r2, r5 + 80043ae: 4625 mov r5, r4 + 80043b0: e7f1 b.n 8004396 + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + 80043b2: 6829 ldr r1, [r5, #0] + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + 80043b4: 6814 ldr r4, [r2, #0] + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + 80043b6: 6011 str r1, [r2, #0] + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + 80043b8: 1ac2 subs r2, r0, r3 + 80043ba: 2a10 cmp r2, #16 + 80043bc: d90f bls.n 80043de + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + 80043be: 18e8 adds r0, r5, r3 + configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); + 80043c0: 0741 lsls r1, r0, #29 + 80043c2: d008 beq.n 80043d6 + 80043c4: f04f 0350 mov.w r3, #80 ; 0x50 + 80043c8: f383 8811 msr BASEPRI, r3 + 80043cc: f3bf 8f6f isb sy + 80043d0: f3bf 8f4f dsb sy + 80043d4: e7fe b.n 80043d4 + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + 80043d6: 6042 str r2, [r0, #4] + pxBlock->xBlockSize = xWantedSize; + 80043d8: 606b str r3, [r5, #4] + prvInsertBlockIntoFreeList( pxNewBlockLink ); + 80043da: f7ff ff79 bl 80042d0 + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + 80043de: 4913 ldr r1, [pc, #76] ; (800442c ) + xFreeBytesRemaining -= pxBlock->xBlockSize; + 80043e0: 686b ldr r3, [r5, #4] + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + 80043e2: 6808 ldr r0, [r1, #0] + xFreeBytesRemaining -= pxBlock->xBlockSize; + 80043e4: 1af6 subs r6, r6, r3 + pxBlock->xBlockSize |= xBlockAllocatedBit; + 80043e6: 431f orrs r7, r3 + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + 80043e8: 4286 cmp r6, r0 + pxBlock->pxNextFreeBlock = NULL; + 80043ea: f04f 0300 mov.w r3, #0 + xFreeBytesRemaining -= pxBlock->xBlockSize; + 80043ee: f8c8 6000 str.w r6, [r8] + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + 80043f2: bf38 it cc + 80043f4: 600e strcc r6, [r1, #0] + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + 80043f6: 3408 adds r4, #8 + pxBlock->xBlockSize |= xBlockAllocatedBit; + 80043f8: 606f str r7, [r5, #4] + pxBlock->pxNextFreeBlock = NULL; + 80043fa: 602b str r3, [r5, #0] + ( void ) xTaskResumeAll(); + 80043fc: f000 fd68 bl 8004ed0 + configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); + 8004400: 0763 lsls r3, r4, #29 + 8004402: d008 beq.n 8004416 + 8004404: f04f 0350 mov.w r3, #80 ; 0x50 + 8004408: f383 8811 msr BASEPRI, r3 + 800440c: f3bf 8f6f isb sy + 8004410: f3bf 8f4f dsb sy + 8004414: e7fe b.n 8004414 +} + 8004416: 4620 mov r0, r4 + 8004418: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 800441c: 200002c4 .word 0x200002c4 + 8004420: 20003ec8 .word 0x20003ec8 + 8004424: 200002c8 .word 0x200002c8 + 8004428: 20003ed4 .word 0x20003ed4 + 800442c: 20003ed0 .word 0x20003ed0 + 8004430: 20003ecc .word 0x20003ecc + +08004434 : +{ + 8004434: b510 push {r4, lr} + if( pv != NULL ) + 8004436: 4604 mov r4, r0 + 8004438: b370 cbz r0, 8004498 + configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + 800443a: 4a18 ldr r2, [pc, #96] ; (800449c ) + 800443c: f850 3c04 ldr.w r3, [r0, #-4] + 8004440: 6812 ldr r2, [r2, #0] + 8004442: 4213 tst r3, r2 + 8004444: d108 bne.n 8004458 + 8004446: f04f 0350 mov.w r3, #80 ; 0x50 + 800444a: f383 8811 msr BASEPRI, r3 + 800444e: f3bf 8f6f isb sy + 8004452: f3bf 8f4f dsb sy + 8004456: e7fe b.n 8004456 + configASSERT( pxLink->pxNextFreeBlock == NULL ); + 8004458: f850 1c08 ldr.w r1, [r0, #-8] + 800445c: b141 cbz r1, 8004470 + 800445e: f04f 0350 mov.w r3, #80 ; 0x50 + 8004462: f383 8811 msr BASEPRI, r3 + 8004466: f3bf 8f6f isb sy + 800446a: f3bf 8f4f dsb sy + 800446e: e7fe b.n 800446e + pxLink->xBlockSize &= ~xBlockAllocatedBit; + 8004470: ea23 0302 bic.w r3, r3, r2 + 8004474: f840 3c04 str.w r3, [r0, #-4] + vTaskSuspendAll(); + 8004478: f000 fc90 bl 8004d9c + xFreeBytesRemaining += pxLink->xBlockSize; + 800447c: 4a08 ldr r2, [pc, #32] ; (80044a0 ) + 800447e: f854 3c04 ldr.w r3, [r4, #-4] + 8004482: 6811 ldr r1, [r2, #0] + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + 8004484: f1a4 0008 sub.w r0, r4, #8 + xFreeBytesRemaining += pxLink->xBlockSize; + 8004488: 440b add r3, r1 + 800448a: 6013 str r3, [r2, #0] + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + 800448c: f7ff ff20 bl 80042d0 +} + 8004490: e8bd 4010 ldmia.w sp!, {r4, lr} + ( void ) xTaskResumeAll(); + 8004494: f000 bd1c b.w 8004ed0 + 8004498: bd10 pop {r4, pc} + 800449a: bf00 nop + 800449c: 20003ec8 .word 0x20003ec8 + 80044a0: 20003ecc .word 0x20003ecc + +080044a4 : + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) +{ + 80044a4: b570 push {r4, r5, r6, lr} + 80044a6: 4615 mov r5, r2 + + /* This function is called from a critical section. */ + + uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) + 80044a8: 6c02 ldr r2, [r0, #64] ; 0x40 + uxMessagesWaiting = pxQueue->uxMessagesWaiting; + 80044aa: 6b86 ldr r6, [r0, #56] ; 0x38 +{ + 80044ac: 4604 mov r4, r0 + if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) + 80044ae: b942 cbnz r2, 80044c2 + { + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + 80044b0: 6805 ldr r5, [r0, #0] + 80044b2: b99d cbnz r5, 80044dc + { + /* The mutex is no longer being held. */ + xReturn = xTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder ); + 80044b4: 6840 ldr r0, [r0, #4] + 80044b6: f000 ff1d bl 80052f4 + pxQueue->pxMutexHolder = NULL; + 80044ba: 6065 str r5, [r4, #4] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + pxQueue->uxMessagesWaiting = uxMessagesWaiting + 1; + 80044bc: 3601 adds r6, #1 + 80044be: 63a6 str r6, [r4, #56] ; 0x38 + + return xReturn; +} + 80044c0: bd70 pop {r4, r5, r6, pc} + else if( xPosition == queueSEND_TO_BACK ) + 80044c2: b96d cbnz r5, 80044e0 + ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. */ + 80044c4: 6880 ldr r0, [r0, #8] + 80044c6: f001 fef5 bl 80062b4 + pxQueue->pcWriteTo += pxQueue->uxItemSize; + 80044ca: 68a3 ldr r3, [r4, #8] + 80044cc: 6c22 ldr r2, [r4, #64] ; 0x40 + 80044ce: 4413 add r3, r2 + if( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + 80044d0: 6862 ldr r2, [r4, #4] + pxQueue->pcWriteTo += pxQueue->uxItemSize; + 80044d2: 60a3 str r3, [r4, #8] + if( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + 80044d4: 4293 cmp r3, r2 + 80044d6: d301 bcc.n 80044dc + pxQueue->pcWriteTo = pxQueue->pcHead; + 80044d8: 6823 ldr r3, [r4, #0] + 80044da: 60a3 str r3, [r4, #8] +BaseType_t xReturn = pdFALSE; + 80044dc: 2000 movs r0, #0 + 80044de: e7ed b.n 80044bc + ( void ) memcpy( ( void * ) pxQueue->u.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 80044e0: 68c0 ldr r0, [r0, #12] + 80044e2: f001 fee7 bl 80062b4 + pxQueue->u.pcReadFrom -= pxQueue->uxItemSize; + 80044e6: 6c23 ldr r3, [r4, #64] ; 0x40 + 80044e8: 68e2 ldr r2, [r4, #12] + if( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + 80044ea: 6821 ldr r1, [r4, #0] + pxQueue->u.pcReadFrom -= pxQueue->uxItemSize; + 80044ec: 425b negs r3, r3 + 80044ee: 441a add r2, r3 + if( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + 80044f0: 428a cmp r2, r1 + pxQueue->u.pcReadFrom -= pxQueue->uxItemSize; + 80044f2: 60e2 str r2, [r4, #12] + pxQueue->u.pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize ); + 80044f4: bf3e ittt cc + 80044f6: 6862 ldrcc r2, [r4, #4] + 80044f8: 189b addcc r3, r3, r2 + 80044fa: 60e3 strcc r3, [r4, #12] + if( xPosition == queueOVERWRITE ) + 80044fc: 2d02 cmp r5, #2 + 80044fe: d1ed bne.n 80044dc + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + 8004500: b10e cbz r6, 8004506 + --uxMessagesWaiting; + 8004502: 3e01 subs r6, #1 + 8004504: e7ea b.n 80044dc +BaseType_t xReturn = pdFALSE; + 8004506: 4630 mov r0, r6 + 8004508: e7d8 b.n 80044bc + +0800450a : +/*-----------------------------------------------------------*/ + +static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) +{ + 800450a: 4603 mov r3, r0 + 800450c: b410 push {r4} + if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) + 800450e: 6c1a ldr r2, [r3, #64] ; 0x40 +{ + 8004510: 4608 mov r0, r1 + if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) + 8004512: b162 cbz r2, 800452e + { + pxQueue->u.pcReadFrom += pxQueue->uxItemSize; + 8004514: 68d9 ldr r1, [r3, #12] + if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ + 8004516: 685c ldr r4, [r3, #4] + pxQueue->u.pcReadFrom += pxQueue->uxItemSize; + 8004518: 4411 add r1, r2 + if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ + 800451a: 42a1 cmp r1, r4 + pxQueue->u.pcReadFrom += pxQueue->uxItemSize; + 800451c: 60d9 str r1, [r3, #12] + { + pxQueue->u.pcReadFrom = pxQueue->pcHead; + 800451e: bf24 itt cs + 8004520: 6819 ldrcs r1, [r3, #0] + 8004522: 60d9 strcs r1, [r3, #12] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */ + 8004524: 68d9 ldr r1, [r3, #12] + } +} + 8004526: f85d 4b04 ldr.w r4, [sp], #4 + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */ + 800452a: f001 bec3 b.w 80062b4 +} + 800452e: f85d 4b04 ldr.w r4, [sp], #4 + 8004532: 4770 bx lr + +08004534 : +/*-----------------------------------------------------------*/ + +static void prvUnlockQueue( Queue_t * const pxQueue ) +{ + 8004534: b570 push {r4, r5, r6, lr} + 8004536: 4604 mov r4, r0 + + /* The lock counts contains the number of extra data items placed or + removed from the queue while the queue was locked. When a queue is + locked items can be added or removed, but the event lists cannot be + updated. */ + taskENTER_CRITICAL(); + 8004538: f7ff fd94 bl 8004064 + { + int8_t cTxLock = pxQueue->cTxLock; + 800453c: f894 5045 ldrb.w r5, [r4, #69] ; 0x45 + { + /* Tasks that are removed from the event list will get added to + the pending ready list as the scheduler is still suspended. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 8004540: f104 0624 add.w r6, r4, #36 ; 0x24 + int8_t cTxLock = pxQueue->cTxLock; + 8004544: b26d sxtb r5, r5 + while( cTxLock > queueLOCKED_UNMODIFIED ) + 8004546: 2d00 cmp r5, #0 + 8004548: dc14 bgt.n 8004574 + #endif /* configUSE_QUEUE_SETS */ + + --cTxLock; + } + + pxQueue->cTxLock = queueUNLOCKED; + 800454a: 23ff movs r3, #255 ; 0xff + 800454c: f884 3045 strb.w r3, [r4, #69] ; 0x45 + } + taskEXIT_CRITICAL(); + 8004550: f7ff fdaa bl 80040a8 + + /* Do the same for the Rx lock. */ + taskENTER_CRITICAL(); + 8004554: f7ff fd86 bl 8004064 + { + int8_t cRxLock = pxQueue->cRxLock; + 8004558: f894 5044 ldrb.w r5, [r4, #68] ; 0x44 + + while( cRxLock > queueLOCKED_UNMODIFIED ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 800455c: f104 0610 add.w r6, r4, #16 + int8_t cRxLock = pxQueue->cRxLock; + 8004560: b26d sxtb r5, r5 + while( cRxLock > queueLOCKED_UNMODIFIED ) + 8004562: 2d00 cmp r5, #0 + 8004564: dc12 bgt.n 800458c + { + break; + } + } + + pxQueue->cRxLock = queueUNLOCKED; + 8004566: 23ff movs r3, #255 ; 0xff + 8004568: f884 3044 strb.w r3, [r4, #68] ; 0x44 + } + taskEXIT_CRITICAL(); +} + 800456c: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + taskEXIT_CRITICAL(); + 8004570: f7ff bd9a b.w 80040a8 + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 8004574: 6a63 ldr r3, [r4, #36] ; 0x24 + 8004576: 2b00 cmp r3, #0 + 8004578: d0e7 beq.n 800454a + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 800457a: 4630 mov r0, r6 + 800457c: f000 fdd2 bl 8005124 + 8004580: b108 cbz r0, 8004586 + vTaskMissedYield(); + 8004582: f000 fe5b bl 800523c + 8004586: 3d01 subs r5, #1 + 8004588: b26d sxtb r5, r5 + 800458a: e7dc b.n 8004546 + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 800458c: 6923 ldr r3, [r4, #16] + 800458e: 2b00 cmp r3, #0 + 8004590: d0e9 beq.n 8004566 + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 8004592: 4630 mov r0, r6 + 8004594: f000 fdc6 bl 8005124 + 8004598: b108 cbz r0, 800459e + vTaskMissedYield(); + 800459a: f000 fe4f bl 800523c + 800459e: 3d01 subs r5, #1 + 80045a0: b26d sxtb r5, r5 + 80045a2: e7de b.n 8004562 + +080045a4 : +{ + 80045a4: b538 push {r3, r4, r5, lr} + 80045a6: 460d mov r5, r1 + configASSERT( pxQueue ); + 80045a8: 4604 mov r4, r0 + 80045aa: b940 cbnz r0, 80045be + 80045ac: f04f 0350 mov.w r3, #80 ; 0x50 + 80045b0: f383 8811 msr BASEPRI, r3 + 80045b4: f3bf 8f6f isb sy + 80045b8: f3bf 8f4f dsb sy + 80045bc: e7fe b.n 80045bc + taskENTER_CRITICAL(); + 80045be: f7ff fd51 bl 8004064 + pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); + 80045c2: 6c20 ldr r0, [r4, #64] ; 0x40 + 80045c4: 6be3 ldr r3, [r4, #60] ; 0x3c + 80045c6: 6822 ldr r2, [r4, #0] + pxQueue->pcWriteTo = pxQueue->pcHead; + 80045c8: 60a2 str r2, [r4, #8] + pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); + 80045ca: 4343 muls r3, r0 + 80045cc: 18d1 adds r1, r2, r3 + pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize ); + 80045ce: 1a1b subs r3, r3, r0 + 80045d0: 4413 add r3, r2 + pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); + 80045d2: 6061 str r1, [r4, #4] + pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize ); + 80045d4: 60e3 str r3, [r4, #12] + pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; + 80045d6: 2100 movs r1, #0 + pxQueue->cRxLock = queueUNLOCKED; + 80045d8: 23ff movs r3, #255 ; 0xff + pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; + 80045da: 63a1 str r1, [r4, #56] ; 0x38 + pxQueue->cRxLock = queueUNLOCKED; + 80045dc: f884 3044 strb.w r3, [r4, #68] ; 0x44 + pxQueue->cTxLock = queueUNLOCKED; + 80045e0: f884 3045 strb.w r3, [r4, #69] ; 0x45 + if( xNewQueue == pdFALSE ) + 80045e4: b995 cbnz r5, 800460c + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 80045e6: 6923 ldr r3, [r4, #16] + 80045e8: b163 cbz r3, 8004604 + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 80045ea: f104 0010 add.w r0, r4, #16 + 80045ee: f000 fd99 bl 8005124 + 80045f2: b138 cbz r0, 8004604 + queueYIELD_IF_USING_PREEMPTION(); + 80045f4: 4b0a ldr r3, [pc, #40] ; (8004620 ) + 80045f6: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 80045fa: 601a str r2, [r3, #0] + 80045fc: f3bf 8f4f dsb sy + 8004600: f3bf 8f6f isb sy + taskEXIT_CRITICAL(); + 8004604: f7ff fd50 bl 80040a8 +} + 8004608: 2001 movs r0, #1 + 800460a: bd38 pop {r3, r4, r5, pc} + vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); + 800460c: f104 0010 add.w r0, r4, #16 + 8004610: f7ff fc88 bl 8003f24 + vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); + 8004614: f104 0024 add.w r0, r4, #36 ; 0x24 + 8004618: f7ff fc84 bl 8003f24 + 800461c: e7f2 b.n 8004604 + 800461e: bf00 nop + 8004620: e000ed04 .word 0xe000ed04 + +08004624 : + { + 8004624: b570 push {r4, r5, r6, lr} + 8004626: 460d mov r5, r1 + configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); + 8004628: 4606 mov r6, r0 + 800462a: b940 cbnz r0, 800463e + 800462c: f04f 0350 mov.w r3, #80 ; 0x50 + 8004630: f383 8811 msr BASEPRI, r3 + 8004634: f3bf 8f6f isb sy + 8004638: f3bf 8f4f dsb sy + 800463c: e7fe b.n 800463c + xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 800463e: 4348 muls r0, r1 + pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); + 8004640: 3048 adds r0, #72 ; 0x48 + 8004642: f7ff fe69 bl 8004318 + if( pxNewQueue != NULL ) + 8004646: 4604 mov r4, r0 + 8004648: b138 cbz r0, 800465a + if( uxItemSize == ( UBaseType_t ) 0 ) + 800464a: b945 cbnz r5, 800465e + pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; + 800464c: 6020 str r0, [r4, #0] + pxNewQueue->uxLength = uxQueueLength; + 800464e: 63e6 str r6, [r4, #60] ; 0x3c + pxNewQueue->uxItemSize = uxItemSize; + 8004650: 6425 str r5, [r4, #64] ; 0x40 + ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); + 8004652: 2101 movs r1, #1 + 8004654: 4620 mov r0, r4 + 8004656: f7ff ffa5 bl 80045a4 + } + 800465a: 4620 mov r0, r4 + 800465c: bd70 pop {r4, r5, r6, pc} + pucQueueStorage = ( ( uint8_t * ) pxNewQueue ) + sizeof( Queue_t ); + 800465e: f100 0348 add.w r3, r0, #72 ; 0x48 + pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; + 8004662: 6003 str r3, [r0, #0] + 8004664: e7f3 b.n 800464e + ... + +08004668 : +{ + 8004668: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 800466c: 4689 mov r9, r1 + 800466e: 9201 str r2, [sp, #4] + 8004670: 461f mov r7, r3 + configASSERT( pxQueue ); + 8004672: 4604 mov r4, r0 + 8004674: b940 cbnz r0, 8004688 + 8004676: f04f 0350 mov.w r3, #80 ; 0x50 + 800467a: f383 8811 msr BASEPRI, r3 + 800467e: f3bf 8f6f isb sy + 8004682: f3bf 8f4f dsb sy + 8004686: e7fe b.n 8004686 + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 8004688: 2900 cmp r1, #0 + 800468a: f040 8088 bne.w 800479e + 800468e: 6c03 ldr r3, [r0, #64] ; 0x40 + 8004690: 2b00 cmp r3, #0 + 8004692: f000 8084 beq.w 800479e + 8004696: f04f 0350 mov.w r3, #80 ; 0x50 + 800469a: f383 8811 msr BASEPRI, r3 + 800469e: f3bf 8f6f isb sy + 80046a2: f3bf 8f4f dsb sy + 80046a6: e7fe b.n 80046a6 + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + 80046a8: 9e01 ldr r6, [sp, #4] + 80046aa: 2e00 cmp r6, #0 + 80046ac: f000 8082 beq.w 80047b4 + 80046b0: f04f 0350 mov.w r3, #80 ; 0x50 + 80046b4: f383 8811 msr BASEPRI, r3 + 80046b8: f3bf 8f6f isb sy + 80046bc: f3bf 8f4f dsb sy + 80046c0: e7fe b.n 80046c0 + if( xTicksToWait == ( TickType_t ) 0 ) + 80046c2: 9d01 ldr r5, [sp, #4] + 80046c4: b91d cbnz r5, 80046ce + taskEXIT_CRITICAL(); + 80046c6: f7ff fcef bl 80040a8 + return errQUEUE_FULL; + 80046ca: 2000 movs r0, #0 + 80046cc: e058 b.n 8004780 + else if( xEntryTimeSet == pdFALSE ) + 80046ce: b916 cbnz r6, 80046d6 + vTaskSetTimeOutState( &xTimeOut ); + 80046d0: a802 add r0, sp, #8 + 80046d2: f000 fd69 bl 80051a8 + taskEXIT_CRITICAL(); + 80046d6: f7ff fce7 bl 80040a8 + vTaskSuspendAll(); + 80046da: f000 fb5f bl 8004d9c + prvLockQueue( pxQueue ); + 80046de: f7ff fcc1 bl 8004064 + 80046e2: f894 3044 ldrb.w r3, [r4, #68] ; 0x44 + 80046e6: 2bff cmp r3, #255 ; 0xff + 80046e8: bf08 it eq + 80046ea: f884 8044 strbeq.w r8, [r4, #68] ; 0x44 + 80046ee: f894 3045 ldrb.w r3, [r4, #69] ; 0x45 + 80046f2: 2bff cmp r3, #255 ; 0xff + 80046f4: bf08 it eq + 80046f6: f884 8045 strbeq.w r8, [r4, #69] ; 0x45 + 80046fa: f7ff fcd5 bl 80040a8 + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + 80046fe: a901 add r1, sp, #4 + 8004700: a802 add r0, sp, #8 + 8004702: f000 fd61 bl 80051c8 + 8004706: 2800 cmp r0, #0 + 8004708: d143 bne.n 8004792 + +static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) +{ +BaseType_t xReturn; + + taskENTER_CRITICAL(); + 800470a: f7ff fcab bl 8004064 + { + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + 800470e: 6ba6 ldr r6, [r4, #56] ; 0x38 + 8004710: 6be5 ldr r5, [r4, #60] ; 0x3c + else + { + xReturn = pdFALSE; + } + } + taskEXIT_CRITICAL(); + 8004712: f7ff fcc9 bl 80040a8 + if( prvIsQueueFull( pxQueue ) != pdFALSE ) + 8004716: 42ae cmp r6, r5 + 8004718: d135 bne.n 8004786 + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); + 800471a: 9901 ldr r1, [sp, #4] + 800471c: f104 0010 add.w r0, r4, #16 + 8004720: f000 fce6 bl 80050f0 + prvUnlockQueue( pxQueue ); + 8004724: 4620 mov r0, r4 + 8004726: f7ff ff05 bl 8004534 + if( xTaskResumeAll() == pdFALSE ) + 800472a: f000 fbd1 bl 8004ed0 + 800472e: b938 cbnz r0, 8004740 + portYIELD_WITHIN_API(); + 8004730: f04f 5380 mov.w r3, #268435456 ; 0x10000000 + 8004734: f8ca 3000 str.w r3, [sl] + 8004738: f3bf 8f4f dsb sy + 800473c: f3bf 8f6f isb sy + 8004740: 2601 movs r6, #1 + taskENTER_CRITICAL(); + 8004742: f7ff fc8f bl 8004064 + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + 8004746: 6ba2 ldr r2, [r4, #56] ; 0x38 + 8004748: 6be3 ldr r3, [r4, #60] ; 0x3c + 800474a: 429a cmp r2, r3 + 800474c: d301 bcc.n 8004752 + 800474e: 2f02 cmp r7, #2 + 8004750: d1b7 bne.n 80046c2 + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + 8004752: 463a mov r2, r7 + 8004754: 4649 mov r1, r9 + 8004756: 4620 mov r0, r4 + 8004758: f7ff fea4 bl 80044a4 + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 800475c: 6a63 ldr r3, [r4, #36] ; 0x24 + 800475e: b11b cbz r3, 8004768 + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 8004760: f104 0024 add.w r0, r4, #36 ; 0x24 + 8004764: f000 fcde bl 8005124 + else if( xYieldRequired != pdFALSE ) + 8004768: b138 cbz r0, 800477a + queueYIELD_IF_USING_PREEMPTION(); + 800476a: 4b19 ldr r3, [pc, #100] ; (80047d0 ) + 800476c: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8004770: 601a str r2, [r3, #0] + 8004772: f3bf 8f4f dsb sy + 8004776: f3bf 8f6f isb sy + taskEXIT_CRITICAL(); + 800477a: f7ff fc95 bl 80040a8 + return pdPASS; + 800477e: 2001 movs r0, #1 +} + 8004780: b004 add sp, #16 + 8004782: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + prvUnlockQueue( pxQueue ); + 8004786: 4620 mov r0, r4 + 8004788: f7ff fed4 bl 8004534 + ( void ) xTaskResumeAll(); + 800478c: f000 fba0 bl 8004ed0 + 8004790: e7d6 b.n 8004740 + prvUnlockQueue( pxQueue ); + 8004792: 4620 mov r0, r4 + 8004794: f7ff fece bl 8004534 + ( void ) xTaskResumeAll(); + 8004798: f000 fb9a bl 8004ed0 + 800479c: e795 b.n 80046ca + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + 800479e: 2f02 cmp r7, #2 + 80047a0: d102 bne.n 80047a8 + 80047a2: 6be3 ldr r3, [r4, #60] ; 0x3c + 80047a4: 2b01 cmp r3, #1 + 80047a6: d10a bne.n 80047be + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + 80047a8: f000 fd4e bl 8005248 + 80047ac: 2800 cmp r0, #0 + 80047ae: f43f af7b beq.w 80046a8 + 80047b2: 2600 movs r6, #0 + prvLockQueue( pxQueue ); + 80047b4: f04f 0800 mov.w r8, #0 + portYIELD_WITHIN_API(); + 80047b8: f8df a014 ldr.w sl, [pc, #20] ; 80047d0 + 80047bc: e7c1 b.n 8004742 + 80047be: f04f 0350 mov.w r3, #80 ; 0x50 + 80047c2: f383 8811 msr BASEPRI, r3 + 80047c6: f3bf 8f6f isb sy + 80047ca: f3bf 8f4f dsb sy + 80047ce: e7fe b.n 80047ce + 80047d0: e000ed04 .word 0xe000ed04 + +080047d4 : +{ + 80047d4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 80047d8: 4688 mov r8, r1 + 80047da: 4691 mov r9, r2 + 80047dc: 461f mov r7, r3 + configASSERT( pxQueue ); + 80047de: 4604 mov r4, r0 + 80047e0: b940 cbnz r0, 80047f4 + 80047e2: f04f 0350 mov.w r3, #80 ; 0x50 + 80047e6: f383 8811 msr BASEPRI, r3 + 80047ea: f3bf 8f6f isb sy + 80047ee: f3bf 8f4f dsb sy + 80047f2: e7fe b.n 80047f2 + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 80047f4: bb09 cbnz r1, 800483a + 80047f6: 6c03 ldr r3, [r0, #64] ; 0x40 + 80047f8: b1fb cbz r3, 800483a + 80047fa: f04f 0350 mov.w r3, #80 ; 0x50 + 80047fe: f383 8811 msr BASEPRI, r3 + 8004802: f3bf 8f6f isb sy + 8004806: f3bf 8f4f dsb sy + 800480a: e7fe b.n 800480a + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 800480c: f104 0024 add.w r0, r4, #36 ; 0x24 + 8004810: f000 fc88 bl 8005124 + 8004814: 2800 cmp r0, #0 + 8004816: d034 beq.n 8004882 + if( pxHigherPriorityTaskWoken != NULL ) + 8004818: f1b9 0f00 cmp.w r9, #0 + 800481c: d031 beq.n 8004882 + *pxHigherPriorityTaskWoken = pdTRUE; + 800481e: 2001 movs r0, #1 + 8004820: f8c9 0000 str.w r0, [r9] + __asm volatile + 8004824: f386 8811 msr BASEPRI, r6 +} + 8004828: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); + 800482c: 3501 adds r5, #1 + 800482e: b26d sxtb r5, r5 + 8004830: f884 5045 strb.w r5, [r4, #69] ; 0x45 + 8004834: e025 b.n 8004882 + xReturn = errQUEUE_FULL; + 8004836: 2000 movs r0, #0 + 8004838: e7f4 b.n 8004824 + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + 800483a: 2f02 cmp r7, #2 + 800483c: d102 bne.n 8004844 + 800483e: 6be3 ldr r3, [r4, #60] ; 0x3c + 8004840: 2b01 cmp r3, #1 + 8004842: d120 bne.n 8004886 + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + 8004844: f7ff fd16 bl 8004274 + __asm volatile + 8004848: f3ef 8611 mrs r6, BASEPRI + 800484c: f04f 0350 mov.w r3, #80 ; 0x50 + 8004850: f383 8811 msr BASEPRI, r3 + 8004854: f3bf 8f6f isb sy + 8004858: f3bf 8f4f dsb sy + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + 800485c: 6ba2 ldr r2, [r4, #56] ; 0x38 + 800485e: 6be3 ldr r3, [r4, #60] ; 0x3c + 8004860: 429a cmp r2, r3 + 8004862: d301 bcc.n 8004868 + 8004864: 2f02 cmp r7, #2 + 8004866: d1e6 bne.n 8004836 + const int8_t cTxLock = pxQueue->cTxLock; + 8004868: f894 5045 ldrb.w r5, [r4, #69] ; 0x45 + ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + 800486c: 463a mov r2, r7 + const int8_t cTxLock = pxQueue->cTxLock; + 800486e: b26d sxtb r5, r5 + ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + 8004870: 4641 mov r1, r8 + 8004872: 4620 mov r0, r4 + 8004874: f7ff fe16 bl 80044a4 + if( cTxLock == queueUNLOCKED ) + 8004878: 1c6b adds r3, r5, #1 + 800487a: d1d7 bne.n 800482c + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 800487c: 6a63 ldr r3, [r4, #36] ; 0x24 + 800487e: 2b00 cmp r3, #0 + 8004880: d1c4 bne.n 800480c + xReturn = pdPASS; + 8004882: 2001 movs r0, #1 + 8004884: e7ce b.n 8004824 + __asm volatile + 8004886: f04f 0350 mov.w r3, #80 ; 0x50 + 800488a: f383 8811 msr BASEPRI, r3 + 800488e: f3bf 8f6f isb sy + 8004892: f3bf 8f4f dsb sy + 8004896: e7fe b.n 8004896 + +08004898 : +{ + 8004898: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 800489c: 4688 mov r8, r1 + 800489e: 9201 str r2, [sp, #4] + 80048a0: 4699 mov r9, r3 + configASSERT( pxQueue ); + 80048a2: 4604 mov r4, r0 + 80048a4: b940 cbnz r0, 80048b8 + 80048a6: f04f 0350 mov.w r3, #80 ; 0x50 + 80048aa: f383 8811 msr BASEPRI, r3 + 80048ae: f3bf 8f6f isb sy + 80048b2: f3bf 8f4f dsb sy + 80048b6: e7fe b.n 80048b6 + configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 80048b8: 2900 cmp r1, #0 + 80048ba: f040 80a5 bne.w 8004a08 + 80048be: 6c03 ldr r3, [r0, #64] ; 0x40 + 80048c0: 2b00 cmp r3, #0 + 80048c2: f000 80a1 beq.w 8004a08 + 80048c6: f04f 0350 mov.w r3, #80 ; 0x50 + 80048ca: f383 8811 msr BASEPRI, r3 + 80048ce: f3bf 8f6f isb sy + 80048d2: f3bf 8f4f dsb sy + 80048d6: e7fe b.n 80048d6 + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + 80048d8: 9e01 ldr r6, [sp, #4] + 80048da: 2e00 cmp r6, #0 + 80048dc: f000 809a beq.w 8004a14 + 80048e0: f04f 0350 mov.w r3, #80 ; 0x50 + 80048e4: f383 8811 msr BASEPRI, r3 + 80048e8: f3bf 8f6f isb sy + 80048ec: f3bf 8f4f dsb sy + 80048f0: e7fe b.n 80048f0 + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 80048f2: 6a63 ldr r3, [r4, #36] ; 0x24 + pxQueue->u.pcReadFrom = pcOriginalReadPosition; + 80048f4: 60e6 str r6, [r4, #12] + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + 80048f6: 2b00 cmp r3, #0 + 80048f8: d06d beq.n 80049d6 + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 80048fa: f104 0024 add.w r0, r4, #36 ; 0x24 + 80048fe: e05f b.n 80049c0 + if( xTicksToWait == ( TickType_t ) 0 ) + 8004900: 9d01 ldr r5, [sp, #4] + 8004902: b91d cbnz r5, 800490c + taskEXIT_CRITICAL(); + 8004904: f7ff fbd0 bl 80040a8 + return errQUEUE_EMPTY; + 8004908: 4628 mov r0, r5 + 800490a: e067 b.n 80049dc + else if( xEntryTimeSet == pdFALSE ) + 800490c: b916 cbnz r6, 8004914 + vTaskSetTimeOutState( &xTimeOut ); + 800490e: a802 add r0, sp, #8 + 8004910: f000 fc4a bl 80051a8 + taskEXIT_CRITICAL(); + 8004914: f7ff fbc8 bl 80040a8 + vTaskSuspendAll(); + 8004918: f000 fa40 bl 8004d9c + prvLockQueue( pxQueue ); + 800491c: f7ff fba2 bl 8004064 + 8004920: f894 3044 ldrb.w r3, [r4, #68] ; 0x44 + 8004924: 2bff cmp r3, #255 ; 0xff + 8004926: bf08 it eq + 8004928: f884 7044 strbeq.w r7, [r4, #68] ; 0x44 + 800492c: f894 3045 ldrb.w r3, [r4, #69] ; 0x45 + 8004930: 2bff cmp r3, #255 ; 0xff + 8004932: bf08 it eq + 8004934: f884 7045 strbeq.w r7, [r4, #69] ; 0x45 + 8004938: f7ff fbb6 bl 80040a8 + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + 800493c: a901 add r1, sp, #4 + 800493e: a802 add r0, sp, #8 + 8004940: f000 fc42 bl 80051c8 + 8004944: 2800 cmp r0, #0 + 8004946: d152 bne.n 80049ee + taskENTER_CRITICAL(); + 8004948: f7ff fb8c bl 8004064 + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + 800494c: 6ba5 ldr r5, [r4, #56] ; 0x38 + taskEXIT_CRITICAL(); + 800494e: f7ff fbab bl 80040a8 + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + 8004952: 2d00 cmp r5, #0 + 8004954: d145 bne.n 80049e2 + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + 8004956: 6823 ldr r3, [r4, #0] + 8004958: b933 cbnz r3, 8004968 + taskENTER_CRITICAL(); + 800495a: f7ff fb83 bl 8004064 + vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder ); + 800495e: 6860 ldr r0, [r4, #4] + 8004960: f000 fc82 bl 8005268 + taskEXIT_CRITICAL(); + 8004964: f7ff fba0 bl 80040a8 + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + 8004968: 9901 ldr r1, [sp, #4] + 800496a: f104 0024 add.w r0, r4, #36 ; 0x24 + 800496e: f000 fbbf bl 80050f0 + prvUnlockQueue( pxQueue ); + 8004972: 4620 mov r0, r4 + 8004974: f7ff fdde bl 8004534 + if( xTaskResumeAll() == pdFALSE ) + 8004978: f000 faaa bl 8004ed0 + 800497c: b938 cbnz r0, 800498e + portYIELD_WITHIN_API(); + 800497e: f04f 5380 mov.w r3, #268435456 ; 0x10000000 + 8004982: f8ca 3000 str.w r3, [sl] + 8004986: f3bf 8f4f dsb sy + 800498a: f3bf 8f6f isb sy + 800498e: 2601 movs r6, #1 + taskENTER_CRITICAL(); + 8004990: f7ff fb68 bl 8004064 + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + 8004994: 6ba5 ldr r5, [r4, #56] ; 0x38 + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + 8004996: 2d00 cmp r5, #0 + 8004998: d0b2 beq.n 8004900 + prvCopyDataFromQueue( pxQueue, pvBuffer ); + 800499a: 4641 mov r1, r8 + 800499c: 4620 mov r0, r4 + pcOriginalReadPosition = pxQueue->u.pcReadFrom; + 800499e: 68e6 ldr r6, [r4, #12] + prvCopyDataFromQueue( pxQueue, pvBuffer ); + 80049a0: f7ff fdb3 bl 800450a + if( xJustPeeking == pdFALSE ) + 80049a4: f1b9 0f00 cmp.w r9, #0 + 80049a8: d1a3 bne.n 80048f2 + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + 80049aa: 6823 ldr r3, [r4, #0] + pxQueue->uxMessagesWaiting = uxMessagesWaiting - 1; + 80049ac: 3d01 subs r5, #1 + 80049ae: 63a5 str r5, [r4, #56] ; 0x38 + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + 80049b0: b913 cbnz r3, 80049b8 + pxQueue->pxMutexHolder = ( int8_t * ) pvTaskIncrementMutexHeldCount(); /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */ + 80049b2: f000 fcef bl 8005394 + 80049b6: 6060 str r0, [r4, #4] + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 80049b8: 6923 ldr r3, [r4, #16] + 80049ba: b163 cbz r3, 80049d6 + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 80049bc: f104 0010 add.w r0, r4, #16 + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + 80049c0: f000 fbb0 bl 8005124 + 80049c4: b138 cbz r0, 80049d6 + queueYIELD_IF_USING_PREEMPTION(); + 80049c6: 4b15 ldr r3, [pc, #84] ; (8004a1c ) + 80049c8: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 80049cc: 601a str r2, [r3, #0] + 80049ce: f3bf 8f4f dsb sy + 80049d2: f3bf 8f6f isb sy + taskEXIT_CRITICAL(); + 80049d6: f7ff fb67 bl 80040a8 + return pdPASS; + 80049da: 2001 movs r0, #1 +} + 80049dc: b004 add sp, #16 + 80049de: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + prvUnlockQueue( pxQueue ); + 80049e2: 4620 mov r0, r4 + 80049e4: f7ff fda6 bl 8004534 + ( void ) xTaskResumeAll(); + 80049e8: f000 fa72 bl 8004ed0 + 80049ec: e7cf b.n 800498e + prvUnlockQueue( pxQueue ); + 80049ee: 4620 mov r0, r4 + 80049f0: f7ff fda0 bl 8004534 + ( void ) xTaskResumeAll(); + 80049f4: f000 fa6c bl 8004ed0 + taskENTER_CRITICAL(); + 80049f8: f7ff fb34 bl 8004064 + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + 80049fc: 6ba5 ldr r5, [r4, #56] ; 0x38 + taskEXIT_CRITICAL(); + 80049fe: f7ff fb53 bl 80040a8 + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + 8004a02: 2d00 cmp r5, #0 + 8004a04: d1c3 bne.n 800498e + 8004a06: e77f b.n 8004908 + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + 8004a08: f000 fc1e bl 8005248 + 8004a0c: 2800 cmp r0, #0 + 8004a0e: f43f af63 beq.w 80048d8 + 8004a12: 2600 movs r6, #0 + prvLockQueue( pxQueue ); + 8004a14: 2700 movs r7, #0 + portYIELD_WITHIN_API(); + 8004a16: f8df a004 ldr.w sl, [pc, #4] ; 8004a1c + 8004a1a: e7b9 b.n 8004990 + 8004a1c: e000ed04 .word 0xe000ed04 + +08004a20 : +{ + 8004a20: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8004a24: 4689 mov r9, r1 + 8004a26: 4690 mov r8, r2 + configASSERT( pxQueue ); + 8004a28: 4605 mov r5, r0 + 8004a2a: b940 cbnz r0, 8004a3e + 8004a2c: f04f 0350 mov.w r3, #80 ; 0x50 + 8004a30: f383 8811 msr BASEPRI, r3 + 8004a34: f3bf 8f6f isb sy + 8004a38: f3bf 8f4f dsb sy + 8004a3c: e7fe b.n 8004a3c + configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + 8004a3e: bb71 cbnz r1, 8004a9e + 8004a40: 6c03 ldr r3, [r0, #64] ; 0x40 + 8004a42: b363 cbz r3, 8004a9e + 8004a44: f04f 0350 mov.w r3, #80 ; 0x50 + 8004a48: f383 8811 msr BASEPRI, r3 + 8004a4c: f3bf 8f6f isb sy + 8004a50: f3bf 8f4f dsb sy + 8004a54: e7fe b.n 8004a54 + const int8_t cRxLock = pxQueue->cRxLock; + 8004a56: f895 6044 ldrb.w r6, [r5, #68] ; 0x44 + prvCopyDataFromQueue( pxQueue, pvBuffer ); + 8004a5a: 4649 mov r1, r9 + const int8_t cRxLock = pxQueue->cRxLock; + 8004a5c: b276 sxtb r6, r6 + prvCopyDataFromQueue( pxQueue, pvBuffer ); + 8004a5e: 4628 mov r0, r5 + 8004a60: f7ff fd53 bl 800450a + pxQueue->uxMessagesWaiting = uxMessagesWaiting - 1; + 8004a64: 3c01 subs r4, #1 + if( cRxLock == queueUNLOCKED ) + 8004a66: 1c73 adds r3, r6, #1 + pxQueue->uxMessagesWaiting = uxMessagesWaiting - 1; + 8004a68: 63ac str r4, [r5, #56] ; 0x38 + if( cRxLock == queueUNLOCKED ) + 8004a6a: d113 bne.n 8004a94 + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + 8004a6c: 692b ldr r3, [r5, #16] + 8004a6e: b90b cbnz r3, 8004a74 + xReturn = pdPASS; + 8004a70: 2001 movs r0, #1 + 8004a72: e00b b.n 8004a8c + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + 8004a74: f105 0010 add.w r0, r5, #16 + 8004a78: f000 fb54 bl 8005124 + 8004a7c: 2800 cmp r0, #0 + 8004a7e: d0f7 beq.n 8004a70 + if( pxHigherPriorityTaskWoken != NULL ) + 8004a80: f1b8 0f00 cmp.w r8, #0 + 8004a84: d0f4 beq.n 8004a70 + *pxHigherPriorityTaskWoken = pdTRUE; + 8004a86: 2001 movs r0, #1 + 8004a88: f8c8 0000 str.w r0, [r8] + __asm volatile + 8004a8c: f387 8811 msr BASEPRI, r7 +} + 8004a90: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); + 8004a94: 3601 adds r6, #1 + 8004a96: b276 sxtb r6, r6 + 8004a98: f885 6044 strb.w r6, [r5, #68] ; 0x44 + 8004a9c: e7e8 b.n 8004a70 + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + 8004a9e: f7ff fbe9 bl 8004274 + __asm volatile + 8004aa2: f3ef 8711 mrs r7, BASEPRI + 8004aa6: f04f 0350 mov.w r3, #80 ; 0x50 + 8004aaa: f383 8811 msr BASEPRI, r3 + 8004aae: f3bf 8f6f isb sy + 8004ab2: f3bf 8f4f dsb sy + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + 8004ab6: 6bac ldr r4, [r5, #56] ; 0x38 + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + 8004ab8: 2c00 cmp r4, #0 + 8004aba: d1cc bne.n 8004a56 + xReturn = pdFAIL; + 8004abc: 4620 mov r0, r4 + 8004abe: e7e5 b.n 8004a8c + +08004ac0 : + +static void prvResetNextTaskUnblockTime( void ) +{ +TCB_t *pxTCB; + + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 8004ac0: 4a06 ldr r2, [pc, #24] ; (8004adc ) + 8004ac2: 6813 ldr r3, [r2, #0] + 8004ac4: 6819 ldr r1, [r3, #0] + 8004ac6: 4b06 ldr r3, [pc, #24] ; (8004ae0 ) + 8004ac8: b919 cbnz r1, 8004ad2 + { + /* The new current delayed list is empty. Set xNextTaskUnblockTime to + the maximum possible value so it is extremely unlikely that the + if( xTickCount >= xNextTaskUnblockTime ) test will pass until + there is an item in the delayed list. */ + xNextTaskUnblockTime = portMAX_DELAY; + 8004aca: f04f 32ff mov.w r2, #4294967295 + /* The new current delayed list is not empty, get the value of + the item at the head of the delayed list. This is the time at + which the task at the head of the delayed list should be removed + from the Blocked state. */ + ( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); + xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); + 8004ace: 601a str r2, [r3, #0] + 8004ad0: 4770 bx lr + ( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); + 8004ad2: 6812 ldr r2, [r2, #0] + 8004ad4: 68d2 ldr r2, [r2, #12] + xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); + 8004ad6: 68d2 ldr r2, [r2, #12] + 8004ad8: 6852 ldr r2, [r2, #4] + 8004ada: e7f8 b.n 8004ace + 8004adc: 20003ee0 .word 0x20003ee0 + 8004ae0: 20003fb8 .word 0x20003fb8 + +08004ae4 : +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + + +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) +{ + 8004ae4: b5f8 push {r3, r4, r5, r6, r7, lr} +TickType_t xTimeToWake; +const TickType_t xConstTickCount = xTickCount; + 8004ae6: 4b1b ldr r3, [pc, #108] ; (8004b54 ) + } + #endif + + /* Remove the task from the ready list before adding it to the blocked list + as the same list item is used for both lists. */ + if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 8004ae8: 4e1b ldr r6, [pc, #108] ; (8004b58 ) +const TickType_t xConstTickCount = xTickCount; + 8004aea: 681d ldr r5, [r3, #0] +{ + 8004aec: 4604 mov r4, r0 + if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 8004aee: 6830 ldr r0, [r6, #0] + 8004af0: 3004 adds r0, #4 +{ + 8004af2: 460f mov r7, r1 + if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 8004af4: f7ff fa47 bl 8003f86 + 8004af8: 4633 mov r3, r6 + 8004afa: b940 cbnz r0, 8004b0e + { + /* The current task must be in a ready list, so there is no need to + check, and the port reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); + 8004afc: 6831 ldr r1, [r6, #0] + 8004afe: 4e17 ldr r6, [pc, #92] ; (8004b5c ) + 8004b00: 6ac9 ldr r1, [r1, #44] ; 0x2c + 8004b02: 6832 ldr r2, [r6, #0] + 8004b04: 2001 movs r0, #1 + 8004b06: 4088 lsls r0, r1 + 8004b08: ea22 0200 bic.w r2, r2, r0 + 8004b0c: 6032 str r2, [r6, #0] + mtCOVERAGE_TEST_MARKER(); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) + 8004b0e: 1c62 adds r2, r4, #1 + 8004b10: d107 bne.n 8004b22 + 8004b12: b137 cbz r7, 8004b22 + { + /* Add the task to the suspended task list instead of a delayed task + list to ensure it is not woken by a timing event. It will block + indefinitely. */ + vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 8004b14: 6819 ldr r1, [r3, #0] + 8004b16: 4812 ldr r0, [pc, #72] ; (8004b60 ) + 8004b18: 3104 adds r1, #4 + + /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ + ( void ) xCanBlockIndefinitely; + } + #endif /* INCLUDE_vTaskSuspend */ +} + 8004b1a: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} + vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 8004b1e: f7ff ba0f b.w 8003f40 + xTimeToWake = xConstTickCount + xTicksToWait; + 8004b22: 442c add r4, r5 + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + 8004b24: 681a ldr r2, [r3, #0] + if( xTimeToWake < xConstTickCount ) + 8004b26: 42a5 cmp r5, r4 + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + 8004b28: 6054 str r4, [r2, #4] + if( xTimeToWake < xConstTickCount ) + 8004b2a: d907 bls.n 8004b3c + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 8004b2c: 4a0d ldr r2, [pc, #52] ; (8004b64 ) + 8004b2e: 6810 ldr r0, [r2, #0] + 8004b30: 6819 ldr r1, [r3, #0] +} + 8004b32: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 8004b36: 3104 adds r1, #4 + 8004b38: f7ff ba0e b.w 8003f58 + vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 8004b3c: 4a0a ldr r2, [pc, #40] ; (8004b68 ) + 8004b3e: 6810 ldr r0, [r2, #0] + 8004b40: 6819 ldr r1, [r3, #0] + 8004b42: 3104 adds r1, #4 + 8004b44: f7ff fa08 bl 8003f58 + if( xTimeToWake < xNextTaskUnblockTime ) + 8004b48: 4b08 ldr r3, [pc, #32] ; (8004b6c ) + 8004b4a: 681a ldr r2, [r3, #0] + 8004b4c: 4294 cmp r4, r2 + xNextTaskUnblockTime = xTimeToWake; + 8004b4e: bf38 it cc + 8004b50: 601c strcc r4, [r3, #0] + 8004b52: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8004b54: 20004000 .word 0x20004000 + 8004b58: 20003edc .word 0x20003edc + 8004b5c: 20003f88 .word 0x20003f88 + 8004b60: 20003fd8 .word 0x20003fd8 + 8004b64: 20003ee4 .word 0x20003ee4 + 8004b68: 20003ee0 .word 0x20003ee0 + 8004b6c: 20003fb8 .word 0x20003fb8 + +08004b70 : + __asm volatile + 8004b70: f04f 0350 mov.w r3, #80 ; 0x50 + 8004b74: f383 8811 msr BASEPRI, r3 + 8004b78: f3bf 8f6f isb sy + 8004b7c: f3bf 8f4f dsb sy + 8004b80: e7fe b.n 8004b80 + ... + +08004b84 : + { + 8004b84: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} + pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8004b88: ea4f 0a82 mov.w sl, r2, lsl #2 + { + 8004b8c: 4680 mov r8, r0 + pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8004b8e: 4650 mov r0, sl + { + 8004b90: 460f mov r7, r1 + 8004b92: 4699 mov r9, r3 + 8004b94: 9e0b ldr r6, [sp, #44] ; 0x2c + pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8004b96: f7ff fbbf bl 8004318 + if( pxStack != NULL ) + 8004b9a: 4605 mov r5, r0 + 8004b9c: 2800 cmp r0, #0 + 8004b9e: f000 8096 beq.w 8004cce + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e961 MISRA exception as the casts are only redundant for some paths. */ + 8004ba2: 2054 movs r0, #84 ; 0x54 + 8004ba4: f7ff fbb8 bl 8004318 + if( pxNewTCB != NULL ) + 8004ba8: 4604 mov r4, r0 + 8004baa: 2800 cmp r0, #0 + 8004bac: f000 808c beq.w 8004cc8 + pxTopOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); + 8004bb0: f1aa 0a04 sub.w sl, sl, #4 + pxNewTCB->pxStack = pxStack; + 8004bb4: 6305 str r5, [r0, #48] ; 0x30 + pxTopOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); + 8004bb6: 4455 add r5, sl + 8004bb8: 1e7b subs r3, r7, #1 + pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. */ + 8004bba: f025 0a07 bic.w sl, r5, #7 + 8004bbe: f100 0234 add.w r2, r0, #52 ; 0x34 + 8004bc2: 370f adds r7, #15 + pxNewTCB->pcTaskName[ x ] = pcName[ x ]; + 8004bc4: 7859 ldrb r1, [r3, #1] + 8004bc6: f802 1b01 strb.w r1, [r2], #1 + if( pcName[ x ] == 0x00 ) + 8004bca: f813 1f01 ldrb.w r1, [r3, #1]! + 8004bce: b109 cbz r1, 8004bd4 + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + 8004bd0: 42bb cmp r3, r7 + 8004bd2: d1f7 bne.n 8004bc4 + 8004bd4: 9d0a ldr r5, [sp, #40] ; 0x28 + 8004bd6: 2d06 cmp r5, #6 + 8004bd8: bf28 it cs + 8004bda: 2506 movcs r5, #6 + pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; + 8004bdc: f04f 0b00 mov.w fp, #0 + vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); + 8004be0: 1d27 adds r7, r4, #4 + pxNewTCB->uxPriority = uxPriority; + 8004be2: 62e5 str r5, [r4, #44] ; 0x2c + pxNewTCB->uxBasePriority = uxPriority; + 8004be4: 6465 str r5, [r4, #68] ; 0x44 + vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); + 8004be6: 4638 mov r0, r7 + pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; + 8004be8: f884 b043 strb.w fp, [r4, #67] ; 0x43 + pxNewTCB->uxMutexesHeld = 0; + 8004bec: f8c4 b048 str.w fp, [r4, #72] ; 0x48 + vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); + 8004bf0: f7ff f9a3 bl 8003f3a + listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8004bf4: f1c5 0507 rsb r5, r5, #7 + vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); + 8004bf8: f104 0018 add.w r0, r4, #24 + 8004bfc: f7ff f99d bl 8003f3a + pxNewTCB->ulNotifiedValue = 0; + 8004c00: f8c4 b04c str.w fp, [r4, #76] ; 0x4c + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); + 8004c04: 6124 str r4, [r4, #16] + listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8004c06: 61a5 str r5, [r4, #24] + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); + 8004c08: 6264 str r4, [r4, #36] ; 0x24 + pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; + 8004c0a: f884 b050 strb.w fp, [r4, #80] ; 0x50 + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); + 8004c0e: 464a mov r2, r9 + 8004c10: 4641 mov r1, r8 + 8004c12: 4650 mov r0, sl + 8004c14: f7ff f9fa bl 800400c + 8004c18: 6020 str r0, [r4, #0] + if( ( void * ) pxCreatedTask != NULL ) + 8004c1a: b106 cbz r6, 8004c1e + *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; + 8004c1c: 6034 str r4, [r6, #0] + taskENTER_CRITICAL(); + 8004c1e: f7ff fa21 bl 8004064 + uxCurrentNumberOfTasks++; + 8004c22: 4b32 ldr r3, [pc, #200] ; (8004cec ) + if( pxCurrentTCB == NULL ) + 8004c24: 4e32 ldr r6, [pc, #200] ; (8004cf0 ) + uxCurrentNumberOfTasks++; + 8004c26: 681a ldr r2, [r3, #0] + 8004c28: f8df 80f0 ldr.w r8, [pc, #240] ; 8004d1c + 8004c2c: 3201 adds r2, #1 + 8004c2e: 601a str r2, [r3, #0] + if( pxCurrentTCB == NULL ) + 8004c30: 6835 ldr r5, [r6, #0] + 8004c32: 2d00 cmp r5, #0 + 8004c34: d14e bne.n 8004cd4 + pxCurrentTCB = pxNewTCB; + 8004c36: 6034 str r4, [r6, #0] + if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) + 8004c38: 681b ldr r3, [r3, #0] + 8004c3a: 2b01 cmp r3, #1 + 8004c3c: d11d bne.n 8004c7a + vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); + 8004c3e: eb08 0005 add.w r0, r8, r5 + 8004c42: 3514 adds r5, #20 + 8004c44: f7ff f96e bl 8003f24 + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + 8004c48: 2d8c cmp r5, #140 ; 0x8c + 8004c4a: d1f8 bne.n 8004c3e + vListInitialise( &xDelayedTaskList1 ); + 8004c4c: f8df 90d0 ldr.w r9, [pc, #208] ; 8004d20 + vListInitialise( &xDelayedTaskList2 ); + 8004c50: 4d28 ldr r5, [pc, #160] ; (8004cf4 ) + vListInitialise( &xDelayedTaskList1 ); + 8004c52: 4648 mov r0, r9 + 8004c54: f7ff f966 bl 8003f24 + vListInitialise( &xDelayedTaskList2 ); + 8004c58: 4628 mov r0, r5 + 8004c5a: f7ff f963 bl 8003f24 + vListInitialise( &xPendingReadyList ); + 8004c5e: 4826 ldr r0, [pc, #152] ; (8004cf8 ) + 8004c60: f7ff f960 bl 8003f24 + vListInitialise( &xTasksWaitingTermination ); + 8004c64: 4825 ldr r0, [pc, #148] ; (8004cfc ) + 8004c66: f7ff f95d bl 8003f24 + vListInitialise( &xSuspendedTaskList ); + 8004c6a: 4825 ldr r0, [pc, #148] ; (8004d00 ) + 8004c6c: f7ff f95a bl 8003f24 + pxDelayedTaskList = &xDelayedTaskList1; + 8004c70: 4b24 ldr r3, [pc, #144] ; (8004d04 ) + 8004c72: f8c3 9000 str.w r9, [r3] + pxOverflowDelayedTaskList = &xDelayedTaskList2; + 8004c76: 4b24 ldr r3, [pc, #144] ; (8004d08 ) + 8004c78: 601d str r5, [r3, #0] + uxTaskNumber++; + 8004c7a: 4a24 ldr r2, [pc, #144] ; (8004d0c ) + prvAddTaskToReadyList( pxNewTCB ); + 8004c7c: 4924 ldr r1, [pc, #144] ; (8004d10 ) + uxTaskNumber++; + 8004c7e: 6813 ldr r3, [r2, #0] + prvAddTaskToReadyList( pxNewTCB ); + 8004c80: 6808 ldr r0, [r1, #0] + uxTaskNumber++; + 8004c82: 3301 adds r3, #1 + 8004c84: 6013 str r3, [r2, #0] + prvAddTaskToReadyList( pxNewTCB ); + 8004c86: 6ae2 ldr r2, [r4, #44] ; 0x2c + 8004c88: 2501 movs r5, #1 + 8004c8a: fa05 f302 lsl.w r3, r5, r2 + 8004c8e: 4303 orrs r3, r0 + 8004c90: 2014 movs r0, #20 + 8004c92: 600b str r3, [r1, #0] + 8004c94: fb00 8002 mla r0, r0, r2, r8 + 8004c98: 4639 mov r1, r7 + 8004c9a: f7ff f951 bl 8003f40 + taskEXIT_CRITICAL(); + 8004c9e: f7ff fa03 bl 80040a8 + if( xSchedulerRunning != pdFALSE ) + 8004ca2: 4b1c ldr r3, [pc, #112] ; (8004d14 ) + 8004ca4: 681b ldr r3, [r3, #0] + 8004ca6: b163 cbz r3, 8004cc2 + if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) + 8004ca8: 6833 ldr r3, [r6, #0] + 8004caa: 6ada ldr r2, [r3, #44] ; 0x2c + 8004cac: 6ae3 ldr r3, [r4, #44] ; 0x2c + 8004cae: 429a cmp r2, r3 + 8004cb0: d207 bcs.n 8004cc2 + taskYIELD_IF_USING_PREEMPTION(); + 8004cb2: 4b19 ldr r3, [pc, #100] ; (8004d18 ) + 8004cb4: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8004cb8: 601a str r2, [r3, #0] + 8004cba: f3bf 8f4f dsb sy + 8004cbe: f3bf 8f6f isb sy + } + 8004cc2: 4628 mov r0, r5 + 8004cc4: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} + vPortFree( pxStack ); + 8004cc8: 4628 mov r0, r5 + 8004cca: f7ff fbb3 bl 8004434 + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + 8004cce: f04f 35ff mov.w r5, #4294967295 + 8004cd2: e7f6 b.n 8004cc2 + if( xSchedulerRunning == pdFALSE ) + 8004cd4: 4b0f ldr r3, [pc, #60] ; (8004d14 ) + 8004cd6: 681b ldr r3, [r3, #0] + 8004cd8: 2b00 cmp r3, #0 + 8004cda: d1ce bne.n 8004c7a + if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) + 8004cdc: 6833 ldr r3, [r6, #0] + 8004cde: 6ada ldr r2, [r3, #44] ; 0x2c + 8004ce0: 6ae3 ldr r3, [r4, #44] ; 0x2c + 8004ce2: 429a cmp r2, r3 + pxCurrentTCB = pxNewTCB; + 8004ce4: bf98 it ls + 8004ce6: 6034 strls r4, [r6, #0] + 8004ce8: e7c7 b.n 8004c7a + 8004cea: bf00 nop + 8004cec: 20003f74 .word 0x20003f74 + 8004cf0: 20003edc .word 0x20003edc + 8004cf4: 20003fa0 .word 0x20003fa0 + 8004cf8: 20003fc0 .word 0x20003fc0 + 8004cfc: 20003fec .word 0x20003fec + 8004d00: 20003fd8 .word 0x20003fd8 + 8004d04: 20003ee0 .word 0x20003ee0 + 8004d08: 20003ee4 .word 0x20003ee4 + 8004d0c: 20003f84 .word 0x20003f84 + 8004d10: 20003f88 .word 0x20003f88 + 8004d14: 20003fd4 .word 0x20003fd4 + 8004d18: e000ed04 .word 0xe000ed04 + 8004d1c: 20003ee8 .word 0x20003ee8 + 8004d20: 20003f8c .word 0x20003f8c + +08004d24 : +{ + 8004d24: b513 push {r0, r1, r4, lr} + xReturn = xTaskCreate( prvIdleTask, + 8004d26: 4b17 ldr r3, [pc, #92] ; (8004d84 ) + 8004d28: 9301 str r3, [sp, #4] + 8004d2a: 2400 movs r4, #0 + 8004d2c: 9400 str r4, [sp, #0] + 8004d2e: 4623 mov r3, r4 + 8004d30: 2280 movs r2, #128 ; 0x80 + 8004d32: 4915 ldr r1, [pc, #84] ; (8004d88 ) + 8004d34: 4815 ldr r0, [pc, #84] ; (8004d8c ) + 8004d36: f7ff ff25 bl 8004b84 + if( xReturn == pdPASS ) + 8004d3a: 2801 cmp r0, #1 + 8004d3c: d114 bne.n 8004d68 + 8004d3e: f04f 0350 mov.w r3, #80 ; 0x50 + 8004d42: f383 8811 msr BASEPRI, r3 + 8004d46: f3bf 8f6f isb sy + 8004d4a: f3bf 8f4f dsb sy + xNextTaskUnblockTime = portMAX_DELAY; + 8004d4e: 4b10 ldr r3, [pc, #64] ; (8004d90 ) + 8004d50: f04f 32ff mov.w r2, #4294967295 + 8004d54: 601a str r2, [r3, #0] + xSchedulerRunning = pdTRUE; + 8004d56: 4b0f ldr r3, [pc, #60] ; (8004d94 ) + 8004d58: 6018 str r0, [r3, #0] + xTickCount = ( TickType_t ) 0U; + 8004d5a: 4b0f ldr r3, [pc, #60] ; (8004d98 ) + 8004d5c: 601c str r4, [r3, #0] +} + 8004d5e: b002 add sp, #8 + 8004d60: e8bd 4010 ldmia.w sp!, {r4, lr} + if( xPortStartScheduler() != pdFALSE ) + 8004d64: f7ff ba10 b.w 8004188 + configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); + 8004d68: 3001 adds r0, #1 + 8004d6a: d108 bne.n 8004d7e + 8004d6c: f04f 0350 mov.w r3, #80 ; 0x50 + 8004d70: f383 8811 msr BASEPRI, r3 + 8004d74: f3bf 8f6f isb sy + 8004d78: f3bf 8f4f dsb sy + 8004d7c: e7fe b.n 8004d7c +} + 8004d7e: b002 add sp, #8 + 8004d80: bd10 pop {r4, pc} + 8004d82: bf00 nop + 8004d84: 20003fb4 .word 0x20003fb4 + 8004d88: 08006c68 .word 0x08006c68 + 8004d8c: 08005009 .word 0x08005009 + 8004d90: 20003fb8 .word 0x20003fb8 + 8004d94: 20003fd4 .word 0x20003fd4 + 8004d98: 20004000 .word 0x20004000 + +08004d9c : + ++uxSchedulerSuspended; + 8004d9c: 4a02 ldr r2, [pc, #8] ; (8004da8 ) + 8004d9e: 6813 ldr r3, [r2, #0] + 8004da0: 3301 adds r3, #1 + 8004da2: 6013 str r3, [r2, #0] + 8004da4: 4770 bx lr + 8004da6: bf00 nop + 8004da8: 20003f80 .word 0x20003f80 + +08004dac : +{ + 8004dac: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 8004db0: 4b3c ldr r3, [pc, #240] ; (8004ea4 ) + 8004db2: 681b ldr r3, [r3, #0] + 8004db4: 2b00 cmp r3, #0 + 8004db6: d153 bne.n 8004e60 + const TickType_t xConstTickCount = xTickCount + 1; + 8004db8: 4b3b ldr r3, [pc, #236] ; (8004ea8 ) + 8004dba: 681c ldr r4, [r3, #0] + 8004dbc: 3401 adds r4, #1 + xTickCount = xConstTickCount; + 8004dbe: 601c str r4, [r3, #0] + if( xConstTickCount == ( TickType_t ) 0U ) + 8004dc0: b9bc cbnz r4, 8004df2 + taskSWITCH_DELAYED_LISTS(); + 8004dc2: 4b3a ldr r3, [pc, #232] ; (8004eac ) + 8004dc4: 681a ldr r2, [r3, #0] + 8004dc6: 6812 ldr r2, [r2, #0] + 8004dc8: b142 cbz r2, 8004ddc + 8004dca: f04f 0350 mov.w r3, #80 ; 0x50 + 8004dce: f383 8811 msr BASEPRI, r3 + 8004dd2: f3bf 8f6f isb sy + 8004dd6: f3bf 8f4f dsb sy + 8004dda: e7fe b.n 8004dda + 8004ddc: 4a34 ldr r2, [pc, #208] ; (8004eb0 ) + 8004dde: 6819 ldr r1, [r3, #0] + 8004de0: 6810 ldr r0, [r2, #0] + 8004de2: 6018 str r0, [r3, #0] + 8004de4: 6011 str r1, [r2, #0] + 8004de6: 4a33 ldr r2, [pc, #204] ; (8004eb4 ) + 8004de8: 6813 ldr r3, [r2, #0] + 8004dea: 3301 adds r3, #1 + 8004dec: 6013 str r3, [r2, #0] + 8004dee: f7ff fe67 bl 8004ac0 + if( xConstTickCount >= xNextTaskUnblockTime ) + 8004df2: 4d31 ldr r5, [pc, #196] ; (8004eb8 ) + 8004df4: 4f31 ldr r7, [pc, #196] ; (8004ebc ) + 8004df6: 682b ldr r3, [r5, #0] + 8004df8: 429c cmp r4, r3 + 8004dfa: f04f 0b00 mov.w fp, #0 + 8004dfe: d33e bcc.n 8004e7e + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 8004e00: f8df 80a8 ldr.w r8, [pc, #168] ; 8004eac + prvAddTaskToReadyList( pxTCB ); + 8004e04: f8df 90c4 ldr.w r9, [pc, #196] ; 8004ecc + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 8004e08: f8d8 2000 ldr.w r2, [r8] + 8004e0c: 6812 ldr r2, [r2, #0] + 8004e0e: bb72 cbnz r2, 8004e6e + xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8004e10: f04f 32ff mov.w r2, #4294967295 + 8004e14: 602a str r2, [r5, #0] + break; + 8004e16: e032 b.n 8004e7e + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 8004e18: f106 0a04 add.w sl, r6, #4 + 8004e1c: 4650 mov r0, sl + 8004e1e: f7ff f8b2 bl 8003f86 + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + 8004e22: 6ab1 ldr r1, [r6, #40] ; 0x28 + 8004e24: b119 cbz r1, 8004e2e + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + 8004e26: f106 0018 add.w r0, r6, #24 + 8004e2a: f7ff f8ac bl 8003f86 + prvAddTaskToReadyList( pxTCB ); + 8004e2e: 6af0 ldr r0, [r6, #44] ; 0x2c + 8004e30: f8d9 3000 ldr.w r3, [r9] + 8004e34: 2201 movs r2, #1 + 8004e36: fa02 f100 lsl.w r1, r2, r0 + 8004e3a: 4319 orrs r1, r3 + 8004e3c: 4b20 ldr r3, [pc, #128] ; (8004ec0 ) + 8004e3e: f8c9 1000 str.w r1, [r9] + 8004e42: f04f 0e14 mov.w lr, #20 + 8004e46: 4651 mov r1, sl + 8004e48: fb0e 3000 mla r0, lr, r0, r3 + 8004e4c: f7ff f878 bl 8003f40 + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + 8004e50: 6838 ldr r0, [r7, #0] + 8004e52: 6af1 ldr r1, [r6, #44] ; 0x2c + 8004e54: 6ac2 ldr r2, [r0, #44] ; 0x2c + xSwitchRequired = pdTRUE; + 8004e56: 4291 cmp r1, r2 + 8004e58: bf28 it cs + 8004e5a: f04f 0b01 movcs.w fp, #1 + 8004e5e: e7d3 b.n 8004e08 + ++uxPendedTicks; + 8004e60: 4a18 ldr r2, [pc, #96] ; (8004ec4 ) + 8004e62: 6813 ldr r3, [r2, #0] + 8004e64: 3301 adds r3, #1 + 8004e66: 6013 str r3, [r2, #0] +BaseType_t xSwitchRequired = pdFALSE; + 8004e68: f04f 0b00 mov.w fp, #0 + 8004e6c: e011 b.n 8004e92 + pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); + 8004e6e: f8d8 2000 ldr.w r2, [r8] + 8004e72: 68d2 ldr r2, [r2, #12] + 8004e74: 68d6 ldr r6, [r2, #12] + xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); + 8004e76: 6871 ldr r1, [r6, #4] + if( xConstTickCount < xItemValue ) + 8004e78: 428c cmp r4, r1 + 8004e7a: d2cd bcs.n 8004e18 + xNextTaskUnblockTime = xItemValue; + 8004e7c: 6029 str r1, [r5, #0] + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) + 8004e7e: 683a ldr r2, [r7, #0] + 8004e80: 4b0f ldr r3, [pc, #60] ; (8004ec0 ) + 8004e82: 6ad1 ldr r1, [r2, #44] ; 0x2c + 8004e84: 2214 movs r2, #20 + 8004e86: 434a muls r2, r1 + 8004e88: 589a ldr r2, [r3, r2] + xSwitchRequired = pdTRUE; + 8004e8a: 2a02 cmp r2, #2 + 8004e8c: bf28 it cs + 8004e8e: f04f 0b01 movcs.w fp, #1 + if( xYieldPending != pdFALSE ) + 8004e92: 4a0d ldr r2, [pc, #52] ; (8004ec8 ) + 8004e94: 6812 ldr r2, [r2, #0] + xSwitchRequired = pdTRUE; + 8004e96: 2a00 cmp r2, #0 + 8004e98: bf18 it ne + 8004e9a: f04f 0b01 movne.w fp, #1 +} + 8004e9e: 4658 mov r0, fp + 8004ea0: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8004ea4: 20003f80 .word 0x20003f80 + 8004ea8: 20004000 .word 0x20004000 + 8004eac: 20003ee0 .word 0x20003ee0 + 8004eb0: 20003ee4 .word 0x20003ee4 + 8004eb4: 20003fbc .word 0x20003fbc + 8004eb8: 20003fb8 .word 0x20003fb8 + 8004ebc: 20003edc .word 0x20003edc + 8004ec0: 20003ee8 .word 0x20003ee8 + 8004ec4: 20003f7c .word 0x20003f7c + 8004ec8: 20004004 .word 0x20004004 + 8004ecc: 20003f88 .word 0x20003f88 + +08004ed0 : +{ + 8004ed0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + configASSERT( uxSchedulerSuspended ); + 8004ed4: 4c31 ldr r4, [pc, #196] ; (8004f9c ) + 8004ed6: 6823 ldr r3, [r4, #0] + 8004ed8: b943 cbnz r3, 8004eec + 8004eda: f04f 0350 mov.w r3, #80 ; 0x50 + 8004ede: f383 8811 msr BASEPRI, r3 + 8004ee2: f3bf 8f6f isb sy + 8004ee6: f3bf 8f4f dsb sy + 8004eea: e7fe b.n 8004eea + taskENTER_CRITICAL(); + 8004eec: f7ff f8ba bl 8004064 + --uxSchedulerSuspended; + 8004ef0: 6823 ldr r3, [r4, #0] + 8004ef2: 3b01 subs r3, #1 + 8004ef4: 6023 str r3, [r4, #0] + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 8004ef6: 6824 ldr r4, [r4, #0] + 8004ef8: b12c cbz r4, 8004f06 +BaseType_t xAlreadyYielded = pdFALSE; + 8004efa: 2400 movs r4, #0 + taskEXIT_CRITICAL(); + 8004efc: f7ff f8d4 bl 80040a8 +} + 8004f00: 4620 mov r0, r4 + 8004f02: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) + 8004f06: 4b26 ldr r3, [pc, #152] ; (8004fa0 ) + 8004f08: 681b ldr r3, [r3, #0] + 8004f0a: 2b00 cmp r3, #0 + 8004f0c: d0f5 beq.n 8004efa + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + 8004f0e: f8df 90a8 ldr.w r9, [pc, #168] ; 8004fb8 + prvAddTaskToReadyList( pxTCB ); + 8004f12: 4f24 ldr r7, [pc, #144] ; (8004fa4 ) + 8004f14: f8df 80a4 ldr.w r8, [pc, #164] ; 8004fbc + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + 8004f18: f8d9 3000 ldr.w r3, [r9] + 8004f1c: b9e3 cbnz r3, 8004f58 + if( pxTCB != NULL ) + 8004f1e: b10c cbz r4, 8004f24 + prvResetNextTaskUnblockTime(); + 8004f20: f7ff fdce bl 8004ac0 + UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */ + 8004f24: 4d20 ldr r5, [pc, #128] ; (8004fa8 ) + 8004f26: 682c ldr r4, [r5, #0] + if( uxPendedCounts > ( UBaseType_t ) 0U ) + 8004f28: b144 cbz r4, 8004f3c + xYieldPending = pdTRUE; + 8004f2a: 4e20 ldr r6, [pc, #128] ; (8004fac ) + 8004f2c: 2701 movs r7, #1 + if( xTaskIncrementTick() != pdFALSE ) + 8004f2e: f7ff ff3d bl 8004dac + 8004f32: b100 cbz r0, 8004f36 + xYieldPending = pdTRUE; + 8004f34: 6037 str r7, [r6, #0] + } while( uxPendedCounts > ( UBaseType_t ) 0U ); + 8004f36: 3c01 subs r4, #1 + 8004f38: d1f9 bne.n 8004f2e + uxPendedTicks = 0; + 8004f3a: 602c str r4, [r5, #0] + if( xYieldPending != pdFALSE ) + 8004f3c: 4b1b ldr r3, [pc, #108] ; (8004fac ) + 8004f3e: 681b ldr r3, [r3, #0] + 8004f40: 2b00 cmp r3, #0 + 8004f42: d0da beq.n 8004efa + taskYIELD_IF_USING_PREEMPTION(); + 8004f44: 4b1a ldr r3, [pc, #104] ; (8004fb0 ) + 8004f46: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8004f4a: 601a str r2, [r3, #0] + 8004f4c: f3bf 8f4f dsb sy + 8004f50: f3bf 8f6f isb sy + xAlreadyYielded = pdTRUE; + 8004f54: 2401 movs r4, #1 + 8004f56: e7d1 b.n 8004efc + pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); + 8004f58: f8d9 300c ldr.w r3, [r9, #12] + 8004f5c: 68dc ldr r4, [r3, #12] + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 8004f5e: 1d26 adds r6, r4, #4 + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + 8004f60: f104 0018 add.w r0, r4, #24 + 8004f64: f7ff f80f bl 8003f86 + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 8004f68: 4630 mov r0, r6 + 8004f6a: f7ff f80c bl 8003f86 + prvAddTaskToReadyList( pxTCB ); + 8004f6e: 6ae2 ldr r2, [r4, #44] ; 0x2c + 8004f70: 6839 ldr r1, [r7, #0] + 8004f72: 2501 movs r5, #1 + 8004f74: fa05 f302 lsl.w r3, r5, r2 + 8004f78: 2014 movs r0, #20 + 8004f7a: 430b orrs r3, r1 + 8004f7c: fb00 8002 mla r0, r0, r2, r8 + 8004f80: 4631 mov r1, r6 + 8004f82: 603b str r3, [r7, #0] + 8004f84: f7fe ffdc bl 8003f40 + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + 8004f88: 4b0a ldr r3, [pc, #40] ; (8004fb4 ) + 8004f8a: 6ae2 ldr r2, [r4, #44] ; 0x2c + 8004f8c: 681b ldr r3, [r3, #0] + 8004f8e: 6adb ldr r3, [r3, #44] ; 0x2c + 8004f90: 429a cmp r2, r3 + xYieldPending = pdTRUE; + 8004f92: bf24 itt cs + 8004f94: 4b05 ldrcs r3, [pc, #20] ; (8004fac ) + 8004f96: 601d strcs r5, [r3, #0] + 8004f98: e7be b.n 8004f18 + 8004f9a: bf00 nop + 8004f9c: 20003f80 .word 0x20003f80 + 8004fa0: 20003f74 .word 0x20003f74 + 8004fa4: 20003f88 .word 0x20003f88 + 8004fa8: 20003f7c .word 0x20003f7c + 8004fac: 20004004 .word 0x20004004 + 8004fb0: e000ed04 .word 0xe000ed04 + 8004fb4: 20003edc .word 0x20003edc + 8004fb8: 20003fc0 .word 0x20003fc0 + 8004fbc: 20003ee8 .word 0x20003ee8 + +08004fc0 : + { + 8004fc0: b508 push {r3, lr} + if( xTicksToDelay > ( TickType_t ) 0U ) + 8004fc2: b940 cbnz r0, 8004fd6 + portYIELD_WITHIN_API(); + 8004fc4: 4b0e ldr r3, [pc, #56] ; (8005000 ) + 8004fc6: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8004fca: 601a str r2, [r3, #0] + 8004fcc: f3bf 8f4f dsb sy + 8004fd0: f3bf 8f6f isb sy + 8004fd4: bd08 pop {r3, pc} + configASSERT( uxSchedulerSuspended == 0 ); + 8004fd6: 4b0b ldr r3, [pc, #44] ; (8005004 ) + 8004fd8: 6819 ldr r1, [r3, #0] + 8004fda: b141 cbz r1, 8004fee + 8004fdc: f04f 0350 mov.w r3, #80 ; 0x50 + 8004fe0: f383 8811 msr BASEPRI, r3 + 8004fe4: f3bf 8f6f isb sy + 8004fe8: f3bf 8f4f dsb sy + 8004fec: e7fe b.n 8004fec + vTaskSuspendAll(); + 8004fee: f7ff fed5 bl 8004d9c + prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); + 8004ff2: f7ff fd77 bl 8004ae4 + xAlreadyYielded = xTaskResumeAll(); + 8004ff6: f7ff ff6b bl 8004ed0 + if( xAlreadyYielded == pdFALSE ) + 8004ffa: 2800 cmp r0, #0 + 8004ffc: d0e2 beq.n 8004fc4 + 8004ffe: bd08 pop {r3, pc} + 8005000: e000ed04 .word 0xe000ed04 + 8005004: 20003f80 .word 0x20003f80 + +08005008 : +{ + 8005008: b508 push {r3, lr} + xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination ); + 800500a: 4e17 ldr r6, [pc, #92] ; (8005068 ) + while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + 800500c: 4c17 ldr r4, [pc, #92] ; (800506c ) + 800500e: 6823 ldr r3, [r4, #0] + 8005010: b963 cbnz r3, 800502c + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) + 8005012: 4b17 ldr r3, [pc, #92] ; (8005070 ) + 8005014: 681b ldr r3, [r3, #0] + 8005016: 2b01 cmp r3, #1 + 8005018: d9f8 bls.n 800500c + taskYIELD(); + 800501a: 4b16 ldr r3, [pc, #88] ; (8005074 ) + 800501c: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8005020: 601a str r2, [r3, #0] + 8005022: f3bf 8f4f dsb sy + 8005026: f3bf 8f6f isb sy + 800502a: e7ef b.n 800500c + vTaskSuspendAll(); + 800502c: f7ff feb6 bl 8004d9c + xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination ); + 8005030: 6835 ldr r5, [r6, #0] + ( void ) xTaskResumeAll(); + 8005032: f7ff ff4d bl 8004ed0 + if( xListIsEmpty == pdFALSE ) + 8005036: 2d00 cmp r5, #0 + 8005038: d0e9 beq.n 800500e + taskENTER_CRITICAL(); + 800503a: f7ff f813 bl 8004064 + pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); + 800503e: 68f3 ldr r3, [r6, #12] + 8005040: 68dd ldr r5, [r3, #12] + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 8005042: 1d28 adds r0, r5, #4 + 8005044: f7fe ff9f bl 8003f86 + --uxCurrentNumberOfTasks; + 8005048: 4a0b ldr r2, [pc, #44] ; (8005078 ) + 800504a: 6813 ldr r3, [r2, #0] + 800504c: 3b01 subs r3, #1 + 800504e: 6013 str r3, [r2, #0] + --uxDeletedTasksWaitingCleanUp; + 8005050: 6823 ldr r3, [r4, #0] + 8005052: 3b01 subs r3, #1 + 8005054: 6023 str r3, [r4, #0] + taskEXIT_CRITICAL(); + 8005056: f7ff f827 bl 80040a8 + vPortFree( pxTCB->pxStack ); + 800505a: 6b28 ldr r0, [r5, #48] ; 0x30 + 800505c: f7ff f9ea bl 8004434 + vPortFree( pxTCB ); + 8005060: 4628 mov r0, r5 + 8005062: f7ff f9e7 bl 8004434 + 8005066: e7d2 b.n 800500e + 8005068: 20003fec .word 0x20003fec + 800506c: 20003f78 .word 0x20003f78 + 8005070: 20003ee8 .word 0x20003ee8 + 8005074: e000ed04 .word 0xe000ed04 + 8005078: 20003f74 .word 0x20003f74 + +0800507c : + if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) + 800507c: 4b17 ldr r3, [pc, #92] ; (80050dc ) + 800507e: 681a ldr r2, [r3, #0] + 8005080: 4b17 ldr r3, [pc, #92] ; (80050e0 ) +{ + 8005082: b510 push {r4, lr} + if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) + 8005084: b112 cbz r2, 800508c + xYieldPending = pdTRUE; + 8005086: 2201 movs r2, #1 + taskSELECT_HIGHEST_PRIORITY_TASK(); + 8005088: 601a str r2, [r3, #0] + 800508a: bd10 pop {r4, pc} + xYieldPending = pdFALSE; + 800508c: 601a str r2, [r3, #0] + taskSELECT_HIGHEST_PRIORITY_TASK(); + 800508e: 4b15 ldr r3, [pc, #84] ; (80050e4 ) + 8005090: 681b ldr r3, [r3, #0] + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + 8005092: fab3 f383 clz r3, r3 + 8005096: b2db uxtb r3, r3 + 8005098: f1c3 031f rsb r3, r3, #31 + 800509c: 2214 movs r2, #20 + 800509e: 4912 ldr r1, [pc, #72] ; (80050e8 ) + 80050a0: 435a muls r2, r3 + 80050a2: 1888 adds r0, r1, r2 + 80050a4: 588c ldr r4, [r1, r2] + 80050a6: b944 cbnz r4, 80050ba + __asm volatile + 80050a8: f04f 0350 mov.w r3, #80 ; 0x50 + 80050ac: f383 8811 msr BASEPRI, r3 + 80050b0: f3bf 8f6f isb sy + 80050b4: f3bf 8f4f dsb sy + 80050b8: e7fe b.n 80050b8 + 80050ba: 6844 ldr r4, [r0, #4] + 80050bc: 3208 adds r2, #8 + 80050be: 6864 ldr r4, [r4, #4] + 80050c0: 6044 str r4, [r0, #4] + 80050c2: 440a add r2, r1 + 80050c4: 4294 cmp r4, r2 + 80050c6: bf04 itt eq + 80050c8: 6862 ldreq r2, [r4, #4] + 80050ca: 6042 streq r2, [r0, #4] + 80050cc: 2214 movs r2, #20 + 80050ce: fb02 1303 mla r3, r2, r3, r1 + 80050d2: 685b ldr r3, [r3, #4] + 80050d4: 68da ldr r2, [r3, #12] + 80050d6: 4b05 ldr r3, [pc, #20] ; (80050ec ) + 80050d8: e7d6 b.n 8005088 + 80050da: bf00 nop + 80050dc: 20003f80 .word 0x20003f80 + 80050e0: 20004004 .word 0x20004004 + 80050e4: 20003f88 .word 0x20003f88 + 80050e8: 20003ee8 .word 0x20003ee8 + 80050ec: 20003edc .word 0x20003edc + +080050f0 : +{ + 80050f0: b510 push {r4, lr} + 80050f2: 460c mov r4, r1 + configASSERT( pxEventList ); + 80050f4: b940 cbnz r0, 8005108 + 80050f6: f04f 0350 mov.w r3, #80 ; 0x50 + 80050fa: f383 8811 msr BASEPRI, r3 + 80050fe: f3bf 8f6f isb sy + 8005102: f3bf 8f4f dsb sy + 8005106: e7fe b.n 8005106 + vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + 8005108: 4b05 ldr r3, [pc, #20] ; (8005120 ) + 800510a: 6819 ldr r1, [r3, #0] + 800510c: 3118 adds r1, #24 + 800510e: f7fe ff23 bl 8003f58 + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + 8005112: 4620 mov r0, r4 + 8005114: 2101 movs r1, #1 +} + 8005116: e8bd 4010 ldmia.w sp!, {r4, lr} + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + 800511a: f7ff bce3 b.w 8004ae4 + 800511e: bf00 nop + 8005120: 20003edc .word 0x20003edc + +08005124 : +{ + 8005124: b538 push {r3, r4, r5, lr} + pxUnblockedTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + 8005126: 68c3 ldr r3, [r0, #12] + 8005128: 68dc ldr r4, [r3, #12] + configASSERT( pxUnblockedTCB ); + 800512a: b944 cbnz r4, 800513e + 800512c: f04f 0350 mov.w r3, #80 ; 0x50 + 8005130: f383 8811 msr BASEPRI, r3 + 8005134: f3bf 8f6f isb sy + 8005138: f3bf 8f4f dsb sy + 800513c: e7fe b.n 800513c + ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); + 800513e: f104 0518 add.w r5, r4, #24 + 8005142: 4628 mov r0, r5 + 8005144: f7fe ff1f bl 8003f86 + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 8005148: 4b11 ldr r3, [pc, #68] ; (8005190 ) + 800514a: 681b ldr r3, [r3, #0] + 800514c: b9e3 cbnz r3, 8005188 + ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); + 800514e: 1d25 adds r5, r4, #4 + 8005150: 4628 mov r0, r5 + 8005152: f7fe ff18 bl 8003f86 + prvAddTaskToReadyList( pxUnblockedTCB ); + 8005156: 490f ldr r1, [pc, #60] ; (8005194 ) + 8005158: 6ae2 ldr r2, [r4, #44] ; 0x2c + 800515a: 6808 ldr r0, [r1, #0] + 800515c: 2301 movs r3, #1 + 800515e: 4093 lsls r3, r2 + 8005160: 4303 orrs r3, r0 + 8005162: 600b str r3, [r1, #0] + 8005164: 4b0c ldr r3, [pc, #48] ; (8005198 ) + 8005166: 2014 movs r0, #20 + 8005168: 4629 mov r1, r5 + 800516a: fb00 3002 mla r0, r0, r2, r3 + vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); + 800516e: f7fe fee7 bl 8003f40 + if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + 8005172: 4b0a ldr r3, [pc, #40] ; (800519c ) + 8005174: 6ae2 ldr r2, [r4, #44] ; 0x2c + 8005176: 681b ldr r3, [r3, #0] + 8005178: 6adb ldr r3, [r3, #44] ; 0x2c + 800517a: 429a cmp r2, r3 + xYieldPending = pdTRUE; + 800517c: bf83 ittte hi + 800517e: 4b08 ldrhi r3, [pc, #32] ; (80051a0 ) + 8005180: 2001 movhi r0, #1 + 8005182: 6018 strhi r0, [r3, #0] + xReturn = pdFALSE; + 8005184: 2000 movls r0, #0 +} + 8005186: bd38 pop {r3, r4, r5, pc} + vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); + 8005188: 4629 mov r1, r5 + 800518a: 4806 ldr r0, [pc, #24] ; (80051a4 ) + 800518c: e7ef b.n 800516e + 800518e: bf00 nop + 8005190: 20003f80 .word 0x20003f80 + 8005194: 20003f88 .word 0x20003f88 + 8005198: 20003ee8 .word 0x20003ee8 + 800519c: 20003edc .word 0x20003edc + 80051a0: 20004004 .word 0x20004004 + 80051a4: 20003fc0 .word 0x20003fc0 + +080051a8 : +{ + 80051a8: b508 push {r3, lr} + configASSERT( pxTimeOut ); + 80051aa: b908 cbnz r0, 80051b0 + 80051ac: f7ff fce0 bl 8004b70 + pxTimeOut->xOverflowCount = xNumOfOverflows; + 80051b0: 4b03 ldr r3, [pc, #12] ; (80051c0 ) + 80051b2: 681b ldr r3, [r3, #0] + 80051b4: 6003 str r3, [r0, #0] + pxTimeOut->xTimeOnEntering = xTickCount; + 80051b6: 4b03 ldr r3, [pc, #12] ; (80051c4 ) + 80051b8: 681b ldr r3, [r3, #0] + 80051ba: 6043 str r3, [r0, #4] + 80051bc: bd08 pop {r3, pc} + 80051be: bf00 nop + 80051c0: 20003fbc .word 0x20003fbc + 80051c4: 20004000 .word 0x20004000 + +080051c8 : +{ + 80051c8: b538 push {r3, r4, r5, lr} + 80051ca: 460d mov r5, r1 + configASSERT( pxTimeOut ); + 80051cc: 4604 mov r4, r0 + 80051ce: b940 cbnz r0, 80051e2 + 80051d0: f04f 0350 mov.w r3, #80 ; 0x50 + 80051d4: f383 8811 msr BASEPRI, r3 + 80051d8: f3bf 8f6f isb sy + 80051dc: f3bf 8f4f dsb sy + 80051e0: e7fe b.n 80051e0 + configASSERT( pxTicksToWait ); + 80051e2: b941 cbnz r1, 80051f6 + 80051e4: f04f 0350 mov.w r3, #80 ; 0x50 + 80051e8: f383 8811 msr BASEPRI, r3 + 80051ec: f3bf 8f6f isb sy + 80051f0: f3bf 8f4f dsb sy + 80051f4: e7fe b.n 80051f4 + taskENTER_CRITICAL(); + 80051f6: f7fe ff35 bl 8004064 + const TickType_t xConstTickCount = xTickCount; + 80051fa: 4b0e ldr r3, [pc, #56] ; (8005234 ) + 80051fc: 6819 ldr r1, [r3, #0] + if( *pxTicksToWait == portMAX_DELAY ) + 80051fe: 682b ldr r3, [r5, #0] + 8005200: 1c5a adds r2, r3, #1 + 8005202: d010 beq.n 8005226 + if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ + 8005204: 4a0c ldr r2, [pc, #48] ; (8005238 ) + 8005206: 6820 ldr r0, [r4, #0] + 8005208: 6812 ldr r2, [r2, #0] + 800520a: 4290 cmp r0, r2 + 800520c: 6862 ldr r2, [r4, #4] + 800520e: d001 beq.n 8005214 + 8005210: 4291 cmp r1, r2 + 8005212: d20d bcs.n 8005230 + else if( ( ( TickType_t ) ( xConstTickCount - pxTimeOut->xTimeOnEntering ) ) < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ + 8005214: 1a88 subs r0, r1, r2 + 8005216: 4283 cmp r3, r0 + 8005218: d90a bls.n 8005230 + *pxTicksToWait -= ( xConstTickCount - pxTimeOut->xTimeOnEntering ); + 800521a: 1a5b subs r3, r3, r1 + 800521c: 4413 add r3, r2 + 800521e: 602b str r3, [r5, #0] + vTaskSetTimeOutState( pxTimeOut ); + 8005220: 4620 mov r0, r4 + 8005222: f7ff ffc1 bl 80051a8 + xReturn = pdFALSE; + 8005226: 2400 movs r4, #0 + taskEXIT_CRITICAL(); + 8005228: f7fe ff3e bl 80040a8 +} + 800522c: 4620 mov r0, r4 + 800522e: bd38 pop {r3, r4, r5, pc} + xReturn = pdTRUE; + 8005230: 2401 movs r4, #1 + 8005232: e7f9 b.n 8005228 + 8005234: 20004000 .word 0x20004000 + 8005238: 20003fbc .word 0x20003fbc + +0800523c : + xYieldPending = pdTRUE; + 800523c: 4b01 ldr r3, [pc, #4] ; (8005244 ) + 800523e: 2201 movs r2, #1 + 8005240: 601a str r2, [r3, #0] + 8005242: 4770 bx lr + 8005244: 20004004 .word 0x20004004 + +08005248 : + if( xSchedulerRunning == pdFALSE ) + 8005248: 4b05 ldr r3, [pc, #20] ; (8005260 ) + 800524a: 681b ldr r3, [r3, #0] + 800524c: b133 cbz r3, 800525c + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 800524e: 4b05 ldr r3, [pc, #20] ; (8005264 ) + 8005250: 681b ldr r3, [r3, #0] + 8005252: 2b00 cmp r3, #0 + xReturn = taskSCHEDULER_SUSPENDED; + 8005254: bf0c ite eq + 8005256: 2002 moveq r0, #2 + 8005258: 2000 movne r0, #0 + 800525a: 4770 bx lr + xReturn = taskSCHEDULER_NOT_STARTED; + 800525c: 2001 movs r0, #1 + } + 800525e: 4770 bx lr + 8005260: 20003fd4 .word 0x20003fd4 + 8005264: 20003f80 .word 0x20003f80 + +08005268 : + { + 8005268: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + if( pxMutexHolder != NULL ) + 800526c: 4604 mov r4, r0 + 800526e: 2800 cmp r0, #0 + 8005270: d038 beq.n 80052e4 + if( pxTCB->uxPriority < pxCurrentTCB->uxPriority ) + 8005272: 4d1d ldr r5, [pc, #116] ; (80052e8 ) + 8005274: 6ac3 ldr r3, [r0, #44] ; 0x2c + 8005276: 682a ldr r2, [r5, #0] + 8005278: 6ad2 ldr r2, [r2, #44] ; 0x2c + 800527a: 4293 cmp r3, r2 + 800527c: d232 bcs.n 80052e4 + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + 800527e: 6982 ldr r2, [r0, #24] + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) + 8005280: 4e1a ldr r6, [pc, #104] ; (80052ec ) + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + 8005282: 2a00 cmp r2, #0 + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8005284: bfa1 itttt ge + 8005286: 682a ldrge r2, [r5, #0] + 8005288: 6ad2 ldrge r2, [r2, #44] ; 0x2c + 800528a: f1c2 0207 rsbge r2, r2, #7 + 800528e: 6182 strge r2, [r0, #24] + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) + 8005290: 2714 movs r7, #20 + 8005292: 6942 ldr r2, [r0, #20] + 8005294: fb07 6303 mla r3, r7, r3, r6 + 8005298: 429a cmp r2, r3 + 800529a: d120 bne.n 80052de + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 800529c: f100 0804 add.w r8, r0, #4 + 80052a0: 4640 mov r0, r8 + 80052a2: f7fe fe70 bl 8003f86 + 80052a6: 4a12 ldr r2, [pc, #72] ; (80052f0 ) + 80052a8: b948 cbnz r0, 80052be + taskRESET_READY_PRIORITY( pxTCB->uxPriority ); + 80052aa: 6ae0 ldr r0, [r4, #44] ; 0x2c + 80052ac: 4347 muls r7, r0 + 80052ae: 59f3 ldr r3, [r6, r7] + 80052b0: b92b cbnz r3, 80052be + 80052b2: 6813 ldr r3, [r2, #0] + 80052b4: 2101 movs r1, #1 + 80052b6: 4081 lsls r1, r0 + 80052b8: ea23 0301 bic.w r3, r3, r1 + 80052bc: 6013 str r3, [r2, #0] + pxTCB->uxPriority = pxCurrentTCB->uxPriority; + 80052be: 682b ldr r3, [r5, #0] + prvAddTaskToReadyList( pxTCB ); + 80052c0: 6811 ldr r1, [r2, #0] + pxTCB->uxPriority = pxCurrentTCB->uxPriority; + 80052c2: 6ad8 ldr r0, [r3, #44] ; 0x2c + 80052c4: 62e0 str r0, [r4, #44] ; 0x2c + prvAddTaskToReadyList( pxTCB ); + 80052c6: 2301 movs r3, #1 + 80052c8: 4083 lsls r3, r0 + 80052ca: 430b orrs r3, r1 + 80052cc: 6013 str r3, [r2, #0] + 80052ce: 2314 movs r3, #20 + 80052d0: 4641 mov r1, r8 + 80052d2: fb03 6000 mla r0, r3, r0, r6 + } + 80052d6: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + prvAddTaskToReadyList( pxTCB ); + 80052da: f7fe be31 b.w 8003f40 + pxTCB->uxPriority = pxCurrentTCB->uxPriority; + 80052de: 682b ldr r3, [r5, #0] + 80052e0: 6adb ldr r3, [r3, #44] ; 0x2c + 80052e2: 62c3 str r3, [r0, #44] ; 0x2c + 80052e4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 80052e8: 20003edc .word 0x20003edc + 80052ec: 20003ee8 .word 0x20003ee8 + 80052f0: 20003f88 .word 0x20003f88 + +080052f4 : + { + 80052f4: b5f8 push {r3, r4, r5, r6, r7, lr} + if( pxMutexHolder != NULL ) + 80052f6: 4604 mov r4, r0 + 80052f8: b908 cbnz r0, 80052fe + BaseType_t xReturn = pdFALSE; + 80052fa: 2000 movs r0, #0 + 80052fc: bdf8 pop {r3, r4, r5, r6, r7, pc} + configASSERT( pxTCB == pxCurrentTCB ); + 80052fe: 4b22 ldr r3, [pc, #136] ; (8005388 ) + 8005300: 681b ldr r3, [r3, #0] + 8005302: 4298 cmp r0, r3 + 8005304: d008 beq.n 8005318 + 8005306: f04f 0350 mov.w r3, #80 ; 0x50 + 800530a: f383 8811 msr BASEPRI, r3 + 800530e: f3bf 8f6f isb sy + 8005312: f3bf 8f4f dsb sy + 8005316: e7fe b.n 8005316 + configASSERT( pxTCB->uxMutexesHeld ); + 8005318: 6c83 ldr r3, [r0, #72] ; 0x48 + 800531a: b943 cbnz r3, 800532e + 800531c: f04f 0350 mov.w r3, #80 ; 0x50 + 8005320: f383 8811 msr BASEPRI, r3 + 8005324: f3bf 8f6f isb sy + 8005328: f3bf 8f4f dsb sy + 800532c: e7fe b.n 800532c + if( pxTCB->uxPriority != pxTCB->uxBasePriority ) + 800532e: 6ac1 ldr r1, [r0, #44] ; 0x2c + 8005330: 6c42 ldr r2, [r0, #68] ; 0x44 + ( pxTCB->uxMutexesHeld )--; + 8005332: 3b01 subs r3, #1 + if( pxTCB->uxPriority != pxTCB->uxBasePriority ) + 8005334: 4291 cmp r1, r2 + ( pxTCB->uxMutexesHeld )--; + 8005336: 6483 str r3, [r0, #72] ; 0x48 + if( pxTCB->uxPriority != pxTCB->uxBasePriority ) + 8005338: d0df beq.n 80052fa + if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) + 800533a: 2b00 cmp r3, #0 + 800533c: d1dd bne.n 80052fa + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 800533e: 1d05 adds r5, r0, #4 + 8005340: 4628 mov r0, r5 + 8005342: f7fe fe20 bl 8003f86 + 8005346: 4e11 ldr r6, [pc, #68] ; (800538c ) + 8005348: 4a11 ldr r2, [pc, #68] ; (8005390 ) + 800534a: b950 cbnz r0, 8005362 + taskRESET_READY_PRIORITY( pxTCB->uxPriority ); + 800534c: 6ae7 ldr r7, [r4, #44] ; 0x2c + 800534e: 2114 movs r1, #20 + 8005350: 4379 muls r1, r7 + 8005352: 5873 ldr r3, [r6, r1] + 8005354: b92b cbnz r3, 8005362 + 8005356: 6813 ldr r3, [r2, #0] + 8005358: 2001 movs r0, #1 + 800535a: 40b8 lsls r0, r7 + 800535c: ea23 0300 bic.w r3, r3, r0 + 8005360: 6013 str r3, [r2, #0] + pxTCB->uxPriority = pxTCB->uxBasePriority; + 8005362: 6c63 ldr r3, [r4, #68] ; 0x44 + 8005364: 62e3 str r3, [r4, #44] ; 0x2c + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8005366: f1c3 0107 rsb r1, r3, #7 + 800536a: 61a1 str r1, [r4, #24] + prvAddTaskToReadyList( pxTCB ); + 800536c: 6811 ldr r1, [r2, #0] + 800536e: 2401 movs r4, #1 + 8005370: fa04 f003 lsl.w r0, r4, r3 + 8005374: 4308 orrs r0, r1 + 8005376: 6010 str r0, [r2, #0] + 8005378: 2014 movs r0, #20 + 800537a: fb00 6003 mla r0, r0, r3, r6 + 800537e: 4629 mov r1, r5 + 8005380: f7fe fdde bl 8003f40 + xReturn = pdTRUE; + 8005384: 4620 mov r0, r4 + } + 8005386: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8005388: 20003edc .word 0x20003edc + 800538c: 20003ee8 .word 0x20003ee8 + 8005390: 20003f88 .word 0x20003f88 + +08005394 : + if( pxCurrentTCB != NULL ) + 8005394: 4b04 ldr r3, [pc, #16] ; (80053a8 ) + 8005396: 681a ldr r2, [r3, #0] + 8005398: b11a cbz r2, 80053a2 + ( pxCurrentTCB->uxMutexesHeld )++; + 800539a: 6819 ldr r1, [r3, #0] + 800539c: 6c8a ldr r2, [r1, #72] ; 0x48 + 800539e: 3201 adds r2, #1 + 80053a0: 648a str r2, [r1, #72] ; 0x48 + return pxCurrentTCB; + 80053a2: 6818 ldr r0, [r3, #0] + } + 80053a4: 4770 bx lr + 80053a6: bf00 nop + 80053a8: 20003edc .word 0x20003edc + +080053ac : + { + 80053ac: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) + 80053b0: 4c1f ldr r4, [pc, #124] ; (8005430 ) + { + 80053b2: 461e mov r6, r3 + 80053b4: 4680 mov r8, r0 + 80053b6: 460f mov r7, r1 + 80053b8: 4615 mov r5, r2 + taskENTER_CRITICAL(); + 80053ba: f7fe fe53 bl 8004064 + if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) + 80053be: 6823 ldr r3, [r4, #0] + 80053c0: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 + 80053c4: 2b02 cmp r3, #2 + 80053c6: d014 beq.n 80053f2 + pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry; + 80053c8: 6823 ldr r3, [r4, #0] + 80053ca: 6cda ldr r2, [r3, #76] ; 0x4c + 80053cc: ea22 0208 bic.w r2, r2, r8 + 80053d0: 64da str r2, [r3, #76] ; 0x4c + pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION; + 80053d2: 6823 ldr r3, [r4, #0] + 80053d4: 2101 movs r1, #1 + 80053d6: f883 1050 strb.w r1, [r3, #80] ; 0x50 + if( xTicksToWait > ( TickType_t ) 0 ) + 80053da: b156 cbz r6, 80053f2 + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + 80053dc: 4630 mov r0, r6 + 80053de: f7ff fb81 bl 8004ae4 + portYIELD_WITHIN_API(); + 80053e2: 4b14 ldr r3, [pc, #80] ; (8005434 ) + 80053e4: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 80053e8: 601a str r2, [r3, #0] + 80053ea: f3bf 8f4f dsb sy + 80053ee: f3bf 8f6f isb sy + taskEXIT_CRITICAL(); + 80053f2: f7fe fe59 bl 80040a8 + taskENTER_CRITICAL(); + 80053f6: f7fe fe35 bl 8004064 + if( pulNotificationValue != NULL ) + 80053fa: b115 cbz r5, 8005402 + *pulNotificationValue = pxCurrentTCB->ulNotifiedValue; + 80053fc: 6823 ldr r3, [r4, #0] + 80053fe: 6cdb ldr r3, [r3, #76] ; 0x4c + 8005400: 602b str r3, [r5, #0] + if( pxCurrentTCB->ucNotifyState == taskWAITING_NOTIFICATION ) + 8005402: 6823 ldr r3, [r4, #0] + 8005404: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 + 8005408: 2b01 cmp r3, #1 + pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit; + 800540a: bf1f itttt ne + 800540c: 6823 ldrne r3, [r4, #0] + 800540e: 6cd9 ldrne r1, [r3, #76] ; 0x4c + 8005410: 43b9 bicne r1, r7 + 8005412: 64d9 strne r1, [r3, #76] ; 0x4c + pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; + 8005414: 6823 ldr r3, [r4, #0] + 8005416: f04f 0200 mov.w r2, #0 + xReturn = pdTRUE; + 800541a: bf14 ite ne + 800541c: 2501 movne r5, #1 + xReturn = pdFALSE; + 800541e: 2500 moveq r5, #0 + pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; + 8005420: f883 2050 strb.w r2, [r3, #80] ; 0x50 + taskEXIT_CRITICAL(); + 8005424: f7fe fe40 bl 80040a8 + } + 8005428: 4628 mov r0, r5 + 800542a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 800542e: bf00 nop + 8005430: 20003edc .word 0x20003edc + 8005434: e000ed04 .word 0xe000ed04 + +08005438 : + { + 8005438: b5f8 push {r3, r4, r5, r6, r7, lr} + 800543a: 460f mov r7, r1 + 800543c: 4616 mov r6, r2 + 800543e: 461d mov r5, r3 + configASSERT( xTaskToNotify ); + 8005440: 4604 mov r4, r0 + 8005442: b940 cbnz r0, 8005456 + 8005444: f04f 0350 mov.w r3, #80 ; 0x50 + 8005448: f383 8811 msr BASEPRI, r3 + 800544c: f3bf 8f6f isb sy + 8005450: f3bf 8f4f dsb sy + 8005454: e7fe b.n 8005454 + taskENTER_CRITICAL(); + 8005456: f7fe fe05 bl 8004064 + if( pulPreviousNotificationValue != NULL ) + 800545a: b10d cbz r5, 8005460 + *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; + 800545c: 6ce3 ldr r3, [r4, #76] ; 0x4c + 800545e: 602b str r3, [r5, #0] + ucOriginalNotifyState = pxTCB->ucNotifyState; + 8005460: f894 5050 ldrb.w r5, [r4, #80] ; 0x50 + pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; + 8005464: 2302 movs r3, #2 + switch( eAction ) + 8005466: 1e72 subs r2, r6, #1 + ucOriginalNotifyState = pxTCB->ucNotifyState; + 8005468: b2ed uxtb r5, r5 + pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; + 800546a: f884 3050 strb.w r3, [r4, #80] ; 0x50 + switch( eAction ) + 800546e: 2a03 cmp r2, #3 + 8005470: d80a bhi.n 8005488 + 8005472: e8df f002 tbb [pc, r2] + 8005476: 0602 .short 0x0602 + 8005478: 1004 .short 0x1004 + pxTCB->ulNotifiedValue |= ulValue; + 800547a: 6ce1 ldr r1, [r4, #76] ; 0x4c + 800547c: 430f orrs r7, r1 + pxTCB->ulNotifiedValue = ulValue; + 800547e: 64e7 str r7, [r4, #76] ; 0x4c + 8005480: e002 b.n 8005488 + ( pxTCB->ulNotifiedValue )++; + 8005482: 6ce3 ldr r3, [r4, #76] ; 0x4c + 8005484: 3301 adds r3, #1 + 8005486: 64e3 str r3, [r4, #76] ; 0x4c + if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) + 8005488: 2d01 cmp r5, #1 + 800548a: d008 beq.n 800549e + { + 800548c: 2501 movs r5, #1 + taskEXIT_CRITICAL(); + 800548e: f7fe fe0b bl 80040a8 + } + 8005492: 4628 mov r0, r5 + 8005494: bdf8 pop {r3, r4, r5, r6, r7, pc} + if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) + 8005496: 2d02 cmp r5, #2 + 8005498: d1f1 bne.n 800547e + xReturn = pdFAIL; + 800549a: 2500 movs r5, #0 + 800549c: e7f7 b.n 800548e + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 800549e: 1d26 adds r6, r4, #4 + 80054a0: 4630 mov r0, r6 + 80054a2: f7fe fd70 bl 8003f86 + prvAddTaskToReadyList( pxTCB ); + 80054a6: 4914 ldr r1, [pc, #80] ; (80054f8 ) + 80054a8: 6ae2 ldr r2, [r4, #44] ; 0x2c + 80054aa: 6808 ldr r0, [r1, #0] + 80054ac: fa05 f302 lsl.w r3, r5, r2 + 80054b0: 4303 orrs r3, r0 + 80054b2: 600b str r3, [r1, #0] + 80054b4: 4b11 ldr r3, [pc, #68] ; (80054fc ) + 80054b6: 2014 movs r0, #20 + 80054b8: fb00 3002 mla r0, r0, r2, r3 + 80054bc: 4631 mov r1, r6 + 80054be: f7fe fd3f bl 8003f40 + configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); + 80054c2: 6aa3 ldr r3, [r4, #40] ; 0x28 + 80054c4: b143 cbz r3, 80054d8 + 80054c6: f04f 0350 mov.w r3, #80 ; 0x50 + 80054ca: f383 8811 msr BASEPRI, r3 + 80054ce: f3bf 8f6f isb sy + 80054d2: f3bf 8f4f dsb sy + 80054d6: e7fe b.n 80054d6 + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + 80054d8: 4b09 ldr r3, [pc, #36] ; (8005500 ) + 80054da: 6ae2 ldr r2, [r4, #44] ; 0x2c + 80054dc: 681b ldr r3, [r3, #0] + 80054de: 6adb ldr r3, [r3, #44] ; 0x2c + 80054e0: 429a cmp r2, r3 + 80054e2: d9d3 bls.n 800548c + taskYIELD_IF_USING_PREEMPTION(); + 80054e4: 4b07 ldr r3, [pc, #28] ; (8005504 ) + 80054e6: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 80054ea: 601a str r2, [r3, #0] + 80054ec: f3bf 8f4f dsb sy + 80054f0: f3bf 8f6f isb sy + 80054f4: e7cb b.n 800548e + 80054f6: bf00 nop + 80054f8: 20003f88 .word 0x20003f88 + 80054fc: 20003ee8 .word 0x20003ee8 + 8005500: 20003edc .word 0x20003edc + 8005504: e000ed04 .word 0xe000ed04 + +08005508 : + { + 8005508: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 800550c: 9f08 ldr r7, [sp, #32] + 800550e: 4689 mov r9, r1 + 8005510: 4690 mov r8, r2 + 8005512: 461d mov r5, r3 + configASSERT( xTaskToNotify ); + 8005514: 4604 mov r4, r0 + 8005516: b940 cbnz r0, 800552a + 8005518: f04f 0350 mov.w r3, #80 ; 0x50 + 800551c: f383 8811 msr BASEPRI, r3 + 8005520: f3bf 8f6f isb sy + 8005524: f3bf 8f4f dsb sy + 8005528: e7fe b.n 8005528 + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + 800552a: f7fe fea3 bl 8004274 + __asm volatile + 800552e: f3ef 8611 mrs r6, BASEPRI + 8005532: f04f 0350 mov.w r3, #80 ; 0x50 + 8005536: f383 8811 msr BASEPRI, r3 + 800553a: f3bf 8f6f isb sy + 800553e: f3bf 8f4f dsb sy + if( pulPreviousNotificationValue != NULL ) + 8005542: b10d cbz r5, 8005548 + *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; + 8005544: 6ce3 ldr r3, [r4, #76] ; 0x4c + 8005546: 602b str r3, [r5, #0] + ucOriginalNotifyState = pxTCB->ucNotifyState; + 8005548: f894 5050 ldrb.w r5, [r4, #80] ; 0x50 + pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; + 800554c: 2302 movs r3, #2 + switch( eAction ) + 800554e: f108 32ff add.w r2, r8, #4294967295 + ucOriginalNotifyState = pxTCB->ucNotifyState; + 8005552: b2ed uxtb r5, r5 + pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; + 8005554: f884 3050 strb.w r3, [r4, #80] ; 0x50 + switch( eAction ) + 8005558: 2a03 cmp r2, #3 + 800555a: d807 bhi.n 800556c + 800555c: e8df f002 tbb [pc, r2] + 8005560: 11130d02 .word 0x11130d02 + pxTCB->ulNotifiedValue |= ulValue; + 8005564: 6ce1 ldr r1, [r4, #76] ; 0x4c + 8005566: ea41 0109 orr.w r1, r1, r9 + 800556a: 64e1 str r1, [r4, #76] ; 0x4c + if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) + 800556c: 2d01 cmp r5, #1 + 800556e: d00d beq.n 800558c + { + 8005570: 2001 movs r0, #1 + __asm volatile + 8005572: f386 8811 msr BASEPRI, r6 + } + 8005576: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + ( pxTCB->ulNotifiedValue )++; + 800557a: 6ce3 ldr r3, [r4, #76] ; 0x4c + 800557c: 3301 adds r3, #1 + 800557e: 64e3 str r3, [r4, #76] ; 0x4c + break; + 8005580: e7f4 b.n 800556c + if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) + 8005582: 2d02 cmp r5, #2 + 8005584: d033 beq.n 80055ee + pxTCB->ulNotifiedValue = ulValue; + 8005586: f8c4 904c str.w r9, [r4, #76] ; 0x4c + 800558a: e7ef b.n 800556c + configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); + 800558c: 6aa3 ldr r3, [r4, #40] ; 0x28 + 800558e: b143 cbz r3, 80055a2 + __asm volatile + 8005590: f04f 0350 mov.w r3, #80 ; 0x50 + 8005594: f383 8811 msr BASEPRI, r3 + 8005598: f3bf 8f6f isb sy + 800559c: f3bf 8f4f dsb sy + 80055a0: e7fe b.n 80055a0 + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 80055a2: 4b14 ldr r3, [pc, #80] ; (80055f4 ) + 80055a4: 681b ldr r3, [r3, #0] + 80055a6: b9db cbnz r3, 80055e0 + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 80055a8: f104 0804 add.w r8, r4, #4 + 80055ac: 4640 mov r0, r8 + 80055ae: f7fe fcea bl 8003f86 + prvAddTaskToReadyList( pxTCB ); + 80055b2: 4a11 ldr r2, [pc, #68] ; (80055f8 ) + 80055b4: 6ae3 ldr r3, [r4, #44] ; 0x2c + 80055b6: 6811 ldr r1, [r2, #0] + 80055b8: 409d lsls r5, r3 + 80055ba: 430d orrs r5, r1 + 80055bc: 6015 str r5, [r2, #0] + 80055be: 4a0f ldr r2, [pc, #60] ; (80055fc ) + 80055c0: 2014 movs r0, #20 + 80055c2: 4641 mov r1, r8 + 80055c4: fb00 2003 mla r0, r0, r3, r2 + vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + 80055c8: f7fe fcba bl 8003f40 + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + 80055cc: 4b0c ldr r3, [pc, #48] ; (8005600 ) + 80055ce: 6ae2 ldr r2, [r4, #44] ; 0x2c + 80055d0: 681b ldr r3, [r3, #0] + 80055d2: 6adb ldr r3, [r3, #44] ; 0x2c + 80055d4: 429a cmp r2, r3 + 80055d6: d9cb bls.n 8005570 + 80055d8: 2001 movs r0, #1 + if( pxHigherPriorityTaskWoken != NULL ) + 80055da: b12f cbz r7, 80055e8 + *pxHigherPriorityTaskWoken = pdTRUE; + 80055dc: 6038 str r0, [r7, #0] + 80055de: e7c8 b.n 8005572 + vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + 80055e0: f104 0118 add.w r1, r4, #24 + 80055e4: 4807 ldr r0, [pc, #28] ; (8005604 ) + 80055e6: e7ef b.n 80055c8 + xYieldPending = pdTRUE; + 80055e8: 4b07 ldr r3, [pc, #28] ; (8005608 ) + 80055ea: 6018 str r0, [r3, #0] + 80055ec: e7c1 b.n 8005572 + xReturn = pdFAIL; + 80055ee: 2000 movs r0, #0 + 80055f0: e7bf b.n 8005572 + 80055f2: bf00 nop + 80055f4: 20003f80 .word 0x20003f80 + 80055f8: 20003f88 .word 0x20003f88 + 80055fc: 20003ee8 .word 0x20003ee8 + 8005600: 20003edc .word 0x20003edc + 8005604: 20003fc0 .word 0x20003fc0 + 8005608: 20004004 .word 0x20004004 + +0800560c : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 800560c: b570 push {r4, r5, r6, lr} + 800560e: b098 sub sp, #96 ; 0x60 + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /**Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + 8005610: 4b2d ldr r3, [pc, #180] ; (80056c8 ) + 8005612: 2100 movs r1, #0 + 8005614: 9101 str r1, [sp, #4] + 8005616: 6c1a ldr r2, [r3, #64] ; 0x40 + 8005618: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 + 800561c: 641a str r2, [r3, #64] ; 0x40 + 800561e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005620: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8005624: 9301 str r3, [sp, #4] + 8005626: 9b01 ldr r3, [sp, #4] + + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8005628: 4b28 ldr r3, [pc, #160] ; (80056cc ) + 800562a: 9102 str r1, [sp, #8] + 800562c: 681a ldr r2, [r3, #0] + 800562e: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 8005632: 601a str r2, [r3, #0] + 8005634: 681b ldr r3, [r3, #0] + 8005636: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800563a: 9302 str r3, [sp, #8] + 800563c: 9b02 ldr r3, [sp, #8] + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 800563e: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8005642: 930d str r3, [sp, #52] ; 0x34 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 8005644: f44f 0380 mov.w r3, #4194304 ; 0x400000 + 8005648: 9313 str r3, [sp, #76] ; 0x4c + RCC_OscInitStruct.PLL.PLLM = 8; + 800564a: 2308 movs r3, #8 + 800564c: 9314 str r3, [sp, #80] ; 0x50 + RCC_OscInitStruct.PLL.PLLN = 336; + 800564e: f44f 73a8 mov.w r3, #336 ; 0x150 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 8005652: 2402 movs r4, #2 + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + 8005654: 2601 movs r6, #1 + RCC_OscInitStruct.PLL.PLLN = 336; + 8005656: 9315 str r3, [sp, #84] ; 0x54 + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8005658: a80c add r0, sp, #48 ; 0x30 + RCC_OscInitStruct.PLL.PLLQ = 7; + 800565a: 2307 movs r3, #7 + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + 800565c: 960c str r6, [sp, #48] ; 0x30 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 800565e: 9412 str r4, [sp, #72] ; 0x48 + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + 8005660: 9416 str r4, [sp, #88] ; 0x58 + RCC_OscInitStruct.PLL.PLLQ = 7; + 8005662: 9317 str r3, [sp, #92] ; 0x5c + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8005664: f7fc fc48 bl 8001ef8 + 8005668: b100 cbz r0, 800566c + 800566a: e7fe b.n 800566a + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + 800566c: f44f 53a0 mov.w r3, #5120 ; 0x1400 + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8005670: 250f movs r5, #15 + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 8005672: 9009 str r0, [sp, #36] ; 0x24 + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + 8005674: 930a str r3, [sp, #40] ; 0x28 + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + 8005676: 2105 movs r1, #5 + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + 8005678: f44f 5380 mov.w r3, #4096 ; 0x1000 + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + 800567c: a807 add r0, sp, #28 + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 800567e: 9507 str r5, [sp, #28] + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 8005680: 9408 str r4, [sp, #32] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + 8005682: 930b str r3, [sp, #44] ; 0x2c + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + 8005684: f7fc fde8 bl 8002258 + 8005688: b100 cbz r0, 800568c + 800568a: e7fe b.n 800568a + { + _Error_Handler(__FILE__, __LINE__); + } + + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + 800568c: 23c0 movs r3, #192 ; 0xc0 + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 800568e: a803 add r0, sp, #12 + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; + 8005690: 9405 str r4, [sp, #20] + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S; + 8005692: 9603 str r6, [sp, #12] + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + 8005694: 9304 str r3, [sp, #16] + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 8005696: f7fc fead bl 80023f4 + 800569a: 4604 mov r4, r0 + 800569c: b100 cbz r0, 80056a0 + 800569e: e7fe b.n 800569e + _Error_Handler(__FILE__, __LINE__); + } + + /**Configure the Systick interrupt time + */ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + 80056a0: f7fc fe74 bl 800238c + 80056a4: f44f 737a mov.w r3, #1000 ; 0x3e8 + 80056a8: fbb0 f0f3 udiv r0, r0, r3 + 80056ac: f7fb fb7c bl 8000da8 + + /**Configure the Systick + */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + 80056b0: 2004 movs r0, #4 + 80056b2: f7fb fb8f bl 8000dd4 + + /* SysTick_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0); + 80056b6: 4622 mov r2, r4 + 80056b8: 4629 mov r1, r5 + 80056ba: f04f 30ff mov.w r0, #4294967295 + 80056be: f7fb fb33 bl 8000d28 +} + 80056c2: b018 add sp, #96 ; 0x60 + 80056c4: bd70 pop {r4, r5, r6, pc} + 80056c6: bf00 nop + 80056c8: 40023800 .word 0x40023800 + 80056cc: 40007000 .word 0x40007000 + +080056d0
: +{ + 80056d0: b580 push {r7, lr} + 80056d2: b094 sub sp, #80 ; 0x50 +{ + + GPIO_InitTypeDef GPIO_InitStruct; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + 80056d4: 2400 movs r4, #0 + HAL_Init(); + 80056d6: f7fb fad5 bl 8000c84 + SystemClock_Config(); + 80056da: f7ff ff97 bl 800560c + __HAL_RCC_GPIOE_CLK_ENABLE(); + 80056de: 4b81 ldr r3, [pc, #516] ; (80058e4 ) + 80056e0: 9401 str r4, [sp, #4] + 80056e2: 6b1a ldr r2, [r3, #48] ; 0x30 + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOE, GPIO_PIN_3, GPIO_PIN_RESET); + 80056e4: 4880 ldr r0, [pc, #512] ; (80058e8 ) + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pin : PA0 */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 80056e6: f8df 8244 ldr.w r8, [pc, #580] ; 800592c + __HAL_RCC_GPIOE_CLK_ENABLE(); + 80056ea: f042 0210 orr.w r2, r2, #16 + 80056ee: 631a str r2, [r3, #48] ; 0x30 + 80056f0: 6b1a ldr r2, [r3, #48] ; 0x30 + 80056f2: f002 0210 and.w r2, r2, #16 + 80056f6: 9201 str r2, [sp, #4] + 80056f8: 9a01 ldr r2, [sp, #4] + __HAL_RCC_GPIOC_CLK_ENABLE(); + 80056fa: 9402 str r4, [sp, #8] + 80056fc: 6b1a ldr r2, [r3, #48] ; 0x30 + 80056fe: f042 0204 orr.w r2, r2, #4 + 8005702: 631a str r2, [r3, #48] ; 0x30 + 8005704: 6b1a ldr r2, [r3, #48] ; 0x30 + 8005706: f002 0204 and.w r2, r2, #4 + 800570a: 9202 str r2, [sp, #8] + 800570c: 9a02 ldr r2, [sp, #8] + __HAL_RCC_GPIOH_CLK_ENABLE(); + 800570e: 9403 str r4, [sp, #12] + 8005710: 6b1a ldr r2, [r3, #48] ; 0x30 + 8005712: f042 0280 orr.w r2, r2, #128 ; 0x80 + 8005716: 631a str r2, [r3, #48] ; 0x30 + 8005718: 6b1a ldr r2, [r3, #48] ; 0x30 + 800571a: f002 0280 and.w r2, r2, #128 ; 0x80 + 800571e: 9203 str r2, [sp, #12] + 8005720: 9a03 ldr r2, [sp, #12] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8005722: 9404 str r4, [sp, #16] + 8005724: 6b1a ldr r2, [r3, #48] ; 0x30 + 8005726: f042 0201 orr.w r2, r2, #1 + 800572a: 631a str r2, [r3, #48] ; 0x30 + 800572c: 6b1a ldr r2, [r3, #48] ; 0x30 + 800572e: f002 0201 and.w r2, r2, #1 + 8005732: 9204 str r2, [sp, #16] + 8005734: 9a04 ldr r2, [sp, #16] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8005736: 9405 str r4, [sp, #20] + 8005738: 6b1a ldr r2, [r3, #48] ; 0x30 + 800573a: f042 0202 orr.w r2, r2, #2 + 800573e: 631a str r2, [r3, #48] ; 0x30 + 8005740: 6b1a ldr r2, [r3, #48] ; 0x30 + 8005742: f002 0202 and.w r2, r2, #2 + 8005746: 9205 str r2, [sp, #20] + 8005748: 9a05 ldr r2, [sp, #20] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 800574a: 9406 str r4, [sp, #24] + 800574c: 6b1a ldr r2, [r3, #48] ; 0x30 + 800574e: f042 0208 orr.w r2, r2, #8 + 8005752: 631a str r2, [r3, #48] ; 0x30 + 8005754: 6b1b ldr r3, [r3, #48] ; 0x30 + 8005756: f003 0308 and.w r3, r3, #8 + 800575a: 9306 str r3, [sp, #24] + HAL_GPIO_WritePin(GPIOE, GPIO_PIN_3, GPIO_PIN_RESET); + 800575c: 4622 mov r2, r4 + 800575e: 2108 movs r1, #8 + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8005760: 9b06 ldr r3, [sp, #24] + HAL_GPIO_WritePin(GPIOE, GPIO_PIN_3, GPIO_PIN_RESET); + 8005762: f7fb fcbb bl 80010dc + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET); + 8005766: 4622 mov r2, r4 + 8005768: 2101 movs r1, #1 + 800576a: 4860 ldr r0, [pc, #384] ; (80058ec ) + 800576c: f7fb fcb6 bl 80010dc + HAL_GPIO_WritePin(GPIOD, GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 + 8005770: 4622 mov r2, r4 + 8005772: f24f 0110 movw r1, #61456 ; 0xf010 + 8005776: 485e ldr r0, [pc, #376] ; (80058f0 ) + 8005778: f7fb fcb0 bl 80010dc + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 800577c: 2601 movs r6, #1 + GPIO_InitStruct.Pin = GPIO_PIN_3; + 800577e: 2508 movs r5, #8 + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 8005780: a90f add r1, sp, #60 ; 0x3c + 8005782: 4859 ldr r0, [pc, #356] ; (80058e8 ) + GPIO_InitStruct.Pin = GPIO_PIN_3; + 8005784: 950f str r5, [sp, #60] ; 0x3c + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8005786: 9610 str r6, [sp, #64] ; 0x40 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8005788: 9411 str r4, [sp, #68] ; 0x44 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800578a: 9412 str r4, [sp, #72] ; 0x48 + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 800578c: f7fb fb2e bl 8000dec + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8005790: a90f add r1, sp, #60 ; 0x3c + 8005792: 4856 ldr r0, [pc, #344] ; (80058ec ) + GPIO_InitStruct.Pin = GPIO_PIN_0; + 8005794: 960f str r6, [sp, #60] ; 0x3c + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8005796: 2702 movs r7, #2 + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8005798: 9610 str r6, [sp, #64] ; 0x40 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800579a: 9411 str r4, [sp, #68] ; 0x44 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800579c: 9412 str r4, [sp, #72] ; 0x48 + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 800579e: f7fb fb25 bl 8000dec + GPIO_InitStruct.Pin = GPIO_PIN_3; + 80057a2: 950f str r5, [sp, #60] ; 0x3c + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80057a4: a90f add r1, sp, #60 ; 0x3c + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + 80057a6: 2505 movs r5, #5 + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80057a8: 4850 ldr r0, [pc, #320] ; (80058ec ) + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80057aa: 9710 str r7, [sp, #64] ; 0x40 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80057ac: 9411 str r4, [sp, #68] ; 0x44 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80057ae: 9412 str r4, [sp, #72] ; 0x48 + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + 80057b0: 9513 str r5, [sp, #76] ; 0x4c + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80057b2: f7fb fb1b bl 8000dec + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80057b6: a90f add r1, sp, #60 ; 0x3c + 80057b8: 484e ldr r0, [pc, #312] ; (80058f4 ) + GPIO_InitStruct.Pin = GPIO_PIN_0; + 80057ba: 960f str r6, [sp, #60] ; 0x3c + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 80057bc: f8cd 8040 str.w r8, [sp, #64] ; 0x40 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80057c0: 9411 str r4, [sp, #68] ; 0x44 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80057c2: f7fb fb13 bl 8000dec + + /*Configure GPIO pin : PB2 */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + 80057c6: 2304 movs r3, #4 + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80057c8: a90f add r1, sp, #60 ; 0x3c + 80057ca: 484b ldr r0, [pc, #300] ; (80058f8 ) + GPIO_InitStruct.Pin = GPIO_PIN_2; + 80057cc: 930f str r3, [sp, #60] ; 0x3c + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 80057ce: 9410 str r4, [sp, #64] ; 0x40 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80057d0: 9411 str r4, [sp, #68] ; 0x44 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80057d2: f7fb fb0b bl 8000dec + + /*Configure GPIO pin : PB10 */ + GPIO_InitStruct.Pin = GPIO_PIN_10; + 80057d6: f44f 6380 mov.w r3, #1024 ; 0x400 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80057da: a90f add r1, sp, #60 ; 0x3c + 80057dc: 4846 ldr r0, [pc, #280] ; (80058f8 ) + GPIO_InitStruct.Pin = GPIO_PIN_10; + 80057de: 930f str r3, [sp, #60] ; 0x3c + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80057e0: 9710 str r7, [sp, #64] ; 0x40 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80057e2: 9411 str r4, [sp, #68] ; 0x44 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80057e4: 9412 str r4, [sp, #72] ; 0x48 + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + 80057e6: 9513 str r5, [sp, #76] ; 0x4c + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80057e8: f7fb fb00 bl 8000dec + + /*Configure GPIO pins : PD12 PD13 PD14 PD15 + PD4 */ + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 + 80057ec: f24f 0310 movw r3, #61456 ; 0xf010 + |GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 80057f0: a90f add r1, sp, #60 ; 0x3c + 80057f2: 483f ldr r0, [pc, #252] ; (80058f0 ) + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 + 80057f4: 930f str r3, [sp, #60] ; 0x3c + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80057f6: 9610 str r6, [sp, #64] ; 0x40 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80057f8: 9411 str r4, [sp, #68] ; 0x44 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80057fa: 9412 str r4, [sp, #72] ; 0x48 + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 80057fc: f7fb faf6 bl 8000dec + + /*Configure GPIO pin : PD5 */ + GPIO_InitStruct.Pin = GPIO_PIN_5; + 8005800: 2320 movs r3, #32 + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 8005802: a90f add r1, sp, #60 ; 0x3c + 8005804: 483a ldr r0, [pc, #232] ; (80058f0 ) + GPIO_InitStruct.Pin = GPIO_PIN_5; + 8005806: 930f str r3, [sp, #60] ; 0x3c + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8005808: 9410 str r4, [sp, #64] ; 0x40 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800580a: 9411 str r4, [sp, #68] ; 0x44 + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 800580c: f7fb faee bl 8000dec + + /*Configure GPIO pin : PE1 */ + GPIO_InitStruct.Pin = GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 8005810: 4835 ldr r0, [pc, #212] ; (80058e8 ) + GPIO_InitStruct.Pin = GPIO_PIN_1; + 8005812: 970f str r7, [sp, #60] ; 0x3c + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 8005814: a90f add r1, sp, #60 ; 0x3c + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 8005816: f8cd 8040 str.w r8, [sp, #64] ; 0x40 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800581a: 9411 str r4, [sp, #68] ; 0x44 + hi2c1.Init.ClockSpeed = 100000; + 800581c: 4e37 ldr r6, [pc, #220] ; (80058fc ) + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 800581e: f7fb fae5 bl 8000dec + hi2c1.Instance = I2C1; + 8005822: 4837 ldr r0, [pc, #220] ; (8005900 ) + hi2c1.Init.ClockSpeed = 100000; + 8005824: 4b37 ldr r3, [pc, #220] ; (8005904 ) + hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; + 8005826: 6084 str r4, [r0, #8] + hi2c1.Init.ClockSpeed = 100000; + 8005828: e880 0048 stmia.w r0, {r3, r6} + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 800582c: f44f 4380 mov.w r3, #16384 ; 0x4000 + hi2c1.Init.OwnAddress1 = 0; + 8005830: 60c4 str r4, [r0, #12] + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 8005832: 6103 str r3, [r0, #16] + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 8005834: 6144 str r4, [r0, #20] + hi2c1.Init.OwnAddress2 = 0; + 8005836: 6184 str r4, [r0, #24] + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 8005838: 61c4 str r4, [r0, #28] + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 800583a: 6204 str r4, [r0, #32] + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 800583c: f7fb fc54 bl 80010e8 + 8005840: b100 cbz r0, 8005844 + 8005842: e7fe b.n 8005842 + hi2s3.Instance = SPI3; + 8005844: 4b30 ldr r3, [pc, #192] ; (8005908 ) + hi2s3.Init.Mode = I2S_MODE_MASTER_TX; + 8005846: 4a31 ldr r2, [pc, #196] ; (800590c ) + hi2s3.Init.Standard = I2S_STANDARD_PHILIPS; + 8005848: 6098 str r0, [r3, #8] + hi2s3.Init.Mode = I2S_MODE_MASTER_TX; + 800584a: f44f 7400 mov.w r4, #512 ; 0x200 + 800584e: e883 0014 stmia.w r3, {r2, r4} + hi2s3.Init.DataFormat = I2S_DATAFORMAT_16B; + 8005852: 60d8 str r0, [r3, #12] + hi2s3.Init.AudioFreq = I2S_AUDIOFREQ_96K; + 8005854: 4a2e ldr r2, [pc, #184] ; (8005910 ) + hi2s3.Init.CPOL = I2S_CPOL_LOW; + 8005856: 6198 str r0, [r3, #24] + hi2s3.Init.ClockSource = I2S_CLOCK_PLL; + 8005858: 61d8 str r0, [r3, #28] + hi2s3.Init.FullDuplexMode = I2S_FULLDUPLEXMODE_DISABLE; + 800585a: 6218 str r0, [r3, #32] + if (HAL_I2S_Init(&hi2s3) != HAL_OK) + 800585c: 4618 mov r0, r3 + hi2s3.Init.MCLKOutput = I2S_MCLKOUTPUT_ENABLE; + 800585e: 611c str r4, [r3, #16] + hi2s3.Init.AudioFreq = I2S_AUDIOFREQ_96K; + 8005860: 615a str r2, [r3, #20] + if (HAL_I2S_Init(&hi2s3) != HAL_OK) + 8005862: f7fb fcb3 bl 80011cc + 8005866: b100 cbz r0, 800586a + 8005868: e7fe b.n 8005868 + hspi1.Instance = SPI1; + 800586a: 4b2a ldr r3, [pc, #168] ; (8005914 ) + hspi1.Init.Mode = SPI_MODE_MASTER; + 800586c: 492a ldr r1, [pc, #168] ; (8005918 ) + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 800586e: 6098 str r0, [r3, #8] + hspi1.Init.Mode = SPI_MODE_MASTER; + 8005870: f44f 7282 mov.w r2, #260 ; 0x104 + 8005874: e883 0006 stmia.w r3, {r1, r2} + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 8005878: 60d8 str r0, [r3, #12] + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 800587a: 6118 str r0, [r3, #16] + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 800587c: 6158 str r0, [r3, #20] + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 800587e: 61d8 str r0, [r3, #28] + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 8005880: 6218 str r0, [r3, #32] + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 8005882: 6258 str r0, [r3, #36] ; 0x24 + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8005884: 6298 str r0, [r3, #40] ; 0x28 + hspi1.Init.CRCPolynomial = 10; + 8005886: 220a movs r2, #10 + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 8005888: 4618 mov r0, r3 + hspi1.Init.NSS = SPI_NSS_SOFT; + 800588a: 619c str r4, [r3, #24] + hspi1.Init.CRCPolynomial = 10; + 800588c: 62da str r2, [r3, #44] ; 0x2c + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 800588e: f7fc fece bl 800262e + 8005892: 4607 mov r7, r0 + 8005894: b100 cbz r0, 8005898 + 8005896: e7fe b.n 8005896 + osThreadDef(Task01, StartTask01, osPriorityNormal, 0, 256); + 8005898: 4c20 ldr r4, [pc, #128] ; (800591c ) + 800589a: cc0f ldmia r4!, {r0, r1, r2, r3} + 800589c: ae0a add r6, sp, #40 ; 0x28 + 800589e: c60f stmia r6!, {r0, r1, r2, r3} + 80058a0: f854 3b04 ldr.w r3, [r4], #4 + 80058a4: 6033 str r3, [r6, #0] + Task01Handle = osThreadCreate(osThread(Task01), NULL); + 80058a6: 4639 mov r1, r7 + 80058a8: a80a add r0, sp, #40 ; 0x28 + 80058aa: f7fe f9a5 bl 8003bf8 + 80058ae: 4b1c ldr r3, [pc, #112] ; (8005920 ) + 80058b0: 6018 str r0, [r3, #0] + osThreadDef(Task02, StartTask02, osPriorityNormal, 0, 128); + 80058b2: cc0f ldmia r4!, {r0, r1, r2, r3} + 80058b4: ae0f add r6, sp, #60 ; 0x3c + 80058b6: c60f stmia r6!, {r0, r1, r2, r3} + 80058b8: 6823 ldr r3, [r4, #0] + 80058ba: 6033 str r3, [r6, #0] + Task02Handle = osThreadCreate(osThread(Task02), NULL); + 80058bc: 4639 mov r1, r7 + 80058be: a80f add r0, sp, #60 ; 0x3c + 80058c0: f7fe f99a bl 8003bf8 + 80058c4: 4b17 ldr r3, [pc, #92] ; (8005924 ) + osMailQDef(myMailQ, 5, GYRO_DATA_T); + 80058c6: 9507 str r5, [sp, #28] + Task02Handle = osThreadCreate(osThread(Task02), NULL); + 80058c8: 6018 str r0, [r3, #0] + myMailQID = osMailCreate(osMailQ(myMailQ), NULL); + 80058ca: 4639 mov r1, r7 + osMailQDef(myMailQ, 5, GYRO_DATA_T); + 80058cc: 2306 movs r3, #6 + myMailQID = osMailCreate(osMailQ(myMailQ), NULL); + 80058ce: a807 add r0, sp, #28 + osMailQDef(myMailQ, 5, GYRO_DATA_T); + 80058d0: 9308 str r3, [sp, #32] + 80058d2: f8cd d024 str.w sp, [sp, #36] ; 0x24 + myMailQID = osMailCreate(osMailQ(myMailQ), NULL); + 80058d6: f7fe fa7c bl 8003dd2 + 80058da: 4b13 ldr r3, [pc, #76] ; (8005928 ) + 80058dc: 6018 str r0, [r3, #0] + osKernelStart(); + 80058de: f7fe f986 bl 8003bee + 80058e2: e7fe b.n 80058e2 + 80058e4: 40023800 .word 0x40023800 + 80058e8: 40021000 .word 0x40021000 + 80058ec: 40020800 .word 0x40020800 + 80058f0: 40020c00 .word 0x40020c00 + 80058f4: 40020000 .word 0x40020000 + 80058f8: 40020400 .word 0x40020400 + 80058fc: 000186a0 .word 0x000186a0 + 8005900: 2000401c .word 0x2000401c + 8005904: 40005400 .word 0x40005400 + 8005908: 200040d0 .word 0x200040d0 + 800590c: 40003c00 .word 0x40003c00 + 8005910: 00017700 .word 0x00017700 + 8005914: 20004078 .word 0x20004078 + 8005918: 40013000 .word 0x40013000 + 800591c: 08006b54 .word 0x08006b54 + 8005920: 20004070 .word 0x20004070 + 8005924: 20004018 .word 0x20004018 + 8005928: 20004074 .word 0x20004074 + 800592c: 10110000 .word 0x10110000 + +08005930 : + +} + +/* USER CODE BEGIN 4 */ +void GYRO_Task(void) +{ + 8005930: b510 push {r4, lr} + 8005932: b086 sub sp, #24 + /* Initialize the L3GD20 Gyroscope */ + if (BSP_ACCELERO_Init() != HAL_OK) + 8005934: f7fb f962 bl 8000bfc + 8005938: b100 cbz r0, 800593c + 800593a: e7fe b.n 800593a + Error_Handler(); + } + /* Infinite loop */ + GYRO_DATA_T gyro_data; + + osSignalWait(0x1, osWaitForever); //Wait for signal. Check cmsis_os.c for API name. + 800593c: f04f 32ff mov.w r2, #4294967295 + 8005940: 2101 movs r1, #1 + 8005942: 4668 mov r0, sp + 8005944: f7fe f9a2 bl 8003c8c + BSP_ACCELERO_GetXYZ((int16_t *)&gyro_data); + /*Send gyroscope data to USB*/ + GYRO_DATA_T *gyro_tx; + do + { + gyro_tx = (GYRO_DATA_T *)osMailAlloc(myMailQID, osWaitForever); //Allocate memory slot + 8005948: 4c2f ldr r4, [pc, #188] ; (8005a08 ) + BSP_ACCELERO_GetXYZ((int16_t *)&gyro_data); + 800594a: a804 add r0, sp, #16 + 800594c: f7fb f97a bl 8000c44 + gyro_tx = (GYRO_DATA_T *)osMailAlloc(myMailQID, osWaitForever); //Allocate memory slot + 8005950: f04f 31ff mov.w r1, #4294967295 + 8005954: 6820 ldr r0, [r4, #0] + 8005956: f7fe fa67 bl 8003e28 + } while (NULL == gyro_tx); //Need to check for NULL because timeout value is not used in FreeRTOS + 800595a: 4601 mov r1, r0 + 800595c: 2800 cmp r0, #0 + 800595e: d0f7 beq.n 8005950 + gyro_tx->x_ang_rate = gyro_data.x_ang_rate; + 8005960: f9bd 3010 ldrsh.w r3, [sp, #16] + 8005964: 8003 strh r3, [r0, #0] + gyro_tx->y_ang_rate = gyro_data.y_ang_rate; + 8005966: f9bd 3012 ldrsh.w r3, [sp, #18] + 800596a: 8043 strh r3, [r0, #2] + gyro_tx->z_ang_rate = gyro_data.z_ang_rate; + 800596c: f9bd 3014 ldrsh.w r3, [sp, #20] + 8005970: 8083 strh r3, [r0, #4] + osMailPut(myMailQID, gyro_tx); //Put data into mail queue. Check cmsis_os.c for API name + 8005972: 6820 ldr r0, [r4, #0] + 8005974: f7fe fa5e bl 8003e34 + + /* Manage data */ + + /* Assume all data within the threshold, turn off all LED */ + BSP_LED_Off(LED3); + 8005978: 2001 movs r0, #1 + 800597a: f7fb f89d bl 8000ab8 + BSP_LED_Off(LED4); + 800597e: 2000 movs r0, #0 + 8005980: f7fb f89a bl 8000ab8 + BSP_LED_Off(LED5); + 8005984: 2002 movs r0, #2 + 8005986: f7fb f897 bl 8000ab8 + BSP_LED_Off(LED6); + 800598a: 2003 movs r0, #3 + 800598c: f7fb f894 bl 8000ab8 + if ((ABS(gyro_data.x_ang_rate)) > (ABS(gyro_data.y_ang_rate))) + 8005990: f9bd 2010 ldrsh.w r2, [sp, #16] + 8005994: f9bd 3012 ldrsh.w r3, [sp, #18] + 8005998: ea82 70e2 eor.w r0, r2, r2, asr #31 + 800599c: ea83 71e3 eor.w r1, r3, r3, asr #31 + 80059a0: eba0 70e2 sub.w r0, r0, r2, asr #31 + 80059a4: eba1 71e3 sub.w r1, r1, r3, asr #31 + 80059a8: 4288 cmp r0, r1 + 80059aa: dd1e ble.n 80059ea + { + if (gyro_data.x_ang_rate > ThresholdHigh) + 80059ac: 4b17 ldr r3, [pc, #92] ; (8005a0c ) + 80059ae: f9b3 3000 ldrsh.w r3, [r3] + 80059b2: 4293 cmp r3, r2 + 80059b4: da12 bge.n 80059dc + { + /* LED5 On */ + BSP_LED_On(LED5); + 80059b6: 2002 movs r0, #2 + osDelay(250); + } + else if (gyro_data.y_ang_rate > ThresholdHigh) + { + /* LED3 On */ + BSP_LED_On(LED3); + 80059b8: f7fb f870 bl 8000a9c + osDelay(250); + 80059bc: 20fa movs r0, #250 ; 0xfa + 80059be: f7fe f933 bl 8003c28 + { + osDelay(250); + } + } + + BSP_LED_Off(LED3); + 80059c2: 2001 movs r0, #1 + 80059c4: f7fb f878 bl 8000ab8 + BSP_LED_Off(LED4); + 80059c8: 2000 movs r0, #0 + 80059ca: f7fb f875 bl 8000ab8 + BSP_LED_Off(LED5); + 80059ce: 2002 movs r0, #2 + 80059d0: f7fb f872 bl 8000ab8 + BSP_LED_Off(LED6); + 80059d4: 2003 movs r0, #3 + 80059d6: f7fb f86f bl 8000ab8 + { + 80059da: e7b6 b.n 800594a + else if (gyro_data.x_ang_rate < ThresholdLow) + 80059dc: 4b0c ldr r3, [pc, #48] ; (8005a10 ) + 80059de: f9b3 3000 ldrsh.w r3, [r3] + 80059e2: 4293 cmp r3, r2 + 80059e4: ddea ble.n 80059bc + BSP_LED_On(LED4); + 80059e6: 2000 movs r0, #0 + 80059e8: e7e6 b.n 80059b8 + if (gyro_data.y_ang_rate < ThresholdLow) + 80059ea: 4a09 ldr r2, [pc, #36] ; (8005a10 ) + 80059ec: f9b2 2000 ldrsh.w r2, [r2] + 80059f0: 429a cmp r2, r3 + 80059f2: dd01 ble.n 80059f8 + BSP_LED_On(LED6); + 80059f4: 2003 movs r0, #3 + 80059f6: e7df b.n 80059b8 + else if (gyro_data.y_ang_rate > ThresholdHigh) + 80059f8: 4a04 ldr r2, [pc, #16] ; (8005a0c ) + 80059fa: f9b2 2000 ldrsh.w r2, [r2] + 80059fe: 429a cmp r2, r3 + 8005a00: dadc bge.n 80059bc + BSP_LED_On(LED3); + 8005a02: 2001 movs r0, #1 + 8005a04: e7d8 b.n 80059b8 + 8005a06: bf00 nop + 8005a08: 20004074 .word 0x20004074 + 8005a0c: 20000194 .word 0x20000194 + 8005a10: 20000196 .word 0x20000196 + +08005a14 : + /* USER CODE END 5 */ +} + +/* StartTask02 function */ +void StartTask02(void const * argument) +{ + 8005a14: b508 push {r3, lr} + /* USER CODE BEGIN StartTask02 */ + /* Infinite loop */ + GYRO_Task(); + 8005a16: f7ff ff8b bl 8005930 + ... + +08005a1c : +{ + 8005a1c: b5f0 push {r4, r5, r6, r7, lr} + uint8_t msg_buf[128] = "HelloWorld\n\r"; + 8005a1e: 4b26 ldr r3, [pc, #152] ; (8005ab8 ) +{ + 8005a20: b0ab sub sp, #172 ; 0xac + uint8_t msg_buf[128] = "HelloWorld\n\r"; + 8005a22: aa0a add r2, sp, #40 ; 0x28 + 8005a24: f103 0608 add.w r6, r3, #8 + 8005a28: 4614 mov r4, r2 + 8005a2a: 6818 ldr r0, [r3, #0] + 8005a2c: 6859 ldr r1, [r3, #4] + 8005a2e: 4615 mov r5, r2 + 8005a30: c503 stmia r5!, {r0, r1} + 8005a32: 3308 adds r3, #8 + 8005a34: 42b3 cmp r3, r6 + 8005a36: 462a mov r2, r5 + 8005a38: d1f7 bne.n 8005a2a + 8005a3a: 6818 ldr r0, [r3, #0] + 8005a3c: 791b ldrb r3, [r3, #4] + 8005a3e: 712b strb r3, [r5, #4] + 8005a40: 6028 str r0, [r5, #0] + 8005a42: 2273 movs r2, #115 ; 0x73 + 8005a44: 2100 movs r1, #0 + 8005a46: f10d 0035 add.w r0, sp, #53 ; 0x35 + 8005a4a: f000 fc3e bl 80062ca + osSignalWait(0x1, osWaitForever); //Wait for USB host to configure port + 8005a4e: f04f 32ff mov.w r2, #4294967295 + 8005a52: 2101 movs r1, #1 + 8005a54: a802 add r0, sp, #8 + 8005a56: f7fe f919 bl 8003c8c + osSignalSet(Task02Handle, 0x1); //Set signal in Task 02 + 8005a5a: 4b18 ldr r3, [pc, #96] ; (8005abc ) + osEvent event = osMailGet(myMailQID, osWaitForever); //Get mail + 8005a5c: 4e18 ldr r6, [pc, #96] ; (8005ac0 ) + osSignalSet(Task02Handle, 0x1); //Set signal in Task 02 + 8005a5e: 6818 ldr r0, [r3, #0] + snprintf((char *)msg_buf, 128, "GYR_X: %d, GYR_Y: %d, GYR_Z: %d\n\r", gyro_rx->x_ang_rate, gyro_rx->y_ang_rate, gyro_rx->z_ang_rate); + 8005a60: 4f18 ldr r7, [pc, #96] ; (8005ac4 ) + osSignalSet(Task02Handle, 0x1); //Set signal in Task 02 + 8005a62: 2101 movs r1, #1 + 8005a64: f7fe f8e8 bl 8003c38 + CDC_Transmit_FS(msg_buf, strlen((const char *)msg_buf)); //Send data to USB host + 8005a68: 4620 mov r0, r4 + 8005a6a: f7fa fbb1 bl 80001d0 + 8005a6e: 4601 mov r1, r0 + 8005a70: 4620 mov r0, r4 + 8005a72: f000 f9fb bl 8005e6c + osEvent event = osMailGet(myMailQID, osWaitForever); //Get mail + 8005a76: 6831 ldr r1, [r6, #0] + 8005a78: a807 add r0, sp, #28 + 8005a7a: f04f 32ff mov.w r2, #4294967295 + 8005a7e: f7fe fa05 bl 8003e8c + GYRO_DATA_T *gyro_rx = event.value.p; + 8005a82: 9d08 ldr r5, [sp, #32] + snprintf((char *)msg_buf, 128, "GYR_X: %d, GYR_Y: %d, GYR_Z: %d\n\r", gyro_rx->x_ang_rate, gyro_rx->y_ang_rate, gyro_rx->z_ang_rate); + 8005a84: f9b5 2004 ldrsh.w r2, [r5, #4] + 8005a88: f9b5 3000 ldrsh.w r3, [r5] + 8005a8c: 9201 str r2, [sp, #4] + 8005a8e: f9b5 2002 ldrsh.w r2, [r5, #2] + 8005a92: 9200 str r2, [sp, #0] + 8005a94: 2180 movs r1, #128 ; 0x80 + 8005a96: 463a mov r2, r7 + 8005a98: 4620 mov r0, r4 + 8005a9a: f000 fcdb bl 8006454 + osMailFree(myMailQID, gyro_rx); //Free mail queue memory + 8005a9e: 4629 mov r1, r5 + 8005aa0: 6830 ldr r0, [r6, #0] + 8005aa2: f7fe fa2f bl 8003f04 + CDC_Transmit_FS(msg_buf, strlen((const char *)msg_buf)); + 8005aa6: 4620 mov r0, r4 + 8005aa8: f7fa fb92 bl 80001d0 + 8005aac: 4601 mov r1, r0 + 8005aae: 4620 mov r0, r4 + 8005ab0: f000 f9dc bl 8005e6c + 8005ab4: e7df b.n 8005a76 + 8005ab6: bf00 nop + 8005ab8: 08006b7c .word 0x08006b7c + 8005abc: 20004018 .word 0x20004018 + 8005ac0: 20004074 .word 0x20004074 + 8005ac4: 08006c6d .word 0x08006c6d + +08005ac8 : +{ + 8005ac8: b508 push {r3, lr} + MX_USB_DEVICE_Init(); + 8005aca: f000 f95f bl 8005d8c + USB_Task(); + 8005ace: f7ff ffa5 bl 8005a1c + ... + +08005ad4 : +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM6) { + 8005ad4: 6802 ldr r2, [r0, #0] + 8005ad6: 4b03 ldr r3, [pc, #12] ; (8005ae4 ) + 8005ad8: 429a cmp r2, r3 + 8005ada: d101 bne.n 8005ae0 + HAL_IncTick(); + 8005adc: f7fb b8ec b.w 8000cb8 + 8005ae0: 4770 bx lr + 8005ae2: bf00 nop + 8005ae4: 40001000 .word 0x40001000 + +08005ae8 <_Error_Handler>: + * @param file: The file name as string. + * @param line: The line in file as a number. + * @retval None + */ +void _Error_Handler(char *file, int line) +{ + 8005ae8: e7fe b.n 8005ae8 <_Error_Handler> + ... + +08005aec : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8005aec: b513 push {r0, r1, r4, lr} + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8005aee: 4b22 ldr r3, [pc, #136] ; (8005b78 ) + 8005af0: 2400 movs r4, #0 + 8005af2: 9400 str r4, [sp, #0] + 8005af4: 6c5a ldr r2, [r3, #68] ; 0x44 + 8005af6: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 8005afa: 645a str r2, [r3, #68] ; 0x44 + 8005afc: 6c5a ldr r2, [r3, #68] ; 0x44 + 8005afe: f402 4280 and.w r2, r2, #16384 ; 0x4000 + 8005b02: 9200 str r2, [sp, #0] + 8005b04: 9a00 ldr r2, [sp, #0] + __HAL_RCC_PWR_CLK_ENABLE(); + 8005b06: 9401 str r4, [sp, #4] + 8005b08: 6c1a ldr r2, [r3, #64] ; 0x40 + 8005b0a: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 + 8005b0e: 641a str r2, [r3, #64] ; 0x40 + 8005b10: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005b12: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8005b16: 9301 str r3, [sp, #4] + + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8005b18: 2003 movs r0, #3 + __HAL_RCC_PWR_CLK_ENABLE(); + 8005b1a: 9b01 ldr r3, [sp, #4] + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8005b1c: f7fb f8f2 bl 8000d04 + + /* System interrupt init*/ + /* MemoryManagement_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0); + 8005b20: 4622 mov r2, r4 + 8005b22: 4621 mov r1, r4 + 8005b24: f06f 000b mvn.w r0, #11 + 8005b28: f7fb f8fe bl 8000d28 + /* BusFault_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0); + 8005b2c: 4622 mov r2, r4 + 8005b2e: 4621 mov r1, r4 + 8005b30: f06f 000a mvn.w r0, #10 + 8005b34: f7fb f8f8 bl 8000d28 + /* UsageFault_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0); + 8005b38: 4622 mov r2, r4 + 8005b3a: 4621 mov r1, r4 + 8005b3c: f06f 0009 mvn.w r0, #9 + 8005b40: f7fb f8f2 bl 8000d28 + /* SVCall_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0); + 8005b44: 4622 mov r2, r4 + 8005b46: 4621 mov r1, r4 + 8005b48: f06f 0004 mvn.w r0, #4 + 8005b4c: f7fb f8ec bl 8000d28 + /* DebugMonitor_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0); + 8005b50: 4622 mov r2, r4 + 8005b52: 4621 mov r1, r4 + 8005b54: f06f 0003 mvn.w r0, #3 + 8005b58: f7fb f8e6 bl 8000d28 + /* PendSV_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); + 8005b5c: 4622 mov r2, r4 + 8005b5e: 210f movs r1, #15 + 8005b60: f06f 0001 mvn.w r0, #1 + 8005b64: f7fb f8e0 bl 8000d28 + /* SysTick_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0); + 8005b68: 4622 mov r2, r4 + 8005b6a: 210f movs r1, #15 + 8005b6c: f04f 30ff mov.w r0, #4294967295 + 8005b70: f7fb f8da bl 8000d28 + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8005b74: b002 add sp, #8 + 8005b76: bd10 pop {r4, pc} + 8005b78: 40023800 .word 0x40023800 + +08005b7c : + +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + 8005b7c: b57f push {r0, r1, r2, r3, r4, r5, r6, lr} + + GPIO_InitTypeDef GPIO_InitStruct; + if(hi2c->Instance==I2C1) + 8005b7e: 6802 ldr r2, [r0, #0] + 8005b80: 4b10 ldr r3, [pc, #64] ; (8005bc4 ) + 8005b82: 429a cmp r2, r3 + 8005b84: d11b bne.n 8005bbe + + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB9 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_9; + 8005b86: f44f 7310 mov.w r3, #576 ; 0x240 + 8005b8a: 9301 str r3, [sp, #4] + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 8005b8c: 2312 movs r3, #18 + 8005b8e: 9302 str r3, [sp, #8] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 8005b90: 2301 movs r3, #1 + 8005b92: 9303 str r3, [sp, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8005b94: 2303 movs r3, #3 + 8005b96: 9304 str r3, [sp, #16] + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 8005b98: 2304 movs r3, #4 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8005b9a: eb0d 0103 add.w r1, sp, r3 + 8005b9e: 480a ldr r0, [pc, #40] ; (8005bc8 ) + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 8005ba0: 9305 str r3, [sp, #20] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8005ba2: f7fb f923 bl 8000dec + + /* Peripheral clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + 8005ba6: 2300 movs r3, #0 + 8005ba8: 9300 str r3, [sp, #0] + 8005baa: 4b08 ldr r3, [pc, #32] ; (8005bcc ) + 8005bac: 6c1a ldr r2, [r3, #64] ; 0x40 + 8005bae: f442 1200 orr.w r2, r2, #2097152 ; 0x200000 + 8005bb2: 641a str r2, [r3, #64] ; 0x40 + 8005bb4: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005bb6: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8005bba: 9300 str r3, [sp, #0] + 8005bbc: 9b00 ldr r3, [sp, #0] + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } + +} + 8005bbe: b007 add sp, #28 + 8005bc0: f85d fb04 ldr.w pc, [sp], #4 + 8005bc4: 40005400 .word 0x40005400 + 8005bc8: 40020400 .word 0x40020400 + 8005bcc: 40023800 .word 0x40023800 + +08005bd0 : + } + +} + +void HAL_I2S_MspInit(I2S_HandleTypeDef* hi2s) +{ + 8005bd0: b570 push {r4, r5, r6, lr} + + GPIO_InitTypeDef GPIO_InitStruct; + if(hi2s->Instance==SPI3) + 8005bd2: 6802 ldr r2, [r0, #0] + 8005bd4: 4b14 ldr r3, [pc, #80] ; (8005c28 ) + 8005bd6: 429a cmp r2, r3 +{ + 8005bd8: b086 sub sp, #24 + if(hi2s->Instance==SPI3) + 8005bda: d123 bne.n 8005c24 + { + /* USER CODE BEGIN SPI3_MspInit 0 */ + + /* USER CODE END SPI3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI3_CLK_ENABLE(); + 8005bdc: 2400 movs r4, #0 + 8005bde: f503 33fe add.w r3, r3, #130048 ; 0x1fc00 + 8005be2: 9400 str r4, [sp, #0] + 8005be4: 6c1a ldr r2, [r3, #64] ; 0x40 + GPIO_InitStruct.Pin = GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8005be6: 4811 ldr r0, [pc, #68] ; (8005c2c ) + __HAL_RCC_SPI3_CLK_ENABLE(); + 8005be8: f442 4200 orr.w r2, r2, #32768 ; 0x8000 + 8005bec: 641a str r2, [r3, #64] ; 0x40 + 8005bee: 6c1b ldr r3, [r3, #64] ; 0x40 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8005bf0: 9403 str r4, [sp, #12] + __HAL_RCC_SPI3_CLK_ENABLE(); + 8005bf2: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8005bf6: 9300 str r3, [sp, #0] + 8005bf8: 9b00 ldr r3, [sp, #0] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8005bfa: 9404 str r4, [sp, #16] + GPIO_InitStruct.Pin = GPIO_PIN_4; + 8005bfc: 2310 movs r3, #16 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8005bfe: 2602 movs r6, #2 + GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; + 8005c00: 2506 movs r5, #6 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8005c02: a901 add r1, sp, #4 + GPIO_InitStruct.Pin = GPIO_PIN_4; + 8005c04: 9301 str r3, [sp, #4] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8005c06: 9602 str r6, [sp, #8] + GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; + 8005c08: 9505 str r5, [sp, #20] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8005c0a: f7fb f8ef bl 8000dec + + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_12; + 8005c0e: f44f 53a4 mov.w r3, #5248 ; 0x1480 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8005c12: a901 add r1, sp, #4 + 8005c14: 4806 ldr r0, [pc, #24] ; (8005c30 ) + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_12; + 8005c16: 9301 str r3, [sp, #4] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8005c18: 9602 str r6, [sp, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8005c1a: 9403 str r4, [sp, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8005c1c: 9404 str r4, [sp, #16] + GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; + 8005c1e: 9505 str r5, [sp, #20] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8005c20: f7fb f8e4 bl 8000dec + /* USER CODE BEGIN SPI3_MspInit 1 */ + + /* USER CODE END SPI3_MspInit 1 */ + } + +} + 8005c24: b006 add sp, #24 + 8005c26: bd70 pop {r4, r5, r6, pc} + 8005c28: 40003c00 .word 0x40003c00 + 8005c2c: 40020000 .word 0x40020000 + 8005c30: 40020800 .word 0x40020800 + +08005c34 : + } + +} + +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 8005c34: b57f push {r0, r1, r2, r3, r4, r5, r6, lr} + + GPIO_InitTypeDef GPIO_InitStruct; + if(hspi->Instance==SPI1) + 8005c36: 6802 ldr r2, [r0, #0] + 8005c38: 4b0f ldr r3, [pc, #60] ; (8005c78 ) + 8005c3a: 429a cmp r2, r3 + 8005c3c: d119 bne.n 8005c72 + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + 8005c3e: 2100 movs r1, #0 + 8005c40: f503 3384 add.w r3, r3, #67584 ; 0x10800 + 8005c44: 9100 str r1, [sp, #0] + 8005c46: 6c5a ldr r2, [r3, #68] ; 0x44 + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8005c48: 480c ldr r0, [pc, #48] ; (8005c7c ) + __HAL_RCC_SPI1_CLK_ENABLE(); + 8005c4a: f442 5280 orr.w r2, r2, #4096 ; 0x1000 + 8005c4e: 645a str r2, [r3, #68] ; 0x44 + 8005c50: 6c5b ldr r3, [r3, #68] ; 0x44 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8005c52: 9103 str r1, [sp, #12] + __HAL_RCC_SPI1_CLK_ENABLE(); + 8005c54: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8005c58: 9300 str r3, [sp, #0] + 8005c5a: 9b00 ldr r3, [sp, #0] + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 8005c5c: 23e0 movs r3, #224 ; 0xe0 + 8005c5e: 9301 str r3, [sp, #4] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8005c60: 2302 movs r3, #2 + 8005c62: 9302 str r3, [sp, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8005c64: 2303 movs r3, #3 + 8005c66: 9304 str r3, [sp, #16] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8005c68: a901 add r1, sp, #4 + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 8005c6a: 2305 movs r3, #5 + 8005c6c: 9305 str r3, [sp, #20] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8005c6e: f7fb f8bd bl 8000dec + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + +} + 8005c72: b007 add sp, #28 + 8005c74: f85d fb04 ldr.w pc, [sp], #4 + 8005c78: 40013000 .word 0x40013000 + 8005c7c: 40020000 .word 0x40020000 + +08005c80 : + +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + + if(hspi->Instance==SPI1) + 8005c80: 6802 ldr r2, [r0, #0] + 8005c82: 4b06 ldr r3, [pc, #24] ; (8005c9c ) + 8005c84: 429a cmp r2, r3 + 8005c86: d108 bne.n 8005c9a + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + 8005c88: 4a05 ldr r2, [pc, #20] ; (8005ca0 ) + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + 8005c8a: 4806 ldr r0, [pc, #24] ; (8005ca4 ) + __HAL_RCC_SPI1_CLK_DISABLE(); + 8005c8c: 6c53 ldr r3, [r2, #68] ; 0x44 + 8005c8e: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 8005c92: 6453 str r3, [r2, #68] ; 0x44 + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + 8005c94: 21e0 movs r1, #224 ; 0xe0 + 8005c96: f7fb b989 b.w 8000fac + 8005c9a: 4770 bx lr + 8005c9c: 40013000 .word 0x40013000 + 8005ca0: 40023800 .word 0x40023800 + 8005ca4: 40020000 .word 0x40020000 + +08005ca8 : + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priorty. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8005ca8: b530 push {r4, r5, lr} + uint32_t uwTimclock = 0; + uint32_t uwPrescalerValue = 0; + uint32_t pFLatency; + + /*Configure the TIM6 IRQ priority */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0); + 8005caa: 4601 mov r1, r0 +{ + 8005cac: b089 sub sp, #36 ; 0x24 + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0); + 8005cae: 2200 movs r2, #0 + 8005cb0: 2036 movs r0, #54 ; 0x36 + 8005cb2: f7fb f839 bl 8000d28 + + /* Enable the TIM6 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + 8005cb6: 2036 movs r0, #54 ; 0x36 + 8005cb8: f7fb f86a bl 8000d90 + + /* Enable TIM6 clock */ + __HAL_RCC_TIM6_CLK_ENABLE(); + 8005cbc: 2500 movs r5, #0 + 8005cbe: 4b15 ldr r3, [pc, #84] ; (8005d14 ) + 8005cc0: 9502 str r5, [sp, #8] + 8005cc2: 6c1a ldr r2, [r3, #64] ; 0x40 + + /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1); + + /* Initialize TIM6 */ + htim6.Instance = TIM6; + 8005cc4: 4c14 ldr r4, [pc, #80] ; (8005d18 ) + __HAL_RCC_TIM6_CLK_ENABLE(); + 8005cc6: f042 0210 orr.w r2, r2, #16 + 8005cca: 641a str r2, [r3, #64] ; 0x40 + 8005ccc: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005cce: f003 0310 and.w r3, r3, #16 + 8005cd2: 9302 str r3, [sp, #8] + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + 8005cd4: a901 add r1, sp, #4 + 8005cd6: a803 add r0, sp, #12 + __HAL_RCC_TIM6_CLK_ENABLE(); + 8005cd8: 9b02 ldr r3, [sp, #8] + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + 8005cda: f7fc fb6d bl 80023b8 + uwTimclock = 2*HAL_RCC_GetPCLK1Freq(); + 8005cde: f7fc fb5b bl 8002398 + htim6.Instance = TIM6; + 8005ce2: 4b0e ldr r3, [pc, #56] ; (8005d1c ) + 8005ce4: 6023 str r3, [r4, #0] + + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + + ClockDivision = 0 + + Counter direction = Up + */ + htim6.Init.Period = (1000000 / 1000) - 1; + 8005ce6: f240 33e7 movw r3, #999 ; 0x3e7 + 8005cea: 60e3 str r3, [r4, #12] + uwTimclock = 2*HAL_RCC_GetPCLK1Freq(); + 8005cec: 0040 lsls r0, r0, #1 + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1); + 8005cee: 4b0c ldr r3, [pc, #48] ; (8005d20 ) + 8005cf0: fbb0 f0f3 udiv r0, r0, r3 + 8005cf4: 3801 subs r0, #1 + htim6.Init.Prescaler = uwPrescalerValue; + 8005cf6: 6060 str r0, [r4, #4] + htim6.Init.ClockDivision = 0; + htim6.Init.CounterMode = TIM_COUNTERMODE_UP; + if(HAL_TIM_Base_Init(&htim6) == HAL_OK) + 8005cf8: 4620 mov r0, r4 + htim6.Init.ClockDivision = 0; + 8005cfa: 6125 str r5, [r4, #16] + htim6.Init.CounterMode = TIM_COUNTERMODE_UP; + 8005cfc: 60a5 str r5, [r4, #8] + if(HAL_TIM_Base_Init(&htim6) == HAL_OK) + 8005cfe: f7fc feff bl 8002b00 + 8005d02: b920 cbnz r0, 8005d0e + { + /* Start the TIM time Base generation in interrupt mode */ + return HAL_TIM_Base_Start_IT(&htim6); + 8005d04: 4620 mov r0, r4 + 8005d06: f7fc fde5 bl 80028d4 + } + + /* Return function status */ + return HAL_ERROR; +} + 8005d0a: b009 add sp, #36 ; 0x24 + 8005d0c: bd30 pop {r4, r5, pc} + return HAL_ERROR; + 8005d0e: 2001 movs r0, #1 + 8005d10: e7fb b.n 8005d0a + 8005d12: bf00 nop + 8005d14: 40023800 .word 0x40023800 + 8005d18: 20004118 .word 0x20004118 + 8005d1c: 40001000 .word 0x40001000 + 8005d20: 000f4240 .word 0x000f4240 + +08005d24 : +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + osSystickHandler(); + 8005d24: f7fe b8f4 b.w 8003f10 + +08005d28 : +void TIM6_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ + + /* USER CODE END TIM6_DAC_IRQn 0 */ + HAL_TIM_IRQHandler(&htim6); + 8005d28: 4801 ldr r0, [pc, #4] ; (8005d30 ) + 8005d2a: f7fc bde2 b.w 80028f2 + 8005d2e: bf00 nop + 8005d30: 20004118 .word 0x20004118 + +08005d34 : +void OTG_FS_IRQHandler(void) +{ + /* USER CODE BEGIN OTG_FS_IRQn 0 */ + + /* USER CODE END OTG_FS_IRQn 0 */ + HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); + 8005d34: 4801 ldr r0, [pc, #4] ; (8005d3c ) + 8005d36: f7fb bd0d b.w 8001754 + 8005d3a: bf00 nop + 8005d3c: 20004400 .word 0x20004400 + +08005d40 : + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + 8005d40: 490f ldr r1, [pc, #60] ; (8005d80 ) + 8005d42: f8d1 3088 ldr.w r3, [r1, #136] ; 0x88 + 8005d46: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 8005d4a: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + 8005d4e: 4b0d ldr r3, [pc, #52] ; (8005d84 ) + 8005d50: 681a ldr r2, [r3, #0] + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + 8005d52: 2000 movs r0, #0 + RCC->CR |= (uint32_t)0x00000001; + 8005d54: f042 0201 orr.w r2, r2, #1 + 8005d58: 601a str r2, [r3, #0] + RCC->CFGR = 0x00000000; + 8005d5a: 6098 str r0, [r3, #8] + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + 8005d5c: 681a ldr r2, [r3, #0] + 8005d5e: f022 7284 bic.w r2, r2, #17301504 ; 0x1080000 + 8005d62: f422 3280 bic.w r2, r2, #65536 ; 0x10000 + 8005d66: 601a str r2, [r3, #0] + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + 8005d68: 4a07 ldr r2, [pc, #28] ; (8005d88 ) + 8005d6a: 605a str r2, [r3, #4] + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + 8005d6c: 681a ldr r2, [r3, #0] + 8005d6e: f422 2280 bic.w r2, r2, #262144 ; 0x40000 + 8005d72: 601a str r2, [r3, #0] + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + 8005d74: 60d8 str r0, [r3, #12] + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + 8005d76: f04f 6300 mov.w r3, #134217728 ; 0x8000000 + 8005d7a: 608b str r3, [r1, #8] + 8005d7c: 4770 bx lr + 8005d7e: bf00 nop + 8005d80: e000ed00 .word 0xe000ed00 + 8005d84: 40023800 .word 0x40023800 + 8005d88: 24003010 .word 0x24003010 + +08005d8c : +/** + * Init USB device Library, add supported class and start the library + * @retval None + */ +void MX_USB_DEVICE_Init(void) +{ + 8005d8c: b510 push {r4, lr} + /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ + + /* USER CODE END USB_DEVICE_Init_PreTreatment */ + + /* Init Device Library, add supported class and start the library. */ + USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS); + 8005d8e: 4c09 ldr r4, [pc, #36] ; (8005db4 ) + 8005d90: 4909 ldr r1, [pc, #36] ; (8005db8 ) + 8005d92: 2200 movs r2, #0 + 8005d94: 4620 mov r0, r4 + 8005d96: f7fd fc09 bl 80035ac + + USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC); + 8005d9a: 4908 ldr r1, [pc, #32] ; (8005dbc ) + 8005d9c: 4620 mov r0, r4 + 8005d9e: f7fd fc1a bl 80035d6 + + USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS); + 8005da2: 4620 mov r0, r4 + 8005da4: 4906 ldr r1, [pc, #24] ; (8005dc0 ) + 8005da6: f7fd fbc2 bl 800352e + + USBD_Start(&hUsbDeviceFS); + 8005daa: 4620 mov r0, r4 + + /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ + + /* USER CODE END USB_DEVICE_Init_PostTreatment */ +} + 8005dac: e8bd 4010 ldmia.w sp!, {r4, lr} + USBD_Start(&hUsbDeviceFS); + 8005db0: f7fd bc18 b.w 80035e4 + 8005db4: 20004154 .word 0x20004154 + 8005db8: 200001ac .word 0x200001ac + 8005dbc: 20000080 .word 0x20000080 + 8005dc0: 2000019c .word 0x2000019c + +08005dc4 : +static int8_t CDC_DeInit_FS(void) +{ + /* USER CODE BEGIN 4 */ + return (USBD_OK); + /* USER CODE END 4 */ +} + 8005dc4: 2000 movs r0, #0 + 8005dc6: 4770 bx lr + +08005dc8 : + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) +{ + 8005dc8: b510 push {r4, lr} + /* USER CODE BEGIN 6 */ + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); + 8005dca: 4c05 ldr r4, [pc, #20] ; (8005de0 ) + 8005dcc: 4601 mov r1, r0 + 8005dce: 4620 mov r0, r4 + 8005dd0: f7fd fbbc bl 800354c + USBD_CDC_ReceivePacket(&hUsbDeviceFS); + 8005dd4: 4620 mov r0, r4 + 8005dd6: f7fd fbd6 bl 8003586 + return (USBD_OK); + /* USER CODE END 6 */ +} + 8005dda: 2000 movs r0, #0 + 8005ddc: bd10 pop {r4, pc} + 8005dde: bf00 nop + 8005de0: 20004154 .word 0x20004154 + +08005de4 : +{ + 8005de4: b510 push {r4, lr} + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); + 8005de6: 4c06 ldr r4, [pc, #24] ; (8005e00 ) + 8005de8: 4906 ldr r1, [pc, #24] ; (8005e04 ) + 8005dea: 2200 movs r2, #0 + 8005dec: 4620 mov r0, r4 + 8005dee: f7fd fba5 bl 800353c + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); + 8005df2: 4905 ldr r1, [pc, #20] ; (8005e08 ) + 8005df4: 4620 mov r0, r4 + 8005df6: f7fd fba9 bl 800354c +} + 8005dfa: 2000 movs r0, #0 + 8005dfc: bd10 pop {r4, pc} + 8005dfe: bf00 nop + 8005e00: 20004154 .word 0x20004154 + 8005e04: 200043b8 .word 0x200043b8 + 8005e08: 20004378 .word 0x20004378 + +08005e0c : + switch(cmd) + 8005e0c: 2820 cmp r0, #32 +{ + 8005e0e: b508 push {r3, lr} + switch(cmd) + 8005e10: d003 beq.n 8005e1a + 8005e12: 2821 cmp r0, #33 ; 0x21 + 8005e14: d016 beq.n 8005e44 +} + 8005e16: 2000 movs r0, #0 + 8005e18: bd08 pop {r3, pc} + TempBuf_USB[0]=pbuf[0]; + 8005e1a: 4b12 ldr r3, [pc, #72] ; (8005e64 ) + 8005e1c: 780a ldrb r2, [r1, #0] + 8005e1e: 701a strb r2, [r3, #0] + TempBuf_USB[1]=pbuf[1]; + 8005e20: 784a ldrb r2, [r1, #1] + 8005e22: 705a strb r2, [r3, #1] + TempBuf_USB[2]=pbuf[2]; + 8005e24: 788a ldrb r2, [r1, #2] + 8005e26: 709a strb r2, [r3, #2] + TempBuf_USB[3]=pbuf[3]; + 8005e28: 78ca ldrb r2, [r1, #3] + 8005e2a: 70da strb r2, [r3, #3] + TempBuf_USB[4]=pbuf[4]; + 8005e2c: 790a ldrb r2, [r1, #4] + 8005e2e: 711a strb r2, [r3, #4] + TempBuf_USB[5]=pbuf[5]; + 8005e30: 794a ldrb r2, [r1, #5] + 8005e32: 715a strb r2, [r3, #5] + TempBuf_USB[6]=pbuf[6]; + 8005e34: 798a ldrb r2, [r1, #6] + 8005e36: 719a strb r2, [r3, #6] + osSignalSet(Task01Handle, 0x1);//Signal Task 1 to start execution + 8005e38: 4b0b ldr r3, [pc, #44] ; (8005e68 ) + 8005e3a: 2101 movs r1, #1 + 8005e3c: 6818 ldr r0, [r3, #0] + 8005e3e: f7fd fefb bl 8003c38 + 8005e42: e7e8 b.n 8005e16 + pbuf[0]=TempBuf_USB[0]; + 8005e44: 4b07 ldr r3, [pc, #28] ; (8005e64 ) + 8005e46: 781a ldrb r2, [r3, #0] + 8005e48: 700a strb r2, [r1, #0] + pbuf[1]=TempBuf_USB[1]; + 8005e4a: 785a ldrb r2, [r3, #1] + 8005e4c: 704a strb r2, [r1, #1] + pbuf[2]=TempBuf_USB[2]; + 8005e4e: 789a ldrb r2, [r3, #2] + 8005e50: 708a strb r2, [r1, #2] + pbuf[3]=TempBuf_USB[3]; + 8005e52: 78da ldrb r2, [r3, #3] + 8005e54: 70ca strb r2, [r1, #3] + pbuf[4]=TempBuf_USB[4]; + 8005e56: 791a ldrb r2, [r3, #4] + 8005e58: 710a strb r2, [r1, #4] + pbuf[5]=TempBuf_USB[5]; + 8005e5a: 795a ldrb r2, [r3, #5] + 8005e5c: 714a strb r2, [r1, #5] + pbuf[6]=TempBuf_USB[6]; + 8005e5e: 799b ldrb r3, [r3, #6] + 8005e60: 718b strb r3, [r1, #6] + break; + 8005e62: e7d8 b.n 8005e16 + 8005e64: 200043f8 .word 0x200043f8 + 8005e68: 20004070 .word 0x20004070 + +08005e6c : + * @param Buf: Buffer of data to be sent + * @param Len: Number of data to be sent (in bytes) + * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY + */ +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) +{ + 8005e6c: b510 push {r4, lr} + uint8_t result = USBD_OK; + /* USER CODE BEGIN 7 */ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData; + 8005e6e: 4c09 ldr r4, [pc, #36] ; (8005e94 ) + 8005e70: f8d4 3218 ldr.w r3, [r4, #536] ; 0x218 + if (hcdc->TxState != 0){ + 8005e74: f8d3 3214 ldr.w r3, [r3, #532] ; 0x214 +{ + 8005e78: 460a mov r2, r1 + if (hcdc->TxState != 0){ + 8005e7a: b943 cbnz r3, 8005e8e + return USBD_BUSY; + } + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len); + 8005e7c: 4601 mov r1, r0 + 8005e7e: 4620 mov r0, r4 + 8005e80: f7fd fb5c bl 800353c + result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); + 8005e84: 4620 mov r0, r4 + /* USER CODE END 7 */ + return result; +} + 8005e86: e8bd 4010 ldmia.w sp!, {r4, lr} + result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); + 8005e8a: f7fd bb65 b.w 8003558 +} + 8005e8e: 2001 movs r0, #1 + 8005e90: bd10 pop {r4, pc} + 8005e92: bf00 nop + 8005e94: 20004154 .word 0x20004154 + +08005e98 : + LL Driver Callbacks (PCD -> USB Device Library) +*******************************************************************************/ +/* MSP Init */ + +void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) +{ + 8005e98: b570 push {r4, r5, r6, lr} + GPIO_InitTypeDef GPIO_InitStruct; + if(pcdHandle->Instance==USB_OTG_FS) + 8005e9a: 6803 ldr r3, [r0, #0] + 8005e9c: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 +{ + 8005ea0: b086 sub sp, #24 + if(pcdHandle->Instance==USB_OTG_FS) + 8005ea2: d139 bne.n 8005f18 + PA10 ------> USB_OTG_FS_ID + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + GPIO_InitStruct.Pin = GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8005ea4: 2400 movs r4, #0 + GPIO_InitStruct.Pin = GPIO_PIN_9; + 8005ea6: f44f 7300 mov.w r3, #512 ; 0x200 + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8005eaa: a901 add r1, sp, #4 + 8005eac: 481b ldr r0, [pc, #108] ; (8005f1c ) + GPIO_InitStruct.Pin = GPIO_PIN_9; + 8005eae: 9301 str r3, [sp, #4] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8005eb0: 9402 str r4, [sp, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8005eb2: 9403 str r4, [sp, #12] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8005eb4: f7fa ff9a bl 8000dec + + GPIO_InitStruct.Pin = GPIO_PIN_10; + 8005eb8: f44f 6380 mov.w r3, #1024 ; 0x400 + 8005ebc: 9301 str r3, [sp, #4] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8005ebe: 2602 movs r6, #2 + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8005ec0: 2303 movs r3, #3 + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + 8005ec2: 250a movs r5, #10 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8005ec4: a901 add r1, sp, #4 + 8005ec6: 4815 ldr r0, [pc, #84] ; (8005f1c ) + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8005ec8: 9304 str r3, [sp, #16] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8005eca: 9602 str r6, [sp, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8005ecc: 9403 str r4, [sp, #12] + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + 8005ece: 9505 str r5, [sp, #20] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8005ed0: f7fa ff8c bl 8000dec + + GPIO_InitStruct.Pin = OTG_FS_DM_Pin|OTG_FS_DP_Pin; + 8005ed4: f44f 53c0 mov.w r3, #6144 ; 0x1800 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8005ed8: a901 add r1, sp, #4 + 8005eda: 4810 ldr r0, [pc, #64] ; (8005f1c ) + GPIO_InitStruct.Pin = OTG_FS_DM_Pin|OTG_FS_DP_Pin; + 8005edc: 9301 str r3, [sp, #4] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8005ede: 9602 str r6, [sp, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8005ee0: 9403 str r4, [sp, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8005ee2: 9404 str r4, [sp, #16] + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + 8005ee4: 9505 str r5, [sp, #20] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8005ee6: f7fa ff81 bl 8000dec + + /* Peripheral clock enable */ + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + 8005eea: 4b0d ldr r3, [pc, #52] ; (8005f20 ) + 8005eec: 6b5a ldr r2, [r3, #52] ; 0x34 + 8005eee: f042 0280 orr.w r2, r2, #128 ; 0x80 + 8005ef2: 635a str r2, [r3, #52] ; 0x34 + 8005ef4: 9400 str r4, [sp, #0] + 8005ef6: 6c5a ldr r2, [r3, #68] ; 0x44 + 8005ef8: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 8005efc: 645a str r2, [r3, #68] ; 0x44 + 8005efe: 6c5b ldr r3, [r3, #68] ; 0x44 + 8005f00: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8005f04: 9300 str r3, [sp, #0] + + /* Peripheral interrupt init */ + HAL_NVIC_SetPriority(OTG_FS_IRQn, 5, 0); + 8005f06: 2043 movs r0, #67 ; 0x43 + 8005f08: 4622 mov r2, r4 + 8005f0a: 2105 movs r1, #5 + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + 8005f0c: 9b00 ldr r3, [sp, #0] + HAL_NVIC_SetPriority(OTG_FS_IRQn, 5, 0); + 8005f0e: f7fa ff0b bl 8000d28 + HAL_NVIC_EnableIRQ(OTG_FS_IRQn); + 8005f12: 2043 movs r0, #67 ; 0x43 + 8005f14: f7fa ff3c bl 8000d90 + /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ + + /* USER CODE END USB_OTG_FS_MspInit 1 */ + } +} + 8005f18: b006 add sp, #24 + 8005f1a: bd70 pop {r4, r5, r6, pc} + 8005f1c: 40020000 .word 0x40020000 + 8005f20: 40023800 .word 0x40023800 + +08005f24 : + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); + 8005f24: f500 716f add.w r1, r0, #956 ; 0x3bc + 8005f28: f8d0 03ec ldr.w r0, [r0, #1004] ; 0x3ec + 8005f2c: f7fd bb71 b.w 8003612 + +08005f30 : + * @param epnum: Endpoint number + * @retval None + */ +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); + 8005f30: 231c movs r3, #28 + 8005f32: fb03 0301 mla r3, r3, r1, r0 + 8005f36: f8d0 03ec ldr.w r0, [r0, #1004] ; 0x3ec + 8005f3a: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 + 8005f3e: f7fd bb95 b.w 800366c + +08005f42 : + * @param epnum: Endpoint number + * @retval None + */ +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); + 8005f42: 231c movs r3, #28 + 8005f44: fb03 0301 mla r3, r3, r1, r0 + 8005f48: f8d0 03ec ldr.w r0, [r0, #1004] ; 0x3ec + 8005f4c: 6c5a ldr r2, [r3, #68] ; 0x44 + 8005f4e: f7fd bbbf b.w 80036d0 + +08005f52 : + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); + 8005f52: f8d0 03ec ldr.w r0, [r0, #1004] ; 0x3ec + 8005f56: f7fd bc3b b.w 80037d0 + +08005f5a : + * @brief Reset callback. + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + 8005f5a: b510 push {r4, lr} + USBD_SpeedTypeDef speed = USBD_SPEED_FULL; + + /* Set USB current speed. */ + switch (hpcd->Init.speed) + 8005f5c: 68c1 ldr r1, [r0, #12] +{ + 8005f5e: 4604 mov r4, r0 + + default: + speed = USBD_SPEED_FULL; + break; + } + USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); + 8005f60: 3100 adds r1, #0 + 8005f62: bf18 it ne + 8005f64: 2101 movne r1, #1 + 8005f66: f8d0 03ec ldr.w r0, [r0, #1004] ; 0x3ec + 8005f6a: f7fd fc1f bl 80037ac + + /* Reset Device. */ + USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); + 8005f6e: f8d4 03ec ldr.w r0, [r4, #1004] ; 0x3ec +} + 8005f72: e8bd 4010 ldmia.w sp!, {r4, lr} + USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); + 8005f76: f7fd bbfa b.w 800376e + ... + +08005f7c : + * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +{ + 8005f7c: b510 push {r4, lr} + 8005f7e: 4604 mov r4, r0 + /* Inform USB library that core enters in suspend Mode. */ + USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); + 8005f80: f8d0 03ec ldr.w r0, [r0, #1004] ; 0x3ec + 8005f84: f7fd fc15 bl 80037b2 + __HAL_PCD_GATE_PHYCLOCK(hpcd); + 8005f88: 6822 ldr r2, [r4, #0] + 8005f8a: f8d2 3e00 ldr.w r3, [r2, #3584] ; 0xe00 + 8005f8e: f043 0301 orr.w r3, r3, #1 + 8005f92: f8c2 3e00 str.w r3, [r2, #3584] ; 0xe00 + /* Enter in STOP mode. */ + /* USER CODE BEGIN 2 */ + if (hpcd->Init.low_power_enable) + 8005f96: 6a23 ldr r3, [r4, #32] + 8005f98: b123 cbz r3, 8005fa4 + { + /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ + SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + 8005f9a: 4a03 ldr r2, [pc, #12] ; (8005fa8 ) + 8005f9c: 6913 ldr r3, [r2, #16] + 8005f9e: f043 0306 orr.w r3, r3, #6 + 8005fa2: 6113 str r3, [r2, #16] + 8005fa4: bd10 pop {r4, pc} + 8005fa6: bf00 nop + 8005fa8: e000ed00 .word 0xe000ed00 + +08005fac : +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +{ + /* USER CODE BEGIN 3 */ + + /* USER CODE END 3 */ + USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); + 8005fac: f8d0 03ec ldr.w r0, [r0, #1004] ; 0x3ec + 8005fb0: f7fd bc08 b.w 80037c4 + +08005fb4 : + * @param epnum: Endpoint number + * @retval None + */ +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); + 8005fb4: f8d0 03ec ldr.w r0, [r0, #1004] ; 0x3ec + 8005fb8: f7fd bc18 b.w 80037ec + +08005fbc : + * @param epnum: Endpoint number + * @retval None + */ +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); + 8005fbc: f8d0 03ec ldr.w r0, [r0, #1004] ; 0x3ec + 8005fc0: f7fd bc12 b.w 80037e8 + +08005fc4 : + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); + 8005fc4: f8d0 03ec ldr.w r0, [r0, #1004] ; 0x3ec + 8005fc8: f7fd bc12 b.w 80037f0 + +08005fcc : + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); + 8005fcc: f8d0 03ec ldr.w r0, [r0, #1004] ; 0x3ec + 8005fd0: f7fd bc10 b.w 80037f4 + +08005fd4 : + * @brief Initializes the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) +{ + 8005fd4: b508 push {r3, lr} + /* Init USB Ip. */ + if (pdev->id == DEVICE_FS) { + 8005fd6: 7802 ldrb r2, [r0, #0] + 8005fd8: bb52 cbnz r2, 8006030 + /* Link the driver to the stack. */ + hpcd_USB_OTG_FS.pData = pdev; + 8005fda: 4b16 ldr r3, [pc, #88] ; (8006034 ) + pdev->pData = &hpcd_USB_OTG_FS; + + hpcd_USB_OTG_FS.Instance = USB_OTG_FS; + hpcd_USB_OTG_FS.Init.dev_endpoints = 4; + 8005fdc: 2104 movs r1, #4 + hpcd_USB_OTG_FS.pData = pdev; + 8005fde: f8c3 03ec str.w r0, [r3, #1004] ; 0x3ec + pdev->pData = &hpcd_USB_OTG_FS; + 8005fe2: f8c0 3220 str.w r3, [r0, #544] ; 0x220 + hpcd_USB_OTG_FS.Init.dev_endpoints = 4; + 8005fe6: f04f 40a0 mov.w r0, #1342177280 ; 0x50000000 + 8005fea: e883 0003 stmia.w r3, {r0, r1} + hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; + 8005fee: 2102 movs r1, #2 + hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; + hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; + hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; + hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; + hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; + if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) + 8005ff0: 4618 mov r0, r3 + hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; + 8005ff2: 60d9 str r1, [r3, #12] + hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; + 8005ff4: 611a str r2, [r3, #16] + hpcd_USB_OTG_FS.Init.ep0_mps = DEP0CTL_MPS_64; + 8005ff6: 615a str r2, [r3, #20] + hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; + 8005ff8: 6199 str r1, [r3, #24] + hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; + 8005ffa: 61da str r2, [r3, #28] + hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; + 8005ffc: 621a str r2, [r3, #32] + hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; + 8005ffe: 625a str r2, [r3, #36] ; 0x24 + hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; + 8006000: 62da str r2, [r3, #44] ; 0x2c + hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; + 8006002: 631a str r2, [r3, #48] ; 0x30 + if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) + 8006004: f7fb fb24 bl 8001650 + 8006008: b120 cbz r0, 8006014 + { + _Error_Handler(__FILE__, __LINE__); + 800600a: f44f 71ad mov.w r1, #346 ; 0x15a + 800600e: 480a ldr r0, [pc, #40] ; (8006038 ) + 8006010: f7ff fd6a bl 8005ae8 <_Error_Handler> + } + + HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); + 8006014: 2180 movs r1, #128 ; 0x80 + 8006016: 4807 ldr r0, [pc, #28] ; (8006034 ) + 8006018: f7fb ff69 bl 8001eee + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); + 800601c: 2240 movs r2, #64 ; 0x40 + 800601e: 2100 movs r1, #0 + 8006020: 4804 ldr r0, [pc, #16] ; (8006034 ) + 8006022: f7fb ff43 bl 8001eac + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); + 8006026: 2280 movs r2, #128 ; 0x80 + 8006028: 2101 movs r1, #1 + 800602a: 4802 ldr r0, [pc, #8] ; (8006034 ) + 800602c: f7fb ff3e bl 8001eac + } + return USBD_OK; +} + 8006030: 2000 movs r0, #0 + 8006032: bd08 pop {r3, pc} + 8006034: 20004400 .word 0x20004400 + 8006038: 08006cb9 .word 0x08006cb9 + +0800603c : + * @brief Starts the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) +{ + 800603c: b508 push {r3, lr} + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_Start(pdev->pData); + 800603e: f8d0 0220 ldr.w r0, [r0, #544] ; 0x220 + 8006042: f7fb fb71 bl 8001728 + 8006046: 2803 cmp r0, #3 + 8006048: bf9a itte ls + 800604a: 4b02 ldrls r3, [pc, #8] ; (8006054 ) + 800604c: 5c18 ldrbls r0, [r3, r0] + 800604e: 2002 movhi r0, #2 + default : + usb_status = USBD_FAIL; + break; + } + return usb_status; +} + 8006050: bd08 pop {r3, pc} + 8006052: bf00 nop + 8006054: 08006cb5 .word 0x08006cb5 + +08006058 : + * @param ep_type: Endpoint type + * @param ep_mps: Endpoint max packet size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) +{ + 8006058: b510 push {r4, lr} + 800605a: 461c mov r4, r3 + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); + 800605c: f8d0 0220 ldr.w r0, [r0, #544] ; 0x220 + 8006060: 4613 mov r3, r2 + 8006062: 4622 mov r2, r4 + 8006064: f7fb fe34 bl 8001cd0 + 8006068: 2803 cmp r0, #3 + 800606a: bf9a itte ls + 800606c: 4b01 ldrls r3, [pc, #4] ; (8006074 ) + 800606e: 5c18 ldrbls r0, [r3, r0] + 8006070: 2002 movhi r0, #2 + default : + usb_status = USBD_FAIL; + break; + } + return usb_status; +} + 8006072: bd10 pop {r4, pc} + 8006074: 08006cb5 .word 0x08006cb5 + +08006078 : + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + 8006078: b508 push {r3, lr} + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); + 800607a: f8d0 0220 ldr.w r0, [r0, #544] ; 0x220 + 800607e: f7fb fe55 bl 8001d2c + 8006082: 2803 cmp r0, #3 + 8006084: bf9a itte ls + 8006086: 4b02 ldrls r3, [pc, #8] ; (8006090 ) + 8006088: 5c18 ldrbls r0, [r3, r0] + 800608a: 2002 movhi r0, #2 + default : + usb_status = USBD_FAIL; + break; + } + return usb_status; +} + 800608c: bd08 pop {r3, pc} + 800608e: bf00 nop + 8006090: 08006cb5 .word 0x08006cb5 + +08006094 : + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + 8006094: b508 push {r3, lr} + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); + 8006096: f8d0 0220 ldr.w r0, [r0, #544] ; 0x220 + 800609a: f7fb feb6 bl 8001e0a + 800609e: 2803 cmp r0, #3 + 80060a0: bf9a itte ls + 80060a2: 4b02 ldrls r3, [pc, #8] ; (80060ac ) + 80060a4: 5c18 ldrbls r0, [r3, r0] + 80060a6: 2002 movhi r0, #2 + default : + usb_status = USBD_FAIL; + break; + } + return usb_status; +} + 80060a8: bd08 pop {r3, pc} + 80060aa: bf00 nop + 80060ac: 08006cb5 .word 0x08006cb5 + +080060b0 : + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + 80060b0: b508 push {r3, lr} + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); + 80060b2: f8d0 0220 ldr.w r0, [r0, #544] ; 0x220 + 80060b6: f7fb fed4 bl 8001e62 + 80060ba: 2803 cmp r0, #3 + 80060bc: bf9a itte ls + 80060be: 4b02 ldrls r3, [pc, #8] ; (80060c8 ) + 80060c0: 5c18 ldrbls r0, [r3, r0] + 80060c2: 2002 movhi r0, #2 + default : + usb_status = USBD_FAIL; + break; + } + return usb_status; +} + 80060c4: bd08 pop {r3, pc} + 80060c6: bf00 nop + 80060c8: 08006cb5 .word 0x08006cb5 + +080060cc : + */ +uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; + + if((ep_addr & 0x80) == 0x80) + 80060cc: f011 0f80 tst.w r1, #128 ; 0x80 + PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; + 80060d0: f8d0 3220 ldr.w r3, [r0, #544] ; 0x220 + 80060d4: f04f 021c mov.w r2, #28 + { + return hpcd->IN_ep[ep_addr & 0x7F].is_stall; + 80060d8: bf1b ittet ne + 80060da: f001 017f andne.w r1, r1, #127 ; 0x7f + 80060de: fb02 3101 mlane r1, r2, r1, r3 + } + else + { + return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; + 80060e2: fb02 3101 mlaeq r1, r2, r1, r3 + return hpcd->IN_ep[ep_addr & 0x7F].is_stall; + 80060e6: f891 003a ldrbne.w r0, [r1, #58] ; 0x3a + return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; + 80060ea: bf08 it eq + 80060ec: f891 01fa ldrbeq.w r0, [r1, #506] ; 0x1fa + } +} + 80060f0: 4770 bx lr + ... + +080060f4 : + * @param pdev: Device handle + * @param dev_addr: Device address + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) +{ + 80060f4: b508 push {r3, lr} + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); + 80060f6: f8d0 0220 ldr.w r0, [r0, #544] ; 0x220 + 80060fa: f7fb fdd7 bl 8001cac + 80060fe: 2803 cmp r0, #3 + 8006100: bf9a itte ls + 8006102: 4b02 ldrls r3, [pc, #8] ; (800610c ) + 8006104: 5c18 ldrbls r0, [r3, r0] + 8006106: 2002 movhi r0, #2 + default : + usb_status = USBD_FAIL; + break; + } + return usb_status; +} + 8006108: bd08 pop {r3, pc} + 800610a: bf00 nop + 800610c: 08006cb5 .word 0x08006cb5 + +08006110 : + * @param pbuf: Pointer to data to be sent + * @param size: Data size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) +{ + 8006110: b508 push {r3, lr} + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); + 8006112: f8d0 0220 ldr.w r0, [r0, #544] ; 0x220 + 8006116: f7fb fe58 bl 8001dca + 800611a: 2803 cmp r0, #3 + 800611c: bf9a itte ls + 800611e: 4b02 ldrls r3, [pc, #8] ; (8006128 ) + 8006120: 5c18 ldrbls r0, [r3, r0] + 8006122: 2002 movhi r0, #2 + default : + usb_status = USBD_FAIL; + break; + } + return usb_status; +} + 8006124: bd08 pop {r3, pc} + 8006126: bf00 nop + 8006128: 08006cb5 .word 0x08006cb5 + +0800612c : + * @param pbuf: Pointer to data to be received + * @param size: Data size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) +{ + 800612c: b508 push {r3, lr} + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); + 800612e: f8d0 0220 ldr.w r0, [r0, #544] ; 0x220 + 8006132: f7fb fe1e bl 8001d72 + 8006136: 2803 cmp r0, #3 + 8006138: bf9a itte ls + 800613a: 4b02 ldrls r3, [pc, #8] ; (8006144 ) + 800613c: 5c18 ldrbls r0, [r3, r0] + 800613e: 2002 movhi r0, #2 + default : + usb_status = USBD_FAIL; + break; + } + return usb_status; +} + 8006140: bd08 pop {r3, pc} + 8006142: bf00 nop + 8006144: 08006cb5 .word 0x08006cb5 + +08006148 : + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval Recived Data Size + */ +uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + 8006148: b508 push {r3, lr} + return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); + 800614a: f8d0 0220 ldr.w r0, [r0, #544] ; 0x220 + 800614e: f7fb fe34 bl 8001dba +} + 8006152: bd08 pop {r3, pc} + +08006154 : + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + *length = sizeof(USBD_FS_DeviceDesc); + 8006154: 2312 movs r3, #18 + 8006156: 800b strh r3, [r1, #0] + return USBD_FS_DeviceDesc; +} + 8006158: 4800 ldr r0, [pc, #0] ; (800615c ) + 800615a: 4770 bx lr + 800615c: 200001c8 .word 0x200001c8 + +08006160 : + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + *length = sizeof(USBD_LangIDDesc); + 8006160: 2304 movs r3, #4 + 8006162: 800b strh r3, [r1, #0] + return USBD_LangIDDesc; +} + 8006164: 4800 ldr r0, [pc, #0] ; (8006168 ) + 8006166: 4770 bx lr + 8006168: 200001dc .word 0x200001dc + +0800616c : + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + 800616c: b510 push {r4, lr} + USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); + 800616e: 4c04 ldr r4, [pc, #16] ; (8006180 ) + 8006170: 4804 ldr r0, [pc, #16] ; (8006184 ) + 8006172: 460a mov r2, r1 + 8006174: 4621 mov r1, r4 + 8006176: f7fd fcdc bl 8003b32 + return USBD_StrDesc; +} + 800617a: 4620 mov r0, r4 + 800617c: bd10 pop {r4, pc} + 800617e: bf00 nop + 8006180: 200047f0 .word 0x200047f0 + 8006184: 08006ce5 .word 0x08006ce5 + +08006188 : +{ + 8006188: b510 push {r4, lr} + USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + 800618a: 4c04 ldr r4, [pc, #16] ; (800619c ) + 800618c: 4804 ldr r0, [pc, #16] ; (80061a0 ) + 800618e: 460a mov r2, r1 + 8006190: 4621 mov r1, r4 + 8006192: f7fd fcce bl 8003b32 +} + 8006196: 4620 mov r0, r4 + 8006198: bd10 pop {r4, pc} + 800619a: bf00 nop + 800619c: 200047f0 .word 0x200047f0 + 80061a0: 08006cf8 .word 0x08006cf8 + +080061a4 : + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + 80061a4: b510 push {r4, lr} + if(speed == USBD_SPEED_HIGH) + { + USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); + 80061a6: 4c04 ldr r4, [pc, #16] ; (80061b8 ) + 80061a8: 4804 ldr r0, [pc, #16] ; (80061bc ) + 80061aa: 460a mov r2, r1 + 80061ac: 4621 mov r1, r4 + 80061ae: f7fd fcc0 bl 8003b32 + else + { + USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); + } + return USBD_StrDesc; +} + 80061b2: 4620 mov r0, r4 + 80061b4: bd10 pop {r4, pc} + 80061b6: bf00 nop + 80061b8: 200047f0 .word 0x200047f0 + 80061bc: 08006d0e .word 0x08006d0e + +080061c0 : + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + 80061c0: b510 push {r4, lr} + if(speed == USBD_SPEED_HIGH) + { + USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + 80061c2: 4c04 ldr r4, [pc, #16] ; (80061d4 ) + 80061c4: 4804 ldr r0, [pc, #16] ; (80061d8 ) + 80061c6: 460a mov r2, r1 + 80061c8: 4621 mov r1, r4 + 80061ca: f7fd fcb2 bl 8003b32 + else + { + USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + } + return USBD_StrDesc; +} + 80061ce: 4620 mov r0, r4 + 80061d0: bd10 pop {r4, pc} + 80061d2: bf00 nop + 80061d4: 200047f0 .word 0x200047f0 + 80061d8: 08006ccc .word 0x08006ccc + +080061dc : + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + 80061dc: b510 push {r4, lr} + if(speed == 0) + { + USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + 80061de: 4c04 ldr r4, [pc, #16] ; (80061f0 ) + 80061e0: 4804 ldr r0, [pc, #16] ; (80061f4 ) + 80061e2: 460a mov r2, r1 + 80061e4: 4621 mov r1, r4 + 80061e6: f7fd fca4 bl 8003b32 + else + { + USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + } + return USBD_StrDesc; +} + 80061ea: 4620 mov r0, r4 + 80061ec: bd10 pop {r4, pc} + 80061ee: bf00 nop + 80061f0: 200047f0 .word 0x200047f0 + 80061f4: 08006cd7 .word 0x08006cd7 + +080061f8 : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + 80061f8: f8df d034 ldr.w sp, [pc, #52] ; 8006230 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + 80061fc: 2100 movs r1, #0 + b LoopCopyDataInit + 80061fe: e003 b.n 8006208 + +08006200 : + +CopyDataInit: + ldr r3, =_sidata + 8006200: 4b0c ldr r3, [pc, #48] ; (8006234 ) + ldr r3, [r3, r1] + 8006202: 585b ldr r3, [r3, r1] + str r3, [r0, r1] + 8006204: 5043 str r3, [r0, r1] + adds r1, r1, #4 + 8006206: 3104 adds r1, #4 + +08006208 : + +LoopCopyDataInit: + ldr r0, =_sdata + 8006208: 480b ldr r0, [pc, #44] ; (8006238 ) + ldr r3, =_edata + 800620a: 4b0c ldr r3, [pc, #48] ; (800623c ) + adds r2, r0, r1 + 800620c: 1842 adds r2, r0, r1 + cmp r2, r3 + 800620e: 429a cmp r2, r3 + bcc CopyDataInit + 8006210: d3f6 bcc.n 8006200 + ldr r2, =_sbss + 8006212: 4a0b ldr r2, [pc, #44] ; (8006240 ) + b LoopFillZerobss + 8006214: e002 b.n 800621c + +08006216 : +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + 8006216: 2300 movs r3, #0 + str r3, [r2], #4 + 8006218: f842 3b04 str.w r3, [r2], #4 + +0800621c : + +LoopFillZerobss: + ldr r3, = _ebss + 800621c: 4b09 ldr r3, [pc, #36] ; (8006244 ) + cmp r2, r3 + 800621e: 429a cmp r2, r3 + bcc FillZerobss + 8006220: d3f9 bcc.n 8006216 + +/* Call the clock system intitialization function.*/ + bl SystemInit + 8006222: f7ff fd8d bl 8005d40 +/* Call static constructors */ + bl __libc_init_array + 8006226: f000 f811 bl 800624c <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 800622a: f7ff fa51 bl 80056d0
+ bx lr + 800622e: 4770 bx lr + ldr sp, =_estack /* set stack pointer */ + 8006230: 20020000 .word 0x20020000 + ldr r3, =_sidata + 8006234: 08006d60 .word 0x08006d60 + ldr r0, =_sdata + 8006238: 20000000 .word 0x20000000 + ldr r3, =_edata + 800623c: 20000244 .word 0x20000244 + ldr r2, =_sbss + 8006240: 20000244 .word 0x20000244 + ldr r3, = _ebss + 8006244: 200049f4 .word 0x200049f4 + +08006248 : + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8006248: e7fe b.n 8006248 + ... + +0800624c <__libc_init_array>: + 800624c: b570 push {r4, r5, r6, lr} + 800624e: 4e0d ldr r6, [pc, #52] ; (8006284 <__libc_init_array+0x38>) + 8006250: 4c0d ldr r4, [pc, #52] ; (8006288 <__libc_init_array+0x3c>) + 8006252: 1ba4 subs r4, r4, r6 + 8006254: 10a4 asrs r4, r4, #2 + 8006256: 2500 movs r5, #0 + 8006258: 42a5 cmp r5, r4 + 800625a: d109 bne.n 8006270 <__libc_init_array+0x24> + 800625c: 4e0b ldr r6, [pc, #44] ; (800628c <__libc_init_array+0x40>) + 800625e: 4c0c ldr r4, [pc, #48] ; (8006290 <__libc_init_array+0x44>) + 8006260: f000 fc6c bl 8006b3c <_init> + 8006264: 1ba4 subs r4, r4, r6 + 8006266: 10a4 asrs r4, r4, #2 + 8006268: 2500 movs r5, #0 + 800626a: 42a5 cmp r5, r4 + 800626c: d105 bne.n 800627a <__libc_init_array+0x2e> + 800626e: bd70 pop {r4, r5, r6, pc} + 8006270: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 8006274: 4798 blx r3 + 8006276: 3501 adds r5, #1 + 8006278: e7ee b.n 8006258 <__libc_init_array+0xc> + 800627a: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 800627e: 4798 blx r3 + 8006280: 3501 adds r5, #1 + 8006282: e7f2 b.n 800626a <__libc_init_array+0x1e> + 8006284: 08006d58 .word 0x08006d58 + 8006288: 08006d58 .word 0x08006d58 + 800628c: 08006d58 .word 0x08006d58 + 8006290: 08006d5c .word 0x08006d5c + +08006294 : + 8006294: 4b02 ldr r3, [pc, #8] ; (80062a0 ) + 8006296: 4601 mov r1, r0 + 8006298: 6818 ldr r0, [r3, #0] + 800629a: f000 b86d b.w 8006378 <_malloc_r> + 800629e: bf00 nop + 80062a0: 200001e0 .word 0x200001e0 + +080062a4 : + 80062a4: 4b02 ldr r3, [pc, #8] ; (80062b0 ) + 80062a6: 4601 mov r1, r0 + 80062a8: 6818 ldr r0, [r3, #0] + 80062aa: f000 b817 b.w 80062dc <_free_r> + 80062ae: bf00 nop + 80062b0: 200001e0 .word 0x200001e0 + +080062b4 : + 80062b4: b510 push {r4, lr} + 80062b6: 1e43 subs r3, r0, #1 + 80062b8: 440a add r2, r1 + 80062ba: 4291 cmp r1, r2 + 80062bc: d100 bne.n 80062c0 + 80062be: bd10 pop {r4, pc} + 80062c0: f811 4b01 ldrb.w r4, [r1], #1 + 80062c4: f803 4f01 strb.w r4, [r3, #1]! + 80062c8: e7f7 b.n 80062ba + +080062ca : + 80062ca: 4402 add r2, r0 + 80062cc: 4603 mov r3, r0 + 80062ce: 4293 cmp r3, r2 + 80062d0: d100 bne.n 80062d4 + 80062d2: 4770 bx lr + 80062d4: f803 1b01 strb.w r1, [r3], #1 + 80062d8: e7f9 b.n 80062ce + ... + +080062dc <_free_r>: + 80062dc: b538 push {r3, r4, r5, lr} + 80062de: 4605 mov r5, r0 + 80062e0: 2900 cmp r1, #0 + 80062e2: d045 beq.n 8006370 <_free_r+0x94> + 80062e4: f851 3c04 ldr.w r3, [r1, #-4] + 80062e8: 1f0c subs r4, r1, #4 + 80062ea: 2b00 cmp r3, #0 + 80062ec: bfb8 it lt + 80062ee: 18e4 addlt r4, r4, r3 + 80062f0: f000 f8e4 bl 80064bc <__malloc_lock> + 80062f4: 4a1f ldr r2, [pc, #124] ; (8006374 <_free_r+0x98>) + 80062f6: 6813 ldr r3, [r2, #0] + 80062f8: 4610 mov r0, r2 + 80062fa: b933 cbnz r3, 800630a <_free_r+0x2e> + 80062fc: 6063 str r3, [r4, #4] + 80062fe: 6014 str r4, [r2, #0] + 8006300: 4628 mov r0, r5 + 8006302: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 8006306: f000 b8da b.w 80064be <__malloc_unlock> + 800630a: 42a3 cmp r3, r4 + 800630c: d90c bls.n 8006328 <_free_r+0x4c> + 800630e: 6821 ldr r1, [r4, #0] + 8006310: 1862 adds r2, r4, r1 + 8006312: 4293 cmp r3, r2 + 8006314: bf04 itt eq + 8006316: 681a ldreq r2, [r3, #0] + 8006318: 685b ldreq r3, [r3, #4] + 800631a: 6063 str r3, [r4, #4] + 800631c: bf04 itt eq + 800631e: 1852 addeq r2, r2, r1 + 8006320: 6022 streq r2, [r4, #0] + 8006322: 6004 str r4, [r0, #0] + 8006324: e7ec b.n 8006300 <_free_r+0x24> + 8006326: 4613 mov r3, r2 + 8006328: 685a ldr r2, [r3, #4] + 800632a: b10a cbz r2, 8006330 <_free_r+0x54> + 800632c: 42a2 cmp r2, r4 + 800632e: d9fa bls.n 8006326 <_free_r+0x4a> + 8006330: 6819 ldr r1, [r3, #0] + 8006332: 1858 adds r0, r3, r1 + 8006334: 42a0 cmp r0, r4 + 8006336: d10b bne.n 8006350 <_free_r+0x74> + 8006338: 6820 ldr r0, [r4, #0] + 800633a: 4401 add r1, r0 + 800633c: 1858 adds r0, r3, r1 + 800633e: 4282 cmp r2, r0 + 8006340: 6019 str r1, [r3, #0] + 8006342: d1dd bne.n 8006300 <_free_r+0x24> + 8006344: 6810 ldr r0, [r2, #0] + 8006346: 6852 ldr r2, [r2, #4] + 8006348: 605a str r2, [r3, #4] + 800634a: 4401 add r1, r0 + 800634c: 6019 str r1, [r3, #0] + 800634e: e7d7 b.n 8006300 <_free_r+0x24> + 8006350: d902 bls.n 8006358 <_free_r+0x7c> + 8006352: 230c movs r3, #12 + 8006354: 602b str r3, [r5, #0] + 8006356: e7d3 b.n 8006300 <_free_r+0x24> + 8006358: 6820 ldr r0, [r4, #0] + 800635a: 1821 adds r1, r4, r0 + 800635c: 428a cmp r2, r1 + 800635e: bf04 itt eq + 8006360: 6811 ldreq r1, [r2, #0] + 8006362: 6852 ldreq r2, [r2, #4] + 8006364: 6062 str r2, [r4, #4] + 8006366: bf04 itt eq + 8006368: 1809 addeq r1, r1, r0 + 800636a: 6021 streq r1, [r4, #0] + 800636c: 605c str r4, [r3, #4] + 800636e: e7c7 b.n 8006300 <_free_r+0x24> + 8006370: bd38 pop {r3, r4, r5, pc} + 8006372: bf00 nop + 8006374: 20004008 .word 0x20004008 + +08006378 <_malloc_r>: + 8006378: b570 push {r4, r5, r6, lr} + 800637a: 1ccd adds r5, r1, #3 + 800637c: f025 0503 bic.w r5, r5, #3 + 8006380: 3508 adds r5, #8 + 8006382: 2d0c cmp r5, #12 + 8006384: bf38 it cc + 8006386: 250c movcc r5, #12 + 8006388: 2d00 cmp r5, #0 + 800638a: 4606 mov r6, r0 + 800638c: db01 blt.n 8006392 <_malloc_r+0x1a> + 800638e: 42a9 cmp r1, r5 + 8006390: d903 bls.n 800639a <_malloc_r+0x22> + 8006392: 230c movs r3, #12 + 8006394: 6033 str r3, [r6, #0] + 8006396: 2000 movs r0, #0 + 8006398: bd70 pop {r4, r5, r6, pc} + 800639a: f000 f88f bl 80064bc <__malloc_lock> + 800639e: 4a23 ldr r2, [pc, #140] ; (800642c <_malloc_r+0xb4>) + 80063a0: 6814 ldr r4, [r2, #0] + 80063a2: 4621 mov r1, r4 + 80063a4: b991 cbnz r1, 80063cc <_malloc_r+0x54> + 80063a6: 4c22 ldr r4, [pc, #136] ; (8006430 <_malloc_r+0xb8>) + 80063a8: 6823 ldr r3, [r4, #0] + 80063aa: b91b cbnz r3, 80063b4 <_malloc_r+0x3c> + 80063ac: 4630 mov r0, r6 + 80063ae: f000 f841 bl 8006434 <_sbrk_r> + 80063b2: 6020 str r0, [r4, #0] + 80063b4: 4629 mov r1, r5 + 80063b6: 4630 mov r0, r6 + 80063b8: f000 f83c bl 8006434 <_sbrk_r> + 80063bc: 1c43 adds r3, r0, #1 + 80063be: d126 bne.n 800640e <_malloc_r+0x96> + 80063c0: 230c movs r3, #12 + 80063c2: 6033 str r3, [r6, #0] + 80063c4: 4630 mov r0, r6 + 80063c6: f000 f87a bl 80064be <__malloc_unlock> + 80063ca: e7e4 b.n 8006396 <_malloc_r+0x1e> + 80063cc: 680b ldr r3, [r1, #0] + 80063ce: 1b5b subs r3, r3, r5 + 80063d0: d41a bmi.n 8006408 <_malloc_r+0x90> + 80063d2: 2b0b cmp r3, #11 + 80063d4: d90f bls.n 80063f6 <_malloc_r+0x7e> + 80063d6: 600b str r3, [r1, #0] + 80063d8: 50cd str r5, [r1, r3] + 80063da: 18cc adds r4, r1, r3 + 80063dc: 4630 mov r0, r6 + 80063de: f000 f86e bl 80064be <__malloc_unlock> + 80063e2: f104 000b add.w r0, r4, #11 + 80063e6: 1d23 adds r3, r4, #4 + 80063e8: f020 0007 bic.w r0, r0, #7 + 80063ec: 1ac3 subs r3, r0, r3 + 80063ee: d01b beq.n 8006428 <_malloc_r+0xb0> + 80063f0: 425a negs r2, r3 + 80063f2: 50e2 str r2, [r4, r3] + 80063f4: bd70 pop {r4, r5, r6, pc} + 80063f6: 428c cmp r4, r1 + 80063f8: bf0d iteet eq + 80063fa: 6863 ldreq r3, [r4, #4] + 80063fc: 684b ldrne r3, [r1, #4] + 80063fe: 6063 strne r3, [r4, #4] + 8006400: 6013 streq r3, [r2, #0] + 8006402: bf18 it ne + 8006404: 460c movne r4, r1 + 8006406: e7e9 b.n 80063dc <_malloc_r+0x64> + 8006408: 460c mov r4, r1 + 800640a: 6849 ldr r1, [r1, #4] + 800640c: e7ca b.n 80063a4 <_malloc_r+0x2c> + 800640e: 1cc4 adds r4, r0, #3 + 8006410: f024 0403 bic.w r4, r4, #3 + 8006414: 42a0 cmp r0, r4 + 8006416: d005 beq.n 8006424 <_malloc_r+0xac> + 8006418: 1a21 subs r1, r4, r0 + 800641a: 4630 mov r0, r6 + 800641c: f000 f80a bl 8006434 <_sbrk_r> + 8006420: 3001 adds r0, #1 + 8006422: d0cd beq.n 80063c0 <_malloc_r+0x48> + 8006424: 6025 str r5, [r4, #0] + 8006426: e7d9 b.n 80063dc <_malloc_r+0x64> + 8006428: bd70 pop {r4, r5, r6, pc} + 800642a: bf00 nop + 800642c: 20004008 .word 0x20004008 + 8006430: 2000400c .word 0x2000400c + +08006434 <_sbrk_r>: + 8006434: b538 push {r3, r4, r5, lr} + 8006436: 4c06 ldr r4, [pc, #24] ; (8006450 <_sbrk_r+0x1c>) + 8006438: 2300 movs r3, #0 + 800643a: 4605 mov r5, r0 + 800643c: 4608 mov r0, r1 + 800643e: 6023 str r3, [r4, #0] + 8006440: f000 fb6e bl 8006b20 <_sbrk> + 8006444: 1c43 adds r3, r0, #1 + 8006446: d102 bne.n 800644e <_sbrk_r+0x1a> + 8006448: 6823 ldr r3, [r4, #0] + 800644a: b103 cbz r3, 800644e <_sbrk_r+0x1a> + 800644c: 602b str r3, [r5, #0] + 800644e: bd38 pop {r3, r4, r5, pc} + 8006450: 200049f0 .word 0x200049f0 + +08006454 : + 8006454: b40c push {r2, r3} + 8006456: b530 push {r4, r5, lr} + 8006458: 4b17 ldr r3, [pc, #92] ; (80064b8 ) + 800645a: 1e0c subs r4, r1, #0 + 800645c: b09d sub sp, #116 ; 0x74 + 800645e: 681d ldr r5, [r3, #0] + 8006460: da08 bge.n 8006474 + 8006462: 238b movs r3, #139 ; 0x8b + 8006464: 602b str r3, [r5, #0] + 8006466: f04f 30ff mov.w r0, #4294967295 + 800646a: b01d add sp, #116 ; 0x74 + 800646c: e8bd 4030 ldmia.w sp!, {r4, r5, lr} + 8006470: b002 add sp, #8 + 8006472: 4770 bx lr + 8006474: f44f 7302 mov.w r3, #520 ; 0x208 + 8006478: f8ad 3014 strh.w r3, [sp, #20] + 800647c: bf14 ite ne + 800647e: f104 33ff addne.w r3, r4, #4294967295 + 8006482: 4623 moveq r3, r4 + 8006484: 9304 str r3, [sp, #16] + 8006486: 9307 str r3, [sp, #28] + 8006488: f64f 73ff movw r3, #65535 ; 0xffff + 800648c: 9002 str r0, [sp, #8] + 800648e: 9006 str r0, [sp, #24] + 8006490: f8ad 3016 strh.w r3, [sp, #22] + 8006494: 9a20 ldr r2, [sp, #128] ; 0x80 + 8006496: ab21 add r3, sp, #132 ; 0x84 + 8006498: a902 add r1, sp, #8 + 800649a: 4628 mov r0, r5 + 800649c: 9301 str r3, [sp, #4] + 800649e: f000 f86b bl 8006578 <_svfiprintf_r> + 80064a2: 1c43 adds r3, r0, #1 + 80064a4: bfbc itt lt + 80064a6: 238b movlt r3, #139 ; 0x8b + 80064a8: 602b strlt r3, [r5, #0] + 80064aa: 2c00 cmp r4, #0 + 80064ac: d0dd beq.n 800646a + 80064ae: 9b02 ldr r3, [sp, #8] + 80064b0: 2200 movs r2, #0 + 80064b2: 701a strb r2, [r3, #0] + 80064b4: e7d9 b.n 800646a + 80064b6: bf00 nop + 80064b8: 200001e0 .word 0x200001e0 + +080064bc <__malloc_lock>: + 80064bc: 4770 bx lr + +080064be <__malloc_unlock>: + 80064be: 4770 bx lr + +080064c0 <__ssputs_r>: + 80064c0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80064c4: 688e ldr r6, [r1, #8] + 80064c6: 429e cmp r6, r3 + 80064c8: 4682 mov sl, r0 + 80064ca: 460c mov r4, r1 + 80064cc: 4691 mov r9, r2 + 80064ce: 4698 mov r8, r3 + 80064d0: d835 bhi.n 800653e <__ssputs_r+0x7e> + 80064d2: 898a ldrh r2, [r1, #12] + 80064d4: f412 6f90 tst.w r2, #1152 ; 0x480 + 80064d8: d031 beq.n 800653e <__ssputs_r+0x7e> + 80064da: 6825 ldr r5, [r4, #0] + 80064dc: 6909 ldr r1, [r1, #16] + 80064de: 1a6f subs r7, r5, r1 + 80064e0: 6965 ldr r5, [r4, #20] + 80064e2: 2302 movs r3, #2 + 80064e4: eb05 0545 add.w r5, r5, r5, lsl #1 + 80064e8: fb95 f5f3 sdiv r5, r5, r3 + 80064ec: f108 0301 add.w r3, r8, #1 + 80064f0: 443b add r3, r7 + 80064f2: 429d cmp r5, r3 + 80064f4: bf38 it cc + 80064f6: 461d movcc r5, r3 + 80064f8: 0553 lsls r3, r2, #21 + 80064fa: d531 bpl.n 8006560 <__ssputs_r+0xa0> + 80064fc: 4629 mov r1, r5 + 80064fe: f7ff ff3b bl 8006378 <_malloc_r> + 8006502: 4606 mov r6, r0 + 8006504: b950 cbnz r0, 800651c <__ssputs_r+0x5c> + 8006506: 230c movs r3, #12 + 8006508: f8ca 3000 str.w r3, [sl] + 800650c: 89a3 ldrh r3, [r4, #12] + 800650e: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8006512: 81a3 strh r3, [r4, #12] + 8006514: f04f 30ff mov.w r0, #4294967295 + 8006518: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800651c: 463a mov r2, r7 + 800651e: 6921 ldr r1, [r4, #16] + 8006520: f7ff fec8 bl 80062b4 + 8006524: 89a3 ldrh r3, [r4, #12] + 8006526: f423 6390 bic.w r3, r3, #1152 ; 0x480 + 800652a: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800652e: 81a3 strh r3, [r4, #12] + 8006530: 6126 str r6, [r4, #16] + 8006532: 6165 str r5, [r4, #20] + 8006534: 443e add r6, r7 + 8006536: 1bed subs r5, r5, r7 + 8006538: 6026 str r6, [r4, #0] + 800653a: 60a5 str r5, [r4, #8] + 800653c: 4646 mov r6, r8 + 800653e: 4546 cmp r6, r8 + 8006540: bf28 it cs + 8006542: 4646 movcs r6, r8 + 8006544: 4632 mov r2, r6 + 8006546: 4649 mov r1, r9 + 8006548: 6820 ldr r0, [r4, #0] + 800654a: f000 fa9f bl 8006a8c + 800654e: 68a3 ldr r3, [r4, #8] + 8006550: 1b9b subs r3, r3, r6 + 8006552: 60a3 str r3, [r4, #8] + 8006554: 6823 ldr r3, [r4, #0] + 8006556: 441e add r6, r3 + 8006558: 6026 str r6, [r4, #0] + 800655a: 2000 movs r0, #0 + 800655c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8006560: 462a mov r2, r5 + 8006562: f000 faad bl 8006ac0 <_realloc_r> + 8006566: 4606 mov r6, r0 + 8006568: 2800 cmp r0, #0 + 800656a: d1e1 bne.n 8006530 <__ssputs_r+0x70> + 800656c: 6921 ldr r1, [r4, #16] + 800656e: 4650 mov r0, sl + 8006570: f7ff feb4 bl 80062dc <_free_r> + 8006574: e7c7 b.n 8006506 <__ssputs_r+0x46> + ... + +08006578 <_svfiprintf_r>: + 8006578: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800657c: b09d sub sp, #116 ; 0x74 + 800657e: 4680 mov r8, r0 + 8006580: 9303 str r3, [sp, #12] + 8006582: 898b ldrh r3, [r1, #12] + 8006584: 061c lsls r4, r3, #24 + 8006586: 460d mov r5, r1 + 8006588: 4616 mov r6, r2 + 800658a: d50f bpl.n 80065ac <_svfiprintf_r+0x34> + 800658c: 690b ldr r3, [r1, #16] + 800658e: b96b cbnz r3, 80065ac <_svfiprintf_r+0x34> + 8006590: 2140 movs r1, #64 ; 0x40 + 8006592: f7ff fef1 bl 8006378 <_malloc_r> + 8006596: 6028 str r0, [r5, #0] + 8006598: 6128 str r0, [r5, #16] + 800659a: b928 cbnz r0, 80065a8 <_svfiprintf_r+0x30> + 800659c: 230c movs r3, #12 + 800659e: f8c8 3000 str.w r3, [r8] + 80065a2: f04f 30ff mov.w r0, #4294967295 + 80065a6: e0c5 b.n 8006734 <_svfiprintf_r+0x1bc> + 80065a8: 2340 movs r3, #64 ; 0x40 + 80065aa: 616b str r3, [r5, #20] + 80065ac: 2300 movs r3, #0 + 80065ae: 9309 str r3, [sp, #36] ; 0x24 + 80065b0: 2320 movs r3, #32 + 80065b2: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 80065b6: 2330 movs r3, #48 ; 0x30 + 80065b8: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 80065bc: f04f 0b01 mov.w fp, #1 + 80065c0: 4637 mov r7, r6 + 80065c2: 463c mov r4, r7 + 80065c4: f814 3b01 ldrb.w r3, [r4], #1 + 80065c8: 2b00 cmp r3, #0 + 80065ca: d13c bne.n 8006646 <_svfiprintf_r+0xce> + 80065cc: ebb7 0a06 subs.w sl, r7, r6 + 80065d0: d00b beq.n 80065ea <_svfiprintf_r+0x72> + 80065d2: 4653 mov r3, sl + 80065d4: 4632 mov r2, r6 + 80065d6: 4629 mov r1, r5 + 80065d8: 4640 mov r0, r8 + 80065da: f7ff ff71 bl 80064c0 <__ssputs_r> + 80065de: 3001 adds r0, #1 + 80065e0: f000 80a3 beq.w 800672a <_svfiprintf_r+0x1b2> + 80065e4: 9b09 ldr r3, [sp, #36] ; 0x24 + 80065e6: 4453 add r3, sl + 80065e8: 9309 str r3, [sp, #36] ; 0x24 + 80065ea: 783b ldrb r3, [r7, #0] + 80065ec: 2b00 cmp r3, #0 + 80065ee: f000 809c beq.w 800672a <_svfiprintf_r+0x1b2> + 80065f2: 2300 movs r3, #0 + 80065f4: f04f 32ff mov.w r2, #4294967295 + 80065f8: 9304 str r3, [sp, #16] + 80065fa: 9307 str r3, [sp, #28] + 80065fc: 9205 str r2, [sp, #20] + 80065fe: 9306 str r3, [sp, #24] + 8006600: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 8006604: 931a str r3, [sp, #104] ; 0x68 + 8006606: 2205 movs r2, #5 + 8006608: 7821 ldrb r1, [r4, #0] + 800660a: 4850 ldr r0, [pc, #320] ; (800674c <_svfiprintf_r+0x1d4>) + 800660c: f7f9 fde8 bl 80001e0 + 8006610: 1c67 adds r7, r4, #1 + 8006612: 9b04 ldr r3, [sp, #16] + 8006614: b9d8 cbnz r0, 800664e <_svfiprintf_r+0xd6> + 8006616: 06d9 lsls r1, r3, #27 + 8006618: bf44 itt mi + 800661a: 2220 movmi r2, #32 + 800661c: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 + 8006620: 071a lsls r2, r3, #28 + 8006622: bf44 itt mi + 8006624: 222b movmi r2, #43 ; 0x2b + 8006626: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 + 800662a: 7822 ldrb r2, [r4, #0] + 800662c: 2a2a cmp r2, #42 ; 0x2a + 800662e: d016 beq.n 800665e <_svfiprintf_r+0xe6> + 8006630: 9a07 ldr r2, [sp, #28] + 8006632: 2100 movs r1, #0 + 8006634: 200a movs r0, #10 + 8006636: 4627 mov r7, r4 + 8006638: 3401 adds r4, #1 + 800663a: 783b ldrb r3, [r7, #0] + 800663c: 3b30 subs r3, #48 ; 0x30 + 800663e: 2b09 cmp r3, #9 + 8006640: d951 bls.n 80066e6 <_svfiprintf_r+0x16e> + 8006642: b1c9 cbz r1, 8006678 <_svfiprintf_r+0x100> + 8006644: e011 b.n 800666a <_svfiprintf_r+0xf2> + 8006646: 2b25 cmp r3, #37 ; 0x25 + 8006648: d0c0 beq.n 80065cc <_svfiprintf_r+0x54> + 800664a: 4627 mov r7, r4 + 800664c: e7b9 b.n 80065c2 <_svfiprintf_r+0x4a> + 800664e: 4a3f ldr r2, [pc, #252] ; (800674c <_svfiprintf_r+0x1d4>) + 8006650: 1a80 subs r0, r0, r2 + 8006652: fa0b f000 lsl.w r0, fp, r0 + 8006656: 4318 orrs r0, r3 + 8006658: 9004 str r0, [sp, #16] + 800665a: 463c mov r4, r7 + 800665c: e7d3 b.n 8006606 <_svfiprintf_r+0x8e> + 800665e: 9a03 ldr r2, [sp, #12] + 8006660: 1d11 adds r1, r2, #4 + 8006662: 6812 ldr r2, [r2, #0] + 8006664: 9103 str r1, [sp, #12] + 8006666: 2a00 cmp r2, #0 + 8006668: db01 blt.n 800666e <_svfiprintf_r+0xf6> + 800666a: 9207 str r2, [sp, #28] + 800666c: e004 b.n 8006678 <_svfiprintf_r+0x100> + 800666e: 4252 negs r2, r2 + 8006670: f043 0302 orr.w r3, r3, #2 + 8006674: 9207 str r2, [sp, #28] + 8006676: 9304 str r3, [sp, #16] + 8006678: 783b ldrb r3, [r7, #0] + 800667a: 2b2e cmp r3, #46 ; 0x2e + 800667c: d10e bne.n 800669c <_svfiprintf_r+0x124> + 800667e: 787b ldrb r3, [r7, #1] + 8006680: 2b2a cmp r3, #42 ; 0x2a + 8006682: f107 0101 add.w r1, r7, #1 + 8006686: d132 bne.n 80066ee <_svfiprintf_r+0x176> + 8006688: 9b03 ldr r3, [sp, #12] + 800668a: 1d1a adds r2, r3, #4 + 800668c: 681b ldr r3, [r3, #0] + 800668e: 9203 str r2, [sp, #12] + 8006690: 2b00 cmp r3, #0 + 8006692: bfb8 it lt + 8006694: f04f 33ff movlt.w r3, #4294967295 + 8006698: 3702 adds r7, #2 + 800669a: 9305 str r3, [sp, #20] + 800669c: 4c2c ldr r4, [pc, #176] ; (8006750 <_svfiprintf_r+0x1d8>) + 800669e: 7839 ldrb r1, [r7, #0] + 80066a0: 2203 movs r2, #3 + 80066a2: 4620 mov r0, r4 + 80066a4: f7f9 fd9c bl 80001e0 + 80066a8: b138 cbz r0, 80066ba <_svfiprintf_r+0x142> + 80066aa: 2340 movs r3, #64 ; 0x40 + 80066ac: 1b00 subs r0, r0, r4 + 80066ae: fa03 f000 lsl.w r0, r3, r0 + 80066b2: 9b04 ldr r3, [sp, #16] + 80066b4: 4303 orrs r3, r0 + 80066b6: 9304 str r3, [sp, #16] + 80066b8: 3701 adds r7, #1 + 80066ba: 7839 ldrb r1, [r7, #0] + 80066bc: 4825 ldr r0, [pc, #148] ; (8006754 <_svfiprintf_r+0x1dc>) + 80066be: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 80066c2: 2206 movs r2, #6 + 80066c4: 1c7e adds r6, r7, #1 + 80066c6: f7f9 fd8b bl 80001e0 + 80066ca: 2800 cmp r0, #0 + 80066cc: d035 beq.n 800673a <_svfiprintf_r+0x1c2> + 80066ce: 4b22 ldr r3, [pc, #136] ; (8006758 <_svfiprintf_r+0x1e0>) + 80066d0: b9fb cbnz r3, 8006712 <_svfiprintf_r+0x19a> + 80066d2: 9b03 ldr r3, [sp, #12] + 80066d4: 3307 adds r3, #7 + 80066d6: f023 0307 bic.w r3, r3, #7 + 80066da: 3308 adds r3, #8 + 80066dc: 9303 str r3, [sp, #12] + 80066de: 9b09 ldr r3, [sp, #36] ; 0x24 + 80066e0: 444b add r3, r9 + 80066e2: 9309 str r3, [sp, #36] ; 0x24 + 80066e4: e76c b.n 80065c0 <_svfiprintf_r+0x48> + 80066e6: fb00 3202 mla r2, r0, r2, r3 + 80066ea: 2101 movs r1, #1 + 80066ec: e7a3 b.n 8006636 <_svfiprintf_r+0xbe> + 80066ee: 2300 movs r3, #0 + 80066f0: 9305 str r3, [sp, #20] + 80066f2: 4618 mov r0, r3 + 80066f4: 240a movs r4, #10 + 80066f6: 460f mov r7, r1 + 80066f8: 3101 adds r1, #1 + 80066fa: 783a ldrb r2, [r7, #0] + 80066fc: 3a30 subs r2, #48 ; 0x30 + 80066fe: 2a09 cmp r2, #9 + 8006700: d903 bls.n 800670a <_svfiprintf_r+0x192> + 8006702: 2b00 cmp r3, #0 + 8006704: d0ca beq.n 800669c <_svfiprintf_r+0x124> + 8006706: 9005 str r0, [sp, #20] + 8006708: e7c8 b.n 800669c <_svfiprintf_r+0x124> + 800670a: fb04 2000 mla r0, r4, r0, r2 + 800670e: 2301 movs r3, #1 + 8006710: e7f1 b.n 80066f6 <_svfiprintf_r+0x17e> + 8006712: ab03 add r3, sp, #12 + 8006714: 9300 str r3, [sp, #0] + 8006716: 462a mov r2, r5 + 8006718: 4b10 ldr r3, [pc, #64] ; (800675c <_svfiprintf_r+0x1e4>) + 800671a: a904 add r1, sp, #16 + 800671c: 4640 mov r0, r8 + 800671e: f3af 8000 nop.w + 8006722: f1b0 3fff cmp.w r0, #4294967295 + 8006726: 4681 mov r9, r0 + 8006728: d1d9 bne.n 80066de <_svfiprintf_r+0x166> + 800672a: 89ab ldrh r3, [r5, #12] + 800672c: 065b lsls r3, r3, #25 + 800672e: f53f af38 bmi.w 80065a2 <_svfiprintf_r+0x2a> + 8006732: 9809 ldr r0, [sp, #36] ; 0x24 + 8006734: b01d add sp, #116 ; 0x74 + 8006736: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800673a: ab03 add r3, sp, #12 + 800673c: 9300 str r3, [sp, #0] + 800673e: 462a mov r2, r5 + 8006740: 4b06 ldr r3, [pc, #24] ; (800675c <_svfiprintf_r+0x1e4>) + 8006742: a904 add r1, sp, #16 + 8006744: 4640 mov r0, r8 + 8006746: f000 f881 bl 800684c <_printf_i> + 800674a: e7ea b.n 8006722 <_svfiprintf_r+0x1aa> + 800674c: 08006d1b .word 0x08006d1b + 8006750: 08006d21 .word 0x08006d21 + 8006754: 08006d25 .word 0x08006d25 + 8006758: 00000000 .word 0x00000000 + 800675c: 080064c1 .word 0x080064c1 + +08006760 <_printf_common>: + 8006760: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8006764: 4691 mov r9, r2 + 8006766: 461f mov r7, r3 + 8006768: 688a ldr r2, [r1, #8] + 800676a: 690b ldr r3, [r1, #16] + 800676c: f8dd 8020 ldr.w r8, [sp, #32] + 8006770: 4293 cmp r3, r2 + 8006772: bfb8 it lt + 8006774: 4613 movlt r3, r2 + 8006776: f8c9 3000 str.w r3, [r9] + 800677a: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 + 800677e: 4606 mov r6, r0 + 8006780: 460c mov r4, r1 + 8006782: b112 cbz r2, 800678a <_printf_common+0x2a> + 8006784: 3301 adds r3, #1 + 8006786: f8c9 3000 str.w r3, [r9] + 800678a: 6823 ldr r3, [r4, #0] + 800678c: 0699 lsls r1, r3, #26 + 800678e: bf42 ittt mi + 8006790: f8d9 3000 ldrmi.w r3, [r9] + 8006794: 3302 addmi r3, #2 + 8006796: f8c9 3000 strmi.w r3, [r9] + 800679a: 6825 ldr r5, [r4, #0] + 800679c: f015 0506 ands.w r5, r5, #6 + 80067a0: d107 bne.n 80067b2 <_printf_common+0x52> + 80067a2: f104 0a19 add.w sl, r4, #25 + 80067a6: 68e3 ldr r3, [r4, #12] + 80067a8: f8d9 2000 ldr.w r2, [r9] + 80067ac: 1a9b subs r3, r3, r2 + 80067ae: 429d cmp r5, r3 + 80067b0: db29 blt.n 8006806 <_printf_common+0xa6> + 80067b2: f894 3043 ldrb.w r3, [r4, #67] ; 0x43 + 80067b6: 6822 ldr r2, [r4, #0] + 80067b8: 3300 adds r3, #0 + 80067ba: bf18 it ne + 80067bc: 2301 movne r3, #1 + 80067be: 0692 lsls r2, r2, #26 + 80067c0: d42e bmi.n 8006820 <_printf_common+0xc0> + 80067c2: f104 0243 add.w r2, r4, #67 ; 0x43 + 80067c6: 4639 mov r1, r7 + 80067c8: 4630 mov r0, r6 + 80067ca: 47c0 blx r8 + 80067cc: 3001 adds r0, #1 + 80067ce: d021 beq.n 8006814 <_printf_common+0xb4> + 80067d0: 6823 ldr r3, [r4, #0] + 80067d2: 68e5 ldr r5, [r4, #12] + 80067d4: f8d9 2000 ldr.w r2, [r9] + 80067d8: f003 0306 and.w r3, r3, #6 + 80067dc: 2b04 cmp r3, #4 + 80067de: bf08 it eq + 80067e0: 1aad subeq r5, r5, r2 + 80067e2: 68a3 ldr r3, [r4, #8] + 80067e4: 6922 ldr r2, [r4, #16] + 80067e6: bf0c ite eq + 80067e8: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 80067ec: 2500 movne r5, #0 + 80067ee: 4293 cmp r3, r2 + 80067f0: bfc4 itt gt + 80067f2: 1a9b subgt r3, r3, r2 + 80067f4: 18ed addgt r5, r5, r3 + 80067f6: f04f 0900 mov.w r9, #0 + 80067fa: 341a adds r4, #26 + 80067fc: 454d cmp r5, r9 + 80067fe: d11b bne.n 8006838 <_printf_common+0xd8> + 8006800: 2000 movs r0, #0 + 8006802: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8006806: 2301 movs r3, #1 + 8006808: 4652 mov r2, sl + 800680a: 4639 mov r1, r7 + 800680c: 4630 mov r0, r6 + 800680e: 47c0 blx r8 + 8006810: 3001 adds r0, #1 + 8006812: d103 bne.n 800681c <_printf_common+0xbc> + 8006814: f04f 30ff mov.w r0, #4294967295 + 8006818: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800681c: 3501 adds r5, #1 + 800681e: e7c2 b.n 80067a6 <_printf_common+0x46> + 8006820: 18e1 adds r1, r4, r3 + 8006822: 1c5a adds r2, r3, #1 + 8006824: 2030 movs r0, #48 ; 0x30 + 8006826: f881 0043 strb.w r0, [r1, #67] ; 0x43 + 800682a: 4422 add r2, r4 + 800682c: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 + 8006830: f882 1043 strb.w r1, [r2, #67] ; 0x43 + 8006834: 3302 adds r3, #2 + 8006836: e7c4 b.n 80067c2 <_printf_common+0x62> + 8006838: 2301 movs r3, #1 + 800683a: 4622 mov r2, r4 + 800683c: 4639 mov r1, r7 + 800683e: 4630 mov r0, r6 + 8006840: 47c0 blx r8 + 8006842: 3001 adds r0, #1 + 8006844: d0e6 beq.n 8006814 <_printf_common+0xb4> + 8006846: f109 0901 add.w r9, r9, #1 + 800684a: e7d7 b.n 80067fc <_printf_common+0x9c> + +0800684c <_printf_i>: + 800684c: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 8006850: 4617 mov r7, r2 + 8006852: 7e0a ldrb r2, [r1, #24] + 8006854: b085 sub sp, #20 + 8006856: 2a6e cmp r2, #110 ; 0x6e + 8006858: 4698 mov r8, r3 + 800685a: 4606 mov r6, r0 + 800685c: 460c mov r4, r1 + 800685e: 9b0c ldr r3, [sp, #48] ; 0x30 + 8006860: f101 0e43 add.w lr, r1, #67 ; 0x43 + 8006864: f000 80bc beq.w 80069e0 <_printf_i+0x194> + 8006868: d81a bhi.n 80068a0 <_printf_i+0x54> + 800686a: 2a63 cmp r2, #99 ; 0x63 + 800686c: d02e beq.n 80068cc <_printf_i+0x80> + 800686e: d80a bhi.n 8006886 <_printf_i+0x3a> + 8006870: 2a00 cmp r2, #0 + 8006872: f000 80c8 beq.w 8006a06 <_printf_i+0x1ba> + 8006876: 2a58 cmp r2, #88 ; 0x58 + 8006878: f000 808a beq.w 8006990 <_printf_i+0x144> + 800687c: f104 0542 add.w r5, r4, #66 ; 0x42 + 8006880: f884 2042 strb.w r2, [r4, #66] ; 0x42 + 8006884: e02a b.n 80068dc <_printf_i+0x90> + 8006886: 2a64 cmp r2, #100 ; 0x64 + 8006888: d001 beq.n 800688e <_printf_i+0x42> + 800688a: 2a69 cmp r2, #105 ; 0x69 + 800688c: d1f6 bne.n 800687c <_printf_i+0x30> + 800688e: 6821 ldr r1, [r4, #0] + 8006890: 681a ldr r2, [r3, #0] + 8006892: f011 0f80 tst.w r1, #128 ; 0x80 + 8006896: d023 beq.n 80068e0 <_printf_i+0x94> + 8006898: 1d11 adds r1, r2, #4 + 800689a: 6019 str r1, [r3, #0] + 800689c: 6813 ldr r3, [r2, #0] + 800689e: e027 b.n 80068f0 <_printf_i+0xa4> + 80068a0: 2a73 cmp r2, #115 ; 0x73 + 80068a2: f000 80b4 beq.w 8006a0e <_printf_i+0x1c2> + 80068a6: d808 bhi.n 80068ba <_printf_i+0x6e> + 80068a8: 2a6f cmp r2, #111 ; 0x6f + 80068aa: d02a beq.n 8006902 <_printf_i+0xb6> + 80068ac: 2a70 cmp r2, #112 ; 0x70 + 80068ae: d1e5 bne.n 800687c <_printf_i+0x30> + 80068b0: 680a ldr r2, [r1, #0] + 80068b2: f042 0220 orr.w r2, r2, #32 + 80068b6: 600a str r2, [r1, #0] + 80068b8: e003 b.n 80068c2 <_printf_i+0x76> + 80068ba: 2a75 cmp r2, #117 ; 0x75 + 80068bc: d021 beq.n 8006902 <_printf_i+0xb6> + 80068be: 2a78 cmp r2, #120 ; 0x78 + 80068c0: d1dc bne.n 800687c <_printf_i+0x30> + 80068c2: 2278 movs r2, #120 ; 0x78 + 80068c4: f884 2045 strb.w r2, [r4, #69] ; 0x45 + 80068c8: 496e ldr r1, [pc, #440] ; (8006a84 <_printf_i+0x238>) + 80068ca: e064 b.n 8006996 <_printf_i+0x14a> + 80068cc: 681a ldr r2, [r3, #0] + 80068ce: f101 0542 add.w r5, r1, #66 ; 0x42 + 80068d2: 1d11 adds r1, r2, #4 + 80068d4: 6019 str r1, [r3, #0] + 80068d6: 6813 ldr r3, [r2, #0] + 80068d8: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 80068dc: 2301 movs r3, #1 + 80068de: e0a3 b.n 8006a28 <_printf_i+0x1dc> + 80068e0: f011 0f40 tst.w r1, #64 ; 0x40 + 80068e4: f102 0104 add.w r1, r2, #4 + 80068e8: 6019 str r1, [r3, #0] + 80068ea: d0d7 beq.n 800689c <_printf_i+0x50> + 80068ec: f9b2 3000 ldrsh.w r3, [r2] + 80068f0: 2b00 cmp r3, #0 + 80068f2: da03 bge.n 80068fc <_printf_i+0xb0> + 80068f4: 222d movs r2, #45 ; 0x2d + 80068f6: 425b negs r3, r3 + 80068f8: f884 2043 strb.w r2, [r4, #67] ; 0x43 + 80068fc: 4962 ldr r1, [pc, #392] ; (8006a88 <_printf_i+0x23c>) + 80068fe: 220a movs r2, #10 + 8006900: e017 b.n 8006932 <_printf_i+0xe6> + 8006902: 6820 ldr r0, [r4, #0] + 8006904: 6819 ldr r1, [r3, #0] + 8006906: f010 0f80 tst.w r0, #128 ; 0x80 + 800690a: d003 beq.n 8006914 <_printf_i+0xc8> + 800690c: 1d08 adds r0, r1, #4 + 800690e: 6018 str r0, [r3, #0] + 8006910: 680b ldr r3, [r1, #0] + 8006912: e006 b.n 8006922 <_printf_i+0xd6> + 8006914: f010 0f40 tst.w r0, #64 ; 0x40 + 8006918: f101 0004 add.w r0, r1, #4 + 800691c: 6018 str r0, [r3, #0] + 800691e: d0f7 beq.n 8006910 <_printf_i+0xc4> + 8006920: 880b ldrh r3, [r1, #0] + 8006922: 4959 ldr r1, [pc, #356] ; (8006a88 <_printf_i+0x23c>) + 8006924: 2a6f cmp r2, #111 ; 0x6f + 8006926: bf14 ite ne + 8006928: 220a movne r2, #10 + 800692a: 2208 moveq r2, #8 + 800692c: 2000 movs r0, #0 + 800692e: f884 0043 strb.w r0, [r4, #67] ; 0x43 + 8006932: 6865 ldr r5, [r4, #4] + 8006934: 60a5 str r5, [r4, #8] + 8006936: 2d00 cmp r5, #0 + 8006938: f2c0 809c blt.w 8006a74 <_printf_i+0x228> + 800693c: 6820 ldr r0, [r4, #0] + 800693e: f020 0004 bic.w r0, r0, #4 + 8006942: 6020 str r0, [r4, #0] + 8006944: 2b00 cmp r3, #0 + 8006946: d13f bne.n 80069c8 <_printf_i+0x17c> + 8006948: 2d00 cmp r5, #0 + 800694a: f040 8095 bne.w 8006a78 <_printf_i+0x22c> + 800694e: 4675 mov r5, lr + 8006950: 2a08 cmp r2, #8 + 8006952: d10b bne.n 800696c <_printf_i+0x120> + 8006954: 6823 ldr r3, [r4, #0] + 8006956: 07da lsls r2, r3, #31 + 8006958: d508 bpl.n 800696c <_printf_i+0x120> + 800695a: 6923 ldr r3, [r4, #16] + 800695c: 6862 ldr r2, [r4, #4] + 800695e: 429a cmp r2, r3 + 8006960: bfde ittt le + 8006962: 2330 movle r3, #48 ; 0x30 + 8006964: f805 3c01 strble.w r3, [r5, #-1] + 8006968: f105 35ff addle.w r5, r5, #4294967295 + 800696c: ebae 0305 sub.w r3, lr, r5 + 8006970: 6123 str r3, [r4, #16] + 8006972: f8cd 8000 str.w r8, [sp] + 8006976: 463b mov r3, r7 + 8006978: aa03 add r2, sp, #12 + 800697a: 4621 mov r1, r4 + 800697c: 4630 mov r0, r6 + 800697e: f7ff feef bl 8006760 <_printf_common> + 8006982: 3001 adds r0, #1 + 8006984: d155 bne.n 8006a32 <_printf_i+0x1e6> + 8006986: f04f 30ff mov.w r0, #4294967295 + 800698a: b005 add sp, #20 + 800698c: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 8006990: f881 2045 strb.w r2, [r1, #69] ; 0x45 + 8006994: 493c ldr r1, [pc, #240] ; (8006a88 <_printf_i+0x23c>) + 8006996: 6822 ldr r2, [r4, #0] + 8006998: 6818 ldr r0, [r3, #0] + 800699a: f012 0f80 tst.w r2, #128 ; 0x80 + 800699e: f100 0504 add.w r5, r0, #4 + 80069a2: 601d str r5, [r3, #0] + 80069a4: d001 beq.n 80069aa <_printf_i+0x15e> + 80069a6: 6803 ldr r3, [r0, #0] + 80069a8: e002 b.n 80069b0 <_printf_i+0x164> + 80069aa: 0655 lsls r5, r2, #25 + 80069ac: d5fb bpl.n 80069a6 <_printf_i+0x15a> + 80069ae: 8803 ldrh r3, [r0, #0] + 80069b0: 07d0 lsls r0, r2, #31 + 80069b2: bf44 itt mi + 80069b4: f042 0220 orrmi.w r2, r2, #32 + 80069b8: 6022 strmi r2, [r4, #0] + 80069ba: b91b cbnz r3, 80069c4 <_printf_i+0x178> + 80069bc: 6822 ldr r2, [r4, #0] + 80069be: f022 0220 bic.w r2, r2, #32 + 80069c2: 6022 str r2, [r4, #0] + 80069c4: 2210 movs r2, #16 + 80069c6: e7b1 b.n 800692c <_printf_i+0xe0> + 80069c8: 4675 mov r5, lr + 80069ca: fbb3 f0f2 udiv r0, r3, r2 + 80069ce: fb02 3310 mls r3, r2, r0, r3 + 80069d2: 5ccb ldrb r3, [r1, r3] + 80069d4: f805 3d01 strb.w r3, [r5, #-1]! + 80069d8: 4603 mov r3, r0 + 80069da: 2800 cmp r0, #0 + 80069dc: d1f5 bne.n 80069ca <_printf_i+0x17e> + 80069de: e7b7 b.n 8006950 <_printf_i+0x104> + 80069e0: 6808 ldr r0, [r1, #0] + 80069e2: 681a ldr r2, [r3, #0] + 80069e4: 6949 ldr r1, [r1, #20] + 80069e6: f010 0f80 tst.w r0, #128 ; 0x80 + 80069ea: d004 beq.n 80069f6 <_printf_i+0x1aa> + 80069ec: 1d10 adds r0, r2, #4 + 80069ee: 6018 str r0, [r3, #0] + 80069f0: 6813 ldr r3, [r2, #0] + 80069f2: 6019 str r1, [r3, #0] + 80069f4: e007 b.n 8006a06 <_printf_i+0x1ba> + 80069f6: f010 0f40 tst.w r0, #64 ; 0x40 + 80069fa: f102 0004 add.w r0, r2, #4 + 80069fe: 6018 str r0, [r3, #0] + 8006a00: 6813 ldr r3, [r2, #0] + 8006a02: d0f6 beq.n 80069f2 <_printf_i+0x1a6> + 8006a04: 8019 strh r1, [r3, #0] + 8006a06: 2300 movs r3, #0 + 8006a08: 6123 str r3, [r4, #16] + 8006a0a: 4675 mov r5, lr + 8006a0c: e7b1 b.n 8006972 <_printf_i+0x126> + 8006a0e: 681a ldr r2, [r3, #0] + 8006a10: 1d11 adds r1, r2, #4 + 8006a12: 6019 str r1, [r3, #0] + 8006a14: 6815 ldr r5, [r2, #0] + 8006a16: 6862 ldr r2, [r4, #4] + 8006a18: 2100 movs r1, #0 + 8006a1a: 4628 mov r0, r5 + 8006a1c: f7f9 fbe0 bl 80001e0 + 8006a20: b108 cbz r0, 8006a26 <_printf_i+0x1da> + 8006a22: 1b40 subs r0, r0, r5 + 8006a24: 6060 str r0, [r4, #4] + 8006a26: 6863 ldr r3, [r4, #4] + 8006a28: 6123 str r3, [r4, #16] + 8006a2a: 2300 movs r3, #0 + 8006a2c: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 8006a30: e79f b.n 8006972 <_printf_i+0x126> + 8006a32: 6923 ldr r3, [r4, #16] + 8006a34: 462a mov r2, r5 + 8006a36: 4639 mov r1, r7 + 8006a38: 4630 mov r0, r6 + 8006a3a: 47c0 blx r8 + 8006a3c: 3001 adds r0, #1 + 8006a3e: d0a2 beq.n 8006986 <_printf_i+0x13a> + 8006a40: 6823 ldr r3, [r4, #0] + 8006a42: 079b lsls r3, r3, #30 + 8006a44: d507 bpl.n 8006a56 <_printf_i+0x20a> + 8006a46: 2500 movs r5, #0 + 8006a48: f104 0919 add.w r9, r4, #25 + 8006a4c: 68e3 ldr r3, [r4, #12] + 8006a4e: 9a03 ldr r2, [sp, #12] + 8006a50: 1a9b subs r3, r3, r2 + 8006a52: 429d cmp r5, r3 + 8006a54: db05 blt.n 8006a62 <_printf_i+0x216> + 8006a56: 68e0 ldr r0, [r4, #12] + 8006a58: 9b03 ldr r3, [sp, #12] + 8006a5a: 4298 cmp r0, r3 + 8006a5c: bfb8 it lt + 8006a5e: 4618 movlt r0, r3 + 8006a60: e793 b.n 800698a <_printf_i+0x13e> + 8006a62: 2301 movs r3, #1 + 8006a64: 464a mov r2, r9 + 8006a66: 4639 mov r1, r7 + 8006a68: 4630 mov r0, r6 + 8006a6a: 47c0 blx r8 + 8006a6c: 3001 adds r0, #1 + 8006a6e: d08a beq.n 8006986 <_printf_i+0x13a> + 8006a70: 3501 adds r5, #1 + 8006a72: e7eb b.n 8006a4c <_printf_i+0x200> + 8006a74: 2b00 cmp r3, #0 + 8006a76: d1a7 bne.n 80069c8 <_printf_i+0x17c> + 8006a78: 780b ldrb r3, [r1, #0] + 8006a7a: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 8006a7e: f104 0542 add.w r5, r4, #66 ; 0x42 + 8006a82: e765 b.n 8006950 <_printf_i+0x104> + 8006a84: 08006d3d .word 0x08006d3d + 8006a88: 08006d2c .word 0x08006d2c + +08006a8c : + 8006a8c: 4288 cmp r0, r1 + 8006a8e: b510 push {r4, lr} + 8006a90: eb01 0302 add.w r3, r1, r2 + 8006a94: d803 bhi.n 8006a9e + 8006a96: 1e42 subs r2, r0, #1 + 8006a98: 4299 cmp r1, r3 + 8006a9a: d10c bne.n 8006ab6 + 8006a9c: bd10 pop {r4, pc} + 8006a9e: 4298 cmp r0, r3 + 8006aa0: d2f9 bcs.n 8006a96 + 8006aa2: 1881 adds r1, r0, r2 + 8006aa4: 1ad2 subs r2, r2, r3 + 8006aa6: 42d3 cmn r3, r2 + 8006aa8: d100 bne.n 8006aac + 8006aaa: bd10 pop {r4, pc} + 8006aac: f813 4d01 ldrb.w r4, [r3, #-1]! + 8006ab0: f801 4d01 strb.w r4, [r1, #-1]! + 8006ab4: e7f7 b.n 8006aa6 + 8006ab6: f811 4b01 ldrb.w r4, [r1], #1 + 8006aba: f802 4f01 strb.w r4, [r2, #1]! + 8006abe: e7eb b.n 8006a98 + +08006ac0 <_realloc_r>: + 8006ac0: b5f8 push {r3, r4, r5, r6, r7, lr} + 8006ac2: 4607 mov r7, r0 + 8006ac4: 4614 mov r4, r2 + 8006ac6: 460e mov r6, r1 + 8006ac8: b921 cbnz r1, 8006ad4 <_realloc_r+0x14> + 8006aca: 4611 mov r1, r2 + 8006acc: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} + 8006ad0: f7ff bc52 b.w 8006378 <_malloc_r> + 8006ad4: b922 cbnz r2, 8006ae0 <_realloc_r+0x20> + 8006ad6: f7ff fc01 bl 80062dc <_free_r> + 8006ada: 4625 mov r5, r4 + 8006adc: 4628 mov r0, r5 + 8006ade: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8006ae0: f000 f814 bl 8006b0c <_malloc_usable_size_r> + 8006ae4: 4284 cmp r4, r0 + 8006ae6: d90f bls.n 8006b08 <_realloc_r+0x48> + 8006ae8: 4621 mov r1, r4 + 8006aea: 4638 mov r0, r7 + 8006aec: f7ff fc44 bl 8006378 <_malloc_r> + 8006af0: 4605 mov r5, r0 + 8006af2: 2800 cmp r0, #0 + 8006af4: d0f2 beq.n 8006adc <_realloc_r+0x1c> + 8006af6: 4631 mov r1, r6 + 8006af8: 4622 mov r2, r4 + 8006afa: f7ff fbdb bl 80062b4 + 8006afe: 4631 mov r1, r6 + 8006b00: 4638 mov r0, r7 + 8006b02: f7ff fbeb bl 80062dc <_free_r> + 8006b06: e7e9 b.n 8006adc <_realloc_r+0x1c> + 8006b08: 4635 mov r5, r6 + 8006b0a: e7e7 b.n 8006adc <_realloc_r+0x1c> + +08006b0c <_malloc_usable_size_r>: + 8006b0c: f851 0c04 ldr.w r0, [r1, #-4] + 8006b10: 2800 cmp r0, #0 + 8006b12: f1a0 0004 sub.w r0, r0, #4 + 8006b16: bfbc itt lt + 8006b18: 580b ldrlt r3, [r1, r0] + 8006b1a: 18c0 addlt r0, r0, r3 + 8006b1c: 4770 bx lr + ... + +08006b20 <_sbrk>: + 8006b20: 4b04 ldr r3, [pc, #16] ; (8006b34 <_sbrk+0x14>) + 8006b22: 6819 ldr r1, [r3, #0] + 8006b24: 4602 mov r2, r0 + 8006b26: b909 cbnz r1, 8006b2c <_sbrk+0xc> + 8006b28: 4903 ldr r1, [pc, #12] ; (8006b38 <_sbrk+0x18>) + 8006b2a: 6019 str r1, [r3, #0] + 8006b2c: 6818 ldr r0, [r3, #0] + 8006b2e: 4402 add r2, r0 + 8006b30: 601a str r2, [r3, #0] + 8006b32: 4770 bx lr + 8006b34: 20004010 .word 0x20004010 + 8006b38: 200049f4 .word 0x200049f4 + +08006b3c <_init>: + 8006b3c: b5f8 push {r3, r4, r5, r6, r7, lr} + 8006b3e: bf00 nop + 8006b40: bcf8 pop {r3, r4, r5, r6, r7} + 8006b42: bc08 pop {r3} + 8006b44: 469e mov lr, r3 + 8006b46: 4770 bx lr + +08006b48 <_fini>: + 8006b48: b5f8 push {r3, r4, r5, r6, r7, lr} + 8006b4a: bf00 nop + 8006b4c: bcf8 pop {r3, r4, r5, r6, r7} + 8006b4e: bc08 pop {r3} + 8006b50: 469e mov lr, r3 + 8006b52: 4770 bx lr diff --git a/F4-Gyro-RTOS/Debug/F4-Gyro-RTOS.map b/F4-Gyro-RTOS/Debug/F4-Gyro-RTOS.map new file mode 100644 index 0000000..088c1a7 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/F4-Gyro-RTOS.map @@ -0,0 +1,4568 @@ +Archive member included to satisfy reference by file (symbol) + +c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-init.o) + startup\startup_stm32f407xx.o (__libc_init_array) +c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-malloc.o) + Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Src\usbd_cdc.o (malloc) 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0x00010000 rw +FLASH 0x08000000 0x00100000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7e-m/fpu/crti.o +LOAD c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7e-m/fpu/crtbegin.o +LOAD Drivers\BSP\Components\cs43l22\cs43l22.o +LOAD Drivers\BSP\Components\exc7200\exc7200.o +LOAD Drivers\BSP\Components\ft6x06\ft6x06.o +LOAD Drivers\BSP\Components\ili9325\ili9325.o +LOAD Drivers\BSP\Components\ili9341\ili9341.o +LOAD Drivers\BSP\Components\l3gd20\l3gd20.o +LOAD Drivers\BSP\Components\lis302dl\lis302dl.o +LOAD Drivers\BSP\Components\lis3dsh\lis3dsh.o +LOAD Drivers\BSP\Components\ls016b8uy\ls016b8uy.o +LOAD Drivers\BSP\Components\lsm303dlhc\lsm303dlhc.o +LOAD Drivers\BSP\Components\mfxstm32l152\mfxstm32l152.o +LOAD Drivers\BSP\Components\otm8009a\otm8009a.o +LOAD Drivers\BSP\Components\ov2640\ov2640.o +LOAD Drivers\BSP\Components\s5k5cag\s5k5cag.o +LOAD Drivers\BSP\Components\st7735\st7735.o +LOAD Drivers\BSP\Components\st7789h2\st7789h2.o +LOAD Drivers\BSP\Components\stmpe1600\stmpe1600.o +LOAD Drivers\BSP\Components\stmpe811\stmpe811.o +LOAD Drivers\BSP\Components\ts3510\ts3510.o +LOAD Drivers\BSP\Components\wm8994\wm8994.o +LOAD Drivers\BSP\STM32F4-Discovery\stm32f4_discovery.o +LOAD Drivers\BSP\STM32F4-Discovery\stm32f4_discovery_accelerometer.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2s_ex.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd_ex.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.o +LOAD Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.o +LOAD Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Src\usbd_cdc.o +LOAD Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_core.o +LOAD Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ctlreq.o +LOAD Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ioreq.o +LOAD Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS\cmsis_os.o +LOAD Middlewares\Third_Party\FreeRTOS\Source\croutine.o +LOAD Middlewares\Third_Party\FreeRTOS\Source\event_groups.o +LOAD Middlewares\Third_Party\FreeRTOS\Source\list.o +LOAD Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.o +LOAD Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.o +LOAD Middlewares\Third_Party\FreeRTOS\Source\queue.o +LOAD Middlewares\Third_Party\FreeRTOS\Source\tasks.o +LOAD Middlewares\Third_Party\FreeRTOS\Source\timers.o +LOAD Src\freertos.o +LOAD Src\main.o +LOAD Src\stm32f4xx_hal_msp.o +LOAD Src\stm32f4xx_hal_timebase_TIM.o +LOAD Src\stm32f4xx_it.o +LOAD Src\system_stm32f4xx.o +LOAD Src\usb_device.o +LOAD Src\usbd_cdc_if.o +LOAD Src\usbd_conf.o +LOAD Src\usbd_desc.o +LOAD startup\startup_stm32f407xx.o + 0x00000080 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9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a +LOAD c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libnosys.a +END GROUP +START GROUP +LOAD c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7e-m/fpu\libgcc.a +LOAD c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a +LOAD c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libnosys.a +END GROUP +LOAD c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7e-m/fpu/crtend.o +LOAD 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Src\usbd_conf.o + 0x0800603c USBD_LL_Start + .text.USBD_LL_OpenEP + 0x08006058 0x20 Src\usbd_conf.o + 0x08006058 USBD_LL_OpenEP + .text.USBD_LL_CloseEP + 0x08006078 0x1c Src\usbd_conf.o + 0x08006078 USBD_LL_CloseEP + .text.USBD_LL_StallEP + 0x08006094 0x1c Src\usbd_conf.o + 0x08006094 USBD_LL_StallEP + .text.USBD_LL_ClearStallEP + 0x080060b0 0x1c Src\usbd_conf.o + 0x080060b0 USBD_LL_ClearStallEP + .text.USBD_LL_IsStallEP + 0x080060cc 0x26 Src\usbd_conf.o + 0x080060cc USBD_LL_IsStallEP + *fill* 0x080060f2 0x2 + .text.USBD_LL_SetUSBAddress + 0x080060f4 0x1c Src\usbd_conf.o + 0x080060f4 USBD_LL_SetUSBAddress + .text.USBD_LL_Transmit + 0x08006110 0x1c Src\usbd_conf.o + 0x08006110 USBD_LL_Transmit + .text.USBD_LL_PrepareReceive + 0x0800612c 0x1c Src\usbd_conf.o + 0x0800612c USBD_LL_PrepareReceive + .text.USBD_LL_GetRxDataSize + 0x08006148 0xc Src\usbd_conf.o + 0x08006148 USBD_LL_GetRxDataSize + .text.USBD_FS_DeviceDescriptor + 0x08006154 0xc Src\usbd_desc.o + 0x08006154 USBD_FS_DeviceDescriptor + .text.USBD_FS_LangIDStrDescriptor + 0x08006160 0xc Src\usbd_desc.o + 0x08006160 USBD_FS_LangIDStrDescriptor + .text.USBD_FS_ManufacturerStrDescriptor + 0x0800616c 0x1c Src\usbd_desc.o + 0x0800616c USBD_FS_ManufacturerStrDescriptor + .text.USBD_FS_ProductStrDescriptor + 0x08006188 0x1c Src\usbd_desc.o + 0x08006188 USBD_FS_ProductStrDescriptor + .text.USBD_FS_SerialStrDescriptor + 0x080061a4 0x1c Src\usbd_desc.o + 0x080061a4 USBD_FS_SerialStrDescriptor + .text.USBD_FS_ConfigStrDescriptor + 0x080061c0 0x1c Src\usbd_desc.o + 0x080061c0 USBD_FS_ConfigStrDescriptor + .text.USBD_FS_InterfaceStrDescriptor + 0x080061dc 0x1c Src\usbd_desc.o + 0x080061dc USBD_FS_InterfaceStrDescriptor + .text.Reset_Handler + 0x080061f8 0x50 startup\startup_stm32f407xx.o + 0x080061f8 Reset_Handler + .text.Default_Handler + 0x08006248 0x2 startup\startup_stm32f407xx.o + 0x08006248 RTC_Alarm_IRQHandler + 0x08006248 HASH_RNG_IRQHandler + 0x08006248 EXTI2_IRQHandler + 0x08006248 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USART6_IRQHandler + 0x08006248 USART3_IRQHandler + 0x08006248 CAN1_RX1_IRQHandler + 0x08006248 UART5_IRQHandler + 0x08006248 DMA2_Stream0_IRQHandler + 0x08006248 TIM4_IRQHandler + 0x08006248 I2C1_EV_IRQHandler + 0x08006248 DMA1_Stream6_IRQHandler + 0x08006248 DMA1_Stream1_IRQHandler + 0x08006248 UART4_IRQHandler + 0x08006248 TIM3_IRQHandler + 0x08006248 RCC_IRQHandler + 0x08006248 TIM8_BRK_TIM12_IRQHandler + 0x08006248 Default_Handler + 0x08006248 EXTI15_10_IRQHandler + 0x08006248 ADC_IRQHandler + 0x08006248 DMA1_Stream7_IRQHandler + 0x08006248 TIM7_IRQHandler + 0x08006248 CAN2_TX_IRQHandler + 0x08006248 TIM5_IRQHandler + 0x08006248 DMA2_Stream7_IRQHandler + 0x08006248 I2C3_EV_IRQHandler + 0x08006248 EXTI9_5_IRQHandler + 0x08006248 RTC_WKUP_IRQHandler + 0x08006248 ETH_WKUP_IRQHandler + 0x08006248 SPI2_IRQHandler + 0x08006248 OTG_HS_EP1_IN_IRQHandler + 0x08006248 MemManage_Handler + 0x08006248 DMA1_Stream0_IRQHandler + 0x08006248 CAN1_TX_IRQHandler + 0x08006248 EXTI4_IRQHandler + 0x08006248 FSMC_IRQHandler + 0x08006248 ETH_IRQHandler + 0x08006248 OTG_HS_EP1_OUT_IRQHandler + 0x08006248 WWDG_IRQHandler + 0x08006248 TIM2_IRQHandler + 0x08006248 OTG_FS_WKUP_IRQHandler + 0x08006248 TIM1_TRG_COM_TIM11_IRQHandler + 0x08006248 OTG_HS_IRQHandler + 0x08006248 EXTI1_IRQHandler + 0x08006248 USART2_IRQHandler + 0x08006248 I2C2_ER_IRQHandler + 0x08006248 DMA2_Stream1_IRQHandler + 0x08006248 CAN1_SCE_IRQHandler + 0x08006248 FLASH_IRQHandler + 0x08006248 DMA2_Stream4_IRQHandler + 0x08006248 BusFault_Handler + 0x08006248 USART1_IRQHandler + 0x08006248 SPI3_IRQHandler + 0x08006248 DMA1_Stream4_IRQHandler + 0x08006248 I2C1_ER_IRQHandler + 0x08006248 DMA2_Stream6_IRQHandler + 0x08006248 DMA1_Stream3_IRQHandler + *fill* 0x0800624a 0x2 + .text.__libc_init_array + 0x0800624c 0x48 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-init.o) + 0x0800624c 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0x080062da 0x2 + .text._free_r 0x080062dc 0x9c c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-nano-freer.o) + 0x080062dc _free_r + .text._malloc_r + 0x08006378 0xbc c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-nano-mallocr.o) + 0x08006378 _malloc_r + .text._sbrk_r 0x08006434 0x20 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-sbrkr.o) + 0x08006434 _sbrk_r + .text.snprintf + 0x08006454 0x68 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-snprintf.o) + 0x08006454 sniprintf + 0x08006454 snprintf + .text.__malloc_lock + 0x080064bc 0x2 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-mlock.o) + 0x080064bc __malloc_lock + .text.__malloc_unlock + 0x080064be 0x2 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-mlock.o) + 0x080064be __malloc_unlock + .text.__ssputs_r + 0x080064c0 0xb6 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-nano-svfprintf.o) + 0x080064c0 __ssputs_r + *fill* 0x08006576 0x2 + .text._svfprintf_r + 0x08006578 0x1e8 c:/users/administrator/desktop/st/atollic/truestudio for stm32 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c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-nano-reallocr.o) + 0x08006ac0 _realloc_r + .text._malloc_usable_size_r + 0x08006b0c 0x12 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-nano-msizer.o) + 0x08006b0c _malloc_usable_size_r + *fill* 0x08006b1e 0x2 + .text._sbrk 0x08006b20 0x1c c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libnosys.a(sbrk.o) + 0x08006b20 _sbrk + *(.glue_7) + .glue_7 0x08006b3c 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x08006b3c 0x0 linker stubs + *(.eh_frame) + .eh_frame 0x08006b3c 0x0 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7e-m/fpu/crtbegin.o + *(.init) + .init 0x08006b3c 0x4 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7e-m/fpu/crti.o + 0x08006b3c _init + .init 0x08006b40 0x8 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7e-m/fpu/crtn.o + *(.fini) + .fini 0x08006b48 0x4 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7e-m/fpu/crti.o + 0x08006b48 _fini + .fini 0x08006b4c 0x8 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7e-m/fpu/crtn.o + 0x08006b54 . = ALIGN (0x4) + 0x08006b54 _etext = . + +.vfp11_veneer 0x08006b54 0x0 + .vfp11_veneer 0x08006b54 0x0 linker stubs + +.v4_bx 0x08006b54 0x0 + .v4_bx 0x08006b54 0x0 linker stubs + +.iplt 0x08006b54 0x0 + .iplt 0x08006b54 0x0 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7e-m/fpu/crtbegin.o + +.rodata 0x08006b54 0x1fc + 0x08006b54 . = ALIGN (0x4) + *(.rodata) + .rodata 0x08006b54 0xa8 Src\main.o + *(.rodata*) + .rodata.CSWTCH.23 + 0x08006bfc 0x64 Drivers\BSP\Components\lis3dsh\lis3dsh.o + .rodata.GPIO_PIN + 0x08006c60 0x8 Drivers\BSP\STM32F4-Discovery\stm32f4_discovery.o + 0x08006c60 GPIO_PIN + .rodata.vTaskStartScheduler.str1.1 + 0x08006c68 0x5 Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .rodata.USB_Task.str1.1 + 0x08006c6d 0x22 Src\main.o + .rodata.str1.1 + 0x08006c8f 0xe Src\main.o + .rodata.AHBPrescTable + 0x08006c9d 0x10 Src\system_stm32f4xx.o + 0x08006c9d AHBPrescTable + .rodata.APBPrescTable + 0x08006cad 0x8 Src\system_stm32f4xx.o + 0x08006cad APBPrescTable + .rodata.CSWTCH.39 + 0x08006cb5 0x4 Src\usbd_conf.o + .rodata.USBD_LL_Init.str1.1 + 0x08006cb9 0x13 Src\usbd_conf.o + .rodata.USBD_FS_ConfigStrDescriptor.str1.1 + 0x08006ccc 0xb Src\usbd_desc.o + .rodata.USBD_FS_InterfaceStrDescriptor.str1.1 + 0x08006cd7 0xe Src\usbd_desc.o + .rodata.USBD_FS_ManufacturerStrDescriptor.str1.1 + 0x08006ce5 0x13 Src\usbd_desc.o + .rodata.USBD_FS_ProductStrDescriptor.str1.1 + 0x08006cf8 0x16 Src\usbd_desc.o + .rodata.USBD_FS_SerialStrDescriptor.str1.1 + 0x08006d0e 0xd Src\usbd_desc.o + .rodata._svfprintf_r.str1.1 + 0x08006d1b 0x11 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-nano-svfprintf.o) + .rodata._printf_i.str1.1 + 0x08006d2c 0x22 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-nano-vfprintf_i.o) + 0x08006d50 . = ALIGN (0x4) + *fill* 0x08006d4e 0x2 + +.ARM.extab + *(.ARM.extab* .gnu.linkonce.armextab.*) + +.ARM 0x08006d50 0x8 + 0x08006d50 __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx 0x08006d50 0x8 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7e-m/fpu\libgcc.a(_udivmoddi4.o) + 0x08006d58 __exidx_end = . + +.rel.dyn 0x08006d58 0x0 + .rel.iplt 0x08006d58 0x0 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7e-m/fpu/crtbegin.o + +.preinit_array 0x08006d58 0x0 + 0x08006d58 PROVIDE (__preinit_array_start, .) + *(.preinit_array*) + 0x08006d58 PROVIDE (__preinit_array_end, .) + +.init_array 0x08006d58 0x4 + 0x08006d58 PROVIDE (__init_array_start, .) + *(SORT(.init_array.*)) + *(.init_array*) + .init_array 0x08006d58 0x4 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7e-m/fpu/crtbegin.o + 0x08006d5c PROVIDE (__init_array_end, .) + +.fini_array 0x08006d5c 0x4 + [!provide] PROVIDE (__fini_array_start, .) + *(SORT(.fini_array.*)) + *(.fini_array*) + .fini_array 0x08006d5c 0x4 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7e-m/fpu/crtbegin.o + [!provide] PROVIDE (__fini_array_end, .) + 0x08006d60 _sidata = LOADADDR (.data) + +.data 0x20000000 0x244 load address 0x08006d60 + 0x20000000 . = ALIGN (0x4) + 0x20000000 _sdata = . + *(.data) + *(.data*) + .data.Lis302dlDrv + 0x20000000 0x34 Drivers\BSP\Components\lis302dl\lis302dl.o + 0x20000000 Lis302dlDrv + .data.Lis3dshDrv + 0x20000034 0x34 Drivers\BSP\Components\lis3dsh\lis3dsh.o + 0x20000034 Lis3dshDrv + .data.GPIO_PORT + 0x20000068 0x10 Drivers\BSP\STM32F4-Discovery\stm32f4_discovery.o + 0x20000068 GPIO_PORT + .data.SpixTimeout + 0x20000078 0x4 Drivers\BSP\STM32F4-Discovery\stm32f4_discovery.o + 0x20000078 SpixTimeout + .data.uwTickFreq + 0x2000007c 0x1 Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.o + 0x2000007c uwTickFreq + *fill* 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Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .bss.uxTaskNumber + 0x20003f84 0x4 Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .bss.uxTopReadyPriority + 0x20003f88 0x4 Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .bss.xDelayedTaskList1 + 0x20003f8c 0x14 Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .bss.xDelayedTaskList2 + 0x20003fa0 0x14 Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .bss.xIdleTaskHandle + 0x20003fb4 0x4 Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .bss.xNextTaskUnblockTime + 0x20003fb8 0x4 Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .bss.xNumOfOverflows + 0x20003fbc 0x4 Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .bss.xPendingReadyList + 0x20003fc0 0x14 Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .bss.xSchedulerRunning + 0x20003fd4 0x4 Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .bss.xSuspendedTaskList + 0x20003fd8 0x14 Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .bss.xTasksWaitingTermination + 0x20003fec 0x14 Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .bss.xTickCount + 0x20004000 0x4 Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .bss.xYieldPending + 0x20004004 0x4 Middlewares\Third_Party\FreeRTOS\Source\tasks.o + .bss.__malloc_free_list + 0x20004008 0x4 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-nano-mallocr.o) + 0x20004008 __malloc_free_list + .bss.__malloc_sbrk_start + 0x2000400c 0x4 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libc_nano.a(lib_a-nano-mallocr.o) + 0x2000400c __malloc_sbrk_start + .bss.heap_end.5239 + 0x20004010 0x4 c:/users/administrator/desktop/st/atollic/truestudio for stm32 9.0.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7e-m/fpu\libnosys.a(sbrk.o) + *(COMMON) + COMMON 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b/F4-Gyro-RTOS/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su @@ -0,0 +1,7 @@ +usbd_ctlreq.c:716:6:USBD_CtlError.constprop 8 static +usbd_ctlreq.c:119:21:USBD_StdDevReq 24 static +usbd_ctlreq.c:170:21:USBD_StdItfReq 16 static +usbd_ctlreq.c:207:21:USBD_StdEPReq 16 static +usbd_ctlreq.c:698:6:USBD_ParseSetupRequest 0 static +usbd_ctlreq.c:716:6:USBD_CtlError 8 static +usbd_ctlreq.c:732:6:USBD_GetString 12 static diff --git a/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/.gitignore b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/.gitignore new file mode 100644 index 0000000..9e390ea --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/.gitignore @@ -0,0 +1,2 @@ +/RVDS/ +/MemMang/ diff --git a/F4-Gyro-RTOS/Debug/Src/main.su b/F4-Gyro-RTOS/Debug/Src/main.su index d78abc5..512b52c 100644 --- a/F4-Gyro-RTOS/Debug/Src/main.su +++ b/F4-Gyro-RTOS/Debug/Src/main.su @@ -1,8 +1,8 @@ -main.c:191:6:SystemClock_Config 112 static +main.c:193:6:SystemClock_Config 112 static main.c:108:5:main 88 static -main.c:408:6:GYRO_Task 32 static -main.c:523:6:StartTask02 8 static -main.c:485:6:USB_Task 192 static -main.c:505:6:StartTask01 8 static -main.c:546:6:HAL_TIM_PeriodElapsedCallback 0 static -main.c:566:6:_Error_Handler 0 static +main.c:417:6:GYRO_Task 32 static +main.c:532:6:StartTask02 8 static +main.c:494:6:USB_Task 192 static +main.c:514:6:StartTask01 8 static +main.c:555:6:HAL_TIM_PeriodElapsedCallback 0 static +main.c:574:6:_Error_Handler 0 static diff --git a/F4-Gyro-RTOS/Debug/Src/usbd_cdc_if.su b/F4-Gyro-RTOS/Debug/Src/usbd_cdc_if.su index 40f27d5..ec157f9 100644 --- a/F4-Gyro-RTOS/Debug/Src/usbd_cdc_if.su +++ b/F4-Gyro-RTOS/Debug/Src/usbd_cdc_if.su @@ -1,5 +1,5 @@ -usbd_cdc_if.c:197:15:CDC_DeInit_FS 0 static -usbd_cdc_if.c:211:15:CDC_Control_FS 0 static -usbd_cdc_if.c:291:15:CDC_Receive_FS 8 static -usbd_cdc_if.c:183:15:CDC_Init_FS 8 static -usbd_cdc_if.c:311:9:CDC_Transmit_FS 8 static +usbd_cdc_if.c:198:15:CDC_DeInit_FS 0 static +usbd_cdc_if.c:307:15:CDC_Receive_FS 8 static +usbd_cdc_if.c:184:15:CDC_Init_FS 8 static +usbd_cdc_if.c:212:15:CDC_Control_FS 8 static +usbd_cdc_if.c:327:9:CDC_Transmit_FS 8 static diff --git a/F4-Gyro-RTOS/Debug/Src/usbd_conf.su b/F4-Gyro-RTOS/Debug/Src/usbd_conf.su new file mode 100644 index 0000000..a33b434 --- /dev/null +++ b/F4-Gyro-RTOS/Debug/Src/usbd_conf.su @@ -0,0 +1,28 @@ +usbd_conf.c:95:6:HAL_PCD_MspInit 40 static +usbd_conf.c:141:6:HAL_PCD_MspDeInit 8 static +usbd_conf.c:173:6:HAL_PCD_SetupStageCallback 0 static +usbd_conf.c:184:6:HAL_PCD_DataOutStageCallback 0 static +usbd_conf.c:195:6:HAL_PCD_DataInStageCallback 0 static +usbd_conf.c:205:6:HAL_PCD_SOFCallback 0 static +usbd_conf.c:215:6:HAL_PCD_ResetCallback 8 static +usbd_conf.c:245:6:HAL_PCD_SuspendCallback 8 static +usbd_conf.c:266:6:HAL_PCD_ResumeCallback 0 static +usbd_conf.c:280:6:HAL_PCD_ISOOUTIncompleteCallback 0 static +usbd_conf.c:291:6:HAL_PCD_ISOINIncompleteCallback 0 static +usbd_conf.c:301:6:HAL_PCD_ConnectCallback 0 static +usbd_conf.c:311:6:HAL_PCD_DisconnectCallback 0 static +usbd_conf.c:325:20:USBD_LL_Init 8 static +usbd_conf.c:361:20:USBD_LL_DeInit 8 static +usbd_conf.c:393:20:USBD_LL_Start 8 static +usbd_conf.c:425:20:USBD_LL_Stop 8 static +usbd_conf.c:460:20:USBD_LL_OpenEP 8 static +usbd_conf.c:493:20:USBD_LL_CloseEP 8 static +usbd_conf.c:526:20:USBD_LL_FlushEP 8 static +usbd_conf.c:559:20:USBD_LL_StallEP 8 static +usbd_conf.c:592:20:USBD_LL_ClearStallEP 8 static +usbd_conf.c:625:9:USBD_LL_IsStallEP 0 static +usbd_conf.c:645:20:USBD_LL_SetUSBAddress 8 static +usbd_conf.c:680:20:USBD_LL_Transmit 8 static +usbd_conf.c:715:20:USBD_LL_PrepareReceive 8 static +usbd_conf.c:748:10:USBD_LL_GetRxDataSize 8 static +usbd_conf.c:796:6:USBD_LL_Delay 0 static diff --git a/F4-Gyro-RTOS/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_audio.c b/F4-Gyro-RTOS/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_audio.c deleted file mode 100644 index fa2e2d7..0000000 --- a/F4-Gyro-RTOS/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_audio.c +++ /dev/null @@ -1,1140 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4_discovery_audio.c - * @author MCD Application Team - * @brief This file provides the Audio driver for the STM32F4-Discovery - * board. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*============================================================================== - User NOTES -1. How To use this driver: --------------------------- - - This driver supports STM32F4xx devices on STM32F4-Discovery Kit: - a) to play an audio file (all functions names start by BSP_AUDIO_OUT_xxx) - b) to record an audio file through MP45DT02, ST MEMS (all functions names start by AUDIO_IN_xxx) - -a) PLAY A FILE: -============== - + Call the function BSP_AUDIO_OUT_Init( - OutputDevice: physical output mode (OUTPUT_DEVICE_SPEAKER, - OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_AUTO or - OUTPUT_DEVICE_BOTH) - Volume: initial volume to be set (0 is min (mute), 100 is max (100%) - AudioFreq: Audio frequency in Hz (8000, 16000, 22500, 32000 ...) - this parameter is relative to the audio file/stream type. - ) - This function configures all the hardware required for the audio application (codec, I2C, I2S, - GPIOs, DMA and interrupt if needed). This function returns 0 if configuration is OK. - If the returned value is different from 0 or the function is stuck then the communication with - the codec (try to un-plug the power or reset device in this case). - - OUTPUT_DEVICE_SPEAKER: only speaker will be set as output for the audio stream. - - OUTPUT_DEVICE_HEADPHONE: only headphones will be set as output for the audio stream. - - OUTPUT_DEVICE_AUTO: Selection of output device is made through external switch (implemented - into the audio jack on the discovery board). When the Headphone is connected it is used - as output. When the headphone is disconnected from the audio jack, the output is - automatically switched to Speaker. - - OUTPUT_DEVICE_BOTH: both Speaker and Headphone are used as outputs for the audio stream - at the same time. - + Call the function BSP_AUDIO_OUT_Play( - pBuffer: pointer to the audio data file address - Size: size of the buffer to be sent in Bytes - ) - to start playing (for the first time) from the audio file/stream. - + Call the function BSP_AUDIO_OUT_Pause() to pause playing - + Call the function BSP_AUDIO_OUT_Resume() to resume playing. - Note. After calling BSP_AUDIO_OUT_Pause() function for pause, only BSP_AUDIO_OUT_Resume() should be called - for resume (it is not allowed to call BSP_AUDIO_OUT_Play() in this case). - Note. This function should be called only when the audio file is played or paused (not stopped). - + For each mode, you may need to implement the relative callback functions into your code. - The Callback functions are named BSP_AUDIO_OUT_XXXCallBack() and only their prototypes are declared in - the stm32f4_discovery_audio.h file. (refer to the example for more details on the callbacks implementations) - + To Stop playing, to modify the volume level, the frequency or to mute, use the functions - BSP_AUDIO_OUT_Stop(), BSP_AUDIO_OUT_SetVolume(), AUDIO_OUT_SetFrequency() BSP_AUDIO_OUT_SetOutputMode and BSP_AUDIO_OUT_SetMute(). - + The driver API and the callback functions are at the end of the stm32f4_discovery_audio.h file. - -Driver architecture: --------------------- - + This driver provide the High Audio Layer: consists of the function API exported in the stm32f4_discovery_audio.h file - (BSP_AUDIO_OUT_Init(), BSP_AUDIO_OUT_Play() ...) - + This driver provide also the Media Access Layer (MAL): which consists of functions allowing to access the media containing/ - providing the audio file/stream. These functions are also included as local functions into - the stm32f4_discovery_audio.c file (I2S3_Init()...) - -Known Limitations: -------------------- - 1- When using the Speaker, if the audio file quality is not high enough, the speaker output - may produce high and uncomfortable noise level. To avoid this issue, to use speaker - output properly, try to increase audio file sampling rate (typically higher than 48KHz). - This operation will lead to larger file size. - 2- Communication with the audio codec (through I2C) may be corrupted if it is interrupted by some - user interrupt routines (in this case, interrupts could be disabled just before the start of - communication then re-enabled when it is over). Note that this communication is only done at - the configuration phase (BSP_AUDIO_OUT_Init() or BSP_AUDIO_OUT_Stop()) and when Volume control modification is - performed (BSP_AUDIO_OUT_SetVolume() or BSP_AUDIO_OUT_SetMute()or BSP_AUDIO_OUT_SetOutputMode()). - When the audio data is played, no communication is required with the audio codec. - 3- Parsing of audio file is not implemented (in order to determine audio file properties: Mono/Stereo, Data size, - File size, Audio Frequency, Audio Data header size ...). The configuration is fixed for the given audio file. - 4- Supports only Stereo audio streaming. To play mono audio streams, each data should be sent twice - on the I2S or should be duplicated on the source buffer. Or convert the stream in stereo before playing. - 5- Supports only 16-bits audio data size. - -b) RECORD A FILE: -================ - + Call the function BSP_AUDIO_IN_Init( - AudioFreq: Audio frequency in Hz (8000, 16000, 22500, 32000 ...) - ) - This function configures all the hardware required for the audio application (I2S, - GPIOs, DMA and interrupt if needed). This function returns 0 if configuration is OK. - - + Call the function BSP_AUDIO_IN_Record( - pbuf Main buffer pointer for the recorded data storing - size Current size of the recorded buffer - ) - to start recording from the microphone. - - + User needs to implement user callbacks to retrieve data saved in the record buffer - (AUDIO_IN_RxHalfCpltCallback/BSP_AUDIO_IN_ReceiveComplete_CallBack) - - + Call the function AUDIO_IN_STOP() to stop recording - -==============================================================================*/ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4_discovery_audio.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY - * @{ - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO STM32F4 DISCOVERY AUDIO - * @brief This file includes the low layer audio driver available on STM32F4-Discovery - * discovery board. - * @{ - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_Private_Types STM32F4 DISCOVERY AUDIO Private Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_Private_Defines STM32F4 DISCOVERY AUDIO Private Defines - * @{ - */ -/* These PLL parameters are valid when the f(VCO clock) = 1Mhz */ -const uint32_t I2SFreq[8] = {8000, 11025, 16000, 22050, 32000, 44100, 48000, 96000}; -const uint32_t I2SPLLN[8] = {256, 429, 213, 429, 426, 271, 258, 344}; -const uint32_t I2SPLLR[8] = {5, 4, 4, 4, 4, 6, 3, 1}; -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_Private_Macros STM32F4 DISCOVERY AUDIO Private Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_Private_Variables STM32F4 DISCOVERY AUDIO Private Variables - * @{ - */ -/*##### PLAY #####*/ -static AUDIO_DrvTypeDef *pAudioDrv; -I2S_HandleTypeDef hAudioOutI2s; - -/*### RECORDER ###*/ -I2S_HandleTypeDef hAudioInI2s; - -/* PDM filters params */ -PDM_Filter_Handler_t PDM_FilterHandler[2]; -PDM_Filter_Config_t PDM_FilterConfig[2]; - -__IO uint16_t AudioInVolume = DEFAULT_AUDIO_IN_VOLUME; -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_Private_Function_Prototypes STM32F4 DISCOVERY AUDIO Private Function Prototypes - * @{ - */ -static uint8_t I2S3_Init(uint32_t AudioFreq); -static uint8_t I2S2_Init(uint32_t AudioFreq); -static void PDMDecoder_Init(uint32_t AudioFreq, uint32_t ChnlNbrIn, uint32_t ChnlNbrOut); -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_OUT_Private_Functions STM32F4 DISCOVERY AUDIO OUT Private Functions - * @{ - */ - -/** - * @brief Configures the audio peripherals. - * @param OutputDevice: OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE, - * OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO . - * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max)) - * @param AudioFreq: Audio frequency used to play the audio stream. - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_OUT_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq) -{ - uint8_t ret = AUDIO_OK; - - /* PLL clock is set depending by the AudioFreq (44.1khz vs 48khz groups) */ - BSP_AUDIO_OUT_ClockConfig(&hAudioOutI2s, AudioFreq, NULL); - - /* I2S data transfer preparation: - Prepare the Media to be used for the audio transfer from memory to I2S peripheral */ - hAudioOutI2s.Instance = I2S3; - if(HAL_I2S_GetState(&hAudioOutI2s) == HAL_I2S_STATE_RESET) - { - /* Init the I2S MSP: this __weak function can be redefined by the application*/ - BSP_AUDIO_OUT_MspInit(&hAudioOutI2s, NULL); - } - - /* I2S data transfer preparation: - Prepare the Media to be used for the audio transfer from memory to I2S peripheral */ - /* Configure the I2S peripheral */ - if(I2S3_Init(AudioFreq) != AUDIO_OK) - { - ret = AUDIO_ERROR; - } - - if(ret == AUDIO_OK) - { - /* Retieve audio codec identifier */ - if(((cs43l22_drv.ReadID(AUDIO_I2C_ADDRESS)) & CS43L22_ID_MASK) == CS43L22_ID) - { - /* Initialize the audio driver structure */ - pAudioDrv = &cs43l22_drv; - } - else - { - ret = AUDIO_ERROR; - } - } - - if(ret == AUDIO_OK) - { - pAudioDrv->Init(AUDIO_I2C_ADDRESS, OutputDevice, Volume, AudioFreq); - } - - return ret; -} - -/** - * @brief Starts playing audio stream from a data buffer for a determined size. - * @param pBuffer: Pointer to the buffer - * @param Size: Number of audio data BYTES. - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_OUT_Play(uint16_t* pBuffer, uint32_t Size) -{ - /* Call the audio Codec Play function */ - if(pAudioDrv->Play(AUDIO_I2C_ADDRESS, pBuffer, Size) != 0) - { - return AUDIO_ERROR; - } - else - { - /* Update the Media layer and enable it for play */ - HAL_I2S_Transmit_DMA(&hAudioOutI2s, pBuffer, DMA_MAX(Size/AUDIODATA_SIZE)); - - /* Return AUDIO_OK when all operations are correctly done */ - return AUDIO_OK; - } -} - -/** - * @brief Sends n-Bytes on the I2S interface. - * @param pData: Pointer to data address - * @param Size: Number of data to be written - */ -void BSP_AUDIO_OUT_ChangeBuffer(uint16_t *pData, uint16_t Size) -{ - HAL_I2S_Transmit_DMA(&hAudioOutI2s, pData, Size); -} - -/** - * @brief Pauses the audio file stream. In case of using DMA, the DMA Pause - * feature is used. - * WARNING: When calling BSP_AUDIO_OUT_Pause() function for pause, only the - * BSP_AUDIO_OUT_Resume() function should be called for resume (use of BSP_AUDIO_OUT_Play() - * function for resume could lead to unexpected behavior). - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_OUT_Pause(void) -{ - /* Call the Audio Codec Pause/Resume function */ - if(pAudioDrv->Pause(AUDIO_I2C_ADDRESS) != 0) - { - return AUDIO_ERROR; - } - else - { - /* Call the Media layer pause function */ - HAL_I2S_DMAPause(&hAudioOutI2s); - - /* Return AUDIO_OK when all operations are correctly done */ - return AUDIO_OK; - } -} - -/** - * @brief Resumes the audio file streaming. - * WARNING: When calling BSP_AUDIO_OUT_Pause() function for pause, only - * BSP_AUDIO_OUT_Resume() function should be called for resume (use of BSP_AUDIO_OUT_Play() - * function for resume could lead to unexpected behavior). - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_OUT_Resume(void) -{ - /* Call the Audio Codec Pause/Resume function */ - if(pAudioDrv->Resume(AUDIO_I2C_ADDRESS) != 0) - { - return AUDIO_ERROR; - } - else - { - /* Call the Media layer resume function */ - HAL_I2S_DMAResume(&hAudioOutI2s); - - /* Return AUDIO_OK when all operations are correctly done */ - return AUDIO_OK; - } -} - -/** - * @brief Stops audio playing and Power down the Audio Codec. - * @param Option: could be one of the following parameters - * - CODEC_PDWN_HW: completely shut down the codec (physically). - * Then need to reconfigure the Codec after power on. - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_OUT_Stop(uint32_t Option) -{ - /* Call DMA Stop to disable DMA stream before stopping codec */ - HAL_I2S_DMAStop(&hAudioOutI2s); - - /* Call Audio Codec Stop function */ - if(pAudioDrv->Stop(AUDIO_I2C_ADDRESS, Option) != 0) - { - return AUDIO_ERROR; - } - else - { - if(Option == CODEC_PDWN_HW) - { - /* Wait at least 1ms */ - HAL_Delay(1); - - /* Reset the pin */ - HAL_GPIO_WritePin(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, GPIO_PIN_RESET); - } - - /* Return AUDIO_OK when all operations are correctly done */ - return AUDIO_OK; - } -} - -/** - * @brief Controls the current audio volume level. - * @param Volume: Volume level to be set in percentage from 0% to 100% (0 for - * Mute and 100 for Max volume level). - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_OUT_SetVolume(uint8_t Volume) -{ - /* Call the codec volume control function with converted volume value */ - if(pAudioDrv->SetVolume(AUDIO_I2C_ADDRESS, Volume) != 0) - { - return AUDIO_ERROR; - } - else - { - /* Return AUDIO_OK when all operations are correctly done */ - return AUDIO_OK; - } -} - -/** - * @brief Enables or disables the MUTE mode by software - * @param Cmd: could be AUDIO_MUTE_ON to mute sound or AUDIO_MUTE_OFF to - * unmute the codec and restore previous volume level. - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_OUT_SetMute(uint32_t Cmd) -{ - /* Call the Codec Mute function */ - if(pAudioDrv->SetMute(AUDIO_I2C_ADDRESS, Cmd) != 0) - { - return AUDIO_ERROR; - } - else - { - /* Return AUDIO_OK when all operations are correctly done */ - return AUDIO_OK; - } -} - -/** - * @brief Switch dynamically (while audio file is played) the output target - * (speaker or headphone). - * @note This function modifies a global variable of the audio codec driver: OutputDev. - * @param Output: specifies the audio output target: OUTPUT_DEVICE_SPEAKER, - * OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_OUT_SetOutputMode(uint8_t Output) -{ - /* Call the Codec output Device function */ - if(pAudioDrv->SetOutputMode(AUDIO_I2C_ADDRESS, Output) != 0) - { - return AUDIO_ERROR; - } - else - { - /* Return AUDIO_OK when all operations are correctly done */ - return AUDIO_OK; - } -} - -/** - * @brief Update the audio frequency. - * @param AudioFreq: Audio frequency used to play the audio stream. - * @note This API should be called after the BSP_AUDIO_OUT_Init() to adjust the - * audio frequency. - */ -void BSP_AUDIO_OUT_SetFrequency(uint32_t AudioFreq) -{ - /* PLL clock is set depending by the AudioFreq (44.1khz vs 48khz groups) */ - BSP_AUDIO_OUT_ClockConfig(&hAudioOutI2s, AudioFreq, NULL); - - /* Update the I2S audio frequency configuration */ - I2S3_Init(AudioFreq); -} - -/** - * @brief Tx Transfer completed callbacks. - * @param hi2s: I2S handle - */ -void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) -{ - if(hi2s->Instance == I2S3) - { - /* Call the user function which will manage directly transfer complete */ - BSP_AUDIO_OUT_TransferComplete_CallBack(); - } -} - -/** - * @brief Tx Half Transfer completed callbacks. - * @param hi2s: I2S handle - */ -void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) -{ - if(hi2s->Instance == I2S3) - { - /* Manage the remaining file size and new address offset: This function should - be coded by user (its prototype is already declared in stm32f4_discovery_audio.h) */ - BSP_AUDIO_OUT_HalfTransfer_CallBack(); - } -} - -/** - * @brief Clock Config. - * @param hi2s: might be required to set audio peripheral predivider if any. - * @param AudioFreq: Audio frequency used to play the audio stream. - * @note This API is called by BSP_AUDIO_OUT_Init() and BSP_AUDIO_OUT_SetFrequency() - * Being __weak it can be overwritten by the application - * @param Params : pointer on additional configuration parameters, can be NULL. - */ -__weak void BSP_AUDIO_OUT_ClockConfig(I2S_HandleTypeDef *hi2s, uint32_t AudioFreq, void *Params) -{ - RCC_PeriphCLKInitTypeDef rccclkinit; - uint8_t index = 0, freqindex = 0xFF; - - for(index = 0; index < 8; index++) - { - if(I2SFreq[index] == AudioFreq) - { - freqindex = index; - } - } - /* Enable PLLI2S clock */ - HAL_RCCEx_GetPeriphCLKConfig(&rccclkinit); - /* PLLI2S_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */ - if ((freqindex & 0x7) == 0) - { - /* I2S clock config - PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) - I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ - rccclkinit.PeriphClockSelection = RCC_PERIPHCLK_I2S; - rccclkinit.PLLI2S.PLLI2SN = I2SPLLN[freqindex]; - rccclkinit.PLLI2S.PLLI2SR = I2SPLLR[freqindex]; - HAL_RCCEx_PeriphCLKConfig(&rccclkinit); - } - else - { - /* I2S clock config - PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) - I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ - rccclkinit.PeriphClockSelection = RCC_PERIPHCLK_I2S; - rccclkinit.PLLI2S.PLLI2SN = 258; - rccclkinit.PLLI2S.PLLI2SR = 3; - HAL_RCCEx_PeriphCLKConfig(&rccclkinit); - } -} - -/** - * @brief AUDIO OUT I2S MSP Init. - * @param hi2s: might be required to set audio peripheral predivider if any. - * @param Params : pointer on additional configuration parameters, can be NULL. - */ -__weak void BSP_AUDIO_OUT_MspInit(I2S_HandleTypeDef *hi2s, void *Params) -{ - static DMA_HandleTypeDef hdma_i2sTx; - GPIO_InitTypeDef GPIO_InitStruct; - - /* Enable I2S3 clock */ - I2S3_CLK_ENABLE(); - - /*** Configure the GPIOs ***/ - /* Enable I2S GPIO clocks */ - I2S3_SCK_SD_CLK_ENABLE(); - I2S3_WS_CLK_ENABLE(); - - /* I2S3 pins configuration: WS, SCK and SD pins ----------------------------*/ - GPIO_InitStruct.Pin = I2S3_SCK_PIN | I2S3_SD_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FAST; - GPIO_InitStruct.Alternate = I2S3_SCK_SD_WS_AF; - HAL_GPIO_Init(I2S3_SCK_SD_GPIO_PORT, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = I2S3_WS_PIN ; - HAL_GPIO_Init(I2S3_WS_GPIO_PORT, &GPIO_InitStruct); - - /* I2S3 pins configuration: MCK pin */ - I2S3_MCK_CLK_ENABLE(); - GPIO_InitStruct.Pin = I2S3_MCK_PIN; - HAL_GPIO_Init(I2S3_MCK_GPIO_PORT, &GPIO_InitStruct); - - /* Enable the I2S DMA clock */ - I2S3_DMAx_CLK_ENABLE(); - - if(hi2s->Instance == I2S3) - { - /* Configure the hdma_i2sTx handle parameters */ - hdma_i2sTx.Init.Channel = I2S3_DMAx_CHANNEL; - hdma_i2sTx.Init.Direction = DMA_MEMORY_TO_PERIPH; - hdma_i2sTx.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_i2sTx.Init.MemInc = DMA_MINC_ENABLE; - hdma_i2sTx.Init.PeriphDataAlignment = I2S3_DMAx_PERIPH_DATA_SIZE; - hdma_i2sTx.Init.MemDataAlignment = I2S3_DMAx_MEM_DATA_SIZE; - hdma_i2sTx.Init.Mode = DMA_NORMAL; - hdma_i2sTx.Init.Priority = DMA_PRIORITY_HIGH; - hdma_i2sTx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; - hdma_i2sTx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - hdma_i2sTx.Init.MemBurst = DMA_MBURST_SINGLE; - hdma_i2sTx.Init.PeriphBurst = DMA_PBURST_SINGLE; - - hdma_i2sTx.Instance = I2S3_DMAx_STREAM; - - /* Associate the DMA handle */ - __HAL_LINKDMA(hi2s, hdmatx, hdma_i2sTx); - - /* Deinitialize the Stream for new transfer */ - HAL_DMA_DeInit(&hdma_i2sTx); - - /* Configure the DMA Stream */ - HAL_DMA_Init(&hdma_i2sTx); - } - - /* I2S DMA IRQ Channel configuration */ - HAL_NVIC_SetPriority(I2S3_DMAx_IRQ, AUDIO_OUT_IRQ_PREPRIO, 0); - HAL_NVIC_EnableIRQ(I2S3_DMAx_IRQ); -} - -/** - * @brief De-Initializes BSP_AUDIO_OUT MSP. - * @param hi2s: might be required to set audio peripheral predivider if any. - * @param Params : pointer on additional configuration parameters, can be NULL. - */ -__weak void BSP_AUDIO_OUT_MspDeInit(I2S_HandleTypeDef *hi2s, void *Params) -{ - GPIO_InitTypeDef GPIO_InitStruct; - - /* I2S DMA IRQ Channel deactivation */ - HAL_NVIC_DisableIRQ(I2S3_DMAx_IRQ); - - if(hi2s->Instance == I2S3) - { - /* Deinitialize the Stream for new transfer */ - HAL_DMA_DeInit(hi2s->hdmatx); - } - - /* Disable I2S block */ - __HAL_I2S_DISABLE(hi2s); - - /* CODEC_I2S pins configuration: SCK and SD pins */ - GPIO_InitStruct.Pin = I2S3_SCK_PIN | I2S3_SD_PIN; - HAL_GPIO_DeInit(I2S3_SCK_SD_GPIO_PORT, GPIO_InitStruct.Pin); - - /* CODEC_I2S pins configuration: WS pin */ - GPIO_InitStruct.Pin = I2S3_WS_PIN; - HAL_GPIO_DeInit(I2S3_WS_GPIO_PORT, GPIO_InitStruct.Pin); - - /* CODEC_I2S pins configuration: MCK pin */ - GPIO_InitStruct.Pin = I2S3_MCK_PIN; - HAL_GPIO_DeInit(I2S3_MCK_GPIO_PORT, GPIO_InitStruct.Pin); - - /* Disable I2S clock */ - I2S3_CLK_DISABLE(); - - /* GPIO pins clock and DMA clock can be shut down in the applic - by surcgarging this __weak function */ -} - -/** - * @brief Manages the DMA full Transfer complete event. - */ -__weak void BSP_AUDIO_OUT_TransferComplete_CallBack(void) -{ -} - -/** - * @brief Manages the DMA Half Transfer complete event. - */ -__weak void BSP_AUDIO_OUT_HalfTransfer_CallBack(void) -{ -} - -/** - * @brief Manages the DMA FIFO error event. - */ -__weak void BSP_AUDIO_OUT_Error_CallBack(void) -{ -} - -/******************************************************************************* - Static Functions -*******************************************************************************/ - -/** - * @brief Initializes the Audio Codec audio interface (I2S). - * @param AudioFreq: Audio frequency to be configured for the I2S peripheral. - */ -static uint8_t I2S3_Init(uint32_t AudioFreq) -{ - /* Initialize the hAudioOutI2s Instance parameter */ - hAudioOutI2s.Instance = I2S3; - - /* Disable I2S block */ - __HAL_I2S_DISABLE(&hAudioOutI2s); - - /* I2S3 peripheral configuration */ - hAudioOutI2s.Init.AudioFreq = AudioFreq; - hAudioOutI2s.Init.ClockSource = I2S_CLOCK_PLL; - hAudioOutI2s.Init.CPOL = I2S_CPOL_LOW; - hAudioOutI2s.Init.DataFormat = I2S_DATAFORMAT_16B; - hAudioOutI2s.Init.MCLKOutput = I2S_MCLKOUTPUT_ENABLE; - hAudioOutI2s.Init.Mode = I2S_MODE_MASTER_TX; - hAudioOutI2s.Init.Standard = I2S_STANDARD; - /* Initialize the I2S peripheral with the structure above */ - if(HAL_I2S_Init(&hAudioOutI2s) != HAL_OK) - { - return AUDIO_ERROR; - } - else - { - return AUDIO_OK; - } -} - -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_IN_Private_Functions STM32F4 DISCOVERY AUDIO IN Private Functions - * @{ - */ - -/** - * @brief Initializes wave recording. - * @param AudioFreq: Audio frequency to be configured for the I2S peripheral. - * @param BitRes: Audio frequency to be configured for the I2S peripheral. - * @param ChnlNbr: Audio frequency to be configured for the I2S peripheral. - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_IN_Init(uint32_t AudioFreq, uint32_t BitRes, uint32_t ChnlNbr) -{ - - /* Configure PLL clock */ - BSP_AUDIO_IN_ClockConfig(&hAudioInI2s, AudioFreq, NULL); - - /* Configure the PDM library */ - /* On STM32F4-Discovery a single microphone is mounted, samples are duplicated - to make stereo audio streams */ - PDMDecoder_Init(AudioFreq, ChnlNbr, 2); - - /* Configure the I2S peripheral */ - hAudioInI2s.Instance = I2S2; - if(HAL_I2S_GetState(&hAudioInI2s) == HAL_I2S_STATE_RESET) - { - /* Initialize the I2S Msp: this __weak function can be rewritten by the application */ - BSP_AUDIO_IN_MspInit(&hAudioInI2s, NULL); - } - - /* Configure the I2S2 */ - I2S2_Init(AudioFreq); - - /* Return AUDIO_OK when all operations are correctly done */ - return AUDIO_OK; -} - -/** - * @brief Starts audio recording. - * @param pbuf: Main buffer pointer for the recorded data storing - * @param size: Current size of the recorded buffer - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_IN_Record(uint16_t* pbuf, uint32_t size) -{ - uint32_t ret = AUDIO_ERROR; - - /* Start the process receive DMA */ - HAL_I2S_Receive_DMA(&hAudioInI2s, pbuf, size); - - /* Return AUDIO_OK when all operations are correctly done */ - ret = AUDIO_OK; - - return ret; -} - -/** - * @brief Stops audio recording. - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_IN_Stop(void) -{ - uint32_t ret = AUDIO_ERROR; - - /* Call the Media layer pause function */ - HAL_I2S_DMAStop(&hAudioInI2s); - - /* Return AUDIO_OK when all operations are correctly done */ - ret = AUDIO_OK; - - return ret; -} - -/** - * @brief Pauses the audio file stream. - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_IN_Pause(void) -{ - /* Call the Media layer pause function */ - HAL_I2S_DMAPause(&hAudioInI2s); - - /* Return AUDIO_OK when all operations are correctly done */ - return AUDIO_OK; -} - -/** - * @brief Resumes the audio file stream. - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_IN_Resume(void) -{ - /* Call the Media layer pause/resume function */ - HAL_I2S_DMAResume(&hAudioInI2s); - - /* Return AUDIO_OK when all operations are correctly done */ - return AUDIO_OK; -} - -/** - * @brief Controls the audio in volume level. - * @param Volume: Volume level to be set in percentage from 0% to 100% (0 for - * Mute and 100 for Max volume level). - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_IN_SetVolume(uint8_t Volume) -{ - /* Set the Global variable AudioInVolume */ - AudioInVolume = Volume; - - /* Return AUDIO_OK when all operations are correctly done */ - return AUDIO_OK; -} - -/** - * @brief Converts audio format from PDM to PCM. - * @param PDMBuf: Pointer to data PDM buffer - * @param PCMBuf: Pointer to data PCM buffer - * @retval AUDIO_OK if correct communication, else wrong communication - */ -uint8_t BSP_AUDIO_IN_PDMToPCM(uint16_t *PDMBuf, uint16_t *PCMBuf) -{ - uint16_t AppPDM[INTERNAL_BUFF_SIZE/2]; - uint32_t index = 0; - - /* PDM Demux */ - for(index = 0; indexInstance == I2S2) - { - /* Configure the hdma_i2sRx handle parameters */ - hdma_i2sRx.Init.Channel = I2S2_DMAx_CHANNEL; - hdma_i2sRx.Init.Direction = DMA_PERIPH_TO_MEMORY; - hdma_i2sRx.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_i2sRx.Init.MemInc = DMA_MINC_ENABLE; - hdma_i2sRx.Init.PeriphDataAlignment = I2S2_DMAx_PERIPH_DATA_SIZE; - hdma_i2sRx.Init.MemDataAlignment = I2S2_DMAx_MEM_DATA_SIZE; - hdma_i2sRx.Init.Mode = DMA_CIRCULAR; - hdma_i2sRx.Init.Priority = DMA_PRIORITY_HIGH; - hdma_i2sRx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - hdma_i2sRx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - hdma_i2sRx.Init.MemBurst = DMA_MBURST_SINGLE; - hdma_i2sRx.Init.PeriphBurst = DMA_MBURST_SINGLE; - - hdma_i2sRx.Instance = I2S2_DMAx_STREAM; - - /* Associate the DMA handle */ - __HAL_LINKDMA(hi2s, hdmarx, hdma_i2sRx); - - /* Deinitialize the Stream for new transfer */ - HAL_DMA_DeInit(&hdma_i2sRx); - - /* Configure the DMA Stream */ - HAL_DMA_Init(&hdma_i2sRx); - } - - /* I2S DMA IRQ Channel configuration */ - HAL_NVIC_SetPriority(I2S2_DMAx_IRQ, AUDIO_IN_IRQ_PREPRIO, 0); - HAL_NVIC_EnableIRQ(I2S2_DMAx_IRQ); -} - -/** - * @brief DeInitializes BSP_AUDIO_IN MSP. - * @param hi2s: I2S handle - * @param Params : pointer on additional configuration parameters, can be NULL. - */ -__weak void BSP_AUDIO_IN_MspDeInit(I2S_HandleTypeDef *hi2s, void *Params) -{ - GPIO_InitTypeDef gpio_init_structure; - - /* I2S DMA IRQ Channel deactivation */ - HAL_NVIC_DisableIRQ(I2S2_DMAx_IRQ); - - if(hi2s->Instance == I2S2) - { - /* Deinitialize the Stream for new transfer */ - HAL_DMA_DeInit(hi2s->hdmarx); - } - - /* Disable I2S block */ - __HAL_I2S_DISABLE(hi2s); - - /* Disable pins: SCK and SD pins */ - gpio_init_structure.Pin = I2S2_SCK_PIN; - HAL_GPIO_DeInit(I2S2_SCK_GPIO_PORT, gpio_init_structure.Pin); - gpio_init_structure.Pin = I2S2_MOSI_PIN; - HAL_GPIO_DeInit(I2S2_MOSI_GPIO_PORT, gpio_init_structure.Pin); - - /* Disable I2S clock */ - I2S2_CLK_DISABLE(); - - /* GPIO pins clock and DMA clock can be shut down in the applic - by surcgarging this __weak function */ -} - -/** - * @brief User callback when record buffer is filled. - */ -__weak void BSP_AUDIO_IN_TransferComplete_CallBack(void) -{ - /* This function should be implemented by the user application. - It is called into this driver when the current buffer is filled - to prepare the next buffer pointer and its size. */ -} - -/** - * @brief Manages the DMA Half Transfer complete event. - */ -__weak void BSP_AUDIO_IN_HalfTransfer_CallBack(void) -{ - /* This function should be implemented by the user application. - It is called into this driver when the current buffer is filled - to prepare the next buffer pointer and its size. */ -} - -/** - * @brief Audio IN Error callback function. - */ -__weak void BSP_AUDIO_IN_Error_Callback(void) -{ - /* This function is called when an Interrupt due to transfer error on or peripheral - error occurs. */ -} - -/******************************************************************************* - Static Functions -*******************************************************************************/ - -/** - * @brief Initializes the PDM library. - * @param AudioFreq: Audio sampling frequency - * @param ChnlNbrIn: Number of input audio channels in the PDM buffer - * @param ChnlNbrOut: Number of desired output audio channels in the resulting PCM buffer - * Number of audio channels (1: mono; 2: stereo) - */ -static void PDMDecoder_Init(uint32_t AudioFreq, uint32_t ChnlNbrIn, uint32_t ChnlNbrOut) -{ - uint32_t index = 0; - - /* Enable CRC peripheral to unlock the PDM library */ - __HAL_RCC_CRC_CLK_ENABLE(); - - for(index = 0; index < ChnlNbrIn; index++) - { - /* Init PDM filters */ - PDM_FilterHandler[index].bit_order = PDM_FILTER_BIT_ORDER_LSB; - PDM_FilterHandler[index].endianness = PDM_FILTER_ENDIANNESS_LE; - PDM_FilterHandler[index].high_pass_tap = 2122358088; - PDM_FilterHandler[index].out_ptr_channels = ChnlNbrOut; - PDM_FilterHandler[index].in_ptr_channels = ChnlNbrIn; - PDM_Filter_Init((PDM_Filter_Handler_t *)(&PDM_FilterHandler[index])); - - /* PDM lib config phase */ - PDM_FilterConfig[index].output_samples_number = AudioFreq/1000; - PDM_FilterConfig[index].mic_gain = 24; - PDM_FilterConfig[index].decimation_factor = PDM_FILTER_DEC_FACTOR_64; - PDM_Filter_setConfig((PDM_Filter_Handler_t *)&PDM_FilterHandler[index], &PDM_FilterConfig[index]); - } -} - -/** - * @brief Initializes the Audio Codec audio interface (I2S) - * @note This function assumes that the I2S input clock (through PLL_R in - * Devices RevA/Z and through dedicated PLLI2S_R in Devices RevB/Y) - * is already configured and ready to be used. - * @param AudioFreq: Audio frequency to be configured for the I2S peripheral. - */ -static uint8_t I2S2_Init(uint32_t AudioFreq) -{ - /* Initialize the hAudioInI2s Instance parameter */ - hAudioInI2s.Instance = I2S2; - - /* Disable I2S block */ - __HAL_I2S_DISABLE(&hAudioInI2s); - - /* I2S2 peripheral configuration */ - hAudioInI2s.Init.AudioFreq = 2 * AudioFreq; - hAudioInI2s.Init.ClockSource = I2S_CLOCK_PLL; - hAudioInI2s.Init.CPOL = I2S_CPOL_HIGH; - hAudioInI2s.Init.DataFormat = I2S_DATAFORMAT_16B; - hAudioInI2s.Init.MCLKOutput = I2S_MCLKOUTPUT_DISABLE; - hAudioInI2s.Init.Mode = I2S_MODE_MASTER_RX; - hAudioInI2s.Init.Standard = I2S_STANDARD_LSB; - - /* Initialize the I2S peripheral with the structure above */ - if(HAL_I2S_Init(&hAudioInI2s) != HAL_OK) - { - return AUDIO_ERROR; - } - else - { - return AUDIO_OK; - } -} - -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_IN_OUT_Private_Functions STM32F4 DISCOVERY AUDIO IN OUT Private Functions - * @{ - */ - -/** - * @brief I2S error callbacks. - * @param hi2s: I2S handle - */ -void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) -{ - /* Manage the error generated on DMA FIFO: This function - should be coded by user (its prototype is already declared in stm32f4_discovery_audio.h) */ - if(hi2s->Instance == I2S3) - { - BSP_AUDIO_OUT_Error_CallBack(); - } - if(hi2s->Instance == I2S2) - { - BSP_AUDIO_IN_Error_Callback(); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/F4-Gyro-RTOS/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_audio.h b/F4-Gyro-RTOS/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_audio.h deleted file mode 100644 index 86939a0..0000000 --- a/F4-Gyro-RTOS/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_audio.h +++ /dev/null @@ -1,274 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4_discovery_audio.h - * @author MCD Application Team - * @brief This file contains the common defines and functions prototypes for - * stm32f4_discovery_audio.c driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4_DISCOVERY_AUDIO_H -#define __STM32F4_DISCOVERY_AUDIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* Include audio component Driver */ -#include "../Components/cs43l22/cs43l22.h" - -#include "stm32f4_discovery.h" -#include "../../../Middlewares/ST/STM32_Audio/Addons/PDM/Inc/pdm2pcm_glo.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY_AUDIO - * @{ - */ - - -/** @defgroup STM32F4_DISCOVERY_AUDIO_Exported_Types STM32F4 DISCOVERY AUDIO Exported Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_OUT_Exported_Constants STM32F4 DISCOVERY AUDIO OUT Exported Constants - * @{ - */ - -/*------------------------------------------------------------------------------ - AUDIO OUT CONFIGURATION -------------------------------------------------------------------------------*/ - -/* I2S peripheral configuration defines */ -#define I2S3 SPI3 -#define I2S3_CLK_ENABLE() __HAL_RCC_SPI3_CLK_ENABLE() -#define I2S3_CLK_DISABLE() __HAL_RCC_SPI3_CLK_DISABLE() -#define I2S3_SCK_SD_WS_AF GPIO_AF6_SPI3 -#define I2S3_SCK_SD_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() -#define I2S3_MCK_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() -#define I2S3_WS_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define I2S3_WS_PIN GPIO_PIN_4 -#define I2S3_SCK_PIN GPIO_PIN_10 -#define I2S3_SD_PIN GPIO_PIN_12 -#define I2S3_MCK_PIN GPIO_PIN_7 -#define I2S3_SCK_SD_GPIO_PORT GPIOC -#define I2S3_WS_GPIO_PORT GPIOA -#define I2S3_MCK_GPIO_PORT GPIOC - -/* I2S DMA Stream definitions */ -#define I2S3_DMAx_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE() -#define I2S3_DMAx_CLK_DISABLE() __HAL_RCC_DMA1_CLK_DISABLE() -#define I2S3_DMAx_STREAM DMA1_Stream7 -#define I2S3_DMAx_CHANNEL DMA_CHANNEL_0 -#define I2S3_DMAx_IRQ DMA1_Stream7_IRQn -#define I2S3_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD -#define I2S3_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD -#define DMA_MAX_SZE 0xFFFF - -#define I2S3_IRQHandler DMA1_Stream7_IRQHandler - -/* Select the interrupt preemption priority and subpriority for the DMA interrupt */ -#define AUDIO_OUT_IRQ_PREPRIO 0x0E /* Select the preemption priority level(0 is the highest) */ - -/*------------------------------------------------------------------------------ - AUDIO IN CONFIGURATION -------------------------------------------------------------------------------*/ -/* SPI Configuration defines */ -#define I2S2 SPI2 -#define I2S2_CLK_ENABLE() __HAL_RCC_SPI2_CLK_ENABLE() -#define I2S2_CLK_DISABLE() __HAL_RCC_SPI2_CLK_DISABLE() -#define I2S2_SCK_PIN GPIO_PIN_10 -#define I2S2_SCK_GPIO_PORT GPIOB -#define I2S2_SCK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() -#define I2S2_SCK_AF GPIO_AF5_SPI2 - -#define I2S2_MOSI_PIN GPIO_PIN_3 -#define I2S2_MOSI_GPIO_PORT GPIOC -#define I2S2_MOSI_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() -#define I2S2_MOSI_AF GPIO_AF5_SPI2 - -/* I2S DMA Stream Rx definitions */ -#define I2S2_DMAx_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE() -#define I2S2_DMAx_CLK_DISABLE() __HAL_RCC_DMA1_CLK_DISABLE() -#define I2S2_DMAx_STREAM DMA1_Stream3 -#define I2S2_DMAx_CHANNEL DMA_CHANNEL_0 -#define I2S2_DMAx_IRQ DMA1_Stream3_IRQn -#define I2S2_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD -#define I2S2_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD - -#define I2S2_IRQHandler DMA1_Stream3_IRQHandler - -/* Select the interrupt preemption priority and subpriority for the IT/DMA interrupt */ -#define AUDIO_IN_IRQ_PREPRIO 0x0F /* Select the preemption priority level(0 is the highest) */ - -/*------------------------------------------------------------------------------ - CONFIGURATION: Audio Driver Configuration parameters -------------------------------------------------------------------------------*/ - -#define AUDIODATA_SIZE 2 /* 16-bits audio data size */ - -/* Audio status definition */ -#define AUDIO_OK 0 -#define AUDIO_ERROR 1 -#define AUDIO_TIMEOUT 2 - -/* AudioFreq * DataSize (2 bytes) * NumChannels (Stereo: 2) */ -#define DEFAULT_AUDIO_IN_FREQ I2S_AUDIOFREQ_16K -#define DEFAULT_AUDIO_IN_BIT_RESOLUTION 16 -#define DEFAULT_AUDIO_IN_CHANNEL_NBR 1 /* Mono = 1, Stereo = 2 */ -#define DEFAULT_AUDIO_IN_VOLUME 64 - -/* PDM buffer input size */ -#define INTERNAL_BUFF_SIZE 128*DEFAULT_AUDIO_IN_FREQ/16000*DEFAULT_AUDIO_IN_CHANNEL_NBR -/* PCM buffer output size */ -#define PCM_OUT_SIZE DEFAULT_AUDIO_IN_FREQ/1000 -#define CHANNEL_DEMUX_MASK 0x55 - -/*------------------------------------------------------------------------------ - OPTIONAL Configuration defines parameters -------------------------------------------------------------------------------*/ - -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_Exported_Variables STM32F4 DISCOVERY AUDIO Exported Variables - * @{ - */ -extern __IO uint16_t AudioInVolume; -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_Exported_Macros STM32F4 DISCOVERY AUDIO Exported Macros - * @{ - */ -#define DMA_MAX(_X_) (((_X_) <= DMA_MAX_SZE)? (_X_):DMA_MAX_SZE) -#define HTONS(A) ((((uint16_t)(A) & 0xff00) >> 8) | (((uint16_t)(A) & 0x00ff) << 8)) -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_OUT_Exported_Functions STM32F4 DISCOVERY AUDIO OUT Exported Functions - * @{ - */ -uint8_t BSP_AUDIO_OUT_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq); -uint8_t BSP_AUDIO_OUT_Play(uint16_t* pBuffer, uint32_t Size); -void BSP_AUDIO_OUT_ChangeBuffer(uint16_t *pData, uint16_t Size); -uint8_t BSP_AUDIO_OUT_Pause(void); -uint8_t BSP_AUDIO_OUT_Resume(void); -uint8_t BSP_AUDIO_OUT_Stop(uint32_t Option); -uint8_t BSP_AUDIO_OUT_SetVolume(uint8_t Volume); -void BSP_AUDIO_OUT_SetFrequency(uint32_t AudioFreq); -uint8_t BSP_AUDIO_OUT_SetMute(uint32_t Cmd); -uint8_t BSP_AUDIO_OUT_SetOutputMode(uint8_t Output); - -/* User Callbacks: user has to implement these functions in his code if they are needed. */ -/* This function is called when the requested data has been completely transferred. */ -void BSP_AUDIO_OUT_TransferComplete_CallBack(void); - -/* This function is called when half of the requested buffer has been transferred. */ -void BSP_AUDIO_OUT_HalfTransfer_CallBack(void); - -/* This function is called when an Interrupt due to transfer error on or peripheral - error occurs. */ -void BSP_AUDIO_OUT_Error_CallBack(void); - -/* These function can be modified in case the current settings (e.g. DMA stream) - need to be changed for specific application needs */ -void BSP_AUDIO_OUT_ClockConfig(I2S_HandleTypeDef *hi2s, uint32_t AudioFreq, void *Params); -void BSP_AUDIO_OUT_MspInit(I2S_HandleTypeDef *hi2s, void *Params); -void BSP_AUDIO_OUT_MspDeInit(I2S_HandleTypeDef *hi2s, void *Params); - -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_IN_Exported_Functions STM32F4 DISCOVERY AUDIO IN Exported Functions - * @{ - */ -uint8_t BSP_AUDIO_IN_Init(uint32_t AudioFreq, uint32_t BitRes, uint32_t ChnlNbr); -uint8_t BSP_AUDIO_IN_Record(uint16_t *pData, uint32_t Size); -uint8_t BSP_AUDIO_IN_Stop(void); -uint8_t BSP_AUDIO_IN_Pause(void); -uint8_t BSP_AUDIO_IN_Resume(void); -uint8_t BSP_AUDIO_IN_SetVolume(uint8_t Volume); -uint8_t BSP_AUDIO_IN_PDMToPCM(uint16_t *PDMBuf, uint16_t *PCMBuf); -/* User Callbacks: user has to implement these functions in his code if they are needed. */ -/* This function should be implemented by the user application. - It is called into this driver when the current buffer is filled to prepare the next - buffer pointer and its size. */ -void BSP_AUDIO_IN_TransferComplete_CallBack(void); -void BSP_AUDIO_IN_HalfTransfer_CallBack(void); - -/* This function is called when an Interrupt due to transfer error on or peripheral - error occurs. */ -void BSP_AUDIO_IN_Error_Callback(void); - -/* These function can be modified in case the current settings (e.g. DMA stream) - need to be changed for specific application needs */ -void BSP_AUDIO_IN_ClockConfig(I2S_HandleTypeDef *hi2s, uint32_t AudioFreq, void *Params); -void BSP_AUDIO_IN_MspInit(I2S_HandleTypeDef *hi2s, void *Params); -void BSP_AUDIO_IN_MspDeInit(I2S_HandleTypeDef *hi2s, void *Params); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4_DISCOVERY_AUDIO_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/F4-Gyro-RTOS/F4-Gyro-RTOS.elf.launch b/F4-Gyro-RTOS/F4-Gyro-RTOS.elf.launch index 279f38f..4f1d72e 100644 --- a/F4-Gyro-RTOS/F4-Gyro-RTOS.elf.launch +++ b/F4-Gyro-RTOS/F4-Gyro-RTOS.elf.launch @@ -25,7 +25,7 @@ - + diff --git a/F4-Gyro-RTOS/F4-Gyro-RTOS.ioc b/F4-Gyro-RTOS/F4-Gyro-RTOS.ioc index a5aebe9..b26e997 100644 --- a/F4-Gyro-RTOS/F4-Gyro-RTOS.ioc +++ b/F4-Gyro-RTOS/F4-Gyro-RTOS.ioc @@ -301,14 +301,14 @@ ProjectManager.KeepUserCode=true ProjectManager.LastFirmware=true ProjectManager.LibraryCopy=1 ProjectManager.MainLocation=Src -ProjectManager.PreviousToolchain= +ProjectManager.PreviousToolchain=TrueSTUDIO ProjectManager.ProjectBuild=false ProjectManager.ProjectFileName=F4-Gyro-RTOS.ioc ProjectManager.ProjectName=F4-Gyro-RTOS ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=MDK-ARM V5 +ProjectManager.TargetToolchain=TrueSTUDIO ProjectManager.ToolChainLocation= -ProjectManager.UnderRoot=false +ProjectManager.UnderRoot=true ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_I2C1_Init-I2C1-false-HAL-true,4-MX_I2S3_Init-I2S3-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-true RCC.48MHZClocksFreq_Value=48000000 RCC.AHBFreq_Value=168000000 diff --git a/F4-Gyro-RTOS/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h b/F4-Gyro-RTOS/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h index cd0551d..d937b2e 100644 --- a/F4-Gyro-RTOS/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h +++ b/F4-Gyro-RTOS/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h @@ -54,7 +54,7 @@ #define CDC_CMD_EP 0x82 /* EP2 for CDC commands */ /* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ -#define CDC_DATA_HS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ +#define CDC_DATA_HS_MAX_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */ #define CDC_DATA_FS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ #define CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */ diff --git a/F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c b/F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c deleted file mode 100644 index 959adfc..0000000 --- a/F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c +++ /dev/null @@ -1,791 +0,0 @@ -/* - FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM CM4F port. - *----------------------------------------------------------*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -#ifndef __TARGET_FPU_VFP - #error This port can only be used when the project options are configured to enable hardware floating point support. -#endif - -#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 - #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html -#endif - -#ifndef configSYSTICK_CLOCK_HZ - #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ - /* Ensure the SysTick is clocked at the same frequency as the core. */ - #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) -#else - /* The way the SysTick is clocked is not modified in case it is not the same - as the core. */ - #define portNVIC_SYSTICK_CLK_BIT ( 0 ) -#endif - -/* The __weak attribute does not work as you might expect with the Keil tools -so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if -the application writer wants to provide their own implementation of -vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION -is defined. */ -#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION - #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0 -#endif - -/* Constants required to manipulate the core. Registers first... */ -#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) ) -#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) ) -#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) ) -#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) ) -/* ...then bits in the registers. */ -#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) -#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) -#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) -#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) -#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) - -/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 -r0p1 port. */ -#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) ) -#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) -#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) - -#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) -#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) - -/* Constants required to check the validity of an interrupt priority. */ -#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) -#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) -#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) ) -#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) -#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) -#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) -#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) -#define portPRIGROUP_SHIFT ( 8UL ) - -/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ -#define portVECTACTIVE_MASK ( 0xFFUL ) - -/* Constants required to manipulate the VFP. */ -#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ -#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) - -/* Constants required to set up the initial stack. */ -#define portINITIAL_XPSR ( 0x01000000 ) -#define portINITIAL_EXEC_RETURN ( 0xfffffffd ) - -/* The systick is a 24-bit counter. */ -#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) - -/* A fiddle factor to estimate the number of SysTick counts that would have -occurred while the SysTick counter is stopped during tickless idle -calculations. */ -#define portMISSED_COUNTS_FACTOR ( 45UL ) - -/* For strict compliance with the Cortex-M spec the task start address should -have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ -#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) - -/* Each task maintains its own interrupt status in the critical nesting -variable. */ -static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; - -/* - * Setup the timer to generate the tick interrupts. The implementation in this - * file is weak to allow application writers to change the timer used to - * generate the tick interrupt. - */ -void vPortSetupTimerInterrupt( void ); - -/* - * Exception handlers. - */ -void xPortPendSVHandler( void ); -void xPortSysTickHandler( void ); -void vPortSVCHandler( void ); - -/* - * Start first task is a separate function so it can be tested in isolation. - */ -static void prvStartFirstTask( void ); - -/* - * Functions defined in portasm.s to enable the VFP. - */ -static void prvEnableVFP( void ); - -/* - * Used to catch tasks that attempt to return from their implementing function. - */ -static void prvTaskExitError( void ); - -/*-----------------------------------------------------------*/ - -/* - * The number of SysTick increments that make up one tick period. - */ -#if configUSE_TICKLESS_IDLE == 1 - static uint32_t ulTimerCountsForOneTick = 0; -#endif /* configUSE_TICKLESS_IDLE */ - -/* - * The maximum number of tick periods that can be suppressed is limited by the - * 24 bit resolution of the SysTick timer. - */ -#if configUSE_TICKLESS_IDLE == 1 - static uint32_t xMaximumPossibleSuppressedTicks = 0; -#endif /* configUSE_TICKLESS_IDLE */ - -/* - * Compensate for the CPU cycles that pass while the SysTick is stopped (low - * power functionality only. - */ -#if configUSE_TICKLESS_IDLE == 1 - static uint32_t ulStoppedTimerCompensation = 0; -#endif /* configUSE_TICKLESS_IDLE */ - -/* - * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure - * FreeRTOS API functions are not called from interrupts that have been assigned - * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. - */ -#if ( configASSERT_DEFINED == 1 ) - static uint8_t ucMaxSysCallPriority = 0; - static uint32_t ulMaxPRIGROUPValue = 0; - static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* configASSERT_DEFINED */ - -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) -{ - /* Simulate the stack frame as it would be created by a context switch - interrupt. */ - - /* Offset added to account for the way the MCU uses the stack on entry/exit - of interrupts, and to ensure alignment. */ - pxTopOfStack--; - - *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ - pxTopOfStack--; - *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ - pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ - - /* Save code space by skipping register initialisation. */ - pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ - *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ - - /* A save method is being used that requires each task to maintain its - own exec return value. */ - pxTopOfStack--; - *pxTopOfStack = portINITIAL_EXEC_RETURN; - - pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -static void prvTaskExitError( void ) -{ - /* A function that implements a task must not exit or attempt to return to - its caller as there is nothing to return to. If a task wants to exit it - should instead call vTaskDelete( NULL ). - - Artificially force an assert() to be triggered if configASSERT() is - defined, then stop here so application writers can catch the error. */ - configASSERT( uxCriticalNesting == ~0UL ); - portDISABLE_INTERRUPTS(); - for( ;; ); -} -/*-----------------------------------------------------------*/ - -__asm void vPortSVCHandler( void ) -{ - PRESERVE8 - - /* Get the location of the current TCB. */ - ldr r3, =pxCurrentTCB - ldr r1, [r3] - ldr r0, [r1] - /* Pop the core registers. */ - ldmia r0!, {r4-r11, r14} - msr psp, r0 - isb - mov r0, #0 - msr basepri, r0 - bx r14 -} -/*-----------------------------------------------------------*/ - -__asm void prvStartFirstTask( void ) -{ - PRESERVE8 - - /* Use the NVIC offset register to locate the stack. */ - ldr r0, =0xE000ED08 - ldr r0, [r0] - ldr r0, [r0] - /* Set the msp back to the start of the stack. */ - msr msp, r0 - /* Globally enable interrupts. */ - cpsie i - cpsie f - dsb - isb - /* Call SVC to start the first task. */ - svc 0 - nop - nop -} -/*-----------------------------------------------------------*/ - -__asm void prvEnableVFP( void ) -{ - PRESERVE8 - - /* The FPU enable bits are in the CPACR. */ - ldr.w r0, =0xE000ED88 - ldr r1, [r0] - - /* Enable CP10 and CP11 coprocessors, then save back. */ - orr r1, r1, #( 0xf << 20 ) - str r1, [r0] - bx r14 - nop -} -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -BaseType_t xPortStartScheduler( void ) -{ - /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. - See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); - - /* This port can be used on all revisions of the Cortex-M7 core other than - the r0p1 parts. r0p1 parts should use the port from the - /source/portable/GCC/ARM_CM7/r0p1 directory. */ - configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); - configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); - - #if( configASSERT_DEFINED == 1 ) - { - volatile uint32_t ulOriginalPriority; - volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - functions can be called. ISR safe functions are those that end in - "FromISR". FreeRTOS maintains separate thread and ISR API functions to - ensure interrupt entry is as fast and simple as possible. - - Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = *pucFirstUserPriorityRegister; - - /* Determine the number of priority bits available. First write to all - possible bits. */ - *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = *pucFirstUserPriorityRegister; - - /* The kernel interrupt priority should be set to the lowest - priority. */ - configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Calculate the maximum acceptable priority group value for the number - of bits read back. */ - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulMaxPRIGROUPValue--; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - /* Shift the priority group value back to its position within the AIRCR - register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - value. */ - *pucFirstUserPriorityRegister = ulOriginalPriority; - } - #endif /* conifgASSERT_DEFINED */ - - /* Make PendSV and SysTick the lowest priority interrupts. */ - portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; - portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; - - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - vPortSetupTimerInterrupt(); - - /* Initialise the critical nesting count ready for the first task. */ - uxCriticalNesting = 0; - - /* Ensure the VFP is enabled - it should be anyway. */ - prvEnableVFP(); - - /* Lazy save always. */ - *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; - - /* Start the first task. */ - prvStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ - configASSERT( uxCriticalNesting == 1000UL ); -} -/*-----------------------------------------------------------*/ - -void vPortEnterCritical( void ) -{ - portDISABLE_INTERRUPTS(); - uxCriticalNesting++; - - /* This is not the interrupt safe version of the enter critical function so - assert() if it is being called from an interrupt context. Only API - functions that end in "FromISR" can be used in an interrupt. Only assert if - the critical nesting count is 1 to protect against recursive calls if the - assert function also uses a critical section. */ - if( uxCriticalNesting == 1 ) - { - configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); - } -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ - configASSERT( uxCriticalNesting ); - uxCriticalNesting--; - if( uxCriticalNesting == 0 ) - { - portENABLE_INTERRUPTS(); - } -} -/*-----------------------------------------------------------*/ - -__asm void xPortPendSVHandler( void ) -{ - extern uxCriticalNesting; - extern pxCurrentTCB; - extern vTaskSwitchContext; - - PRESERVE8 - - mrs r0, psp - isb - /* Get the location of the current TCB. */ - ldr r3, =pxCurrentTCB - ldr r2, [r3] - - /* Is the task using the FPU context? If so, push high vfp registers. */ - tst r14, #0x10 - it eq - vstmdbeq r0!, {s16-s31} - - /* Save the core registers. */ - stmdb r0!, {r4-r11, r14} - - /* Save the new top of stack into the first member of the TCB. */ - str r0, [r2] - - stmdb sp!, {r3} - mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 - dsb - isb - bl vTaskSwitchContext - mov r0, #0 - msr basepri, r0 - ldmia sp!, {r3} - - /* The first item in pxCurrentTCB is the task top of stack. */ - ldr r1, [r3] - ldr r0, [r1] - - /* Pop the core registers. */ - ldmia r0!, {r4-r11, r14} - - /* Is the task using the FPU context? If so, pop the high vfp registers - too. */ - tst r14, #0x10 - it eq - vldmiaeq r0!, {s16-s31} - - msr psp, r0 - isb - #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */ - #if WORKAROUND_PMU_CM001 == 1 - push { r14 } - pop { pc } - nop - #endif - #endif - - bx r14 - nop - nop -} -/*-----------------------------------------------------------*/ - -void xPortSysTickHandler( void ) -{ - /* The SysTick runs at the lowest interrupt priority, so when this interrupt - executes all interrupts must be unmasked. There is therefore no need to - save and then restore the interrupt mask value as its value is already - known - therefore the slightly faster vPortRaiseBASEPRI() function is used - in place of portSET_INTERRUPT_MASK_FROM_ISR(). */ - vPortRaiseBASEPRI(); - { - /* Increment the RTOS tick. */ - if( xTaskIncrementTick() != pdFALSE ) - { - /* A context switch is required. Context switching is performed in - the PendSV interrupt. Pend the PendSV interrupt. */ - portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; - } - } - vPortClearBASEPRIFromISR(); -} -/*-----------------------------------------------------------*/ - -#if configUSE_TICKLESS_IDLE == 1 - - __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) - { - uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL; - TickType_t xModifiableIdleTime; - - /* Make sure the SysTick reload value does not overflow the counter. */ - if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) - { - xExpectedIdleTime = xMaximumPossibleSuppressedTicks; - } - - /* Stop the SysTick momentarily. The time the SysTick is stopped for - is accounted for as best it can be, but using the tickless mode will - inevitably result in some tiny drift of the time maintained by the - kernel with respect to calendar time. */ - portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; - - /* Calculate the reload value required to wait xExpectedIdleTime - tick periods. -1 is used because this code will execute part way - through one of the tick periods. */ - ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); - if( ulReloadValue > ulStoppedTimerCompensation ) - { - ulReloadValue -= ulStoppedTimerCompensation; - } - - /* Enter a critical section but don't use the taskENTER_CRITICAL() - method as that will mask interrupts that should exit sleep mode. */ - __disable_irq(); - __dsb( portSY_FULL_READ_WRITE ); - __isb( portSY_FULL_READ_WRITE ); - - /* If a context switch is pending or a task is waiting for the scheduler - to be unsuspended then abandon the low power entry. */ - if( eTaskConfirmSleepModeStatus() == eAbortSleep ) - { - /* Restart from whatever is left in the count register to complete - this tick period. */ - portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; - - /* Restart SysTick. */ - portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; - - /* Reset the reload register to the value required for normal tick - periods. */ - portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; - - /* Re-enable interrupts - see comments above __disable_irq() call - above. */ - __enable_irq(); - } - else - { - /* Set the new reload value. */ - portNVIC_SYSTICK_LOAD_REG = ulReloadValue; - - /* Clear the SysTick count flag and set the count value back to - zero. */ - portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; - - /* Restart SysTick. */ - portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; - - /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can - set its parameter to 0 to indicate that its implementation contains - its own wait for interrupt or wait for event instruction, and so wfi - should not be executed again. However, the original expected idle - time variable must remain unmodified, so a copy is taken. */ - xModifiableIdleTime = xExpectedIdleTime; - configPRE_SLEEP_PROCESSING( &xModifiableIdleTime ); - if( xModifiableIdleTime > 0 ) - { - __dsb( portSY_FULL_READ_WRITE ); - __wfi(); - __isb( portSY_FULL_READ_WRITE ); - } - configPOST_SLEEP_PROCESSING( &xExpectedIdleTime ); - - /* Stop SysTick. Again, the time the SysTick is stopped for is - accounted for as best it can be, but using the tickless mode will - inevitably result in some tiny drift of the time maintained by the - kernel with respect to calendar time. */ - ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG; - portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT ); - - /* Re-enable interrupts - see comments above __disable_irq() call - above. */ - __enable_irq(); - - if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) - { - uint32_t ulCalculatedLoadValue; - - /* The tick interrupt has already executed, and the SysTick - count reloaded with ulReloadValue. Reset the - portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick - period. */ - ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); - - /* Don't allow a tiny value, or values that have somehow - underflowed because the post sleep hook did something - that took too long. */ - if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) - { - ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); - } - - portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; - - /* The tick interrupt handler will already have pended the tick - processing in the kernel. As the pending tick will be - processed as soon as this function exits, the tick value - maintained by the tick is stepped forward by one less than the - time spent waiting. */ - ulCompleteTickPeriods = xExpectedIdleTime - 1UL; - } - else - { - /* Something other than the tick interrupt ended the sleep. - Work out how long the sleep lasted rounded to complete tick - periods (not the ulReload value which accounted for part - ticks). */ - ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; - - /* How many complete tick periods passed while the processor - was waiting? */ - ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; - - /* The reload value is set to whatever fraction of a single tick - period remains. */ - portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; - } - - /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG - again, then set portNVIC_SYSTICK_LOAD_REG back to its standard - value. The critical section is used to ensure the tick interrupt - can only execute once in the case that the reload register is near - zero. */ - portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; - portENTER_CRITICAL(); - { - portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; - vTaskStepTick( ulCompleteTickPeriods ); - portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; - } - portEXIT_CRITICAL(); - } - } - -#endif /* #if configUSE_TICKLESS_IDLE */ - -/*-----------------------------------------------------------*/ - -/* - * Setup the SysTick timer to generate the tick interrupts at the required - * frequency. - */ -#if configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 - - void vPortSetupTimerInterrupt( void ) - { - /* Calculate the constants required to configure the tick interrupt. */ - #if configUSE_TICKLESS_IDLE == 1 - { - ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); - xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; - ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); - } - #endif /* configUSE_TICKLESS_IDLE */ - - /* Configure SysTick to interrupt at the requested rate. */ - portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; - portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); - } - -#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */ -/*-----------------------------------------------------------*/ - -__asm uint32_t vPortGetIPSR( void ) -{ - PRESERVE8 - - mrs r0, ipsr - bx r14 -} -/*-----------------------------------------------------------*/ - -#if( configASSERT_DEFINED == 1 ) - - void vPortValidateInterruptPriority( void ) - { - uint32_t ulCurrentInterrupt; - uint8_t ucCurrentPriority; - - /* Obtain the number of the currently executing interrupt. */ - ulCurrentInterrupt = vPortGetIPSR(); - - /* Is the interrupt number a user defined interrupt? */ - if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) - { - /* Look up the interrupt's priority. */ - ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; - - /* The following assertion will fail if a service routine (ISR) for - an interrupt that has been assigned a priority above - configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API - function. ISR safe FreeRTOS API functions must *only* be called - from interrupts that have been assigned a priority at or below - configMAX_SYSCALL_INTERRUPT_PRIORITY. - - Numerically low interrupt priority numbers represent logically high - interrupt priorities, therefore the priority of the interrupt must - be set to a value equal to or numerically *higher* than - configMAX_SYSCALL_INTERRUPT_PRIORITY. - - Interrupts that use the FreeRTOS API must not be left at their - default priority of zero as that is the highest possible priority, - which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, - and therefore also guaranteed to be invalid. - - FreeRTOS maintains separate thread and ISR API functions to ensure - interrupt entry is as fast and simple as possible. - - The following links provide detailed information: - http://www.freertos.org/RTOS-Cortex-M3-M4.html - http://www.freertos.org/FAQHelp.html */ - configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); - } - - /* Priority grouping: The interrupt controller (NVIC) allows the bits - that define each interrupt's priority to be split between bits that - define the interrupt's pre-emption priority bits and bits that define - the interrupt's sub-priority. For simplicity all bits must be defined - to be pre-emption priority bits. The following assertion will fail if - this is not the case (if some bits represent a sub-priority). - - If the application only uses CMSIS libraries for interrupt - configuration then the correct setting can be achieved on all Cortex-M - devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the - scheduler. Note however that some vendor specific peripheral libraries - assume a non-zero priority group setting, in which cases using a value - of zero will result in unpredicable behaviour. */ - configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); - } - -#endif /* configASSERT_DEFINED */ - - diff --git a/F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h b/F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h deleted file mode 100644 index 0b6eb5a..0000000 --- a/F4-Gyro-RTOS/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE uint32_t -#define portBASE_TYPE long - -typedef portSTACK_TYPE StackType_t; -typedef long BaseType_t; -typedef unsigned long UBaseType_t; - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff -#else - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 -#endif -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 - -/* Constants used with memory barrier intrinsics. */ -#define portSY_FULL_READ_WRITE ( 15 ) - -/*-----------------------------------------------------------*/ - -/* Scheduler utilities. */ -#define portYIELD() \ -{ \ - /* Set a PendSV to request a context switch. */ \ - portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ - \ - /* Barriers are normally not required but do ensure the code is completely \ - within the specified behaviour for the architecture. */ \ - __dsb( portSY_FULL_READ_WRITE ); \ - __isb( portSY_FULL_READ_WRITE ); \ -} -/*-----------------------------------------------------------*/ - -#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) ) -#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD() -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) -/*-----------------------------------------------------------*/ - -/* Critical section management. */ -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() -#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x) - -/*-----------------------------------------------------------*/ - -/* Tickless idle/low power functionality. */ -#ifndef portSUPPRESS_TICKS_AND_SLEEP - extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) -#endif -/*-----------------------------------------------------------*/ - -/* Port specific optimisations. */ -#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 -#endif - -#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 - - /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif - - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - - /*-----------------------------------------------------------*/ - - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) - -#endif /* taskRECORD_READY_PRIORITY */ -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. These are -not necessary for to use this port. They are defined so the common demo files -(which build with all the ports) will build. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) -/*-----------------------------------------------------------*/ - -#ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() -#endif - -/* portNOP() is not required by this port. */ -#define portNOP() - -#define portINLINE __inline - -#ifndef portFORCE_INLINE - #define portFORCE_INLINE __forceinline -#endif - -/*-----------------------------------------------------------*/ - -static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) -{ - __asm - { - /* Barrier instructions are not used as this function is only used to - lower the BASEPRI value. */ - msr basepri, ulBASEPRI - } -} -/*-----------------------------------------------------------*/ - -static portFORCE_INLINE void vPortRaiseBASEPRI( void ) -{ -uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; - - __asm - { - /* Set BASEPRI to the max syscall priority to effect a critical - section. */ - msr basepri, ulNewBASEPRI - dsb - isb - } -} -/*-----------------------------------------------------------*/ - -static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) -{ - __asm - { - /* Set BASEPRI to 0 so no interrupts are masked. This function is only - used to lower the mask in an interrupt, so memory barriers are not - used. */ - msr basepri, #0 - } -} -/*-----------------------------------------------------------*/ - -static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) -{ -uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; - - __asm - { - /* Set BASEPRI to the max syscall priority to effect a critical - section. */ - mrs ulReturn, basepri - msr basepri, ulNewBASEPRI - dsb - isb - } - - return ulReturn; -} -/*-----------------------------------------------------------*/ - -static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) -{ -uint32_t ulCurrentInterrupt; -BaseType_t xReturn; - - /* Obtain the number of the currently executing interrupt. */ - __asm - { - mrs ulCurrentInterrupt, ipsr - } - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; -} - - -#ifdef __cplusplus -} -#endif - -#endif /* PORTMACRO_H */ - diff --git a/F4-Gyro-RTOS/Src/main.c b/F4-Gyro-RTOS/Src/main.c index ee1d7d4..798589e 100644 --- a/F4-Gyro-RTOS/Src/main.c +++ b/F4-Gyro-RTOS/Src/main.c @@ -88,8 +88,8 @@ static void MX_GPIO_Init(void); static void MX_I2C1_Init(void); static void MX_I2S3_Init(void); static void MX_SPI1_Init(void); -void StartTask01(void const *argument); -void StartTask02(void const *argument); +void StartTask01(void const * argument); +void StartTask02(void const * argument); /* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ @@ -166,10 +166,11 @@ int main(void) osMailQDef(myMailQ, 5, GYRO_DATA_T); myMailQID = osMailCreate(osMailQ(myMailQ), NULL); /* USER CODE END RTOS_QUEUES */ + /* Start scheduler */ osKernelStart(); - + /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ @@ -177,11 +178,12 @@ int main(void) while (1) { - /* USER CODE END WHILE */ + /* USER CODE END WHILE */ - /* USER CODE BEGIN 3 */ + /* USER CODE BEGIN 3 */ } /* USER CODE END 3 */ + } /** @@ -195,13 +197,13 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -216,9 +218,10 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; @@ -237,11 +240,11 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Configure the Systick interrupt time + /**Configure the Systick interrupt time */ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000); + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - /**Configure the Systick + /**Configure the Systick */ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); @@ -266,6 +269,7 @@ static void MX_I2C1_Init(void) { _Error_Handler(__FILE__, __LINE__); } + } /* I2S3 init function */ @@ -285,6 +289,7 @@ static void MX_I2S3_Init(void) { _Error_Handler(__FILE__, __LINE__); } + } /* SPI1 init function */ @@ -308,6 +313,7 @@ static void MX_SPI1_Init(void) { _Error_Handler(__FILE__, __LINE__); } + } /** Configure pins as @@ -339,7 +345,8 @@ static void MX_GPIO_Init(void) HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOD, GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15 | GPIO_PIN_4, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 + |GPIO_PIN_4, GPIO_PIN_RESET); /*Configure GPIO pin : PE3 */ GPIO_InitStruct.Pin = GPIO_PIN_3; @@ -385,7 +392,8 @@ static void MX_GPIO_Init(void) /*Configure GPIO pins : PD12 PD13 PD14 PD15 PD4 */ - GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15 | GPIO_PIN_4; + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 + |GPIO_PIN_4; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; @@ -402,6 +410,7 @@ static void MX_GPIO_Init(void) GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + } /* USER CODE BEGIN 4 */ @@ -502,7 +511,7 @@ void USB_Task(void) /* USER CODE END 4 */ /* StartTask01 function */ -void StartTask01(void const *argument) +void StartTask01(void const * argument) { /* init code for USB_DEVICE */ MX_USB_DEVICE_Init(); @@ -516,11 +525,11 @@ void StartTask01(void const *argument) // HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_13); // osDelay(250); } - /* USER CODE END 5 */ + /* USER CODE END 5 */ } /* StartTask02 function */ -void StartTask02(void const *argument) +void StartTask02(void const * argument) { /* USER CODE BEGIN StartTask02 */ /* Infinite loop */ @@ -548,8 +557,7 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ - if (htim->Instance == TIM6) - { + if (htim->Instance == TIM6) { HAL_IncTick(); } /* USER CODE BEGIN Callback 1 */ @@ -573,7 +581,7 @@ void _Error_Handler(char *file, int line) /* USER CODE END Error_Handler_Debug */ } -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** * @brief Reports the name of the source file and the source line number * where the assert_param error has occurred. @@ -581,8 +589,8 @@ void _Error_Handler(char *file, int line) * @param line: assert_param error line source number * @retval None */ -void assert_failed(uint8_t *file, uint32_t line) -{ +void assert_failed(uint8_t* file, uint32_t line) +{ /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */