diff --git a/.gitignore b/.gitignore index 3fdb2d060..dad48a269 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,6 @@ .opt_build/ .sconf_temp/ +.sst_build/ .sconsign.dblite bin/macsim config.log @@ -23,3 +24,4 @@ Makefile Makefile.in *.dirstamp sst-unit-test/*.out +.vscode/ \ No newline at end of file diff --git a/SConscript b/SConscript index 493156540..1999645ab 100644 --- a/SConscript +++ b/SConscript @@ -10,6 +10,7 @@ import sys import os import glob +from build import get_cmd_output ######################################################################################### # Build option @@ -317,6 +318,33 @@ if flags['qsim'] == '1': if flags['ramulator'] == '1': libraries.append('ramulator') +if flags['sst'] == '1': # Compile Macsim for SST + macsim_component_name = 'macsimComponent' + macsim_component_src = [x for x in macsim_src if 'main.cc' not in x] # We don't want main.cc + macsim_component_src += [ + 'macsimComponent.cpp' + ] + + sst_build_cxx = get_cmd_output(['sst-config', '--CXX']).split(' ') + sst_build_cxxflags = get_cmd_output(['sst-config', '--ELEMENT_CXXFLAGS']).split(' ') + sst_build_linkflags = get_cmd_output(['sst-config', '--ELEMENT_LDFLAGS']).split(' ') + + # Set CXX compiler + sst_compiler = sst_build_cxx[0] + env['CXX'] = sst_compiler + + # Set CXXFLAGS + env['CPPFLAGS'] += ' ' + ' '.join(sst_build_cxxflags) + env['CPPFLAGS'] += ' -DUSING_SST' + + # Set LINKFLAGS + env['LINKFLAGS'] = sst_build_linkflags # Overriding + + # Generate SST component as shared library + env.SharedLibrary(macsim_component_name, macsim_component_src) + Return() # Finish gracefully + +# Build Macsim executable env.Program( 'macsim', macsim_src, diff --git a/SConstruct b/SConstruct index 2995cf000..fcf57589e 100644 --- a/SConstruct +++ b/SConstruct @@ -79,6 +79,7 @@ flags['gprof'] = Config.get('Build', 'gprof', fallback='0') flags['pin_3_13_trace'] = Config.get('Build', 'pin_3_13_trace', fallback='0') flags['val'] = Config.get('Build_Extra', 'val', fallback='0') flags['ramulator'] = Config.get('Library', 'ramulator', fallback='0') +flags['sst'] = Config.get('Build', 'sst', fallback='0') ## Configuration from commandline flags['debug'] = ARGUMENTS.get('debug', flags['debug']) @@ -90,12 +91,12 @@ flags['dram'] = ARGUMENTS.get('dram', flags['dram']) flags['val'] = ARGUMENTS.get('val', flags['val']) flags['qsim'] = ARGUMENTS.get('qsim', flags['qsim']) flags['ramulator'] = ARGUMENTS.get('ramulator', flags['ramulator']) - +flags['sst'] = ARGUMENTS.get('sst', flags['sst']) ## Checkout DRAMSim2 copy if flags['dram'] == '1': if not os.path.exists('src/DRAMSim2'): - os.system('git clone git://github.com/dramninjasUMD/DRAMSim2.git src/DRAMSim2') + os.system('git clone https://github.com/umd-memsys/DRAMSim2.git src/DRAMSim2') ## Checkout Ramulator copy if flags['ramulator'] == '1': @@ -105,9 +106,12 @@ if flags['ramulator'] == '1': ## Create stat/knobs SConscript('scripts/SConscript', exports='flags') - +## sst element build (with/without debug) +if flags['sst'] == '1': + SConscript('SConscript', variant_dir='.sst_build', duplicate=0, exports='flags') + Clean('.', '.sst_build') ## debug build -if flags['debug'] == '1': +elif flags['debug'] == '1' and not flags['sst'] == '1': SConscript('SConscript', variant_dir='.dbg_build', duplicate=0, exports='flags') Clean('.', '.dbg_build') ## gprof build diff --git a/build.py b/build.py index 757528d07..12dcf4c2c 100755 --- a/build.py +++ b/build.py @@ -10,7 +10,7 @@ import sys import itertools from optparse import OptionParser - +import subprocess ######################################################################################### # argument parsing @@ -29,6 +29,8 @@ def parse_arg(): parser.add_option("--power", action="store_true", dest="power", default=False, help="EI Power") parser.add_option("--iris", action="store_true", dest="iris", default=False, help="IRIS") parser.add_option("--ramulator", action="store_true", dest="ramulator", default=False, help="Ramulator") + parser.add_option("--sst", action="store_true", dest="sst", default=False, help="Build Macsim SST Element") + parser.add_option("--sst-install", action="store_true", dest="sst_install", default=False, help="Install Macsim SST Element") return parser @@ -57,6 +59,27 @@ def build_test(): else: print('%s %s failed' % (build_option[ii], ' '.join(opt))) +######################################################################################### +# Util Functions +######################################################################################### +def get_cmd_output(cmd:list, abort_on_error:bool=True): + """ + Run a command and return the output. + :param cmd: The command to run as a list of tokens. + :param abort_on_error: If True, abort on error. + :return: The stdout, stderr, and return code of the command. + """ + process = subprocess.Popen(cmd, stdout=subprocess.PIPE) + stdout, stderr = process.communicate() + stdout = stdout.decode('utf-8', errors='replace').strip() if stdout is not None else '' + stderr = stderr.decode('utf-8', errors='replace').strip() if stderr is not None else '' + if abort_on_error and process.returncode != 0: + print(f'Error: Shell command failed (return code: {process.returncode}): ', ' '.join(cmd), file=sys.stderr) + print('\tstdout:', stdout, file=sys.stderr) + print('\tstderr:', stderr, file=sys.stderr) + sys.exit(1) + return stdout + ######################################################################################### # main function @@ -88,6 +111,37 @@ def main(): if options.dramsim: cmd += 'dram=1 ' + if options.sst: + cmd += 'sst=1 ' + + if options.sst_install: + component = 'macsimComponent' + component_lib_dir = os.path.abspath('.sst_build') + component_src_dir = os.getcwd() + component_tests_dir = os.path.abspath('sst-unit-test') + + # Check if macsim component exists + if not os.path.exists(f'{component_lib_dir}/lib{component}.so'): + print(f"ERROR: {component} not found in {component_lib_dir}, build with sst=1 option first") + exit(0) + + print(f"Registering SST element: {component}") + print(f" SRCDIR: {component_src_dir}") + print(f" LIBDIR: {component_lib_dir}") + print(f" TESTDIR: {component_tests_dir}") + os.system(f'sst-register {component} {component}_LIBDIR={component_lib_dir}') + os.system(f'sst-register SST_ELEMENT_SOURCE {component}={component_src_dir}') + os.system(f'sst-register SST_ELEMENT_TESTS {component}={component_tests_dir}') + + # Check if component is registered successfully + sst_info_out = get_cmd_output(['sst-info', component]) + if 'Component 0: macsimComponent' in sst_info_out: + print(f"Successfully registered SST element: {component}") + exit(0) + else: + print(f"ERROR: Failed to register SST element: {component}") + exit(1) + # EI power if options.power: cmd += 'power=1 ' diff --git a/build.rover.py b/build.rover.py new file mode 100755 index 000000000..52c5e2111 --- /dev/null +++ b/build.rover.py @@ -0,0 +1,200 @@ +#!/usr/bin/env python3 + +######################################################################################### +# Author : Jaekyu Lee (jq.lee17@gmail.com) +# Description : wrapper script for scons build +######################################################################################### + + +import os +import sys +import itertools +from optparse import OptionParser +import subprocess + +######################################################################################### +# argument parsing +######################################################################################### +def parse_arg(): + parser = OptionParser(usage="usage: %prog [options] filename", version="%prog 1.0") + parser.add_option("-j", "--thread", action="store", dest="thread", default=1, help="-j option for the parallel build") + parser.add_option("-d", "--debug", action="store_true", dest="debug", default=False, help="debug build") + parser.add_option("-p", "--gprof", action="store_true", dest="gprof", default=False, help="gprof build") + parser.add_option("-c", "--clean", action="store_true", dest="clean", default=False, help="clean") + parser.add_option("-t", "--test", action="store_true", dest="test", default=False, help="clean") + parser.add_option("-v", "--val", action="store_true", dest="val", default=False, help="build version used for gpu validation") + parser.add_option("--newpin", action="store_true", dest="pin_3_13_trace", default=False, help="trace based on pin 3.13 ") + parser.add_option("-q", "--qsim", action="store_true", dest="qsim", default=False, help="use qsim to drive macsim") + parser.add_option("--dramsim", action="store_true", dest="dramsim", default=False, help="DRAMSim2") + parser.add_option("--power", action="store_true", dest="power", default=False, help="EI Power") + parser.add_option("--iris", action="store_true", dest="iris", default=False, help="IRIS") + parser.add_option("--ramulator", action="store_true", dest="ramulator", default=False, help="Ramulator") + parser.add_option("--sst", action="store_true", dest="sst", default=False, help="Build Macsim SST Element") + parser.add_option("--sst-install", action="store_true", dest="sst_install", default=False, help="Install Macsim SST Element") + + return parser + + +######################################################################################### +# build test for all possible build combinations +######################################################################################### +def build_test(): + build_option = ['', 'debug=1', 'gprof=1', 'qsim=1', 'pin_3_13_trace=1'] + build_dir = ['.opt_build', '.dbg_build', '.gpf_build'] + build_libs = ['dram=1', 'power=1', 'iris=1', 'ramulator=1'] + + for ii in range(0, len(build_option)): + os.system('rm -rf %s' % build_dir[ii]) + for jj in range(0, len(build_libs)+1): + for opt in itertools.combinations(build_libs, jj): + cmd = 'scons -j 4 %s %s' % (build_option[ii], ' '.join(opt)) + redir = '> /dev/null 2>&1' + + if os.path.exists('%s/macsim' % build_dir[ii]): + os.system('rm -f %s/macsim' % build_dir[ii]) + + os.system('%s %s' % (cmd, redir)) + if os.path.exists('%s/macsim' % build_dir[ii]): + print('%s %s successful' % (build_option[ii], ' '.join(opt))) + else: + print('%s %s failed' % (build_option[ii], ' '.join(opt))) + +######################################################################################### +# Util Functions +######################################################################################### +def get_cmd_output(cmd, abort_on_error=True): + """ + Run a command and return the output. + :param cmd: The command to run as a list of tokens. + :param abort_on_error: If True, abort on error. + :return: The stdout, stderr, and return code of the command. + """ + process = subprocess.Popen(cmd, stdout=subprocess.PIPE) + stdout, stderr = process.communicate() + stdout = stdout.decode('utf-8', errors='replace').strip() if stdout is not None else '' + stderr = stderr.decode('utf-8', errors='replace').strip() if stderr is not None else '' + if abort_on_error and process.returncode != 0: + #print(f'Error: Shell command failed (return code: {process.returncode}): ', ' '.join(cmd), file=sys.stderr) + #print('\tstdout:', stdout, file=sys.stderr) + #print('\tstderr:', stderr, file=sys.stderr) + print >> sys.stderr, 'Error: Shell command failed (return code: {}): {}'.format(process.returncode, ' '.join(cmd)) + print >> sys.stderr, '\tstdout:', stdout + print >> sys.stderr, '\tstderr:', stderr + sys.exit(1) + return stdout + + +######################################################################################### +# main function +######################################################################################### +def main(): + parser = parse_arg() + (options, args) = parser.parse_args() + + ## Build test + if options.test: + build_test() + sys.exit(0) + + + ## Prepare scons command + cmd = 'scons ' + + ## Main build options (opt, dbg, gpf) + if options.debug: + cmd += 'debug=1 ' + elif options.gprof: + cmd += 'gprof=1 ' + + if options.val: + cmd += 'val=1 ' + + ## External libraries (dramsim, ei, iris) + # DRAMSim2 + if options.dramsim: + cmd += 'dram=1 ' + + if options.sst: + cmd += 'sst=1 ' + + if options.sst_install: + component = 'macsimComponent' + component_lib_dir = os.path.abspath('.sst_build') + component_src_dir = os.getcwd() + component_tests_dir = os.path.abspath('sst-unit-test') + + # Check if macsim component exists + if not os.path.exists('{}/lib{}.so'.format(component_lib_dir, component)): + print("ERROR: {} not found in {}, build with sst=1 option first".format(component, component_lib_dir)) + #if not os.path.exists(f'{component_lib_dir}/lib{component}.so'): + #print(f"ERROR: {component} not found in {component_lib_dir}, build with sst=1 option first") + exit(0) + + print("Registering SST element: {}".format(component)) + print(" SRCDIR: {}".format(component_src_dir)) + print(" LIBDIR: {}".format(component_lib_dir)) + print(" TESTDIR: {}".format(component_tests_dir)) + os.system('sst-register {} {}_LIBDIR={}'.format(component, component, component_lib_dir)) + os.system('sst-register SST_ELEMENT_SOURCE {}={}'.format(component, component_src_dir)) + os.system('sst-register SST_ELEMENT_TESTS {}={}'.format(component, component_tests_dir)) + + # Check if component is registered successfully + sst_info_out = get_cmd_output(['sst-info', component]) + if 'Component 0: macsimComponent' in sst_info_out: + print("Successfully registered SST element: {}".format(component)) + exit(0) + else: + print("ERROR: Failed to register SST element: {}".format(component)) + exit(1) + + # EI power + if options.power: + cmd += 'power=1 ' + + # IRIS + if options.iris: + cmd += 'iris=1 ' + + # Qsim + if options.qsim: + cmd += 'qsim=1 ' + + # NEW PIN + if options.pin_3_13_trace: + cmd += 'pin_3_13_trace=1 ' + + # Ramulator + if options.ramulator: + cmd += 'ramulator=1 ' + + ## Parallel building + cmd += '-j %s ' % options.thread + + if options.clean: + cmd += '-c' + + + ## run scons command + os.system(cmd) + + + ## Create a symbolic link + if not options.clean: + if options.debug: + build_dir = '.dbg_build' + elif options.gprof: + build_dir = '.gpf_build' + else: + build_dir = '.opt_build' + + if os.path.exists('%s/macsim' % build_dir): + os.chdir('bin') + + if os.path.exists('macsim'): + os.system('rm -f macsim') + os.system('ln -s ../%s/macsim' % build_dir) + + + +if __name__ == '__main__': + main() diff --git a/macsimComponent.cpp b/macsimComponent.cpp index 681e4b15c..74c414d76 100644 --- a/macsimComponent.cpp +++ b/macsimComponent.cpp @@ -4,12 +4,13 @@ #include #include -#include -#include -#include +// #include // Th is include is REQUIRED for all implementation files +// #include // FIXME: one of these should be removed +// #include +// #include -#include -#include +// #include +// #include #include "src/global_defs.h" #include "src/uop.h" @@ -56,9 +57,7 @@ macsimComponent::macsimComponent(ComponentId_t id, Params& params) m_command_line = params.find("command_line", found); m_clock_freq = params.find("frequency", found); - TimeConverter* tc = registerClock( - m_clock_freq, - new Clock::Handler(this, &macsimComponent::ticReceived)); + if (!found) m_dbg->fatal(CALL_INFO, -1, "Couldn't find frequency parameter\n"); if (params.find("ptx_core", 0)) { m_acc_type = PTX_CORE; @@ -66,7 +65,7 @@ macsimComponent::macsimComponent(ComponentId_t id, Params& params) } else if (params.find("igpu_core", 0)) { m_acc_type = IGPU_CORE; m_acc_core = 1; - } else if (params.find("nvbit_core", 0)) { + } else if (params.find("nvbit_core", 0)) { // Fixed: Need to add Constant Cache and Texture Cache m_acc_type = NVBIT_CORE; m_acc_core = 1; @@ -75,34 +74,53 @@ macsimComponent::macsimComponent(ComponentId_t id, Params& params) m_acc_type = NO_ACC; } m_num_link = params.find("num_link", 1); + m_macsim_component_num = params.find("component_num", 0); + m_mem_size = params.find("mem_size", 1 * 1024 * 1024 * 1024); + MSC_DEBUG("Memory address space: %" PRId64 " Bytes (0x%" PRIx64 " - 0x%" PRIx64 ")\n", m_mem_size, 0x0UL, m_mem_size - 1); + + registerAsPrimaryComponent(); + primaryComponentDoNotEndSim(); + + // Register clock handler + tc = registerClock( + m_clock_freq, + new Clock::Handler(this, &macsimComponent::ticReceived)); + + // Configure links configureLinks(params, tc); + // Show link information + MSC_DEBUG("Number of links: %d\n", m_num_link); + for (unsigned int l = 0; l < m_num_link; ++l) { + MSC_DEBUG("-- Core: %d --------\n", l); + MSC_DEBUG(" I cache link: %s\n", m_instruction_cache_links[l]->getName().c_str()); + MSC_DEBUG(" D cache link: %s\n", m_data_cache_links[l]->getName().c_str()); + if (m_acc_core) { + MSC_DEBUG(" C cache link: %s\n", m_const_cache_links[l]->getName().c_str()); + MSC_DEBUG(" T cache link: %s\n", m_texture_cache_links[l]->getName().c_str()); + } + } + m_cube_connected = params.find("cube_connected", 0); if (m_cube_connected) { - m_cube_link = loadUserSubComponent( + m_cube_link = loadUserSubComponent( "cube_link", ComponentInfo::SHARE_NONE, tc, - new Interfaces::SimpleMem::Handler( + new Interfaces::StandardMem::Handler( this, &macsimComponent::handleCubeEvent)); if (!m_cube_link) { Params interfaceParams; interfaceParams.insert("port", "cube_link"); - m_cube_link = loadAnonymousSubComponent( - "memHierarchy.memInterface", "cube_link", 0, + m_cube_link = loadAnonymousSubComponent( + "memHierarchy.standardInterface", "cube_link", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, interfaceParams, tc, - new Interfaces::SimpleMem::Handler( + new Interfaces::StandardMem::Handler( this, &macsimComponent::handleCubeEvent)); } } else { m_cube_link = NULL; } - m_mem_size = params.find("mem_size", 1 * 1024 * 1024 * 1024); - MSC_DEBUG("Size of memory address space: 0x%" PRIx64 "\n", m_mem_size); - - registerAsPrimaryComponent(); - primaryComponentDoNotEndSim(); - m_macsim = new macsim_c(); m_sim_running = false; @@ -111,6 +129,7 @@ macsimComponent::macsimComponent(ComponentId_t id, Params& params) // Upon completion, MacSim will return an event to another SST component. m_operation_mode = params.find("operation_mode", (int)OperationMode::MASTER); + MSC_DEBUG("Operation mode: %s\n", m_operation_mode == OperationMode::MASTER ? "MASTER" : "SLAVE"); if (m_operation_mode == OperationMode::MASTER) { m_triggered = true; m_ipc_link = NULL; @@ -127,75 +146,92 @@ macsimComponent::macsimComponent() : Component(-1) { void macsimComponent::configureLinks(SST::Params& params, TimeConverter* tc) { for (unsigned int l = 0; l < m_num_link; ++l) { - auto icache_link = loadUserSubComponent( - "core" + std::to_string(l) + "-icache", ComponentInfo::SHARE_NONE, tc, - new Interfaces::SimpleMem::Handler( + //////////////////////////////////////// + // Configure ICache Link + std::string icache_portname = "macsim" + std::to_string(m_macsim_component_num) + "_core" + std::to_string(l) + "_icache"; + auto icache_link = loadUserSubComponent( + icache_portname, ComponentInfo::SHARE_NONE, tc, + new Interfaces::StandardMem::Handler( this, &macsimComponent::handleInstructionCacheEvent)); if (!icache_link) { Params interfaceParams; - interfaceParams.insert("port", "core" + std::to_string(l) + "-icache"); - icache_link = loadAnonymousSubComponent( - "memHierarchy.memInterface", "core" + std::to_string(l) + "-icache", 0, + interfaceParams.insert("port", icache_portname); + icache_link = loadAnonymousSubComponent( + "memHierarchy.standardInterface", icache_portname, 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, interfaceParams, tc, - new Interfaces::SimpleMem::Handler( + new Interfaces::StandardMem::Handler( this, &macsimComponent::handleInstructionCacheEvent)); } + if(!icache_link) m_dbg->fatal(CALL_INFO, -1, "Configuring icache link failed\n"); m_instruction_cache_links.push_back(icache_link); m_instruction_cache_requests.push_back(std::map()); m_instruction_cache_responses.push_back(std::set()); - auto dcache_link = loadUserSubComponent( - "core" + std::to_string(l) + "-dcache", ComponentInfo::SHARE_NONE, tc, - new Interfaces::SimpleMem::Handler( + //////////////////////////////////////// + // Configure DCache Link + std::string dcache_portname = "macsim" + std::to_string(m_macsim_component_num) + "_core" + std::to_string(l) + "_dcache"; + + auto dcache_link = loadUserSubComponent( + dcache_portname, ComponentInfo::SHARE_NONE, tc, + new Interfaces::StandardMem::Handler( this, &macsimComponent::handleDataCacheEvent)); if (!dcache_link) { Params interfaceParams; - interfaceParams.insert("port", "core" + std::to_string(l) + "-dcache"); - dcache_link = loadAnonymousSubComponent( - "memHierarchy.memInterface", "core" + std::to_string(l) + "-dcache", 0, + interfaceParams.insert("port", dcache_portname); + dcache_link = loadAnonymousSubComponent( + "memHierarchy.standardInterface", dcache_portname, 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, interfaceParams, tc, - new Interfaces::SimpleMem::Handler( + new Interfaces::StandardMem::Handler( this, &macsimComponent::handleDataCacheEvent)); } + if(!dcache_link) m_dbg->fatal(CALL_INFO, -1, "Configuring dcache link failed\n"); m_data_cache_links.push_back(dcache_link); m_data_cache_requests.push_back(std::map()); m_data_cache_responses.push_back(std::set()); if (m_acc_core) { - auto ccache_link = loadUserSubComponent( - "core" + std::to_string(l) + "-ccache", ComponentInfo::SHARE_NONE, tc, - new Interfaces::SimpleMem::Handler( + //////////////////////////////////////// + // Configure Const Cache Link + std::string ccache_portname = "macsim" + std::to_string(m_macsim_component_num) + "_core" + std::to_string(l) + "_ccache"; + auto ccache_link = loadUserSubComponent( + ccache_portname, ComponentInfo::SHARE_NONE, tc, + new Interfaces::StandardMem::Handler( this, &macsimComponent::handleConstCacheEvent)); if (!ccache_link) { Params interfaceParams; - interfaceParams.insert("port", "core" + std::to_string(l) + "-ccache"); - ccache_link = loadAnonymousSubComponent( - "memHierarchy.memInterface", "core" + std::to_string(l) + "-ccache", + interfaceParams.insert("port", ccache_portname); + ccache_link = loadAnonymousSubComponent( + "memHierarchy.standardInterface", ccache_portname, 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, interfaceParams, tc, - new Interfaces::SimpleMem::Handler( + new Interfaces::StandardMem::Handler( this, &macsimComponent::handleConstCacheEvent)); } + if(!ccache_link) m_dbg->fatal(CALL_INFO, -1, "Configuring ccache link failed\n"); m_const_cache_links.push_back(ccache_link); m_const_cache_requests.push_back(std::map()); m_const_cache_responses.push_back(std::set()); - auto tcache_link = loadUserSubComponent( - "core" + std::to_string(l) + "-tcache", ComponentInfo::SHARE_NONE, tc, - new Interfaces::SimpleMem::Handler( + //////////////////////////////////////// + // Configure Texture Cache Link + std::string tcache_portname = "macsim" + std::to_string(m_macsim_component_num) + "_core" + std::to_string(l) + "_tcache"; + auto tcache_link = loadUserSubComponent( + tcache_portname, ComponentInfo::SHARE_NONE, tc, + new Interfaces::StandardMem::Handler( this, &macsimComponent::handleTextureCacheEvent)); if (!tcache_link) { Params interfaceParams; - interfaceParams.insert("port", "core" + std::to_string(l) + "-tcache"); - tcache_link = loadAnonymousSubComponent( - "memHierarchy.memInterface", "core" + std::to_string(l) + "-tcache", + interfaceParams.insert("port", tcache_portname); + tcache_link = loadAnonymousSubComponent( + "memHierarchy.standardInterface", tcache_portname, 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, interfaceParams, tc, - new Interfaces::SimpleMem::Handler( + new Interfaces::StandardMem::Handler( this, &macsimComponent::handleTextureCacheEvent)); } + if(!tcache_link) m_dbg->fatal(CALL_INFO, -1, "Configuring tcache link failed\n"); m_texture_cache_links.push_back(tcache_link); m_texture_cache_requests.push_back(std::map()); m_texture_cache_responses.push_back(std::set()); @@ -216,14 +252,20 @@ void macsimComponent::configureLinks(SST::Params& params, TimeConverter* tc) { } void macsimComponent::init(unsigned int phase) { - if (!phase) { - for (unsigned int l = 0; l < m_num_link; ++l) { - m_instruction_cache_links[l]->init(phase); - m_data_cache_links[l]->init(phase); - } + MSC_DEBUG("Participating in phase %d of init.\n", phase); - if (m_cube_connected) m_cube_link->init(phase); + // if (!phase) { + for (unsigned int l = 0; l < m_num_link; ++l) { + m_instruction_cache_links[l]->init(phase); + m_data_cache_links[l]->init(phase); + if (m_acc_core) { + m_const_cache_links[l]->init(phase); + m_texture_cache_links[l]->init(phase); + } } + + if (m_cube_connected) m_cube_link->init(phase); + // } } void macsimComponent::setup() { @@ -317,6 +359,23 @@ void macsimComponent::setup() { m_macsim->registerCallback(scr, scrq); } + + // Setup memory links + for (unsigned int l = 0; l < m_num_link; ++l) { // Standard CPU does this but others don't, why?? + m_instruction_cache_links[l]->setup(); + m_data_cache_links[l]->setup(); + if(m_acc_core){ + m_const_cache_links[l]->setup(); + m_texture_cache_links[l]->setup(); + } + } + if (m_cube_connected) m_cube_link->setup(); + +} + +void macsimComponent::complete(unsigned int phase) { + // output.verbose(CALL_INFO, 1, 0, "Component is participating in phase %d of complete.\n", phase); + MSC_DEBUG("Participating in phase %d of complete.\n", phase); } void macsimComponent::finish() { @@ -324,6 +383,7 @@ void macsimComponent::finish() { m_macsim->finalize(); } + /******************************************************* * ticReceived * return value @@ -403,22 +463,26 @@ bool macsimComponent::ticReceived(Cycle_t) { //////////////////////////////////////// void macsimComponent::sendInstructionCacheRequest(int core_id, uint64_t key, uint64_t addr, int size) { + // mask address to make sure it lies in address range + uint64_t req_addr = addr & (m_mem_size - 1); + #ifndef USE_VAULTSIM_HMC - SimpleMem::Request* req = new SimpleMem::Request( - SimpleMem::Request::Read, addr & (m_mem_size - 1), size); + // StandardMem::Request* req = new StandardMem::Request( + // StandardMem::Request::Read, addr & (m_mem_size - 1), size); + StandardMem::Request* req = new StandardMem::Read(req_addr, size); #else - SimpleMem::Request* req = new SimpleMem::Request( - SimpleMem::Request::Read, addr & (m_mem_size - 1), size, 0, HMC_NONE); + StandardMem::Request* req = new StandardMem::Request( + StandardMem::Request::Read, req_addr, size, 0, HMC_NONE); #endif - m_instruction_cache_links[core_id]->sendRequest(req); - m_instruction_cache_request_counters[core_id]++; - m_instruction_cache_requests[core_id].insert(make_pair(req->id, key)); + // Print out the request if (m_debug_all || m_debug_addr == addr) { MSC_DEBUG("I$[%d] request sent: addr = %#" PRIx64 " (orig addr = %#" PRIx64 - ", size = %d\n", - core_id, addr & 0x3FFFFFFF, addr, size); + "), size = %d\n", core_id, req_addr, addr, size); } + m_instruction_cache_links[core_id]->send(req); + m_instruction_cache_request_counters[core_id]++; + m_instruction_cache_requests[core_id].insert(make_pair(req->getID(), key)); } bool macsimComponent::strobeInstructionCacheRespQ(int core_id, uint64_t key) { @@ -433,17 +497,21 @@ bool macsimComponent::strobeInstructionCacheRespQ(int core_id, uint64_t key) { // incoming events are scanned and deleted void macsimComponent::handleInstructionCacheEvent( - Interfaces::SimpleMem::Request* req) { + Interfaces::StandardMem::Request* req) { for (unsigned int l = 0; l < m_num_link; ++l) { - auto i = m_instruction_cache_requests[l].find(req->id); + auto i = m_instruction_cache_requests[l].find(req->getID()); if (m_instruction_cache_requests[l].end() == i) { // No matching request continue; } else { - if (m_debug_all || m_debug_addr == req->addr) { - MSC_DEBUG("I$[%d] response arrived: addr = %#" PRIx64 "\n", l, - req->addr); - } + // Get request + auto m_instruction_req = m_instruction_cache_requests[l].find(req->getID()); // FIXME: + + if (m_debug_all/* || m_debug_addr == req->pAddr*/) { // FIXME: debugging a particular address requires sophisticated handling. see juno example + MSC_DEBUG("I$[%d] response arrived: (%s)\n", l, req->getString().c_str()); + // MSC_DEBUG("I$[%d] response arrived: addr = %#" PRIx64 ", size = %lu (%s)\n", + // l, req->pAddr, req->size, req->getString().c_str()); + } m_instruction_cache_responses[l].insert(i->second); m_instruction_cache_response_counters[l]++; m_instruction_cache_requests[l].erase(i); @@ -473,19 +541,41 @@ inline bool isStore(Mem_Type type) { #ifndef USE_VAULTSIM_HMC void macsimComponent::sendDataCacheRequest(int core_id, uint64_t key, uint64_t addr, int size, int type) { + // FIXME: + // mask address to make sure it lies in address range + uint64_t req_addr = addr & (m_mem_size - 1); + bool doWrite = isStore((Mem_Type)type); - SimpleMem::Request* req = new SimpleMem::Request( - doWrite ? SimpleMem::Request::Write : SimpleMem::Request::Read, - addr & (m_mem_size - 1), size); - m_data_cache_links[core_id]->sendRequest(req); - m_data_cache_request_counters[core_id]++; - m_data_cache_requests[core_id].insert(make_pair(req->id, key)); + + StandardMem::Request* req; + + if(doWrite) { + std::vector data; + + // Update the write request to push the data packets according to the size + for (int i = size; i > 0; i--) { + data.push_back((req_addr >> (8 * (i-1))) & 0xff); + } + + req = new StandardMem::Write(req_addr, size, data); + } + else { + req = new StandardMem::Read(req_addr, size); + } + + // StandardMem::Request* req = new StandardMem::Request( + // doWrite ? StandardMem::Request::Write : StandardMem::Request::Read, + // addr & (m_mem_size - 1), size); if (m_debug_all || m_debug_addr == addr) { MSC_DEBUG("D$[%d] request sent: addr = %#" PRIx64 " (orig addr = %#" PRIx64 - "), %s, size = %d\n", - core_id, addr & 0x3FFFFFFF, addr, doWrite ? "write" : "read", - size); + "), %s, size = %d\n", + core_id, req_addr, addr, doWrite ? "write" : "read", + size); } + + m_data_cache_links[core_id]->send(req); + m_data_cache_request_counters[core_id]++; + m_data_cache_requests[core_id].insert(make_pair(req->getID(), key)); } #else void macsimComponent::sendDataCacheRequest(int core_id, uint64_t key, @@ -495,11 +585,11 @@ void macsimComponent::sendDataCacheRequest(int core_id, uint64_t key, bool doWrite = isStore((Mem_Type)type); unsigned flag = 0; if ((hmc_type & 0x0080) != 0) { - flag = SimpleMem::Request::F_NONCACHEABLE; + flag = StandardMem::Request::F_NONCACHEABLE; hmc_type = hmc_type & 0b01111111; } - SimpleMem::Request* req = new SimpleMem::Request( - doWrite ? SimpleMem::Request::Write : SimpleMem::Request::Read, + StandardMem::Request* req = new StandardMem::Request( + doWrite ? StandardMem::Request::Write : StandardMem::Request::Read, addr & (m_mem_size - 1), size, flag, hmc_type); m_data_cache_links[core_id]->sendRequest(req); m_data_cache_request_counters[core_id]++; @@ -525,16 +615,19 @@ bool macsimComponent::strobeDataCacheRespQ(int core_id, uint64_t key) { // incoming events are scanned and deleted void macsimComponent::handleDataCacheEvent( - Interfaces::SimpleMem::Request* req) { + Interfaces::StandardMem::Request* req) { for (unsigned int l = 0; l < m_num_link; ++l) { - auto i = m_data_cache_requests[l].find(req->id); + auto i = m_data_cache_requests[l].find(req->getID()); if (m_data_cache_requests[l].end() == i) { // No matching request continue; } else { - if (m_debug_all || m_debug_addr == req->addr) { - MSC_DEBUG("D$[%d] response arrived: addr = %#" PRIx64 ", size = %lu\n", - l, req->addr, req->size); + // FIXME: + if (m_debug_all /*|| m_debug_addr == req->pAddr*/) { + MSC_DEBUG("D$[%d] response arrived: (%s)\n", + l, req->getString().c_str()); + // MSC_DEBUG("D$[%d] response arrived: addr = %#" PRIx64 ", size = %lu (%s)\n", + // l, req->pAddr, req->size, req->getString().c_str()); } m_data_cache_responses[l].insert(i->second); m_data_cache_response_counters[l]++; @@ -552,17 +645,17 @@ void macsimComponent::handleDataCacheEvent( //////////////////////////////////////// void macsimComponent::sendConstCacheRequest(int core_id, uint64_t key, uint64_t addr, int size) { - SimpleMem::Request* req = new SimpleMem::Request( - SimpleMem::Request::Read, addr & (m_mem_size - 1), size); - m_const_cache_links[core_id]->sendRequest(req); - m_const_cache_request_counters[core_id]++; - m_const_cache_requests[core_id].insert(make_pair(req->id, key)); + uint64_t req_addr = addr & (m_mem_size - 1); + StandardMem::Request* req = new StandardMem::Read(req_addr, size); if (m_debug_all || m_debug_addr == addr) { MSC_DEBUG("C$[%d] request sent: addr = %#" PRIx64 " (orig addr = %#" PRIx64 ", size = %d\n", - core_id, addr & (m_mem_size - 1), addr, size); + core_id, req_addr, addr, size); } + m_const_cache_links[core_id]->send(req); + m_const_cache_request_counters[core_id]++; + m_const_cache_requests[core_id].insert(make_pair(req->getID(), key)); } bool macsimComponent::strobeConstCacheRespQ(int core_id, uint64_t key) { @@ -577,16 +670,16 @@ bool macsimComponent::strobeConstCacheRespQ(int core_id, uint64_t key) { } // incoming events are scanned and deleted -void macsimComponent::handleConstCacheEvent( - Interfaces::SimpleMem::Request* req) { +void macsimComponent::handleConstCacheEvent(Interfaces::StandardMem::Request* req) { for (unsigned int l = 0; l < m_num_link; ++l) { - auto i = m_const_cache_requests[l].find(req->id); + auto i = m_const_cache_requests[l].find(req->getID()); if (m_const_cache_requests[l].end() == i) { // No matching request continue; } else { - if (m_debug_all || m_debug_addr == req->addr) { - MSC_DEBUG("C$[%d] response arrived: addr = %#" PRIx64 ", size = %lu\n", - l, req->addr, req->size); + if (m_debug_all/* || m_debug_addr == req->pAddr*/) { // FIXME: debugging a particular address requires sophisticated handling. see juno example + MSC_DEBUG("C$[%d] response arrived: (%s)\n", l, req->getString().c_str()); + // MSC_DEBUG("I$[%d] response arrived: addr = %#" PRIx64 ", size = %lu (%s)\n", + // l, req->pAddr, req->size, req->getString().c_str()); } m_const_cache_responses[l].insert(i->second); m_const_cache_response_counters[l]++; @@ -605,14 +698,18 @@ void macsimComponent::handleConstCacheEvent( //////////////////////////////////////// void macsimComponent::sendTextureCacheRequest(int core_id, uint64_t key, uint64_t addr, int size) { - SimpleMem::Request* req = new SimpleMem::Request( - SimpleMem::Request::Read, addr & (m_mem_size - 1), size); - m_texture_cache_links[core_id]->sendRequest(req); - m_texture_cache_request_counters[core_id]++; - m_texture_cache_requests[core_id].insert(make_pair(req->id, key)); + // mask address to make sure it lies in address range + uint64_t req_addr = addr & (m_mem_size - 1); + StandardMem::Request* req = new StandardMem::Read(req_addr, size); + MSC_DEBUG("T$[%d] request sent: addr = %#" PRIx64 " (orig addr = %#" PRIx64 - ", size = %d\n", - core_id, addr & (m_mem_size - 1), addr, size); + ", size = %d\n", + core_id, req_addr, addr, size); + + m_texture_cache_links[core_id]->send(req); + m_texture_cache_request_counters[core_id]++; + m_texture_cache_requests[core_id].insert(make_pair(req->getID(), key)); + } bool macsimComponent::strobeTextureCacheRespQ(int core_id, uint64_t key) { @@ -628,15 +725,17 @@ bool macsimComponent::strobeTextureCacheRespQ(int core_id, uint64_t key) { // incoming events are scanned and deleted void macsimComponent::handleTextureCacheEvent( - Interfaces::SimpleMem::Request* req) { + Interfaces::StandardMem::Request* req) { +// FIXME: for (unsigned int l = 0; l < m_num_link; ++l) { - auto i = m_texture_cache_requests[l].find(req->id); + auto i = m_texture_cache_requests[l].find(req->getID()); if (m_texture_cache_requests[l].end() == i) { // No matching request continue; } else { - if (m_debug_all || m_debug_addr == req->addr) { - MSC_DEBUG("T$[%d] response arrived: addr = %#" PRIx64 ", size = %lu\n", - l, req->addr, req->size); + if (m_debug_all/* || m_debug_addr == req->pAddr*/) { // FIXME: debugging a particular address requires sophisticated handling. see juno example + MSC_DEBUG("T$[%d] response arrived: (%s)\n", l, req->getString().c_str()); + // MSC_DEBUG("I$[%d] response arrived: addr = %#" PRIx64 ", size = %lu (%s)\n", + // l, req->pAddr, req->size, req->getString().c_str()); } m_texture_cache_responses[l].insert(i->second); m_texture_cache_response_counters[l]++; @@ -655,18 +754,35 @@ void macsimComponent::handleTextureCacheEvent( //////////////////////////////////////// void macsimComponent::sendCubeRequest(uint64_t key, uint64_t addr, int size, int type) { + // mask address to make sure it lies in address range + uint64_t req_addr = addr & (m_mem_size - 1); + bool doWrite = isStore((Mem_Type)type); - SimpleMem::Request* req = new SimpleMem::Request( - doWrite ? SimpleMem::Request::Write : SimpleMem::Request::Read, - addr & 0x3FFFFFFF, size); - m_cube_link->sendRequest(req); + StandardMem::Request* req; + if(doWrite) { + std::vector data; + data.push_back((req_addr >> 24) & 0xff); + data.push_back((req_addr >> 16) & 0xff); + data.push_back((req_addr >> 8) & 0xff); + data.push_back((req_addr >> 0) & 0xff); + req = new StandardMem::Write(req_addr, size, data); + } + else { + req = new StandardMem::Read(req_addr, size); + } +// FIXME: +// bool doWrite = isStore((Mem_Type)type); +// StandardMem::Request* req = new StandardMem::Request( +// doWrite ? StandardMem::Request::Write : StandardMem::Request::Read, +// addr & 0x3FFFFFFF, size); +// m_cube_link->sendRequest(req); if (m_debug_all || m_debug_addr == addr) { MSC_DEBUG("Cube request sent: addr = %#" PRIx64 "(orig addr = %#" PRIx64 "), %s %s, size = %d\n", addr & 0x3FFFFFFF, addr, (type == -1) ? "instruction" : "data", doWrite ? "write" : "read", size); } - m_cube_requests.insert(make_pair(req->id, key)); + m_cube_requests.insert(make_pair(req->getID(), key)); } bool macsimComponent::strobeCubeRespQ(uint64_t key) { @@ -680,15 +796,17 @@ bool macsimComponent::strobeCubeRespQ(uint64_t key) { } // incoming events are scanned and deleted -void macsimComponent::handleCubeEvent(Interfaces::SimpleMem::Request* req) { - auto i = m_cube_requests.find(req->id); +void macsimComponent::handleCubeEvent(Interfaces::StandardMem::Request* req) { + auto i = m_cube_requests.find(req->getID()); if (m_cube_requests.end() == i) { // No matching request - m_dbg->fatal(CALL_INFO, -1, "Event (%#" PRIx64 ") not found!\n", req->id); + m_dbg->fatal(CALL_INFO, -1, "Event (%#" PRIx64 ") not found!\n", req->getID()); } else { - if (m_debug_all || m_debug_addr == req->addr) { - MSC_DEBUG("Cube response arrived: addr = %#" PRIx64 ", size = %lu\n", - req->addr, req->size); + if (m_debug_all /*|| m_debug_addr == req->pAddr*/) { + MSC_DEBUG("Cube request sent response arrived: (%s)\n", + req->getString().c_str()); + // MSC_DEBUG("D$[%d] response arrived: addr = %#" PRIx64 ", size = %lu (%s)\n", + // l, req->pAddr, req->size, req->getString().c_str()); } m_cube_responses.insert(i->second); m_cube_requests.erase(i); diff --git a/macsimComponent.h b/macsimComponent.h index cc625f9ee..61e778bc2 100644 --- a/macsimComponent.h +++ b/macsimComponent.h @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include "src/macsim.h" @@ -40,11 +40,15 @@ class macsimComponent : public SST::Component { public: /* SST ELI */ - SST_ELI_REGISTER_COMPONENT(macsimComponent, "macsimComponent", - "macsimComponent", - SST_ELI_ELEMENT_VERSION(1, 0, 0), - "A Heterogeneous Architecture Simulator", - COMPONENT_CATEGORY_PROCESSOR) + SST_ELI_REGISTER_COMPONENT( + macsimComponent, // Class Name + "macsimComponent", // Name of Library + "macsimComponent", // Lookup name for the component + SST_ELI_ELEMENT_VERSION(1, 0, 0), // Component version + "A Heterogeneous Architecture Simulator", // Description + COMPONENT_CATEGORY_PROCESSOR + ) + SST_ELI_DOCUMENT_PARAMS( {"param_file", "params.in", NULL}, {"trace_file", "trace_file_list", NULL}, {"output_dir", "output (stats, params.out, etc.) directory", NULL}, @@ -67,20 +71,24 @@ class macsimComponent : public SST::Component SST_ELI_DOCUMENT_PORTS( {"ipc_link", "Port for Inter Processor Communication", {}}, - {"core%(core_id)d-icache", "Ports connected to instruction cache", {}}, - {"core%(core_id)d-dcache", "Ports connected to data cache", {}}, - {"core%(core_id)d-ccache", + {"macsim%(macsim_id)d_core%(core_id)d_icache", "Ports connected to instruction cache", {}}, + {"macsim%(macsim_id)d_core%(core_id)d_dcache", "Ports connected to data cache", {}}, + {"macsim%(macsim_id)d_core%(core_id)d_ccache", "Ports connected to const cache (only for GPU core)", {}}, - {"core%(core_id)d-tcache", + {"macsim%(macsim_id)d_core%(core_id)d_tcache", "Ports connected to texture cache (only for GPU core)", {}}) public: macsimComponent(SST::ComponentId_t id, SST::Params ¶ms); - void init(unsigned int phase); - void setup(); - void finish(); + + // SST lifecycle functions + void init(unsigned int phase) override; + void setup() override; + void complete(unsigned int phase) override; + void finish() override; + // void emergencyShutdown() override; private: macsimComponent(); // for serialization only @@ -90,11 +98,23 @@ class macsimComponent : public SST::Component void configureLinks(SST::Params ¶ms, TimeConverter *tc); virtual bool ticReceived(Cycle_t); - void handleInstructionCacheEvent(SimpleMem::Request *req); - void handleDataCacheEvent(SimpleMem::Request *req); - void handleConstCacheEvent(SimpleMem::Request *req); - void handleTextureCacheEvent(SimpleMem::Request *req); - void handleCubeEvent(SimpleMem::Request *req); + + // TODO: Correct way to implement handlers: see juno example + // class ICacheHandlers : public Interfaces::StandardMem::RequestHandler { + // public: + // friend class macsimComponent; + // macsimComponent* macsim_component; + // MemHandlers(macsimComponent* macsim_component, SST::Output* out) : Interfaces::StandardMem::RequestHandler(out), macsim_component(macsim_component) {} + // virtual ~MemHandlers() {} + // virtual void handle(Interfaces::StandardMem::ReadResp* resp) override; + // virtual void handle(Interfaces::StandardMem::WriteResp* resp) override; + // }; + + void handleInstructionCacheEvent(Interfaces::StandardMem::Request *req); + void handleDataCacheEvent(Interfaces::StandardMem::Request *req); + void handleConstCacheEvent(Interfaces::StandardMem::Request *req); + void handleTextureCacheEvent(Interfaces::StandardMem::Request *req); + void handleCubeEvent(Interfaces::StandardMem::Request *req); string m_param_file; string m_trace_file; @@ -117,12 +137,13 @@ class macsimComponent : public SST::Component SST::Link *m_ipc_link; // links + uint32_t m_macsim_component_num; // Specify Macsim component num uint32_t m_num_link; - vector m_instruction_cache_links; - vector m_data_cache_links; - vector m_const_cache_links; - vector m_texture_cache_links; - Interfaces::SimpleMem *m_cube_link; + vector m_instruction_cache_links; + vector m_data_cache_links; + vector m_const_cache_links; + vector m_texture_cache_links; + Interfaces::StandardMem *m_cube_link; // debugging vector m_instruction_cache_request_counters; @@ -167,6 +188,7 @@ class macsimComponent : public SST::Component bool strobeTextureCacheRespQ(int, uint64_t); bool strobeCubeRespQ(uint64_t); + TimeConverter* tc; Output *m_dbg; Cycle_t m_cycle; }; // class macsimComponent diff --git a/macsimEvent.h b/macsimEvent.h index b20fde77b..383637e45 100644 --- a/macsimEvent.h +++ b/macsimEvent.h @@ -1,6 +1,8 @@ #ifndef MACSIM_EVENT_H #define MACSIM_EVENT_H +#include + namespace SST { namespace MacSim { @@ -21,7 +23,7 @@ class MacSimEvent : public SST::Event m_type = type; } - NotSerializable(MacSimEvent) + NotSerializable(MacSimEvent); private : MacSimEventType m_type; diff --git a/src/exec.cc b/src/exec.cc index 43d3bd3c7..f7952f24d 100644 --- a/src/exec.cc +++ b/src/exec.cc @@ -318,7 +318,7 @@ bool exec_c::exec(int thread_id, int entry, uop_c* uop) { // constant memory if (uop->m_mem_type == MEM_LD_CM) { #ifdef USING_SST - uop_latency = access_const_texture_cache(uop); + uop_latency = access_const_texture_cache(uop); //FIXME: Is this correct ? #else uop_latency = core->get_const_cache()->load(uop); #endif @@ -789,7 +789,7 @@ void exec_c::run_a_cycle(void) { #ifdef USING_SST // Strobing core_c* core = m_simBase->m_core_pointers[m_core_id]; - for (auto I = m_uop_buffer.begin(), E = m_uop_buffer.end(); I != E; I++) { + for (auto I = m_uop_buffer.begin(); I != m_uop_buffer.end(); ) { uint64_t key = I->first; uop_c* uop = I->second; @@ -851,7 +851,9 @@ void exec_c::run_a_cycle(void) { "from memHierarchy!\n", m_core_id, uop->m_thread_id, uop->m_uop_num, uop->m_inst_num, uop->m_vaddr); - m_uop_buffer.erase(I); + I = m_uop_buffer.erase(I); // erase returns next valid iterator + } else { + ++I; } } #else // USING_SST @@ -901,8 +903,12 @@ int exec_c::access_data_cache(uop_c* uop) { // if the requested block spans a cache line boundary, generate only one request for the first block Addr offset = uop->m_vaddr % block_size; - if (offset + uop->m_mem_size > block_size) + if ((offset + uop->m_mem_size) > block_size){ uop->m_mem_size = block_size - offset; + }else if(uop->m_mem_size == 0 && offset == 0){ + // Manually change the mem_size to be 16 when getting a zero mem_size and offset to avoid runtime error with SST + uop->m_mem_size = 16; + } DEBUG_CORE(m_core_id, "sending memory request (core_id:%d thread_id:%d uop_num:%llu " @@ -968,8 +974,12 @@ int exec_c::access_const_texture_cache(uop_c* uop) { // if the requested block spans a cache line boundary, generate only one request for the first block Addr offset = uop->m_vaddr % block_size; - if (offset + uop->m_mem_size > block_size) + if ((offset + uop->m_mem_size) > block_size){ uop->m_mem_size = block_size - offset; + }else if(uop->m_mem_size == 0 && offset == 0){ + // Manually change the mem_size to be 16 when getting a zero mem_size and offset to avoid runtime error with SST + uop->m_mem_size = 16; + } if (uop->m_mem_type == MEM_LD_CM) { DEBUG_CORE(m_core_id, diff --git a/src/global_defs.h b/src/global_defs.h index 1dfbeceb9..e685893d0 100644 --- a/src/global_defs.h +++ b/src/global_defs.h @@ -238,9 +238,9 @@ typedef SST::MacSim::CallbackBase CallbackStrobeTextureCacheRespQ; typedef SST::MacSim::CallbackBase CallbackStrobeCubeRespQ; +// Update the UNIQUE_KEY to allow a max of 4096 different threads IDs #define UNIQUE_KEY(C, T, U, A, I) \ - ((A << 35) | ((U & 0xFFF) << 23) | ((C & 0x3F) << 17) | ((T & 0x7F) << 10) | \ - I) + ((A << 36) | ((U & 0xFFF) << 24) | ((C & 0x3F) << 18) | ((T & 0xFFF) << 6) | (I & 0x3F)) #endif // USING_SST #endif diff --git a/src/global_types.h b/src/global_types.h index 6cf323aca..b21529b59 100644 --- a/src/global_types.h +++ b/src/global_types.h @@ -83,6 +83,7 @@ typedef enum uop_latency_map { // enum for x86 latency maps - Michael typedef enum _ACC_Type_enum { NO_ACC = 0, /**< no accelerator */ PTX_CORE, /**< PTX core */ - IGPU_CORE /**< IGPU core */ + IGPU_CORE, /**< IGPU core */ + NVBIT_CORE/**< NVBIT core */ } ACC_Type; #endif diff --git a/src/macsim.cc b/src/macsim.cc index dbf5b7b9b..ff53c9b2f 100644 --- a/src/macsim.cc +++ b/src/macsim.cc @@ -182,9 +182,9 @@ void macsim_c::register_functions(void) { #ifdef DRAMSIM dram_factory_c::get()->register_class("DRAMSIM", dramsim_controller); #endif -#ifdef USING_SST - dram_factory_c::get()->register_class("VAULTSIM", vaultsim_controller); -#endif +// #ifdef USING_SST // ** DEPRICATED ** +// dram_factory_c::get()->register_class("VAULTSIM", vaultsim_controller); +// #endif fetch_factory_c::get()->register_class("rr", fetch_factory); pref_factory_c::get()->register_class(pref_factory); diff --git a/sst-unit-test/common.py b/sst-unit-test/common.py new file mode 100644 index 000000000..9e90583d9 --- /dev/null +++ b/sst-unit-test/common.py @@ -0,0 +1,26 @@ +################################################################################ +# Util functions + +KIB = 1024 +MIB = 1024 * KIB +GIB = 1024 * MIB + +def bytes2str(nbytes): + if nbytes >= GIB: + return "%dGiB" % (nbytes / GIB) + elif nbytes >= MIB: + return "%dMiB" % (nbytes / MIB) + elif nbytes >= KIB: + return "%dKiB" % (nbytes / KIB) + else: + return "%dB" % nbytes + +def str2bytes(s): + if s.endswith("GiB"): + return int(s[:-3]) * GIB + elif s.endswith("MiB"): + return int(s[:-3]) * MIB + elif s.endswith("KiB"): + return int(s[:-3]) * KIB + else: + return int(s) diff --git a/sst-unit-test/macsimComponent-test-002_i.py b/sst-unit-test/macsimComponent-test-002_i.py new file mode 100644 index 000000000..4ec9baa9d --- /dev/null +++ b/sst-unit-test/macsimComponent-test-002_i.py @@ -0,0 +1,114 @@ +import sst + +################################################################################ +# Parameters +DEBUG_L1 = 1 +DEBUG_MEM = 1 +DEBUG_CORE = 1 +DEBUG_LEVEL = 10 + +MEM_SIZE_S = '512MiB' + +MEM_SIZE = str2bytes(MEM_SIZE_S) +MEM_START = 0 +MEM_END = MEM_START + MEM_SIZE - 1 + +print("MEM_SIZE: %d (%s): 0x%x - 0x%x" % (MEM_SIZE, MEM_SIZE_S, MEM_START, MEM_END)) + + +################################################################################ +# Macsim -> L1 Caches -> (MemController) Memory +################################################################################ +macsim = sst.Component("macsim", "macsimComponent.macsimComponent") +macsim.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=1 --num_sim_large_cores=1 --num_sim_small_cores=0 --use_memhierarchy=1 --core_type=x86", + "frequency" : "2GHz", + "num_cores" : "1", + "num_links": "1", + "mem_size" : MEM_SIZE, + "debug_level": "9", +}) + +l1_icache = sst.Component("l1_icache", "memHierarchy.Cache") +l1_icache.addParams({ + "access_latency_cycles" : "4", + "cache_frequency" : "2 Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug_level" : DEBUG_LEVEL, + "L1" : "1", + "debug" : DEBUG_L1, + "cache_size" : "64 KB" +}) + +l1_dcache = sst.Component("l1_dcache", "memHierarchy.Cache") +l1_dcache.addParams({ + "access_latency_cycles" : "4", + "cache_frequency" : "2 Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug_level" : DEBUG_LEVEL, + "L1" : "1", + "debug" : DEBUG_L1, + "cache_size" : "64 KB" +}) + +# Bus between caches and memory controller +mem_bus = sst.Component("mem_bus", "memHierarchy.Bus") +mem_bus.addParams({ + "debug" : "8", + "bus_frequency" : "4 Ghz" +}) + +# Memory Controller +memctrl = sst.Component("memory", "memHierarchy.MemController") +memctrl.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + # "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) + +# Memory +memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") +memory.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + + +######################################## +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") + +######################################## +# Links + +# Macsim::icache -> l1_icache +link_msi_l1icache = sst.Link("link_msi_l1icache") +link_msi_l1icache.connect((macsim, "core0_icache", "1000ps"), (l1_icache, "highlink", "1000ps")) + +# Macsim::dcache -> l1_dcache +link_msd_l1dcache = sst.Link("link_msd_l1dcache") +link_msd_l1dcache.connect((macsim, "core0_dcache", "1000ps"), (l1_dcache, "highlink", "1000ps")) + +# L1_icache -> Bus +link_l1icache_bus = sst.Link("link_l1icache_bus") +link_l1icache_bus.connect((l1_icache, "lowlink", "50ps"), (mem_bus, "highlink0", "50ps")) + +# L1_dcache -> Bus +# link_l1dcache_bus = sst.Link("link_l1dcache_bus") +# link_l1dcache_bus.connect((l1_dcache, "lowlink", "50ps"), (mem_bus, "highlink1", "50ps")) + +# Bus -> memctrl +link_bus_memctrl = sst.Link("link_bus_memctrl") +link_bus_memctrl.connect((mem_bus, "lowlink0", "50ps"), (memctrl, "highlink", "50ps")) diff --git a/sst-unit-test/macsimComponent-test-002_port.py b/sst-unit-test/macsimComponent-test-002_port.py new file mode 100644 index 000000000..d270e9b15 --- /dev/null +++ b/sst-unit-test/macsimComponent-test-002_port.py @@ -0,0 +1,130 @@ +################################################################################ +# Description: +# - Macsim is connected to L1 caches, followed by a bus and memory controller. +# - Macsim ports (stdInterface) are loaded as subcomponents explictly. +################################################################################ +import sst +from common import * + +# 0: None, 1: Stdout, 2: Stderr, 3: File +DEBUG_CORE = 1 +DEBUG_L1 = 0 +DEBUG_MEM = 1 + +DEBUG_LINKS = 0 +DEBUG_BUS = 0 + +DEBUG_LEVEL = 5 +VERBOSE = 10 + +######################################## +# System Parameters +MEM_SIZE_S = '512MiB' +MEM_SIZE = str2bytes(MEM_SIZE_S) +MEM_START = 0 +MEM_END = MEM_START + MEM_SIZE - 1 + + +######################################## +# Macsim +macsim = sst.Component("macsimComponent", "macsimComponent.macsimComponent") +macsim.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=1 --num_sim_large_cores=1 --num_sim_small_cores=0 --use_memhierarchy=1 --core_type=x86", + "frequency" : "2GHz", + "num_cores" : "1", + "num_links": "1", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, +}) + + +######################################## +# L1 Caches +core0_icache = sst.Component("core0_icache", "memHierarchy.Cache") +core0_icache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +core0_dcache = sst.Component("core0_dcache", "memHierarchy.Cache") +core0_dcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +######################################## +# Bus between L1 caches and memory controller +mem_bus = sst.Component("mem_bus", "memHierarchy.Bus") +mem_bus.addParams({ + "debug" : DEBUG_LINKS, + "debug_level" : DEBUG_LEVEL, + "bus_frequency" : "4 Ghz" +}) + + +######################################## +# Memory Controller +memctrl = sst.Component("memctrl", "memHierarchy.MemController") +memctrl.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + # "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") +memory.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + + +######################################## +# Links + +# Macsim::core0_icache -> L1 ICache +link_macsim_icache = sst.Link("link_macsim_icache") +link_macsim_icache.connect( (macsim, "core0_icache", "1000ps"), (core0_icache, "high_network_0", "1000ps") ) + +# Macsim::core0_dcache -> L1 DCache +link_macsim_dcache = sst.Link("link_macsim_dcache") +link_macsim_dcache.connect( (macsim, "core0_dcache", "1000ps"), (core0_dcache, "high_network_0", "1000ps") ) + +# L1 I/DCache -> Bus +link_icache_bus = sst.Link("link_icache_bus") +link_icache_bus.connect( (core0_icache, "low_network_0", "50ps"), (mem_bus, "high_network_0", "50ps") ) +link_dcache_bus = sst.Link("link_dcache_bus") +link_dcache_bus.connect( (core0_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_1", "50ps") ) + +# Bus -> Memory +link_bus_mem = sst.Link("link_bus_mem") +link_bus_mem.connect( (mem_bus, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) + + +######################################## +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") \ No newline at end of file diff --git a/sst-unit-test/params.in b/sst-unit-test/params.in index 5b00ac3aa..05228b2bf 100644 --- a/sst-unit-test/params.in +++ b/sst-unit-test/params.in @@ -2,38 +2,38 @@ # Simulation Configuration num_sim_cores 16 num_sim_small_cores 16 -core_type ptx -max_threads_per_core 80 +core_type nvbit +max_threads_per_core 1024 num_sim_medium_cores 0 num_sim_large_cores 0 # Clock # from device query for gtx580 on damint - gpu clock - 1.66 GHz, mem clock - 2100 MHz -clock_cpu 4.0 -clock_gpu 4.0 -clock_llc 4.0 -clock_noc 4.0 -clock_mc 4.0 +clock_cpu 2.0 +clock_gpu 2.0 +clock_llc 2.0 +clock_noc 2.0 +clock_mc 2.0 # Small Core Configuration -fetch_wdith 2 +fetch_wdith 4 width 1 fetch_latency 5 alloc_latency 5 rob_size 1024 schedule ooo isched_rate 4 -msched_rate 2 -fsched_rate 2 +msched_rate 4 +fsched_rate 4 bp_hist_length 14 -max_block_per_core 4 +max_block_per_core 8 fetch_policy rr mt_no_fetch_br 1 fetch_only_load_ready 0 -schedule_ratio 2 -fetch_ratio 2 +schedule_ratio 4 +fetch_ratio 4 gpu_sched 1 icache_num_set 8 @@ -53,21 +53,25 @@ shared_mem_cycles 2 shared_mem_ports 1 byte_level_access 0 -l1_small_line_size 128 -#48 KB -l1_small_num_set 64 +l1_small_line_size 64 +#96 KB +l1_small_num_set 128 l1_small_assoc 6 #16 KB #l1_small_num_set 32 #l1_small_assoc 4 -# L3 Cache -num_llc 6 +l1_small_latency 30 +l2_small_latency 100 +llc_latency 200 + +# L3 Cache (4.5MB 24 way) +num_llc 12 llc_num_set 128 llc_line_size 128 -llc_assoc 8 +llc_assoc 24 llc_num_bank 4 -llc_latency 10 +llc_latency 200 # DRAM @@ -77,7 +81,7 @@ dram_column 11 dram_activate 25 dram_precharge 10 dram_num_banks 16 -dram_num_channel 1 +dram_num_channel 8 dram_rowbuffer_size 2048 dram_scheduling_policy FRFCFS @@ -94,7 +98,7 @@ bug_detector_enable 1 sim_cycle_count 0 max_insts 200000000 heartbeat_interval 1000000 -forward_progress_limit 50000 +forward_progress_limit 100000 blocks_to_simulate 0 ptx_exec_ratio 2 num_warp_scheduler 2 @@ -117,6 +121,7 @@ debug_retire_stage 0 debug_map_stage 0 debug_mem 0 debug_trace_read 0 +debug_print_trace 1 debug_sim_thread_schedule 0 debug_cache_lib 0 debug_bp_dir 0 diff --git a/sst-unit-test/sdl-00-instantiation.py b/sst-unit-test/sdl-00-instantiation.py new file mode 100644 index 000000000..68ffbf2f6 --- /dev/null +++ b/sst-unit-test/sdl-00-instantiation.py @@ -0,0 +1,20 @@ +################################################################################ +# Description: +# - macsimComponent instantiation test +# - It will fail since nothing is connected +# - It should something similar to the folowing: +# FATAL: macsimComponent, Error: unable to configure link on port 'core0_icache' +# SST Fatal Backtrace Information: +# ... +################################################################################ +import sst + +obj = sst.Component("macsimComponent", "macsimComponent.macsimComponent") +obj.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list", + "output_dir": "output_dir", + "frequency" : "2GHz", + "num_cores" : "4", + "cache_size" : "512KB" +}) diff --git a/sst-unit-test/sdl-01a-cpu-split-hier-port.py b/sst-unit-test/sdl-01a-cpu-split-hier-port.py new file mode 100644 index 000000000..6abcb44ef --- /dev/null +++ b/sst-unit-test/sdl-01a-cpu-split-hier-port.py @@ -0,0 +1,97 @@ +################################################################################ +# Description: +# - Macsim is connected to 2 individual memory controllers for instruction and +# data memory +################################################################################ +import sst +from common import * + +# 0: None, 1: Stdout, 2: Stderr, 3: File +DEBUG_CORE = 1 # Macsim +DEBUG_CORE_LINKS = 1 # Ports/Subcomponents of Macsim + +DEBUG_L1 = 0 # L1 Caches +DEBUG_L2 = 0 # L2 Caches +DEBUG_MEM = 1 # Memory Controllers + +DEBUG_LINKS = 0 # Links +DEBUG_BUS = 0 # Buses + +DEBUG_LEVEL = 5 # Debug Level +VERBOSE = 10 # Verbose Level + +######################################## +# System Parameters +MEM_SIZE_S = '512MiB' +MEM_SIZE = str2bytes(MEM_SIZE_S) +MEM_START = 0 +MEM_END = MEM_START + MEM_SIZE - 1 + + +######################################## +# Macsim +macsim = sst.Component("macsimComponent", "macsimComponent.macsimComponent") +macsim.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list_cpu", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=1 --num_sim_large_cores=1 --num_sim_small_cores=0 --use_memhierarchy=1 --core_type=x86", + "frequency" : "2GHz", + "num_cores" : "1", + "num_link": "1", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, +}) + + +######################################## +# Instruction Memory Controller +memctrl_i = sst.Component("memory_i", "memHierarchy.MemController") +memctrl_i.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + # "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory_i = memctrl_i.setSubComponent("backend", "memHierarchy.simpleMem") +memory_i.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + + +######################################## +# Data Memory Controller +memctrl_d = sst.Component("memory_d", "memHierarchy.MemController") +memctrl_d.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory_d = memctrl_d.setSubComponent("backend", "memHierarchy.simpleMem") +memory_d.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + + +######################################## +# Links +link_bus_memctrl_i = sst.Link("link_bus_memctrl_i") +link_bus_memctrl_i.connect((macsim, "macsim0_core0_icache", "50ps"), (memctrl_i, "direct_link", "50ps")) +link_bus_memctrl_d = sst.Link("link_bus_memctrl_d") +link_bus_memctrl_d.connect((macsim, "macsim0_core0_dcache", "50ps"), (memctrl_d, "direct_link", "50ps")) + + +######################################## +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") +# sst.setStatisticOutput("sst.statOutputCSV", {"filepath" : "./sst_stats.csv", "separator" : ", " } ) + +sst.enableAllStatisticsForComponentType("memHierarchy.MemController") diff --git a/sst-unit-test/sdl-01b-cpu-split-hier-subcomp.py b/sst-unit-test/sdl-01b-cpu-split-hier-subcomp.py new file mode 100644 index 000000000..f79931f47 --- /dev/null +++ b/sst-unit-test/sdl-01b-cpu-split-hier-subcomp.py @@ -0,0 +1,109 @@ +################################################################################ +# Description: +# - Macsim is connected to 2 individual memory controllers for instruction and +# data memory. +# - Macsim ports (stdInterface) are loaded as subcomponents explictly. +################################################################################ +import sst +from common import * + +# 0: None, 1: Stdout, 2: Stderr, 3: File +DEBUG_CORE = 1 +DEBUG_CORE_LINKS = 0 +DEBUG_L1 = 0 +DEBUG_L2 = 0 # L2 Caches +DEBUG_MEM = 1 + +DEBUG_LINKS = 0 +DEBUG_BUS = 0 + +DEBUG_LEVEL = 0 +VERBOSE = 0 + +######################################## +# System Parameters +MEM_SIZE_S = '512MiB' +MEM_SIZE = str2bytes(MEM_SIZE_S) +MEM_START = 0 +MEM_END = MEM_START + MEM_SIZE - 1 + + +######################################## +# Macsim +macsim = sst.Component("macsimComponent", "macsimComponent.macsimComponent") +macsim.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list_cpu", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=1 --num_sim_large_cores=1 --num_sim_small_cores=0 --use_memhierarchy=1 --core_type=x86", + "frequency" : "2GHz", + "num_cores" : "1", + "num_link": "1", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, +}) +macsim_icache_if = macsim.setSubComponent("macsim0_core0_icache", "memHierarchy.standardInterface") +macsim_icache_if.addParams({ + 'debug': DEBUG_CORE_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_dcache_if = macsim.setSubComponent("macsim0_core0_dcache", "memHierarchy.standardInterface") +macsim_dcache_if.addParams({ + 'debug': DEBUG_CORE_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + + +######################################## +# Instruction Memory Controller +memctrl_i = sst.Component("memory_i", "memHierarchy.MemController") +memctrl_i.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + # "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory_i = memctrl_i.setSubComponent("backend", "memHierarchy.simpleMem") +memory_i.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + + +######################################## +# Data Memory Controller +memctrl_d = sst.Component("memory_d", "memHierarchy.MemController") +memctrl_d.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory_d = memctrl_d.setSubComponent("backend", "memHierarchy.simpleMem") +memory_d.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + + +######################################## +# Links +link_bus_memctrl_i = sst.Link("link_bus_memctrl_i") +link_bus_memctrl_i.connect((macsim_icache_if, "port", "50ps"), (memctrl_i, "direct_link", "50ps")) +link_bus_memctrl_d = sst.Link("link_bus_memctrl_d") +link_bus_memctrl_d.connect((macsim_dcache_if, "port", "50ps"), (memctrl_d, "direct_link", "50ps")) + + +######################################## +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") +# sst.setStatisticOutput("sst.statOutputCSV", {"filepath" : "./sst_stats.csv", "separator" : ", " } ) + +sst.enableAllStatisticsForComponentType("memHierarchy.MemController") diff --git a/sst-unit-test/sdl-02a-gpu-split-hier-port.py b/sst-unit-test/sdl-02a-gpu-split-hier-port.py new file mode 100644 index 000000000..a3b1be743 --- /dev/null +++ b/sst-unit-test/sdl-02a-gpu-split-hier-port.py @@ -0,0 +1,134 @@ +################################################################################ +# Description: +# - Macsim is connected to 2 individual memory controllers for instruction and +# data memory +################################################################################ +import sst +from common import * + +# 0: None, 1: Stdout, 2: Stderr, 3: File +DEBUG_CORE = 1 +DEBUG_CORE_LINKS = 0 +DEBUG_L1 = 0 +DEBUG_MEM = 0 + +DEBUG_LINKS = 0 +DEBUG_BUS = 0 + +DEBUG_LEVEL = 0 +VERBOSE = 0 + +######################################## +# System Parameters +MEM_SIZE_S = '512MiB' +MEM_SIZE = str2bytes(MEM_SIZE_S) +MEM_START = 0 +MEM_END = MEM_START + MEM_SIZE - 1 + + +######################################## +# Macsim +macsim = sst.Component("macsimComponent", "macsimComponent.macsimComponent") +macsim.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list_gpu", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=1 --num_sim_large_cores=0 --num_sim_small_cores=1 --use_memhierarchy=1 --core_type=nvbit", + "frequency" : "2GHz", + "num_cores" : "1", + "num_link": "1", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, + "nvbit_core": True, +}) + + +######################################## +# Instruction Memory Controller +memctrl_i = sst.Component("memory_i", "memHierarchy.MemController") +memctrl_i.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + # "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory_i = memctrl_i.setSubComponent("backend", "memHierarchy.simpleMem") +memory_i.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + + +######################################## +# Data Memory Controller +memctrl_d = sst.Component("memory_d", "memHierarchy.MemController") +memctrl_d.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory_d = memctrl_d.setSubComponent("backend", "memHierarchy.simpleMem") +memory_d.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + +######################################## +# Constant Memory Controller +memctrl_c = sst.Component("memory_c", "memHierarchy.MemController") +memctrl_c.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory_c = memctrl_c.setSubComponent("backend", "memHierarchy.simpleMem") +memory_c.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + +######################################## +# Texture Memory Controller +memctrl_t = sst.Component("memory_t", "memHierarchy.MemController") +memctrl_t.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory_t = memctrl_t.setSubComponent("backend", "memHierarchy.simpleMem") +memory_t.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + + +######################################## +# Links +link_bus_memctrl_i = sst.Link("link_bus_memctrl_i") +link_bus_memctrl_i.connect((macsim, "macsim0_core0_icache", "50ps"), (memctrl_i, "direct_link", "50ps")) +link_bus_memctrl_d = sst.Link("link_bus_memctrl_d") +link_bus_memctrl_d.connect((macsim, "macsim0_core0_dcache", "50ps"), (memctrl_d, "direct_link", "50ps")) +link_bus_memctrl_c = sst.Link("link_bus_memctrl_c") +link_bus_memctrl_c.connect((macsim, "macsim0_core0_ccache", "50ps"), (memctrl_c, "direct_link", "50ps")) +link_bus_memctrl_t = sst.Link("link_bus_memctrl_t") +link_bus_memctrl_t.connect((macsim, "macsim0_core0_tcache", "50ps"), (memctrl_t, "direct_link", "50ps")) + + +######################################## +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") +# sst.setStatisticOutput("sst.statOutputCSV", {"filepath" : "./sst_stats.csv", "separator" : ", " } ) + +sst.enableAllStatisticsForComponentType("memHierarchy.MemController") diff --git a/sst-unit-test/sdl-02b-gpu-split-hier-subcomp.py b/sst-unit-test/sdl-02b-gpu-split-hier-subcomp.py new file mode 100644 index 000000000..2cd444b36 --- /dev/null +++ b/sst-unit-test/sdl-02b-gpu-split-hier-subcomp.py @@ -0,0 +1,161 @@ +################################################################################ +# Description: +# - Macsim is connected to 2 individual memory controllers for instruction and +# data memory. +# - Macsim ports (stdInterface) are loaded as subcomponents explictly. +################################################################################ +import sst +from common import * + +# 0: None, 1: Stdout, 2: Stderr, 3: File +DEBUG_CORE = 1 +DEBUG_CORE_LINKS = 1 +DEBUG_L1 = 0 +DEBUG_L2 = 0 # L2 Caches +DEBUG_MEM = 0 + +DEBUG_LINKS = 0 +DEBUG_BUS = 0 + +DEBUG_LEVEL = 0 +VERBOSE = 0 + +######################################## +# System Parameters +MEM_SIZE_S = '512MiB' +MEM_SIZE = str2bytes(MEM_SIZE_S) +MEM_START = 0 +MEM_END = MEM_START + MEM_SIZE - 1 + + +######################################## +# Macsim +macsim = sst.Component("macsimComponent", "macsimComponent.macsimComponent") +macsim.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list_gpu", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=1 --num_sim_large_cores=0 --num_sim_small_cores=1 --use_memhierarchy=1 --core_type=nvbit", + "frequency" : "2GHz", + "num_cores" : "1", + "num_link": "1", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, + "nvbit_core": True, +}) +macsim_icache_if = macsim.setSubComponent("macsim0_core0_icache", "memHierarchy.standardInterface") +macsim_icache_if.addParams({ + 'debug': DEBUG_CORE_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_dcache_if = macsim.setSubComponent("macsim0_core0_dcache", "memHierarchy.standardInterface") +macsim_dcache_if.addParams({ + 'debug': DEBUG_CORE_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +macsim_ccache_if = macsim.setSubComponent("macsim0_core0_ccache", "memHierarchy.standardInterface") +macsim_ccache_if.addParams({ + 'debug': DEBUG_CORE_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if = macsim.setSubComponent("macsim0_core0_tcache", "memHierarchy.standardInterface") +macsim_tcache_if.addParams({ + 'debug': DEBUG_CORE_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# Instruction Memory Controller +memctrl_i = sst.Component("memory_i", "memHierarchy.MemController") +memctrl_i.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + # "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory_i = memctrl_i.setSubComponent("backend", "memHierarchy.simpleMem") +memory_i.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + + +######################################## +# Data Memory Controller +memctrl_d = sst.Component("memory_d", "memHierarchy.MemController") +memctrl_d.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory_d = memctrl_d.setSubComponent("backend", "memHierarchy.simpleMem") +memory_d.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + + +######################################## +# Constant Memory Controller +memctrl_c = sst.Component("memory_c", "memHierarchy.MemController") +memctrl_c.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory_c = memctrl_c.setSubComponent("backend", "memHierarchy.simpleMem") +memory_c.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + +######################################## +# Texture Memory Controller +memctrl_t = sst.Component("memory_t", "memHierarchy.MemController") +memctrl_t.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory_t = memctrl_t.setSubComponent("backend", "memHierarchy.simpleMem") +memory_t.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + + +######################################## +# Links +link_bus_memctrl_i = sst.Link("link_bus_memctrl_i") +link_bus_memctrl_i.connect((macsim_icache_if, "port", "50ps"), (memctrl_i, "direct_link", "50ps")) +link_bus_memctrl_d = sst.Link("link_bus_memctrl_d") +link_bus_memctrl_d.connect((macsim_dcache_if, "port", "50ps"), (memctrl_d, "direct_link", "50ps")) +link_bus_memctrl_c = sst.Link("link_bus_memctrl_c") +link_bus_memctrl_c.connect((macsim_ccache_if, "port", "50ps"), (memctrl_c, "direct_link", "50ps")) +link_bus_memctrl_t = sst.Link("link_bus_memctrl_t") +link_bus_memctrl_t.connect((macsim_tcache_if, "port", "50ps"), (memctrl_t, "direct_link", "50ps")) + + +######################################## +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") +# sst.setStatisticOutput("sst.statOutputCSV", {"filepath" : "./sst_stats.csv", "separator" : ", " } ) + +sst.enableAllStatisticsForComponentType("memHierarchy.MemController") diff --git a/sst-unit-test/sdl-03a-cpu-L1-mem.py b/sst-unit-test/sdl-03a-cpu-L1-mem.py new file mode 100644 index 000000000..1ec59b1df --- /dev/null +++ b/sst-unit-test/sdl-03a-cpu-L1-mem.py @@ -0,0 +1,142 @@ +################################################################################ +# Description: +# - Macsim is connected to L1 caches, followed by a bus and memory controller. +# - Macsim ports (stdInterface) are loaded as subcomponents explictly. +################################################################################ +import sst +from common import * + +# 0: None, 1: Stdout, 2: Stderr, 3: File +DEBUG_CORE = 1 +DEBUG_L1 = 0 +DEBUG_MEM = 1 + +DEBUG_LINKS = 0 +DEBUG_BUS = 0 + +DEBUG_LEVEL = 5 +VERBOSE = 10 + +######################################## +# System Parameters +MEM_SIZE_S = '512MiB' +MEM_SIZE = str2bytes(MEM_SIZE_S) +MEM_START = 0 +MEM_END = MEM_START + MEM_SIZE - 1 + + +######################################## +# Macsim +macsim = sst.Component("macsimComponent", "macsimComponent.macsimComponent") +macsim.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list_cpu", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=1 --num_sim_large_cores=1 --num_sim_small_cores=0 --use_memhierarchy=1 --core_type=x86", + "frequency" : "2GHz", + "num_cores" : "1", + "num_link": "1", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, +}) +macsim_icache_if = macsim.setSubComponent("macsim0_core0_icache", "memHierarchy.standardInterface") +macsim_icache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if = macsim.setSubComponent("macsim0_core0_dcache", "memHierarchy.standardInterface") +macsim_dcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) + + +######################################## +# L1 Caches +macsim0_core0_icache = sst.Component("macsim0_core0_icache", "memHierarchy.Cache") +macsim0_core0_icache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim0_core0_dcache = sst.Component("macsim0_core0_dcache", "memHierarchy.Cache") +macsim0_core0_dcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + + +######################################## +# Bus between L1 caches and memory controller +mem_bus = sst.Component("mem_bus", "memHierarchy.Bus") +mem_bus.addParams({ + "debug" : DEBUG_LINKS, + "debug_level" : DEBUG_LEVEL, + "bus_frequency" : "4 Ghz" +}) + + +######################################## +# Memory Controller +memctrl = sst.Component("memctrl", "memHierarchy.MemController") +memctrl.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + # "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") +memory.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + +######################################## +# Links + +# Macsim::core0_icache -> L1 ICache +link_macsim_icache = sst.Link("link_macsim_icache") +link_macsim_icache.connect( (macsim_icache_if, "port", "1000ps"), (macsim0_core0_icache, "high_network_0", "1000ps") ) + +# Macsim::core0_dcache -> L1 DCache +link_macsim_dcache = sst.Link("link_macsim_dcache") +link_macsim_dcache.connect( (macsim_dcache_if, "port", "1000ps"), (macsim0_core0_dcache, "high_network_0", "1000ps") ) + +# L1 I/DCache -> Bus +link_icache_bus = sst.Link("link_icache_bus") +link_icache_bus.connect( (macsim0_core0_icache, "low_network_0", "50ps"), (mem_bus, "high_network_0", "50ps") ) +link_dcache_bus = sst.Link("link_dcache_bus") +link_dcache_bus.connect( (macsim0_core0_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_1", "50ps") ) + +# Bus -> Memory +link_bus_mem = sst.Link("link_bus_mem") +link_bus_mem.connect( (mem_bus, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) + + +######################################## +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") \ No newline at end of file diff --git a/sst-unit-test/sdl-03b-gpu-L1-mem.py b/sst-unit-test/sdl-03b-gpu-L1-mem.py new file mode 100644 index 000000000..703ad4140 --- /dev/null +++ b/sst-unit-test/sdl-03b-gpu-L1-mem.py @@ -0,0 +1,198 @@ +################################################################################ +# Description: +# - Macsim is connected to L1 caches, followed by a bus and memory controller. +# - Macsim ports (stdInterface) are loaded as subcomponents explictly. +################################################################################ +import sst +from common import * + +# 0: None, 1: Stdout, 2: Stderr, 3: File +DEBUG_CORE = 1 +DEBUG_L1 = 0 +DEBUG_MEM = 1 + +DEBUG_LINKS = 0 +DEBUG_BUS = 0 + +DEBUG_LEVEL = 1 +VERBOSE = 1 + +######################################## +# System Parameters +MEM_SIZE_S = '512MiB' +MEM_SIZE = str2bytes(MEM_SIZE_S) +MEM_START = 0 +MEM_END = MEM_START + MEM_SIZE - 1 + + +######################################## +# Macsim +macsim = sst.Component("macsimComponent", "macsimComponent.macsimComponent") +macsim.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list_gpu", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=1 --num_sim_large_cores=0 --num_sim_small_cores=1 --use_memhierarchy=1 --core_type=nvbit", + "frequency" : "2GHz", + "num_cores" : "1", + "num_link": "1", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, + "nvbit_core": True, +}) +macsim_icache_if = macsim.setSubComponent("macsim0_core0_icache", "memHierarchy.standardInterface") +macsim_icache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if = macsim.setSubComponent("macsim0_core0_dcache", "memHierarchy.standardInterface") +macsim_dcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if = macsim.setSubComponent("macsim0_core0_ccache", "memHierarchy.standardInterface") +macsim_ccache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if = macsim.setSubComponent("macsim0_core0_tcache", "memHierarchy.standardInterface") +macsim_tcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + + +######################################## +# L1 Caches +macsim0_core0_icache = sst.Component("macsim0_core0_icache", "memHierarchy.Cache") +macsim0_core0_icache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim0_core0_dcache = sst.Component("macsim0_core0_dcache", "memHierarchy.Cache") +macsim0_core0_dcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) +# ######################################## +# # Const Caches +macsim0_core0_ccache = sst.Component("macsim0_core0_ccache", "memHierarchy.Cache") +macsim0_core0_ccache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim0_core0_tcache = sst.Component("macsim0_core0_tcache", "memHierarchy.Cache") +macsim0_core0_tcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", #set this to be 128 to align with int block_size = KNOB(KNOB_L1_SMALL_LINE_SIZE)->getValue(); + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + + +######################################## +# Bus between L1 caches and memory controller +mem_bus = sst.Component("mem_bus", "memHierarchy.Bus") +mem_bus.addParams({ + "debug" : DEBUG_LINKS, + "debug_level" : DEBUG_LEVEL, + "bus_frequency" : "4 Ghz" +}) + + +######################################## +# Memory Controller +memctrl = sst.Component("memctrl", "memHierarchy.MemController") +memctrl.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + # "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") +memory.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + +######################################## +# Links + +# Macsim::macsim0_core0_icache -> L1 ICache +link_macsim_icache = sst.Link("link_macsim_icache") +link_macsim_icache.connect( (macsim_icache_if, "port", "1000ps"), (macsim0_core0_icache, "high_network_0", "1000ps") ) + +# Macsim::macsim0_core0_dcache -> L1 DCache +link_macsim_dcache = sst.Link("link_macsim_dcache") +link_macsim_dcache.connect( (macsim_dcache_if, "port", "1000ps"), (macsim0_core0_dcache, "high_network_0", "1000ps") ) + +# # Macsim::macsim0_core0_ccache -> L1 CCache +link_macsim_ccache = sst.Link("link_macsim_ccache") +link_macsim_ccache.connect( (macsim_ccache_if, "port", "1000ps"), (macsim0_core0_ccache, "high_network_0", "1000ps") ) + +# # Macsim::macsim0_core0_tcache -> L1 TCache +link_macsim_tcache = sst.Link("link_macsim_tcache") +link_macsim_tcache.connect( (macsim_tcache_if, "port", "1000ps"), (macsim0_core0_tcache, "high_network_0", "1000ps") ) + +# L1 I/DCache -> Bus +link_icache_bus = sst.Link("link_icache_bus") +link_icache_bus.connect( (macsim0_core0_icache, "low_network_0", "50ps"), (mem_bus, "high_network_0", "50ps") ) +link_dcache_bus = sst.Link("link_dcache_bus") +link_dcache_bus.connect( (macsim0_core0_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_1", "50ps") ) +link_ccache_bus = sst.Link("link_ccache_bus") +link_ccache_bus.connect( (macsim0_core0_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_2", "50ps") ) +link_tcache_bus = sst.Link("link_tcache_bus") +link_tcache_bus.connect( (macsim0_core0_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_3", "50ps") ) + +# Bus -> Memory +link_bus_mem = sst.Link("link_bus_mem") +link_bus_mem.connect( (mem_bus, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) + + +######################################## +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") \ No newline at end of file diff --git a/sst-unit-test/sdl-03c-gpu-L1-mem-L2.py b/sst-unit-test/sdl-03c-gpu-L1-mem-L2.py new file mode 100644 index 000000000..199890e0f --- /dev/null +++ b/sst-unit-test/sdl-03c-gpu-L1-mem-L2.py @@ -0,0 +1,215 @@ +################################################################################ +# Description: +# - Macsim is connected to L1 caches, followed by a bus and memory controller. +# - Macsim ports (stdInterface) are loaded as subcomponents explictly. +################################################################################ +import sst +from common import * + +# 0: None, 1: Stdout, 2: Stderr, 3: File +DEBUG_CORE = 1 +DEBUG_L1 = 0 +DEBUG_MEM = 1 + +DEBUG_LINKS = 0 +DEBUG_BUS = 0 + +DEBUG_LEVEL = 0 +VERBOSE = 0 + +######################################## +# System Parameters +MEM_SIZE_S = '512MiB' +MEM_SIZE = str2bytes(MEM_SIZE_S) +MEM_START = 0 +MEM_END = MEM_START + MEM_SIZE - 1 + + +######################################## +# Macsim +macsim = sst.Component("macsimComponent", "macsimComponent.macsimComponent") +macsim.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list_gpu", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=1 --num_sim_large_cores=0 --num_sim_small_cores=1 --use_memhierarchy=1 --core_type=nvbit", + "frequency" : "2GHz", + "num_cores" : "1", + "num_link": "1", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, + "nvbit_core": True, +}) +macsim_icache_if = macsim.setSubComponent("macsim0_core0_icache", "memHierarchy.standardInterface") +macsim_icache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if = macsim.setSubComponent("macsim0_core0_dcache", "memHierarchy.standardInterface") +macsim_dcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if = macsim.setSubComponent("macsim0_core0_ccache", "memHierarchy.standardInterface") +macsim_ccache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if = macsim.setSubComponent("macsim0_core0_tcache", "memHierarchy.standardInterface") +macsim_tcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + + +######################################## +# L1 Caches +macsim0_core0_icache = sst.Component("macsim0_core0_icache", "memHierarchy.Cache") +macsim0_core0_icache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim0_core0_dcache = sst.Component("macsim0_core0_dcache", "memHierarchy.Cache") +macsim0_core0_dcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) +# ######################################## +# # Const Caches +macsim0_core0_ccache = sst.Component("macsim0_core0_ccache", "memHierarchy.Cache") +macsim0_core0_ccache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim0_core0_tcache = sst.Component("macsim0_core0_tcache", "memHierarchy.Cache") +macsim0_core0_tcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", #set this to be 128 to align with int block_size = KNOB(KNOB_L1_SMALL_LINE_SIZE)->getValue(); + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +gpu_l2cache = sst.Component("l2cache", "memHierarchy.Cache") +gpu_l2cache.addParams({ + "access_latency_cycles" : "8", + "cache_frequency" : "4Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "8", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "0", + "cache_size" : "64KiB" +}) + + +######################################## +# Bus between L1 caches and memory controller +mem_bus = sst.Component("mem_bus", "memHierarchy.Bus") +mem_bus.addParams({ + "debug" : DEBUG_LINKS, + "debug_level" : DEBUG_LEVEL, + "bus_frequency" : "4 Ghz" +}) + + +######################################## +# Memory Controller +memctrl = sst.Component("memctrl", "memHierarchy.MemController") +memctrl.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + # "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") +memory.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + +######################################## +# Links + +# Macsim::macsim0_core0_icache -> L1 ICache +link_macsim_icache = sst.Link("link_macsim_icache") +link_macsim_icache.connect( (macsim_icache_if, "port", "1000ps"), (macsim0_core0_icache, "high_network_0", "1000ps") ) + +# Macsim::macsim0_core0_dcache -> L1 DCache +link_macsim_dcache = sst.Link("link_macsim_dcache") +link_macsim_dcache.connect( (macsim_dcache_if, "port", "1000ps"), (macsim0_core0_dcache, "high_network_0", "1000ps") ) + +# # Macsim::macsim0_core0_ccache -> L1 CCache +link_macsim_ccache = sst.Link("link_macsim_ccache") +link_macsim_ccache.connect( (macsim_ccache_if, "port", "1000ps"), (macsim0_core0_ccache, "high_network_0", "1000ps") ) + +# # Macsim::macsim0_core0_tcache -> L1 TCache +link_macsim_tcache = sst.Link("link_macsim_tcache") +link_macsim_tcache.connect( (macsim_tcache_if, "port", "1000ps"), (macsim0_core0_tcache, "high_network_0", "1000ps") ) + +# L1 I/DCache -> Bus +link_icache_bus = sst.Link("link_icache_bus") +link_icache_bus.connect( (macsim0_core0_icache, "low_network_0", "50ps"), (mem_bus, "high_network_0", "50ps") ) +link_dcache_bus = sst.Link("link_dcache_bus") +link_dcache_bus.connect( (macsim0_core0_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_1", "50ps") ) +link_ccache_bus = sst.Link("link_ccache_bus") +link_ccache_bus.connect( (macsim0_core0_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_2", "50ps") ) +link_tcache_bus = sst.Link("link_tcache_bus") +link_tcache_bus.connect( (macsim0_core0_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_3", "50ps") ) + +# Bus -> Memory +link_bus_L2 = sst.Link("link_bus_L2") +link_bus_L2.connect( (mem_bus, "low_network_0", "50ps"), (gpu_l2cache, "high_network_0", "50ps") ) +link_bus_mem = sst.Link("link_bus_mem") +link_bus_mem.connect( (gpu_l2cache, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) + + +######################################## +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") \ No newline at end of file diff --git a/sst-unit-test/sdl-04a-gpu-2-core-L1-mem.py b/sst-unit-test/sdl-04a-gpu-2-core-L1-mem.py new file mode 100644 index 000000000..c8104ef3e --- /dev/null +++ b/sst-unit-test/sdl-04a-gpu-2-core-L1-mem.py @@ -0,0 +1,312 @@ +################################################################################ +# Description: +# - Macsim is connected to L1 caches, followed by a bus and memory controller. +# - Macsim ports (stdInterface) are loaded as subcomponents explictly. +################################################################################ +import sst +from common import * + +# 0: None, 1: Stdout, 2: Stderr, 3: File +DEBUG_CORE = 1 +DEBUG_L1 = 1 +DEBUG_MEM = 1 + +DEBUG_LINKS = 0 +DEBUG_BUS = 0 + +DEBUG_LEVEL = 0 +VERBOSE = 0 + +######################################## +# System Parameters +MEM_SIZE_S = '512MiB' +MEM_SIZE = str2bytes(MEM_SIZE_S) +MEM_START = 0 +MEM_END = MEM_START + MEM_SIZE - 1 + + +######################################## +# Macsim +macsim = sst.Component("macsimComponent", "macsimComponent.macsimComponent") +macsim.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list_gpu", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=2 --num_sim_large_cores=0 --num_sim_small_cores=2 --use_memhierarchy=1 --core_type=nvbit", + "frequency" : "2GHz", + "num_link": "2", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, + "nvbit_core": True, +}) + +# Core 0 interface +macsim_icache_if = macsim.setSubComponent("macsim0_core0_icache", "memHierarchy.standardInterface") +macsim_icache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if = macsim.setSubComponent("macsim0_core0_dcache", "memHierarchy.standardInterface") +macsim_dcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if = macsim.setSubComponent("macsim0_core0_ccache", "memHierarchy.standardInterface") +macsim_ccache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if = macsim.setSubComponent("macsim0_core0_tcache", "memHierarchy.standardInterface") +macsim_tcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +# Core 1 Interfaces +macsim_icache_if_1 = macsim.setSubComponent("macsim0_core1_icache", "memHierarchy.standardInterface") +macsim_icache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_1 = macsim.setSubComponent("macsim0_core1_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_1 = macsim.setSubComponent("macsim0_core1_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_1 = macsim.setSubComponent("macsim0_core1_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + + +######################################## +# L1 Caches +macsim0_core0_icache = sst.Component("macsim0_core0_icache", "memHierarchy.Cache") +macsim0_core0_icache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim0_core0_dcache = sst.Component("macsim0_core0_dcache", "memHierarchy.Cache") +macsim0_core0_dcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) +# ######################################## +# # Const Caches +macsim0_core0_ccache = sst.Component("macsim0_core0_ccache", "memHierarchy.Cache") +macsim0_core0_ccache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim0_core0_tcache = sst.Component("macsim0_core0_tcache", "memHierarchy.Cache") +macsim0_core0_tcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", #set this to be 128 to align with int block_size = KNOB(KNOB_L1_SMALL_LINE_SIZE)->getValue(); + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + + +# Core 1 L1 Caches +macsim0_core1_icache = sst.Component("macsim0_core1_icache", "memHierarchy.Cache") +macsim0_core1_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core1_dcache = sst.Component("macsim0_core1_dcache", "memHierarchy.Cache") +macsim0_core1_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core1_ccache = sst.Component("macsim0_core1_ccache", "memHierarchy.Cache") +macsim0_core1_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core1_tcache = sst.Component("macsim0_core1_tcache", "memHierarchy.Cache") +macsim0_core1_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Bus between L1 caches and memory controller +mem_bus = sst.Component("mem_bus", "memHierarchy.Bus") +mem_bus.addParams({ + "debug" : DEBUG_LINKS, + "debug_level" : DEBUG_LEVEL, + "bus_frequency" : "4 Ghz" +}) + + +######################################## +# Memory Controller +memctrl = sst.Component("memctrl", "memHierarchy.MemController") +memctrl.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + # "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") +memory.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + +######################################## +# Links + +# Macsim::macsim0_core0_icache -> L1 ICache +link_macsim_icache = sst.Link("link_macsim_icache") +link_macsim_icache.connect( (macsim_icache_if, "port", "1000ps"), (macsim0_core0_icache, "high_network_0", "1000ps") ) + +# Macsim::macsim0_core0_dcache -> L1 DCache +link_macsim_dcache = sst.Link("link_macsim_dcache") +link_macsim_dcache.connect( (macsim_dcache_if, "port", "1000ps"), (macsim0_core0_dcache, "high_network_0", "1000ps") ) + +# # Macsim::macsim0_core0_ccache -> L1 CCache +link_macsim_ccache = sst.Link("link_macsim_ccache") +link_macsim_ccache.connect( (macsim_ccache_if, "port", "1000ps"), (macsim0_core0_ccache, "high_network_0", "1000ps") ) + +# # Macsim::macsim0_core0_tcache -> L1 TCache +link_macsim_tcache = sst.Link("link_macsim_tcache") +link_macsim_tcache.connect( (macsim_tcache_if, "port", "1000ps"), (macsim0_core0_tcache, "high_network_0", "1000ps") ) + +# Core 1 Links +link_macsim_icache_1 = sst.Link("link_macsim_icache_1") +link_macsim_icache_1.connect((macsim_icache_if_1, "port", "1000ps"), (macsim0_core1_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_1 = sst.Link("link_macsim_dcache_1") +link_macsim_dcache_1.connect((macsim_dcache_if_1, "port", "1000ps"), (macsim0_core1_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_1 = sst.Link("link_macsim_ccache_1") +link_macsim_ccache_1.connect((macsim_ccache_if_1, "port", "1000ps"), (macsim0_core1_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_1 = sst.Link("link_macsim_tcache_1") +link_macsim_tcache_1.connect((macsim_tcache_if_1, "port", "1000ps"), (macsim0_core1_tcache, "high_network_0", "1000ps")) + +# L1 I/DCache -> Bus +link_icache_bus = sst.Link("link_icache_bus") +link_icache_bus.connect( (macsim0_core0_icache, "low_network_0", "50ps"), (mem_bus, "high_network_0", "50ps") ) +link_dcache_bus = sst.Link("link_dcache_bus") +link_dcache_bus.connect( (macsim0_core0_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_1", "50ps") ) +link_ccache_bus = sst.Link("link_ccache_bus") +link_ccache_bus.connect( (macsim0_core0_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_2", "50ps") ) +link_tcache_bus = sst.Link("link_tcache_bus") +link_tcache_bus.connect( (macsim0_core0_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_3", "50ps") ) + +link_icache_bus_1 = sst.Link("link_icache_bus_1") +link_icache_bus_1.connect((macsim0_core1_icache, "low_network_0", "50ps"), (mem_bus, "high_network_4", "50ps")) + +link_dcache_bus_1 = sst.Link("link_dcache_bus_1") +link_dcache_bus_1.connect((macsim0_core1_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_5", "50ps")) + +link_ccache_bus_1 = sst.Link("link_ccache_bus_1") +link_ccache_bus_1.connect((macsim0_core1_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_6", "50ps")) + +link_tcache_bus_1 = sst.Link("link_tcache_bus_1") +link_tcache_bus_1.connect((macsim0_core1_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_7", "50ps")) + +# Bus -> Memory +link_bus_mem = sst.Link("link_bus_mem") +link_bus_mem.connect( (mem_bus, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) + + +######################################## +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") \ No newline at end of file diff --git a/sst-unit-test/sdl-04b-gpu-16-core-L1-mem.py b/sst-unit-test/sdl-04b-gpu-16-core-L1-mem.py new file mode 100644 index 000000000..ffbe616a6 --- /dev/null +++ b/sst-unit-test/sdl-04b-gpu-16-core-L1-mem.py @@ -0,0 +1,1999 @@ +################################################################################ +# Description: +# - Macsim is connected to L1 caches, followed by a bus and memory controller. +# - Macsim ports (stdInterface) are loaded as subcomponents explictly. +################################################################################ +import sst +from common import * + +# 0: None, 1: Stdout, 2: Stderr, 3: File +DEBUG_CORE = 1 +DEBUG_L1 = 1 +DEBUG_MEM = 1 + +DEBUG_LINKS = 0 +DEBUG_BUS = 0 + +DEBUG_LEVEL = 0 +VERBOSE = 0 + +######################################## +# System Parameters +MEM_SIZE_S = '512MiB' +MEM_SIZE = str2bytes(MEM_SIZE_S) +MEM_START = 0 +MEM_END = MEM_START + MEM_SIZE - 1 + + +######################################## +# Macsim +macsim = sst.Component("macsimComponent", "macsimComponent.macsimComponent") +macsim.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list_gpu", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=16 --num_sim_large_cores=0 --num_sim_small_cores=16 --use_memhierarchy=1 --core_type=nvbit", + "frequency" : "2GHz", + "num_link": "16", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, + "nvbit_core": True, +}) + +######################################## +# Core 0 + +# Interfaces +macsim_icache_if_0 = macsim.setSubComponent("macsim0_core0_icache", "memHierarchy.standardInterface") +macsim_icache_if_0.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_0 = macsim.setSubComponent("macsim0_core0_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_0.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_0 = macsim.setSubComponent("macsim0_core0_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_0.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_0 = macsim.setSubComponent("macsim0_core0_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_0.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core0_icache = sst.Component("macsim0_core0_icache", "memHierarchy.Cache") +macsim0_core0_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core0_dcache = sst.Component("macsim0_core0_dcache", "memHierarchy.Cache") +macsim0_core0_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core0_ccache = sst.Component("macsim0_core0_ccache", "memHierarchy.Cache") +macsim0_core0_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core0_tcache = sst.Component("macsim0_core0_tcache", "memHierarchy.Cache") +macsim0_core0_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 1 + +# Interfaces +macsim_icache_if_1 = macsim.setSubComponent("macsim0_core1_icache", "memHierarchy.standardInterface") +macsim_icache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_1 = macsim.setSubComponent("macsim0_core1_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_1 = macsim.setSubComponent("macsim0_core1_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_1 = macsim.setSubComponent("macsim0_core1_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core1_icache = sst.Component("macsim0_core1_icache", "memHierarchy.Cache") +macsim0_core1_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core1_dcache = sst.Component("macsim0_core1_dcache", "memHierarchy.Cache") +macsim0_core1_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core1_ccache = sst.Component("macsim0_core1_ccache", "memHierarchy.Cache") +macsim0_core1_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core1_tcache = sst.Component("macsim0_core1_tcache", "memHierarchy.Cache") +macsim0_core1_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 2 + +# Interfaces +macsim_icache_if_2 = macsim.setSubComponent("macsim0_core2_icache", "memHierarchy.standardInterface") +macsim_icache_if_2.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_2 = macsim.setSubComponent("macsim0_core2_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_2.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_2 = macsim.setSubComponent("macsim0_core2_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_2.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_2 = macsim.setSubComponent("macsim0_core2_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_2.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core2_icache = sst.Component("macsim0_core2_icache", "memHierarchy.Cache") +macsim0_core2_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core2_dcache = sst.Component("macsim0_core2_dcache", "memHierarchy.Cache") +macsim0_core2_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core2_ccache = sst.Component("macsim0_core2_ccache", "memHierarchy.Cache") +macsim0_core2_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core2_tcache = sst.Component("macsim0_core2_tcache", "memHierarchy.Cache") +macsim0_core2_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 3 + +# Interfaces +macsim_icache_if_3 = macsim.setSubComponent("macsim0_core3_icache", "memHierarchy.standardInterface") +macsim_icache_if_3.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_3 = macsim.setSubComponent("macsim0_core3_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_3.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_3 = macsim.setSubComponent("macsim0_core3_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_3.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_3 = macsim.setSubComponent("macsim0_core3_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_3.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core3_icache = sst.Component("macsim0_core3_icache", "memHierarchy.Cache") +macsim0_core3_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core3_dcache = sst.Component("macsim0_core3_dcache", "memHierarchy.Cache") +macsim0_core3_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core3_ccache = sst.Component("macsim0_core3_ccache", "memHierarchy.Cache") +macsim0_core3_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core3_tcache = sst.Component("macsim0_core3_tcache", "memHierarchy.Cache") +macsim0_core3_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 4 + +# Interfaces +macsim_icache_if_4 = macsim.setSubComponent("macsim0_core4_icache", "memHierarchy.standardInterface") +macsim_icache_if_4.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_4 = macsim.setSubComponent("macsim0_core4_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_4.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_4 = macsim.setSubComponent("macsim0_core4_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_4.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_4 = macsim.setSubComponent("macsim0_core4_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_4.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core4_icache = sst.Component("macsim0_core4_icache", "memHierarchy.Cache") +macsim0_core4_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core4_dcache = sst.Component("macsim0_core4_dcache", "memHierarchy.Cache") +macsim0_core4_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core4_ccache = sst.Component("macsim0_core4_ccache", "memHierarchy.Cache") +macsim0_core4_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core4_tcache = sst.Component("macsim0_core4_tcache", "memHierarchy.Cache") +macsim0_core4_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 5 + +# Interfaces +macsim_icache_if_5 = macsim.setSubComponent("macsim0_core5_icache", "memHierarchy.standardInterface") +macsim_icache_if_5.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_5 = macsim.setSubComponent("macsim0_core5_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_5.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_5 = macsim.setSubComponent("macsim0_core5_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_5.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_5 = macsim.setSubComponent("macsim0_core5_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_5.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core5_icache = sst.Component("macsim0_core5_icache", "memHierarchy.Cache") +macsim0_core5_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core5_dcache = sst.Component("macsim0_core5_dcache", "memHierarchy.Cache") +macsim0_core5_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core5_ccache = sst.Component("macsim0_core5_ccache", "memHierarchy.Cache") +macsim0_core5_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core5_tcache = sst.Component("macsim0_core5_tcache", "memHierarchy.Cache") +macsim0_core5_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 6 + +# Interfaces +macsim_icache_if_6 = macsim.setSubComponent("macsim0_core6_icache", "memHierarchy.standardInterface") +macsim_icache_if_6.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_6 = macsim.setSubComponent("macsim0_core6_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_6.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_6 = macsim.setSubComponent("macsim0_core6_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_6.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_6 = macsim.setSubComponent("macsim0_core6_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_6.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core6_icache = sst.Component("macsim0_core6_icache", "memHierarchy.Cache") +macsim0_core6_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core6_dcache = sst.Component("macsim0_core6_dcache", "memHierarchy.Cache") +macsim0_core6_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core6_ccache = sst.Component("macsim0_core6_ccache", "memHierarchy.Cache") +macsim0_core6_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core6_tcache = sst.Component("macsim0_core6_tcache", "memHierarchy.Cache") +macsim0_core6_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 7 + +# Interfaces +macsim_icache_if_7 = macsim.setSubComponent("macsim0_core7_icache", "memHierarchy.standardInterface") +macsim_icache_if_7.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_7 = macsim.setSubComponent("macsim0_core7_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_7.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_7 = macsim.setSubComponent("macsim0_core7_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_7.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_7 = macsim.setSubComponent("macsim0_core7_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_7.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core7_icache = sst.Component("macsim0_core7_icache", "memHierarchy.Cache") +macsim0_core7_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core7_dcache = sst.Component("macsim0_core7_dcache", "memHierarchy.Cache") +macsim0_core7_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core7_ccache = sst.Component("macsim0_core7_ccache", "memHierarchy.Cache") +macsim0_core7_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core7_tcache = sst.Component("macsim0_core7_tcache", "memHierarchy.Cache") +macsim0_core7_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 8 + +# Interfaces +macsim_icache_if_8 = macsim.setSubComponent("macsim0_core8_icache", "memHierarchy.standardInterface") +macsim_icache_if_8.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_8 = macsim.setSubComponent("macsim0_core8_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_8.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_8 = macsim.setSubComponent("macsim0_core8_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_8.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_8 = macsim.setSubComponent("macsim0_core8_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_8.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core8_icache = sst.Component("macsim0_core8_icache", "memHierarchy.Cache") +macsim0_core8_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core8_dcache = sst.Component("macsim0_core8_dcache", "memHierarchy.Cache") +macsim0_core8_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core8_ccache = sst.Component("macsim0_core8_ccache", "memHierarchy.Cache") +macsim0_core8_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core8_tcache = sst.Component("macsim0_core8_tcache", "memHierarchy.Cache") +macsim0_core8_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 9 + +# Interfaces +macsim_icache_if_9 = macsim.setSubComponent("macsim0_core9_icache", "memHierarchy.standardInterface") +macsim_icache_if_9.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_9 = macsim.setSubComponent("macsim0_core9_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_9.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_9 = macsim.setSubComponent("macsim0_core9_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_9.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_9 = macsim.setSubComponent("macsim0_core9_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_9.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core9_icache = sst.Component("macsim0_core9_icache", "memHierarchy.Cache") +macsim0_core9_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core9_dcache = sst.Component("macsim0_core9_dcache", "memHierarchy.Cache") +macsim0_core9_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core9_ccache = sst.Component("macsim0_core9_ccache", "memHierarchy.Cache") +macsim0_core9_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core9_tcache = sst.Component("macsim0_core9_tcache", "memHierarchy.Cache") +macsim0_core9_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 10 + +# Interfaces +macsim_icache_if_10 = macsim.setSubComponent("macsim0_core10_icache", "memHierarchy.standardInterface") +macsim_icache_if_10.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_10 = macsim.setSubComponent("macsim0_core10_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_10.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_10 = macsim.setSubComponent("macsim0_core10_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_10.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_10 = macsim.setSubComponent("macsim0_core10_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_10.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core10_icache = sst.Component("macsim0_core10_icache", "memHierarchy.Cache") +macsim0_core10_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core10_dcache = sst.Component("macsim0_core10_dcache", "memHierarchy.Cache") +macsim0_core10_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core10_ccache = sst.Component("macsim0_core10_ccache", "memHierarchy.Cache") +macsim0_core10_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core10_tcache = sst.Component("macsim0_core10_tcache", "memHierarchy.Cache") +macsim0_core10_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 11 + +# Interfaces +macsim_icache_if_11 = macsim.setSubComponent("macsim0_core11_icache", "memHierarchy.standardInterface") +macsim_icache_if_11.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_11 = macsim.setSubComponent("macsim0_core11_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_11.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_11 = macsim.setSubComponent("macsim0_core11_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_11.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_11 = macsim.setSubComponent("macsim0_core11_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_11.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core11_icache = sst.Component("macsim0_core11_icache", "memHierarchy.Cache") +macsim0_core11_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core11_dcache = sst.Component("macsim0_core11_dcache", "memHierarchy.Cache") +macsim0_core11_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core11_ccache = sst.Component("macsim0_core11_ccache", "memHierarchy.Cache") +macsim0_core11_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core11_tcache = sst.Component("macsim0_core11_tcache", "memHierarchy.Cache") +macsim0_core11_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 12 + +# Interfaces +macsim_icache_if_12 = macsim.setSubComponent("macsim0_core12_icache", "memHierarchy.standardInterface") +macsim_icache_if_12.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_12 = macsim.setSubComponent("macsim0_core12_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_12.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_12 = macsim.setSubComponent("macsim0_core12_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_12.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_12 = macsim.setSubComponent("macsim0_core12_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_12.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core12_icache = sst.Component("macsim0_core12_icache", "memHierarchy.Cache") +macsim0_core12_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core12_dcache = sst.Component("macsim0_core12_dcache", "memHierarchy.Cache") +macsim0_core12_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core12_ccache = sst.Component("macsim0_core12_ccache", "memHierarchy.Cache") +macsim0_core12_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core12_tcache = sst.Component("macsim0_core12_tcache", "memHierarchy.Cache") +macsim0_core12_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 13 + +# Interfaces +macsim_icache_if_13 = macsim.setSubComponent("macsim0_core13_icache", "memHierarchy.standardInterface") +macsim_icache_if_13.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_13 = macsim.setSubComponent("macsim0_core13_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_13.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_13 = macsim.setSubComponent("macsim0_core13_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_13.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_13 = macsim.setSubComponent("macsim0_core13_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_13.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core13_icache = sst.Component("macsim0_core13_icache", "memHierarchy.Cache") +macsim0_core13_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core13_dcache = sst.Component("macsim0_core13_dcache", "memHierarchy.Cache") +macsim0_core13_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core13_ccache = sst.Component("macsim0_core13_ccache", "memHierarchy.Cache") +macsim0_core13_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core13_tcache = sst.Component("macsim0_core13_tcache", "memHierarchy.Cache") +macsim0_core13_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 14 + +# Interfaces +macsim_icache_if_14 = macsim.setSubComponent("macsim0_core14_icache", "memHierarchy.standardInterface") +macsim_icache_if_14.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_14 = macsim.setSubComponent("macsim0_core14_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_14.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_14 = macsim.setSubComponent("macsim0_core14_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_14.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_14 = macsim.setSubComponent("macsim0_core14_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_14.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core14_icache = sst.Component("macsim0_core14_icache", "memHierarchy.Cache") +macsim0_core14_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core14_dcache = sst.Component("macsim0_core14_dcache", "memHierarchy.Cache") +macsim0_core14_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core14_ccache = sst.Component("macsim0_core14_ccache", "memHierarchy.Cache") +macsim0_core14_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core14_tcache = sst.Component("macsim0_core14_tcache", "memHierarchy.Cache") +macsim0_core14_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 15 + +# Interfaces +macsim_icache_if_15 = macsim.setSubComponent("macsim0_core15_icache", "memHierarchy.standardInterface") +macsim_icache_if_15.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_15 = macsim.setSubComponent("macsim0_core15_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_15.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_15 = macsim.setSubComponent("macsim0_core15_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_15.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_15 = macsim.setSubComponent("macsim0_core15_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_15.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core15_icache = sst.Component("macsim0_core15_icache", "memHierarchy.Cache") +macsim0_core15_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core15_dcache = sst.Component("macsim0_core15_dcache", "memHierarchy.Cache") +macsim0_core15_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core15_ccache = sst.Component("macsim0_core15_ccache", "memHierarchy.Cache") +macsim0_core15_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core15_tcache = sst.Component("macsim0_core15_tcache", "memHierarchy.Cache") +macsim0_core15_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Bus between L1 caches and memory controller +mem_bus = sst.Component("mem_bus", "memHierarchy.Bus") +mem_bus.addParams({ + "debug" : DEBUG_LINKS, + "debug_level" : DEBUG_LEVEL, + "bus_frequency" : "4 Ghz" +}) + + +######################################## +# Memory Controller +memctrl = sst.Component("memctrl", "memHierarchy.MemController") +memctrl.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + # "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") +memory.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + + +# Links for Core 0 +link_macsim_icache_0 = sst.Link("link_macsim_icache_0") +link_macsim_icache_0.connect((macsim_icache_if_0, "port", "1000ps"), (macsim0_core0_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_0 = sst.Link("link_macsim_dcache_0") +link_macsim_dcache_0.connect((macsim_dcache_if_0, "port", "1000ps"), (macsim0_core0_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_0 = sst.Link("link_macsim_ccache_0") +link_macsim_ccache_0.connect((macsim_ccache_if_0, "port", "1000ps"), (macsim0_core0_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_0 = sst.Link("link_macsim_tcache_0") +link_macsim_tcache_0.connect((macsim_tcache_if_0, "port", "1000ps"), (macsim0_core0_tcache, "high_network_0", "1000ps")) + + +# Links for Core 1 +link_macsim_icache_1 = sst.Link("link_macsim_icache_1") +link_macsim_icache_1.connect((macsim_icache_if_1, "port", "1000ps"), (macsim0_core1_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_1 = sst.Link("link_macsim_dcache_1") +link_macsim_dcache_1.connect((macsim_dcache_if_1, "port", "1000ps"), (macsim0_core1_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_1 = sst.Link("link_macsim_ccache_1") +link_macsim_ccache_1.connect((macsim_ccache_if_1, "port", "1000ps"), (macsim0_core1_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_1 = sst.Link("link_macsim_tcache_1") +link_macsim_tcache_1.connect((macsim_tcache_if_1, "port", "1000ps"), (macsim0_core1_tcache, "high_network_0", "1000ps")) + + +# Links for Core 2 +link_macsim_icache_2 = sst.Link("link_macsim_icache_2") +link_macsim_icache_2.connect((macsim_icache_if_2, "port", "1000ps"), (macsim0_core2_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_2 = sst.Link("link_macsim_dcache_2") +link_macsim_dcache_2.connect((macsim_dcache_if_2, "port", "1000ps"), (macsim0_core2_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_2 = sst.Link("link_macsim_ccache_2") +link_macsim_ccache_2.connect((macsim_ccache_if_2, "port", "1000ps"), (macsim0_core2_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_2 = sst.Link("link_macsim_tcache_2") +link_macsim_tcache_2.connect((macsim_tcache_if_2, "port", "1000ps"), (macsim0_core2_tcache, "high_network_0", "1000ps")) + + +# Links for Core 3 +link_macsim_icache_3 = sst.Link("link_macsim_icache_3") +link_macsim_icache_3.connect((macsim_icache_if_3, "port", "1000ps"), (macsim0_core3_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_3 = sst.Link("link_macsim_dcache_3") +link_macsim_dcache_3.connect((macsim_dcache_if_3, "port", "1000ps"), (macsim0_core3_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_3 = sst.Link("link_macsim_ccache_3") +link_macsim_ccache_3.connect((macsim_ccache_if_3, "port", "1000ps"), (macsim0_core3_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_3 = sst.Link("link_macsim_tcache_3") +link_macsim_tcache_3.connect((macsim_tcache_if_3, "port", "1000ps"), (macsim0_core3_tcache, "high_network_0", "1000ps")) + + +# Links for Core 4 +link_macsim_icache_4 = sst.Link("link_macsim_icache_4") +link_macsim_icache_4.connect((macsim_icache_if_4, "port", "1000ps"), (macsim0_core4_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_4 = sst.Link("link_macsim_dcache_4") +link_macsim_dcache_4.connect((macsim_dcache_if_4, "port", "1000ps"), (macsim0_core4_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_4 = sst.Link("link_macsim_ccache_4") +link_macsim_ccache_4.connect((macsim_ccache_if_4, "port", "1000ps"), (macsim0_core4_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_4 = sst.Link("link_macsim_tcache_4") +link_macsim_tcache_4.connect((macsim_tcache_if_4, "port", "1000ps"), (macsim0_core4_tcache, "high_network_0", "1000ps")) + + +# Links for Core 5 +link_macsim_icache_5 = sst.Link("link_macsim_icache_5") +link_macsim_icache_5.connect((macsim_icache_if_5, "port", "1000ps"), (macsim0_core5_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_5 = sst.Link("link_macsim_dcache_5") +link_macsim_dcache_5.connect((macsim_dcache_if_5, "port", "1000ps"), (macsim0_core5_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_5 = sst.Link("link_macsim_ccache_5") +link_macsim_ccache_5.connect((macsim_ccache_if_5, "port", "1000ps"), (macsim0_core5_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_5 = sst.Link("link_macsim_tcache_5") +link_macsim_tcache_5.connect((macsim_tcache_if_5, "port", "1000ps"), (macsim0_core5_tcache, "high_network_0", "1000ps")) + + +# Links for Core 6 +link_macsim_icache_6 = sst.Link("link_macsim_icache_6") +link_macsim_icache_6.connect((macsim_icache_if_6, "port", "1000ps"), (macsim0_core6_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_6 = sst.Link("link_macsim_dcache_6") +link_macsim_dcache_6.connect((macsim_dcache_if_6, "port", "1000ps"), (macsim0_core6_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_6 = sst.Link("link_macsim_ccache_6") +link_macsim_ccache_6.connect((macsim_ccache_if_6, "port", "1000ps"), (macsim0_core6_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_6 = sst.Link("link_macsim_tcache_6") +link_macsim_tcache_6.connect((macsim_tcache_if_6, "port", "1000ps"), (macsim0_core6_tcache, "high_network_0", "1000ps")) + + +# Links for Core 7 +link_macsim_icache_7 = sst.Link("link_macsim_icache_7") +link_macsim_icache_7.connect((macsim_icache_if_7, "port", "1000ps"), (macsim0_core7_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_7 = sst.Link("link_macsim_dcache_7") +link_macsim_dcache_7.connect((macsim_dcache_if_7, "port", "1000ps"), (macsim0_core7_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_7 = sst.Link("link_macsim_ccache_7") +link_macsim_ccache_7.connect((macsim_ccache_if_7, "port", "1000ps"), (macsim0_core7_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_7 = sst.Link("link_macsim_tcache_7") +link_macsim_tcache_7.connect((macsim_tcache_if_7, "port", "1000ps"), (macsim0_core7_tcache, "high_network_0", "1000ps")) + + +# Links for Core 8 +link_macsim_icache_8 = sst.Link("link_macsim_icache_8") +link_macsim_icache_8.connect((macsim_icache_if_8, "port", "1000ps"), (macsim0_core8_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_8 = sst.Link("link_macsim_dcache_8") +link_macsim_dcache_8.connect((macsim_dcache_if_8, "port", "1000ps"), (macsim0_core8_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_8 = sst.Link("link_macsim_ccache_8") +link_macsim_ccache_8.connect((macsim_ccache_if_8, "port", "1000ps"), (macsim0_core8_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_8 = sst.Link("link_macsim_tcache_8") +link_macsim_tcache_8.connect((macsim_tcache_if_8, "port", "1000ps"), (macsim0_core8_tcache, "high_network_0", "1000ps")) + + +# Links for Core 9 +link_macsim_icache_9 = sst.Link("link_macsim_icache_9") +link_macsim_icache_9.connect((macsim_icache_if_9, "port", "1000ps"), (macsim0_core9_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_9 = sst.Link("link_macsim_dcache_9") +link_macsim_dcache_9.connect((macsim_dcache_if_9, "port", "1000ps"), (macsim0_core9_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_9 = sst.Link("link_macsim_ccache_9") +link_macsim_ccache_9.connect((macsim_ccache_if_9, "port", "1000ps"), (macsim0_core9_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_9 = sst.Link("link_macsim_tcache_9") +link_macsim_tcache_9.connect((macsim_tcache_if_9, "port", "1000ps"), (macsim0_core9_tcache, "high_network_0", "1000ps")) + + +# Links for Core 10 +link_macsim_icache_10 = sst.Link("link_macsim_icache_10") +link_macsim_icache_10.connect((macsim_icache_if_10, "port", "1000ps"), (macsim0_core10_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_10 = sst.Link("link_macsim_dcache_10") +link_macsim_dcache_10.connect((macsim_dcache_if_10, "port", "1000ps"), (macsim0_core10_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_10 = sst.Link("link_macsim_ccache_10") +link_macsim_ccache_10.connect((macsim_ccache_if_10, "port", "1000ps"), (macsim0_core10_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_10 = sst.Link("link_macsim_tcache_10") +link_macsim_tcache_10.connect((macsim_tcache_if_10, "port", "1000ps"), (macsim0_core10_tcache, "high_network_0", "1000ps")) + + +# Links for Core 11 +link_macsim_icache_11 = sst.Link("link_macsim_icache_11") +link_macsim_icache_11.connect((macsim_icache_if_11, "port", "1000ps"), (macsim0_core11_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_11 = sst.Link("link_macsim_dcache_11") +link_macsim_dcache_11.connect((macsim_dcache_if_11, "port", "1000ps"), (macsim0_core11_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_11 = sst.Link("link_macsim_ccache_11") +link_macsim_ccache_11.connect((macsim_ccache_if_11, "port", "1000ps"), (macsim0_core11_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_11 = sst.Link("link_macsim_tcache_11") +link_macsim_tcache_11.connect((macsim_tcache_if_11, "port", "1000ps"), (macsim0_core11_tcache, "high_network_0", "1000ps")) + + +# Links for Core 12 +link_macsim_icache_12 = sst.Link("link_macsim_icache_12") +link_macsim_icache_12.connect((macsim_icache_if_12, "port", "1000ps"), (macsim0_core12_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_12 = sst.Link("link_macsim_dcache_12") +link_macsim_dcache_12.connect((macsim_dcache_if_12, "port", "1000ps"), (macsim0_core12_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_12 = sst.Link("link_macsim_ccache_12") +link_macsim_ccache_12.connect((macsim_ccache_if_12, "port", "1000ps"), (macsim0_core12_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_12 = sst.Link("link_macsim_tcache_12") +link_macsim_tcache_12.connect((macsim_tcache_if_12, "port", "1000ps"), (macsim0_core12_tcache, "high_network_0", "1000ps")) + + +# Links for Core 13 +link_macsim_icache_13 = sst.Link("link_macsim_icache_13") +link_macsim_icache_13.connect((macsim_icache_if_13, "port", "1000ps"), (macsim0_core13_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_13 = sst.Link("link_macsim_dcache_13") +link_macsim_dcache_13.connect((macsim_dcache_if_13, "port", "1000ps"), (macsim0_core13_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_13 = sst.Link("link_macsim_ccache_13") +link_macsim_ccache_13.connect((macsim_ccache_if_13, "port", "1000ps"), (macsim0_core13_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_13 = sst.Link("link_macsim_tcache_13") +link_macsim_tcache_13.connect((macsim_tcache_if_13, "port", "1000ps"), (macsim0_core13_tcache, "high_network_0", "1000ps")) + + +# Links for Core 14 +link_macsim_icache_14 = sst.Link("link_macsim_icache_14") +link_macsim_icache_14.connect((macsim_icache_if_14, "port", "1000ps"), (macsim0_core14_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_14 = sst.Link("link_macsim_dcache_14") +link_macsim_dcache_14.connect((macsim_dcache_if_14, "port", "1000ps"), (macsim0_core14_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_14 = sst.Link("link_macsim_ccache_14") +link_macsim_ccache_14.connect((macsim_ccache_if_14, "port", "1000ps"), (macsim0_core14_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_14 = sst.Link("link_macsim_tcache_14") +link_macsim_tcache_14.connect((macsim_tcache_if_14, "port", "1000ps"), (macsim0_core14_tcache, "high_network_0", "1000ps")) + + +# Links for Core 15 +link_macsim_icache_15 = sst.Link("link_macsim_icache_15") +link_macsim_icache_15.connect((macsim_icache_if_15, "port", "1000ps"), (macsim0_core15_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_15 = sst.Link("link_macsim_dcache_15") +link_macsim_dcache_15.connect((macsim_dcache_if_15, "port", "1000ps"), (macsim0_core15_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_15 = sst.Link("link_macsim_ccache_15") +link_macsim_ccache_15.connect((macsim_ccache_if_15, "port", "1000ps"), (macsim0_core15_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_15 = sst.Link("link_macsim_tcache_15") +link_macsim_tcache_15.connect((macsim_tcache_if_15, "port", "1000ps"), (macsim0_core15_tcache, "high_network_0", "1000ps")) + + +# Links bus for Core 0 +link_icache_bus_0 = sst.Link("link_icache_bus_0") +link_icache_bus_0.connect((macsim0_core0_icache, "low_network_0", "50ps"), (mem_bus, "high_network_0", "50ps")) + +link_dcache_bus_0 = sst.Link("link_dcache_bus_0") +link_dcache_bus_0.connect((macsim0_core0_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_1", "50ps")) + +link_ccache_bus_0 = sst.Link("link_ccache_bus_0") +link_ccache_bus_0.connect((macsim0_core0_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_2", "50ps")) + +link_tcache_bus_0 = sst.Link("link_tcache_bus_0") +link_tcache_bus_0.connect((macsim0_core0_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_3", "50ps")) + + +# Links bus for Core 1 +link_icache_bus_1 = sst.Link("link_icache_bus_1") +link_icache_bus_1.connect((macsim0_core1_icache, "low_network_0", "50ps"), (mem_bus, "high_network_4", "50ps")) + +link_dcache_bus_1 = sst.Link("link_dcache_bus_1") +link_dcache_bus_1.connect((macsim0_core1_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_5", "50ps")) + +link_ccache_bus_1 = sst.Link("link_ccache_bus_1") +link_ccache_bus_1.connect((macsim0_core1_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_6", "50ps")) + +link_tcache_bus_1 = sst.Link("link_tcache_bus_1") +link_tcache_bus_1.connect((macsim0_core1_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_7", "50ps")) + + +# Links bus for Core 2 +link_icache_bus_2 = sst.Link("link_icache_bus_2") +link_icache_bus_2.connect((macsim0_core2_icache, "low_network_0", "50ps"), (mem_bus, "high_network_8", "50ps")) + +link_dcache_bus_2 = sst.Link("link_dcache_bus_2") +link_dcache_bus_2.connect((macsim0_core2_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_9", "50ps")) + +link_ccache_bus_2 = sst.Link("link_ccache_bus_2") +link_ccache_bus_2.connect((macsim0_core2_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_10", "50ps")) + +link_tcache_bus_2 = sst.Link("link_tcache_bus_2") +link_tcache_bus_2.connect((macsim0_core2_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_11", "50ps")) + + +# Links bus for Core 3 +link_icache_bus_3 = sst.Link("link_icache_bus_3") +link_icache_bus_3.connect((macsim0_core3_icache, "low_network_0", "50ps"), (mem_bus, "high_network_12", "50ps")) + +link_dcache_bus_3 = sst.Link("link_dcache_bus_3") +link_dcache_bus_3.connect((macsim0_core3_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_13", "50ps")) + +link_ccache_bus_3 = sst.Link("link_ccache_bus_3") +link_ccache_bus_3.connect((macsim0_core3_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_14", "50ps")) + +link_tcache_bus_3 = sst.Link("link_tcache_bus_3") +link_tcache_bus_3.connect((macsim0_core3_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_15", "50ps")) + + +# Links bus for Core 4 +link_icache_bus_4 = sst.Link("link_icache_bus_4") +link_icache_bus_4.connect((macsim0_core4_icache, "low_network_0", "50ps"), (mem_bus, "high_network_16", "50ps")) + +link_dcache_bus_4 = sst.Link("link_dcache_bus_4") +link_dcache_bus_4.connect((macsim0_core4_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_17", "50ps")) + +link_ccache_bus_4 = sst.Link("link_ccache_bus_4") +link_ccache_bus_4.connect((macsim0_core4_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_18", "50ps")) + +link_tcache_bus_4 = sst.Link("link_tcache_bus_4") +link_tcache_bus_4.connect((macsim0_core4_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_19", "50ps")) + + +# Links bus for Core 5 +link_icache_bus_5 = sst.Link("link_icache_bus_5") +link_icache_bus_5.connect((macsim0_core5_icache, "low_network_0", "50ps"), (mem_bus, "high_network_20", "50ps")) + +link_dcache_bus_5 = sst.Link("link_dcache_bus_5") +link_dcache_bus_5.connect((macsim0_core5_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_21", "50ps")) + +link_ccache_bus_5 = sst.Link("link_ccache_bus_5") +link_ccache_bus_5.connect((macsim0_core5_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_22", "50ps")) + +link_tcache_bus_5 = sst.Link("link_tcache_bus_5") +link_tcache_bus_5.connect((macsim0_core5_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_23", "50ps")) + + +# Links bus for Core 6 +link_icache_bus_6 = sst.Link("link_icache_bus_6") +link_icache_bus_6.connect((macsim0_core6_icache, "low_network_0", "50ps"), (mem_bus, "high_network_24", "50ps")) + +link_dcache_bus_6 = sst.Link("link_dcache_bus_6") +link_dcache_bus_6.connect((macsim0_core6_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_25", "50ps")) + +link_ccache_bus_6 = sst.Link("link_ccache_bus_6") +link_ccache_bus_6.connect((macsim0_core6_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_26", "50ps")) + +link_tcache_bus_6 = sst.Link("link_tcache_bus_6") +link_tcache_bus_6.connect((macsim0_core6_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_27", "50ps")) + + +# Links bus for Core 7 +link_icache_bus_7 = sst.Link("link_icache_bus_7") +link_icache_bus_7.connect((macsim0_core7_icache, "low_network_0", "50ps"), (mem_bus, "high_network_28", "50ps")) + +link_dcache_bus_7 = sst.Link("link_dcache_bus_7") +link_dcache_bus_7.connect((macsim0_core7_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_29", "50ps")) + +link_ccache_bus_7 = sst.Link("link_ccache_bus_7") +link_ccache_bus_7.connect((macsim0_core7_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_30", "50ps")) + +link_tcache_bus_7 = sst.Link("link_tcache_bus_7") +link_tcache_bus_7.connect((macsim0_core7_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_31", "50ps")) + + +# Links bus for Core 8 +link_icache_bus_8 = sst.Link("link_icache_bus_8") +link_icache_bus_8.connect((macsim0_core8_icache, "low_network_0", "50ps"), (mem_bus, "high_network_32", "50ps")) + +link_dcache_bus_8 = sst.Link("link_dcache_bus_8") +link_dcache_bus_8.connect((macsim0_core8_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_33", "50ps")) + +link_ccache_bus_8 = sst.Link("link_ccache_bus_8") +link_ccache_bus_8.connect((macsim0_core8_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_34", "50ps")) + +link_tcache_bus_8 = sst.Link("link_tcache_bus_8") +link_tcache_bus_8.connect((macsim0_core8_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_35", "50ps")) + + +# Links bus for Core 9 +link_icache_bus_9 = sst.Link("link_icache_bus_9") +link_icache_bus_9.connect((macsim0_core9_icache, "low_network_0", "50ps"), (mem_bus, "high_network_36", "50ps")) + +link_dcache_bus_9 = sst.Link("link_dcache_bus_9") +link_dcache_bus_9.connect((macsim0_core9_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_37", "50ps")) + +link_ccache_bus_9 = sst.Link("link_ccache_bus_9") +link_ccache_bus_9.connect((macsim0_core9_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_38", "50ps")) + +link_tcache_bus_9 = sst.Link("link_tcache_bus_9") +link_tcache_bus_9.connect((macsim0_core9_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_39", "50ps")) + + +# Links bus for Core 10 +link_icache_bus_10 = sst.Link("link_icache_bus_10") +link_icache_bus_10.connect((macsim0_core10_icache, "low_network_0", "50ps"), (mem_bus, "high_network_40", "50ps")) + +link_dcache_bus_10 = sst.Link("link_dcache_bus_10") +link_dcache_bus_10.connect((macsim0_core10_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_41", "50ps")) + +link_ccache_bus_10 = sst.Link("link_ccache_bus_10") +link_ccache_bus_10.connect((macsim0_core10_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_42", "50ps")) + +link_tcache_bus_10 = sst.Link("link_tcache_bus_10") +link_tcache_bus_10.connect((macsim0_core10_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_43", "50ps")) + + +# Links bus for Core 11 +link_icache_bus_11 = sst.Link("link_icache_bus_11") +link_icache_bus_11.connect((macsim0_core11_icache, "low_network_0", "50ps"), (mem_bus, "high_network_44", "50ps")) + +link_dcache_bus_11 = sst.Link("link_dcache_bus_11") +link_dcache_bus_11.connect((macsim0_core11_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_45", "50ps")) + +link_ccache_bus_11 = sst.Link("link_ccache_bus_11") +link_ccache_bus_11.connect((macsim0_core11_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_46", "50ps")) + +link_tcache_bus_11 = sst.Link("link_tcache_bus_11") +link_tcache_bus_11.connect((macsim0_core11_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_47", "50ps")) + + +# Links bus for Core 12 +link_icache_bus_12 = sst.Link("link_icache_bus_12") +link_icache_bus_12.connect((macsim0_core12_icache, "low_network_0", "50ps"), (mem_bus, "high_network_48", "50ps")) + +link_dcache_bus_12 = sst.Link("link_dcache_bus_12") +link_dcache_bus_12.connect((macsim0_core12_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_49", "50ps")) + +link_ccache_bus_12 = sst.Link("link_ccache_bus_12") +link_ccache_bus_12.connect((macsim0_core12_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_50", "50ps")) + +link_tcache_bus_12 = sst.Link("link_tcache_bus_12") +link_tcache_bus_12.connect((macsim0_core12_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_51", "50ps")) + + +# Links bus for Core 13 +link_icache_bus_13 = sst.Link("link_icache_bus_13") +link_icache_bus_13.connect((macsim0_core13_icache, "low_network_0", "50ps"), (mem_bus, "high_network_52", "50ps")) + +link_dcache_bus_13 = sst.Link("link_dcache_bus_13") +link_dcache_bus_13.connect((macsim0_core13_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_53", "50ps")) + +link_ccache_bus_13 = sst.Link("link_ccache_bus_13") +link_ccache_bus_13.connect((macsim0_core13_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_54", "50ps")) + +link_tcache_bus_13 = sst.Link("link_tcache_bus_13") +link_tcache_bus_13.connect((macsim0_core13_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_55", "50ps")) + + +# Links bus for Core 14 +link_icache_bus_14 = sst.Link("link_icache_bus_14") +link_icache_bus_14.connect((macsim0_core14_icache, "low_network_0", "50ps"), (mem_bus, "high_network_56", "50ps")) + +link_dcache_bus_14 = sst.Link("link_dcache_bus_14") +link_dcache_bus_14.connect((macsim0_core14_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_57", "50ps")) + +link_ccache_bus_14 = sst.Link("link_ccache_bus_14") +link_ccache_bus_14.connect((macsim0_core14_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_58", "50ps")) + +link_tcache_bus_14 = sst.Link("link_tcache_bus_14") +link_tcache_bus_14.connect((macsim0_core14_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_59", "50ps")) + + +# Links bus for Core 15 +link_icache_bus_15 = sst.Link("link_icache_bus_15") +link_icache_bus_15.connect((macsim0_core15_icache, "low_network_0", "50ps"), (mem_bus, "high_network_60", "50ps")) + +link_dcache_bus_15 = sst.Link("link_dcache_bus_15") +link_dcache_bus_15.connect((macsim0_core15_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_61", "50ps")) + +link_ccache_bus_15 = sst.Link("link_ccache_bus_15") +link_ccache_bus_15.connect((macsim0_core15_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_62", "50ps")) + +link_tcache_bus_15 = sst.Link("link_tcache_bus_15") +link_tcache_bus_15.connect((macsim0_core15_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_63", "50ps")) + +# Bus -> Memory +link_bus_mem = sst.Link("link_bus_mem") +link_bus_mem.connect( (mem_bus, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) + + +######################################## +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") diff --git a/sst-unit-test/sdl-04c-gpu-16-core-L1-L2-mem.py b/sst-unit-test/sdl-04c-gpu-16-core-L1-L2-mem.py new file mode 100644 index 000000000..d7b453f3b --- /dev/null +++ b/sst-unit-test/sdl-04c-gpu-16-core-L1-L2-mem.py @@ -0,0 +1,2017 @@ +################################################################################ +# Description: +# - Macsim is connected to L1 caches, followed by a bus and memory controller. +# - Macsim ports (stdInterface) are loaded as subcomponents explictly. +################################################################################ +import sst +from common import * + +# 0: None, 1: Stdout, 2: Stderr, 3: File +DEBUG_CORE = 1 +DEBUG_L1 = 0 +DEBUG_MEM = 1 + +DEBUG_LINKS = 0 +DEBUG_BUS = 0 + +DEBUG_LEVEL = 0 +VERBOSE = 0 + +######################################## +# System Parameters +MEM_SIZE_S = '512MiB' +MEM_SIZE = str2bytes(MEM_SIZE_S) +MEM_START = 0 +MEM_END = MEM_START + MEM_SIZE - 1 + + +######################################## +# Macsim +macsim = sst.Component("macsimComponent", "macsimComponent.macsimComponent") +macsim.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list_gpu", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=16 --num_sim_large_cores=0 --num_sim_small_cores=16 --use_memhierarchy=1 --core_type=nvbit", + "frequency" : "2GHz", + "num_link": "16", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, + "nvbit_core": True, +}) + +######################################## +# Core 0 + +# Interfaces +macsim_icache_if_0 = macsim.setSubComponent("macsim0_core0_icache", "memHierarchy.standardInterface") +macsim_icache_if_0.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_0 = macsim.setSubComponent("macsim0_core0_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_0.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_0 = macsim.setSubComponent("macsim0_core0_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_0.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_0 = macsim.setSubComponent("macsim0_core0_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_0.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core0_icache = sst.Component("macsim0_core0_icache", "memHierarchy.Cache") +macsim0_core0_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core0_dcache = sst.Component("macsim0_core0_dcache", "memHierarchy.Cache") +macsim0_core0_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core0_ccache = sst.Component("macsim0_core0_ccache", "memHierarchy.Cache") +macsim0_core0_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core0_tcache = sst.Component("macsim0_core0_tcache", "memHierarchy.Cache") +macsim0_core0_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 1 + +# Interfaces +macsim_icache_if_1 = macsim.setSubComponent("macsim0_core1_icache", "memHierarchy.standardInterface") +macsim_icache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_1 = macsim.setSubComponent("macsim0_core1_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_1 = macsim.setSubComponent("macsim0_core1_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_1 = macsim.setSubComponent("macsim0_core1_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core1_icache = sst.Component("macsim0_core1_icache", "memHierarchy.Cache") +macsim0_core1_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core1_dcache = sst.Component("macsim0_core1_dcache", "memHierarchy.Cache") +macsim0_core1_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core1_ccache = sst.Component("macsim0_core1_ccache", "memHierarchy.Cache") +macsim0_core1_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core1_tcache = sst.Component("macsim0_core1_tcache", "memHierarchy.Cache") +macsim0_core1_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 2 + +# Interfaces +macsim_icache_if_2 = macsim.setSubComponent("macsim0_core2_icache", "memHierarchy.standardInterface") +macsim_icache_if_2.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_2 = macsim.setSubComponent("macsim0_core2_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_2.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_2 = macsim.setSubComponent("macsim0_core2_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_2.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_2 = macsim.setSubComponent("macsim0_core2_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_2.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core2_icache = sst.Component("macsim0_core2_icache", "memHierarchy.Cache") +macsim0_core2_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core2_dcache = sst.Component("macsim0_core2_dcache", "memHierarchy.Cache") +macsim0_core2_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core2_ccache = sst.Component("macsim0_core2_ccache", "memHierarchy.Cache") +macsim0_core2_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core2_tcache = sst.Component("macsim0_core2_tcache", "memHierarchy.Cache") +macsim0_core2_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 3 + +# Interfaces +macsim_icache_if_3 = macsim.setSubComponent("macsim0_core3_icache", "memHierarchy.standardInterface") +macsim_icache_if_3.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_3 = macsim.setSubComponent("macsim0_core3_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_3.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_3 = macsim.setSubComponent("macsim0_core3_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_3.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_3 = macsim.setSubComponent("macsim0_core3_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_3.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core3_icache = sst.Component("macsim0_core3_icache", "memHierarchy.Cache") +macsim0_core3_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core3_dcache = sst.Component("macsim0_core3_dcache", "memHierarchy.Cache") +macsim0_core3_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core3_ccache = sst.Component("macsim0_core3_ccache", "memHierarchy.Cache") +macsim0_core3_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core3_tcache = sst.Component("macsim0_core3_tcache", "memHierarchy.Cache") +macsim0_core3_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 4 + +# Interfaces +macsim_icache_if_4 = macsim.setSubComponent("macsim0_core4_icache", "memHierarchy.standardInterface") +macsim_icache_if_4.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_4 = macsim.setSubComponent("macsim0_core4_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_4.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_4 = macsim.setSubComponent("macsim0_core4_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_4.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_4 = macsim.setSubComponent("macsim0_core4_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_4.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core4_icache = sst.Component("macsim0_core4_icache", "memHierarchy.Cache") +macsim0_core4_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core4_dcache = sst.Component("macsim0_core4_dcache", "memHierarchy.Cache") +macsim0_core4_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core4_ccache = sst.Component("macsim0_core4_ccache", "memHierarchy.Cache") +macsim0_core4_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core4_tcache = sst.Component("macsim0_core4_tcache", "memHierarchy.Cache") +macsim0_core4_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 5 + +# Interfaces +macsim_icache_if_5 = macsim.setSubComponent("macsim0_core5_icache", "memHierarchy.standardInterface") +macsim_icache_if_5.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_5 = macsim.setSubComponent("macsim0_core5_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_5.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_5 = macsim.setSubComponent("macsim0_core5_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_5.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_5 = macsim.setSubComponent("macsim0_core5_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_5.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core5_icache = sst.Component("macsim0_core5_icache", "memHierarchy.Cache") +macsim0_core5_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core5_dcache = sst.Component("macsim0_core5_dcache", "memHierarchy.Cache") +macsim0_core5_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core5_ccache = sst.Component("macsim0_core5_ccache", "memHierarchy.Cache") +macsim0_core5_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core5_tcache = sst.Component("macsim0_core5_tcache", "memHierarchy.Cache") +macsim0_core5_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 6 + +# Interfaces +macsim_icache_if_6 = macsim.setSubComponent("macsim0_core6_icache", "memHierarchy.standardInterface") +macsim_icache_if_6.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_6 = macsim.setSubComponent("macsim0_core6_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_6.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_6 = macsim.setSubComponent("macsim0_core6_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_6.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_6 = macsim.setSubComponent("macsim0_core6_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_6.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core6_icache = sst.Component("macsim0_core6_icache", "memHierarchy.Cache") +macsim0_core6_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core6_dcache = sst.Component("macsim0_core6_dcache", "memHierarchy.Cache") +macsim0_core6_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core6_ccache = sst.Component("macsim0_core6_ccache", "memHierarchy.Cache") +macsim0_core6_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core6_tcache = sst.Component("macsim0_core6_tcache", "memHierarchy.Cache") +macsim0_core6_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 7 + +# Interfaces +macsim_icache_if_7 = macsim.setSubComponent("macsim0_core7_icache", "memHierarchy.standardInterface") +macsim_icache_if_7.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_7 = macsim.setSubComponent("macsim0_core7_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_7.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_7 = macsim.setSubComponent("macsim0_core7_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_7.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_7 = macsim.setSubComponent("macsim0_core7_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_7.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core7_icache = sst.Component("macsim0_core7_icache", "memHierarchy.Cache") +macsim0_core7_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core7_dcache = sst.Component("macsim0_core7_dcache", "memHierarchy.Cache") +macsim0_core7_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core7_ccache = sst.Component("macsim0_core7_ccache", "memHierarchy.Cache") +macsim0_core7_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core7_tcache = sst.Component("macsim0_core7_tcache", "memHierarchy.Cache") +macsim0_core7_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 8 + +# Interfaces +macsim_icache_if_8 = macsim.setSubComponent("macsim0_core8_icache", "memHierarchy.standardInterface") +macsim_icache_if_8.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_8 = macsim.setSubComponent("macsim0_core8_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_8.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_8 = macsim.setSubComponent("macsim0_core8_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_8.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_8 = macsim.setSubComponent("macsim0_core8_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_8.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core8_icache = sst.Component("macsim0_core8_icache", "memHierarchy.Cache") +macsim0_core8_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core8_dcache = sst.Component("macsim0_core8_dcache", "memHierarchy.Cache") +macsim0_core8_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core8_ccache = sst.Component("macsim0_core8_ccache", "memHierarchy.Cache") +macsim0_core8_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core8_tcache = sst.Component("macsim0_core8_tcache", "memHierarchy.Cache") +macsim0_core8_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 9 + +# Interfaces +macsim_icache_if_9 = macsim.setSubComponent("macsim0_core9_icache", "memHierarchy.standardInterface") +macsim_icache_if_9.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_9 = macsim.setSubComponent("macsim0_core9_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_9.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_9 = macsim.setSubComponent("macsim0_core9_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_9.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_9 = macsim.setSubComponent("macsim0_core9_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_9.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core9_icache = sst.Component("macsim0_core9_icache", "memHierarchy.Cache") +macsim0_core9_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core9_dcache = sst.Component("macsim0_core9_dcache", "memHierarchy.Cache") +macsim0_core9_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core9_ccache = sst.Component("macsim0_core9_ccache", "memHierarchy.Cache") +macsim0_core9_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core9_tcache = sst.Component("macsim0_core9_tcache", "memHierarchy.Cache") +macsim0_core9_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 10 + +# Interfaces +macsim_icache_if_10 = macsim.setSubComponent("macsim0_core10_icache", "memHierarchy.standardInterface") +macsim_icache_if_10.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_10 = macsim.setSubComponent("macsim0_core10_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_10.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_10 = macsim.setSubComponent("macsim0_core10_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_10.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_10 = macsim.setSubComponent("macsim0_core10_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_10.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core10_icache = sst.Component("macsim0_core10_icache", "memHierarchy.Cache") +macsim0_core10_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core10_dcache = sst.Component("macsim0_core10_dcache", "memHierarchy.Cache") +macsim0_core10_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core10_ccache = sst.Component("macsim0_core10_ccache", "memHierarchy.Cache") +macsim0_core10_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core10_tcache = sst.Component("macsim0_core10_tcache", "memHierarchy.Cache") +macsim0_core10_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 11 + +# Interfaces +macsim_icache_if_11 = macsim.setSubComponent("macsim0_core11_icache", "memHierarchy.standardInterface") +macsim_icache_if_11.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_11 = macsim.setSubComponent("macsim0_core11_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_11.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_11 = macsim.setSubComponent("macsim0_core11_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_11.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_11 = macsim.setSubComponent("macsim0_core11_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_11.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core11_icache = sst.Component("macsim0_core11_icache", "memHierarchy.Cache") +macsim0_core11_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core11_dcache = sst.Component("macsim0_core11_dcache", "memHierarchy.Cache") +macsim0_core11_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core11_ccache = sst.Component("macsim0_core11_ccache", "memHierarchy.Cache") +macsim0_core11_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core11_tcache = sst.Component("macsim0_core11_tcache", "memHierarchy.Cache") +macsim0_core11_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 12 + +# Interfaces +macsim_icache_if_12 = macsim.setSubComponent("macsim0_core12_icache", "memHierarchy.standardInterface") +macsim_icache_if_12.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_12 = macsim.setSubComponent("macsim0_core12_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_12.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_12 = macsim.setSubComponent("macsim0_core12_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_12.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_12 = macsim.setSubComponent("macsim0_core12_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_12.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core12_icache = sst.Component("macsim0_core12_icache", "memHierarchy.Cache") +macsim0_core12_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core12_dcache = sst.Component("macsim0_core12_dcache", "memHierarchy.Cache") +macsim0_core12_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core12_ccache = sst.Component("macsim0_core12_ccache", "memHierarchy.Cache") +macsim0_core12_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core12_tcache = sst.Component("macsim0_core12_tcache", "memHierarchy.Cache") +macsim0_core12_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 13 + +# Interfaces +macsim_icache_if_13 = macsim.setSubComponent("macsim0_core13_icache", "memHierarchy.standardInterface") +macsim_icache_if_13.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_13 = macsim.setSubComponent("macsim0_core13_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_13.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_13 = macsim.setSubComponent("macsim0_core13_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_13.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_13 = macsim.setSubComponent("macsim0_core13_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_13.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core13_icache = sst.Component("macsim0_core13_icache", "memHierarchy.Cache") +macsim0_core13_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core13_dcache = sst.Component("macsim0_core13_dcache", "memHierarchy.Cache") +macsim0_core13_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core13_ccache = sst.Component("macsim0_core13_ccache", "memHierarchy.Cache") +macsim0_core13_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core13_tcache = sst.Component("macsim0_core13_tcache", "memHierarchy.Cache") +macsim0_core13_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 14 + +# Interfaces +macsim_icache_if_14 = macsim.setSubComponent("macsim0_core14_icache", "memHierarchy.standardInterface") +macsim_icache_if_14.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_14 = macsim.setSubComponent("macsim0_core14_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_14.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_14 = macsim.setSubComponent("macsim0_core14_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_14.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_14 = macsim.setSubComponent("macsim0_core14_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_14.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core14_icache = sst.Component("macsim0_core14_icache", "memHierarchy.Cache") +macsim0_core14_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core14_dcache = sst.Component("macsim0_core14_dcache", "memHierarchy.Cache") +macsim0_core14_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core14_ccache = sst.Component("macsim0_core14_ccache", "memHierarchy.Cache") +macsim0_core14_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core14_tcache = sst.Component("macsim0_core14_tcache", "memHierarchy.Cache") +macsim0_core14_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Core 15 + +# Interfaces +macsim_icache_if_15 = macsim.setSubComponent("macsim0_core15_icache", "memHierarchy.standardInterface") +macsim_icache_if_15.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_dcache_if_15 = macsim.setSubComponent("macsim0_core15_dcache", "memHierarchy.standardInterface") +macsim_dcache_if_15.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_ccache_if_15 = macsim.setSubComponent("macsim0_core15_ccache", "memHierarchy.standardInterface") +macsim_ccache_if_15.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_tcache_if_15 = macsim.setSubComponent("macsim0_core15_tcache", "memHierarchy.standardInterface") +macsim_tcache_if_15.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# L1 Caches +macsim0_core15_icache = sst.Component("macsim0_core15_icache", "memHierarchy.Cache") +macsim0_core15_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core15_dcache = sst.Component("macsim0_core15_dcache", "memHierarchy.Cache") +macsim0_core15_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core15_ccache = sst.Component("macsim0_core15_ccache", "memHierarchy.Cache") +macsim0_core15_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim0_core15_tcache = sst.Component("macsim0_core15_tcache", "memHierarchy.Cache") +macsim0_core15_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +######################################## +# L2 caches +gpu_l2cache = sst.Component("l2cache", "memHierarchy.Cache") +gpu_l2cache.addParams({ + "access_latency_cycles" : "8", + "cache_frequency" : "4Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "8", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "0", + "cache_size" : "64KiB" +}) + +######################################## +# Bus between L1 caches and memory controller +mem_bus = sst.Component("mem_bus", "memHierarchy.Bus") +mem_bus.addParams({ + "debug" : DEBUG_LINKS, + "debug_level" : DEBUG_LEVEL, + "bus_frequency" : "4 Ghz" +}) + + +######################################## +# Memory Controller +memctrl = sst.Component("memctrl", "memHierarchy.MemController") +memctrl.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + # "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") +memory.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + + +# Links for Core 0 +link_macsim_icache_0 = sst.Link("link_macsim_icache_0") +link_macsim_icache_0.connect((macsim_icache_if_0, "port", "1000ps"), (macsim0_core0_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_0 = sst.Link("link_macsim_dcache_0") +link_macsim_dcache_0.connect((macsim_dcache_if_0, "port", "1000ps"), (macsim0_core0_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_0 = sst.Link("link_macsim_ccache_0") +link_macsim_ccache_0.connect((macsim_ccache_if_0, "port", "1000ps"), (macsim0_core0_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_0 = sst.Link("link_macsim_tcache_0") +link_macsim_tcache_0.connect((macsim_tcache_if_0, "port", "1000ps"), (macsim0_core0_tcache, "high_network_0", "1000ps")) + + +# Links for Core 1 +link_macsim_icache_1 = sst.Link("link_macsim_icache_1") +link_macsim_icache_1.connect((macsim_icache_if_1, "port", "1000ps"), (macsim0_core1_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_1 = sst.Link("link_macsim_dcache_1") +link_macsim_dcache_1.connect((macsim_dcache_if_1, "port", "1000ps"), (macsim0_core1_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_1 = sst.Link("link_macsim_ccache_1") +link_macsim_ccache_1.connect((macsim_ccache_if_1, "port", "1000ps"), (macsim0_core1_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_1 = sst.Link("link_macsim_tcache_1") +link_macsim_tcache_1.connect((macsim_tcache_if_1, "port", "1000ps"), (macsim0_core1_tcache, "high_network_0", "1000ps")) + + +# Links for Core 2 +link_macsim_icache_2 = sst.Link("link_macsim_icache_2") +link_macsim_icache_2.connect((macsim_icache_if_2, "port", "1000ps"), (macsim0_core2_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_2 = sst.Link("link_macsim_dcache_2") +link_macsim_dcache_2.connect((macsim_dcache_if_2, "port", "1000ps"), (macsim0_core2_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_2 = sst.Link("link_macsim_ccache_2") +link_macsim_ccache_2.connect((macsim_ccache_if_2, "port", "1000ps"), (macsim0_core2_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_2 = sst.Link("link_macsim_tcache_2") +link_macsim_tcache_2.connect((macsim_tcache_if_2, "port", "1000ps"), (macsim0_core2_tcache, "high_network_0", "1000ps")) + + +# Links for Core 3 +link_macsim_icache_3 = sst.Link("link_macsim_icache_3") +link_macsim_icache_3.connect((macsim_icache_if_3, "port", "1000ps"), (macsim0_core3_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_3 = sst.Link("link_macsim_dcache_3") +link_macsim_dcache_3.connect((macsim_dcache_if_3, "port", "1000ps"), (macsim0_core3_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_3 = sst.Link("link_macsim_ccache_3") +link_macsim_ccache_3.connect((macsim_ccache_if_3, "port", "1000ps"), (macsim0_core3_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_3 = sst.Link("link_macsim_tcache_3") +link_macsim_tcache_3.connect((macsim_tcache_if_3, "port", "1000ps"), (macsim0_core3_tcache, "high_network_0", "1000ps")) + + +# Links for Core 4 +link_macsim_icache_4 = sst.Link("link_macsim_icache_4") +link_macsim_icache_4.connect((macsim_icache_if_4, "port", "1000ps"), (macsim0_core4_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_4 = sst.Link("link_macsim_dcache_4") +link_macsim_dcache_4.connect((macsim_dcache_if_4, "port", "1000ps"), (macsim0_core4_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_4 = sst.Link("link_macsim_ccache_4") +link_macsim_ccache_4.connect((macsim_ccache_if_4, "port", "1000ps"), (macsim0_core4_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_4 = sst.Link("link_macsim_tcache_4") +link_macsim_tcache_4.connect((macsim_tcache_if_4, "port", "1000ps"), (macsim0_core4_tcache, "high_network_0", "1000ps")) + + +# Links for Core 5 +link_macsim_icache_5 = sst.Link("link_macsim_icache_5") +link_macsim_icache_5.connect((macsim_icache_if_5, "port", "1000ps"), (macsim0_core5_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_5 = sst.Link("link_macsim_dcache_5") +link_macsim_dcache_5.connect((macsim_dcache_if_5, "port", "1000ps"), (macsim0_core5_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_5 = sst.Link("link_macsim_ccache_5") +link_macsim_ccache_5.connect((macsim_ccache_if_5, "port", "1000ps"), (macsim0_core5_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_5 = sst.Link("link_macsim_tcache_5") +link_macsim_tcache_5.connect((macsim_tcache_if_5, "port", "1000ps"), (macsim0_core5_tcache, "high_network_0", "1000ps")) + + +# Links for Core 6 +link_macsim_icache_6 = sst.Link("link_macsim_icache_6") +link_macsim_icache_6.connect((macsim_icache_if_6, "port", "1000ps"), (macsim0_core6_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_6 = sst.Link("link_macsim_dcache_6") +link_macsim_dcache_6.connect((macsim_dcache_if_6, "port", "1000ps"), (macsim0_core6_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_6 = sst.Link("link_macsim_ccache_6") +link_macsim_ccache_6.connect((macsim_ccache_if_6, "port", "1000ps"), (macsim0_core6_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_6 = sst.Link("link_macsim_tcache_6") +link_macsim_tcache_6.connect((macsim_tcache_if_6, "port", "1000ps"), (macsim0_core6_tcache, "high_network_0", "1000ps")) + + +# Links for Core 7 +link_macsim_icache_7 = sst.Link("link_macsim_icache_7") +link_macsim_icache_7.connect((macsim_icache_if_7, "port", "1000ps"), (macsim0_core7_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_7 = sst.Link("link_macsim_dcache_7") +link_macsim_dcache_7.connect((macsim_dcache_if_7, "port", "1000ps"), (macsim0_core7_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_7 = sst.Link("link_macsim_ccache_7") +link_macsim_ccache_7.connect((macsim_ccache_if_7, "port", "1000ps"), (macsim0_core7_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_7 = sst.Link("link_macsim_tcache_7") +link_macsim_tcache_7.connect((macsim_tcache_if_7, "port", "1000ps"), (macsim0_core7_tcache, "high_network_0", "1000ps")) + + +# Links for Core 8 +link_macsim_icache_8 = sst.Link("link_macsim_icache_8") +link_macsim_icache_8.connect((macsim_icache_if_8, "port", "1000ps"), (macsim0_core8_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_8 = sst.Link("link_macsim_dcache_8") +link_macsim_dcache_8.connect((macsim_dcache_if_8, "port", "1000ps"), (macsim0_core8_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_8 = sst.Link("link_macsim_ccache_8") +link_macsim_ccache_8.connect((macsim_ccache_if_8, "port", "1000ps"), (macsim0_core8_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_8 = sst.Link("link_macsim_tcache_8") +link_macsim_tcache_8.connect((macsim_tcache_if_8, "port", "1000ps"), (macsim0_core8_tcache, "high_network_0", "1000ps")) + + +# Links for Core 9 +link_macsim_icache_9 = sst.Link("link_macsim_icache_9") +link_macsim_icache_9.connect((macsim_icache_if_9, "port", "1000ps"), (macsim0_core9_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_9 = sst.Link("link_macsim_dcache_9") +link_macsim_dcache_9.connect((macsim_dcache_if_9, "port", "1000ps"), (macsim0_core9_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_9 = sst.Link("link_macsim_ccache_9") +link_macsim_ccache_9.connect((macsim_ccache_if_9, "port", "1000ps"), (macsim0_core9_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_9 = sst.Link("link_macsim_tcache_9") +link_macsim_tcache_9.connect((macsim_tcache_if_9, "port", "1000ps"), (macsim0_core9_tcache, "high_network_0", "1000ps")) + + +# Links for Core 10 +link_macsim_icache_10 = sst.Link("link_macsim_icache_10") +link_macsim_icache_10.connect((macsim_icache_if_10, "port", "1000ps"), (macsim0_core10_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_10 = sst.Link("link_macsim_dcache_10") +link_macsim_dcache_10.connect((macsim_dcache_if_10, "port", "1000ps"), (macsim0_core10_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_10 = sst.Link("link_macsim_ccache_10") +link_macsim_ccache_10.connect((macsim_ccache_if_10, "port", "1000ps"), (macsim0_core10_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_10 = sst.Link("link_macsim_tcache_10") +link_macsim_tcache_10.connect((macsim_tcache_if_10, "port", "1000ps"), (macsim0_core10_tcache, "high_network_0", "1000ps")) + + +# Links for Core 11 +link_macsim_icache_11 = sst.Link("link_macsim_icache_11") +link_macsim_icache_11.connect((macsim_icache_if_11, "port", "1000ps"), (macsim0_core11_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_11 = sst.Link("link_macsim_dcache_11") +link_macsim_dcache_11.connect((macsim_dcache_if_11, "port", "1000ps"), (macsim0_core11_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_11 = sst.Link("link_macsim_ccache_11") +link_macsim_ccache_11.connect((macsim_ccache_if_11, "port", "1000ps"), (macsim0_core11_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_11 = sst.Link("link_macsim_tcache_11") +link_macsim_tcache_11.connect((macsim_tcache_if_11, "port", "1000ps"), (macsim0_core11_tcache, "high_network_0", "1000ps")) + + +# Links for Core 12 +link_macsim_icache_12 = sst.Link("link_macsim_icache_12") +link_macsim_icache_12.connect((macsim_icache_if_12, "port", "1000ps"), (macsim0_core12_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_12 = sst.Link("link_macsim_dcache_12") +link_macsim_dcache_12.connect((macsim_dcache_if_12, "port", "1000ps"), (macsim0_core12_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_12 = sst.Link("link_macsim_ccache_12") +link_macsim_ccache_12.connect((macsim_ccache_if_12, "port", "1000ps"), (macsim0_core12_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_12 = sst.Link("link_macsim_tcache_12") +link_macsim_tcache_12.connect((macsim_tcache_if_12, "port", "1000ps"), (macsim0_core12_tcache, "high_network_0", "1000ps")) + + +# Links for Core 13 +link_macsim_icache_13 = sst.Link("link_macsim_icache_13") +link_macsim_icache_13.connect((macsim_icache_if_13, "port", "1000ps"), (macsim0_core13_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_13 = sst.Link("link_macsim_dcache_13") +link_macsim_dcache_13.connect((macsim_dcache_if_13, "port", "1000ps"), (macsim0_core13_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_13 = sst.Link("link_macsim_ccache_13") +link_macsim_ccache_13.connect((macsim_ccache_if_13, "port", "1000ps"), (macsim0_core13_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_13 = sst.Link("link_macsim_tcache_13") +link_macsim_tcache_13.connect((macsim_tcache_if_13, "port", "1000ps"), (macsim0_core13_tcache, "high_network_0", "1000ps")) + + +# Links for Core 14 +link_macsim_icache_14 = sst.Link("link_macsim_icache_14") +link_macsim_icache_14.connect((macsim_icache_if_14, "port", "1000ps"), (macsim0_core14_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_14 = sst.Link("link_macsim_dcache_14") +link_macsim_dcache_14.connect((macsim_dcache_if_14, "port", "1000ps"), (macsim0_core14_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_14 = sst.Link("link_macsim_ccache_14") +link_macsim_ccache_14.connect((macsim_ccache_if_14, "port", "1000ps"), (macsim0_core14_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_14 = sst.Link("link_macsim_tcache_14") +link_macsim_tcache_14.connect((macsim_tcache_if_14, "port", "1000ps"), (macsim0_core14_tcache, "high_network_0", "1000ps")) + + +# Links for Core 15 +link_macsim_icache_15 = sst.Link("link_macsim_icache_15") +link_macsim_icache_15.connect((macsim_icache_if_15, "port", "1000ps"), (macsim0_core15_icache, "high_network_0", "1000ps")) + +link_macsim_dcache_15 = sst.Link("link_macsim_dcache_15") +link_macsim_dcache_15.connect((macsim_dcache_if_15, "port", "1000ps"), (macsim0_core15_dcache, "high_network_0", "1000ps")) + +link_macsim_ccache_15 = sst.Link("link_macsim_ccache_15") +link_macsim_ccache_15.connect((macsim_ccache_if_15, "port", "1000ps"), (macsim0_core15_ccache, "high_network_0", "1000ps")) + +link_macsim_tcache_15 = sst.Link("link_macsim_tcache_15") +link_macsim_tcache_15.connect((macsim_tcache_if_15, "port", "1000ps"), (macsim0_core15_tcache, "high_network_0", "1000ps")) + + +# Links bus for Core 0 +link_icache_bus_0 = sst.Link("link_icache_bus_0") +link_icache_bus_0.connect((macsim0_core0_icache, "low_network_0", "50ps"), (mem_bus, "high_network_0", "50ps")) + +link_dcache_bus_0 = sst.Link("link_dcache_bus_0") +link_dcache_bus_0.connect((macsim0_core0_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_1", "50ps")) + +link_ccache_bus_0 = sst.Link("link_ccache_bus_0") +link_ccache_bus_0.connect((macsim0_core0_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_2", "50ps")) + +link_tcache_bus_0 = sst.Link("link_tcache_bus_0") +link_tcache_bus_0.connect((macsim0_core0_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_3", "50ps")) + + +# Links bus for Core 1 +link_icache_bus_1 = sst.Link("link_icache_bus_1") +link_icache_bus_1.connect((macsim0_core1_icache, "low_network_0", "50ps"), (mem_bus, "high_network_4", "50ps")) + +link_dcache_bus_1 = sst.Link("link_dcache_bus_1") +link_dcache_bus_1.connect((macsim0_core1_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_5", "50ps")) + +link_ccache_bus_1 = sst.Link("link_ccache_bus_1") +link_ccache_bus_1.connect((macsim0_core1_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_6", "50ps")) + +link_tcache_bus_1 = sst.Link("link_tcache_bus_1") +link_tcache_bus_1.connect((macsim0_core1_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_7", "50ps")) + + +# Links bus for Core 2 +link_icache_bus_2 = sst.Link("link_icache_bus_2") +link_icache_bus_2.connect((macsim0_core2_icache, "low_network_0", "50ps"), (mem_bus, "high_network_8", "50ps")) + +link_dcache_bus_2 = sst.Link("link_dcache_bus_2") +link_dcache_bus_2.connect((macsim0_core2_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_9", "50ps")) + +link_ccache_bus_2 = sst.Link("link_ccache_bus_2") +link_ccache_bus_2.connect((macsim0_core2_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_10", "50ps")) + +link_tcache_bus_2 = sst.Link("link_tcache_bus_2") +link_tcache_bus_2.connect((macsim0_core2_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_11", "50ps")) + + +# Links bus for Core 3 +link_icache_bus_3 = sst.Link("link_icache_bus_3") +link_icache_bus_3.connect((macsim0_core3_icache, "low_network_0", "50ps"), (mem_bus, "high_network_12", "50ps")) + +link_dcache_bus_3 = sst.Link("link_dcache_bus_3") +link_dcache_bus_3.connect((macsim0_core3_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_13", "50ps")) + +link_ccache_bus_3 = sst.Link("link_ccache_bus_3") +link_ccache_bus_3.connect((macsim0_core3_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_14", "50ps")) + +link_tcache_bus_3 = sst.Link("link_tcache_bus_3") +link_tcache_bus_3.connect((macsim0_core3_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_15", "50ps")) + + +# Links bus for Core 4 +link_icache_bus_4 = sst.Link("link_icache_bus_4") +link_icache_bus_4.connect((macsim0_core4_icache, "low_network_0", "50ps"), (mem_bus, "high_network_16", "50ps")) + +link_dcache_bus_4 = sst.Link("link_dcache_bus_4") +link_dcache_bus_4.connect((macsim0_core4_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_17", "50ps")) + +link_ccache_bus_4 = sst.Link("link_ccache_bus_4") +link_ccache_bus_4.connect((macsim0_core4_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_18", "50ps")) + +link_tcache_bus_4 = sst.Link("link_tcache_bus_4") +link_tcache_bus_4.connect((macsim0_core4_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_19", "50ps")) + + +# Links bus for Core 5 +link_icache_bus_5 = sst.Link("link_icache_bus_5") +link_icache_bus_5.connect((macsim0_core5_icache, "low_network_0", "50ps"), (mem_bus, "high_network_20", "50ps")) + +link_dcache_bus_5 = sst.Link("link_dcache_bus_5") +link_dcache_bus_5.connect((macsim0_core5_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_21", "50ps")) + +link_ccache_bus_5 = sst.Link("link_ccache_bus_5") +link_ccache_bus_5.connect((macsim0_core5_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_22", "50ps")) + +link_tcache_bus_5 = sst.Link("link_tcache_bus_5") +link_tcache_bus_5.connect((macsim0_core5_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_23", "50ps")) + + +# Links bus for Core 6 +link_icache_bus_6 = sst.Link("link_icache_bus_6") +link_icache_bus_6.connect((macsim0_core6_icache, "low_network_0", "50ps"), (mem_bus, "high_network_24", "50ps")) + +link_dcache_bus_6 = sst.Link("link_dcache_bus_6") +link_dcache_bus_6.connect((macsim0_core6_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_25", "50ps")) + +link_ccache_bus_6 = sst.Link("link_ccache_bus_6") +link_ccache_bus_6.connect((macsim0_core6_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_26", "50ps")) + +link_tcache_bus_6 = sst.Link("link_tcache_bus_6") +link_tcache_bus_6.connect((macsim0_core6_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_27", "50ps")) + + +# Links bus for Core 7 +link_icache_bus_7 = sst.Link("link_icache_bus_7") +link_icache_bus_7.connect((macsim0_core7_icache, "low_network_0", "50ps"), (mem_bus, "high_network_28", "50ps")) + +link_dcache_bus_7 = sst.Link("link_dcache_bus_7") +link_dcache_bus_7.connect((macsim0_core7_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_29", "50ps")) + +link_ccache_bus_7 = sst.Link("link_ccache_bus_7") +link_ccache_bus_7.connect((macsim0_core7_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_30", "50ps")) + +link_tcache_bus_7 = sst.Link("link_tcache_bus_7") +link_tcache_bus_7.connect((macsim0_core7_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_31", "50ps")) + + +# Links bus for Core 8 +link_icache_bus_8 = sst.Link("link_icache_bus_8") +link_icache_bus_8.connect((macsim0_core8_icache, "low_network_0", "50ps"), (mem_bus, "high_network_32", "50ps")) + +link_dcache_bus_8 = sst.Link("link_dcache_bus_8") +link_dcache_bus_8.connect((macsim0_core8_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_33", "50ps")) + +link_ccache_bus_8 = sst.Link("link_ccache_bus_8") +link_ccache_bus_8.connect((macsim0_core8_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_34", "50ps")) + +link_tcache_bus_8 = sst.Link("link_tcache_bus_8") +link_tcache_bus_8.connect((macsim0_core8_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_35", "50ps")) + + +# Links bus for Core 9 +link_icache_bus_9 = sst.Link("link_icache_bus_9") +link_icache_bus_9.connect((macsim0_core9_icache, "low_network_0", "50ps"), (mem_bus, "high_network_36", "50ps")) + +link_dcache_bus_9 = sst.Link("link_dcache_bus_9") +link_dcache_bus_9.connect((macsim0_core9_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_37", "50ps")) + +link_ccache_bus_9 = sst.Link("link_ccache_bus_9") +link_ccache_bus_9.connect((macsim0_core9_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_38", "50ps")) + +link_tcache_bus_9 = sst.Link("link_tcache_bus_9") +link_tcache_bus_9.connect((macsim0_core9_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_39", "50ps")) + + +# Links bus for Core 10 +link_icache_bus_10 = sst.Link("link_icache_bus_10") +link_icache_bus_10.connect((macsim0_core10_icache, "low_network_0", "50ps"), (mem_bus, "high_network_40", "50ps")) + +link_dcache_bus_10 = sst.Link("link_dcache_bus_10") +link_dcache_bus_10.connect((macsim0_core10_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_41", "50ps")) + +link_ccache_bus_10 = sst.Link("link_ccache_bus_10") +link_ccache_bus_10.connect((macsim0_core10_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_42", "50ps")) + +link_tcache_bus_10 = sst.Link("link_tcache_bus_10") +link_tcache_bus_10.connect((macsim0_core10_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_43", "50ps")) + + +# Links bus for Core 11 +link_icache_bus_11 = sst.Link("link_icache_bus_11") +link_icache_bus_11.connect((macsim0_core11_icache, "low_network_0", "50ps"), (mem_bus, "high_network_44", "50ps")) + +link_dcache_bus_11 = sst.Link("link_dcache_bus_11") +link_dcache_bus_11.connect((macsim0_core11_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_45", "50ps")) + +link_ccache_bus_11 = sst.Link("link_ccache_bus_11") +link_ccache_bus_11.connect((macsim0_core11_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_46", "50ps")) + +link_tcache_bus_11 = sst.Link("link_tcache_bus_11") +link_tcache_bus_11.connect((macsim0_core11_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_47", "50ps")) + + +# Links bus for Core 12 +link_icache_bus_12 = sst.Link("link_icache_bus_12") +link_icache_bus_12.connect((macsim0_core12_icache, "low_network_0", "50ps"), (mem_bus, "high_network_48", "50ps")) + +link_dcache_bus_12 = sst.Link("link_dcache_bus_12") +link_dcache_bus_12.connect((macsim0_core12_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_49", "50ps")) + +link_ccache_bus_12 = sst.Link("link_ccache_bus_12") +link_ccache_bus_12.connect((macsim0_core12_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_50", "50ps")) + +link_tcache_bus_12 = sst.Link("link_tcache_bus_12") +link_tcache_bus_12.connect((macsim0_core12_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_51", "50ps")) + + +# Links bus for Core 13 +link_icache_bus_13 = sst.Link("link_icache_bus_13") +link_icache_bus_13.connect((macsim0_core13_icache, "low_network_0", "50ps"), (mem_bus, "high_network_52", "50ps")) + +link_dcache_bus_13 = sst.Link("link_dcache_bus_13") +link_dcache_bus_13.connect((macsim0_core13_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_53", "50ps")) + +link_ccache_bus_13 = sst.Link("link_ccache_bus_13") +link_ccache_bus_13.connect((macsim0_core13_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_54", "50ps")) + +link_tcache_bus_13 = sst.Link("link_tcache_bus_13") +link_tcache_bus_13.connect((macsim0_core13_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_55", "50ps")) + + +# Links bus for Core 14 +link_icache_bus_14 = sst.Link("link_icache_bus_14") +link_icache_bus_14.connect((macsim0_core14_icache, "low_network_0", "50ps"), (mem_bus, "high_network_56", "50ps")) + +link_dcache_bus_14 = sst.Link("link_dcache_bus_14") +link_dcache_bus_14.connect((macsim0_core14_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_57", "50ps")) + +link_ccache_bus_14 = sst.Link("link_ccache_bus_14") +link_ccache_bus_14.connect((macsim0_core14_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_58", "50ps")) + +link_tcache_bus_14 = sst.Link("link_tcache_bus_14") +link_tcache_bus_14.connect((macsim0_core14_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_59", "50ps")) + + +# Links bus for Core 15 +link_icache_bus_15 = sst.Link("link_icache_bus_15") +link_icache_bus_15.connect((macsim0_core15_icache, "low_network_0", "50ps"), (mem_bus, "high_network_60", "50ps")) + +link_dcache_bus_15 = sst.Link("link_dcache_bus_15") +link_dcache_bus_15.connect((macsim0_core15_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_61", "50ps")) + +link_ccache_bus_15 = sst.Link("link_ccache_bus_15") +link_ccache_bus_15.connect((macsim0_core15_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_62", "50ps")) + +link_tcache_bus_15 = sst.Link("link_tcache_bus_15") +link_tcache_bus_15.connect((macsim0_core15_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_63", "50ps")) + +# Bus -> Memory +link_bus_L2 = sst.Link("link_bus_L2") +link_bus_L2.connect( (mem_bus, "low_network_0", "50ps"), (gpu_l2cache, "high_network_0", "50ps") ) +link_bus_mem = sst.Link("link_bus_mem") +link_bus_mem.connect( (gpu_l2cache, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) + + +######################################## +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") diff --git a/sst-unit-test/sdl-05a-2-gpu-2-core-L1-mem.py b/sst-unit-test/sdl-05a-2-gpu-2-core-L1-mem.py new file mode 100644 index 000000000..095c171b8 --- /dev/null +++ b/sst-unit-test/sdl-05a-2-gpu-2-core-L1-mem.py @@ -0,0 +1,563 @@ +################################################################################ +# Description: +# - Macsim is connected to L1 caches, followed by a bus and memory controller. +# - Macsim ports (stdInterface) are loaded as subcomponents explictly. +################################################################################ +import sst +from common import * + +# 0: None, 1: Stdout, 2: Stderr, 3: File +DEBUG_CORE = 1 +DEBUG_L1 = 1 +DEBUG_MEM = 1 + +DEBUG_LINKS = 0 +DEBUG_BUS = 0 + +DEBUG_LEVEL = 0 +VERBOSE = 0 + +######################################## +# System Parameters +MEM_SIZE_S = '512MiB' +MEM_SIZE = str2bytes(MEM_SIZE_S) +MEM_START = 0 +MEM_END = MEM_START + MEM_SIZE - 1 + + +######################################## +# Macsim 0 +macsim_0 = sst.Component("macsimComponent0", "macsimComponent.macsimComponent") +macsim_0.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list_gpu", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=2 --num_sim_large_cores=0 --num_sim_small_cores=2 --use_memhierarchy=1 --core_type=nvbit", + "frequency" : "2GHz", + "num_link": "2", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, + "nvbit_core": True, + "component_num": 0, +}) + +######################################## +# Macsim 1 +macsim_1 = sst.Component("macsimComponent1", "macsimComponent.macsimComponent") +macsim_1.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list_gpu", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=2 --num_sim_large_cores=0 --num_sim_small_cores=2 --use_memhierarchy=1 --core_type=nvbit", + "frequency" : "2GHz", + "num_link": "2", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, + "nvbit_core": True, + "component_num": 1, +}) + +######################################## +# Macsim 0 +# Core 0 interface +macsim_0_icache_if = macsim_0.setSubComponent("macsim0_core0_icache", "memHierarchy.standardInterface") +macsim_0_icache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_0_dcache_if = macsim_0.setSubComponent("macsim0_core0_dcache", "memHierarchy.standardInterface") +macsim_0_dcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_0_ccache_if = macsim_0.setSubComponent("macsim0_core0_ccache", "memHierarchy.standardInterface") +macsim_0_ccache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_0_tcache_if = macsim_0.setSubComponent("macsim0_core0_tcache", "memHierarchy.standardInterface") +macsim_0_tcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +# Core 1 Interfaces +macsim_0_icache_if_1 = macsim_0.setSubComponent("macsim0_core1_icache", "memHierarchy.standardInterface") +macsim_0_icache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_0_dcache_if_1 = macsim_0.setSubComponent("macsim0_core1_dcache", "memHierarchy.standardInterface") +macsim_0_dcache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_0_ccache_if_1 = macsim_0.setSubComponent("macsim0_core1_ccache", "memHierarchy.standardInterface") +macsim_0_ccache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_0_tcache_if_1 = macsim_0.setSubComponent("macsim0_core1_tcache", "memHierarchy.standardInterface") +macsim_0_tcache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# Macsim 1 +# Core 0 interface +macsim_1_icache_if = macsim_1.setSubComponent("macsim1_core0_icache", "memHierarchy.standardInterface") +macsim_1_icache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_1_dcache_if = macsim_1.setSubComponent("macsim1_core0_dcache", "memHierarchy.standardInterface") +macsim_1_dcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_1_ccache_if = macsim_1.setSubComponent("macsim1_core0_ccache", "memHierarchy.standardInterface") +macsim_1_ccache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_1_tcache_if = macsim_1.setSubComponent("macsim1_core0_tcache", "memHierarchy.standardInterface") +macsim_1_tcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +# Core 1 Interfaces +macsim_1_icache_if_1 = macsim_1.setSubComponent("macsim1_core1_icache", "memHierarchy.standardInterface") +macsim_1_icache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_1_dcache_if_1 = macsim_1.setSubComponent("macsim1_core1_dcache", "memHierarchy.standardInterface") +macsim_1_dcache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_1_ccache_if_1 = macsim_1.setSubComponent("macsim1_core1_ccache", "memHierarchy.standardInterface") +macsim_1_ccache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_1_tcache_if_1 = macsim_1.setSubComponent("macsim1_core1_tcache", "memHierarchy.standardInterface") +macsim_1_tcache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + + +######################################## +# Macsim 0 +# Core 0 L1 Caches +macsim_0_core0_icache = sst.Component("macsim0_core0_icache", "memHierarchy.Cache") +macsim_0_core0_icache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim_0_core0_dcache = sst.Component("macsim0_core0_dcache", "memHierarchy.Cache") +macsim_0_core0_dcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) +# ######################################## +# # Const Caches +macsim_0_core0_ccache = sst.Component("macsim0_core0_ccache", "memHierarchy.Cache") +macsim_0_core0_ccache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim_0_core0_tcache = sst.Component("macsim0_core0_tcache", "memHierarchy.Cache") +macsim_0_core0_tcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", #set this to be 128 to align with int block_size = KNOB(KNOB_L1_SMALL_LINE_SIZE)->getValue(); + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +######################################## +# Macsim 0 +# Core 1 L1 Caches +macsim_0_core1_icache = sst.Component("macsim0_core1_icache", "memHierarchy.Cache") +macsim_0_core1_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim_0_core1_dcache = sst.Component("macsim0_core1_dcache", "memHierarchy.Cache") +macsim_0_core1_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim_0_core1_ccache = sst.Component("macsim0_core1_ccache", "memHierarchy.Cache") +macsim_0_core1_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim_0_core1_tcache = sst.Component("macsim0_core1_tcache", "memHierarchy.Cache") +macsim_0_core1_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + + +######################################## +# Macsim 1 +# Core 0 L1 Caches +macsim_1_core0_icache = sst.Component("macsim1_core0_icache", "memHierarchy.Cache") +macsim_1_core0_icache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim_1_core0_dcache = sst.Component("macsim1_core0_dcache", "memHierarchy.Cache") +macsim_1_core0_dcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) +# ######################################## +# # Const Caches +macsim_1_core0_ccache = sst.Component("macsim1_core0_ccache", "memHierarchy.Cache") +macsim_1_core0_ccache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim_1_core0_tcache = sst.Component("macsim1_core0_tcache", "memHierarchy.Cache") +macsim_1_core0_tcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", #set this to be 128 to align with int block_size = KNOB(KNOB_L1_SMALL_LINE_SIZE)->getValue(); + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +######################################## +# Macsim 1 +# Core 1 L1 Caches +macsim_1_core1_icache = sst.Component("macsim1_core1_icache", "memHierarchy.Cache") +macsim_1_core1_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim_1_core1_dcache = sst.Component("macsim1_core1_dcache", "memHierarchy.Cache") +macsim_1_core1_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim_1_core1_ccache = sst.Component("macsim1_core1_ccache", "memHierarchy.Cache") +macsim_1_core1_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim_1_core1_tcache = sst.Component("macsim1_core1_tcache", "memHierarchy.Cache") +macsim_1_core1_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + +######################################## +# Bus between L1 caches and memory controller +mem_bus = sst.Component("mem_bus", "memHierarchy.Bus") +mem_bus.addParams({ + "debug" : DEBUG_LINKS, + "debug_level" : DEBUG_LEVEL, + "bus_frequency" : "4 Ghz" +}) + + +######################################## +# Memory Controller +memctrl = sst.Component("memctrl", "memHierarchy.MemController") +memctrl.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + # "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") +memory.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + +######################################## +# Macsim 0 Links + +# Core 0 Links +# Macsim::core0_icache -> L1 ICache +link_macsim_0_icache = sst.Link("link_macsim_0_icache") +link_macsim_0_icache.connect( (macsim_0_icache_if, "port", "1000ps"), (macsim_0_core0_icache, "high_network_0", "1000ps") ) +# Macsim::core0_dcache -> L1 DCache +link_macsim_0_dcache = sst.Link("link_macsim_0_dcache") +link_macsim_0_dcache.connect( (macsim_0_dcache_if, "port", "1000ps"), (macsim_0_core0_dcache, "high_network_0", "1000ps") ) +# # Macsim::core0_ccache -> L1 CCache +link_macsim_0_ccache = sst.Link("link_macsim_0_ccache") +link_macsim_0_ccache.connect( (macsim_0_ccache_if, "port", "1000ps"), (macsim_0_core0_ccache, "high_network_0", "1000ps") ) +# # Macsim::core0_tcache -> L1 TCache +link_macsim_0_tcache = sst.Link("link_macsim_0_tcache") +link_macsim_0_tcache.connect( (macsim_0_tcache_if, "port", "1000ps"), (macsim_0_core0_tcache, "high_network_0", "1000ps") ) + +# Core 1 Links +# Macsim::core1_icache -> L1 ICache +link_macsim_0_icache_1 = sst.Link("link_macsim_0_icache_1") +link_macsim_0_icache_1.connect((macsim_0_icache_if_1, "port", "1000ps"), (macsim_0_core1_icache, "high_network_0", "1000ps")) +# Macsim::core1_dcache -> L1 DCache +link_macsim_0_dcache_1 = sst.Link("link_macsim_0_dcache_1") +link_macsim_0_dcache_1.connect((macsim_0_dcache_if_1, "port", "1000ps"), (macsim_0_core1_dcache, "high_network_0", "1000ps")) +# # Macsim::core1_ccache -> L1 CCache +link_macsim_0_ccache_1 = sst.Link("link_macsim_0_ccache_1") +link_macsim_0_ccache_1.connect((macsim_0_ccache_if_1, "port", "1000ps"), (macsim_0_core1_ccache, "high_network_0", "1000ps")) + # Macsim::core1_tcache -> L1 TCache +link_macsim_0_tcache_1 = sst.Link("link_macsim_0_tcache_1") +link_macsim_0_tcache_1.connect((macsim_0_tcache_if_1, "port", "1000ps"), (macsim_0_core1_tcache, "high_network_0", "1000ps")) + +# L1 I/DCache -> Bus +macsim_0_link_icache_bus = sst.Link("macsim_0_link_icache_bus") +macsim_0_link_icache_bus.connect( (macsim_0_core0_icache, "low_network_0", "50ps"), (mem_bus, "high_network_0", "50ps") ) +macsim_0_link_dcache_bus = sst.Link("macsim_0_link_dcache_bus") +macsim_0_link_dcache_bus.connect( (macsim_0_core0_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_1", "50ps") ) +macsim_0_link_ccache_bus = sst.Link("macsim_0_link_ccache_bus") +macsim_0_link_ccache_bus.connect( (macsim_0_core0_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_2", "50ps") ) +macsim_0_link_tcache_bus = sst.Link("macsim_0_link_tcache_bus") +macsim_0_link_tcache_bus.connect( (macsim_0_core0_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_3", "50ps") ) + +macsim_0_link_icache_bus_1 = sst.Link("macsim_0_link_icache_bus_1") +macsim_0_link_icache_bus_1.connect((macsim_0_core1_icache, "low_network_0", "50ps"), (mem_bus, "high_network_4", "50ps")) +macsim_0_link_dcache_bus_1 = sst.Link("macsim_0_link_dcache_bus_1") +macsim_0_link_dcache_bus_1.connect((macsim_0_core1_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_5", "50ps")) +macsim_0_link_ccache_bus_1 = sst.Link("macsim_0_link_ccache_bus_1") +macsim_0_link_ccache_bus_1.connect((macsim_0_core1_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_6", "50ps")) +macsim_0_link_tcache_bus_1 = sst.Link("macsim_0_link_tcache_bus_1") +macsim_0_link_tcache_bus_1.connect((macsim_0_core1_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_7", "50ps")) + + +######################################## +# Macsim 1 Links + +# Core 0 Links +# Macsim::core0_icache -> L1 ICache +link_macsim_1_icache = sst.Link("link_macsim_1_icache") +link_macsim_1_icache.connect( (macsim_1_icache_if, "port", "1000ps"), (macsim_1_core0_icache, "high_network_0", "1000ps") ) +# Macsim::core0_dcache -> L1 DCache +link_macsim_1_dcache = sst.Link("link_macsim_1_dcache") +link_macsim_1_dcache.connect( (macsim_1_dcache_if, "port", "1000ps"), (macsim_1_core0_dcache, "high_network_0", "1000ps") ) +# # Macsim::core0_ccache -> L1 CCache +link_macsim_1_ccache = sst.Link("link_macsim_1_ccache") +link_macsim_1_ccache.connect( (macsim_1_ccache_if, "port", "1000ps"), (macsim_1_core0_ccache, "high_network_0", "1000ps") ) +# # Macsim::core0_tcache -> L1 TCache +link_macsim_1_tcache = sst.Link("link_macsim_1_tcache") +link_macsim_1_tcache.connect( (macsim_1_tcache_if, "port", "1000ps"), (macsim_1_core0_tcache, "high_network_0", "1000ps") ) + +# Core 1 Links +# Macsim::core1_icache -> L1 ICache +link_macsim_1_icache_1 = sst.Link("link_macsim_1_icache_1") +link_macsim_1_icache_1.connect((macsim_1_icache_if_1, "port", "1000ps"), (macsim_1_core1_icache, "high_network_0", "1000ps")) +# Macsim::core1_dcache -> L1 DCache +link_macsim_1_dcache_1 = sst.Link("link_macsim_1_dcache_1") +link_macsim_1_dcache_1.connect((macsim_1_dcache_if_1, "port", "1000ps"), (macsim_1_core1_dcache, "high_network_0", "1000ps")) +# # Macsim::core1_ccache -> L1 CCache +link_macsim_1_ccache_1 = sst.Link("link_macsim_1_ccache_1") +link_macsim_1_ccache_1.connect((macsim_1_ccache_if_1, "port", "1000ps"), (macsim_1_core1_ccache, "high_network_0", "1000ps")) + # Macsim::core1_tcache -> L1 TCache +link_macsim_1_tcache_1 = sst.Link("link_macsim_1_tcache_1") +link_macsim_1_tcache_1.connect((macsim_1_tcache_if_1, "port", "1000ps"), (macsim_1_core1_tcache, "high_network_0", "1000ps")) + +# L1 I/DCache -> Bus +macsim_1_link_icache_bus = sst.Link("macsim_1_link_icache_bus") +macsim_1_link_icache_bus.connect( (macsim_1_core0_icache, "low_network_0", "50ps"), (mem_bus, "high_network_8", "50ps") ) +macsim_1_link_dcache_bus = sst.Link("macsim_1_link_dcache_bus") +macsim_1_link_dcache_bus.connect( (macsim_1_core0_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_9", "50ps") ) +macsim_1_link_ccache_bus = sst.Link("macsim_1_link_ccache_bus") +macsim_1_link_ccache_bus.connect( (macsim_1_core0_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_10", "50ps") ) +macsim_1_link_tcache_bus = sst.Link("macsim_1_link_tcache_bus") +macsim_1_link_tcache_bus.connect( (macsim_1_core0_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_11", "50ps") ) + +macsim_1_link_icache_bus_1 = sst.Link("macsim_1_link_icache_bus_1") +macsim_1_link_icache_bus_1.connect((macsim_1_core1_icache, "low_network_0", "50ps"), (mem_bus, "high_network_12", "50ps")) +macsim_1_link_dcache_bus_1 = sst.Link("macsim_1_link_dcache_bus_1") +macsim_1_link_dcache_bus_1.connect((macsim_1_core1_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_13", "50ps")) +macsim_1_link_ccache_bus_1 = sst.Link("macsim_1_link_ccache_bus_1") +macsim_1_link_ccache_bus_1.connect((macsim_1_core1_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_14", "50ps")) +macsim_1_link_tcache_bus_1 = sst.Link("macsim_1_link_tcache_bus_1") +macsim_1_link_tcache_bus_1.connect((macsim_1_core1_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_15", "50ps")) + +# Bus -> Memory +link_bus_mem = sst.Link("link_bus_mem") +link_bus_mem.connect( (mem_bus, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps")) + +######################################## +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") \ No newline at end of file diff --git a/sst-unit-test/sdl-05b-2-gpu-2-core-L1-mem-L2.py b/sst-unit-test/sdl-05b-2-gpu-2-core-L1-mem-L2.py new file mode 100644 index 000000000..72e5e5de8 --- /dev/null +++ b/sst-unit-test/sdl-05b-2-gpu-2-core-L1-mem-L2.py @@ -0,0 +1,583 @@ +################################################################################ +# Description: +# - Macsim is connected to L1 caches, followed by a bus and memory controller. +# - Macsim ports (stdInterface) are loaded as subcomponents explictly. +################################################################################ +import sst +from common import * + +# 0: None, 1: Stdout, 2: Stderr, 3: File +DEBUG_CORE = 1 +DEBUG_L1 = 1 +DEBUG_MEM = 1 + +DEBUG_LINKS = 0 +DEBUG_BUS = 0 + +DEBUG_LEVEL = 0 +VERBOSE = 0 + +######################################## +# System Parameters +MEM_SIZE_S = '512MiB' +MEM_SIZE = str2bytes(MEM_SIZE_S) +MEM_START = 0 +MEM_END = MEM_START + MEM_SIZE - 1 + + +######################################## +# Macsim 0 +macsim_0 = sst.Component("macsimComponent0", "macsimComponent.macsimComponent") +macsim_0.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list_gpu", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=2 --num_sim_large_cores=0 --num_sim_small_cores=2 --use_memhierarchy=1 --core_type=nvbit", + "frequency" : "2GHz", + "num_link": "2", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, + "nvbit_core": True, + "component_num": 0, +}) + +######################################## +# Macsim 1 +macsim_1 = sst.Component("macsimComponent1", "macsimComponent.macsimComponent") +macsim_1.addParams({ + "param_file": "params.in", + "trace_file": "trace_file_list", + "output_dir": "output_dir", + "command_line": "--num_sim_cores=2 --num_sim_large_cores=0 --num_sim_small_cores=2 --use_memhierarchy=1 --core_type=nvbit", + "frequency" : "2GHz", + "num_link": "2", + "mem_size" : MEM_SIZE, + "debug": DEBUG_CORE, + "debug_level": DEBUG_LEVEL, + "nvbit_core": True, + "component_num": 1, +}) + +######################################## +# Macsim 0 +# Core 0 interface +macsim_0_icache_if = macsim_0.setSubComponent("macsim0_core0_icache", "memHierarchy.standardInterface") +macsim_0_icache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_0_dcache_if = macsim_0.setSubComponent("macsim0_core0_dcache", "memHierarchy.standardInterface") +macsim_0_dcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_0_ccache_if = macsim_0.setSubComponent("macsim0_core0_ccache", "memHierarchy.standardInterface") +macsim_0_ccache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_0_tcache_if = macsim_0.setSubComponent("macsim0_core0_tcache", "memHierarchy.standardInterface") +macsim_0_tcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +# Core 1 Interfaces +macsim_0_icache_if_1 = macsim_0.setSubComponent("macsim0_core1_icache", "memHierarchy.standardInterface") +macsim_0_icache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_0_dcache_if_1 = macsim_0.setSubComponent("macsim0_core1_dcache", "memHierarchy.standardInterface") +macsim_0_dcache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_0_ccache_if_1 = macsim_0.setSubComponent("macsim0_core1_ccache", "memHierarchy.standardInterface") +macsim_0_ccache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_0_tcache_if_1 = macsim_0.setSubComponent("macsim0_core1_tcache", "memHierarchy.standardInterface") +macsim_0_tcache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +######################################## +# Macsim 1 +# Core 0 interface +macsim_1_icache_if = macsim_1.setSubComponent("macsim1_core0_icache", "memHierarchy.standardInterface") +macsim_1_icache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_1_dcache_if = macsim_1.setSubComponent("macsim1_core0_dcache", "memHierarchy.standardInterface") +macsim_1_dcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_1_ccache_if = macsim_1.setSubComponent("macsim1_core0_ccache", "memHierarchy.standardInterface") +macsim_1_ccache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_1_tcache_if = macsim_1.setSubComponent("macsim1_core0_tcache", "memHierarchy.standardInterface") +macsim_1_tcache_if.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + +# Core 1 Interfaces +macsim_1_icache_if_1 = macsim_1.setSubComponent("macsim1_core1_icache", "memHierarchy.standardInterface") +macsim_1_icache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_1_dcache_if_1 = macsim_1.setSubComponent("macsim1_core1_dcache", "memHierarchy.standardInterface") +macsim_1_dcache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': VERBOSE +}) +macsim_1_ccache_if_1 = macsim_1.setSubComponent("macsim1_core1_ccache", "memHierarchy.standardInterface") +macsim_1_ccache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) +macsim_1_tcache_if_1 = macsim_1.setSubComponent("macsim1_core1_tcache", "memHierarchy.standardInterface") +macsim_1_tcache_if_1.addParams({ + 'debug': DEBUG_LINKS, + 'debug_level': DEBUG_LEVEL, + 'verbose': 10 +}) + + +######################################## +# Macsim 0 +# Core 0 L1 Caches +macsim_0_core0_icache = sst.Component("macsim0_core0_icache", "memHierarchy.Cache") +macsim_0_core0_icache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim_0_core0_dcache = sst.Component("macsim0_core0_dcache", "memHierarchy.Cache") +macsim_0_core0_dcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) +# ######################################## +# # Const Caches +macsim_0_core0_ccache = sst.Component("macsim0_core0_ccache", "memHierarchy.Cache") +macsim_0_core0_ccache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim_0_core0_tcache = sst.Component("macsim0_core0_tcache", "memHierarchy.Cache") +macsim_0_core0_tcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", #set this to be 128 to align with int block_size = KNOB(KNOB_L1_SMALL_LINE_SIZE)->getValue(); + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +######################################## +# Macsim 0 +# Core 1 L1 Caches +macsim_0_core1_icache = sst.Component("macsim0_core1_icache", "memHierarchy.Cache") +macsim_0_core1_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim_0_core1_dcache = sst.Component("macsim0_core1_dcache", "memHierarchy.Cache") +macsim_0_core1_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim_0_core1_ccache = sst.Component("macsim0_core1_ccache", "memHierarchy.Cache") +macsim_0_core1_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim_0_core1_tcache = sst.Component("macsim0_core1_tcache", "memHierarchy.Cache") +macsim_0_core1_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + + + +######################################## +# Macsim 1 +# Core 0 L1 Caches +macsim_1_core0_icache = sst.Component("macsim1_core0_icache", "memHierarchy.Cache") +macsim_1_core0_icache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim_1_core0_dcache = sst.Component("macsim1_core0_dcache", "memHierarchy.Cache") +macsim_1_core0_dcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) +# ######################################## +# # Const Caches +macsim_1_core0_ccache = sst.Component("macsim1_core0_ccache", "memHierarchy.Cache") +macsim_1_core0_ccache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +macsim_1_core0_tcache = sst.Component("macsim1_core0_tcache", "memHierarchy.Cache") +macsim_1_core0_tcache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "4", + "cache_line_size" : "64", #set this to be 128 to align with int block_size = KNOB(KNOB_L1_SMALL_LINE_SIZE)->getValue(); + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "1", + "cache_size" : "2KiB" +}) + +######################################## +# Macsim 1 +# Core 1 L1 Caches +macsim_1_core1_icache = sst.Component("macsim1_core1_icache", "memHierarchy.Cache") +macsim_1_core1_icache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim_1_core1_dcache = sst.Component("macsim1_core1_dcache", "memHierarchy.Cache") +macsim_1_core1_dcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim_1_core1_ccache = sst.Component("macsim1_core1_ccache", "memHierarchy.Cache") +macsim_1_core1_ccache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +macsim_1_core1_tcache = sst.Component("macsim1_core1_tcache", "memHierarchy.Cache") +macsim_1_core1_tcache.addParams({ + "access_latency_cycles": "3", + "cache_frequency": "3.5Ghz", + "replacement_policy": "lru", + "coherence_protocol": "MSI", + "associativity": "4", + "cache_line_size": "64", + "debug": DEBUG_L1, + "debug_level": DEBUG_LEVEL, + "verbose": VERBOSE, + "L1": "1", + "cache_size": "2KiB" +}) + +######################################## +# L2 caches +gpu_l2cache = sst.Component("l2cache", "memHierarchy.Cache") +gpu_l2cache.addParams({ + "access_latency_cycles" : "8", + "cache_frequency" : "4Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MSI", + "associativity" : "8", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : VERBOSE, + "L1" : "0", + "cache_size" : "64KiB" +}) + + +######################################## +# Bus between L1 caches and memory controller +mem_bus = sst.Component("mem_bus", "memHierarchy.Bus") +mem_bus.addParams({ + "debug" : DEBUG_LINKS, + "debug_level" : DEBUG_LEVEL, + "bus_frequency" : "4 Ghz" +}) + + +######################################## +# Memory Controller +memctrl = sst.Component("memctrl", "memHierarchy.MemController") +memctrl.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : VERBOSE, + # "addr_range_start" : MEM_START, + "addr_range_end" : MEM_END, +}) +memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") +memory.addParams({ + "access_time" : "1000ns", + "mem_size" : MEM_SIZE_S +}) + +######################################## +# Macsim 0 Links + +# Core 0 Links +# Macsim::core0_icache -> L1 ICache +link_macsim_0_icache = sst.Link("link_macsim_0_icache") +link_macsim_0_icache.connect( (macsim_0_icache_if, "port", "1000ps"), (macsim_0_core0_icache, "high_network_0", "1000ps") ) +# Macsim::core0_dcache -> L1 DCache +link_macsim_0_dcache = sst.Link("link_macsim_0_dcache") +link_macsim_0_dcache.connect( (macsim_0_dcache_if, "port", "1000ps"), (macsim_0_core0_dcache, "high_network_0", "1000ps") ) +# # Macsim::core0_ccache -> L1 CCache +link_macsim_0_ccache = sst.Link("link_macsim_0_ccache") +link_macsim_0_ccache.connect( (macsim_0_ccache_if, "port", "1000ps"), (macsim_0_core0_ccache, "high_network_0", "1000ps") ) +# # Macsim::core0_tcache -> L1 TCache +link_macsim_0_tcache = sst.Link("link_macsim_0_tcache") +link_macsim_0_tcache.connect( (macsim_0_tcache_if, "port", "1000ps"), (macsim_0_core0_tcache, "high_network_0", "1000ps") ) + +# Core 1 Links +# Macsim::core1_icache -> L1 ICache +link_macsim_0_icache_1 = sst.Link("link_macsim_0_icache_1") +link_macsim_0_icache_1.connect((macsim_0_icache_if_1, "port", "1000ps"), (macsim_0_core1_icache, "high_network_0", "1000ps")) +# Macsim::core1_dcache -> L1 DCache +link_macsim_0_dcache_1 = sst.Link("link_macsim_0_dcache_1") +link_macsim_0_dcache_1.connect((macsim_0_dcache_if_1, "port", "1000ps"), (macsim_0_core1_dcache, "high_network_0", "1000ps")) +# # Macsim::core1_ccache -> L1 CCache +link_macsim_0_ccache_1 = sst.Link("link_macsim_0_ccache_1") +link_macsim_0_ccache_1.connect((macsim_0_ccache_if_1, "port", "1000ps"), (macsim_0_core1_ccache, "high_network_0", "1000ps")) + # Macsim::core1_tcache -> L1 TCache +link_macsim_0_tcache_1 = sst.Link("link_macsim_0_tcache_1") +link_macsim_0_tcache_1.connect((macsim_0_tcache_if_1, "port", "1000ps"), (macsim_0_core1_tcache, "high_network_0", "1000ps")) + +# L1 I/DCache -> Bus +macsim_0_link_icache_bus = sst.Link("macsim_0_link_icache_bus") +macsim_0_link_icache_bus.connect( (macsim_0_core0_icache, "low_network_0", "50ps"), (mem_bus, "high_network_0", "50ps") ) +macsim_0_link_dcache_bus = sst.Link("macsim_0_link_dcache_bus") +macsim_0_link_dcache_bus.connect( (macsim_0_core0_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_1", "50ps") ) +macsim_0_link_ccache_bus = sst.Link("macsim_0_link_ccache_bus") +macsim_0_link_ccache_bus.connect( (macsim_0_core0_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_2", "50ps") ) +macsim_0_link_tcache_bus = sst.Link("macsim_0_link_tcache_bus") +macsim_0_link_tcache_bus.connect( (macsim_0_core0_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_3", "50ps") ) + +macsim_0_link_icache_bus_1 = sst.Link("macsim_0_link_icache_bus_1") +macsim_0_link_icache_bus_1.connect((macsim_0_core1_icache, "low_network_0", "50ps"), (mem_bus, "high_network_4", "50ps")) +macsim_0_link_dcache_bus_1 = sst.Link("macsim_0_link_dcache_bus_1") +macsim_0_link_dcache_bus_1.connect((macsim_0_core1_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_5", "50ps")) +macsim_0_link_ccache_bus_1 = sst.Link("macsim_0_link_ccache_bus_1") +macsim_0_link_ccache_bus_1.connect((macsim_0_core1_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_6", "50ps")) +macsim_0_link_tcache_bus_1 = sst.Link("macsim_0_link_tcache_bus_1") +macsim_0_link_tcache_bus_1.connect((macsim_0_core1_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_7", "50ps")) + + +######################################## +# Macsim 1 Links + +# Core 0 Links +# Macsim::core0_icache -> L1 ICache +link_macsim_1_icache = sst.Link("link_macsim_1_icache") +link_macsim_1_icache.connect( (macsim_1_icache_if, "port", "1000ps"), (macsim_1_core0_icache, "high_network_0", "1000ps") ) +# Macsim::core0_dcache -> L1 DCache +link_macsim_1_dcache = sst.Link("link_macsim_1_dcache") +link_macsim_1_dcache.connect( (macsim_1_dcache_if, "port", "1000ps"), (macsim_1_core0_dcache, "high_network_0", "1000ps") ) +# # Macsim::core0_ccache -> L1 CCache +link_macsim_1_ccache = sst.Link("link_macsim_1_ccache") +link_macsim_1_ccache.connect( (macsim_1_ccache_if, "port", "1000ps"), (macsim_1_core0_ccache, "high_network_0", "1000ps") ) +# # Macsim::core0_tcache -> L1 TCache +link_macsim_1_tcache = sst.Link("link_macsim_1_tcache") +link_macsim_1_tcache.connect( (macsim_1_tcache_if, "port", "1000ps"), (macsim_1_core0_tcache, "high_network_0", "1000ps") ) + +# Core 1 Links +# Macsim::core1_icache -> L1 ICache +link_macsim_1_icache_1 = sst.Link("link_macsim_1_icache_1") +link_macsim_1_icache_1.connect((macsim_1_icache_if_1, "port", "1000ps"), (macsim_1_core1_icache, "high_network_0", "1000ps")) +# Macsim::core1_dcache -> L1 DCache +link_macsim_1_dcache_1 = sst.Link("link_macsim_1_dcache_1") +link_macsim_1_dcache_1.connect((macsim_1_dcache_if_1, "port", "1000ps"), (macsim_1_core1_dcache, "high_network_0", "1000ps")) +# # Macsim::core1_ccache -> L1 CCache +link_macsim_1_ccache_1 = sst.Link("link_macsim_1_ccache_1") +link_macsim_1_ccache_1.connect((macsim_1_ccache_if_1, "port", "1000ps"), (macsim_1_core1_ccache, "high_network_0", "1000ps")) + # Macsim::core1_tcache -> L1 TCache +link_macsim_1_tcache_1 = sst.Link("link_macsim_1_tcache_1") +link_macsim_1_tcache_1.connect((macsim_1_tcache_if_1, "port", "1000ps"), (macsim_1_core1_tcache, "high_network_0", "1000ps")) + +# L1 I/DCache -> Bus +macsim_1_link_icache_bus = sst.Link("macsim_1_link_icache_bus") +macsim_1_link_icache_bus.connect( (macsim_1_core0_icache, "low_network_0", "50ps"), (mem_bus, "high_network_8", "50ps") ) +macsim_1_link_dcache_bus = sst.Link("macsim_1_link_dcache_bus") +macsim_1_link_dcache_bus.connect( (macsim_1_core0_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_9", "50ps") ) +macsim_1_link_ccache_bus = sst.Link("macsim_1_link_ccache_bus") +macsim_1_link_ccache_bus.connect( (macsim_1_core0_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_10", "50ps") ) +macsim_1_link_tcache_bus = sst.Link("macsim_1_link_tcache_bus") +macsim_1_link_tcache_bus.connect( (macsim_1_core0_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_11", "50ps") ) + +macsim_1_link_icache_bus_1 = sst.Link("macsim_1_link_icache_bus_1") +macsim_1_link_icache_bus_1.connect((macsim_1_core1_icache, "low_network_0", "50ps"), (mem_bus, "high_network_12", "50ps")) +macsim_1_link_dcache_bus_1 = sst.Link("macsim_1_link_dcache_bus_1") +macsim_1_link_dcache_bus_1.connect((macsim_1_core1_dcache, "low_network_0", "50ps"), (mem_bus, "high_network_13", "50ps")) +macsim_1_link_ccache_bus_1 = sst.Link("macsim_1_link_ccache_bus_1") +macsim_1_link_ccache_bus_1.connect((macsim_1_core1_ccache, "low_network_0", "50ps"), (mem_bus, "high_network_14", "50ps")) +macsim_1_link_tcache_bus_1 = sst.Link("macsim_1_link_tcache_bus_1") +macsim_1_link_tcache_bus_1.connect((macsim_1_core1_tcache, "low_network_0", "50ps"), (mem_bus, "high_network_15", "50ps")) + +# Bus -> Memory +link_bus_L2 = sst.Link("link_bus_L2") +link_bus_L2.connect( (mem_bus, "low_network_0", "50ps"), (gpu_l2cache, "high_network_0", "50ps") ) +link_bus_mem = sst.Link("link_bus_mem") +link_bus_mem.connect( (gpu_l2cache, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) + + +######################################## +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") \ No newline at end of file diff --git a/sst-unit-test/sdl1.py b/sst-unit-test/sdl1.py index 73d8898ea..342a8bfc2 100644 --- a/sst-unit-test/sdl1.py +++ b/sst-unit-test/sdl1.py @@ -1,5 +1,12 @@ # Automatically generated by SST + import sst +import warnings +warnings.warn( + "This script uses deprecated SST components or parameters. " + "Please use sdl-xx-*.py scripts for updated examples.", + DeprecationWarning +) KB = 1024 MB = 1024*KB diff --git a/sst-unit-test/sdl2.py b/sst-unit-test/sdl2.py index cd24e5e39..45e39b64a 100644 --- a/sst-unit-test/sdl2.py +++ b/sst-unit-test/sdl2.py @@ -1,5 +1,11 @@ # Automatically generated by SST import sst +import warnings +warnings.warn( + "This script uses deprecated SST components or parameters. " + "Please use sdl-xx-*.py scripts for updated examples.", + DeprecationWarning +) KB = 1024 MB = 1024*KB diff --git a/sst-unit-test/sdl3.py b/sst-unit-test/sdl3.py index 680784eb8..486c55239 100644 --- a/sst-unit-test/sdl3.py +++ b/sst-unit-test/sdl3.py @@ -1,5 +1,11 @@ # Automatically generated by SST import sst +import warnings +warnings.warn( + "This script uses deprecated SST components or parameters. " + "Please use sdl-xx-*.py scripts for updated examples.", + DeprecationWarning +) # Define SST Program Options: sst.setProgramOption("timebase", "1ps") diff --git a/sst-unit-test/sdl4.py b/sst-unit-test/sdl4.py index 51a331759..1fbc5de57 100644 --- a/sst-unit-test/sdl4.py +++ b/sst-unit-test/sdl4.py @@ -1,5 +1,11 @@ # Automatically generated by SST import sst +import warnings +warnings.warn( + "This script uses deprecated SST components or parameters. " + "Please use sdl-xx-*.py scripts for updated examples.", + DeprecationWarning +) import os import math diff --git a/sst-unit-test/test_sstmacsim.py b/sst-unit-test/test_sstmacsim.py new file mode 100644 index 000000000..738beea8e --- /dev/null +++ b/sst-unit-test/test_sstmacsim.py @@ -0,0 +1,73 @@ +from sst_unittest import * +from sst_unittest_support import * +import threading + +################################################################################ +# Code to support a single instance module initialize, must be called in setUp method + +module_init = 0 +module_sema = threading.Semaphore() + +def initializeTestModule_SingleInstance(class_inst): + global module_init + global module_sema + + module_sema.acquire() + if module_init != 1: + try: + # Put your single instance Init Code Here + pass + except: + pass + module_init = 1 + module_sema.release() + +################################################################################ + +class TestSSTExternalElement(SSTTestCase): + + def initializeClass(self, testName): + super().initializeClass(testName) + # Put test-based setup code here. It is called before testing starts. + + def setUp(self): + super().setUp() + initializeTestModule_SingleInstance(self) + # Put test-based setup code here. It is called once before every test. + + def tearDown(self): + # Put test-based teardown code here. It is called once after every test. + super().tearDown() + + ##### + @unittest.skipIf(testing_check_get_num_ranks() > 1, "Test skipped if ranks > 1 - single component in config") + @unittest.skipIf(testing_check_get_num_threads() > 1, "Test skipped if threads > 1 - single component in config") + def test_sst_external_element_001(self): + self.sst_external_element_test_template("macsimComponent-test-001") + + ##### + def sst_external_element_test_template(self, testcase): + test_path = self.get_testsuite_dir() + outdir = self.get_test_output_run_dir() + tmpdir = self.get_test_output_tmp_dir() + + testDataFileName = "sst_external_element_{0}".format(testcase) + + sdlfile = "{0}/{1}.py".format(test_path, testcase) + reffile = "{0}/refFiles/{1}.out".format(test_path, testcase) + outfile = "{0}/{1}.out".format(outdir, testDataFileName) + errfile = "{0}/{1}.err".format(outdir, testDataFileName) + mpioutfiles = "{0}/{1}.testfile".format(outdir, testDataFileName) + + self.run_sst(sdlfile, outfile, errfile, mpi_out_files=mpioutfiles) + + testing_remove_component_warning_from_file(outfile) + + # Perform the tests + self.assertFalse(os_test_file(errfile, "-s"), "Test {0} has non-empty Error File {1}".format(testDataFileName, errfile)) + + cmp_result = testing_compare_sorted_diff(testcase, outfile, reffile) + if not cmp_result: + diffdata = testing_get_diff_data(testcase) + log_failure(diffdata) + self.assertTrue(cmp_result, "Sorted output file {0} does not match sorted reference file {1}".format(outfile, reffile)) diff --git a/sst-unit-test/trace_file_list b/sst-unit-test/trace_file_list deleted file mode 100644 index fae27d2e7..000000000 --- a/sst-unit-test/trace_file_list +++ /dev/null @@ -1,2 +0,0 @@ -1 -./traces/vectoradd/kernel_config.txt diff --git a/sst-unit-test/trace_file_list_cpu b/sst-unit-test/trace_file_list_cpu new file mode 100644 index 000000000..90588d57a --- /dev/null +++ b/sst-unit-test/trace_file_list_cpu @@ -0,0 +1,2 @@ +1 +./traces/x86/mergesort.txt \ No newline at end of file diff --git a/sst-unit-test/trace_file_list_gpu b/sst-unit-test/trace_file_list_gpu new file mode 100644 index 000000000..0e2bf8483 --- /dev/null +++ b/sst-unit-test/trace_file_list_gpu @@ -0,0 +1,2 @@ +1 +./traces/nvbit/vectormultadd/4096/kernel_config.txt \ No newline at end of file