From b020b74710a48083707f262b885cd55ac745b60c Mon Sep 17 00:00:00 2001 From: Haolan Date: Tue, 8 Jul 2025 17:16:43 +0800 Subject: [PATCH] feat: add esp32 Release-as: esp32/v1.0.0 --- esp32/FreeRTOS.go | 193 ++ esp32/FreeRTOSConfig_arch.go | 11 + esp32/adc_channel.go | 44 + esp32/adc_hal.go | 146 ++ esp32/adc_hal_common.go | 80 + esp32/adc_ll.go | 61 + esp32/adc_oneshot_hal.go | 86 + esp32/adc_share_hw_ctrl.go | 125 + esp32/adc_types.go | 127 + esp32/adc_types_private.go | 27 + esp32/aes.go | 41 + esp32/aes_hal.go | 77 + esp32/aes_ll.go | 14 + esp32/aes_types.go | 22 + esp32/apb_backup_dma.go | 11 + esp32/apb_ctrl_reg.go | 234 ++ esp32/apb_ctrl_struct.go | 338 +++ esp32/apb_saradc_reg.go | 232 ++ esp32/apb_saradc_struct.go | 298 +++ esp32/apm_types.go | 14 + esp32/assert.go | 12 + esp32/assist_debug_reg.go | 457 ++++ esp32/assist_debug_struct.go | 206 ++ esp32/atomic.go | 3 + esp32/bb_reg.go | 12 + esp32/bigint.go | 27 + esp32/boot_mode.go | 5 + esp32/brownout.go | 9 + esp32/brownout_hal.go | 23 + esp32/brownout_ll.go | 3 + esp32/cache.go | 1284 ++++++++++ esp32/cache_err_int.go | 46 + esp32/cache_hal.go | 144 ++ esp32/cache_ll.go | 9 + esp32/cache_types.go | 25 + esp32/cacheasm.go | 3 + esp32/cacheattrasm.go | 8 + esp32/cam_ctlr_types.go | 30 + esp32/cam_hal.go | 72 + esp32/cam_types.go | 11 + esp32/cc.go | 18 + esp32/cdc_acm.go | 220 ++ esp32/check.go | 3 + esp32/chip_revision.go | 3 + esp32/chip_usb_dw_wrapper.go | 21 + esp32/clk_ctrl_os.go | 36 + esp32/clk_tree_defs.go | 254 ++ esp32/clk_tree_hal.go | 67 + esp32/clk_tree_ll.go | 28 + esp32/clkout_channel.go | 17 + esp32/color_hal.go | 18 + esp32/color_types.go | 151 ++ esp32/core-isa.go | 434 ++++ esp32/core-macros.go | 3 + esp32/core-matmap.go | 120 + esp32/core.go | 150 ++ esp32/coreasm.go | 5 + esp32/corebits.go | 108 + esp32/cpio.go | 129 + esp32/cpu_hal.go | 14 + esp32/crc.go | 90 + esp32/critical_section.go | 7 + esp32/crosscore_int.go | 70 + esp32/dac_types.go | 32 + esp32/debug_probe.go | 152 ++ esp32/debug_probe_types.go | 17 + esp32/dedic_gpio_ll.go | 3 + esp32/dedic_gpio_periph.go | 14 + esp32/defs.go | 3 + esp32/deprecated_definitions.go | 3 + esp32/digital_signature.go | 111 + esp32/dma2d.go | 390 +++ esp32/dma2d_hal.go | 49 + esp32/dma2d_types.go | 102 + esp32/dma_types.go | 37 + esp32/dport_access.go | 16 + esp32/dport_reg.go | 3 + esp32/ds_hal.go | 68 + esp32/ds_ll.go | 3 + esp32/ds_types.go | 23 + esp32/dw_gdma.go | 420 ++++ esp32/dw_gdma_hal.go | 45 + esp32/dw_gdma_types.go | 80 + esp32/ecc_hal.go | 101 + esp32/ecc_types.go | 36 + esp32/ecdsa_hal.go | 61 + esp32/ecdsa_types.go | 32 + esp32/efuse.go | 349 +++ esp32/efuse_defs.go | 14 + esp32/efuse_hal.go | 54 + esp32/efuse_reg.go | 331 +++ esp32/efuse_struct.go | 1054 ++++++++ esp32/eh_frame_parser.go | 16 + esp32/eri.go | 16 + esp32/esp_assert.go | 3 + esp32/esp_async_memcpy.go | 99 + esp32/esp_attr.go | 3 + esp32/esp_bit_defs.go | 36 + esp32/esp_check.go | 3 + esp32/esp_chip_info.go | 41 + esp32/esp_clk.go | 91 + esp32/esp_clk_tree.go | 36 + esp32/esp_clk_tree_common.go | 86 + esp32/esp_clk_utils.go | 24 + esp32/esp_compiler.go | 3 + esp32/esp_cpu.go | 163 ++ esp32/esp_cpu_internal.go | 5 + esp32/esp_cpu_utils.go | 3 + esp32/esp_crypto_lock.go | 63 + esp32/esp_crypto_lock_internal.go | 3 + esp32/esp_debug_helpers.go | 126 + esp32/esp_dma_utils.go | 181 ++ esp32/esp_dpa_protection.go | 36 + esp32/esp_ds.go | 188 ++ esp32/esp_ds_err.go | 3 + esp32/esp_err.go | 77 + esp32/esp_etm.go | 154 ++ esp32/esp_expression_with_stack.go | 35 + esp32/esp_fault.go | 3 + esp32/esp_flash_err.go | 11 + esp32/esp_freertos_hooks.go | 111 + esp32/esp_gpio_reserve.go | 35 + esp32/esp_heap_caps.go | 446 ++++ esp32/esp_heap_caps_init.go | 102 + esp32/esp_heap_trace.go | 194 ++ esp32/esp_hmac.go | 80 + esp32/esp_idf_version.go | 23 + esp32/esp_int_wdt.go | 23 + esp32/esp_interface.go | 16 + esp32/esp_intr_alloc.go | 248 ++ esp32/esp_intr_types.go | 21 + esp32/esp_ipc.go | 79 + esp32/esp_ipc_isr.go | 120 + esp32/esp_ipc_isr_port.go | 26 + esp32/esp_ldo_regulator.go | 83 + esp32/esp_log.go | 49 + esp32/esp_log_buffer.go | 57 + esp32/esp_log_color.go | 32 + esp32/esp_log_level.go | 54 + esp32/esp_log_timestamp.go | 48 + esp32/esp_mac.go | 174 ++ esp32/esp_macros.go | 3 + esp32/esp_memory_utils.go | 46 + esp32/esp_memprot.go | 198 ++ esp32/esp_memprot_err.go | 3 + esp32/esp_memprot_internal.go | 250 ++ esp32/esp_memprot_types.go | 23 + esp32/esp_modem_clock.go | 97 + esp32/esp_pmu.go | 14 + esp32/esp_random.go | 36 + esp32/esp_rom_caps.go | 3 + esp32/esp_rom_crc.go | 72 + esp32/esp_rom_efuse.go | 60 + esp32/esp_rom_gpio.go | 73 + esp32/esp_rom_lldesc.go | 19 + esp32/esp_rom_md5.go | 49 + esp32/esp_rom_multi_heap.go | 3 + esp32/esp_rom_regi2c.go | 54 + esp32/esp_rom_spiflash.go | 385 +++ esp32/esp_rom_spiflash_defs.go | 5 + esp32/esp_rom_sys.go | 126 + esp32/esp_rom_tlsf.go | 34 + esp32/esp_rom_uart.go | 132 + esp32/esp_sleep.go | 656 +++++ esp32/esp_sleep_internal.go | 101 + esp32/esp_system.go | 111 + esp32/esp_systick_etm.go | 20 + esp32/esp_task.go | 3 + esp32/esp_task_wdt.go | 244 ++ esp32/esp_task_wdt_impl.go | 85 + esp32/esp_types.go | 3 + esp32/esp_wake_stub.go | 47 + esp32/esp_xt_wdt.go | 55 + esp32/eth_types.go | 53 + esp32/etm_hal.go | 34 + esp32/etm_interface.go | 20 + esp32/ets_sys.go | 396 +++ esp32/event_groups.go | 496 ++++ esp32/ext_mem_defs.go | 31 + esp32/extmem_reg.go | 514 ++++ esp32/extmem_struct.go | 394 +++ esp32/extreg.go | 5 + esp32/fe_reg.go | 12 + esp32/freertos_autogen_link.go | 7 + esp32/freertos_debug.go | 97 + esp32/freertos_idf_additions_priv.go | 111 + esp32/freertos_tasks_c_additions.go | 30 + esp32/freertos_test_utils.go | 23 + esp32/gdma.go | 407 +++ esp32/gdma_channel.go | 3 + esp32/gdma_hal.go | 120 + esp32/gdma_hal_ahb.go | 73 + esp32/gdma_hal_axi.go | 73 + esp32/gdma_link.go | 174 ++ esp32/gdma_ll.go | 15 + esp32/gdma_periph.go | 16 + esp32/gdma_reg.go | 1772 +++++++++++++ esp32/gdma_sleep_retention.go | 28 + esp32/gdma_struct.go | 150 ++ esp32/gdma_types.go | 45 + esp32/glitch_filter_types.go | 5 + esp32/go.mod | 5 + esp32/go.sum | 2 + esp32/gpio.go | 189 ++ esp32/gpio_hal.go | 46 + esp32/gpio_ll.go | 3 + esp32/gpio_num.go | 58 + esp32/gpio_pins.go | 3 + esp32/gpio_reg.go | 3420 ++++++++++++++++++++++++++ esp32/gpio_sd_reg.go | 61 + esp32/gpio_sd_struct.go | 21 + esp32/gpio_sig_map.go | 445 ++++ esp32/gpio_struct.go | 139 ++ esp32/gpio_types.go | 70 + esp32/hal.go | 747 ++++++ esp32/hal_utils.go | 116 + esp32/heap_memory_layout.go | 73 + esp32/hinf_reg.go | 88 + esp32/hinf_struct.go | 82 + esp32/hmac.go | 50 + esp32/hmac_hal.go | 82 + esp32/hmac_ll.go | 10 + esp32/hmac_types.go | 15 + esp32/host_reg.go | 672 +++++ esp32/host_struct.go | 216 ++ esp32/hw_stack_guard.go | 26 + esp32/hwcrypto_reg.go | 10 + esp32/i2c_hal.go | 174 ++ esp32/i2c_ll.go | 55 + esp32/i2c_periph.go | 15 + esp32/i2c_reg.go | 166 ++ esp32/i2c_struct.go | 267 ++ esp32/i2c_types.go | 101 + esp32/i2s_hal.go | 202 ++ esp32/i2s_ll.go | 7 + esp32/i2s_periph.go | 23 + esp32/i2s_reg.go | 371 +++ esp32/i2s_struct.go | 87 + esp32/i2s_types.go | 144 ++ esp32/idf_additions.go | 275 +++ esp32/idmaasm.go | 3 + esp32/ieee802154_periph.go | 11 + esp32/image_process.go | 33 + esp32/interrupt_controller_hal.go | 31 + esp32/interrupt_core0_reg.go | 318 +++ esp32/interrupt_core0_struct.go | 724 ++++++ esp32/interrupt_core1_reg.go | 318 +++ esp32/interrupt_core1_struct.go | 1236 ++++++++++ esp32/interrupt_reg.go | 3 + esp32/interrupt_struct.go | 8 + esp32/interrupts.go | 110 + esp32/intr_types.go | 5 + esp32/inttypes_ext.go | 5 + esp32/io_mux.go | 45 + esp32/io_mux_reg.go | 213 ++ esp32/isp_hal.go | 260 ++ esp32/isp_types.go | 239 ++ esp32/jpeg_defs.go | 64 + esp32/jpeg_hal.go | 57 + esp32/jpeg_types.go | 54 + esp32/key_mgr_types.go | 92 + esp32/lcd_cam_reg.go | 131 + esp32/lcd_cam_struct.go | 179 ++ esp32/lcd_hal.go | 41 + esp32/lcd_ll.go | 15 + esp32/lcd_periph.go | 29 + esp32/lcd_types.go | 69 + esp32/ldo_types.go | 15 + esp32/ledc_hal.go | 146 ++ esp32/ledc_ll.go | 3 + esp32/ledc_periph.go | 13 + esp32/ledc_reg.go | 536 ++++ esp32/ledc_struct.go | 65 + esp32/ledc_types.go | 98 + esp32/list.go | 116 + esp32/llcppg.cfg | 674 +++++ esp32/llcppg.pub | 1544 ++++++++++++ esp32/lldesc.go | 75 + esp32/llpkg.cfg | 8 + esp32/log.go | 3 + esp32/log_level.go | 35 + esp32/log_lock.go | 12 + esp32/log_timestamp.go | 47 + esp32/log_util.go | 63 + esp32/lp_i2s_hal.go | 27 + esp32/mcpwm_hal.go | 74 + esp32/mcpwm_ll.go | 22 + esp32/mcpwm_periph.go | 27 + esp32/mcpwm_reg.go | 461 ++++ esp32/mcpwm_struct.go | 315 +++ esp32/mcpwm_types.go | 74 + esp32/memprot.go | 658 +++++ esp32/memprot_defs.go | 39 + esp32/memprot_ll.go | 3 + esp32/memprot_types.go | 40 + esp32/message_buffer.go | 5 + esp32/miniz.go | 320 +++ esp32/mipi_csi_hal.go | 49 + esp32/mipi_csi_periph.go | 16 + esp32/mipi_csi_share_hw_ctrl.go | 41 + esp32/mipi_csi_types.go | 8 + esp32/mipi_dsi_hal.go | 202 ++ esp32/mipi_dsi_periph.go | 16 + esp32/mipi_dsi_types.go | 50 + esp32/misc.go | 3 + esp32/mmu.go | 6 + esp32/mmu_hal.go | 119 + esp32/mmu_ll.go | 3 + esp32/mmu_types.go | 46 + esp32/modem_clock_types.go | 35 + esp32/mpi_hal.go | 142 ++ esp32/mpi_ll.go | 3 + esp32/mpi_types.go | 23 + esp32/mpu_caps.go | 8 + esp32/mpu_hal.go | 16 + esp32/mpu_prototypes.go | 347 +++ esp32/mpu_syscall_numbers.go | 75 + esp32/mpu_types.go | 15 + esp32/mpu_wrappers.go | 3 + esp32/mpuasm.go | 3 + esp32/mspi_timing_config.go | 29 + esp32/mspi_timing_tuning.go | 45 + esp32/mspi_timing_tuning_ll.go | 22 + esp32/mspi_timing_types.go | 13 + esp32/multi_heap.go | 225 ++ esp32/mwdt_ll.go | 18 + esp32/nrx_reg.go | 20 + esp32/opi_flash.go | 290 +++ esp32/panic_internal.go | 75 + esp32/panic_reason.go | 13 + esp32/parlio_hal.go | 34 + esp32/parlio_types.go | 25 + esp32/pcnt_hal.go | 27 + esp32/pcnt_ll.go | 20 + esp32/pcnt_periph.go | 19 + esp32/pcnt_reg.go | 134 + esp32/pcnt_struct.go | 115 + esp32/pcnt_types.go | 32 + esp32/peri_backup_reg.go | 63 + esp32/peri_backup_struct.go | 86 + esp32/periph_ctrl.go | 105 + esp32/periph_defs.go | 53 + esp32/pmu_types.go | 32 + esp32/port_systick.go | 9 + esp32/portable.go | 96 + esp32/portbenchmark.go | 3 + esp32/portmacro.go | 295 +++ esp32/portmacro_idf.go | 9 + esp32/ppa_hal.go | 34 + esp32/ppa_types.go | 83 + esp32/projdefs.go | 46 + esp32/psdet_types.go | 13 + esp32/psram_ctrlr_ll.go | 16 + esp32/psram_types.go | 13 + esp32/queue.go | 763 ++++++ esp32/reent.go | 11 + esp32/reg_base.go | 63 + esp32/regi2c_bbpll.go | 123 + esp32/regi2c_brownout.go | 9 + esp32/regi2c_ctrl.go | 46 + esp32/regi2c_defs.go | 9 + esp32/regi2c_dig_reg.go | 39 + esp32/regi2c_lp_bias.go | 10 + esp32/regi2c_saradc.go | 48 + esp32/regi2c_ulp.go | 15 + esp32/reset_reasons.go | 35 + esp32/rmt_hal.go | 54 + esp32/rmt_ll.go | 20 + esp32/rmt_periph.go | 14 + esp32/rmt_reg.go | 356 +++ esp32/rmt_struct.go | 190 ++ esp32/rmt_types.go | 16 + esp32/rom_layout.go | 58 + esp32/rsa_pss.go | 27 + esp32/rtc.go | 853 +++++++ esp32/rtc_clk.go | 47 + esp32/rtc_cntl_ll.go | 3 + esp32/rtc_cntl_reg.go | 1326 ++++++++++ esp32/rtc_cntl_struct.go | 269 ++ esp32/rtc_ctrl.go | 61 + esp32/rtc_hal.go | 44 + esp32/rtc_i2c_reg.go | 103 + esp32/rtc_i2c_struct.go | 158 ++ esp32/rtc_io_channel.go | 48 + esp32/rtc_io_hal.go | 46 + esp32/rtc_io_ll.go | 30 + esp32/rtc_io_periph.go | 30 + esp32/rtc_io_reg.go | 772 ++++++ esp32/rtc_io_struct.go | 150 ++ esp32/rtc_io_types.go | 17 + esp32/rwdt_ll.go | 20 + esp32/sar_ctrl_ll.go | 16 + esp32/sar_periph_ctrl.go | 98 + esp32/sd_types.go | 14 + esp32/sdio_slave_periph.go | 18 + esp32/sdio_slave_types.go | 36 + esp32/sdm_hal.go | 26 + esp32/sdm_ll.go | 3 + esp32/sdm_periph.go | 12 + esp32/sdm_types.go | 5 + esp32/sdmmc_hal.go | 22 + esp32/sdmmc_ll.go | 17 + esp32/sdmmc_periph.go | 27 + esp32/sdmmc_reg.go | 3 + esp32/sdmmc_struct.go | 134 + esp32/secure_boot.go | 75 + esp32/semphr.go | 5 + esp32/sens_reg.go | 601 +++++ esp32/sensitive_reg.go | 2046 +++++++++++++++ esp32/sensitive_struct.go | 1418 +++++++++++ esp32/sha.go | 63 + esp32/sha_hal.go | 65 + esp32/sha_ll.go | 3 + esp32/sha_types.go | 5 + esp32/sleep_clock.go | 29 + esp32/sleep_console.go | 21 + esp32/sleep_cpu.go | 59 + esp32/sleep_event.go | 84 + esp32/sleep_gpio.go | 9 + esp32/sleep_modem.go | 105 + esp32/sleep_sys_periph.go | 14 + esp32/soc.go | 52 + esp32/soc_caps.go | 175 ++ esp32/soc_hal.go | 3 + esp32/soc_memprot_types.go | 64 + esp32/soc_ulp.go | 3 + esp32/specreg.go | 81 + esp32/spi_hal.go | 331 +++ esp32/spi_ll.go | 49 + esp32/spi_mem_reg.go | 708 ++++++ esp32/spi_mem_struct.go | 337 +++ esp32/spi_periph.go | 44 + esp32/spi_pins.go | 35 + esp32/spi_reg.go | 554 +++++ esp32/spi_share_hw_ctrl.go | 370 +++ esp32/spi_slave_hal.go | 160 ++ esp32/spi_slave_hd_hal.go | 292 +++ esp32/spi_struct.go | 98 + esp32/spi_types.go | 61 + esp32/spimem_flash_ll.go | 3 + esp32/spinlock.go | 16 + esp32/stack_macros.go | 5 + esp32/startup_internal.go | 25 + esp32/stream_buffer.go | 579 +++++ esp32/syscon_reg.go | 247 ++ esp32/syscon_struct.go | 338 +++ esp32/system.go | 85 + esp32/system_internal.go | 78 + esp32/system_reg.go | 361 +++ esp32/system_struct.go | 1114 +++++++++ esp32/systimer.go | 30 + esp32/systimer_hal.go | 150 ++ esp32/systimer_ll.go | 3 + esp32/systimer_reg.go | 152 ++ esp32/systimer_struct.go | 186 ++ esp32/systimer_types.go | 21 + esp32/task.go | 2179 ++++++++++++++++ esp32/temperature_sensor_ll.go | 3 + esp32/temperature_sensor_periph.go | 14 + esp32/temperature_sensor_types.go | 22 + esp32/tie-asm.go | 19 + esp32/tie.go | 41 + esp32/timer_group_reg.go | 73 + esp32/timer_group_struct.go | 253 ++ esp32/timer_hal.go | 58 + esp32/timer_ll.go | 3 + esp32/timer_periph.go | 13 + esp32/timer_types.go | 14 + esp32/timers.go | 604 +++++ esp32/tjpgd.go | 82 + esp32/touch_channel.go | 5 + esp32/touch_sensor_channel.go | 18 + esp32/touch_sensor_hal.go | 160 ++ esp32/touch_sensor_ll.go | 9 + esp32/touch_sensor_pins.go | 3 + esp32/touch_sensor_types.go | 221 ++ esp32/tracemem_config.go | 6 + esp32/trax.go | 69 + esp32/traxreg.go | 76 + esp32/twai_hal.go | 121 + esp32/twai_ll.go | 19 + esp32/twai_periph.go | 18 + esp32/twai_struct.go | 62 + esp32/twai_types.go | 68 + esp32/uart.go | 317 +++ esp32/uart_channel.go | 12 + esp32/uart_hal.go | 395 +++ esp32/uart_ll.go | 31 + esp32/uart_periph.go | 18 + esp32/uart_pins.go | 12 + esp32/uart_reg.go | 187 ++ esp32/uart_share_hw_ctrl.go | 3 + esp32/uart_struct.go | 313 +++ esp32/uart_types.go | 102 + esp32/uhci_ll.go | 15 + esp32/uhci_reg.go | 265 ++ esp32/uhci_struct.go | 69 + esp32/uhci_types.go | 31 + esp32/usb_cdc.go | 116 + esp32/usb_console.go | 86 + esp32/usb_dc.go | 394 +++ esp32/usb_descriptor.go | 15 + esp32/usb_device.go | 311 +++ esp32/usb_dfu.go | 99 + esp32/usb_dwc_cfg.go | 54 + esp32/usb_dwc_hal.go | 347 +++ esp32/usb_dwc_ll.go | 26 + esp32/usb_dwc_periph.go | 114 + esp32/usb_dwc_struct.go | 408 +++ esp32/usb_dwc_types.go | 32 + esp32/usb_os_glue.go | 18 + esp32/usb_periph.go | 23 + esp32/usb_persist.go | 17 + esp32/usb_phy_types.go | 42 + esp32/usb_pins.go | 12 + esp32/usb_reg.go | 2428 ++++++++++++++++++ esp32/usb_serial_jtag_hal.go | 30 + esp32/usb_serial_jtag_ll.go | 19 + esp32/usb_serial_jtag_reg.go | 251 ++ esp32/usb_serial_jtag_struct.go | 81 + esp32/usb_serial_jtag_types.go | 17 + esp32/usb_struct.go | 101 + esp32/usb_wrap_hal.go | 38 + esp32/usb_wrap_ll.go | 5 + esp32/usb_wrap_reg.go | 67 + esp32/usb_wrap_struct.go | 291 +++ esp32/usb_wrap_types.go | 36 + esp32/wait_for_event.go | 31 + esp32/wdev_reg.go | 5 + esp32/wdt_hal.go | 167 ++ esp32/wdt_periph.go | 5 + esp32/wdt_types.go | 48 + esp32/world_controller_reg.go | 150 ++ esp32/world_controller_struct.go | 814 ++++++ esp32/xdm-regs.go | 262 ++ esp32/xt_instr_macros.go | 7 + esp32/xt_perf_consts.go | 159 ++ esp32/xt_trax.go | 42 + esp32/xt_wdt_hal.go | 51 + esp32/xt_wdt_ll.go | 75 + esp32/xtensa-debug-module.go | 24 + esp32/xtensa-libdb-macros.go | 7 + esp32/xtensa-versions.go | 292 +++ esp32/xtensa-xer.go | 30 + esp32/xtensa_api.go | 85 + esp32/xtensa_config.go | 8 + esp32/xtensa_context.go | 108 + esp32/xtensa_rtos.go | 13 + esp32/xtensa_timer.go | 8 + esp32/xtruntime-core-state.go | 54 + esp32/xtruntime-frames.go | 57 + esp32/xtruntime.go | 99 + 552 files changed, 75278 insertions(+) create mode 100644 esp32/FreeRTOS.go create mode 100644 esp32/FreeRTOSConfig_arch.go create mode 100644 esp32/adc_channel.go create mode 100644 esp32/adc_hal.go create mode 100644 esp32/adc_hal_common.go create mode 100644 esp32/adc_ll.go create mode 100644 esp32/adc_oneshot_hal.go create mode 100644 esp32/adc_share_hw_ctrl.go create mode 100644 esp32/adc_types.go create mode 100644 esp32/adc_types_private.go create mode 100644 esp32/aes.go create mode 100644 esp32/aes_hal.go create mode 100644 esp32/aes_ll.go create mode 100644 esp32/aes_types.go create mode 100644 esp32/apb_backup_dma.go create mode 100644 esp32/apb_ctrl_reg.go create mode 100644 esp32/apb_ctrl_struct.go create mode 100644 esp32/apb_saradc_reg.go create mode 100644 esp32/apb_saradc_struct.go create mode 100644 esp32/apm_types.go create mode 100644 esp32/assert.go create mode 100644 esp32/assist_debug_reg.go create mode 100644 esp32/assist_debug_struct.go create mode 100644 esp32/atomic.go create mode 100644 esp32/bb_reg.go create mode 100644 esp32/bigint.go create mode 100644 esp32/boot_mode.go create mode 100644 esp32/brownout.go create mode 100644 esp32/brownout_hal.go create mode 100644 esp32/brownout_ll.go create mode 100644 esp32/cache.go create mode 100644 esp32/cache_err_int.go create mode 100644 esp32/cache_hal.go create mode 100644 esp32/cache_ll.go create mode 100644 esp32/cache_types.go create mode 100644 esp32/cacheasm.go create mode 100644 esp32/cacheattrasm.go create mode 100644 esp32/cam_ctlr_types.go create mode 100644 esp32/cam_hal.go create mode 100644 esp32/cam_types.go create mode 100644 esp32/cc.go create mode 100644 esp32/cdc_acm.go create mode 100644 esp32/check.go create mode 100644 esp32/chip_revision.go create mode 100644 esp32/chip_usb_dw_wrapper.go create mode 100644 esp32/clk_ctrl_os.go create mode 100644 esp32/clk_tree_defs.go create mode 100644 esp32/clk_tree_hal.go create mode 100644 esp32/clk_tree_ll.go create mode 100644 esp32/clkout_channel.go create mode 100644 esp32/color_hal.go create mode 100644 esp32/color_types.go create mode 100644 esp32/core-isa.go create mode 100644 esp32/core-macros.go create mode 100644 esp32/core-matmap.go create mode 100644 esp32/core.go create mode 100644 esp32/coreasm.go create mode 100644 esp32/corebits.go create mode 100644 esp32/cpio.go create mode 100644 esp32/cpu_hal.go create mode 100644 esp32/crc.go create mode 100644 esp32/critical_section.go create mode 100644 esp32/crosscore_int.go create mode 100644 esp32/dac_types.go create mode 100644 esp32/debug_probe.go create mode 100644 esp32/debug_probe_types.go create mode 100644 esp32/dedic_gpio_ll.go create mode 100644 esp32/dedic_gpio_periph.go create mode 100644 esp32/defs.go create mode 100644 esp32/deprecated_definitions.go create mode 100644 esp32/digital_signature.go create mode 100644 esp32/dma2d.go create mode 100644 esp32/dma2d_hal.go create mode 100644 esp32/dma2d_types.go create mode 100644 esp32/dma_types.go create mode 100644 esp32/dport_access.go create mode 100644 esp32/dport_reg.go create mode 100644 esp32/ds_hal.go create mode 100644 esp32/ds_ll.go create mode 100644 esp32/ds_types.go create mode 100644 esp32/dw_gdma.go create mode 100644 esp32/dw_gdma_hal.go create mode 100644 esp32/dw_gdma_types.go create mode 100644 esp32/ecc_hal.go create mode 100644 esp32/ecc_types.go create mode 100644 esp32/ecdsa_hal.go create mode 100644 esp32/ecdsa_types.go create mode 100644 esp32/efuse.go create mode 100644 esp32/efuse_defs.go create mode 100644 esp32/efuse_hal.go create mode 100644 esp32/efuse_reg.go create mode 100644 esp32/efuse_struct.go create mode 100644 esp32/eh_frame_parser.go create mode 100644 esp32/eri.go create mode 100644 esp32/esp_assert.go create mode 100644 esp32/esp_async_memcpy.go create mode 100644 esp32/esp_attr.go create mode 100644 esp32/esp_bit_defs.go create mode 100644 esp32/esp_check.go create mode 100644 esp32/esp_chip_info.go create mode 100644 esp32/esp_clk.go create mode 100644 esp32/esp_clk_tree.go create mode 100644 esp32/esp_clk_tree_common.go create mode 100644 esp32/esp_clk_utils.go create mode 100644 esp32/esp_compiler.go create mode 100644 esp32/esp_cpu.go create mode 100644 esp32/esp_cpu_internal.go create mode 100644 esp32/esp_cpu_utils.go create mode 100644 esp32/esp_crypto_lock.go create mode 100644 esp32/esp_crypto_lock_internal.go create mode 100644 esp32/esp_debug_helpers.go create mode 100644 esp32/esp_dma_utils.go create mode 100644 esp32/esp_dpa_protection.go create mode 100644 esp32/esp_ds.go create mode 100644 esp32/esp_ds_err.go create mode 100644 esp32/esp_err.go create mode 100644 esp32/esp_etm.go create mode 100644 esp32/esp_expression_with_stack.go create mode 100644 esp32/esp_fault.go create mode 100644 esp32/esp_flash_err.go create mode 100644 esp32/esp_freertos_hooks.go create mode 100644 esp32/esp_gpio_reserve.go create mode 100644 esp32/esp_heap_caps.go create mode 100644 esp32/esp_heap_caps_init.go create mode 100644 esp32/esp_heap_trace.go create mode 100644 esp32/esp_hmac.go create mode 100644 esp32/esp_idf_version.go create mode 100644 esp32/esp_int_wdt.go create mode 100644 esp32/esp_interface.go create mode 100644 esp32/esp_intr_alloc.go create mode 100644 esp32/esp_intr_types.go create mode 100644 esp32/esp_ipc.go create mode 100644 esp32/esp_ipc_isr.go create mode 100644 esp32/esp_ipc_isr_port.go create mode 100644 esp32/esp_ldo_regulator.go create mode 100644 esp32/esp_log.go create mode 100644 esp32/esp_log_buffer.go create mode 100644 esp32/esp_log_color.go create mode 100644 esp32/esp_log_level.go create mode 100644 esp32/esp_log_timestamp.go create mode 100644 esp32/esp_mac.go create mode 100644 esp32/esp_macros.go create mode 100644 esp32/esp_memory_utils.go create mode 100644 esp32/esp_memprot.go create mode 100644 esp32/esp_memprot_err.go create mode 100644 esp32/esp_memprot_internal.go create mode 100644 esp32/esp_memprot_types.go create mode 100644 esp32/esp_modem_clock.go create mode 100644 esp32/esp_pmu.go create mode 100644 esp32/esp_random.go create mode 100644 esp32/esp_rom_caps.go create mode 100644 esp32/esp_rom_crc.go create mode 100644 esp32/esp_rom_efuse.go create mode 100644 esp32/esp_rom_gpio.go create mode 100644 esp32/esp_rom_lldesc.go create mode 100644 esp32/esp_rom_md5.go create mode 100644 esp32/esp_rom_multi_heap.go create mode 100644 esp32/esp_rom_regi2c.go create mode 100644 esp32/esp_rom_spiflash.go create mode 100644 esp32/esp_rom_spiflash_defs.go create mode 100644 esp32/esp_rom_sys.go create mode 100644 esp32/esp_rom_tlsf.go create mode 100644 esp32/esp_rom_uart.go create mode 100644 esp32/esp_sleep.go create mode 100644 esp32/esp_sleep_internal.go create mode 100644 esp32/esp_system.go create mode 100644 esp32/esp_systick_etm.go create mode 100644 esp32/esp_task.go create mode 100644 esp32/esp_task_wdt.go create mode 100644 esp32/esp_task_wdt_impl.go create mode 100644 esp32/esp_types.go create mode 100644 esp32/esp_wake_stub.go create mode 100644 esp32/esp_xt_wdt.go create mode 100644 esp32/eth_types.go create mode 100644 esp32/etm_hal.go create mode 100644 esp32/etm_interface.go create mode 100644 esp32/ets_sys.go create mode 100644 esp32/event_groups.go create mode 100644 esp32/ext_mem_defs.go create mode 100644 esp32/extmem_reg.go create mode 100644 esp32/extmem_struct.go create mode 100644 esp32/extreg.go create mode 100644 esp32/fe_reg.go create mode 100644 esp32/freertos_autogen_link.go create mode 100644 esp32/freertos_debug.go create mode 100644 esp32/freertos_idf_additions_priv.go create mode 100644 esp32/freertos_tasks_c_additions.go create mode 100644 esp32/freertos_test_utils.go create mode 100644 esp32/gdma.go create mode 100644 esp32/gdma_channel.go create mode 100644 esp32/gdma_hal.go create mode 100644 esp32/gdma_hal_ahb.go create mode 100644 esp32/gdma_hal_axi.go create mode 100644 esp32/gdma_link.go create mode 100644 esp32/gdma_ll.go create mode 100644 esp32/gdma_periph.go create mode 100644 esp32/gdma_reg.go create mode 100644 esp32/gdma_sleep_retention.go create mode 100644 esp32/gdma_struct.go create mode 100644 esp32/gdma_types.go create mode 100644 esp32/glitch_filter_types.go create mode 100644 esp32/go.mod create mode 100644 esp32/go.sum create mode 100644 esp32/gpio.go create mode 100644 esp32/gpio_hal.go create mode 100644 esp32/gpio_ll.go create mode 100644 esp32/gpio_num.go create mode 100644 esp32/gpio_pins.go create mode 100644 esp32/gpio_reg.go create mode 100644 esp32/gpio_sd_reg.go create mode 100644 esp32/gpio_sd_struct.go create mode 100644 esp32/gpio_sig_map.go create mode 100644 esp32/gpio_struct.go create mode 100644 esp32/gpio_types.go create mode 100644 esp32/hal.go create mode 100644 esp32/hal_utils.go create mode 100644 esp32/heap_memory_layout.go create mode 100644 esp32/hinf_reg.go create mode 100644 esp32/hinf_struct.go create mode 100644 esp32/hmac.go create mode 100644 esp32/hmac_hal.go create mode 100644 esp32/hmac_ll.go create mode 100644 esp32/hmac_types.go create mode 100644 esp32/host_reg.go create mode 100644 esp32/host_struct.go create mode 100644 esp32/hw_stack_guard.go create mode 100644 esp32/hwcrypto_reg.go create mode 100644 esp32/i2c_hal.go create mode 100644 esp32/i2c_ll.go create mode 100644 esp32/i2c_periph.go create mode 100644 esp32/i2c_reg.go create mode 100644 esp32/i2c_struct.go create mode 100644 esp32/i2c_types.go create mode 100644 esp32/i2s_hal.go create mode 100644 esp32/i2s_ll.go create mode 100644 esp32/i2s_periph.go create mode 100644 esp32/i2s_reg.go create mode 100644 esp32/i2s_struct.go create mode 100644 esp32/i2s_types.go create mode 100644 esp32/idf_additions.go create mode 100644 esp32/idmaasm.go create mode 100644 esp32/ieee802154_periph.go create mode 100644 esp32/image_process.go create mode 100644 esp32/interrupt_controller_hal.go create mode 100644 esp32/interrupt_core0_reg.go create mode 100644 esp32/interrupt_core0_struct.go create mode 100644 esp32/interrupt_core1_reg.go create mode 100644 esp32/interrupt_core1_struct.go create mode 100644 esp32/interrupt_reg.go create mode 100644 esp32/interrupt_struct.go create mode 100644 esp32/interrupts.go create mode 100644 esp32/intr_types.go create mode 100644 esp32/inttypes_ext.go create mode 100644 esp32/io_mux.go create mode 100644 esp32/io_mux_reg.go create mode 100644 esp32/isp_hal.go create mode 100644 esp32/isp_types.go create mode 100644 esp32/jpeg_defs.go create mode 100644 esp32/jpeg_hal.go create mode 100644 esp32/jpeg_types.go create mode 100644 esp32/key_mgr_types.go create mode 100644 esp32/lcd_cam_reg.go create mode 100644 esp32/lcd_cam_struct.go create mode 100644 esp32/lcd_hal.go create mode 100644 esp32/lcd_ll.go create mode 100644 esp32/lcd_periph.go create mode 100644 esp32/lcd_types.go create mode 100644 esp32/ldo_types.go create mode 100644 esp32/ledc_hal.go create mode 100644 esp32/ledc_ll.go create mode 100644 esp32/ledc_periph.go create mode 100644 esp32/ledc_reg.go create mode 100644 esp32/ledc_struct.go create mode 100644 esp32/ledc_types.go create mode 100644 esp32/list.go create mode 100644 esp32/llcppg.cfg create mode 100644 esp32/llcppg.pub create mode 100644 esp32/lldesc.go create mode 100644 esp32/llpkg.cfg create mode 100644 esp32/log.go create mode 100644 esp32/log_level.go create mode 100644 esp32/log_lock.go create mode 100644 esp32/log_timestamp.go create mode 100644 esp32/log_util.go create mode 100644 esp32/lp_i2s_hal.go create mode 100644 esp32/mcpwm_hal.go create mode 100644 esp32/mcpwm_ll.go create mode 100644 esp32/mcpwm_periph.go create mode 100644 esp32/mcpwm_reg.go create mode 100644 esp32/mcpwm_struct.go create mode 100644 esp32/mcpwm_types.go create mode 100644 esp32/memprot.go create mode 100644 esp32/memprot_defs.go create mode 100644 esp32/memprot_ll.go create mode 100644 esp32/memprot_types.go create mode 100644 esp32/message_buffer.go create mode 100644 esp32/miniz.go create mode 100644 esp32/mipi_csi_hal.go create mode 100644 esp32/mipi_csi_periph.go create mode 100644 esp32/mipi_csi_share_hw_ctrl.go create mode 100644 esp32/mipi_csi_types.go create mode 100644 esp32/mipi_dsi_hal.go create mode 100644 esp32/mipi_dsi_periph.go create mode 100644 esp32/mipi_dsi_types.go create mode 100644 esp32/misc.go create mode 100644 esp32/mmu.go create mode 100644 esp32/mmu_hal.go create mode 100644 esp32/mmu_ll.go create mode 100644 esp32/mmu_types.go create mode 100644 esp32/modem_clock_types.go create mode 100644 esp32/mpi_hal.go create mode 100644 esp32/mpi_ll.go create mode 100644 esp32/mpi_types.go create mode 100644 esp32/mpu_caps.go create mode 100644 esp32/mpu_hal.go create mode 100644 esp32/mpu_prototypes.go create mode 100644 esp32/mpu_syscall_numbers.go create mode 100644 esp32/mpu_types.go create mode 100644 esp32/mpu_wrappers.go create mode 100644 esp32/mpuasm.go create mode 100644 esp32/mspi_timing_config.go create mode 100644 esp32/mspi_timing_tuning.go create mode 100644 esp32/mspi_timing_tuning_ll.go create mode 100644 esp32/mspi_timing_types.go create mode 100644 esp32/multi_heap.go create mode 100644 esp32/mwdt_ll.go create mode 100644 esp32/nrx_reg.go create mode 100644 esp32/opi_flash.go create mode 100644 esp32/panic_internal.go create mode 100644 esp32/panic_reason.go create mode 100644 esp32/parlio_hal.go create mode 100644 esp32/parlio_types.go create mode 100644 esp32/pcnt_hal.go create mode 100644 esp32/pcnt_ll.go create mode 100644 esp32/pcnt_periph.go create mode 100644 esp32/pcnt_reg.go create mode 100644 esp32/pcnt_struct.go create mode 100644 esp32/pcnt_types.go create mode 100644 esp32/peri_backup_reg.go create mode 100644 esp32/peri_backup_struct.go create mode 100644 esp32/periph_ctrl.go create mode 100644 esp32/periph_defs.go create mode 100644 esp32/pmu_types.go create mode 100644 esp32/port_systick.go create mode 100644 esp32/portable.go create mode 100644 esp32/portbenchmark.go create mode 100644 esp32/portmacro.go create mode 100644 esp32/portmacro_idf.go create mode 100644 esp32/ppa_hal.go create mode 100644 esp32/ppa_types.go create mode 100644 esp32/projdefs.go create mode 100644 esp32/psdet_types.go create mode 100644 esp32/psram_ctrlr_ll.go create mode 100644 esp32/psram_types.go create mode 100644 esp32/queue.go create mode 100644 esp32/reent.go create mode 100644 esp32/reg_base.go create mode 100644 esp32/regi2c_bbpll.go create mode 100644 esp32/regi2c_brownout.go create mode 100644 esp32/regi2c_ctrl.go create mode 100644 esp32/regi2c_defs.go create mode 100644 esp32/regi2c_dig_reg.go create mode 100644 esp32/regi2c_lp_bias.go create mode 100644 esp32/regi2c_saradc.go create mode 100644 esp32/regi2c_ulp.go create mode 100644 esp32/reset_reasons.go create mode 100644 esp32/rmt_hal.go create mode 100644 esp32/rmt_ll.go create mode 100644 esp32/rmt_periph.go create mode 100644 esp32/rmt_reg.go create mode 100644 esp32/rmt_struct.go create mode 100644 esp32/rmt_types.go create mode 100644 esp32/rom_layout.go create mode 100644 esp32/rsa_pss.go create mode 100644 esp32/rtc.go create mode 100644 esp32/rtc_clk.go create mode 100644 esp32/rtc_cntl_ll.go create mode 100644 esp32/rtc_cntl_reg.go create mode 100644 esp32/rtc_cntl_struct.go create mode 100644 esp32/rtc_ctrl.go create mode 100644 esp32/rtc_hal.go create mode 100644 esp32/rtc_i2c_reg.go create mode 100644 esp32/rtc_i2c_struct.go create mode 100644 esp32/rtc_io_channel.go create mode 100644 esp32/rtc_io_hal.go create mode 100644 esp32/rtc_io_ll.go create mode 100644 esp32/rtc_io_periph.go create mode 100644 esp32/rtc_io_reg.go create mode 100644 esp32/rtc_io_struct.go create mode 100644 esp32/rtc_io_types.go create mode 100644 esp32/rwdt_ll.go create mode 100644 esp32/sar_ctrl_ll.go create mode 100644 esp32/sar_periph_ctrl.go create mode 100644 esp32/sd_types.go create mode 100644 esp32/sdio_slave_periph.go create mode 100644 esp32/sdio_slave_types.go create mode 100644 esp32/sdm_hal.go create mode 100644 esp32/sdm_ll.go create mode 100644 esp32/sdm_periph.go create mode 100644 esp32/sdm_types.go create mode 100644 esp32/sdmmc_hal.go create mode 100644 esp32/sdmmc_ll.go create mode 100644 esp32/sdmmc_periph.go create mode 100644 esp32/sdmmc_reg.go create mode 100644 esp32/sdmmc_struct.go create mode 100644 esp32/secure_boot.go create mode 100644 esp32/semphr.go create mode 100644 esp32/sens_reg.go create mode 100644 esp32/sensitive_reg.go create mode 100644 esp32/sensitive_struct.go create mode 100644 esp32/sha.go create mode 100644 esp32/sha_hal.go create mode 100644 esp32/sha_ll.go create mode 100644 esp32/sha_types.go create mode 100644 esp32/sleep_clock.go create mode 100644 esp32/sleep_console.go create mode 100644 esp32/sleep_cpu.go create mode 100644 esp32/sleep_event.go create mode 100644 esp32/sleep_gpio.go create mode 100644 esp32/sleep_modem.go create mode 100644 esp32/sleep_sys_periph.go create mode 100644 esp32/soc.go create mode 100644 esp32/soc_caps.go create mode 100644 esp32/soc_hal.go create mode 100644 esp32/soc_memprot_types.go create mode 100644 esp32/soc_ulp.go create mode 100644 esp32/specreg.go create mode 100644 esp32/spi_hal.go create mode 100644 esp32/spi_ll.go create mode 100644 esp32/spi_mem_reg.go create mode 100644 esp32/spi_mem_struct.go create mode 100644 esp32/spi_periph.go create mode 100644 esp32/spi_pins.go create mode 100644 esp32/spi_reg.go create mode 100644 esp32/spi_share_hw_ctrl.go create mode 100644 esp32/spi_slave_hal.go create mode 100644 esp32/spi_slave_hd_hal.go create mode 100644 esp32/spi_struct.go create mode 100644 esp32/spi_types.go create mode 100644 esp32/spimem_flash_ll.go create mode 100644 esp32/spinlock.go create mode 100644 esp32/stack_macros.go create mode 100644 esp32/startup_internal.go create mode 100644 esp32/stream_buffer.go create mode 100644 esp32/syscon_reg.go create mode 100644 esp32/syscon_struct.go create mode 100644 esp32/system.go create mode 100644 esp32/system_internal.go create mode 100644 esp32/system_reg.go create mode 100644 esp32/system_struct.go create mode 100644 esp32/systimer.go create mode 100644 esp32/systimer_hal.go create mode 100644 esp32/systimer_ll.go create mode 100644 esp32/systimer_reg.go create mode 100644 esp32/systimer_struct.go create mode 100644 esp32/systimer_types.go create mode 100644 esp32/task.go create mode 100644 esp32/temperature_sensor_ll.go create mode 100644 esp32/temperature_sensor_periph.go create mode 100644 esp32/temperature_sensor_types.go create mode 100644 esp32/tie-asm.go create mode 100644 esp32/tie.go create mode 100644 esp32/timer_group_reg.go create mode 100644 esp32/timer_group_struct.go create mode 100644 esp32/timer_hal.go create mode 100644 esp32/timer_ll.go create mode 100644 esp32/timer_periph.go create mode 100644 esp32/timer_types.go create mode 100644 esp32/timers.go create mode 100644 esp32/tjpgd.go create mode 100644 esp32/touch_channel.go create mode 100644 esp32/touch_sensor_channel.go create mode 100644 esp32/touch_sensor_hal.go create mode 100644 esp32/touch_sensor_ll.go create mode 100644 esp32/touch_sensor_pins.go create mode 100644 esp32/touch_sensor_types.go create mode 100644 esp32/tracemem_config.go create mode 100644 esp32/trax.go create mode 100644 esp32/traxreg.go create mode 100644 esp32/twai_hal.go create mode 100644 esp32/twai_ll.go create mode 100644 esp32/twai_periph.go create mode 100644 esp32/twai_struct.go create mode 100644 esp32/twai_types.go create mode 100644 esp32/uart.go create mode 100644 esp32/uart_channel.go create mode 100644 esp32/uart_hal.go create mode 100644 esp32/uart_ll.go create mode 100644 esp32/uart_periph.go create mode 100644 esp32/uart_pins.go create mode 100644 esp32/uart_reg.go create mode 100644 esp32/uart_share_hw_ctrl.go create mode 100644 esp32/uart_struct.go create mode 100644 esp32/uart_types.go create mode 100644 esp32/uhci_ll.go create mode 100644 esp32/uhci_reg.go create mode 100644 esp32/uhci_struct.go create mode 100644 esp32/uhci_types.go create mode 100644 esp32/usb_cdc.go create mode 100644 esp32/usb_console.go create mode 100644 esp32/usb_dc.go create mode 100644 esp32/usb_descriptor.go create mode 100644 esp32/usb_device.go create mode 100644 esp32/usb_dfu.go create mode 100644 esp32/usb_dwc_cfg.go create mode 100644 esp32/usb_dwc_hal.go create mode 100644 esp32/usb_dwc_ll.go create mode 100644 esp32/usb_dwc_periph.go create mode 100644 esp32/usb_dwc_struct.go create mode 100644 esp32/usb_dwc_types.go create mode 100644 esp32/usb_os_glue.go create mode 100644 esp32/usb_periph.go create mode 100644 esp32/usb_persist.go create mode 100644 esp32/usb_phy_types.go create mode 100644 esp32/usb_pins.go create mode 100644 esp32/usb_reg.go create mode 100644 esp32/usb_serial_jtag_hal.go create mode 100644 esp32/usb_serial_jtag_ll.go create mode 100644 esp32/usb_serial_jtag_reg.go create mode 100644 esp32/usb_serial_jtag_struct.go create mode 100644 esp32/usb_serial_jtag_types.go create mode 100644 esp32/usb_struct.go create mode 100644 esp32/usb_wrap_hal.go create mode 100644 esp32/usb_wrap_ll.go create mode 100644 esp32/usb_wrap_reg.go create mode 100644 esp32/usb_wrap_struct.go create mode 100644 esp32/usb_wrap_types.go create mode 100644 esp32/wait_for_event.go create mode 100644 esp32/wdev_reg.go create mode 100644 esp32/wdt_hal.go create mode 100644 esp32/wdt_periph.go create mode 100644 esp32/wdt_types.go create mode 100644 esp32/world_controller_reg.go create mode 100644 esp32/world_controller_struct.go create mode 100644 esp32/xdm-regs.go create mode 100644 esp32/xt_instr_macros.go create mode 100644 esp32/xt_perf_consts.go create mode 100644 esp32/xt_trax.go create mode 100644 esp32/xt_wdt_hal.go create mode 100644 esp32/xt_wdt_ll.go create mode 100644 esp32/xtensa-debug-module.go create mode 100644 esp32/xtensa-libdb-macros.go create mode 100644 esp32/xtensa-versions.go create mode 100644 esp32/xtensa-xer.go create mode 100644 esp32/xtensa_api.go create mode 100644 esp32/xtensa_config.go create mode 100644 esp32/xtensa_context.go create mode 100644 esp32/xtensa_rtos.go create mode 100644 esp32/xtensa_timer.go create mode 100644 esp32/xtruntime-core-state.go create mode 100644 esp32/xtruntime-frames.go create mode 100644 esp32/xtruntime.go diff --git a/esp32/FreeRTOS.go b/esp32/FreeRTOS.go new file mode 100644 index 00000000..ec7da3c4 --- /dev/null +++ b/esp32/FreeRTOS.go @@ -0,0 +1,193 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ConfigUSE_C_RUNTIME_TLS_SUPPORT = 1 +const INCLUDE_xQueueGetMutexHolder = 0 +const ConfigUSE_DAEMON_TASK_STARTUP_HOOK = 0 +const ConfigUSE_APPLICATION_TASK_TAG = 0 +const ConfigUSE_ALTERNATIVE_API = 0 +const ConfigASSERT_DEFINED = 1 +const ConfigPRECONDITION_DEFINED = 0 +const ConfigUSE_MINI_LIST_ITEM = 1 +const ConfigGENERATE_RUN_TIME_STATS = 0 +const ConfigUSE_MALLOC_FAILED_HOOK = 0 +const ConfigEXPECTED_IDLE_TIME_BEFORE_SLEEP = 2 +const ConfigINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS = 0 +const ConfigUSE_STATS_FORMATTING_FUNCTIONS = 0 +const ConfigUSE_TRACE_FACILITY = 0 +const ConfigUSE_POSIX_ERRNO = 0 +const ConfigUSE_SB_COMPLETED_CALLBACK = 0 +const ConfigINITIAL_TICK_COUNT = 0 +const ConfigUSE_TASK_FPU_SUPPORT = 1 +const ConfigENABLE_MPU = 0 +const ConfigENABLE_FPU = 1 +const ConfigENABLE_MVE = 0 +const ConfigENABLE_TRUSTZONE = 1 +const ConfigRUN_FREERTOS_SECURE_ONLY = 0 +const ConfigRUN_ADDITIONAL_TESTS = 0 + +/* + * In line with software engineering best practice, FreeRTOS implements a strict + * data hiding policy, so the real structures used by FreeRTOS to maintain the + * state of tasks, queues, semaphores, etc. are not accessible to the application + * code. However, if the application writer wants to statically allocate such + * an object then the size of the object needs to be known. Dummy structures + * that are guaranteed to have the same size and alignment requirements of the + * real objects are used for this purpose. The dummy list and list item + * structures below are used for inclusion in such a dummy structure. + */ +type XSTATICLISTITEM struct { + XDummy2 TickTypeT + PvDummy3 [4]c.Pointer +} +type StaticListItemT XSTATICLISTITEM + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ + +type XSTATICMINILISTITEM struct { + XDummy2 TickTypeT + PvDummy3 [2]c.Pointer +} +type StaticMiniListItemT XSTATICMINILISTITEM + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ + +type XSTATICLIST struct { + UxDummy2 UBaseTypeT + PvDummy3 c.Pointer + XDummy4 StaticMiniListItemT +} +type StaticListT XSTATICLIST + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Task structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a task then + * the size of the task object needs to be known. The StaticTask_t structure + * below is provided for this purpose. Its sizes and alignment requirements are + * guaranteed to match those of the genuine structure, no matter which + * architecture is being used, and no matter how the values in FreeRTOSConfig.h + * are set. Its contents are somewhat obfuscated in the hope users will + * recognise that it would be unwise to make direct use of the structure members. + */ +type XSTATICTCB struct { + PxDummy1 c.Pointer + XDummy3 [2]StaticListItemT + UxDummy5 UBaseTypeT + PxDummy6 c.Pointer + UcDummy7 [16]c.Uint8T + XDummyCoreID BaseTypeT + PxDummy8 c.Pointer + UxDummy12 [2]UBaseTypeT + PvDummy15 [2]c.Pointer + XDummy17 X_reent + UlDummy18 [1]c.Uint32T + UcDummy19 [1]c.Uint8T + UxDummy20 c.Uint8T + UcDummy21 c.Uint8T +} +type StaticTaskT XSTATICTCB + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Queue structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a queue + * then the size of the queue object needs to be known. The StaticQueue_t + * structure below is provided for this purpose. Its sizes and alignment + * requirements are guaranteed to match those of the genuine structure, no + * matter which architecture is being used, and no matter how the values in + * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope + * users will recognise that it would be unwise to make direct use of the + * structure members. + */ +type XSTATICQUEUE struct { + PvDummy1 [3]c.Pointer + U struct { + PvDummy2 c.Pointer + } + XDummy3 [2]StaticListT + UxDummy4 [3]UBaseTypeT + UcDummy5 [2]c.Uint8T + UcDummy6 c.Uint8T + PvDummy7 c.Pointer + XDummyQueueLock PortMUXTYPE +} +type StaticQueueT XSTATICQUEUE +type StaticSemaphoreT StaticQueueT + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the event group structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create an event group then the size of the event group object needs to be + * know. The StaticEventGroup_t structure below is provided for this purpose. + * Its sizes and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +type XSTATICEVENTGROUP struct { + XDummy1 TickTypeT + XDummy2 StaticListT + UcDummy4 c.Uint8T + XDummyEventGroupLock PortMUXTYPE +} +type StaticEventGroupT XSTATICEVENTGROUP + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the software timer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a software timer then the size of the queue object needs to be known. + * The StaticTimer_t structure below is provided for this purpose. Its sizes + * and alignment requirements are guaranteed to match those of the genuine + * structure, no matter which architecture is being used, and no matter how the + * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in + * the hope users will recognise that it would be unwise to make direct use of + * the structure members. + */ +type XSTATICTIMER struct { + PvDummy1 c.Pointer + XDummy2 StaticListItemT + XDummy3 TickTypeT + PvDummy5 c.Pointer + PvDummy6 c.Int + UcDummy8 c.Uint8T +} +type StaticTimerT XSTATICTIMER + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the stream buffer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a stream buffer then the size of the stream buffer object needs to be + * known. The StaticStreamBuffer_t structure below is provided for this + * purpose. Its size and alignment requirements are guaranteed to match those + * of the genuine structure, no matter which architecture is being used, and + * no matter how the values in FreeRTOSConfig.h are set. Its contents are + * somewhat obfuscated in the hope users will recognise that it would be unwise + * to make direct use of the structure members. + */ +type XSTATICSTREAMBUFFER struct { + UxDummy1 [4]c.SizeT + PvDummy2 [3]c.Pointer + UcDummy3 c.Uint8T + XDummyStreamBufferLock PortMUXTYPE +} +type StaticStreamBufferT XSTATICSTREAMBUFFER +type StaticMessageBufferT StaticStreamBufferT diff --git a/esp32/FreeRTOSConfig_arch.go b/esp32/FreeRTOSConfig_arch.go new file mode 100644 index 00000000..86a30a86 --- /dev/null +++ b/esp32/FreeRTOSConfig_arch.go @@ -0,0 +1,11 @@ +package freertos + +import _ "unsafe" + +const ConfigUSE_PORT_OPTIMISED_TASK_SELECTION = 0 +const ConfigMAX_API_CALL_INTERRUPT_PRIORITY = 0 +const ConfigUSE_NEWLIB_REENTRANT = 1 +const ConfigINCLUDE_FREERTOS_TASK_C_ADDITIONS_H = 1 +const INCLUDE_xTaskDelayUntil = 1 +const INCLUDE_uxTaskGetStackHighWaterMark2 = 1 +const INCLUDE_vTaskDelayUntil = 1 diff --git a/esp32/adc_channel.go b/esp32/adc_channel.go new file mode 100644 index 00000000..bc770fda --- /dev/null +++ b/esp32/adc_channel.go @@ -0,0 +1,44 @@ +package freertos + +import _ "unsafe" + +const ADC1_GPIO1_CHANNEL = 0 +const ADC1_CHANNEL_0_GPIO_NUM = 1 +const ADC1_GPIO2_CHANNEL = 1 +const ADC1_CHANNEL_1_GPIO_NUM = 2 +const ADC1_GPIO3_CHANNEL = 2 +const ADC1_CHANNEL_2_GPIO_NUM = 3 +const ADC1_GPIO4_CHANNEL = 3 +const ADC1_CHANNEL_3_GPIO_NUM = 4 +const ADC1_GPIO5_CHANNEL = 4 +const ADC1_CHANNEL_4_GPIO_NUM = 5 +const ADC1_GPIO6_CHANNEL = 5 +const ADC1_CHANNEL_5_GPIO_NUM = 6 +const ADC1_GPIO7_CHANNEL = 6 +const ADC1_CHANNEL_6_GPIO_NUM = 7 +const ADC1_GPIO8_CHANNEL = 7 +const ADC1_CHANNEL_7_GPIO_NUM = 8 +const ADC1_GPIO9_CHANNEL = 8 +const ADC1_CHANNEL_8_GPIO_NUM = 9 +const ADC1_GPIO10_CHANNEL = 9 +const ADC1_CHANNEL_9_GPIO_NUM = 10 +const ADC2_GPIO11_CHANNEL = 0 +const ADC2_CHANNEL_0_GPIO_NUM = 11 +const ADC2_GPIO12_CHANNEL = 1 +const ADC2_CHANNEL_1_GPIO_NUM = 12 +const ADC2_GPIO13_CHANNEL = 2 +const ADC2_CHANNEL_2_GPIO_NUM = 13 +const ADC2_GPIO14_CHANNEL = 3 +const ADC2_CHANNEL_3_GPIO_NUM = 14 +const ADC2_GPIO15_CHANNEL = 4 +const ADC2_CHANNEL_4_GPIO_NUM = 15 +const ADC2_GPIO16_CHANNEL = 5 +const ADC2_CHANNEL_5_GPIO_NUM = 16 +const ADC2_GPIO17_CHANNEL = 6 +const ADC2_CHANNEL_6_GPIO_NUM = 17 +const ADC2_GPIO18_CHANNEL = 7 +const ADC2_CHANNEL_7_GPIO_NUM = 18 +const ADC2_GPIO19_CHANNEL = 8 +const ADC2_CHANNEL_8_GPIO_NUM = 19 +const ADC2_GPIO20_CHANNEL = 9 +const ADC2_CHANNEL_9_GPIO_NUM = 20 diff --git a/esp32/adc_hal.go b/esp32/adc_hal.go new file mode 100644 index 00000000..52f286c5 --- /dev/null +++ b/esp32/adc_hal.go @@ -0,0 +1,146 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type AdcHalDmaDescStatusT c.Int + +const ( + ADC_HAL_DMA_DESC_VALID AdcHalDmaDescStatusT = 0 + ADC_HAL_DMA_DESC_WAITING AdcHalDmaDescStatusT = 1 + ADC_HAL_DMA_DESC_NULL AdcHalDmaDescStatusT = 2 +) + +/** + * @brief Configuration of the HAL + */ + +type AdcHalDmaConfigT struct { + EofDescNum c.Uint32T + EofStep c.Uint32T + EofNum c.Uint32T +} + +/** + * @brief Context of the HAL + */ + +type AdcHalDmaCtxT struct { + RxDesc *DmaDescriptorT + DescDummyHead DmaDescriptorT + CurDescPtr *DmaDescriptorT + EofDescNum c.Uint32T + EofStep c.Uint32T + EofNum c.Uint32T +} + +type AdcHalDigiCtrlrCfgT struct { + AdcPatternLen c.Uint32T + AdcPattern *AdcDigiPatternConfigT + SampleFreqHz c.Uint32T + ConvMode AdcDigiConvertModeT + BitWidth c.Uint32T + ClkSrc AdcContinuousClkSrcT + ClkSrcFreqHz c.Uint32T +} + +/*--------------------------------------------------------------- + Digital controller setting +---------------------------------------------------------------*/ +/** + * @brief Initialize the HW + * + * @param hal Context of the HAL + */ +// llgo:link (*AdcHalDmaCtxT).AdcHalDigiInit C.adc_hal_digi_init +func (recv_ *AdcHalDmaCtxT) AdcHalDigiInit() { +} + +/** + * Digital controller deinitialization. + * + */ +//go:linkname AdcHalDigiDeinit C.adc_hal_digi_deinit +func AdcHalDigiDeinit() + +/** + * @brief Initialize the hal context + * + * @param hal Context of the HAL + * @param config Configuration of the HAL + */ +// llgo:link (*AdcHalDmaCtxT).AdcHalDmaCtxConfig C.adc_hal_dma_ctx_config +func (recv_ *AdcHalDmaCtxT) AdcHalDmaCtxConfig(config *AdcHalDmaConfigT) { +} + +/** + * Setting the digital controller. + * + * @param hal Context of the HAL + * @param cfg Pointer to digital controller parameter. + */ +// llgo:link (*AdcHalDmaCtxT).AdcHalDigiControllerConfig C.adc_hal_digi_controller_config +func (recv_ *AdcHalDmaCtxT) AdcHalDigiControllerConfig(cfg *AdcHalDigiCtrlrCfgT) { +} + +/** + * @brief Link DMA descriptor + * + * @param hal Context of the HAL + * @param data_buf Pointer to the data buffer, the length should be multiple of ``desc_max_num`` and ``eof_num`` in ``adc_hal_dma_ctx_t`` + */ +// llgo:link (*AdcHalDmaCtxT).AdcHalDigiDmaLink C.adc_hal_digi_dma_link +func (recv_ *AdcHalDmaCtxT) AdcHalDigiDmaLink(data_buf *c.Uint8T) { +} + +/** + * @brief Get the ADC reading result + * + * @param hal Context of the HAL + * @param eof_desc_addr The last descriptor that is finished by HW. Should be got from DMA + * @param[out] buffer ADC reading result buffer + * @param[out] len ADC reading result len + * + * @return See ``adc_hal_dma_desc_status_t`` + */ +// llgo:link (*AdcHalDmaCtxT).AdcHalGetReadingResult C.adc_hal_get_reading_result +func (recv_ *AdcHalDmaCtxT) AdcHalGetReadingResult(eof_desc_addr c.IntptrT, buffer **c.Uint8T, len *c.Uint32T) AdcHalDmaDescStatusT { + return 0 +} + +/** + * @brief Enable or disable ADC digital controller + * + * @param enable true to enable, false to disable + */ +//go:linkname AdcHalDigiEnable C.adc_hal_digi_enable +func AdcHalDigiEnable(enable bool) + +/** + * @brief Enable pr disable output data to DMA from adc digital controller. + * + * @param enable true to enable, false to disable + */ +//go:linkname AdcHalDigiConnect C.adc_hal_digi_connect +func AdcHalDigiConnect(enable bool) + +/** + * @brief Reset adc digital controller. + */ +//go:linkname AdcHalDigiReset C.adc_hal_digi_reset +func AdcHalDigiReset() + +/** + * @brief Set ADC monitor with high and low thresholds, and will enable the interrupts accordingly + * + * @param monitor_id Monitor to configure + * @param adc_n Which ADC unit will be monitored + * @param adc_ch Which ADC channel will be monitored + * @param h_thres High threshold (disable if < 0) + * @param l_thres Low threshold (disable if < 0) + */ +// llgo:link AdcMonitorIdT.AdcHalDigiMonitorSetThres C.adc_hal_digi_monitor_set_thres +func (recv_ AdcMonitorIdT) AdcHalDigiMonitorSetThres(adc_n AdcUnitT, adc_ch c.Uint8T, h_thres c.Int32T, l_thres c.Int32T) { +} diff --git a/esp32/adc_hal_common.go b/esp32/adc_hal_common.go new file mode 100644 index 00000000..d38a9905 --- /dev/null +++ b/esp32/adc_hal_common.go @@ -0,0 +1,80 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type AdcHalWorkModeT c.Int + +const ( + ADC_HAL_SINGLE_READ_MODE AdcHalWorkModeT = 0 + ADC_HAL_CONTINUOUS_READ_MODE AdcHalWorkModeT = 1 + ADC_HAL_PWDET_MODE AdcHalWorkModeT = 2 + ADC_HAL_LP_MODE AdcHalWorkModeT = 3 +) + +/** + * Set ADC work mode + * + * @param unit ADC unit + * @param work_mode see `adc_hal_work_mode_t` + */ +// llgo:link AdcUnitT.AdcHalSetController C.adc_hal_set_controller +func (recv_ AdcUnitT) AdcHalSetController(work_mode AdcHalWorkModeT) { +} + +//No ADC2 controller arbiter on ESP32 +/** + * Config ADC2 module arbiter. + * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority, + * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data. + * + * @note Only ADC2 support arbiter. + * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode. + * @note Default priority: Wi-Fi > RTC > Digital; + * + * @param config Refer to ``adc_arbiter_t``. + */ +// llgo:link (*AdcArbiterT).AdcHalArbiterConfig C.adc_hal_arbiter_config +func (recv_ *AdcArbiterT) AdcHalArbiterConfig() { +} + +/** + * @brief Initialize default parameter for the calibration block. + * + * @param adc_n ADC index number + */ +// llgo:link AdcUnitT.AdcHalCalibrationInit C.adc_hal_calibration_init +func (recv_ AdcUnitT) AdcHalCalibrationInit() { +} + +/** + * Set the calibration result (initial data) to ADC. + * + * @note Different ADC units and different attenuation options use different calibration data (initial data). + * + * @param adc_n ADC index number. + * @param param the calibration parameter to configure + */ +// llgo:link AdcUnitT.AdcHalSetCalibrationParam C.adc_hal_set_calibration_param +func (recv_ AdcUnitT) AdcHalSetCalibrationParam(param c.Uint32T) { +} + +/** + * Calibrate the ADC using internal connections. + * + * @note Different ADC units and different attenuation options use different calibration data (initial data). + * + * @param adc_n ADC index number. + * @param atten ADC attenuation + * @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage. + * false: Use IO external voltage as calibration voltage. + * + * @return + * - The calibration result (initial data) to ADC, use `adc_hal_set_calibration_param` to set. + */ +// llgo:link AdcUnitT.AdcHalSelfCalibration C.adc_hal_self_calibration +func (recv_ AdcUnitT) AdcHalSelfCalibration(atten AdcAttenT, internal_gnd bool) c.Uint32T { + return 0 +} diff --git a/esp32/adc_ll.go b/esp32/adc_ll.go new file mode 100644 index 00000000..8b4a71f7 --- /dev/null +++ b/esp32/adc_ll.go @@ -0,0 +1,61 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ADC_LL_CLKM_DIV_NUM_DEFAULT = 15 +const ADC_LL_CLKM_DIV_B_DEFAULT = 1 +const ADC_LL_CLKM_DIV_A_DEFAULT = 0 +const ADC_LL_DEFAULT_CONV_LIMIT_EN = 0 +const ADC_LL_DEFAULT_CONV_LIMIT_NUM = 10 + +type AdcLlPowerT c.Int + +const ( + ADC_LL_POWER_BY_FSM AdcLlPowerT = 0 + ADC_LL_POWER_SW_ON AdcLlPowerT = 1 + ADC_LL_POWER_SW_OFF AdcLlPowerT = 2 +) + +type AdcLlRtcRawDataT c.Int + +const ( + ADC_LL_RTC_DATA_OK AdcLlRtcRawDataT = 0 + ADC_LL_RTC_CTRL_UNSELECTED AdcLlRtcRawDataT = 1 + ADC_LL_RTC_CTRL_BREAK AdcLlRtcRawDataT = 2 + ADC_LL_RTC_DATA_FAIL AdcLlRtcRawDataT = -1 +) + +type AdcLlControllerT c.Int + +const ( + ADC_LL_CTRL_RTC AdcLlControllerT = 0 + ADC_LL_CTRL_ULP AdcLlControllerT = 1 + ADC_LL_CTRL_DIG AdcLlControllerT = 2 + ADC_LL_CTRL_ARB AdcLlControllerT = 3 +) + +type AdcLlDigiConvertModeT c.Int + +const ( + ADC_LL_DIGI_CONV_ONLY_ADC1 AdcLlDigiConvertModeT = 0 + ADC_LL_DIGI_CONV_ONLY_ADC2 AdcLlDigiConvertModeT = 1 + ADC_LL_DIGI_CONV_BOTH_UNIT AdcLlDigiConvertModeT = 2 + ADC_LL_DIGI_CONV_ALTER_UNIT AdcLlDigiConvertModeT = 3 +) + +type AdcLlDigiPatternTableT struct { + Unused [8]uint8 +} + +/** + * @brief Analyze whether the obtained raw data is correct. + * ADC2 use arbiter by default. The arbitration result can be judged by the flag bit in the original data. + * + */ + +type AdcLlRtcOutputDataT struct { + Unused [8]uint8 +} diff --git a/esp32/adc_oneshot_hal.go b/esp32/adc_oneshot_hal.go new file mode 100644 index 00000000..a4fc5a32 --- /dev/null +++ b/esp32/adc_oneshot_hal.go @@ -0,0 +1,86 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type Sens_Dev_________ struct { + Unused [8]uint8 +} +type AdcOneshotSocHandleT *Sens_Dev_________ + +type AdcOneshotHalCfgT struct { + Unit AdcUnitT + WorkMode AdcHalWorkModeT + ClkSrc AdcOneshotClkSrcT + ClkSrcFreqHz c.Uint32T +} + +/** + * ADC channel configuration + */ + +type AdcOneshotHalChanCfgT struct { + Atten AdcAttenT + Bitwidth AdcBitwidthT +} + +/** + * Context of the ADC unit, should be maintained by both the driver and the HAL. + */ + +type AdcOneshotHalCtxT struct { + Dev AdcOneshotSocHandleT + Unit AdcUnitT + WorkMode AdcHalWorkModeT + ChanConfigs [10]AdcOneshotHalChanCfgT + ClkSrc AdcOneshotClkSrcT + ClkSrcFreqHz c.Uint32T +} + +/** + * Initialise the context + * + * @param hal ADC Oneshot Hal context + * @param config ADC Oneshot Hal init config + */ +// llgo:link (*AdcOneshotHalCtxT).AdcOneshotHalInit C.adc_oneshot_hal_init +func (recv_ *AdcOneshotHalCtxT) AdcOneshotHalInit(config *AdcOneshotHalCfgT) { +} + +/** + * Prepare ADC Oneshot hal context + * + * @param hal ADC Oneshot Hal context + * @param config ADC Oneshot Hal configuration + * @param chan ADC Channel + */ +// llgo:link (*AdcOneshotHalCtxT).AdcOneshotHalChannelConfig C.adc_oneshot_hal_channel_config +func (recv_ *AdcOneshotHalCtxT) AdcOneshotHalChannelConfig(config *AdcOneshotHalChanCfgT, chan_ AdcChannelT) { +} + +/** + * Set ADC Oneshot mode required registers + * + * @param hal ADC Oneshot Hal context + * @param channel ADC Channel + */ +// llgo:link (*AdcOneshotHalCtxT).AdcOneshotHalSetup C.adc_oneshot_hal_setup +func (recv_ *AdcOneshotHalCtxT) AdcOneshotHalSetup(channel AdcChannelT) { +} + +/** + * Start ADC conversion in Oneshot mode and get the raw result + * + * @param hal ADC Oneshot Hal context + * @param[out] out_raw ADC oneshot conversion raw result + * + * @return + * - true: ADC raw result is valid + * - false: ADC raw result is invalid + */ +// llgo:link (*AdcOneshotHalCtxT).AdcOneshotHalConvert C.adc_oneshot_hal_convert +func (recv_ *AdcOneshotHalCtxT) AdcOneshotHalConvert(out_raw *c.Int) bool { + return false +} diff --git a/esp32/adc_share_hw_ctrl.go b/esp32/adc_share_hw_ctrl.go new file mode 100644 index 00000000..a13b70aa --- /dev/null +++ b/esp32/adc_share_hw_ctrl.go @@ -0,0 +1,125 @@ +package freertos + +import _ "unsafe" + +/*--------------------------------------------------------------- + ADC Hardware Calibration +---------------------------------------------------------------*/ +/** + * @brief Calculate the ADC HW calibration code. (Based on the pre-stored efuse or actual calibration) + * + * @param adc_n ADC unit to calibrate + * @param atten Attenuation to use + */ +// llgo:link AdcUnitT.AdcCalcHwCalibrationCode C.adc_calc_hw_calibration_code +func (recv_ AdcUnitT) AdcCalcHwCalibrationCode(atten AdcAttenT) { +} + +/** + * @brief Set the ADC HW calibration code. + * + * @param adc_n ADC unit to calibrate + * @param atten Attenuation to use + */ +// llgo:link AdcUnitT.AdcSetHwCalibrationCode C.adc_set_hw_calibration_code +func (recv_ AdcUnitT) AdcSetHwCalibrationCode(atten AdcAttenT) { +} + +/*--------------------------------------------------------------- + ADC Cross Peripheral Locks +---------------------------------------------------------------*/ +/** + * @brief Acquire ADC lock by unit + * + * The lock acquiring sequence will be: ADC1, ADC2, ... + * + * @note If any of the locks are taken, this API will wait until the lock is successfully acquired. + * + * @param[in] adc_unit ADC unit ID + * + * @return + * - ESP_OK: On success + */ +// llgo:link AdcUnitT.AdcLockAcquire C.adc_lock_acquire +func (recv_ AdcUnitT) AdcLockAcquire() EspErrT { + return 0 +} + +/** + * @brief Release ADC lock by unit + * + * The lock releasing sequence will be: ..., ADC2, ADC1 + * + * @param[in] adc_unit ADC unit ID + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_STATE: The lock(s) isn't acquired yet + */ +// llgo:link AdcUnitT.AdcLockRelease C.adc_lock_release +func (recv_ AdcUnitT) AdcLockRelease() EspErrT { + return 0 +} + +/** + * @brief Try to acquire ADC lock by unit + * + * The lock acquiring sequence will be: ADC1, ADC2, ... + * + * @note If any of the locks are taken, this API will return immediately with an error `ESP_ERR_TIMEOUT` + * + * @param[in] adc_unit ADC unit ID + * + * @return + * - ESP_OK: On success + * - ESP_ERR_TIMEOUT: Lock(s) is taken already + */ +// llgo:link AdcUnitT.AdcLockTryAcquire C.adc_lock_try_acquire +func (recv_ AdcUnitT) AdcLockTryAcquire() EspErrT { + return 0 +} + +/** + * @brief For WIFI module to claim the usage of ADC2. + * + * Other tasks will be forbidden to use ADC2 between ``adc2_wifi_acquire`` and ``adc2_wifi_release``. + * The WIFI module may have to wait for a short time for the current conversion (if exist) to finish. + * + * @return + * - ESP_OK success + * - ESP_ERR_TIMEOUT reserved for future use. Currently the function will wait until success. + */ +//go:linkname Adc2WifiAcquire C.adc2_wifi_acquire +func Adc2WifiAcquire() EspErrT + +/** + * @brief For WIFI module to let other tasks use the ADC2 when WIFI is not work. + * + * Other tasks will be forbidden to use ADC2 between ``adc2_wifi_acquire`` and ``adc2_wifi_release``. + * Call this function to release the occupation of ADC2 by WIFI. + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_STATE: The lock(s) isn't acquired yet + */ +//go:linkname Adc2WifiRelease C.adc2_wifi_release +func Adc2WifiRelease() EspErrT + +/*------------------------------------------------------------------------------ +* For those who use APB_SARADC periph +*----------------------------------------------------------------------------*/ +/** + * @brief Claim the usage of the APB_SARADC periph + * + * Reference count inside + */ +//go:linkname AdcApbPeriphClaim C.adc_apb_periph_claim +func AdcApbPeriphClaim() + +/** + * @brief Free the usage of the APB_SARADC periph + * + * Reference count inside + */ +//go:linkname AdcApbPeriphFree C.adc_apb_periph_free +func AdcApbPeriphFree() diff --git a/esp32/adc_types.go b/esp32/adc_types.go new file mode 100644 index 00000000..ee851630 --- /dev/null +++ b/esp32/adc_types.go @@ -0,0 +1,127 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type AdcUnitT c.Int + +const ( + ADC_UNIT_1 AdcUnitT = 0 + ADC_UNIT_2 AdcUnitT = 1 +) + +type AdcChannelT c.Int + +const ( + ADC_CHANNEL_0 AdcChannelT = 0 + ADC_CHANNEL_1 AdcChannelT = 1 + ADC_CHANNEL_2 AdcChannelT = 2 + ADC_CHANNEL_3 AdcChannelT = 3 + ADC_CHANNEL_4 AdcChannelT = 4 + ADC_CHANNEL_5 AdcChannelT = 5 + ADC_CHANNEL_6 AdcChannelT = 6 + ADC_CHANNEL_7 AdcChannelT = 7 + ADC_CHANNEL_8 AdcChannelT = 8 + ADC_CHANNEL_9 AdcChannelT = 9 +) + +type AdcAttenT c.Int + +const ( + ADC_ATTEN_DB_0 AdcAttenT = 0 + ADC_ATTEN_DB_2_5 AdcAttenT = 1 + ADC_ATTEN_DB_6 AdcAttenT = 2 + ADC_ATTEN_DB_12 AdcAttenT = 3 + ADC_ATTEN_DB_11 AdcAttenT = 3 +) + +type AdcBitwidthT c.Int + +const ( + ADC_BITWIDTH_DEFAULT AdcBitwidthT = 0 + ADC_BITWIDTH_9 AdcBitwidthT = 9 + ADC_BITWIDTH_10 AdcBitwidthT = 10 + ADC_BITWIDTH_11 AdcBitwidthT = 11 + ADC_BITWIDTH_12 AdcBitwidthT = 12 + ADC_BITWIDTH_13 AdcBitwidthT = 13 +) + +type AdcUlpModeT c.Int + +const ( + ADC_ULP_MODE_DISABLE AdcUlpModeT = 0 + ADC_ULP_MODE_FSM AdcUlpModeT = 1 + ADC_ULP_MODE_RISCV AdcUlpModeT = 2 +) + +type AdcDigiConvertModeT c.Int + +const ( + ADC_CONV_SINGLE_UNIT_1 AdcDigiConvertModeT = 1 + ADC_CONV_SINGLE_UNIT_2 AdcDigiConvertModeT = 2 + ADC_CONV_BOTH_UNIT AdcDigiConvertModeT = 3 + ADC_CONV_ALTER_UNIT AdcDigiConvertModeT = 7 +) + +type AdcDigiOutputFormatT c.Int + +const ( + ADC_DIGI_OUTPUT_FORMAT_TYPE1 AdcDigiOutputFormatT = 0 + ADC_DIGI_OUTPUT_FORMAT_TYPE2 AdcDigiOutputFormatT = 1 +) + +type AdcOneshotClkSrcT SocPeriphAdcRtcClkSrcT +type AdcContinuousClkSrcT SocPeriphAdcDigiClkSrcT + +/** + * @brief ADC digital controller pattern configuration + */ + +type AdcDigiPatternConfigT struct { + Atten c.Uint8T + Channel c.Uint8T + Unit c.Uint8T + BitWidth c.Uint8T +} +type AdcDigiIirFilterT c.Int + +const ( + ADC_DIGI_IIR_FILTER_0 AdcDigiIirFilterT = 0 + ADC_DIGI_IIR_FILTER_1 AdcDigiIirFilterT = 1 +) + +type AdcDigiIirFilterCoeffT c.Int + +const ( + ADC_DIGI_IIR_FILTER_COEFF_2 AdcDigiIirFilterCoeffT = 0 + ADC_DIGI_IIR_FILTER_COEFF_4 AdcDigiIirFilterCoeffT = 1 + ADC_DIGI_IIR_FILTER_COEFF_8 AdcDigiIirFilterCoeffT = 2 + ADC_DIGI_IIR_FILTER_COEFF_16 AdcDigiIirFilterCoeffT = 3 + ADC_DIGI_IIR_FILTER_COEFF_32 AdcDigiIirFilterCoeffT = 4 + ADC_DIGI_IIR_FILTER_COEFF_64 AdcDigiIirFilterCoeffT = 5 +) + +type AdcMonitorIdT c.Int + +const ( + ADC_MONITOR_0 AdcMonitorIdT = 0 + ADC_MONITOR_1 AdcMonitorIdT = 1 +) + +type AdcMonitorModeT c.Int + +const ( + ADC_MONITOR_MODE_HIGH AdcMonitorModeT = 0 + ADC_MONITOR_MODE_LOW AdcMonitorModeT = 1 +) + +/** + * @brief ADC digital controller (DMA mode) output data format. + * Used to analyze the acquired ADC (DMA) data. + */ + +type AdcDigiOutputDataT struct { + Unused [8]uint8 +} diff --git a/esp32/adc_types_private.go b/esp32/adc_types_private.go new file mode 100644 index 00000000..d5108757 --- /dev/null +++ b/esp32/adc_types_private.go @@ -0,0 +1,27 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type AdcArbiterModeT c.Int + +const ( + ADC_ARB_MODE_SHIELD AdcArbiterModeT = 0 + ADC_ARB_MODE_FIX AdcArbiterModeT = 1 + ADC_ARB_MODE_LOOP AdcArbiterModeT = 2 +) + +/** + * @brief ADC arbiter work mode and priority setting. + * + * @note Only ADC2 support arbiter. + */ + +type AdcArbiterT struct { + Mode AdcArbiterModeT + RtcPri c.Uint8T + DigPri c.Uint8T + PwdetPri c.Uint8T +} diff --git a/esp32/aes.go b/esp32/aes.go new file mode 100644 index 00000000..da25aa7b --- /dev/null +++ b/esp32/aes.go @@ -0,0 +1,41 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type AESTYPE c.Int + +const ( + AES_ENC AESTYPE = 0 + AES_DEC AESTYPE = 1 +) + +type AESBITS c.Int + +const ( + AES128 AESBITS = 0 + AES192 AESBITS = 1 + AES256 AESBITS = 2 +) + +//go:linkname EtsAesEnable C.ets_aes_enable +func EtsAesEnable() + +//go:linkname EtsAesDisable C.ets_aes_disable +func EtsAesDisable() + +// llgo:link AESTYPE.EtsAesSetkey C.ets_aes_setkey +func (recv_ AESTYPE) EtsAesSetkey(key c.Pointer, bits AESBITS) c.Int { + return 0 +} + +//go:linkname EtsAesSetkeyEnc C.ets_aes_setkey_enc +func EtsAesSetkeyEnc(key c.Pointer, bits AESBITS) c.Int + +//go:linkname EtsAesSetkeyDec C.ets_aes_setkey_dec +func EtsAesSetkeyDec(key c.Pointer, bits AESBITS) c.Int + +//go:linkname EtsAesBlock C.ets_aes_block +func EtsAesBlock(input c.Pointer, output c.Pointer) diff --git a/esp32/aes_hal.go b/esp32/aes_hal.go new file mode 100644 index 00000000..82bdab76 --- /dev/null +++ b/esp32/aes_hal.go @@ -0,0 +1,77 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Sets the key used for AES encryption/decryption + * + * @param key pointer to the key + * @param key_bytes number of bytes in key + * @param mode key mode, 0 : decrypt, 1: encrypt + * + * @return uint8_t number of key bytes written to hardware, used for fault injection check + */ +//go:linkname AesHalSetkey C.aes_hal_setkey +func AesHalSetkey(key *c.Uint8T, key_bytes c.SizeT, mode c.Int) c.Uint8T + +/** + * @brief encrypts/decrypts a single block + * + * @param input_block input block, size of AES_BLOCK_BYTES + * @param output_block output block, size of AES_BLOCK_BYTES + */ +//go:linkname AesHalTransformBlock C.aes_hal_transform_block +func AesHalTransformBlock(input_block c.Pointer, output_block c.Pointer) + +/** + * @brief Inits the AES mode of operation + * + * @param mode mode of operation, e.g. CTR or CBC + */ +// llgo:link EspAesModeT.AesHalModeInit C.aes_hal_mode_init +func (recv_ EspAesModeT) AesHalModeInit() { +} + +/** + * @brief Sets the initialization vector for the transform + * + * @note The same IV must never be reused with the same key + * + * @param iv the initialization vector, length = IV_BYTES (16 bytes) + */ +//go:linkname AesHalSetIv C.aes_hal_set_iv +func AesHalSetIv(iv *c.Uint8T) + +/** + * @brief Reads the initialization vector + * + * @param iv initialization vector read from HW, length = IV_BYTES (16 bytes) + */ +//go:linkname AesHalReadIv C.aes_hal_read_iv +func AesHalReadIv(iv *c.Uint8T) + +/** + * @brief Busy waits until the AES operation is done + * + * @param output pointer to inlink descriptor + */ +//go:linkname AesHalWaitDone C.aes_hal_wait_done +func AesHalWaitDone() + +/** + * @brief Starts an already configured AES DMA transform + * + * @param num_blocks Number of blocks to transform + */ +//go:linkname AesHalTransformDmaStart C.aes_hal_transform_dma_start +func AesHalTransformDmaStart(num_blocks c.SizeT) + +/** + * @brief Finish up a AES DMA conversion, release DMA + * + */ +//go:linkname AesHalTransformDmaFinish C.aes_hal_transform_dma_finish +func AesHalTransformDmaFinish() diff --git a/esp32/aes_ll.go b/esp32/aes_ll.go new file mode 100644 index 00000000..fe868b2d --- /dev/null +++ b/esp32/aes_ll.go @@ -0,0 +1,14 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EspAesStateT c.Int + +const ( + ESP_AES_STATE_IDLE EspAesStateT = 0 + ESP_AES_STATE_BUSY EspAesStateT = 1 + ESP_AES_STATE_DONE EspAesStateT = 2 +) diff --git a/esp32/aes_types.go b/esp32/aes_types.go new file mode 100644 index 00000000..f12ee80a --- /dev/null +++ b/esp32/aes_types.go @@ -0,0 +1,22 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ESP_AES_ENCRYPT = 1 +const ESP_AES_DECRYPT = 0 + +type EspAesModeT c.Int + +const ( + ESP_AES_BLOCK_MODE_ECB EspAesModeT = 0 + ESP_AES_BLOCK_MODE_CBC EspAesModeT = 1 + ESP_AES_BLOCK_MODE_OFB EspAesModeT = 2 + ESP_AES_BLOCK_MODE_CTR EspAesModeT = 3 + ESP_AES_BLOCK_MODE_CFB8 EspAesModeT = 4 + ESP_AES_BLOCK_MODE_CFB128 EspAesModeT = 5 + ESP_AES_BLOCK_MODE_GCM EspAesModeT = 6 + ESP_AES_BLOCK_MODE_MAX EspAesModeT = 7 +) diff --git a/esp32/apb_backup_dma.go b/esp32/apb_backup_dma.go new file mode 100644 index 00000000..1cbaa5d2 --- /dev/null +++ b/esp32/apb_backup_dma.go @@ -0,0 +1,11 @@ +package freertos + +import _ "unsafe" + +/* + * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +//go:linkname EtsApbBackupInitLockFunc C.ets_apb_backup_init_lock_func +func EtsApbBackupInitLockFunc(_apb_backup_lock func(), _apb_backup_unlock func()) diff --git a/esp32/apb_ctrl_reg.go b/esp32/apb_ctrl_reg.go new file mode 100644 index 00000000..4e9e9626 --- /dev/null +++ b/esp32/apb_ctrl_reg.go @@ -0,0 +1,234 @@ +package freertos + +import _ "unsafe" + +const APB_CTRL_RST_TICK_CNT_V = 0x1 +const APB_CTRL_RST_TICK_CNT_S = 12 +const APB_CTRL_CLK_EN_V = 0x1 +const APB_CTRL_CLK_EN_S = 11 +const APB_CTRL_CLK_320M_EN_V = 0x1 +const APB_CTRL_CLK_320M_EN_S = 10 +const APB_CTRL_PRE_DIV_CNT = 0x000003FF +const APB_CTRL_PRE_DIV_CNT_V = 0x3FF +const APB_CTRL_PRE_DIV_CNT_S = 0 +const APB_CTRL_TICK_ENABLE_V = 0x1 +const APB_CTRL_TICK_ENABLE_S = 16 +const APB_CTRL_CK8M_TICK_NUM = 0x000000FF +const APB_CTRL_CK8M_TICK_NUM_V = 0xFF +const APB_CTRL_CK8M_TICK_NUM_S = 8 +const APB_CTRL_XTAL_TICK_NUM = 0x000000FF +const APB_CTRL_XTAL_TICK_NUM_V = 0xFF +const APB_CTRL_XTAL_TICK_NUM_S = 0 +const APB_CTRL_CLK_XTAL_OEN_V = 0x1 +const APB_CTRL_CLK_XTAL_OEN_S = 10 +const APB_CTRL_CLK40X_BB_OEN_V = 0x1 +const APB_CTRL_CLK40X_BB_OEN_S = 9 +const APB_CTRL_CLK_DAC_CPU_OEN_V = 0x1 +const APB_CTRL_CLK_DAC_CPU_OEN_S = 8 +const APB_CTRL_CLK_ADC_INF_OEN_V = 0x1 +const APB_CTRL_CLK_ADC_INF_OEN_S = 7 +const APB_CTRL_CLK_320M_OEN_V = 0x1 +const APB_CTRL_CLK_320M_OEN_S = 6 +const APB_CTRL_CLK160_OEN_V = 0x1 +const APB_CTRL_CLK160_OEN_S = 5 +const APB_CTRL_CLK80_OEN_V = 0x1 +const APB_CTRL_CLK80_OEN_S = 4 +const APB_CTRL_CLK_BB_OEN_V = 0x1 +const APB_CTRL_CLK_BB_OEN_S = 3 +const APB_CTRL_CLK44_OEN_V = 0x1 +const APB_CTRL_CLK44_OEN_S = 2 +const APB_CTRL_CLK22_OEN_V = 0x1 +const APB_CTRL_CLK22_OEN_S = 1 +const APB_CTRL_CLK20_OEN_V = 0x1 +const APB_CTRL_CLK20_OEN_S = 0 +const APB_CTRL_WIFI_BB_CFG = 0xFFFFFFFF +const APB_CTRL_WIFI_BB_CFG_V = 0xFFFFFFFF +const APB_CTRL_WIFI_BB_CFG_S = 0 +const APB_CTRL_WIFI_BB_CFG_2 = 0xFFFFFFFF +const APB_CTRL_WIFI_BB_CFG_2_V = 0xFFFFFFFF +const APB_CTRL_WIFI_BB_CFG_2_S = 0 +const APB_CTRL_WIFI_CLK_EN = 0xFFFFFFFF +const APB_CTRL_WIFI_CLK_EN_V = 0xFFFFFFFF +const APB_CTRL_WIFI_CLK_EN_S = 0 +const APB_CTRL_WIFI_RST = 0xFFFFFFFF +const APB_CTRL_WIFI_RST_V = 0xFFFFFFFF +const APB_CTRL_WIFI_RST_S = 0 +const APB_CTRL_PERI_IO_SWAP = 0x000000FF +const APB_CTRL_PERI_IO_SWAP_V = 0xFF +const APB_CTRL_PERI_IO_SWAP_S = 0 +const APB_CTRL_EXT_MEM_PMS_LOCK_V = 0x1 +const APB_CTRL_EXT_MEM_PMS_LOCK_S = 0 +const APB_CTRL_WRITEBACK_BYPASS_V = 0x1 +const APB_CTRL_WRITEBACK_BYPASS_S = 0 +const APB_CTRL_FLASH_ACE0_ATTR = 0x000001FF +const APB_CTRL_FLASH_ACE0_ATTR_V = 0x1FF +const APB_CTRL_FLASH_ACE0_ATTR_S = 0 +const APB_CTRL_FLASH_ACE1_ATTR = 0x000001FF +const APB_CTRL_FLASH_ACE1_ATTR_V = 0x1FF +const APB_CTRL_FLASH_ACE1_ATTR_S = 0 +const APB_CTRL_FLASH_ACE2_ATTR = 0x000001FF +const APB_CTRL_FLASH_ACE2_ATTR_V = 0x1FF +const APB_CTRL_FLASH_ACE2_ATTR_S = 0 +const APB_CTRL_FLASH_ACE3_ATTR = 0x000001FF +const APB_CTRL_FLASH_ACE3_ATTR_V = 0x1FF +const APB_CTRL_FLASH_ACE3_ATTR_S = 0 +const APB_CTRL_FLASH_ACE0_ADDR_S = 0xFFFFFFFF +const APB_CTRL_FLASH_ACE0_ADDR_S_V = 0xFFFFFFFF +const APB_CTRL_FLASH_ACE0_ADDR_S_S = 0 +const APB_CTRL_FLASH_ACE1_ADDR_S = 0xFFFFFFFF +const APB_CTRL_FLASH_ACE1_ADDR_S_V = 0xFFFFFFFF +const APB_CTRL_FLASH_ACE1_ADDR_S_S = 0 +const APB_CTRL_FLASH_ACE2_ADDR_S = 0xFFFFFFFF +const APB_CTRL_FLASH_ACE2_ADDR_S_V = 0xFFFFFFFF +const APB_CTRL_FLASH_ACE2_ADDR_S_S = 0 +const APB_CTRL_FLASH_ACE3_ADDR_S = 0xFFFFFFFF +const APB_CTRL_FLASH_ACE3_ADDR_S_V = 0xFFFFFFFF +const APB_CTRL_FLASH_ACE3_ADDR_S_S = 0 +const APB_CTRL_FLASH_ACE0_SIZE = 0x0000FFFF +const APB_CTRL_FLASH_ACE0_SIZE_V = 0xFFFF +const APB_CTRL_FLASH_ACE0_SIZE_S = 0 +const APB_CTRL_FLASH_ACE1_SIZE = 0x0000FFFF +const APB_CTRL_FLASH_ACE1_SIZE_V = 0xFFFF +const APB_CTRL_FLASH_ACE1_SIZE_S = 0 +const APB_CTRL_FLASH_ACE2_SIZE = 0x0000FFFF +const APB_CTRL_FLASH_ACE2_SIZE_V = 0xFFFF +const APB_CTRL_FLASH_ACE2_SIZE_S = 0 +const APB_CTRL_FLASH_ACE3_SIZE = 0x0000FFFF +const APB_CTRL_FLASH_ACE3_SIZE_V = 0xFFFF +const APB_CTRL_FLASH_ACE3_SIZE_S = 0 +const APB_CTRL_SRAM_ACE0_ATTR = 0x000001FF +const APB_CTRL_SRAM_ACE0_ATTR_V = 0x1FF +const APB_CTRL_SRAM_ACE0_ATTR_S = 0 +const APB_CTRL_SRAM_ACE1_ATTR = 0x000001FF +const APB_CTRL_SRAM_ACE1_ATTR_V = 0x1FF +const APB_CTRL_SRAM_ACE1_ATTR_S = 0 +const APB_CTRL_SRAM_ACE2_ATTR = 0x000001FF +const APB_CTRL_SRAM_ACE2_ATTR_V = 0x1FF +const APB_CTRL_SRAM_ACE2_ATTR_S = 0 +const APB_CTRL_SRAM_ACE3_ATTR = 0x000001FF +const APB_CTRL_SRAM_ACE3_ATTR_V = 0x1FF +const APB_CTRL_SRAM_ACE3_ATTR_S = 0 +const APB_CTRL_SRAM_ACE0_ADDR_S = 0xFFFFFFFF +const APB_CTRL_SRAM_ACE0_ADDR_S_V = 0xFFFFFFFF +const APB_CTRL_SRAM_ACE0_ADDR_S_S = 0 +const APB_CTRL_SRAM_ACE1_ADDR_S = 0xFFFFFFFF +const APB_CTRL_SRAM_ACE1_ADDR_S_V = 0xFFFFFFFF +const APB_CTRL_SRAM_ACE1_ADDR_S_S = 0 +const APB_CTRL_SRAM_ACE2_ADDR_S = 0xFFFFFFFF +const APB_CTRL_SRAM_ACE2_ADDR_S_V = 0xFFFFFFFF +const APB_CTRL_SRAM_ACE2_ADDR_S_S = 0 +const APB_CTRL_SRAM_ACE3_ADDR_S = 0xFFFFFFFF +const APB_CTRL_SRAM_ACE3_ADDR_S_V = 0xFFFFFFFF +const APB_CTRL_SRAM_ACE3_ADDR_S_S = 0 +const APB_CTRL_SRAM_ACE0_SIZE = 0x0000FFFF +const APB_CTRL_SRAM_ACE0_SIZE_V = 0xFFFF +const APB_CTRL_SRAM_ACE0_SIZE_S = 0 +const APB_CTRL_SRAM_ACE1_SIZE = 0x0000FFFF +const APB_CTRL_SRAM_ACE1_SIZE_V = 0xFFFF +const APB_CTRL_SRAM_ACE1_SIZE_S = 0 +const APB_CTRL_SRAM_ACE2_SIZE = 0x0000FFFF +const APB_CTRL_SRAM_ACE2_SIZE_V = 0xFFFF +const APB_CTRL_SRAM_ACE2_SIZE_S = 0 +const APB_CTRL_SRAM_ACE3_SIZE = 0x0000FFFF +const APB_CTRL_SRAM_ACE3_SIZE_V = 0xFFFF +const APB_CTRL_SRAM_ACE3_SIZE_S = 0 +const APB_CTRL_SPI_MEM_REJECT_CDE = 0x0000001F +const APB_CTRL_SPI_MEM_REJECT_CDE_V = 0x1F +const APB_CTRL_SPI_MEM_REJECT_CDE_S = 2 +const APB_CTRL_SPI_MEM_REJECT_CLR_V = 0x1 +const APB_CTRL_SPI_MEM_REJECT_CLR_S = 1 +const APB_CTRL_SPI_MEM_REJECT_INT_V = 0x1 +const APB_CTRL_SPI_MEM_REJECT_INT_S = 0 +const APB_CTRL_SPI_MEM_REJECT_ADDR = 0xFFFFFFFF +const APB_CTRL_SPI_MEM_REJECT_ADDR_V = 0xFFFFFFFF +const APB_CTRL_SPI_MEM_REJECT_ADDR_S = 0 +const APB_CTRL_SDIO_WIN_ACCESS_EN_V = 0x1 +const APB_CTRL_SDIO_WIN_ACCESS_EN_S = 0 +const APB_CTRL_REDCY_ANDOR_V = 0x1 +const APB_CTRL_REDCY_ANDOR_S = 31 +const APB_CTRL_REDCY_SIG0 = 0x7FFFFFFF +const APB_CTRL_REDCY_SIG0_V = 0x7FFFFFFF +const APB_CTRL_REDCY_SIG0_S = 0 +const APB_CTRL_REDCY_NANDOR_V = 0x1 +const APB_CTRL_REDCY_NANDOR_S = 31 +const APB_CTRL_REDCY_SIG1 = 0x7FFFFFFF +const APB_CTRL_REDCY_SIG1_V = 0x7FFFFFFF +const APB_CTRL_REDCY_SIG1_S = 0 +const APB_CTRL_FREQ_MEM_FORCE_PD_V = 0x1 +const APB_CTRL_FREQ_MEM_FORCE_PD_S = 7 +const APB_CTRL_FREQ_MEM_FORCE_PU_V = 0x1 +const APB_CTRL_FREQ_MEM_FORCE_PU_S = 6 +const APB_CTRL_DC_MEM_FORCE_PD_V = 0x1 +const APB_CTRL_DC_MEM_FORCE_PD_S = 5 +const APB_CTRL_DC_MEM_FORCE_PU_V = 0x1 +const APB_CTRL_DC_MEM_FORCE_PU_S = 4 +const APB_CTRL_PBUS_MEM_FORCE_PD_V = 0x1 +const APB_CTRL_PBUS_MEM_FORCE_PD_S = 3 +const APB_CTRL_PBUS_MEM_FORCE_PU_V = 0x1 +const APB_CTRL_PBUS_MEM_FORCE_PU_S = 2 +const APB_CTRL_AGC_MEM_FORCE_PD_V = 0x1 +const APB_CTRL_AGC_MEM_FORCE_PD_S = 1 +const APB_CTRL_AGC_MEM_FORCE_PU_V = 0x1 +const APB_CTRL_AGC_MEM_FORCE_PU_S = 0 +const APB_CTRL_SRAM_PAGE_SIZE = 0x00000003 +const APB_CTRL_SRAM_PAGE_SIZE_V = 0x3 +const APB_CTRL_SRAM_PAGE_SIZE_S = 20 +const APB_CTRL_FLASH_PAGE_SIZE = 0x00000003 +const APB_CTRL_FLASH_PAGE_SIZE_V = 0x3 +const APB_CTRL_FLASH_PAGE_SIZE_S = 18 +const APB_CTRL_SRAM_CLKGATE_FORCE_ON = 0x000007FF +const APB_CTRL_SRAM_CLKGATE_FORCE_ON_V = 0x7FF +const APB_CTRL_SRAM_CLKGATE_FORCE_ON_S = 3 +const APB_CTRL_ROM_CLKGATE_FORCE_ON = 0x00000007 +const APB_CTRL_ROM_CLKGATE_FORCE_ON_V = 0x7 +const APB_CTRL_ROM_CLKGATE_FORCE_ON_S = 0 +const APB_CTRL_SRAM_POWER_DOWN = 0x000007FF +const APB_CTRL_SRAM_POWER_DOWN_V = 0x7FF +const APB_CTRL_SRAM_POWER_DOWN_S = 3 +const APB_CTRL_ROM_POWER_DOWN = 0x00000007 +const APB_CTRL_ROM_POWER_DOWN_V = 0x7 +const APB_CTRL_ROM_POWER_DOWN_S = 0 +const APB_CTRL_SRAM_POWER_UP = 0x000007FF +const APB_CTRL_SRAM_POWER_UP_V = 0x7FF +const APB_CTRL_SRAM_POWER_UP_S = 3 +const APB_CTRL_ROM_POWER_UP = 0x00000007 +const APB_CTRL_ROM_POWER_UP_V = 0x7 +const APB_CTRL_ROM_POWER_UP_S = 0 +const APB_CTRL_NOBYPASS_CPU_ISO_RST_V = 0x1 +const APB_CTRL_NOBYPASS_CPU_ISO_RST_S = 27 +const APB_CTRL_RETENTION_CPU_LINK_ADDR = 0x07FFFFFF +const APB_CTRL_RETENTION_CPU_LINK_ADDR_V = 0x7FFFFFF +const APB_CTRL_RETENTION_CPU_LINK_ADDR_S = 0 +const APB_CTRL_RETENTION_TAG_LINK_ADDR = 0x07FFFFFF +const APB_CTRL_RETENTION_TAG_LINK_ADDR_V = 0x7FFFFFF +const APB_CTRL_RETENTION_TAG_LINK_ADDR_S = 0 +const APB_CTRL_RET_ICACHE_ENABLE_V = 0x1 +const APB_CTRL_RET_ICACHE_ENABLE_S = 31 +const APB_CTRL_RET_ICACHE_START_POINT = 0x000000FF +const APB_CTRL_RET_ICACHE_START_POINT_V = 0xFF +const APB_CTRL_RET_ICACHE_START_POINT_S = 22 +const APB_CTRL_RET_ICACHE_VLD_SIZE = 0x000000FF +const APB_CTRL_RET_ICACHE_VLD_SIZE_V = 0xFF +const APB_CTRL_RET_ICACHE_VLD_SIZE_S = 13 +const APB_CTRL_RET_ICACHE_SIZE = 0x000000FF +const APB_CTRL_RET_ICACHE_SIZE_V = 0xFF +const APB_CTRL_RET_ICACHE_SIZE_S = 4 +const APB_CTRL_RET_DCACHE_ENABLE_V = 0x1 +const APB_CTRL_RET_DCACHE_ENABLE_S = 31 +const APB_CTRL_RET_DCACHE_START_POINT = 0x000001FF +const APB_CTRL_RET_DCACHE_START_POINT_V = 0x1FF +const APB_CTRL_RET_DCACHE_START_POINT_S = 22 +const APB_CTRL_RET_DCACHE_VLD_SIZE = 0x000001FF +const APB_CTRL_RET_DCACHE_VLD_SIZE_V = 0x1FF +const APB_CTRL_RET_DCACHE_VLD_SIZE_S = 13 +const APB_CTRL_RET_DCACHE_SIZE = 0x000001FF +const APB_CTRL_RET_DCACHE_SIZE_V = 0x1FF +const APB_CTRL_RET_DCACHE_SIZE_S = 4 +const APB_CTRL_RETENTION_INV_CFG = 0xFFFFFFFF +const APB_CTRL_RETENTION_INV_CFG_V = 0xFFFFFFFF +const APB_CTRL_RETENTION_INV_CFG_S = 0 +const APB_CTRL_RETENTION_DISABLE_V = 0x1 +const APB_CTRL_RETENTION_DISABLE_S = 0 +const APB_CTRL_DATE = 0xFFFFFFFF +const APB_CTRL_DATE_V = 0xFFFFFFFF +const APB_CTRL_DATE_S = 0 diff --git a/esp32/apb_ctrl_struct.go b/esp32/apb_ctrl_struct.go new file mode 100644 index 00000000..57c155ee --- /dev/null +++ b/esp32/apb_ctrl_struct.go @@ -0,0 +1,338 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type ApbCtrlDevS struct { + ClkConf struct { + Val c.Uint32T + } + TickConf struct { + Val c.Uint32T + } + ClkOutEn struct { + Val c.Uint32T + } + WifiBbCfg c.Uint32T + WifiBbCfg2 c.Uint32T + WifiClkEn c.Uint32T + WifiRstEn c.Uint32T + HostInfSel struct { + Val c.Uint32T + } + ExtMemPmsLock struct { + Val c.Uint32T + } + ExtMemWritebackBypass struct { + Val c.Uint32T + } + FlashAce0Attr struct { + Val c.Uint32T + } + FlashAce1Attr struct { + Val c.Uint32T + } + FlashAce2Attr struct { + Val c.Uint32T + } + FlashAce3Attr struct { + Val c.Uint32T + } + FlashAce0Addr c.Uint32T + FlashAce1Addr c.Uint32T + FlashAce2Addr c.Uint32T + FlashAce3Addr c.Uint32T + FlashAce0Size struct { + Val c.Uint32T + } + FlashAce1Size struct { + Val c.Uint32T + } + FlashAce2Size struct { + Val c.Uint32T + } + FlashAce3Size struct { + Val c.Uint32T + } + SramAce0Attr struct { + Val c.Uint32T + } + SramAce1Attr struct { + Val c.Uint32T + } + SramAce2Attr struct { + Val c.Uint32T + } + SramAce3Attr struct { + Val c.Uint32T + } + SramAce0Addr c.Uint32T + SramAce1Addr c.Uint32T + SramAce2Addr c.Uint32T + SramAce3Addr c.Uint32T + SramAce0Size struct { + Val c.Uint32T + } + SramAce1Size struct { + Val c.Uint32T + } + SramAce2Size struct { + Val c.Uint32T + } + SramAce3Size struct { + Val c.Uint32T + } + SpiMemPmsCtrl struct { + Val c.Uint32T + } + SpiMemRejectAddr c.Uint32T + SdioCtrl struct { + Val c.Uint32T + } + RedcySig0 struct { + Val c.Uint32T + } + RedcySig1 struct { + Val c.Uint32T + } + FrontEndMemPd struct { + Val c.Uint32T + } + SpiMemEccCtrl struct { + Val c.Uint32T + } + ReservedA4 c.Uint32T + ClkgateForceOn struct { + Val c.Uint32T + } + MemPowerDown struct { + Val c.Uint32T + } + MemPowerUp struct { + Val c.Uint32T + } + RetentionCtrl struct { + Val c.Uint32T + } + RetentionCtrl1 struct { + Val c.Uint32T + } + RetentionCtrl2 struct { + Val c.Uint32T + } + RetentionCtrl3 struct { + Val c.Uint32T + } + RetentionCtrl4 c.Uint32T + RetentionCtrl5 struct { + Val c.Uint32T + } + ReservedCc c.Uint32T + ReservedD0 c.Uint32T + ReservedD4 c.Uint32T + ReservedD8 c.Uint32T + ReservedDc c.Uint32T + ReservedE0 c.Uint32T + ReservedE4 c.Uint32T + ReservedE8 c.Uint32T + ReservedEc c.Uint32T + ReservedF0 c.Uint32T + ReservedF4 c.Uint32T + ReservedF8 c.Uint32T + ReservedFc c.Uint32T + Reserved100 c.Uint32T + Reserved104 c.Uint32T + Reserved108 c.Uint32T + Reserved10c c.Uint32T + Reserved110 c.Uint32T + Reserved114 c.Uint32T + Reserved118 c.Uint32T + Reserved11c c.Uint32T + Reserved120 c.Uint32T + Reserved124 c.Uint32T + Reserved128 c.Uint32T + Reserved12c c.Uint32T + Reserved130 c.Uint32T + Reserved134 c.Uint32T + Reserved138 c.Uint32T + Reserved13c c.Uint32T + Reserved140 c.Uint32T + Reserved144 c.Uint32T + Reserved148 c.Uint32T + Reserved14c c.Uint32T + Reserved150 c.Uint32T + Reserved154 c.Uint32T + Reserved158 c.Uint32T + Reserved15c c.Uint32T + Reserved160 c.Uint32T + Reserved164 c.Uint32T + Reserved168 c.Uint32T + Reserved16c c.Uint32T + Reserved170 c.Uint32T + Reserved174 c.Uint32T + Reserved178 c.Uint32T + Reserved17c c.Uint32T + Reserved180 c.Uint32T + Reserved184 c.Uint32T + Reserved188 c.Uint32T + Reserved18c c.Uint32T + Reserved190 c.Uint32T + Reserved194 c.Uint32T + Reserved198 c.Uint32T + Reserved19c c.Uint32T + Reserved1a0 c.Uint32T + Reserved1a4 c.Uint32T + Reserved1a8 c.Uint32T + Reserved1ac c.Uint32T + Reserved1b0 c.Uint32T + Reserved1b4 c.Uint32T + Reserved1b8 c.Uint32T + Reserved1bc c.Uint32T + Reserved1c0 c.Uint32T + Reserved1c4 c.Uint32T + Reserved1c8 c.Uint32T + Reserved1cc c.Uint32T + Reserved1d0 c.Uint32T + Reserved1d4 c.Uint32T + Reserved1d8 c.Uint32T + Reserved1dc c.Uint32T + Reserved1e0 c.Uint32T + Reserved1e4 c.Uint32T + Reserved1e8 c.Uint32T + Reserved1ec c.Uint32T + Reserved1f0 c.Uint32T + Reserved1f4 c.Uint32T + Reserved1f8 c.Uint32T + Reserved1fc c.Uint32T + Reserved200 c.Uint32T + Reserved204 c.Uint32T + Reserved208 c.Uint32T + Reserved20c c.Uint32T + Reserved210 c.Uint32T + Reserved214 c.Uint32T + Reserved218 c.Uint32T + Reserved21c c.Uint32T + Reserved220 c.Uint32T + Reserved224 c.Uint32T + Reserved228 c.Uint32T + Reserved22c c.Uint32T + Reserved230 c.Uint32T + Reserved234 c.Uint32T + Reserved238 c.Uint32T + Reserved23c c.Uint32T + Reserved240 c.Uint32T + Reserved244 c.Uint32T + Reserved248 c.Uint32T + Reserved24c c.Uint32T + Reserved250 c.Uint32T + Reserved254 c.Uint32T + Reserved258 c.Uint32T + Reserved25c c.Uint32T + Reserved260 c.Uint32T + Reserved264 c.Uint32T + Reserved268 c.Uint32T + Reserved26c c.Uint32T + Reserved270 c.Uint32T + Reserved274 c.Uint32T + Reserved278 c.Uint32T + Reserved27c c.Uint32T + Reserved280 c.Uint32T + Reserved284 c.Uint32T + Reserved288 c.Uint32T + Reserved28c c.Uint32T + Reserved290 c.Uint32T + Reserved294 c.Uint32T + Reserved298 c.Uint32T + Reserved29c c.Uint32T + Reserved2a0 c.Uint32T + Reserved2a4 c.Uint32T + Reserved2a8 c.Uint32T + Reserved2ac c.Uint32T + Reserved2b0 c.Uint32T + Reserved2b4 c.Uint32T + Reserved2b8 c.Uint32T + Reserved2bc c.Uint32T + Reserved2c0 c.Uint32T + Reserved2c4 c.Uint32T + Reserved2c8 c.Uint32T + Reserved2cc c.Uint32T + Reserved2d0 c.Uint32T + Reserved2d4 c.Uint32T + Reserved2d8 c.Uint32T + Reserved2dc c.Uint32T + Reserved2e0 c.Uint32T + Reserved2e4 c.Uint32T + Reserved2e8 c.Uint32T + Reserved2ec c.Uint32T + Reserved2f0 c.Uint32T + Reserved2f4 c.Uint32T + Reserved2f8 c.Uint32T + Reserved2fc c.Uint32T + Reserved300 c.Uint32T + Reserved304 c.Uint32T + Reserved308 c.Uint32T + Reserved30c c.Uint32T + Reserved310 c.Uint32T + Reserved314 c.Uint32T + Reserved318 c.Uint32T + Reserved31c c.Uint32T + Reserved320 c.Uint32T + Reserved324 c.Uint32T + Reserved328 c.Uint32T + Reserved32c c.Uint32T + Reserved330 c.Uint32T + Reserved334 c.Uint32T + Reserved338 c.Uint32T + Reserved33c c.Uint32T + Reserved340 c.Uint32T + Reserved344 c.Uint32T + Reserved348 c.Uint32T + Reserved34c c.Uint32T + Reserved350 c.Uint32T + Reserved354 c.Uint32T + Reserved358 c.Uint32T + Reserved35c c.Uint32T + Reserved360 c.Uint32T + Reserved364 c.Uint32T + Reserved368 c.Uint32T + Reserved36c c.Uint32T + Reserved370 c.Uint32T + Reserved374 c.Uint32T + Reserved378 c.Uint32T + Reserved37c c.Uint32T + Reserved380 c.Uint32T + Reserved384 c.Uint32T + Reserved388 c.Uint32T + Reserved38c c.Uint32T + Reserved390 c.Uint32T + Reserved394 c.Uint32T + Reserved398 c.Uint32T + Reserved39c c.Uint32T + Reserved3a0 c.Uint32T + Reserved3a4 c.Uint32T + Reserved3a8 c.Uint32T + Reserved3ac c.Uint32T + Reserved3b0 c.Uint32T + Reserved3b4 c.Uint32T + Reserved3b8 c.Uint32T + Reserved3bc c.Uint32T + Reserved3c0 c.Uint32T + Reserved3c4 c.Uint32T + Reserved3c8 c.Uint32T + Reserved3cc c.Uint32T + Reserved3d0 c.Uint32T + Reserved3d4 c.Uint32T + Reserved3d8 c.Uint32T + Reserved3dc c.Uint32T + Reserved3e0 c.Uint32T + Reserved3e4 c.Uint32T + Reserved3e8 c.Uint32T + Reserved3ec c.Uint32T + Reserved3f0 c.Uint32T + Reserved3f4 c.Uint32T + Reserved3f8 c.Uint32T + Date c.Uint32T +} +type ApbCtrlDevT ApbCtrlDevS diff --git a/esp32/apb_saradc_reg.go b/esp32/apb_saradc_reg.go new file mode 100644 index 00000000..4cca6809 --- /dev/null +++ b/esp32/apb_saradc_reg.go @@ -0,0 +1,232 @@ +package freertos + +import _ "unsafe" + +const APB_SARADC_WAIT_ARB_CYCLE = 0x00000003 +const APB_SARADC_WAIT_ARB_CYCLE_V = 0x3 +const APB_SARADC_WAIT_ARB_CYCLE_S = 30 +const APB_SARADC_XPD_SAR_FORCE = 0x00000003 +const APB_SARADC_XPD_SAR_FORCE_V = 0x3 +const APB_SARADC_XPD_SAR_FORCE_S = 27 +const APB_SARADC_DATA_TO_I2S_V = 0x1 +const APB_SARADC_DATA_TO_I2S_S = 26 +const APB_SARADC_DATA_SAR_SEL_V = 0x1 +const APB_SARADC_DATA_SAR_SEL_S = 25 +const APB_SARADC_SAR2_PATT_P_CLEAR_V = 0x1 +const APB_SARADC_SAR2_PATT_P_CLEAR_S = 24 +const APB_SARADC_SAR1_PATT_P_CLEAR_V = 0x1 +const APB_SARADC_SAR1_PATT_P_CLEAR_S = 23 +const APB_SARADC_SAR2_PATT_LEN = 0x0000000F +const APB_SARADC_SAR2_PATT_LEN_V = 0xF +const APB_SARADC_SAR2_PATT_LEN_S = 19 +const APB_SARADC_SAR1_PATT_LEN = 0x0000000F +const APB_SARADC_SAR1_PATT_LEN_V = 0xF +const APB_SARADC_SAR1_PATT_LEN_S = 15 +const APB_SARADC_SAR_CLK_DIV = 0x000000FF +const APB_SARADC_SAR_CLK_DIV_V = 0xFF +const APB_SARADC_SAR_CLK_DIV_S = 7 +const APB_SARADC_SAR_CLK_GATED_V = 0x1 +const APB_SARADC_SAR_CLK_GATED_S = 6 +const APB_SARADC_SAR_SEL_V = 0x1 +const APB_SARADC_SAR_SEL_S = 5 +const APB_SARADC_WORK_MODE = 0x00000003 +const APB_SARADC_WORK_MODE_V = 0x3 +const APB_SARADC_WORK_MODE_S = 3 +const APB_SARADC_START_V = 0x1 +const APB_SARADC_START_S = 1 +const APB_SARADC_START_FORCE_V = 0x1 +const APB_SARADC_START_FORCE_S = 0 +const APB_SARADC_TIMER_EN_V = 0x1 +const APB_SARADC_TIMER_EN_S = 24 +const APB_SARADC_TIMER_TARGET = 0x00000FFF +const APB_SARADC_TIMER_TARGET_V = 0xFFF +const APB_SARADC_TIMER_TARGET_S = 12 +const APB_SARADC_TIMER_SEL_V = 0x1 +const APB_SARADC_TIMER_SEL_S = 11 +const APB_SARADC_SAR2_INV_V = 0x1 +const APB_SARADC_SAR2_INV_S = 10 +const APB_SARADC_SAR1_INV_V = 0x1 +const APB_SARADC_SAR1_INV_S = 9 +const APB_SARADC_MAX_MEAS_NUM = 0x000000FF +const APB_SARADC_MAX_MEAS_NUM_V = 0xFF +const APB_SARADC_MAX_MEAS_NUM_S = 1 +const APB_SARADC_MEAS_NUM_LIMIT_V = 0x1 +const APB_SARADC_MEAS_NUM_LIMIT_S = 0 +const APB_SARADC_FILTER_FACTOR0 = 0x00000007 +const APB_SARADC_FILTER_FACTOR0_V = 0x7 +const APB_SARADC_FILTER_FACTOR0_S = 29 +const APB_SARADC_FILTER_FACTOR1 = 0x00000007 +const APB_SARADC_FILTER_FACTOR1_V = 0x7 +const APB_SARADC_FILTER_FACTOR1_S = 26 +const APB_SARADC_STANDBY_WAIT = 0x000000FF +const APB_SARADC_STANDBY_WAIT_V = 0xFF +const APB_SARADC_STANDBY_WAIT_S = 16 +const APB_SARADC_RSTB_WAIT = 0x000000FF +const APB_SARADC_RSTB_WAIT_V = 0xFF +const APB_SARADC_RSTB_WAIT_S = 8 +const APB_SARADC_XPD_WAIT = 0x000000FF +const APB_SARADC_XPD_WAIT_V = 0xFF +const APB_SARADC_XPD_WAIT_S = 0 +const APB_SARADC_SAR1_STATUS = 0xFFFFFFFF +const APB_SARADC_SAR1_STATUS_V = 0xFFFFFFFF +const APB_SARADC_SAR1_STATUS_S = 0 +const APB_SARADC_SAR2_STATUS = 0xFFFFFFFF +const APB_SARADC_SAR2_STATUS_V = 0xFFFFFFFF +const APB_SARADC_SAR2_STATUS_S = 0 +const APB_SARADC_SAR1_PATT_TAB1 = 0x00FFFFFF +const APB_SARADC_SAR1_PATT_TAB1_V = 0xFFFFFF +const APB_SARADC_SAR1_PATT_TAB1_S = 0 +const APB_SARADC_SAR1_PATT_TAB2 = 0x00FFFFFF +const APB_SARADC_SAR1_PATT_TAB2_V = 0xFFFFFF +const APB_SARADC_SAR1_PATT_TAB2_S = 0 +const APB_SARADC_SAR1_PATT_TAB3 = 0x00FFFFFF +const APB_SARADC_SAR1_PATT_TAB3_V = 0xFFFFFF +const APB_SARADC_SAR1_PATT_TAB3_S = 0 +const APB_SARADC_SAR1_PATT_TAB4 = 0x00FFFFFF +const APB_SARADC_SAR1_PATT_TAB4_V = 0xFFFFFF +const APB_SARADC_SAR1_PATT_TAB4_S = 0 +const APB_SARADC_SAR2_PATT_TAB1 = 0x00FFFFFF +const APB_SARADC_SAR2_PATT_TAB1_V = 0xFFFFFF +const APB_SARADC_SAR2_PATT_TAB1_S = 0 +const APB_SARADC_SAR2_PATT_TAB2 = 0x00FFFFFF +const APB_SARADC_SAR2_PATT_TAB2_V = 0xFFFFFF +const APB_SARADC_SAR2_PATT_TAB2_S = 0 +const APB_SARADC_SAR2_PATT_TAB3 = 0x00FFFFFF +const APB_SARADC_SAR2_PATT_TAB3_V = 0xFFFFFF +const APB_SARADC_SAR2_PATT_TAB3_S = 0 +const APB_SARADC_SAR2_PATT_TAB4 = 0x00FFFFFF +const APB_SARADC_SAR2_PATT_TAB4_V = 0xFFFFFF +const APB_SARADC_SAR2_PATT_TAB4_S = 0 +const APB_SARADC_ADC_ARB_FIX_PRIORITY_V = 0x1 +const APB_SARADC_ADC_ARB_FIX_PRIORITY_S = 12 +const APB_SARADC_ADC_ARB_WIFI_PRIORITY = 0x00000003 +const APB_SARADC_ADC_ARB_WIFI_PRIORITY_V = 0x3 +const APB_SARADC_ADC_ARB_WIFI_PRIORITY_S = 10 +const APB_SARADC_ADC_ARB_RTC_PRIORITY = 0x00000003 +const APB_SARADC_ADC_ARB_RTC_PRIORITY_V = 0x3 +const APB_SARADC_ADC_ARB_RTC_PRIORITY_S = 8 +const APB_SARADC_ADC_ARB_APB_PRIORITY = 0x00000003 +const APB_SARADC_ADC_ARB_APB_PRIORITY_V = 0x3 +const APB_SARADC_ADC_ARB_APB_PRIORITY_S = 6 +const APB_SARADC_ADC_ARB_GRANT_FORCE_V = 0x1 +const APB_SARADC_ADC_ARB_GRANT_FORCE_S = 5 +const APB_SARADC_ADC_ARB_WIFI_FORCE_V = 0x1 +const APB_SARADC_ADC_ARB_WIFI_FORCE_S = 4 +const APB_SARADC_ADC_ARB_RTC_FORCE_V = 0x1 +const APB_SARADC_ADC_ARB_RTC_FORCE_S = 3 +const APB_SARADC_ADC_ARB_APB_FORCE_V = 0x1 +const APB_SARADC_ADC_ARB_APB_FORCE_S = 2 +const APB_SARADC_FILTER_RESET_V = 0x1 +const APB_SARADC_FILTER_RESET_S = 31 +const APB_SARADC_FILTER_CHANNEL0 = 0x0000001F +const APB_SARADC_FILTER_CHANNEL0_V = 0x1F +const APB_SARADC_FILTER_CHANNEL0_S = 19 +const APB_SARADC_FILTER_CHANNEL1 = 0x0000001F +const APB_SARADC_FILTER_CHANNEL1_V = 0x1F +const APB_SARADC_FILTER_CHANNEL1_S = 14 +const APB_SARADC_ADC1_DATA = 0x0001FFFF +const APB_SARADC_ADC1_DATA_V = 0x1FFFF +const APB_SARADC_ADC1_DATA_S = 0 +const APB_SARADC_THRES0_LOW = 0x00001FFF +const APB_SARADC_THRES0_LOW_V = 0x1FFF +const APB_SARADC_THRES0_LOW_S = 18 +const APB_SARADC_THRES0_HIGH = 0x00001FFF +const APB_SARADC_THRES0_HIGH_V = 0x1FFF +const APB_SARADC_THRES0_HIGH_S = 5 +const APB_SARADC_THRES0_CHANNEL = 0x0000001F +const APB_SARADC_THRES0_CHANNEL_V = 0x1F +const APB_SARADC_THRES0_CHANNEL_S = 0 +const APB_SARADC_THRES1_LOW = 0x00001FFF +const APB_SARADC_THRES1_LOW_V = 0x1FFF +const APB_SARADC_THRES1_LOW_S = 18 +const APB_SARADC_THRES1_HIGH = 0x00001FFF +const APB_SARADC_THRES1_HIGH_V = 0x1FFF +const APB_SARADC_THRES1_HIGH_S = 5 +const APB_SARADC_THRES1_CHANNEL = 0x0000001F +const APB_SARADC_THRES1_CHANNEL_V = 0x1F +const APB_SARADC_THRES1_CHANNEL_S = 0 +const APB_SARADC_THRES0_EN_V = 0x1 +const APB_SARADC_THRES0_EN_S = 31 +const APB_SARADC_THRES1_EN_V = 0x1 +const APB_SARADC_THRES1_EN_S = 30 +const APB_SARADC_THRES2_EN_V = 0x1 +const APB_SARADC_THRES2_EN_S = 29 +const APB_SARADC_THRES3_EN_V = 0x1 +const APB_SARADC_THRES3_EN_S = 28 +const APB_SARADC_THRES_ALL_EN_V = 0x1 +const APB_SARADC_THRES_ALL_EN_S = 27 +const APB_SARADC_ADC1_DONE_INT_ENA_V = 0x1 +const APB_SARADC_ADC1_DONE_INT_ENA_S = 31 +const APB_SARADC_ADC2_DONE_INT_ENA_V = 0x1 +const APB_SARADC_ADC2_DONE_INT_ENA_S = 30 +const APB_SARADC_THRES0_HIGH_INT_ENA_V = 0x1 +const APB_SARADC_THRES0_HIGH_INT_ENA_S = 29 +const APB_SARADC_THRES1_HIGH_INT_ENA_V = 0x1 +const APB_SARADC_THRES1_HIGH_INT_ENA_S = 28 +const APB_SARADC_THRES0_LOW_INT_ENA_V = 0x1 +const APB_SARADC_THRES0_LOW_INT_ENA_S = 27 +const APB_SARADC_THRES1_LOW_INT_ENA_V = 0x1 +const APB_SARADC_THRES1_LOW_INT_ENA_S = 26 +const APB_SARADC_ADC1_DONE_INT_RAW_V = 0x1 +const APB_SARADC_ADC1_DONE_INT_RAW_S = 31 +const APB_SARADC_ADC2_DONE_INT_RAW_V = 0x1 +const APB_SARADC_ADC2_DONE_INT_RAW_S = 30 +const APB_SARADC_THRES0_HIGH_INT_RAW_V = 0x1 +const APB_SARADC_THRES0_HIGH_INT_RAW_S = 29 +const APB_SARADC_THRES1_HIGH_INT_RAW_V = 0x1 +const APB_SARADC_THRES1_HIGH_INT_RAW_S = 28 +const APB_SARADC_THRES0_LOW_INT_RAW_V = 0x1 +const APB_SARADC_THRES0_LOW_INT_RAW_S = 27 +const APB_SARADC_THRES1_LOW_INT_RAW_V = 0x1 +const APB_SARADC_THRES1_LOW_INT_RAW_S = 26 +const APB_SARADC_ADC1_DONE_INT_ST_V = 0x1 +const APB_SARADC_ADC1_DONE_INT_ST_S = 31 +const APB_SARADC_ADC2_DONE_INT_ST_V = 0x1 +const APB_SARADC_ADC2_DONE_INT_ST_S = 30 +const APB_SARADC_THRES0_HIGH_INT_ST_V = 0x1 +const APB_SARADC_THRES0_HIGH_INT_ST_S = 29 +const APB_SARADC_THRES1_HIGH_INT_ST_V = 0x1 +const APB_SARADC_THRES1_HIGH_INT_ST_S = 28 +const APB_SARADC_THRES0_LOW_INT_ST_V = 0x1 +const APB_SARADC_THRES0_LOW_INT_ST_S = 27 +const APB_SARADC_THRES1_LOW_INT_ST_V = 0x1 +const APB_SARADC_THRES1_LOW_INT_ST_S = 26 +const APB_SARADC_ADC1_DONE_INT_CLR_V = 0x1 +const APB_SARADC_ADC1_DONE_INT_CLR_S = 31 +const APB_SARADC_ADC2_DONE_INT_CLR_V = 0x1 +const APB_SARADC_ADC2_DONE_INT_CLR_S = 30 +const APB_SARADC_THRES0_HIGH_INT_CLR_V = 0x1 +const APB_SARADC_THRES0_HIGH_INT_CLR_S = 29 +const APB_SARADC_THRES1_HIGH_INT_CLR_V = 0x1 +const APB_SARADC_THRES1_HIGH_INT_CLR_S = 28 +const APB_SARADC_THRES0_LOW_INT_CLR_V = 0x1 +const APB_SARADC_THRES0_LOW_INT_CLR_S = 27 +const APB_SARADC_THRES1_LOW_INT_CLR_V = 0x1 +const APB_SARADC_THRES1_LOW_INT_CLR_S = 26 +const APB_SARADC_APB_ADC_TRANS_V = 0x1 +const APB_SARADC_APB_ADC_TRANS_S = 31 +const APB_SARADC_APB_ADC_RESET_FSM_V = 0x1 +const APB_SARADC_APB_ADC_RESET_FSM_S = 30 +const APB_SARADC_APB_ADC_EOF_NUM = 0x0000FFFF +const APB_SARADC_APB_ADC_EOF_NUM_V = 0xFFFF +const APB_SARADC_APB_ADC_EOF_NUM_S = 0 +const APB_SARADC_CLK_SEL = 0x00000003 +const APB_SARADC_CLK_SEL_V = 0x3 +const APB_SARADC_CLK_SEL_S = 21 +const APB_SARADC_CLK_EN_V = 0x1 +const APB_SARADC_CLK_EN_S = 20 +const APB_SARADC_CLKM_DIV_A = 0x0000003F +const APB_SARADC_CLKM_DIV_A_V = 0x3F +const APB_SARADC_CLKM_DIV_A_S = 14 +const APB_SARADC_CLKM_DIV_B = 0x0000003F +const APB_SARADC_CLKM_DIV_B_V = 0x3F +const APB_SARADC_CLKM_DIV_B_S = 8 +const APB_SARADC_CLKM_DIV_NUM = 0x000000FF +const APB_SARADC_CLKM_DIV_NUM_V = 0xFF +const APB_SARADC_CLKM_DIV_NUM_S = 0 +const APB_SARADC_ADC2_DATA = 0x0001FFFF +const APB_SARADC_ADC2_DATA_V = 0x1FFFF +const APB_SARADC_ADC2_DATA_S = 0 +const APB_SARADC_APB_CTRL_DATE = 0xFFFFFFFF +const APB_SARADC_APB_CTRL_DATE_V = 0xFFFFFFFF +const APB_SARADC_APB_CTRL_DATE_S = 0 diff --git a/esp32/apb_saradc_struct.go b/esp32/apb_saradc_struct.go new file mode 100644 index 00000000..5a90f564 --- /dev/null +++ b/esp32/apb_saradc_struct.go @@ -0,0 +1,298 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type ApbSaradcDevS struct { + Ctrl struct { + Val c.Uint32T + } + Ctrl2 struct { + Val c.Uint32T + } + FilterCtrl1 struct { + Val c.Uint32T + } + FsmWait struct { + Val c.Uint32T + } + Sar1Status c.Uint32T + Sar2Status c.Uint32T + Sar1PattTab [4]struct { + Val c.Uint32T + } + Sar2PattTab [4]struct { + Val c.Uint32T + } + ApbAdcArbCtrl struct { + Val c.Uint32T + } + FilterCtrl0 struct { + Val c.Uint32T + } + ApbSaradc1DataStatus struct { + Val c.Uint32T + } + Thres0Ctrl struct { + Val c.Uint32T + } + Thres1Ctrl struct { + Val c.Uint32T + } + Reserved4c c.Uint32T + Reserved50 c.Uint32T + Reserved54 c.Uint32T + ThresCtrl struct { + Val c.Uint32T + } + IntEna struct { + Val c.Uint32T + } + IntRaw struct { + Val c.Uint32T + } + IntSt struct { + Val c.Uint32T + } + IntClr struct { + Val c.Uint32T + } + DmaConf struct { + Val c.Uint32T + } + ApbAdcClkmConf struct { + Val c.Uint32T + } + Reserved74 c.Uint32T + ApbSaradc2DataStatus struct { + Val c.Uint32T + } + Reserved7c c.Uint32T + Reserved80 c.Uint32T + Reserved84 c.Uint32T + Reserved88 c.Uint32T + Reserved8c c.Uint32T + Reserved90 c.Uint32T + Reserved94 c.Uint32T + Reserved98 c.Uint32T + Reserved9c c.Uint32T + ReservedA0 c.Uint32T + ReservedA4 c.Uint32T + ReservedA8 c.Uint32T + ReservedAc c.Uint32T + ReservedB0 c.Uint32T + ReservedB4 c.Uint32T + ReservedB8 c.Uint32T + ReservedBc c.Uint32T + ReservedC0 c.Uint32T + ReservedC4 c.Uint32T + ReservedC8 c.Uint32T + ReservedCc c.Uint32T + ReservedD0 c.Uint32T + ReservedD4 c.Uint32T + ReservedD8 c.Uint32T + ReservedDc c.Uint32T + ReservedE0 c.Uint32T + ReservedE4 c.Uint32T + ReservedE8 c.Uint32T + ReservedEc c.Uint32T + ReservedF0 c.Uint32T + ReservedF4 c.Uint32T + ReservedF8 c.Uint32T + ReservedFc c.Uint32T + Reserved100 c.Uint32T + Reserved104 c.Uint32T + Reserved108 c.Uint32T + Reserved10c c.Uint32T + Reserved110 c.Uint32T + Reserved114 c.Uint32T + Reserved118 c.Uint32T + Reserved11c c.Uint32T + Reserved120 c.Uint32T + Reserved124 c.Uint32T + Reserved128 c.Uint32T + Reserved12c c.Uint32T + Reserved130 c.Uint32T + Reserved134 c.Uint32T + Reserved138 c.Uint32T + Reserved13c c.Uint32T + Reserved140 c.Uint32T + Reserved144 c.Uint32T + Reserved148 c.Uint32T + Reserved14c c.Uint32T + Reserved150 c.Uint32T + Reserved154 c.Uint32T + Reserved158 c.Uint32T + Reserved15c c.Uint32T + Reserved160 c.Uint32T + Reserved164 c.Uint32T + Reserved168 c.Uint32T + Reserved16c c.Uint32T + Reserved170 c.Uint32T + Reserved174 c.Uint32T + Reserved178 c.Uint32T + Reserved17c c.Uint32T + Reserved180 c.Uint32T + Reserved184 c.Uint32T + Reserved188 c.Uint32T + Reserved18c c.Uint32T + Reserved190 c.Uint32T + Reserved194 c.Uint32T + Reserved198 c.Uint32T + Reserved19c c.Uint32T + Reserved1a0 c.Uint32T + Reserved1a4 c.Uint32T + Reserved1a8 c.Uint32T + Reserved1ac c.Uint32T + Reserved1b0 c.Uint32T + Reserved1b4 c.Uint32T + Reserved1b8 c.Uint32T + Reserved1bc c.Uint32T + Reserved1c0 c.Uint32T + Reserved1c4 c.Uint32T + Reserved1c8 c.Uint32T + Reserved1cc c.Uint32T + Reserved1d0 c.Uint32T + Reserved1d4 c.Uint32T + Reserved1d8 c.Uint32T + Reserved1dc c.Uint32T + Reserved1e0 c.Uint32T + Reserved1e4 c.Uint32T + Reserved1e8 c.Uint32T + Reserved1ec c.Uint32T + Reserved1f0 c.Uint32T + Reserved1f4 c.Uint32T + Reserved1f8 c.Uint32T + Reserved1fc c.Uint32T + Reserved200 c.Uint32T + Reserved204 c.Uint32T + Reserved208 c.Uint32T + Reserved20c c.Uint32T + Reserved210 c.Uint32T + Reserved214 c.Uint32T + Reserved218 c.Uint32T + Reserved21c c.Uint32T + Reserved220 c.Uint32T + Reserved224 c.Uint32T + Reserved228 c.Uint32T + Reserved22c c.Uint32T + Reserved230 c.Uint32T + Reserved234 c.Uint32T + Reserved238 c.Uint32T + Reserved23c c.Uint32T + Reserved240 c.Uint32T + Reserved244 c.Uint32T + Reserved248 c.Uint32T + Reserved24c c.Uint32T + Reserved250 c.Uint32T + Reserved254 c.Uint32T + Reserved258 c.Uint32T + Reserved25c c.Uint32T + Reserved260 c.Uint32T + Reserved264 c.Uint32T + Reserved268 c.Uint32T + Reserved26c c.Uint32T + Reserved270 c.Uint32T + Reserved274 c.Uint32T + Reserved278 c.Uint32T + Reserved27c c.Uint32T + Reserved280 c.Uint32T + Reserved284 c.Uint32T + Reserved288 c.Uint32T + Reserved28c c.Uint32T + Reserved290 c.Uint32T + Reserved294 c.Uint32T + Reserved298 c.Uint32T + Reserved29c c.Uint32T + Reserved2a0 c.Uint32T + Reserved2a4 c.Uint32T + Reserved2a8 c.Uint32T + Reserved2ac c.Uint32T + Reserved2b0 c.Uint32T + Reserved2b4 c.Uint32T + Reserved2b8 c.Uint32T + Reserved2bc c.Uint32T + Reserved2c0 c.Uint32T + Reserved2c4 c.Uint32T + Reserved2c8 c.Uint32T + Reserved2cc c.Uint32T + Reserved2d0 c.Uint32T + Reserved2d4 c.Uint32T + Reserved2d8 c.Uint32T + Reserved2dc c.Uint32T + Reserved2e0 c.Uint32T + Reserved2e4 c.Uint32T + Reserved2e8 c.Uint32T + Reserved2ec c.Uint32T + Reserved2f0 c.Uint32T + Reserved2f4 c.Uint32T + Reserved2f8 c.Uint32T + Reserved2fc c.Uint32T + Reserved300 c.Uint32T + Reserved304 c.Uint32T + Reserved308 c.Uint32T + Reserved30c c.Uint32T + Reserved310 c.Uint32T + Reserved314 c.Uint32T + Reserved318 c.Uint32T + Reserved31c c.Uint32T + Reserved320 c.Uint32T + Reserved324 c.Uint32T + Reserved328 c.Uint32T + Reserved32c c.Uint32T + Reserved330 c.Uint32T + Reserved334 c.Uint32T + Reserved338 c.Uint32T + Reserved33c c.Uint32T + Reserved340 c.Uint32T + Reserved344 c.Uint32T + Reserved348 c.Uint32T + Reserved34c c.Uint32T + Reserved350 c.Uint32T + Reserved354 c.Uint32T + Reserved358 c.Uint32T + Reserved35c c.Uint32T + Reserved360 c.Uint32T + Reserved364 c.Uint32T + Reserved368 c.Uint32T + Reserved36c c.Uint32T + Reserved370 c.Uint32T + Reserved374 c.Uint32T + Reserved378 c.Uint32T + Reserved37c c.Uint32T + Reserved380 c.Uint32T + Reserved384 c.Uint32T + Reserved388 c.Uint32T + Reserved38c c.Uint32T + Reserved390 c.Uint32T + Reserved394 c.Uint32T + Reserved398 c.Uint32T + Reserved39c c.Uint32T + Reserved3a0 c.Uint32T + Reserved3a4 c.Uint32T + Reserved3a8 c.Uint32T + Reserved3ac c.Uint32T + Reserved3b0 c.Uint32T + Reserved3b4 c.Uint32T + Reserved3b8 c.Uint32T + Reserved3bc c.Uint32T + Reserved3c0 c.Uint32T + Reserved3c4 c.Uint32T + Reserved3c8 c.Uint32T + Reserved3cc c.Uint32T + Reserved3d0 c.Uint32T + Reserved3d4 c.Uint32T + Reserved3d8 c.Uint32T + Reserved3dc c.Uint32T + Reserved3e0 c.Uint32T + Reserved3e4 c.Uint32T + Reserved3e8 c.Uint32T + Reserved3ec c.Uint32T + Reserved3f0 c.Uint32T + Reserved3f4 c.Uint32T + Reserved3f8 c.Uint32T + ApbCtrlDate c.Uint32T +} +type ApbSaradcDevT ApbSaradcDevS diff --git a/esp32/apm_types.go b/esp32/apm_types.go new file mode 100644 index 00000000..5c1db293 --- /dev/null +++ b/esp32/apm_types.go @@ -0,0 +1,14 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type ApmRegionPmsT c.Int + +const ( + APM_REGION_PMS_X ApmRegionPmsT = 1 + APM_REGION_PMS_W ApmRegionPmsT = 2 + APM_REGION_PMS_R ApmRegionPmsT = 4 +) diff --git a/esp32/assert.go b/esp32/assert.go new file mode 100644 index 00000000..197498d8 --- /dev/null +++ b/esp32/assert.go @@ -0,0 +1,12 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +//go:linkname X__assertFunc C.__assert_func +func X__assertFunc(file *c.Char, line c.Int, func_ *c.Char, expr *c.Char) + +//go:linkname Abort C.abort +func Abort() diff --git a/esp32/assist_debug_reg.go b/esp32/assist_debug_reg.go new file mode 100644 index 00000000..ff9b60ed --- /dev/null +++ b/esp32/assist_debug_reg.go @@ -0,0 +1,457 @@ +package freertos + +import _ "unsafe" + +const ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S = 11 +const ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S = 10 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S = 9 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S = 8 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S = 7 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S = 6 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S = 5 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S = 4 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S = 3 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S = 2 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S = 1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S = 0 +const ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S = 11 +const ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S = 10 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S = 9 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S = 8 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S = 7 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S = 6 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S = 5 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S = 4 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S = 3 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S = 2 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S = 1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S = 0 +const ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S = 11 +const ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S = 10 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S = 9 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S = 8 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S = 7 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S = 6 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S = 5 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S = 4 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S = 3 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S = 2 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S = 1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S = 0 +const ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S = 11 +const ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S = 10 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S = 9 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S = 8 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S = 7 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S = 6 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S = 5 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S = 4 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S = 3 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S = 2 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S = 1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S = 0 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S = 0 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S = 0 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S = 0 +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S = 0 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S = 0 +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S = 0 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S = 0 +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S = 0 +const ASSIST_DEBUG_CORE_0_AREA_SP = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_SP_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_SP_S = 0 +const ASSIST_DEBUG_CORE_0_AREA_PC = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_PC_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_AREA_PC_S = 0 +const ASSIST_DEBUG_CORE_0_SP_UNSTABLE = 0x000000FF +const ASSIST_DEBUG_CORE_0_SP_UNSTABLE_V = 0xFF +const ASSIST_DEBUG_CORE_0_SP_UNSTABLE_S = 0 +const ASSIST_DEBUG_CORE_0_SP_MIN = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_SP_MIN_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_SP_MIN_S = 0 +const ASSIST_DEBUG_CORE_0_SP_MAX = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_SP_MAX_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_SP_MAX_S = 0 +const ASSIST_DEBUG_CORE_0_SP_PC = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_SP_PC_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_SP_PC_S = 0 +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_V = 0x1 +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_S = 0 +const ASSIST_DEBUG_CORE_0_RCD_RECORDING_V = 0x1 +const ASSIST_DEBUG_CORE_0_RCD_RECORDING_S = 0 +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_S = 0 +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS = 0x000000FF +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_V = 0xFF +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_S = 0 +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_S = 0 +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S = 0 +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_S = 0 +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_S = 0 +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_S = 0 +const ASSIST_DEBUG_CORE_0_RCD_SP = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_RCD_SP_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_RCD_SP_S = 0 +const ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V = 0x1 +const ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S = 25 +const ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V = 0x1 +const ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S = 24 +const ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 = 0x00FFFFFF +const ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V = 0xFFFFFF +const ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S = 0 +const ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V = 0x1 +const ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S = 25 +const ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V = 0x1 +const ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S = 24 +const ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 = 0x00FFFFFF +const ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V = 0xFFFFFF +const ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S = 0 +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V = 0x1 +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S = 22 +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 = 0x003FFFFF +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V = 0x3FFFFF +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S = 0 +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 = 0x0000FFFF +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V = 0xFFFF +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S = 0 +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S = 0 +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V = 0x1 +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S = 22 +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 = 0x003FFFFF +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V = 0x3FFFFF +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S = 0 +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 = 0x0000FFFF +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V = 0xFFFF +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S = 0 +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S = 0 +const ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_S = 11 +const ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_S = 10 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_S = 9 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S = 8 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_S = 7 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_S = 6 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_S = 5 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S = 4 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_S = 3 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_S = 2 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_S = 1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S = 0 +const ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_S = 11 +const ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_S = 10 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S = 9 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_S = 8 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_S = 7 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_S = 6 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S = 5 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_S = 4 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_S = 3 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_S = 2 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S = 1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_S = 0 +const ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_S = 11 +const ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_S = 10 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_S = 9 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_S = 8 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_S = 7 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S = 6 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_S = 5 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_S = 4 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_S = 3 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S = 2 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_S = 1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_S = 0 +const ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_S = 11 +const ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_S = 10 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_S = 9 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S = 8 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_S = 7 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_S = 6 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_S = 5 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S = 4 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_S = 3 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_S = 2 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_S = 1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V = 0x1 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S = 0 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S = 0 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S = 0 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S = 0 +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S = 0 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S = 0 +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S = 0 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S = 0 +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S = 0 +const ASSIST_DEBUG_CORE_1_AREA_PC = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_PC_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_PC_S = 0 +const ASSIST_DEBUG_CORE_1_AREA_SP = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_SP_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_AREA_SP_S = 0 +const ASSIST_DEBUG_CORE_1_SP_UNSTABLE = 0x000000FF +const ASSIST_DEBUG_CORE_1_SP_UNSTABLE_V = 0xFF +const ASSIST_DEBUG_CORE_1_SP_UNSTABLE_S = 0 +const ASSIST_DEBUG_CORE_1_SP_MIN = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_SP_MIN_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_SP_MIN_S = 0 +const ASSIST_DEBUG_CORE_1_SP_MAX = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_SP_MAX_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_SP_MAX_S = 0 +const ASSIST_DEBUG_CORE_1_SP_PC = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_SP_PC_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_SP_PC_S = 0 +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_V = 0x1 +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_S = 0 +const ASSIST_DEBUG_CORE_1_RCD_RECORDING_V = 0x1 +const ASSIST_DEBUG_CORE_1_RCD_RECORDING_S = 0 +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_S = 0 +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS = 0x000000FF +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_V = 0xFF +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_S = 0 +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_S = 0 +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S = 0 +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_S = 0 +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_S = 0 +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_S = 0 +const ASSIST_DEBUG_CORE_1_RCD_SP = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_RCD_SP_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_RCD_SP_S = 0 +const ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_V = 0x1 +const ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_S = 25 +const ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V = 0x1 +const ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S = 24 +const ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0 = 0x00FFFFFF +const ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V = 0xFFFFFF +const ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S = 0 +const ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_V = 0x1 +const ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_S = 25 +const ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V = 0x1 +const ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S = 24 +const ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1 = 0x00FFFFFF +const ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V = 0xFFFFFF +const ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S = 0 +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_V = 0x1 +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_S = 22 +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0 = 0x003FFFFF +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V = 0x3FFFFF +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S = 0 +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0 = 0x0000FFFF +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V = 0xFFFF +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S = 0 +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0 = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S = 0 +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_V = 0x1 +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_S = 22 +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1 = 0x003FFFFF +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V = 0x3FFFFF +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S = 0 +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1 = 0x0000FFFF +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V = 0xFFFF +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S = 0 +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1 = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V = 0xFFFFFFFF +const ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S = 0 +const ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 = 0x000FFFFF +const ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V = 0xFFFFF +const ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S = 0 +const ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 = 0x000FFFFF +const ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V = 0xFFFFF +const ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S = 0 +const ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V = 0x1 +const ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S = 6 +const ASSIST_DEBUG_LOG_MODE = 0x00000007 +const ASSIST_DEBUG_LOG_MODE_V = 0x7 +const ASSIST_DEBUG_LOG_MODE_S = 3 +const ASSIST_DEBUG_LOG_ENA = 0x00000007 +const ASSIST_DEBUG_LOG_ENA_V = 0x7 +const ASSIST_DEBUG_LOG_ENA_S = 0 +const ASSIST_DEBUG_LOG_DATA_0 = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_DATA_0_V = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_DATA_0_S = 0 +const ASSIST_DEBUG_LOG_DATA_1 = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_DATA_1_V = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_DATA_1_S = 0 +const ASSIST_DEBUG_LOG_DATA_2 = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_DATA_2_V = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_DATA_2_S = 0 +const ASSIST_DEBUG_LOG_DATA_3 = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_DATA_3_V = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_DATA_3_S = 0 +const ASSIST_DEBUG_LOG_DATA_SIZE = 0x0000FFFF +const ASSIST_DEBUG_LOG_DATA_SIZE_V = 0xFFFF +const ASSIST_DEBUG_LOG_DATA_SIZE_S = 0 +const ASSIST_DEBUG_LOG_MIN = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_MIN_V = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_MIN_S = 0 +const ASSIST_DEBUG_LOG_MAX = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_MAX_V = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_MAX_S = 0 +const ASSIST_DEBUG_LOG_MEM_START = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_MEM_START_V = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_MEM_START_S = 0 +const ASSIST_DEBUG_LOG_MEM_END = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_MEM_END_V = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_MEM_END_S = 0 +const ASSIST_DEBUG_LOG_MEM_WRITING_ADDR = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V = 0xFFFFFFFF +const ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S = 0 +const ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V = 0x1 +const ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S = 0 +const ASSIST_DEBUG_REG_DATE = 0x0FFFFFFF +const ASSIST_DEBUG_REG_DATE_V = 0xFFFFFFF +const ASSIST_DEBUG_REG_DATE_S = 0 diff --git a/esp32/assist_debug_struct.go b/esp32/assist_debug_struct.go new file mode 100644 index 00000000..16a97637 --- /dev/null +++ b/esp32/assist_debug_struct.go @@ -0,0 +1,206 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type AssistDebugDevS struct { + Core0InterruptEna struct { + Val c.Uint32T + } + Core0InterruptRaw struct { + Val c.Uint32T + } + Core0InterruptRls struct { + Val c.Uint32T + } + Core0InterruptClr struct { + Val c.Uint32T + } + Core0AreaDram00Min c.Uint32T + Core0AreaDram00Max c.Uint32T + Core0AreaDram01Min c.Uint32T + Core0AreaDram01Max c.Uint32T + Core0AreaPif0Min c.Uint32T + Core0AreaPif0Max c.Uint32T + Core0AreaPif1Min c.Uint32T + Core0AreaPif1Max c.Uint32T + Core0AreaSp c.Uint32T + Core0AreaPc c.Uint32T + Core0SpUnstable struct { + Val c.Uint32T + } + Core0SpMin c.Uint32T + Core0SpMax c.Uint32T + Core0SpPc c.Uint32T + Core0RcdPdebugenable struct { + Val c.Uint32T + } + Core0RcdRecording struct { + Val c.Uint32T + } + Core0RcdPdebuginst c.Uint32T + Core0RcdPdebugstatus struct { + Val c.Uint32T + } + Core0RcdPdebugdata c.Uint32T + Core0RcdPdebugpc c.Uint32T + Core0RcdPdebugls0stat c.Uint32T + Core0RcdPdebugls0addr c.Uint32T + Core0RcdPdebugls0data c.Uint32T + Core0RcdSp c.Uint32T + Core0Iram0ExceptionMonitor0 struct { + Val c.Uint32T + } + Core0Iram0ExceptionMonitor1 struct { + Val c.Uint32T + } + Core0Dram0ExceptionMonitor0 struct { + Val c.Uint32T + } + Core0Dram0ExceptionMonitor1 struct { + Val c.Uint32T + } + Core0Dram0ExceptionMonitor2 c.Uint32T + Core0Dram0ExceptionMonitor3 struct { + Val c.Uint32T + } + Core0Dram0ExceptionMonitor4 struct { + Val c.Uint32T + } + Core0Dram0ExceptionMonitor5 c.Uint32T + Core1InterruptEna struct { + Val c.Uint32T + } + Core1InterruptRaw struct { + Val c.Uint32T + } + Core1InterruptRls struct { + Val c.Uint32T + } + Core1InterruptClr struct { + Val c.Uint32T + } + Core1AreaDram00Min c.Uint32T + Core1AreaDram00Max c.Uint32T + Core1AreaDram01Min c.Uint32T + Core1AreaDram01Max c.Uint32T + Core1AreaPif0Min c.Uint32T + Core1AreaPif0Max c.Uint32T + Core1AreaPif1Min c.Uint32T + Core1AreaPif1Max c.Uint32T + Core1AreaPc c.Uint32T + Core1AreaSp c.Uint32T + Core1SpUnstable struct { + Val c.Uint32T + } + Core1SpMin c.Uint32T + Core1SpMax c.Uint32T + Core1SpPc c.Uint32T + Core1RcdPdebugenable struct { + Val c.Uint32T + } + Core1RcdRecording struct { + Val c.Uint32T + } + Core1RcdPdebuginst c.Uint32T + Core1RcdPdebugstatus struct { + Val c.Uint32T + } + Core1RcdPdebugdata c.Uint32T + Core1RcdPdebugpc c.Uint32T + Core1RcdPdebugls0stat c.Uint32T + Core1RcdPdebugls0addr c.Uint32T + Core1RcdPdebugls0data c.Uint32T + Core1RcdSp c.Uint32T + Core1Iram0ExceptionMonitor0 struct { + Val c.Uint32T + } + Core1Iram0ExceptionMonitor1 struct { + Val c.Uint32T + } + Core1Dram0ExceptionMonitor0 struct { + Val c.Uint32T + } + Core1Dram0ExceptionMonitor1 struct { + Val c.Uint32T + } + Core1Dram0ExceptionMonitor2 c.Uint32T + Core1Dram0ExceptionMonitor3 struct { + Val c.Uint32T + } + Core1Dram0ExceptionMonitor4 struct { + Val c.Uint32T + } + Core1Dram0ExceptionMonitor5 c.Uint32T + CoreXIram0Dram0ExceptionMonitor0 struct { + Val c.Uint32T + } + CoreXIram0Dram0ExceptionMonitor1 struct { + Val c.Uint32T + } + LogSetting struct { + Val c.Uint32T + } + LogData0 c.Uint32T + LogData1 c.Uint32T + LogData2 c.Uint32T + LogData3 c.Uint32T + LogDataMask struct { + Val c.Uint32T + } + LogMin c.Uint32T + LogMax c.Uint32T + LogMemStart c.Uint32T + LogMemEnd c.Uint32T + LogMemWritingAddr c.Uint32T + LogMemFullFlag struct { + Val c.Uint32T + } + Reserved158 c.Uint32T + Reserved15c c.Uint32T + Reserved160 c.Uint32T + Reserved164 c.Uint32T + Reserved168 c.Uint32T + Reserved16c c.Uint32T + Reserved170 c.Uint32T + Reserved174 c.Uint32T + Reserved178 c.Uint32T + Reserved17c c.Uint32T + Reserved180 c.Uint32T + Reserved184 c.Uint32T + Reserved188 c.Uint32T + Reserved18c c.Uint32T + Reserved190 c.Uint32T + Reserved194 c.Uint32T + Reserved198 c.Uint32T + Reserved19c c.Uint32T + Reserved1a0 c.Uint32T + Reserved1a4 c.Uint32T + Reserved1a8 c.Uint32T + Reserved1ac c.Uint32T + Reserved1b0 c.Uint32T + Reserved1b4 c.Uint32T + Reserved1b8 c.Uint32T + Reserved1bc c.Uint32T + Reserved1c0 c.Uint32T + Reserved1c4 c.Uint32T + Reserved1c8 c.Uint32T + Reserved1cc c.Uint32T + Reserved1d0 c.Uint32T + Reserved1d4 c.Uint32T + Reserved1d8 c.Uint32T + Reserved1dc c.Uint32T + Reserved1e0 c.Uint32T + Reserved1e4 c.Uint32T + Reserved1e8 c.Uint32T + Reserved1ec c.Uint32T + Reserved1f0 c.Uint32T + Reserved1f4 c.Uint32T + Reserved1f8 c.Uint32T + RegDate struct { + Val c.Uint32T + } +} +type AssistDebugDevT AssistDebugDevS diff --git a/esp32/atomic.go b/esp32/atomic.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/atomic.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/bb_reg.go b/esp32/bb_reg.go new file mode 100644 index 00000000..cab04eb9 --- /dev/null +++ b/esp32/bb_reg.go @@ -0,0 +1,12 @@ +package freertos + +import _ "unsafe" + +const BB_FFT_FORCE_PU_V = 1 +const BB_FFT_FORCE_PU_S = 3 +const BB_FFT_FORCE_PD_V = 1 +const BB_FFT_FORCE_PD_S = 2 +const BB_DC_EST_FORCE_PU_V = 1 +const BB_DC_EST_FORCE_PU_S = 1 +const BB_DC_EST_FORCE_PD_V = 1 +const BB_DC_EST_FORCE_PD_S = 0 diff --git a/esp32/bigint.go b/esp32/bigint.go new file mode 100644 index 00000000..8e71b459 --- /dev/null +++ b/esp32/bigint.go @@ -0,0 +1,27 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +//go:linkname EtsBigintEnable C.ets_bigint_enable +func EtsBigintEnable() + +//go:linkname EtsBigintDisable C.ets_bigint_disable +func EtsBigintDisable() + +//go:linkname EtsBigintMultiply C.ets_bigint_multiply +func EtsBigintMultiply(x *c.Uint32T, y *c.Uint32T, len_words c.Uint32T) c.Int + +//go:linkname EtsBigintModmult C.ets_bigint_modmult +func EtsBigintModmult(x *c.Uint32T, y *c.Uint32T, m *c.Uint32T, m_dash c.Uint32T, rb *c.Uint32T, len_words c.Uint32T) c.Int + +//go:linkname EtsBigintModexp C.ets_bigint_modexp +func EtsBigintModexp(x *c.Uint32T, y *c.Uint32T, m *c.Uint32T, m_dash c.Uint32T, rb *c.Uint32T, constant_time bool, len_words c.Uint32T) c.Int + +//go:linkname EtsBigintWaitFinish C.ets_bigint_wait_finish +func EtsBigintWaitFinish() + +//go:linkname EtsBigintGetz C.ets_bigint_getz +func EtsBigintGetz(z *c.Uint32T, len_words c.Uint32T) c.Int diff --git a/esp32/boot_mode.go b/esp32/boot_mode.go new file mode 100644 index 00000000..7f3c3875 --- /dev/null +++ b/esp32/boot_mode.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +const SEL_NO_BOOT = 0 diff --git a/esp32/brownout.go b/esp32/brownout.go new file mode 100644 index 00000000..ae82d86a --- /dev/null +++ b/esp32/brownout.go @@ -0,0 +1,9 @@ +package freertos + +import _ "unsafe" + +//go:linkname EspBrownoutInit C.esp_brownout_init +func EspBrownoutInit() + +//go:linkname EspBrownoutDisable C.esp_brownout_disable +func EspBrownoutDisable() diff --git a/esp32/brownout_hal.go b/esp32/brownout_hal.go new file mode 100644 index 00000000..49bc085b --- /dev/null +++ b/esp32/brownout_hal.go @@ -0,0 +1,23 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type BrownoutHalConfigT struct { + Threshold c.Uint8T + Enabled bool + ResetEnabled bool + FlashPowerDown bool + RfPowerDown bool +} + +/** + * @brief Config brown out hal. + * + * @param cfg Pointer of brown out configuration structure. + */ +// llgo:link (*BrownoutHalConfigT).BrownoutHalConfig C.brownout_hal_config +func (recv_ *BrownoutHalConfigT) BrownoutHalConfig() { +} diff --git a/esp32/brownout_ll.go b/esp32/brownout_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/brownout_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/cache.go b/esp32/cache.go new file mode 100644 index 00000000..0f63213e --- /dev/null +++ b/esp32/cache.go @@ -0,0 +1,1284 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const MIN_ICACHE_SIZE = 16384 +const MAX_ICACHE_SIZE = 32768 +const MIN_DCACHE_SIZE = 32768 +const MAX_DCACHE_SIZE = 65536 +const MIN_ICACHE_WAYS = 4 +const MAX_ICACHE_WAYS = 8 +const MIN_DCACHE_WAYS = 4 +const MAX_DCACHE_WAYS = 4 +const MAX_CACHE_WAYS = 8 +const MIN_CACHE_LINE_SIZE = 16 +const TAG_SIZE = 4 +const MIN_ICACHE_BANK_NUM = 1 +const MAX_ICACHE_BANK_NUM = 2 +const MIN_DCACHE_BANK_NUM = 1 +const MAX_DCACHE_BANK_NUM = 2 +const CACHE_MEMORY_BANK_NUM = 4 +const CACHE_MEMORY_IBANK_SIZE = 0x4000 +const CACHE_MEMORY_DBANK_SIZE = 0x8000 +const ESP_ROM_ERR_INVALID_ARG = 1 +const MMU_SET_ADDR_ALIGNED_ERROR = 2 +const MMU_SET_PASE_SIZE_ERROR = 3 +const MMU_SET_VADDR_OUT_RANGE = 4 +const CACHE_OP_ICACHE_Y = 1 +const CACHE_OP_ICACHE_N = 0 + +type CacheT c.Int + +const ( + CACHE_DCACHE CacheT = 0 + CACHE_ICACHE0 CacheT = 1 + CACHE_ICACHE1 CacheT = 2 +) + +type CacheArrayT c.Int + +const ( + CACHE_MEMORY_INVALID CacheArrayT = 0 + CACHE_MEMORY_IBANK0 CacheArrayT = 1 + CACHE_MEMORY_IBANK1 CacheArrayT = 2 + CACHE_MEMORY_IBANK2 CacheArrayT = 4 + CACHE_MEMORY_IBANK3 CacheArrayT = 8 + CACHE_MEMORY_DBANK0 CacheArrayT = 1 + CACHE_MEMORY_DBANK1 CacheArrayT = 2 + CACHE_MEMORY_DBANK2 CacheArrayT = 4 + CACHE_MEMORY_DBANK3 CacheArrayT = 8 +) + +type CacheSizeT c.Int + +const ( + CACHE_SIZE_HALF CacheSizeT = 0 + CACHE_SIZE_FULL CacheSizeT = 1 +) + +type CacheWaysT c.Int + +const ( + CACHE_4WAYS_ASSOC CacheWaysT = 0 + CACHE_8WAYS_ASSOC CacheWaysT = 1 +) + +type CacheLineSizeT c.Int + +const ( + CACHE_LINE_SIZE_16B CacheLineSizeT = 0 + CACHE_LINE_SIZE_32B CacheLineSizeT = 1 + CACHE_LINE_SIZE_64B CacheLineSizeT = 2 +) + +type CacheAutoloadOrderT c.Int + +const ( + CACHE_AUTOLOAD_POSITIVE CacheAutoloadOrderT = 0 + CACHE_AUTOLOAD_NEGATIVE CacheAutoloadOrderT = 1 +) + +type CacheAutoloadRegionT c.Int + +const ( + CACHE_AUTOLOAD_REGION0 CacheAutoloadRegionT = 0 + CACHE_AUTOLOAD_REGION1 CacheAutoloadRegionT = 1 +) + +type CacheAutoloadTriggerT c.Int + +const ( + CACHE_AUTOLOAD_MISS_TRIGGER CacheAutoloadTriggerT = 0 + CACHE_AUTOLOAD_HIT_TRIGGER CacheAutoloadTriggerT = 1 + CACHE_AUTOLOAD_BOTH_TRIGGER CacheAutoloadTriggerT = 2 +) + +type CacheFreezeModeT c.Int + +const ( + CACHE_FREEZE_ACK_BUSY CacheFreezeModeT = 0 + CACHE_FREEZE_ACK_ERROR CacheFreezeModeT = 1 +) + +type CacheMode struct { + CacheSize c.Uint32T + CacheLineSize c.Uint16T + CacheWays c.Uint8T + Icache c.Uint8T +} + +type IcacheTagItem struct { + Valid c.Uint32T + Lock c.Uint32T + Attr c.Uint32T + FifoCnt c.Uint32T + Tag c.Uint32T + Reserved c.Uint32T +} + +type DcacheTagItem struct { + Dirty c.Uint32T + Valid c.Uint32T + Lock c.Uint32T + Occupy c.Uint32T + Attr c.Uint32T + FifoCnt c.Uint32T + Tag c.Uint32T + Reserved c.Uint32T +} + +type AutoloadConfig struct { + Ena c.Uint8T + Order c.Uint8T + Trigger c.Uint8T + Size c.Uint8T +} + +type AutoloadRegionConfig struct { + Region c.Uint8T + Ena c.Uint8T + Addr c.Uint32T + Size c.Uint32T +} + +type TagGroupInfo struct { + Mode CacheMode + FilterAddr c.Uint32T + VaddrOffset c.Uint32T + TagAddr [8]c.Uint32T + CacheMemoryOffset [8]c.Uint32T + UseLegacy c.Uint8T +} + +type LockConfig struct { + Addr c.Uint32T + Size c.Uint16T + Group c.Uint16T +} + +type CacheInternalStubTable struct { + IcacheLineSize c.Pointer + DcacheLineSize c.Pointer + IcacheAddr c.Pointer + DcacheAddr c.Pointer + InvalidateIcacheItems c.Pointer + InvalidateDcacheItems c.Pointer + CleanItems c.Pointer + WritebackItems c.Pointer + LockIcacheItems c.Pointer + LockDcacheItems c.Pointer + UnlockIcacheItems c.Pointer + UnlockDcacheItems c.Pointer + OccupyItems c.Pointer + SuspendIcacheAutoload c.Pointer + ResumeIcacheAutoload c.Pointer + SuspendDcacheAutoload c.Pointer + ResumeDcacheAutoload c.Pointer + FreezeIcacheEnable c.Pointer + FreezeIcacheDisable c.Pointer + FreezeDcacheEnable c.Pointer + FreezeDcacheDisable c.Pointer + OpAddr c.Pointer +} + +// llgo:type C +type CacheOpStart func() + +// llgo:type C +type CacheOpEnd func() + +type CacheOpCbT struct { + Start CacheOpStart + End CacheOpEnd +} + +/** + * @brief Initialise cache mmu, mark all entries as invalid. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +//go:linkname CacheMMUInit C.Cache_MMU_Init +func CacheMMUInit() + +/** + * @brief Set ICache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t ext_ram : SOC_MMU_ACCESS_FLASH for flash, SOC_MMU_ACCESS_SPIRAM for spiram, SOC_MMU_INVALID for invalid. + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + * + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +//go:linkname CacheIbusMMUSet C.Cache_Ibus_MMU_Set +func CacheIbusMMUSet(ext_ram c.Uint32T, vaddr c.Uint32T, paddr c.Uint32T, psize c.Uint32T, num c.Uint32T, fixed c.Uint32T) c.Int + +/** + * @brief Set DCache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t ext_ram : SOC_MMU_ACCESS_FLASH for flash, SOC_MMU_ACCESS_SPIRAM for spiram, SOC_MMU_INVALID for invalid. + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +//go:linkname CacheDbusMMUSet C.Cache_Dbus_MMU_Set +func CacheDbusMMUSet(ext_ram c.Uint32T, vaddr c.Uint32T, paddr c.Uint32T, psize c.Uint32T, num c.Uint32T, fixed c.Uint32T) c.Int + +/** + * @brief Count the pages in the bus room address which map to Flash. + * Please do not call this function in your SDK application. + * + * @param uint32_t bus : the bus to count with. + * + * @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count. + * + * return uint32_t : the number of pages which map to Flash. + */ +//go:linkname CacheCountFlashPages C.Cache_Count_Flash_Pages +func CacheCountFlashPages(bus c.Uint32T, page0_mapped *c.Uint32T) c.Uint32T + +/** + * @brief Copy Instruction or rodata from Flash to SPIRAM, and remap to SPIRAM. + * Please do not call this function in your SDK application. + * + * @param uint32_t bus : the bus which need to copy to SPIRAM. + * + * @param uint32_t bus_start_addr : the start virtual address for the bus. + * + * @param uint32_t start_page : the start (64KB) page number in SPIRAM. + * + * @param uint32_t * page0_page : the flash page0 in SPIRAM page number, 0xffff for invalid. + * + * return uint32_t : the next start page number for SPIRAM not mapped. + */ +//go:linkname CacheFlashToSPIRAMCopy C.Cache_Flash_To_SPIRAM_Copy +func CacheFlashToSPIRAMCopy(bus c.Uint32T, bus_start_addr c.Uint32T, start_page c.Uint32T, page0_page *c.Uint32T) c.Uint32T + +/** + * @brief allocate memory to used by ICache. + * Please do not call this function in your SDK application. + * + * @param cache_array_t icache_low : the data array bank used by icache low part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0 + * + * @param cache_array_t icache_high : the data array bank used by icache high part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, or CACHE_MEMORY_IBANK1 only if icache_low and icache_high is CACHE_MEMORY_IBANK0 + * + * return none + */ +// llgo:link CacheArrayT.CacheOccupyICacheMEMORY C.Cache_Occupy_ICache_MEMORY +func (recv_ CacheArrayT) CacheOccupyICacheMEMORY(icache_high CacheArrayT) { +} + +/** + * @brief allocate memory to used by DCache. + * Please do not call this function in your SDK application. + * + * @param cache_array_t dcache_low : the data array bank used by dcache low part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, CACHE_MEMORY_DBANK1 + * + * @param cache_array_t dcache1_high : the data array bank used by dcache high part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, or CACHE_MEMORY_DBANK0 only if dcache_low0 and dcache_low1 is CACHE_MEMORY_DBANK1 + * + * return none + */ +// llgo:link CacheArrayT.CacheOccupyDCacheMEMORY C.Cache_Occupy_DCache_MEMORY +func (recv_ CacheArrayT) CacheOccupyDCacheMEMORY(dcache_high CacheArrayT) { +} + +/** + * @brief Get cache mode of ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field + * + * return none + */ +// llgo:link (*CacheMode).CacheGetMode C.Cache_Get_Mode +func (recv_ *CacheMode) CacheGetMode() { +} + +/** + * @brief set ICache modes: cache size, associate ways and cache line size. + * Please do not call this function in your SDK application. + * + * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL + * + * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC + * + * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B and CACHE_LINE_SIZE_32B + * + * return none + */ +// llgo:link CacheSizeT.CacheSetICacheMode C.Cache_Set_ICache_Mode +func (recv_ CacheSizeT) CacheSetICacheMode(ways CacheWaysT, cache_line_size CacheLineSizeT) { +} + +/** + * @brief set DCache modes: cache size, associate ways and cache line size. + * Please do not call this function in your SDK application. + * + * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL + * + * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC, only CACHE_4WAYS_ASSOC works + * + * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B + * + * return none + */ +// llgo:link CacheSizeT.CacheSetDCacheMode C.Cache_Set_DCache_Mode +func (recv_ CacheSizeT) CacheSetDCacheMode(ways CacheWaysT, cache_line_size CacheLineSizeT) { +} + +/** + * @brief check if the address is accessed through ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : the address to check. + * + * @return 1 if the address is accessed through ICache, 0 if not. + */ +//go:linkname CacheAddressThroughICache C.Cache_Address_Through_ICache +func CacheAddressThroughICache(addr c.Uint32T) c.Uint32T + +/** + * @brief check if the address is accessed through DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : the address to check. + * + * @return 1 if the address is accessed through DCache, 0 if not. + */ +//go:linkname CacheAddressThroughDCache C.Cache_Address_Through_DCache +func CacheAddressThroughDCache(addr c.Uint32T) c.Uint32T + +/** + * @brief Init Cache for ROM boot, including resetting the Dcache, initializing Owner, MMU, setting DCache mode, Enabling DCache, unmasking bus. + * + * @param None + * + * @return None + */ +//go:linkname ROMBootCacheInit C.ROM_Boot_Cache_Init +func ROMBootCacheInit() + +/** + * @brief Init mmu owner register to make i/d cache use half mmu entries. + * + * @param None + * + * @return None + */ +//go:linkname CacheOwnerInit C.Cache_Owner_Init +func CacheOwnerInit() + +/** + * @brief Invalidate the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to invalidate + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +//go:linkname CacheInvalidateICacheItems C.Cache_Invalidate_ICache_Items +func CacheInvalidateICacheItems(addr c.Uint32T, items c.Uint32T) + +/** + * @brief Invalidate the cache items for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to invalidate + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +//go:linkname CacheInvalidateDCacheItems C.Cache_Invalidate_DCache_Items +func CacheInvalidateDCacheItems(addr c.Uint32T, items c.Uint32T) + +/** + * @brief Clean the dirty bit of cache Items of DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to Clean + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +//go:linkname CacheCleanItems C.Cache_Clean_Items +func CacheCleanItems(addr c.Uint32T, items c.Uint32T) + +/** + * @brief Write back the cache items of DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to write back + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +//go:linkname CacheWriteBackItems C.Cache_WriteBack_Items +func CacheWriteBackItems(addr c.Uint32T, items c.Uint32T) + +/** + * @brief Invalidate the Cache items in the region from ICache or DCache. + * If the region is not in Cache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : invalidated region start address. + * + * @param uint32_t size : invalidated region size. + * + * @return 0 for success + * 1 for invalid argument + */ +//go:linkname CacheInvalidateAddr C.Cache_Invalidate_Addr +func CacheInvalidateAddr(addr c.Uint32T, size c.Uint32T) c.Int + +/** + * @brief Clean the dirty bit of Cache items in the region from DCache. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : cleaned region start address. + * + * @param uint32_t size : cleaned region size. + * + * @return 0 for success + * 1 for invalid argument + */ +//go:linkname CacheCleanAddr C.Cache_Clean_Addr +func CacheCleanAddr(addr c.Uint32T, size c.Uint32T) c.Int + +/** + * @brief Writeback the Cache items(also clean the dirty bit) in the region from DCache. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : writeback region start address. + * + * @param uint32_t size : writeback region size. + * + * @return 0 for success + * 1 for invalid argument + */ +//go:linkname CacheWriteBackAddr C.Cache_WriteBack_Addr +func CacheWriteBackAddr(addr c.Uint32T, size c.Uint32T) c.Int + +/** + * @brief Invalidate all cache items in ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +//go:linkname CacheInvalidateICacheAll C.Cache_Invalidate_ICache_All +func CacheInvalidateICacheAll() + +/** + * @brief Invalidate all cache items in DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +//go:linkname CacheInvalidateDCacheAll C.Cache_Invalidate_DCache_All +func CacheInvalidateDCacheAll() + +/** + * @brief Clean the dirty bit of all cache items in DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +//go:linkname CacheCleanAll C.Cache_Clean_All +func CacheCleanAll() + +/** + * @brief WriteBack all cache items in DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +//go:linkname CacheWriteBackAll C.Cache_WriteBack_All +func CacheWriteBackAll() + +/** + * @brief Mask all buses through ICache and DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +//go:linkname CacheMaskAll C.Cache_Mask_All +func CacheMaskAll() + +/** + * @brief UnMask DRam0 bus through DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +//go:linkname CacheUnMaskDram0 C.Cache_UnMask_Dram0 +func CacheUnMaskDram0() + +/** + * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache not auto preload before suspend. + */ +//go:linkname CacheSuspendICacheAutoload C.Cache_Suspend_ICache_Autoload +func CacheSuspendICacheAutoload() c.Uint32T + +/** + * @brief Resume ICache auto preload operation after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before suspend. + * + * @return None. + */ +//go:linkname CacheResumeICacheAutoload C.Cache_Resume_ICache_Autoload +func CacheResumeICacheAutoload(autoload c.Uint32T) + +/** + * @brief Suspend DCache auto preload operation, then you can resume it after some DCache operations. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for DCache not auto preload before suspend. + */ +//go:linkname CacheSuspendDCacheAutoload C.Cache_Suspend_DCache_Autoload +func CacheSuspendDCacheAutoload() c.Uint32T + +/** + * @brief Resume DCache auto preload operation after some DCache operations. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for DCache not auto preload before suspend. + * + * @return None. + */ +//go:linkname CacheResumeDCacheAutoload C.Cache_Resume_DCache_Autoload +func CacheResumeDCacheAutoload(autoload c.Uint32T) + +/** + * @brief Start an ICache manual preload, will suspend auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of the preload region. + * + * @param uint32_t size : size of the preload region, should not exceed the size of ICache. + * + * @param uint32_t order : the preload order, 0 for positive, other for negative + * + * @return uint32_t : 0 for ICache not auto preload before manual preload. + */ +//go:linkname CacheStartICachePreload C.Cache_Start_ICache_Preload +func CacheStartICachePreload(addr c.Uint32T, size c.Uint32T, order c.Uint32T) c.Uint32T + +/** + * @brief Return if the ICache manual preload done. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache manual preload not done. + */ +//go:linkname CacheICachePreloadDone C.Cache_ICache_Preload_Done +func CacheICachePreloadDone() c.Uint32T + +/** + * @brief End the ICache manual preload to resume auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before manual preload. + * + * @return None + */ +//go:linkname CacheEndICachePreload C.Cache_End_ICache_Preload +func CacheEndICachePreload(autoload c.Uint32T) + +/** + * @brief Start an DCache manual preload, will suspend auto preload of DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of the preload region. + * + * @param uint32_t size : size of the preload region, should not exceed the size of DCache. + * + * @param uint32_t order : the preload order, 0 for positive, other for negative + * + * @return uint32_t : 0 for DCache not auto preload before manual preload. + */ +//go:linkname CacheStartDCachePreload C.Cache_Start_DCache_Preload +func CacheStartDCachePreload(addr c.Uint32T, size c.Uint32T, order c.Uint32T) c.Uint32T + +/** + * @brief Return if the DCache manual preload done. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for DCache manual preload not done. + */ +//go:linkname CacheDCachePreloadDone C.Cache_DCache_Preload_Done +func CacheDCachePreloadDone() c.Uint32T + +/** + * @brief End the DCache manual preload to resume auto preload of DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for DCache not auto preload before manual preload. + * + * @return None + */ +//go:linkname CacheEndDCachePreload C.Cache_End_DCache_Preload +func CacheEndDCachePreload(autoload c.Uint32T) + +/** + * @brief Config autoload parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_config * config : autoload parameters. + * + * @return None + */ +// llgo:link (*AutoloadConfig).CacheConfigICacheAutoload C.Cache_Config_ICache_Autoload +func (recv_ *AutoloadConfig) CacheConfigICacheAutoload() { +} + +/** + * @brief Config region autoload parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_region_config * config : region autoload parameters. + * + * @return ESP_ROM_ERR_INVALID_ARG : invalid param, 0 : success + */ +// llgo:link (*AutoloadRegionConfig).CacheConfigICacheRegionAutoload C.Cache_Config_ICache_Region_Autoload +func (recv_ *AutoloadRegionConfig) CacheConfigICacheRegionAutoload() c.Int { + return 0 +} + +/** + * @brief Enable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +//go:linkname CacheEnableICacheAutoload C.Cache_Enable_ICache_Autoload +func CacheEnableICacheAutoload() + +/** + * @brief Disable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +//go:linkname CacheDisableICacheAutoload C.Cache_Disable_ICache_Autoload +func CacheDisableICacheAutoload() + +/** + * @brief Config autoload parameters of DCache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_config * config : autoload parameters. + * + * @return None + */ +// llgo:link (*AutoloadConfig).CacheConfigDCacheAutoload C.Cache_Config_DCache_Autoload +func (recv_ *AutoloadConfig) CacheConfigDCacheAutoload() { +} + +/** + * @brief Config region autoload parameters of DCache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_region_config * config : region autoload parameters. + * + * @return ESP_ROM_ERR_INVALID_ARG : invalid param, 0 : success + */ +// llgo:link (*AutoloadRegionConfig).CacheConfigDCacheRegionAutoload C.Cache_Config_DCache_Region_Autoload +func (recv_ *AutoloadRegionConfig) CacheConfigDCacheRegionAutoload() c.Int { + return 0 +} + +/** + * @brief Enable auto preload for DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +//go:linkname CacheEnableDCacheAutoload C.Cache_Enable_DCache_Autoload +func CacheEnableDCacheAutoload() + +/** + * @brief Disable auto preload for DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +//go:linkname CacheDisableDCacheAutoload C.Cache_Disable_DCache_Autoload +func CacheDisableDCacheAutoload() + +/** + * @brief Config a group of prelock parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct lock_config * config : a group of lock parameters. + * + * @return None + */ +// llgo:link (*LockConfig).CacheEnableICachePreLock C.Cache_Enable_ICache_PreLock +func (recv_ *LockConfig) CacheEnableICachePreLock() { +} + +/** + * @brief Disable a group of prelock parameters for ICache. + * However, the locked data will not be released. + * Please do not call this function in your SDK application. + * + * @param uint16_t group : 0 for group0, 1 for group1. + * + * @return None + */ +//go:linkname CacheDisableICachePreLock C.Cache_Disable_ICache_PreLock +func CacheDisableICachePreLock(group c.Uint16T) + +/** + * @brief Lock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to lock + * + * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +//go:linkname CacheLockICacheItems C.Cache_Lock_ICache_Items +func CacheLockICacheItems(addr c.Uint32T, items c.Uint32T) + +/** + * @brief Unlock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to unlock + * + * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +//go:linkname CacheUnlockICacheItems C.Cache_Unlock_ICache_Items +func CacheUnlockICacheItems(addr c.Uint32T, items c.Uint32T) + +/** + * @brief Config a group of prelock parameters of DCache. + * Please do not call this function in your SDK application. + * + * @param struct lock_config * config : a group of lock parameters. + * + * @return None + */ +// llgo:link (*LockConfig).CacheEnableDCachePreLock C.Cache_Enable_DCache_PreLock +func (recv_ *LockConfig) CacheEnableDCachePreLock() { +} + +/** + * @brief Disable a group of prelock parameters for DCache. + * However, the locked data will not be released. + * Please do not call this function in your SDK application. + * + * @param uint16_t group : 0 for group0, 1 for group1. + * + * @return None + */ +//go:linkname CacheDisableDCachePreLock C.Cache_Disable_DCache_PreLock +func CacheDisableDCachePreLock(group c.Uint16T) + +/** + * @brief Lock the cache items for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to lock + * + * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +//go:linkname CacheLockDCacheItems C.Cache_Lock_DCache_Items +func CacheLockDCacheItems(addr c.Uint32T, items c.Uint32T) + +/** + * @brief Unlock the cache items for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to unlock + * + * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +//go:linkname CacheUnlockDCacheItems C.Cache_Unlock_DCache_Items +func CacheUnlockDCacheItems(addr c.Uint32T, items c.Uint32T) + +/** + * @brief Lock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of lock region. + * + * @param uint32_t size : size of lock region. + * + * @return 0 for success + * 1 for invalid argument + */ +//go:linkname CacheLockAddr C.Cache_Lock_Addr +func CacheLockAddr(addr c.Uint32T, size c.Uint32T) c.Int + +/** + * @brief Unlock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of unlock region. + * + * @param uint32_t size : size of unlock region. + * + * @return 0 for success + * 1 for invalid argument + */ +//go:linkname CacheUnlockAddr C.Cache_Unlock_Addr +func CacheUnlockAddr(addr c.Uint32T, size c.Uint32T) c.Int + +/** + * @brief Disable ICache access for the cpu. + * This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle. + * Please do not call this function in your SDK application. + * + * @return uint32_t : auto preload enabled before + */ +//go:linkname CacheDisableICache C.Cache_Disable_ICache +func CacheDisableICache() c.Uint32T + +/** + * @brief Enable ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +//go:linkname CacheEnableICache C.Cache_Enable_ICache +func CacheEnableICache(autoload c.Uint32T) + +/** + * @brief Disable DCache access for the cpu. + * This operation will make all DCache tag memory invalid, CPU can't access DCache, DCache will keep idle + * Please do not call this function in your SDK application. + * + * @return uint32_t : auto preload enabled before + */ +//go:linkname CacheDisableDCache C.Cache_Disable_DCache +func CacheDisableDCache() c.Uint32T + +/** + * @brief Enable DCache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : DCache will preload then. + * + * @return None + */ +//go:linkname CacheEnableDCache C.Cache_Enable_DCache +func CacheEnableDCache(autoload c.Uint32T) + +/** + * @brief Suspend ICache access for the cpu. + * The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle. + * Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : auto preload enabled before + */ +//go:linkname CacheSuspendICache C.Cache_Suspend_ICache +func CacheSuspendICache() c.Uint32T + +/** + * @brief Resume ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +//go:linkname CacheResumeICache C.Cache_Resume_ICache +func CacheResumeICache(autoload c.Uint32T) + +/** + * @brief Suspend DCache access for the cpu. + * The ICache tag memory is still there, CPU can't access DCache, DCache will keep idle. + × Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : auto preload enabled before +*/ +//go:linkname CacheSuspendDCache C.Cache_Suspend_DCache +func CacheSuspendDCache() c.Uint32T + +/** + * @brief Resume DCache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : DCache will preload then. + * + * @return None + */ +//go:linkname CacheResumeDCache C.Cache_Resume_DCache +func CacheResumeDCache(autoload c.Uint32T) + +/** + * @brief Get ICache cache line size + * + * @param None + * + * @return uint32_t: 16, 32, 64 Byte + */ +//go:linkname CacheGetICacheLineSize C.Cache_Get_ICache_Line_Size +func CacheGetICacheLineSize() c.Uint32T + +/** + * @brief Get DCache cache line size + * + * @param None + * + * @return uint32_t: 16, 32, 64 Byte + */ +//go:linkname CacheGetDCacheLineSize C.Cache_Get_DCache_Line_Size +func CacheGetDCacheLineSize() c.Uint32T + +/** + * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. + * + * @param None + * + * @return None + */ +//go:linkname CacheSetDefaultMode C.Cache_Set_Default_Mode +func CacheSetDefaultMode() + +/** + * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. + * + * @param None + * + * @return None + */ +//go:linkname CacheEnableDefalutICacheMode C.Cache_Enable_Defalut_ICache_Mode +func CacheEnableDefalutICacheMode() + +/** + * @brief Occupy the cache items for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of occupy region + * + * @param uint32_t items : cache lines to occupy, items * cache_line_size should not exceed the cache_size + * + * @return None + */ +//go:linkname CacheOccupyItems C.Cache_Occupy_Items +func CacheOccupyItems(addr c.Uint32T, items c.Uint32T) + +/** + * @brief Occupy the cache addr for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of occupy region + * + * @param uint32_t size : size of occupy region, size should not exceed the cache_size + */ +//go:linkname CacheOccupyAddr C.Cache_Occupy_Addr +func CacheOccupyAddr(addr c.Uint32T, size c.Uint32T) c.Int + +/** + * @brief Enable freeze for ICache. + * Any miss request will be rejected, including cpu miss and preload/autoload miss. + * Please do not call this function in your SDK application. + * + * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit + * + * @return None + */ +// llgo:link CacheFreezeModeT.CacheFreezeICacheEnable C.Cache_Freeze_ICache_Enable +func (recv_ CacheFreezeModeT) CacheFreezeICacheEnable() { +} + +/** + * @brief Disable freeze for ICache. + * Please do not call this function in your SDK application. + * + * @return None + */ +//go:linkname CacheFreezeICacheDisable C.Cache_Freeze_ICache_Disable +func CacheFreezeICacheDisable() + +/** + * @brief Enable freeze for DCache. + * Any miss request will be rejected, including cpu miss and preload/autoload miss. + * Please do not call this function in your SDK application. + * + * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit + * + * @return None + */ +// llgo:link CacheFreezeModeT.CacheFreezeDCacheEnable C.Cache_Freeze_DCache_Enable +func (recv_ CacheFreezeModeT) CacheFreezeDCacheEnable() { +} + +/** + * @brief Disable freeze for DCache. + * Please do not call this function in your SDK application. + * + * @return None + */ +//go:linkname CacheFreezeDCacheDisable C.Cache_Freeze_DCache_Disable +func CacheFreezeDCacheDisable() + +/** + * @brief Travel tag memory to run a call back function. + * ICache and DCache are suspend when doing this. + * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to check and the cache mode. + * + * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. + * 0 for do not filter, all cache lines will be returned. + * + * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. + * + * @return None + */ +// llgo:link (*CacheMode).CacheTravelTagMemory C.Cache_Travel_Tag_Memory +func (recv_ *CacheMode) CacheTravelTagMemory(filter_addr c.Uint32T, process func(*TagGroupInfo)) { +} + +/** + * @brief Travel tag memory to run a call back function, using 2nd tag registers. + * ICache and DCache are suspend when doing this. + * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to check and the cache mode. + * + * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. + * 0 for do not filter, all cache lines will be returned. + * + * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. + * + * @return None + */ +// llgo:link (*CacheMode).CacheTravelTagMemory2 C.Cache_Travel_Tag_Memory2 +func (recv_ *CacheMode) CacheTravelTagMemory2(filter_addr c.Uint32T, process func(*TagGroupInfo)) { +} + +/** + * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. + * + * @param uint32_t tag : the tag part of a tag item, 12-14 bits. + * + * @param uint32_t addr_offset : the virtual address offset of the cache ways. + * + * @return uint32_t : the virtual address. + */ +// llgo:link (*CacheMode).CacheGetVirtualAddr C.Cache_Get_Virtual_Addr +func (recv_ *CacheMode) CacheGetVirtualAddr(tag c.Uint32T, vaddr_offset c.Uint32T) c.Uint32T { + return 0 +} + +/** + * @brief Get cache memory block base address. + * Please do not call this function in your SDK application. + * + * @param uint32_t icache : 0 for dcache, other for icache. + * + * @param uint32_t bank_no : 0 ~ 3 bank. + * + * @return uint32_t : the cache memory block base address, 0 if the block not used. + */ +//go:linkname CacheGetMemoryBaseAddr C.Cache_Get_Memory_BaseAddr +func CacheGetMemoryBaseAddr(icache c.Uint32T, bank_no c.Uint32T) c.Uint32T + +/** + * @brief Get the cache memory address from cache mode, cache memory offset and the virtual address offset of cache ways. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. + * + * @param uint32_t cache_memory_offset : the cache memory offset of the whole cache (ICache or DCache) for the cache line. + * + * @param uint32_t addr_offset : the virtual address offset of the cache ways. + * + * @return uint32_t : the virtual address. + */ +// llgo:link (*CacheMode).CacheGetMemoryAddr C.Cache_Get_Memory_Addr +func (recv_ *CacheMode) CacheGetMemoryAddr(cache_memory_offset c.Uint32T, vaddr_offset c.Uint32T) c.Uint32T { + return 0 +} + +/** + * @brief Get the cache memory value by DRAM address. + * Please do not call this function in your SDK application. + * + * @param uint32_t cache_memory_addr : DRAM address for the cache memory, should be 4 byte aligned for IBus address. + * + * @return uint32_t : the word value of the address. + */ +//go:linkname CacheGetMemoryValue C.Cache_Get_Memory_value +func CacheGetMemoryValue(cache_memory_addr c.Uint32T) c.Uint32T + +/** + * @brief Get the cache MMU IROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +//go:linkname CacheGetIROMMMUEnd C.Cache_Get_IROM_MMU_End +func CacheGetIROMMMUEnd() c.Uint32T + +/** + * @brief Get the cache MMU DROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +//go:linkname CacheGetDROMMMUEnd C.Cache_Get_DROM_MMU_End +func CacheGetDROMMMUEnd() c.Uint32T + +/** + * @brief Configure cache MMU page size according to instruction and rodata size + * + * @param irom_size The instruction cache MMU page size + * @param drom_size The rodata data cache MMU page size + */ +//go:linkname CacheSetIDROMMMUSize C.Cache_Set_IDROM_MMU_Size +func CacheSetIDROMMMUSize(irom_size c.Uint32T, drom_size c.Uint32T) + +/** + * @brief Configure cache MMU page information + * + * @param instr_page_num The instruction cache MMU page num + * @param rodata_page_num The rodata cache MMU page num + * @param rodata_start The rodata start cache address + * @param rodata_end The rodata end cache address + * @param i_off The offset of instruction when instruction copied from flash to xip_psram + * @param ro_off The offset of rodata when rodata copied from flash to xip_psram + */ +//go:linkname CacheSetIDROMMMUInfo C.Cache_Set_IDROM_MMU_Info +func CacheSetIDROMMMUInfo(instr_page_num c.Uint32T, rodata_page_num c.Uint32T, rodata_start c.Uint32T, rodata_end c.Uint32T, i_off c.Int, ro_off c.Int) + +/** + * @brief Used by SPI flash mmap + * + */ +//go:linkname Flash2spiramInstructionOffset C.flash2spiram_instruction_offset +func Flash2spiramInstructionOffset() c.Int + +//go:linkname Flash2spiramRodataOffset C.flash2spiram_rodata_offset +func Flash2spiramRodataOffset() c.Int + +//go:linkname FlashInstrRodataStartPage C.flash_instr_rodata_start_page +func FlashInstrRodataStartPage(bus c.Uint32T) c.Uint32T + +//go:linkname FlashInstrRodataEndPage C.flash_instr_rodata_end_page +func FlashInstrRodataEndPage(bus c.Uint32T) c.Uint32T diff --git a/esp32/cache_err_int.go b/esp32/cache_err_int.go new file mode 100644 index 00000000..f661411b --- /dev/null +++ b/esp32/cache_err_int.go @@ -0,0 +1,46 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief initialize cache invalid access interrupt + * + * This function enables cache invalid access interrupt source and connects it + * to interrupt input number. It is called from the startup code. + * + * On ESP32, the interrupt input number is ETS_MEMACCESS_ERR_INUM. On other targets + * it is ETS_CACHEERR_INUM. See soc/soc.h for more information. + */ +//go:linkname EspCacheErrIntInit C.esp_cache_err_int_init +func EspCacheErrIntInit() + +/** + * @brief get the CPU which caused cache invalid access interrupt. Helper function in + * panic handling. + * @return + * - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt + * - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt + * - (-1) otherwise + */ +//go:linkname EspCacheErrGetCpuid C.esp_cache_err_get_cpuid +func EspCacheErrGetCpuid() c.Int + +/** + * @brief Returns a pointer to the cache error message + * + * @return const char* Pointer to the error message + */ +//go:linkname EspCacheErrPanicString C.esp_cache_err_panic_string +func EspCacheErrPanicString() *c.Char + +/** + * @brief Checks if any cache errors are active + * + * @return true + * @return false + */ +//go:linkname EspCacheErrHasActiveErr C.esp_cache_err_has_active_err +func EspCacheErrHasActiveErr() bool diff --git a/esp32/cache_hal.go b/esp32/cache_hal.go new file mode 100644 index 00000000..6f301d30 --- /dev/null +++ b/esp32/cache_hal.go @@ -0,0 +1,144 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Cache init and cache hal context init + */ +//go:linkname CacheHalInit C.cache_hal_init +func CacheHalInit() + +/** + * @brief Disable Cache + * + * Disable the ICache or DCache or both, of a certain level or all levels. + * All the items in the corresponding Cache(s) will be invalideated. + * Next request to these items will trigger a transaction to the physical memory + * + * @note If the autoload feature is enabled, this API will return until the ICache autoload is disabled. + * + * @param cache_level Level of the Cache(s) + * @param type see `cache_type_t` + */ +//go:linkname CacheHalDisable C.cache_hal_disable +func CacheHalDisable(cache_level c.Uint32T, type_ CacheTypeT) + +/** + * @brief Enable Cache + * + * Enable the ICache or DCache or both, of a certain level or all levels. + * + * @param cache_level Level of the Cache(s) + * @param type see `cache_type_t` + */ +//go:linkname CacheHalEnable C.cache_hal_enable +func CacheHalEnable(cache_level c.Uint32T, type_ CacheTypeT) + +/** + * @brief Suspend Cache + * + * Suspend the ICache or DCache or both, of a certain level or all levels. + * This API suspends the CPU access to cache for a while, without invalidation. + * + * @param cache_level Level of the Cache(s) + * @param type see `cache_type_t` + */ +//go:linkname CacheHalSuspend C.cache_hal_suspend +func CacheHalSuspend(cache_level c.Uint32T, type_ CacheTypeT) + +/** + * @brief Resume Cache + * + * Resume the ICache or DCache or both, of a certain level or all levels. + * + * @param cache_level Level of the Cache(s) + * @param type see `cache_type_t` + */ +//go:linkname CacheHalResume C.cache_hal_resume +func CacheHalResume(cache_level c.Uint32T, type_ CacheTypeT) + +/** + * @brief Check if corresponding cache is enabled or not + * + * @param cache_level Level of the Cache(s) + * @param type see `cache_type_t` + * + * @return true: enabled; false: disabled + */ +//go:linkname CacheHalIsCacheEnabled C.cache_hal_is_cache_enabled +func CacheHalIsCacheEnabled(cache_level c.Uint32T, type_ CacheTypeT) bool + +/** + * @brief Invalidate Cache supported addr + * + * Invalidate a Cache item for either ICache or DCache. + * + * @param vaddr Start address of the region to be invalidated + * @param size Size of the region to be invalidated + * + * @return True for valid address. No operation if invalid + */ +//go:linkname CacheHalInvalidateAddr C.cache_hal_invalidate_addr +func CacheHalInvalidateAddr(vaddr c.Uint32T, size c.Uint32T) bool + +/** + * @brief Writeback Cache supported addr + * + * Writeback the DCache item to external memory + * + * @param vaddr Start address of the region to writeback + * @param size Size of the region to writeback + * + * @return True for valid address. No operation if invalid + */ +//go:linkname CacheHalWritebackAddr C.cache_hal_writeback_addr +func CacheHalWritebackAddr(vaddr c.Uint32T, size c.Uint32T) bool + +/** + * @brief Freeze Cache + * + * Freeze cache, CPU access to cache will be suspended, until the cache is unfrozen. + * + * @param cache_level Level of the Cache(s) + * @param type see `cache_type_t` + */ +//go:linkname CacheHalFreeze C.cache_hal_freeze +func CacheHalFreeze(cache_level c.Uint32T, type_ CacheTypeT) + +/** + * @brief Unfreeze cache + * + * Unfreeze cache, CPU access to cache will be restored + * + * @param cache_level Level of the Cache(s) + * @param type see `cache_type_t` + */ +//go:linkname CacheHalUnfreeze C.cache_hal_unfreeze +func CacheHalUnfreeze(cache_level c.Uint32T, type_ CacheTypeT) + +/** + * @brief Get cache line size, in bytes + * + * @param cache_level Level of the Cache(s) + * @param type see `cache_type_t` + * + * @return cache line size, in bytes. 0 stands for no such cache in this type or level + */ +//go:linkname CacheHalGetCacheLineSize C.cache_hal_get_cache_line_size +func CacheHalGetCacheLineSize(cache_level c.Uint32T, type_ CacheTypeT) c.Uint32T + +/** + * @brief Get Cache level and the ID of the vaddr + * + * @param vaddr_start virtual address start + * @param len vaddr length + * @param out_level cache level + * @param out_id cache id + * + * @return true for valid, false for invalid addr or null pointer + */ +//go:linkname CacheHalVaddrToCacheLevelId C.cache_hal_vaddr_to_cache_level_id +func CacheHalVaddrToCacheLevelId(vaddr_start c.Uint32T, len c.Uint32T, out_level *c.Uint32T, out_id *c.Uint32T) bool diff --git a/esp32/cache_ll.go b/esp32/cache_ll.go new file mode 100644 index 00000000..9d0dbd6e --- /dev/null +++ b/esp32/cache_ll.go @@ -0,0 +1,9 @@ +package freertos + +import _ "unsafe" + +const CACHE_LL_ID_ALL = 2 +const CACHE_LL_LEVEL_INT_MEM = 0 +const CACHE_LL_LEVEL_EXT_MEM = 1 +const CACHE_LL_LEVEL_ALL = 2 +const CACHE_LL_LEVEL_NUMS = 1 diff --git a/esp32/cache_types.go b/esp32/cache_types.go new file mode 100644 index 00000000..0465885e --- /dev/null +++ b/esp32/cache_types.go @@ -0,0 +1,25 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type CacheTypeT c.Int + +const ( + CACHE_TYPE_DATA CacheTypeT = 0 + CACHE_TYPE_INSTRUCTION CacheTypeT = 1 + CACHE_TYPE_ALL CacheTypeT = 2 +) + +type CacheBusMaskT c.Int + +const ( + CACHE_BUS_IBUS0 CacheBusMaskT = 1 + CACHE_BUS_IBUS1 CacheBusMaskT = 2 + CACHE_BUS_IBUS2 CacheBusMaskT = 4 + CACHE_BUS_DBUS0 CacheBusMaskT = 8 + CACHE_BUS_DBUS1 CacheBusMaskT = 16 + CACHE_BUS_DBUS2 CacheBusMaskT = 32 +) diff --git a/esp32/cacheasm.go b/esp32/cacheasm.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/cacheasm.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/cacheattrasm.go b/esp32/cacheattrasm.go new file mode 100644 index 00000000..d4ef8fd4 --- /dev/null +++ b/esp32/cacheattrasm.go @@ -0,0 +1,8 @@ +package freertos + +import _ "unsafe" + +const XCHAL_CACHEATTR_ALL_BYPASS = 0x22222222 +const XCHAL_FCA_ENAMASK = 0x003A +const XCHAL_LCA_ENAMASK = 0x0033 +const XCHAL_SCA_ENAMASK = 0x0033 diff --git a/esp32/cam_ctlr_types.go b/esp32/cam_ctlr_types.go new file mode 100644 index 00000000..c8c0b3d7 --- /dev/null +++ b/esp32/cam_ctlr_types.go @@ -0,0 +1,30 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type CamCtlrColorT c.Int + +const ( + CAM_CTLR_COLOR_RAW8 CamCtlrColorT = 16777216 + CAM_CTLR_COLOR_RAW10 CamCtlrColorT = 16777217 + CAM_CTLR_COLOR_RAW12 CamCtlrColorT = 16777218 + CAM_CTLR_COLOR_RGB565 CamCtlrColorT = 33554434 + CAM_CTLR_COLOR_RGB666 CamCtlrColorT = 33554433 + CAM_CTLR_COLOR_RGB888 CamCtlrColorT = 33554432 + CAM_CTLR_COLOR_YUV420 CamCtlrColorT = 50331650 + CAM_CTLR_COLOR_YUV422 CamCtlrColorT = 50331649 + CAM_CTLR_COLOR_GRAY4 CamCtlrColorT = 67108864 + CAM_CTLR_COLOR_GRAY8 CamCtlrColorT = 67108865 +) + +type CamCtlrDataWidthT c.Int + +const ( + CAM_CTLR_DATA_WIDTH_8 CamCtlrDataWidthT = 8 + CAM_CTLR_DATA_WIDTH_10 CamCtlrDataWidthT = 10 + CAM_CTLR_DATA_WIDTH_12 CamCtlrDataWidthT = 12 + CAM_CTLR_DATA_WIDTH_16 CamCtlrDataWidthT = 16 +) diff --git a/esp32/cam_hal.go b/esp32/cam_hal.go new file mode 100644 index 00000000..59989a4d --- /dev/null +++ b/esp32/cam_hal.go @@ -0,0 +1,72 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type CamDevT LcdCamDevT + +/** + * @brief CAM hardware interface object data + */ + +type CamHalContext struct { + Hw *CamDevT +} +type CamHalContextT CamHalContext + +/** + * @brief CAM HAL driver configuration + */ + +type CamHalConfig struct { + Port c.Int + ByteSwapEn bool +} +type CamHalConfigT CamHalConfig + +/** + * @brief Initialize CAM hardware + * + * @param hal CAM object data pointer + * @param config CAM configuration + * + * @return None + */ +// llgo:link (*CamHalContextT).CamHalInit C.cam_hal_init +func (recv_ *CamHalContextT) CamHalInit(config *CamHalConfigT) { +} + +/** + * @brief De-initialize CAM hardware + * + * @param hal CAM object data pointer + * + * @return None + */ +// llgo:link (*CamHalContextT).CamHalDeinit C.cam_hal_deinit +func (recv_ *CamHalContextT) CamHalDeinit() { +} + +/** + * @brief Start CAM to receive frame data + * + * @param hal CAM object data pointer + * + * @return None + */ +// llgo:link (*CamHalContextT).CamHalStartStreaming C.cam_hal_start_streaming +func (recv_ *CamHalContextT) CamHalStartStreaming() { +} + +/** + * @brief Stop CAM receiving frame data + * + * @param hal CAM object data pointer + * + * @return None + */ +// llgo:link (*CamHalContextT).CamHalStopStreaming C.cam_hal_stop_streaming +func (recv_ *CamHalContextT) CamHalStopStreaming() { +} diff --git a/esp32/cam_types.go b/esp32/cam_types.go new file mode 100644 index 00000000..d1a9a567 --- /dev/null +++ b/esp32/cam_types.go @@ -0,0 +1,11 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const CAP_DVP_PERIPH_NUM = 0 +const CAM_DVP_DATA_SIG_NUM = 0 + +type CamClockSourceT c.Int diff --git a/esp32/cc.go b/esp32/cc.go new file mode 100644 index 00000000..f23c1d81 --- /dev/null +++ b/esp32/cc.go @@ -0,0 +1,18 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const S16_F = "d" +const U16_F = "d" +const X16_F = "x" + +type U8T c.Uint8T +type S8T c.Int8T +type U16T c.Uint16T +type S16T c.Int16T +type U32T c.Uint32T +type S32T c.Int32T +type SysProtT c.Int diff --git a/esp32/cdc_acm.go b/esp32/cdc_acm.go new file mode 100644 index 00000000..0eff60dc --- /dev/null +++ b/esp32/cdc_acm.go @@ -0,0 +1,220 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ACM_BYTES_PER_TX = 64 + +type CdcAcmDevice c.Void + +// llgo:type C +type UartIrqCallbackT func(*CdcAcmDevice, c.Int) + +/** + * @brief Get amount of received characters in buffer + * + * @returns character count + */ +// llgo:link (*CdcAcmDevice).CdcAcmRxFifoCnt C.cdc_acm_rx_fifo_cnt +func (recv_ *CdcAcmDevice) CdcAcmRxFifoCnt() c.Int { + return 0 +} + +/* + * @brief Output a character in polled mode. + * + * The UART poll method for USB UART is simulated by waiting till + * we get the next BULK In upcall from the USB device controller or 100 ms. + * + * @return the same character which is sent + */ +// llgo:link (*CdcAcmDevice).CdcAcmPollOut C.cdc_acm_poll_out +func (recv_ *CdcAcmDevice) CdcAcmPollOut(c c.Char) c.Char { + return 0 +} + +/** + * @brief Fill FIFO with data + * + * @param dev CDC ACM device struct. + * @param tx_data Data to transmit. + * @param len Number of bytes to send. + * + * @return Number of bytes sent. + */ +// llgo:link (*CdcAcmDevice).CdcAcmFifoFill C.cdc_acm_fifo_fill +func (recv_ *CdcAcmDevice) CdcAcmFifoFill(tx_data *c.Uint8T, len c.Int) c.Int { + return 0 +} + +/** + * @brief Read data from FIFO + * + * @param dev CDC ACM device struct. + * @param rx_data Pointer to data container. + * @param size Container size. + * + * @return Number of bytes read. + */ +// llgo:link (*CdcAcmDevice).CdcAcmFifoRead C.cdc_acm_fifo_read +func (recv_ *CdcAcmDevice) CdcAcmFifoRead(rx_data *c.Uint8T, size c.Int) c.Int { + return 0 +} + +/** + * @brief Enable TX interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +// llgo:link (*CdcAcmDevice).CdcAcmIrqTxEnable C.cdc_acm_irq_tx_enable +func (recv_ *CdcAcmDevice) CdcAcmIrqTxEnable() { +} + +/** + * @brief Disable TX interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +// llgo:link (*CdcAcmDevice).CdcAcmIrqTxDisable C.cdc_acm_irq_tx_disable +func (recv_ *CdcAcmDevice) CdcAcmIrqTxDisable() { +} + +/** + * @brief Check if Tx IRQ has been raised + * + * @param dev CDC ACM device struct. + * + * @return 1 if a Tx IRQ is pending, 0 otherwise. + */ +// llgo:link (*CdcAcmDevice).CdcAcmIrqTxReady C.cdc_acm_irq_tx_ready +func (recv_ *CdcAcmDevice) CdcAcmIrqTxReady() c.Int { + return 0 +} + +/** + * @brief Enable RX interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A + */ +// llgo:link (*CdcAcmDevice).CdcAcmIrqRxEnable C.cdc_acm_irq_rx_enable +func (recv_ *CdcAcmDevice) CdcAcmIrqRxEnable() { +} + +/** + * @brief Disable RX interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +// llgo:link (*CdcAcmDevice).CdcAcmIrqRxDisable C.cdc_acm_irq_rx_disable +func (recv_ *CdcAcmDevice) CdcAcmIrqRxDisable() { +} + +/** + * @brief Enable line state interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +// llgo:link (*CdcAcmDevice).CdcAcmIrqStateEnable C.cdc_acm_irq_state_enable +func (recv_ *CdcAcmDevice) CdcAcmIrqStateEnable() { +} + +/** + * @brief Disable line state interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +// llgo:link (*CdcAcmDevice).CdcAcmIrqStateDisable C.cdc_acm_irq_state_disable +func (recv_ *CdcAcmDevice) CdcAcmIrqStateDisable() { +} + +/** + * @brief Check if Rx IRQ has been raised + * + * @param dev CDC ACM device struct. + * + * @return 1 if an IRQ is ready, 0 otherwise. + */ +// llgo:link (*CdcAcmDevice).CdcAcmIrqRxReady C.cdc_acm_irq_rx_ready +func (recv_ *CdcAcmDevice) CdcAcmIrqRxReady() c.Int { + return 0 +} + +/** + * @brief Check if Tx or Rx IRQ is pending + * + * @param dev CDC ACM device struct. + * + * @return 1 if a Tx or Rx IRQ is pending, 0 otherwise. + */ +// llgo:link (*CdcAcmDevice).CdcAcmIrqIsPending C.cdc_acm_irq_is_pending +func (recv_ *CdcAcmDevice) CdcAcmIrqIsPending() c.Int { + return 0 +} + +/** + * @brief Set the callback function pointer for IRQ. + * + * @param dev CDC ACM device struct. + * @param cb Callback function pointer. + * + * @return N/A + */ +// llgo:link (*CdcAcmDevice).CdcAcmIrqCallbackSet C.cdc_acm_irq_callback_set +func (recv_ *CdcAcmDevice) CdcAcmIrqCallbackSet(cb UartIrqCallbackT) { +} + +/** + * @brief Manipulate line control for UART. + * + * @param dev CDC ACM device struct + * @param ctrl The line control to be manipulated + * @param val Value to set the line control + * + * @return 0 if successful, failed otherwise. + */ +// llgo:link (*CdcAcmDevice).CdcAcmLineCtrlSet C.cdc_acm_line_ctrl_set +func (recv_ *CdcAcmDevice) CdcAcmLineCtrlSet(ctrl c.Uint32T, val c.Uint32T) c.Int { + return 0 +} + +/** + * @brief Manipulate line control for UART. + * + * @param dev CDC ACM device struct + * @param ctrl The line control to be manipulated + * @param val Value to set the line control + * + * @return 0 if successful, failed otherwise. + */ +// llgo:link (*CdcAcmDevice).CdcAcmLineCtrlGet C.cdc_acm_line_ctrl_get +func (recv_ *CdcAcmDevice) CdcAcmLineCtrlGet(ctrl c.Uint32T, val *c.Uint32T) c.Int { + return 0 +} + +/** + * @brief Initialize UART channel + * + * This routine is called to reset the chip in a quiescent state. + * It is assumed that this function is called only once per UART. + * + * @param mem_chunk Memory chunk to use for internal use + * @param mem_chunk_size Size of the memory chunk in bytes + * + * @return dev or NULL + */ +//go:linkname CdcAcmInit C.cdc_acm_init +func CdcAcmInit(mem_chunk c.Pointer, mem_chunk_size c.Int) *CdcAcmDevice diff --git a/esp32/check.go b/esp32/check.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/check.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/chip_revision.go b/esp32/chip_revision.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/chip_revision.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/chip_usb_dw_wrapper.go b/esp32/chip_usb_dw_wrapper.go new file mode 100644 index 00000000..3b1caa43 --- /dev/null +++ b/esp32/chip_usb_dw_wrapper.go @@ -0,0 +1,21 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +//go:linkname ChipUsbDwInit C.chip_usb_dw_init +func ChipUsbDwInit() c.Int + +//go:linkname ChipUsbDwDidPersist C.chip_usb_dw_did_persist +func ChipUsbDwDidPersist() c.Int + +//go:linkname ChipUsbDwPreparePersist C.chip_usb_dw_prepare_persist +func ChipUsbDwPreparePersist() + +//go:linkname ChipUsbGetPersistFlags C.chip_usb_get_persist_flags +func ChipUsbGetPersistFlags() c.Uint32T + +//go:linkname ChipUsbSetPersistFlags C.chip_usb_set_persist_flags +func ChipUsbSetPersistFlags(flags c.Uint32T) diff --git a/esp32/clk_ctrl_os.go b/esp32/clk_ctrl_os.go new file mode 100644 index 00000000..b98dd6bf --- /dev/null +++ b/esp32/clk_ctrl_os.go @@ -0,0 +1,36 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief This function is used to enable the digital RC_FAST clock, + * to support the peripherals. + * + * @note If this function is called a number of times, the `periph_rtc_dig_clk8m_disable` + * function needs to be called same times to disable. + * + * @return true: success for enable the RC_FAST clock, false: RC_FAST clock enable failed + */ +//go:linkname PeriphRtcDigClk8mEnable C.periph_rtc_dig_clk8m_enable +func PeriphRtcDigClk8mEnable() bool + +/** + * @brief This function is used to disable the digital RC_FAST clock, which should be called + * with the `periph_rtc_dig_clk8m_enable` pairedly + * + * @note If this function is called a number of times, the `periph_rtc_dig_clk8m_disable` + * function needs to be called same times to disable. + */ +//go:linkname PeriphRtcDigClk8mDisable C.periph_rtc_dig_clk8m_disable +func PeriphRtcDigClk8mDisable() + +/** + * @brief This function is used to get the real clock frequency value of RC_FAST clock + * + * @return The real clock value, in Hz + */ +//go:linkname PeriphRtcDigClk8mGetFreq C.periph_rtc_dig_clk8m_get_freq +func PeriphRtcDigClk8mGetFreq() c.Uint32T diff --git a/esp32/clk_tree_defs.go b/esp32/clk_tree_defs.go new file mode 100644 index 00000000..69a6f755 --- /dev/null +++ b/esp32/clk_tree_defs.go @@ -0,0 +1,254 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const SOC_CLK_RC_FAST_FREQ_APPROX = 17500000 +const SOC_CLK_RC_SLOW_FREQ_APPROX = 136000 +const SOC_CLK_XTAL32K_FREQ_APPROX = 32768 + +type SocRootClkT c.Int + +const ( + SOC_ROOT_CLK_INT_RC_FAST SocRootClkT = 0 + SOC_ROOT_CLK_INT_RC_SLOW SocRootClkT = 1 + SOC_ROOT_CLK_EXT_XTAL SocRootClkT = 2 + SOC_ROOT_CLK_EXT_XTAL32K SocRootClkT = 3 +) + +type SocCpuClkSrcT c.Int + +const ( + SOC_CPU_CLK_SRC_XTAL SocCpuClkSrcT = 0 + SOC_CPU_CLK_SRC_PLL SocCpuClkSrcT = 1 + SOC_CPU_CLK_SRC_RC_FAST SocCpuClkSrcT = 2 + SOC_CPU_CLK_SRC_INVALID SocCpuClkSrcT = 3 +) + +type SocRtcSlowClkSrcT c.Int + +const ( + SOC_RTC_SLOW_CLK_SRC_RC_SLOW SocRtcSlowClkSrcT = 0 + SOC_RTC_SLOW_CLK_SRC_XTAL32K SocRtcSlowClkSrcT = 1 + SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 SocRtcSlowClkSrcT = 2 + SOC_RTC_SLOW_CLK_SRC_INVALID SocRtcSlowClkSrcT = 3 +) + +type SocRtcFastClkSrcT c.Int + +const ( + SOC_RTC_FAST_CLK_SRC_XTAL_D2 SocRtcFastClkSrcT = 0 + SOC_RTC_FAST_CLK_SRC_XTAL_DIV SocRtcFastClkSrcT = 0 + SOC_RTC_FAST_CLK_SRC_RC_FAST SocRtcFastClkSrcT = 1 + SOC_RTC_FAST_CLK_SRC_INVALID SocRtcFastClkSrcT = 2 +) + +type SocXtalFreqT c.Int + +const ( + SOC_XTAL_FREQ_32M SocXtalFreqT = 32 + SOC_XTAL_FREQ_40M SocXtalFreqT = 40 +) + +type SocModuleClkT c.Int + +const ( + SOC_MOD_CLK_CPU SocModuleClkT = 1 + SOC_MOD_CLK_RTC_FAST SocModuleClkT = 2 + SOC_MOD_CLK_RTC_SLOW SocModuleClkT = 3 + SOC_MOD_CLK_APB SocModuleClkT = 4 + SOC_MOD_CLK_PLL_F80M SocModuleClkT = 5 + SOC_MOD_CLK_PLL_F160M SocModuleClkT = 6 + SOC_MOD_CLK_PLL_D2 SocModuleClkT = 7 + SOC_MOD_CLK_XTAL32K SocModuleClkT = 8 + SOC_MOD_CLK_RC_FAST SocModuleClkT = 9 + SOC_MOD_CLK_RC_FAST_D256 SocModuleClkT = 10 + SOC_MOD_CLK_XTAL SocModuleClkT = 11 + SOC_MOD_CLK_TEMP_SENSOR SocModuleClkT = 12 + SOC_MOD_CLK_INVALID SocModuleClkT = 13 +) + +type SocPeriphSystimerClkSrcT c.Int + +const ( + SYSTIMER_CLK_SRC_XTAL SocPeriphSystimerClkSrcT = 11 + SYSTIMER_CLK_SRC_DEFAULT SocPeriphSystimerClkSrcT = 11 +) + +type SocPeriphGptimerClkSrcT c.Int + +const ( + GPTIMER_CLK_SRC_APB SocPeriphGptimerClkSrcT = 4 + GPTIMER_CLK_SRC_XTAL SocPeriphGptimerClkSrcT = 11 + GPTIMER_CLK_SRC_DEFAULT SocPeriphGptimerClkSrcT = 4 +) + +type SocPeriphTgClkSrcLegacyT c.Int + +const ( + TIMER_SRC_CLK_APB SocPeriphTgClkSrcLegacyT = 4 + TIMER_SRC_CLK_XTAL SocPeriphTgClkSrcLegacyT = 11 + TIMER_SRC_CLK_DEFAULT SocPeriphTgClkSrcLegacyT = 4 +) + +type SocPeriphLcdClkSrcT c.Int + +const ( + LCD_CLK_SRC_PLL160M SocPeriphLcdClkSrcT = 6 + LCD_CLK_SRC_PLL240M SocPeriphLcdClkSrcT = 7 + LCD_CLK_SRC_XTAL SocPeriphLcdClkSrcT = 11 + LCD_CLK_SRC_DEFAULT SocPeriphLcdClkSrcT = 6 +) + +type SocPeriphRmtClkSrcT c.Int + +const ( + RMT_CLK_SRC_APB SocPeriphRmtClkSrcT = 4 + RMT_CLK_SRC_RC_FAST SocPeriphRmtClkSrcT = 9 + RMT_CLK_SRC_XTAL SocPeriphRmtClkSrcT = 11 + RMT_CLK_SRC_DEFAULT SocPeriphRmtClkSrcT = 4 +) + +type SocPeriphRmtClkSrcLegacyT c.Int + +const ( + RMT_BASECLK_APB SocPeriphRmtClkSrcLegacyT = 4 + RMT_BASECLK_XTAL SocPeriphRmtClkSrcLegacyT = 11 + RMT_BASECLK_DEFAULT SocPeriphRmtClkSrcLegacyT = 4 +) + +type SocPeriphTemperatureSensorClkSrcT c.Int + +const ( + TEMPERATURE_SENSOR_CLK_SRC_RC_FAST SocPeriphTemperatureSensorClkSrcT = 12 + TEMPERATURE_SENSOR_CLK_SRC_DEFAULT SocPeriphTemperatureSensorClkSrcT = 12 +) + +type SocPeriphUartClkSrcLegacyT c.Int + +const ( + UART_SCLK_APB SocPeriphUartClkSrcLegacyT = 4 + UART_SCLK_RTC SocPeriphUartClkSrcLegacyT = 9 + UART_SCLK_XTAL SocPeriphUartClkSrcLegacyT = 11 + UART_SCLK_DEFAULT SocPeriphUartClkSrcLegacyT = 4 +) + +type SocPeriphMcpwmTimerClkSrcT c.Int + +const ( + MCPWM_TIMER_CLK_SRC_PLL160M SocPeriphMcpwmTimerClkSrcT = 6 + MCPWM_TIMER_CLK_SRC_DEFAULT SocPeriphMcpwmTimerClkSrcT = 6 +) + +type SocPeriphMcpwmCaptureClkSrcT c.Int + +const ( + MCPWM_CAPTURE_CLK_SRC_APB SocPeriphMcpwmCaptureClkSrcT = 4 + MCPWM_CAPTURE_CLK_SRC_DEFAULT SocPeriphMcpwmCaptureClkSrcT = 4 +) + +type SocPeriphMcpwmCarrierClkSrcT c.Int + +const ( + MCPWM_CARRIER_CLK_SRC_PLL160M SocPeriphMcpwmCarrierClkSrcT = 6 + MCPWM_CARRIER_CLK_SRC_DEFAULT SocPeriphMcpwmCarrierClkSrcT = 6 +) + +type SocPeriphI2sClkSrcT c.Int + +const ( + I2S_CLK_SRC_DEFAULT SocPeriphI2sClkSrcT = 6 + I2S_CLK_SRC_PLL_160M SocPeriphI2sClkSrcT = 6 + I2S_CLK_SRC_XTAL SocPeriphI2sClkSrcT = 11 + I2S_CLK_SRC_EXTERNAL SocPeriphI2sClkSrcT = -1 +) + +type SocPeriphI2cClkSrcT c.Int + +const ( + I2C_CLK_SRC_XTAL SocPeriphI2cClkSrcT = 11 + I2C_CLK_SRC_RC_FAST SocPeriphI2cClkSrcT = 9 + I2C_CLK_SRC_DEFAULT SocPeriphI2cClkSrcT = 11 +) + +type SocPeriphSpiClkSrcT c.Int + +const ( + SPI_CLK_SRC_DEFAULT SocPeriphSpiClkSrcT = 4 + SPI_CLK_SRC_APB SocPeriphSpiClkSrcT = 4 + SPI_CLK_SRC_XTAL SocPeriphSpiClkSrcT = 11 +) + +type SocPeriphSdmClkSrcT c.Int + +const ( + SDM_CLK_SRC_APB SocPeriphSdmClkSrcT = 4 + SDM_CLK_SRC_DEFAULT SocPeriphSdmClkSrcT = 4 +) + +type SocPeriphGlitchFilterClkSrcT c.Int + +const ( + GLITCH_FILTER_CLK_SRC_APB SocPeriphGlitchFilterClkSrcT = 4 + GLITCH_FILTER_CLK_SRC_DEFAULT SocPeriphGlitchFilterClkSrcT = 4 +) + +type SocPeriphTwaiClkSrcT c.Int + +const ( + TWAI_CLK_SRC_APB SocPeriphTwaiClkSrcT = 4 + TWAI_CLK_SRC_DEFAULT SocPeriphTwaiClkSrcT = 4 +) + +type SocPeriphAdcDigiClkSrcT c.Int + +const ( + ADC_DIGI_CLK_SRC_APB SocPeriphAdcDigiClkSrcT = 4 + ADC_DIGI_CLK_SRC_PLL_F240M SocPeriphAdcDigiClkSrcT = 7 + ADC_DIGI_CLK_SRC_DEFAULT SocPeriphAdcDigiClkSrcT = 4 +) + +type SocPeriphAdcRtcClkSrcT c.Int + +const ( + ADC_RTC_CLK_SRC_RC_FAST SocPeriphAdcRtcClkSrcT = 9 + ADC_RTC_CLK_SRC_DEFAULT SocPeriphAdcRtcClkSrcT = 9 +) + +type SocPeriphMwdtClkSrcT c.Int + +const ( + MWDT_CLK_SRC_APB SocPeriphMwdtClkSrcT = 4 + MWDT_CLK_SRC_DEFAULT SocPeriphMwdtClkSrcT = 4 +) + +type SocPeriphLedcClkSrcLegacyT c.Int + +const ( + LEDC_AUTO_CLK SocPeriphLedcClkSrcLegacyT = 0 + LEDC_USE_APB_CLK SocPeriphLedcClkSrcLegacyT = 4 + LEDC_USE_RC_FAST_CLK SocPeriphLedcClkSrcLegacyT = 9 + LEDC_USE_XTAL_CLK SocPeriphLedcClkSrcLegacyT = 11 + LEDC_USE_RTC8M_CLK SocPeriphLedcClkSrcLegacyT = 9 +) + +type SocPeriphSdmmcClkSrcT c.Int + +const ( + SDMMC_CLK_SRC_DEFAULT SocPeriphSdmmcClkSrcT = 6 + SDMMC_CLK_SRC_PLL160M SocPeriphSdmmcClkSrcT = 6 + SDMMC_CLK_SRC_XTAL SocPeriphSdmmcClkSrcT = 11 +) + +type SocClkoutSigIdT c.Int + +const ( + CLKOUT_SIG_PLL SocClkoutSigIdT = 1 + CLKOUT_SIG_RC_SLOW SocClkoutSigIdT = 4 + CLKOUT_SIG_XTAL SocClkoutSigIdT = 5 + CLKOUT_SIG_PLL_F80M SocClkoutSigIdT = 13 + CLKOUT_SIG_RC_FAST SocClkoutSigIdT = 14 + CLKOUT_SIG_INVALID SocClkoutSigIdT = 255 +) diff --git a/esp32/clk_tree_hal.go b/esp32/clk_tree_hal.go new file mode 100644 index 00000000..e1312612 --- /dev/null +++ b/esp32/clk_tree_hal.go @@ -0,0 +1,67 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Get SOC_ROOT_CLK frequency + * + * @param cpu_clk_src One of the clock sources in soc_cpu_clk_src_t + * + * @return SOC ROOT clock frequency, in MHz. Returns 0 if input argument is invalid. + */ +// llgo:link SocCpuClkSrcT.ClkHalSocRootGetFreqMhz C.clk_hal_soc_root_get_freq_mhz +func (recv_ SocCpuClkSrcT) ClkHalSocRootGetFreqMhz() c.Uint32T { + return 0 +} + +/** + * @brief Get CPU_CLK frequency + * + * @return CPU clock frequency, in Hz. Returns 0 if internal clock configuration is invalid. + */ +//go:linkname ClkHalCpuGetFreqHz C.clk_hal_cpu_get_freq_hz +func ClkHalCpuGetFreqHz() c.Uint32T + +/** + * @brief Get APB_CLK frequency + * + * @return APB clock frequency, in Hz. Returns 0 if internal clock configuration is invalid. + */ +//go:linkname ClkHalApbGetFreqHz C.clk_hal_apb_get_freq_hz +func ClkHalApbGetFreqHz() c.Uint32T + +/** + * @brief Get LP_SLOW_CLK (i.e. RTC_SLOW_CLK) approximate frequency + * + * @return LP Slow clock frequency, in Hz. Returns 0 if LP_SLOW clock source is invalid. + */ +//go:linkname ClkHalLpSlowGetFreqHz C.clk_hal_lp_slow_get_freq_hz +func ClkHalLpSlowGetFreqHz() c.Uint32T + +/** + * @brief Get XTAL_CLK frequency + * + * @return XTAL clock frequency, in MHz + */ +//go:linkname ClkHalXtalGetFreqMhz C.clk_hal_xtal_get_freq_mhz +func ClkHalXtalGetFreqMhz() c.Uint32T + +/** + * @brief Set up clock output channel + * @param clk_sig The clock signal source to be mapped to GPIOs + * @param channel_id The clock output channel to setup + */ +// llgo:link SocClkoutSigIdT.ClkHalClockOutputSetup C.clk_hal_clock_output_setup +func (recv_ SocClkoutSigIdT) ClkHalClockOutputSetup(channel_id ClockOutChannelT) { +} + +/** + * @brief Teardown clock output channel configuration + * @param channel_id The clock output channel to teardown + */ +// llgo:link ClockOutChannelT.ClkHalClockOutputTeardown C.clk_hal_clock_output_teardown +func (recv_ ClockOutChannelT) ClkHalClockOutputTeardown() { +} diff --git a/esp32/clk_tree_ll.go b/esp32/clk_tree_ll.go new file mode 100644 index 00000000..6658aa0a --- /dev/null +++ b/esp32/clk_tree_ll.go @@ -0,0 +1,28 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const CLK_LL_RC_FAST_WAIT_DEFAULT = 20 +const CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT = 5 + +type ClkLlXtal32kEnableModeT c.Int + +const ( + CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL ClkLlXtal32kEnableModeT = 0 + CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL ClkLlXtal32kEnableModeT = 1 + CLK_LL_XTAL32K_ENABLE_MODE_BOOTSTRAP ClkLlXtal32kEnableModeT = 2 +) + +/** + * @brief XTAL32K_CLK configuration structure + */ + +type ClkLlXtal32kConfigT struct { + Dac c.Uint32T + Dres c.Uint32T + Dgm c.Uint32T + Dbuf c.Uint32T +} diff --git a/esp32/clkout_channel.go b/esp32/clkout_channel.go new file mode 100644 index 00000000..456959de --- /dev/null +++ b/esp32/clkout_channel.go @@ -0,0 +1,17 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type ClockOutChannel c.Int + +const ( + CLKOUT_CHANNEL_1 ClockOutChannel = 0 + CLKOUT_CHANNEL_2 ClockOutChannel = 1 + CLKOUT_CHANNEL_3 ClockOutChannel = 2 + CLKOUT_CHANNEL_MAX ClockOutChannel = 3 +) + +type ClockOutChannelT ClockOutChannel diff --git a/esp32/color_hal.go b/esp32/color_hal.go new file mode 100644 index 00000000..bdfe36aa --- /dev/null +++ b/esp32/color_hal.go @@ -0,0 +1,18 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Get the bit depth (bits/pixel) of each color space pixel format + * + * @param color_type_id Value constructed in color_space_pixel_format_t struct + * + * @return Number of bits per pixel + */ +// llgo:link ColorSpacePixelFormatT.ColorHalPixelFormatGetBitDepth C.color_hal_pixel_format_get_bit_depth +func (recv_ ColorSpacePixelFormatT) ColorHalPixelFormatGetBitDepth() c.Uint32T { + return 0 +} diff --git a/esp32/color_types.go b/esp32/color_types.go new file mode 100644 index 00000000..f910abaf --- /dev/null +++ b/esp32/color_types.go @@ -0,0 +1,151 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const COLOR_SPACE_BITWIDTH = 8 +const COLOR_PIXEL_FORMAT_BITWIDTH = 24 + +type ColorSpaceT c.Int + +const ( + COLOR_SPACE_RAW ColorSpaceT = 1 + COLOR_SPACE_RGB ColorSpaceT = 2 + COLOR_SPACE_YUV ColorSpaceT = 3 + COLOR_SPACE_GRAY ColorSpaceT = 4 + COLOR_SPACE_ARGB ColorSpaceT = 5 + COLOR_SPACE_ALPHA ColorSpaceT = 6 + COLOR_SPACE_CLUT ColorSpaceT = 7 +) + +type ColorPixelRawFormatT c.Int + +const ( + COLOR_PIXEL_RAW8 ColorPixelRawFormatT = 0 + COLOR_PIXEL_RAW10 ColorPixelRawFormatT = 1 + COLOR_PIXEL_RAW12 ColorPixelRawFormatT = 2 +) + +type ColorPixelRgbFormatT c.Int + +const ( + COLOR_PIXEL_RGB888 ColorPixelRgbFormatT = 0 + COLOR_PIXEL_RGB666 ColorPixelRgbFormatT = 1 + COLOR_PIXEL_RGB565 ColorPixelRgbFormatT = 2 +) + +type ColorPixelYuvFormatT c.Int + +const ( + COLOR_PIXEL_YUV444 ColorPixelYuvFormatT = 0 + COLOR_PIXEL_YUV422 ColorPixelYuvFormatT = 1 + COLOR_PIXEL_YUV420 ColorPixelYuvFormatT = 2 + COLOR_PIXEL_YUV411 ColorPixelYuvFormatT = 3 +) + +type ColorPixelGrayFormatT c.Int + +const ( + COLOR_PIXEL_GRAY4 ColorPixelGrayFormatT = 0 + COLOR_PIXEL_GRAY8 ColorPixelGrayFormatT = 1 +) + +type ColorPixelArgbFormatT c.Int + +const COLOR_PIXEL_ARGB8888 ColorPixelArgbFormatT = 0 + +type ColorPixelAlphaFormatT c.Int + +const ( + COLOR_PIXEL_A4 ColorPixelAlphaFormatT = 0 + COLOR_PIXEL_A8 ColorPixelAlphaFormatT = 1 +) + +type ColorPixelClutFormatT c.Int + +const ( + COLOR_PIXEL_L4 ColorPixelClutFormatT = 0 + COLOR_PIXEL_L8 ColorPixelClutFormatT = 1 +) + +/** + * @brief Color Space Info Structure + */ + +type ColorSpacePixelFormatT struct { + ColorTypeId c.Uint32T +} +type ColorRangeT c.Int + +const ( + COLOR_RANGE_LIMIT ColorRangeT = 0 + COLOR_RANGE_FULL ColorRangeT = 1 +) + +type ColorConvStdRgbYuvT c.Int + +const ( + COLOR_CONV_STD_RGB_YUV_BT601 ColorConvStdRgbYuvT = 0 + COLOR_CONV_STD_RGB_YUV_BT709 ColorConvStdRgbYuvT = 1 +) + +type ColorRawElementOrderT c.Int + +const ( + COLOR_RAW_ELEMENT_ORDER_BGGR ColorRawElementOrderT = 0 + COLOR_RAW_ELEMENT_ORDER_GBRG ColorRawElementOrderT = 1 + COLOR_RAW_ELEMENT_ORDER_GRBG ColorRawElementOrderT = 2 + COLOR_RAW_ELEMENT_ORDER_RGGB ColorRawElementOrderT = 3 +) + +type ColorRgbElementOrderT c.Int + +const ( + COLOR_RGB_ELEMENT_ORDER_RGB ColorRgbElementOrderT = 0 + COLOR_RGB_ELEMENT_ORDER_BGR ColorRgbElementOrderT = 1 +) + +/** + * @brief Data structure for ARGB8888 pixel unit + */ + +type ColorPixelArgb8888DataT struct { + Val c.Uint32T +} + +/** + * @brief Data structure for RGB888 pixel unit + */ + +type ColorPixelRgb888DataT struct { + B c.Uint8T + G c.Uint8T + R c.Uint8T +} + +/** + * @brief Data structure for RGB565 pixel unit + */ + +type ColorPixelRgb565DataT struct { + Val c.Uint16T +} +type ColorComponentT c.Int + +const ( + COLOR_COMPONENT_R ColorComponentT = 0 + COLOR_COMPONENT_G ColorComponentT = 1 + COLOR_COMPONENT_B ColorComponentT = 2 + COLOR_COMPONENT_INVALID ColorComponentT = 3 +) + +type ColorYuv422PackOrderT c.Int + +const ( + COLOR_YUV422_PACK_ORDER_YUYV ColorYuv422PackOrderT = 0 + COLOR_YUV422_PACK_ORDER_YVYU ColorYuv422PackOrderT = 1 + COLOR_YUV422_PACK_ORDER_UYVY ColorYuv422PackOrderT = 2 + COLOR_YUV422_PACK_ORDER_VYUY ColorYuv422PackOrderT = 3 +) diff --git a/esp32/core-isa.go b/esp32/core-isa.go new file mode 100644 index 00000000..48e7b291 --- /dev/null +++ b/esp32/core-isa.go @@ -0,0 +1,434 @@ +package freertos + +import _ "unsafe" + +const XCHAL_HAVE_BE = 0 +const XCHAL_HAVE_WINDOWED = 1 +const XCHAL_NUM_AREGS = 64 +const XCHAL_NUM_AREGS_LOG2 = 6 +const XCHAL_MAX_INSTRUCTION_SIZE = 4 +const XCHAL_HAVE_DEBUG = 1 +const XCHAL_HAVE_DENSITY = 1 +const XCHAL_HAVE_LOOPS = 1 +const XCHAL_LOOP_BUFFER_SIZE = 256 +const XCHAL_HAVE_NSA = 1 +const XCHAL_HAVE_MINMAX = 1 +const XCHAL_HAVE_SEXT = 1 +const XCHAL_HAVE_DEPBITS = 0 +const XCHAL_HAVE_CLAMPS = 1 +const XCHAL_HAVE_MUL16 = 1 +const XCHAL_HAVE_MUL32 = 1 +const XCHAL_HAVE_MUL32_HIGH = 1 +const XCHAL_HAVE_DIV32 = 1 +const XCHAL_HAVE_L32R = 1 +const XCHAL_HAVE_ABSOLUTE_LITERALS = 0 +const XCHAL_HAVE_CONST16 = 0 +const XCHAL_HAVE_ADDX = 1 +const XCHAL_HAVE_EXCLUSIVE = 0 +const XCHAL_HAVE_WIDE_BRANCHES = 0 +const XCHAL_HAVE_PREDICTED_BRANCHES = 0 +const XCHAL_HAVE_CALL4AND12 = 1 +const XCHAL_HAVE_ABS = 1 +const XCHAL_HAVE_RELEASE_SYNC = 1 +const XCHAL_HAVE_S32C1I = 1 +const XCHAL_HAVE_SPECULATION = 0 +const XCHAL_HAVE_FULL_RESET = 1 +const XCHAL_NUM_CONTEXTS = 1 +const XCHAL_NUM_MISC_REGS = 4 +const XCHAL_HAVE_TAP_MASTER = 0 +const XCHAL_HAVE_PRID = 1 +const XCHAL_HAVE_EXTERN_REGS = 1 +const XCHAL_HAVE_MX = 0 +const XCHAL_HAVE_MP_INTERRUPTS = 0 +const XCHAL_HAVE_MP_RUNSTALL = 0 +const XCHAL_HAVE_PSO = 0 +const XCHAL_HAVE_PSO_CDM = 0 +const XCHAL_HAVE_PSO_FULL_RETENTION = 0 +const XCHAL_HAVE_THREADPTR = 1 +const XCHAL_HAVE_BOOLEANS = 1 +const XCHAL_HAVE_CP = 1 +const XCHAL_CP_MAXCFG = 8 +const XCHAL_HAVE_MAC16 = 1 +const XCHAL_HAVE_FUSION = 0 +const XCHAL_HAVE_FUSION_FP = 0 +const XCHAL_HAVE_FUSION_LOW_POWER = 0 +const XCHAL_HAVE_FUSION_AES = 0 +const XCHAL_HAVE_FUSION_CONVENC = 0 +const XCHAL_HAVE_FUSION_LFSR_CRC = 0 +const XCHAL_HAVE_FUSION_BITOPS = 0 +const XCHAL_HAVE_FUSION_AVS = 0 +const XCHAL_HAVE_FUSION_16BIT_BASEBAND = 0 +const XCHAL_HAVE_FUSION_VITERBI = 0 +const XCHAL_HAVE_FUSION_SOFTDEMAP = 0 +const XCHAL_HAVE_HIFIPRO = 0 +const XCHAL_HAVE_HIFI5 = 0 +const XCHAL_HAVE_HIFI5_NN_MAC = 0 +const XCHAL_HAVE_HIFI5_VFPU = 0 +const XCHAL_HAVE_HIFI5_HP_VFPU = 0 +const XCHAL_HAVE_HIFI4 = 0 +const XCHAL_HAVE_HIFI4_VFPU = 0 +const XCHAL_HAVE_HIFI3 = 0 +const XCHAL_HAVE_HIFI3_VFPU = 0 +const XCHAL_HAVE_HIFI3Z = 0 +const XCHAL_HAVE_HIFI3Z_VFPU = 0 +const XCHAL_HAVE_HIFI2 = 0 +const XCHAL_HAVE_HIFI2EP = 0 +const XCHAL_HAVE_HIFI_MINI = 0 +const XCHAL_HAVE_VECTORFPU2005 = 0 +const XCHAL_HAVE_USER_DPFPU = 0 +const XCHAL_HAVE_USER_SPFPU = 0 +const XCHAL_HAVE_FP = 1 +const XCHAL_HAVE_FP_DIV = 1 +const XCHAL_HAVE_FP_RECIP = 1 +const XCHAL_HAVE_FP_SQRT = 1 +const XCHAL_HAVE_FP_RSQRT = 1 +const XCHAL_HAVE_DFP = 0 +const XCHAL_HAVE_DFP_DIV = 0 +const XCHAL_HAVE_DFP_RECIP = 0 +const XCHAL_HAVE_DFP_SQRT = 0 +const XCHAL_HAVE_DFP_RSQRT = 0 +const XCHAL_HAVE_DFP_ACCEL = 0 +const XCHAL_HAVE_DFPU_SINGLE_ONLY = 1 +const XCHAL_HAVE_DFPU_SINGLE_DOUBLE = 0 +const XCHAL_HAVE_VECTRA1 = 0 +const XCHAL_HAVE_VECTRALX = 0 +const XCHAL_HAVE_FUSIONG = 0 +const XCHAL_HAVE_FUSIONG3 = 0 +const XCHAL_HAVE_FUSIONG6 = 0 +const XCHAL_HAVE_FUSIONG_SP_VFPU = 0 +const XCHAL_HAVE_FUSIONG_DP_VFPU = 0 +const XCHAL_FUSIONG_SIMD32 = 0 +const XCHAL_HAVE_PDX = 0 +const XCHAL_PDX_SIMD32 = 0 +const XCHAL_HAVE_PDX4 = 0 +const XCHAL_HAVE_PDX8 = 0 +const XCHAL_HAVE_PDX16 = 0 +const XCHAL_HAVE_CONNXD2 = 0 +const XCHAL_HAVE_CONNXD2_DUALLSFLIX = 0 +const XCHAL_HAVE_BBE16 = 0 +const XCHAL_HAVE_BBE16_RSQRT = 0 +const XCHAL_HAVE_BBE16_VECDIV = 0 +const XCHAL_HAVE_BBE16_DESPREAD = 0 +const XCHAL_HAVE_BBENEP = 0 +const XCHAL_HAVE_BBENEP_SP_VFPU = 0 +const XCHAL_HAVE_BSP3 = 0 +const XCHAL_HAVE_BSP3_TRANSPOSE = 0 +const XCHAL_HAVE_SSP16 = 0 +const XCHAL_HAVE_SSP16_VITERBI = 0 +const XCHAL_HAVE_TURBO16 = 0 +const XCHAL_HAVE_BBP16 = 0 +const XCHAL_HAVE_FLIX3 = 0 +const XCHAL_HAVE_GRIVPEP = 0 +const XCHAL_HAVE_GRIVPEP_HISTOGRAM = 0 +const XCHAL_HAVE_VISION = 0 +const XCHAL_VISION_SIMD16 = 0 +const XCHAL_VISION_TYPE = 0 +const XCHAL_VISION_QUAD_MAC_TYPE = 0 +const XCHAL_HAVE_VISION_HISTOGRAM = 0 +const XCHAL_HAVE_VISION_SP_VFPU = 0 +const XCHAL_HAVE_VISION_HP_VFPU = 0 +const XCHAL_HAVE_VISIONC = 0 +const XCHAL_NUM_LOADSTORE_UNITS = 1 +const XCHAL_NUM_WRITEBUFFER_ENTRIES = 4 +const XCHAL_INST_FETCH_WIDTH = 4 +const XCHAL_DATA_WIDTH = 16 +const XCHAL_DATA_PIPE_DELAY = 1 +const XCHAL_CLOCK_GATING_GLOBAL = 1 +const XCHAL_CLOCK_GATING_FUNCUNIT = 1 +const XCHAL_UNALIGNED_LOAD_EXCEPTION = 0 +const XCHAL_UNALIGNED_STORE_EXCEPTION = 0 +const XCHAL_UNALIGNED_LOAD_HW = 1 +const XCHAL_UNALIGNED_STORE_HW = 1 +const XCHAL_SW_VERSION = 1200012 +const XCHAL_CORE_ID = "LX7_ESP32_S3_MP" +const XCHAL_BUILD_UNIQUE_ID = 0x00090F1F +const XCHAL_HW_CONFIGID0 = 0xC2F0FFFE +const XCHAL_HW_CONFIGID1 = 0x23090F1F +const XCHAL_HW_VERSION_NAME = "LX7.0.12" +const XCHAL_HW_VERSION_MAJOR = 2700 +const XCHAL_HW_VERSION_MINOR = 12 +const XCHAL_HW_VERSION = 270012 +const XCHAL_HW_REL_LX7 = 1 +const XCHAL_HW_REL_LX7_0 = 1 +const XCHAL_HW_REL_LX7_0_12 = 1 +const XCHAL_HW_CONFIGID_RELIABLE = 1 +const XCHAL_HW_MIN_VERSION_MAJOR = 2700 +const XCHAL_HW_MIN_VERSION_MINOR = 12 +const XCHAL_HW_MIN_VERSION = 270012 +const XCHAL_HW_MAX_VERSION_MAJOR = 2700 +const XCHAL_HW_MAX_VERSION_MINOR = 12 +const XCHAL_HW_MAX_VERSION = 270012 +const XCHAL_ICACHE_LINESIZE = 4 +const XCHAL_DCACHE_LINESIZE = 16 +const XCHAL_ICACHE_LINEWIDTH = 2 +const XCHAL_DCACHE_LINEWIDTH = 4 +const XCHAL_ICACHE_SIZE = 0 +const XCHAL_DCACHE_SIZE = 0 +const XCHAL_DCACHE_IS_WRITEBACK = 0 +const XCHAL_DCACHE_IS_COHERENT = 0 +const XCHAL_HAVE_PREFETCH = 0 +const XCHAL_HAVE_PREFETCH_L1 = 0 +const XCHAL_PREFETCH_CASTOUT_LINES = 0 +const XCHAL_PREFETCH_ENTRIES = 0 +const XCHAL_PREFETCH_BLOCK_ENTRIES = 0 +const XCHAL_HAVE_CACHE_BLOCKOPS = 0 +const XCHAL_HAVE_ICACHE_TEST = 0 +const XCHAL_HAVE_DCACHE_TEST = 0 +const XCHAL_HAVE_ICACHE_DYN_WAYS = 0 +const XCHAL_HAVE_DCACHE_DYN_WAYS = 0 +const XCHAL_HAVE_PIF = 1 +const XCHAL_HAVE_AXI = 0 +const XCHAL_HAVE_AXI_ECC = 0 +const XCHAL_HAVE_ACELITE = 0 +const XCHAL_HAVE_PIF_WR_RESP = 0 +const XCHAL_HAVE_PIF_REQ_ATTR = 1 +const XCHAL_ICACHE_SETWIDTH = 0 +const XCHAL_DCACHE_SETWIDTH = 0 +const XCHAL_ICACHE_WAYS = 1 +const XCHAL_DCACHE_WAYS = 1 +const XCHAL_ICACHE_LINE_LOCKABLE = 0 +const XCHAL_DCACHE_LINE_LOCKABLE = 0 +const XCHAL_ICACHE_ECC_PARITY = 0 +const XCHAL_DCACHE_ECC_PARITY = 0 +const XCHAL_ICACHE_ECC_WIDTH = 1 +const XCHAL_DCACHE_ECC_WIDTH = 1 +const XCHAL_ICACHE_ACCESS_SIZE = 1 +const XCHAL_DCACHE_ACCESS_SIZE = 1 +const XCHAL_DCACHE_BANKS = 0 +const XCHAL_CA_BITS = 4 +const XCHAL_NUM_INSTROM = 0 +const XCHAL_NUM_INSTRAM = 1 +const XCHAL_NUM_DATAROM = 0 +const XCHAL_NUM_DATARAM = 1 +const XCHAL_NUM_URAM = 0 +const XCHAL_NUM_XLMI = 0 +const XCHAL_INSTRAM0_VADDR = 0x40000000 +const XCHAL_INSTRAM0_PADDR = 0x40000000 +const XCHAL_INSTRAM0_SIZE = 67108864 +const XCHAL_INSTRAM0_ECC_PARITY = 0 +const XCHAL_HAVE_INSTRAM0 = 1 +const XCHAL_INSTRAM0_HAVE_IDMA = 0 +const XCHAL_DATARAM0_VADDR = 0x3C000000 +const XCHAL_DATARAM0_PADDR = 0x3C000000 +const XCHAL_DATARAM0_SIZE = 67108864 +const XCHAL_DATARAM0_ECC_PARITY = 0 +const XCHAL_DATARAM0_BANKS = 1 +const XCHAL_HAVE_DATARAM0 = 1 +const XCHAL_DATARAM0_HAVE_IDMA = 0 +const XCHAL_HAVE_IDMA = 0 +const XCHAL_HAVE_IDMA_TRANSPOSE = 0 +const XCHAL_HAVE_IMEM_LOADSTORE = 1 +const XCHAL_HAVE_INTERRUPTS = 1 +const XCHAL_HAVE_HIGHPRI_INTERRUPTS = 1 +const XCHAL_HAVE_NMI = 1 +const XCHAL_HAVE_CCOUNT = 1 +const XCHAL_NUM_TIMERS = 3 +const XCHAL_NUM_INTERRUPTS = 32 +const XCHAL_NUM_INTERRUPTS_LOG2 = 5 +const XCHAL_NUM_EXTINTERRUPTS = 26 +const XCHAL_NUM_INTLEVELS = 6 +const XCHAL_EXCM_LEVEL = 3 +const XCHAL_INTLEVEL1_MASK = 0x000637FF +const XCHAL_INTLEVEL2_MASK = 0x00380000 +const XCHAL_INTLEVEL3_MASK = 0x28C08800 +const XCHAL_INTLEVEL4_MASK = 0x53000000 +const XCHAL_INTLEVEL5_MASK = 0x84010000 +const XCHAL_INTLEVEL6_MASK = 0x00000000 +const XCHAL_INTLEVEL7_MASK = 0x00004000 +const XCHAL_INTLEVEL1_ANDBELOW_MASK = 0x000637FF +const XCHAL_INTLEVEL2_ANDBELOW_MASK = 0x003E37FF +const XCHAL_INTLEVEL3_ANDBELOW_MASK = 0x28FEBFFF +const XCHAL_INTLEVEL4_ANDBELOW_MASK = 0x7BFEBFFF +const XCHAL_INTLEVEL5_ANDBELOW_MASK = 0xFFFFBFFF +const XCHAL_INTLEVEL6_ANDBELOW_MASK = 0xFFFFBFFF +const XCHAL_INTLEVEL7_ANDBELOW_MASK = 0xFFFFFFFF +const XCHAL_INT0_LEVEL = 1 +const XCHAL_INT1_LEVEL = 1 +const XCHAL_INT2_LEVEL = 1 +const XCHAL_INT3_LEVEL = 1 +const XCHAL_INT4_LEVEL = 1 +const XCHAL_INT5_LEVEL = 1 +const XCHAL_INT6_LEVEL = 1 +const XCHAL_INT7_LEVEL = 1 +const XCHAL_INT8_LEVEL = 1 +const XCHAL_INT9_LEVEL = 1 +const XCHAL_INT10_LEVEL = 1 +const XCHAL_INT11_LEVEL = 3 +const XCHAL_INT12_LEVEL = 1 +const XCHAL_INT13_LEVEL = 1 +const XCHAL_INT14_LEVEL = 7 +const XCHAL_INT15_LEVEL = 3 +const XCHAL_INT16_LEVEL = 5 +const XCHAL_INT17_LEVEL = 1 +const XCHAL_INT18_LEVEL = 1 +const XCHAL_INT19_LEVEL = 2 +const XCHAL_INT20_LEVEL = 2 +const XCHAL_INT21_LEVEL = 2 +const XCHAL_INT22_LEVEL = 3 +const XCHAL_INT23_LEVEL = 3 +const XCHAL_INT24_LEVEL = 4 +const XCHAL_INT25_LEVEL = 4 +const XCHAL_INT26_LEVEL = 5 +const XCHAL_INT27_LEVEL = 3 +const XCHAL_INT28_LEVEL = 4 +const XCHAL_INT29_LEVEL = 3 +const XCHAL_INT30_LEVEL = 4 +const XCHAL_INT31_LEVEL = 5 +const XCHAL_DEBUGLEVEL = 6 +const XCHAL_HAVE_DEBUG_EXTERN_INT = 1 +const XCHAL_NMILEVEL = 7 +const XCHAL_INTTYPE_MASK_UNCONFIGURED = 0x00000000 +const XCHAL_INTTYPE_MASK_SOFTWARE = 0x20000080 +const XCHAL_INTTYPE_MASK_EXTERN_EDGE = 0x50400400 +const XCHAL_INTTYPE_MASK_EXTERN_LEVEL = 0x8FBE333F +const XCHAL_INTTYPE_MASK_TIMER = 0x00018040 +const XCHAL_INTTYPE_MASK_NMI = 0x00004000 +const XCHAL_INTTYPE_MASK_WRITE_ERROR = 0x00000000 +const XCHAL_INTTYPE_MASK_PROFILING = 0x00000800 +const XCHAL_INTTYPE_MASK_IDMA_DONE = 0x00000000 +const XCHAL_INTTYPE_MASK_IDMA_ERR = 0x00000000 +const XCHAL_INTTYPE_MASK_GS_ERR = 0x00000000 +const XCHAL_TIMER0_INTERRUPT = 6 +const XCHAL_TIMER1_INTERRUPT = 15 +const XCHAL_TIMER2_INTERRUPT = 16 +const XCHAL_NMI_INTERRUPT = 14 +const XCHAL_PROFILING_INTERRUPT = 11 +const XCHAL_INTLEVEL7_NUM = 14 +const XCHAL_EXTINT0_NUM = 0 +const XCHAL_EXTINT1_NUM = 1 +const XCHAL_EXTINT2_NUM = 2 +const XCHAL_EXTINT3_NUM = 3 +const XCHAL_EXTINT4_NUM = 4 +const XCHAL_EXTINT5_NUM = 5 +const XCHAL_EXTINT6_NUM = 8 +const XCHAL_EXTINT7_NUM = 9 +const XCHAL_EXTINT8_NUM = 10 +const XCHAL_EXTINT9_NUM = 12 +const XCHAL_EXTINT10_NUM = 13 +const XCHAL_EXTINT11_NUM = 14 +const XCHAL_EXTINT12_NUM = 17 +const XCHAL_EXTINT13_NUM = 18 +const XCHAL_EXTINT14_NUM = 19 +const XCHAL_EXTINT15_NUM = 20 +const XCHAL_EXTINT16_NUM = 21 +const XCHAL_EXTINT17_NUM = 22 +const XCHAL_EXTINT18_NUM = 23 +const XCHAL_EXTINT19_NUM = 24 +const XCHAL_EXTINT20_NUM = 25 +const XCHAL_EXTINT21_NUM = 26 +const XCHAL_EXTINT22_NUM = 27 +const XCHAL_EXTINT23_NUM = 28 +const XCHAL_EXTINT24_NUM = 30 +const XCHAL_EXTINT25_NUM = 31 +const XCHAL_INT0_EXTNUM = 0 +const XCHAL_INT1_EXTNUM = 1 +const XCHAL_INT2_EXTNUM = 2 +const XCHAL_INT3_EXTNUM = 3 +const XCHAL_INT4_EXTNUM = 4 +const XCHAL_INT5_EXTNUM = 5 +const XCHAL_INT8_EXTNUM = 6 +const XCHAL_INT9_EXTNUM = 7 +const XCHAL_INT10_EXTNUM = 8 +const XCHAL_INT12_EXTNUM = 9 +const XCHAL_INT13_EXTNUM = 10 +const XCHAL_INT14_EXTNUM = 11 +const XCHAL_INT17_EXTNUM = 12 +const XCHAL_INT18_EXTNUM = 13 +const XCHAL_INT19_EXTNUM = 14 +const XCHAL_INT20_EXTNUM = 15 +const XCHAL_INT21_EXTNUM = 16 +const XCHAL_INT22_EXTNUM = 17 +const XCHAL_INT23_EXTNUM = 18 +const XCHAL_INT24_EXTNUM = 19 +const XCHAL_INT25_EXTNUM = 20 +const XCHAL_INT26_EXTNUM = 21 +const XCHAL_INT27_EXTNUM = 22 +const XCHAL_INT28_EXTNUM = 23 +const XCHAL_INT30_EXTNUM = 24 +const XCHAL_INT31_EXTNUM = 25 +const XCHAL_XEA_VERSION = 2 +const XCHAL_HAVE_XEA1 = 0 +const XCHAL_HAVE_XEA2 = 1 +const XCHAL_HAVE_XEAX = 0 +const XCHAL_HAVE_EXCEPTIONS = 1 +const XCHAL_HAVE_HALT = 0 +const XCHAL_HAVE_BOOTLOADER = 0 +const XCHAL_HAVE_MEM_ECC_PARITY = 0 +const XCHAL_HAVE_VECTOR_SELECT = 1 +const XCHAL_HAVE_VECBASE = 1 +const XCHAL_VECBASE_RESET_VADDR = 0x40000000 +const XCHAL_VECBASE_RESET_PADDR = 0x40000000 +const XCHAL_RESET_VECBASE_OVERLAP = 0 +const XCHAL_RESET_VECTOR0_VADDR = 0x50000000 +const XCHAL_RESET_VECTOR0_PADDR = 0x50000000 +const XCHAL_RESET_VECTOR1_VADDR = 0x40000400 +const XCHAL_RESET_VECTOR1_PADDR = 0x40000400 +const XCHAL_RESET_VECTOR_VADDR = 0x40000400 +const XCHAL_RESET_VECTOR_PADDR = 0x40000400 +const XCHAL_USER_VECOFS = 0x00000340 +const XCHAL_USER_VECTOR_VADDR = 0x40000340 +const XCHAL_USER_VECTOR_PADDR = 0x40000340 +const XCHAL_KERNEL_VECOFS = 0x00000300 +const XCHAL_KERNEL_VECTOR_VADDR = 0x40000300 +const XCHAL_KERNEL_VECTOR_PADDR = 0x40000300 +const XCHAL_DOUBLEEXC_VECOFS = 0x000003C0 +const XCHAL_DOUBLEEXC_VECTOR_VADDR = 0x400003C0 +const XCHAL_DOUBLEEXC_VECTOR_PADDR = 0x400003C0 +const XCHAL_WINDOW_OF4_VECOFS = 0x00000000 +const XCHAL_WINDOW_UF4_VECOFS = 0x00000040 +const XCHAL_WINDOW_OF8_VECOFS = 0x00000080 +const XCHAL_WINDOW_UF8_VECOFS = 0x000000C0 +const XCHAL_WINDOW_OF12_VECOFS = 0x00000100 +const XCHAL_WINDOW_UF12_VECOFS = 0x00000140 +const XCHAL_WINDOW_VECTORS_VADDR = 0x40000000 +const XCHAL_WINDOW_VECTORS_PADDR = 0x40000000 +const XCHAL_INTLEVEL2_VECOFS = 0x00000180 +const XCHAL_INTLEVEL2_VECTOR_VADDR = 0x40000180 +const XCHAL_INTLEVEL2_VECTOR_PADDR = 0x40000180 +const XCHAL_INTLEVEL3_VECOFS = 0x000001C0 +const XCHAL_INTLEVEL3_VECTOR_VADDR = 0x400001C0 +const XCHAL_INTLEVEL3_VECTOR_PADDR = 0x400001C0 +const XCHAL_INTLEVEL4_VECOFS = 0x00000200 +const XCHAL_INTLEVEL4_VECTOR_VADDR = 0x40000200 +const XCHAL_INTLEVEL4_VECTOR_PADDR = 0x40000200 +const XCHAL_INTLEVEL5_VECOFS = 0x00000240 +const XCHAL_INTLEVEL5_VECTOR_VADDR = 0x40000240 +const XCHAL_INTLEVEL5_VECTOR_PADDR = 0x40000240 +const XCHAL_INTLEVEL6_VECOFS = 0x00000280 +const XCHAL_INTLEVEL6_VECTOR_VADDR = 0x40000280 +const XCHAL_INTLEVEL6_VECTOR_PADDR = 0x40000280 +const XCHAL_NMI_VECOFS = 0x000002C0 +const XCHAL_NMI_VECTOR_VADDR = 0x400002C0 +const XCHAL_NMI_VECTOR_PADDR = 0x400002C0 +const XCHAL_HAVE_DEBUG_ERI = 1 +const XCHAL_HAVE_DEBUG_APB = 0 +const XCHAL_HAVE_DEBUG_JTAG = 1 +const XCHAL_HAVE_OCD = 1 +const XCHAL_NUM_IBREAK = 2 +const XCHAL_NUM_DBREAK = 2 +const XCHAL_HAVE_OCD_DIR_ARRAY = 0 +const XCHAL_HAVE_OCD_LS32DDR = 1 +const XCHAL_HAVE_TRAX = 1 +const XCHAL_TRAX_MEM_SIZE = 16384 +const XCHAL_TRAX_MEM_SHAREABLE = 1 +const XCHAL_TRAX_ATB_WIDTH = 0 +const XCHAL_TRAX_TIME_WIDTH = 0 +const XCHAL_NUM_PERF_COUNTERS = 2 +const XCHAL_HAVE_TLBS = 1 +const XCHAL_HAVE_SPANNING_WAY = 1 +const XCHAL_SPANNING_WAY = 0 +const XCHAL_HAVE_IDENTITY_MAP = 1 +const XCHAL_HAVE_CACHEATTR = 0 +const XCHAL_HAVE_MIMIC_CACHEATTR = 1 +const XCHAL_HAVE_XLT_CACHEATTR = 0 +const XCHAL_HAVE_PTP_MMU = 0 +const XCHAL_MMU_ASID_BITS = 0 +const XCHAL_MMU_RINGS = 1 +const XCHAL_MMU_RING_BITS = 0 +const XCHAL_HAVE_MPU = 0 +const XCHAL_MPU_ENTRIES = 0 +const XCHAL_MPU_ALIGN_REQ = 1 +const XCHAL_MPU_BACKGROUND_ENTRIES = 0 +const XCHAL_MPU_BG_CACHEADRDIS = 0 +const XCHAL_MPU_ALIGN_BITS = 0 +const XCHAL_MPU_ALIGN = 0 diff --git a/esp32/core-macros.go b/esp32/core-macros.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/core-macros.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/core-matmap.go b/esp32/core-matmap.go new file mode 100644 index 00000000..e5322703 --- /dev/null +++ b/esp32/core-matmap.go @@ -0,0 +1,120 @@ +package freertos + +import _ "unsafe" + +const XCHAL_CA_BYPASS = 2 +const XCHAL_CA_BYPASSBUF = 6 +const XCHAL_CA_WRITETHRU = 1 +const XCHAL_CA_WRITEBACK = 2 +const XCHAL_HAVE_CA_WRITEBACK_NOALLOC = 0 +const XCHAL_CA_WRITEBACK_NOALLOC = 2 +const XCHAL_CA_BYPASS_RW = 0 +const XCHAL_CA_WRITETHRU_RW = 0 +const XCHAL_CA_WRITEBACK_RW = 0 +const XCHAL_CA_WRITEBACK_NOALLOC_RW = 0 +const XCHAL_CA_ILLEGAL = 15 +const XCHAL_CA_ISOLATE = 0 +const XCHAL_MMU_ASID_INVALID = 0 +const XCHAL_MMU_ASID_KERNEL = 0 +const XCHAL_MMU_SR_BITS = 0 +const XCHAL_MMU_CA_BITS = 4 +const XCHAL_MMU_MAX_PTE_PAGE_SIZE = 29 +const XCHAL_MMU_MIN_PTE_PAGE_SIZE = 29 +const XCHAL_ITLB_WAY_BITS = 0 +const XCHAL_ITLB_WAYS = 1 +const XCHAL_ITLB_ARF_WAYS = 0 +const XCHAL_ITLB_SETS = 1 +const XCHAL_ITLB_WAY0_SET = 0 +const XCHAL_ITLB_ARF_SETS = 0 +const XCHAL_ITLB_MINWIRED_SETS = 0 +const XCHAL_ITLB_SET0_WAY = 0 +const XCHAL_ITLB_SET0_WAYS = 1 +const XCHAL_ITLB_SET0_ENTRIES_LOG2 = 3 +const XCHAL_ITLB_SET0_ENTRIES = 8 +const XCHAL_ITLB_SET0_ARF = 0 +const XCHAL_ITLB_SET0_PAGESIZES = 1 +const XCHAL_ITLB_SET0_PAGESZ_BITS = 0 +const XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN = 29 +const XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX = 29 +const XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST = 29 +const XCHAL_ITLB_SET0_ASID_CONSTMASK = 0 +const XCHAL_ITLB_SET0_VPN_CONSTMASK = 0x00000000 +const XCHAL_ITLB_SET0_PPN_CONSTMASK = 0xE0000000 +const XCHAL_ITLB_SET0_CA_CONSTMASK = 0 +const XCHAL_ITLB_SET0_ASID_RESET = 0 +const XCHAL_ITLB_SET0_VPN_RESET = 0 +const XCHAL_ITLB_SET0_PPN_RESET = 0 +const XCHAL_ITLB_SET0_CA_RESET = 1 +const XCHAL_ITLB_SET0_E0_VPN_CONST = 0x00000000 +const XCHAL_ITLB_SET0_E1_VPN_CONST = 0x20000000 +const XCHAL_ITLB_SET0_E2_VPN_CONST = 0x40000000 +const XCHAL_ITLB_SET0_E3_VPN_CONST = 0x60000000 +const XCHAL_ITLB_SET0_E4_VPN_CONST = 0x80000000 +const XCHAL_ITLB_SET0_E5_VPN_CONST = 0xA0000000 +const XCHAL_ITLB_SET0_E6_VPN_CONST = 0xC0000000 +const XCHAL_ITLB_SET0_E7_VPN_CONST = 0xE0000000 +const XCHAL_ITLB_SET0_E0_PPN_CONST = 0x00000000 +const XCHAL_ITLB_SET0_E1_PPN_CONST = 0x20000000 +const XCHAL_ITLB_SET0_E2_PPN_CONST = 0x40000000 +const XCHAL_ITLB_SET0_E3_PPN_CONST = 0x60000000 +const XCHAL_ITLB_SET0_E4_PPN_CONST = 0x80000000 +const XCHAL_ITLB_SET0_E5_PPN_CONST = 0xA0000000 +const XCHAL_ITLB_SET0_E6_PPN_CONST = 0xC0000000 +const XCHAL_ITLB_SET0_E7_PPN_CONST = 0xE0000000 +const XCHAL_ITLB_SET0_E0_CA_RESET = 0x02 +const XCHAL_ITLB_SET0_E1_CA_RESET = 0x02 +const XCHAL_ITLB_SET0_E2_CA_RESET = 0x02 +const XCHAL_ITLB_SET0_E3_CA_RESET = 0x02 +const XCHAL_ITLB_SET0_E4_CA_RESET = 0x02 +const XCHAL_ITLB_SET0_E5_CA_RESET = 0x02 +const XCHAL_ITLB_SET0_E6_CA_RESET = 0x02 +const XCHAL_ITLB_SET0_E7_CA_RESET = 0x02 +const XCHAL_DTLB_WAY_BITS = 0 +const XCHAL_DTLB_WAYS = 1 +const XCHAL_DTLB_ARF_WAYS = 0 +const XCHAL_DTLB_SETS = 1 +const XCHAL_DTLB_WAY0_SET = 0 +const XCHAL_DTLB_ARF_SETS = 0 +const XCHAL_DTLB_MINWIRED_SETS = 0 +const XCHAL_DTLB_SET0_WAY = 0 +const XCHAL_DTLB_SET0_WAYS = 1 +const XCHAL_DTLB_SET0_ENTRIES_LOG2 = 3 +const XCHAL_DTLB_SET0_ENTRIES = 8 +const XCHAL_DTLB_SET0_ARF = 0 +const XCHAL_DTLB_SET0_PAGESIZES = 1 +const XCHAL_DTLB_SET0_PAGESZ_BITS = 0 +const XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN = 29 +const XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX = 29 +const XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST = 29 +const XCHAL_DTLB_SET0_ASID_CONSTMASK = 0 +const XCHAL_DTLB_SET0_VPN_CONSTMASK = 0x00000000 +const XCHAL_DTLB_SET0_PPN_CONSTMASK = 0xE0000000 +const XCHAL_DTLB_SET0_CA_CONSTMASK = 0 +const XCHAL_DTLB_SET0_ASID_RESET = 0 +const XCHAL_DTLB_SET0_VPN_RESET = 0 +const XCHAL_DTLB_SET0_PPN_RESET = 0 +const XCHAL_DTLB_SET0_CA_RESET = 1 +const XCHAL_DTLB_SET0_E0_VPN_CONST = 0x00000000 +const XCHAL_DTLB_SET0_E1_VPN_CONST = 0x20000000 +const XCHAL_DTLB_SET0_E2_VPN_CONST = 0x40000000 +const XCHAL_DTLB_SET0_E3_VPN_CONST = 0x60000000 +const XCHAL_DTLB_SET0_E4_VPN_CONST = 0x80000000 +const XCHAL_DTLB_SET0_E5_VPN_CONST = 0xA0000000 +const XCHAL_DTLB_SET0_E6_VPN_CONST = 0xC0000000 +const XCHAL_DTLB_SET0_E7_VPN_CONST = 0xE0000000 +const XCHAL_DTLB_SET0_E0_PPN_CONST = 0x00000000 +const XCHAL_DTLB_SET0_E1_PPN_CONST = 0x20000000 +const XCHAL_DTLB_SET0_E2_PPN_CONST = 0x40000000 +const XCHAL_DTLB_SET0_E3_PPN_CONST = 0x60000000 +const XCHAL_DTLB_SET0_E4_PPN_CONST = 0x80000000 +const XCHAL_DTLB_SET0_E5_PPN_CONST = 0xA0000000 +const XCHAL_DTLB_SET0_E6_PPN_CONST = 0xC0000000 +const XCHAL_DTLB_SET0_E7_PPN_CONST = 0xE0000000 +const XCHAL_DTLB_SET0_E0_CA_RESET = 0x02 +const XCHAL_DTLB_SET0_E1_CA_RESET = 0x02 +const XCHAL_DTLB_SET0_E2_CA_RESET = 0x02 +const XCHAL_DTLB_SET0_E3_CA_RESET = 0x02 +const XCHAL_DTLB_SET0_E4_CA_RESET = 0x02 +const XCHAL_DTLB_SET0_E5_CA_RESET = 0x02 +const XCHAL_DTLB_SET0_E6_CA_RESET = 0x02 +const XCHAL_DTLB_SET0_E7_CA_RESET = 0x02 diff --git a/esp32/core.go b/esp32/core.go new file mode 100644 index 00000000..e889485b --- /dev/null +++ b/esp32/core.go @@ -0,0 +1,150 @@ +package freertos + +import _ "unsafe" + +const XCHAL_ERRATUM_453 = 0 +const XCHAL_ERRATUM_497 = 0 +const XCHAL_ERRATUM_572 = 1 +const XCHAL_HAVE_LE = 1 +const XCHAL_NUM_LOWPRI_LEVELS = 1 +const XCHAL_INTLEVEL0_MASK = 0x00000000 +const XCHAL_INTLEVEL8_MASK = 0x00000000 +const XCHAL_INTLEVEL9_MASK = 0x00000000 +const XCHAL_INTLEVEL10_MASK = 0x00000000 +const XCHAL_INTLEVEL11_MASK = 0x00000000 +const XCHAL_INTLEVEL12_MASK = 0x00000000 +const XCHAL_INTLEVEL13_MASK = 0x00000000 +const XCHAL_INTLEVEL14_MASK = 0x00000000 +const XCHAL_INTLEVEL15_MASK = 0x00000000 +const XCHAL_INTLEVEL0_ANDBELOW_MASK = 0x00000000 +const XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION = 0 +const XCHAL_EXCCAUSE_SYSTEM_CALL = 1 +const XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR = 2 +const XCHAL_EXCCAUSE_LOAD_STORE_ERROR = 3 +const XCHAL_EXCCAUSE_LEVEL1_INTERRUPT = 4 +const XCHAL_EXCCAUSE_ALLOCA = 5 +const XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO = 6 +const XCHAL_EXCCAUSE_SPECULATION = 7 +const XCHAL_EXCCAUSE_PRIVILEGED = 8 +const XCHAL_EXCCAUSE_UNALIGNED = 9 +const XCHAL_EXCCAUSE_ITLB_MISS = 16 +const XCHAL_EXCCAUSE_ITLB_MULTIHIT = 17 +const XCHAL_EXCCAUSE_ITLB_PRIVILEGE = 18 +const XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION = 19 +const XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE = 20 +const XCHAL_EXCCAUSE_DTLB_MISS = 24 +const XCHAL_EXCCAUSE_DTLB_MULTIHIT = 25 +const XCHAL_EXCCAUSE_DTLB_PRIVILEGE = 26 +const XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION = 27 +const XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE = 28 +const XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE = 29 +const XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED = 32 +const XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED = 33 +const XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED = 34 +const XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED = 35 +const XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED = 36 +const XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED = 37 +const XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED = 38 +const XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED = 39 +const XCHAL_DBREAKC_VALIDMASK = 0xC000003F +const XCHAL_DBREAKC_MASK_BITS = 6 +const XCHAL_DBREAKC_MASK_NUM = 64 +const XCHAL_DBREAKC_MASK_SHIFT = 0 +const XCHAL_DBREAKC_MASK_MASK = 0x0000003F +const XCHAL_DBREAKC_LOADBREAK_BITS = 1 +const XCHAL_DBREAKC_LOADBREAK_NUM = 2 +const XCHAL_DBREAKC_LOADBREAK_SHIFT = 30 +const XCHAL_DBREAKC_LOADBREAK_MASK = 0x40000000 +const XCHAL_DBREAKC_STOREBREAK_BITS = 1 +const XCHAL_DBREAKC_STOREBREAK_NUM = 2 +const XCHAL_DBREAKC_STOREBREAK_SHIFT = 31 +const XCHAL_DBREAKC_STOREBREAK_MASK = 0x80000000 +const XCHAL_PS_VALIDMASK = 0x00070F3F +const XCHAL_PS_INTLEVEL_BITS = 4 +const XCHAL_PS_INTLEVEL_NUM = 16 +const XCHAL_PS_INTLEVEL_SHIFT = 0 +const XCHAL_PS_INTLEVEL_MASK = 0x0000000F +const XCHAL_PS_EXCM_BITS = 1 +const XCHAL_PS_EXCM_NUM = 2 +const XCHAL_PS_EXCM_SHIFT = 4 +const XCHAL_PS_EXCM_MASK = 0x00000010 +const XCHAL_PS_UM_BITS = 1 +const XCHAL_PS_UM_NUM = 2 +const XCHAL_PS_UM_SHIFT = 5 +const XCHAL_PS_UM_MASK = 0x00000020 +const XCHAL_PS_RING_BITS = 2 +const XCHAL_PS_RING_NUM = 4 +const XCHAL_PS_RING_SHIFT = 6 +const XCHAL_PS_RING_MASK = 0x000000C0 +const XCHAL_PS_OWB_BITS = 4 +const XCHAL_PS_OWB_NUM = 16 +const XCHAL_PS_OWB_SHIFT = 8 +const XCHAL_PS_OWB_MASK = 0x00000F00 +const XCHAL_PS_CALLINC_BITS = 2 +const XCHAL_PS_CALLINC_NUM = 4 +const XCHAL_PS_CALLINC_SHIFT = 16 +const XCHAL_PS_CALLINC_MASK = 0x00030000 +const XCHAL_PS_WOE_BITS = 1 +const XCHAL_PS_WOE_NUM = 2 +const XCHAL_PS_WOE_SHIFT = 18 +const XCHAL_PS_WOE_MASK = 0x00040000 +const XCHAL_EXCCAUSE_VALIDMASK = 0x0000003F +const XCHAL_EXCCAUSE_BITS = 6 +const XCHAL_EXCCAUSE_NUM = 64 +const XCHAL_EXCCAUSE_SHIFT = 0 +const XCHAL_EXCCAUSE_MASK = 0x0000003F +const XCHAL_DEBUGCAUSE_VALIDMASK = 0x0000003F +const XCHAL_DEBUGCAUSE_ICOUNT_BITS = 1 +const XCHAL_DEBUGCAUSE_ICOUNT_NUM = 2 +const XCHAL_DEBUGCAUSE_ICOUNT_SHIFT = 0 +const XCHAL_DEBUGCAUSE_ICOUNT_MASK = 0x00000001 +const XCHAL_DEBUGCAUSE_IBREAK_BITS = 1 +const XCHAL_DEBUGCAUSE_IBREAK_NUM = 2 +const XCHAL_DEBUGCAUSE_IBREAK_SHIFT = 1 +const XCHAL_DEBUGCAUSE_IBREAK_MASK = 0x00000002 +const XCHAL_DEBUGCAUSE_DBREAK_BITS = 1 +const XCHAL_DEBUGCAUSE_DBREAK_NUM = 2 +const XCHAL_DEBUGCAUSE_DBREAK_SHIFT = 2 +const XCHAL_DEBUGCAUSE_DBREAK_MASK = 0x00000004 +const XCHAL_DEBUGCAUSE_BREAK_BITS = 1 +const XCHAL_DEBUGCAUSE_BREAK_NUM = 2 +const XCHAL_DEBUGCAUSE_BREAK_SHIFT = 3 +const XCHAL_DEBUGCAUSE_BREAK_MASK = 0x00000008 +const XCHAL_DEBUGCAUSE_BREAKN_BITS = 1 +const XCHAL_DEBUGCAUSE_BREAKN_NUM = 2 +const XCHAL_DEBUGCAUSE_BREAKN_SHIFT = 4 +const XCHAL_DEBUGCAUSE_BREAKN_MASK = 0x00000010 +const XCHAL_DEBUGCAUSE_DEBUGINT_BITS = 1 +const XCHAL_DEBUGCAUSE_DEBUGINT_NUM = 2 +const XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT = 5 +const XCHAL_DEBUGCAUSE_DEBUGINT_MASK = 0x00000020 +const XCHAL_CACHE_PREFCTL_DEFAULT = 0x01044 +const XCHAL_ICACHE_TAG_V_SHIFT = 0 +const XCHAL_ICACHE_TAG_V = 0x1 +const XCHAL_ICACHE_TAG_F_SHIFT = 0 +const XCHAL_ICACHE_TAG_F = 0 +const XCHAL_ICACHE_TAG_L = 0 +const XCHAL_DCACHE_TAG_V_SHIFT = 0 +const XCHAL_DCACHE_TAG_V = 0x1 +const XCHAL_DCACHE_TAG_F_SHIFT = 0 +const XCHAL_DCACHE_TAG_F = 0 +const XCHAL_DCACHE_TAG_D = 0 +const XCHAL_DCACHE_TAG_L = 0 +const X_MEMCTL_SNOOP_EN = 0x00 +const X_MEMCTL_L0IBUF_EN = 0x01 +const XCHAL_CP1_NAME = 0 +const XCHAL_CP1_SA_CONTENTS_LIBDB_NUM = 0 +const XCHAL_CP2_NAME = 0 +const XCHAL_CP2_SA_CONTENTS_LIBDB_NUM = 0 +const XCHAL_CP4_NAME = 0 +const XCHAL_CP4_SA_CONTENTS_LIBDB_NUM = 0 +const XCHAL_CP5_NAME = 0 +const XCHAL_CP5_SA_CONTENTS_LIBDB_NUM = 0 +const XCHAL_CP6_NAME = 0 +const XCHAL_CP6_SA_CONTENTS_LIBDB_NUM = 0 +const XCHAL_CP7_NAME = 0 +const XCHAL_CP7_SA_CONTENTS_LIBDB_NUM = 0 +const XCHAL_INST_ILLN = 0xF06D +const XCHAL_INST_ILLN_BYTE0 = 0x6D +const XCHAL_INST_ILLN_BYTE1 = 0xF0 +const XTHAL_INST_ILL = 0x000000 diff --git a/esp32/coreasm.go b/esp32/coreasm.go new file mode 100644 index 00000000..8b756c6a --- /dev/null +++ b/esp32/coreasm.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +const ABI_ENTRY_MINSIZE = 3 diff --git a/esp32/corebits.go b/esp32/corebits.go new file mode 100644 index 00000000..655dde97 --- /dev/null +++ b/esp32/corebits.go @@ -0,0 +1,108 @@ +package freertos + +import _ "unsafe" + +const EXCCAUSE_EXCCAUSE_SHIFT = 0 +const EXCCAUSE_EXCCAUSE_MASK = 0x3F +const EXCCAUSE_ILLEGAL = 0 +const EXCCAUSE_SYSCALL = 1 +const EXCCAUSE_INSTR_ERROR = 2 +const EXCCAUSE_IFETCHERROR = 2 +const EXCCAUSE_LOAD_STORE_ERROR = 3 +const EXCCAUSE_LOADSTOREERROR = 3 +const EXCCAUSE_LEVEL1_INTERRUPT = 4 +const EXCCAUSE_LEVEL1INTERRUPT = 4 +const EXCCAUSE_ALLOCA = 5 +const EXCCAUSE_DIVIDE_BY_ZERO = 6 +const EXCCAUSE_SPECULATION = 7 +const EXCCAUSE_PC_ERROR = 7 +const EXCCAUSE_PRIVILEGED = 8 +const EXCCAUSE_UNALIGNED = 9 +const EXCCAUSE_EXTREG_PRIVILEGE = 10 +const EXCCAUSE_EXCLUSIVE_ERROR = 11 +const EXCCAUSE_INSTR_DATA_ERROR = 12 +const EXCCAUSE_LOAD_STORE_DATA_ERROR = 13 +const EXCCAUSE_INSTR_ADDR_ERROR = 14 +const EXCCAUSE_LOAD_STORE_ADDR_ERROR = 15 +const EXCCAUSE_ITLB_MISS = 16 +const EXCCAUSE_ITLB_MULTIHIT = 17 +const EXCCAUSE_INSTR_RING = 18 +const EXCCAUSE_INSTR_PROHIBITED = 20 +const EXCCAUSE_DTLB_MISS = 24 +const EXCCAUSE_DTLB_MULTIHIT = 25 +const EXCCAUSE_LOAD_STORE_RING = 26 +const EXCCAUSE_LOAD_PROHIBITED = 28 +const EXCCAUSE_STORE_PROHIBITED = 29 +const EXCCAUSE_CP0_DISABLED = 32 +const EXCCAUSE_CP1_DISABLED = 33 +const EXCCAUSE_CP2_DISABLED = 34 +const EXCCAUSE_CP3_DISABLED = 35 +const EXCCAUSE_CP4_DISABLED = 36 +const EXCCAUSE_CP5_DISABLED = 37 +const EXCCAUSE_CP6_DISABLED = 38 +const EXCCAUSE_CP7_DISABLED = 39 +const PS_WOE_SHIFT = 18 +const PS_WOE_MASK = 0x00040000 +const PS_CALLINC_SHIFT = 16 +const PS_CALLINC_MASK = 0x00030000 +const PS_OWB_SHIFT = 8 +const PS_OWB_MASK = 0x00000F00 +const PS_RING_SHIFT = 6 +const PS_RING_MASK = 0x000000C0 +const PS_UM_SHIFT = 5 +const PS_UM_MASK = 0x00000020 +const PS_EXCM_SHIFT = 4 +const PS_EXCM_MASK = 0x00000010 +const PS_INTLEVEL_SHIFT = 0 +const PS_INTLEVEL_MASK = 0x0000000F +const DBREAKC_MASK_SHIFT = 0 +const DBREAKC_MASK_MASK = 0x0000003F +const DBREAKC_LOADBREAK_SHIFT = 30 +const DBREAKC_LOADBREAK_MASK = 0x40000000 +const DBREAKC_STOREBREAK_SHIFT = 31 +const DBREAKC_STOREBREAK_MASK = 0x80000000 +const DEBUGCAUSE_DEBUGINT_SHIFT = 5 +const DEBUGCAUSE_DEBUGINT_MASK = 0x20 +const DEBUGCAUSE_BREAKN_SHIFT = 4 +const DEBUGCAUSE_BREAKN_MASK = 0x10 +const DEBUGCAUSE_BREAK_SHIFT = 3 +const DEBUGCAUSE_BREAK_MASK = 0x08 +const DEBUGCAUSE_DBREAK_SHIFT = 2 +const DEBUGCAUSE_DBREAK_MASK = 0x04 +const DEBUGCAUSE_IBREAK_SHIFT = 1 +const DEBUGCAUSE_IBREAK_MASK = 0x02 +const DEBUGCAUSE_ICOUNT_SHIFT = 0 +const DEBUGCAUSE_ICOUNT_MASK = 0x01 +const MESR_MEME = 0x00000001 +const MESR_MEME_SHIFT = 0 +const MESR_DME = 0x00000002 +const MESR_DME_SHIFT = 1 +const MESR_RCE = 0x00000010 +const MESR_RCE_SHIFT = 4 +const MESR_ERRENAB = 0x00000100 +const MESR_ERRENAB_SHIFT = 8 +const MESR_ERRTEST = 0x00000200 +const MESR_ERRTEST_SHIFT = 9 +const MESR_DATEXC = 0x00000400 +const MESR_DATEXC_SHIFT = 10 +const MESR_INSEXC = 0x00000800 +const MESR_INSEXC_SHIFT = 11 +const MESR_WAYNUM_SHIFT = 16 +const MESR_ACCTYPE_SHIFT = 20 +const MESR_MEMTYPE_SHIFT = 24 +const MESR_ERRTYPE_SHIFT = 30 +const MEMCTL_SNOOP_EN_SHIFT = 1 +const MEMCTL_SNOOP_EN = 0x02 +const MEMCTL_L0IBUF_EN_SHIFT = 0 +const MEMCTL_L0IBUF_EN = 0x01 +const MEMCTL_INV_EN_SHIFT = 23 +const MEMCTL_INV_EN = 0x00800000 +const MEMCTL_DCWU_SHIFT = 8 +const MEMCTL_DCWU_BITS = 5 +const MEMCTL_DCWA_SHIFT = 13 +const MEMCTL_DCWA_BITS = 5 +const MEMCTL_ICWU_SHIFT = 18 +const MEMCTL_ICWU_BITS = 5 +const MEMCTL_DCWU_MASK = 0x00001F00 +const MEMCTL_DCWA_MASK = 0x0003E000 +const MEMCTL_ICWU_MASK = 0x007C0000 diff --git a/esp32/cpio.go b/esp32/cpio.go new file mode 100644 index 00000000..06ba11c2 --- /dev/null +++ b/esp32/cpio.go @@ -0,0 +1,129 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const CPIO_MODE_FILETYPE_MASK = 0xF000 +const CPIO_MODE_FILETYPE_SOCKET = 0xC000 +const CPIO_MODE_FILETYPE_SYMLINK = 0xA000 +const CPIO_MODE_FILETYPE_REGULAR = 0x8000 +const CPIO_MODE_FILETYPE_BLOCKDEV = 0x6000 +const CPIO_MODE_FILETYPE_DIR = 0x4000 +const CPIO_MODE_FILETYPE_CHARDEV = 0x2000 +const CPIO_MODE_FILETYPE_FIFO = 0x1000 +const CPIO_MODE_SUID = 0x0800 +const CPIO_MODE_SGID = 0x0400 +const CPIO_MODE_STICKY = 0x0200 + +type CpioFileT struct { + Filesize c.SizeT + Name *c.Char + Mode c.Uint32T + Check c.Uint32T +} +type CpioRetT c.Int + +const ( + CPIO_RET_MORE CpioRetT = 0 + CPIO_RET_DONE CpioRetT = 1 + CPIO_RET_ERR CpioRetT = 2 +) + +type CpioHandleDataT struct { + Unused [8]uint8 +} +type CpioHandleT *CpioHandleDataT +type CpioCallbackReasonT c.Int + +const ( + CPIO_RSN_FILE_ALL CpioCallbackReasonT = 0 + CPIO_RSN_FILE_INITIAL CpioCallbackReasonT = 1 + CPIO_RSN_FILE_MORE CpioCallbackReasonT = 2 + CPIO_RSN_FILE_END CpioCallbackReasonT = 3 +) + +// llgo:type C +type CpioCallbackT func(CpioCallbackReasonT, *CpioFileT, c.SizeT, c.SizeT, *c.Char, c.Pointer) + +/** + * @brief Initialize a cpio handle. + * + * Call this to start parsing a cpio archive. You can set the callback that handles the + * files/data here. + * + * @param callback The callback that will handle the data of the files inside the cpio archive + * + * @param cbarg User-supplied argument. The callback will be called with this as an argument. + * + * @param buflen Length of internal buffer used. + * If this is zero, the callback will be called with data that lives in the data buffer + * supplied to the cpio library by whomever called cpio_feed(). Because this library has + * no power over that buffer, the callback can be passed as little as 1 and as many as + * INT_MAX bytes at a time. + * If this is non-zero, the library will allocate an internal buffer of this size. All + * cpio_feed()-calls will be rebuffered, and the callback is guaranteed to only be called + * with this many bytes in the buffer, given there's enough data in the file to fill it. + * + * @param memchunk Chunk of memory to allocate everything (handle, I/O buffer, filename buffer) in. Minimum size + * (estimate) is 160+buflen+sizeof(largest filename/path). + * @param memchunklen Size of the mem chunk + * + * @return + * - Success: A pointer to a cpio handle + * - Error: NULL + * + */ +//go:linkname CpioStart C.cpio_start +func CpioStart(callback CpioCallbackT, cbarg c.Pointer, buflen c.SizeT, memchunk c.Pointer, memchunklen c.Int) CpioHandleT + +/** + * @brief Feed data from a cpio archive into the library + * + * This routine is used to feed consecutive data of the cpio archive into the library. While processing, + * the library can call the callback function one or more times if needed. + * + * @param cpio Handle obtained by calling cpio_start() + * + * @param buffer Pointer to buffer containing cpio archive data + * + * @param len Length of the buffer, in bytes + * + * @return + * - CPIO_RET_MORE: CPIO archive isn't done yet, please feed more data. + * - CPIO_RET_DONE: CPUI archive is finished. + * - CPIO_RET_ERR: Invalid CPIO archive data; decoding aborted. + * + */ +//go:linkname CpioFeed C.cpio_feed +func CpioFeed(cpio CpioHandleT, buffer *c.Char, len c.Int) CpioRetT + +/** + * @brief Indicate there is no more cpio data to be fed into the archive + * + * This call is to be called when the source data is exhausted. Normally, the library can find the end of the + * cpio archive by looking for the end marker, + * + * @param timer_conf Pointer of LEDC timer configure struct + * + * + * @return + * - CPIO_RET_DONE on success + * - CPIO_RET_ERR when cpio archive is invalid + * + */ +//go:linkname CpioDone C.cpio_done +func CpioDone(cpio CpioHandleT) CpioRetT + +/** + * @brief Free the memory allocated for a cpio handle. + * + * @param cpio Handle obtained by calling cpio_start() + * + * @return + * - CPIO_RET_DONE on success + * + */ +//go:linkname CpioDestroy C.cpio_destroy +func CpioDestroy(cpio CpioHandleT) CpioRetT diff --git a/esp32/cpu_hal.go b/esp32/cpu_hal.go new file mode 100644 index 00000000..32d2f1ba --- /dev/null +++ b/esp32/cpu_hal.go @@ -0,0 +1,14 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type WatchpointTriggerT c.Int + +const ( + WATCHPOINT_TRIGGER_ON_RO WatchpointTriggerT = 0 + WATCHPOINT_TRIGGER_ON_WO WatchpointTriggerT = 1 + WATCHPOINT_TRIGGER_ON_RW WatchpointTriggerT = 2 +) diff --git a/esp32/crc.go b/esp32/crc.go new file mode 100644 index 00000000..a19b5dba --- /dev/null +++ b/esp32/crc.go @@ -0,0 +1,90 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Crc32 value that is in little endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +//go:linkname Crc32Le C.crc32_le +func Crc32Le(crc c.Uint32T, buf *c.Uint8T, len c.Uint32T) c.Uint32T + +/** + * @brief Crc32 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +//go:linkname Crc32Be C.crc32_be +func Crc32Be(crc c.Uint32T, buf *c.Uint8T, len c.Uint32T) c.Uint32T + +/** + * @brief Crc16 value that is in little endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +//go:linkname Crc16Le C.crc16_le +func Crc16Le(crc c.Uint16T, buf *c.Uint8T, len c.Uint32T) c.Uint16T + +/** + * @brief Crc16 value that is in big endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +//go:linkname Crc16Be C.crc16_be +func Crc16Be(crc c.Uint16T, buf *c.Uint8T, len c.Uint32T) c.Uint16T + +/** + * @brief Crc8 value that is in little endian. + * + * @param uint8_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +//go:linkname Crc8Le C.crc8_le +func Crc8Le(crc c.Uint8T, buf *c.Uint8T, len c.Uint32T) c.Uint8T + +/** + * @brief Crc8 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +//go:linkname Crc8Be C.crc8_be +func Crc8Be(crc c.Uint8T, buf *c.Uint8T, len c.Uint32T) c.Uint8T diff --git a/esp32/critical_section.go b/esp32/critical_section.go new file mode 100644 index 00000000..2c5e42b3 --- /dev/null +++ b/esp32/critical_section.go @@ -0,0 +1,7 @@ +package freertos + +import _ "unsafe" + +const OS_SPINLOCK = 1 + +type EspOsSpinlockT SpinlockT diff --git a/esp32/crosscore_int.go b/esp32/crosscore_int.go new file mode 100644 index 00000000..fbe29d8c --- /dev/null +++ b/esp32/crosscore_int.go @@ -0,0 +1,70 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Initialize the crosscore interrupt system for this CPU. + * This needs to be called once on every CPU that is used + * by FreeRTOS. + * + * If multicore FreeRTOS support is enabled, this will be + * called automatically by the startup code and should not + * be called manually. + */ +//go:linkname EspCrosscoreIntInit C.esp_crosscore_int_init +func EspCrosscoreIntInit() + +/** + * Send an interrupt to a CPU indicating it should yield its + * currently running task in favour of a higher-priority task + * that presumably just woke up. + * + * This is used internally by FreeRTOS in multicore mode + * and should not be called by the user. + * + * @param core_id Core that should do the yielding + */ +//go:linkname EspCrosscoreIntSendYield C.esp_crosscore_int_send_yield +func EspCrosscoreIntSendYield(core_id c.Int) + +/** + * Send an interrupt to a CPU indicating it should update its + * CCOMPARE1 value due to a frequency switch. + * + * This is used internally when dynamic frequency switching is + * enabled, and should not be called from application code. + * + * @param core_id Core that should update its CCOMPARE1 value + */ +//go:linkname EspCrosscoreIntSendFreqSwitch C.esp_crosscore_int_send_freq_switch +func EspCrosscoreIntSendFreqSwitch(core_id c.Int) + +//go:linkname EspCrosscoreIntSendGdbCall C.esp_crosscore_int_send_gdb_call +func EspCrosscoreIntSendGdbCall(core_id c.Int) + +/** + * Send an interrupt to a CPU indicating it should print its current backtrace + * + * This is used internally by the Task Watchdog to dump the backtrace of the + * opposite core and should not be called from application code. + * + * @param core_id Core that should print its backtrace + */ +//go:linkname EspCrosscoreIntSendPrintBacktrace C.esp_crosscore_int_send_print_backtrace +func EspCrosscoreIntSendPrintBacktrace(core_id c.Int) + +/** + * Send an interrupt to a CPU indicating it call `task_wdt_timeout_abort_xtensa`. + * This will make the CPU abort, using the interrupted task frame. + * + * This is used internally by the Task Watchdog when it should abort after a task, + * running on the other core than the one running the TWDT ISR, failed to reset + * its timer. + * + * @param core_id Core that should abort + */ +//go:linkname EspCrosscoreIntSendTwdtAbort C.esp_crosscore_int_send_twdt_abort +func EspCrosscoreIntSendTwdtAbort(core_id c.Int) diff --git a/esp32/dac_types.go b/esp32/dac_types.go new file mode 100644 index 00000000..4e883cba --- /dev/null +++ b/esp32/dac_types.go @@ -0,0 +1,32 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type DacChannelT c.Int + +const ( + DAC_CHAN_0 DacChannelT = 0 + DAC_CHAN_1 DacChannelT = 1 + DAC_CHANNEL_1 DacChannelT = 0 + DAC_CHANNEL_2 DacChannelT = 1 +) + +type DacCosineAttenT c.Int + +const ( + DAC_COSINE_ATTEN_DEFAULT DacCosineAttenT = 0 + DAC_COSINE_ATTEN_DB_0 DacCosineAttenT = 0 + DAC_COSINE_ATTEN_DB_6 DacCosineAttenT = 1 + DAC_COSINE_ATTEN_DB_12 DacCosineAttenT = 2 + DAC_COSINE_ATTEN_DB_18 DacCosineAttenT = 3 +) + +type DacCosinePhaseT c.Int + +const ( + DAC_COSINE_PHASE_0 DacCosinePhaseT = 2 + DAC_COSINE_PHASE_180 DacCosinePhaseT = 3 +) diff --git a/esp32/debug_probe.go b/esp32/debug_probe.go new file mode 100644 index 00000000..915c5099 --- /dev/null +++ b/esp32/debug_probe.go @@ -0,0 +1,152 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type DebugProbeUnitT struct { + Unused [8]uint8 +} +type DebugProbeUnitHandleT *DebugProbeUnitT + +type DebugProbeChannelT struct { + Unused [8]uint8 +} +type DebugProbeChannelHandleT *DebugProbeChannelT + +/** + * @brief Configuration for a debug probe unit + */ + +type DebugProbeUnitConfigT struct { + ProbeOutGpioNums [16]GpioNumT +} + +/** + * @brief Create a new debug probe unit + * + * @param[in] config Configuration for the debug probe unit + * @param[out] out_handle Handle of the created debug probe unit + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the configuration is invalid + * - ESP_ERR_NOT_FOUND if there is no free unit slot + * - ESP_ERR_NO_MEM if memory allocation failed + * - ESP_FAIL if an internal error occurred + */ +// llgo:link (*DebugProbeUnitConfigT).DebugProbeNewUnit C.debug_probe_new_unit +func (recv_ *DebugProbeUnitConfigT) DebugProbeNewUnit(out_handle *DebugProbeUnitHandleT) EspErrT { + return 0 +} + +/** + * @brief Delete a debug probe unit + * + * @param[in] unit Handle of the debug probe unit + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the handle is invalid + * - ESP_FAIL if an internal error occurred + */ +//go:linkname DebugProbeDelUnit C.debug_probe_del_unit +func DebugProbeDelUnit(unit DebugProbeUnitHandleT) EspErrT + +/** + * @brief Configuration for a debug probe channel + */ + +type DebugProbeChannelConfigT struct { + TargetModule DebugProbeTargetT +} + +/** + * @brief Create a new debug probe channel in a unit + * + * @param[in] unit Handle of the debug probe unit + * @param[in] config Configuration for the debug probe channel + * @param[out] out_handle Handle of the created debug probe channel + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the handle or configuration is invalid + * - ESP_ERR_NOT_FOUND if there is no free channel slot + * - ESP_ERR_NO_MEM if memory allocation failed + * - ESP_FAIL if an internal error occurred + */ +//go:linkname DebugProbeNewChannel C.debug_probe_new_channel +func DebugProbeNewChannel(unit DebugProbeUnitHandleT, config *DebugProbeChannelConfigT, out_handle *DebugProbeChannelHandleT) EspErrT + +/** + * @brief Delete a debug probe channel + * + * @param[in] chan Handle of the debug probe channel + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the handle is invalid + * - ESP_FAIL if an internal error occurred + */ +//go:linkname DebugProbeDelChannel C.debug_probe_del_channel +func DebugProbeDelChannel(chan_ DebugProbeChannelHandleT) EspErrT + +/** + * @brief Add signals to a debug probe channel + * + * @note The n-th byte of channel output comes from the n-th byte in the sig_group. + * @note The signals to be added must aligned to the byte boundary. + * byte_idx = 0: signal 0-7 in the group + * byte_idx = 1: signal 8-15 in the group + * ... + * @note If you add the signals from different groups but with the same byte_idx, only the last added signal will be effective. + * @note You can save up to 32 signals in a channel, but in the end, only the part of them (e.g. upper or lower 16 signals) can be output to the GPIO pads. + * + * @param[in] chan Handle of the debug probe channel + * @param[in] byte_idx Byte index of the signals, ranges from 0 to 3 + * @param[in] sig_group Signal group of the signal, ranges from 0 to 15 + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the parameters are invalid + * - ESP_FAIL if an internal error occurred + */ +//go:linkname DebugProbeChanAddSignalByByte C.debug_probe_chan_add_signal_by_byte +func DebugProbeChanAddSignalByByte(chan_ DebugProbeChannelHandleT, byte_idx c.Uint8T, sig_group c.Uint8T) EspErrT + +/** + * @brief Merge the part of the channel output to the debug probe unit output + * + * +----upper16---+ + * chan_0 ---+ | + * +----lower16---+ + * | + * +-------unit_output[31:0] + * | + * +----upper16---+ + * chan_1 ---+ | + * +----lower16---+ + * + * @param[in] unit Handle of the debug probe unit + * @param[in] chan0 Handle of the debug probe channel 0, whose output will be merged to the lower 16 signals of the unit output + * @param[in] split_of_chan0 Part of the channel 0 output to be merged + * @param[in] chan1 Handle of the debug probe channel 1, whose output will be merged to the upper 16 signals of the unit output + * @param[in] split_of_chan1 Part of the channel 1 output to be merged + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the parameters are invalid + * - ESP_FAIL if an internal error occurred + */ +//go:linkname DebugProbeUnitMerge16 C.debug_probe_unit_merge16 +func DebugProbeUnitMerge16(unit DebugProbeUnitHandleT, chan0 DebugProbeChannelHandleT, split_of_chan0 DebugProbeSplitU16T, chan1 DebugProbeChannelHandleT, split_of_chan1 DebugProbeSplitU16T) EspErrT + +/** + * @brief Read the value of the debug probe unit + * + * @note Only the lower 16 signals of the probe unit can be routed to the GPIO pads. + * + * @param[in] unit Handle of the debug probe unit + * @param[out] value Current value of the debug probe unit output + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the handle or value is invalid + * - ESP_FAIL if an internal error occurred + */ +//go:linkname DebugProbeUnitRead C.debug_probe_unit_read +func DebugProbeUnitRead(unit DebugProbeUnitHandleT, value *c.Uint32T) EspErrT diff --git a/esp32/debug_probe_types.go b/esp32/debug_probe_types.go new file mode 100644 index 00000000..4210ea2b --- /dev/null +++ b/esp32/debug_probe_types.go @@ -0,0 +1,17 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const DEBUG_PROBE_MAX_OUTPUT_WIDTH = 16 + +type DebugProbeSplitU16T c.Int + +const ( + DEBUG_PROBE_SPLIT_LOWER16 DebugProbeSplitU16T = 0 + DEBUG_PROBE_SPLIT_UPPER16 DebugProbeSplitU16T = 1 +) + +type DebugProbeTargetT c.Int diff --git a/esp32/dedic_gpio_ll.go b/esp32/dedic_gpio_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/dedic_gpio_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/dedic_gpio_periph.go b/esp32/dedic_gpio_periph.go new file mode 100644 index 00000000..68354198 --- /dev/null +++ b/esp32/dedic_gpio_periph.go @@ -0,0 +1,14 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type DedicGpioSignalConnT struct { + Irq c.Int + Cores [2]struct { + InSigPerChannel [8]c.Int + OutSigPerChannel [8]c.Int + } +} diff --git a/esp32/defs.go b/esp32/defs.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/defs.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/deprecated_definitions.go b/esp32/deprecated_definitions.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/deprecated_definitions.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/digital_signature.go b/esp32/digital_signature.go new file mode 100644 index 00000000..daac9bd4 --- /dev/null +++ b/esp32/digital_signature.go @@ -0,0 +1,111 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ETS_DS_IV_LEN = 16 + +/* Encrypted ETS data. Recommended to store in flash in this format. + */ + +type EtsDsDataT struct { + RsaLength c.Uint + Iv [16]c.Uint8T + C [1584]c.Uint8T +} +type EtsDsResultT c.Int + +const ( + ETS_DS_OK EtsDsResultT = 0 + ETS_DS_INVALID_PARAM EtsDsResultT = 1 + ETS_DS_INVALID_KEY EtsDsResultT = 2 + ETS_DS_INVALID_PADDING EtsDsResultT = 3 + ETS_DS_INVALID_DIGEST EtsDsResultT = 4 +) + +//go:linkname EtsDsEnable C.ets_ds_enable +func EtsDsEnable() + +//go:linkname EtsDsDisable C.ets_ds_disable +func EtsDsDisable() + +/* + * @brief Start signing a message (or padded message digest) using the Digital Signature peripheral + * + * - @param message Pointer to message (or padded digest) containing the message to sign. Should be + * (data->rsa_length + 1)*4 bytes long. @param data Pointer to DS data. Can be a pointer to data + * in flash. + * + * Caller must have already called ets_ds_enable() and ets_hmac_calculate_downstream() before calling + * this function, and is responsible for calling ets_ds_finish_sign() and then + * ets_hmac_invalidate_downstream() afterwards. + * + * @return ETS_DS_OK if signature is in progress, ETS_DS_INVALID_PARAM if param is invalid, + * EST_DS_INVALID_KEY if key or HMAC peripheral is configured incorrectly. + */ +//go:linkname EtsDsStartSign C.ets_ds_start_sign +func EtsDsStartSign(message c.Pointer, data *EtsDsDataT) EtsDsResultT + +/* + * @brief Returns true if the DS peripheral is busy following a call to ets_ds_start_sign() + * + * A result of false indicates that a call to ets_ds_finish_sign() will not block. + * + * Only valid if ets_ds_enable() has been called. + */ +//go:linkname EtsDsIsBusy C.ets_ds_is_busy +func EtsDsIsBusy() bool + +/* @brief Finish signing a message using the Digital Signature peripheral + * + * Must be called after ets_ds_start_sign(). Can use ets_ds_busy() to wait until + * peripheral is no longer busy. + * + * - @param signature Pointer to buffer to contain the signature. Should be + * (data->rsa_length + 1)*4 bytes long. + * - @param data Should match the 'data' parameter passed to ets_ds_start_sign() + * + * @param ETS_DS_OK if signing succeeded, ETS_DS_INVALID_PARAM if param is invalid, + * ETS_DS_INVALID_DIGEST or ETS_DS_INVALID_PADDING if there is a problem with the + * encrypted data digest or padding bytes (in case of ETS_DS_INVALID_PADDING, a + * digest is produced anyhow.) + */ +//go:linkname EtsDsFinishSign C.ets_ds_finish_sign +func EtsDsFinishSign(signature c.Pointer, data *EtsDsDataT) EtsDsResultT + +/* +Plaintext parameters used by Digital Signature. + + Not used for signing with DS peripheral, but can be encrypted + in-device by calling ets_ds_encrypt_params() +*/ +type EtsDsPDataT struct { + Y [128]c.Uint32T + M [128]c.Uint32T + Rb [128]c.Uint32T + MPrime c.Uint32T + Length c.Uint32T +} +type EtsDsKeyT c.Int + +const ( + ETS_DS_KEY_HMAC EtsDsKeyT = 0 + ETS_DS_KEY_AES EtsDsKeyT = 1 +) + +/* @brief Encrypt DS parameters suitable for storing and later use with DS peripheral + * + * @param data Output buffer to store encrypted data, suitable for later use generating signatures. + * @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time. + * @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process is done and 'data' is stored. + * @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the corresponding HMAC key will be stored to efuse and then permanently erased. + * @param key_type Type of key stored in 'key' (either the AES-256 DS key, or an HMAC DS key from which the AES DS key is derived using HMAC peripheral) + * + * @return ETS_DS_INVALID_PARAM if any parameter is invalid, or ETS_DS_OK if 'data' is successfully generated from the input parameters. + */ +// llgo:link (*EtsDsDataT).EtsDsEncryptParams C.ets_ds_encrypt_params +func (recv_ *EtsDsDataT) EtsDsEncryptParams(iv c.Pointer, p_data *EtsDsPDataT, key c.Pointer, key_type EtsDsKeyT) EtsDsResultT { + return 0 +} diff --git a/esp32/dma2d.go b/esp32/dma2d.go new file mode 100644 index 00000000..361aa64f --- /dev/null +++ b/esp32/dma2d.go @@ -0,0 +1,390 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type Dma2dGroupT struct { + Unused [8]uint8 +} +type Dma2dPoolHandleT *Dma2dGroupT + +type Dma2dTransS struct { + Unused [8]uint8 +} +type Dma2dTransT Dma2dTransS + +/** + * @brief Get the size for struct `dma2d_trans_t` + * + * @return size_t Size of struct `dma2d_trans_t` + */ +//go:linkname Dma2dGetTransElmSize C.dma2d_get_trans_elm_size +func Dma2dGetTransElmSize() c.SizeT + +/** + * @brief A collection of configuration items that used for allocating a 2D-DMA pool + */ + +type Dma2dPoolConfigT struct { + PoolId c.Uint32T + IntrPriority c.Uint32T +} + +/** + * @brief Acquire a 2D-DMA pool + * + * @param[in] config Pointer to a collection of configurations for the 2D-DMA pool + * @param[out] ret_pool Returned pool handle + * @return + * - ESP_OK: Acquire the 2D-DMA pool successfully + * - ESP_ERR_INVALID_ARG: Acquire the 2D-DMA pool failed because of invalid argument + * - ESP_ERR_NO_MEM: Acquire the 2D-DMA pool failed because out of memory + * - ESP_FAIL: Acquire the 2D-DMA pool failed because of other error + */ +// llgo:link (*Dma2dPoolConfigT).Dma2dAcquirePool C.dma2d_acquire_pool +func (recv_ *Dma2dPoolConfigT) Dma2dAcquirePool(ret_pool *Dma2dPoolHandleT) EspErrT { + return 0 +} + +/** + * @brief Release a 2D-DMA pool + * + * @warning Upper driver should make sure there is no pending transaction (enqueued by the driver, but haven't be + * processed) before calling this function. + * + * @param[in] dma2d_pool 2D-DMA pool handle, allocated by `dma2d_acquire_pool` + * @return + * - ESP_OK: Release the 2D-DMA pool successfully + * - ESP_ERR_INVALID_ARG: Release the 2D-DMA pool failed because of invalid argument + * - ESP_ERR_NOT_ALLOWED: Release the 2D-DMA pool failed because there is pending transactions in the pool, + * pool can not be destroyed + */ +//go:linkname Dma2dReleasePool C.dma2d_release_pool +func Dma2dReleasePool(dma2d_pool Dma2dPoolHandleT) EspErrT + +type Dma2dChannelT struct { + Unused [8]uint8 +} +type Dma2dChannelHandleT *Dma2dChannelT + +/** + * @brief Struct to save the necessary information of a 2D-DMA channel for upper drivers to configure the channels + */ + +type Dma2dTransChannelInfoT struct { + Dir Dma2dChannelDirectionT + Chan Dma2dChannelHandleT +} + +// llgo:type C +type Dma2dTransOnPickedCallbackT func(c.Uint32T, *Dma2dTransChannelInfoT, c.Pointer) bool + +/** + * @brief A collection of configuration items for a 2D-DMA transaction + */ + +type Dma2dTransConfigT struct { + TxChannelNum c.Uint32T + RxChannelNum c.Uint32T + ChannelFlags c.Uint32T + SpecifiedTxChannelMask c.Uint32T + SpecifiedRxChannelMask c.Uint32T + OnJobPicked Dma2dTransOnPickedCallbackT + UserConfig c.Pointer +} + +/** + * @brief Enqueue a 2D-DMA transaction to be picked up by a certain 2D-DMA pool + * + * @param[in] dma2d_pool 2D-DMA pool handle, allocated by `dma2d_acquire_pool` + * @param[in] trans_desc Pointer to a collection of configurations for a transaction + * The context must exist at least until `on_job_picked` callback function is called. + * @param[in] trans_placeholder Address to the memory for storing this transaction context + * Caller must malloc a placeholder for storing the 2D-DMA transaction, and pass it into the function. + * Size of the placeholder can be get from `SIZEOF_DMA2D_TRANS_T` macro. + * Freeing the 2D-DMA transaction placeholder should also be taken care by the upper driver. + * It can be freed when `on_job_picked` callback function is called or anytime later. + * @return + * - ESP_OK: Enqueue the 2D-DMA transaction successfully + * - ESP_ERR_INVALID_ARG: Enqueue the 2D-DMA transaction failed because of invalid argument + */ +//go:linkname Dma2dEnqueue C.dma2d_enqueue +func Dma2dEnqueue(dma2d_pool Dma2dPoolHandleT, trans_desc *Dma2dTransConfigT, trans_placeholder *Dma2dTransT) EspErrT + +/** + * @brief Force end an in-flight 2D-DMA transaction + * + * This API is useful when the error was caused by the DMA consumer (such as JPEG). The error can only be detected + * by the consumer module, and the error info will only be propagated to the consumer driver. The 2D-DMA channels being + * involved to transfer the data has no way to be informed about the error at its upstream, it will keep waiting for + * the data. + * + * Therefore, when the consumer driver is doing the error handling, it is required to call this API to end the on-going + * transaction and release the taken TX and RX channels. It will stop and free the TX and RX channels that are bundled + * together to process the transaction. + * + * @param[in] trans Pointer to the 2D-DMA transaction context + * @param[out] need_yield Pointer to a status flag to record whether a task switch is needed if this API is being called in an ISR + * @return + * - ESP_OK: Force end an in-flight transaction successfully + * - ESP_ERR_INVALID_ARG: Force end failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Force end failed because the transaction is not yet in-flight + */ +// llgo:link (*Dma2dTransT).Dma2dForceEnd C.dma2d_force_end +func (recv_ *Dma2dTransT) Dma2dForceEnd(need_yield *bool) EspErrT { + return 0 +} + +/** + * @brief Type of 2D-DMA engine trigger + */ + +type Dma2dTriggerT struct { + Periph Dma2dTriggerPeripheralT + PeriphSelId c.Int +} + +/** + * @brief Connect 2D-DMA channel to trigger peripheral, and configure all other channel settings to a certain state (the channel will be reset first) + * + * Usually only to be called in `on_job_picked` callback, and is the first step to do inside the callback, since it resets other configurations to a default mode. + * + * @param[in] dma2d_chan 2D-DMA channel handle, get from the `on_job_picked` callback input argument `dma2d_chans` + * @param[in] trig_periph 2D-DMA trigger peripheral + * @return + * - ESP_OK: Connect 2D-DMA channel successfully + * - ESP_ERR_INVALID_ARG: Connect 2D-DMA channel failed because of invalid argument + */ +//go:linkname Dma2dConnect C.dma2d_connect +func Dma2dConnect(dma2d_chan Dma2dChannelHandleT, trig_periph *Dma2dTriggerT) EspErrT + +/** + * @brief A collection of strategy items that each 2D-DMA channel could apply + */ + +type Dma2dStrategyConfigT struct { + OwnerCheck bool + AutoUpdateDesc bool + EofTillDataPopped bool +} + +/** + * @brief Apply channel strategy for 2D-DMA channel + * + * Usually only to be called in `on_job_picked` callback. + * + * @param[in] dma2d_chan 2D-DMA channel handle, get from the `on_job_picked` callback input argument `dma2d_chans` + * @param[in] config Configuration of 2D-DMA channel strategy + * @return + * - ESP_OK: Apply channel strategy successfully + * - ESP_ERR_INVALID_ARG: Apply channel strategy failed because of invalid argument + */ +//go:linkname Dma2dApplyStrategy C.dma2d_apply_strategy +func Dma2dApplyStrategy(dma2d_chan Dma2dChannelHandleT, config *Dma2dStrategyConfigT) EspErrT + +/** + * @brief A collection of transfer ability items that each 2D-DMA channel could apply to improve transfer efficiency + * + * @note The 2D-DMA driver has no knowledge about the DMA buffer (address and size) used by upper layer. + * So it's the responsibility of the **upper layer** to take care of the buffer address and size. + * Usually RX buffer at least requires 4-byte alignment to avoid overwriting other data by DMA write PSRAM process + * or its data being overwritten. + */ + +type Dma2dTransferAbilityT struct { + DescBurstEn bool + DataBurstLength Dma2dDataBurstLengthT + MbSize Dma2dMacroBlockSizeT +} + +/** + * @brief Configure 2D-DMA channel transfer ability for transfer efficiency + * + * Usually only to be called in `on_job_picked` callback. + * + * @param[in] dma2d_chan 2D-DMA channel handle, get from the `on_job_picked` callback input argument `dma2d_chans` + * @param[in] ability Configuration of 2D-DMA channel transfer ability + * @return + * - ESP_OK: Set channel transfer ability successfully + * - ESP_ERR_INVALID_ARG: Set channel transfer ability failed because of invalid argument + */ +//go:linkname Dma2dSetTransferAbility C.dma2d_set_transfer_ability +func Dma2dSetTransferAbility(dma2d_chan Dma2dChannelHandleT, ability *Dma2dTransferAbilityT) EspErrT + +/** + * @brief A collection of color space conversion (CSC) items that each 2D-DMA channel could apply + */ + +type Dma2dCscConfigT struct { + PreScramble Dma2dScrambleOrderT + PostScramble Dma2dScrambleOrderT +} + +/** + * @brief Configure color space conversion setting for 2D-DMA channel + * + * Usually only to be called in `on_job_picked` callback. + * + * @param[in] dma2d_chan 2D-DMA channel handle, get from the `on_job_picked` callback input argument `dma2d_chans` + * @param[in] config Configuration of 2D-DMA channel color space conversion + * @return + * - ESP_OK: Configure DMA color space conversion successfully + * - ESP_ERR_INVALID_ARG: Configure DMA color space conversion failed because of invalid argument + */ +//go:linkname Dma2dConfigureColorSpaceConversion C.dma2d_configure_color_space_conversion +func Dma2dConfigureColorSpaceConversion(dma2d_chan Dma2dChannelHandleT, config *Dma2dCscConfigT) EspErrT + +/** + * @brief A collection of configurations apply to 2D-DMA channel DSCR-PORT mode + */ + +type Dma2dDscrPortModeConfigT struct { + BlockH c.Uint32T + BlockV c.Uint32T +} + +/** + * @brief Configure 2D-DMA channel DSCR-PORT mode + * + * @note This API only targets PPA SRM, which uses 2D-DMA DSCR-PORT mode. + * + * @param[in] dma2d_chan 2D-DMA channel handle, get from the `on_job_picked` callback input argument `dma2d_chans` + * @param[in] config Configuration of 2D-DMA channel DSCR-PORT mode + * @return + * - ESP_OK: Configure 2D-DMA dscr-port mode successfully + * - ESP_ERR_INVALID_ARG: Configure 2D-DMA dscr-port mode failed because of invalid argument + */ +//go:linkname Dma2dConfigureDscrPortMode C.dma2d_configure_dscr_port_mode +func Dma2dConfigureDscrPortMode(dma2d_chan Dma2dChannelHandleT, config *Dma2dDscrPortModeConfigT) EspErrT + +/** + * @brief Type of 2D-DMA event data + */ + +type Dma2dEventDataT struct { + Transaction *Dma2dTransT +} + +// llgo:type C +type Dma2dEventCallbackT func(Dma2dChannelHandleT, *Dma2dEventDataT, c.Pointer) bool + +/** + * @brief Group of supported 2D-DMA TX callbacks + * @note The callbacks are all running under ISR environment + */ + +type Dma2dTxEventCallbacksT struct { + OnDescDone Dma2dEventCallbackT +} + +/** + * @brief Group of supported 2D-DMA RX callbacks + * @note The callbacks are all running under ISR environment + * + * Users should be clear on the unique responsibility of each callback when writing the callback functions, such as + * where to free the transaction memory. + */ + +type Dma2dRxEventCallbacksT struct { + OnRecvEof Dma2dEventCallbackT + OnDescDone Dma2dEventCallbackT + OnDescEmpty Dma2dEventCallbackT +} + +/** + * @brief Set 2D-DMA event callbacks for TX channel + * + * Usually only to be called in `on_job_picked` callback. + * + * @param[in] dma2d_chan 2D-DMA TX channel handle, get from the `on_job_picked` callback input argument `dma2d_chans` + * @param[in] cbs Group of callback functions + * @param[in] user_data User data, which will be passed to callback functions directly + * @return + * - ESP_OK: Set event callbacks successfully + * - ESP_ERR_INVALID_ARG: Set event callbacks failed because of invalid argument + */ +//go:linkname Dma2dRegisterTxEventCallbacks C.dma2d_register_tx_event_callbacks +func Dma2dRegisterTxEventCallbacks(dma2d_chan Dma2dChannelHandleT, cbs *Dma2dTxEventCallbacksT, user_data c.Pointer) EspErrT + +/** + * @brief Set 2D-DMA event callbacks for RX channel + * + * Usually only to be called in `on_job_picked` callback. + * + * @param[in] dma2d_chan 2D-DMA RX channel handle, get from the `on_job_picked` callback input argument `dma2d_chans` + * @param[in] cbs Group of callback functions + * @param[in] user_data User data, which will be passed to callback functions directly + * @return + * - ESP_OK: Set event callbacks successfully + * - ESP_ERR_INVALID_ARG: Set event callbacks failed because of invalid argument + */ +//go:linkname Dma2dRegisterRxEventCallbacks C.dma2d_register_rx_event_callbacks +func Dma2dRegisterRxEventCallbacks(dma2d_chan Dma2dChannelHandleT, cbs *Dma2dRxEventCallbacksT, user_data c.Pointer) EspErrT + +/** + * @brief Set descriptor address for 2D-DMA channel + * + * Usually only to be called in `on_job_picked` callback. + * + * @param[in] dma2d_chan 2D-DMA channel handle, get from the `on_job_picked` callback input argument `dma2d_chans` + * @param[in] desc_base_addr Base address of descriptors + * @return + * - ESP_OK: Set 2D-DMA descriptor addr successfully + * - ESP_ERR_INVALID_ARG: Set 2D-DMA descriptor addr failed because of invalid argument + */ +//go:linkname Dma2dSetDescAddr C.dma2d_set_desc_addr +func Dma2dSetDescAddr(dma2d_chan Dma2dChannelHandleT, desc_base_addr c.IntptrT) EspErrT + +/** + * @brief Start engine for 2D-DMA channel + * + * Usually only to be called in `on_job_picked` callback. + * + * @param[in] dma2d_chan 2D-DMA channel handle, get from the `on_job_picked` callback input argument `dma2d_chans` + * @return + * - ESP_OK: Start 2D-DMA engine successfully + * - ESP_ERR_INVALID_ARG: Start 2D-DMA engine failed because of invalid argument + */ +//go:linkname Dma2dStart C.dma2d_start +func Dma2dStart(dma2d_chan Dma2dChannelHandleT) EspErrT + +/** + * @brief Stop engine for 2D-DMA channel + * + * Usually to be called in ISR context. + * + * @param[in] dma2d_chan 2D-DMA channel handle + * @return + * - ESP_OK: Stop 2D-DMA engine successfully + * - ESP_ERR_INVALID_ARG: Stop 2D-DMA engine failed because of invalid argument + */ +//go:linkname Dma2dStop C.dma2d_stop +func Dma2dStop(dma2d_chan Dma2dChannelHandleT) EspErrT + +/** + * @brief Make the appended descriptors be aware to the 2D-DMA engine + * + * Usually to be called in ISR context. + * + * @param[in] dma2d_chan 2D-DMA channel handle + * @return + * - ESP_OK: Send append command to 2D-DMA engine successfully + * - ESP_ERR_INVALID_ARG: Send append command to 2D-DMA engine failed because of invalid argument + */ +//go:linkname Dma2dAppend C.dma2d_append +func Dma2dAppend(dma2d_chan Dma2dChannelHandleT) EspErrT + +/** + * @brief Reset engine for 2D-DMA channel + * + * Usually to be called in ISR context. + * + * @param[in] dma2d_chan 2D-DMA channel handle + * @return + * - ESP_OK: Reset 2D-DMA engine successfully + * - ESP_ERR_INVALID_ARG: Reset 2D-DMA engine failed because of invalid argument + */ +//go:linkname Dma2dReset C.dma2d_reset +func Dma2dReset(dma2d_chan Dma2dChannelHandleT) EspErrT diff --git a/esp32/dma2d_hal.go b/esp32/dma2d_hal.go new file mode 100644 index 00000000..79585504 --- /dev/null +++ b/esp32/dma2d_hal.go @@ -0,0 +1,49 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type Dma2dDevT struct { + Unused [8]uint8 +} +type Dma2dSocHandleT *Dma2dDevT + +/** + * Context that should be maintained by both the driver and the HAL + */ + +type Dma2dHalContextT struct { + Dev Dma2dSocHandleT +} + +/** + * @brief Init the 2D-DMA hal. This function should be called first before other hal layer function is called + * + * @param hal Context of the HAL layer + * @param group_id The 2D-DMA group number + */ +// llgo:link (*Dma2dHalContextT).Dma2dHalInit C.dma2d_hal_init +func (recv_ *Dma2dHalContextT) Dma2dHalInit(group_id c.Int) { +} + +/** + * @brief Reset 2D-DMA TX channel + * + * @param hal Context of the HAL layer + * @param channel TX channel ID + */ +// llgo:link (*Dma2dHalContextT).Dma2dHalTxResetChannel C.dma2d_hal_tx_reset_channel +func (recv_ *Dma2dHalContextT) Dma2dHalTxResetChannel(channel c.Uint32T) { +} + +/** + * @brief Reset 2D-DMA RX channel + * + * @param hal Context of the HAL layer + * @param channel RX channel ID + */ +// llgo:link (*Dma2dHalContextT).Dma2dHalRxResetChannel C.dma2d_hal_rx_reset_channel +func (recv_ *Dma2dHalContextT) Dma2dHalRxResetChannel(channel c.Uint32T) { +} diff --git a/esp32/dma2d_types.go b/esp32/dma2d_types.go new file mode 100644 index 00000000..dd2df0f8 --- /dev/null +++ b/esp32/dma2d_types.go @@ -0,0 +1,102 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type Dma2dDescriptorAlign8S struct { + Buffer c.Pointer + Next *Dma2dDescriptorAlign8T +} +type Dma2dDescriptorAlign8T Dma2dDescriptorAlign8S +type Dma2dDescriptorT Dma2dDescriptorAlign8T +type Dma2dTriggerPeripheralT c.Int + +const ( + DMA2D_TRIG_PERIPH_M2M Dma2dTriggerPeripheralT = 0 + DMA2D_TRIG_PERIPH_JPEG_ENCODER Dma2dTriggerPeripheralT = 1 + DMA2D_TRIG_PERIPH_JPEG_DECODER Dma2dTriggerPeripheralT = 2 + DMA2D_TRIG_PERIPH_PPA_SRM Dma2dTriggerPeripheralT = 3 + DMA2D_TRIG_PERIPH_PPA_BLEND Dma2dTriggerPeripheralT = 4 +) + +type Dma2dChannelDirectionT c.Int + +const ( + DMA2D_CHANNEL_DIRECTION_TX Dma2dChannelDirectionT = 0 + DMA2D_CHANNEL_DIRECTION_RX Dma2dChannelDirectionT = 1 +) + +type Dma2dDataBurstLengthT c.Int + +const ( + DMA2D_DATA_BURST_LENGTH_8 Dma2dDataBurstLengthT = 1 + DMA2D_DATA_BURST_LENGTH_16 Dma2dDataBurstLengthT = 2 + DMA2D_DATA_BURST_LENGTH_32 Dma2dDataBurstLengthT = 3 + DMA2D_DATA_BURST_LENGTH_64 Dma2dDataBurstLengthT = 4 + DMA2D_DATA_BURST_LENGTH_128 Dma2dDataBurstLengthT = 5 + DMA2D_DATA_BURST_LENGTH_INVALID Dma2dDataBurstLengthT = 6 +) + +type Dma2dMacroBlockSizeT c.Int + +const ( + DMA2D_MACRO_BLOCK_SIZE_NONE Dma2dMacroBlockSizeT = 0 + DMA2D_MACRO_BLOCK_SIZE_8_8 Dma2dMacroBlockSizeT = 1 + DMA2D_MACRO_BLOCK_SIZE_8_16 Dma2dMacroBlockSizeT = 2 + DMA2D_MACRO_BLOCK_SIZE_16_16 Dma2dMacroBlockSizeT = 3 + DMA2D_MACRO_BLOCK_SIZE_INVALID Dma2dMacroBlockSizeT = 4 +) + +type Dma2dScrambleOrderT c.Int + +const ( + DMA2D_SCRAMBLE_ORDER_BYTE2_1_0 Dma2dScrambleOrderT = 0 + DMA2D_SCRAMBLE_ORDER_BYTE2_0_1 Dma2dScrambleOrderT = 1 + DMA2D_SCRAMBLE_ORDER_BYTE1_0_2 Dma2dScrambleOrderT = 2 + DMA2D_SCRAMBLE_ORDER_BYTE1_2_0 Dma2dScrambleOrderT = 3 + DMA2D_SCRAMBLE_ORDER_BYTE0_2_1 Dma2dScrambleOrderT = 4 + DMA2D_SCRAMBLE_ORDER_BYTE0_1_2 Dma2dScrambleOrderT = 5 + DMA2D_SCRAMBLE_ORDER_INVALID Dma2dScrambleOrderT = 6 +) + +type Dma2dCscTxOptionT c.Int + +const ( + DMA2D_CSC_TX_NONE Dma2dCscTxOptionT = 0 + DMA2D_CSC_TX_SCRAMBLE Dma2dCscTxOptionT = 1 + DMA2D_CSC_TX_RGB888_TO_RGB565 Dma2dCscTxOptionT = 2 + DMA2D_CSC_TX_RGB565_TO_RGB888 Dma2dCscTxOptionT = 3 + DMA2D_CSC_TX_RGB888_TO_YUV444_601 Dma2dCscTxOptionT = 4 + DMA2D_CSC_TX_RGB888_TO_YUV444_709 Dma2dCscTxOptionT = 5 + DMA2D_CSC_TX_RGB888_TO_YUV422_601 Dma2dCscTxOptionT = 6 + DMA2D_CSC_TX_RGB888_TO_YUV422_709 Dma2dCscTxOptionT = 7 + DMA2D_CSC_TX_YUV444_TO_RGB888_601 Dma2dCscTxOptionT = 8 + DMA2D_CSC_TX_YUV444_TO_RGB888_709 Dma2dCscTxOptionT = 9 + DMA2D_CSC_TX_YUV422_TO_RGB888_601 Dma2dCscTxOptionT = 10 + DMA2D_CSC_TX_YUV422_TO_RGB888_709 Dma2dCscTxOptionT = 11 + DMA2D_CSC_TX_INVALID Dma2dCscTxOptionT = 12 +) + +type Dma2dCscRxOptionT c.Int + +const ( + DMA2D_CSC_RX_NONE Dma2dCscRxOptionT = 0 + DMA2D_CSC_RX_SCRAMBLE Dma2dCscRxOptionT = 1 + DMA2D_CSC_RX_YUV422_TO_YUV444 Dma2dCscRxOptionT = 2 + DMA2D_CSC_RX_YUV420_TO_YUV444 Dma2dCscRxOptionT = 3 + DMA2D_CSC_RX_YUV420_TO_RGB888_601 Dma2dCscRxOptionT = 4 + DMA2D_CSC_RX_YUV420_TO_RGB565_601 Dma2dCscRxOptionT = 5 + DMA2D_CSC_RX_YUV420_TO_RGB888_709 Dma2dCscRxOptionT = 6 + DMA2D_CSC_RX_YUV420_TO_RGB565_709 Dma2dCscRxOptionT = 7 + DMA2D_CSC_RX_YUV422_TO_RGB888_601 Dma2dCscRxOptionT = 8 + DMA2D_CSC_RX_YUV422_TO_RGB565_601 Dma2dCscRxOptionT = 9 + DMA2D_CSC_RX_YUV422_TO_RGB888_709 Dma2dCscRxOptionT = 10 + DMA2D_CSC_RX_YUV422_TO_RGB565_709 Dma2dCscRxOptionT = 11 + DMA2D_CSC_RX_YUV444_TO_RGB888_601 Dma2dCscRxOptionT = 12 + DMA2D_CSC_RX_YUV444_TO_RGB565_601 Dma2dCscRxOptionT = 13 + DMA2D_CSC_RX_YUV444_TO_RGB888_709 Dma2dCscRxOptionT = 14 + DMA2D_CSC_RX_YUV444_TO_RGB565_709 Dma2dCscRxOptionT = 15 + DMA2D_CSC_RX_INVALID Dma2dCscRxOptionT = 16 +) diff --git a/esp32/dma_types.go b/esp32/dma_types.go new file mode 100644 index 00000000..9f6ed550 --- /dev/null +++ b/esp32/dma_types.go @@ -0,0 +1,37 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type DmaDescriptorS struct { + Dw0 struct { + Size c.Uint32T + Length c.Uint32T + Reversed2427 c.Uint32T + ErrEof c.Uint32T + Reserved29 c.Uint32T + SucEof c.Uint32T + Owner c.Uint32T + } + Buffer c.Pointer + Next *DmaDescriptorT +} +type DmaDescriptorT DmaDescriptorS +type DmaDescriptorAlign4T DmaDescriptorT + +type DmaDescriptorAlign8S struct { + Dw0 struct { + Size c.Uint32T + Length c.Uint32T + Reversed2427 c.Uint32T + ErrEof c.Uint32T + Reserved29 c.Uint32T + SucEof c.Uint32T + Owner c.Uint32T + } + Buffer c.Pointer + Next *DmaDescriptorAlign8T +} +type DmaDescriptorAlign8T DmaDescriptorAlign8S diff --git a/esp32/dport_access.go b/esp32/dport_access.go new file mode 100644 index 00000000..ed5bdcff --- /dev/null +++ b/esp32/dport_access.go @@ -0,0 +1,16 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Read a sequence of DPORT registers to the buffer. + * + * @param[out] buff_out Contains the read data. + * @param[in] address Initial address for reading registers. + * @param[in] num_words The number of words. + */ +//go:linkname EspDportAccessReadBuffer C.esp_dport_access_read_buffer +func EspDportAccessReadBuffer(buff_out *c.Uint32T, address c.Uint32T, num_words c.Uint32T) diff --git a/esp32/dport_reg.go b/esp32/dport_reg.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/dport_reg.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/ds_hal.go b/esp32/ds_hal.go new file mode 100644 index 00000000..cbd8510a --- /dev/null +++ b/esp32/ds_hal.go @@ -0,0 +1,68 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Start the whole signing process after the input key is ready. + * + * Call this before using any of the functions below. The input key is ready must be ready at this point. + */ +//go:linkname DsHalStart C.ds_hal_start +func DsHalStart() + +/** + * @brief Finish the whole signing process. Call this after the signature is read or in case of an error. + */ +//go:linkname DsHalFinish C.ds_hal_finish +func DsHalFinish() + +/** + * @brief Write the initialization vector. + */ +//go:linkname DsHalConfigureIv C.ds_hal_configure_iv +func DsHalConfigureIv(iv *c.Uint32T) + +/** + * @brief Write the message which should be signed. + * + * @param msg Pointer to the message. + * @param size Length of signature result in bytes. It is the RSA signature length in bytes. + */ +//go:linkname DsHalWriteMessage C.ds_hal_write_message +func DsHalWriteMessage(msg *c.Uint8T, size c.SizeT) + +/** + * @brief Write the encrypted private key parameters. + */ +//go:linkname DsHalWritePrivateKeyParams C.ds_hal_write_private_key_params +func DsHalWritePrivateKeyParams(block *c.Uint8T) + +/** + * @brief Begin signing procedure. + */ +//go:linkname DsHalStartSign C.ds_hal_start_sign +func DsHalStartSign() + +/** + * @brief Check whether the hardware is busy with an operation. + * + * @return True if the hardware has finished the signing procedure, otherwise false. + */ +//go:linkname DsHalBusy C.ds_hal_busy +func DsHalBusy() bool + +/** + * @brief Check and read the signature from the hardware. + * + * @return + * - DS_SIGNATURE_OK if no issue is detected with the signature. + * - DS_SIGNATURE_PADDING_FAIL if the padding of the private key parameters is wrong. + * - DS_SIGNATURE_MD_FAIL if the message digest check failed. This means that the message digest calculated using + * the private key parameters fails, i.e., the integrity of the private key parameters is not protected. + * - DS_SIGNATURE_PADDING_AND_MD_FAIL if both padding and message digest check fail. + */ +//go:linkname DsHalReadResult C.ds_hal_read_result +func DsHalReadResult(result *c.Uint8T, size c.SizeT) DsSignatureCheckT diff --git a/esp32/ds_ll.go b/esp32/ds_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/ds_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/ds_types.go b/esp32/ds_types.go new file mode 100644 index 00000000..7fcf45a0 --- /dev/null +++ b/esp32/ds_types.go @@ -0,0 +1,23 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type DsKeyCheckT c.Int + +const ( + DS_KEY_INPUT_OK DsKeyCheckT = 0 + DS_NO_KEY_INPUT DsKeyCheckT = 1 + DS_OTHER_WRONG DsKeyCheckT = 2 +) + +type DsSignatureCheckT c.Int + +const ( + DS_SIGNATURE_OK DsSignatureCheckT = 0 + DS_SIGNATURE_PADDING_FAIL DsSignatureCheckT = 1 + DS_SIGNATURE_MD_FAIL DsSignatureCheckT = 2 + DS_SIGNATURE_PADDING_AND_MD_FAIL DsSignatureCheckT = 3 +) diff --git a/esp32/dw_gdma.go b/esp32/dw_gdma.go new file mode 100644 index 00000000..53dd98e4 --- /dev/null +++ b/esp32/dw_gdma.go @@ -0,0 +1,420 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type DwGdmaChannelT struct { + Unused [8]uint8 +} +type DwGdmaChannelHandleT *DwGdmaChannelT + +type DwGdmaLinkListT struct { + Unused [8]uint8 +} +type DwGdmaLinkListHandleT *DwGdmaLinkListT + +type DwGdmaLinkListItemT struct { + Unused [8]uint8 +} +type DwGdmaLliHandleT *DwGdmaLinkListItemT + +/** + * @brief A group of channel's static configurations + * + * @note By static, we mean these channel end configurations shouldn't be changed after the DMA channel is created. + */ + +type DwGdmaChannelStaticConfigT struct { + BlockTransferType DwGdmaBlockTransferTypeT + Role DwGdmaRoleT + HandshakeType DwGdmaHandshakeTypeT + NumOutstandingRequests c.Uint8T + StatusFetchAddr c.Uint32T +} + +/** + * @brief Configurations for allocating a DMA channel + */ + +type DwGdmaChannelAllocConfigT struct { + Src DwGdmaChannelStaticConfigT + Dst DwGdmaChannelStaticConfigT + FlowController DwGdmaFlowControllerT + ChanPriority c.Int + IntrPriority c.Int +} + +/** + * @brief Create a DMA channel + * + * @param[in] config Channel allocation configuration + * @param[out] ret_chan Returned channel handle + * @return + * - ESP_OK: Create DMA channel successfully + * - ESP_ERR_INVALID_ARG: Create DMA channel failed because of invalid argument + * - ESP_ERR_NO_MEM: Create DMA channel failed because out of memory + * - ESP_FAIL: Create DMA channel failed because of other error + */ +// llgo:link (*DwGdmaChannelAllocConfigT).DwGdmaNewChannel C.dw_gdma_new_channel +func (recv_ *DwGdmaChannelAllocConfigT) DwGdmaNewChannel(ret_chan *DwGdmaChannelHandleT) EspErrT { + return 0 +} + +/** + * @brief Delete DMA channel + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @return + * - ESP_OK: Delete DMA channel successfully + * - ESP_ERR_INVALID_ARG: Delete DMA channel failed because of invalid argument + * - ESP_FAIL: Delete DMA channel failed because of other error + */ +//go:linkname DwGdmaDelChannel C.dw_gdma_del_channel +func DwGdmaDelChannel(chan_ DwGdmaChannelHandleT) EspErrT + +/** + * @brief Get the DMA channel ID + * + * @note This API breaks the encapsulation of DW_GDMA Channel Object. + * With the returned channel ID, you can even bypass all other driver API and access Low Level API directly. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @param[out] channel_id Returned channel ID + * @return + * - ESP_OK: Get DW_GDMA channel ID successfully + * - ESP_ERR_INVALID_ARG: Get DW_GDMA channel ID failed because of invalid argument + * - ESP_FAIL: Get DW_GDMA channel ID failed because of other error + */ +//go:linkname DwGdmaChannelGetId C.dw_gdma_channel_get_id +func DwGdmaChannelGetId(chan_ DwGdmaChannelHandleT, channel_id *c.Int) EspErrT + +/** + * @brief A group of channel's dynamic configurations + * + * @note By dynamic, we mean these channel end configurations can be changed in each transfer. + */ + +type DwGdmaChannelDynamicConfigT struct { + Addr c.Uint32T + Width DwGdmaTransferWidthT + BurstMode DwGdmaBurstModeT + BurstItems DwGdmaBurstItemsT + BurstLen c.Uint8T + Flags struct { + EnStatusWriteBack c.Uint32T + } +} + +/** + * @brief Channel block transfer configurations + */ + +type DwGdmaBlockTransferConfigT struct { + Src DwGdmaChannelDynamicConfigT + Dst DwGdmaChannelDynamicConfigT + Size c.SizeT +} + +/** + * @brief Configure transfer parameters for a DMA channel + * + * @note This is an "all-in-one" function for set up the block transfer. + * @note This function can't work with Link-List transfer type. For Link-List transfer, please use `dw_gdma_lli_config_transfer` instead. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @param[in] config Block transfer configurations + * @return + * - ESP_OK: Configure DMA channel block transfer successfully + * - ESP_ERR_INVALID_ARG: Configure DMA channel block transfer failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Configure DMA channel block transfer failed because the channel has Link-List transfer type + * - ESP_FAIL: Configure DMA channel block transfer failed because of other error + */ +//go:linkname DwGdmaChannelConfigTransfer C.dw_gdma_channel_config_transfer +func DwGdmaChannelConfigTransfer(chan_ DwGdmaChannelHandleT, config *DwGdmaBlockTransferConfigT) EspErrT + +/** + * @brief Enable or disable a DMA channel + * + * @note Before enabling a channel, you need to setup the channel transfer by either `dw_gdma_channel_config_transfer` or `dw_gdma_lli_config_transfer` + * @note When a DMA channel is disabled, the DMA engine will stop working. You need to reconfigure the channel before enabling it again. + * @note After all block transfers are completed, the DMA channel will be disabled automatically. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @param[in] en_or_dis True to enable, false to disable the DMA channel + * @return + * - ESP_OK: Enable or disable DMA channel successfully + * - ESP_ERR_INVALID_ARG: Enable or disable DMA channel failed because of invalid argument + * - ESP_FAIL: Enable or disable DMA channel failed because of other error + */ +//go:linkname DwGdmaChannelEnableCtrl C.dw_gdma_channel_enable_ctrl +func DwGdmaChannelEnableCtrl(chan_ DwGdmaChannelHandleT, en_or_dis bool) EspErrT + +/** + * @brief Suspend or resume a DMA channel + * + * @note When a DMA channel is suspended, the DMA engine will stop working gracefully and the channel's status will be saved. + * @note The channel will exit the suspend state automatically if it is disabled. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @param[in] enter_or_exit True to suspend, false to resume the DMA channel + * @return + * - ESP_OK: Suspend or resume DMA channel successfully + * - ESP_ERR_INVALID_ARG: Suspend or resume DMA channel failed because of invalid argument + * - ESP_FAIL: Suspend or resume DMA channel failed because of other error + */ +//go:linkname DwGdmaChannelSuspendCtrl C.dw_gdma_channel_suspend_ctrl +func DwGdmaChannelSuspendCtrl(chan_ DwGdmaChannelHandleT, enter_or_exit bool) EspErrT + +/** + * @brief Abort the DMA channel + * + * @note If the channel is aborted, it will be disabled immediately, which may cause AXI bus protocol violation. + * @note This function is recommended to only be used when the channel hangs. Recommend to try `dw_gdma_channel_enable_ctrl` first, then opt for aborting. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @return + * - ESP_OK: Abort DMA channel successfully + * - ESP_ERR_INVALID_ARG: Abort DMA channel failed because of invalid argument + * - ESP_FAIL: Abort DMA channel failed because of other error + */ +//go:linkname DwGdmaChannelAbort C.dw_gdma_channel_abort +func DwGdmaChannelAbort(chan_ DwGdmaChannelHandleT) EspErrT + +/** + * @brief Lock the DMA channel at specific transfer level + * + * @note When a DMA channel is locked, no other channels are granted control of the master bus for the duration specified by the lock level. + * @note Only lock the channel if you want to exclusive access to the master bus. + * @note Channel locking feature is only for M2M transfer. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @param[in] level Transfer level + * @return + * - ESP_OK: Lock DMA channel successfully + * - ESP_ERR_INVALID_ARG: Lock DMA channel failed because of invalid argument + * - ESP_FAIL: Lock DMA channel failed because of other error + */ +//go:linkname DwGdmaChannelLock C.dw_gdma_channel_lock +func DwGdmaChannelLock(chan_ DwGdmaChannelHandleT, level DwGdmaLockLevelT) EspErrT + +/** + * @brief Unlock the DMA channel + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @return + * - ESP_OK: Unlock DMA channel successfully + * - ESP_ERR_INVALID_ARG: Unlock DMA channel failed because of invalid argument + * - ESP_FAIL: Unlock DMA channel failed because of other error + */ +//go:linkname DwGdmaChannelUnlock C.dw_gdma_channel_unlock +func DwGdmaChannelUnlock(chan_ DwGdmaChannelHandleT) EspErrT + +/** + * @brief Continue the temporarily stopped DMA transfer because of invalid block + * + * @note You should only call this API when the block becomes valid again, + * by calling `dw_gdma_lli_set_block_markers`/`dw_gdma_channel_set_block_markers` with `is_valid` set to true. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @return + * - ESP_OK: Continue DMA transfer successfully + * - ESP_ERR_INVALID_ARG: Continue DMA transfer failed because of invalid argument + * - ESP_FAIL: Continue DMA transfer failed because of other error + */ +//go:linkname DwGdmaChannelContinue C.dw_gdma_channel_continue +func DwGdmaChannelContinue(chan_ DwGdmaChannelHandleT) EspErrT + +/** + * @brief Type of DW_GDMA trans done event data + */ + +type DwGdmaTransDoneEventDataT struct { + Unused [8]uint8 +} + +// llgo:type C +type DwGdmaTransDoneEventCallbackT func(DwGdmaChannelHandleT, *DwGdmaTransDoneEventDataT, c.Pointer) bool + +/** + * @brief Type of DW_GDMA break event data + */ + +type DwGdmaBreakEventDataT struct { + InvalidLli DwGdmaLliHandleT +} + +// llgo:type C +type DwGdmaBreakEventCallbackT func(DwGdmaChannelHandleT, *DwGdmaBreakEventDataT, c.Pointer) bool + +/** + * @brief Group of supported DW_GDMA callbacks + * @note The callbacks are all running under ISR environment + */ + +type DwGdmaEventCallbacksT struct { + OnBlockTransDone DwGdmaTransDoneEventCallbackT + OnFullTransDone DwGdmaTransDoneEventCallbackT + OnInvalidBlock DwGdmaBreakEventCallbackT +} + +/** + * @brief Set DW_GDMA event callbacks for a channel + * @note This API will lazy install the DW_GDMA interrupt service + * + * @param[in] chan DW_GDMA channel handle, allocated by `dw_gdma_new_channel` + * @param[in] cbs Group of callback functions + * @param[in] user_data User data, which will be passed to callback functions directly + * @return + * - ESP_OK: Set event callbacks successfully + * - ESP_ERR_INVALID_ARG: Set event callbacks failed because of invalid argument + * - ESP_FAIL: Set event callbacks failed because of other error + */ +//go:linkname DwGdmaChannelRegisterEventCallbacks C.dw_gdma_channel_register_event_callbacks +func DwGdmaChannelRegisterEventCallbacks(chan_ DwGdmaChannelHandleT, cbs *DwGdmaEventCallbacksT, user_data c.Pointer) EspErrT + +type DwGdmaLinkListTypeT c.Int + +const ( + DW_GDMA_LINKED_LIST_TYPE_SINGLY DwGdmaLinkListTypeT = 0 + DW_GDMA_LINKED_LIST_TYPE_CIRCULAR DwGdmaLinkListTypeT = 1 +) + +/** + * @brief DMA link list configurations + */ + +type DwGdmaLinkListConfigT struct { + NumItems c.Uint32T + LinkType DwGdmaLinkListTypeT +} + +/** + * @brief Create a DMA link list + * + * @param[in] config Link list configurations + * @param[out] ret_list Returned link list handle + * @return + * - ESP_OK: Create DMA link list successfully + * - ESP_ERR_INVALID_ARG: Create DMA link list failed because of invalid argument + * - ESP_ERR_NO_MEM: Create DMA link list failed because out of memory + * - ESP_FAIL: Create DMA link list failed because of other error + */ +// llgo:link (*DwGdmaLinkListConfigT).DwGdmaNewLinkList C.dw_gdma_new_link_list +func (recv_ *DwGdmaLinkListConfigT) DwGdmaNewLinkList(ret_list *DwGdmaLinkListHandleT) EspErrT { + return 0 +} + +/** + * @brief Delete a DMA link list + * + * @param[in] list Link list handle, allocated by `dw_gdma_new_link_list` + * @return + * - ESP_OK: Delete DMA link list successfully + * - ESP_ERR_INVALID_ARG: Delete DMA link list failed because of invalid argument + * - ESP_FAIL: Delete DMA link list failed because of other error + */ +//go:linkname DwGdmaDelLinkList C.dw_gdma_del_link_list +func DwGdmaDelLinkList(list DwGdmaLinkListHandleT) EspErrT + +/** + * @brief Apply a link list to a DMA channel + * + * @note This function can only work with Link-List transfer type. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @param[in] list Link list handle, allocated by `dw_gdma_new_link_list` + * @return + * - ESP_OK: Apply link list to DMA channel successfully + * - ESP_ERR_INVALID_ARG: Apply link list to DMA channel failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Apply link list to DMA channel failed because the channel is not with Link-List transfer type + * - ESP_FAIL: Apply link list to DMA channel failed because of other error + */ +//go:linkname DwGdmaChannelUseLinkList C.dw_gdma_channel_use_link_list +func DwGdmaChannelUseLinkList(chan_ DwGdmaChannelHandleT, list DwGdmaLinkListHandleT) EspErrT + +/** + * @brief A helper function to return an item from a given link list, by index + * + * @note The address of the returned item is not behind the cache + * + * @param[in] list Link list handle, allocated by `dw_gdma_new_link_list` + * @param[in] item_index Index of the item + * @return + * - NULL: Invalid argument + * - Others: Link list item handle + */ +//go:linkname DwGdmaLinkListGetItem C.dw_gdma_link_list_get_item +func DwGdmaLinkListGetItem(list DwGdmaLinkListHandleT, item_index c.Int) DwGdmaLliHandleT + +/** + * @brief Configure transfer parameters for a DMA link list item + * + * @note This is an "all-in-one" function for set up the link list item. + * @note This function can only work with Link-List transfer type. For other transfer types, please use `dw_gdma_channel_config_transfer` instead. + * + * @param[in] lli Link list item + * @param[in] config Block transfer configurations + * @return + * - ESP_OK: Configure link list item block transfer successfully + * - ESP_ERR_INVALID_ARG: Configure link list item block transfer failed because of invalid argument + * - ESP_FAIL: Configure link list item block transfer failed because of other error + */ +//go:linkname DwGdmaLliConfigTransfer C.dw_gdma_lli_config_transfer +func DwGdmaLliConfigTransfer(lli DwGdmaLliHandleT, config *DwGdmaBlockTransferConfigT) EspErrT + +/** + * @brief Set the next link list item for a given DMA link list item + * + * @param[in] lli Current link list item, can be obtained from `dw_gdma_link_list_get_item` + * @param[in] next Next link list item, can be obtained from `dw_gdma_link_list_get_item` + * @return + * - ESP_OK: Set next link list item successfully + * - ESP_ERR_INVALID_ARG: Set next link list item failed because of invalid argument + * - ESP_FAIL: Set next link list item failed because of other error + */ +//go:linkname DwGdmaLliSetNext C.dw_gdma_lli_set_next +func DwGdmaLliSetNext(lli DwGdmaLliHandleT, next DwGdmaLliHandleT) EspErrT + +/** + * @brief Markers of a DW_GDMA block + */ + +type DwGdmaBlockMarkersT struct { + IsLast c.Uint32T + IsValid c.Uint32T + EnTransDoneIntr c.Uint32T +} + +/** + * @brief Set block markers for a DMA channel + * + * @note This function doesn't work for Link-List transfer type. For Link-List transfer, please use `dw_gdma_lli_set_block_markers` instead. + * @note Setting the markers should always be the last step of configuring a block transfer, before enabling/continuing the channel. + * + * @param[in] chan DMA channel handle, allocated by `dw_gdma_new_channel` + * @param[in] markers Block markers + * @return + * - ESP_OK: Set block markers successfully + * - ESP_ERR_INVALID_ARG: Set block markers failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Set block markers failed because the channel has Link-List transfer type + * - ESP_FAIL: Set block markers failed because of other error + */ +//go:linkname DwGdmaChannelSetBlockMarkers C.dw_gdma_channel_set_block_markers +func DwGdmaChannelSetBlockMarkers(chan_ DwGdmaChannelHandleT, markers DwGdmaBlockMarkersT) EspErrT + +/** + * @brief Set block markers for a DMA link list item + * + * @note Setting the markers should always be the last step of configuring a block transfer, before enabling/continuing the channel. + * + * @param[in] lli Link list item + * @param[in] markers Block markers + * @return + * - ESP_OK: Set block markers successfully + * - ESP_ERR_INVALID_ARG: Set block markers failed because of invalid argument + * - ESP_FAIL: Set block markers failed because of other error + */ +//go:linkname DwGdmaLliSetBlockMarkers C.dw_gdma_lli_set_block_markers +func DwGdmaLliSetBlockMarkers(lli DwGdmaLliHandleT, markers DwGdmaBlockMarkersT) EspErrT diff --git a/esp32/dw_gdma_hal.go b/esp32/dw_gdma_hal.go new file mode 100644 index 00000000..0eecdc58 --- /dev/null +++ b/esp32/dw_gdma_hal.go @@ -0,0 +1,45 @@ +package freertos + +import _ "unsafe" + +type DwGdmaDevT struct { + Unused [8]uint8 +} +type DwGdmaSocHandleT *DwGdmaDevT + +/** + * @brief DW_GDMA HAL driver context + */ + +type DwGdmaHalContextT struct { + Dev DwGdmaSocHandleT +} + +/** + * @brief DW_GDMA HAL driver configuration + */ + +type DwGdmaHalConfigT struct { + Unused [8]uint8 +} + +/** + * @brief DW_GDMA HAL driver initialization + * + * @note Caller should malloc the memory for the hal context + * + * @param hal Pointer to the HAL driver context + * @param config Pointer to the HAL driver configuration + */ +// llgo:link (*DwGdmaHalContextT).DwGdmaHalInit C.dw_gdma_hal_init +func (recv_ *DwGdmaHalContextT) DwGdmaHalInit(config *DwGdmaHalConfigT) { +} + +/** + * @brief DW_GDMA HAL driver deinitialization + * + * @param hal Pointer to the HAL driver context + */ +// llgo:link (*DwGdmaHalContextT).DwGdmaHalDeinit C.dw_gdma_hal_deinit +func (recv_ *DwGdmaHalContextT) DwGdmaHalDeinit() { +} diff --git a/esp32/dw_gdma_types.go b/esp32/dw_gdma_types.go new file mode 100644 index 00000000..026586a8 --- /dev/null +++ b/esp32/dw_gdma_types.go @@ -0,0 +1,80 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type DwGdmaBlockTransferTypeT c.Int + +const ( + DW_GDMA_BLOCK_TRANSFER_CONTIGUOUS DwGdmaBlockTransferTypeT = 0 + DW_GDMA_BLOCK_TRANSFER_RELOAD DwGdmaBlockTransferTypeT = 1 + DW_GDMA_BLOCK_TRANSFER_SHADOW DwGdmaBlockTransferTypeT = 2 + DW_GDMA_BLOCK_TRANSFER_LIST DwGdmaBlockTransferTypeT = 3 +) + +type DwGdmaFlowControllerT c.Int + +const ( + DW_GDMA_FLOW_CTRL_SELF DwGdmaFlowControllerT = 0 + DW_GDMA_FLOW_CTRL_SRC DwGdmaFlowControllerT = 1 + DW_GDMA_FLOW_CTRL_DST DwGdmaFlowControllerT = 2 +) + +type DwGdmaHandshakeTypeT c.Int + +const ( + DW_GDMA_HANDSHAKE_HW DwGdmaHandshakeTypeT = 0 + DW_GDMA_HANDSHAKE_SW DwGdmaHandshakeTypeT = 1 +) + +type DwGdmaRoleT c.Int + +const ( + DW_GDMA_ROLE_MEM DwGdmaRoleT = 0 + DW_GDMA_ROLE_PERIPH_DSI DwGdmaRoleT = 1 + DW_GDMA_ROLE_PERIPH_CSI DwGdmaRoleT = 2 + DW_GDMA_ROLE_PERIPH_ISP DwGdmaRoleT = 3 +) + +type DwGdmaLockLevelT c.Int + +const ( + DW_GDMA_LOCK_LEVEL_FULL_TRANS DwGdmaLockLevelT = 0 + DW_GDMA_LOCK_LEVEL_BLOCK_TRANS DwGdmaLockLevelT = 1 +) + +type DwGdmaTransferWidthT c.Int + +const ( + DW_GDMA_TRANS_WIDTH_8 DwGdmaTransferWidthT = 0 + DW_GDMA_TRANS_WIDTH_16 DwGdmaTransferWidthT = 1 + DW_GDMA_TRANS_WIDTH_32 DwGdmaTransferWidthT = 2 + DW_GDMA_TRANS_WIDTH_64 DwGdmaTransferWidthT = 3 + DW_GDMA_TRANS_WIDTH_128 DwGdmaTransferWidthT = 4 + DW_GDMA_TRANS_WIDTH_256 DwGdmaTransferWidthT = 5 + DW_GDMA_TRANS_WIDTH_512 DwGdmaTransferWidthT = 6 +) + +type DwGdmaBurstModeT c.Int + +const ( + DW_GDMA_BURST_MODE_INCREMENT DwGdmaBurstModeT = 0 + DW_GDMA_BURST_MODE_FIXED DwGdmaBurstModeT = 1 +) + +type DwGdmaBurstItemsT c.Int + +const ( + DW_GDMA_BURST_ITEMS_1 DwGdmaBurstItemsT = 0 + DW_GDMA_BURST_ITEMS_4 DwGdmaBurstItemsT = 1 + DW_GDMA_BURST_ITEMS_8 DwGdmaBurstItemsT = 2 + DW_GDMA_BURST_ITEMS_16 DwGdmaBurstItemsT = 3 + DW_GDMA_BURST_ITEMS_32 DwGdmaBurstItemsT = 4 + DW_GDMA_BURST_ITEMS_64 DwGdmaBurstItemsT = 5 + DW_GDMA_BURST_ITEMS_128 DwGdmaBurstItemsT = 6 + DW_GDMA_BURST_ITEMS_256 DwGdmaBurstItemsT = 7 + DW_GDMA_BURST_ITEMS_512 DwGdmaBurstItemsT = 8 + DW_GDMA_BURST_ITEMS_1024 DwGdmaBurstItemsT = 9 +) diff --git a/esp32/ecc_hal.go b/esp32/ecc_hal.go new file mode 100644 index 00000000..5b262042 --- /dev/null +++ b/esp32/ecc_hal.go @@ -0,0 +1,101 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Set the work mode of the operation + * + * @param mode Mode of operation + */ +// llgo:link EccModeT.EccHalSetMode C.ecc_hal_set_mode +func (recv_ EccModeT) EccHalSetMode() { +} + +/** + * @brief Set the ECC curve of operation + * + * @param curve Curve to use for operation + */ +// llgo:link EccCurveT.EccHalSetCurve C.ecc_hal_set_curve +func (recv_ EccCurveT) EccHalSetCurve() { +} + +/** + * @brief Start calculation + * + */ +//go:linkname EccHalStartCalc C.ecc_hal_start_calc +func EccHalStartCalc() + +/** + * @brief Check whether the calculation has finished + * + * @return - 1 if the hardware has finished calculating + * - 0 otherwise + */ +//go:linkname EccHalIsCalcFinished C.ecc_hal_is_calc_finished +func EccHalIsCalcFinished() c.Int + +/** + * @brief Write parameters for point multiplication (K * (Px, Py)) + * + * @param k Scalar value + * @param px X coordinate of the ECC point + * @param py Y coordinate of the ECC point + * @param len Length (in bytes) of the ECC point + * - 32 bytes for SECP256R1 + * - 24 bytes for SECP192R1 + */ +//go:linkname EccHalWriteMulParam C.ecc_hal_write_mul_param +func EccHalWriteMulParam(k *c.Uint8T, px *c.Uint8T, py *c.Uint8T, len c.Uint16T) + +/** + * @brief Write parameters for point verification, + * i.e to check if the point lies on the curve + * + * @param px X coordinate of the ECC point + * @param py Y coordinate of the ECC point + * @param len Length (in bytes) of the ECC point + * - 32 for SECP256R1 + * - 24 for SECP192R1 + */ +//go:linkname EccHalWriteVerifyParam C.ecc_hal_write_verify_param +func EccHalWriteVerifyParam(px *c.Uint8T, py *c.Uint8T, len c.Uint16T) + +/** + * @brief Read point multiplication result + * + * @param rx X coordinate of the multiplication result + * @param ry Y coordinate of the multiplication result + * @param len Length (in bytes) of the ECC point + * - 32 for SECP256R1 + * - 24 for SECP192R1 + * + * @return - 0 if the operation was successful + * - -1 if the operation was not successful + * + * In case the operation is not successful, rx and ry will contain + * all zeros + */ +//go:linkname EccHalReadMulResult C.ecc_hal_read_mul_result +func EccHalReadMulResult(rx *c.Uint8T, ry *c.Uint8T, len c.Uint16T) c.Int + +/** + * @brief Read point verification result + * + * @return - 1 if point lies on curve + * - 0 otherwise + */ +//go:linkname EccHalReadVerifyResult C.ecc_hal_read_verify_result +func EccHalReadVerifyResult() c.Int + +/** + * @brief Enable constant time multiplication operations + * + * @param true: enable; false: disable + */ +//go:linkname EccHalEnableConstantTimePointMul C.ecc_hal_enable_constant_time_point_mul +func EccHalEnableConstantTimePointMul(enable bool) diff --git a/esp32/ecc_types.go b/esp32/ecc_types.go new file mode 100644 index 00000000..f179956a --- /dev/null +++ b/esp32/ecc_types.go @@ -0,0 +1,36 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EccModeT c.Int + +const ( + ECC_MODE_POINT_MUL EccModeT = 0 + ECC_MODE_INVERSE_MUL EccModeT = 1 + ECC_MODE_VERIFY EccModeT = 2 + ECC_MODE_VERIFY_THEN_POINT_MUL EccModeT = 3 + ECC_MODE_JACOBIAN_POINT_MUL EccModeT = 4 + ECC_MODE_POINT_ADD EccModeT = 5 + ECC_MODE_JACOBIAN_POINT_VERIFY EccModeT = 6 + ECC_MODE_POINT_VERIFY_JACOBIAN_MUL EccModeT = 7 + ECC_MODE_MOD_ADD EccModeT = 8 + ECC_MODE_MOD_SUB EccModeT = 9 + ECC_MODE_MOD_MUL EccModeT = 10 +) + +type EccCurveT c.Int + +const ( + ECC_CURVE_SECP192R1 EccCurveT = 0 + ECC_CURVE_SECP256R1 EccCurveT = 1 +) + +type EccModBaseT c.Int + +const ( + ECC_MOD_N EccModBaseT = 0 + ECC_MOD_P EccModBaseT = 1 +) diff --git a/esp32/ecdsa_hal.go b/esp32/ecdsa_hal.go new file mode 100644 index 00000000..9c1ef1a4 --- /dev/null +++ b/esp32/ecdsa_hal.go @@ -0,0 +1,61 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* + * ECDSA peripheral config structure + */ + +type EcdsaHalConfigT struct { + Mode EcdsaModeT + Curve EcdsaCurveT + ShaMode EcdsaShaModeT + EfuseKeyBlk c.Int + UseKmKey bool + SignType EcdsaSignTypeT + LoopNumber c.Uint16T +} + +/** + * @brief Generate ECDSA signature + * + * @param conf Configuration for ECDSA operation, see ``ecdsa_hal_config_t`` + * @param hash Hash that is to be signed + * @param r_out Buffer that will contain `R` component of ECDSA signature + * @param s_out Buffer that will contain `S` component of ECDSA signature + * @param len Length of the r_out and s_out buffer (32 bytes for SECP256R1, 24 for SECP192R1) + */ +// llgo:link (*EcdsaHalConfigT).EcdsaHalGenSignature C.ecdsa_hal_gen_signature +func (recv_ *EcdsaHalConfigT) EcdsaHalGenSignature(hash *c.Uint8T, r_out *c.Uint8T, s_out *c.Uint8T, len c.Uint16T) { +} + +/** + * @brief Verify given ECDSA signature + * + * @param conf Configuration for ECDSA operation, see ``ecdsa_hal_config_t`` + * @param hash Hash that was signed + * @param r `R` component of ECDSA signature + * @param s `S` component of ECDSA signature + * @param pub_x X coordinate of public key + * @param pub_y Y coordinate of public key + * @param len Length of r and s buffer (32 bytes for SECP256R1, 24 for SECP192R1) + * + * @return - 0, if the signature matches + * - -1, if verification fails + */ +// llgo:link (*EcdsaHalConfigT).EcdsaHalVerifySignature C.ecdsa_hal_verify_signature +func (recv_ *EcdsaHalConfigT) EcdsaHalVerifySignature(hash *c.Uint8T, r *c.Uint8T, s *c.Uint8T, pub_x *c.Uint8T, pub_y *c.Uint8T, len c.Uint16T) c.Int { + return 0 +} + +/** + * @brief Check if the ECDSA operation is successful + * + * @return - true, if the ECDSA operation is successful + * - false, if the ECDSA operation fails + */ +//go:linkname EcdsaHalGetOperationResult C.ecdsa_hal_get_operation_result +func EcdsaHalGetOperationResult() bool diff --git a/esp32/ecdsa_types.go b/esp32/ecdsa_types.go new file mode 100644 index 00000000..ef762d39 --- /dev/null +++ b/esp32/ecdsa_types.go @@ -0,0 +1,32 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EcdsaModeT c.Int + +const ( + ECDSA_MODE_SIGN_VERIFY EcdsaModeT = 0 + ECDSA_MODE_SIGN_GEN EcdsaModeT = 1 + ECDSA_MODE_EXPORT_PUBKEY EcdsaModeT = 2 +) + +type EcdsaCurveT c.Int + +const ( + ECDSA_CURVE_SECP192R1 EcdsaCurveT = 0 + ECDSA_CURVE_SECP256R1 EcdsaCurveT = 1 +) + +type EcdsaShaModeT c.Int + +const ( + ECDSA_Z_USE_SHA_PERI EcdsaShaModeT = 0 + ECDSA_Z_USER_PROVIDED EcdsaShaModeT = 1 +) + +type EcdsaSignTypeT c.Int + +const ECDSA_K_TYPE_TRNG EcdsaSignTypeT = 0 diff --git a/esp32/efuse.go b/esp32/efuse.go new file mode 100644 index 00000000..aa8881d3 --- /dev/null +++ b/esp32/efuse.go @@ -0,0 +1,349 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const EFUSE_SPICONFIG_SPI_DEFAULTS = 0 +const EFUSE_SPICONFIG_HSPI_DEFAULTS = 1 +const EFUSE_SPICONFIG_RET_SPICLK_MASK = 0x3f +const EFUSE_SPICONFIG_RET_SPICLK_SHIFT = 0 +const EFUSE_SPICONFIG_RET_SPIQ_MASK = 0x3f +const EFUSE_SPICONFIG_RET_SPIQ_SHIFT = 6 +const EFUSE_SPICONFIG_RET_SPID_MASK = 0x3f +const EFUSE_SPICONFIG_RET_SPID_SHIFT = 12 +const EFUSE_SPICONFIG_RET_SPICS0_MASK = 0x3f +const EFUSE_SPICONFIG_RET_SPICS0_SHIFT = 18 +const EFUSE_SPICONFIG_RET_SPIHD_MASK = 0x3f +const EFUSE_SPICONFIG_RET_SPIHD_SHIFT = 24 + +type EtsEfusePurposeT c.Int + +const ( + ETS_EFUSE_KEY_PURPOSE_USER EtsEfusePurposeT = 0 + ETS_EFUSE_KEY_PURPOSE_RESERVED EtsEfusePurposeT = 1 + ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 EtsEfusePurposeT = 2 + ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 EtsEfusePurposeT = 3 + ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY EtsEfusePurposeT = 4 + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL EtsEfusePurposeT = 5 + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG EtsEfusePurposeT = 6 + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE EtsEfusePurposeT = 7 + ETS_EFUSE_KEY_PURPOSE_HMAC_UP EtsEfusePurposeT = 8 + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 EtsEfusePurposeT = 9 + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 EtsEfusePurposeT = 10 + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 EtsEfusePurposeT = 11 + ETS_EFUSE_KEY_PURPOSE_MAX EtsEfusePurposeT = 12 +) + +type EtsEfuseBlockT c.Int + +const ( + ETS_EFUSE_BLOCK0 EtsEfuseBlockT = 0 + ETS_EFUSE_MAC_SPI_SYS_0 EtsEfuseBlockT = 1 + ETS_EFUSE_BLOCK_SYS_DATA EtsEfuseBlockT = 2 + ETS_EFUSE_BLOCK_USR_DATA EtsEfuseBlockT = 3 + ETS_EFUSE_BLOCK_KEY0 EtsEfuseBlockT = 4 + ETS_EFUSE_BLOCK_KEY1 EtsEfuseBlockT = 5 + ETS_EFUSE_BLOCK_KEY2 EtsEfuseBlockT = 6 + ETS_EFUSE_BLOCK_KEY3 EtsEfuseBlockT = 7 + ETS_EFUSE_BLOCK_KEY4 EtsEfuseBlockT = 8 + ETS_EFUSE_BLOCK_KEY5 EtsEfuseBlockT = 9 + ETS_EFUSE_BLOCK_KEY6 EtsEfuseBlockT = 10 + ETS_EFUSE_BLOCK_MAX EtsEfuseBlockT = 11 +) + +/** + * @brief set timing according the apb clock, so no read error or write error happens. + * + * @param clock: apb clock in HZ, only accept 5M(in FPGA), 10M(in FPGA), 20M, 40M, 80M. + * + * @return : 0 if success, others if clock not accepted + */ +//go:linkname EtsEfuseSetTiming C.ets_efuse_set_timing +func EtsEfuseSetTiming(clock c.Uint32T) c.Int + +/** + * @brief Efuse read operation: copies data from physical efuses to efuse read registers. + * + * @param null + * + * @return : 0 if success, others if apb clock is not accepted + */ +//go:linkname EtsEfuseRead C.ets_efuse_read +func EtsEfuseRead() c.Int + +/** + * @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time. + * + * @note This function does not update read efuses, call ets_efuse_read() once all programming is complete. + * + * @return : 0 if success, others if apb clock is not accepted + */ +// llgo:link EtsEfuseBlockT.EtsEfuseProgram C.ets_efuse_program +func (recv_ EtsEfuseBlockT) EtsEfuseProgram() c.Int { + return 0 +} + +/** + * @brief Set all Efuse program registers to zero. + * + * Call this before writing new data to the program registers. + */ +//go:linkname EtsEfuseClearProgramRegisters C.ets_efuse_clear_program_registers +func EtsEfuseClearProgramRegisters() + +/** + * @brief Program a block of key data to an efuse block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused). + * @param purpose Purpose to set for this key. Purpose must be already unset. + * @param data Pointer to data to write. + * @param data_len Length of data to write. + * + * @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose) + */ +// llgo:link EtsEfuseBlockT.EtsEfuseWriteKey C.ets_efuse_write_key +func (recv_ EtsEfuseBlockT) EtsEfuseWriteKey(purpose EtsEfusePurposeT, data c.Pointer, data_len c.SizeT) c.Int { + return 0 +} + +/* @brief Return the address of a particular efuse block's first read register + * + * @param block Index of efuse block to look up + * + * @return 0 if block is invalid, otherwise a numeric read register address + * of the first word in the block. + */ +// llgo:link EtsEfuseBlockT.EtsEfuseGetReadRegisterAddress C.ets_efuse_get_read_register_address +func (recv_ EtsEfuseBlockT) EtsEfuseGetReadRegisterAddress() c.Uint32T { + return 0 +} + +/** + * @brief Return the current purpose set for an efuse key block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. + */ +// llgo:link EtsEfuseBlockT.EtsEfuseGetKeyPurpose C.ets_efuse_get_key_purpose +func (recv_ EtsEfuseBlockT) EtsEfuseGetKeyPurpose() EtsEfusePurposeT { + return 0 +} + +/** + * @brief Find a key block with the particular purpose set + * + * @param purpose Purpose to search for. + * @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists. + * @return true if found, false if not found. If false, value at key_block pointer is unchanged. + */ +// llgo:link EtsEfusePurposeT.EtsEfuseFindPurpose C.ets_efuse_find_purpose +func (recv_ EtsEfusePurposeT) EtsEfuseFindPurpose(key_block *EtsEfuseBlockT) bool { + return false +} + +/** + * Return true if the key block is unused, false otherwise. + * + * An unused key block is all zero content, not read or write protected, + * and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER) + * + * @param key_block key block to check. + * + * @return true if key block is unused, false if key block or used + * or the specified block index is not a key block. + */ +// llgo:link EtsEfuseBlockT.EtsEfuseKeyBlockUnused C.ets_efuse_key_block_unused +func (recv_ EtsEfuseBlockT) EtsEfuseKeyBlockUnused() bool { + return false +} + +/** + * @brief Search for an unused key block and return the first one found. + * + * See @ref ets_efuse_key_block_unused for a description of an unused key block. + * + * @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found. + */ +//go:linkname EtsEfuseFindUnusedKeyBlock C.ets_efuse_find_unused_key_block +func EtsEfuseFindUnusedKeyBlock() EtsEfuseBlockT + +/** + * @brief Return the number of unused efuse key blocks (0-6) + */ +//go:linkname EtsEfuseCountUnusedKeyBlocks C.ets_efuse_count_unused_key_blocks +func EtsEfuseCountUnusedKeyBlocks() c.Uint + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +//go:linkname EtsEfuseRsCalculate C.ets_efuse_rs_calculate +func EtsEfuseRsCalculate(data c.Pointer, rs_values c.Pointer) + +/** + * @brief Read spi flash pads configuration from Efuse + * + * @return + * - 0 for default SPI pins. + * - 1 for default HSPI pins. + * - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK, + * EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros. + * WP pin (for quad I/O modes) is not saved in efuse and not returned by this function. + */ +//go:linkname EtsEfuseGetSpiconfig C.ets_efuse_get_spiconfig +func EtsEfuseGetSpiconfig() c.Uint32T + +/** + * @brief Read spi flash wp pad from Efuse + * + * @return + * - 0x3f for invalid. + * - 0~46 is valid. + */ +//go:linkname EtsEfuseGetWpPad C.ets_efuse_get_wp_pad +func EtsEfuseGetWpPad() c.Uint32T + +/** + * @brief Read if download mode disabled from Efuse + * + * @return + * - true for efuse disable download mode. + * - false for efuse doesn't disable download mode. + */ +//go:linkname EtsEfuseDownloadModesDisabled C.ets_efuse_download_modes_disabled +func EtsEfuseDownloadModesDisabled() bool + +/** + * @brief Read if legacy spi flash boot mode disabled from Efuse + * + * @return + * - true for efuse disable legacy spi flash boot mode. + * - false for efuse doesn't disable legacy spi flash boot mode. + */ +//go:linkname EtsEfuseLegacySpiBootModeDisabled C.ets_efuse_legacy_spi_boot_mode_disabled +func EtsEfuseLegacySpiBootModeDisabled() bool + +/** + * @brief Read if uart print control value from Efuse + * + * @return + * - 0 for uart force print. + * - 1 for uart print when GPIO46 is low when digital reset. + * 2 for uart print when GPIO46 is high when digital reset. + * 3 for uart force silent + */ +//go:linkname EtsEfuseGetUartPrintControl C.ets_efuse_get_uart_print_control +func EtsEfuseGetUartPrintControl() c.Uint32T + +/** + * @brief Read if USB-Serial-JTAG print during rom boot is disabled from Efuse + * + * @return + * - 1 for efuse disable USB-Serial-JTAG print during rom boot. + * - 0 for efuse doesn't disable USB-Serial-JTAG print during rom boot. + */ +//go:linkname EtsEfuseUsbSerialJtagPrintIsDisabled C.ets_efuse_usb_serial_jtag_print_is_disabled +func EtsEfuseUsbSerialJtagPrintIsDisabled() c.Uint32T + +/** + * @brief Read if usb download mode disabled from Efuse + * + * (Also returns true if security download mode is enabled, as this mode + * disables USB download.) + * + * @return + * - true for efuse disable usb download mode. + * - false for efuse doesn't disable usb download mode. + */ +//go:linkname EtsEfuseUsbDownloadModeDisabled C.ets_efuse_usb_download_mode_disabled +func EtsEfuseUsbDownloadModeDisabled() bool + +/** + * @brief Read if usb module disabled from Efuse + * + * @return + * - true for efuse disable usb module. + * - false for efuse doesn't disable usb module. + */ +//go:linkname EtsEfuseUsbModuleDisabled C.ets_efuse_usb_module_disabled +func EtsEfuseUsbModuleDisabled() bool + +/** + * @brief Read if security download modes enabled from Efuse + * + * @return + * - true for efuse enable security download mode. + * - false for efuse doesn't enable security download mode. + */ +//go:linkname EtsEfuseSecurityDownloadModesEnabled C.ets_efuse_security_download_modes_enabled +func EtsEfuseSecurityDownloadModesEnabled() bool + +/** + * @brief Return true if secure boot is enabled in EFuse + */ +//go:linkname EtsEfuseSecureBootEnabled C.ets_efuse_secure_boot_enabled +func EtsEfuseSecureBootEnabled() bool + +/** + * @brief Return true if secure boot aggressive revoke is enabled in EFuse + */ +//go:linkname EtsEfuseSecureBootAggressiveRevokeEnabled C.ets_efuse_secure_boot_aggressive_revoke_enabled +func EtsEfuseSecureBootAggressiveRevokeEnabled() bool + +/** + * @brief Return true if cache encryption (flash, PSRAM, etc) is enabled from boot via EFuse + */ +//go:linkname EtsEfuseCacheEncryptionEnabled C.ets_efuse_cache_encryption_enabled +func EtsEfuseCacheEncryptionEnabled() bool + +/** + * @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU + */ +//go:linkname EtsEfuseFlashOpi5padsPowerSelVddspi C.ets_efuse_flash_opi_5pads_power_sel_vddspi +func EtsEfuseFlashOpi5padsPowerSelVddspi() bool + +/** + * @brief Return true if EFuse indicates to send a flash resume command. + */ +//go:linkname EtsEfuseForceSendResume C.ets_efuse_force_send_resume +func EtsEfuseForceSendResume() bool + +/** + * @brief return the time in us ROM boot need wait flash to power on from Efuse + * + * @return + * - uint32_t the time in us. + */ +//go:linkname EtsEfuseGetFlashDelayUs C.ets_efuse_get_flash_delay_us +func EtsEfuseGetFlashDelayUs() c.Uint32T + +/** + * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into + * the JTAG_CTRL registers. + * + * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse. + * + * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match. + * + * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user. + * @param key_block Index of a key block containing the source for this key. + * + * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled. + */ +//go:linkname EtsJtagEnableTemporarily C.ets_jtag_enable_temporarily +func EtsJtagEnableTemporarily(jtag_hmac_key *c.Uint8T, key_block EtsEfuseBlockT) c.Int + +/** + * @brief A crc8 algorithm used for MAC addresses in efuse + * + * @param unsigned char const *p : Pointer to original data. + * + * @param unsigned int len : Data length in byte. + * + * @return unsigned char: Crc value. + */ +//go:linkname EspCrc8 C.esp_crc8 +func EspCrc8(p *c.Char, len c.Uint) c.Char diff --git a/esp32/efuse_defs.go b/esp32/efuse_defs.go new file mode 100644 index 00000000..c4794c4e --- /dev/null +++ b/esp32/efuse_defs.go @@ -0,0 +1,14 @@ +package freertos + +import _ "unsafe" + +const EFUSE_WRITE_OP_CODE = 0x5a5a +const EFUSE_READ_OP_CODE = 0x5aa5 +const EFUSE_PKG_VERSION_ESP32S3 = 0 +const EFUSE_PKG_VERSION_ESP32S3PICO = 1 +const EFUSE_SPI_PAD_CONF_1 = 0xFFFFFFFF +const EFUSE_SPI_PAD_CONF_1_V = 0xFFFFFFFF +const EFUSE_SPI_PAD_CONF_1_S = 0 +const EFUSE_SPI_PAD_CONF_2 = 0x0003FFFF +const EFUSE_SPI_PAD_CONF_2_V = 0x3FFFF +const EFUSE_SPI_PAD_CONF_2_S = 0 diff --git a/esp32/efuse_hal.go b/esp32/efuse_hal.go new file mode 100644 index 00000000..e1e41fa8 --- /dev/null +++ b/esp32/efuse_hal.go @@ -0,0 +1,54 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief set eFuse timings + * + * @param apb_freq_hz APB frequency in Hz + */ +//go:linkname EfuseHalSetTiming C.efuse_hal_set_timing +func EfuseHalSetTiming(apb_freq_hz c.Uint32T) + +/** + * @brief trigger eFuse read operation + */ +//go:linkname EfuseHalRead C.efuse_hal_read +func EfuseHalRead() + +/** + * @brief clear registers for programming eFuses + */ +//go:linkname EfuseHalClearProgramRegisters C.efuse_hal_clear_program_registers +func EfuseHalClearProgramRegisters() + +/** + * @brief burn eFuses written in programming registers (one block at once) + * + * @param block block number + */ +//go:linkname EfuseHalProgram C.efuse_hal_program +func EfuseHalProgram(block c.Uint32T) + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +//go:linkname EfuseHalRsCalculate C.efuse_hal_rs_calculate +func EfuseHalRsCalculate(data c.Pointer, rs_values c.Pointer) + +/** + * @brief Checks coding error in a block + * + * @param block Index of efuse block + * + * @return True - block has an error. + * False - no error. + */ +//go:linkname EfuseHalIsCodingErrorInBlock C.efuse_hal_is_coding_error_in_block +func EfuseHalIsCodingErrorInBlock(block c.Uint) bool diff --git a/esp32/efuse_reg.go b/esp32/efuse_reg.go new file mode 100644 index 00000000..3bc89c4e --- /dev/null +++ b/esp32/efuse_reg.go @@ -0,0 +1,331 @@ +package freertos + +import _ "unsafe" + +const EFUSE_PGM_DATA_0_S = 0 +const EFUSE_PGM_DATA_1_S = 0 +const EFUSE_PGM_DATA_2_S = 0 +const EFUSE_PGM_DATA_3_S = 0 +const EFUSE_PGM_DATA_4_S = 0 +const EFUSE_PGM_DATA_5_S = 0 +const EFUSE_PGM_DATA_6_S = 0 +const EFUSE_PGM_DATA_7_S = 0 +const EFUSE_PGM_RS_DATA_0_S = 0 +const EFUSE_PGM_RS_DATA_1_S = 0 +const EFUSE_PGM_RS_DATA_2_S = 0 +const EFUSE_WR_DIS_S = 0 +const EFUSE_RD_DIS_S = 0 +const EFUSE_DIS_RTC_RAM_BOOT_S = 7 +const EFUSE_DIS_ICACHE_S = 8 +const EFUSE_DIS_DCACHE_S = 9 +const EFUSE_DIS_DOWNLOAD_ICACHE_S = 10 +const EFUSE_DIS_DOWNLOAD_DCACHE_S = 11 +const EFUSE_DIS_FORCE_DOWNLOAD_S = 12 +const EFUSE_DIS_USB_OTG_S = 13 +const EFUSE_DIS_TWAI_S = 14 +const EFUSE_DIS_APP_CPU_S = 15 +const EFUSE_SOFT_DIS_JTAG_S = 16 +const EFUSE_DIS_PAD_JTAG_S = 19 +const EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S = 20 +const EFUSE_USB_DREFH_S = 21 +const EFUSE_USB_DREFL_S = 23 +const EFUSE_USB_EXCHG_PINS_S = 25 +const EFUSE_USB_EXT_PHY_ENABLE_S = 26 +const EFUSE_BTLC_GPIO_ENABLE_S = 27 +const EFUSE_VDD_SPI_MODECURLIM_S = 29 +const EFUSE_VDD_SPI_DREFH_S = 30 +const EFUSE_VDD_SPI_DREFM_S = 0 +const EFUSE_VDD_SPI_DREFL_S = 2 +const EFUSE_VDD_SPI_XPD_S = 4 +const EFUSE_VDD_SPI_TIEH_S = 5 +const EFUSE_VDD_SPI_FORCE_S = 6 +const EFUSE_VDD_SPI_EN_INIT_S = 7 +const EFUSE_VDD_SPI_ENCURLIM_S = 8 +const EFUSE_VDD_SPI_DCURLIM_S = 9 +const EFUSE_VDD_SPI_INIT_S = 12 +const EFUSE_VDD_SPI_DCAP_S = 14 +const EFUSE_WDT_DELAY_SEL_S = 16 +const EFUSE_SPI_BOOT_CRYPT_CNT_S = 18 +const EFUSE_SECURE_BOOT_KEY_REVOKE0_S = 21 +const EFUSE_SECURE_BOOT_KEY_REVOKE1_S = 22 +const EFUSE_SECURE_BOOT_KEY_REVOKE2_S = 23 +const EFUSE_KEY_PURPOSE_0_S = 24 +const EFUSE_KEY_PURPOSE_1_S = 28 +const EFUSE_KEY_PURPOSE_2_S = 0 +const EFUSE_KEY_PURPOSE_3_S = 4 +const EFUSE_KEY_PURPOSE_4_S = 8 +const EFUSE_KEY_PURPOSE_5_S = 12 +const EFUSE_RPT4_RESERVED0_S = 16 +const EFUSE_SECURE_BOOT_EN_S = 20 +const EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S = 21 +const EFUSE_DIS_USB_JTAG_S = 22 +const EFUSE_DIS_USB_SERIAL_JTAG_S = 23 +const EFUSE_STRAP_JTAG_SEL_S = 24 +const EFUSE_USB_PHY_SEL_S = 25 +const EFUSE_POWER_GLITCH_DSENSE_S = 26 +const EFUSE_FLASH_TPUW_S = 28 +const EFUSE_DIS_DOWNLOAD_MODE_S = 0 +const EFUSE_DIS_DIRECT_BOOT_S = 1 +const EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S = 2 +const EFUSE_FLASH_ECC_MODE_S = 3 +const EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S = 4 +const EFUSE_ENABLE_SECURITY_DOWNLOAD_S = 5 +const EFUSE_UART_PRINT_CONTROL_S = 6 +const EFUSE_PIN_POWER_SELECTION_S = 8 +const EFUSE_FLASH_TYPE_S = 9 +const EFUSE_FLASH_PAGE_SIZE_S = 10 +const EFUSE_FLASH_ECC_EN_S = 12 +const EFUSE_FORCE_SEND_RESUME_S = 13 +const EFUSE_SECURE_VERSION_S = 14 +const EFUSE_POWERGLITCH_EN_S = 30 +const EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S = 31 +const EFUSE_DISABLE_WAFER_VERSION_MAJOR_S = 0 +const EFUSE_DISABLE_BLK_VERSION_MAJOR_S = 1 +const EFUSE_RESERVED_0_162_S = 2 +const EFUSE_MAC_0_S = 0 +const EFUSE_MAC_1_S = 0 +const EFUSE_SPI_PAD_CONFIG_CLK_S = 16 +const EFUSE_SPI_PAD_CONFIG_Q_S = 22 +const EFUSE_SPI_PAD_CONFIG_D_S = 28 +const EFUSE_SPI_PAD_CONFIG_D_1_S = 0 +const EFUSE_SPI_PAD_CONFIG_CS_S = 2 +const EFUSE_SPI_PAD_CONFIG_HD_S = 8 +const EFUSE_SPI_PAD_CONFIG_WP_S = 14 +const EFUSE_SPI_PAD_CONFIG_DQS_S = 20 +const EFUSE_SPI_PAD_CONFIG_D4_S = 26 +const EFUSE_SPI_PAD_CONFIG_D5_S = 0 +const EFUSE_SPI_PAD_CONFIG_D6_S = 6 +const EFUSE_SPI_PAD_CONFIG_D7_S = 12 +const EFUSE_WAFER_VERSION_MINOR_LO_S = 18 +const EFUSE_PKG_VERSION_S = 21 +const EFUSE_BLK_VERSION_MINOR_S = 24 +const EFUSE_FLASH_CAP_S = 27 +const EFUSE_FLASH_TEMP_S = 30 +const EFUSE_FLASH_VENDOR_S = 0 +const EFUSE_PSRAM_CAP_S = 3 +const EFUSE_PSRAM_TEMP_S = 5 +const EFUSE_PSRAM_VENDOR_S = 7 +const EFUSE_RESERVED_1_137_S = 9 +const EFUSE_K_RTC_LDO_S = 13 +const EFUSE_K_DIG_LDO_S = 20 +const EFUSE_V_RTC_DBIAS20_S = 27 +const EFUSE_V_RTC_DBIAS20_1_S = 0 +const EFUSE_V_DIG_DBIAS20_S = 3 +const EFUSE_DIG_DBIAS_HVT_S = 11 +const EFUSE_RESERVED_1_176_S = 16 +const EFUSE_PSRAM_CAP_3_S = 19 +const EFUSE_RESERVED_1_180_S = 20 +const EFUSE_WAFER_VERSION_MINOR_HI_S = 23 +const EFUSE_WAFER_VERSION_MAJOR_S = 24 +const EFUSE_ADC2_CAL_VOL_ATTEN3_S = 26 +const EFUSE_OPTIONAL_UNIQUE_ID_S = 0 +const EFUSE_OPTIONAL_UNIQUE_ID_1_S = 0 +const EFUSE_OPTIONAL_UNIQUE_ID_2_S = 0 +const EFUSE_OPTIONAL_UNIQUE_ID_3_S = 0 +const EFUSE_BLK_VERSION_MAJOR_S = 0 +const EFUSE_RESERVED_2_130_S = 2 +const EFUSE_TEMP_CALIB_S = 4 +const EFUSE_OCODE_S = 13 +const EFUSE_ADC1_INIT_CODE_ATTEN0_S = 21 +const EFUSE_ADC1_INIT_CODE_ATTEN1_S = 29 +const EFUSE_ADC1_INIT_CODE_ATTEN1_1_S = 0 +const EFUSE_ADC1_INIT_CODE_ATTEN2_S = 3 +const EFUSE_ADC1_INIT_CODE_ATTEN3_S = 9 +const EFUSE_ADC2_INIT_CODE_ATTEN0_S = 15 +const EFUSE_ADC2_INIT_CODE_ATTEN1_S = 23 +const EFUSE_ADC2_INIT_CODE_ATTEN2_S = 29 +const EFUSE_ADC2_INIT_CODE_ATTEN2_1_S = 0 +const EFUSE_ADC2_INIT_CODE_ATTEN3_S = 3 +const EFUSE_ADC1_CAL_VOL_ATTEN0_S = 9 +const EFUSE_ADC1_CAL_VOL_ATTEN1_S = 17 +const EFUSE_ADC1_CAL_VOL_ATTEN2_S = 25 +const EFUSE_ADC1_CAL_VOL_ATTEN2_1_S = 0 +const EFUSE_ADC1_CAL_VOL_ATTEN3_S = 1 +const EFUSE_ADC2_CAL_VOL_ATTEN0_S = 9 +const EFUSE_ADC2_CAL_VOL_ATTEN1_S = 17 +const EFUSE_ADC2_CAL_VOL_ATTEN2_S = 24 +const EFUSE_RESERVED_2_255_S = 31 +const EFUSE_USR_DATA0_S = 0 +const EFUSE_USR_DATA1_S = 0 +const EFUSE_USR_DATA2_S = 0 +const EFUSE_USR_DATA3_S = 0 +const EFUSE_USR_DATA4_S = 0 +const EFUSE_USR_DATA5_S = 0 +const EFUSE_RESERVED_3_192_S = 0 +const EFUSE_CUSTOM_MAC_S = 8 +const EFUSE_CUSTOM_MAC_1_S = 0 +const EFUSE_RESERVED_3_248_S = 24 +const EFUSE_KEY0_DATA0_S = 0 +const EFUSE_KEY0_DATA1_S = 0 +const EFUSE_KEY0_DATA2_S = 0 +const EFUSE_KEY0_DATA3_S = 0 +const EFUSE_KEY0_DATA4_S = 0 +const EFUSE_KEY0_DATA5_S = 0 +const EFUSE_KEY0_DATA6_S = 0 +const EFUSE_KEY0_DATA7_S = 0 +const EFUSE_KEY1_DATA0_S = 0 +const EFUSE_KEY1_DATA1_S = 0 +const EFUSE_KEY1_DATA2_S = 0 +const EFUSE_KEY1_DATA3_S = 0 +const EFUSE_KEY1_DATA4_S = 0 +const EFUSE_KEY1_DATA5_S = 0 +const EFUSE_KEY1_DATA6_S = 0 +const EFUSE_KEY1_DATA7_S = 0 +const EFUSE_KEY2_DATA0_S = 0 +const EFUSE_KEY2_DATA1_S = 0 +const EFUSE_KEY2_DATA2_S = 0 +const EFUSE_KEY2_DATA3_S = 0 +const EFUSE_KEY2_DATA4_S = 0 +const EFUSE_KEY2_DATA5_S = 0 +const EFUSE_KEY2_DATA6_S = 0 +const EFUSE_KEY2_DATA7_S = 0 +const EFUSE_KEY3_DATA0_S = 0 +const EFUSE_KEY3_DATA1_S = 0 +const EFUSE_KEY3_DATA2_S = 0 +const EFUSE_KEY3_DATA3_S = 0 +const EFUSE_KEY3_DATA4_S = 0 +const EFUSE_KEY3_DATA5_S = 0 +const EFUSE_KEY3_DATA6_S = 0 +const EFUSE_KEY3_DATA7_S = 0 +const EFUSE_KEY4_DATA0_S = 0 +const EFUSE_KEY4_DATA1_S = 0 +const EFUSE_KEY4_DATA2_S = 0 +const EFUSE_KEY4_DATA3_S = 0 +const EFUSE_KEY4_DATA4_S = 0 +const EFUSE_KEY4_DATA5_S = 0 +const EFUSE_KEY4_DATA6_S = 0 +const EFUSE_KEY4_DATA7_S = 0 +const EFUSE_KEY5_DATA0_S = 0 +const EFUSE_KEY5_DATA1_S = 0 +const EFUSE_KEY5_DATA2_S = 0 +const EFUSE_KEY5_DATA3_S = 0 +const EFUSE_KEY5_DATA4_S = 0 +const EFUSE_KEY5_DATA5_S = 0 +const EFUSE_KEY5_DATA6_S = 0 +const EFUSE_KEY5_DATA7_S = 0 +const EFUSE_SYS_DATA_PART2_0_S = 0 +const EFUSE_SYS_DATA_PART2_1_S = 0 +const EFUSE_SYS_DATA_PART2_2_S = 0 +const EFUSE_SYS_DATA_PART2_3_S = 0 +const EFUSE_SYS_DATA_PART2_4_S = 0 +const EFUSE_SYS_DATA_PART2_5_S = 0 +const EFUSE_SYS_DATA_PART2_6_S = 0 +const EFUSE_SYS_DATA_PART2_7_S = 0 +const EFUSE_RD_DIS_ERR_S = 0 +const EFUSE_DIS_RTC_RAM_BOOT_ERR_S = 7 +const EFUSE_DIS_ICACHE_ERR_S = 8 +const EFUSE_DIS_DCACHE_ERR_S = 9 +const EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S = 10 +const EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S = 11 +const EFUSE_DIS_FORCE_DOWNLOAD_ERR_S = 12 +const EFUSE_DIS_USB_ERR_S = 13 +const EFUSE_DIS_CAN_ERR_S = 14 +const EFUSE_DIS_APP_CPU_ERR_S = 15 +const EFUSE_SOFT_DIS_JTAG_ERR_S = 16 +const EFUSE_DIS_PAD_JTAG_ERR_S = 19 +const EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S = 20 +const EFUSE_USB_DREFH_ERR_S = 21 +const EFUSE_USB_DREFL_ERR_S = 23 +const EFUSE_USB_EXCHG_PINS_ERR_S = 25 +const EFUSE_EXT_PHY_ENABLE_ERR_S = 26 +const EFUSE_BTLC_GPIO_ENABLE_ERR_S = 27 +const EFUSE_VDD_SPI_MODECURLIM_ERR_S = 29 +const EFUSE_VDD_SPI_DREFH_ERR_S = 30 +const EFUSE_VDD_SPI_DREFM_ERR_S = 0 +const EFUSE_VDD_SPI_DREFL_ERR_S = 2 +const EFUSE_VDD_SPI_XPD_ERR_S = 4 +const EFUSE_VDD_SPI_TIEH_ERR_S = 5 +const EFUSE_VDD_SPI_FORCE_ERR_S = 6 +const EFUSE_VDD_SPI_EN_INIT_ERR_S = 7 +const EFUSE_VDD_SPI_ENCURLIM_ERR_S = 8 +const EFUSE_VDD_SPI_DCURLIM_ERR_S = 9 +const EFUSE_VDD_SPI_INIT_ERR_S = 12 +const EFUSE_VDD_SPI_DCAP_ERR_S = 14 +const EFUSE_WDT_DELAY_SEL_ERR_S = 16 +const EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S = 18 +const EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S = 21 +const EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S = 22 +const EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S = 23 +const EFUSE_KEY_PURPOSE_0_ERR_S = 24 +const EFUSE_KEY_PURPOSE_1_ERR_S = 28 +const EFUSE_KEY_PURPOSE_2_ERR_S = 0 +const EFUSE_KEY_PURPOSE_3_ERR_S = 4 +const EFUSE_KEY_PURPOSE_4_ERR_S = 8 +const EFUSE_KEY_PURPOSE_5_ERR_S = 12 +const EFUSE_RPT4_RESERVED0_ERR_S = 16 +const EFUSE_SECURE_BOOT_EN_ERR_S = 20 +const EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S = 21 +const EFUSE_DIS_USB_JTAG_ERR_S = 22 +const EFUSE_DIS_USB_DEVICE_ERR_S = 23 +const EFUSE_STRAP_JTAG_SEL_ERR_S = 24 +const EFUSE_USB_PHY_SEL_ERR_S = 25 +const EFUSE_POWER_GLITCH_DSENSE_ERR_S = 26 +const EFUSE_FLASH_TPUW_ERR_S = 28 +const EFUSE_DIS_DOWNLOAD_MODE_ERR_S = 0 +const EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S = 1 +const EFUSE_UART_PRINT_CHANNEL_ERR_S = 2 +const EFUSE_FLASH_ECC_MODE_ERR_S = 3 +const EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S = 4 +const EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S = 5 +const EFUSE_UART_PRINT_CONTROL_ERR_S = 6 +const EFUSE_PIN_POWER_SELECTION_ERR_S = 8 +const EFUSE_FLASH_TYPE_ERR_S = 9 +const EFUSE_FLASH_PAGE_SIZE_ERR_S = 10 +const EFUSE_FLASH_ECC_EN_ERR_S = 12 +const EFUSE_FORCE_SEND_RESUME_ERR_S = 13 +const EFUSE_SECURE_VERSION_ERR_S = 14 +const EFUSE_POWERGLITCH_EN_ERR_S = 30 +const EFUSE_RPT4_RESERVED1_ERR_S = 31 +const EFUSE_RPT4_RESERVED2_ERR_S = 0 +const EFUSE_MAC_SPI_8M_ERR_NUM_S = 0 +const EFUSE_MAC_SPI_8M_FAIL_S = 3 +const EFUSE_SYS_PART1_NUM_S = 4 +const EFUSE_SYS_PART1_FAIL_S = 7 +const EFUSE_USR_DATA_ERR_NUM_S = 8 +const EFUSE_USR_DATA_FAIL_S = 11 +const EFUSE_KEY0_ERR_NUM_S = 12 +const EFUSE_KEY0_FAIL_S = 15 +const EFUSE_KEY1_ERR_NUM_S = 16 +const EFUSE_KEY1_FAIL_S = 19 +const EFUSE_KEY2_ERR_NUM_S = 20 +const EFUSE_KEY2_FAIL_S = 23 +const EFUSE_KEY3_ERR_NUM_S = 24 +const EFUSE_KEY3_FAIL_S = 27 +const EFUSE_KEY4_ERR_NUM_S = 28 +const EFUSE_KEY4_FAIL_S = 31 +const EFUSE_KEY5_ERR_NUM_S = 0 +const EFUSE_KEY5_FAIL_S = 3 +const EFUSE_SYS_PART2_ERR_NUM_S = 4 +const EFUSE_SYS_PART2_FAIL_S = 7 +const EFUSE_EFUSE_MEM_FORCE_PD_S = 0 +const EFUSE_MEM_CLK_FORCE_ON_S = 1 +const EFUSE_EFUSE_MEM_FORCE_PU_S = 2 +const EFUSE_CLK_EN_S = 16 +const EFUSE_OP_CODE_S = 0 +const EFUSE_STATE_S = 0 +const EFUSE_OTP_LOAD_SW_S = 4 +const EFUSE_OTP_VDDQ_C_SYNC2_S = 5 +const EFUSE_OTP_STROBE_SW_S = 6 +const EFUSE_OTP_CSB_SW_S = 7 +const EFUSE_OTP_PGENB_SW_S = 8 +const EFUSE_OTP_VDDQ_IS_SW_S = 9 +const EFUSE_REPEAT_ERR_CNT_S = 10 +const EFUSE_READ_CMD_S = 0 +const EFUSE_PGM_CMD_S = 1 +const EFUSE_BLK_NUM_S = 2 +const EFUSE_READ_DONE_INT_RAW_S = 0 +const EFUSE_PGM_DONE_INT_RAW_S = 1 +const EFUSE_READ_DONE_INT_ST_S = 0 +const EFUSE_PGM_DONE_INT_ST_S = 1 +const EFUSE_READ_DONE_INT_ENA_S = 0 +const EFUSE_PGM_DONE_INT_ENA_S = 1 +const EFUSE_READ_DONE_INT_CLR_S = 0 +const EFUSE_PGM_DONE_INT_CLR_S = 1 +const EFUSE_DAC_CLK_DIV_S = 0 +const EFUSE_DAC_CLK_PAD_SEL_S = 8 +const EFUSE_DAC_NUM_S = 9 +const EFUSE_OE_CLR_S = 17 +const EFUSE_READ_INIT_NUM_S = 24 +const EFUSE_PWR_ON_NUM_S = 8 +const EFUSE_PWR_OFF_NUM_S = 0 +const EFUSE_DATE_S = 0 diff --git a/esp32/efuse_struct.go b/esp32/efuse_struct.go new file mode 100644 index 00000000..37b8ce80 --- /dev/null +++ b/esp32/efuse_struct.go @@ -0,0 +1,1054 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** Group: PGM Data Register */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. + */ + +type EfusePgmData0RegT struct { + Val c.Uint32T +} + +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. + */ + +type EfusePgmData1RegT struct { + Val c.Uint32T +} + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ + +type EfusePgmData2RegT struct { + Val c.Uint32T +} + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ + +type EfusePgmData3RegT struct { + Val c.Uint32T +} + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ + +type EfusePgmData4RegT struct { + Val c.Uint32T +} + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ + +type EfusePgmData5RegT struct { + Val c.Uint32T +} + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ + +type EfusePgmData6RegT struct { + Val c.Uint32T +} + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ + +type EfusePgmData7RegT struct { + Val c.Uint32T +} + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ + +type EfusePgmCheckValue0RegT struct { + Val c.Uint32T +} + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ + +type EfusePgmCheckValue1RegT struct { + Val c.Uint32T +} + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ + +type EfusePgmCheckValue2RegT struct { + Val c.Uint32T +} + +/** Group: Read Data Register */ +/** Type of rd_wr_dis register + * BLOCK0 data register 0. + */ + +type EfuseRdWrDisRegT struct { + Val c.Uint32T +} + +/** Type of rd_repeat_data0 register + * BLOCK0 data register 1. + */ + +type EfuseRdRepeatData0RegT struct { + Val c.Uint32T +} + +/** Type of rd_repeat_data1 register + * BLOCK0 data register 2. + */ + +type EfuseRdRepeatData1RegT struct { + Val c.Uint32T +} + +/** Type of rd_repeat_data2 register + * BLOCK0 data register 3. + */ + +type EfuseRdRepeatData2RegT struct { + Val c.Uint32T +} + +/** Type of rd_repeat_data3 register + * BLOCK0 data register 4. + */ + +type EfuseRdRepeatData3RegT struct { + Val c.Uint32T +} + +/** Type of rd_repeat_data4 register + * BLOCK0 data register 5. + */ + +type EfuseRdRepeatData4RegT struct { + Val c.Uint32T +} + +/** Type of rd_mac_spi_sys_0 register + * BLOCK1 data register 0. + */ + +type EfuseRdMacSpiSys0RegT struct { + Val c.Uint32T +} + +/** Type of rd_mac_spi_sys_1 register + * BLOCK1 data register 1. + */ + +type EfuseRdMacSpiSys1RegT struct { + Val c.Uint32T +} + +/** Type of rd_mac_spi_sys_2 register + * BLOCK1 data register 2. + */ + +type EfuseRdMacSpiSys2RegT struct { + Val c.Uint32T +} + +/** Type of rd_mac_spi_sys_3 register + * BLOCK1 data register 3. + */ + +type EfuseRdMacSpiSys3RegT struct { + Val c.Uint32T +} + +/** Type of rd_mac_spi_sys_4 register + * BLOCK1 data register 4. + */ + +type EfuseRdMacSpiSys4RegT struct { + Val c.Uint32T +} + +/** Type of rd_mac_spi_sys_5 register + * BLOCK1 data register 5. + */ + +type EfuseRdMacSpiSys5RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part1_data0 register + * Register 0 of BLOCK2 (system). + */ + +type EfuseRdSysPart1Data0RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part1_data1 register + * Register 1 of BLOCK2 (system). + */ + +type EfuseRdSysPart1Data1RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part1_data2 register + * Register 2 of BLOCK2 (system). + */ + +type EfuseRdSysPart1Data2RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part1_data3 register + * Register 3 of BLOCK2 (system). + */ + +type EfuseRdSysPart1Data3RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part1_data4 register + * Register 4 of BLOCK2 (system). + */ + +type EfuseRdSysPart1Data4RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part1_data5 register + * Register 5 of BLOCK2 (system). + */ + +type EfuseRdSysPart1Data5RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part1_data6 register + * Register 6 of BLOCK2 (system). + */ + +type EfuseRdSysPart1Data6RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part1_data7 register + * Register 7 of BLOCK2 (system). + */ + +type EfuseRdSysPart1Data7RegT struct { + Val c.Uint32T +} + +/** Type of rd_usr_data0 register + * Register 0 of BLOCK3 (user). + */ + +type EfuseRdUsrData0RegT struct { + Val c.Uint32T +} + +/** Type of rd_usr_data1 register + * Register 1 of BLOCK3 (user). + */ + +type EfuseRdUsrData1RegT struct { + Val c.Uint32T +} + +/** Type of rd_usr_data2 register + * Register 2 of BLOCK3 (user). + */ + +type EfuseRdUsrData2RegT struct { + Val c.Uint32T +} + +/** Type of rd_usr_data3 register + * Register 3 of BLOCK3 (user). + */ + +type EfuseRdUsrData3RegT struct { + Val c.Uint32T +} + +/** Type of rd_usr_data4 register + * Register 4 of BLOCK3 (user). + */ + +type EfuseRdUsrData4RegT struct { + Val c.Uint32T +} + +/** Type of rd_usr_data5 register + * Register 5 of BLOCK3 (user). + */ + +type EfuseRdUsrData5RegT struct { + Val c.Uint32T +} + +/** Type of rd_usr_data6 register + * Register 6 of BLOCK3 (user). + */ + +type EfuseRdUsrData6RegT struct { + Val c.Uint32T +} + +/** Type of rd_usr_data7 register + * Register 7 of BLOCK3 (user). + */ + +type EfuseRdUsrData7RegT struct { + Val c.Uint32T +} + +/** Type of rd_key0_data0 register + * Register 0 of BLOCK4 (KEY0). + */ + +type EfuseRdKey0Data0RegT struct { + Val c.Uint32T +} + +/** Type of rd_key0_data1 register + * Register 1 of BLOCK4 (KEY0). + */ + +type EfuseRdKey0Data1RegT struct { + Val c.Uint32T +} + +/** Type of rd_key0_data2 register + * Register 2 of BLOCK4 (KEY0). + */ + +type EfuseRdKey0Data2RegT struct { + Val c.Uint32T +} + +/** Type of rd_key0_data3 register + * Register 3 of BLOCK4 (KEY0). + */ + +type EfuseRdKey0Data3RegT struct { + Val c.Uint32T +} + +/** Type of rd_key0_data4 register + * Register 4 of BLOCK4 (KEY0). + */ + +type EfuseRdKey0Data4RegT struct { + Val c.Uint32T +} + +/** Type of rd_key0_data5 register + * Register 5 of BLOCK4 (KEY0). + */ + +type EfuseRdKey0Data5RegT struct { + Val c.Uint32T +} + +/** Type of rd_key0_data6 register + * Register 6 of BLOCK4 (KEY0). + */ + +type EfuseRdKey0Data6RegT struct { + Val c.Uint32T +} + +/** Type of rd_key0_data7 register + * Register 7 of BLOCK4 (KEY0). + */ + +type EfuseRdKey0Data7RegT struct { + Val c.Uint32T +} + +/** Type of rd_key1_data0 register + * Register 0 of BLOCK5 (KEY1). + */ + +type EfuseRdKey1Data0RegT struct { + Val c.Uint32T +} + +/** Type of rd_key1_data1 register + * Register 1 of BLOCK5 (KEY1). + */ + +type EfuseRdKey1Data1RegT struct { + Val c.Uint32T +} + +/** Type of rd_key1_data2 register + * Register 2 of BLOCK5 (KEY1). + */ + +type EfuseRdKey1Data2RegT struct { + Val c.Uint32T +} + +/** Type of rd_key1_data3 register + * Register 3 of BLOCK5 (KEY1). + */ + +type EfuseRdKey1Data3RegT struct { + Val c.Uint32T +} + +/** Type of rd_key1_data4 register + * Register 4 of BLOCK5 (KEY1). + */ + +type EfuseRdKey1Data4RegT struct { + Val c.Uint32T +} + +/** Type of rd_key1_data5 register + * Register 5 of BLOCK5 (KEY1). + */ + +type EfuseRdKey1Data5RegT struct { + Val c.Uint32T +} + +/** Type of rd_key1_data6 register + * Register 6 of BLOCK5 (KEY1). + */ + +type EfuseRdKey1Data6RegT struct { + Val c.Uint32T +} + +/** Type of rd_key1_data7 register + * Register 7 of BLOCK5 (KEY1). + */ + +type EfuseRdKey1Data7RegT struct { + Val c.Uint32T +} + +/** Type of rd_key2_data0 register + * Register 0 of BLOCK6 (KEY2). + */ + +type EfuseRdKey2Data0RegT struct { + Val c.Uint32T +} + +/** Type of rd_key2_data1 register + * Register 1 of BLOCK6 (KEY2). + */ + +type EfuseRdKey2Data1RegT struct { + Val c.Uint32T +} + +/** Type of rd_key2_data2 register + * Register 2 of BLOCK6 (KEY2). + */ + +type EfuseRdKey2Data2RegT struct { + Val c.Uint32T +} + +/** Type of rd_key2_data3 register + * Register 3 of BLOCK6 (KEY2). + */ + +type EfuseRdKey2Data3RegT struct { + Val c.Uint32T +} + +/** Type of rd_key2_data4 register + * Register 4 of BLOCK6 (KEY2). + */ + +type EfuseRdKey2Data4RegT struct { + Val c.Uint32T +} + +/** Type of rd_key2_data5 register + * Register 5 of BLOCK6 (KEY2). + */ + +type EfuseRdKey2Data5RegT struct { + Val c.Uint32T +} + +/** Type of rd_key2_data6 register + * Register 6 of BLOCK6 (KEY2). + */ + +type EfuseRdKey2Data6RegT struct { + Val c.Uint32T +} + +/** Type of rd_key2_data7 register + * Register 7 of BLOCK6 (KEY2). + */ + +type EfuseRdKey2Data7RegT struct { + Val c.Uint32T +} + +/** Type of rd_key3_data0 register + * Register 0 of BLOCK7 (KEY3). + */ + +type EfuseRdKey3Data0RegT struct { + Val c.Uint32T +} + +/** Type of rd_key3_data1 register + * Register 1 of BLOCK7 (KEY3). + */ + +type EfuseRdKey3Data1RegT struct { + Val c.Uint32T +} + +/** Type of rd_key3_data2 register + * Register 2 of BLOCK7 (KEY3). + */ + +type EfuseRdKey3Data2RegT struct { + Val c.Uint32T +} + +/** Type of rd_key3_data3 register + * Register 3 of BLOCK7 (KEY3). + */ + +type EfuseRdKey3Data3RegT struct { + Val c.Uint32T +} + +/** Type of rd_key3_data4 register + * Register 4 of BLOCK7 (KEY3). + */ + +type EfuseRdKey3Data4RegT struct { + Val c.Uint32T +} + +/** Type of rd_key3_data5 register + * Register 5 of BLOCK7 (KEY3). + */ + +type EfuseRdKey3Data5RegT struct { + Val c.Uint32T +} + +/** Type of rd_key3_data6 register + * Register 6 of BLOCK7 (KEY3). + */ + +type EfuseRdKey3Data6RegT struct { + Val c.Uint32T +} + +/** Type of rd_key3_data7 register + * Register 7 of BLOCK7 (KEY3). + */ + +type EfuseRdKey3Data7RegT struct { + Val c.Uint32T +} + +/** Type of rd_key4_data0 register + * Register 0 of BLOCK8 (KEY4). + */ + +type EfuseRdKey4Data0RegT struct { + Val c.Uint32T +} + +/** Type of rd_key4_data1 register + * Register 1 of BLOCK8 (KEY4). + */ + +type EfuseRdKey4Data1RegT struct { + Val c.Uint32T +} + +/** Type of rd_key4_data2 register + * Register 2 of BLOCK8 (KEY4). + */ + +type EfuseRdKey4Data2RegT struct { + Val c.Uint32T +} + +/** Type of rd_key4_data3 register + * Register 3 of BLOCK8 (KEY4). + */ + +type EfuseRdKey4Data3RegT struct { + Val c.Uint32T +} + +/** Type of rd_key4_data4 register + * Register 4 of BLOCK8 (KEY4). + */ + +type EfuseRdKey4Data4RegT struct { + Val c.Uint32T +} + +/** Type of rd_key4_data5 register + * Register 5 of BLOCK8 (KEY4). + */ + +type EfuseRdKey4Data5RegT struct { + Val c.Uint32T +} + +/** Type of rd_key4_data6 register + * Register 6 of BLOCK8 (KEY4). + */ + +type EfuseRdKey4Data6RegT struct { + Val c.Uint32T +} + +/** Type of rd_key4_data7 register + * Register 7 of BLOCK8 (KEY4). + */ + +type EfuseRdKey4Data7RegT struct { + Val c.Uint32T +} + +/** Type of rd_key5_data0 register + * Register 0 of BLOCK9 (KEY5). + */ + +type EfuseRdKey5Data0RegT struct { + Val c.Uint32T +} + +/** Type of rd_key5_data1 register + * Register 1 of BLOCK9 (KEY5). + */ + +type EfuseRdKey5Data1RegT struct { + Val c.Uint32T +} + +/** Type of rd_key5_data2 register + * Register 2 of BLOCK9 (KEY5). + */ + +type EfuseRdKey5Data2RegT struct { + Val c.Uint32T +} + +/** Type of rd_key5_data3 register + * Register 3 of BLOCK9 (KEY5). + */ + +type EfuseRdKey5Data3RegT struct { + Val c.Uint32T +} + +/** Type of rd_key5_data4 register + * Register 4 of BLOCK9 (KEY5). + */ + +type EfuseRdKey5Data4RegT struct { + Val c.Uint32T +} + +/** Type of rd_key5_data5 register + * Register 5 of BLOCK9 (KEY5). + */ + +type EfuseRdKey5Data5RegT struct { + Val c.Uint32T +} + +/** Type of rd_key5_data6 register + * Register 6 of BLOCK9 (KEY5). + */ + +type EfuseRdKey5Data6RegT struct { + Val c.Uint32T +} + +/** Type of rd_key5_data7 register + * Register 7 of BLOCK9 (KEY5). + */ + +type EfuseRdKey5Data7RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part2_data0 register + * Register 0 of BLOCK10 (system). + */ + +type EfuseRdSysPart2Data0RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part2_data1 register + * Register 1 of BLOCK9 (KEY5). + */ + +type EfuseRdSysPart2Data1RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part2_data2 register + * Register 2 of BLOCK10 (system). + */ + +type EfuseRdSysPart2Data2RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part2_data3 register + * Register 3 of BLOCK10 (system). + */ + +type EfuseRdSysPart2Data3RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part2_data4 register + * Register 4 of BLOCK10 (system). + */ + +type EfuseRdSysPart2Data4RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part2_data5 register + * Register 5 of BLOCK10 (system). + */ + +type EfuseRdSysPart2Data5RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part2_data6 register + * Register 6 of BLOCK10 (system). + */ + +type EfuseRdSysPart2Data6RegT struct { + Val c.Uint32T +} + +/** Type of rd_sys_part2_data7 register + * Register 7 of BLOCK10 (system). + */ + +type EfuseRdSysPart2Data7RegT struct { + Val c.Uint32T +} + +/** Group: Report Register */ +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. + */ + +type EfuseRdRepeatErr0RegT struct { + Val c.Uint32T +} + +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. + */ + +type EfuseRdRepeatErr1RegT struct { + Val c.Uint32T +} + +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. + */ + +type EfuseRdRepeatErr2RegT struct { + Val c.Uint32T +} + +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. + */ + +type EfuseRdRepeatErr3RegT struct { + Val c.Uint32T +} + +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. + */ + +type EfuseRdRepeatErr4RegT struct { + Val c.Uint32T +} + +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. + */ + +type EfuseRdRsErr0RegT struct { + Val c.Uint32T +} + +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. + */ + +type EfuseRdRsErr1RegT struct { + Val c.Uint32T +} + +/** Group: Configuration Register */ +/** Type of clk register + * eFuse clcok configuration register. + */ + +type EfuseClkRegT struct { + Val c.Uint32T +} + +/** Type of conf register + * eFuse operation mode configuration register + */ + +type EfuseConfRegT struct { + Val c.Uint32T +} + +/** Type of cmd register + * eFuse command register. + */ + +type EfuseCmdRegT struct { + Val c.Uint32T +} + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ + +type EfuseDacConfRegT struct { + Val c.Uint32T +} + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ + +type EfuseRdTimConfRegT struct { + Val c.Uint32T +} + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ + +type EfuseWrTimConf1RegT struct { + Val c.Uint32T +} + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ + +type EfuseWrTimConf2RegT struct { + Val c.Uint32T +} + +/** Group: Status Register */ +/** Type of status register + * eFuse status register. + */ + +type EfuseStatusRegT struct { + Val c.Uint32T +} + +/** Group: Interrupt Register */ +/** Type of int_raw register + * eFuse raw interrupt register. + */ + +type EfuseIntRawRegT struct { + Val c.Uint32T +} + +/** Type of int_st register + * eFuse interrupt status register. + */ + +type EfuseIntStRegT struct { + Val c.Uint32T +} + +/** Type of int_ena register + * eFuse interrupt enable register. + */ + +type EfuseIntEnaRegT struct { + Val c.Uint32T +} + +/** Type of int_clr register + * eFuse interrupt clear register. + */ + +type EfuseIntClrRegT struct { + Val c.Uint32T +} + +/** Group: Version Register */ +/** Type of date register + * eFuse version register. + */ + +type EfuseDateRegT struct { + Val c.Uint32T +} + +type EfuseDevT struct { + PgmData0 EfusePgmData0RegT + PgmData1 EfusePgmData1RegT + PgmData2 EfusePgmData2RegT + PgmData3 EfusePgmData3RegT + PgmData4 EfusePgmData4RegT + PgmData5 EfusePgmData5RegT + PgmData6 EfusePgmData6RegT + PgmData7 EfusePgmData7RegT + PgmCheckValue0 EfusePgmCheckValue0RegT + PgmCheckValue1 EfusePgmCheckValue1RegT + PgmCheckValue2 EfusePgmCheckValue2RegT + RdWrDis EfuseRdWrDisRegT + RdRepeatData0 EfuseRdRepeatData0RegT + RdRepeatData1 EfuseRdRepeatData1RegT + RdRepeatData2 EfuseRdRepeatData2RegT + RdRepeatData3 EfuseRdRepeatData3RegT + RdRepeatData4 EfuseRdRepeatData4RegT + RdMacSpiSys0 EfuseRdMacSpiSys0RegT + RdMacSpiSys1 EfuseRdMacSpiSys1RegT + RdMacSpiSys2 EfuseRdMacSpiSys2RegT + RdMacSpiSys3 EfuseRdMacSpiSys3RegT + RdMacSpiSys4 EfuseRdMacSpiSys4RegT + RdMacSpiSys5 EfuseRdMacSpiSys5RegT + RdSysPart1Data0 EfuseRdSysPart1Data0RegT + RdSysPart1Data1 EfuseRdSysPart1Data1RegT + RdSysPart1Data2 EfuseRdSysPart1Data2RegT + RdSysPart1Data3 EfuseRdSysPart1Data3RegT + RdSysPart1Data4 EfuseRdSysPart1Data4RegT + RdSysPart1Data5 EfuseRdSysPart1Data5RegT + RdSysPart1Data6 EfuseRdSysPart1Data6RegT + RdSysPart1Data7 EfuseRdSysPart1Data7RegT + RdUsrData0 EfuseRdUsrData0RegT + RdUsrData1 EfuseRdUsrData1RegT + RdUsrData2 EfuseRdUsrData2RegT + RdUsrData3 EfuseRdUsrData3RegT + RdUsrData4 EfuseRdUsrData4RegT + RdUsrData5 EfuseRdUsrData5RegT + RdUsrData6 EfuseRdUsrData6RegT + RdUsrData7 EfuseRdUsrData7RegT + RdKey0Data0 EfuseRdKey0Data0RegT + RdKey0Data1 EfuseRdKey0Data1RegT + RdKey0Data2 EfuseRdKey0Data2RegT + RdKey0Data3 EfuseRdKey0Data3RegT + RdKey0Data4 EfuseRdKey0Data4RegT + RdKey0Data5 EfuseRdKey0Data5RegT + RdKey0Data6 EfuseRdKey0Data6RegT + RdKey0Data7 EfuseRdKey0Data7RegT + RdKey1Data0 EfuseRdKey1Data0RegT + RdKey1Data1 EfuseRdKey1Data1RegT + RdKey1Data2 EfuseRdKey1Data2RegT + RdKey1Data3 EfuseRdKey1Data3RegT + RdKey1Data4 EfuseRdKey1Data4RegT + RdKey1Data5 EfuseRdKey1Data5RegT + RdKey1Data6 EfuseRdKey1Data6RegT + RdKey1Data7 EfuseRdKey1Data7RegT + RdKey2Data0 EfuseRdKey2Data0RegT + RdKey2Data1 EfuseRdKey2Data1RegT + RdKey2Data2 EfuseRdKey2Data2RegT + RdKey2Data3 EfuseRdKey2Data3RegT + RdKey2Data4 EfuseRdKey2Data4RegT + RdKey2Data5 EfuseRdKey2Data5RegT + RdKey2Data6 EfuseRdKey2Data6RegT + RdKey2Data7 EfuseRdKey2Data7RegT + RdKey3Data0 EfuseRdKey3Data0RegT + RdKey3Data1 EfuseRdKey3Data1RegT + RdKey3Data2 EfuseRdKey3Data2RegT + RdKey3Data3 EfuseRdKey3Data3RegT + RdKey3Data4 EfuseRdKey3Data4RegT + RdKey3Data5 EfuseRdKey3Data5RegT + RdKey3Data6 EfuseRdKey3Data6RegT + RdKey3Data7 EfuseRdKey3Data7RegT + RdKey4Data0 EfuseRdKey4Data0RegT + RdKey4Data1 EfuseRdKey4Data1RegT + RdKey4Data2 EfuseRdKey4Data2RegT + RdKey4Data3 EfuseRdKey4Data3RegT + RdKey4Data4 EfuseRdKey4Data4RegT + RdKey4Data5 EfuseRdKey4Data5RegT + RdKey4Data6 EfuseRdKey4Data6RegT + RdKey4Data7 EfuseRdKey4Data7RegT + RdKey5Data0 EfuseRdKey5Data0RegT + RdKey5Data1 EfuseRdKey5Data1RegT + RdKey5Data2 EfuseRdKey5Data2RegT + RdKey5Data3 EfuseRdKey5Data3RegT + RdKey5Data4 EfuseRdKey5Data4RegT + RdKey5Data5 EfuseRdKey5Data5RegT + RdKey5Data6 EfuseRdKey5Data6RegT + RdKey5Data7 EfuseRdKey5Data7RegT + RdSysPart2Data0 EfuseRdSysPart2Data0RegT + RdSysPart2Data1 EfuseRdSysPart2Data1RegT + RdSysPart2Data2 EfuseRdSysPart2Data2RegT + RdSysPart2Data3 EfuseRdSysPart2Data3RegT + RdSysPart2Data4 EfuseRdSysPart2Data4RegT + RdSysPart2Data5 EfuseRdSysPart2Data5RegT + RdSysPart2Data6 EfuseRdSysPart2Data6RegT + RdSysPart2Data7 EfuseRdSysPart2Data7RegT + RdRepeatErr0 EfuseRdRepeatErr0RegT + RdRepeatErr1 EfuseRdRepeatErr1RegT + RdRepeatErr2 EfuseRdRepeatErr2RegT + RdRepeatErr3 EfuseRdRepeatErr3RegT + Reserved18c c.Uint32T + RdRepeatErr4 EfuseRdRepeatErr4RegT + Reserved194 [11]c.Uint32T + RdRsErr0 EfuseRdRsErr0RegT + RdRsErr1 EfuseRdRsErr1RegT + Clk EfuseClkRegT + Conf EfuseConfRegT + Status EfuseStatusRegT + Cmd EfuseCmdRegT + IntRaw EfuseIntRawRegT + IntSt EfuseIntStRegT + IntEna EfuseIntEnaRegT + IntClr EfuseIntClrRegT + DacConf EfuseDacConfRegT + RdTimConf EfuseRdTimConfRegT + Reserved1f0 c.Uint32T + WrTimConf1 EfuseWrTimConf1RegT + WrTimConf2 EfuseWrTimConf2RegT + Date EfuseDateRegT +} diff --git a/esp32/eh_frame_parser.go b/esp32/eh_frame_parser.go new file mode 100644 index 00000000..8ee41f05 --- /dev/null +++ b/esp32/eh_frame_parser.go @@ -0,0 +1,16 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Print backtrace for the given execution frame. + * + * @param frame_or Snapshot of the CPU registers when the program stopped its + * normal execution. This frame is usually generated on the + * stack when an exception or an interrupt occurs. + */ +//go:linkname EspEhFramePrintBacktrace C.esp_eh_frame_print_backtrace +func EspEhFramePrintBacktrace(frame_or c.Pointer) diff --git a/esp32/eri.go b/esp32/eri.go new file mode 100644 index 00000000..dafc119f --- /dev/null +++ b/esp32/eri.go @@ -0,0 +1,16 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Perform an ERI write + * @param addr : ERI register to write to + * @param data : Value to write + * + * @return Value read + */ +//go:linkname EriWrite C.eri_write +func EriWrite(addr c.Int, data c.Uint32T) diff --git a/esp32/esp_assert.go b/esp32/esp_assert.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/esp_assert.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/esp_async_memcpy.go b/esp32/esp_async_memcpy.go new file mode 100644 index 00000000..678c2975 --- /dev/null +++ b/esp32/esp_async_memcpy.go @@ -0,0 +1,99 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type AsyncMemcpyContextT struct { + Unused [8]uint8 +} +type AsyncMemcpyHandleT *AsyncMemcpyContextT +type AsyncMemcpyT AsyncMemcpyHandleT + +/** + * @brief Async memory copy event data + */ + +type AsyncMemcpyEventT struct { + Data c.Pointer +} + +// llgo:type C +type AsyncMemcpyIsrCbT func(AsyncMemcpyHandleT, *AsyncMemcpyEventT, c.Pointer) bool + +/** + * @brief Type of async memcpy configuration + */ + +type AsyncMemcpyConfigT struct { + Backlog c.Uint32T + SramTransAlign c.SizeT + Flags c.Uint32T +} + +/** + * @brief Install async memcpy driver, with AHB-GDMA as the backend + * + * @param[in] config Configuration of async memcpy + * @param[out] mcp Returned driver handle + * @return + * - ESP_OK: Install async memcpy driver successfully + * - ESP_ERR_INVALID_ARG: Install async memcpy driver failed because of invalid argument + * - ESP_ERR_NO_MEM: Install async memcpy driver failed because out of memory + * - ESP_FAIL: Install async memcpy driver failed because of other error + */ +// llgo:link (*AsyncMemcpyConfigT).EspAsyncMemcpyInstallGdmaAhb C.esp_async_memcpy_install_gdma_ahb +func (recv_ *AsyncMemcpyConfigT) EspAsyncMemcpyInstallGdmaAhb(mcp *AsyncMemcpyHandleT) EspErrT { + return 0 +} + +/** + * @brief Install async memcpy driver with the default DMA backend + * + * @note On chip with CPDMA support, CPDMA is the default choice. + * On chip with AHB-GDMA support, AHB-GDMA is the default choice. + * + * @param[in] config Configuration of async memcpy + * @param[out] mcp Returned driver handle + * @return + * - ESP_OK: Install async memcpy driver successfully + * - ESP_ERR_INVALID_ARG: Install async memcpy driver failed because of invalid argument + * - ESP_ERR_NO_MEM: Install async memcpy driver failed because out of memory + * - ESP_FAIL: Install async memcpy driver failed because of other error + */ +// llgo:link (*AsyncMemcpyConfigT).EspAsyncMemcpyInstall C.esp_async_memcpy_install +func (recv_ *AsyncMemcpyConfigT) EspAsyncMemcpyInstall(mcp *AsyncMemcpyHandleT) EspErrT { + return 0 +} + +/** + * @brief Uninstall async memcpy driver + * + * @param[in] mcp Handle of async memcpy driver that returned from `esp_async_memcpy_install` + * @return + * - ESP_OK: Uninstall async memcpy driver successfully + * - ESP_ERR_INVALID_ARG: Uninstall async memcpy driver failed because of invalid argument + * - ESP_FAIL: Uninstall async memcpy driver failed because of other error + */ +//go:linkname EspAsyncMemcpyUninstall C.esp_async_memcpy_uninstall +func EspAsyncMemcpyUninstall(mcp AsyncMemcpyHandleT) EspErrT + +/** + * @brief Send an asynchronous memory copy request + * + * @note The callback function is invoked in interrupt context, never do blocking jobs in the callback. + * + * @param[in] mcp Handle of async memcpy driver that returned from `esp_async_memcpy_install` + * @param[in] dst Destination address (copy to) + * @param[in] src Source address (copy from) + * @param[in] n Number of bytes to copy + * @param[in] cb_isr Callback function, which got invoked in interrupt context. Set to NULL can bypass the callback. + * @param[in] cb_args User defined argument to be passed to the callback function + * @return + * - ESP_OK: Send memory copy request successfully + * - ESP_ERR_INVALID_ARG: Send memory copy request failed because of invalid argument + * - ESP_FAIL: Send memory copy request failed because of other error + */ +//go:linkname EspAsyncMemcpy C.esp_async_memcpy +func EspAsyncMemcpy(mcp AsyncMemcpyHandleT, dst c.Pointer, src c.Pointer, n c.SizeT, cb_isr AsyncMemcpyIsrCbT, cb_args c.Pointer) EspErrT diff --git a/esp32/esp_attr.go b/esp32/esp_attr.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/esp_attr.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/esp_bit_defs.go b/esp32/esp_bit_defs.go new file mode 100644 index 00000000..71cf1f9e --- /dev/null +++ b/esp32/esp_bit_defs.go @@ -0,0 +1,36 @@ +package freertos + +import _ "unsafe" + +const BIT31 = 0x80000000 +const BIT30 = 0x40000000 +const BIT29 = 0x20000000 +const BIT28 = 0x10000000 +const BIT27 = 0x08000000 +const BIT26 = 0x04000000 +const BIT25 = 0x02000000 +const BIT24 = 0x01000000 +const BIT23 = 0x00800000 +const BIT22 = 0x00400000 +const BIT21 = 0x00200000 +const BIT20 = 0x00100000 +const BIT19 = 0x00080000 +const BIT18 = 0x00040000 +const BIT17 = 0x00020000 +const BIT16 = 0x00010000 +const BIT15 = 0x00008000 +const BIT14 = 0x00004000 +const BIT13 = 0x00002000 +const BIT12 = 0x00001000 +const BIT11 = 0x00000800 +const BIT10 = 0x00000400 +const BIT9 = 0x00000200 +const BIT8 = 0x00000100 +const BIT7 = 0x00000080 +const BIT6 = 0x00000040 +const BIT5 = 0x00000020 +const BIT4 = 0x00000010 +const BIT3 = 0x00000008 +const BIT2 = 0x00000004 +const BIT1 = 0x00000002 +const BIT0 = 0x00000001 diff --git a/esp32/esp_check.go b/esp32/esp_check.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/esp_check.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/esp_chip_info.go b/esp32/esp_chip_info.go new file mode 100644 index 00000000..97158096 --- /dev/null +++ b/esp32/esp_chip_info.go @@ -0,0 +1,41 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EspChipModelT c.Int + +const ( + CHIP_ESP32 EspChipModelT = 1 + CHIP_ESP32S2 EspChipModelT = 2 + CHIP_ESP32S3 EspChipModelT = 9 + CHIP_ESP32C3 EspChipModelT = 5 + CHIP_ESP32C2 EspChipModelT = 12 + CHIP_ESP32C6 EspChipModelT = 13 + CHIP_ESP32H2 EspChipModelT = 16 + CHIP_ESP32P4 EspChipModelT = 18 + CHIP_ESP32C61 EspChipModelT = 20 + CHIP_ESP32C5 EspChipModelT = 23 + CHIP_POSIX_LINUX EspChipModelT = 999 +) + +/** + * @brief The structure represents information about the chip + */ + +type EspChipInfoT struct { + Model EspChipModelT + Features c.Uint32T + Revision c.Uint16T + Cores c.Uint8T +} + +/** + * @brief Fill an esp_chip_info_t structure with information about the chip + * @param[out] out_info structure to be filled + */ +// llgo:link (*EspChipInfoT).EspChipInfo C.esp_chip_info +func (recv_ *EspChipInfoT) EspChipInfo() { +} diff --git a/esp32/esp_clk.go b/esp32/esp_clk.go new file mode 100644 index 00000000..0698096b --- /dev/null +++ b/esp32/esp_clk.go @@ -0,0 +1,91 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Get the calibration value of RTC slow clock + * + * The value is in the same format as returned by rtc_clk_cal (microseconds, + * in Q13.19 fixed-point format). + * + * @return the calibration value obtained using rtc_clk_cal, at startup time + */ +//go:linkname EspClkSlowclkCalGet C.esp_clk_slowclk_cal_get +func EspClkSlowclkCalGet() c.Uint32T + +/** + * @brief Update the calibration value of RTC slow clock + * + * The value has to be in the same format as returned by rtc_clk_cal (microseconds, + * in Q13.19 fixed-point format). + * This value is used by timekeeping functions (such as gettimeofday) to + * calculate current time based on RTC counter value. + * @param value calibration value obtained using rtc_clk_cal + */ +//go:linkname EspClkSlowclkCalSet C.esp_clk_slowclk_cal_set +func EspClkSlowclkCalSet(value c.Uint32T) + +/** + * @brief Return current CPU clock frequency + * When frequency switching is performed, this frequency may change. + * However it is guaranteed that the frequency never changes with a critical + * section. + * + * @return CPU clock frequency, in Hz + */ +//go:linkname EspClkCpuFreq C.esp_clk_cpu_freq +func EspClkCpuFreq() c.Int + +/** + * @brief Return current APB clock frequency + * + * When frequency switching is performed, this frequency may change. + * However it is guaranteed that the frequency never changes with a critical + * section. + * + * @return APB clock frequency, in Hz + */ +//go:linkname EspClkApbFreq C.esp_clk_apb_freq +func EspClkApbFreq() c.Int + +/** + * @brief Return frequency of the main XTAL + * + * Frequency of the main XTAL can be either auto-detected or set at compile + * time (see CONFIG_XTAL_FREQ_SEL sdkconfig option). In both cases, this + * function returns the actual value at run time. + * + * @return XTAL frequency, in Hz + */ +//go:linkname EspClkXtalFreq C.esp_clk_xtal_freq +func EspClkXtalFreq() c.Int + +/** + * @brief Read value of RTC counter, converting it to microseconds + * @attention The value returned by this function may change abruptly when + * calibration value of RTC counter is updated via esp_clk_slowclk_cal_set + * function. This should not happen unless application calls esp_clk_slowclk_cal_set. + * In ESP-IDF, esp_clk_slowclk_cal_set is only called in startup code. + * + * @return Value or RTC counter, expressed in microseconds + */ +//go:linkname EspClkRtcTime C.esp_clk_rtc_time +func EspClkRtcTime() c.Uint64T + +/** + * @brief obtain internal critical section used esp_clk implementation. + * + * This is used by the esp_light_sleep_start() to avoid deadlocking when it + * calls esp_clk related API after stalling the other CPU. + */ +//go:linkname EspClkPrivateLock C.esp_clk_private_lock +func EspClkPrivateLock() + +/** + * @brief counterpart of esp_clk_private_lock + */ +//go:linkname EspClkPrivateUnlock C.esp_clk_private_unlock +func EspClkPrivateUnlock() diff --git a/esp32/esp_clk_tree.go b/esp32/esp_clk_tree.go new file mode 100644 index 00000000..07a70f40 --- /dev/null +++ b/esp32/esp_clk_tree.go @@ -0,0 +1,36 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EspClkTreeSrcFreqPrecisionT c.Int + +const ( + ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED EspClkTreeSrcFreqPrecisionT = 0 + ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX EspClkTreeSrcFreqPrecisionT = 1 + ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT EspClkTreeSrcFreqPrecisionT = 2 + ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID EspClkTreeSrcFreqPrecisionT = 3 +) + +/** + * @brief Get frequency of module clock source + * + * @param[in] clk_src Clock source available to modules, in soc_module_clk_t + * @param[in] precision Degree of precision, one of esp_clk_tree_src_freq_precision_t values + * This arg only applies to the clock sources that their frequencies can vary: + * SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_RTC_SLOW, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_RC_FAST_D256, + * SOC_MOD_CLK_XTAL32K + * For other clock sources, this field is ignored. + * @param[out] freq_value Frequency of the clock source, in Hz + * + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG Parameter error + * - ESP_FAIL Calibration failed + */ +// llgo:link SocModuleClkT.EspClkTreeSrcGetFreqHz C.esp_clk_tree_src_get_freq_hz +func (recv_ SocModuleClkT) EspClkTreeSrcGetFreqHz(precision EspClkTreeSrcFreqPrecisionT, freq_value *c.Uint32T) EspErrT { + return 0 +} diff --git a/esp32/esp_clk_tree_common.go b/esp32/esp_clk_tree_common.go new file mode 100644 index 00000000..9beb5cef --- /dev/null +++ b/esp32/esp_clk_tree_common.go @@ -0,0 +1,86 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Get frequency of RC_FAST_D256_CLK + * + * @param precision Degree of precision of the returned frequency value, one of esp_clk_tree_src_freq_precision_t values + * + * @return RC_FAST_D256 clock frequency, in Hz. Returns 0 if degree of precision is invalid or calibration failed. + */ +// llgo:link EspClkTreeSrcFreqPrecisionT.EspClkTreeRcFastD256GetFreqHz C.esp_clk_tree_rc_fast_d256_get_freq_hz +func (recv_ EspClkTreeSrcFreqPrecisionT) EspClkTreeRcFastD256GetFreqHz() c.Uint32T { + return 0 +} + +/** + * @brief Get frequency of XTAL32K_CLK + * + * @param precision Degree of precision of the returned frequency value, one of esp_clk_tree_src_freq_precision_t values + * + * @return XTAL32K clock frequency, in Hz. Returns 0 if degree of precision is invalid or calibration failed. + */ +// llgo:link EspClkTreeSrcFreqPrecisionT.EspClkTreeXtal32kGetFreqHz C.esp_clk_tree_xtal32k_get_freq_hz +func (recv_ EspClkTreeSrcFreqPrecisionT) EspClkTreeXtal32kGetFreqHz() c.Uint32T { + return 0 +} + +/** + * @brief Get frequency of RC_FAST_CLK + * + * @param precision Degree of precision of the returned frequency value, one of esp_clk_tree_src_freq_precision_t values + * + * @return RC_FAST clock frequency, in Hz. Returns 0 if degree of precision is invalid or calibration failed. + */ +// llgo:link EspClkTreeSrcFreqPrecisionT.EspClkTreeRcFastGetFreqHz C.esp_clk_tree_rc_fast_get_freq_hz +func (recv_ EspClkTreeSrcFreqPrecisionT) EspClkTreeRcFastGetFreqHz() c.Uint32T { + return 0 +} + +/** + * @brief Get frequency of LP_SLOW_CLK (i.e. RTC_SLOW_CLK) + * + * @param precision Degree of precision of the returned frequency value, one of esp_clk_tree_src_freq_precision_t values + * + * @return LP_SLOW clock frequency, in Hz. Returns 0 if degree of precision is invalid or calibration failed. + */ +// llgo:link EspClkTreeSrcFreqPrecisionT.EspClkTreeLpSlowGetFreqHz C.esp_clk_tree_lp_slow_get_freq_hz +func (recv_ EspClkTreeSrcFreqPrecisionT) EspClkTreeLpSlowGetFreqHz() c.Uint32T { + return 0 +} + +/** + * @brief Get frequency of LP_FAST_CLK (i.e. RTC_FAST_CLK) + * + * @param precision Degree of precision of the returned frequency value, one of esp_clk_tree_src_freq_precision_t values + * + * @return LP_FAST clock frequency, in Hz. Returns 0 if degree of precision is invalid or calibration failed. + */ +// llgo:link EspClkTreeSrcFreqPrecisionT.EspClkTreeLpFastGetFreqHz C.esp_clk_tree_lp_fast_get_freq_hz +func (recv_ EspClkTreeSrcFreqPrecisionT) EspClkTreeLpFastGetFreqHz() c.Uint32T { + return 0 +} + +/** + * @brief Enable / Disable the clock gate of the clock source + * + * @param[in] clk_src Clock source available to modules, in soc_module_clk_t + * @param[in] enable Enable / Disable the clock gate + * + * @note !!! WARNING !!! + * There's no reference counter to protect the clock source status, the caller should use the interface + * with CAUTION to disable the clock source to avoid damaging other peripherals that are dependent on + * the clock source. + * + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG Parameter error + */ +// llgo:link SocModuleClkT.EspClkTreeEnableSrc C.esp_clk_tree_enable_src +func (recv_ SocModuleClkT) EspClkTreeEnableSrc(enable bool) EspErrT { + return 0 +} diff --git a/esp32/esp_clk_utils.go b/esp32/esp_clk_utils.go new file mode 100644 index 00000000..3b2d993e --- /dev/null +++ b/esp32/esp_clk_utils.go @@ -0,0 +1,24 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Sync MSPI speed mode before CPU frequency switching, only needed when frequency is decreasing. + * + * @param target_cpu_src_freq Target clock source frequency for CPU frequency switching + * @param target_cpu_freq CPU frequency switching target frequency + */ +//go:linkname EspClkUtilsMspiSpeedModeSyncBeforeCpuFreqSwitching C.esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching +func EspClkUtilsMspiSpeedModeSyncBeforeCpuFreqSwitching(target_cpu_src_freq c.Uint32T, target_cpu_freq c.Uint32T) + +/** + * @brief Sync MSPI speed mode after CPU frequency switching, only needed when frequency is upcreasing. + * + * @param target_cpu_src_freq Target clock source frequency for CPU frequency switching + * @param target_cpu_freq CPU frequency switching target frequency + */ +//go:linkname EspClkUtilsMspiSpeedModeSyncAfterCpuFreqSwitching C.esp_clk_utils_mspi_speed_mode_sync_after_cpu_freq_switching +func EspClkUtilsMspiSpeedModeSyncAfterCpuFreqSwitching(target_cpu_src_freq c.Uint32T, target_cpu_freq c.Uint32T) diff --git a/esp32/esp_compiler.go b/esp32/esp_compiler.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/esp_compiler.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/esp_cpu.go b/esp32/esp_cpu.go new file mode 100644 index 00000000..595fffc8 --- /dev/null +++ b/esp32/esp_cpu.go @@ -0,0 +1,163 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ESP_CPU_INTR_DESC_FLAG_SPECIAL = 0x01 +const ESP_CPU_INTR_DESC_FLAG_RESVD = 0x02 + +type EspCpuCycleCountT c.Uint32T +type EspCpuIntrTypeT c.Int + +const ( + ESP_CPU_INTR_TYPE_LEVEL EspCpuIntrTypeT = 0 + ESP_CPU_INTR_TYPE_EDGE EspCpuIntrTypeT = 1 + ESP_CPU_INTR_TYPE_NA EspCpuIntrTypeT = 2 +) + +/** + * @brief CPU interrupt descriptor + * + * Each particular CPU interrupt has an associated descriptor describing that + * particular interrupt's characteristics. Call esp_cpu_intr_get_desc() to get + * the descriptors of a particular interrupt. + */ + +type EspCpuIntrDescT struct { + Priority c.Int + Type EspCpuIntrTypeT + Flags c.Uint32T +} + +// llgo:type C +type EspCpuIntrHandlerT func(c.Pointer) +type EspCpuWatchpointTriggerT c.Int + +const ( + ESP_CPU_WATCHPOINT_LOAD EspCpuWatchpointTriggerT = 0 + ESP_CPU_WATCHPOINT_STORE EspCpuWatchpointTriggerT = 1 + ESP_CPU_WATCHPOINT_ACCESS EspCpuWatchpointTriggerT = 2 +) + +/** + * @brief Stall a CPU core + * + * @param core_id The core's ID + */ +//go:linkname EspCpuStall C.esp_cpu_stall +func EspCpuStall(core_id c.Int) + +/** + * @brief Resume a previously stalled CPU core + * + * @param core_id The core's ID + */ +//go:linkname EspCpuUnstall C.esp_cpu_unstall +func EspCpuUnstall(core_id c.Int) + +/** + * @brief Reset a CPU core + * + * @param core_id The core's ID + */ +//go:linkname EspCpuReset C.esp_cpu_reset +func EspCpuReset(core_id c.Int) + +/** + * @brief Wait for Interrupt + * + * This function causes the current CPU core to execute its Wait For Interrupt + * (WFI or equivalent) instruction. After executing this function, the CPU core + * will stop execution until an interrupt occurs. + */ +//go:linkname EspCpuWaitForIntr C.esp_cpu_wait_for_intr +func EspCpuWaitForIntr() + +/** + * @brief Get a CPU interrupt's descriptor + * + * Each CPU interrupt has a descriptor describing the interrupt's capabilities + * and restrictions. This function gets the descriptor of a particular interrupt + * on a particular CPU. + * + * @param[in] core_id The core's ID + * @param[in] intr_num Interrupt number + * @param[out] intr_desc_ret The interrupt's descriptor + */ +//go:linkname EspCpuIntrGetDesc C.esp_cpu_intr_get_desc +func EspCpuIntrGetDesc(core_id c.Int, intr_num c.Int, intr_desc_ret *EspCpuIntrDescT) + +/** + * @brief Configure the CPU to disable access to invalid memory regions + */ +//go:linkname EspCpuConfigureRegionProtection C.esp_cpu_configure_region_protection +func EspCpuConfigureRegionProtection() + +/** + * @brief Set and enable a hardware breakpoint on the current CPU + * + * @note This function is meant to be called by the panic handler to set a + * breakpoint for an attached debugger during a panic. + * @note Overwrites previously set breakpoint with same breakpoint number. + * @param bp_num Hardware breakpoint number [0..SOC_CPU_BREAKPOINTS_NUM - 1] + * @param bp_addr Address to set a breakpoint on + * @return ESP_OK if breakpoint is set. Failure otherwise + */ +//go:linkname EspCpuSetBreakpoint C.esp_cpu_set_breakpoint +func EspCpuSetBreakpoint(bp_num c.Int, bp_addr c.Pointer) EspErrT + +/** + * @brief Clear a hardware breakpoint on the current CPU + * + * @note Clears a breakpoint regardless of whether it was previously set + * @param bp_num Hardware breakpoint number [0..SOC_CPU_BREAKPOINTS_NUM - 1] + * @return ESP_OK if breakpoint is cleared. Failure otherwise + */ +//go:linkname EspCpuClearBreakpoint C.esp_cpu_clear_breakpoint +func EspCpuClearBreakpoint(bp_num c.Int) EspErrT + +/** + * @brief Set and enable a hardware watchpoint on the current CPU + * + * Set and enable a hardware watchpoint on the current CPU, specifying the + * memory range and trigger operation. Watchpoints will break/panic the CPU when + * the CPU accesses (according to the trigger type) on a certain memory range. + * + * @note Overwrites previously set watchpoint with same watchpoint number. + * On RISC-V chips, this API uses method0(Exact matching) and method1(NAPOT matching) according to the + * riscv-debug-spec-0.13 specification for address matching. + * If the watch region size is 1byte, it uses exact matching (method 0). + * If the watch region size is larger than 1byte, it uses NAPOT matching (method 1). This mode requires + * the watching region start address to be aligned to the watching region size. + * + * @param wp_num Hardware watchpoint number [0..SOC_CPU_WATCHPOINTS_NUM - 1] + * @param wp_addr Watchpoint's base address, must be naturally aligned to the size of the region + * @param size Size of the region to watch. Must be one of 2^n and in the range of [1 ... SOC_CPU_WATCHPOINT_MAX_REGION_SIZE] + * @param trigger Trigger type + * @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise + */ +//go:linkname EspCpuSetWatchpoint C.esp_cpu_set_watchpoint +func EspCpuSetWatchpoint(wp_num c.Int, wp_addr c.Pointer, size c.SizeT, trigger EspCpuWatchpointTriggerT) EspErrT + +/** + * @brief Clear a hardware watchpoint on the current CPU + * + * @note Clears a watchpoint regardless of whether it was previously set + * @param wp_num Hardware watchpoint number [0..SOC_CPU_WATCHPOINTS_NUM - 1] + * @return ESP_OK if watchpoint was cleared. Failure otherwise. + */ +//go:linkname EspCpuClearWatchpoint C.esp_cpu_clear_watchpoint +func EspCpuClearWatchpoint(wp_num c.Int) EspErrT + +/** + * @brief Atomic compare-and-set operation + * + * @param addr Address of atomic variable + * @param compare_value Value to compare the atomic variable to + * @param new_value New value to set the atomic variable to + * @return Whether the atomic variable was set or not + */ +//go:linkname EspCpuCompareAndSet C.esp_cpu_compare_and_set +func EspCpuCompareAndSet(addr *c.Uint32T, compare_value c.Uint32T, new_value c.Uint32T) bool diff --git a/esp32/esp_cpu_internal.go b/esp32/esp_cpu_internal.go new file mode 100644 index 00000000..417b5a43 --- /dev/null +++ b/esp32/esp_cpu_internal.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +type EspCpuFrameT XtExcFrame diff --git a/esp32/esp_cpu_utils.go b/esp32/esp_cpu_utils.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/esp_cpu_utils.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/esp_crypto_lock.go b/esp32/esp_crypto_lock.go new file mode 100644 index 00000000..dad955fe --- /dev/null +++ b/esp32/esp_crypto_lock.go @@ -0,0 +1,63 @@ +package freertos + +import _ "unsafe" + +/** + * @brief Acquire lock for HMAC cryptography peripheral + * + * Internally also locks the SHA peripheral, as the HMAC depends on the SHA peripheral + */ +//go:linkname EspCryptoHmacLockAcquire C.esp_crypto_hmac_lock_acquire +func EspCryptoHmacLockAcquire() + +/** + * @brief Release lock for HMAC cryptography peripheral + * + * Internally also releases the SHA peripheral, as the HMAC depends on the SHA peripheral + */ +//go:linkname EspCryptoHmacLockRelease C.esp_crypto_hmac_lock_release +func EspCryptoHmacLockRelease() + +/** + * @brief Acquire lock for DS cryptography peripheral + * + * Internally also locks the HMAC (which locks SHA), AES and MPI peripheral, as the DS depends on these peripherals + */ +//go:linkname EspCryptoDsLockAcquire C.esp_crypto_ds_lock_acquire +func EspCryptoDsLockAcquire() + +/** + * @brief Release lock for DS cryptography peripheral + * + * Internally also releases the HMAC (which locks SHA), AES and MPI peripheral, as the DS depends on these peripherals + */ +//go:linkname EspCryptoDsLockRelease C.esp_crypto_ds_lock_release +func EspCryptoDsLockRelease() + +/** + * @brief Acquire lock for the SHA and AES cryptography peripheral. + * + */ +//go:linkname EspCryptoShaAesLockAcquire C.esp_crypto_sha_aes_lock_acquire +func EspCryptoShaAesLockAcquire() + +/** + * @brief Release lock for the SHA and AES cryptography peripheral. + * + */ +//go:linkname EspCryptoShaAesLockRelease C.esp_crypto_sha_aes_lock_release +func EspCryptoShaAesLockRelease() + +/** + * @brief Acquire lock for the mpi cryptography peripheral. + * + */ +//go:linkname EspCryptoMpiLockAcquire C.esp_crypto_mpi_lock_acquire +func EspCryptoMpiLockAcquire() + +/** + * @brief Release lock for the mpi/rsa cryptography peripheral. + * + */ +//go:linkname EspCryptoMpiLockRelease C.esp_crypto_mpi_lock_release +func EspCryptoMpiLockRelease() diff --git a/esp32/esp_crypto_lock_internal.go b/esp32/esp_crypto_lock_internal.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/esp_crypto_lock_internal.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/esp_debug_helpers.go b/esp32/esp_debug_helpers.go new file mode 100644 index 00000000..f9ce6185 --- /dev/null +++ b/esp32/esp_debug_helpers.go @@ -0,0 +1,126 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* + * @brief Structure used for backtracing + * + * This structure stores the backtrace information of a particular stack frame + * (i.e. the PC and SP). This structure is used iteratively with the + * esp_cpu_get_next_backtrace_frame() function to traverse each frame within a + * single stack. The next_pc represents the PC of the current frame's caller, thus + * a next_pc of 0 indicates that the current frame is the last frame on the stack. + * + * @note Call esp_backtrace_get_start() to obtain initialization values for + * this structure + */ + +type EspBacktraceFrameT struct { + Pc c.Uint32T + Sp c.Uint32T + NextPc c.Uint32T + ExcFrame c.Pointer +} + +/** + * @brief If an OCD is connected over JTAG. set breakpoint 0 to the given function + * address. Do nothing otherwise. + * @param fn Pointer to the target breakpoint position + */ +//go:linkname EspSetBreakpointIfJtag C.esp_set_breakpoint_if_jtag +func EspSetBreakpointIfJtag(fn c.Pointer) + +/** + * Get the first frame of the current stack's backtrace + * + * Given the following function call flow (B -> A -> X -> esp_backtrace_get_start), + * this function will do the following. + * - Flush CPU registers and window frames onto the current stack + * - Return PC and SP of function A (i.e. start of the stack's backtrace) + * - Return PC of function B (i.e. next_pc) + * + * @note This function is implemented in assembly + * + * @param[out] pc PC of the first frame in the backtrace + * @param[out] sp SP of the first frame in the backtrace + * @param[out] next_pc PC of the first frame's caller + */ +//go:linkname EspBacktraceGetStart C.esp_backtrace_get_start +func EspBacktraceGetStart(pc *c.Uint32T, sp *c.Uint32T, next_pc *c.Uint32T) + +/** + * Get the next frame on a stack for backtracing + * + * Given a stack frame(i), this function will obtain the next stack frame(i-1) + * on the same call stack (i.e. the caller of frame(i)). This function is meant to be + * called iteratively when doing a backtrace. + * + * Entry Conditions: Frame structure containing valid SP and next_pc + * Exit Conditions: + * - Frame structure updated with SP and PC of frame(i-1). next_pc now points to frame(i-2). + * - If a next_pc of 0 is returned, it indicates that frame(i-1) is last frame on the stack + * + * @param[inout] frame Pointer to frame structure + * + * @return + * - True if the SP and PC of the next frame(i-1) are sane + * - False otherwise + */ +// llgo:link (*EspBacktraceFrameT).EspBacktraceGetNextFrame C.esp_backtrace_get_next_frame +func (recv_ *EspBacktraceFrameT) EspBacktraceGetNextFrame() bool { + return false +} + +/** + * @brief Print the backtrace from specified frame. + * + * @param depth The maximum number of stack frames to print (should be > 0) + * @param frame Starting frame to print from + * @param panic Indicator if backtrace print is during a system panic + * + * @note On the ESP32, users must call esp_backtrace_get_start() first to flush the stack. + * @note If a esp_backtrace_frame_t* frame is obtained though a call to esp_backtrace_get_start() + * from some example function func_a(), then frame is only valid within the frame/scope of func_a(). + * Users should not attempt to pass/use frame other frames within the same stack of different stacks. + * + * @return + * - ESP_OK Backtrace successfully printed to completion or to depth limit + * - ESP_FAIL Backtrace is corrupted + */ +//go:linkname EspBacktracePrintFromFrame C.esp_backtrace_print_from_frame +func EspBacktracePrintFromFrame(depth c.Int, frame *EspBacktraceFrameT, panic bool) EspErrT + +/** + * @brief Print the backtrace of the current stack + * + * @param depth The maximum number of stack frames to print (should be > 0) + * + * @note On RISC-V targets printing backtrace at run-time is only available if + * CONFIG_ESP_SYSTEM_USE_EH_FRAME is selected. Otherwise we simply print + * a register dump. Function assumes it is called in a context where the + * calling task will not migrate to another core, e.g. interrupts disabled/panic handler. + * + * @return + * - ESP_OK Backtrace successfully printed to completion or to depth limit + * - ESP_FAIL Backtrace is corrupted + */ +//go:linkname EspBacktracePrint C.esp_backtrace_print +func EspBacktracePrint(depth c.Int) EspErrT + +/** + * @brief Print the backtrace of all tasks + * + * @param depth The maximum number of stack frames to print (must be > 0) + * + * @note Users must ensure that no tasks are created or deleted while this function is running. + * @note This function must be called from a task context. + * + * @return + * - ESP_OK All backtraces successfully printed to completion or to depth limit + * - ESP_FAIL One or more backtraces are corrupt + */ +//go:linkname EspBacktracePrintAllTasks C.esp_backtrace_print_all_tasks +func EspBacktracePrintAllTasks(depth c.Int) EspErrT diff --git a/esp32/esp_dma_utils.go b/esp32/esp_dma_utils.go new file mode 100644 index 00000000..891c9d62 --- /dev/null +++ b/esp32/esp_dma_utils.go @@ -0,0 +1,181 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief DMA Mem info + */ + +type EspDmaMemInfoT struct { + ExtraHeapCaps c.Int + DmaAlignmentBytes c.SizeT +} + +/** + * @brief Helper function for malloc a DMA capable memory buffer + * + * @note This API will take care of the cache alignment internally, + * you will need to set `esp_dma_mem_info_t: dma_alignment_bytes` + * with either the custom alignment or DMA alignment of used peripheral driver. + * + * @param[in] size Size in bytes, the amount of memory to allocate + * @param[in] dma_mem_info DMA and memory info, see `esp_dma_mem_info_t` + * @param[out] out_ptr A pointer to the memory allocated successfully + * @param[out] actual_size Actual size for allocation in bytes, when the size you specified doesn't meet the DMA alignment requirements, this value might be bigger than the size you specified. Set null if you don't care this value. + * + * @return + * - ESP_OK: + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_NO_MEM: No enough memory for allocation + */ +//go:linkname EspDmaCapableMalloc C.esp_dma_capable_malloc +func EspDmaCapableMalloc(size c.SizeT, dma_mem_info *EspDmaMemInfoT, out_ptr *c.Pointer, actual_size *c.SizeT) EspErrT + +/** + * @brief Helper function for calloc a DMA capable memory buffer + * + * @param[in] calloc_num Number of elements to allocate + * @param[in] size Size in bytes, the amount of memory to allocate + * @param[in] dma_mem_info DMA and memory info, see `esp_dma_mem_info_t` + * @param[out] out_ptr A pointer to the memory allocated successfully + * @param[out] actual_size Actual size for allocation in bytes, when the size you specified doesn't meet the DMA alignment requirements, this value might be bigger than the size you specified. Set null if you don't care this value. + * + * @return + * - ESP_OK: + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_NO_MEM: No enough memory for allocation + */ +//go:linkname EspDmaCapableCalloc C.esp_dma_capable_calloc +func EspDmaCapableCalloc(calloc_num c.SizeT, size c.SizeT, dma_mem_info *EspDmaMemInfoT, out_ptr *c.Pointer, actual_size *c.SizeT) EspErrT + +/** + * @brief Helper function to check if a DMA buffer pointer and size meet both hardware alignment requirements and custom alignment requirements + * + * @param[in] ptr Pointer to the buffer + * @param[in] size Size of the buffer + * @param[in] dma_mem_info DMA and memory info, see `esp_dma_mem_info_t` + * + * @return + * - True: Buffer is aligned + * - False: Buffer is not aligned, or buffer is not DMA capable + */ +//go:linkname EspDmaIsBufferAlignmentSatisfied C.esp_dma_is_buffer_alignment_satisfied +func EspDmaIsBufferAlignmentSatisfied(ptr c.Pointer, size c.SizeT, dma_mem_info EspDmaMemInfoT) bool + +/** + * @brief Needed info to get GDMA alignment + */ + +type DmaAlignmentInfoT struct { + IsDesc bool + OnPsram bool +} + +/** + * @note This API will use MAX alignment requirement + */ +//go:linkname EspDmaMalloc C.esp_dma_malloc +func EspDmaMalloc(size c.SizeT, flags c.Uint32T, out_ptr *c.Pointer, actual_size *c.SizeT) EspErrT + +/** + * @note This API will use MAX alignment requirement + */ +//go:linkname EspDmaCalloc C.esp_dma_calloc +func EspDmaCalloc(n c.SizeT, size c.SizeT, flags c.Uint32T, out_ptr *c.Pointer, actual_size *c.SizeT) EspErrT + +type EspDmaBufLocationT c.Int + +const ( + ESP_DMA_BUF_LOCATION_INTERNAL EspDmaBufLocationT = 0 + ESP_DMA_BUF_LOCATION_PSRAM EspDmaBufLocationT = 1 + ESP_DMA_BUF_LOCATION_AUTO EspDmaBufLocationT = 2 +) + +/** + * @note This API will use MAX alignment requirement + */ +//go:linkname EspDmaIsBufferAligned C.esp_dma_is_buffer_aligned +func EspDmaIsBufferAligned(ptr c.Pointer, size c.SizeT, location EspDmaBufLocationT) bool + +/** + * @brief DMA buffer information + */ + +type DmaBufferSplitInfoT struct { + AlignedBuffer c.Pointer + RecoveryAddress c.Pointer + Length c.SizeT +} + +/** + * @brief DMA buffer aligned array + * The array contains three parts: head, body and tail. + * Length of each part will be >=0, especially, length=0 means that there is no such part. + */ + +type DmaBufferSplitArrayT struct { + Unused [8]uint8 +} + +/** + * @brief Split DMA RX buffer to cache aligned buffers + * + * @note After the original RX buffer is split into an array, caller should mount the buffer array to the DMA controller in scatter-gather mode. + * Don't read/write the aligned buffers before the DMA finished using them. + * + * @param[in] rx_buffer The origin DMA buffer used for receiving data + * @param[in] buffer_len rx_buffer length + * @param[out] align_buf_array Aligned DMA buffer array + * @param[out] ret_stash_buffer Allocated stash buffer (caller should free it after use) + * @return + * - ESP_OK: Split to aligned buffer successfully + * - ESP_ERR_INVALID_ARG: Split to aligned buffer failed because of invalid argument + * + * brief sketch: + * cache alignment delimiter cache alignment delimiter + * │ │ + * Origin Buffer │ Origin Buffer │ + * │ │ │ │ + * │ ▼ ▼ ▼ + * │ ...---xxxxx|xxxxxxxxxxxxxxxxxxxxxxxxxxxxx|xxxxx----... + * │ │ │ │ + * │ │ ▼ │ + * │ │ |xxxxxxxxxxxxxxxxxxxxxxxxxxxxx| │ + * │ │ ▲ │ + * ▼ │ │ │ + * Aligned buffers └──► Head Body Tail ◄──────┘ + * │ │ + * ▼ ▼ + * |xxxxx......| |xxxxx......| + */ +//go:linkname EspDmaSplitRxBufferToCacheAligned C.esp_dma_split_rx_buffer_to_cache_aligned +func EspDmaSplitRxBufferToCacheAligned(rx_buffer c.Pointer, buffer_len c.SizeT, align_buf_array *DmaBufferSplitArrayT, ret_stash_buffer **c.Uint8T) EspErrT + +/** + * @brief Merge aligned RX buffer array to origin buffer + * + * @note This function can be used in the ISR context. + * + * @param[in] align_buf_array Aligned DMA buffer array + * @return + * - ESP_OK: Merge aligned buffer to origin buffer successfully + * - ESP_ERR_INVALID_ARG: Merge aligned buffer to origin buffer failed because of invalid argument + */ +// llgo:link (*DmaBufferSplitArrayT).EspDmaMergeAlignedRxBuffers C.esp_dma_merge_aligned_rx_buffers +func (recv_ *DmaBufferSplitArrayT) EspDmaMergeAlignedRxBuffers() EspErrT { + return 0 +} + +/** + * @brief Calculate the number of DMA linked list nodes required for a given buffer size + * + * @param[in] buffer_size Total size of the buffer + * @param[in] buffer_alignment Alignment requirement for the buffer + * @param[in] max_buffer_size_per_node Maximum buffer size that each node can handle + * @return Number of DMA linked list nodes required + */ +//go:linkname EspDmaCalculateNodeCount C.esp_dma_calculate_node_count +func EspDmaCalculateNodeCount(buffer_size c.SizeT, buffer_alignment c.SizeT, max_buffer_size_per_node c.SizeT) c.SizeT diff --git a/esp32/esp_dpa_protection.go b/esp32/esp_dpa_protection.go new file mode 100644 index 00000000..225b7fd0 --- /dev/null +++ b/esp32/esp_dpa_protection.go @@ -0,0 +1,36 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EspCryptoDpaSecLevelT c.Int + +const ( + ESP_CRYPTO_DPA_SEC_LEVEL_OFF EspCryptoDpaSecLevelT = 0 + ESP_CRYPTO_DPA_SEC_LEVEL_LOW EspCryptoDpaSecLevelT = 1 + ESP_CRYPTO_DPA_SEC_LEVEL_MIDDLE EspCryptoDpaSecLevelT = 2 + ESP_CRYPTO_DPA_SEC_LEVEL_HIGH EspCryptoDpaSecLevelT = 3 +) + +/** + * @brief Enable DPA (Differential Power Analysis) related protection + * + * @note + * Enabling the DPA protection can help to make it difficult to perform SCA + * attacks on the crypto peripherals. However, based on the security level + * set there will be a performance impact, higher the level higher the impact. + * Please refer to the TRM for more details. + * + * @param level DPA Security Level of type `esp_crypto_dpa_sec_level_t` + */ +// llgo:link EspCryptoDpaSecLevelT.EspCryptoDpaProtectionEnable C.esp_crypto_dpa_protection_enable +func (recv_ EspCryptoDpaSecLevelT) EspCryptoDpaProtectionEnable() { +} + +/** + * @brief Disable DPA (Differential Power Analysis) related protection + */ +//go:linkname EspCryptoDpaProtectionDisable C.esp_crypto_dpa_protection_disable +func EspCryptoDpaProtectionDisable() diff --git a/esp32/esp_ds.go b/esp32/esp_ds.go new file mode 100644 index 00000000..40f2be6a --- /dev/null +++ b/esp32/esp_ds.go @@ -0,0 +1,188 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ESP_DS_IV_BIT_LEN = 128 +const ESP_DS_SIGNATURE_MD_BIT_LEN = 256 +const ESP_DS_SIGNATURE_M_PRIME_BIT_LEN = 32 +const ESP_DS_SIGNATURE_L_BIT_LEN = 32 +const ESP_DS_SIGNATURE_PADDING_BIT_LEN = 64 + +type EspDsContext struct { + Unused [8]uint8 +} +type EspDsContextT EspDsContext +type EspDigitalSignatureLengthT c.Int + +const ( + ESP_DS_RSA_1024 EspDigitalSignatureLengthT = 31 + ESP_DS_RSA_2048 EspDigitalSignatureLengthT = 63 + ESP_DS_RSA_3072 EspDigitalSignatureLengthT = 95 + ESP_DS_RSA_4096 EspDigitalSignatureLengthT = 127 +) + +/** + * Encrypted private key data. Recommended to store in flash in this format. + * + * @note This struct has to match to one from the ROM code! This documentation is mostly taken from there. + */ + +type EspDigitalSignatureData struct { + RsaLength EspDigitalSignatureLengthT + Iv [4]c.Uint32T + C [1584]c.Uint8T +} +type EspDsDataT EspDigitalSignatureData + +/** + * Plaintext parameters used by Digital Signature. + * + * This is only used for encrypting the RSA parameters by calling esp_ds_encrypt_params(). + * Afterwards, the result can be stored in flash or in other persistent memory. + * The encryption is a prerequisite step before any signature operation can be done. + * + * @note + * Y, M, Rb, & M_Prime must all be in little endian format. + */ + +type EspDsPDataT struct { + Y [128]c.Uint32T + M [128]c.Uint32T + Rb [128]c.Uint32T + MPrime c.Uint32T + Length c.Uint32T +} + +/** +* @brief Sign the message with a hardware key from specific key slot. +* The function calculates a plain RSA signature with help of the DS peripheral. +* The RSA encryption operation is as follows: +* Z = XY mod M where, +* Z is the signature, X is the input message, +* Y and M are the RSA private key parameters. +* +* This function is a wrapper around \c esp_ds_finish_sign() and \c esp_ds_start_sign(), so do not use them +* in parallel. +* It blocks until the signing is finished and then returns the signature. +* +* @note +* Please see note section of \c esp_ds_start_sign() for more details about the input parameters. +* +* @param message the message to be signed; its length should be (data->rsa_length + 1)*4 bytes, and those + bytes must be in little endian format. It is your responsibility to apply your hash function + and padding before calling this function, if required. (e.g. message = padding(hash(inputMsg))) +* @param data the encrypted signing key data (AES encrypted RSA key + IV) +* @param key_id the HMAC key ID determining the HMAC key of the HMAC which will be used to decrypt the +* signing key data +* @param signature the destination of the signature, should be (data->rsa_length + 1)*4 bytes long +* +* @return +* - ESP_OK if successful, the signature was written to the parameter \c signature. +* - ESP_ERR_INVALID_ARG if one of the parameters is NULL or data->rsa_length is too long or 0 +* - ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL if there was an HMAC failure during retrieval of the decryption key +* - ESP_ERR_NO_MEM if there hasn't been enough memory to allocate the context object +* - ESP_ERR_HW_CRYPTO_DS_INVALID_KEY if there's a problem with passing the HMAC key to the DS component +* - ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST if the message digest didn't match; the signature is invalid. +* - ESP_ERR_HW_CRYPTO_DS_INVALID_PADDING if the message padding is incorrect, the signature can be read though +* since the message digest matches. +*/ +//go:linkname EspDsSign C.esp_ds_sign +func EspDsSign(message c.Pointer, data *EspDsDataT, key_id HmacKeyIdT, signature c.Pointer) EspErrT + +/** +* @brief Start the signing process. +* +* This function yields a context object which needs to be passed to \c esp_ds_finish_sign() to finish the signing +* process. +* The function calculates a plain RSA signature with help of the DS peripheral. +* The RSA encryption operation is as follows: +* Z = XY mod M where, +* Z is the signature, X is the input message, +* Y and M are the RSA private key parameters. +* +* @note +* This function locks the HMAC, SHA, AES and RSA components, so the user has to ensure to call +* \c esp_ds_finish_sign() in a timely manner. +* The numbers Y, M, Rb which are a part of esp_ds_data_t should be provided in little endian format +* and should be of length equal to the RSA private key bit length +* The message length in bits should also be equal to the RSA private key bit length. +* No padding is applied to the message automatically, Please ensure the message is appropriate padded before +* calling the API. +* +* @param message the message to be signed; its length should be (data->rsa_length + 1)*4 bytes, and those + bytes must be in little endian format. It is your responsibility to apply your hash function + and padding before calling this function, if required. (e.g. message = padding(hash(inputMsg))) +* @param data the encrypted signing key data (AES encrypted RSA key + IV) +* @param key_id the HMAC key ID determining the HMAC key of the HMAC which will be used to decrypt the +* signing key data +* @param esp_ds_ctx the context object which is needed for finishing the signing process later +* +* @return +* - ESP_OK if successful, the ds operation was started now and has to be finished with \c esp_ds_finish_sign() +* - ESP_ERR_INVALID_ARG if one of the parameters is NULL or data->rsa_length is too long or 0 +* - ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL if there was an HMAC failure during retrieval of the decryption key +* - ESP_ERR_NO_MEM if there hasn't been enough memory to allocate the context object +* - ESP_ERR_HW_CRYPTO_DS_INVALID_KEY if there's a problem with passing the HMAC key to the DS component +*/ +//go:linkname EspDsStartSign C.esp_ds_start_sign +func EspDsStartSign(message c.Pointer, data *EspDsDataT, key_id HmacKeyIdT, esp_ds_ctx **EspDsContextT) EspErrT + +/** + * Return true if the DS peripheral is busy, otherwise false. + * + * @note Only valid if \c esp_ds_start_sign() was called before. + */ +//go:linkname EspDsIsBusy C.esp_ds_is_busy +func EspDsIsBusy() bool + +/** +* @brief Finish the signing process. +* +* @param signature the destination of the signature, should be (data->rsa_length + 1)*4 bytes long, + the resultant signature bytes shall be written in little endian format. +* @param esp_ds_ctx the context object retrieved by \c esp_ds_start_sign() +* +* @return +* - ESP_OK if successful, the ds operation has been finished and the result is written to signature. +* - ESP_ERR_INVALID_ARG if one of the parameters is NULL +* - ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST if the message digest didn't match; the signature is invalid. +* This means that the encrypted RSA key parameters are invalid, indicating that they may have been tampered +* with or indicating a flash error, etc. +* - ESP_ERR_HW_CRYPTO_DS_INVALID_PADDING if the message padding is incorrect, the signature can be read though +* since the message digest matches (see TRM for more details). +*/ +//go:linkname EspDsFinishSign C.esp_ds_finish_sign +func EspDsFinishSign(signature c.Pointer, esp_ds_ctx *EspDsContextT) EspErrT + +/** + * @brief Encrypt the private key parameters. + * + * The encryption is a prerequisite step before any signature operation can be done. + * It is not strictly necessary to use this encryption function, the encryption could also happen on an external + * device. + * + * @param data Output buffer to store encrypted data, suitable for later use generating signatures. + * @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time. + * @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process + * is done and 'data' is stored. + * @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the + * corresponding HMAC key will be stored to efuse and then permanently erased. + * + * @note + * The numbers Y, M, Rb which are a part of esp_ds_data_t should be provided in little endian format + * and should be of length equal to the RSA private key bit length + * The message length in bits should also be equal to the RSA private key bit length. + * No padding is applied to the message automatically, Please ensure the message is appropriate padded before + * calling the API. + * + * @return + * - ESP_OK if successful, the ds operation has been finished and the result is written to signature. + * - ESP_ERR_INVALID_ARG if one of the parameters is NULL or p_data->rsa_length is too long + */ +// llgo:link (*EspDsDataT).EspDsEncryptParams C.esp_ds_encrypt_params +func (recv_ *EspDsDataT) EspDsEncryptParams(iv c.Pointer, p_data *EspDsPDataT, key c.Pointer) EspErrT { + return 0 +} diff --git a/esp32/esp_ds_err.go b/esp32/esp_ds_err.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/esp_ds_err.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/esp_err.go b/esp32/esp_err.go new file mode 100644 index 00000000..5f243771 --- /dev/null +++ b/esp32/esp_err.go @@ -0,0 +1,77 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ESP_OK = 0 +const ESP_ERR_NO_MEM = 0x101 +const ESP_ERR_INVALID_ARG = 0x102 +const ESP_ERR_INVALID_STATE = 0x103 +const ESP_ERR_INVALID_SIZE = 0x104 +const ESP_ERR_NOT_FOUND = 0x105 +const ESP_ERR_NOT_SUPPORTED = 0x106 +const ESP_ERR_TIMEOUT = 0x107 +const ESP_ERR_INVALID_RESPONSE = 0x108 +const ESP_ERR_INVALID_CRC = 0x109 +const ESP_ERR_INVALID_VERSION = 0x10A +const ESP_ERR_INVALID_MAC = 0x10B +const ESP_ERR_NOT_FINISHED = 0x10C +const ESP_ERR_NOT_ALLOWED = 0x10D +const ESP_ERR_WIFI_BASE = 0x3000 +const ESP_ERR_MESH_BASE = 0x4000 +const ESP_ERR_FLASH_BASE = 0x6000 +const ESP_ERR_HW_CRYPTO_BASE = 0xc000 +const ESP_ERR_MEMPROT_BASE = 0xd000 +const X__ASSERT_FUNC = "??" + +type EspErrT c.Int + +/** + * @brief Returns string for esp_err_t error codes + * + * This function finds the error code in a pre-generated lookup-table and + * returns its string representation. + * + * The function is generated by the Python script + * tools/gen_esp_err_to_name.py which should be run each time an esp_err_t + * error is modified, created or removed from the IDF project. + * + * @param code esp_err_t error code + * @return string error message + */ +// llgo:link EspErrT.EspErrToName C.esp_err_to_name +func (recv_ EspErrT) EspErrToName() *c.Char { + return nil +} + +/** + * @brief Returns string for esp_err_t and system error codes + * + * This function finds the error code in a pre-generated lookup-table of + * esp_err_t errors and returns its string representation. If the error code + * is not found then it is attempted to be found among system errors. + * + * The function is generated by the Python script + * tools/gen_esp_err_to_name.py which should be run each time an esp_err_t + * error is modified, created or removed from the IDF project. + * + * @param code esp_err_t error code + * @param[out] buf buffer where the error message should be written + * @param buflen Size of buffer buf. At most buflen bytes are written into the buf buffer (including the terminating null byte). + * @return buf containing the string error message + */ +// llgo:link EspErrT.EspErrToNameR C.esp_err_to_name_r +func (recv_ EspErrT) EspErrToNameR(buf *c.Char, buflen c.SizeT) *c.Char { + return nil +} + +/** @cond */ +// llgo:link EspErrT.X_espErrorCheckFailed C._esp_error_check_failed +func (recv_ EspErrT) X_espErrorCheckFailed(file *c.Char, line c.Int, function *c.Char, expression *c.Char) { +} + +// llgo:link EspErrT.X_espErrorCheckFailedWithoutAbort C._esp_error_check_failed_without_abort +func (recv_ EspErrT) X_espErrorCheckFailedWithoutAbort(file *c.Char, line c.Int, function *c.Char, expression *c.Char) { +} diff --git a/esp32/esp_etm.go b/esp32/esp_etm.go new file mode 100644 index 00000000..6c588039 --- /dev/null +++ b/esp32/esp_etm.go @@ -0,0 +1,154 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EspEtmChannelT struct { + Unused [8]uint8 +} +type EspEtmChannelHandleT *EspEtmChannelT + +type EspEtmEventT struct { + EventId c.Uint32T + TrigPeriph EtmTriggerPeripheralT + Del c.Pointer +} +type EspEtmEventHandleT *EspEtmEventT + +type EspEtmTaskT struct { + TaskId c.Uint32T + TrigPeriph EtmTriggerPeripheralT + Del c.Pointer +} +type EspEtmTaskHandleT *EspEtmTaskT + +/** + * @brief ETM channel configuration + */ + +type EspEtmChannelConfigT struct { + Flags EtmChanFlags +} + +type EtmChanFlags struct { + Unused [8]uint8 +} + +/** + * @brief Allocate an ETM channel + * + * @note The channel can later be freed by `esp_etm_del_channel` + * + * @param[in] config ETM channel configuration + * @param[out] ret_chan Returned ETM channel handle + * @return + * - ESP_OK: Allocate ETM channel successfully + * - ESP_ERR_INVALID_ARG: Allocate ETM channel failed because of invalid argument + * - ESP_ERR_NO_MEM: Allocate ETM channel failed because of out of memory + * - ESP_ERR_NOT_FOUND: Allocate ETM channel failed because all channels are used up and no more free one + * - ESP_FAIL: Allocate ETM channel failed because of other reasons + */ +// llgo:link (*EspEtmChannelConfigT).EspEtmNewChannel C.esp_etm_new_channel +func (recv_ *EspEtmChannelConfigT) EspEtmNewChannel(ret_chan *EspEtmChannelHandleT) EspErrT { + return 0 +} + +/** + * @brief Delete an ETM channel + * + * @param[in] chan ETM channel handle that created by `esp_etm_new_channel` + * @return + * - ESP_OK: Delete ETM channel successfully + * - ESP_ERR_INVALID_ARG: Delete ETM channel failed because of invalid argument + * - ESP_FAIL: Delete ETM channel failed because of other reasons + */ +//go:linkname EspEtmDelChannel C.esp_etm_del_channel +func EspEtmDelChannel(chan_ EspEtmChannelHandleT) EspErrT + +/** + * @brief Enable ETM channel + * + * @note This function will transit the channel state from init to enable. + * + * @param[in] chan ETM channel handle that created by `esp_etm_new_channel` + * @return + * - ESP_OK: Enable ETM channel successfully + * - ESP_ERR_INVALID_ARG: Enable ETM channel failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Enable ETM channel failed because the channel has been enabled already + * - ESP_FAIL: Enable ETM channel failed because of other reasons + */ +//go:linkname EspEtmChannelEnable C.esp_etm_channel_enable +func EspEtmChannelEnable(chan_ EspEtmChannelHandleT) EspErrT + +/** + * @brief Disable ETM channel + * + * @note This function will transit the channel state from enable to init. + * + * @param[in] chan ETM channel handle that created by `esp_etm_new_channel` + * @return + * - ESP_OK: Disable ETM channel successfully + * - ESP_ERR_INVALID_ARG: Disable ETM channel failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Disable ETM channel failed because the channel is not enabled yet + * - ESP_FAIL: Disable ETM channel failed because of other reasons + */ +//go:linkname EspEtmChannelDisable C.esp_etm_channel_disable +func EspEtmChannelDisable(chan_ EspEtmChannelHandleT) EspErrT + +/** + * @brief Connect an ETM event to an ETM task via a previously allocated ETM channel + * + * @note Setting the ETM event/task handle to NULL means to disconnect the channel from any event/task + * + * @param[in] chan ETM channel handle that created by `esp_etm_new_channel` + * @param[in] event ETM event handle obtained from a driver/peripheral, e.g. `xxx_new_etm_event` + * @param[in] task ETM task handle obtained from a driver/peripheral, e.g. `xxx_new_etm_task` + * @return + * - ESP_OK: Connect ETM event and task to the channel successfully + * - ESP_ERR_INVALID_ARG: Connect ETM event and task to the channel failed because of invalid argument + * - ESP_FAIL: Connect ETM event and task to the channel failed because of other reasons + */ +//go:linkname EspEtmChannelConnect C.esp_etm_channel_connect +func EspEtmChannelConnect(chan_ EspEtmChannelHandleT, event EspEtmEventHandleT, task EspEtmTaskHandleT) EspErrT + +/** + * @brief Delete ETM event + * + * @note Although the ETM event comes from various peripherals, we provide the same user API to delete the event handle seamlessly. + * + * @param[in] event ETM event handle obtained from a driver/peripheral, e.g. `xxx_new_etm_event` + * @return + * - ESP_OK: Delete ETM event successfully + * - ESP_ERR_INVALID_ARG: Delete ETM event failed because of invalid argument + * - ESP_FAIL: Delete ETM event failed because of other reasons + */ +//go:linkname EspEtmDelEvent C.esp_etm_del_event +func EspEtmDelEvent(event EspEtmEventHandleT) EspErrT + +/** + * @brief Delete ETM task + * + * @note Although the ETM task comes from various peripherals, we provide the same user API to delete the task handle seamlessly. + * + * @param[in] task ETM task handle obtained from a driver/peripheral, e.g. `xxx_new_etm_task` + * @return + * - ESP_OK: Delete ETM task successfully + * - ESP_ERR_INVALID_ARG: Delete ETM task failed because of invalid argument + * - ESP_FAIL: Delete ETM task failed because of other reasons + */ +//go:linkname EspEtmDelTask C.esp_etm_del_task +func EspEtmDelTask(task EspEtmTaskHandleT) EspErrT + +/** + * @brief Dump ETM channel usages to the given IO stream + * + * @param[in] out_stream IO stream (e.g. stdout) + * @return + * - ESP_OK: Dump ETM channel usages successfully + * - ESP_ERR_INVALID_ARG: Dump ETM channel usages failed because of invalid argument + * - ESP_FAIL: Dump ETM channel usages failed because of other reasons + */ +//go:linkname EspEtmDump C.esp_etm_dump +func EspEtmDump(out_stream *c.FILE) EspErrT diff --git a/esp32/esp_expression_with_stack.go b/esp32/esp_expression_with_stack.go new file mode 100644 index 00000000..35b76077 --- /dev/null +++ b/esp32/esp_expression_with_stack.go @@ -0,0 +1,35 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:type C +type SharedStackFunction func() + +/** + * @brief Calls function on user defined shared stack space + * + * After returning, the original stack is used again. + * + * @warning This function does minimal preparation of the provided piece of memory (\c stack). + * DO NOT do any of the following in \c function or any of its callees: + * * Use Thread-local storage + * * Use the Floating-point unit on ESP32-P4 + * * Use the AI co-processor on ESP32-P4 + * * Call vTaskDelete(NULL) (deleting the currently running task) + * Furthermore, backtraces will be wrong when called from \c function or any of its callees. + * The limitations are quite sever, so that we might deprecate this function in the future. + * If you have any use case which can only be implemented using this function, please open + * an issue on github. + * + * @param lock Mutex object to protect in case of shared stack + * @param stack Pointer to user allocated stack + * @param stack_size Size of current stack in bytes + * @param function pointer to the shared stack function to be executed + * @note if either lock, stack or stack size is invalid, the expression will + * be called using the current stack. + */ +//go:linkname EspExecuteSharedStackFunction C.esp_execute_shared_stack_function +func EspExecuteSharedStackFunction(lock SemaphoreHandleT, stack c.Pointer, stack_size c.SizeT, function SharedStackFunction) diff --git a/esp32/esp_fault.go b/esp32/esp_fault.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/esp_fault.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/esp_flash_err.go b/esp32/esp_flash_err.go new file mode 100644 index 00000000..0ec5a3e3 --- /dev/null +++ b/esp32/esp_flash_err.go @@ -0,0 +1,11 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ( + ESP_ERR_FLASH_SIZE_NOT_MATCH c.Int = 260 + ESP_ERR_FLASH_NO_RESPONSE c.Int = 264 +) diff --git a/esp32/esp_freertos_hooks.go b/esp32/esp_freertos_hooks.go new file mode 100644 index 00000000..abedecf1 --- /dev/null +++ b/esp32/esp_freertos_hooks.go @@ -0,0 +1,111 @@ +package freertos + +import _ "unsafe" + +// llgo:type C +type EspFreertosIdleCbT func() bool + +// llgo:type C +type EspFreertosTickCbT func() + +/** + * @brief Register a callback to be called from the specified core's idle hook. + * The callback should return true if it should be called by the idle hook + * once per interrupt (or FreeRTOS tick), and return false if it should + * be called repeatedly as fast as possible by the idle hook. + * + * @warning Idle callbacks MUST NOT, UNDER ANY CIRCUMSTANCES, CALL + * A FUNCTION THAT MIGHT BLOCK. + * + * @param[in] new_idle_cb Callback to be called + * @param[in] cpuid id of the core + * + * @return + * - ESP_OK: Callback registered to the specified core's idle hook + * - ESP_ERR_NO_MEM: No more space on the specified core's idle hook to register callback + * - ESP_ERR_INVALID_ARG: cpuid is invalid + */ +//go:linkname EspRegisterFreertosIdleHookForCpu C.esp_register_freertos_idle_hook_for_cpu +func EspRegisterFreertosIdleHookForCpu(new_idle_cb EspFreertosIdleCbT, cpuid UBaseTypeT) EspErrT + +/** + * @brief Register a callback to the idle hook of the core that calls this function. + * The callback should return true if it should be called by the idle hook + * once per interrupt (or FreeRTOS tick), and return false if it should + * be called repeatedly as fast as possible by the idle hook. + * + * @warning Idle callbacks MUST NOT, UNDER ANY CIRCUMSTANCES, CALL + * A FUNCTION THAT MIGHT BLOCK. + * + * @param[in] new_idle_cb Callback to be called + * + * @return + * - ESP_OK: Callback registered to the calling core's idle hook + * - ESP_ERR_NO_MEM: No more space on the calling core's idle hook to register callback + */ +//go:linkname EspRegisterFreertosIdleHook C.esp_register_freertos_idle_hook +func EspRegisterFreertosIdleHook(new_idle_cb EspFreertosIdleCbT) EspErrT + +/** + * @brief Register a callback to be called from the specified core's tick hook. + * + * @param[in] new_tick_cb Callback to be called + * @param[in] cpuid id of the core + * + * @return + * - ESP_OK: Callback registered to specified core's tick hook + * - ESP_ERR_NO_MEM: No more space on the specified core's tick hook to register the callback + * - ESP_ERR_INVALID_ARG: cpuid is invalid + */ +//go:linkname EspRegisterFreertosTickHookForCpu C.esp_register_freertos_tick_hook_for_cpu +func EspRegisterFreertosTickHookForCpu(new_tick_cb EspFreertosTickCbT, cpuid UBaseTypeT) EspErrT + +/** + * @brief Register a callback to be called from the calling core's tick hook. + * + * @param[in] new_tick_cb Callback to be called + * + * @return + * - ESP_OK: Callback registered to the calling core's tick hook + * - ESP_ERR_NO_MEM: No more space on the calling core's tick hook to register the callback + */ +//go:linkname EspRegisterFreertosTickHook C.esp_register_freertos_tick_hook +func EspRegisterFreertosTickHook(new_tick_cb EspFreertosTickCbT) EspErrT + +/** + * @brief Unregister an idle callback from the idle hook of the specified core + * + * @param[in] old_idle_cb Callback to be unregistered + * @param[in] cpuid id of the core + */ +//go:linkname EspDeregisterFreertosIdleHookForCpu C.esp_deregister_freertos_idle_hook_for_cpu +func EspDeregisterFreertosIdleHookForCpu(old_idle_cb EspFreertosIdleCbT, cpuid UBaseTypeT) + +/** + * @brief Unregister an idle callback. If the idle callback is registered to + * the idle hooks of both cores, the idle hook will be unregistered from + * both cores + * + * @param[in] old_idle_cb Callback to be unregistered + */ +//go:linkname EspDeregisterFreertosIdleHook C.esp_deregister_freertos_idle_hook +func EspDeregisterFreertosIdleHook(old_idle_cb EspFreertosIdleCbT) + +/** + * @brief Unregister a tick callback from the tick hook of the specified core + * + * @param[in] old_tick_cb Callback to be unregistered + * @param[in] cpuid id of the core + */ +//go:linkname EspDeregisterFreertosTickHookForCpu C.esp_deregister_freertos_tick_hook_for_cpu +func EspDeregisterFreertosTickHookForCpu(old_tick_cb EspFreertosTickCbT, cpuid UBaseTypeT) + +/** + * @brief Unregister a tick callback. If the tick callback is registered to the + * tick hooks of both cores, the tick hook will be unregistered from + * both cores + * + * @param[in] old_tick_cb Callback to be unregistered + */ +//go:linkname EspDeregisterFreertosTickHook C.esp_deregister_freertos_tick_hook +func EspDeregisterFreertosTickHook(old_tick_cb EspFreertosTickCbT) diff --git a/esp32/esp_gpio_reserve.go b/esp32/esp_gpio_reserve.go new file mode 100644 index 00000000..39193e4a --- /dev/null +++ b/esp32/esp_gpio_reserve.go @@ -0,0 +1,35 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Reserve the given GPIOs by mask, so they can't be used by others + * + * @param gpio_mask Mask of the GPIOs to be reserved + * @return The mask of the GPIOs that were already reserved before this call + */ +//go:linkname EspGpioReserve C.esp_gpio_reserve +func EspGpioReserve(gpio_mask c.Uint64T) c.Uint64T + +/** + * @brief Revoke the given GPIOs by mask, so they can be reused again by others + * + * @param gpio_mask Mask of the GPIOs to be revoked + * @return The mask of the GPIOs that were already reserved before this call + */ +//go:linkname EspGpioRevoke C.esp_gpio_revoke +func EspGpioRevoke(gpio_mask c.Uint64T) c.Uint64T + +/** + * @brief Check whether the given GPIOs are reserved + * + * @param gpio_mask Mask of the GPIOs to be checked + * @return + * - true Any of the given GPIO(s) is reserved + * - false Any of the given GPIO(s) is not reserved + */ +//go:linkname EspGpioIsReserved C.esp_gpio_is_reserved +func EspGpioIsReserved(gpio_mask c.Uint64T) bool diff --git a/esp32/esp_heap_caps.go b/esp32/esp_heap_caps.go new file mode 100644 index 00000000..4311dfe4 --- /dev/null +++ b/esp32/esp_heap_caps.go @@ -0,0 +1,446 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:type C +type EspAllocFailedHookT func(c.SizeT, c.Uint32T, *c.Char) + +/** + * @brief registers a callback function to be invoked if a memory allocation operation fails + * @param callback caller defined callback to be invoked + * @return ESP_OK if callback was registered. + */ +//go:linkname HeapCapsRegisterFailedAllocCallback C.heap_caps_register_failed_alloc_callback +func HeapCapsRegisterFailedAllocCallback(callback EspAllocFailedHookT) EspErrT + +/** + * @brief Allocate a chunk of memory which has the given capabilities + * + * Equivalent semantics to libc malloc(), for capability-aware memory. + * + * @param size Size, in bytes, of the amount of memory to allocate + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type + * of memory to be returned + * + * @return A pointer to the memory allocated on success, NULL on failure + */ +//go:linkname HeapCapsMalloc C.heap_caps_malloc +func HeapCapsMalloc(size c.SizeT, caps c.Uint32T) c.Pointer + +/** + * @brief Free memory previously allocated via heap_caps_malloc() or heap_caps_realloc(). + * + * Equivalent semantics to libc free(), for capability-aware memory. + * + * In IDF, ``free(p)`` is equivalent to ``heap_caps_free(p)``. + * + * @param ptr Pointer to memory previously returned from heap_caps_malloc() or heap_caps_realloc(). Can be NULL. + */ +//go:linkname HeapCapsFree C.heap_caps_free +func HeapCapsFree(ptr c.Pointer) + +/** + * @brief Reallocate memory previously allocated via heap_caps_malloc() or heap_caps_realloc(). + * + * Equivalent semantics to libc realloc(), for capability-aware memory. + * + * In IDF, ``realloc(p, s)`` is equivalent to ``heap_caps_realloc(p, s, MALLOC_CAP_8BIT)``. + * + * 'caps' parameter can be different to the capabilities that any original 'ptr' was allocated with. In this way, + * realloc can be used to "move" a buffer if necessary to ensure it meets a new set of capabilities. + * + * @param ptr Pointer to previously allocated memory, or NULL for a new allocation. + * @param size Size of the new buffer requested, or 0 to free the buffer. + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type + * of memory desired for the new allocation. + * + * @return Pointer to a new buffer of size 'size' with capabilities 'caps', or NULL if allocation failed. + */ +//go:linkname HeapCapsRealloc C.heap_caps_realloc +func HeapCapsRealloc(ptr c.Pointer, size c.SizeT, caps c.Uint32T) c.Pointer + +/** + * @brief Allocate an aligned chunk of memory which has the given capabilities + * + * Equivalent semantics to libc aligned_alloc(), for capability-aware memory. + * @param alignment How the pointer received needs to be aligned + * must be a power of two + * @param size Size, in bytes, of the amount of memory to allocate + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type + * of memory to be returned + * + * @return A pointer to the memory allocated on success, NULL on failure + * + * + */ +//go:linkname HeapCapsAlignedAlloc C.heap_caps_aligned_alloc +func HeapCapsAlignedAlloc(alignment c.SizeT, size c.SizeT, caps c.Uint32T) c.Pointer + +/** + * @brief Used to deallocate memory previously allocated with heap_caps_aligned_alloc + * + * @param ptr Pointer to the memory allocated + * @note This function is deprecated, please consider using heap_caps_free() instead + */ +//go:linkname HeapCapsAlignedFree C.heap_caps_aligned_free +func HeapCapsAlignedFree(ptr c.Pointer) + +/** + * @brief Allocate an aligned chunk of memory which has the given capabilities. The initialized value in the memory is set to zero. + * + * @param alignment How the pointer received needs to be aligned + * must be a power of two + * @param n Number of continuing chunks of memory to allocate + * @param size Size, in bytes, of a chunk of memory to allocate + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type + * of memory to be returned + * + * @return A pointer to the memory allocated on success, NULL on failure + * + */ +//go:linkname HeapCapsAlignedCalloc C.heap_caps_aligned_calloc +func HeapCapsAlignedCalloc(alignment c.SizeT, n c.SizeT, size c.SizeT, caps c.Uint32T) c.Pointer + +/** + * @brief Allocate a chunk of memory which has the given capabilities. The initialized value in the memory is set to zero. + * + * Equivalent semantics to libc calloc(), for capability-aware memory. + * + * In IDF, ``calloc(p)`` is equivalent to ``heap_caps_calloc(p, MALLOC_CAP_8BIT)``. + * + * @param n Number of continuing chunks of memory to allocate + * @param size Size, in bytes, of a chunk of memory to allocate + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type + * of memory to be returned + * + * @return A pointer to the memory allocated on success, NULL on failure + */ +//go:linkname HeapCapsCalloc C.heap_caps_calloc +func HeapCapsCalloc(n c.SizeT, size c.SizeT, caps c.Uint32T) c.Pointer + +/** + * @brief Get the total size of all the regions that have the given capabilities + * + * This function takes all regions capable of having the given capabilities allocated in them + * and adds up the total space they have. + * + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type + * of memory + * + * @return total size in bytes + */ +//go:linkname HeapCapsGetTotalSize C.heap_caps_get_total_size +func HeapCapsGetTotalSize(caps c.Uint32T) c.SizeT + +/** + * @brief Get the total free size of all the regions that have the given capabilities + * + * This function takes all regions capable of having the given capabilities allocated in them + * and adds up the free space they have. + * + * @note Note that because of heap fragmentation it is probably not possible to allocate a single block of memory + * of this size. Use heap_caps_get_largest_free_block() for this purpose. + + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type + * of memory + * + * @return Amount of free bytes in the regions + */ +//go:linkname HeapCapsGetFreeSize C.heap_caps_get_free_size +func HeapCapsGetFreeSize(caps c.Uint32T) c.SizeT + +/** + * @brief Get the total minimum free memory of all regions with the given capabilities + * + * This adds all the low watermarks of the regions capable of delivering the memory + * with the given capabilities. + * + * @note Note the result may be less than the global all-time minimum available heap of this kind, as "low watermarks" are + * tracked per-region. Individual regions' heaps may have reached their "low watermarks" at different points in time. However, + * this result still gives a "worst case" indication for all-time minimum free heap. + * + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type + * of memory + * + * @return Amount of free bytes in the regions + */ +//go:linkname HeapCapsGetMinimumFreeSize C.heap_caps_get_minimum_free_size +func HeapCapsGetMinimumFreeSize(caps c.Uint32T) c.SizeT + +/** + * @brief Get the largest free block of memory able to be allocated with the given capabilities. + * + * Returns the largest value of ``s`` for which ``heap_caps_malloc(s, caps)`` will succeed. + * + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type + * of memory + * + * @return Size of the largest free block in bytes. + */ +//go:linkname HeapCapsGetLargestFreeBlock C.heap_caps_get_largest_free_block +func HeapCapsGetLargestFreeBlock(caps c.Uint32T) c.SizeT + +/** + * @brief Start monitoring the value of minimum_free_bytes from the moment this + * function is called instead of from startup. + * + * @note This allows to detect local lows of the minimum_free_bytes value + * that wouldn't be detected otherwise. + * + * @return esp_err_t ESP_OK if the function executed properly + * ESP_FAIL if called when monitoring already active + */ +//go:linkname HeapCapsMonitorLocalMinimumFreeSizeStart C.heap_caps_monitor_local_minimum_free_size_start +func HeapCapsMonitorLocalMinimumFreeSizeStart() EspErrT + +/** + * @brief Stop monitoring the value of minimum_free_bytes. After this call + * the minimum_free_bytes value calculated from startup will be returned in + * heap_caps_get_info and heap_caps_get_minimum_free_size. + * + * @return esp_err_t ESP_OK if the function executed properly + * ESP_FAIL if called when monitoring not active + */ +//go:linkname HeapCapsMonitorLocalMinimumFreeSizeStop C.heap_caps_monitor_local_minimum_free_size_stop +func HeapCapsMonitorLocalMinimumFreeSizeStop() EspErrT + +/** + * @brief Get heap info for all regions with the given capabilities. + * + * Calls multi_heap_info() on all heaps which share the given capabilities. The information returned is an aggregate + * across all matching heaps. The meanings of fields are the same as defined for multi_heap_info_t, except that + * ``minimum_free_bytes`` has the same caveats described in heap_caps_get_minimum_free_size(). + * + * @param info Pointer to a structure which will be filled with relevant + * heap metadata. + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type + * of memory + * + */ +// llgo:link (*MultiHeapInfoT).HeapCapsGetInfo C.heap_caps_get_info +func (recv_ *MultiHeapInfoT) HeapCapsGetInfo(caps c.Uint32T) { +} + +/** + * @brief Print a summary of all memory with the given capabilities. + * + * Calls multi_heap_info on all heaps which share the given capabilities, and + * prints a two-line summary for each, then a total summary. + * + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type + * of memory + * + */ +//go:linkname HeapCapsPrintHeapInfo C.heap_caps_print_heap_info +func HeapCapsPrintHeapInfo(caps c.Uint32T) + +/** + * @brief Check integrity of all heap memory in the system. + * + * Calls multi_heap_check on all heaps. Optionally print errors if heaps are corrupt. + * + * Calling this function is equivalent to calling heap_caps_check_integrity + * with the caps argument set to MALLOC_CAP_INVALID. + * + * @param print_errors Print specific errors if heap corruption is found. + * + * @note Please increase the value of `CONFIG_ESP_INT_WDT_TIMEOUT_MS` when using this API + * with PSRAM enabled. + * + * @return True if all heaps are valid, False if at least one heap is corrupt. + */ +//go:linkname HeapCapsCheckIntegrityAll C.heap_caps_check_integrity_all +func HeapCapsCheckIntegrityAll(print_errors bool) bool + +/** + * @brief Check integrity of all heaps with the given capabilities. + * + * Calls multi_heap_check on all heaps which share the given capabilities. Optionally + * print errors if the heaps are corrupt. + * + * See also heap_caps_check_integrity_all to check all heap memory + * in the system and heap_caps_check_integrity_addr to check memory + * around a single address. + * + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type + * of memory + * @param print_errors Print specific errors if heap corruption is found. + * + * @note Please increase the value of `CONFIG_ESP_INT_WDT_TIMEOUT_MS` when using this API + * with PSRAM capability flag. + * + * @return True if all heaps are valid, False if at least one heap is corrupt. + */ +//go:linkname HeapCapsCheckIntegrity C.heap_caps_check_integrity +func HeapCapsCheckIntegrity(caps c.Uint32T, print_errors bool) bool + +/** + * @brief Check integrity of heap memory around a given address. + * + * This function can be used to check the integrity of a single region of heap memory, + * which contains the given address. + * + * This can be useful if debugging heap integrity for corruption at a known address, + * as it has a lower overhead than checking all heap regions. Note that if the corrupt + * address moves around between runs (due to timing or other factors) then this approach + * won't work, and you should call heap_caps_check_integrity or + * heap_caps_check_integrity_all instead. + * + * @note The entire heap region around the address is checked, not only the adjacent + * heap blocks. + * + * @param addr Address in memory. Check for corruption in region containing this address. + * @param print_errors Print specific errors if heap corruption is found. + * + * @return True if the heap containing the specified address is valid, + * False if at least one heap is corrupt or the address doesn't belong to a heap region. + */ +//go:linkname HeapCapsCheckIntegrityAddr C.heap_caps_check_integrity_addr +func HeapCapsCheckIntegrityAddr(addr c.IntptrT, print_errors bool) bool + +/** + * @brief Enable malloc() in external memory and set limit below which + * malloc() attempts are placed in internal memory. + * + * When external memory is in use, the allocation strategy is to initially try to + * satisfy smaller allocation requests with internal memory and larger requests + * with external memory. This sets the limit between the two, as well as generally + * enabling allocation in external memory. + * + * @param limit Limit, in bytes. + */ +//go:linkname HeapCapsMallocExtmemEnable C.heap_caps_malloc_extmem_enable +func HeapCapsMallocExtmemEnable(limit c.SizeT) + +/** + * @brief Allocate a chunk of memory as preference in decreasing order. + * + * @attention The variable parameters are bitwise OR of MALLOC_CAP_* flags indicating the type of memory. + * This API prefers to allocate memory with the first parameter. If failed, allocate memory with + * the next parameter. It will try in this order until allocating a chunk of memory successfully + * or fail to allocate memories with any of the parameters. + * + * @param size Size, in bytes, of the amount of memory to allocate + * @param num Number of variable parameters + * + * @return A pointer to the memory allocated on success, NULL on failure + */ +//go:linkname HeapCapsMallocPrefer C.heap_caps_malloc_prefer +func HeapCapsMallocPrefer(size c.SizeT, num c.SizeT, __llgo_va_list ...interface{}) c.Pointer + +/** + * @brief Reallocate a chunk of memory as preference in decreasing order. + * + * @param ptr Pointer to previously allocated memory, or NULL for a new allocation. + * @param size Size of the new buffer requested, or 0 to free the buffer. + * @param num Number of variable parameters + * + * @return Pointer to a new buffer of size 'size', or NULL if allocation failed. + */ +//go:linkname HeapCapsReallocPrefer C.heap_caps_realloc_prefer +func HeapCapsReallocPrefer(ptr c.Pointer, size c.SizeT, num c.SizeT, __llgo_va_list ...interface{}) c.Pointer + +/** + * @brief Allocate a chunk of memory as preference in decreasing order. + * + * @param n Number of continuing chunks of memory to allocate + * @param size Size, in bytes, of a chunk of memory to allocate + * @param num Number of variable parameters + * + * @return A pointer to the memory allocated on success, NULL on failure + */ +//go:linkname HeapCapsCallocPrefer C.heap_caps_calloc_prefer +func HeapCapsCallocPrefer(n c.SizeT, size c.SizeT, num c.SizeT, __llgo_va_list ...interface{}) c.Pointer + +/** + * @brief Dump the full structure of all heaps with matching capabilities. + * + * Prints a large amount of output to serial (because of locking limitations, + * the output bypasses stdout/stderr). For each (variable sized) block + * in each matching heap, the following output is printed on a single line: + * + * - Block address (the data buffer returned by malloc is 4 bytes after this + * if heap debugging is set to Basic, or 8 bytes otherwise). + * - Data size (the data size may be larger than the size requested by malloc, + * either due to heap fragmentation or because of heap debugging level). + * - Address of next block in the heap. + * - If the block is free, the address of the next free block is also printed. + * + * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type + * of memory + */ +//go:linkname HeapCapsDump C.heap_caps_dump +func HeapCapsDump(caps c.Uint32T) + +/** + * @brief Dump the full structure of all heaps. + * + * Covers all registered heaps. Prints a large amount of output to serial. + * + * Output is the same as for heap_caps_dump. + * + */ +//go:linkname HeapCapsDumpAll C.heap_caps_dump_all +func HeapCapsDumpAll() + +/** + * @brief Return the size that a particular pointer was allocated with. + * + * @param ptr Pointer to currently allocated heap memory. Must be a pointer value previously + * returned by heap_caps_malloc, malloc, calloc, etc. and not yet freed. + * + * @note The app will crash with an assertion failure if the pointer is not valid. + * + * @return Size of the memory allocated at this block. + * + */ +//go:linkname HeapCapsGetAllocatedSize C.heap_caps_get_allocated_size +func HeapCapsGetAllocatedSize(ptr c.Pointer) c.SizeT + +/** + * @brief Structure used to store heap related data passed to + * the walker callback function + */ + +type WalkerHeapInfo struct { + Start c.IntptrT + End c.IntptrT +} +type WalkerHeapIntoT WalkerHeapInfo + +/** + * @brief Structure used to store block related data passed to + * the walker callback function + */ + +type WalkerBlockInfo struct { + Ptr c.Pointer + Size c.SizeT + Used bool +} +type WalkerBlockInfoT WalkerBlockInfo + +// llgo:type C +type HeapCapsWalkerCbT func(WalkerHeapIntoT, WalkerBlockInfoT, c.Pointer) bool + +/** + * @brief Function called to walk through the heaps with the given set of capabilities + * + * @param caps The set of capabilities assigned to the heaps to walk through + * @param walker_func Callback called for each block of the heaps being traversed + * @param user_data Opaque pointer to user defined data + */ +//go:linkname HeapCapsWalk C.heap_caps_walk +func HeapCapsWalk(caps c.Uint32T, walker_func HeapCapsWalkerCbT, user_data c.Pointer) + +/** + * @brief Function called to walk through all heaps defined by the heap component + * + * @param walker_func Callback called for each block of the heaps being traversed + * @param user_data Opaque pointer to user defined data + */ +//go:linkname HeapCapsWalkAll C.heap_caps_walk_all +func HeapCapsWalkAll(walker_func HeapCapsWalkerCbT, user_data c.Pointer) diff --git a/esp32/esp_heap_caps_init.go b/esp32/esp_heap_caps_init.go new file mode 100644 index 00000000..1b761a86 --- /dev/null +++ b/esp32/esp_heap_caps_init.go @@ -0,0 +1,102 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Initialize the capability-aware heap allocator. + * + * This is called once in the IDF startup code. Do not call it + * at other times. + */ +//go:linkname HeapCapsInit C.heap_caps_init +func HeapCapsInit() + +/** + * @brief Enable heap(s) in memory regions where the startup stacks are located. + * + * On startup, the pro/app CPUs have a certain memory region they use as stack, so we + * cannot do allocations in the regions these stack frames are. When FreeRTOS is + * completely started, they do not use that memory anymore and heap(s) there can + * be enabled. + */ +//go:linkname HeapCapsEnableNonosStackHeaps C.heap_caps_enable_nonos_stack_heaps +func HeapCapsEnableNonosStackHeaps() + +/** +* @brief Add a region of memory to the collection of heaps at runtime. +* +* Most memory regions are defined in soc_memory_layout.c for the SoC, +* and are registered via heap_caps_init(). Some regions can't be used +* immediately and are later enabled via heap_caps_enable_nonos_stack_heaps(). +* +* Call this function to add a region of memory to the heap at some later time. +* +* This function does not consider any of the "reserved" regions or other data in soc_memory_layout, caller needs to +* consider this themselves. +* +* All memory within the region specified by start & end parameters must be otherwise unused. +* +* The capabilities of the newly registered memory will be determined by the start address, as looked up in the regions +* specified in soc_memory_layout.c. +* +* Use heap_caps_add_region_with_caps() to register a region with custom capabilities. +* +* @note Please refer to following example for memory regions allowed for addition to heap based on an existing region +* (address range for demonstration purpose only): +@verbatim + Existing region: 0x1000 <-> 0x3000 + New region: 0x1000 <-> 0x3000 (Allowed) + New region: 0x1000 <-> 0x2000 (Allowed) + New region: 0x0000 <-> 0x1000 (Allowed) + New region: 0x3000 <-> 0x4000 (Allowed) + New region: 0x0000 <-> 0x2000 (NOT Allowed) + New region: 0x0000 <-> 0x4000 (NOT Allowed) + New region: 0x1000 <-> 0x4000 (NOT Allowed) + New region: 0x2000 <-> 0x4000 (NOT Allowed) +@endverbatim +* +* @param start Start address of new region. +* @param end End address of new region. +* +* @return ESP_OK on success, ESP_ERR_INVALID_ARG if a parameter is invalid, ESP_ERR_NOT_FOUND if the +* specified start address doesn't reside in a known region, or any error returned by heap_caps_add_region_with_caps(). +*/ +//go:linkname HeapCapsAddRegion C.heap_caps_add_region +func HeapCapsAddRegion(start c.IntptrT, end c.IntptrT) EspErrT + +/** +* @brief Add a region of memory to the collection of heaps at runtime, with custom capabilities. +* +* Similar to heap_caps_add_region(), only custom memory capabilities are specified by the caller. +* +* @note Please refer to following example for memory regions allowed for addition to heap based on an existing region +* (address range for demonstration purpose only): +@verbatim + Existing region: 0x1000 <-> 0x3000 + New region: 0x1000 <-> 0x3000 (Allowed) + New region: 0x1000 <-> 0x2000 (Allowed) + New region: 0x0000 <-> 0x1000 (Allowed) + New region: 0x3000 <-> 0x4000 (Allowed) + New region: 0x0000 <-> 0x2000 (NOT Allowed) + New region: 0x0000 <-> 0x4000 (NOT Allowed) + New region: 0x1000 <-> 0x4000 (NOT Allowed) + New region: 0x2000 <-> 0x4000 (NOT Allowed) +@endverbatim +* +* @param caps Ordered array of capability masks for the new region, in order of priority. Must have length +* SOC_MEMORY_TYPE_NO_PRIOS. Does not need to remain valid after the call returns. +* @param start Start address of new region. +* @param end End address of new region. +* +* @return +* - ESP_OK on success +* - ESP_ERR_INVALID_ARG if a parameter is invalid +* - ESP_ERR_NO_MEM if no memory to register new heap. +* - ESP_ERR_INVALID_SIZE if the memory region is too small to fit a heap +* - ESP_FAIL if region overlaps the start and/or end of an existing region +*/ +//go:linkname HeapCapsAddRegionWithCaps C.heap_caps_add_region_with_caps +func HeapCapsAddRegionWithCaps(caps *c.Uint32T, start c.IntptrT, end c.IntptrT) EspErrT diff --git a/esp32/esp_heap_trace.go b/esp32/esp_heap_trace.go new file mode 100644 index 00000000..e1c56852 --- /dev/null +++ b/esp32/esp_heap_trace.go @@ -0,0 +1,194 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const CONFIG_HEAP_TRACING_STACK_DEPTH = 0 + +type HeapTraceModeT c.Int + +const ( + HEAP_TRACE_ALL HeapTraceModeT = 0 + HEAP_TRACE_LEAKS HeapTraceModeT = 1 +) + +/** + * @brief Trace record data type. Stores information about an allocated region of memory. + */ + +type HeapTraceRecordT struct { + Ccount c.Uint32T + Address c.Pointer + Size c.SizeT + AllocedBy [0]c.Pointer + FreedBy [0]c.Pointer +} + +/** + * @brief Stores information about the result of a heap trace. + */ + +type HeapTraceSummaryT struct { + Mode HeapTraceModeT + TotalAllocations c.SizeT + TotalFrees c.SizeT + Count c.SizeT + Capacity c.SizeT + HighWaterMark c.SizeT + HasOverflowed c.SizeT +} + +/** + * @brief Initialise heap tracing in standalone mode. + * + * This function must be called before any other heap tracing functions. + * + * To disable heap tracing and allow the buffer to be freed, stop tracing and then call heap_trace_init_standalone(NULL, 0); + * + * @param record_buffer Provide a buffer to use for heap trace data. + * Note: External RAM is allowed, but it prevents recording allocations made from ISR's. + * @param num_records Size of the heap trace buffer, as number of record structures. + * @return + * - ESP_ERR_NOT_SUPPORTED Project was compiled without heap tracing enabled in menuconfig. + * - ESP_ERR_INVALID_STATE Heap tracing is currently in progress. + * - ESP_OK Heap tracing initialised successfully. + */ +// llgo:link (*HeapTraceRecordT).HeapTraceInitStandalone C.heap_trace_init_standalone +func (recv_ *HeapTraceRecordT) HeapTraceInitStandalone(num_records c.SizeT) EspErrT { + return 0 +} + +/** + * @brief Initialise heap tracing in host-based mode. + * + * This function must be called before any other heap tracing functions. + * + * @return + * - ESP_ERR_INVALID_STATE Heap tracing is currently in progress. + * - ESP_OK Heap tracing initialised successfully. + */ +//go:linkname HeapTraceInitTohost C.heap_trace_init_tohost +func HeapTraceInitTohost() EspErrT + +/** + * @brief Start heap tracing. All heap allocations & frees will be traced, until heap_trace_stop() is called. + * + * @note heap_trace_init_standalone() must be called to provide a valid buffer, before this function is called. + * + * @note Calling this function while heap tracing is running will reset the heap trace state and continue tracing. + * + * @param mode Mode for tracing. + * - HEAP_TRACE_ALL means all heap allocations and frees are traced. + * - HEAP_TRACE_LEAKS means only suspected memory leaks are traced. (When memory is freed, the record is removed from the trace buffer.) + * @return + * - ESP_ERR_NOT_SUPPORTED Project was compiled without heap tracing enabled in menuconfig. + * - ESP_ERR_INVALID_STATE A non-zero-length buffer has not been set via heap_trace_init_standalone(). + * - ESP_OK Tracing is started. + */ +// llgo:link HeapTraceModeT.HeapTraceStart C.heap_trace_start +func (recv_ HeapTraceModeT) HeapTraceStart() EspErrT { + return 0 +} + +/** + * @brief Stop heap tracing. + * + * @return + * - ESP_ERR_NOT_SUPPORTED Project was compiled without heap tracing enabled in menuconfig. + * - ESP_ERR_INVALID_STATE Heap tracing was not in progress. + * - ESP_OK Heap tracing stopped. + */ +//go:linkname HeapTraceStop C.heap_trace_stop +func HeapTraceStop() EspErrT + +/** + * @brief Pause heap tracing of allocations. + * + * @note This function puts the heap tracing in the state where the new allocations + * will no longer be traced but the free will still be. This can be used to e.g., + * strategically monitor a set of allocations to make sure each of them will get freed + * without polluting the list of records with unwanted allocations. + * + * @return + * - ESP_ERR_NOT_SUPPORTED Project was compiled without heap tracing enabled in menuconfig. + * - ESP_ERR_INVALID_STATE Heap tracing was not in progress. + * - ESP_OK Heap tracing paused. + */ +//go:linkname HeapTraceAllocPause C.heap_trace_alloc_pause +func HeapTraceAllocPause() EspErrT + +/** + * @brief Resume heap tracing which was previously stopped. + * + * Unlike heap_trace_start(), this function does not clear the + * buffer of any pre-existing trace records. + * + * The heap trace mode is the same as when heap_trace_start() was + * last called (or HEAP_TRACE_ALL if heap_trace_start() was never called). + * + * @return + * - ESP_ERR_NOT_SUPPORTED Project was compiled without heap tracing enabled in menuconfig. + * - ESP_ERR_INVALID_STATE Heap tracing was already started. + * - ESP_OK Heap tracing resumed. + */ +//go:linkname HeapTraceResume C.heap_trace_resume +func HeapTraceResume() EspErrT + +/** + * @brief Return number of records in the heap trace buffer + * + * It is safe to call this function while heap tracing is running. + */ +//go:linkname HeapTraceGetCount C.heap_trace_get_count +func HeapTraceGetCount() c.SizeT + +/** + * @brief Return a raw record from the heap trace buffer + * + * @note It is safe to call this function while heap tracing is + * running, however in HEAP_TRACE_LEAK mode record indexing may + * skip entries unless heap tracing is stopped first. + * + * @param index Index (zero-based) of the record to return. + * @param[out] record Record where the heap trace record will be copied. + * @return + * - ESP_ERR_NOT_SUPPORTED Project was compiled without heap tracing enabled in menuconfig. + * - ESP_ERR_INVALID_STATE Heap tracing was not initialised. + * - ESP_ERR_INVALID_ARG Index is out of bounds for current heap trace record count. + * - ESP_OK Record returned successfully. + */ +//go:linkname HeapTraceGet C.heap_trace_get +func HeapTraceGet(index c.SizeT, record *HeapTraceRecordT) EspErrT + +/** + * @brief Dump heap trace record data to stdout + * + * @note It is safe to call this function while heap tracing is + * running, however in HEAP_TRACE_LEAK mode the dump may skip + * entries unless heap tracing is stopped first. + */ +//go:linkname HeapTraceDump C.heap_trace_dump +func HeapTraceDump() + +/** + * @brief Dump heap trace from the memory of the capabilities passed as parameter. + * + * @param caps Capability(ies) of the memory from which to dump the trace. + * Set MALLOC_CAP_INTERNAL to dump heap trace data from internal memory. + * Set MALLOC_CAP_SPIRAM to dump heap trace data from PSRAM. + * Set both to dump both heap trace data. + */ +//go:linkname HeapTraceDumpCaps C.heap_trace_dump_caps +func HeapTraceDumpCaps(caps c.Uint32T) + +/** + * @brief Get summary information about the result of a heap trace + * + * @note It is safe to call this function while heap tracing is running. + */ +// llgo:link (*HeapTraceSummaryT).HeapTraceSummary C.heap_trace_summary +func (recv_ *HeapTraceSummaryT) HeapTraceSummary() EspErrT { + return 0 +} diff --git a/esp32/esp_hmac.go b/esp32/esp_hmac.go new file mode 100644 index 00000000..2c88eab6 --- /dev/null +++ b/esp32/esp_hmac.go @@ -0,0 +1,80 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type HmacKeyIdT c.Int + +const ( + HMAC_KEY0 HmacKeyIdT = 0 + HMAC_KEY1 HmacKeyIdT = 1 + HMAC_KEY2 HmacKeyIdT = 2 + HMAC_KEY3 HmacKeyIdT = 3 + HMAC_KEY4 HmacKeyIdT = 4 + HMAC_KEY5 HmacKeyIdT = 5 + HMAC_KEY_MAX HmacKeyIdT = 6 +) + +/** + * @brief + * Calculate the HMAC of a given message. + * + * Calculate the HMAC \c hmac of a given message \c message with length \c message_len. + * SHA256 is used for the calculation. + * + * @note Uses the HMAC peripheral in "upstream" mode. + * + * @param key_id Determines which of the 6 key blocks in the efuses should be used for the HMAC calculation. + * The corresponding purpose field of the key block in the efuse must be set to the HMAC upstream purpose value. + * @param message the message for which to calculate the HMAC + * @param message_len message length + * return ESP_ERR_INVALID_STATE if unsuccessful + * @param [out] hmac the hmac result; the buffer behind the provided pointer must be a writeable buffer of 32 bytes + * + * @return + * * ESP_OK, if the calculation was successful, + * * ESP_ERR_INVALID_ARG if message or hmac is a nullptr or if key_id out of range + * * ESP_FAIL, if the hmac calculation failed + */ +// llgo:link HmacKeyIdT.EspHmacCalculate C.esp_hmac_calculate +func (recv_ HmacKeyIdT) EspHmacCalculate(message c.Pointer, message_len c.SizeT, hmac *c.Uint8T) EspErrT { + return 0 +} + +/** + * @brief Use HMAC peripheral in Downstream mode to re-enable the JTAG, if it is not permanently disabled by HW. + * In downstream mode, HMAC calculations performed by peripheral are used internally and not provided back to user. + * + * @param key_id Determines which of the 6 key blocks in the efuses should be used for the HMAC calculation. + * The corresponding purpose field of the key block in the efuse must be set to HMAC downstream purpose. + * + * @param token Pre calculated HMAC value of the 32-byte 0x00 using SHA-256 and the known private HMAC key. The key is already + * programmed to a eFuse key block. The key block number is provided as the first parameter to this function. + * + * @return + * * ESP_OK, if the key_purpose of the key_id matches to HMAC downstread mode, + * The API returns success even if calculated HMAC does not match with the provided token. + * However, The JTAG will be re-enabled only if the calculated HMAC value matches with provided token, + * otherwise JTAG will remain disabled. + * * ESP_FAIL, if the key_purpose of the key_id is not set to HMAC downstream purpose + * or JTAG is permanently disabled by EFUSE_HARD_DIS_JTAG eFuse parameter. + * * ESP_ERR_INVALID_ARG, invalid input arguments + * + * @note Return value of the API does not indicate the JTAG status. + */ +// llgo:link HmacKeyIdT.EspHmacJtagEnable C.esp_hmac_jtag_enable +func (recv_ HmacKeyIdT) EspHmacJtagEnable(token *c.Uint8T) EspErrT { + return 0 +} + +/** + * @brief Disable the JTAG which might be enabled using the HMAC downstream mode. This function just clears the result generated + * by calling esp_hmac_jtag_enable() API. + * + * @return + * * ESP_OK return ESP_OK after writing the HMAC_SET_INVALIDATE_JTAG_REG with value 1. + */ +//go:linkname EspHmacJtagDisable C.esp_hmac_jtag_disable +func EspHmacJtagDisable() EspErrT diff --git a/esp32/esp_idf_version.go b/esp32/esp_idf_version.go new file mode 100644 index 00000000..4c9566e9 --- /dev/null +++ b/esp32/esp_idf_version.go @@ -0,0 +1,23 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ESP_IDF_VERSION_MAJOR = 5 +const ESP_IDF_VERSION_MINOR = 4 +const ESP_IDF_VERSION_PATCH = 2 + +/** + * Return full IDF version string, same as 'git describe' output. + * + * @note If you are printing the ESP-IDF version in a log file or other information, + * this function provides more information than using the numerical version macros. + * For example, numerical version macros don't differentiate between development, + * pre-release and release versions, but the output of this function does. + * + * @return constant string from IDF_VER + */ +//go:linkname EspGetIdfVersion C.esp_get_idf_version +func EspGetIdfVersion() *c.Char diff --git a/esp32/esp_int_wdt.go b/esp32/esp_int_wdt.go new file mode 100644 index 00000000..622e98ac --- /dev/null +++ b/esp32/esp_int_wdt.go @@ -0,0 +1,23 @@ +package freertos + +import _ "unsafe" + +/** + * @brief Initialize the non-CPU-specific parts of interrupt watchdog. + * + * This function is automatically called during application startup if the + * interrupt watchdog is enabled in menuconfig. + */ +//go:linkname EspIntWdtInit C.esp_int_wdt_init +func EspIntWdtInit() + +/** + * @brief Enable the interrupt watchdog on the current CPU. + * + * This function is automatically called during application startup for each CPU + * that has enabled the interrupt watchdog in menuconfig. + * + * @note esp_int_wdt_init() must be called first before calling this function + */ +//go:linkname EspIntWdtCpuInit C.esp_int_wdt_cpu_init +func EspIntWdtCpuInit() diff --git a/esp32/esp_interface.go b/esp32/esp_interface.go new file mode 100644 index 00000000..c8f953c5 --- /dev/null +++ b/esp32/esp_interface.go @@ -0,0 +1,16 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EspInterfaceT c.Int + +const ( + ESP_IF_WIFI_STA EspInterfaceT = 0 + ESP_IF_WIFI_AP EspInterfaceT = 1 + ESP_IF_WIFI_NAN EspInterfaceT = 2 + ESP_IF_ETH EspInterfaceT = 3 + ESP_IF_MAX EspInterfaceT = 4 +) diff --git a/esp32/esp_intr_alloc.go b/esp32/esp_intr_alloc.go new file mode 100644 index 00000000..474bcbb8 --- /dev/null +++ b/esp32/esp_intr_alloc.go @@ -0,0 +1,248 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Mark an interrupt as a shared interrupt + * + * This will mark a certain interrupt on the specified CPU as + * an interrupt that can be used to hook shared interrupt handlers + * to. + * + * @param intno The number of the interrupt (0-31) + * @param cpu CPU on which the interrupt should be marked as shared (0 or 1) + * @param is_in_iram Shared interrupt is for handlers that reside in IRAM and + * the int can be left enabled while the flash cache is disabled. + * + * @return ESP_ERR_INVALID_ARG if cpu or intno is invalid + * ESP_OK otherwise + */ +//go:linkname EspIntrMarkShared C.esp_intr_mark_shared +func EspIntrMarkShared(intno c.Int, cpu c.Int, is_in_iram bool) EspErrT + +/** + * @brief Reserve an interrupt to be used outside of this framework + * + * This will mark a certain interrupt on the specified CPU as + * reserved, not to be allocated for any reason. + * + * @param intno The number of the interrupt (0-31) + * @param cpu CPU on which the interrupt should be marked as shared (0 or 1) + * + * @return ESP_ERR_INVALID_ARG if cpu or intno is invalid + * ESP_OK otherwise + */ +//go:linkname EspIntrReserve C.esp_intr_reserve +func EspIntrReserve(intno c.Int, cpu c.Int) EspErrT + +/** + * @brief Allocate an interrupt with the given parameters. + * + * This finds an interrupt that matches the restrictions as given in the flags + * parameter, maps the given interrupt source to it and hooks up the given + * interrupt handler (with optional argument) as well. If needed, it can return + * a handle for the interrupt as well. + * + * The interrupt will always be allocated on the core that runs this function. + * + * If ESP_INTR_FLAG_IRAM flag is used, and handler address is not in IRAM or + * RTC_FAST_MEM, then ESP_ERR_INVALID_ARG is returned. + * + * @param source The interrupt source. One of the ETS_*_INTR_SOURCE interrupt mux + * sources, as defined in soc/soc.h, or one of the internal + * ETS_INTERNAL_*_INTR_SOURCE sources as defined in this header. + * @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the + * choice of interrupts that this routine can choose from. If this value + * is 0, it will default to allocating a non-shared interrupt of level + * 1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared + * interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return + * from this function with the interrupt disabled. + * @param handler The interrupt handler. Must be NULL when an interrupt of level >3 + * is requested, because these types of interrupts aren't C-callable. + * @param arg Optional argument for passed to the interrupt handler + * @param ret_handle Pointer to an intr_handle_t to store a handle that can later be + * used to request details or free the interrupt. Can be NULL if no handle + * is required. + * + * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid. + * ESP_ERR_NOT_FOUND No free interrupt found with the specified flags + * ESP_OK otherwise + */ +//go:linkname EspIntrAlloc C.esp_intr_alloc +func EspIntrAlloc(source c.Int, flags c.Int, handler IntrHandlerT, arg c.Pointer, ret_handle *IntrHandleT) EspErrT + +/** + * @brief Allocate an interrupt with the given parameters. + * + * + * This essentially does the same as esp_intr_alloc, but allows specifying a register and mask + * combo. For shared interrupts, the handler is only called if a read from the specified + * register, ANDed with the mask, returns non-zero. By passing an interrupt status register + * address and a fitting mask, this can be used to accelerate interrupt handling in the case + * a shared interrupt is triggered; by checking the interrupt statuses first, the code can + * decide which ISRs can be skipped + * + * @param source The interrupt source. One of the ETS_*_INTR_SOURCE interrupt mux + * sources, as defined in soc/soc.h, or one of the internal + * ETS_INTERNAL_*_INTR_SOURCE sources as defined in this header. + * @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the + * choice of interrupts that this routine can choose from. If this value + * is 0, it will default to allocating a non-shared interrupt of level + * 1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared + * interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return + * from this function with the interrupt disabled. + * @param intrstatusreg The address of an interrupt status register + * @param intrstatusmask A mask. If a read of address intrstatusreg has any of the bits + * that are 1 in the mask set, the ISR will be called. If not, it will be + * skipped. + * @param handler The interrupt handler. Must be NULL when an interrupt of level >3 + * is requested, because these types of interrupts aren't C-callable. + * @param arg Optional argument for passed to the interrupt handler + * @param ret_handle Pointer to an intr_handle_t to store a handle that can later be + * used to request details or free the interrupt. Can be NULL if no handle + * is required. + * + * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid. + * ESP_ERR_NOT_FOUND No free interrupt found with the specified flags + * ESP_OK otherwise + */ +//go:linkname EspIntrAllocIntrstatus C.esp_intr_alloc_intrstatus +func EspIntrAllocIntrstatus(source c.Int, flags c.Int, intrstatusreg c.Uint32T, intrstatusmask c.Uint32T, handler IntrHandlerT, arg c.Pointer, ret_handle *IntrHandleT) EspErrT + +/** + * @brief Disable and free an interrupt. + * + * Use an interrupt handle to disable the interrupt and release the resources associated with it. + * If the current core is not the core that registered this interrupt, this routine will be assigned to + * the core that allocated this interrupt, blocking and waiting until the resource is successfully released. + * + * @note + * When the handler shares its source with other handlers, the interrupt status + * bits it's responsible for should be managed properly before freeing it. see + * ``esp_intr_disable`` for more details. Please do not call this function in ``esp_ipc_call_blocking``. + * + * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus + * + * @return ESP_ERR_INVALID_ARG the handle is NULL + * ESP_FAIL failed to release this handle + * ESP_OK otherwise + */ +//go:linkname EspIntrFree C.esp_intr_free +func EspIntrFree(handle IntrHandleT) EspErrT + +/** + * @brief Get CPU number an interrupt is tied to + * + * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus + * + * @return The core number where the interrupt is allocated + */ +//go:linkname EspIntrGetCpu C.esp_intr_get_cpu +func EspIntrGetCpu(handle IntrHandleT) c.Int + +/** + * @brief Get the allocated interrupt for a certain handle + * + * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus + * + * @return The interrupt number + */ +//go:linkname EspIntrGetIntno C.esp_intr_get_intno +func EspIntrGetIntno(handle IntrHandleT) c.Int + +/** + * @brief Disable the interrupt associated with the handle + * + * @note + * 1. For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the + * CPU the interrupt is allocated on. Other interrupts have no such restriction. + * 2. When several handlers sharing a same interrupt source, interrupt status bits, which are + * handled in the handler to be disabled, should be masked before the disabling, or handled + * in other enabled interrupts properly. Miss of interrupt status handling will cause infinite + * interrupt calls and finally system crash. + * + * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus + * + * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid. + * ESP_OK otherwise + */ +//go:linkname EspIntrDisable C.esp_intr_disable +func EspIntrDisable(handle IntrHandleT) EspErrT + +/** + * @brief Enable the interrupt associated with the handle + * + * @note For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the + * CPU the interrupt is allocated on. Other interrupts have no such restriction. + * + * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus + * + * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid. + * ESP_OK otherwise + */ +//go:linkname EspIntrEnable C.esp_intr_enable +func EspIntrEnable(handle IntrHandleT) EspErrT + +/** + * @brief Set the "in IRAM" status of the handler. + * + * @note Does not work on shared interrupts. + * + * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus + * @param is_in_iram Whether the handler associated with this handle resides in IRAM. + * Handlers residing in IRAM can be called when cache is disabled. + * + * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid. + * ESP_OK otherwise + */ +//go:linkname EspIntrSetInIram C.esp_intr_set_in_iram +func EspIntrSetInIram(handle IntrHandleT, is_in_iram bool) EspErrT + +/** + * @brief Disable interrupts that aren't specifically marked as running from IRAM + */ +//go:linkname EspIntrNoniramDisable C.esp_intr_noniram_disable +func EspIntrNoniramDisable() + +/** + * @brief Re-enable interrupts disabled by esp_intr_noniram_disable + */ +//go:linkname EspIntrNoniramEnable C.esp_intr_noniram_enable +func EspIntrNoniramEnable() + +/** + * @brief enable the interrupt source based on its number + * @param inum interrupt number from 0 to 31 + */ +//go:linkname EspIntrEnableSource C.esp_intr_enable_source +func EspIntrEnableSource(inum c.Int) + +/** + * @brief disable the interrupt source based on its number + * @param inum interrupt number from 0 to 31 + */ +//go:linkname EspIntrDisableSource C.esp_intr_disable_source +func EspIntrDisableSource(inum c.Int) + +/** + * @brief Dump the status of allocated interrupts + * @param stream The stream to dump to, if NULL then stdout is used + * @return ESP_OK on success + */ +//go:linkname EspIntrDump C.esp_intr_dump +func EspIntrDump(stream *c.FILE) EspErrT + +/** + * @brief Check if the given pointer is in the safe ISR area. + * In other words, make sure that the pointer's content is accessible at + * any time, regardless of the cache status + * + * @param ptr Pointer to check + * + * @return true if `ptr` points to ISR area, false else + */ +//go:linkname EspIntrPtrInIsrRegion C.esp_intr_ptr_in_isr_region +func EspIntrPtrInIsrRegion(ptr c.Pointer) bool diff --git a/esp32/esp_intr_types.go b/esp32/esp_intr_types.go new file mode 100644 index 00000000..10e9219d --- /dev/null +++ b/esp32/esp_intr_types.go @@ -0,0 +1,21 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:type C +type IntrHandlerT func(c.Pointer) + +type IntrHandleDataT struct { + Unused [8]uint8 +} +type IntrHandleT *IntrHandleDataT +type EspIntrCpuAffinityT c.Int + +const ( + ESP_INTR_CPU_AFFINITY_AUTO EspIntrCpuAffinityT = 0 + ESP_INTR_CPU_AFFINITY_0 EspIntrCpuAffinityT = 1 + ESP_INTR_CPU_AFFINITY_1 EspIntrCpuAffinityT = 2 +) diff --git a/esp32/esp_ipc.go b/esp32/esp_ipc.go new file mode 100644 index 00000000..217e7cbc --- /dev/null +++ b/esp32/esp_ipc.go @@ -0,0 +1,79 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:type C +type EspIpcFuncT func(c.Pointer) + +/** + * @brief Execute a callback on a given CPU + * + * Execute a given callback on a particular CPU. The callback must be of type "esp_ipc_func_t" and will be invoked in + * the context of the target CPU's IPC task. + * + * - This function will block the target CPU's IPC task has begun execution of the callback + * - If another IPC call is ongoing, this function will block until the ongoing IPC call completes + * - The stack size of the IPC task can be configured via the CONFIG_ESP_IPC_TASK_STACK_SIZE option + * + * @note In single-core mode, returns ESP_ERR_INVALID_ARG for cpu_id 1. + * + * @param[in] cpu_id CPU where the given function should be executed (0 or 1) + * @param[in] func Pointer to a function of type void func(void* arg) to be executed + * @param[in] arg Arbitrary argument of type void* to be passed into the function + * + * @return + * - ESP_ERR_INVALID_ARG if cpu_id is invalid + * - ESP_ERR_INVALID_STATE if the FreeRTOS scheduler is not running + * - ESP_OK otherwise + */ +//go:linkname EspIpcCall C.esp_ipc_call +func EspIpcCall(cpu_id c.Uint32T, func_ EspIpcFuncT, arg c.Pointer) EspErrT + +/** + * @brief Execute a callback on a given CPU until and block until it completes + * + * This function is identical to esp_ipc_call() except that this function will block until the execution of the callback + * completes. + * + * @note In single-core mode, returns ESP_ERR_INVALID_ARG for cpu_id 1. + * + * @param[in] cpu_id CPU where the given function should be executed (0 or 1) + * @param[in] func Pointer to a function of type void func(void* arg) to be executed + * @param[in] arg Arbitrary argument of type void* to be passed into the function + * + * @return + * - ESP_ERR_INVALID_ARG if cpu_id is invalid + * - ESP_ERR_INVALID_STATE if the FreeRTOS scheduler is not running + * - ESP_OK otherwise + */ +//go:linkname EspIpcCallBlocking C.esp_ipc_call_blocking +func EspIpcCallBlocking(cpu_id c.Uint32T, func_ EspIpcFuncT, arg c.Pointer) EspErrT + +/** + * @brief Execute a callback on a given CPU without any blocking operations for the caller + * + * Since it does not have any blocking operations it is suitable to be run from interrupts + * or even when the Scheduler on the current core is suspended. + * + * The function: + * - does not wait for the callback to begin or complete execution, + * - does not change the IPC priority. + * The function returns after sending a notification to the IPC task to execute the callback. + * + * @param[in] cpu_id CPU where the given function should be executed (0 or 1) + * @param[in] func Pointer to a function of type void func(void* arg) to be executed + * @param[in] arg Arbitrary argument of type void* to be passed into the function + * + * @return + * - ESP_ERR_INVALID_ARG if cpu_id is invalid + * - ESP_ERR_INVALID_STATE 1. IPC tasks have not been initialized yet, + * 2. cpu_id requests IPC on the current core, but the FreeRTOS scheduler is not running on it + * (the IPC task cannot be executed). + * - ESP_FAIL IPC is busy due to a previous call was not completed. + * - ESP_OK otherwise + */ +//go:linkname EspIpcCallNonblocking C.esp_ipc_call_nonblocking +func EspIpcCallNonblocking(cpu_id c.Uint32T, func_ EspIpcFuncT, arg c.Pointer) EspErrT diff --git a/esp32/esp_ipc_isr.go b/esp32/esp_ipc_isr.go new file mode 100644 index 00000000..70f361a2 --- /dev/null +++ b/esp32/esp_ipc_isr.go @@ -0,0 +1,120 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:type C +type EspIpcIsrFuncT func(c.Pointer) + +/** + * @brief Execute an ISR callback on the other CPU + * + * Execute a given callback on the other CPU in the context of a High Priority Interrupt. + * + * - This function will busy-wait in a critical section until the other CPU has started execution of the callback + * - The callback must be written: + * - in assembly for XTENSA chips (such as ESP32, ESP32S3). + * The function is invoked using a CALLX0 instruction and can use only a2, a3, a4 registers. + * See :doc:`IPC in Interrupt Context ` doc for more details. + * - in C or assembly for RISCV chips (such as ESP32P4). + * + * @note This function is not available in single-core mode. + * + * @param[in] func Pointer to a function of type void func(void* arg) to be executed + * @param[in] arg Arbitrary argument of type void* to be passed into the function + */ +//go:linkname EspIpcIsrCall C.esp_ipc_isr_call +func EspIpcIsrCall(func_ EspIpcIsrFuncT, arg c.Pointer) + +/** + * @brief Execute an ISR callback on the other CPU and busy-wait until it completes + * + * This function is identical to esp_ipc_isr_call() except that this function will busy-wait until the execution of + * the callback completes. + * + * @note This function is not available in single-core mode. + * + * @param[in] func Pointer to a function of type void func(void* arg) to be executed + * @param[in] arg Arbitrary argument of type void* to be passed into the function + */ +//go:linkname EspIpcIsrCallBlocking C.esp_ipc_isr_call_blocking +func EspIpcIsrCallBlocking(func_ EspIpcIsrFuncT, arg c.Pointer) + +/** + * @brief Stall the other CPU + * + * This function will stall the other CPU. The other CPU is stalled by busy-waiting in the context of a High Priority + * Interrupt. The other CPU will not be resumed until esp_ipc_isr_release_other_cpu() is called. + * + * - This function is internally implemented using IPC ISR + * - This function is used for DPORT workaround. + * - If the stall feature is paused using esp_ipc_isr_stall_pause(), this function will have no effect + * + * @note This function is not available in single-core mode. + * @note It is the caller's responsibility to avoid deadlocking on spinlocks + */ +//go:linkname EspIpcIsrStallOtherCpu C.esp_ipc_isr_stall_other_cpu +func EspIpcIsrStallOtherCpu() + +/** + * @brief Release the other CPU + * + * This function will release the other CPU that was previously stalled from calling esp_ipc_isr_stall_other_cpu() + * + * - This function is used for DPORT workaround. + * - If the stall feature is paused using esp_ipc_isr_stall_pause(), this function will have no effect + * + * @note This function is not available in single-core mode. + */ +//go:linkname EspIpcIsrReleaseOtherCpu C.esp_ipc_isr_release_other_cpu +func EspIpcIsrReleaseOtherCpu() + +/** + * @brief Puase the CPU stall feature + * + * This function will pause the CPU stall feature. Once paused, calls to esp_ipc_isr_stall_other_cpu() and + * esp_ipc_isr_release_other_cpu() will have no effect. If a IPC ISR call is already in progress, this function will + * busy-wait until the call completes before pausing the CPU stall feature. + */ +//go:linkname EspIpcIsrStallPause C.esp_ipc_isr_stall_pause +func EspIpcIsrStallPause() + +/** + * @brief Abort a CPU stall + * + * This function will abort any stalling routine of the other CPU due to a pervious call to + * esp_ipc_isr_stall_other_cpu(). This function aborts the stall in a non-recoverable manner, thus should only be called + * in case of a panic(). + * + * - This function is used in panic handling code + */ +//go:linkname EspIpcIsrStallAbort C.esp_ipc_isr_stall_abort +func EspIpcIsrStallAbort() + +/** + * @brief Resume the CPU stall feature + * + * This function will resume the CPU stall feature that was previously paused by calling esp_ipc_isr_stall_pause(). Once + * resumed, calls to esp_ipc_isr_stall_other_cpu() and esp_ipc_isr_release_other_cpu() will have effect again. + */ +//go:linkname EspIpcIsrStallResume C.esp_ipc_isr_stall_resume +func EspIpcIsrStallResume() + +/** + * @brief Initialize the IPC ISR feature, must be called for each CPU + * + * @note This function is called from ipc_task(). + * + * This function initializes the IPC ISR feature and must be called before any other esp_ipc_isr...() functions. + * The IPC ISR feature allows for callbacks (written in assembly) to be run on a particular CPU in the context of a + * High Priority Interrupt. + * + * - This function will register a High Priority Interrupt for a CPU where it is called. The priority of the interrupts is dependent on + * the CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL option. + * - Callbacks written in assembly can then run in context of the registered High Priority Interrupts + * - Callbacks can be executed by calling esp_ipc_isr_call() or esp_ipc_isr_call_blocking() + */ +//go:linkname EspIpcIsrInit C.esp_ipc_isr_init +func EspIpcIsrInit() diff --git a/esp32/esp_ipc_isr_port.go b/esp32/esp_ipc_isr_port.go new file mode 100644 index 00000000..a6669afc --- /dev/null +++ b/esp32/esp_ipc_isr_port.go @@ -0,0 +1,26 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Initialize the IPC ISR interrupt for a specific CPU. + * + * This function initializes the IPC ISR (Inter-Processor Communication Interrupt) + * for a specific CPU core. It configures the interrupt source and enables the + * IPC ISR interrupt for the specified CPU. + * + * @param[in] cpuid The ID of the CPU core to initialize IPC ISR for. + */ +//go:linkname EspIpcIsrPortInit C.esp_ipc_isr_port_init +func EspIpcIsrPortInit(cpuid c.Int) + +/** + * @brief Trigger an interrupt on a specific CPU core. + * + * @param[in] cpuid The ID of the CPU core to trigger the interrupt on (0 or 1). + */ +//go:linkname EspIpcIsrPortIntTrigger C.esp_ipc_isr_port_int_trigger +func EspIpcIsrPortIntTrigger(cpuid c.Int) diff --git a/esp32/esp_ldo_regulator.go b/esp32/esp_ldo_regulator.go new file mode 100644 index 00000000..ffcb6d14 --- /dev/null +++ b/esp32/esp_ldo_regulator.go @@ -0,0 +1,83 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type LdoRegulatorChannelT struct { + Unused [8]uint8 +} +type EspLdoChannelHandleT *LdoRegulatorChannelT + +/** + * @brief LDO channel configurations + */ + +type EspLdoChannelConfigT struct { + ChanId c.Int + VoltageMv c.Int + Flags LdoExtraFlags +} + +type LdoExtraFlags struct { + Unused [8]uint8 +} + +/** + * @brief Acquire an LDO channel with the specified configuration + * + * @note This function can't automatically search a LDO channel for you, you must specify a LDO channel ID manually, based on your schematic. + * @note The same channel can be acquired multiple times in different places of the application code, however, + * if the LDO channel is adjustable, you can't acquire it multiple times, in case user A changes the voltage and breaks the voltage setting of user B. + * @note You should release the channel by `esp_ldo_release_channel` when it's no longer needed. + * + * @param[in] config The configuration of the LDO channel + * @param[out] out_handle The returned LDO channel handle + * @return + * - ESP_OK: Acquire the LDO channel successfully + * - ESP_ERR_INVALID_ARG: Acquire the LDO channel failed due to invalid arguments + * - ESP_FAIL: Acquire the LDO channel failed due to other reasons + */ +// llgo:link (*EspLdoChannelConfigT).EspLdoAcquireChannel C.esp_ldo_acquire_channel +func (recv_ *EspLdoChannelConfigT) EspLdoAcquireChannel(out_handle *EspLdoChannelHandleT) EspErrT { + return 0 +} + +/** + * @brief Release the LDO channel + * + * @param[in] chan The LDO channel handle returned from `esp_ldo_acquire_channel` + * @return + * - ESP_OK: Release the LDO channel successfully + * - ESP_ERR_INVALID_ARG: Release the LDO channel failed due to invalid arguments + * - ESP_ERR_INVALID_STATE: Release the LDO channel failed due to invalid state, e.g., the channel handle is double released + * - ESP_FAIL: Release the LDO channel failed due to other reasons + */ +//go:linkname EspLdoReleaseChannel C.esp_ldo_release_channel +func EspLdoReleaseChannel(chan_ EspLdoChannelHandleT) EspErrT + +/** + * @brief Adjust the voltage of the LDO channel + * + * @param[in] chan The LDO channel handle returned from `esp_ldo_acquire_channel` + * @param[in] voltage_mv The voltage value to be set to the LDO channel, in millivolts + * @return + * - ESP_OK: Adjust the voltage of the LDO channel successfully + * - ESP_ERR_INVALID_ARG: Adjust the voltage of the LDO channel failed due to invalid arguments + * - ESP_ERR_NOT_SUPPORTED: Adjust the voltage of the LDO channel failed due to the channel is not adjustable + * - ESP_FAIL: Adjust the voltage of the LDO channel failed due to other reasons + */ +//go:linkname EspLdoChannelAdjustVoltage C.esp_ldo_channel_adjust_voltage +func EspLdoChannelAdjustVoltage(chan_ EspLdoChannelHandleT, voltage_mv c.Int) EspErrT + +/** + * @brief Dump LDO channel status to the specified stream + * + * @param[in] stream IO stream. Can be stdout, stderr, or a file/string stream. + * @return + * - ESP_OK: Dump the LDO channel status successfully + * - ESP_FAIL: Dump the LDO channel status failed + */ +//go:linkname EspLdoDump C.esp_ldo_dump +func EspLdoDump(stream *c.FILE) EspErrT diff --git a/esp32/esp_log.go b/esp32/esp_log.go new file mode 100644 index 00000000..95b0a29b --- /dev/null +++ b/esp32/esp_log.go @@ -0,0 +1,49 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:type C +type VprintfLikeT func(*c.Char, c.VaList) c.Int + +/** + * @brief Set function used to output log entries + * + * By default, log output goes to UART0. This function can be used to redirect log + * output to some other destination, such as file or network. Returns the original + * log handler, which may be necessary to return output to the previous destination. + * + * @note Please note that function callback here must be re-entrant as it can be + * invoked in parallel from multiple thread context. + * + * @param func new Function used for output. Must have same signature as vprintf. + * + * @return func old Function used for output. + */ +//go:linkname EspLogSetVprintf C.esp_log_set_vprintf +func EspLogSetVprintf(func_ VprintfLikeT) VprintfLikeT + +/** + * @brief Write message into the log + * + * This function is not intended to be used directly. Instead, use one of + * ESP_LOGE, ESP_LOGW, ESP_LOGI, ESP_LOGD, ESP_LOGV macros. + * + * This function or these macros should not be used from an interrupt. + */ +// llgo:link EspLogLevelT.EspLogWrite C.esp_log_write +func (recv_ EspLogLevelT) EspLogWrite(tag *c.Char, format *c.Char, __llgo_va_list ...interface{}) { +} + +/** + * @brief Write message into the log, va_list variant + * @see esp_log_write() + * + * This function is provided to ease integration toward other logging framework, + * so that esp_log can be used as a log sink. + */ +// llgo:link EspLogLevelT.EspLogWritev C.esp_log_writev +func (recv_ EspLogLevelT) EspLogWritev(tag *c.Char, format *c.Char, args c.VaList) { +} diff --git a/esp32/esp_log_buffer.go b/esp32/esp_log_buffer.go new file mode 100644 index 00000000..f4f874f9 --- /dev/null +++ b/esp32/esp_log_buffer.go @@ -0,0 +1,57 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Logs a buffer of hexadecimal bytes at the specified log level. + * + * This function logs a buffer of hexadecimal bytes with 16 bytes per line. The + * log level determines the severity of the log message. + * + * @note This function does not check the log level against the ESP_LOCAL_LEVEL. + * The log level comparison should be done in esp_log.h. + * + * @param tag Description tag to identify the log. + * @param buffer Pointer to the buffer array containing the data to be logged. + * @param buff_len Length of the buffer in bytes. + * @param level Log level indicating the severity of the log message. + */ +//go:linkname EspLogBufferHexInternal C.esp_log_buffer_hex_internal +func EspLogBufferHexInternal(tag *c.Char, buffer c.Pointer, buff_len c.Uint16T, level EspLogLevelT) + +/** + * @brief This function logs a buffer of characters with 16 characters per line. + * The buffer should contain only printable characters. The log level determines + * the severity of the log message. + * + * @note This function does not check the log level against the ESP_LOCAL_LEVEL. + * The log level comparison should be done in esp_log.h. + * + * @param tag Description tag to identify the log. + * @param buffer Pointer to the buffer array containing the data to be logged. + * @param buff_len Length of the buffer in bytes. + * @param level Log level indicating the severity of the log message. + */ +//go:linkname EspLogBufferCharInternal C.esp_log_buffer_char_internal +func EspLogBufferCharInternal(tag *c.Char, buffer c.Pointer, buff_len c.Uint16T, level EspLogLevelT) + +/** + * @brief This function dumps a buffer to the log in a formatted hex dump style, + * displaying both the memory address and the corresponding hex and ASCII values + * of the bytes. The log level determines the severity of the log message. + * + * @note This function does not check the log level against the ESP_LOCAL_LEVEL. + * The log level comparison should be done in esp_log.h. + * @note It is recommended to use terminals with a width of at least 102 + * characters to display the log dump properly. + * + * @param tag Description tag to identify the log. + * @param buffer Pointer to the buffer array containing the data to be logged. + * @param buff_len Length of the buffer in bytes. + * @param log_level Log level indicating the severity of the log message. + */ +//go:linkname EspLogBufferHexdumpInternal C.esp_log_buffer_hexdump_internal +func EspLogBufferHexdumpInternal(tag *c.Char, buffer c.Pointer, buff_len c.Uint16T, log_level EspLogLevelT) diff --git a/esp32/esp_log_color.go b/esp32/esp_log_color.go new file mode 100644 index 00000000..2ccde455 --- /dev/null +++ b/esp32/esp_log_color.go @@ -0,0 +1,32 @@ +package freertos + +import _ "unsafe" + +const LOG_ANSI_COLOR_BLACK = "30" +const LOG_ANSI_COLOR_RED = "31" +const LOG_ANSI_COLOR_GREEN = "32" +const LOG_ANSI_COLOR_YELLOW = "33" +const LOG_ANSI_COLOR_BLUE = "34" +const LOG_ANSI_COLOR_MAGENTA = "35" +const LOG_ANSI_COLOR_CYAN = "36" +const LOG_ANSI_COLOR_WHITE = "37" +const LOG_ANSI_COLOR_DEFAULT = "39" +const LOG_ANSI_COLOR_BG_BLACK = "40" +const LOG_ANSI_COLOR_BG_RED = "41" +const LOG_ANSI_COLOR_BG_GREEN = "42" +const LOG_ANSI_COLOR_BG_YELLOW = "43" +const LOG_ANSI_COLOR_BG_BLUE = "44" +const LOG_ANSI_COLOR_BG_MAGENTA = "45" +const LOG_ANSI_COLOR_BG_CYAN = "46" +const LOG_ANSI_COLOR_BG_WHITE = "47" +const LOG_ANSI_COLOR_BG_DEFAULT = "49" +const LOG_ANSI_COLOR_STYLE_RESET = "0" +const LOG_ANSI_COLOR_STYLE_BOLD = "1" +const LOG_ANSI_COLOR_STYLE_ITALIC = "3" +const LOG_ANSI_COLOR_STYLE_UNDERLINE = "4" +const LOG_RESET_COLOR = "" +const LOG_COLOR_E = "" +const LOG_COLOR_W = "" +const LOG_COLOR_I = "" +const LOG_COLOR_D = "" +const LOG_COLOR_V = "" diff --git a/esp32/esp_log_level.go b/esp32/esp_log_level.go new file mode 100644 index 00000000..7acf911c --- /dev/null +++ b/esp32/esp_log_level.go @@ -0,0 +1,54 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EspLogLevelT c.Int + +const ( + ESP_LOG_NONE EspLogLevelT = 0 + ESP_LOG_ERROR EspLogLevelT = 1 + ESP_LOG_WARN EspLogLevelT = 2 + ESP_LOG_INFO EspLogLevelT = 3 + ESP_LOG_DEBUG EspLogLevelT = 4 + ESP_LOG_VERBOSE EspLogLevelT = 5 + ESP_LOG_MAX EspLogLevelT = 6 +) + +/** + * @brief Set log level for given tag + * + * If logging for given component has already been enabled, changes previous setting. + * + * @note Note that this function can not raise log level above the level set using + * CONFIG_LOG_MAXIMUM_LEVEL setting in menuconfig. + * + * To raise log level above the default one for a given file, define + * LOG_LOCAL_LEVEL to one of the ESP_LOG_* values, before including esp_log.h in this file. + * + * If CONFIG_LOG_DYNAMIC_LEVEL_CONTROL is not selected the static (no-op) implementation of log level is used. + * Changing the log level is not possible, esp_log_level_set does not work. + * + * @param tag Tag of the log entries to enable. Must be a non-NULL zero terminated string. + * Value "*" resets log level for all tags to the given value. + * If the tag is NULL then a silent return happens. + * @param level Selects log level to enable. + * Only logs at this and lower verbosity levels will be shown. + */ +//go:linkname EspLogLevelSet C.esp_log_level_set +func EspLogLevelSet(tag *c.Char, level EspLogLevelT) + +/** + * @brief Get log level for a given tag, can be used to avoid expensive log statements + * + * If CONFIG_LOG_DYNAMIC_LEVEL_CONTROL is not selected the static (no-op) implementation of log level is used. + * Changing the log level is not possible, esp_log_level_set does not work. This function returns the default log level. + * + * @param tag Tag of the log to query current level. Must be a zero terminated string. + * If tag is NULL then the default log level is returned (see esp_log_get_default_level()). + * @return The current log level for the given tag. + */ +//go:linkname EspLogLevelGet C.esp_log_level_get +func EspLogLevelGet(tag *c.Char) EspLogLevelT diff --git a/esp32/esp_log_timestamp.go b/esp32/esp_log_timestamp.go new file mode 100644 index 00000000..f7fc516b --- /dev/null +++ b/esp32/esp_log_timestamp.go @@ -0,0 +1,48 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Function which returns timestamp to be used in log output + * + * This function is used in expansion of ESP_LOGx macros. + * In the 2nd stage bootloader, and at early application startup stage + * this function uses CPU cycle counter as time source. Later when + * FreeRTOS scheduler start running, it switches to FreeRTOS tick count. + * + * For now, we ignore millisecond counter overflow. + * + * @return timestamp, in milliseconds + */ +//go:linkname EspLogTimestamp C.esp_log_timestamp +func EspLogTimestamp() c.Uint32T + +/** + * @brief Function which returns system timestamp to be used in log output + * + * This function is used in expansion of ESP_LOGx macros to print + * the system time as "HH:MM:SS.sss". The system time is initialized to + * 0 on startup, this can be set to the correct time with an SNTP sync, + * or manually with standard POSIX time functions. + * + * Currently, this will not get used in logging from binary blobs + * (i.e. Wi-Fi & Bluetooth libraries), these will still print the RTOS tick time. + * + * @return timestamp, in "HH:MM:SS.sss" + */ +//go:linkname EspLogSystemTimestamp C.esp_log_system_timestamp +func EspLogSystemTimestamp() *c.Char + +/** + * @brief Function which returns timestamp to be used in log output + * + * This function uses HW cycle counter and does not depend on OS, + * so it can be safely used after application crash. + * + * @return timestamp, in milliseconds + */ +//go:linkname EspLogEarlyTimestamp C.esp_log_early_timestamp +func EspLogEarlyTimestamp() c.Uint32T diff --git a/esp32/esp_mac.go b/esp32/esp_mac.go new file mode 100644 index 00000000..77d06e23 --- /dev/null +++ b/esp32/esp_mac.go @@ -0,0 +1,174 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const MACSTR = "%02x:%02x:%02x:%02x:%02x:%02x" +const ONE_UNIVERSAL_MAC_ADDR = 1 +const TWO_UNIVERSAL_MAC_ADDR = 2 +const FOUR_UNIVERSAL_MAC_ADDR = 4 + +type EspMacTypeT c.Int + +const ( + ESP_MAC_WIFI_STA EspMacTypeT = 0 + ESP_MAC_WIFI_SOFTAP EspMacTypeT = 1 + ESP_MAC_BT EspMacTypeT = 2 + ESP_MAC_ETH EspMacTypeT = 3 + ESP_MAC_IEEE802154 EspMacTypeT = 4 + ESP_MAC_BASE EspMacTypeT = 5 + ESP_MAC_EFUSE_FACTORY EspMacTypeT = 6 + ESP_MAC_EFUSE_CUSTOM EspMacTypeT = 7 + ESP_MAC_EFUSE_EXT EspMacTypeT = 8 +) + +/** + * @brief Set base MAC address with the MAC address which is stored in BLK3 of EFUSE or + * external storage e.g. flash and EEPROM. + * + * Base MAC address is used to generate the MAC addresses used by network interfaces. + * + * If using a custom base MAC address, call this API before initializing any network interfaces. + * Refer to the ESP-IDF Programming Guide for details about how the Base MAC is used. + * + * @note Base MAC must be a unicast MAC (least significant bit of first byte must be zero). + * + * @note If not using a valid OUI, set the "locally administered" bit + * (bit value 0x02 in the first byte) to avoid collisions. + * + * @param mac base MAC address, length: 6 bytes. + * length: 6 bytes for MAC-48 + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG If mac is NULL or is not a unicast MAC + */ +//go:linkname EspBaseMacAddrSet C.esp_base_mac_addr_set +func EspBaseMacAddrSet(mac *c.Uint8T) EspErrT + +/** + * @brief Return base MAC address which is set using esp_base_mac_addr_set. + * + * @note If no custom Base MAC has been set, this returns the pre-programmed Espressif base MAC address. + * + * @param mac base MAC address, length: 6 bytes. + * length: 6 bytes for MAC-48 + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG mac is NULL + * ESP_ERR_INVALID_MAC base MAC address has not been set + */ +//go:linkname EspBaseMacAddrGet C.esp_base_mac_addr_get +func EspBaseMacAddrGet(mac *c.Uint8T) EspErrT + +/** + * @brief Return base MAC address which was previously written to BLK3 of EFUSE. + * + * Base MAC address is used to generate the MAC addresses used by the networking interfaces. + * This API returns the custom base MAC address which was previously written to EFUSE BLK3 in + * a specified format. + * + * Writing this EFUSE allows setting of a different (non-Espressif) base MAC address. It is also + * possible to store a custom base MAC address elsewhere, see esp_base_mac_addr_set() for details. + * + * @note This function is currently only supported on ESP32. + * + * @param mac base MAC address, length: 6 bytes/8 bytes. + * length: 6 bytes for MAC-48 + * 8 bytes for EUI-64(used for IEEE 802.15.4, if CONFIG_SOC_IEEE802154_SUPPORTED=y) + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG mac is NULL + * ESP_ERR_INVALID_MAC CUSTOM_MAC address has not been set, all zeros (for esp32-xx) + * ESP_ERR_INVALID_VERSION An invalid MAC version field was read from BLK3 of EFUSE (for esp32) + * ESP_ERR_INVALID_CRC An invalid MAC CRC was read from BLK3 of EFUSE (for esp32) + */ +//go:linkname EspEfuseMacGetCustom C.esp_efuse_mac_get_custom +func EspEfuseMacGetCustom(mac *c.Uint8T) EspErrT + +/** + * @brief Return base MAC address which is factory-programmed by Espressif in EFUSE. + * + * @param mac base MAC address, length: 6 bytes/8 bytes. + * length: 6 bytes for MAC-48 + * 8 bytes for EUI-64(used for IEEE 802.15.4, if CONFIG_SOC_IEEE802154_SUPPORTED=y) + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG mac is NULL + */ +//go:linkname EspEfuseMacGetDefault C.esp_efuse_mac_get_default +func EspEfuseMacGetDefault(mac *c.Uint8T) EspErrT + +/** + * @brief Read base MAC address and set MAC address of the interface. + * + * This function first get base MAC address using esp_base_mac_addr_get(). + * Then calculates the MAC address of the specific interface requested, + * refer to ESP-IDF Programming Guide for the algorithm. + * + * The MAC address set by the esp_iface_mac_addr_set() function will not depend on the base MAC address. + * + * @param mac base MAC address, length: 6 bytes/8 bytes. + * length: 6 bytes for MAC-48 + * 8 bytes for EUI-64(used for IEEE 802.15.4, if CONFIG_SOC_IEEE802154_SUPPORTED=y) + * @param type Type of MAC address to return + * + * @return ESP_OK on success + */ +//go:linkname EspReadMac C.esp_read_mac +func EspReadMac(mac *c.Uint8T, type_ EspMacTypeT) EspErrT + +/** + * @brief Derive local MAC address from universal MAC address. + * + * This function copies a universal MAC address and then sets the "locally + * administered" bit (bit 0x2) in the first octet, creating a locally + * administered MAC address. + * + * If the universal MAC address argument is already a locally administered MAC + * address, then the first octet is XORed with 0x4 in order to create a different + * locally administered MAC address. + * + * @param local_mac base MAC address, length: 6 bytes. + * length: 6 bytes for MAC-48 + * @param universal_mac Source universal MAC address, length: 6 bytes. + * + * @return ESP_OK on success + */ +//go:linkname EspDeriveLocalMac C.esp_derive_local_mac +func EspDeriveLocalMac(local_mac *c.Uint8T, universal_mac *c.Uint8T) EspErrT + +/** + * @brief Set custom MAC address of the interface. This function allows you to overwrite the MAC addresses + * of the interfaces set by the base MAC address. + * + * @param mac MAC address, length: 6 bytes/8 bytes. + * length: 6 bytes for MAC-48 + * 8 bytes for EUI-64(used for ESP_MAC_IEEE802154 type, if CONFIG_SOC_IEEE802154_SUPPORTED=y) + * @param type Type of MAC address + * + * @return ESP_OK on success + */ +//go:linkname EspIfaceMacAddrSet C.esp_iface_mac_addr_set +func EspIfaceMacAddrSet(mac *c.Uint8T, type_ EspMacTypeT) EspErrT + +/** + * @brief Return the size of the MAC type in bytes. + * + * If CONFIG_SOC_IEEE802154_SUPPORTED is set then for these types: + * - ESP_MAC_IEEE802154 is 8 bytes. + * - ESP_MAC_BASE, ESP_MAC_EFUSE_FACTORY and ESP_MAC_EFUSE_CUSTOM the MAC size is 6 bytes. + * - ESP_MAC_EFUSE_EXT is 2 bytes. + * If CONFIG_SOC_IEEE802154_SUPPORTED is not set then for all types it returns 6 bytes. + * + * @param type Type of MAC address + * + * @return 0 MAC type not found (not supported) + * 6 bytes for MAC-48. + * 8 bytes for EUI-64. + */ +// llgo:link EspMacTypeT.EspMacAddrLenGet C.esp_mac_addr_len_get +func (recv_ EspMacTypeT) EspMacAddrLenGet() c.SizeT { + return 0 +} diff --git a/esp32/esp_macros.go b/esp32/esp_macros.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/esp_macros.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/esp_memory_utils.go b/esp32/esp_memory_utils.go new file mode 100644 index 00000000..ae59a0dd --- /dev/null +++ b/esp32/esp_memory_utils.go @@ -0,0 +1,46 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Check if the pointer is in external ram dma capable region + * + * @param p pointer + * + * @return true: capable; false: not capable + */ +//go:linkname EspPtrDmaExtCapable C.esp_ptr_dma_ext_capable +func EspPtrDmaExtCapable(p c.Pointer) bool + +/** + * @brief Check if the pointer is executable + * + * @param p pointer + * + * @return true: is executable; false: not executable + */ +//go:linkname EspPtrExecutable C.esp_ptr_executable +func EspPtrExecutable(p c.Pointer) bool + +/** + * @brief Check if the pointer is byte accessible + * + * @param p pointer + * + * @return true: is byte accessible; false: not byte accessible + */ +//go:linkname EspPtrByteAccessible C.esp_ptr_byte_accessible +func EspPtrByteAccessible(p c.Pointer) bool + +/** + * @brief Check if the pointer is in external ram + * + * @param p pointer + * + * @return true: is in external ram; false: not in external ram + */ +//go:linkname EspPtrExternalRam C.esp_ptr_external_ram +func EspPtrExternalRam(p c.Pointer) bool diff --git a/esp32/esp_memprot.go b/esp32/esp_memprot.go new file mode 100644 index 00000000..373c34e6 --- /dev/null +++ b/esp32/esp_memprot.go @@ -0,0 +1,198 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** +* @brief Basic PMS interrupt source info + */ +type EspMempIntrSourceT struct { + MemType EspMprotMemT + Core c.Int +} + +/** + * @brief Clears current interrupt ON flag for given Memory type and CPU/Core ID + * + * This operation is non-atomic for some chips by PMS module design + * In such a case the interrupt clearing happens in two steps: + * 1. Interrupt CLR flag is set (clears interrupt-ON status and inhibits linked interrupt processing) + * 2. Interrupt CLR flag is reset (resumes the interrupt monitoring) + * + * @param mem_type Memory type (see esp_mprot_mem_t enum) + * @param core Target CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG on passing invalid pointer + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + */ +// llgo:link EspMprotMemT.EspMprotMonitorClearIntr C.esp_mprot_monitor_clear_intr +func (recv_ EspMprotMemT) EspMprotMonitorClearIntr(core c.Int) EspErrT { + return 0 +} + +/** + * @brief Checks whether any of the PMS settings is locked + * + * @param[out] locked Any lock on? (true/false) + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG on invalid locked ptr + * Other failures: error code of any failing esp_mprot_get_*_lock() routine (called internally) + */ +//go:linkname EspMprotIsConfLockedAny C.esp_mprot_is_conf_locked_any +func EspMprotIsConfLockedAny(locked *bool) EspErrT + +/** + * @brief Checks whether any PMS violation-interrupt monitoring is enabled + * + * @param[out] locked Any PMS violation interrupt monitor is enabled (true/false) + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG on invalid enabled ptr + * Other failures: error code of esp_mprot_get_monitor_en() routine (called internally for all Memory types) + */ +//go:linkname EspMprotIsIntrEnaAny C.esp_mprot_is_intr_ena_any +func EspMprotIsIntrEnaAny(enabled *bool) EspErrT + +/** + * @brief Returns active PMS violation-interrupt Memory type if any (MEMPROT_TYPE_NONE when none detected) + * and the CPU/CoreID which was running the faulty code (-1 when no interrupt available) + * + * If there are more interrupts indicated on (shouldn't happen), the order of precedence is given by 'esp_mprot_mem_t' enum definition (low->high) + * + * @param[out] mem_type Out-pointer for Memory type given by the faulting address (see esp_mprot_mem_t enum) + * @param[out] core Out-pointer for CPU/Core ID (see *_CPU_NUM defs in soc.h) + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG on passing invalid pointer(s) + */ +// llgo:link (*EspMempIntrSourceT).EspMprotGetActiveIntr C.esp_mprot_get_active_intr +func (recv_ *EspMempIntrSourceT) EspMprotGetActiveIntr() EspErrT { + return 0 +} + +/** + * @brief Returns the address which caused the violation interrupt for given Memory type and CPU/Core ID. + * This function is to be called after a basic resolving of (current) interrupt's parameters (ie corresponding + * Memory type and CPU ID see esp_mprot_get_active_intr()). This is to minimize processing time of actual exception + * as this API is typicaly used in a panic-handling code. + * If there is no active interrupt available for the Memory type/CPU ID required, fault_addr is set to NULL. + * + * @param mem_type memory type + * @param[out] fault_addr Address of the operation which caused the PMS violation interrupt + * @param core Faulting instruction CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + * ESP_ERR_INVALID_ARG on invalid fault_addr pointer + */ +// llgo:link EspMprotMemT.EspMprotGetViolateAddr C.esp_mprot_get_violate_addr +func (recv_ EspMprotMemT) EspMprotGetViolateAddr(fault_addr *c.Pointer, core c.Int) EspErrT { + return 0 +} + +/** + * @brief Returns PMS World identifier of the code causing the violation interrupt + * + * The value is read from appropriate PMS violation status register and thus might be 0 if the interrupt is not currently active. + * + * @param mem_type Memory type + * @param[out] world PMS World type (see esp_mprot_pms_world_t) + * @param core Faulting instruction CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + * ESP_ERR_INVALID_ARG on passing invalid pointer(s) + * ESP_ERR_MEMPROT_WORLD_INVALID on invalid World identifier fetched from the register + */ +// llgo:link EspMprotMemT.EspMprotGetViolateWorld C.esp_mprot_get_violate_world +func (recv_ EspMprotMemT) EspMprotGetViolateWorld(world *EspMprotPmsWorldT, core c.Int) EspErrT { + return 0 +} + +/** + * @brief Returns an operation type which caused the violation interrupt + * + * The operation resolving is processed over various PMS status register flags, according to given Memory type argument. + * If the interrupt is not active the result returned is irrelevant (likely evaluated to MEMPROT_OP_READ). + * + * @param mem_type Memory type + * @param[out] oper Operation type (see MEMPROT_OP_* defines) + * @param core Faulting instruction CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + * ESP_ERR_INVALID_ARG on invalid oper pointer + */ +// llgo:link EspMprotMemT.EspMprotGetViolateOperation C.esp_mprot_get_violate_operation +func (recv_ EspMprotMemT) EspMprotGetViolateOperation(oper *c.Uint32T, core c.Int) EspErrT { + return 0 +} + +/** +* @brief Checks whether given memory type supports byte-enables info +* +* Byte-enables status is available only for DMA/DRAM operations + * +* @param mem_type memory type +* +* @return byte-enables info available true/false +*/ +// llgo:link EspMprotMemT.EspMprotHasByteEnables C.esp_mprot_has_byte_enables +func (recv_ EspMprotMemT) EspMprotHasByteEnables() bool { + return false +} + +/** + * @brief Returns byte-enables for the address which caused the violation interrupt + * + * The value is taken from appropriate PMS violation status register, based on given Memory type + * + * @param mem_type Memory type (MEMPROT_TYPE_DRAM0_SRAM) + * @param[out] byte_en Byte-enables bits + * @param core Faulting instruction CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + * ESP_ERR_INVALID_ARGUMENT on invalid byte_en pointer + */ +// llgo:link EspMprotMemT.EspMprotGetViolateByteEnables C.esp_mprot_get_violate_byte_enables +func (recv_ EspMprotMemT) EspMprotGetViolateByteEnables(byte_en *c.Uint32T, core c.Int) EspErrT { + return 0 +} + +/** + * @brief Convenient routine for setting the PMS defaults + * + * Called on system startup, depending on ESP_SYSTEM_MEMPROT_FEATURE Kconfig value + * + * @param memp_config pointer to Memprot configuration structure (esp_memp_config_t). The structure si chip-specific, + * for details and defaults see appropriate [target-chip]/soc_memprot_types.h + * + * @return ESP_OK on success + * Other failures: error code of the failing routine called internally. No specific error processing provided in such a case + * due to large number of embedded calls (ie no global unique error table is provided and thus one error code can have different meanings, + * depending on the routine issuing the error) + */ +// llgo:link (*EspMempConfigT).EspMprotSetProt C.esp_mprot_set_prot +func (recv_ *EspMempConfigT) EspMprotSetProt() EspErrT { + return 0 +} + +/** + * @brief Generates PMS configuration string of actual device (diagnostics) + * + * The functions generates a string from current configuration, control and status registers of the PMS (or similar) module of actual device. + * The values are fetched using HAL LL calls to help finding possible errors in the Memprot API implementation + * + * @param[out] dump_info_string configuration string buffer pointer. The string is allocated by the callee and must be freed by the caller. + * + * @return ESP_OK on success + * ESP_ERR_NO_MEM on buffer allocation failure + * ESP_ERR_INVALID_ARGUMENT on invalid dump_info_string pointer + */ +//go:linkname EspMprotDumpConfiguration C.esp_mprot_dump_configuration +func EspMprotDumpConfiguration(dump_info_string **c.Char) EspErrT diff --git a/esp32/esp_memprot_err.go b/esp32/esp_memprot_err.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/esp_memprot_err.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/esp_memprot_internal.go b/esp32/esp_memprot_internal.go new file mode 100644 index 00000000..a7f51792 --- /dev/null +++ b/esp32/esp_memprot_internal.go @@ -0,0 +1,250 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** +* @brief Convert Memprot low level errors to esp_err_t + */ +// llgo:link MemprotHalErrT.EspMprotLlErrToEspErr C.esp_mprot_ll_err_to_esp_err +func (recv_ MemprotHalErrT) EspMprotLlErrToEspErr() EspErrT { + return 0 +} + +/** + * @brief Convert Memprot low level PMS World IDs to esp_mprot_pms_world_t + */ +// llgo:link MemprotHalWorldT.EspMprotLlWorldToHlWorld C.esp_mprot_ll_world_to_hl_world +func (recv_ MemprotHalWorldT) EspMprotLlWorldToHlWorld() EspMprotPmsWorldT { + return 0 +} + +/** + * @brief Converts operation type to string, no combination of operations allowed + * + * @param oper_type PMS operation type + */ +//go:linkname EspMprotOperTypeToStr C.esp_mprot_oper_type_to_str +func EspMprotOperTypeToStr(oper_type c.Uint32T) *c.Char + +/** + * @brief Converts PMS World type to string + * + * @param area_type PMS World type + */ +// llgo:link EspMprotPmsWorldT.EspMprotPmsWorldToStr C.esp_mprot_pms_world_to_str +func (recv_ EspMprotPmsWorldT) EspMprotPmsWorldToStr() *c.Char { + return nil +} + +/** + * @brief Sets splitting address for given line type in the target Memory type + * + * @param mem_type memory type + * @param line_type split address type + * @param line_addr target address from a memory range relevant to given line_addr + * @param core Target CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + * ESP_ERR_MEMPROT_SPLIT_ADDR_INVALID on invalid line_type + * ESP_ERR_MEMPROT_SPLIT_ADDR_OUT_OF_RANGE on splitting line out of given memory-type range + * ESP_ERR_MEMPROT_SPLIT_ADDR_UNALIGNED on splitting line not aligned to PMS-required boundaries + */ +// llgo:link EspMprotMemT.EspMprotSetSplitAddr C.esp_mprot_set_split_addr +func (recv_ EspMprotMemT) EspMprotSetSplitAddr(line_type EspMprotSplitAddrT, line_addr c.Pointer, core c.Int) EspErrT { + return 0 +} + +/** + * @brief Gets PMS splitting address for given split_addr type + * + * The value is read from the PMS configuration registers + * + * @param mem_type memory type + * @param line_type Split line type (see esp_mprot_split_addr_t enum) + * @param[out] line_addr Split line address from the configuration register + * @param core Target CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG on line_addr is pointer + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + * ESP_ERR_MEMPROT_SPLIT_ADDR_INVALID on invalid line_type + */ +// llgo:link EspMprotMemT.EspMprotGetSplitAddr C.esp_mprot_get_split_addr +func (recv_ EspMprotMemT) EspMprotGetSplitAddr(line_type EspMprotSplitAddrT, line_addr *c.Pointer, core c.Int) EspErrT { + return 0 +} + +/** + * @brief Returns default main I/D splitting address for given Memory type + * + * @param mem_type memory type + * @param[out] def_split_addr Main I/D splitting address of required mem_type + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG on invalid def_split_addr pointer + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + */ +// llgo:link EspMprotMemT.EspMprotGetDefaultMainSplitAddr C.esp_mprot_get_default_main_split_addr +func (recv_ EspMprotMemT) EspMprotGetDefaultMainSplitAddr(def_split_addr *c.Pointer) EspErrT { + return 0 +} + +/** + * @brief Sets a lock for the main IRAM/DRAM splitting addresses + * Locks can be unlocked only by digital system reset + * + * @param mem_type memory type + * @param core Target CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + */ +// llgo:link EspMprotMemT.EspMprotSetSplitAddrLock C.esp_mprot_set_split_addr_lock +func (recv_ EspMprotMemT) EspMprotSetSplitAddrLock(core c.Int) EspErrT { + return 0 +} + +/** + * @brief Gets a lock status for the splitting address configuration of given Memory type + * + * @param mem_type memory type + * @param[out] locked mem_type related lock status + * @param core Target CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARGUMENT on invalid locked pointer + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + */ +// llgo:link EspMprotMemT.EspMprotGetSplitAddrLock C.esp_mprot_get_split_addr_lock +func (recv_ EspMprotMemT) EspMprotGetSplitAddrLock(locked *bool, core c.Int) EspErrT { + return 0 +} + +/** + * @brief Sets a lock for PMS Area settings of required Memory type + * Locks can be unlocked only by digital system reset + * + * @param mem_type memory type + * @param core Target CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + */ +// llgo:link EspMprotMemT.EspMprotSetPmsLock C.esp_mprot_set_pms_lock +func (recv_ EspMprotMemT) EspMprotSetPmsLock(core c.Int) EspErrT { + return 0 +} + +/** + * @brief Gets a lock status for PMS Area settings of required Memory type + * + * @param mem_type memory type + * @param[out] locked mem_type related lock status + * @param core Target CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + * ESP_ERR_INVALID_ARGUMENT on invalid locked pointer + */ +// llgo:link EspMprotMemT.EspMprotGetPmsLock C.esp_mprot_get_pms_lock +func (recv_ EspMprotMemT) EspMprotGetPmsLock(locked *bool, core c.Int) EspErrT { + return 0 +} + +/** + * @brief Sets permissions for given PMS Area + * + * @param area_type PMS area type + * @param flags combination of MEMPROT_OP_* defines + * @param core Target CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + */ +// llgo:link EspMprotPmsAreaT.EspMprotSetPmsArea C.esp_mprot_set_pms_area +func (recv_ EspMprotPmsAreaT) EspMprotSetPmsArea(flags c.Uint32T, core c.Int) EspErrT { + return 0 +} + +/** + * @brief Gets current permissions for given PMS Area + * + * @param area_type PMS area type + * @param[out] flags combination of MEMPROT_OP_* defines + * @param core Target CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + * ESP_ERR_INVALID_ARG on invalid flags pointer + */ +// llgo:link EspMprotPmsAreaT.EspMprotGetPmsArea C.esp_mprot_get_pms_area +func (recv_ EspMprotPmsAreaT) EspMprotGetPmsArea(flags *c.Uint32T, core c.Int) EspErrT { + return 0 +} + +/** + * @brief Sets a lock for PMS interrupt monitor settings of required Memory type + * + * Locks can be unlocked only by digital system reset + * + * @param mem_type memory type (see esp_mprot_mem_t enum) + * @param core Target CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + */ +// llgo:link EspMprotMemT.EspMprotSetMonitorLock C.esp_mprot_set_monitor_lock +func (recv_ EspMprotMemT) EspMprotSetMonitorLock(core c.Int) EspErrT { + return 0 +} + +/** + * @brief Gets a lock status for PMS interrupt monitor settings of required Memory type + * + * @param mem_type memory type + * @param[out] locked mem_type related lock status + * @param core Target CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + * ESP_ERR_INVALID_ARG on invalid locked pointer + */ +// llgo:link EspMprotMemT.EspMprotGetMonitorLock C.esp_mprot_get_monitor_lock +func (recv_ EspMprotMemT) EspMprotGetMonitorLock(locked *bool, core c.Int) EspErrT { + return 0 +} + +/** + * @brief Enable PMS violation interrupt monitoring of required Memory type + * + * @param mem_type memory type + * @param enable enable/disable violation interrupt monitoring + * @param core Target CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + */ +// llgo:link EspMprotMemT.EspMprotSetMonitorEn C.esp_mprot_set_monitor_en +func (recv_ EspMprotMemT) EspMprotSetMonitorEn(enable bool, core c.Int) EspErrT { + return 0 +} + +/** + * @brief Gets PMS violation-monitoring-enabled flag for required Memory type + * + * @param mem_type memory type + * @param[out] enabled violation interrupt monitoring enable flag + * @param core Target CPU/Core ID (see *_CPU_NUM defs in soc.h). Can be NULL on 1-CPU systems + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG on invalid enabled pointer + * ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID on invalid mem_type + */ +// llgo:link EspMprotMemT.EspMprotGetMonitorEn C.esp_mprot_get_monitor_en +func (recv_ EspMprotMemT) EspMprotGetMonitorEn(enabled *bool, core c.Int) EspErrT { + return 0 +} diff --git a/esp32/esp_memprot_types.go b/esp32/esp_memprot_types.go new file mode 100644 index 00000000..d3840207 --- /dev/null +++ b/esp32/esp_memprot_types.go @@ -0,0 +1,23 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const MEMPROT_OP_NONE = 0x00000000 +const MEMPROT_OP_READ = 0x00000001 +const MEMPROT_OP_WRITE = 0x00000002 +const MEMPROT_OP_EXEC = 0x00000004 +const MEMPROT_OP_INVALID = 0x80000000 + +type EspMprotPmsWorldT c.Int + +const ( + MEMPROT_PMS_WORLD_NONE EspMprotPmsWorldT = 0 + MEMPROT_PMS_WORLD_0 EspMprotPmsWorldT = 1 + MEMPROT_PMS_WORLD_1 EspMprotPmsWorldT = 2 + MEMPROT_PMS_WORLD_2 EspMprotPmsWorldT = 4 + MEMPROT_PMS_WORLD_ALL EspMprotPmsWorldT = 2147483647 + MEMPROT_PMS_WORLD_INVALID EspMprotPmsWorldT = -2147483648 +) diff --git a/esp32/esp_modem_clock.go b/esp32/esp_modem_clock.go new file mode 100644 index 00000000..ae0c2241 --- /dev/null +++ b/esp32/esp_modem_clock.go @@ -0,0 +1,97 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Enable the clock of modem module + * + * Solve the clock dependency between modem modules, For example, the wifi + * module depends on the wifi mac, wifi baseband and FE, when wifi module + * clock is enabled, the wifi MAC, baseband and FE clocks will be enabled + * + * This interface and modem_clock_module_disable will jointly maintain the + * ref_cnt of each device clock source. The ref_cnt indicates how many modules + * are relying on the clock source. Each enable ops will add 1 to the ref_cnt of + * the clock source that the module depends on, and only when the ref_cnt of + * the module is from 0 to 1 will the clock enable be actually configured. + * + * !!! Do not use the hal/ll layer interface to configure the clock for the + * consistency of the hardware state maintained in the driver and the hardware + * actual state. + * + * @param module modem module + */ +// llgo:link PeriphModuleT.ModemClockModuleEnable C.modem_clock_module_enable +func (recv_ PeriphModuleT) ModemClockModuleEnable() { +} + +/** + * @brief Disable the clock of modem module + * + * This interface and modem_clock_module_enable will jointly maintain the ref_cnt + * of each device clock source. The ref_cnt indicates how many modules are relying + * on the clock source. Each disable ops will minus 1 to the ref_cnt of the clock + * source that the module depends on, and only when the ref_cnt of the module is + * from 1 to 0 will the clock disable be actually configured. + * + * !!! Do not use the hal/ll layer interface to configure the clock for the + * consistency of the hardware state maintained in the driver and the hardware + * actual state. + * + * @param module modem module + */ +// llgo:link PeriphModuleT.ModemClockModuleDisable C.modem_clock_module_disable +func (recv_ PeriphModuleT) ModemClockModuleDisable() { +} + +/** + * @brief Reset the mac of modem module + * + * @param module modem module, must be one of + * PERIPH_WIFI_MODULE / PERIPH_BT_MODULE /PERIPH_IEEE802154_MODULE + */ +// llgo:link PeriphModuleT.ModemClockModuleMacReset C.modem_clock_module_mac_reset +func (recv_ PeriphModuleT) ModemClockModuleMacReset() { +} + +/** + * @brief Select the modem module lowpower clock source and configure the clock divider + * + * @param module modem module + * @param src lowpower clock source + * @param divider divider value to lowpower clock source + */ +// llgo:link PeriphModuleT.ModemClockSelectLpClockSource C.modem_clock_select_lp_clock_source +func (recv_ PeriphModuleT) ModemClockSelectLpClockSource(src ModemClockLpclkSrcT, divider c.Uint32T) { +} + +/** + * @brief Disable lowpower clock source selection + * @param module modem module + */ +// llgo:link PeriphModuleT.ModemClockDeselectLpClockSource C.modem_clock_deselect_lp_clock_source +func (recv_ PeriphModuleT) ModemClockDeselectLpClockSource() { +} + +/** +* @brief Disable all modem module's lowpower clock source selection + */ +//go:linkname ModemClockDeselectAllModuleLpClockSource C.modem_clock_deselect_all_module_lp_clock_source +func ModemClockDeselectAllModuleLpClockSource() + +/** + * @brief Reset wifi mac + */ +//go:linkname ModemClockWifiMacReset C.modem_clock_wifi_mac_reset +func ModemClockWifiMacReset() + +/** + * @brief Enable clock registers which shared by both modem and ADC. Need a ref count to enable/disable them + * + * @param enable true: enable; false: disable + */ +//go:linkname ModemClockSharedEnable C.modem_clock_shared_enable +func ModemClockSharedEnable(enable bool) diff --git a/esp32/esp_pmu.go b/esp32/esp_pmu.go new file mode 100644 index 00000000..bcb64b29 --- /dev/null +++ b/esp32/esp_pmu.go @@ -0,0 +1,14 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type PmuHpIcgModemModeT c.Int + +const ( + PMU_HP_ICG_MODEM_CODE_SLEEP PmuHpIcgModemModeT = 0 + PMU_HP_ICG_MODEM_CODE_MODEM PmuHpIcgModemModeT = 1 + PMU_HP_ICG_MODEM_CODE_ACTIVE PmuHpIcgModemModeT = 2 +) diff --git a/esp32/esp_random.go b/esp32/esp_random.go new file mode 100644 index 00000000..6749b056 --- /dev/null +++ b/esp32/esp_random.go @@ -0,0 +1,36 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Get one random 32-bit word from hardware RNG + * + * If Wi-Fi or Bluetooth are enabled, this function returns true random numbers. In other + * situations, if true random numbers are required then consult the ESP-IDF Programming + * Guide "Random Number Generation" section for necessary prerequisites. + * + * This function automatically busy-waits to ensure enough external entropy has been + * introduced into the hardware RNG state, before returning a new random number. + * This delay makes sure the reading frequency does not exceed 15-75 KHz. The actual + * value is dependent on the specific chip. More information on this can be found in + * components/esp_hw_support/hw_random.c. + * + * @return Random value between 0 and UINT32_MAX + */ +//go:linkname EspRandom C.esp_random +func EspRandom() c.Uint32T + +/** + * @brief Fill a buffer with random bytes from hardware RNG + * + * @note This function is implemented via calls to esp_random(), so the same + * constraints apply. + * + * @param buf Pointer to buffer to fill with random numbers. + * @param len Length of buffer in bytes + */ +//go:linkname EspFillRandom C.esp_fill_random +func EspFillRandom(buf c.Pointer, len c.SizeT) diff --git a/esp32/esp_rom_caps.go b/esp32/esp_rom_caps.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/esp_rom_caps.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/esp_rom_crc.go b/esp32/esp_rom_crc.go new file mode 100644 index 00000000..79e3ddaa --- /dev/null +++ b/esp32/esp_rom_crc.go @@ -0,0 +1,72 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief CRC32 value in little endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC32 value + */ +//go:linkname EspRomCrc32Le C.esp_rom_crc32_le +func EspRomCrc32Le(crc c.Uint32T, buf *c.Uint8T, len c.Uint32T) c.Uint32T + +/** + * @brief CRC32 value in big endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC32 value + */ +//go:linkname EspRomCrc32Be C.esp_rom_crc32_be +func EspRomCrc32Be(crc c.Uint32T, buf *c.Uint8T, len c.Uint32T) c.Uint32T + +/** + * @brief CRC16 value in little endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC16 value + */ +//go:linkname EspRomCrc16Le C.esp_rom_crc16_le +func EspRomCrc16Le(crc c.Uint16T, buf *c.Uint8T, len c.Uint32T) c.Uint16T + +/** + * @brief CRC16 value in big endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC16 value + */ +//go:linkname EspRomCrc16Be C.esp_rom_crc16_be +func EspRomCrc16Be(crc c.Uint16T, buf *c.Uint8T, len c.Uint32T) c.Uint16T + +/** + * @brief CRC8 value in little endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC8 value + */ +//go:linkname EspRomCrc8Le C.esp_rom_crc8_le +func EspRomCrc8Le(crc c.Uint8T, buf *c.Uint8T, len c.Uint32T) c.Uint8T + +/** + * @brief CRC8 value in big endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC8 value + */ +//go:linkname EspRomCrc8Be C.esp_rom_crc8_be +func EspRomCrc8Be(crc c.Uint8T, buf *c.Uint8T, len c.Uint32T) c.Uint8T diff --git a/esp32/esp_rom_efuse.go b/esp32/esp_rom_efuse.go new file mode 100644 index 00000000..51359383 --- /dev/null +++ b/esp32/esp_rom_efuse.go @@ -0,0 +1,60 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief A CRC8 algorithm used for MAC addresses stored in eFuse + * + * @param data Pointer to the original data + * @param len Data length in byte + * @return uint8_t CRC value + */ +//go:linkname EspRomEfuseMacAddressCrc8 C.esp_rom_efuse_mac_address_crc8 +func EspRomEfuseMacAddressCrc8(data *c.Uint8T, len c.Uint32T) c.Uint8T + +/** + * @brief Get SPI Flash GPIO pin configurations from eFuse + * + * @return uint32_t + * - 0: default SPI pins (ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) + * - 1: default HSPI pins (ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) + * - Others: Customized pin configuration mask. Pins are encoded as per the + * EFUSE_SPICONFIG_RET_SPICLK, EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, + * EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros. + * + * @note WP pin (for quad I/O modes) is not saved in eFuse and not returned by this function. + */ +//go:linkname EspRomEfuseGetFlashGpioInfo C.esp_rom_efuse_get_flash_gpio_info +func EspRomEfuseGetFlashGpioInfo() c.Uint32T + +/** + * @brief Get SPI Flash WP pin information from eFuse + * + * @return uint32_t + * - 0x3F: invalid GPIO number + * - 0~46: valid GPIO number + */ +//go:linkname EspRomEfuseGetFlashWpGpio C.esp_rom_efuse_get_flash_wp_gpio +func EspRomEfuseGetFlashWpGpio() c.Uint32T + +/** + * @brief Read opi flash pads configuration from Efuse + * + * @return + * - 0 for default SPI pins. + * - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for: + * DQS, D4, D5, D6, D7 accordingly. + */ +//go:linkname EspRomEfuseGetOpiconfig C.esp_rom_efuse_get_opiconfig +func EspRomEfuseGetOpiconfig() c.Uint32T + +/** + * @brief Read eFuse to check whether secure boot has been enabled or not + * + * @return true if secure boot is enabled, otherwise false + */ +//go:linkname EspRomEfuseIsSecureBootEnabled C.esp_rom_efuse_is_secure_boot_enabled +func EspRomEfuseIsSecureBootEnabled() bool diff --git a/esp32/esp_rom_gpio.go b/esp32/esp_rom_gpio.go new file mode 100644 index 00000000..b700ec3c --- /dev/null +++ b/esp32/esp_rom_gpio.go @@ -0,0 +1,73 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Configure IO Pad as General Purpose IO, + * so that it can be connected to internal Matrix, + * then combined with one or more peripheral signals. + * + * @param iopad_num IO Pad number + */ +//go:linkname EspRomGpioPadSelectGpio C.esp_rom_gpio_pad_select_gpio +func EspRomGpioPadSelectGpio(iopad_num c.Uint32T) + +/** + * @brief Enable internal pull up, and disable internal pull down. + * + * @param iopad_num IO Pad number + */ +//go:linkname EspRomGpioPadPullupOnly C.esp_rom_gpio_pad_pullup_only +func EspRomGpioPadPullupOnly(iopad_num c.Uint32T) + +/** + * @brief Unhold the IO Pad. + * @note When the Pad is set to hold, the state is latched at that moment and won't get changed. + * + * @param iopad_num IP Pad number + */ +//go:linkname EspRomGpioPadUnhold C.esp_rom_gpio_pad_unhold +func EspRomGpioPadUnhold(gpio_num c.Uint32T) + +/** + * @brief Set IO Pad current drive capability. + * + * @param iopad_num IO Pad number + * @param drv Numeric to indicate the capability of current drive + * - 0: 5mA + * - 1: 10mA + * - 2: 20mA + * - 3: 40mA + */ +//go:linkname EspRomGpioPadSetDrv C.esp_rom_gpio_pad_set_drv +func EspRomGpioPadSetDrv(iopad_num c.Uint32T, drv c.Uint32T) + +/** + * @brief Combine a GPIO input with a peripheral signal, which tagged as input attribute. + * + * @note There's no limitation on the number of signals that a GPIO can combine with. + * + * @param gpio_num GPIO number, especially, `GPIO_MATRIX_CONST_ZERO_INPUT` means connect logic 0 to signal + * `GPIO_MATRIX_CONST_ONE_INPUT` means connect logic 1 to signal + * @param signal_idx Peripheral signal index (tagged as input attribute) + * @param inv Whether the GPIO input to be inverted or not + */ +//go:linkname EspRomGpioConnectInSignal C.esp_rom_gpio_connect_in_signal +func EspRomGpioConnectInSignal(gpio_num c.Uint32T, signal_idx c.Uint32T, inv bool) + +/** + * @brief Combine a peripheral signal which tagged as output attribute with a GPIO. + * + * @note There's no limitation on the number of signals that a GPIO can combine with. + * @note Internally, the signal will be connected first, then output will be enabled on the pad. + * + * @param gpio_num GPIO number + * @param signal_idx Peripheral signal index (tagged as output attribute). Particularly, `SIG_GPIO_OUT_IDX` means disconnect GPIO and other peripherals. Only the GPIO driver can control the output level. + * @param out_inv Whether to signal to be inverted or not + * @param oen_inv Whether the output enable control is inverted or not + */ +//go:linkname EspRomGpioConnectOutSignal C.esp_rom_gpio_connect_out_signal +func EspRomGpioConnectOutSignal(gpio_num c.Uint32T, signal_idx c.Uint32T, out_inv bool, oen_inv bool) diff --git a/esp32/esp_rom_lldesc.go b/esp32/esp_rom_lldesc.go new file mode 100644 index 00000000..d9a99898 --- /dev/null +++ b/esp32/esp_rom_lldesc.go @@ -0,0 +1,19 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* this bitfield is start from the LSB!!! */ + +type LldescS struct { + Size c.Uint32T + Length c.Uint32T + Offset c.Uint32T + Sosf c.Uint32T + Eof c.Uint32T + Owner c.Uint32T + Buf *c.Uint8T +} +type LldescT LldescS diff --git a/esp32/esp_rom_md5.go b/esp32/esp_rom_md5.go new file mode 100644 index 00000000..1051d1c5 --- /dev/null +++ b/esp32/esp_rom_md5.go @@ -0,0 +1,49 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ESP_ROM_MD5_DIGEST_LEN = 16 + +/** + * @brief Type defined for MD5 context + * + */ + +type MD5Context struct { + Buf [4]c.Uint32T + Bits [2]c.Uint32T + In [64]c.Uint8T +} +type Md5ContextT MD5Context + +/** + * @brief Initialize the MD5 context + * + * @param context Context object allocated by user + */ +// llgo:link (*Md5ContextT).EspRomMd5Init C.esp_rom_md5_init +func (recv_ *Md5ContextT) EspRomMd5Init() { +} + +/** + * @brief Running MD5 algorithm over input data + * + * @param context MD5 context which has been initialized by `MD5Init` + * @param buf Input buffer + * @param len Buffer length in bytes + */ +// llgo:link (*Md5ContextT).EspRomMd5Update C.esp_rom_md5_update +func (recv_ *Md5ContextT) EspRomMd5Update(buf c.Pointer, len c.Uint32T) { +} + +/** + * @brief Extract the MD5 result, and erase the context + * + * @param digest Where to store the 128-bit digest value + * @param context MD5 context + */ +//go:linkname EspRomMd5Final C.esp_rom_md5_final +func EspRomMd5Final(digest *c.Uint8T, context *Md5ContextT) diff --git a/esp32/esp_rom_multi_heap.go b/esp32/esp_rom_multi_heap.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/esp_rom_multi_heap.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/esp_rom_regi2c.go b/esp32/esp_rom_regi2c.go new file mode 100644 index 00000000..f79c9873 --- /dev/null +++ b/esp32/esp_rom_regi2c.go @@ -0,0 +1,54 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Read internal register + * + * @param block Block of the register + * @param host_id Host of the register + * @param reg_add Address of the register + * @return uint8_t Register value + */ +//go:linkname EspRomRegi2cRead C.esp_rom_regi2c_read +func EspRomRegi2cRead(block c.Uint8T, host_id c.Uint8T, reg_add c.Uint8T) c.Uint8T + +/** + * @brief Read internal register, in bits + * + * @param block Block of the register + * @param host_id Host of the register + * @param reg_add Address of the register + * @param msb MSB of the register + * @param lsb LSB of the register + * @return uint8_t Register value + */ +//go:linkname EspRomRegi2cReadMask C.esp_rom_regi2c_read_mask +func EspRomRegi2cReadMask(block c.Uint8T, host_id c.Uint8T, reg_add c.Uint8T, msb c.Uint8T, lsb c.Uint8T) c.Uint8T + +/** + * @brief Write internal register + * + * @param block Block of the register + * @param host_id Host of the register + * @param reg_add Address of the register + * @param data Value to write + */ +//go:linkname EspRomRegi2cWrite C.esp_rom_regi2c_write +func EspRomRegi2cWrite(block c.Uint8T, host_id c.Uint8T, reg_add c.Uint8T, data c.Uint8T) + +/** + * @brief Write internal register, in bits + * + * @param block Block of the register + * @param host_id Host of the register + * @param reg_add Address of the register + * @param msb MSB of the register + * @param lsb LSB of the register + * @param data Value to write + */ +//go:linkname EspRomRegi2cWriteMask C.esp_rom_regi2c_write_mask +func EspRomRegi2cWriteMask(block c.Uint8T, host_id c.Uint8T, reg_add c.Uint8T, msb c.Uint8T, lsb c.Uint8T, data c.Uint8T) diff --git a/esp32/esp_rom_spiflash.go b/esp32/esp_rom_spiflash.go new file mode 100644 index 00000000..0c91bf97 --- /dev/null +++ b/esp32/esp_rom_spiflash.go @@ -0,0 +1,385 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EspRomSpiflashReadModeT c.Int + +const ( + ESP_ROM_SPIFLASH_QIO_MODE EspRomSpiflashReadModeT = 0 + ESP_ROM_SPIFLASH_QOUT_MODE EspRomSpiflashReadModeT = 1 + ESP_ROM_SPIFLASH_DIO_MODE EspRomSpiflashReadModeT = 2 + ESP_ROM_SPIFLASH_DOUT_MODE EspRomSpiflashReadModeT = 3 + ESP_ROM_SPIFLASH_FASTRD_MODE EspRomSpiflashReadModeT = 4 + ESP_ROM_SPIFLASH_SLOWRD_MODE EspRomSpiflashReadModeT = 5 + ESP_ROM_SPIFLASH_OPI_STR_MODE EspRomSpiflashReadModeT = 6 + ESP_ROM_SPIFLASH_OPI_DTR_MODE EspRomSpiflashReadModeT = 7 + ESP_ROM_SPIFLASH_OOUT_MODE EspRomSpiflashReadModeT = 8 + ESP_ROM_SPIFLASH_OIO_STR_MODE EspRomSpiflashReadModeT = 9 + ESP_ROM_SPIFLASH_OIO_DTR_MODE EspRomSpiflashReadModeT = 10 + ESP_ROM_SPIFLASH_QPI_MODE EspRomSpiflashReadModeT = 11 + ESP_ROM_SPIFLASH_OPI_HEX_DTR_MODE EspRomSpiflashReadModeT = 12 +) + +type EspRomSpiflashChipT struct { + DeviceId c.Uint32T + ChipSize c.Uint32T + BlockSize c.Uint32T + SectorSize c.Uint32T + PageSize c.Uint32T + StatusMask c.Uint32T +} +type EspRomSpiflashResultT c.Int + +const ( + ESP_ROM_SPIFLASH_RESULT_OK EspRomSpiflashResultT = 0 + ESP_ROM_SPIFLASH_RESULT_ERR EspRomSpiflashResultT = 1 + ESP_ROM_SPIFLASH_RESULT_TIMEOUT EspRomSpiflashResultT = 2 +) + +/** + * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode. + * Please do not call this function in SDK. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @param uint8_t legacy: always keeping false. + * + * @return None + */ +//go:linkname EspRomSpiflashAttach C.esp_rom_spiflash_attach +func EspRomSpiflashAttach(ishspi c.Uint32T, legacy bool) + +/** + * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +// llgo:link (*EspRomSpiflashChipT).EspRomSpiflashReadStatus C.esp_rom_spiflash_read_status +func (recv_ *EspRomSpiflashChipT) EspRomSpiflashReadStatus(status *c.Uint32T) EspRomSpiflashResultT { + return 0 +} + +/** + * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +// llgo:link (*EspRomSpiflashChipT).EspRomSpiflashReadStatushigh C.esp_rom_spiflash_read_statushigh +func (recv_ *EspRomSpiflashChipT) EspRomSpiflashReadStatushigh(status *c.Uint32T) EspRomSpiflashResultT { + return 0 +} + +/** + * @brief Write status to Flash status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t status_value : Value to . + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. + */ +// llgo:link (*EspRomSpiflashChipT).EspRomSpiflashWriteStatus C.esp_rom_spiflash_write_status +func (recv_ *EspRomSpiflashChipT) EspRomSpiflashWriteStatus(status_value c.Uint32T) EspRomSpiflashResultT { + return 0 +} + +/** + * @brief Use a command to Read Flash status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t*status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +//go:linkname EspRomSpiflashReadUserCmd C.esp_rom_spiflash_read_user_cmd +func EspRomSpiflashReadUserCmd(status *c.Uint32T, cmd c.Uint8T) EspRomSpiflashResultT + +/** + * @brief Config SPI Flash read mode when init. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. + * + * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +// llgo:link EspRomSpiflashReadModeT.EspRomSpiflashConfigReadmode C.esp_rom_spiflash_config_readmode +func (recv_ EspRomSpiflashReadModeT) EspRomSpiflashConfigReadmode() EspRomSpiflashResultT { + return 0 +} + +/** + * @brief Config SPI Flash clock divisor. + * Please do not call this function in SDK. + * + * @param uint8_t freqdiv: clock divisor. + * + * @param uint8_t spi: 0 for SPI0, 1 for SPI1. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +//go:linkname EspRomSpiflashConfigClk C.esp_rom_spiflash_config_clk +func EspRomSpiflashConfigClk(freqdiv c.Uint8T, spi c.Uint8T) EspRomSpiflashResultT + +/** + * @brief Update SPI Flash parameter. + * Please do not call this function in SDK. + * + * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. + * + * @param uint32_t chip_size : The Flash size. + * + * @param uint32_t block_size : The Flash block size. + * + * @param uint32_t sector_size : The Flash sector size. + * + * @param uint32_t page_size : The Flash page size. + * + * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. + */ +//go:linkname EspRomSpiflashConfigParam C.esp_rom_spiflash_config_param +func EspRomSpiflashConfigParam(deviceId c.Uint32T, chip_size c.Uint32T, block_size c.Uint32T, sector_size c.Uint32T, page_size c.Uint32T, status_mask c.Uint32T) EspRomSpiflashResultT + +/** + * @brief Erase whole flash chip. + * Please do not call this function in SDK. + * + * @param None + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +//go:linkname EspRomSpiflashEraseChip C.esp_rom_spiflash_erase_chip +func EspRomSpiflashEraseChip() EspRomSpiflashResultT + +/** + * @brief Erase a 64KB block of flash + * Uses SPI flash command D8H. + * Please do not call this function in SDK. + * + * @param uint32_t block_num : Which block to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +//go:linkname EspRomSpiflashEraseBlock C.esp_rom_spiflash_erase_block +func EspRomSpiflashEraseBlock(block_num c.Uint32T) EspRomSpiflashResultT + +/** + * @brief Erase a sector of flash. + * Uses SPI flash command 20H. + * Please do not call this function in SDK. + * + * @param uint32_t sector_num : Which sector to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +//go:linkname EspRomSpiflashEraseSector C.esp_rom_spiflash_erase_sector +func EspRomSpiflashEraseSector(sector_num c.Uint32T) EspRomSpiflashResultT + +/** + * @brief Erase some sectors. + * Please do not call this function in SDK. + * + * @param uint32_t start_addr : Start addr to erase, should be sector aligned. + * + * @param uint32_t area_len : Length to erase, should be sector aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +//go:linkname EspRomSpiflashEraseArea C.esp_rom_spiflash_erase_area +func EspRomSpiflashEraseArea(start_addr c.Uint32T, area_len c.Uint32T) EspRomSpiflashResultT + +/** + * @brief Write Data to Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. + * + * @param const uint32_t *src : The pointer to data which is to write. + * + * @param uint32_t len : Length to write, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. + */ +//go:linkname EspRomSpiflashWrite C.esp_rom_spiflash_write +func EspRomSpiflashWrite(dest_addr c.Uint32T, src *c.Uint32T, len c.Int32T) EspRomSpiflashResultT + +/** + * @brief Read Data from Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. + * + * @param uint32_t *dest : The buf to read the data. + * + * @param uint32_t len : Length to read, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. + */ +//go:linkname EspRomSpiflashRead C.esp_rom_spiflash_read +func EspRomSpiflashRead(src_addr c.Uint32T, dest *c.Uint32T, len c.Int32T) EspRomSpiflashResultT + +/** + * @brief SPI1 go into encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +//go:linkname EspRomSpiflashWriteEncryptedEnable C.esp_rom_spiflash_write_encrypted_enable +func EspRomSpiflashWriteEncryptedEnable() + +/** + * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. + * + * @param uint32_t *data : The pointer to data which is to write. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. + */ +//go:linkname EspRomSpiflashPrepareEncryptedData C.esp_rom_spiflash_prepare_encrypted_data +func EspRomSpiflashPrepareEncryptedData(flash_addr c.Uint32T, data *c.Uint32T) EspRomSpiflashResultT + +/** + * @brief SPI1 go out of encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +//go:linkname EspRomSpiflashWriteEncryptedDisable C.esp_rom_spiflash_write_encrypted_disable +func EspRomSpiflashWriteEncryptedDisable() + +/** + * @brief Write data to flash with transparent encryption. + * @note Sectors to be written should already be erased. + * + * @note Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. + * + * @param uint32_t *data : The pointer to data to write. Note, this pointer must + * be 32 bit aligned and the content of the data will be + * modified by the encryption function. + * + * @param uint32_t len : Length to write, should be 32 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. + * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. + */ +//go:linkname EspRomSpiflashWriteEncrypted C.esp_rom_spiflash_write_encrypted +func EspRomSpiflashWriteEncrypted(flash_addr c.Uint32T, data *c.Uint32T, len c.Uint32T) EspRomSpiflashResultT + +/** @brief Wait until SPI flash write operation is complete + * + * @note Please do not call this function in SDK. + * + * Reads the Write In Progress bit of the SPI flash status register, + * repeats until this bit is zero (indicating write complete). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete + * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. + */ +// llgo:link (*EspRomSpiflashChipT).EspRomSpiflashWaitIdle C.esp_rom_spiflash_wait_idle +func (recv_ *EspRomSpiflashChipT) EspRomSpiflashWaitIdle() EspRomSpiflashResultT { + return 0 +} + +/** @brief Enable Quad I/O pin functions + * + * @note Please do not call this function in SDK. + * + * Sets the HD & WP pin functions for Quad I/O modes, based on the + * efuse SPI pin configuration. + * + * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. + * + * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). + * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. + * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. + * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used + * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). + * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. + */ +//go:linkname EspRomSpiflashSelectQioPins C.esp_rom_spiflash_select_qio_pins +func EspRomSpiflashSelectQioPins(wp_gpio_num c.Uint8T, spiconfig c.Uint32T) + +/** + * @brief Clear WEL bit unconditionally. + * + * @return always ESP_ROM_SPIFLASH_RESULT_OK + */ +//go:linkname EspRomSpiflashWriteDisable C.esp_rom_spiflash_write_disable +func EspRomSpiflashWriteDisable() EspRomSpiflashResultT + +/** + * @brief Set WREN bit. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @return always ESP_ROM_SPIFLASH_RESULT_OK + */ +// llgo:link (*EspRomSpiflashChipT).EspRomSpiflashWriteEnable C.esp_rom_spiflash_write_enable +func (recv_ *EspRomSpiflashChipT) EspRomSpiflashWriteEnable() EspRomSpiflashResultT { + return 0 +} + +/* Flash data defined in ROM*/ + +type EspRomSpiflashLegacyDataT struct { + Chip EspRomSpiflashChipT + DummyLenPlus [3]c.Uint8T + SigMatrix c.Uint8T +} diff --git a/esp32/esp_rom_spiflash_defs.go b/esp32/esp_rom_spiflash_defs.go new file mode 100644 index 00000000..e3fe8109 --- /dev/null +++ b/esp32/esp_rom_spiflash_defs.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +const FLASH_ID_GD25LQ32C = 0xC86016 diff --git a/esp32/esp_rom_sys.go b/esp32/esp_rom_sys.go new file mode 100644 index 00000000..d1cf687a --- /dev/null +++ b/esp32/esp_rom_sys.go @@ -0,0 +1,126 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Software Reset digital core include RTC. + * + * It is not recommended to use this function in esp-idf, use + * esp_restart() instead. + */ +//go:linkname EspRomSoftwareResetSystem C.esp_rom_software_reset_system +func EspRomSoftwareResetSystem() + +/** + * @brief Software Reset cpu core. + * + * It is not recommended to use this function in esp-idf, use + * esp_restart() instead. + * + * @param cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU. + */ +//go:linkname EspRomSoftwareResetCpu C.esp_rom_software_reset_cpu +func EspRomSoftwareResetCpu(cpu_no c.Int) + +/** + * @brief Print formatted string to console device + * @note float and long long data are not supported! + * + * @param fmt Format string + * @param ... Additional arguments, depending on the format string + * @return int: Total number of characters written on success; A negative number on failure. + */ +//go:linkname EspRomPrintf C.esp_rom_printf +func EspRomPrintf(fmt *c.Char, __llgo_va_list ...interface{}) c.Int + +/** + * @brief Print formatted string to console device + * @note float and long long data are not supported! + * + * @param fmt Format string + * @param ap List of arguments. + * @return int: Total number of characters written on success; A negative number on failure. + */ +//go:linkname EspRomVprintf C.esp_rom_vprintf +func EspRomVprintf(fmt *c.Char, ap c.VaList) c.Int + +/** + * @brief Pauses execution for us microseconds + * + * @param us Number of microseconds to pause + */ +//go:linkname EspRomDelayUs C.esp_rom_delay_us +func EspRomDelayUs(us c.Uint32T) + +/** + * @brief esp_rom_printf can print message to different channels simultaneously. + * This function can help install the low level putc function for esp_rom_printf. + * + * @param channel Channel number (starting from 1) + * @param putc Function pointer to the putc implementation. Set NULL can disconnect esp_rom_printf with putc. + */ +//go:linkname EspRomInstallChannelPutc C.esp_rom_install_channel_putc +func EspRomInstallChannelPutc(channel c.Int, putc func(c.Char)) + +/** + * @brief It outputs a character to different channels simultaneously. + * This function is used by esp_rom_printf/esp_rom_vprintf. + * + * @param c Char to output. + */ +//go:linkname EspRomOutputToChannels C.esp_rom_output_to_channels +func EspRomOutputToChannels(c c.Char) + +/** + * @brief Install UART1 as the default console channel, equivalent to `esp_rom_install_channel_putc(1, esp_rom_output_putc)` + */ +//go:linkname EspRomInstallUartPrintf C.esp_rom_install_uart_printf +func EspRomInstallUartPrintf() + +/** + * @brief Get reset reason of CPU + * + * @param cpu_no CPU number + * @return Reset reason code (see in soc/reset_reasons.h) + */ +//go:linkname EspRomGetResetReason C.esp_rom_get_reset_reason +func EspRomGetResetReason(cpu_no c.Int) SocResetReasonT + +/** + * @brief Route peripheral interrupt sources to CPU's interrupt port by matrix + * + * Usually there're 4 steps to use an interrupt: + * 1. Route peripheral interrupt source to CPU. e.g. esp_rom_route_intr_matrix(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM) + * 2. Set interrupt handler for CPU + * 3. Enable CPU interrupt + * 4. Enable peripheral interrupt + * + * @param cpu_core The CPU number, which the peripheral interrupt will inform to + * @param periph_intr_id The peripheral interrupt source number + * @param cpu_intr_num The CPU (external) interrupt number. On targets that use CLIC as their interrupt controller, + * this number represents the external interrupt number. For example, passing `cpu_intr_num = i` + * to this function would in fact bind peripheral source to CPU interrupt `CLIC_EXT_INTR_NUM_OFFSET + i`. + */ +//go:linkname EspRomRouteIntrMatrix C.esp_rom_route_intr_matrix +func EspRomRouteIntrMatrix(cpu_core c.Int, periph_intr_id c.Uint32T, cpu_intr_num c.Uint32T) + +/** + * @brief Get the real CPU ticks per us + * + * @return CPU ticks per us + */ +//go:linkname EspRomGetCpuTicksPerUs C.esp_rom_get_cpu_ticks_per_us +func EspRomGetCpuTicksPerUs() c.Uint32T + +/** + * @brief Set the real CPU tick rate + * + * @note Call this function when CPU frequency is changed, otherwise the `esp_rom_delay_us` can be inaccurate. + * + * @param ticks_per_us CPU ticks per us + */ +//go:linkname EspRomSetCpuTicksPerUs C.esp_rom_set_cpu_ticks_per_us +func EspRomSetCpuTicksPerUs(ticks_per_us c.Uint32T) diff --git a/esp32/esp_rom_tlsf.go b/esp32/esp_rom_tlsf.go new file mode 100644 index 00000000..7c6a5b60 --- /dev/null +++ b/esp32/esp_rom_tlsf.go @@ -0,0 +1,34 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:type C +type PoisonFillPfuncT func(c.Pointer, c.SizeT, bool) + +// llgo:type C +type PoisonCheckPfuncT func(c.Pointer, c.SizeT, bool, bool) bool + +/*! + * @brief Set the function to call for filling memory region when + * poisoning is configured. + * + * @note Please keep in mind that this function in ROM still accepts void*. + * + * @param pfunc The callback function to trigger for poisoning + * a memory region. + */ +//go:linkname TlsfPoisonFillPfuncSet C.tlsf_poison_fill_pfunc_set +func TlsfPoisonFillPfuncSet(pfunc PoisonFillPfuncT) + +/*! + * @brief Set the function to call for checking memory region when + * poisoning is configured. + * + * @param pfunc The callback function to trigger for checking + * the content of a memory region. + */ +//go:linkname TlsfPoisonCheckPfuncSet C.tlsf_poison_check_pfunc_set +func TlsfPoisonCheckPfuncSet(pfunc PoisonCheckPfuncT) diff --git a/esp32/esp_rom_uart.go b/esp32/esp_rom_uart.go new file mode 100644 index 00000000..7193add3 --- /dev/null +++ b/esp32/esp_rom_uart.go @@ -0,0 +1,132 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ESP_ROM_CDC_ACM_WORK_BUF_MIN = 128 + +type EspRomUartNumT c.Int + +const ( + ESP_ROM_UART_0 EspRomUartNumT = 0 + ESP_ROM_UART_1 EspRomUartNumT = 1 + ESP_ROM_UART_USB EspRomUartNumT = 2 +) + +/** + * @brief Wait for UART TX FIFO is empty and all data has been sent out. + * + * @param serial_num The serial number defined in ROM, including UART_x, USB_OTG, USB_SERIAL_JTAG.. + */ +//go:linkname EspRomOutputTxWaitIdle C.esp_rom_output_tx_wait_idle +func EspRomOutputTxWaitIdle(serial_num c.Uint8T) + +//go:linkname EspRomUartTxWaitIdle C.esp_rom_uart_tx_wait_idle +func EspRomUartTxWaitIdle(serial_num c.Uint8T) + +/** + * @brief Wait until UART TX FIFO is empty (i.e. flush TX FIFO) + * + * @param serial_num UART port number + */ +//go:linkname EspRomOutputFlushTx C.esp_rom_output_flush_tx +func EspRomOutputFlushTx(serial_num c.Uint8T) + +//go:linkname EspRomUartFlushTx C.esp_rom_uart_flush_tx +func EspRomUartFlushTx(serial_num c.Uint8T) + +/** + * @brief Transmit one character to the console channel. + * + * @param c Character to send + * @return + * - 0 on success + * - 1 on failure + */ +//go:linkname EspRomOutputTxOneChar C.esp_rom_output_tx_one_char +func EspRomOutputTxOneChar(c c.Uint8T) c.Int + +//go:linkname EspRomUartTxOneChar C.esp_rom_uart_tx_one_char +func EspRomUartTxOneChar(c c.Uint8T) c.Int + +/** + * @brief Transmit one character to the console channel. + * @note This function is a wrapper over esp_rom_uart_tx_one_char, it can help handle line ending issue by replacing '\n' with '\r\n'. + * + * @param c Character to send + */ +//go:linkname EspRomOutputPutc C.esp_rom_output_putc +func EspRomOutputPutc(c c.Char) + +//go:linkname EspRomUartPutc C.esp_rom_uart_putc +func EspRomUartPutc(c c.Char) + +/** + * @brief Get one character from the console channel. + * + * @param c Where to store the character + * @return + * - 0 on success + * - 1 on failure or no data available + */ +//go:linkname EspRomOutputRxOneChar C.esp_rom_output_rx_one_char +func EspRomOutputRxOneChar(c *c.Uint8T) c.Int + +//go:linkname EspRomUartRxOneChar C.esp_rom_uart_rx_one_char +func EspRomUartRxOneChar(c *c.Uint8T) c.Int + +/** + * @brief Get one line of string from console channel (line ending won't be stored in the buffer). + * + * @param str Where to store the string + * @param max_len Maximum length of the buffer (including the NULL delimiter) + * @return always return 0 when on success or wait in a loop for rx data + */ +//go:linkname EspRomOutputRxString C.esp_rom_output_rx_string +func EspRomOutputRxString(str *c.Uint8T, max_len c.Uint8T) c.Int + +//go:linkname EspRomUartRxString C.esp_rom_uart_rx_string +func EspRomUartRxString(str *c.Uint8T, max_len c.Uint8T) c.Int + +/** + * @brief Set the UART port used by ets_printf. + * + * @note USB-CDC port is also treated as "UART" port in the ROM code. + * Use ESP_ROM_USB_SERIAL_DEVICE_NUM or ESP_ROM_USB_OTG_NUM to identify USB_SERIAL_JTAG and USB_OTG, respectively. + * + * @param serial_num UART port number + */ +//go:linkname EspRomOutputSetAsConsole C.esp_rom_output_set_as_console +func EspRomOutputSetAsConsole(serial_num c.Uint8T) + +//go:linkname EspRomUartSetAsConsole C.esp_rom_uart_set_as_console +func EspRomUartSetAsConsole(serial_num c.Uint8T) + +/** + * @brief Switch the UART port that will use a buffer for TX and RX. + * + * @note USB-CDC port is also treated as "UART" port in the ROM code. + * Use ESP_ROM_USB_SERIAL_DEVICE_NUM or ESP_ROM_USB_OTG_NUM to identify USB_SERIAL_JTAG and USB_OTG, respectively. + * + * @param serial_num UART port number + */ +//go:linkname EspRomOutputSwitchBuffer C.esp_rom_output_switch_buffer +func EspRomOutputSwitchBuffer(serial_num c.Uint8T) + +//go:linkname EspRomUartSwitchBuffer C.esp_rom_uart_switch_buffer +func EspRomUartSwitchBuffer(serial_num c.Uint8T) + +/** + * @brief Initialize the USB ACM UART + * @note The ACM working memroy should be at least 128 bytes (ESP_ROM_CDC_ACM_WORK_BUF_MIN) in size. + * + * @param cdc_acm_work_mem Pointer to the work memroy used for CDC-ACM + * @param cdc_acm_work_mem_len Length of work memory + */ +//go:linkname EspRomOutputUsbAcmInit C.esp_rom_output_usb_acm_init +func EspRomOutputUsbAcmInit(cdc_acm_work_mem c.Pointer, cdc_acm_work_mem_len c.Int) + +//go:linkname EspRomUartUsbAcmInit C.esp_rom_uart_usb_acm_init +func EspRomUartUsbAcmInit(serial_num c.Uint8T) diff --git a/esp32/esp_sleep.go b/esp32/esp_sleep.go new file mode 100644 index 00000000..9d3b02a8 --- /dev/null +++ b/esp32/esp_sleep.go @@ -0,0 +1,656 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:type C +type EspDeepSleepCbT func() +type EspSleepExt1WakeupModeT c.Int + +const ( + ESP_EXT1_WAKEUP_ANY_LOW EspSleepExt1WakeupModeT = 0 + ESP_EXT1_WAKEUP_ANY_HIGH EspSleepExt1WakeupModeT = 1 + ESP_EXT1_WAKEUP_ALL_LOW EspSleepExt1WakeupModeT = 0 +) + +type EspSleepPdDomainT c.Int + +const ( + ESP_PD_DOMAIN_RTC_PERIPH EspSleepPdDomainT = 0 + ESP_PD_DOMAIN_XTAL EspSleepPdDomainT = 1 + ESP_PD_DOMAIN_RC_FAST EspSleepPdDomainT = 2 + ESP_PD_DOMAIN_CPU EspSleepPdDomainT = 3 + ESP_PD_DOMAIN_VDDSDIO EspSleepPdDomainT = 4 + ESP_PD_DOMAIN_MODEM EspSleepPdDomainT = 5 + ESP_PD_DOMAIN_MAX EspSleepPdDomainT = 6 +) + +type EspSleepPdOptionT c.Int + +const ( + ESP_PD_OPTION_OFF EspSleepPdOptionT = 0 + ESP_PD_OPTION_ON EspSleepPdOptionT = 1 + ESP_PD_OPTION_AUTO EspSleepPdOptionT = 2 +) + +type EspSleepSourceT c.Int + +const ( + ESP_SLEEP_WAKEUP_UNDEFINED EspSleepSourceT = 0 + ESP_SLEEP_WAKEUP_ALL EspSleepSourceT = 1 + ESP_SLEEP_WAKEUP_EXT0 EspSleepSourceT = 2 + ESP_SLEEP_WAKEUP_EXT1 EspSleepSourceT = 3 + ESP_SLEEP_WAKEUP_TIMER EspSleepSourceT = 4 + ESP_SLEEP_WAKEUP_TOUCHPAD EspSleepSourceT = 5 + ESP_SLEEP_WAKEUP_ULP EspSleepSourceT = 6 + ESP_SLEEP_WAKEUP_GPIO EspSleepSourceT = 7 + ESP_SLEEP_WAKEUP_UART EspSleepSourceT = 8 + ESP_SLEEP_WAKEUP_WIFI EspSleepSourceT = 9 + ESP_SLEEP_WAKEUP_COCPU EspSleepSourceT = 10 + ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG EspSleepSourceT = 11 + ESP_SLEEP_WAKEUP_BT EspSleepSourceT = 12 + ESP_SLEEP_WAKEUP_VAD EspSleepSourceT = 13 +) + +type EspSleepModeT c.Int + +const ( + ESP_SLEEP_MODE_LIGHT_SLEEP EspSleepModeT = 0 + ESP_SLEEP_MODE_DEEP_SLEEP EspSleepModeT = 1 +) + +type EspSleepWakeupCauseT EspSleepSourceT + +const ( + ESP_ERR_SLEEP_REJECT c.Int = 259 + ESP_ERR_SLEEP_TOO_SHORT_SLEEP_DURATION c.Int = 258 +) + +/** + * @brief Disable wakeup source + * + * This function is used to deactivate wake up trigger for source + * defined as parameter of the function. + * + * @note This function does not modify wake up configuration in RTC. + * It will be performed in esp_deep_sleep_start/esp_light_sleep_start function. + * + * See docs/sleep-modes.rst for details. + * + * @param source - number of source to disable of type esp_sleep_source_t + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_STATE if trigger was not active + */ +// llgo:link EspSleepSourceT.EspSleepDisableWakeupSource C.esp_sleep_disable_wakeup_source +func (recv_ EspSleepSourceT) EspSleepDisableWakeupSource() EspErrT { + return 0 +} + +/** + * @brief Enable wakeup by ULP coprocessor + * @note On ESP32, ULP wakeup source cannot be used when RTC_PERIPH power domain is forced, + * to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup source is used. + * @return + * - ESP_OK on success + * - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT) is enabled. + * - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict + */ +//go:linkname EspSleepEnableUlpWakeup C.esp_sleep_enable_ulp_wakeup +func EspSleepEnableUlpWakeup() EspErrT + +/** + * @brief Enable wakeup by timer + * @param time_in_us time before wakeup, in microseconds + * @note The valid `time_in_us` value depends on the bit width of the lp_timer/rtc_timer counter and the + * current slow clock source selection (Refer RTC clock source configuration in menuconfig). + * Valid values should be positive values less than RTC slow clock period * (2 ^ RTC timer bitwidth). + * + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if value is out of range. + */ +//go:linkname EspSleepEnableTimerWakeup C.esp_sleep_enable_timer_wakeup +func EspSleepEnableTimerWakeup(time_in_us c.Uint64T) EspErrT + +/** + * @brief Enable wakeup by touch sensor + * + * @note On ESP32, touch wakeup source can not be used when RTC_PERIPH power domain is forced + * to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup source is used. + * + * @note The FSM mode of the touch button should be configured + * as the timer trigger mode. + * + * @return + * - ESP_OK on success + * - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT) is enabled. + * - ESP_ERR_INVALID_STATE if wakeup triggers conflict + */ +//go:linkname EspSleepEnableTouchpadWakeup C.esp_sleep_enable_touchpad_wakeup +func EspSleepEnableTouchpadWakeup() EspErrT + +/** + * @brief Get the touch pad which caused wakeup + * + * If wakeup was caused by another source, this function will return TOUCH_PAD_MAX; + * + * @return touch pad which caused wakeup + */ +//go:linkname EspSleepGetTouchpadWakeupStatus C.esp_sleep_get_touchpad_wakeup_status +func EspSleepGetTouchpadWakeupStatus() TouchPadT + +/** + * @brief Returns true if a GPIO number is valid for use as wakeup source. + * + * @note For SoCs with RTC IO capability, this can be any valid RTC IO input pin. + * + * @param gpio_num Number of the GPIO to test for wakeup source capability + * + * @return True if this GPIO number will be accepted as a sleep wakeup source. + */ +// llgo:link GpioNumT.EspSleepIsValidWakeupGpio C.esp_sleep_is_valid_wakeup_gpio +func (recv_ GpioNumT) EspSleepIsValidWakeupGpio() bool { + return false +} + +/** + * @brief Enable wakeup using a pin + * + * This function uses external wakeup feature of RTC_IO peripheral. + * It will work only if RTC peripherals are kept on during sleep. + * + * This feature can monitor any pin which is an RTC IO. Once the pin transitions + * into the state given by level argument, the chip will be woken up. + * + * @note This function does not modify pin configuration. The pin is + * configured in esp_deep_sleep_start/esp_light_sleep_start, + * immediately before entering sleep mode. + * + * @note ESP32: ext0 wakeup source can not be used together with touch or ULP wakeup sources. + * + * @param gpio_num GPIO number used as wakeup source. Only GPIOs with the RTC + * functionality can be used. For different SoCs, the related GPIOs are: + * - ESP32: 0, 2, 4, 12-15, 25-27, 32-39; + * - ESP32-S2: 0-21; + * - ESP32-S3: 0-21. + * @param level input level which will trigger wakeup (0=low, 1=high) + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the selected GPIO is not an RTC GPIO, + * or the mode is invalid + * - ESP_ERR_INVALID_STATE if wakeup triggers conflict + */ +// llgo:link GpioNumT.EspSleepEnableExt0Wakeup C.esp_sleep_enable_ext0_wakeup +func (recv_ GpioNumT) EspSleepEnableExt0Wakeup(level c.Int) EspErrT { + return 0 +} + +/** + * @brief Enable wakeup using multiple pins + * + * This function uses external wakeup feature of RTC controller. + * It will work even if RTC peripherals are shut down during sleep. + * + * This feature can monitor any number of pins which are in RTC IOs. + * Once selected pins go into the state given by level_mode argument, + * the chip will be woken up. + * + * @note This function does not modify pin configuration. The pins are + * configured in esp_deep_sleep_start/esp_light_sleep_start, + * immediately before entering sleep mode. + * + * @note Internal pullups and pulldowns don't work when RTC peripherals are + * shut down. In this case, external resistors need to be added. + * Alternatively, RTC peripherals (and pullups/pulldowns) may be + * kept enabled using esp_sleep_pd_config function. If we turn off the + * ``RTC_PERIPH`` domain or certain chips lack the ``RTC_PERIPH`` domain, + * we will use the HOLD feature to maintain the pull-up and pull-down on + * the pins during sleep. HOLD feature will be acted on the pin internally + * before the system entering sleep, and this can further reduce power consumption. + * + * @note Call this func will reset the previous ext1 configuration. + * + * @note This function will be deprecated in release/v6.0. Please switch to use `esp_sleep_enable_ext1_wakeup_io` and `esp_sleep_disable_ext1_wakeup_io` + * + * @param io_mask Bit mask of GPIO numbers which will cause wakeup. Only GPIOs + * which have RTC functionality can be used in this bit map. + * For different SoCs, the related GPIOs are: + * - ESP32: 0, 2, 4, 12-15, 25-27, 32-39 + * - ESP32-S2: 0-21 + * - ESP32-S3: 0-21 + * - ESP32-C6: 0-7 + * - ESP32-H2: 7-14 + * @param level_mode Select logic function used to determine wakeup condition: + * When target chip is ESP32: + * - ESP_EXT1_WAKEUP_ALL_LOW: wake up when all selected GPIOs are low + * - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high + * When target chip is ESP32-S2, ESP32-S3, ESP32-C6 or ESP32-H2: + * - ESP_EXT1_WAKEUP_ANY_LOW: wake up when any of the selected GPIOs is low + * - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if io_mask is zero,, + * or mode is invalid + */ +//go:linkname EspSleepEnableExt1Wakeup C.esp_sleep_enable_ext1_wakeup +func EspSleepEnableExt1Wakeup(io_mask c.Uint64T, level_mode EspSleepExt1WakeupModeT) EspErrT + +/** + * @brief Enable ext1 wakeup pins with IO masks. + * + * This will append selected IOs to the wakeup IOs, it will not reset previously enabled IOs. + * To reset specific previously enabled IOs, call esp_sleep_disable_ext1_wakeup_io with the io_mask. + * To reset all the enabled IOs, call esp_sleep_disable_ext1_wakeup_io(0). + * + * This function uses external wakeup feature of RTC controller. + * It will work even if RTC peripherals are shut down during sleep. + * + * This feature can monitor any number of pins which are in RTC IOs. + * Once selected pins go into the state given by level_mode argument, + * the chip will be woken up. + * + * @note This function does not modify pin configuration. The pins are + * configured in esp_deep_sleep_start/esp_light_sleep_start, + * immediately before entering sleep mode. + * + * @note Internal pullups and pulldowns don't work when RTC peripherals are + * shut down. In this case, external resistors need to be added. + * Alternatively, RTC peripherals (and pullups/pulldowns) may be + * kept enabled using esp_sleep_pd_config function. If we turn off the + * ``RTC_PERIPH`` domain or certain chips lack the ``RTC_PERIPH`` domain, + * we will use the HOLD feature to maintain the pull-up and pull-down on + * the pins during sleep. HOLD feature will be acted on the pin internally + * before the system entering sleep, and this can further reduce power consumption. + * + * @param io_mask Bit mask of GPIO numbers which will cause wakeup. Only GPIOs + * which have RTC functionality can be used in this bit map. + * For different SoCs, the related GPIOs are: + * - ESP32: 0, 2, 4, 12-15, 25-27, 32-39 + * - ESP32-S2: 0-21 + * - ESP32-S3: 0-21 + * - ESP32-C6: 0-7 + * - ESP32-H2: 7-14 + * @param level_mode Select logic function used to determine wakeup condition: + * When target chip is ESP32: + * - ESP_EXT1_WAKEUP_ALL_LOW: wake up when all selected GPIOs are low + * - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high + * When target chip is ESP32-S2, ESP32-S3, ESP32-C6 or ESP32-H2: + * - ESP_EXT1_WAKEUP_ANY_LOW: wake up when any of the selected GPIOs is low + * - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if any of the selected GPIOs is not an RTC GPIO, + * or mode is invalid + * - ESP_ERR_NOT_ALLOWED when wakeup level will become different between + * ext1 IOs if !SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN + */ +//go:linkname EspSleepEnableExt1WakeupIo C.esp_sleep_enable_ext1_wakeup_io +func EspSleepEnableExt1WakeupIo(io_mask c.Uint64T, level_mode EspSleepExt1WakeupModeT) EspErrT + +/** + * @brief Disable ext1 wakeup pins with IO masks. This will remove selected IOs from the wakeup IOs. + * @param io_mask Bit mask of GPIO numbers which will cause wakeup. Only GPIOs + * which have RTC functionality can be used in this bit map. + * If value is zero, this func will remove all previous ext1 configuration. + * For different SoCs, the related GPIOs are: + * - ESP32: 0, 2, 4, 12-15, 25-27, 32-39 + * - ESP32-S2: 0-21 + * - ESP32-S3: 0-21 + * - ESP32-C6: 0-7 + * - ESP32-H2: 7-14 + * + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if any of the selected GPIOs is not an RTC GPIO. + */ +//go:linkname EspSleepDisableExt1WakeupIo C.esp_sleep_disable_ext1_wakeup_io +func EspSleepDisableExt1WakeupIo(io_mask c.Uint64T) EspErrT + +/** + * @brief Enable wakeup from light sleep using GPIOs + * + * Each GPIO supports wakeup function, which can be triggered on either low level + * or high level. Unlike EXT0 and EXT1 wakeup sources, this method can be used + * both for all IOs: RTC IOs and digital IOs. It can only be used to wakeup from + * light sleep though. + * + * To enable wakeup, first call gpio_wakeup_enable, specifying gpio number and + * wakeup level, for each GPIO which is used for wakeup. + * Then call this function to enable wakeup feature. + * + * @note 1. On ESP32, GPIO wakeup source can not be used together with touch or ULP wakeup sources. + * 2. If PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP is enabled (if target supported), + * this API is unavailable since the GPIO module is powered down during sleep. + * You can use `esp_deep_sleep_enable_gpio_wakeup` instead, or use EXT1 wakeup source + * by `esp_sleep_enable_ext1_wakeup_io` to achieve the same function. + * (Only GPIOs which have RTC functionality can be used) + * + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_STATE if wakeup triggers conflict + */ +//go:linkname EspSleepEnableGpioWakeup C.esp_sleep_enable_gpio_wakeup +func EspSleepEnableGpioWakeup() EspErrT + +/** + * @brief Enable wakeup from light sleep using UART + * + * Use uart_set_wakeup_threshold function to configure UART wakeup threshold. + * + * Wakeup from light sleep takes some time, so not every character sent + * to the UART can be received by the application. + * + * @note 1. ESP32 does not support wakeup from UART2. + * 2. If PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP is enabled (if target supported), + * this API is unavailable since the UART module is powered down during sleep. + * + * @param uart_num UART port to wake up from + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if wakeup from given UART is not supported + */ +//go:linkname EspSleepEnableUartWakeup C.esp_sleep_enable_uart_wakeup +func EspSleepEnableUartWakeup(uart_num c.Int) EspErrT + +/** + * @brief Enable wakeup by bluetooth + * @return + * - ESP_OK on success + * - ESP_ERR_NOT_SUPPORTED if wakeup from bluetooth is not supported + */ +//go:linkname EspSleepEnableBtWakeup C.esp_sleep_enable_bt_wakeup +func EspSleepEnableBtWakeup() EspErrT + +/** + * @brief Disable wakeup by bluetooth + * @return + * - ESP_OK on success + * - ESP_ERR_NOT_SUPPORTED if wakeup from bluetooth is not supported + */ +//go:linkname EspSleepDisableBtWakeup C.esp_sleep_disable_bt_wakeup +func EspSleepDisableBtWakeup() EspErrT + +/** + * @brief Enable wakeup by WiFi MAC + * @return + * - ESP_OK on success + */ +//go:linkname EspSleepEnableWifiWakeup C.esp_sleep_enable_wifi_wakeup +func EspSleepEnableWifiWakeup() EspErrT + +/** + * @brief Disable wakeup by WiFi MAC + * @return + * - ESP_OK on success + */ +//go:linkname EspSleepDisableWifiWakeup C.esp_sleep_disable_wifi_wakeup +func EspSleepDisableWifiWakeup() EspErrT + +/** + * @brief Enable beacon wakeup by WiFi MAC, it will wake up the system into modem state + * @return + * - ESP_OK on success + */ +//go:linkname EspSleepEnableWifiBeaconWakeup C.esp_sleep_enable_wifi_beacon_wakeup +func EspSleepEnableWifiBeaconWakeup() EspErrT + +/** + * @brief Disable beacon wakeup by WiFi MAC + * @return + * - ESP_OK on success + */ +//go:linkname EspSleepDisableWifiBeaconWakeup C.esp_sleep_disable_wifi_beacon_wakeup +func EspSleepDisableWifiBeaconWakeup() EspErrT + +/** + * @brief Get the bit mask of GPIOs which caused wakeup (ext1) + * + * If wakeup was caused by another source, this function will return 0. + * + * @return bit mask, if GPIOn caused wakeup, BIT(n) will be set + */ +//go:linkname EspSleepGetExt1WakeupStatus C.esp_sleep_get_ext1_wakeup_status +func EspSleepGetExt1WakeupStatus() c.Uint64T + +/** + * @brief Set power down mode for an RTC power domain in sleep mode + * + * If not set set using this API, all power domains default to ESP_PD_OPTION_AUTO. + * + * @param domain power domain to configure + * @param option power down option (ESP_PD_OPTION_OFF, ESP_PD_OPTION_ON, or ESP_PD_OPTION_AUTO) + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if either of the arguments is out of range + */ +// llgo:link EspSleepPdDomainT.EspSleepPdConfig C.esp_sleep_pd_config +func (recv_ EspSleepPdDomainT) EspSleepPdConfig(option EspSleepPdOptionT) EspErrT { + return 0 +} + +/** + * @brief Enter deep sleep with the configured wakeup options + * + * @note In general, the function does not return, but if the sleep is rejected, + * then it returns from it. + * + * The reason for the rejection can be such as a short sleep time. + * + * @return + * - No return - If the sleep is not rejected. + * - ESP_ERR_SLEEP_REJECT sleep request is rejected(wakeup source set before the sleep request) + */ +//go:linkname EspDeepSleepTryToStart C.esp_deep_sleep_try_to_start +func EspDeepSleepTryToStart() EspErrT + +/** + * @brief Enter deep sleep with the configured wakeup options + * + * @note The function does not do a return (no rejection). Even if wakeup source set before the sleep request + * it goes to deep sleep anyway. + */ +//go:linkname EspDeepSleepStart C.esp_deep_sleep_start +func EspDeepSleepStart() + +/** + * @brief Enter light sleep with the configured wakeup options + * + * @return + * - ESP_OK on success (returned after wakeup) + * - ESP_ERR_SLEEP_REJECT sleep request is rejected(wakeup source set before the sleep request) + * - ESP_ERR_SLEEP_TOO_SHORT_SLEEP_DURATION after deducting the sleep flow overhead, the final sleep duration + * is too short to cover the minimum sleep duration of the chip, when + * rtc timer wakeup source enabled + */ +//go:linkname EspLightSleepStart C.esp_light_sleep_start +func EspLightSleepStart() EspErrT + +/** + * @brief Enter deep-sleep mode + * + * The device will automatically wake up after the deep-sleep time + * Upon waking up, the device calls deep sleep wake stub, and then proceeds + * to load application. + * + * Call to this function is equivalent to a call to esp_deep_sleep_enable_timer_wakeup + * followed by a call to esp_deep_sleep_start. + * + * @note In general, the function does not return, but if the sleep is rejected, + * then it returns from it. + * + * The reason for the rejection can be such as a short sleep time. + * + * @param time_in_us deep-sleep time, unit: microsecond + * + * @return + * - No return - If the sleep is not rejected. + * - ESP_ERR_SLEEP_REJECT sleep request is rejected(wakeup source set before the sleep request) + */ +//go:linkname EspDeepSleepTry C.esp_deep_sleep_try +func EspDeepSleepTry(time_in_us c.Uint64T) EspErrT + +/** + * @brief Enter deep-sleep mode + * + * The device will automatically wake up after the deep-sleep time + * Upon waking up, the device calls deep sleep wake stub, and then proceeds + * to load application. + * + * Call to this function is equivalent to a call to esp_deep_sleep_enable_timer_wakeup + * followed by a call to esp_deep_sleep_start. + * + * @note The function does not do a return (no rejection).. Even if wakeup source set before the sleep request + * it goes to deep sleep anyway. + * + * @param time_in_us deep-sleep time, unit: microsecond + */ +//go:linkname EspDeepSleep C.esp_deep_sleep +func EspDeepSleep(time_in_us c.Uint64T) + +/** + * @brief Register a callback to be called from the deep sleep prepare + * + * @warning deepsleep callbacks should without parameters, and MUST NOT, + * UNDER ANY CIRCUMSTANCES, CALL A FUNCTION THAT MIGHT BLOCK. + * + * @param new_dslp_cb Callback to be called + * + * @return + * - ESP_OK: Callback registered to the deepsleep misc_modules_sleep_prepare + * - ESP_ERR_NO_MEM: No more hook space for register the callback + */ +//go:linkname EspDeepSleepRegisterHook C.esp_deep_sleep_register_hook +func EspDeepSleepRegisterHook(new_dslp_cb EspDeepSleepCbT) EspErrT + +/** + * @brief Unregister an deepsleep callback + * + * @param old_dslp_cb Callback to be unregistered + */ +//go:linkname EspDeepSleepDeregisterHook C.esp_deep_sleep_deregister_hook +func EspDeepSleepDeregisterHook(old_dslp_cb EspDeepSleepCbT) + +/** + * @brief Get the wakeup source which caused wakeup from sleep + * + * @return cause of wake up from last sleep (deep sleep or light sleep) + */ +//go:linkname EspSleepGetWakeupCause C.esp_sleep_get_wakeup_cause +func EspSleepGetWakeupCause() EspSleepWakeupCauseT + +/** + * @brief Default stub to run on wake from deep sleep. + * + * Allows for executing code immediately on wake from sleep, before + * the software bootloader or ESP-IDF app has started up. + * + * This function is weak-linked, so you can implement your own version + * to run code immediately when the chip wakes from + * sleep. + * + * See docs/deep-sleep-stub.rst for details. + */ +//go:linkname EspWakeDeepSleep C.esp_wake_deep_sleep +func EspWakeDeepSleep() + +// llgo:type C +type EspDeepSleepWakeStubFnT func() + +/** + * @brief Install a new stub at runtime to run on wake from deep sleep + * + * If implementing esp_wake_deep_sleep() then it is not necessary to + * call this function. + * + * However, it is possible to call this function to substitute a + * different deep sleep stub. Any function used as a deep sleep stub + * must be marked RTC_IRAM_ATTR, and must obey the same rules given + * for esp_wake_deep_sleep(). + */ +//go:linkname EspSetDeepSleepWakeStub C.esp_set_deep_sleep_wake_stub +func EspSetDeepSleepWakeStub(new_stub EspDeepSleepWakeStubFnT) + +/** + * @brief Set wake stub entry to default `esp_wake_stub_entry` + */ +//go:linkname EspSetDeepSleepWakeStubDefaultEntry C.esp_set_deep_sleep_wake_stub_default_entry +func EspSetDeepSleepWakeStubDefaultEntry() + +/** + * @brief Get current wake from deep sleep stub + * @return Return current wake from deep sleep stub, or NULL if + * no stub is installed. + */ +//go:linkname EspGetDeepSleepWakeStub C.esp_get_deep_sleep_wake_stub +func EspGetDeepSleepWakeStub() EspDeepSleepWakeStubFnT + +/** + * @brief The default esp-idf-provided esp_wake_deep_sleep() stub. + * + * See docs/deep-sleep-stub.rst for details. + */ +//go:linkname EspDefaultWakeDeepSleep C.esp_default_wake_deep_sleep +func EspDefaultWakeDeepSleep() + +/** + * @brief Disable logging from the ROM code after deep sleep. + * + * Using LSB of RTC_STORE4. + */ +//go:linkname EspDeepSleepDisableRomLogging C.esp_deep_sleep_disable_rom_logging +func EspDeepSleepDisableRomLogging() + +/** + * @brief CPU Power down low-level initialize, enable CPU power down during light sleep + * @return + * - ESP_OK on success + * - ESP_ERR_NO_MEM not enough retention memory + */ +//go:linkname EspSleepCpuPdLowInit C.esp_sleep_cpu_pd_low_init +func EspSleepCpuPdLowInit() EspErrT + +/** + * @brief CPU Power down low-level deinitialize, disable CPU power down during light sleep + * @return + * - ESP_OK on success + * - ESP_ERR_NO_MEM not enough retention memory + */ +//go:linkname EspSleepCpuPdLowDeinit C.esp_sleep_cpu_pd_low_deinit +func EspSleepCpuPdLowDeinit() EspErrT + +/** + * @brief CPU Power down initialize + * + * @return + * - ESP_OK on success + * - ESP_ERR_NO_MEM not enough retention memory + */ +//go:linkname EspSleepCpuRetentionInit C.esp_sleep_cpu_retention_init +func EspSleepCpuRetentionInit() EspErrT + +/** + * @brief CPU Power down de-initialize + * + * @return + * - ESP_OK on success + * + * Release system retention memory. + */ +//go:linkname EspSleepCpuRetentionDeinit C.esp_sleep_cpu_retention_deinit +func EspSleepCpuRetentionDeinit() EspErrT + +/** + * @brief Configure to isolate all GPIO pins in sleep state + */ +//go:linkname EspSleepConfigGpioIsolate C.esp_sleep_config_gpio_isolate +func EspSleepConfigGpioIsolate() + +/** + * @brief Enable or disable GPIO pins status switching between slept status and waked status. + * @param enable decide whether to switch status or not + */ +//go:linkname EspSleepEnableGpioSwitch C.esp_sleep_enable_gpio_switch +func EspSleepEnableGpioSwitch(enable bool) diff --git a/esp32/esp_sleep_internal.go b/esp32/esp_sleep_internal.go new file mode 100644 index 00000000..23ca55d3 --- /dev/null +++ b/esp32/esp_sleep_internal.go @@ -0,0 +1,101 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EspSleepSubModeT c.Int + +const ( + ESP_SLEEP_RTC_USE_RC_FAST_MODE EspSleepSubModeT = 0 + ESP_SLEEP_DIG_USE_RC_FAST_MODE EspSleepSubModeT = 1 + ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE EspSleepSubModeT = 2 + ESP_SLEEP_ULTRA_LOW_MODE EspSleepSubModeT = 3 + ESP_SLEEP_RTC_FAST_USE_XTAL_MODE EspSleepSubModeT = 4 + ESP_SLEEP_DIG_USE_XTAL_MODE EspSleepSubModeT = 5 + ESP_SLEEP_LP_USE_XTAL_MODE EspSleepSubModeT = 6 + ESP_SLEEP_MODE_MAX EspSleepSubModeT = 7 +) + +/** + * @brief Set sub-sleep power mode in sleep, mode enabled status is maintained by reference count. + * The caller should ensure that the enabling and disabling behavior is symmetric. + * This submode configuration will kept after deep sleep wakeup. + * + * @param mode sub-sleep mode type + * @param activate Activate or deactivate the sleep sub mode + * + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if either of the arguments is out of range + */ +// llgo:link EspSleepSubModeT.EspSleepSubModeConfig C.esp_sleep_sub_mode_config +func (recv_ EspSleepSubModeT) EspSleepSubModeConfig(activate bool) EspErrT { + return 0 +} + +/** + * @brief Force disable sub-sleep power mode in sleep, usually used during initialization. + * + * @param mode sub-sleep mode type + * + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if either of the arguments is out of range + */ +// llgo:link EspSleepSubModeT.EspSleepSubModeForceDisable C.esp_sleep_sub_mode_force_disable +func (recv_ EspSleepSubModeT) EspSleepSubModeForceDisable() EspErrT { + return 0 +} + +/** + * Dump the sub-sleep power mode enable status + * @param stream The stream to dump to, if NULL then nothing will be dumped + * @return return the reference count array pointer + */ +//go:linkname EspSleepSubModeDumpConfig C.esp_sleep_sub_mode_dump_config +func EspSleepSubModeDumpConfig(stream *c.FILE) *c.Int32T + +/** + * @brief Isolate all digital IOs except those that are held during deep sleep + * + * Reduce digital IOs current leakage during deep sleep. + */ +//go:linkname EspSleepIsolateDigitalGpio C.esp_sleep_isolate_digital_gpio +func EspSleepIsolateDigitalGpio() + +/** + * Register a callback to be called from the deep sleep prepare for maintain the PHY state + * CPU is equal to min_freq_mhz (if DFS is enabled) when running this callback, + * and PLL clock is exists) + * + * @warning deepsleep PHY callbacks should without parameters, and MUST NOT, + * UNDER ANY CIRCUMSTANCES, CALL A FUNCTION THAT MIGHT BLOCK. + * + * @param new_dslp_cb Callback to be called to close PHY related modules + * + * @return + * - ESP_OK: PHY callback registered to the phy modules deepsleep prepare + * - ESP_ERR_NO_MEM: No more hook space for register the callback + */ +//go:linkname EspDeepSleepRegisterPhyHook C.esp_deep_sleep_register_phy_hook +func EspDeepSleepRegisterPhyHook(new_dslp_cb EspDeepSleepCbT) EspErrT + +/** + * @brief Unregister an PHY deepsleep callback + * + * @param old_dslp_cb Callback to be unregistered + */ +//go:linkname EspDeepSleepDeregisterPhyHook C.esp_deep_sleep_deregister_phy_hook +func EspDeepSleepDeregisterPhyHook(old_dslp_cb EspDeepSleepCbT) + +/** + * @brief Notify the sleep process that `sleep_time_overhead_out` needs to be remeasured, which must be called + * in the following scenarios: + * 1. When the CPU frequency changes to below the crystal oscillator frequency. + * 2. When a new callback function is registered in the sleep process. + * 3. Other events occur that affect the execution time of the CPU sleep process. + */ +//go:linkname EspSleepOverheadOutTimeRefresh C.esp_sleep_overhead_out_time_refresh +func EspSleepOverheadOutTimeRefresh() diff --git a/esp32/esp_system.go b/esp32/esp_system.go new file mode 100644 index 00000000..a2fa39fa --- /dev/null +++ b/esp32/esp_system.go @@ -0,0 +1,111 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EspResetReasonT c.Int + +const ( + ESP_RST_UNKNOWN EspResetReasonT = 0 + ESP_RST_POWERON EspResetReasonT = 1 + ESP_RST_EXT EspResetReasonT = 2 + ESP_RST_SW EspResetReasonT = 3 + ESP_RST_PANIC EspResetReasonT = 4 + ESP_RST_INT_WDT EspResetReasonT = 5 + ESP_RST_TASK_WDT EspResetReasonT = 6 + ESP_RST_WDT EspResetReasonT = 7 + ESP_RST_DEEPSLEEP EspResetReasonT = 8 + ESP_RST_BROWNOUT EspResetReasonT = 9 + ESP_RST_SDIO EspResetReasonT = 10 + ESP_RST_USB EspResetReasonT = 11 + ESP_RST_JTAG EspResetReasonT = 12 + ESP_RST_EFUSE EspResetReasonT = 13 + ESP_RST_PWR_GLITCH EspResetReasonT = 14 + ESP_RST_CPU_LOCKUP EspResetReasonT = 15 +) + +// llgo:type C +type ShutdownHandlerT func() + +/** + * @brief Register shutdown handler + * + * This function allows you to register a handler that gets invoked before + * the application is restarted using esp_restart function. + * @param handle function to execute on restart + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_STATE if the handler has already been registered + * - ESP_ERR_NO_MEM if no more shutdown handler slots are available + */ +//go:linkname EspRegisterShutdownHandler C.esp_register_shutdown_handler +func EspRegisterShutdownHandler(handle ShutdownHandlerT) EspErrT + +/** + * @brief Unregister shutdown handler + * + * This function allows you to unregister a handler which was previously + * registered using esp_register_shutdown_handler function. + * - ESP_OK on success + * - ESP_ERR_INVALID_STATE if the given handler hasn't been registered before + */ +//go:linkname EspUnregisterShutdownHandler C.esp_unregister_shutdown_handler +func EspUnregisterShutdownHandler(handle ShutdownHandlerT) EspErrT + +/** + * @brief Restart PRO and APP CPUs. + * + * This function can be called both from PRO and APP CPUs. + * After successful restart, CPU reset reason will be SW_CPU_RESET. + * Peripherals (except for Wi-Fi, BT, UART0, SPI1, and legacy timers) are not reset. + * This function does not return. + */ +//go:linkname EspRestart C.esp_restart +func EspRestart() + +/** + * @brief Get reason of last reset + * @return See description of esp_reset_reason_t for explanation of each value. + */ +//go:linkname EspResetReason C.esp_reset_reason +func EspResetReason() EspResetReasonT + +/** + * @brief Get the size of available heap. + * + * @note Note that the returned value may be larger than the maximum contiguous block + * which can be allocated. + * + * @return Available heap size, in bytes. + */ +//go:linkname EspGetFreeHeapSize C.esp_get_free_heap_size +func EspGetFreeHeapSize() c.Uint32T + +/** + * @brief Get the size of available internal heap. + * + * @note Note that the returned value may be larger than the maximum contiguous block + * which can be allocated. + * + * @return Available internal heap size, in bytes. + */ +//go:linkname EspGetFreeInternalHeapSize C.esp_get_free_internal_heap_size +func EspGetFreeInternalHeapSize() c.Uint32T + +/** + * @brief Get the minimum heap that has ever been available + * + * @return Minimum free heap ever available + */ +//go:linkname EspGetMinimumFreeHeapSize C.esp_get_minimum_free_heap_size +func EspGetMinimumFreeHeapSize() c.Uint32T + +/** + * @brief Trigger a software abort + * + * @param details Details that will be displayed during panic handling. + */ +//go:linkname EspSystemAbort C.esp_system_abort +func EspSystemAbort(details *c.Char) diff --git a/esp32/esp_systick_etm.go b/esp32/esp_systick_etm.go new file mode 100644 index 00000000..6cea218a --- /dev/null +++ b/esp32/esp_systick_etm.go @@ -0,0 +1,20 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Get the ETM event handle of systick hardware's alarm/heartbeat event + * + * @note The created ETM event object can be deleted later by calling `esp_etm_del_event` + * + * @param[in] core_id CPU core ID + * @param[out] out_event Returned ETM event handle + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG Parameter error + */ +//go:linkname EspSystickNewEtmAlarmEvent C.esp_systick_new_etm_alarm_event +func EspSystickNewEtmAlarmEvent(core_id c.Int, out_event *EspEtmEventHandleT) EspErrT diff --git a/esp32/esp_task.go b/esp32/esp_task.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/esp_task.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/esp_task_wdt.go b/esp32/esp_task_wdt.go new file mode 100644 index 00000000..97125bcc --- /dev/null +++ b/esp32/esp_task_wdt.go @@ -0,0 +1,244 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Task Watchdog Timer (TWDT) configuration structure + */ + +type EspTaskWdtConfigT struct { + TimeoutMs c.Uint32T + IdleCoreMask c.Uint32T + TriggerPanic bool +} + +type EspTaskWdtUserHandleS struct { + Unused [8]uint8 +} +type EspTaskWdtUserHandleT *EspTaskWdtUserHandleS + +/** + * @brief Initialize the Task Watchdog Timer (TWDT) + * + * This function configures and initializes the TWDT. This function will subscribe the idle tasks if + * configured to do so. For other tasks, users can subscribe them using esp_task_wdt_add() or esp_task_wdt_add_user(). + * This function won't start the timer if no task have been registered yet. + * + * @note esp_task_wdt_init() must only be called after the scheduler is started. Moreover, it must not be called by + * multiple tasks simultaneously. + * @param[in] config Configuration structure + * @return + * - ESP_OK: Initialization was successful + * - ESP_ERR_INVALID_STATE: Already initialized + * - Other: Failed to initialize TWDT + */ +// llgo:link (*EspTaskWdtConfigT).EspTaskWdtInit C.esp_task_wdt_init +func (recv_ *EspTaskWdtConfigT) EspTaskWdtInit() EspErrT { + return 0 +} + +/** + * @brief Reconfigure the Task Watchdog Timer (TWDT) + * + * The function reconfigures the running TWDT. It must already be initialized when this function is called. + * + * @note esp_task_wdt_reconfigure() must not be called by multiple tasks simultaneously. + * + * @param[in] config Configuration structure + * + * @return + * - ESP_OK: Reconfiguring was successful + * - ESP_ERR_INVALID_STATE: TWDT not initialized yet + * - Other: Failed to initialize TWDT + */ +// llgo:link (*EspTaskWdtConfigT).EspTaskWdtReconfigure C.esp_task_wdt_reconfigure +func (recv_ *EspTaskWdtConfigT) EspTaskWdtReconfigure() EspErrT { + return 0 +} + +/** + * @brief Deinitialize the Task Watchdog Timer (TWDT) + * + * This function will deinitialize the TWDT, and unsubscribe any idle tasks. Calling this function whilst other tasks + * are still subscribed to the TWDT, or when the TWDT is already deinitialized, will result in an error code being + * returned. + * + * @note esp_task_wdt_deinit() must not be called by multiple tasks simultaneously. + * @return + * - ESP_OK: TWDT successfully deinitialized + * - Other: Failed to deinitialize TWDT + */ +//go:linkname EspTaskWdtDeinit C.esp_task_wdt_deinit +func EspTaskWdtDeinit() EspErrT + +/** + * @brief Subscribe a task to the Task Watchdog Timer (TWDT) + * + * This function subscribes a task to the TWDT. Each subscribed task must periodically call esp_task_wdt_reset() to + * prevent the TWDT from elapsing its timeout period. Failure to do so will result in a TWDT timeout. + * + * @param task_handle Handle of the task. Input NULL to subscribe the current running task to the TWDT + * @return + * - ESP_OK: Successfully subscribed the task to the TWDT + * - Other: Failed to subscribe task + */ +//go:linkname EspTaskWdtAdd C.esp_task_wdt_add +func EspTaskWdtAdd(task_handle TaskHandleT) EspErrT + +/** + * @brief Subscribe a user to the Task Watchdog Timer (TWDT) + * + * This function subscribes a user to the TWDT. A user of the TWDT is usually a function that needs to run + * periodically. Each subscribed user must periodically call esp_task_wdt_reset_user() to prevent the TWDT from elapsing + * its timeout period. Failure to do so will result in a TWDT timeout. + * + * @param[in] user_name String to identify the user + * @param[out] user_handle_ret Handle of the user + * @return + * - ESP_OK: Successfully subscribed the user to the TWDT + * - Other: Failed to subscribe user + */ +//go:linkname EspTaskWdtAddUser C.esp_task_wdt_add_user +func EspTaskWdtAddUser(user_name *c.Char, user_handle_ret *EspTaskWdtUserHandleT) EspErrT + +/** + * @brief Reset the Task Watchdog Timer (TWDT) on behalf of the currently running task + * + * This function will reset the TWDT on behalf of the currently running task. Each subscribed task must periodically + * call this function to prevent the TWDT from timing out. If one or more subscribed tasks fail to reset the TWDT on + * their own behalf, a TWDT timeout will occur. + * + * @return + * - ESP_OK: Successfully reset the TWDT on behalf of the currently running task + * - Other: Failed to reset + */ +//go:linkname EspTaskWdtReset C.esp_task_wdt_reset +func EspTaskWdtReset() EspErrT + +/** + * @brief Reset the Task Watchdog Timer (TWDT) on behalf of a user + * + * This function will reset the TWDT on behalf of a user. Each subscribed user must periodically call this function to + * prevent the TWDT from timing out. If one or more subscribed users fail to reset the TWDT on their own behalf, a TWDT + * timeout will occur. + * + * @param[in] user_handle User handle + * - ESP_OK: Successfully reset the TWDT on behalf of the user + * - Other: Failed to reset + */ +//go:linkname EspTaskWdtResetUser C.esp_task_wdt_reset_user +func EspTaskWdtResetUser(user_handle EspTaskWdtUserHandleT) EspErrT + +/** + * @brief Unsubscribes a task from the Task Watchdog Timer (TWDT) + * + * This function will unsubscribe a task from the TWDT. After being unsubscribed, the task should no longer call + * esp_task_wdt_reset(). + * + * @param[in] task_handle Handle of the task. Input NULL to unsubscribe the current running task. + * @return + * - ESP_OK: Successfully unsubscribed the task from the TWDT + * - Other: Failed to unsubscribe task + */ +//go:linkname EspTaskWdtDelete C.esp_task_wdt_delete +func EspTaskWdtDelete(task_handle TaskHandleT) EspErrT + +/** + * @brief Unsubscribes a user from the Task Watchdog Timer (TWDT) + * + * This function will unsubscribe a user from the TWDT. After being unsubscribed, the user should no longer call + * esp_task_wdt_reset_user(). + * + * @param[in] user_handle User handle + * @return + * - ESP_OK: Successfully unsubscribed the user from the TWDT + * - Other: Failed to unsubscribe user + */ +//go:linkname EspTaskWdtDeleteUser C.esp_task_wdt_delete_user +func EspTaskWdtDeleteUser(user_handle EspTaskWdtUserHandleT) EspErrT + +/** + * @brief Query whether a task is subscribed to the Task Watchdog Timer (TWDT) + * + * This function will query whether a task is currently subscribed to the TWDT, or whether the TWDT is initialized. + * + * @param[in] task_handle Handle of the task. Input NULL to query the current running task. + * @return: + * - ESP_OK: The task is currently subscribed to the TWDT + * - ESP_ERR_NOT_FOUND: The task is not subscribed + * - ESP_ERR_INVALID_STATE: TWDT was never initialized + */ +//go:linkname EspTaskWdtStatus C.esp_task_wdt_status +func EspTaskWdtStatus(task_handle TaskHandleT) EspErrT + +/** + * @brief User ISR callback placeholder + * + * This function is called by task_wdt_isr function (ISR for when TWDT times out). It can be defined in user code to + * handle TWDT events. + * + * @note It has the same limitations as the interrupt function. Do not use ESP_LOGx functions inside. + */ +//go:linkname EspTaskWdtIsrUserHandler C.esp_task_wdt_isr_user_handler +func EspTaskWdtIsrUserHandler() + +// llgo:type C +type TaskWdtMsgHandler func(c.Pointer, *c.Char) + +/** + * @brief Prints or retrieves information about tasks/users that triggered the Task Watchdog Timeout. + * + * This function provides various operations to handle tasks/users that did not reset the Task Watchdog in time. + * It can print detailed information about these tasks/users, such as their names, associated CPUs, and whether they have been reset. + * Additionally, it can retrieve the total length of the printed information or the CPU affinity of the failing tasks. + * + * @param[in] msg_handler Optional message handler function that will be called for each printed line. + * @param[in] opaque Optional pointer to opaque data that will be passed to the message handler function. + * @param[out] cpus_fail Optional pointer to an integer where the CPU affinity of the failing tasks will be stored. + * + * @return + * - ESP_OK: The function executed successfully. + * - ESP_FAIL: No triggered tasks were found, and thus no information was printed or retrieved. + * + * @note + * - If `msg_handler` is not provided, the information will be printed to console using ESP_EARLY_LOGE. + * - If `msg_handler` is provided, the function will send the printed information to the provided message handler function. + * - If `cpus_fail` is provided, the function will store the CPU affinity of the failing tasks in the provided integer. + * - During the execution of this function, logging is allowed in critical sections, as TWDT timeouts are considered fatal errors. + */ +//go:linkname EspTaskWdtPrintTriggeredTasks C.esp_task_wdt_print_triggered_tasks +func EspTaskWdtPrintTriggeredTasks(msg_handler TaskWdtMsgHandler, opaque c.Pointer, cpus_fail *c.Int) EspErrT + +type TwdtCtxT c.Pointer + +// llgo:type C +type TwdtIsrCallback func(c.Pointer) + +/** + * @brief Stop the Task Watchdog Timer (TWDT) + * + * This function will temporarily stop the timer until it is restarted by a call to esp_task_wdt_restart(). + + * @note esp_task_wdt_stop() must not be called by multiple tasks simultaneously. + * @return + * - ESP_OK: TWDT successfully stopped + * - Other: Failed to stop the TWDT + */ +//go:linkname EspTaskWdtStop C.esp_task_wdt_stop +func EspTaskWdtStop() EspErrT + +/** + * @brief Restart the Task Watchdog Timer (TWDT) + * + * This function will restart the timer after it has been stopped by esp_task_wdt_stop(). + + * @note esp_task_wdt_restart() must not be called by multiple tasks simultaneously. + * @return + * - ESP_OK: TWDT successfully stopped + * - Other: Failed to stop the TWDT + */ +//go:linkname EspTaskWdtRestart C.esp_task_wdt_restart +func EspTaskWdtRestart() EspErrT diff --git a/esp32/esp_task_wdt_impl.go b/esp32/esp_task_wdt_impl.go new file mode 100644 index 00000000..08088773 --- /dev/null +++ b/esp32/esp_task_wdt_impl.go @@ -0,0 +1,85 @@ +package freertos + +import _ "unsafe" + +/** + * @brief Allocate and initialize the Task Watchdog Timer (TWDT) with the given configuration. + * + * @param[in] config Pointer to the configuration structure + * @param[out] obj Abstract context for the current timer, this will be passed to all the other functions + * + * @return + * - ESP_OK: Successfully initialized and configured the timer + * - Other: Failed to initialize the timer + */ +// llgo:link (*EspTaskWdtConfigT).EspTaskWdtImplTimerAllocate C.esp_task_wdt_impl_timer_allocate +func (recv_ *EspTaskWdtConfigT) EspTaskWdtImplTimerAllocate(callback TwdtIsrCallback, obj *TwdtCtxT) EspErrT { + return 0 +} + +/** + * @brief Reconfigure a timer. + * + * The timer must be stopped when calling this function. The timer will not be restarted at the end of this + * function. + * + * @param[in] config Pointer to the configuration structure + * + * @return + * - ESP_OK: Successfully reconfigured the timer + * - Other: Failed to reconfigure the timer + */ +//go:linkname EspTaskWdtImplTimerReconfigure C.esp_task_wdt_impl_timer_reconfigure +func EspTaskWdtImplTimerReconfigure(obj TwdtCtxT, config *EspTaskWdtConfigT) EspErrT + +/** + * @brief Free the Task Watchdog Timer (TWDT). + * + * @param[in] obj Abstract implementation context + * + */ +//go:linkname EspTaskWdtImplTimerFree C.esp_task_wdt_impl_timer_free +func EspTaskWdtImplTimerFree(obj TwdtCtxT) + +/** + * @brief Feed the Task Watchdog Timer (TWDT) + * + * Feed the timer underneath to prevent it from triggering for the next period (configured at initialization). + * + * @param[in] obj Abstract implementation context + * @return + * - ESP_OK: timer successfully feeded + * - Other: failed to feed the timer + */ +//go:linkname EspTaskWdtImplTimerFeed C.esp_task_wdt_impl_timer_feed +func EspTaskWdtImplTimerFeed(obj TwdtCtxT) EspErrT + +/** + * @brief Function invoked as soon as the Task Watchdog Timer (TWDT) ISR callback is called. + * + * @param[in] obj Abstract implementation context + */ +//go:linkname EspTaskWdtImplTimeoutTriggered C.esp_task_wdt_impl_timeout_triggered +func EspTaskWdtImplTimeoutTriggered(obj TwdtCtxT) + +/** + * @brief Stop the Task Watchdog Timer (TWDT). + * + * @param[in] obj Abstract implementation context + * + */ +//go:linkname EspTaskWdtImplTimerStop C.esp_task_wdt_impl_timer_stop +func EspTaskWdtImplTimerStop(obj TwdtCtxT) EspErrT + +/** + * @brief Restart the Task Watchdog Timer (TWDT) + * + * This function will restart/resume the timer after it has been stopped. + * + * @param[in] obj Abstract implementation context + * @return + * - ESP_OK: timer successfully stopped + * - Other: failed to stop the timer + */ +//go:linkname EspTaskWdtImplTimerRestart C.esp_task_wdt_impl_timer_restart +func EspTaskWdtImplTimerRestart(obj TwdtCtxT) EspErrT diff --git a/esp32/esp_types.go b/esp32/esp_types.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/esp_types.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/esp_wake_stub.go b/esp32/esp_wake_stub.go new file mode 100644 index 00000000..2debfcb1 --- /dev/null +++ b/esp32/esp_wake_stub.go @@ -0,0 +1,47 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Enter deep-sleep mode from deep sleep wake stub code + * + * This should be called from the wake stub code. + * + * @param new_stub new wake stub function will be set + */ +//go:linkname EspWakeStubSleep C.esp_wake_stub_sleep +func EspWakeStubSleep(new_stub EspDeepSleepWakeStubFnT) + +/** + * @brief Wait while uart transmission is in progress + * + * This function is waiting while uart transmission is not completed, + * and this function should be called from the wake stub code. + * + * @param uart_no UART port to wait idle + */ +//go:linkname EspWakeStubUartTxWaitIdle C.esp_wake_stub_uart_tx_wait_idle +func EspWakeStubUartTxWaitIdle(uart_no c.Uint8T) + +/** + * @brief Set wakeup time from deep sleep stub. + * + * This should be called from the wake stub code. + * + * @param time_in_us wakeup time in us + */ +//go:linkname EspWakeStubSetWakeupTime C.esp_wake_stub_set_wakeup_time +func EspWakeStubSetWakeupTime(time_in_us c.Uint64T) + +/** + * @brief Get wakeup cause from deep sleep stub. + * + * This should be called from the wake stub code. + * + * @return wakeup casue value + */ +//go:linkname EspWakeStubGetWakeupCause C.esp_wake_stub_get_wakeup_cause +func EspWakeStubGetWakeupCause() c.Uint32T diff --git a/esp32/esp_xt_wdt.go b/esp32/esp_xt_wdt.go new file mode 100644 index 00000000..5ac95997 --- /dev/null +++ b/esp32/esp_xt_wdt.go @@ -0,0 +1,55 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief esp_xt_wdt configuration struct + * + */ + +type EspXtWdtConfigT struct { + Timeout c.Uint8T + AutoBackupClkEnable bool +} + +// llgo:type C +type EspXtCallbackT func(c.Pointer) + +/** + * @brief Initializes the xtal32k watchdog timer + * + * @param cfg Pointer to configuration struct + * @return esp_err_t + * - ESP_OK: XTWDT was successfully enabled + * - ESP_ERR_NO_MEM: Failed to allocate ISR + */ +// llgo:link (*EspXtWdtConfigT).EspXtWdtInit C.esp_xt_wdt_init +func (recv_ *EspXtWdtConfigT) EspXtWdtInit() EspErrT { + return 0 +} + +/** + * @brief Register a callback function that will be called when the watchdog + * times out. + * + * @note This function will be called from an interrupt context where the cache might be disabled. + * Thus the function should be placed in IRAM and must not perform any blocking operations. + * + * Only one callback function can be registered, any call to esp_xt_wdt_register_callback + * will override the previous callback function. + * + * @param func The callback function to register + * @param arg Pointer to argument that will be passed to the callback function + */ +//go:linkname EspXtWdtRegisterCallback C.esp_xt_wdt_register_callback +func EspXtWdtRegisterCallback(func_ EspXtCallbackT, arg c.Pointer) + +/** + * @brief Restores the xtal32k clock and re-enables the WDT + * + */ +//go:linkname EspXtWdtRestoreClk C.esp_xt_wdt_restore_clk +func EspXtWdtRestoreClk() diff --git a/esp32/eth_types.go b/esp32/eth_types.go new file mode 100644 index 00000000..c7635e92 --- /dev/null +++ b/esp32/eth_types.go @@ -0,0 +1,53 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EthDataInterfaceT c.Int + +const ( + EMAC_DATA_INTERFACE_RMII EthDataInterfaceT = 0 + EMAC_DATA_INTERFACE_MII EthDataInterfaceT = 1 +) + +type EthLinkT c.Int + +const ( + ETH_LINK_UP EthLinkT = 0 + ETH_LINK_DOWN EthLinkT = 1 +) + +type EthSpeedT c.Int + +const ( + ETH_SPEED_10M EthSpeedT = 0 + ETH_SPEED_100M EthSpeedT = 1 + ETH_SPEED_MAX EthSpeedT = 2 +) + +type EthDuplexT c.Int + +const ( + ETH_DUPLEX_HALF EthDuplexT = 0 + ETH_DUPLEX_FULL EthDuplexT = 1 +) + +type EthChecksumT c.Int + +const ( + ETH_CHECKSUM_SW EthChecksumT = 0 + ETH_CHECKSUM_HW EthChecksumT = 1 +) + +type EthMacDmaBurstLenT c.Int + +const ( + ETH_DMA_BURST_LEN_32 EthMacDmaBurstLenT = 0 + ETH_DMA_BURST_LEN_16 EthMacDmaBurstLenT = 1 + ETH_DMA_BURST_LEN_8 EthMacDmaBurstLenT = 2 + ETH_DMA_BURST_LEN_4 EthMacDmaBurstLenT = 3 + ETH_DMA_BURST_LEN_2 EthMacDmaBurstLenT = 4 + ETH_DMA_BURST_LEN_1 EthMacDmaBurstLenT = 5 +) diff --git a/esp32/etm_hal.go b/esp32/etm_hal.go new file mode 100644 index 00000000..87adc696 --- /dev/null +++ b/esp32/etm_hal.go @@ -0,0 +1,34 @@ +package freertos + +import _ "unsafe" + +type SocEtmDevT struct { + Unused [8]uint8 +} +type EtmSocHandleT *SocEtmDevT + +/** + * @brief HAL context type of ETM driver + */ + +type EtmHalContextT struct { + Regs EtmSocHandleT +} + +/** + * @brief Initialize the ETM HAL driver + * + * @param hal: ETM HAL context + */ +// llgo:link (*EtmHalContextT).EtmHalInit C.etm_hal_init +func (recv_ *EtmHalContextT) EtmHalInit() { +} + +/** + * @brief Deinitialize the ETM HAL driver + * + * @param hal: ETM HAL context + */ +// llgo:link (*EtmHalContextT).EtmHalDeinit C.etm_hal_deinit +func (recv_ *EtmHalContextT) EtmHalDeinit() { +} diff --git a/esp32/etm_interface.go b/esp32/etm_interface.go new file mode 100644 index 00000000..967c8dd3 --- /dev/null +++ b/esp32/etm_interface.go @@ -0,0 +1,20 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EtmTriggerPeripheralT c.Int + +const ( + ETM_TRIG_PERIPH_GPIO EtmTriggerPeripheralT = 0 + ETM_TRIG_PERIPH_GDMA EtmTriggerPeripheralT = 1 + ETM_TRIG_PERIPH_GPTIMER EtmTriggerPeripheralT = 2 + ETM_TRIG_PERIPH_SYSTIMER EtmTriggerPeripheralT = 3 + ETM_TRIG_PERIPH_MCPWM EtmTriggerPeripheralT = 4 + ETM_TRIG_PERIPH_ANA_CMPR EtmTriggerPeripheralT = 5 + ETM_TRIG_PERIPH_TSENS EtmTriggerPeripheralT = 6 + ETM_TRIG_PERIPH_I2S EtmTriggerPeripheralT = 7 + ETM_TRIG_PERIPH_LP_CORE EtmTriggerPeripheralT = 8 +) diff --git a/esp32/ets_sys.go b/esp32/ets_sys.go new file mode 100644 index 00000000..fecec9b5 --- /dev/null +++ b/esp32/ets_sys.go @@ -0,0 +1,396 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type ETSSTATUS c.Int + +const ( + ETS_OK ETSSTATUS = 0 + ETS_FAILED ETSSTATUS = 1 + ETS_PENDING ETSSTATUS = 2 + ETS_BUSY ETSSTATUS = 3 + ETS_CANCEL ETSSTATUS = 4 +) + +type EtsStatusT ETSSTATUS +type ETSSignal c.Uint32T +type ETSParam c.Uint32T + +type ETSEventTag struct { + Sig ETSSignal + Par ETSParam +} +type ETSEvent ETSEventTag + +// llgo:type C +type ETSTask func(*ETSEvent) + +// llgo:type C +type EtsIdleCbT func(c.Pointer) + +/** + * @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed. + * When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the PRO Entry code address value in uint32_t + * + * @return None + */ +//go:linkname EtsSetUserStart C.ets_set_user_start +func EtsSetUserStart(start c.Uint32T) + +/** + * @brief Set App cpu Entry code, code can be called in PRO CPU. + * When APP booting is completed, APP CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D. + * + * @return None + */ +//go:linkname EtsSetAppcpuBootAddr C.ets_set_appcpu_boot_addr +func EtsSetAppcpuBootAddr(start c.Uint32T) + +/** + * @brief Printf the strings to uart or other devices, similar with printf, simple than printf. + * Can not print float point data format, or longlong data format. + * So we maybe only use this in ROM. + * + * @param const char *fmt : See printf. + * + * @param ... : See printf. + * + * @return int : the length printed to the output device. + */ +//go:linkname EtsPrintf C.ets_printf +func EtsPrintf(fmt *c.Char, __llgo_va_list ...interface{}) c.Int + +/** + * @brief Get the uart channel of ets_printf(uart_tx_one_char). + * + * @return uint8_t uart channel used by ets_printf(uart_tx_one_char). + */ +//go:linkname EtsGetPrintfChannel C.ets_get_printf_channel +func EtsGetPrintfChannel() c.Uint8T + +/** + * @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function. + * Can not print float point data format, or longlong data format + * + * @param char c : char to output. + * + * @return None + */ +//go:linkname EtsWriteCharUart C.ets_write_char_uart +func EtsWriteCharUart(c c.Char) + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need output. + * To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +//go:linkname EtsInstallPutc1 C.ets_install_putc1 +func EtsInstallPutc1(p func(c.Char)) + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need output. + * To install putc2, which is defaulted installed as NULL. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +//go:linkname EtsInstallPutc2 C.ets_install_putc2 +func EtsInstallPutc2(p func(c.Char)) + +/** + * @brief Install putc1 as ets_write_char_uart. + * In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok. + * + * @param None + * + * @return None + */ +//go:linkname EtsInstallUartPrintf C.ets_install_uart_printf +func EtsInstallUartPrintf() + +// llgo:type C +type ETSTimerFunc func(c.Pointer) + +type X_ETSTIMER_ struct { + TimerNext *X_ETSTIMER_ + TimerExpire c.Uint32T + TimerPeriod c.Uint32T + TimerFunc *ETSTimerFunc + TimerArg c.Pointer +} +type ETSTimer X_ETSTIMER_ + +/** + * @brief Init ets timer, this timer range is 640 us to 429496 ms + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +//go:linkname EtsTimerInit C.ets_timer_init +func EtsTimerInit() + +/** + * @brief In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +//go:linkname EtsTimerDeinit C.ets_timer_deinit +func EtsTimerDeinit() + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in ms, range is 1 to 429496. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +// llgo:link (*ETSTimer).EtsTimerArm C.ets_timer_arm +func (recv_ *ETSTimer) EtsTimerArm(tmout c.Uint32T, repeat bool) { +} + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in us, range is 1 to 429496729. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +// llgo:link (*ETSTimer).EtsTimerArmUs C.ets_timer_arm_us +func (recv_ *ETSTimer) EtsTimerArmUs(us c.Uint32T, repeat bool) { +} + +/** + * @brief Disarm an ets timer. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +// llgo:link (*ETSTimer).EtsTimerDisarm C.ets_timer_disarm +func (recv_ *ETSTimer) EtsTimerDisarm() { +} + +/** + * @brief Set timer callback and argument. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param ETSTimerFunc *pfunction : Timer callback. + * + * @param void *parg : Timer callback argument. + * + * @return None + */ +// llgo:link (*ETSTimer).EtsTimerSetfn C.ets_timer_setfn +func (recv_ *ETSTimer) EtsTimerSetfn(pfunction ETSTimerFunc, parg c.Pointer) { +} + +/** + * @brief Unset timer callback and argument to NULL. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +// llgo:link (*ETSTimer).EtsTimerDone C.ets_timer_done +func (recv_ *ETSTimer) EtsTimerDone() { +} + +/** + * @brief CPU do while loop for some time. + * In FreeRTOS task, please call FreeRTOS apis. + * + * @param uint32_t us : Delay time in us. + * + * @return None + */ +//go:linkname EtsDelayUs C.ets_delay_us +func EtsDelayUs(us c.Uint32T) + +/** + * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. + * Call this function when CPU frequency is changed. + * + * @param uint32_t ticks_per_us : CPU ticks per us. + * + * @return None + */ +//go:linkname EtsUpdateCpuFrequency C.ets_update_cpu_frequency +func EtsUpdateCpuFrequency(ticks_per_us c.Uint32T) + +/** + * @brief Get the real CPU ticks per us to the ets. + * This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency. + * + * @param None + * + * @return uint32_t : CPU ticks per us record in ets. + */ +//go:linkname EtsGetCpuFrequency C.ets_get_cpu_frequency +func EtsGetCpuFrequency() c.Uint32T + +/** + * @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store. + * + * @param None + * + * @return uint32_t : if stored in efuse(not 0) + * clock = ets_efuse_get_xtal_freq() * 1000000; + * else if analog_8M in efuse + * clock = ets_get_xtal_scale() * 625 / 16 * ets_efuse_get_8M_clock(); + * else clock = 40M. + */ +//go:linkname EtsGetXtalFreq C.ets_get_xtal_freq +func EtsGetXtalFreq() c.Uint32T + +/** + * @brief Get the apb divisor. The xtal frequency gets divided + * by this value to generate the APB clock. + * When any types of reset happens, the default value is 2. + * + * @param None + * + * @return uint32_t : 1 or 2. + */ +//go:linkname EtsGetXtalDiv C.ets_get_xtal_div +func EtsGetXtalDiv() c.Uint32T + +/** + * @brief Modifies the apb divisor. The xtal frequency gets divided by this to + * generate the APB clock. + * + * @note The xtal frequency divisor is 2 by default as the glitch detector + * doesn't properly stop glitches when it is 1. Please do not set the + * divisor to 1 before the PLL is active without being aware that you + * may be introducing a security risk. + * + * @param div Divisor. 1 = xtal freq, 2 = 1/2th xtal freq. + */ +//go:linkname EtsSetXtalDiv C.ets_set_xtal_div +func EtsSetXtalDiv(div c.Int) + +/** + * @brief Get apb_freq value, If value not stored in RTC_STORE5, than store. + * + * @param None + * + * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register. + * clock = (REG_READ(RTC_STORE5) & 0xffff) << 12; + * else store ets_get_detected_xtal_freq() in. + */ +//go:linkname EtsGetApbFreq C.ets_get_apb_freq +func EtsGetApbFreq() c.Uint32T + +// llgo:type C +type EtsIsrT func(c.Pointer) + +/** + * @brief Attach a interrupt handler to a CPU interrupt number. + * This function equals to _xtos_set_interrupt_handler_arg(i, func, arg). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param int i : CPU interrupt number. + * + * @param ets_isr_t func : Interrupt handler. + * + * @param void *arg : argument of the handler. + * + * @return None + */ +//go:linkname EtsIsrAttach C.ets_isr_attach +func EtsIsrAttach(i c.Int, func_ EtsIsrT, arg c.Pointer) + +/** + * @brief Mask the interrupts which show in mask bits. + * This function equals to _xtos_ints_off(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +//go:linkname EtsIsrMask C.ets_isr_mask +func EtsIsrMask(mask c.Uint32T) + +/** + * @brief Unmask the interrupts which show in mask bits. + * This function equals to _xtos_ints_on(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +//go:linkname EtsIsrUnmask C.ets_isr_unmask +func EtsIsrUnmask(unmask c.Uint32T) + +/** + * @brief Lock the interrupt to level 2. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +//go:linkname EtsIntrLock C.ets_intr_lock +func EtsIntrLock() + +/** + * @brief Unlock the interrupt to level 0. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +//go:linkname EtsIntrUnlock C.ets_intr_unlock +func EtsIntrUnlock() + +/** + * @brief Attach an CPU interrupt to a hardware source. + * We have 4 steps to use an interrupt: + * 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM); + * 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL); + * 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM); + * 4.Enable interrupt in the module. + * + * @param int cpu_no : The CPU which the interrupt number belongs. + * + * @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table. + * + * @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table. + * + * @return None + */ +//go:linkname IntrMatrixSet C.intr_matrix_set +func IntrMatrixSet(cpu_no c.Int, model_num c.Uint32T, intr_num c.Uint32T) diff --git a/esp32/event_groups.go b/esp32/event_groups.go new file mode 100644 index 00000000..ab132e51 --- /dev/null +++ b/esp32/event_groups.go @@ -0,0 +1,496 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * + * Type by which event groups are referenced. For example, a call to + * xEventGroupCreate() returns an EventGroupHandle_t variable that can then + * be used as a parameter to other event group functions. + * + * \ingroup EventGroup + */ + +type EventGroupDefT struct { + Unused [8]uint8 +} +type EventGroupHandleT *EventGroupDefT +type EventBitsT TickTypeT + +/** + * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGroupCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see https://www.FreeRTOS.org/a00111.html). If an event group is created + * using xEventGroupCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @return If the event group was created then a handle to the event group is + * returned. If there was insufficient FreeRTOS heap available to create the + * event group then NULL is returned. See https://www.FreeRTOS.org/a00111.html + * + * Example usage: + * @code{c} + * // Declare a variable to hold the created event group. + * EventGroupHandle_t xCreatedEventGroup; + * + * // Attempt to create the event group. + * xCreatedEventGroup = xEventGroupCreate(); + * + * // Was the event group created successfully? + * if( xCreatedEventGroup == NULL ) + * { + * // The event group was not created because there was insufficient + * // FreeRTOS heap available. + * } + * else + * { + * // The event group was created. + * } + * @endcode + * \ingroup EventGroup + */ +//go:linkname XEventGroupCreate C.xEventGroupCreate +func XEventGroupCreate() EventGroupHandleT + +/** + * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGroupCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see https://www.FreeRTOS.org/a00111.html). If an event group is created + * using xEventGroupCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type + * StaticEventGroup_t, which will be then be used to hold the event group's data + * structures, removing the need for the memory to be allocated dynamically. + * + * @return If the event group was created then a handle to the event group is + * returned. If pxEventGroupBuffer was NULL then NULL is returned. + * + * Example usage: + * @code{c} + * // StaticEventGroup_t is a publicly accessible structure that has the same + * // size and alignment requirements as the real event group structure. It is + * // provided as a mechanism for applications to know the size of the event + * // group (which is dependent on the architecture and configuration file + * // settings) without breaking the strict data hiding policy by exposing the + * // real event group internals. This StaticEventGroup_t variable is passed + * // into the xSemaphoreCreateEventGroupStatic() function and is used to store + * // the event group's data structures + * StaticEventGroup_t xEventGroupBuffer; + * + * // Create the event group without dynamically allocating any memory. + * xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer ); + * @endcode + */ +// llgo:link (*StaticEventGroupT).XEventGroupCreateStatic C.xEventGroupCreateStatic +func (recv_ *StaticEventGroupT) XEventGroupCreateStatic() EventGroupHandleT { + return nil +} + +/** + * + * [Potentially] block to wait for one or more bits to be set within a + * previously created event group. + * + * This function cannot be called from an interrupt. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and/or bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within + * uxBitsToWaitFor that are set within the event group will be cleared before + * xEventGroupWaitBits() returns if the wait condition was met (if the function + * returns for a reason other than a timeout). If xClearOnExit is set to + * pdFALSE then the bits set in the event group are not altered when the call to + * xEventGroupWaitBits() returns. + * + * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then + * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor + * are set or the specified block time expires. If xWaitForAllBits is set to + * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set + * in uxBitsToWaitFor is set or the specified block time expires. The block + * time is specified by the xTicksToWait parameter. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for one/all (depending on the xWaitForAllBits value) of the bits specified by + * uxBitsToWaitFor to become set. A value of portMAX_DELAY can be used to block + * indefinitely (provided INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h). + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupWaitBits() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupWaitBits() returned because the bits it was waiting for were set + * then the returned value is the event group value before any bits were + * automatically cleared in the case that xClearOnExit parameter was set to + * pdTRUE. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * void aFunction( EventGroupHandle_t xEventGroup ) + * { + * EventBits_t uxBits; + * const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS; + * + * // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within + * // the event group. Clear the bits before exiting. + * uxBits = xEventGroupWaitBits( + * xEventGroup, // The event group being tested. + * BIT_0 | BIT_4, // The bits within the event group to wait for. + * pdTRUE, // BIT_0 and BIT_4 should be cleared before returning. + * pdFALSE, // Don't wait for both bits, either bit will do. + * xTicksToWait ); // Wait a maximum of 100ms for either bit to be set. + * + * if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) ) + * { + * // xEventGroupWaitBits() returned because both bits were set. + * } + * else if( ( uxBits & BIT_0 ) != 0 ) + * { + * // xEventGroupWaitBits() returned because just BIT_0 was set. + * } + * else if( ( uxBits & BIT_4 ) != 0 ) + * { + * // xEventGroupWaitBits() returned because just BIT_4 was set. + * } + * else + * { + * // xEventGroupWaitBits() returned because xTicksToWait ticks passed + * // without either BIT_0 or BIT_4 becoming set. + * } + * } + * @endcode + * \ingroup EventGroup + */ +//go:linkname XEventGroupWaitBits C.xEventGroupWaitBits +func XEventGroupWaitBits(xEventGroup EventGroupHandleT, uxBitsToWaitFor EventBitsT, xClearOnExit BaseTypeT, xWaitForAllBits BaseTypeT, xTicksToWait TickTypeT) EventBitsT + +/** + * + * Clear bits within an event group. This function cannot be called from an + * interrupt. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear + * in the event group. For example, to clear bit 3 only, set uxBitsToClear to + * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. + * + * @return The value of the event group before the specified bits were cleared. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * void aFunction( EventGroupHandle_t xEventGroup ) + * { + * EventBits_t uxBits; + * + * // Clear bit 0 and bit 4 in xEventGroup. + * uxBits = xEventGroupClearBits( + * xEventGroup, // The event group being updated. + * BIT_0 | BIT_4 );// The bits being cleared. + * + * if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) ) + * { + * // Both bit 0 and bit 4 were set before xEventGroupClearBits() was + * // called. Both will now be clear (not set). + * } + * else if( ( uxBits & BIT_0 ) != 0 ) + * { + * // Bit 0 was set before xEventGroupClearBits() was called. It will + * // now be clear. + * } + * else if( ( uxBits & BIT_4 ) != 0 ) + * { + * // Bit 4 was set before xEventGroupClearBits() was called. It will + * // now be clear. + * } + * else + * { + * // Neither bit 0 nor bit 4 were set in the first place. + * } + * } + * @endcode + * \ingroup EventGroup + */ +//go:linkname XEventGroupClearBits C.xEventGroupClearBits +func XEventGroupClearBits(xEventGroup EventGroupHandleT, uxBitsToClear EventBitsT) EventBitsT + +/** + * + * Set bits within an event group. + * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() + * is a version that can be called from an interrupt. + * + * Setting bits in an event group will automatically unblock tasks that are + * blocked waiting for the bits. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @return The value of the event group at the time the call to + * xEventGroupSetBits() returns. There are two reasons why the returned value + * might have the bits specified by the uxBitsToSet parameter cleared. First, + * if setting a bit results in a task that was waiting for the bit leaving the + * blocked state then it is possible the bit will be cleared automatically + * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any + * unblocked (or otherwise Ready state) task that has a priority above that of + * the task that called xEventGroupSetBits() will execute and may change the + * event group value before the call to xEventGroupSetBits() returns. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * void aFunction( EventGroupHandle_t xEventGroup ) + * { + * EventBits_t uxBits; + * + * // Set bit 0 and bit 4 in xEventGroup. + * uxBits = xEventGroupSetBits( + * xEventGroup, // The event group being updated. + * BIT_0 | BIT_4 );// The bits being set. + * + * if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) ) + * { + * // Both bit 0 and bit 4 remained set when the function returned. + * } + * else if( ( uxBits & BIT_0 ) != 0 ) + * { + * // Bit 0 remained set when the function returned, but bit 4 was + * // cleared. It might be that bit 4 was cleared automatically as a + * // task that was waiting for bit 4 was removed from the Blocked + * // state. + * } + * else if( ( uxBits & BIT_4 ) != 0 ) + * { + * // Bit 4 remained set when the function returned, but bit 0 was + * // cleared. It might be that bit 0 was cleared automatically as a + * // task that was waiting for bit 0 was removed from the Blocked + * // state. + * } + * else + * { + * // Neither bit 0 nor bit 4 remained set. It might be that a task + * // was waiting for both of the bits to be set, and the bits were + * // cleared as the task left the Blocked state. + * } + * } + * @endcode + * \ingroup EventGroup + */ +//go:linkname XEventGroupSetBits C.xEventGroupSetBits +func XEventGroupSetBits(xEventGroup EventGroupHandleT, uxBitsToSet EventBitsT) EventBitsT + +/** + * + * Atomically set bits within an event group, then wait for a combination of + * bits to be set within the same event group. This functionality is typically + * used to synchronise multiple tasks, where each task has to wait for the other + * tasks to reach a synchronisation point before proceeding. + * + * This function cannot be used from an interrupt. + * + * The function will return before its block time expires if the bits specified + * by the uxBitsToWait parameter are set, or become set within that time. In + * this case all the bits specified by uxBitsToWait will be automatically + * cleared before the function returns. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToSet The bits to set in the event group before determining + * if, and possibly waiting for, all the bits specified by the uxBitsToWait + * parameter are set. + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for all of the bits specified by uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupSync() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupSync() returned because all the bits it was waiting for were + * set then the returned value is the event group value before any bits were + * automatically cleared. + * + * Example usage: + * @code{c} + * // Bits used by the three tasks. + * #define TASK_0_BIT ( 1 << 0 ) + * #define TASK_1_BIT ( 1 << 1 ) + * #define TASK_2_BIT ( 1 << 2 ) + * + * #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT ) + * + * // Use an event group to synchronise three tasks. It is assumed this event + * // group has already been created elsewhere. + * EventGroupHandle_t xEventBits; + * + * void vTask0( void *pvParameters ) + * { + * EventBits_t uxReturn; + * TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS; + * + * for( ;; ) + * { + * // Perform task functionality here. + * + * // Set bit 0 in the event flag to note this task has reached the + * // sync point. The other two tasks will set the other two bits defined + * // by ALL_SYNC_BITS. All three tasks have reached the synchronisation + * // point when all the ALL_SYNC_BITS are set. Wait a maximum of 100ms + * // for this to happen. + * uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait ); + * + * if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS ) + * { + * // All three tasks reached the synchronisation point before the call + * // to xEventGroupSync() timed out. + * } + * } + * } + * + * void vTask1( void *pvParameters ) + * { + * for( ;; ) + * { + * // Perform task functionality here. + * + * // Set bit 1 in the event flag to note this task has reached the + * // synchronisation point. The other two tasks will set the other two + * // bits defined by ALL_SYNC_BITS. All three tasks have reached the + * // synchronisation point when all the ALL_SYNC_BITS are set. Wait + * // indefinitely for this to happen. + * xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY ); + * + * // xEventGroupSync() was called with an indefinite block time, so + * // this task will only reach here if the synchronisation was made by all + * // three tasks, so there is no need to test the return value. + * } + * } + * + * void vTask2( void *pvParameters ) + * { + * for( ;; ) + * { + * // Perform task functionality here. + * + * // Set bit 2 in the event flag to note this task has reached the + * // synchronisation point. The other two tasks will set the other two + * // bits defined by ALL_SYNC_BITS. All three tasks have reached the + * // synchronisation point when all the ALL_SYNC_BITS are set. Wait + * // indefinitely for this to happen. + * xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY ); + * + * // xEventGroupSync() was called with an indefinite block time, so + * // this task will only reach here if the synchronisation was made by all + * // three tasks, so there is no need to test the return value. + * } + * } + * + * @endcode + * \ingroup EventGroup + */ +//go:linkname XEventGroupSync C.xEventGroupSync +func XEventGroupSync(xEventGroup EventGroupHandleT, uxBitsToSet EventBitsT, uxBitsToWaitFor EventBitsT, xTicksToWait TickTypeT) EventBitsT + +/** + * + * A version of xEventGroupGetBits() that can be called from an ISR. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. + * + * \ingroup EventGroup + */ +//go:linkname XEventGroupGetBitsFromISR C.xEventGroupGetBitsFromISR +func XEventGroupGetBitsFromISR(xEventGroup EventGroupHandleT) EventBitsT + +/** + * + * Delete an event group that was previously created by a call to + * xEventGroupCreate(). Tasks that are blocked on the event group will be + * unblocked and obtain 0 as the event group's value. + * + * @param xEventGroup The event group being deleted. + */ +//go:linkname VEventGroupDelete C.vEventGroupDelete +func VEventGroupDelete(xEventGroup EventGroupHandleT) + +/** + * + * Retrieve a pointer to a statically created event groups's data structure + * buffer. It is the same buffer that is supplied at the time of creation. + * + * @param xEventGroup The event group for which to retrieve the buffer. + * + * @param ppxEventGroupBuffer Used to return a pointer to the event groups's + * data structure buffer. + * + * @return pdTRUE if the buffer was retrieved, pdFALSE otherwise. + */ +//go:linkname XEventGroupGetStaticBuffer C.xEventGroupGetStaticBuffer +func XEventGroupGetStaticBuffer(xEventGroup EventGroupHandleT, ppxEventGroupBuffer **StaticEventGroupT) BaseTypeT + +/* For internal use only. */ +//go:linkname VEventGroupSetBitsCallback C.vEventGroupSetBitsCallback +func VEventGroupSetBitsCallback(pvEventGroup c.Pointer, ulBitsToSet c.Uint32T) + +//go:linkname VEventGroupClearBitsCallback C.vEventGroupClearBitsCallback +func VEventGroupClearBitsCallback(pvEventGroup c.Pointer, ulBitsToClear c.Uint32T) diff --git a/esp32/ext_mem_defs.go b/esp32/ext_mem_defs.go new file mode 100644 index 00000000..9fe6a571 --- /dev/null +++ b/esp32/ext_mem_defs.go @@ -0,0 +1,31 @@ +package freertos + +import _ "unsafe" + +const SOC_IRAM0_ADDRESS_LOW = 0x40370000 +const SOC_IRAM0_ADDRESS_HIGH = 0x403E0000 +const SOC_IRAM0_CACHE_ADDRESS_LOW = 0x42000000 +const SOC_IRAM0_CACHE_ADDRESS_HIGH = 0x44000000 +const SOC_DRAM0_ADDRESS_LOW = 0x3FC88000 +const SOC_DRAM0_ADDRESS_HIGH = 0x3FD00000 +const SOC_DRAM0_CACHE_ADDRESS_LOW = 0x3C000000 +const SOC_DRAM0_CACHE_ADDRESS_HIGH = 0x3E000000 +const SOC_MMU_VALID = 0 +const SOC_MMU_ACCESS_FLASH = 0 +const SOC_MMU_VALID_VAL_MASK = 0x3fff +const SOC_MMU_MAX_PADDR_PAGE_NUM = 16384 +const SOC_MMU_VADDR_MASK = 0x1FFFFFF +const SOC_MMU_ENTRY_NUM = 512 +const SOC_MMU_DBUS_VADDR_BASE = 0x3C000000 +const SOC_MMU_IBUS_VADDR_BASE = 0x42000000 +const SOC_MMU_LINEAR_ADDR_MASK = 0x1FFFFFF +const CACHE_IBUS = 0 +const CACHE_IBUS_MMU_START = 0 +const CACHE_IBUS_MMU_END = 0x800 +const CACHE_DBUS = 1 +const CACHE_DBUS_MMU_START = 0 +const CACHE_DBUS_MMU_END = 0x800 +const CACHE_IROM_MMU_START = 0 +const CACHE_DROM_MMU_MAX_END = 0x400 +const ICACHE_MMU_SIZE = 0x800 +const DCACHE_MMU_SIZE = 0x800 diff --git a/esp32/extmem_reg.go b/esp32/extmem_reg.go new file mode 100644 index 00000000..a8adb0a7 --- /dev/null +++ b/esp32/extmem_reg.go @@ -0,0 +1,514 @@ +package freertos + +import _ "unsafe" + +const EXTMEM_DCACHE_BLOCKSIZE_MODE = 0x00000003 +const EXTMEM_DCACHE_BLOCKSIZE_MODE_V = 0x3 +const EXTMEM_DCACHE_BLOCKSIZE_MODE_S = 3 +const EXTMEM_DCACHE_SIZE_MODE_V = 0x1 +const EXTMEM_DCACHE_SIZE_MODE_S = 2 +const EXTMEM_DCACHE_ENABLE_V = 0x1 +const EXTMEM_DCACHE_ENABLE_S = 0 +const EXTMEM_DCACHE_SHUT_CORE1_BUS_V = 0x1 +const EXTMEM_DCACHE_SHUT_CORE1_BUS_S = 1 +const EXTMEM_DCACHE_SHUT_CORE0_BUS_V = 0x1 +const EXTMEM_DCACHE_SHUT_CORE0_BUS_S = 0 +const EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V = 0x1 +const EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S = 2 +const EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V = 0x1 +const EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S = 1 +const EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V = 0x1 +const EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S = 0 +const EXTMEM_DCACHE_PRELOCK_SCT1_EN_V = 0x1 +const EXTMEM_DCACHE_PRELOCK_SCT1_EN_S = 1 +const EXTMEM_DCACHE_PRELOCK_SCT0_EN_V = 0x1 +const EXTMEM_DCACHE_PRELOCK_SCT0_EN_S = 0 +const EXTMEM_DCACHE_PRELOCK_SCT0_ADDR = 0xFFFFFFFF +const EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V = 0xFFFFFFFF +const EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S = 0 +const EXTMEM_DCACHE_PRELOCK_SCT1_ADDR = 0xFFFFFFFF +const EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V = 0xFFFFFFFF +const EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S = 0 +const EXTMEM_DCACHE_PRELOCK_SCT0_SIZE = 0x0000FFFF +const EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V = 0xFFFF +const EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S = 16 +const EXTMEM_DCACHE_PRELOCK_SCT1_SIZE = 0x0000FFFF +const EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V = 0xFFFF +const EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S = 0 +const EXTMEM_DCACHE_LOCK_DONE_V = 0x1 +const EXTMEM_DCACHE_LOCK_DONE_S = 2 +const EXTMEM_DCACHE_UNLOCK_ENA_V = 0x1 +const EXTMEM_DCACHE_UNLOCK_ENA_S = 1 +const EXTMEM_DCACHE_LOCK_ENA_V = 0x1 +const EXTMEM_DCACHE_LOCK_ENA_S = 0 +const EXTMEM_DCACHE_LOCK_ADDR = 0xFFFFFFFF +const EXTMEM_DCACHE_LOCK_ADDR_V = 0xFFFFFFFF +const EXTMEM_DCACHE_LOCK_ADDR_S = 0 +const EXTMEM_DCACHE_LOCK_SIZE = 0x0000FFFF +const EXTMEM_DCACHE_LOCK_SIZE_V = 0xFFFF +const EXTMEM_DCACHE_LOCK_SIZE_S = 0 +const EXTMEM_DCACHE_SYNC_DONE_V = 0x1 +const EXTMEM_DCACHE_SYNC_DONE_S = 3 +const EXTMEM_DCACHE_CLEAN_ENA_V = 0x1 +const EXTMEM_DCACHE_CLEAN_ENA_S = 2 +const EXTMEM_DCACHE_WRITEBACK_ENA_V = 0x1 +const EXTMEM_DCACHE_WRITEBACK_ENA_S = 1 +const EXTMEM_DCACHE_INVALIDATE_ENA_V = 0x1 +const EXTMEM_DCACHE_INVALIDATE_ENA_S = 0 +const EXTMEM_DCACHE_SYNC_ADDR = 0xFFFFFFFF +const EXTMEM_DCACHE_SYNC_ADDR_V = 0xFFFFFFFF +const EXTMEM_DCACHE_SYNC_ADDR_S = 0 +const EXTMEM_DCACHE_SYNC_SIZE = 0x007FFFFF +const EXTMEM_DCACHE_SYNC_SIZE_V = 0x7FFFFF +const EXTMEM_DCACHE_SYNC_SIZE_S = 0 +const EXTMEM_DCACHE_OCCUPY_DONE_V = 0x1 +const EXTMEM_DCACHE_OCCUPY_DONE_S = 1 +const EXTMEM_DCACHE_OCCUPY_ENA_V = 0x1 +const EXTMEM_DCACHE_OCCUPY_ENA_S = 0 +const EXTMEM_DCACHE_OCCUPY_ADDR = 0xFFFFFFFF +const EXTMEM_DCACHE_OCCUPY_ADDR_V = 0xFFFFFFFF +const EXTMEM_DCACHE_OCCUPY_ADDR_S = 0 +const EXTMEM_DCACHE_OCCUPY_SIZE = 0x0000FFFF +const EXTMEM_DCACHE_OCCUPY_SIZE_V = 0xFFFF +const EXTMEM_DCACHE_OCCUPY_SIZE_S = 0 +const EXTMEM_DCACHE_PRELOAD_ORDER_V = 0x1 +const EXTMEM_DCACHE_PRELOAD_ORDER_S = 2 +const EXTMEM_DCACHE_PRELOAD_DONE_V = 0x1 +const EXTMEM_DCACHE_PRELOAD_DONE_S = 1 +const EXTMEM_DCACHE_PRELOAD_ENA_V = 0x1 +const EXTMEM_DCACHE_PRELOAD_ENA_S = 0 +const EXTMEM_DCACHE_PRELOAD_ADDR = 0xFFFFFFFF +const EXTMEM_DCACHE_PRELOAD_ADDR_V = 0xFFFFFFFF +const EXTMEM_DCACHE_PRELOAD_ADDR_S = 0 +const EXTMEM_DCACHE_PRELOAD_SIZE = 0x0000FFFF +const EXTMEM_DCACHE_PRELOAD_SIZE_V = 0xFFFF +const EXTMEM_DCACHE_PRELOAD_SIZE_S = 0 +const EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_V = 0x1 +const EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_S = 9 +const EXTMEM_DCACHE_AUTOLOAD_SIZE = 0x00000003 +const EXTMEM_DCACHE_AUTOLOAD_SIZE_V = 0x3 +const EXTMEM_DCACHE_AUTOLOAD_SIZE_S = 7 +const EXTMEM_DCACHE_AUTOLOAD_RQST = 0x00000003 +const EXTMEM_DCACHE_AUTOLOAD_RQST_V = 0x3 +const EXTMEM_DCACHE_AUTOLOAD_RQST_S = 5 +const EXTMEM_DCACHE_AUTOLOAD_ORDER_V = 0x1 +const EXTMEM_DCACHE_AUTOLOAD_ORDER_S = 4 +const EXTMEM_DCACHE_AUTOLOAD_DONE_V = 0x1 +const EXTMEM_DCACHE_AUTOLOAD_DONE_S = 3 +const EXTMEM_DCACHE_AUTOLOAD_ENA_V = 0x1 +const EXTMEM_DCACHE_AUTOLOAD_ENA_S = 2 +const EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V = 0x1 +const EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S = 1 +const EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V = 0x1 +const EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S = 0 +const EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR = 0xFFFFFFFF +const EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V = 0xFFFFFFFF +const EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S = 0 +const EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE = 0x07FFFFFF +const EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V = 0x7FFFFFF +const EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S = 0 +const EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR = 0xFFFFFFFF +const EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V = 0xFFFFFFFF +const EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S = 0 +const EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE = 0x07FFFFFF +const EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V = 0x7FFFFFF +const EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S = 0 +const EXTMEM_ICACHE_BLOCKSIZE_MODE_V = 0x1 +const EXTMEM_ICACHE_BLOCKSIZE_MODE_S = 3 +const EXTMEM_ICACHE_SIZE_MODE_V = 0x1 +const EXTMEM_ICACHE_SIZE_MODE_S = 2 +const EXTMEM_ICACHE_WAY_MODE_V = 0x1 +const EXTMEM_ICACHE_WAY_MODE_S = 1 +const EXTMEM_ICACHE_ENABLE_V = 0x1 +const EXTMEM_ICACHE_ENABLE_S = 0 +const EXTMEM_ICACHE_SHUT_CORE1_BUS_V = 0x1 +const EXTMEM_ICACHE_SHUT_CORE1_BUS_S = 1 +const EXTMEM_ICACHE_SHUT_CORE0_BUS_V = 0x1 +const EXTMEM_ICACHE_SHUT_CORE0_BUS_S = 0 +const EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V = 0x1 +const EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S = 2 +const EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V = 0x1 +const EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S = 1 +const EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V = 0x1 +const EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S = 0 +const EXTMEM_ICACHE_PRELOCK_SCT1_EN_V = 0x1 +const EXTMEM_ICACHE_PRELOCK_SCT1_EN_S = 1 +const EXTMEM_ICACHE_PRELOCK_SCT0_EN_V = 0x1 +const EXTMEM_ICACHE_PRELOCK_SCT0_EN_S = 0 +const EXTMEM_ICACHE_PRELOCK_SCT0_ADDR = 0xFFFFFFFF +const EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V = 0xFFFFFFFF +const EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S = 0 +const EXTMEM_ICACHE_PRELOCK_SCT1_ADDR = 0xFFFFFFFF +const EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V = 0xFFFFFFFF +const EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S = 0 +const EXTMEM_ICACHE_PRELOCK_SCT0_SIZE = 0x0000FFFF +const EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V = 0xFFFF +const EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S = 16 +const EXTMEM_ICACHE_PRELOCK_SCT1_SIZE = 0x0000FFFF +const EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V = 0xFFFF +const EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S = 0 +const EXTMEM_ICACHE_LOCK_DONE_V = 0x1 +const EXTMEM_ICACHE_LOCK_DONE_S = 2 +const EXTMEM_ICACHE_UNLOCK_ENA_V = 0x1 +const EXTMEM_ICACHE_UNLOCK_ENA_S = 1 +const EXTMEM_ICACHE_LOCK_ENA_V = 0x1 +const EXTMEM_ICACHE_LOCK_ENA_S = 0 +const EXTMEM_ICACHE_LOCK_ADDR = 0xFFFFFFFF +const EXTMEM_ICACHE_LOCK_ADDR_V = 0xFFFFFFFF +const EXTMEM_ICACHE_LOCK_ADDR_S = 0 +const EXTMEM_ICACHE_LOCK_SIZE = 0x0000FFFF +const EXTMEM_ICACHE_LOCK_SIZE_V = 0xFFFF +const EXTMEM_ICACHE_LOCK_SIZE_S = 0 +const EXTMEM_ICACHE_SYNC_DONE_V = 0x1 +const EXTMEM_ICACHE_SYNC_DONE_S = 1 +const EXTMEM_ICACHE_INVALIDATE_ENA_V = 0x1 +const EXTMEM_ICACHE_INVALIDATE_ENA_S = 0 +const EXTMEM_ICACHE_SYNC_ADDR = 0xFFFFFFFF +const EXTMEM_ICACHE_SYNC_ADDR_V = 0xFFFFFFFF +const EXTMEM_ICACHE_SYNC_ADDR_S = 0 +const EXTMEM_ICACHE_SYNC_SIZE = 0x007FFFFF +const EXTMEM_ICACHE_SYNC_SIZE_V = 0x7FFFFF +const EXTMEM_ICACHE_SYNC_SIZE_S = 0 +const EXTMEM_ICACHE_PRELOAD_ORDER_V = 0x1 +const EXTMEM_ICACHE_PRELOAD_ORDER_S = 2 +const EXTMEM_ICACHE_PRELOAD_DONE_V = 0x1 +const EXTMEM_ICACHE_PRELOAD_DONE_S = 1 +const EXTMEM_ICACHE_PRELOAD_ENA_V = 0x1 +const EXTMEM_ICACHE_PRELOAD_ENA_S = 0 +const EXTMEM_ICACHE_PRELOAD_ADDR = 0xFFFFFFFF +const EXTMEM_ICACHE_PRELOAD_ADDR_V = 0xFFFFFFFF +const EXTMEM_ICACHE_PRELOAD_ADDR_S = 0 +const EXTMEM_ICACHE_PRELOAD_SIZE = 0x0000FFFF +const EXTMEM_ICACHE_PRELOAD_SIZE_V = 0xFFFF +const EXTMEM_ICACHE_PRELOAD_SIZE_S = 0 +const EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_V = 0x1 +const EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_S = 9 +const EXTMEM_ICACHE_AUTOLOAD_SIZE = 0x00000003 +const EXTMEM_ICACHE_AUTOLOAD_SIZE_V = 0x3 +const EXTMEM_ICACHE_AUTOLOAD_SIZE_S = 7 +const EXTMEM_ICACHE_AUTOLOAD_RQST = 0x00000003 +const EXTMEM_ICACHE_AUTOLOAD_RQST_V = 0x3 +const EXTMEM_ICACHE_AUTOLOAD_RQST_S = 5 +const EXTMEM_ICACHE_AUTOLOAD_ORDER_V = 0x1 +const EXTMEM_ICACHE_AUTOLOAD_ORDER_S = 4 +const EXTMEM_ICACHE_AUTOLOAD_DONE_V = 0x1 +const EXTMEM_ICACHE_AUTOLOAD_DONE_S = 3 +const EXTMEM_ICACHE_AUTOLOAD_ENA_V = 0x1 +const EXTMEM_ICACHE_AUTOLOAD_ENA_S = 2 +const EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V = 0x1 +const EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S = 1 +const EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V = 0x1 +const EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S = 0 +const EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR = 0xFFFFFFFF +const EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V = 0xFFFFFFFF +const EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S = 0 +const EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE = 0x07FFFFFF +const EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V = 0x7FFFFFF +const EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S = 0 +const EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR = 0xFFFFFFFF +const EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V = 0xFFFFFFFF +const EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S = 0 +const EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE = 0x07FFFFFF +const EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V = 0x7FFFFFF +const EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S = 0 +const EXTMEM_IBUS_TO_FLASH_START_VADDR = 0xFFFFFFFF +const EXTMEM_IBUS_TO_FLASH_START_VADDR_V = 0xFFFFFFFF +const EXTMEM_IBUS_TO_FLASH_START_VADDR_S = 0 +const EXTMEM_IBUS_TO_FLASH_END_VADDR = 0xFFFFFFFF +const EXTMEM_IBUS_TO_FLASH_END_VADDR_V = 0xFFFFFFFF +const EXTMEM_IBUS_TO_FLASH_END_VADDR_S = 0 +const EXTMEM_DBUS_TO_FLASH_START_VADDR = 0xFFFFFFFF +const EXTMEM_DBUS_TO_FLASH_START_VADDR_V = 0xFFFFFFFF +const EXTMEM_DBUS_TO_FLASH_START_VADDR_S = 0 +const EXTMEM_DBUS_TO_FLASH_END_VADDR = 0xFFFFFFFF +const EXTMEM_DBUS_TO_FLASH_END_VADDR_V = 0xFFFFFFFF +const EXTMEM_DBUS_TO_FLASH_END_VADDR_S = 0 +const EXTMEM_ICACHE_ACS_CNT_CLR_V = 0x1 +const EXTMEM_ICACHE_ACS_CNT_CLR_S = 1 +const EXTMEM_DCACHE_ACS_CNT_CLR_V = 0x1 +const EXTMEM_DCACHE_ACS_CNT_CLR_S = 0 +const EXTMEM_IBUS_ACS_MISS_CNT = 0xFFFFFFFF +const EXTMEM_IBUS_ACS_MISS_CNT_V = 0xFFFFFFFF +const EXTMEM_IBUS_ACS_MISS_CNT_S = 0 +const EXTMEM_IBUS_ACS_CNT = 0xFFFFFFFF +const EXTMEM_IBUS_ACS_CNT_V = 0xFFFFFFFF +const EXTMEM_IBUS_ACS_CNT_S = 0 +const EXTMEM_DBUS_ACS_FLASH_MISS_CNT = 0xFFFFFFFF +const EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V = 0xFFFFFFFF +const EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S = 0 +const EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT = 0xFFFFFFFF +const EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V = 0xFFFFFFFF +const EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S = 0 +const EXTMEM_DBUS_ACS_CNT = 0xFFFFFFFF +const EXTMEM_DBUS_ACS_CNT_V = 0xFFFFFFFF +const EXTMEM_DBUS_ACS_CNT_S = 0 +const EXTMEM_DBUS_CNT_OVF_INT_ENA_V = 0x1 +const EXTMEM_DBUS_CNT_OVF_INT_ENA_S = 8 +const EXTMEM_IBUS_CNT_OVF_INT_ENA_V = 0x1 +const EXTMEM_IBUS_CNT_OVF_INT_ENA_S = 7 +const EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_V = 0x1 +const EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_S = 6 +const EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V = 0x1 +const EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S = 5 +const EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V = 0x1 +const EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S = 4 +const EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_V = 0x1 +const EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_S = 3 +const EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_V = 0x1 +const EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_S = 2 +const EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V = 0x1 +const EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S = 1 +const EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V = 0x1 +const EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S = 0 +const EXTMEM_DBUS_CNT_OVF_INT_CLR_V = 0x1 +const EXTMEM_DBUS_CNT_OVF_INT_CLR_S = 8 +const EXTMEM_IBUS_CNT_OVF_INT_CLR_V = 0x1 +const EXTMEM_IBUS_CNT_OVF_INT_CLR_S = 7 +const EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_V = 0x1 +const EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_S = 6 +const EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V = 0x1 +const EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S = 5 +const EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V = 0x1 +const EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S = 4 +const EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_V = 0x1 +const EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_S = 3 +const EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_V = 0x1 +const EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_S = 2 +const EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V = 0x1 +const EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S = 1 +const EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V = 0x1 +const EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S = 0 +const EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_V = 0x1 +const EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_S = 11 +const EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V = 0x1 +const EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S = 10 +const EXTMEM_DBUS_ACS_CNT_OVF_ST_V = 0x1 +const EXTMEM_DBUS_ACS_CNT_OVF_ST_S = 9 +const EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V = 0x1 +const EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S = 8 +const EXTMEM_IBUS_ACS_CNT_OVF_ST_V = 0x1 +const EXTMEM_IBUS_ACS_CNT_OVF_ST_S = 7 +const EXTMEM_DCACHE_OCCUPY_EXC_ST_V = 0x1 +const EXTMEM_DCACHE_OCCUPY_EXC_ST_S = 6 +const EXTMEM_MMU_ENTRY_FAULT_ST_V = 0x1 +const EXTMEM_MMU_ENTRY_FAULT_ST_S = 5 +const EXTMEM_DCACHE_WRITE_FLASH_ST_V = 0x1 +const EXTMEM_DCACHE_WRITE_FLASH_ST_S = 4 +const EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_V = 0x1 +const EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_S = 3 +const EXTMEM_DCACHE_SYNC_OP_FAULT_ST_V = 0x1 +const EXTMEM_DCACHE_SYNC_OP_FAULT_ST_S = 2 +const EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V = 0x1 +const EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S = 1 +const EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V = 0x1 +const EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S = 0 +const EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V = 0x1 +const EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S = 4 +const EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_V = 0x1 +const EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_S = 3 +const EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V = 0x1 +const EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S = 2 +const EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V = 0x1 +const EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S = 1 +const EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V = 0x1 +const EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S = 0 +const EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V = 0x1 +const EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S = 4 +const EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_V = 0x1 +const EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_S = 3 +const EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V = 0x1 +const EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S = 2 +const EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V = 0x1 +const EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S = 1 +const EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V = 0x1 +const EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S = 0 +const EXTMEM_CORE0_DBUS_REJECT_ST_V = 0x1 +const EXTMEM_CORE0_DBUS_REJECT_ST_S = 4 +const EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_V = 0x1 +const EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_S = 3 +const EXTMEM_CORE0_IBUS_REJECT_ST_V = 0x1 +const EXTMEM_CORE0_IBUS_REJECT_ST_S = 2 +const EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V = 0x1 +const EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S = 1 +const EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V = 0x1 +const EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S = 0 +const EXTMEM_CORE1_DBUS_REJECT_INT_ENA_V = 0x1 +const EXTMEM_CORE1_DBUS_REJECT_INT_ENA_S = 4 +const EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_V = 0x1 +const EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_S = 3 +const EXTMEM_CORE1_IBUS_REJECT_INT_ENA_V = 0x1 +const EXTMEM_CORE1_IBUS_REJECT_INT_ENA_S = 2 +const EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_V = 0x1 +const EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_S = 1 +const EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_V = 0x1 +const EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_S = 0 +const EXTMEM_CORE1_DBUS_REJECT_INT_CLR_V = 0x1 +const EXTMEM_CORE1_DBUS_REJECT_INT_CLR_S = 4 +const EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_V = 0x1 +const EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_S = 3 +const EXTMEM_CORE1_IBUS_REJECT_INT_CLR_V = 0x1 +const EXTMEM_CORE1_IBUS_REJECT_INT_CLR_S = 2 +const EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_V = 0x1 +const EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_S = 1 +const EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_V = 0x1 +const EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_S = 0 +const EXTMEM_CORE1_DBUS_REJECT_ST_V = 0x1 +const EXTMEM_CORE1_DBUS_REJECT_ST_S = 4 +const EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_V = 0x1 +const EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_S = 3 +const EXTMEM_CORE1_IBUS_REJECT_ST_V = 0x1 +const EXTMEM_CORE1_IBUS_REJECT_ST_S = 2 +const EXTMEM_CORE1_IBUS_WR_ICACHE_ST_V = 0x1 +const EXTMEM_CORE1_IBUS_WR_ICACHE_ST_S = 1 +const EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_V = 0x1 +const EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_S = 0 +const EXTMEM_CORE0_DBUS_WORLD_V = 0x1 +const EXTMEM_CORE0_DBUS_WORLD_S = 6 +const EXTMEM_CORE0_DBUS_ATTR = 0x00000007 +const EXTMEM_CORE0_DBUS_ATTR_V = 0x7 +const EXTMEM_CORE0_DBUS_ATTR_S = 3 +const EXTMEM_CORE0_DBUS_TAG_ATTR = 0x00000007 +const EXTMEM_CORE0_DBUS_TAG_ATTR_V = 0x7 +const EXTMEM_CORE0_DBUS_TAG_ATTR_S = 0 +const EXTMEM_CORE0_DBUS_VADDR = 0xFFFFFFFF +const EXTMEM_CORE0_DBUS_VADDR_V = 0xFFFFFFFF +const EXTMEM_CORE0_DBUS_VADDR_S = 0 +const EXTMEM_CORE0_IBUS_WORLD_V = 0x1 +const EXTMEM_CORE0_IBUS_WORLD_S = 6 +const EXTMEM_CORE0_IBUS_ATTR = 0x00000007 +const EXTMEM_CORE0_IBUS_ATTR_V = 0x7 +const EXTMEM_CORE0_IBUS_ATTR_S = 3 +const EXTMEM_CORE0_IBUS_TAG_ATTR = 0x00000007 +const EXTMEM_CORE0_IBUS_TAG_ATTR_V = 0x7 +const EXTMEM_CORE0_IBUS_TAG_ATTR_S = 0 +const EXTMEM_CORE0_IBUS_VADDR = 0xFFFFFFFF +const EXTMEM_CORE0_IBUS_VADDR_V = 0xFFFFFFFF +const EXTMEM_CORE0_IBUS_VADDR_S = 0 +const EXTMEM_CORE1_DBUS_WORLD_V = 0x1 +const EXTMEM_CORE1_DBUS_WORLD_S = 6 +const EXTMEM_CORE1_DBUS_ATTR = 0x00000007 +const EXTMEM_CORE1_DBUS_ATTR_V = 0x7 +const EXTMEM_CORE1_DBUS_ATTR_S = 3 +const EXTMEM_CORE1_DBUS_TAG_ATTR = 0x00000007 +const EXTMEM_CORE1_DBUS_TAG_ATTR_V = 0x7 +const EXTMEM_CORE1_DBUS_TAG_ATTR_S = 0 +const EXTMEM_CORE1_DBUS_VADDR = 0xFFFFFFFF +const EXTMEM_CORE1_DBUS_VADDR_V = 0xFFFFFFFF +const EXTMEM_CORE1_DBUS_VADDR_S = 0 +const EXTMEM_CORE1_IBUS_WORLD_V = 0x1 +const EXTMEM_CORE1_IBUS_WORLD_S = 6 +const EXTMEM_CORE1_IBUS_ATTR = 0x00000007 +const EXTMEM_CORE1_IBUS_ATTR_V = 0x7 +const EXTMEM_CORE1_IBUS_ATTR_S = 3 +const EXTMEM_CORE1_IBUS_TAG_ATTR = 0x00000007 +const EXTMEM_CORE1_IBUS_TAG_ATTR_V = 0x7 +const EXTMEM_CORE1_IBUS_TAG_ATTR_S = 0 +const EXTMEM_CORE1_IBUS_VADDR = 0xFFFFFFFF +const EXTMEM_CORE1_IBUS_VADDR_V = 0xFFFFFFFF +const EXTMEM_CORE1_IBUS_VADDR_S = 0 +const EXTMEM_CACHE_MMU_FAULT_CODE = 0x0000000F +const EXTMEM_CACHE_MMU_FAULT_CODE_V = 0xF +const EXTMEM_CACHE_MMU_FAULT_CODE_S = 16 +const EXTMEM_CACHE_MMU_FAULT_CONTENT = 0x0000FFFF +const EXTMEM_CACHE_MMU_FAULT_CONTENT_V = 0xFFFF +const EXTMEM_CACHE_MMU_FAULT_CONTENT_S = 0 +const EXTMEM_CACHE_MMU_FAULT_VADDR = 0xFFFFFFFF +const EXTMEM_CACHE_MMU_FAULT_VADDR_V = 0xFFFFFFFF +const EXTMEM_CACHE_MMU_FAULT_VADDR_S = 0 +const EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_V = 0x1 +const EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_S = 1 +const EXTMEM_CACHE_FLASH_WRAP_AROUND_V = 0x1 +const EXTMEM_CACHE_FLASH_WRAP_AROUND_S = 0 +const EXTMEM_CACHE_MMU_MEM_FORCE_PU_V = 0x1 +const EXTMEM_CACHE_MMU_MEM_FORCE_PU_S = 2 +const EXTMEM_CACHE_MMU_MEM_FORCE_PD_V = 0x1 +const EXTMEM_CACHE_MMU_MEM_FORCE_PD_S = 1 +const EXTMEM_CACHE_MMU_MEM_FORCE_ON_V = 0x1 +const EXTMEM_CACHE_MMU_MEM_FORCE_ON_S = 0 +const EXTMEM_DCACHE_STATE = 0x00000FFF +const EXTMEM_DCACHE_STATE_V = 0xFFF +const EXTMEM_DCACHE_STATE_S = 12 +const EXTMEM_ICACHE_STATE = 0x00000FFF +const EXTMEM_ICACHE_STATE_V = 0xFFF +const EXTMEM_ICACHE_STATE_S = 0 +const EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V = 0x1 +const EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S = 1 +const EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V = 0x1 +const EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S = 0 +const EXTMEM_CLK_FORCE_ON_CRYPT_V = 0x1 +const EXTMEM_CLK_FORCE_ON_CRYPT_S = 2 +const EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V = 0x1 +const EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S = 1 +const EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V = 0x1 +const EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S = 0 +const EXTMEM_ALLOC_WB_HOLD_ARBITER_V = 0x1 +const EXTMEM_ALLOC_WB_HOLD_ARBITER_S = 0 +const EXTMEM_DCACHE_PRELOAD_INT_CLR_V = 0x1 +const EXTMEM_DCACHE_PRELOAD_INT_CLR_S = 5 +const EXTMEM_DCACHE_PRELOAD_INT_ENA_V = 0x1 +const EXTMEM_DCACHE_PRELOAD_INT_ENA_S = 4 +const EXTMEM_DCACHE_PRELOAD_INT_ST_V = 0x1 +const EXTMEM_DCACHE_PRELOAD_INT_ST_S = 3 +const EXTMEM_ICACHE_PRELOAD_INT_CLR_V = 0x1 +const EXTMEM_ICACHE_PRELOAD_INT_CLR_S = 2 +const EXTMEM_ICACHE_PRELOAD_INT_ENA_V = 0x1 +const EXTMEM_ICACHE_PRELOAD_INT_ENA_S = 1 +const EXTMEM_ICACHE_PRELOAD_INT_ST_V = 0x1 +const EXTMEM_ICACHE_PRELOAD_INT_ST_S = 0 +const EXTMEM_DCACHE_SYNC_INT_CLR_V = 0x1 +const EXTMEM_DCACHE_SYNC_INT_CLR_S = 5 +const EXTMEM_DCACHE_SYNC_INT_ENA_V = 0x1 +const EXTMEM_DCACHE_SYNC_INT_ENA_S = 4 +const EXTMEM_DCACHE_SYNC_INT_ST_V = 0x1 +const EXTMEM_DCACHE_SYNC_INT_ST_S = 3 +const EXTMEM_ICACHE_SYNC_INT_CLR_V = 0x1 +const EXTMEM_ICACHE_SYNC_INT_CLR_S = 2 +const EXTMEM_ICACHE_SYNC_INT_ENA_V = 0x1 +const EXTMEM_ICACHE_SYNC_INT_ENA_S = 1 +const EXTMEM_ICACHE_SYNC_INT_ST_V = 0x1 +const EXTMEM_ICACHE_SYNC_INT_ST_S = 0 +const EXTMEM_CACHE_MMU_OWNER = 0x00FFFFFF +const EXTMEM_CACHE_MMU_OWNER_V = 0xFFFFFF +const EXTMEM_CACHE_MMU_OWNER_S = 0 +const EXTMEM_CACHE_TRACE_ENA_V = 0x1 +const EXTMEM_CACHE_TRACE_ENA_S = 2 +const EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V = 0x1 +const EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S = 1 +const EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V = 0x1 +const EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S = 0 +const EXTMEM_DCACHE_FREEZE_DONE_V = 0x1 +const EXTMEM_DCACHE_FREEZE_DONE_S = 2 +const EXTMEM_DCACHE_FREEZE_MODE_V = 0x1 +const EXTMEM_DCACHE_FREEZE_MODE_S = 1 +const EXTMEM_DCACHE_FREEZE_ENA_V = 0x1 +const EXTMEM_DCACHE_FREEZE_ENA_S = 0 +const EXTMEM_ICACHE_FREEZE_DONE_V = 0x1 +const EXTMEM_ICACHE_FREEZE_DONE_S = 2 +const EXTMEM_ICACHE_FREEZE_MODE_V = 0x1 +const EXTMEM_ICACHE_FREEZE_MODE_S = 1 +const EXTMEM_ICACHE_FREEZE_ENA_V = 0x1 +const EXTMEM_ICACHE_FREEZE_ENA_S = 0 +const EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V = 0x1 +const EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S = 0 +const EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_V = 0x1 +const EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_S = 0 +const EXTMEM_CACHE_REQUEST_BYPASS_V = 0x1 +const EXTMEM_CACHE_REQUEST_BYPASS_S = 0 +const EXTMEM_CLK_EN_V = 0x1 +const EXTMEM_CLK_EN_S = 0 +const EXTMEM_DCACHE_TAG_OBJECT_V = 0x1 +const EXTMEM_DCACHE_TAG_OBJECT_S = 1 +const EXTMEM_ICACHE_TAG_OBJECT_V = 0x1 +const EXTMEM_ICACHE_TAG_OBJECT_S = 0 +const EXTMEM_CACHE_TAG_WAY_OBJECT = 0x00000007 +const EXTMEM_CACHE_TAG_WAY_OBJECT_V = 0x7 +const EXTMEM_CACHE_TAG_WAY_OBJECT_S = 0 +const EXTMEM_CACHE_VADDR = 0xFFFFFFFF +const EXTMEM_CACHE_VADDR_V = 0xFFFFFFFF +const EXTMEM_CACHE_VADDR_S = 0 +const EXTMEM_CACHE_TAG_CONTENT = 0xFFFFFFFF +const EXTMEM_CACHE_TAG_CONTENT_V = 0xFFFFFFFF +const EXTMEM_CACHE_TAG_CONTENT_S = 0 +const EXTMEM_DATE = 0x0FFFFFFF +const EXTMEM_DATE_V = 0xFFFFFFF +const EXTMEM_DATE_S = 0 diff --git a/esp32/extmem_struct.go b/esp32/extmem_struct.go new file mode 100644 index 00000000..347bb116 --- /dev/null +++ b/esp32/extmem_struct.go @@ -0,0 +1,394 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type ExtmemDevS struct { + DcacheCtrl struct { + Val c.Uint32T + } + DcacheCtrl1 struct { + Val c.Uint32T + } + DcacheTagPowerCtrl struct { + Val c.Uint32T + } + DcachePrelockCtrl struct { + Val c.Uint32T + } + DcachePrelockSct0Addr c.Uint32T + DcachePrelockSct1Addr c.Uint32T + DcachePrelockSctSize struct { + Val c.Uint32T + } + DcacheLockCtrl struct { + Val c.Uint32T + } + DcacheLockAddr c.Uint32T + DcacheLockSize struct { + Val c.Uint32T + } + DcacheSyncCtrl struct { + Val c.Uint32T + } + DcacheSyncAddr c.Uint32T + DcacheSyncSize struct { + Val c.Uint32T + } + DcacheOccupyCtrl struct { + Val c.Uint32T + } + DcacheOccupyAddr c.Uint32T + DcacheOccupySize struct { + Val c.Uint32T + } + DcachePreloadCtrl struct { + Val c.Uint32T + } + DcachePreloadAddr c.Uint32T + DcachePreloadSize struct { + Val c.Uint32T + } + DcacheAutoloadCtrl struct { + Val c.Uint32T + } + DcacheAutoloadSct0Addr c.Uint32T + DcacheAutoloadSct0Size struct { + Val c.Uint32T + } + DcacheAutoloadSct1Addr c.Uint32T + DcacheAutoloadSct1Size struct { + Val c.Uint32T + } + IcacheCtrl struct { + Val c.Uint32T + } + IcacheCtrl1 struct { + Val c.Uint32T + } + IcacheTagPowerCtrl struct { + Val c.Uint32T + } + IcachePrelockCtrl struct { + Val c.Uint32T + } + IcachePrelockSct0Addr c.Uint32T + IcachePrelockSct1Addr c.Uint32T + IcachePrelockSctSize struct { + Val c.Uint32T + } + IcacheLockCtrl struct { + Val c.Uint32T + } + IcacheLockAddr c.Uint32T + IcacheLockSize struct { + Val c.Uint32T + } + IcacheSyncCtrl struct { + Val c.Uint32T + } + IcacheSyncAddr c.Uint32T + IcacheSyncSize struct { + Val c.Uint32T + } + IcachePreloadCtrl struct { + Val c.Uint32T + } + IcachePreloadAddr c.Uint32T + IcachePreloadSize struct { + Val c.Uint32T + } + IcacheAutoloadCtrl struct { + Val c.Uint32T + } + IcacheAutoloadSct0Addr c.Uint32T + IcacheAutoloadSct0Size struct { + Val c.Uint32T + } + IcacheAutoloadSct1Addr c.Uint32T + IcacheAutoloadSct1Size struct { + Val c.Uint32T + } + IbusToFlashStartVaddr c.Uint32T + IbusToFlashEndVaddr c.Uint32T + DbusToFlashStartVaddr c.Uint32T + DbusToFlashEndVaddr c.Uint32T + CacheAcsCntClr struct { + Val c.Uint32T + } + IbusAcsMissCnt c.Uint32T + IbusAcsCnt c.Uint32T + DbusAcsFlashMissCnt c.Uint32T + DbusAcsSpiramMissCnt c.Uint32T + DbusAcsCnt c.Uint32T + CacheIlgIntEna struct { + Val c.Uint32T + } + CacheIlgIntClr struct { + Val c.Uint32T + } + CacheIlgIntSt struct { + Val c.Uint32T + } + Core0AcsCacheIntEna struct { + Val c.Uint32T + } + Core0AcsCacheIntClr struct { + Val c.Uint32T + } + Core0AcsCacheIntSt struct { + Val c.Uint32T + } + Core1AcsCacheIntEna struct { + Val c.Uint32T + } + Core1AcsCacheIntClr struct { + Val c.Uint32T + } + Core1AcsCacheIntSt struct { + Val c.Uint32T + } + Core0DbusRejectSt struct { + Val c.Uint32T + } + Core0DbusRejectVaddr c.Uint32T + Core0IbusRejectSt struct { + Val c.Uint32T + } + Core0IbusRejectVaddr c.Uint32T + Core1DbusRejectSt struct { + Val c.Uint32T + } + Core1DbusRejectVaddr c.Uint32T + Core1IbusRejectSt struct { + Val c.Uint32T + } + Core1IbusRejectVaddr c.Uint32T + CacheMmuFaultContent struct { + Val c.Uint32T + } + CacheMmuFaultVaddr c.Uint32T + CacheWrapAroundCtrl struct { + Val c.Uint32T + } + CacheMmuPowerCtrl struct { + Val c.Uint32T + } + CacheState struct { + Val c.Uint32T + } + CacheEncryptDecryptRecordDisable struct { + Val c.Uint32T + } + CacheEncryptDecryptClkForceOn struct { + Val c.Uint32T + } + CacheBridgeArbiterCtrl struct { + Val c.Uint32T + } + CachePreloadIntCtrl struct { + Val c.Uint32T + } + CacheSyncIntCtrl struct { + Val c.Uint32T + } + CacheMmuOwner struct { + Val c.Uint32T + } + CacheConfMisc struct { + Val c.Uint32T + } + DcacheFreeze struct { + Val c.Uint32T + } + IcacheFreeze struct { + Val c.Uint32T + } + IcacheAtomicOperateEna struct { + Val c.Uint32T + } + DcacheAtomicOperateEna struct { + Val c.Uint32T + } + CacheRequest struct { + Val c.Uint32T + } + ClockGate struct { + Val c.Uint32T + } + Reserved168 c.Uint32T + Reserved16c c.Uint32T + Reserved170 c.Uint32T + Reserved174 c.Uint32T + Reserved178 c.Uint32T + Reserved17c c.Uint32T + CacheTagObjectCtrl struct { + Val c.Uint32T + } + CacheTagWayObject struct { + Val c.Uint32T + } + CacheVaddr c.Uint32T + CacheTagContent c.Uint32T + Reserved190 c.Uint32T + Reserved194 c.Uint32T + Reserved198 c.Uint32T + Reserved19c c.Uint32T + Reserved1a0 c.Uint32T + Reserved1a4 c.Uint32T + Reserved1a8 c.Uint32T + Reserved1ac c.Uint32T + Reserved1b0 c.Uint32T + Reserved1b4 c.Uint32T + Reserved1b8 c.Uint32T + Reserved1bc c.Uint32T + Reserved1c0 c.Uint32T + Reserved1c4 c.Uint32T + Reserved1c8 c.Uint32T + Reserved1cc c.Uint32T + Reserved1d0 c.Uint32T + Reserved1d4 c.Uint32T + Reserved1d8 c.Uint32T + Reserved1dc c.Uint32T + Reserved1e0 c.Uint32T + Reserved1e4 c.Uint32T + Reserved1e8 c.Uint32T + Reserved1ec c.Uint32T + Reserved1f0 c.Uint32T + Reserved1f4 c.Uint32T + Reserved1f8 c.Uint32T + Reserved1fc c.Uint32T + Reserved200 c.Uint32T + Reserved204 c.Uint32T + Reserved208 c.Uint32T + Reserved20c c.Uint32T + Reserved210 c.Uint32T + Reserved214 c.Uint32T + Reserved218 c.Uint32T + Reserved21c c.Uint32T + Reserved220 c.Uint32T + Reserved224 c.Uint32T + Reserved228 c.Uint32T + Reserved22c c.Uint32T + Reserved230 c.Uint32T + Reserved234 c.Uint32T + Reserved238 c.Uint32T + Reserved23c c.Uint32T + Reserved240 c.Uint32T + Reserved244 c.Uint32T + Reserved248 c.Uint32T + Reserved24c c.Uint32T + Reserved250 c.Uint32T + Reserved254 c.Uint32T + Reserved258 c.Uint32T + Reserved25c c.Uint32T + Reserved260 c.Uint32T + Reserved264 c.Uint32T + Reserved268 c.Uint32T + Reserved26c c.Uint32T + Reserved270 c.Uint32T + Reserved274 c.Uint32T + Reserved278 c.Uint32T + Reserved27c c.Uint32T + Reserved280 c.Uint32T + Reserved284 c.Uint32T + Reserved288 c.Uint32T + Reserved28c c.Uint32T + Reserved290 c.Uint32T + Reserved294 c.Uint32T + Reserved298 c.Uint32T + Reserved29c c.Uint32T + Reserved2a0 c.Uint32T + Reserved2a4 c.Uint32T + Reserved2a8 c.Uint32T + Reserved2ac c.Uint32T + Reserved2b0 c.Uint32T + Reserved2b4 c.Uint32T + Reserved2b8 c.Uint32T + Reserved2bc c.Uint32T + Reserved2c0 c.Uint32T + Reserved2c4 c.Uint32T + Reserved2c8 c.Uint32T + Reserved2cc c.Uint32T + Reserved2d0 c.Uint32T + Reserved2d4 c.Uint32T + Reserved2d8 c.Uint32T + Reserved2dc c.Uint32T + Reserved2e0 c.Uint32T + Reserved2e4 c.Uint32T + Reserved2e8 c.Uint32T + Reserved2ec c.Uint32T + Reserved2f0 c.Uint32T + Reserved2f4 c.Uint32T + Reserved2f8 c.Uint32T + Reserved2fc c.Uint32T + Reserved300 c.Uint32T + Reserved304 c.Uint32T + Reserved308 c.Uint32T + Reserved30c c.Uint32T + Reserved310 c.Uint32T + Reserved314 c.Uint32T + Reserved318 c.Uint32T + Reserved31c c.Uint32T + Reserved320 c.Uint32T + Reserved324 c.Uint32T + Reserved328 c.Uint32T + Reserved32c c.Uint32T + Reserved330 c.Uint32T + Reserved334 c.Uint32T + Reserved338 c.Uint32T + Reserved33c c.Uint32T + Reserved340 c.Uint32T + Reserved344 c.Uint32T + Reserved348 c.Uint32T + Reserved34c c.Uint32T + Reserved350 c.Uint32T + Reserved354 c.Uint32T + Reserved358 c.Uint32T + Reserved35c c.Uint32T + Reserved360 c.Uint32T + Reserved364 c.Uint32T + Reserved368 c.Uint32T + Reserved36c c.Uint32T + Reserved370 c.Uint32T + Reserved374 c.Uint32T + Reserved378 c.Uint32T + Reserved37c c.Uint32T + Reserved380 c.Uint32T + Reserved384 c.Uint32T + Reserved388 c.Uint32T + Reserved38c c.Uint32T + Reserved390 c.Uint32T + Reserved394 c.Uint32T + Reserved398 c.Uint32T + Reserved39c c.Uint32T + Reserved3a0 c.Uint32T + Reserved3a4 c.Uint32T + Reserved3a8 c.Uint32T + Reserved3ac c.Uint32T + Reserved3b0 c.Uint32T + Reserved3b4 c.Uint32T + Reserved3b8 c.Uint32T + Reserved3bc c.Uint32T + Reserved3c0 c.Uint32T + Reserved3c4 c.Uint32T + Reserved3c8 c.Uint32T + Reserved3cc c.Uint32T + Reserved3d0 c.Uint32T + Reserved3d4 c.Uint32T + Reserved3d8 c.Uint32T + Reserved3dc c.Uint32T + Reserved3e0 c.Uint32T + Reserved3e4 c.Uint32T + Reserved3e8 c.Uint32T + Reserved3ec c.Uint32T + Reserved3f0 c.Uint32T + Reserved3f4 c.Uint32T + Reserved3f8 c.Uint32T + Date struct { + Val c.Uint32T + } +} +type ExtmemDevT ExtmemDevS diff --git a/esp32/extreg.go b/esp32/extreg.go new file mode 100644 index 00000000..73dc2d1e --- /dev/null +++ b/esp32/extreg.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +const DSRSET = 0x10200C diff --git a/esp32/fe_reg.go b/esp32/fe_reg.go new file mode 100644 index 00000000..500b1845 --- /dev/null +++ b/esp32/fe_reg.go @@ -0,0 +1,12 @@ +package freertos + +import _ "unsafe" + +const FE_IQ_EST_FORCE_PU_V = 1 +const FE_IQ_EST_FORCE_PU_S = 5 +const FE_IQ_EST_FORCE_PD_V = 1 +const FE_IQ_EST_FORCE_PD_S = 4 +const FE2_TX_INF_FORCE_PU_V = 1 +const FE2_TX_INF_FORCE_PU_S = 10 +const FE2_TX_INF_FORCE_PD_V = 1 +const FE2_TX_INF_FORCE_PD_S = 9 diff --git a/esp32/freertos_autogen_link.go b/esp32/freertos_autogen_link.go new file mode 100644 index 00000000..40067759 --- /dev/null +++ b/esp32/freertos_autogen_link.go @@ -0,0 +1,7 @@ +package freertos + +import ( + _ "github.com/goplus/lib/c" + _ "github.com/goplus/lib/c/os" + _ "github.com/goplus/lib/c/time" +) diff --git a/esp32/freertos_debug.go b/esp32/freertos_debug.go new file mode 100644 index 00000000..11e1ca73 --- /dev/null +++ b/esp32/freertos_debug.go @@ -0,0 +1,97 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Task Snapshot structure + * + * - Used with the uxTaskGetSnapshotAll() function to save memory snapshot of each task in the system. + * - We need this structure because TCB_t is defined (hidden) in tasks.c. + */ + +type XTASKSNAPSHOT struct { + PxTCB c.Pointer + PxTopOfStack *StackTypeT + PxEndOfStack *StackTypeT +} +type TaskSnapshotT XTASKSNAPSHOT + +/** + * @brief Task Snapshot iterator + * + * Used in xTaskGetNext(). Must be zero/null initialized on the first call. + */ + +type TaskIterator struct { + UxCurrentListIndex UBaseTypeT + PxNextListItem *ListItemT + PxTaskHandle TaskHandleT +} +type TaskIteratorT TaskIterator + +/** + * @brief Get the next task using the task iterator. + * + * This function retrieves the next task in the traversal sequence. + * + * @param xIterator Pointer to the task iterator structure. + * + * @return Index of the current task list. Returns -1 if all tasks have been traversed. + * + * @note The task iterator keeps track of the current state during task traversal, + * including the index of the current task list and the pointer of the next task list item. + * When all tasks have been traversed, this function returns -1. + * If a broken or corrupted task is encountered, the task handle is set to NULL. + * + */ +// llgo:link (*TaskIteratorT).XTaskGetNext C.xTaskGetNext +func (recv_ *TaskIteratorT) XTaskGetNext() c.Int { + return 0 +} + +/** + * @brief Fill a TaskSnapshot_t structure for specified task. + * + * - This function is used by the panic handler to get the snapshot of a particular task. + * + * @note This function should only be called when FreeRTOS is no longer running (e.g., during a panic) as this function + * does not acquire any locks. + * @param[in] pxTask Task's handle + * @param[out] pxTaskSnapshot Snapshot of the task + * @return pdTRUE if operation was successful else pdFALSE + */ +//go:linkname VTaskGetSnapshot C.vTaskGetSnapshot +func VTaskGetSnapshot(pxTask TaskHandleT, pxTaskSnapshot *TaskSnapshotT) BaseTypeT + +/** + * @brief Fill an array of TaskSnapshot_t structures for every task in the system + * + * - This function is used by the panic handler to get a snapshot of all tasks in the system + * + * @note This function should only be called when FreeRTOS is no longer running (e.g., during a panic) as this function + * does not acquire any locks. + * @param[out] pxTaskSnapshotArray Array of TaskSnapshot_t structures filled by this function + * @param[in] uxArrayLength Length of the provided array + * @param[out] pxTCBSize Size of the a task's TCB structure (can be set to NULL) + * @return UBaseType_t + */ +// llgo:link (*TaskSnapshotT).UxTaskGetSnapshotAll C.uxTaskGetSnapshotAll +func (recv_ *TaskSnapshotT) UxTaskGetSnapshotAll(uxArrayLength UBaseTypeT, pxTCBSize *UBaseTypeT) UBaseTypeT { + return 0 +} + +/** + * @brief Get a void pointer to the current TCB of a particular core + * + * @note This function provides no guarantee that the return TCB will still be the current task (or that the task still + * exists) when it returns. It is the caller's responsibility to ensure that the task does not get scheduled or deleted. + * @param xCoreID The core to query + * @return Void pointer to current TCB + */ +// llgo:link BaseTypeT.PvTaskGetCurrentTCBForCore C.pvTaskGetCurrentTCBForCore +func (recv_ BaseTypeT) PvTaskGetCurrentTCBForCore() c.Pointer { + return nil +} diff --git a/esp32/freertos_idf_additions_priv.go b/esp32/freertos_idf_additions_priv.go new file mode 100644 index 00000000..15e6ee89 --- /dev/null +++ b/esp32/freertos_idf_additions_priv.go @@ -0,0 +1,111 @@ +package freertos + +import _ "unsafe" + +/* + * In ESP-IDF FreeRTOS under SMP builds, spinlocks are to protect different + * groups of data. This function is a wrapper to take the "xKernelLock" spinlock + * of tasks.c. + * + * This lock is taken whenever any of the kernel's data structures are + * accessed/modified, such as when adding/removing tasks to/from the delayed + * task list or various event lists. + * + * In more cases, kernel data structures are not accessed by functions outside + * tasks.c. Thus, all accesses of the kernel data structures inside tasks.c will + * handle the taking/releasing of the "xKerneLock". + * + * This functions is meant to be called by xEventGroupSetBits() and + * vEventGroupDelete() as both those functions will directly access event lists + * (which are kernel data structures). Thus, a wrapper function must be provided + * to take/release the "xKernelLock" from outside tasks.c. + */ +//go:linkname PrvTakeKernelLock C.prvTakeKernelLock +func PrvTakeKernelLock() + +//go:linkname PrvReleaseKernelLock C.prvReleaseKernelLock +func PrvReleaseKernelLock() + +/* + * In ESP-IDF FreeRTOS (i.e., multi-core SMP), core 0 manages the the FreeRTOS + * tick count. Thus only core 0 calls xTaskIncrementTick(). + * + * However, all other cores also receive a periodic tick interrupt. Thus all + * other cores should call this function instead. + * + * This function will check if the current core requires time slicing, and also + * call the application tick hook. However, the tick count will remain unchanged. + */ +//go:linkname XTaskIncrementTickOtherCores C.xTaskIncrementTickOtherCores +func XTaskIncrementTickOtherCores() BaseTypeT + +/** + * @brief Structure to save a task's previous priority + * + * This structure is meant to be used with prvTaskPriorityRaise() and + * prvTaskPriorityRestore(). + */ + +type PrvTaskSavedPriorityT struct { + UxPriority UBaseTypeT + UxBasePriority UBaseTypeT +} + +/** + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * Saves the current priority and current base priority of a task, then raises + * the task's current and base priority to uxNewPriority if uxNewPriority is of + * a higher priority. + * + * Once a task's priority has been raised with this function, the priority + * can be restored by calling prvTaskPriorityRestore() + * + * - Note that this function differs from vTaskPrioritySet() as the task's + * current priority will be modified even if the task has already + * inherited a priority. + * - This function is intended for special circumstance where a task must be + * forced immediately to a higher priority. + * + * For configUSE_MUTEXES == 0: A context switch will occur before the + * function returns if the priority being set is higher than the priority of the + * currently executing task. + * + * @note This functions is private and should only be called internally + * within various IDF components. Users should never call this function from + * their application. + * + * @note vTaskPrioritySet() should not be called while a task's priority is + * already raised via this function + * + * @param pxSavedPriority returns base and current priorities + * + * @param uxNewPriority The priority to which the task's priority will be + * set. + */ +// llgo:link (*PrvTaskSavedPriorityT).PrvTaskPriorityRaise C.prvTaskPriorityRaise +func (recv_ *PrvTaskSavedPriorityT) PrvTaskPriorityRaise(uxNewPriority UBaseTypeT) { +} + +/** + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * Restore a task's priority that was previously raised by + * prvTaskPriorityRaise(). + * + * For configUSE_MUTEXES == 0: A context switch will occur before the function + * returns if the priority being set is higher than the priority of the currently + * executing task. + * + * @note This functions is private and should only be called internally within + * various IDF components. Users should never call this function from their + * application. + * + * @param pxSavedPriority previously saved base and current priorities that need + * to be restored + */ +// llgo:link (*PrvTaskSavedPriorityT).PrvTaskPriorityRestore C.prvTaskPriorityRestore +func (recv_ *PrvTaskSavedPriorityT) PrvTaskPriorityRestore() { +} diff --git a/esp32/freertos_tasks_c_additions.go b/esp32/freertos_tasks_c_additions.go new file mode 100644 index 00000000..666c09a1 --- /dev/null +++ b/esp32/freertos_tasks_c_additions.go @@ -0,0 +1,30 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Get reentrancy structure of the current task + * + * - This function is required by newlib (when __DYNAMIC_REENT__ is enabled) + * - It will return a pointer to the current task's reent struct + * - If FreeRTOS is not running, it will return the global reent struct + * + * @return Pointer to a the (current taks's)/(global) reent struct + */ +//go:linkname X__getreent C.__getreent +func X__getreent() *X_reent + +const ( + ESP_FREERTOS_DEBUG_TABLE_SIZE c.Int = 0 + ESP_FREERTOS_DEBUG_TABLE_VERSION c.Int = 1 + ESP_FREERTOS_DEBUG_KERNEL_VER_MAJOR c.Int = 2 + ESP_FREERTOS_DEBUG_KERNEL_VER_MINOR c.Int = 3 + ESP_FREERTOS_DEBUG_KERNEL_VER_BUILD c.Int = 4 + ESP_FREERTOS_DEBUG_UX_TOP_USED_PIORITY c.Int = 5 + ESP_FREERTOS_DEBUG_PX_TOP_OF_STACK c.Int = 6 + ESP_FREERTOS_DEBUG_PC_TASK_NAME c.Int = 7 + ESP_FREERTOS_DEBUG_TABLE_END c.Int = 8 +) diff --git a/esp32/freertos_test_utils.go b/esp32/freertos_test_utils.go new file mode 100644 index 00000000..6ca98638 --- /dev/null +++ b/esp32/freertos_test_utils.go @@ -0,0 +1,23 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:type C +type TestFunctionT func(c.Pointer) + +/** + * @brief Run a test function on each core + * + * This function will internally create a task pinned to each core, where each task will call the provided test + * function. This function will block until all cores finish executing the test function. + * + * @param pxTestCode Test function + * @param pvTestCodeArg Argument provided to test function + * @param ulStackDepth Stack depth of the created tasks + * @param uxPriority Priority of the created tasks + */ +//go:linkname VTestOnAllCores C.vTestOnAllCores +func VTestOnAllCores(pxTestCode TestFunctionT, pvTestCodeArg c.Pointer, ulStackDepth c.Uint32T, uxPriority UBaseTypeT) diff --git a/esp32/gdma.go b/esp32/gdma.go new file mode 100644 index 00000000..27d6fcc3 --- /dev/null +++ b/esp32/gdma.go @@ -0,0 +1,407 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type GdmaChannelT struct { + Unused [8]uint8 +} +type GdmaChannelHandleT *GdmaChannelT + +/** + * @brief Collection of configuration items that used for allocating GDMA channel + * + */ + +type GdmaChannelAllocConfigT struct { + SiblingChan GdmaChannelHandleT + Direction GdmaChannelDirectionT + Flags struct { + ReserveSibling c.Int + IsrCacheSafe c.Int + } +} + +/** + * @brief Type of GDMA event data + */ + +type GdmaEventDataT struct { + Flags struct { + AbnormalEof c.Uint32T + NormalEof c.Uint32T + } +} + +// llgo:type C +type GdmaEventCallbackT func(GdmaChannelHandleT, *GdmaEventDataT, c.Pointer) bool + +/** + * @brief Group of supported GDMA TX callbacks + * @note The callbacks are all running under ISR environment + */ + +type GdmaTxEventCallbacksT struct { + OnTransEof GdmaEventCallbackT + OnDescrErr GdmaEventCallbackT +} + +/** + * @brief Group of supported GDMA RX callbacks + * @note The callbacks are all running under ISR environment + */ + +type GdmaRxEventCallbacksT struct { + OnRecvEof GdmaEventCallbackT + OnDescrErr GdmaEventCallbackT + OnRecvDone GdmaEventCallbackT +} + +/** + * @brief Type of GDMA engine trigger + * @note It's recommended to initialize this structure with `GDMA_MAKE_TRIGGER`. + * + */ + +type GdmaTriggerT struct { + Periph GdmaTriggerPeripheralT + InstanceId c.Int + BusId c.Int +} + +/** + * @brief A collection of strategy item that each GDMA channel could apply + * + */ + +type GdmaStrategyConfigT struct { + OwnerCheck bool + AutoUpdateDesc bool + EofTillDataPopped bool +} + +/** + * @brief Create AHB-GDMA channel + * @note This API won't install interrupt service for the allocated channel. + * If interrupt service is needed, user has to register GDMA event callback by `gdma_register_tx_event_callbacks` or `gdma_register_rx_event_callbacks`. + * + * @param[in] config Pointer to a collection of configurations for allocating GDMA channel + * @param[out] ret_chan Returned channel handle + * @return + * - ESP_OK: Create DMA channel successfully + * - ESP_ERR_INVALID_ARG: Create DMA channel failed because of invalid argument + * - ESP_ERR_NO_MEM: Create DMA channel failed because out of memory + * - ESP_FAIL: Create DMA channel failed because of other error + */ +// llgo:link (*GdmaChannelAllocConfigT).GdmaNewAhbChannel C.gdma_new_ahb_channel +func (recv_ *GdmaChannelAllocConfigT) GdmaNewAhbChannel(ret_chan *GdmaChannelHandleT) EspErrT { + return 0 +} + +/** + * @brief Create AXI-GDMA channel + * @note This API won't install interrupt service for the allocated channel. + * If interrupt service is needed, user has to register GDMA event callback by `gdma_register_tx_event_callbacks` or `gdma_register_rx_event_callbacks`. + * + * @param[in] config Pointer to a collection of configurations for allocating GDMA channel + * @param[out] ret_chan Returned channel handle + * @return + * - ESP_OK: Create DMA channel successfully + * - ESP_ERR_INVALID_ARG: Create DMA channel failed because of invalid argument + * - ESP_ERR_NO_MEM: Create DMA channel failed because out of memory + * - ESP_FAIL: Create DMA channel failed because of other error + */ +// llgo:link (*GdmaChannelAllocConfigT).GdmaNewAxiChannel C.gdma_new_axi_channel +func (recv_ *GdmaChannelAllocConfigT) GdmaNewAxiChannel(ret_chan *GdmaChannelHandleT) EspErrT { + return 0 +} + +/** + * @brief Connect GDMA channel to trigger peripheral + * + * @note Suggest to use helper macro `GDMA_MAKE_TRIGGER` to construct parameter `trig_periph`. e.g. GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SHA,0) + * @note Connecting to a peripheral will also reset the DMA FIFO and FSM automatically + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] trig_periph GDMA trigger peripheral + * @return + * - ESP_OK: Connect GDMA channel successfully + * - ESP_ERR_INVALID_ARG: Connect GDMA channel failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Connect GDMA channel failed because DMA channel is working with another peripheral + * - ESP_FAIL: Connect GDMA channel failed because of other error + */ +//go:linkname GdmaConnect C.gdma_connect +func GdmaConnect(dma_chan GdmaChannelHandleT, trig_periph GdmaTriggerT) EspErrT + +/** + * @brief Disconnect GMA channel from peripheral + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @return + * - ESP_OK: Disconnect GDMA channel successfully + * - ESP_ERR_INVALID_ARG: Disconnect GDMA channel failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Disconnect GDMA channel failed because DMA channel is not connected to any peripheral + * - ESP_FAIL: Disconnect DMA channel failed because of other error + */ +//go:linkname GdmaDisconnect C.gdma_disconnect +func GdmaDisconnect(dma_chan GdmaChannelHandleT) EspErrT + +/** + * @brief Channel transfer configurations + */ + +type GdmaTransferConfigT struct { + MaxDataBurstSize c.Uint32T + AccessExtMem bool +} + +/** + * @brief Configure transfer parameters for a DMA channel + * + * @note It's highly recommended to enable the burst mode and set proper burst size for the DMA channel, + * which can improve the performance in accessing external memory by a lot. + * + * @param[in] chan DMA channel handle, allocated by `gdma_new_channel` + * @param[in] config Transfer configurations + * @return + * - ESP_OK: Configure DMA transfer parameters successfully + * - ESP_ERR_INVALID_ARG: Configure DMA transfer parameters failed because of invalid argument + * - ESP_FAIL: Configure DMA transfer parameters failed because of other error + */ +//go:linkname GdmaConfigTransfer C.gdma_config_transfer +func GdmaConfigTransfer(dma_chan GdmaChannelHandleT, config *GdmaTransferConfigT) EspErrT + +/** + * @brief Get the alignment constraints for internal and external memory + * + * @note You should call this function after `gdma_config_transfer`, the later one can + * adjust the alignment constraints based on various conditions, e.g. burst size, memory encryption, etc. + * @note You can use returned alignment value to validate if a DMA buffer provided by the upper layer meets the constraints. + * @note The returned alignment doesn't take the cache line size into account, if you want to do aligned memory allocation, + * you should align the buffer size to the cache line size by yourself if the DMA buffer is behind a cache. + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[out] int_mem_alignment Internal memory alignment + * @param[out] ext_mem_alignment External memory alignment + * @return + * - ESP_OK: Get alignment constraints successfully + * - ESP_ERR_INVALID_ARG: Get alignment constraints failed because of invalid argument + * - ESP_FAIL: Get alignment constraints failed because of other error + */ +//go:linkname GdmaGetAlignmentConstraints C.gdma_get_alignment_constraints +func GdmaGetAlignmentConstraints(dma_chan GdmaChannelHandleT, int_mem_alignment *c.SizeT, ext_mem_alignment *c.SizeT) EspErrT + +/** + * @brief Apply channel strategy for GDMA channel + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] config Configuration of GDMA channel strategy + * - ESP_OK: Apply channel strategy successfully + * - ESP_ERR_INVALID_ARG: Apply channel strategy failed because of invalid argument + * - ESP_FAIL: Apply channel strategy failed because of other error + */ +//go:linkname GdmaApplyStrategy C.gdma_apply_strategy +func GdmaApplyStrategy(dma_chan GdmaChannelHandleT, config *GdmaStrategyConfigT) EspErrT + +/** + * @brief Set GDMA channel priority + * + * @note By default, all GDMA channels are with the same priority: 0. Channels with the same priority are served in round-robin manner. + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] priority Priority of GDMA channel, higher value means higher priority + * @return + * - ESP_OK: Set GDMA channel priority successfully + * - ESP_ERR_INVALID_ARG: Set GDMA channel priority failed because of invalid argument, e.g. priority out of range [0,GDMA_LL_CHANNEL_MAX_PRIORITY] + * - ESP_FAIL: Set GDMA channel priority failed because of other error + */ +//go:linkname GdmaSetPriority C.gdma_set_priority +func GdmaSetPriority(dma_chan GdmaChannelHandleT, priority c.Uint32T) EspErrT + +/** + * @brief Delete GDMA channel + * @note If you call `gdma_new_channel` several times for a same peripheral, make sure you call this API the same times. + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @return + * - ESP_OK: Delete GDMA channel successfully + * - ESP_ERR_INVALID_ARG: Delete GDMA channel failed because of invalid argument + * - ESP_FAIL: Delete GDMA channel failed because of other error + */ +//go:linkname GdmaDelChannel C.gdma_del_channel +func GdmaDelChannel(dma_chan GdmaChannelHandleT) EspErrT + +/** + * @brief Get the group ID and the channel ID + * + * @note This API breaks the encapsulation of GDMA Channel Object. + * With the returned group/channel ID, you can even bypass all other GDMA driver API and access Low Level API directly. + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[out] group_id Returned group ID + * @param[out] channel_id Returned channel ID + * @return + * - ESP_OK: Get GDMA channel/group ID successfully + * - ESP_ERR_INVALID_ARG: Get GDMA channel/group ID failed because of invalid argument + * - ESP_FAIL: Get GDMA channel ID failed because of other error + */ +//go:linkname GdmaGetGroupChannelId C.gdma_get_group_channel_id +func GdmaGetGroupChannelId(dma_chan GdmaChannelHandleT, group_id *c.Int, channel_id *c.Int) EspErrT + +/** + * @brief Set GDMA event callbacks for TX channel + * @note This API will install GDMA interrupt service for the channel internally + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] cbs Group of callback functions + * @param[in] user_data User data, which will be passed to callback functions directly + * @return + * - ESP_OK: Set event callbacks successfully + * - ESP_ERR_INVALID_ARG: Set event callbacks failed because of invalid argument + * - ESP_FAIL: Set event callbacks failed because of other error + */ +//go:linkname GdmaRegisterTxEventCallbacks C.gdma_register_tx_event_callbacks +func GdmaRegisterTxEventCallbacks(dma_chan GdmaChannelHandleT, cbs *GdmaTxEventCallbacksT, user_data c.Pointer) EspErrT + +/** + * @brief Set GDMA event callbacks for RX channel + * @note This API will install GDMA interrupt service for the channel internally + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] cbs Group of callback functions + * @param[in] user_data User data, which will be passed to callback functions directly + * @return + * - ESP_OK: Set event callbacks successfully + * - ESP_ERR_INVALID_ARG: Set event callbacks failed because of invalid argument + * - ESP_FAIL: Set event callbacks failed because of other error + */ +//go:linkname GdmaRegisterRxEventCallbacks C.gdma_register_rx_event_callbacks +func GdmaRegisterRxEventCallbacks(dma_chan GdmaChannelHandleT, cbs *GdmaRxEventCallbacksT, user_data c.Pointer) EspErrT + +/** + * @brief Set DMA descriptor address and start engine + * + * @note This function is allowed to run within ISR context + * @note This function is also allowed to run when Cache is disabled, if `CONFIG_GDMA_CTRL_FUNC_IN_IRAM` is enabled + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] desc_base_addr Base address of descriptors (usually the descriptors are chained into a link or ring) + * @return + * - ESP_OK: Start DMA engine successfully + * - ESP_ERR_INVALID_ARG: Start DMA engine failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Start DMA engine failed because of invalid state, e.g. the channel is controlled by ETM, so can't start it manually + * - ESP_FAIL: Start DMA engine failed because of other error + */ +//go:linkname GdmaStart C.gdma_start +func GdmaStart(dma_chan GdmaChannelHandleT, desc_base_addr c.IntptrT) EspErrT + +/** + * @brief Stop DMA engine + * + * @note This function is allowed to run within ISR context + * @note This function is also allowed to run when Cache is disabled, if `CONFIG_GDMA_CTRL_FUNC_IN_IRAM` is enabled + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @return + * - ESP_OK: Stop DMA engine successfully + * - ESP_ERR_INVALID_ARG: Stop DMA engine failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Stop DMA engine failed because of invalid state, e.g. the channel is controlled by ETM, so can't stop it manually + * - ESP_FAIL: Stop DMA engine failed because of other error + */ +//go:linkname GdmaStop C.gdma_stop +func GdmaStop(dma_chan GdmaChannelHandleT) EspErrT + +/** + * @brief Make the appended descriptors be aware to the DMA engine + * + * @note This function is allowed to run within ISR context + * @note This function is also allowed to run when Cache is disabled, if `CONFIG_GDMA_CTRL_FUNC_IN_IRAM` is enabled + * @note This API could also resume a paused DMA engine, make sure new descriptors have been appended to the descriptor chain before calling it. + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @return + * - ESP_OK: Send append command to DMA engine successfully + * - ESP_ERR_INVALID_ARG: Send append command to DMA engine failed because of invalid argument + * - ESP_FAIL: Send append command to DMA engine failed because of other error + */ +//go:linkname GdmaAppend C.gdma_append +func GdmaAppend(dma_chan GdmaChannelHandleT) EspErrT + +/** + * @brief Reset DMA channel FIFO and internal finite state machine + * + * @note This function is allowed to run within ISR context + * @note This function is also allowed to run when Cache is disabled, if `CONFIG_GDMA_CTRL_FUNC_IN_IRAM` is enabled + * @note Resetting a DMA channel won't break the connection with the target peripheral + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @return + * - ESP_OK: DMA channel reset successfully + * - ESP_ERR_INVALID_ARG: DMA channel reset failed due to invalid arguments + * - ESP_FAIL: DMA channel reset failed due to other errors + */ +//go:linkname GdmaReset C.gdma_reset +func GdmaReset(dma_chan GdmaChannelHandleT) EspErrT + +/** + * @brief Get the mask of free M2M trigger IDs + * + * @note On some ESP targets (e.g. ESP32C3/S3), DMA trigger used for memory copy can be any of valid peripheral's trigger ID, + * which can bring conflict if the peripheral is also using the same trigger ID. This function can return the free IDs + * for memory copy, at the runtime. + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[out] mask Returned mask of free M2M trigger IDs + * @return + * - ESP_OK: Get free M2M trigger IDs successfully + * - ESP_ERR_INVALID_ARG: Get free M2M trigger IDs failed because of invalid argument + * - ESP_FAIL: Get free M2M trigger IDs failed because of other error + */ +//go:linkname GdmaGetFreeM2mTrigIdMask C.gdma_get_free_m2m_trig_id_mask +func GdmaGetFreeM2mTrigIdMask(dma_chan GdmaChannelHandleT, mask *c.Uint32T) EspErrT + +/** @cond */ +/** + * @brief Create GDMA channel (Legacy API) + * + * @param[in] config Pointer to a collection of configurations for allocating GDMA channel + * @param[out] ret_chan Returned channel handle + * @return + * - ESP_OK: Create DMA channel successfully + * - ESP_ERR_INVALID_ARG: Create DMA channel failed because of invalid argument + * - ESP_ERR_NO_MEM: Create DMA channel failed because out of memory + * - ESP_FAIL: Create DMA channel failed because of other error + */ +// llgo:link (*GdmaChannelAllocConfigT).GdmaNewChannel C.gdma_new_channel +func (recv_ *GdmaChannelAllocConfigT) GdmaNewChannel(ret_chan *GdmaChannelHandleT) EspErrT { + return 0 +} + +/** + * @brief GDMA transfer ability + * + * @note The alignment set in this structure is **not** a guarantee that gdma driver will take care of the nonalignment cases. + * Actually the GDMA driver has no knowledge about the DMA buffer (address and size) used by upper layer. + * So it's the responsibility of the **upper layer** to take care of the buffer address and size. + * + */ + +type GdmaTransferAbilityT struct { + SramTransAlign c.SizeT + PsramTransAlign c.SizeT +} + +/** + * @brief Set DMA channel transfer ability + * + * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[in] ability Transfer ability, e.g. alignment + * @return + * - ESP_OK: Set DMA channel transfer ability successfully + * - ESP_ERR_INVALID_ARG: Set DMA channel transfer ability failed because of invalid argument + * - ESP_FAIL: Set DMA channel transfer ability failed because of other error + */ +//go:linkname GdmaSetTransferAbility C.gdma_set_transfer_ability +func GdmaSetTransferAbility(dma_chan GdmaChannelHandleT, ability *GdmaTransferAbilityT) EspErrT diff --git a/esp32/gdma_channel.go b/esp32/gdma_channel.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/gdma_channel.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/gdma_hal.go b/esp32/gdma_hal.go new file mode 100644 index 00000000..eb1feb9d --- /dev/null +++ b/esp32/gdma_hal.go @@ -0,0 +1,120 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type GdmaHalContextT struct { + PrivData *GdmaHalPrivDataT + StartWithDesc c.Pointer + Stop c.Pointer + Append c.Pointer + Reset c.Pointer + SetPriority c.Pointer + ConnectPeri c.Pointer + DisconnectPeri c.Pointer + EnableBurst c.Pointer + SetBurstSize c.Pointer + SetStrategy c.Pointer + GetIntrStatusReg c.Pointer + EnableIntr c.Pointer + ClearIntr c.Pointer + ReadIntrStatus c.Pointer + GetEofDescAddr c.Pointer + EnableAccessEncryptMem c.Pointer +} + +/** + * @brief GDMA HAL configuration + */ + +type GdmaHalConfigT struct { + GroupId c.Int +} + +type GdmaHalCrcConfigT struct { + InitValue c.Uint32T + CrcBitWidth c.Uint32T + PolyHex c.Uint32T + ReverseDataMask bool +} + +/** + * @brief GDMA HAL private data + */ + +type GdmaHalPrivDataT struct { + M2mFreePeriphMask c.Uint32T +} + +// llgo:link (*GdmaHalContextT).GdmaHalDeinit C.gdma_hal_deinit +func (recv_ *GdmaHalContextT) GdmaHalDeinit() { +} + +// llgo:link (*GdmaHalContextT).GdmaHalStartWithDesc C.gdma_hal_start_with_desc +func (recv_ *GdmaHalContextT) GdmaHalStartWithDesc(chan_id c.Int, dir GdmaChannelDirectionT, desc_base_addr c.IntptrT) { +} + +// llgo:link (*GdmaHalContextT).GdmaHalStop C.gdma_hal_stop +func (recv_ *GdmaHalContextT) GdmaHalStop(chan_id c.Int, dir GdmaChannelDirectionT) { +} + +// llgo:link (*GdmaHalContextT).GdmaHalAppend C.gdma_hal_append +func (recv_ *GdmaHalContextT) GdmaHalAppend(chan_id c.Int, dir GdmaChannelDirectionT) { +} + +// llgo:link (*GdmaHalContextT).GdmaHalReset C.gdma_hal_reset +func (recv_ *GdmaHalContextT) GdmaHalReset(chan_id c.Int, dir GdmaChannelDirectionT) { +} + +// llgo:link (*GdmaHalContextT).GdmaHalSetPriority C.gdma_hal_set_priority +func (recv_ *GdmaHalContextT) GdmaHalSetPriority(chan_id c.Int, dir GdmaChannelDirectionT, priority c.Uint32T) { +} + +// llgo:link (*GdmaHalContextT).GdmaHalConnectPeri C.gdma_hal_connect_peri +func (recv_ *GdmaHalContextT) GdmaHalConnectPeri(chan_id c.Int, dir GdmaChannelDirectionT, periph GdmaTriggerPeripheralT, periph_sub_id c.Int) { +} + +// llgo:link (*GdmaHalContextT).GdmaHalDisconnectPeri C.gdma_hal_disconnect_peri +func (recv_ *GdmaHalContextT) GdmaHalDisconnectPeri(chan_id c.Int, dir GdmaChannelDirectionT) { +} + +// llgo:link (*GdmaHalContextT).GdmaHalEnableBurst C.gdma_hal_enable_burst +func (recv_ *GdmaHalContextT) GdmaHalEnableBurst(chan_id c.Int, dir GdmaChannelDirectionT, en_data_burst bool, en_desc_burst bool) { +} + +// llgo:link (*GdmaHalContextT).GdmaHalSetBurstSize C.gdma_hal_set_burst_size +func (recv_ *GdmaHalContextT) GdmaHalSetBurstSize(chan_id c.Int, dir GdmaChannelDirectionT, burst_sz c.Uint32T) { +} + +// llgo:link (*GdmaHalContextT).GdmaHalSetStrategy C.gdma_hal_set_strategy +func (recv_ *GdmaHalContextT) GdmaHalSetStrategy(chan_id c.Int, dir GdmaChannelDirectionT, en_owner_check bool, en_desc_write_back bool, eof_till_popped bool) { +} + +// llgo:link (*GdmaHalContextT).GdmaHalEnableIntr C.gdma_hal_enable_intr +func (recv_ *GdmaHalContextT) GdmaHalEnableIntr(chan_id c.Int, dir GdmaChannelDirectionT, intr_event_mask c.Uint32T, en_or_dis bool) { +} + +// llgo:link (*GdmaHalContextT).GdmaHalClearIntr C.gdma_hal_clear_intr +func (recv_ *GdmaHalContextT) GdmaHalClearIntr(chan_id c.Int, dir GdmaChannelDirectionT, intr_event_mask c.Uint32T) { +} + +// llgo:link (*GdmaHalContextT).GdmaHalGetIntrStatusReg C.gdma_hal_get_intr_status_reg +func (recv_ *GdmaHalContextT) GdmaHalGetIntrStatusReg(chan_id c.Int, dir GdmaChannelDirectionT) c.Uint32T { + return 0 +} + +// llgo:link (*GdmaHalContextT).GdmaHalReadIntrStatus C.gdma_hal_read_intr_status +func (recv_ *GdmaHalContextT) GdmaHalReadIntrStatus(chan_id c.Int, dir GdmaChannelDirectionT, raw bool) c.Uint32T { + return 0 +} + +// llgo:link (*GdmaHalContextT).GdmaHalGetEofDescAddr C.gdma_hal_get_eof_desc_addr +func (recv_ *GdmaHalContextT) GdmaHalGetEofDescAddr(chan_id c.Int, dir GdmaChannelDirectionT, is_success bool) c.Uint32T { + return 0 +} + +// llgo:link (*GdmaHalContextT).GdmaHalEnableAccessEncryptMem C.gdma_hal_enable_access_encrypt_mem +func (recv_ *GdmaHalContextT) GdmaHalEnableAccessEncryptMem(chan_id c.Int, dir GdmaChannelDirectionT, en_or_dis bool) { +} diff --git a/esp32/gdma_hal_ahb.go b/esp32/gdma_hal_ahb.go new file mode 100644 index 00000000..4ffec126 --- /dev/null +++ b/esp32/gdma_hal_ahb.go @@ -0,0 +1,73 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:link (*GdmaHalContextT).GdmaAhbHalStartWithDesc C.gdma_ahb_hal_start_with_desc +func (recv_ *GdmaHalContextT) GdmaAhbHalStartWithDesc(chan_id c.Int, dir GdmaChannelDirectionT, desc_base_addr c.IntptrT) { +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalStop C.gdma_ahb_hal_stop +func (recv_ *GdmaHalContextT) GdmaAhbHalStop(chan_id c.Int, dir GdmaChannelDirectionT) { +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalAppend C.gdma_ahb_hal_append +func (recv_ *GdmaHalContextT) GdmaAhbHalAppend(chan_id c.Int, dir GdmaChannelDirectionT) { +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalReset C.gdma_ahb_hal_reset +func (recv_ *GdmaHalContextT) GdmaAhbHalReset(chan_id c.Int, dir GdmaChannelDirectionT) { +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalSetPriority C.gdma_ahb_hal_set_priority +func (recv_ *GdmaHalContextT) GdmaAhbHalSetPriority(chan_id c.Int, dir GdmaChannelDirectionT, priority c.Uint32T) { +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalConnectPeri C.gdma_ahb_hal_connect_peri +func (recv_ *GdmaHalContextT) GdmaAhbHalConnectPeri(chan_id c.Int, dir GdmaChannelDirectionT, periph GdmaTriggerPeripheralT, periph_sub_id c.Int) { +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalDisconnectPeri C.gdma_ahb_hal_disconnect_peri +func (recv_ *GdmaHalContextT) GdmaAhbHalDisconnectPeri(chan_id c.Int, dir GdmaChannelDirectionT) { +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalEnableBurst C.gdma_ahb_hal_enable_burst +func (recv_ *GdmaHalContextT) GdmaAhbHalEnableBurst(chan_id c.Int, dir GdmaChannelDirectionT, en_data_burst bool, en_desc_burst bool) { +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalSetBurstSize C.gdma_ahb_hal_set_burst_size +func (recv_ *GdmaHalContextT) GdmaAhbHalSetBurstSize(chan_id c.Int, dir GdmaChannelDirectionT, burst_sz c.Uint32T) { +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalSetStrategy C.gdma_ahb_hal_set_strategy +func (recv_ *GdmaHalContextT) GdmaAhbHalSetStrategy(chan_id c.Int, dir GdmaChannelDirectionT, en_owner_check bool, en_desc_write_back bool, eof_till_popped bool) { +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalEnableIntr C.gdma_ahb_hal_enable_intr +func (recv_ *GdmaHalContextT) GdmaAhbHalEnableIntr(chan_id c.Int, dir GdmaChannelDirectionT, intr_event_mask c.Uint32T, en_or_dis bool) { +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalClearIntr C.gdma_ahb_hal_clear_intr +func (recv_ *GdmaHalContextT) GdmaAhbHalClearIntr(chan_id c.Int, dir GdmaChannelDirectionT, intr_event_mask c.Uint32T) { +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalReadIntrStatus C.gdma_ahb_hal_read_intr_status +func (recv_ *GdmaHalContextT) GdmaAhbHalReadIntrStatus(chan_id c.Int, dir GdmaChannelDirectionT, raw bool) c.Uint32T { + return 0 +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalGetIntrStatusReg C.gdma_ahb_hal_get_intr_status_reg +func (recv_ *GdmaHalContextT) GdmaAhbHalGetIntrStatusReg(chan_id c.Int, dir GdmaChannelDirectionT) c.Uint32T { + return 0 +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalGetEofDescAddr C.gdma_ahb_hal_get_eof_desc_addr +func (recv_ *GdmaHalContextT) GdmaAhbHalGetEofDescAddr(chan_id c.Int, dir GdmaChannelDirectionT, is_success bool) c.Uint32T { + return 0 +} + +// llgo:link (*GdmaHalContextT).GdmaAhbHalInit C.gdma_ahb_hal_init +func (recv_ *GdmaHalContextT) GdmaAhbHalInit(config *GdmaHalConfigT) { +} diff --git a/esp32/gdma_hal_axi.go b/esp32/gdma_hal_axi.go new file mode 100644 index 00000000..3ef1f939 --- /dev/null +++ b/esp32/gdma_hal_axi.go @@ -0,0 +1,73 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:link (*GdmaHalContextT).GdmaAxiHalStartWithDesc C.gdma_axi_hal_start_with_desc +func (recv_ *GdmaHalContextT) GdmaAxiHalStartWithDesc(chan_id c.Int, dir GdmaChannelDirectionT, desc_base_addr c.IntptrT) { +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalStop C.gdma_axi_hal_stop +func (recv_ *GdmaHalContextT) GdmaAxiHalStop(chan_id c.Int, dir GdmaChannelDirectionT) { +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalAppend C.gdma_axi_hal_append +func (recv_ *GdmaHalContextT) GdmaAxiHalAppend(chan_id c.Int, dir GdmaChannelDirectionT) { +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalReset C.gdma_axi_hal_reset +func (recv_ *GdmaHalContextT) GdmaAxiHalReset(chan_id c.Int, dir GdmaChannelDirectionT) { +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalSetPriority C.gdma_axi_hal_set_priority +func (recv_ *GdmaHalContextT) GdmaAxiHalSetPriority(chan_id c.Int, dir GdmaChannelDirectionT, priority c.Uint32T) { +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalConnectPeri C.gdma_axi_hal_connect_peri +func (recv_ *GdmaHalContextT) GdmaAxiHalConnectPeri(chan_id c.Int, dir GdmaChannelDirectionT, periph GdmaTriggerPeripheralT, periph_sub_id c.Int) { +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalDisconnectPeri C.gdma_axi_hal_disconnect_peri +func (recv_ *GdmaHalContextT) GdmaAxiHalDisconnectPeri(chan_id c.Int, dir GdmaChannelDirectionT) { +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalEnableBurst C.gdma_axi_hal_enable_burst +func (recv_ *GdmaHalContextT) GdmaAxiHalEnableBurst(chan_id c.Int, dir GdmaChannelDirectionT, en_data_burst bool, en_desc_burst bool) { +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalSetBurstSize C.gdma_axi_hal_set_burst_size +func (recv_ *GdmaHalContextT) GdmaAxiHalSetBurstSize(chan_id c.Int, dir GdmaChannelDirectionT, burst_sz c.Uint32T) { +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalSetStrategy C.gdma_axi_hal_set_strategy +func (recv_ *GdmaHalContextT) GdmaAxiHalSetStrategy(chan_id c.Int, dir GdmaChannelDirectionT, en_owner_check bool, en_desc_write_back bool, eof_till_popped bool) { +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalEnableIntr C.gdma_axi_hal_enable_intr +func (recv_ *GdmaHalContextT) GdmaAxiHalEnableIntr(chan_id c.Int, dir GdmaChannelDirectionT, intr_event_mask c.Uint32T, en_or_dis bool) { +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalClearIntr C.gdma_axi_hal_clear_intr +func (recv_ *GdmaHalContextT) GdmaAxiHalClearIntr(chan_id c.Int, dir GdmaChannelDirectionT, intr_event_mask c.Uint32T) { +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalReadIntrStatus C.gdma_axi_hal_read_intr_status +func (recv_ *GdmaHalContextT) GdmaAxiHalReadIntrStatus(chan_id c.Int, dir GdmaChannelDirectionT, raw bool) c.Uint32T { + return 0 +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalGetIntrStatusReg C.gdma_axi_hal_get_intr_status_reg +func (recv_ *GdmaHalContextT) GdmaAxiHalGetIntrStatusReg(chan_id c.Int, dir GdmaChannelDirectionT) c.Uint32T { + return 0 +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalGetEofDescAddr C.gdma_axi_hal_get_eof_desc_addr +func (recv_ *GdmaHalContextT) GdmaAxiHalGetEofDescAddr(chan_id c.Int, dir GdmaChannelDirectionT, is_success bool) c.Uint32T { + return 0 +} + +// llgo:link (*GdmaHalContextT).GdmaAxiHalInit C.gdma_axi_hal_init +func (recv_ *GdmaHalContextT) GdmaAxiHalInit(config *GdmaHalConfigT) { +} diff --git a/esp32/gdma_link.go b/esp32/gdma_link.go new file mode 100644 index 00000000..e0d65565 --- /dev/null +++ b/esp32/gdma_link.go @@ -0,0 +1,174 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type GdmaLinkListT struct { + Unused [8]uint8 +} +type GdmaLinkListHandleT *GdmaLinkListT + +/** + * @brief DMA link list configurations + */ + +type GdmaLinkListConfigT struct { + NumItems c.Uint32T + ItemAlignment c.SizeT + BufferAlignment c.SizeT + Flags GdmaLinkListFlags +} + +type GdmaLinkListFlags struct { + Unused [8]uint8 +} + +/** + * @brief Create a DMA link list + * + * @note This function will allocate memory for the link list. + * + * @param[in] config Link list configurations + * @param[out] ret_list Returned link list handle + * @return + * - ESP_OK: Create DMA link list successfully + * - ESP_ERR_INVALID_ARG: Create DMA link list failed because of invalid argument + * - ESP_ERR_NO_MEM: Create DMA link list failed because out of memory + * - ESP_FAIL: Create DMA link list failed because of other error + */ +// llgo:link (*GdmaLinkListConfigT).GdmaNewLinkList C.gdma_new_link_list +func (recv_ *GdmaLinkListConfigT) GdmaNewLinkList(ret_list *GdmaLinkListHandleT) EspErrT { + return 0 +} + +/** + * @brief Delete a DMA link list + * + * @param[in] list Link list handle, allocated by `gdma_new_link_list` + * @return + * - ESP_OK: Delete DMA link list successfully + * - ESP_ERR_INVALID_ARG: Delete DMA link list failed because of invalid argument + * - ESP_FAIL: Delete DMA link list failed because of other error + */ +//go:linkname GdmaDelLinkList C.gdma_del_link_list +func GdmaDelLinkList(list GdmaLinkListHandleT) EspErrT + +/** + * @brief DMA buffer mount configurations + */ + +type GdmaBufferMountConfigT struct { + Buffer c.Pointer + Length c.SizeT + Flags GdmaBufferMountFlags +} + +type GdmaBufferMountFlags struct { + Unused [8]uint8 +} + +/** + * @brief Mount one or more buffers to a given link list + * + * @note Different buffers won't be mounted to the same DMA link list item + * @note After mount to the last list item, the next list item will be the head item (wrap around) + * + * @param[in] list Link list handle, allocated by `gdma_new_link_list` + * @param[in] start_item_index Index of the first item in the link list to be mounted + * @param[in] buf_config_array Array of buffer mount configurations + * @param[in] num_buf Number of buffers to be mounted + * @param[out] end_item_index Index of the last item in the link list that has been mounted + * @return + * - ESP_OK: Mount the buffer successfully + * - ESP_ERR_INVALID_ARG: Mount the buffer failed because of invalid argument + * - ESP_FAIL: Mount the buffer failed because of other error + */ +//go:linkname GdmaLinkMountBuffers C.gdma_link_mount_buffers +func GdmaLinkMountBuffers(list GdmaLinkListHandleT, start_item_index c.Int, buf_config_array *GdmaBufferMountConfigT, num_buf c.SizeT, end_item_index *c.Int) EspErrT + +/** + * @brief Get the address of the head item in the link list + * + * @note The head address can be used to start a DMA transfer + * + * @param[in] list Link list handle, allocated by `gdma_new_link_list` + * @return + * - Address of the head item in the link list + * - NULL: Get the address failed + */ +//go:linkname GdmaLinkGetHeadAddr C.gdma_link_get_head_addr +func GdmaLinkGetHeadAddr(list GdmaLinkListHandleT) c.UintptrT + +/** + * @brief Concatenate two link lists as follows: + * + * Link A: A1 --> A2 --> A3 --> A4 + * | item_index + * +-----+ + * | + * v item_index + * Link B: B1 --> B2 --> B3 --> B4 + * + * After concatenation: + * Link A: A1 --> B3 --> B4 + * Link B: B1 --> B2 --> B3 --> B4 + * + * @param[in] first_link First link list handle, allocated by `gdma_new_link_list` + * @param[in] first_link_item_index Index of the item in the first link list (-1 means the last item) + * @param[in] second_link Second link list handle, allocated by `gdma_new_link_list` + * @param[in] second_link_item_index Index of the item in the second link list (-1 means the last item) + * @return + * - ESP_OK: Concatenate the link lists successfully + * - ESP_ERR_INVALID_ARG: Concatenate the link lists failed because of invalid argument + * - ESP_FAIL: Concatenate the link lists failed because of other error + */ +//go:linkname GdmaLinkConcat C.gdma_link_concat +func GdmaLinkConcat(first_link GdmaLinkListHandleT, first_link_item_index c.Int, second_link GdmaLinkListHandleT, second_link_item_index c.Int) EspErrT + +type GdmaLliOwnerT c.Int + +const ( + GDMA_LLI_OWNER_CPU GdmaLliOwnerT = 0 + GDMA_LLI_OWNER_DMA GdmaLliOwnerT = 1 +) + +/** + * @brief Set the ownership for a DMA link list item + * + * @param[in] list Link list handle, allocated by `gdma_new_link_list` + * @param[in] item_index Index of the link list item (-1 means the last item) + * @param[in] owner Ownership + * @return + * - ESP_OK: Set the ownership successfully + * - ESP_ERR_INVALID_ARG: Set the ownership failed because of invalid argument + * - ESP_FAIL: Set the ownership failed because of other error + */ +//go:linkname GdmaLinkSetOwner C.gdma_link_set_owner +func GdmaLinkSetOwner(list GdmaLinkListHandleT, item_index c.Int, owner GdmaLliOwnerT) EspErrT + +/** + * @brief Get the ownership of a DMA link list item + * + * @param[in] list Link list handle, allocated by `gdma_new_link_list` + * @param[in] item_index Index of the link list item (-1 means the last item) + * @param[out] owner Ownership + * @return + * - ESP_OK: Get the ownership successfully + * - ESP_ERR_INVALID_ARG: Get the ownership failed because of invalid argument + * - ESP_FAIL: Get the ownership failed because of other error + */ +//go:linkname GdmaLinkGetOwner C.gdma_link_get_owner +func GdmaLinkGetOwner(list GdmaLinkListHandleT, item_index c.Int, owner *GdmaLliOwnerT) EspErrT + +/** + * @brief Get the size of the buffer that is mounted to the link list until the eof item (inclusive) + * + * @param[in] list Link list handle, allocated by `gdma_new_link_list` + * @param[in] start_item_index Index of the first item in the link list to be calculated + * @return Size of the buffer that is mounted to the link list until the eof item (inclusive). + * If the link list is empty or invalid, return 0. + */ +//go:linkname GdmaLinkCountBufferSizeTillEof C.gdma_link_count_buffer_size_till_eof +func GdmaLinkCountBufferSizeTillEof(list GdmaLinkListHandleT, start_item_index c.Int) c.SizeT diff --git a/esp32/gdma_ll.go b/esp32/gdma_ll.go new file mode 100644 index 00000000..e3906824 --- /dev/null +++ b/esp32/gdma_ll.go @@ -0,0 +1,15 @@ +package freertos + +import _ "unsafe" + +const GDMA_LL_CHANNEL_MAX_PRIORITY = 5 +const GDMA_LL_L2FIFO_BASE_SIZE = 16 +const GDMA_LL_EXT_MEM_BK_SIZE_16B = 0 +const GDMA_LL_EXT_MEM_BK_SIZE_32B = 1 +const GDMA_LL_EXT_MEM_BK_SIZE_64B = 2 +const GDMA_LL_AHB_GROUP_START_ID = 0 +const GDMA_LL_AHB_NUM_GROUPS = 1 +const GDMA_LL_AHB_PAIRS_PER_GROUP = 5 +const GDMA_LL_AHB_DESC_ALIGNMENT = 4 +const GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE = 1 +const GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT = 1 diff --git a/esp32/gdma_periph.go b/esp32/gdma_periph.go new file mode 100644 index 00000000..bd15c147 --- /dev/null +++ b/esp32/gdma_periph.go @@ -0,0 +1,16 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type GdmaSignalConnT struct { + Groups [1]struct { + Module PeriphModuleT + Pairs [5]struct { + RxIrqId c.Int + TxIrqId c.Int + } + } +} diff --git a/esp32/gdma_reg.go b/esp32/gdma_reg.go new file mode 100644 index 00000000..14072b29 --- /dev/null +++ b/esp32/gdma_reg.go @@ -0,0 +1,1772 @@ +package freertos + +import _ "unsafe" + +const GDMA_MEM_TRANS_EN_CH0_V = 0x1 +const GDMA_MEM_TRANS_EN_CH0_S = 4 +const GDMA_IN_DATA_BURST_EN_CH0_V = 0x1 +const GDMA_IN_DATA_BURST_EN_CH0_S = 3 +const GDMA_INDSCR_BURST_EN_CH0_V = 0x1 +const GDMA_INDSCR_BURST_EN_CH0_S = 2 +const GDMA_IN_LOOP_TEST_CH0_V = 0x1 +const GDMA_IN_LOOP_TEST_CH0_S = 1 +const GDMA_IN_RST_CH0_V = 0x1 +const GDMA_IN_RST_CH0_S = 0 +const GDMA_IN_EXT_MEM_BK_SIZE_CH0 = 0x00000003 +const GDMA_IN_EXT_MEM_BK_SIZE_CH0_V = 0x3 +const GDMA_IN_EXT_MEM_BK_SIZE_CH0_S = 13 +const GDMA_IN_CHECK_OWNER_CH0_V = 0x1 +const GDMA_IN_CHECK_OWNER_CH0_S = 12 +const GDMA_DMA_INFIFO_FULL_THRS_CH0 = 0x00000FFF +const GDMA_DMA_INFIFO_FULL_THRS_CH0_V = 0xFFF +const GDMA_DMA_INFIFO_FULL_THRS_CH0_S = 0 +const GDMA_INFIFO_UDF_L3_CH0_INT_RAW_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH0_INT_RAW_S = 9 +const GDMA_INFIFO_OVF_L3_CH0_INT_RAW_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH0_INT_RAW_S = 8 +const GDMA_INFIFO_UDF_L1_CH0_INT_RAW_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH0_INT_RAW_S = 7 +const GDMA_INFIFO_OVF_L1_CH0_INT_RAW_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH0_INT_RAW_S = 6 +const GDMA_INFIFO_FULL_WM_CH0_INT_RAW_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH0_INT_RAW_S = 5 +const GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S = 4 +const GDMA_IN_DSCR_ERR_CH0_INT_RAW_V = 0x1 +const GDMA_IN_DSCR_ERR_CH0_INT_RAW_S = 3 +const GDMA_IN_ERR_EOF_CH0_INT_RAW_V = 0x1 +const GDMA_IN_ERR_EOF_CH0_INT_RAW_S = 2 +const GDMA_IN_SUC_EOF_CH0_INT_RAW_V = 0x1 +const GDMA_IN_SUC_EOF_CH0_INT_RAW_S = 1 +const GDMA_IN_DONE_CH0_INT_RAW_V = 0x1 +const GDMA_IN_DONE_CH0_INT_RAW_S = 0 +const GDMA_INFIFO_UDF_L3_CH0_INT_ST_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH0_INT_ST_S = 9 +const GDMA_INFIFO_OVF_L3_CH0_INT_ST_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH0_INT_ST_S = 8 +const GDMA_INFIFO_UDF_L1_CH0_INT_ST_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH0_INT_ST_S = 7 +const GDMA_INFIFO_OVF_L1_CH0_INT_ST_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH0_INT_ST_S = 6 +const GDMA_INFIFO_FULL_WM_CH0_INT_ST_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH0_INT_ST_S = 5 +const GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S = 4 +const GDMA_IN_DSCR_ERR_CH0_INT_ST_V = 0x1 +const GDMA_IN_DSCR_ERR_CH0_INT_ST_S = 3 +const GDMA_IN_ERR_EOF_CH0_INT_ST_V = 0x1 +const GDMA_IN_ERR_EOF_CH0_INT_ST_S = 2 +const GDMA_IN_SUC_EOF_CH0_INT_ST_V = 0x1 +const GDMA_IN_SUC_EOF_CH0_INT_ST_S = 1 +const GDMA_IN_DONE_CH0_INT_ST_V = 0x1 +const GDMA_IN_DONE_CH0_INT_ST_S = 0 +const GDMA_INFIFO_UDF_L3_CH0_INT_ENA_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH0_INT_ENA_S = 9 +const GDMA_INFIFO_OVF_L3_CH0_INT_ENA_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH0_INT_ENA_S = 8 +const GDMA_INFIFO_UDF_L1_CH0_INT_ENA_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH0_INT_ENA_S = 7 +const GDMA_INFIFO_OVF_L1_CH0_INT_ENA_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH0_INT_ENA_S = 6 +const GDMA_INFIFO_FULL_WM_CH0_INT_ENA_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH0_INT_ENA_S = 5 +const GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S = 4 +const GDMA_IN_DSCR_ERR_CH0_INT_ENA_V = 0x1 +const GDMA_IN_DSCR_ERR_CH0_INT_ENA_S = 3 +const GDMA_IN_ERR_EOF_CH0_INT_ENA_V = 0x1 +const GDMA_IN_ERR_EOF_CH0_INT_ENA_S = 2 +const GDMA_IN_SUC_EOF_CH0_INT_ENA_V = 0x1 +const GDMA_IN_SUC_EOF_CH0_INT_ENA_S = 1 +const GDMA_IN_DONE_CH0_INT_ENA_V = 0x1 +const GDMA_IN_DONE_CH0_INT_ENA_S = 0 +const GDMA_INFIFO_UDF_L3_CH0_INT_CLR_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH0_INT_CLR_S = 9 +const GDMA_INFIFO_OVF_L3_CH0_INT_CLR_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH0_INT_CLR_S = 8 +const GDMA_INFIFO_UDF_L1_CH0_INT_CLR_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH0_INT_CLR_S = 7 +const GDMA_INFIFO_OVF_L1_CH0_INT_CLR_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH0_INT_CLR_S = 6 +const GDMA_DMA_INFIFO_FULL_WM_CH0_INT_CLR_V = 0x1 +const GDMA_DMA_INFIFO_FULL_WM_CH0_INT_CLR_S = 5 +const GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S = 4 +const GDMA_IN_DSCR_ERR_CH0_INT_CLR_V = 0x1 +const GDMA_IN_DSCR_ERR_CH0_INT_CLR_S = 3 +const GDMA_IN_ERR_EOF_CH0_INT_CLR_V = 0x1 +const GDMA_IN_ERR_EOF_CH0_INT_CLR_S = 2 +const GDMA_IN_SUC_EOF_CH0_INT_CLR_V = 0x1 +const GDMA_IN_SUC_EOF_CH0_INT_CLR_S = 1 +const GDMA_IN_DONE_CH0_INT_CLR_V = 0x1 +const GDMA_IN_DONE_CH0_INT_CLR_S = 0 +const GDMA_IN_BUF_HUNGRY_CH0_V = 0x1 +const GDMA_IN_BUF_HUNGRY_CH0_S = 28 +const GDMA_IN_REMAIN_UNDER_4B_L3_CH0_V = 0x1 +const GDMA_IN_REMAIN_UNDER_4B_L3_CH0_S = 27 +const GDMA_IN_REMAIN_UNDER_3B_L3_CH0_V = 0x1 +const GDMA_IN_REMAIN_UNDER_3B_L3_CH0_S = 26 +const GDMA_IN_REMAIN_UNDER_2B_L3_CH0_V = 0x1 +const GDMA_IN_REMAIN_UNDER_2B_L3_CH0_S = 25 +const GDMA_IN_REMAIN_UNDER_1B_L3_CH0_V = 0x1 +const GDMA_IN_REMAIN_UNDER_1B_L3_CH0_S = 24 +const GDMA_INFIFO_CNT_L3_CH0 = 0x0000001F +const GDMA_INFIFO_CNT_L3_CH0_V = 0x1F +const GDMA_INFIFO_CNT_L3_CH0_S = 19 +const GDMA_INFIFO_CNT_L2_CH0 = 0x0000007F +const GDMA_INFIFO_CNT_L2_CH0_V = 0x7F +const GDMA_INFIFO_CNT_L2_CH0_S = 12 +const GDMA_INFIFO_CNT_L1_CH0 = 0x0000003F +const GDMA_INFIFO_CNT_L1_CH0_V = 0x3F +const GDMA_INFIFO_CNT_L1_CH0_S = 6 +const GDMA_INFIFO_EMPTY_L3_CH0_V = 0x1 +const GDMA_INFIFO_EMPTY_L3_CH0_S = 5 +const GDMA_INFIFO_FULL_L3_CH0_V = 0x1 +const GDMA_INFIFO_FULL_L3_CH0_S = 4 +const GDMA_INFIFO_EMPTY_L2_CH0_V = 0x1 +const GDMA_INFIFO_EMPTY_L2_CH0_S = 3 +const GDMA_INFIFO_FULL_L2_CH0_V = 0x1 +const GDMA_INFIFO_FULL_L2_CH0_S = 2 +const GDMA_INFIFO_EMPTY_L1_CH0_V = 0x1 +const GDMA_INFIFO_EMPTY_L1_CH0_S = 1 +const GDMA_INFIFO_FULL_L1_CH0_V = 0x1 +const GDMA_INFIFO_FULL_L1_CH0_S = 0 +const GDMA_INFIFO_POP_CH0_V = 0x1 +const GDMA_INFIFO_POP_CH0_S = 12 +const GDMA_INFIFO_RDATA_CH0 = 0x00000FFF +const GDMA_INFIFO_RDATA_CH0_V = 0xFFF +const GDMA_INFIFO_RDATA_CH0_S = 0 +const GDMA_INLINK_PARK_CH0_V = 0x1 +const GDMA_INLINK_PARK_CH0_S = 24 +const GDMA_INLINK_RESTART_CH0_V = 0x1 +const GDMA_INLINK_RESTART_CH0_S = 23 +const GDMA_INLINK_START_CH0_V = 0x1 +const GDMA_INLINK_START_CH0_S = 22 +const GDMA_INLINK_STOP_CH0_V = 0x1 +const GDMA_INLINK_STOP_CH0_S = 21 +const GDMA_INLINK_AUTO_RET_CH0_V = 0x1 +const GDMA_INLINK_AUTO_RET_CH0_S = 20 +const GDMA_INLINK_ADDR_CH0 = 0x000FFFFF +const GDMA_INLINK_ADDR_CH0_V = 0xFFFFF +const GDMA_INLINK_ADDR_CH0_S = 0 +const GDMA_IN_STATE_CH0 = 0x00000007 +const GDMA_IN_STATE_CH0_V = 0x7 +const GDMA_IN_STATE_CH0_S = 20 +const GDMA_IN_DSCR_STATE_CH0 = 0x00000003 +const GDMA_IN_DSCR_STATE_CH0_V = 0x3 +const GDMA_IN_DSCR_STATE_CH0_S = 18 +const GDMA_INLINK_DSCR_ADDR_CH0 = 0x0003FFFF +const GDMA_INLINK_DSCR_ADDR_CH0_V = 0x3FFFF +const GDMA_INLINK_DSCR_ADDR_CH0_S = 0 +const GDMA_IN_SUC_EOF_DES_ADDR_CH0 = 0xFFFFFFFF +const GDMA_IN_SUC_EOF_DES_ADDR_CH0_V = 0xFFFFFFFF +const GDMA_IN_SUC_EOF_DES_ADDR_CH0_S = 0 +const GDMA_IN_ERR_EOF_DES_ADDR_CH0 = 0xFFFFFFFF +const GDMA_IN_ERR_EOF_DES_ADDR_CH0_V = 0xFFFFFFFF +const GDMA_IN_ERR_EOF_DES_ADDR_CH0_S = 0 +const GDMA_INLINK_DSCR_CH0 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_CH0_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_CH0_S = 0 +const GDMA_INLINK_DSCR_BF0_CH0 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF0_CH0_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF0_CH0_S = 0 +const GDMA_INLINK_DSCR_BF1_CH0 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF1_CH0_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF1_CH0_S = 0 +const GDMA_RX_WEIGHT_CH0 = 0x0000000F +const GDMA_RX_WEIGHT_CH0_V = 0xF +const GDMA_RX_WEIGHT_CH0_S = 8 +const GDMA_RX_PRI_CH0 = 0x0000000F +const GDMA_RX_PRI_CH0_V = 0xF +const GDMA_RX_PRI_CH0_S = 0 +const GDMA_PERI_IN_SEL_CH0 = 0x0000003F +const GDMA_PERI_IN_SEL_CH0_V = 0x3F +const GDMA_PERI_IN_SEL_CH0_S = 0 +const GDMA_OUT_DATA_BURST_EN_CH0_V = 0x1 +const GDMA_OUT_DATA_BURST_EN_CH0_S = 5 +const GDMA_OUTDSCR_BURST_EN_CH0_V = 0x1 +const GDMA_OUTDSCR_BURST_EN_CH0_S = 4 +const GDMA_OUT_EOF_MODE_CH0_V = 0x1 +const GDMA_OUT_EOF_MODE_CH0_S = 3 +const GDMA_OUT_AUTO_WRBACK_CH0_V = 0x1 +const GDMA_OUT_AUTO_WRBACK_CH0_S = 2 +const GDMA_OUT_LOOP_TEST_CH0_V = 0x1 +const GDMA_OUT_LOOP_TEST_CH0_S = 1 +const GDMA_OUT_RST_CH0_V = 0x1 +const GDMA_OUT_RST_CH0_S = 0 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH0 = 0x00000003 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH0_V = 0x3 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH0_S = 13 +const GDMA_OUT_CHECK_OWNER_CH0_V = 0x1 +const GDMA_OUT_CHECK_OWNER_CH0_S = 12 +const GDMA_OUTFIFO_UDF_L3_CH0_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH0_INT_RAW_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH0_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH0_INT_RAW_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW_S = 4 +const GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S = 3 +const GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S = 2 +const GDMA_OUT_EOF_CH0_INT_RAW_V = 0x1 +const GDMA_OUT_EOF_CH0_INT_RAW_S = 1 +const GDMA_OUT_DONE_CH0_INT_RAW_V = 0x1 +const GDMA_OUT_DONE_CH0_INT_RAW_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH0_INT_ST_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH0_INT_ST_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH0_INT_ST_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH0_INT_ST_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH0_INT_ST_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH0_INT_ST_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH0_INT_ST_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH0_INT_ST_S = 4 +const GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S = 3 +const GDMA_OUT_DSCR_ERR_CH0_INT_ST_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH0_INT_ST_S = 2 +const GDMA_OUT_EOF_CH0_INT_ST_V = 0x1 +const GDMA_OUT_EOF_CH0_INT_ST_S = 1 +const GDMA_OUT_DONE_CH0_INT_ST_V = 0x1 +const GDMA_OUT_DONE_CH0_INT_ST_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH0_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH0_INT_ENA_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH0_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH0_INT_ENA_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH0_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH0_INT_ENA_S = 4 +const GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S = 3 +const GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S = 2 +const GDMA_OUT_EOF_CH0_INT_ENA_V = 0x1 +const GDMA_OUT_EOF_CH0_INT_ENA_S = 1 +const GDMA_OUT_DONE_CH0_INT_ENA_V = 0x1 +const GDMA_OUT_DONE_CH0_INT_ENA_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH0_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH0_INT_CLR_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH0_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH0_INT_CLR_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR_S = 4 +const GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S = 3 +const GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S = 2 +const GDMA_OUT_EOF_CH0_INT_CLR_V = 0x1 +const GDMA_OUT_EOF_CH0_INT_CLR_S = 1 +const GDMA_OUT_DONE_CH0_INT_CLR_V = 0x1 +const GDMA_OUT_DONE_CH0_INT_CLR_S = 0 +const GDMA_OUT_REMAIN_UNDER_4B_L3_CH0_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_4B_L3_CH0_S = 26 +const GDMA_OUT_REMAIN_UNDER_3B_L3_CH0_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_3B_L3_CH0_S = 25 +const GDMA_OUT_REMAIN_UNDER_2B_L3_CH0_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_2B_L3_CH0_S = 24 +const GDMA_OUT_REMAIN_UNDER_1B_L3_CH0_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_1B_L3_CH0_S = 23 +const GDMA_OUTFIFO_CNT_L3_CH0 = 0x0000001F +const GDMA_OUTFIFO_CNT_L3_CH0_V = 0x1F +const GDMA_OUTFIFO_CNT_L3_CH0_S = 18 +const GDMA_OUTFIFO_CNT_L2_CH0 = 0x0000007F +const GDMA_OUTFIFO_CNT_L2_CH0_V = 0x7F +const GDMA_OUTFIFO_CNT_L2_CH0_S = 11 +const GDMA_OUTFIFO_CNT_L1_CH0 = 0x0000001F +const GDMA_OUTFIFO_CNT_L1_CH0_V = 0x1F +const GDMA_OUTFIFO_CNT_L1_CH0_S = 6 +const GDMA_OUTFIFO_EMPTY_L3_CH0_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L3_CH0_S = 5 +const GDMA_OUTFIFO_FULL_L3_CH0_V = 0x1 +const GDMA_OUTFIFO_FULL_L3_CH0_S = 4 +const GDMA_OUTFIFO_EMPTY_L2_CH0_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L2_CH0_S = 3 +const GDMA_OUTFIFO_FULL_L2_CH0_V = 0x1 +const GDMA_OUTFIFO_FULL_L2_CH0_S = 2 +const GDMA_OUTFIFO_EMPTY_L1_CH0_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L1_CH0_S = 1 +const GDMA_OUTFIFO_FULL_L1_CH0_V = 0x1 +const GDMA_OUTFIFO_FULL_L1_CH0_S = 0 +const GDMA_OUTFIFO_PUSH_CH0_V = 0x1 +const GDMA_OUTFIFO_PUSH_CH0_S = 9 +const GDMA_OUTFIFO_WDATA_CH0 = 0x000001FF +const GDMA_OUTFIFO_WDATA_CH0_V = 0x1FF +const GDMA_OUTFIFO_WDATA_CH0_S = 0 +const GDMA_OUTLINK_PARK_CH0_V = 0x1 +const GDMA_OUTLINK_PARK_CH0_S = 23 +const GDMA_OUTLINK_RESTART_CH0_V = 0x1 +const GDMA_OUTLINK_RESTART_CH0_S = 22 +const GDMA_OUTLINK_START_CH0_V = 0x1 +const GDMA_OUTLINK_START_CH0_S = 21 +const GDMA_OUTLINK_STOP_CH0_V = 0x1 +const GDMA_OUTLINK_STOP_CH0_S = 20 +const GDMA_OUTLINK_ADDR_CH0 = 0x000FFFFF +const GDMA_OUTLINK_ADDR_CH0_V = 0xFFFFF +const GDMA_OUTLINK_ADDR_CH0_S = 0 +const GDMA_OUT_STATE_CH0 = 0x00000007 +const GDMA_OUT_STATE_CH0_V = 0x7 +const GDMA_OUT_STATE_CH0_S = 20 +const GDMA_OUT_DSCR_STATE_CH0 = 0x00000003 +const GDMA_OUT_DSCR_STATE_CH0_V = 0x3 +const GDMA_OUT_DSCR_STATE_CH0_S = 18 +const GDMA_OUTLINK_DSCR_ADDR_CH0 = 0x0003FFFF +const GDMA_OUTLINK_DSCR_ADDR_CH0_V = 0x3FFFF +const GDMA_OUTLINK_DSCR_ADDR_CH0_S = 0 +const GDMA_OUT_EOF_DES_ADDR_CH0 = 0xFFFFFFFF +const GDMA_OUT_EOF_DES_ADDR_CH0_V = 0xFFFFFFFF +const GDMA_OUT_EOF_DES_ADDR_CH0_S = 0 +const GDMA_OUT_EOF_BFR_DES_ADDR_CH0 = 0xFFFFFFFF +const GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V = 0xFFFFFFFF +const GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S = 0 +const GDMA_OUTLINK_DSCR_CH0 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_CH0_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_CH0_S = 0 +const GDMA_OUTLINK_DSCR_BF0_CH0 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF0_CH0_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF0_CH0_S = 0 +const GDMA_OUTLINK_DSCR_BF1_CH0 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF1_CH0_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF1_CH0_S = 0 +const GDMA_TX_WEIGHT_CH0 = 0x0000000F +const GDMA_TX_WEIGHT_CH0_V = 0xF +const GDMA_TX_WEIGHT_CH0_S = 8 +const GDMA_TX_PRI_CH0 = 0x0000000F +const GDMA_TX_PRI_CH0_V = 0xF +const GDMA_TX_PRI_CH0_S = 0 +const GDMA_PERI_OUT_SEL_CH0 = 0x0000003F +const GDMA_PERI_OUT_SEL_CH0_V = 0x3F +const GDMA_PERI_OUT_SEL_CH0_S = 0 +const GDMA_MEM_TRANS_EN_CH1_V = 0x1 +const GDMA_MEM_TRANS_EN_CH1_S = 4 +const GDMA_IN_DATA_BURST_EN_CH1_V = 0x1 +const GDMA_IN_DATA_BURST_EN_CH1_S = 3 +const GDMA_INDSCR_BURST_EN_CH1_V = 0x1 +const GDMA_INDSCR_BURST_EN_CH1_S = 2 +const GDMA_IN_LOOP_TEST_CH1_V = 0x1 +const GDMA_IN_LOOP_TEST_CH1_S = 1 +const GDMA_IN_RST_CH1_V = 0x1 +const GDMA_IN_RST_CH1_S = 0 +const GDMA_IN_EXT_MEM_BK_SIZE_CH1 = 0x00000003 +const GDMA_IN_EXT_MEM_BK_SIZE_CH1_V = 0x3 +const GDMA_IN_EXT_MEM_BK_SIZE_CH1_S = 13 +const GDMA_IN_CHECK_OWNER_CH1_V = 0x1 +const GDMA_IN_CHECK_OWNER_CH1_S = 12 +const GDMA_DMA_INFIFO_FULL_THRS_CH1 = 0x00000FFF +const GDMA_DMA_INFIFO_FULL_THRS_CH1_V = 0xFFF +const GDMA_DMA_INFIFO_FULL_THRS_CH1_S = 0 +const GDMA_INFIFO_UDF_L3_CH1_INT_RAW_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH1_INT_RAW_S = 9 +const GDMA_INFIFO_OVF_L3_CH1_INT_RAW_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH1_INT_RAW_S = 8 +const GDMA_INFIFO_UDF_L1_CH1_INT_RAW_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH1_INT_RAW_S = 7 +const GDMA_INFIFO_OVF_L1_CH1_INT_RAW_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH1_INT_RAW_S = 6 +const GDMA_INFIFO_FULL_WM_CH1_INT_RAW_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH1_INT_RAW_S = 5 +const GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S = 4 +const GDMA_IN_DSCR_ERR_CH1_INT_RAW_V = 0x1 +const GDMA_IN_DSCR_ERR_CH1_INT_RAW_S = 3 +const GDMA_IN_ERR_EOF_CH1_INT_RAW_V = 0x1 +const GDMA_IN_ERR_EOF_CH1_INT_RAW_S = 2 +const GDMA_IN_SUC_EOF_CH1_INT_RAW_V = 0x1 +const GDMA_IN_SUC_EOF_CH1_INT_RAW_S = 1 +const GDMA_IN_DONE_CH1_INT_RAW_V = 0x1 +const GDMA_IN_DONE_CH1_INT_RAW_S = 0 +const GDMA_INFIFO_UDF_L3_CH1_INT_ST_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH1_INT_ST_S = 9 +const GDMA_INFIFO_OVF_L3_CH1_INT_ST_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH1_INT_ST_S = 8 +const GDMA_INFIFO_UDF_L1_CH1_INT_ST_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH1_INT_ST_S = 7 +const GDMA_INFIFO_OVF_L1_CH1_INT_ST_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH1_INT_ST_S = 6 +const GDMA_INFIFO_FULL_WM_CH1_INT_ST_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH1_INT_ST_S = 5 +const GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S = 4 +const GDMA_IN_DSCR_ERR_CH1_INT_ST_V = 0x1 +const GDMA_IN_DSCR_ERR_CH1_INT_ST_S = 3 +const GDMA_IN_ERR_EOF_CH1_INT_ST_V = 0x1 +const GDMA_IN_ERR_EOF_CH1_INT_ST_S = 2 +const GDMA_IN_SUC_EOF_CH1_INT_ST_V = 0x1 +const GDMA_IN_SUC_EOF_CH1_INT_ST_S = 1 +const GDMA_IN_DONE_CH1_INT_ST_V = 0x1 +const GDMA_IN_DONE_CH1_INT_ST_S = 0 +const GDMA_INFIFO_UDF_L3_CH1_INT_ENA_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH1_INT_ENA_S = 9 +const GDMA_INFIFO_OVF_L3_CH1_INT_ENA_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH1_INT_ENA_S = 8 +const GDMA_INFIFO_UDF_L1_CH1_INT_ENA_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH1_INT_ENA_S = 7 +const GDMA_INFIFO_OVF_L1_CH1_INT_ENA_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH1_INT_ENA_S = 6 +const GDMA_INFIFO_FULL_WM_CH1_INT_ENA_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH1_INT_ENA_S = 5 +const GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S = 4 +const GDMA_IN_DSCR_ERR_CH1_INT_ENA_V = 0x1 +const GDMA_IN_DSCR_ERR_CH1_INT_ENA_S = 3 +const GDMA_IN_ERR_EOF_CH1_INT_ENA_V = 0x1 +const GDMA_IN_ERR_EOF_CH1_INT_ENA_S = 2 +const GDMA_IN_SUC_EOF_CH1_INT_ENA_V = 0x1 +const GDMA_IN_SUC_EOF_CH1_INT_ENA_S = 1 +const GDMA_IN_DONE_CH1_INT_ENA_V = 0x1 +const GDMA_IN_DONE_CH1_INT_ENA_S = 0 +const GDMA_INFIFO_UDF_L3_CH1_INT_CLR_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH1_INT_CLR_S = 9 +const GDMA_INFIFO_OVF_L3_CH1_INT_CLR_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH1_INT_CLR_S = 8 +const GDMA_INFIFO_UDF_L1_CH1_INT_CLR_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH1_INT_CLR_S = 7 +const GDMA_INFIFO_OVF_L1_CH1_INT_CLR_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH1_INT_CLR_S = 6 +const GDMA_DMA_INFIFO_FULL_WM_CH1_INT_CLR_V = 0x1 +const GDMA_DMA_INFIFO_FULL_WM_CH1_INT_CLR_S = 5 +const GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S = 4 +const GDMA_IN_DSCR_ERR_CH1_INT_CLR_V = 0x1 +const GDMA_IN_DSCR_ERR_CH1_INT_CLR_S = 3 +const GDMA_IN_ERR_EOF_CH1_INT_CLR_V = 0x1 +const GDMA_IN_ERR_EOF_CH1_INT_CLR_S = 2 +const GDMA_IN_SUC_EOF_CH1_INT_CLR_V = 0x1 +const GDMA_IN_SUC_EOF_CH1_INT_CLR_S = 1 +const GDMA_IN_DONE_CH1_INT_CLR_V = 0x1 +const GDMA_IN_DONE_CH1_INT_CLR_S = 0 +const GDMA_IN_BUF_HUNGRY_CH1_V = 0x1 +const GDMA_IN_BUF_HUNGRY_CH1_S = 28 +const GDMA_IN_REMAIN_UNDER_4B_L3_CH1_V = 0x1 +const GDMA_IN_REMAIN_UNDER_4B_L3_CH1_S = 27 +const GDMA_IN_REMAIN_UNDER_3B_L3_CH1_V = 0x1 +const GDMA_IN_REMAIN_UNDER_3B_L3_CH1_S = 26 +const GDMA_IN_REMAIN_UNDER_2B_L3_CH1_V = 0x1 +const GDMA_IN_REMAIN_UNDER_2B_L3_CH1_S = 25 +const GDMA_IN_REMAIN_UNDER_1B_L3_CH1_V = 0x1 +const GDMA_IN_REMAIN_UNDER_1B_L3_CH1_S = 24 +const GDMA_INFIFO_CNT_L3_CH1 = 0x0000001F +const GDMA_INFIFO_CNT_L3_CH1_V = 0x1F +const GDMA_INFIFO_CNT_L3_CH1_S = 19 +const GDMA_INFIFO_CNT_L2_CH1 = 0x0000007F +const GDMA_INFIFO_CNT_L2_CH1_V = 0x7F +const GDMA_INFIFO_CNT_L2_CH1_S = 12 +const GDMA_INFIFO_CNT_L1_CH1 = 0x0000003F +const GDMA_INFIFO_CNT_L1_CH1_V = 0x3F +const GDMA_INFIFO_CNT_L1_CH1_S = 6 +const GDMA_INFIFO_EMPTY_L3_CH1_V = 0x1 +const GDMA_INFIFO_EMPTY_L3_CH1_S = 5 +const GDMA_INFIFO_FULL_L3_CH1_V = 0x1 +const GDMA_INFIFO_FULL_L3_CH1_S = 4 +const GDMA_INFIFO_EMPTY_L2_CH1_V = 0x1 +const GDMA_INFIFO_EMPTY_L2_CH1_S = 3 +const GDMA_INFIFO_FULL_L2_CH1_V = 0x1 +const GDMA_INFIFO_FULL_L2_CH1_S = 2 +const GDMA_INFIFO_EMPTY_L1_CH1_V = 0x1 +const GDMA_INFIFO_EMPTY_L1_CH1_S = 1 +const GDMA_INFIFO_FULL_L1_CH1_V = 0x1 +const GDMA_INFIFO_FULL_L1_CH1_S = 0 +const GDMA_INFIFO_POP_CH1_V = 0x1 +const GDMA_INFIFO_POP_CH1_S = 12 +const GDMA_INFIFO_RDATA_CH1 = 0x00000FFF +const GDMA_INFIFO_RDATA_CH1_V = 0xFFF +const GDMA_INFIFO_RDATA_CH1_S = 0 +const GDMA_INLINK_PARK_CH1_V = 0x1 +const GDMA_INLINK_PARK_CH1_S = 24 +const GDMA_INLINK_RESTART_CH1_V = 0x1 +const GDMA_INLINK_RESTART_CH1_S = 23 +const GDMA_INLINK_START_CH1_V = 0x1 +const GDMA_INLINK_START_CH1_S = 22 +const GDMA_INLINK_STOP_CH1_V = 0x1 +const GDMA_INLINK_STOP_CH1_S = 21 +const GDMA_INLINK_AUTO_RET_CH1_V = 0x1 +const GDMA_INLINK_AUTO_RET_CH1_S = 20 +const GDMA_INLINK_ADDR_CH1 = 0x000FFFFF +const GDMA_INLINK_ADDR_CH1_V = 0xFFFFF +const GDMA_INLINK_ADDR_CH1_S = 0 +const GDMA_IN_STATE_CH1 = 0x00000007 +const GDMA_IN_STATE_CH1_V = 0x7 +const GDMA_IN_STATE_CH1_S = 20 +const GDMA_IN_DSCR_STATE_CH1 = 0x00000003 +const GDMA_IN_DSCR_STATE_CH1_V = 0x3 +const GDMA_IN_DSCR_STATE_CH1_S = 18 +const GDMA_INLINK_DSCR_ADDR_CH1 = 0x0003FFFF +const GDMA_INLINK_DSCR_ADDR_CH1_V = 0x3FFFF +const GDMA_INLINK_DSCR_ADDR_CH1_S = 0 +const GDMA_IN_SUC_EOF_DES_ADDR_CH1 = 0xFFFFFFFF +const GDMA_IN_SUC_EOF_DES_ADDR_CH1_V = 0xFFFFFFFF +const GDMA_IN_SUC_EOF_DES_ADDR_CH1_S = 0 +const GDMA_IN_ERR_EOF_DES_ADDR_CH1 = 0xFFFFFFFF +const GDMA_IN_ERR_EOF_DES_ADDR_CH1_V = 0xFFFFFFFF +const GDMA_IN_ERR_EOF_DES_ADDR_CH1_S = 0 +const GDMA_INLINK_DSCR_CH1 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_CH1_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_CH1_S = 0 +const GDMA_INLINK_DSCR_BF0_CH1 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF0_CH1_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF0_CH1_S = 0 +const GDMA_INLINK_DSCR_BF1_CH1 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF1_CH1_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF1_CH1_S = 0 +const GDMA_RX_WEIGHT_CH1 = 0x0000000F +const GDMA_RX_WEIGHT_CH1_V = 0xF +const GDMA_RX_WEIGHT_CH1_S = 8 +const GDMA_RX_PRI_CH1 = 0x0000000F +const GDMA_RX_PRI_CH1_V = 0xF +const GDMA_RX_PRI_CH1_S = 0 +const GDMA_PERI_IN_SEL_CH1 = 0x0000003F +const GDMA_PERI_IN_SEL_CH1_V = 0x3F +const GDMA_PERI_IN_SEL_CH1_S = 0 +const GDMA_OUT_DATA_BURST_EN_CH1_V = 0x1 +const GDMA_OUT_DATA_BURST_EN_CH1_S = 5 +const GDMA_OUTDSCR_BURST_EN_CH1_V = 0x1 +const GDMA_OUTDSCR_BURST_EN_CH1_S = 4 +const GDMA_OUT_EOF_MODE_CH1_V = 0x1 +const GDMA_OUT_EOF_MODE_CH1_S = 3 +const GDMA_OUT_AUTO_WRBACK_CH1_V = 0x1 +const GDMA_OUT_AUTO_WRBACK_CH1_S = 2 +const GDMA_OUT_LOOP_TEST_CH1_V = 0x1 +const GDMA_OUT_LOOP_TEST_CH1_S = 1 +const GDMA_OUT_RST_CH1_V = 0x1 +const GDMA_OUT_RST_CH1_S = 0 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH1 = 0x00000003 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH1_V = 0x3 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH1_S = 13 +const GDMA_OUT_CHECK_OWNER_CH1_V = 0x1 +const GDMA_OUT_CHECK_OWNER_CH1_S = 12 +const GDMA_OUTFIFO_UDF_L3_CH1_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH1_INT_RAW_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH1_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH1_INT_RAW_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW_S = 4 +const GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S = 3 +const GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S = 2 +const GDMA_OUT_EOF_CH1_INT_RAW_V = 0x1 +const GDMA_OUT_EOF_CH1_INT_RAW_S = 1 +const GDMA_OUT_DONE_CH1_INT_RAW_V = 0x1 +const GDMA_OUT_DONE_CH1_INT_RAW_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH1_INT_ST_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH1_INT_ST_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH1_INT_ST_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH1_INT_ST_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH1_INT_ST_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH1_INT_ST_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH1_INT_ST_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH1_INT_ST_S = 4 +const GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S = 3 +const GDMA_OUT_DSCR_ERR_CH1_INT_ST_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH1_INT_ST_S = 2 +const GDMA_OUT_EOF_CH1_INT_ST_V = 0x1 +const GDMA_OUT_EOF_CH1_INT_ST_S = 1 +const GDMA_OUT_DONE_CH1_INT_ST_V = 0x1 +const GDMA_OUT_DONE_CH1_INT_ST_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH1_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH1_INT_ENA_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH1_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH1_INT_ENA_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH1_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH1_INT_ENA_S = 4 +const GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S = 3 +const GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S = 2 +const GDMA_OUT_EOF_CH1_INT_ENA_V = 0x1 +const GDMA_OUT_EOF_CH1_INT_ENA_S = 1 +const GDMA_OUT_DONE_CH1_INT_ENA_V = 0x1 +const GDMA_OUT_DONE_CH1_INT_ENA_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH1_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH1_INT_CLR_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH1_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH1_INT_CLR_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR_S = 4 +const GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S = 3 +const GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S = 2 +const GDMA_OUT_EOF_CH1_INT_CLR_V = 0x1 +const GDMA_OUT_EOF_CH1_INT_CLR_S = 1 +const GDMA_OUT_DONE_CH1_INT_CLR_V = 0x1 +const GDMA_OUT_DONE_CH1_INT_CLR_S = 0 +const GDMA_OUT_REMAIN_UNDER_4B_L3_CH1_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_4B_L3_CH1_S = 26 +const GDMA_OUT_REMAIN_UNDER_3B_L3_CH1_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_3B_L3_CH1_S = 25 +const GDMA_OUT_REMAIN_UNDER_2B_L3_CH1_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_2B_L3_CH1_S = 24 +const GDMA_OUT_REMAIN_UNDER_1B_L3_CH1_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_1B_L3_CH1_S = 23 +const GDMA_OUTFIFO_CNT_L3_CH1 = 0x0000001F +const GDMA_OUTFIFO_CNT_L3_CH1_V = 0x1F +const GDMA_OUTFIFO_CNT_L3_CH1_S = 18 +const GDMA_OUTFIFO_CNT_L2_CH1 = 0x0000007F +const GDMA_OUTFIFO_CNT_L2_CH1_V = 0x7F +const GDMA_OUTFIFO_CNT_L2_CH1_S = 11 +const GDMA_OUTFIFO_CNT_L1_CH1 = 0x0000001F +const GDMA_OUTFIFO_CNT_L1_CH1_V = 0x1F +const GDMA_OUTFIFO_CNT_L1_CH1_S = 6 +const GDMA_OUTFIFO_EMPTY_L3_CH1_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L3_CH1_S = 5 +const GDMA_OUTFIFO_FULL_L3_CH1_V = 0x1 +const GDMA_OUTFIFO_FULL_L3_CH1_S = 4 +const GDMA_OUTFIFO_EMPTY_L2_CH1_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L2_CH1_S = 3 +const GDMA_OUTFIFO_FULL_L2_CH1_V = 0x1 +const GDMA_OUTFIFO_FULL_L2_CH1_S = 2 +const GDMA_OUTFIFO_EMPTY_L1_CH1_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L1_CH1_S = 1 +const GDMA_OUTFIFO_FULL_L1_CH1_V = 0x1 +const GDMA_OUTFIFO_FULL_L1_CH1_S = 0 +const GDMA_OUTFIFO_PUSH_CH1_V = 0x1 +const GDMA_OUTFIFO_PUSH_CH1_S = 9 +const GDMA_OUTFIFO_WDATA_CH1 = 0x000001FF +const GDMA_OUTFIFO_WDATA_CH1_V = 0x1FF +const GDMA_OUTFIFO_WDATA_CH1_S = 0 +const GDMA_OUTLINK_PARK_CH1_V = 0x1 +const GDMA_OUTLINK_PARK_CH1_S = 23 +const GDMA_OUTLINK_RESTART_CH1_V = 0x1 +const GDMA_OUTLINK_RESTART_CH1_S = 22 +const GDMA_OUTLINK_START_CH1_V = 0x1 +const GDMA_OUTLINK_START_CH1_S = 21 +const GDMA_OUTLINK_STOP_CH1_V = 0x1 +const GDMA_OUTLINK_STOP_CH1_S = 20 +const GDMA_OUTLINK_ADDR_CH1 = 0x000FFFFF +const GDMA_OUTLINK_ADDR_CH1_V = 0xFFFFF +const GDMA_OUTLINK_ADDR_CH1_S = 0 +const GDMA_OUT_STATE_CH1 = 0x00000007 +const GDMA_OUT_STATE_CH1_V = 0x7 +const GDMA_OUT_STATE_CH1_S = 20 +const GDMA_OUT_DSCR_STATE_CH1 = 0x00000003 +const GDMA_OUT_DSCR_STATE_CH1_V = 0x3 +const GDMA_OUT_DSCR_STATE_CH1_S = 18 +const GDMA_OUTLINK_DSCR_ADDR_CH1 = 0x0003FFFF +const GDMA_OUTLINK_DSCR_ADDR_CH1_V = 0x3FFFF +const GDMA_OUTLINK_DSCR_ADDR_CH1_S = 0 +const GDMA_OUT_EOF_DES_ADDR_CH1 = 0xFFFFFFFF +const GDMA_OUT_EOF_DES_ADDR_CH1_V = 0xFFFFFFFF +const GDMA_OUT_EOF_DES_ADDR_CH1_S = 0 +const GDMA_OUT_EOF_BFR_DES_ADDR_CH1 = 0xFFFFFFFF +const GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V = 0xFFFFFFFF +const GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S = 0 +const GDMA_OUTLINK_DSCR_CH1 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_CH1_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_CH1_S = 0 +const GDMA_OUTLINK_DSCR_BF0_CH1 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF0_CH1_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF0_CH1_S = 0 +const GDMA_OUTLINK_DSCR_BF1_CH1 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF1_CH1_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF1_CH1_S = 0 +const GDMA_TX_WEIGHT_CH1 = 0x0000000F +const GDMA_TX_WEIGHT_CH1_V = 0xF +const GDMA_TX_WEIGHT_CH1_S = 8 +const GDMA_TX_PRI_CH1 = 0x0000000F +const GDMA_TX_PRI_CH1_V = 0xF +const GDMA_TX_PRI_CH1_S = 0 +const GDMA_PERI_OUT_SEL_CH1 = 0x0000003F +const GDMA_PERI_OUT_SEL_CH1_V = 0x3F +const GDMA_PERI_OUT_SEL_CH1_S = 0 +const GDMA_MEM_TRANS_EN_CH2_V = 0x1 +const GDMA_MEM_TRANS_EN_CH2_S = 4 +const GDMA_IN_DATA_BURST_EN_CH2_V = 0x1 +const GDMA_IN_DATA_BURST_EN_CH2_S = 3 +const GDMA_INDSCR_BURST_EN_CH2_V = 0x1 +const GDMA_INDSCR_BURST_EN_CH2_S = 2 +const GDMA_IN_LOOP_TEST_CH2_V = 0x1 +const GDMA_IN_LOOP_TEST_CH2_S = 1 +const GDMA_IN_RST_CH2_V = 0x1 +const GDMA_IN_RST_CH2_S = 0 +const GDMA_IN_EXT_MEM_BK_SIZE_CH2 = 0x00000003 +const GDMA_IN_EXT_MEM_BK_SIZE_CH2_V = 0x3 +const GDMA_IN_EXT_MEM_BK_SIZE_CH2_S = 13 +const GDMA_IN_CHECK_OWNER_CH2_V = 0x1 +const GDMA_IN_CHECK_OWNER_CH2_S = 12 +const GDMA_DMA_INFIFO_FULL_THRS_CH2 = 0x00000FFF +const GDMA_DMA_INFIFO_FULL_THRS_CH2_V = 0xFFF +const GDMA_DMA_INFIFO_FULL_THRS_CH2_S = 0 +const GDMA_INFIFO_UDF_L3_CH2_INT_RAW_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH2_INT_RAW_S = 9 +const GDMA_INFIFO_OVF_L3_CH2_INT_RAW_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH2_INT_RAW_S = 8 +const GDMA_INFIFO_UDF_L1_CH2_INT_RAW_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH2_INT_RAW_S = 7 +const GDMA_INFIFO_OVF_L1_CH2_INT_RAW_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH2_INT_RAW_S = 6 +const GDMA_INFIFO_FULL_WM_CH2_INT_RAW_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH2_INT_RAW_S = 5 +const GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S = 4 +const GDMA_IN_DSCR_ERR_CH2_INT_RAW_V = 0x1 +const GDMA_IN_DSCR_ERR_CH2_INT_RAW_S = 3 +const GDMA_IN_ERR_EOF_CH2_INT_RAW_V = 0x1 +const GDMA_IN_ERR_EOF_CH2_INT_RAW_S = 2 +const GDMA_IN_SUC_EOF_CH2_INT_RAW_V = 0x1 +const GDMA_IN_SUC_EOF_CH2_INT_RAW_S = 1 +const GDMA_IN_DONE_CH2_INT_RAW_V = 0x1 +const GDMA_IN_DONE_CH2_INT_RAW_S = 0 +const GDMA_INFIFO_UDF_L3_CH2_INT_ST_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH2_INT_ST_S = 9 +const GDMA_INFIFO_OVF_L3_CH2_INT_ST_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH2_INT_ST_S = 8 +const GDMA_INFIFO_UDF_L1_CH2_INT_ST_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH2_INT_ST_S = 7 +const GDMA_INFIFO_OVF_L1_CH2_INT_ST_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH2_INT_ST_S = 6 +const GDMA_INFIFO_FULL_WM_CH2_INT_ST_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH2_INT_ST_S = 5 +const GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S = 4 +const GDMA_IN_DSCR_ERR_CH2_INT_ST_V = 0x1 +const GDMA_IN_DSCR_ERR_CH2_INT_ST_S = 3 +const GDMA_IN_ERR_EOF_CH2_INT_ST_V = 0x1 +const GDMA_IN_ERR_EOF_CH2_INT_ST_S = 2 +const GDMA_IN_SUC_EOF_CH2_INT_ST_V = 0x1 +const GDMA_IN_SUC_EOF_CH2_INT_ST_S = 1 +const GDMA_IN_DONE_CH2_INT_ST_V = 0x1 +const GDMA_IN_DONE_CH2_INT_ST_S = 0 +const GDMA_INFIFO_UDF_L3_CH2_INT_ENA_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH2_INT_ENA_S = 9 +const GDMA_INFIFO_OVF_L3_CH2_INT_ENA_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH2_INT_ENA_S = 8 +const GDMA_INFIFO_UDF_L1_CH2_INT_ENA_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH2_INT_ENA_S = 7 +const GDMA_INFIFO_OVF_L1_CH2_INT_ENA_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH2_INT_ENA_S = 6 +const GDMA_INFIFO_FULL_WM_CH2_INT_ENA_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH2_INT_ENA_S = 5 +const GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S = 4 +const GDMA_IN_DSCR_ERR_CH2_INT_ENA_V = 0x1 +const GDMA_IN_DSCR_ERR_CH2_INT_ENA_S = 3 +const GDMA_IN_ERR_EOF_CH2_INT_ENA_V = 0x1 +const GDMA_IN_ERR_EOF_CH2_INT_ENA_S = 2 +const GDMA_IN_SUC_EOF_CH2_INT_ENA_V = 0x1 +const GDMA_IN_SUC_EOF_CH2_INT_ENA_S = 1 +const GDMA_IN_DONE_CH2_INT_ENA_V = 0x1 +const GDMA_IN_DONE_CH2_INT_ENA_S = 0 +const GDMA_INFIFO_UDF_L3_CH2_INT_CLR_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH2_INT_CLR_S = 9 +const GDMA_INFIFO_OVF_L3_CH2_INT_CLR_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH2_INT_CLR_S = 8 +const GDMA_INFIFO_UDF_L1_CH2_INT_CLR_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH2_INT_CLR_S = 7 +const GDMA_INFIFO_OVF_L1_CH2_INT_CLR_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH2_INT_CLR_S = 6 +const GDMA_DMA_INFIFO_FULL_WM_CH2_INT_CLR_V = 0x1 +const GDMA_DMA_INFIFO_FULL_WM_CH2_INT_CLR_S = 5 +const GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S = 4 +const GDMA_IN_DSCR_ERR_CH2_INT_CLR_V = 0x1 +const GDMA_IN_DSCR_ERR_CH2_INT_CLR_S = 3 +const GDMA_IN_ERR_EOF_CH2_INT_CLR_V = 0x1 +const GDMA_IN_ERR_EOF_CH2_INT_CLR_S = 2 +const GDMA_IN_SUC_EOF_CH2_INT_CLR_V = 0x1 +const GDMA_IN_SUC_EOF_CH2_INT_CLR_S = 1 +const GDMA_IN_DONE_CH2_INT_CLR_V = 0x1 +const GDMA_IN_DONE_CH2_INT_CLR_S = 0 +const GDMA_IN_BUF_HUNGRY_CH2_V = 0x1 +const GDMA_IN_BUF_HUNGRY_CH2_S = 28 +const GDMA_IN_REMAIN_UNDER_4B_L3_CH2_V = 0x1 +const GDMA_IN_REMAIN_UNDER_4B_L3_CH2_S = 27 +const GDMA_IN_REMAIN_UNDER_3B_L3_CH2_V = 0x1 +const GDMA_IN_REMAIN_UNDER_3B_L3_CH2_S = 26 +const GDMA_IN_REMAIN_UNDER_2B_L3_CH2_V = 0x1 +const GDMA_IN_REMAIN_UNDER_2B_L3_CH2_S = 25 +const GDMA_IN_REMAIN_UNDER_1B_L3_CH2_V = 0x1 +const GDMA_IN_REMAIN_UNDER_1B_L3_CH2_S = 24 +const GDMA_INFIFO_CNT_L3_CH2 = 0x0000001F +const GDMA_INFIFO_CNT_L3_CH2_V = 0x1F +const GDMA_INFIFO_CNT_L3_CH2_S = 19 +const GDMA_INFIFO_CNT_L2_CH2 = 0x0000007F +const GDMA_INFIFO_CNT_L2_CH2_V = 0x7F +const GDMA_INFIFO_CNT_L2_CH2_S = 12 +const GDMA_INFIFO_CNT_L1_CH2 = 0x0000003F +const GDMA_INFIFO_CNT_L1_CH2_V = 0x3F +const GDMA_INFIFO_CNT_L1_CH2_S = 6 +const GDMA_INFIFO_EMPTY_L3_CH2_V = 0x1 +const GDMA_INFIFO_EMPTY_L3_CH2_S = 5 +const GDMA_INFIFO_FULL_L3_CH2_V = 0x1 +const GDMA_INFIFO_FULL_L3_CH2_S = 4 +const GDMA_INFIFO_EMPTY_L2_CH2_V = 0x1 +const GDMA_INFIFO_EMPTY_L2_CH2_S = 3 +const GDMA_INFIFO_FULL_L2_CH2_V = 0x1 +const GDMA_INFIFO_FULL_L2_CH2_S = 2 +const GDMA_INFIFO_EMPTY_L1_CH2_V = 0x1 +const GDMA_INFIFO_EMPTY_L1_CH2_S = 1 +const GDMA_INFIFO_FULL_L1_CH2_V = 0x1 +const GDMA_INFIFO_FULL_L1_CH2_S = 0 +const GDMA_INFIFO_POP_CH2_V = 0x1 +const GDMA_INFIFO_POP_CH2_S = 12 +const GDMA_INFIFO_RDATA_CH2 = 0x00000FFF +const GDMA_INFIFO_RDATA_CH2_V = 0xFFF +const GDMA_INFIFO_RDATA_CH2_S = 0 +const GDMA_INLINK_PARK_CH2_V = 0x1 +const GDMA_INLINK_PARK_CH2_S = 24 +const GDMA_INLINK_RESTART_CH2_V = 0x1 +const GDMA_INLINK_RESTART_CH2_S = 23 +const GDMA_INLINK_START_CH2_V = 0x1 +const GDMA_INLINK_START_CH2_S = 22 +const GDMA_INLINK_STOP_CH2_V = 0x1 +const GDMA_INLINK_STOP_CH2_S = 21 +const GDMA_INLINK_AUTO_RET_CH2_V = 0x1 +const GDMA_INLINK_AUTO_RET_CH2_S = 20 +const GDMA_INLINK_ADDR_CH2 = 0x000FFFFF +const GDMA_INLINK_ADDR_CH2_V = 0xFFFFF +const GDMA_INLINK_ADDR_CH2_S = 0 +const GDMA_IN_STATE_CH2 = 0x00000007 +const GDMA_IN_STATE_CH2_V = 0x7 +const GDMA_IN_STATE_CH2_S = 20 +const GDMA_IN_DSCR_STATE_CH2 = 0x00000003 +const GDMA_IN_DSCR_STATE_CH2_V = 0x3 +const GDMA_IN_DSCR_STATE_CH2_S = 18 +const GDMA_INLINK_DSCR_ADDR_CH2 = 0x0003FFFF +const GDMA_INLINK_DSCR_ADDR_CH2_V = 0x3FFFF +const GDMA_INLINK_DSCR_ADDR_CH2_S = 0 +const GDMA_IN_SUC_EOF_DES_ADDR_CH2 = 0xFFFFFFFF +const GDMA_IN_SUC_EOF_DES_ADDR_CH2_V = 0xFFFFFFFF +const GDMA_IN_SUC_EOF_DES_ADDR_CH2_S = 0 +const GDMA_IN_ERR_EOF_DES_ADDR_CH2 = 0xFFFFFFFF +const GDMA_IN_ERR_EOF_DES_ADDR_CH2_V = 0xFFFFFFFF +const GDMA_IN_ERR_EOF_DES_ADDR_CH2_S = 0 +const GDMA_INLINK_DSCR_CH2 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_CH2_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_CH2_S = 0 +const GDMA_INLINK_DSCR_BF0_CH2 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF0_CH2_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF0_CH2_S = 0 +const GDMA_INLINK_DSCR_BF1_CH2 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF1_CH2_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF1_CH2_S = 0 +const GDMA_RX_WEIGHT_CH2 = 0x0000000F +const GDMA_RX_WEIGHT_CH2_V = 0xF +const GDMA_RX_WEIGHT_CH2_S = 8 +const GDMA_RX_PRI_CH2 = 0x0000000F +const GDMA_RX_PRI_CH2_V = 0xF +const GDMA_RX_PRI_CH2_S = 0 +const GDMA_PERI_IN_SEL_CH2 = 0x0000003F +const GDMA_PERI_IN_SEL_CH2_V = 0x3F +const GDMA_PERI_IN_SEL_CH2_S = 0 +const GDMA_OUT_DATA_BURST_EN_CH2_V = 0x1 +const GDMA_OUT_DATA_BURST_EN_CH2_S = 5 +const GDMA_OUTDSCR_BURST_EN_CH2_V = 0x1 +const GDMA_OUTDSCR_BURST_EN_CH2_S = 4 +const GDMA_OUT_EOF_MODE_CH2_V = 0x1 +const GDMA_OUT_EOF_MODE_CH2_S = 3 +const GDMA_OUT_AUTO_WRBACK_CH2_V = 0x1 +const GDMA_OUT_AUTO_WRBACK_CH2_S = 2 +const GDMA_OUT_LOOP_TEST_CH2_V = 0x1 +const GDMA_OUT_LOOP_TEST_CH2_S = 1 +const GDMA_OUT_RST_CH2_V = 0x1 +const GDMA_OUT_RST_CH2_S = 0 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH2 = 0x00000003 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH2_V = 0x3 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH2_S = 13 +const GDMA_OUT_CHECK_OWNER_CH2_V = 0x1 +const GDMA_OUT_CHECK_OWNER_CH2_S = 12 +const GDMA_OUTFIFO_UDF_L3_CH2_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH2_INT_RAW_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH2_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH2_INT_RAW_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW_S = 4 +const GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S = 3 +const GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S = 2 +const GDMA_OUT_EOF_CH2_INT_RAW_V = 0x1 +const GDMA_OUT_EOF_CH2_INT_RAW_S = 1 +const GDMA_OUT_DONE_CH2_INT_RAW_V = 0x1 +const GDMA_OUT_DONE_CH2_INT_RAW_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH2_INT_ST_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH2_INT_ST_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH2_INT_ST_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH2_INT_ST_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH2_INT_ST_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH2_INT_ST_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH2_INT_ST_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH2_INT_ST_S = 4 +const GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S = 3 +const GDMA_OUT_DSCR_ERR_CH2_INT_ST_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH2_INT_ST_S = 2 +const GDMA_OUT_EOF_CH2_INT_ST_V = 0x1 +const GDMA_OUT_EOF_CH2_INT_ST_S = 1 +const GDMA_OUT_DONE_CH2_INT_ST_V = 0x1 +const GDMA_OUT_DONE_CH2_INT_ST_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH2_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH2_INT_ENA_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH2_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH2_INT_ENA_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH2_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH2_INT_ENA_S = 4 +const GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S = 3 +const GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S = 2 +const GDMA_OUT_EOF_CH2_INT_ENA_V = 0x1 +const GDMA_OUT_EOF_CH2_INT_ENA_S = 1 +const GDMA_OUT_DONE_CH2_INT_ENA_V = 0x1 +const GDMA_OUT_DONE_CH2_INT_ENA_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH2_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH2_INT_CLR_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH2_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH2_INT_CLR_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR_S = 4 +const GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S = 3 +const GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S = 2 +const GDMA_OUT_EOF_CH2_INT_CLR_V = 0x1 +const GDMA_OUT_EOF_CH2_INT_CLR_S = 1 +const GDMA_OUT_DONE_CH2_INT_CLR_V = 0x1 +const GDMA_OUT_DONE_CH2_INT_CLR_S = 0 +const GDMA_OUT_REMAIN_UNDER_4B_L3_CH2_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_4B_L3_CH2_S = 26 +const GDMA_OUT_REMAIN_UNDER_3B_L3_CH2_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_3B_L3_CH2_S = 25 +const GDMA_OUT_REMAIN_UNDER_2B_L3_CH2_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_2B_L3_CH2_S = 24 +const GDMA_OUT_REMAIN_UNDER_1B_L3_CH2_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_1B_L3_CH2_S = 23 +const GDMA_OUTFIFO_CNT_L3_CH2 = 0x0000001F +const GDMA_OUTFIFO_CNT_L3_CH2_V = 0x1F +const GDMA_OUTFIFO_CNT_L3_CH2_S = 18 +const GDMA_OUTFIFO_CNT_L2_CH2 = 0x0000007F +const GDMA_OUTFIFO_CNT_L2_CH2_V = 0x7F +const GDMA_OUTFIFO_CNT_L2_CH2_S = 11 +const GDMA_OUTFIFO_CNT_L1_CH2 = 0x0000001F +const GDMA_OUTFIFO_CNT_L1_CH2_V = 0x1F +const GDMA_OUTFIFO_CNT_L1_CH2_S = 6 +const GDMA_OUTFIFO_EMPTY_L3_CH2_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L3_CH2_S = 5 +const GDMA_OUTFIFO_FULL_L3_CH2_V = 0x1 +const GDMA_OUTFIFO_FULL_L3_CH2_S = 4 +const GDMA_OUTFIFO_EMPTY_L2_CH2_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L2_CH2_S = 3 +const GDMA_OUTFIFO_FULL_L2_CH2_V = 0x1 +const GDMA_OUTFIFO_FULL_L2_CH2_S = 2 +const GDMA_OUTFIFO_EMPTY_L1_CH2_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L1_CH2_S = 1 +const GDMA_OUTFIFO_FULL_L1_CH2_V = 0x1 +const GDMA_OUTFIFO_FULL_L1_CH2_S = 0 +const GDMA_OUTFIFO_PUSH_CH2_V = 0x1 +const GDMA_OUTFIFO_PUSH_CH2_S = 9 +const GDMA_OUTFIFO_WDATA_CH2 = 0x000001FF +const GDMA_OUTFIFO_WDATA_CH2_V = 0x1FF +const GDMA_OUTFIFO_WDATA_CH2_S = 0 +const GDMA_OUTLINK_PARK_CH2_V = 0x1 +const GDMA_OUTLINK_PARK_CH2_S = 23 +const GDMA_OUTLINK_RESTART_CH2_V = 0x1 +const GDMA_OUTLINK_RESTART_CH2_S = 22 +const GDMA_OUTLINK_START_CH2_V = 0x1 +const GDMA_OUTLINK_START_CH2_S = 21 +const GDMA_OUTLINK_STOP_CH2_V = 0x1 +const GDMA_OUTLINK_STOP_CH2_S = 20 +const GDMA_OUTLINK_ADDR_CH2 = 0x000FFFFF +const GDMA_OUTLINK_ADDR_CH2_V = 0xFFFFF +const GDMA_OUTLINK_ADDR_CH2_S = 0 +const GDMA_OUT_STATE_CH2 = 0x00000007 +const GDMA_OUT_STATE_CH2_V = 0x7 +const GDMA_OUT_STATE_CH2_S = 20 +const GDMA_OUT_DSCR_STATE_CH2 = 0x00000003 +const GDMA_OUT_DSCR_STATE_CH2_V = 0x3 +const GDMA_OUT_DSCR_STATE_CH2_S = 18 +const GDMA_OUTLINK_DSCR_ADDR_CH2 = 0x0003FFFF +const GDMA_OUTLINK_DSCR_ADDR_CH2_V = 0x3FFFF +const GDMA_OUTLINK_DSCR_ADDR_CH2_S = 0 +const GDMA_OUT_EOF_DES_ADDR_CH2 = 0xFFFFFFFF +const GDMA_OUT_EOF_DES_ADDR_CH2_V = 0xFFFFFFFF +const GDMA_OUT_EOF_DES_ADDR_CH2_S = 0 +const GDMA_OUT_EOF_BFR_DES_ADDR_CH2 = 0xFFFFFFFF +const GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V = 0xFFFFFFFF +const GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S = 0 +const GDMA_OUTLINK_DSCR_CH2 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_CH2_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_CH2_S = 0 +const GDMA_OUTLINK_DSCR_BF0_CH2 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF0_CH2_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF0_CH2_S = 0 +const GDMA_OUTLINK_DSCR_BF1_CH2 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF1_CH2_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF1_CH2_S = 0 +const GDMA_TX_WEIGHT_CH2 = 0x0000000F +const GDMA_TX_WEIGHT_CH2_V = 0xF +const GDMA_TX_WEIGHT_CH2_S = 8 +const GDMA_TX_PRI_CH2 = 0x0000000F +const GDMA_TX_PRI_CH2_V = 0xF +const GDMA_TX_PRI_CH2_S = 0 +const GDMA_PERI_OUT_SEL_CH2 = 0x0000003F +const GDMA_PERI_OUT_SEL_CH2_V = 0x3F +const GDMA_PERI_OUT_SEL_CH2_S = 0 +const GDMA_MEM_TRANS_EN_CH3_V = 0x1 +const GDMA_MEM_TRANS_EN_CH3_S = 4 +const GDMA_IN_DATA_BURST_EN_CH3_V = 0x1 +const GDMA_IN_DATA_BURST_EN_CH3_S = 3 +const GDMA_INDSCR_BURST_EN_CH3_V = 0x1 +const GDMA_INDSCR_BURST_EN_CH3_S = 2 +const GDMA_IN_LOOP_TEST_CH3_V = 0x1 +const GDMA_IN_LOOP_TEST_CH3_S = 1 +const GDMA_IN_RST_CH3_V = 0x1 +const GDMA_IN_RST_CH3_S = 0 +const GDMA_IN_EXT_MEM_BK_SIZE_CH3 = 0x00000003 +const GDMA_IN_EXT_MEM_BK_SIZE_CH3_V = 0x3 +const GDMA_IN_EXT_MEM_BK_SIZE_CH3_S = 13 +const GDMA_IN_CHECK_OWNER_CH3_V = 0x1 +const GDMA_IN_CHECK_OWNER_CH3_S = 12 +const GDMA_DMA_INFIFO_FULL_THRS_CH3 = 0x00000FFF +const GDMA_DMA_INFIFO_FULL_THRS_CH3_V = 0xFFF +const GDMA_DMA_INFIFO_FULL_THRS_CH3_S = 0 +const GDMA_INFIFO_UDF_L3_CH3_INT_RAW_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH3_INT_RAW_S = 9 +const GDMA_INFIFO_OVF_L3_CH3_INT_RAW_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH3_INT_RAW_S = 8 +const GDMA_INFIFO_UDF_L1_CH3_INT_RAW_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH3_INT_RAW_S = 7 +const GDMA_INFIFO_OVF_L1_CH3_INT_RAW_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH3_INT_RAW_S = 6 +const GDMA_INFIFO_FULL_WM_CH3_INT_RAW_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH3_INT_RAW_S = 5 +const GDMA_IN_DSCR_EMPTY_CH3_INT_RAW_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH3_INT_RAW_S = 4 +const GDMA_IN_DSCR_ERR_CH3_INT_RAW_V = 0x1 +const GDMA_IN_DSCR_ERR_CH3_INT_RAW_S = 3 +const GDMA_IN_ERR_EOF_CH3_INT_RAW_V = 0x1 +const GDMA_IN_ERR_EOF_CH3_INT_RAW_S = 2 +const GDMA_IN_SUC_EOF_CH3_INT_RAW_V = 0x1 +const GDMA_IN_SUC_EOF_CH3_INT_RAW_S = 1 +const GDMA_IN_DONE_CH3_INT_RAW_V = 0x1 +const GDMA_IN_DONE_CH3_INT_RAW_S = 0 +const GDMA_INFIFO_UDF_L3_CH3_INT_ST_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH3_INT_ST_S = 9 +const GDMA_INFIFO_OVF_L3_CH3_INT_ST_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH3_INT_ST_S = 8 +const GDMA_INFIFO_UDF_L1_CH3_INT_ST_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH3_INT_ST_S = 7 +const GDMA_INFIFO_OVF_L1_CH3_INT_ST_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH3_INT_ST_S = 6 +const GDMA_INFIFO_FULL_WM_CH3_INT_ST_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH3_INT_ST_S = 5 +const GDMA_IN_DSCR_EMPTY_CH3_INT_ST_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH3_INT_ST_S = 4 +const GDMA_IN_DSCR_ERR_CH3_INT_ST_V = 0x1 +const GDMA_IN_DSCR_ERR_CH3_INT_ST_S = 3 +const GDMA_IN_ERR_EOF_CH3_INT_ST_V = 0x1 +const GDMA_IN_ERR_EOF_CH3_INT_ST_S = 2 +const GDMA_IN_SUC_EOF_CH3_INT_ST_V = 0x1 +const GDMA_IN_SUC_EOF_CH3_INT_ST_S = 1 +const GDMA_IN_DONE_CH3_INT_ST_V = 0x1 +const GDMA_IN_DONE_CH3_INT_ST_S = 0 +const GDMA_INFIFO_UDF_L3_CH3_INT_ENA_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH3_INT_ENA_S = 9 +const GDMA_INFIFO_OVF_L3_CH3_INT_ENA_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH3_INT_ENA_S = 8 +const GDMA_INFIFO_UDF_L1_CH3_INT_ENA_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH3_INT_ENA_S = 7 +const GDMA_INFIFO_OVF_L1_CH3_INT_ENA_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH3_INT_ENA_S = 6 +const GDMA_INFIFO_FULL_WM_CH3_INT_ENA_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH3_INT_ENA_S = 5 +const GDMA_IN_DSCR_EMPTY_CH3_INT_ENA_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH3_INT_ENA_S = 4 +const GDMA_IN_DSCR_ERR_CH3_INT_ENA_V = 0x1 +const GDMA_IN_DSCR_ERR_CH3_INT_ENA_S = 3 +const GDMA_IN_ERR_EOF_CH3_INT_ENA_V = 0x1 +const GDMA_IN_ERR_EOF_CH3_INT_ENA_S = 2 +const GDMA_IN_SUC_EOF_CH3_INT_ENA_V = 0x1 +const GDMA_IN_SUC_EOF_CH3_INT_ENA_S = 1 +const GDMA_IN_DONE_CH3_INT_ENA_V = 0x1 +const GDMA_IN_DONE_CH3_INT_ENA_S = 0 +const GDMA_INFIFO_UDF_L3_CH3_INT_CLR_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH3_INT_CLR_S = 9 +const GDMA_INFIFO_OVF_L3_CH3_INT_CLR_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH3_INT_CLR_S = 8 +const GDMA_INFIFO_UDF_L1_CH3_INT_CLR_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH3_INT_CLR_S = 7 +const GDMA_INFIFO_OVF_L1_CH3_INT_CLR_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH3_INT_CLR_S = 6 +const GDMA_DMA_INFIFO_FULL_WM_CH3_INT_CLR_V = 0x1 +const GDMA_DMA_INFIFO_FULL_WM_CH3_INT_CLR_S = 5 +const GDMA_IN_DSCR_EMPTY_CH3_INT_CLR_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH3_INT_CLR_S = 4 +const GDMA_IN_DSCR_ERR_CH3_INT_CLR_V = 0x1 +const GDMA_IN_DSCR_ERR_CH3_INT_CLR_S = 3 +const GDMA_IN_ERR_EOF_CH3_INT_CLR_V = 0x1 +const GDMA_IN_ERR_EOF_CH3_INT_CLR_S = 2 +const GDMA_IN_SUC_EOF_CH3_INT_CLR_V = 0x1 +const GDMA_IN_SUC_EOF_CH3_INT_CLR_S = 1 +const GDMA_IN_DONE_CH3_INT_CLR_V = 0x1 +const GDMA_IN_DONE_CH3_INT_CLR_S = 0 +const GDMA_IN_BUF_HUNGRY_CH3_V = 0x1 +const GDMA_IN_BUF_HUNGRY_CH3_S = 28 +const GDMA_IN_REMAIN_UNDER_4B_L3_CH3_V = 0x1 +const GDMA_IN_REMAIN_UNDER_4B_L3_CH3_S = 27 +const GDMA_IN_REMAIN_UNDER_3B_L3_CH3_V = 0x1 +const GDMA_IN_REMAIN_UNDER_3B_L3_CH3_S = 26 +const GDMA_IN_REMAIN_UNDER_2B_L3_CH3_V = 0x1 +const GDMA_IN_REMAIN_UNDER_2B_L3_CH3_S = 25 +const GDMA_IN_REMAIN_UNDER_1B_L3_CH3_V = 0x1 +const GDMA_IN_REMAIN_UNDER_1B_L3_CH3_S = 24 +const GDMA_INFIFO_CNT_L3_CH3 = 0x0000001F +const GDMA_INFIFO_CNT_L3_CH3_V = 0x1F +const GDMA_INFIFO_CNT_L3_CH3_S = 19 +const GDMA_INFIFO_CNT_L2_CH3 = 0x0000007F +const GDMA_INFIFO_CNT_L2_CH3_V = 0x7F +const GDMA_INFIFO_CNT_L2_CH3_S = 12 +const GDMA_INFIFO_CNT_L1_CH3 = 0x0000003F +const GDMA_INFIFO_CNT_L1_CH3_V = 0x3F +const GDMA_INFIFO_CNT_L1_CH3_S = 6 +const GDMA_INFIFO_EMPTY_L3_CH3_V = 0x1 +const GDMA_INFIFO_EMPTY_L3_CH3_S = 5 +const GDMA_INFIFO_FULL_L3_CH3_V = 0x1 +const GDMA_INFIFO_FULL_L3_CH3_S = 4 +const GDMA_INFIFO_EMPTY_L2_CH3_V = 0x1 +const GDMA_INFIFO_EMPTY_L2_CH3_S = 3 +const GDMA_INFIFO_FULL_L2_CH3_V = 0x1 +const GDMA_INFIFO_FULL_L2_CH3_S = 2 +const GDMA_INFIFO_EMPTY_L1_CH3_V = 0x1 +const GDMA_INFIFO_EMPTY_L1_CH3_S = 1 +const GDMA_INFIFO_FULL_L1_CH3_V = 0x1 +const GDMA_INFIFO_FULL_L1_CH3_S = 0 +const GDMA_INFIFO_POP_CH3_V = 0x1 +const GDMA_INFIFO_POP_CH3_S = 12 +const GDMA_INFIFO_RDATA_CH3 = 0x00000FFF +const GDMA_INFIFO_RDATA_CH3_V = 0xFFF +const GDMA_INFIFO_RDATA_CH3_S = 0 +const GDMA_INLINK_PARK_CH3_V = 0x1 +const GDMA_INLINK_PARK_CH3_S = 24 +const GDMA_INLINK_RESTART_CH3_V = 0x1 +const GDMA_INLINK_RESTART_CH3_S = 23 +const GDMA_INLINK_START_CH3_V = 0x1 +const GDMA_INLINK_START_CH3_S = 22 +const GDMA_INLINK_STOP_CH3_V = 0x1 +const GDMA_INLINK_STOP_CH3_S = 21 +const GDMA_INLINK_AUTO_RET_CH3_V = 0x1 +const GDMA_INLINK_AUTO_RET_CH3_S = 20 +const GDMA_INLINK_ADDR_CH3 = 0x000FFFFF +const GDMA_INLINK_ADDR_CH3_V = 0xFFFFF +const GDMA_INLINK_ADDR_CH3_S = 0 +const GDMA_IN_STATE_CH3 = 0x00000007 +const GDMA_IN_STATE_CH3_V = 0x7 +const GDMA_IN_STATE_CH3_S = 20 +const GDMA_IN_DSCR_STATE_CH3 = 0x00000003 +const GDMA_IN_DSCR_STATE_CH3_V = 0x3 +const GDMA_IN_DSCR_STATE_CH3_S = 18 +const GDMA_INLINK_DSCR_ADDR_CH3 = 0x0003FFFF +const GDMA_INLINK_DSCR_ADDR_CH3_V = 0x3FFFF +const GDMA_INLINK_DSCR_ADDR_CH3_S = 0 +const GDMA_IN_SUC_EOF_DES_ADDR_CH3 = 0xFFFFFFFF +const GDMA_IN_SUC_EOF_DES_ADDR_CH3_V = 0xFFFFFFFF +const GDMA_IN_SUC_EOF_DES_ADDR_CH3_S = 0 +const GDMA_IN_ERR_EOF_DES_ADDR_CH3 = 0xFFFFFFFF +const GDMA_IN_ERR_EOF_DES_ADDR_CH3_V = 0xFFFFFFFF +const GDMA_IN_ERR_EOF_DES_ADDR_CH3_S = 0 +const GDMA_INLINK_DSCR_CH3 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_CH3_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_CH3_S = 0 +const GDMA_INLINK_DSCR_BF0_CH3 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF0_CH3_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF0_CH3_S = 0 +const GDMA_INLINK_DSCR_BF1_CH3 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF1_CH3_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF1_CH3_S = 0 +const GDMA_RX_WEIGHT_CH3 = 0x0000000F +const GDMA_RX_WEIGHT_CH3_V = 0xF +const GDMA_RX_WEIGHT_CH3_S = 8 +const GDMA_RX_PRI_CH3 = 0x0000000F +const GDMA_RX_PRI_CH3_V = 0xF +const GDMA_RX_PRI_CH3_S = 0 +const GDMA_PERI_IN_SEL_CH3 = 0x0000003F +const GDMA_PERI_IN_SEL_CH3_V = 0x3F +const GDMA_PERI_IN_SEL_CH3_S = 0 +const GDMA_OUT_DATA_BURST_EN_CH3_V = 0x1 +const GDMA_OUT_DATA_BURST_EN_CH3_S = 5 +const GDMA_OUTDSCR_BURST_EN_CH3_V = 0x1 +const GDMA_OUTDSCR_BURST_EN_CH3_S = 4 +const GDMA_OUT_EOF_MODE_CH3_V = 0x1 +const GDMA_OUT_EOF_MODE_CH3_S = 3 +const GDMA_OUT_AUTO_WRBACK_CH3_V = 0x1 +const GDMA_OUT_AUTO_WRBACK_CH3_S = 2 +const GDMA_OUT_LOOP_TEST_CH3_V = 0x1 +const GDMA_OUT_LOOP_TEST_CH3_S = 1 +const GDMA_OUT_RST_CH3_V = 0x1 +const GDMA_OUT_RST_CH3_S = 0 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH3 = 0x00000003 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH3_V = 0x3 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH3_S = 13 +const GDMA_OUT_CHECK_OWNER_CH3_V = 0x1 +const GDMA_OUT_CHECK_OWNER_CH3_S = 12 +const GDMA_OUTFIFO_UDF_L3_CH3_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH3_INT_RAW_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH3_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH3_INT_RAW_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH3_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH3_INT_RAW_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW_S = 4 +const GDMA_OUT_TOTAL_EOF_CH3_INT_RAW_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH3_INT_RAW_S = 3 +const GDMA_OUT_DSCR_ERR_CH3_INT_RAW_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH3_INT_RAW_S = 2 +const GDMA_OUT_EOF_CH3_INT_RAW_V = 0x1 +const GDMA_OUT_EOF_CH3_INT_RAW_S = 1 +const GDMA_OUT_DONE_CH3_INT_RAW_V = 0x1 +const GDMA_OUT_DONE_CH3_INT_RAW_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH3_INT_ST_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH3_INT_ST_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH3_INT_ST_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH3_INT_ST_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH3_INT_ST_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH3_INT_ST_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH3_INT_ST_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH3_INT_ST_S = 4 +const GDMA_OUT_TOTAL_EOF_CH3_INT_ST_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH3_INT_ST_S = 3 +const GDMA_OUT_DSCR_ERR_CH3_INT_ST_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH3_INT_ST_S = 2 +const GDMA_OUT_EOF_CH3_INT_ST_V = 0x1 +const GDMA_OUT_EOF_CH3_INT_ST_S = 1 +const GDMA_OUT_DONE_CH3_INT_ST_V = 0x1 +const GDMA_OUT_DONE_CH3_INT_ST_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH3_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH3_INT_ENA_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH3_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH3_INT_ENA_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH3_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH3_INT_ENA_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH3_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH3_INT_ENA_S = 4 +const GDMA_OUT_TOTAL_EOF_CH3_INT_ENA_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH3_INT_ENA_S = 3 +const GDMA_OUT_DSCR_ERR_CH3_INT_ENA_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH3_INT_ENA_S = 2 +const GDMA_OUT_EOF_CH3_INT_ENA_V = 0x1 +const GDMA_OUT_EOF_CH3_INT_ENA_S = 1 +const GDMA_OUT_DONE_CH3_INT_ENA_V = 0x1 +const GDMA_OUT_DONE_CH3_INT_ENA_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH3_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH3_INT_CLR_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH3_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH3_INT_CLR_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH3_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH3_INT_CLR_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH3_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH3_INT_CLR_S = 4 +const GDMA_OUT_TOTAL_EOF_CH3_INT_CLR_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH3_INT_CLR_S = 3 +const GDMA_OUT_DSCR_ERR_CH3_INT_CLR_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH3_INT_CLR_S = 2 +const GDMA_OUT_EOF_CH3_INT_CLR_V = 0x1 +const GDMA_OUT_EOF_CH3_INT_CLR_S = 1 +const GDMA_OUT_DONE_CH3_INT_CLR_V = 0x1 +const GDMA_OUT_DONE_CH3_INT_CLR_S = 0 +const GDMA_OUT_REMAIN_UNDER_4B_L3_CH3_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_4B_L3_CH3_S = 26 +const GDMA_OUT_REMAIN_UNDER_3B_L3_CH3_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_3B_L3_CH3_S = 25 +const GDMA_OUT_REMAIN_UNDER_2B_L3_CH3_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_2B_L3_CH3_S = 24 +const GDMA_OUT_REMAIN_UNDER_1B_L3_CH3_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_1B_L3_CH3_S = 23 +const GDMA_OUTFIFO_CNT_L3_CH3 = 0x0000001F +const GDMA_OUTFIFO_CNT_L3_CH3_V = 0x1F +const GDMA_OUTFIFO_CNT_L3_CH3_S = 18 +const GDMA_OUTFIFO_CNT_L2_CH3 = 0x0000007F +const GDMA_OUTFIFO_CNT_L2_CH3_V = 0x7F +const GDMA_OUTFIFO_CNT_L2_CH3_S = 11 +const GDMA_OUTFIFO_CNT_L1_CH3 = 0x0000001F +const GDMA_OUTFIFO_CNT_L1_CH3_V = 0x1F +const GDMA_OUTFIFO_CNT_L1_CH3_S = 6 +const GDMA_OUTFIFO_EMPTY_L3_CH3_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L3_CH3_S = 5 +const GDMA_OUTFIFO_FULL_L3_CH3_V = 0x1 +const GDMA_OUTFIFO_FULL_L3_CH3_S = 4 +const GDMA_OUTFIFO_EMPTY_L2_CH3_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L2_CH3_S = 3 +const GDMA_OUTFIFO_FULL_L2_CH3_V = 0x1 +const GDMA_OUTFIFO_FULL_L2_CH3_S = 2 +const GDMA_OUTFIFO_EMPTY_L1_CH3_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L1_CH3_S = 1 +const GDMA_OUTFIFO_FULL_L1_CH3_V = 0x1 +const GDMA_OUTFIFO_FULL_L1_CH3_S = 0 +const GDMA_OUTFIFO_PUSH_CH3_V = 0x1 +const GDMA_OUTFIFO_PUSH_CH3_S = 9 +const GDMA_OUTFIFO_WDATA_CH3 = 0x000001FF +const GDMA_OUTFIFO_WDATA_CH3_V = 0x1FF +const GDMA_OUTFIFO_WDATA_CH3_S = 0 +const GDMA_OUTLINK_PARK_CH3_V = 0x1 +const GDMA_OUTLINK_PARK_CH3_S = 23 +const GDMA_OUTLINK_RESTART_CH3_V = 0x1 +const GDMA_OUTLINK_RESTART_CH3_S = 22 +const GDMA_OUTLINK_START_CH3_V = 0x1 +const GDMA_OUTLINK_START_CH3_S = 21 +const GDMA_OUTLINK_STOP_CH3_V = 0x1 +const GDMA_OUTLINK_STOP_CH3_S = 20 +const GDMA_OUTLINK_ADDR_CH3 = 0x000FFFFF +const GDMA_OUTLINK_ADDR_CH3_V = 0xFFFFF +const GDMA_OUTLINK_ADDR_CH3_S = 0 +const GDMA_OUT_STATE_CH3 = 0x00000007 +const GDMA_OUT_STATE_CH3_V = 0x7 +const GDMA_OUT_STATE_CH3_S = 20 +const GDMA_OUT_DSCR_STATE_CH3 = 0x00000003 +const GDMA_OUT_DSCR_STATE_CH3_V = 0x3 +const GDMA_OUT_DSCR_STATE_CH3_S = 18 +const GDMA_OUTLINK_DSCR_ADDR_CH3 = 0x0003FFFF +const GDMA_OUTLINK_DSCR_ADDR_CH3_V = 0x3FFFF +const GDMA_OUTLINK_DSCR_ADDR_CH3_S = 0 +const GDMA_OUT_EOF_DES_ADDR_CH3 = 0xFFFFFFFF +const GDMA_OUT_EOF_DES_ADDR_CH3_V = 0xFFFFFFFF +const GDMA_OUT_EOF_DES_ADDR_CH3_S = 0 +const GDMA_OUT_EOF_BFR_DES_ADDR_CH3 = 0xFFFFFFFF +const GDMA_OUT_EOF_BFR_DES_ADDR_CH3_V = 0xFFFFFFFF +const GDMA_OUT_EOF_BFR_DES_ADDR_CH3_S = 0 +const GDMA_OUTLINK_DSCR_CH3 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_CH3_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_CH3_S = 0 +const GDMA_OUTLINK_DSCR_BF0_CH3 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF0_CH3_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF0_CH3_S = 0 +const GDMA_OUTLINK_DSCR_BF1_CH3 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF1_CH3_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF1_CH3_S = 0 +const GDMA_TX_WEIGHT_CH3 = 0x0000000F +const GDMA_TX_WEIGHT_CH3_V = 0xF +const GDMA_TX_WEIGHT_CH3_S = 8 +const GDMA_TX_PRI_CH3 = 0x0000000F +const GDMA_TX_PRI_CH3_V = 0xF +const GDMA_TX_PRI_CH3_S = 0 +const GDMA_PERI_OUT_SEL_CH3 = 0x0000003F +const GDMA_PERI_OUT_SEL_CH3_V = 0x3F +const GDMA_PERI_OUT_SEL_CH3_S = 0 +const GDMA_MEM_TRANS_EN_CH4_V = 0x1 +const GDMA_MEM_TRANS_EN_CH4_S = 4 +const GDMA_IN_DATA_BURST_EN_CH4_V = 0x1 +const GDMA_IN_DATA_BURST_EN_CH4_S = 3 +const GDMA_INDSCR_BURST_EN_CH4_V = 0x1 +const GDMA_INDSCR_BURST_EN_CH4_S = 2 +const GDMA_IN_LOOP_TEST_CH4_V = 0x1 +const GDMA_IN_LOOP_TEST_CH4_S = 1 +const GDMA_IN_RST_CH4_V = 0x1 +const GDMA_IN_RST_CH4_S = 0 +const GDMA_IN_EXT_MEM_BK_SIZE_CH4 = 0x00000003 +const GDMA_IN_EXT_MEM_BK_SIZE_CH4_V = 0x3 +const GDMA_IN_EXT_MEM_BK_SIZE_CH4_S = 13 +const GDMA_IN_CHECK_OWNER_CH4_V = 0x1 +const GDMA_IN_CHECK_OWNER_CH4_S = 12 +const GDMA_DMA_INFIFO_FULL_THRS_CH4 = 0x00000FFF +const GDMA_DMA_INFIFO_FULL_THRS_CH4_V = 0xFFF +const GDMA_DMA_INFIFO_FULL_THRS_CH4_S = 0 +const GDMA_INFIFO_UDF_L3_CH4_INT_RAW_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH4_INT_RAW_S = 9 +const GDMA_INFIFO_OVF_L3_CH4_INT_RAW_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH4_INT_RAW_S = 8 +const GDMA_INFIFO_UDF_L1_CH4_INT_RAW_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH4_INT_RAW_S = 7 +const GDMA_INFIFO_OVF_L1_CH4_INT_RAW_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH4_INT_RAW_S = 6 +const GDMA_INFIFO_FULL_WM_CH4_INT_RAW_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH4_INT_RAW_S = 5 +const GDMA_IN_DSCR_EMPTY_CH4_INT_RAW_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH4_INT_RAW_S = 4 +const GDMA_IN_DSCR_ERR_CH4_INT_RAW_V = 0x1 +const GDMA_IN_DSCR_ERR_CH4_INT_RAW_S = 3 +const GDMA_IN_ERR_EOF_CH4_INT_RAW_V = 0x1 +const GDMA_IN_ERR_EOF_CH4_INT_RAW_S = 2 +const GDMA_IN_SUC_EOF_CH4_INT_RAW_V = 0x1 +const GDMA_IN_SUC_EOF_CH4_INT_RAW_S = 1 +const GDMA_IN_DONE_CH4_INT_RAW_V = 0x1 +const GDMA_IN_DONE_CH4_INT_RAW_S = 0 +const GDMA_INFIFO_UDF_L3_CH4_INT_ST_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH4_INT_ST_S = 9 +const GDMA_INFIFO_OVF_L3_CH4_INT_ST_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH4_INT_ST_S = 8 +const GDMA_INFIFO_UDF_L1_CH4_INT_ST_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH4_INT_ST_S = 7 +const GDMA_INFIFO_OVF_L1_CH4_INT_ST_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH4_INT_ST_S = 6 +const GDMA_INFIFO_FULL_WM_CH4_INT_ST_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH4_INT_ST_S = 5 +const GDMA_IN_DSCR_EMPTY_CH4_INT_ST_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH4_INT_ST_S = 4 +const GDMA_IN_DSCR_ERR_CH4_INT_ST_V = 0x1 +const GDMA_IN_DSCR_ERR_CH4_INT_ST_S = 3 +const GDMA_IN_ERR_EOF_CH4_INT_ST_V = 0x1 +const GDMA_IN_ERR_EOF_CH4_INT_ST_S = 2 +const GDMA_IN_SUC_EOF_CH4_INT_ST_V = 0x1 +const GDMA_IN_SUC_EOF_CH4_INT_ST_S = 1 +const GDMA_IN_DONE_CH4_INT_ST_V = 0x1 +const GDMA_IN_DONE_CH4_INT_ST_S = 0 +const GDMA_INFIFO_UDF_L3_CH4_INT_ENA_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH4_INT_ENA_S = 9 +const GDMA_INFIFO_OVF_L3_CH4_INT_ENA_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH4_INT_ENA_S = 8 +const GDMA_INFIFO_UDF_L1_CH4_INT_ENA_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH4_INT_ENA_S = 7 +const GDMA_INFIFO_OVF_L1_CH4_INT_ENA_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH4_INT_ENA_S = 6 +const GDMA_INFIFO_FULL_WM_CH4_INT_ENA_V = 0x1 +const GDMA_INFIFO_FULL_WM_CH4_INT_ENA_S = 5 +const GDMA_IN_DSCR_EMPTY_CH4_INT_ENA_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH4_INT_ENA_S = 4 +const GDMA_IN_DSCR_ERR_CH4_INT_ENA_V = 0x1 +const GDMA_IN_DSCR_ERR_CH4_INT_ENA_S = 3 +const GDMA_IN_ERR_EOF_CH4_INT_ENA_V = 0x1 +const GDMA_IN_ERR_EOF_CH4_INT_ENA_S = 2 +const GDMA_IN_SUC_EOF_CH4_INT_ENA_V = 0x1 +const GDMA_IN_SUC_EOF_CH4_INT_ENA_S = 1 +const GDMA_IN_DONE_CH4_INT_ENA_V = 0x1 +const GDMA_IN_DONE_CH4_INT_ENA_S = 0 +const GDMA_INFIFO_UDF_L3_CH4_INT_CLR_V = 0x1 +const GDMA_INFIFO_UDF_L3_CH4_INT_CLR_S = 9 +const GDMA_INFIFO_OVF_L3_CH4_INT_CLR_V = 0x1 +const GDMA_INFIFO_OVF_L3_CH4_INT_CLR_S = 8 +const GDMA_INFIFO_UDF_L1_CH4_INT_CLR_V = 0x1 +const GDMA_INFIFO_UDF_L1_CH4_INT_CLR_S = 7 +const GDMA_INFIFO_OVF_L1_CH4_INT_CLR_V = 0x1 +const GDMA_INFIFO_OVF_L1_CH4_INT_CLR_S = 6 +const GDMA_DMA_INFIFO_FULL_WM_CH4_INT_CLR_V = 0x1 +const GDMA_DMA_INFIFO_FULL_WM_CH4_INT_CLR_S = 5 +const GDMA_IN_DSCR_EMPTY_CH4_INT_CLR_V = 0x1 +const GDMA_IN_DSCR_EMPTY_CH4_INT_CLR_S = 4 +const GDMA_IN_DSCR_ERR_CH4_INT_CLR_V = 0x1 +const GDMA_IN_DSCR_ERR_CH4_INT_CLR_S = 3 +const GDMA_IN_ERR_EOF_CH4_INT_CLR_V = 0x1 +const GDMA_IN_ERR_EOF_CH4_INT_CLR_S = 2 +const GDMA_IN_SUC_EOF_CH4_INT_CLR_V = 0x1 +const GDMA_IN_SUC_EOF_CH4_INT_CLR_S = 1 +const GDMA_IN_DONE_CH4_INT_CLR_V = 0x1 +const GDMA_IN_DONE_CH4_INT_CLR_S = 0 +const GDMA_IN_BUF_HUNGRY_CH4_V = 0x1 +const GDMA_IN_BUF_HUNGRY_CH4_S = 28 +const GDMA_IN_REMAIN_UNDER_4B_L3_CH4_V = 0x1 +const GDMA_IN_REMAIN_UNDER_4B_L3_CH4_S = 27 +const GDMA_IN_REMAIN_UNDER_3B_L3_CH4_V = 0x1 +const GDMA_IN_REMAIN_UNDER_3B_L3_CH4_S = 26 +const GDMA_IN_REMAIN_UNDER_2B_L3_CH4_V = 0x1 +const GDMA_IN_REMAIN_UNDER_2B_L3_CH4_S = 25 +const GDMA_IN_REMAIN_UNDER_1B_L3_CH4_V = 0x1 +const GDMA_IN_REMAIN_UNDER_1B_L3_CH4_S = 24 +const GDMA_INFIFO_CNT_L3_CH4 = 0x0000001F +const GDMA_INFIFO_CNT_L3_CH4_V = 0x1F +const GDMA_INFIFO_CNT_L3_CH4_S = 19 +const GDMA_INFIFO_CNT_L2_CH4 = 0x0000007F +const GDMA_INFIFO_CNT_L2_CH4_V = 0x7F +const GDMA_INFIFO_CNT_L2_CH4_S = 12 +const GDMA_INFIFO_CNT_L1_CH4 = 0x0000003F +const GDMA_INFIFO_CNT_L1_CH4_V = 0x3F +const GDMA_INFIFO_CNT_L1_CH4_S = 6 +const GDMA_INFIFO_EMPTY_L3_CH4_V = 0x1 +const GDMA_INFIFO_EMPTY_L3_CH4_S = 5 +const GDMA_INFIFO_FULL_L3_CH4_V = 0x1 +const GDMA_INFIFO_FULL_L3_CH4_S = 4 +const GDMA_INFIFO_EMPTY_L2_CH4_V = 0x1 +const GDMA_INFIFO_EMPTY_L2_CH4_S = 3 +const GDMA_INFIFO_FULL_L2_CH4_V = 0x1 +const GDMA_INFIFO_FULL_L2_CH4_S = 2 +const GDMA_INFIFO_EMPTY_L1_CH4_V = 0x1 +const GDMA_INFIFO_EMPTY_L1_CH4_S = 1 +const GDMA_INFIFO_FULL_L1_CH4_V = 0x1 +const GDMA_INFIFO_FULL_L1_CH4_S = 0 +const GDMA_INFIFO_POP_CH4_V = 0x1 +const GDMA_INFIFO_POP_CH4_S = 12 +const GDMA_INFIFO_RDATA_CH4 = 0x00000FFF +const GDMA_INFIFO_RDATA_CH4_V = 0xFFF +const GDMA_INFIFO_RDATA_CH4_S = 0 +const GDMA_INLINK_PARK_CH4_V = 0x1 +const GDMA_INLINK_PARK_CH4_S = 24 +const GDMA_INLINK_RESTART_CH4_V = 0x1 +const GDMA_INLINK_RESTART_CH4_S = 23 +const GDMA_INLINK_START_CH4_V = 0x1 +const GDMA_INLINK_START_CH4_S = 22 +const GDMA_INLINK_STOP_CH4_V = 0x1 +const GDMA_INLINK_STOP_CH4_S = 21 +const GDMA_INLINK_AUTO_RET_CH4_V = 0x1 +const GDMA_INLINK_AUTO_RET_CH4_S = 20 +const GDMA_INLINK_ADDR_CH4 = 0x000FFFFF +const GDMA_INLINK_ADDR_CH4_V = 0xFFFFF +const GDMA_INLINK_ADDR_CH4_S = 0 +const GDMA_IN_STATE_CH4 = 0x00000007 +const GDMA_IN_STATE_CH4_V = 0x7 +const GDMA_IN_STATE_CH4_S = 20 +const GDMA_IN_DSCR_STATE_CH4 = 0x00000003 +const GDMA_IN_DSCR_STATE_CH4_V = 0x3 +const GDMA_IN_DSCR_STATE_CH4_S = 18 +const GDMA_INLINK_DSCR_ADDR_CH4 = 0x0003FFFF +const GDMA_INLINK_DSCR_ADDR_CH4_V = 0x3FFFF +const GDMA_INLINK_DSCR_ADDR_CH4_S = 0 +const GDMA_IN_SUC_EOF_DES_ADDR_CH4 = 0xFFFFFFFF +const GDMA_IN_SUC_EOF_DES_ADDR_CH4_V = 0xFFFFFFFF +const GDMA_IN_SUC_EOF_DES_ADDR_CH4_S = 0 +const GDMA_IN_ERR_EOF_DES_ADDR_CH4 = 0xFFFFFFFF +const GDMA_IN_ERR_EOF_DES_ADDR_CH4_V = 0xFFFFFFFF +const GDMA_IN_ERR_EOF_DES_ADDR_CH4_S = 0 +const GDMA_INLINK_DSCR_CH4 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_CH4_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_CH4_S = 0 +const GDMA_INLINK_DSCR_BF0_CH4 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF0_CH4_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF0_CH4_S = 0 +const GDMA_INLINK_DSCR_BF1_CH4 = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF1_CH4_V = 0xFFFFFFFF +const GDMA_INLINK_DSCR_BF1_CH4_S = 0 +const GDMA_RX_WEIGHT_CH4 = 0x0000000F +const GDMA_RX_WEIGHT_CH4_V = 0xF +const GDMA_RX_WEIGHT_CH4_S = 8 +const GDMA_RX_PRI_CH4 = 0x0000000F +const GDMA_RX_PRI_CH4_V = 0xF +const GDMA_RX_PRI_CH4_S = 0 +const GDMA_PERI_IN_SEL_CH4 = 0x0000003F +const GDMA_PERI_IN_SEL_CH4_V = 0x3F +const GDMA_PERI_IN_SEL_CH4_S = 0 +const GDMA_OUT_DATA_BURST_EN_CH4_V = 0x1 +const GDMA_OUT_DATA_BURST_EN_CH4_S = 5 +const GDMA_OUTDSCR_BURST_EN_CH4_V = 0x1 +const GDMA_OUTDSCR_BURST_EN_CH4_S = 4 +const GDMA_OUT_EOF_MODE_CH4_V = 0x1 +const GDMA_OUT_EOF_MODE_CH4_S = 3 +const GDMA_OUT_AUTO_WRBACK_CH4_V = 0x1 +const GDMA_OUT_AUTO_WRBACK_CH4_S = 2 +const GDMA_OUT_LOOP_TEST_CH4_V = 0x1 +const GDMA_OUT_LOOP_TEST_CH4_S = 1 +const GDMA_OUT_RST_CH4_V = 0x1 +const GDMA_OUT_RST_CH4_S = 0 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH4 = 0x00000003 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH4_V = 0x3 +const GDMA_OUT_EXT_MEM_BK_SIZE_CH4_S = 13 +const GDMA_OUT_CHECK_OWNER_CH4_V = 0x1 +const GDMA_OUT_CHECK_OWNER_CH4_S = 12 +const GDMA_OUTFIFO_UDF_L3_CH4_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH4_INT_RAW_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH4_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH4_INT_RAW_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH4_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH4_INT_RAW_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW_S = 4 +const GDMA_OUT_TOTAL_EOF_CH4_INT_RAW_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH4_INT_RAW_S = 3 +const GDMA_OUT_DSCR_ERR_CH4_INT_RAW_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH4_INT_RAW_S = 2 +const GDMA_OUT_EOF_CH4_INT_RAW_V = 0x1 +const GDMA_OUT_EOF_CH4_INT_RAW_S = 1 +const GDMA_OUT_DONE_CH4_INT_RAW_V = 0x1 +const GDMA_OUT_DONE_CH4_INT_RAW_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH4_INT_ST_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH4_INT_ST_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH4_INT_ST_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH4_INT_ST_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH4_INT_ST_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH4_INT_ST_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH4_INT_ST_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH4_INT_ST_S = 4 +const GDMA_OUT_TOTAL_EOF_CH4_INT_ST_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH4_INT_ST_S = 3 +const GDMA_OUT_DSCR_ERR_CH4_INT_ST_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH4_INT_ST_S = 2 +const GDMA_OUT_EOF_CH4_INT_ST_V = 0x1 +const GDMA_OUT_EOF_CH4_INT_ST_S = 1 +const GDMA_OUT_DONE_CH4_INT_ST_V = 0x1 +const GDMA_OUT_DONE_CH4_INT_ST_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH4_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH4_INT_ENA_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH4_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH4_INT_ENA_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH4_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH4_INT_ENA_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH4_INT_ENA_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH4_INT_ENA_S = 4 +const GDMA_OUT_TOTAL_EOF_CH4_INT_ENA_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH4_INT_ENA_S = 3 +const GDMA_OUT_DSCR_ERR_CH4_INT_ENA_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH4_INT_ENA_S = 2 +const GDMA_OUT_EOF_CH4_INT_ENA_V = 0x1 +const GDMA_OUT_EOF_CH4_INT_ENA_S = 1 +const GDMA_OUT_DONE_CH4_INT_ENA_V = 0x1 +const GDMA_OUT_DONE_CH4_INT_ENA_S = 0 +const GDMA_OUTFIFO_UDF_L3_CH4_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_UDF_L3_CH4_INT_CLR_S = 7 +const GDMA_OUTFIFO_OVF_L3_CH4_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_OVF_L3_CH4_INT_CLR_S = 6 +const GDMA_OUTFIFO_UDF_L1_CH4_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_UDF_L1_CH4_INT_CLR_S = 5 +const GDMA_OUTFIFO_OVF_L1_CH4_INT_CLR_V = 0x1 +const GDMA_OUTFIFO_OVF_L1_CH4_INT_CLR_S = 4 +const GDMA_OUT_TOTAL_EOF_CH4_INT_CLR_V = 0x1 +const GDMA_OUT_TOTAL_EOF_CH4_INT_CLR_S = 3 +const GDMA_OUT_DSCR_ERR_CH4_INT_CLR_V = 0x1 +const GDMA_OUT_DSCR_ERR_CH4_INT_CLR_S = 2 +const GDMA_OUT_EOF_CH4_INT_CLR_V = 0x1 +const GDMA_OUT_EOF_CH4_INT_CLR_S = 1 +const GDMA_OUT_DONE_CH4_INT_CLR_V = 0x1 +const GDMA_OUT_DONE_CH4_INT_CLR_S = 0 +const GDMA_OUT_REMAIN_UNDER_4B_L3_CH4_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_4B_L3_CH4_S = 26 +const GDMA_OUT_REMAIN_UNDER_3B_L3_CH4_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_3B_L3_CH4_S = 25 +const GDMA_OUT_REMAIN_UNDER_2B_L3_CH4_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_2B_L3_CH4_S = 24 +const GDMA_OUT_REMAIN_UNDER_1B_L3_CH4_V = 0x1 +const GDMA_OUT_REMAIN_UNDER_1B_L3_CH4_S = 23 +const GDMA_OUTFIFO_CNT_L3_CH4 = 0x0000001F +const GDMA_OUTFIFO_CNT_L3_CH4_V = 0x1F +const GDMA_OUTFIFO_CNT_L3_CH4_S = 18 +const GDMA_OUTFIFO_CNT_L2_CH4 = 0x0000007F +const GDMA_OUTFIFO_CNT_L2_CH4_V = 0x7F +const GDMA_OUTFIFO_CNT_L2_CH4_S = 11 +const GDMA_OUTFIFO_CNT_L1_CH4 = 0x0000001F +const GDMA_OUTFIFO_CNT_L1_CH4_V = 0x1F +const GDMA_OUTFIFO_CNT_L1_CH4_S = 6 +const GDMA_OUTFIFO_EMPTY_L3_CH4_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L3_CH4_S = 5 +const GDMA_OUTFIFO_FULL_L3_CH4_V = 0x1 +const GDMA_OUTFIFO_FULL_L3_CH4_S = 4 +const GDMA_OUTFIFO_EMPTY_L2_CH4_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L2_CH4_S = 3 +const GDMA_OUTFIFO_FULL_L2_CH4_V = 0x1 +const GDMA_OUTFIFO_FULL_L2_CH4_S = 2 +const GDMA_OUTFIFO_EMPTY_L1_CH4_V = 0x1 +const GDMA_OUTFIFO_EMPTY_L1_CH4_S = 1 +const GDMA_OUTFIFO_FULL_L1_CH4_V = 0x1 +const GDMA_OUTFIFO_FULL_L1_CH4_S = 0 +const GDMA_OUTFIFO_PUSH_CH4_V = 0x1 +const GDMA_OUTFIFO_PUSH_CH4_S = 9 +const GDMA_OUTFIFO_WDATA_CH4 = 0x000001FF +const GDMA_OUTFIFO_WDATA_CH4_V = 0x1FF +const GDMA_OUTFIFO_WDATA_CH4_S = 0 +const GDMA_OUTLINK_PARK_CH4_V = 0x1 +const GDMA_OUTLINK_PARK_CH4_S = 23 +const GDMA_OUTLINK_RESTART_CH4_V = 0x1 +const GDMA_OUTLINK_RESTART_CH4_S = 22 +const GDMA_OUTLINK_START_CH4_V = 0x1 +const GDMA_OUTLINK_START_CH4_S = 21 +const GDMA_OUTLINK_STOP_CH4_V = 0x1 +const GDMA_OUTLINK_STOP_CH4_S = 20 +const GDMA_OUTLINK_ADDR_CH4 = 0x000FFFFF +const GDMA_OUTLINK_ADDR_CH4_V = 0xFFFFF +const GDMA_OUTLINK_ADDR_CH4_S = 0 +const GDMA_OUT_STATE_CH4 = 0x00000007 +const GDMA_OUT_STATE_CH4_V = 0x7 +const GDMA_OUT_STATE_CH4_S = 20 +const GDMA_OUT_DSCR_STATE_CH4 = 0x00000003 +const GDMA_OUT_DSCR_STATE_CH4_V = 0x3 +const GDMA_OUT_DSCR_STATE_CH4_S = 18 +const GDMA_OUTLINK_DSCR_ADDR_CH4 = 0x0003FFFF +const GDMA_OUTLINK_DSCR_ADDR_CH4_V = 0x3FFFF +const GDMA_OUTLINK_DSCR_ADDR_CH4_S = 0 +const GDMA_OUT_EOF_DES_ADDR_CH4 = 0xFFFFFFFF +const GDMA_OUT_EOF_DES_ADDR_CH4_V = 0xFFFFFFFF +const GDMA_OUT_EOF_DES_ADDR_CH4_S = 0 +const GDMA_OUT_EOF_BFR_DES_ADDR_CH4 = 0xFFFFFFFF +const GDMA_OUT_EOF_BFR_DES_ADDR_CH4_V = 0xFFFFFFFF +const GDMA_OUT_EOF_BFR_DES_ADDR_CH4_S = 0 +const GDMA_OUTLINK_DSCR_CH4 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_CH4_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_CH4_S = 0 +const GDMA_OUTLINK_DSCR_BF0_CH4 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF0_CH4_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF0_CH4_S = 0 +const GDMA_OUTLINK_DSCR_BF1_CH4 = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF1_CH4_V = 0xFFFFFFFF +const GDMA_OUTLINK_DSCR_BF1_CH4_S = 0 +const GDMA_TX_WEIGHT_CH4 = 0x0000000F +const GDMA_TX_WEIGHT_CH4_V = 0xF +const GDMA_TX_WEIGHT_CH4_S = 8 +const GDMA_TX_PRI_CH4 = 0x0000000F +const GDMA_TX_PRI_CH4_V = 0xF +const GDMA_TX_PRI_CH4_S = 0 +const GDMA_PERI_OUT_SEL_CH4 = 0x0000003F +const GDMA_PERI_OUT_SEL_CH4_V = 0x3F +const GDMA_PERI_OUT_SEL_CH4_S = 0 +const GDMA_AHB_TESTADDR = 0x00000003 +const GDMA_AHB_TESTADDR_V = 0x3 +const GDMA_AHB_TESTADDR_S = 4 +const GDMA_AHB_TESTMODE = 0x00000007 +const GDMA_AHB_TESTMODE_V = 0x7 +const GDMA_AHB_TESTMODE_S = 0 +const GDMA_DMA_RAM_CLK_FO_V = 0x1 +const GDMA_DMA_RAM_CLK_FO_S = 6 +const GDMA_DMA_RAM_FORCE_PU_V = 0x1 +const GDMA_DMA_RAM_FORCE_PU_S = 5 +const GDMA_DMA_RAM_FORCE_PD_V = 0x1 +const GDMA_DMA_RAM_FORCE_PD_S = 4 +const GDMA_CLK_EN_V = 0x1 +const GDMA_CLK_EN_S = 4 +const GDMA_ARB_PRI_DIS_V = 0x1 +const GDMA_ARB_PRI_DIS_S = 2 +const GDMA_AHBM_RST_EXTER_V = 0x1 +const GDMA_AHBM_RST_EXTER_S = 1 +const GDMA_AHBM_RST_INTER_V = 0x1 +const GDMA_AHBM_RST_INTER_S = 0 +const GDMA_IN_SIZE_CH0 = 0x0000007F +const GDMA_IN_SIZE_CH0_V = 0x7F +const GDMA_IN_SIZE_CH0_S = 0 +const GDMA_OUT_SIZE_CH0 = 0x0000007F +const GDMA_OUT_SIZE_CH0_V = 0x7F +const GDMA_OUT_SIZE_CH0_S = 0 +const GDMA_IN_SIZE_CH1 = 0x0000007F +const GDMA_IN_SIZE_CH1_V = 0x7F +const GDMA_IN_SIZE_CH1_S = 0 +const GDMA_OUT_SIZE_CH1 = 0x0000007F +const GDMA_OUT_SIZE_CH1_V = 0x7F +const GDMA_OUT_SIZE_CH1_S = 0 +const GDMA_IN_SIZE_CH2 = 0x0000007F +const GDMA_IN_SIZE_CH2_V = 0x7F +const GDMA_IN_SIZE_CH2_S = 0 +const GDMA_OUT_SIZE_CH2 = 0x0000007F +const GDMA_OUT_SIZE_CH2_V = 0x7F +const GDMA_OUT_SIZE_CH2_S = 0 +const GDMA_IN_SIZE_CH3 = 0x0000007F +const GDMA_IN_SIZE_CH3_V = 0x7F +const GDMA_IN_SIZE_CH3_S = 0 +const GDMA_OUT_SIZE_CH3 = 0x0000007F +const GDMA_OUT_SIZE_CH3_V = 0x7F +const GDMA_OUT_SIZE_CH3_S = 0 +const GDMA_IN_SIZE_CH4 = 0x0000007F +const GDMA_IN_SIZE_CH4_V = 0x7F +const GDMA_IN_SIZE_CH4_S = 0 +const GDMA_OUT_SIZE_CH4 = 0x0000007F +const GDMA_OUT_SIZE_CH4_V = 0x7F +const GDMA_OUT_SIZE_CH4_S = 0 +const GDMA_EXTMEM_REJECT_ADDR = 0xFFFFFFFF +const GDMA_EXTMEM_REJECT_ADDR_V = 0xFFFFFFFF +const GDMA_EXTMEM_REJECT_ADDR_S = 0 +const GDMA_EXTMEM_REJECT_PERI_NUM = 0x0000003F +const GDMA_EXTMEM_REJECT_PERI_NUM_V = 0x3F +const GDMA_EXTMEM_REJECT_PERI_NUM_S = 6 +const GDMA_EXTMEM_REJECT_CHANNEL_NUM = 0x0000000F +const GDMA_EXTMEM_REJECT_CHANNEL_NUM_V = 0xF +const GDMA_EXTMEM_REJECT_CHANNEL_NUM_S = 2 +const GDMA_EXTMEM_REJECT_ATTR = 0x00000003 +const GDMA_EXTMEM_REJECT_ATTR_V = 0x3 +const GDMA_EXTMEM_REJECT_ATTR_S = 0 +const GDMA_EXTMEM_REJECT_INT_RAW_V = 0x1 +const GDMA_EXTMEM_REJECT_INT_RAW_S = 0 +const GDMA_EXTMEM_REJECT_INT_ST_V = 0x1 +const GDMA_EXTMEM_REJECT_INT_ST_S = 0 +const GDMA_EXTMEM_REJECT_INT_ENA_V = 0x1 +const GDMA_EXTMEM_REJECT_INT_ENA_S = 0 +const GDMA_EXTMEM_REJECT_INT_CLR_V = 0x1 +const GDMA_EXTMEM_REJECT_INT_CLR_S = 0 +const GDMA_DATE = 0xFFFFFFFF +const GDMA_DATE_V = 0xFFFFFFFF +const GDMA_DATE_S = 0 diff --git a/esp32/gdma_sleep_retention.go b/esp32/gdma_sleep_retention.go new file mode 100644 index 00000000..22ff2034 --- /dev/null +++ b/esp32/gdma_sleep_retention.go @@ -0,0 +1,28 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Initialize GDMA channel retention link for powerdown the TOP powerdomain during lightsleep + * @param group_id Group id + * @param pair_id Pair id + * @return + * - ESP_OK: Create DMA retention link successfully + * - ESP_ERR_NO_MEM: Create DMA retention link failed because out of memory + */ +//go:linkname GdmaSleepRetentionInit C.gdma_sleep_retention_init +func GdmaSleepRetentionInit(group_id c.Int, pair_id c.Int) EspErrT + +/** + * Destroy GDMA channel retention link + * @param group_id Group id + * @param pair_id Pair id + * @return + * - ESP_OK: GDMA channel retention link destrory successfully + * - ESP_ERR_INVALID_STATE: GDMA channel retention link not create yet + */ +//go:linkname GdmaSleepRetentionDeinit C.gdma_sleep_retention_deinit +func GdmaSleepRetentionDeinit(group_id c.Int, pair_id c.Int) EspErrT diff --git a/esp32/gdma_struct.go b/esp32/gdma_struct.go new file mode 100644 index 00000000..e9248ff9 --- /dev/null +++ b/esp32/gdma_struct.go @@ -0,0 +1,150 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type GdmaDevS struct { + Channel [5]struct { + In struct { + Conf0 struct { + Val c.Uint32T + } + Conf1 struct { + Val c.Uint32T + } + IntRaw struct { + Val c.Uint32T + } + IntSt struct { + Val c.Uint32T + } + IntEna struct { + Val c.Uint32T + } + IntClr struct { + Val c.Uint32T + } + InfifoStatus struct { + Val c.Uint32T + } + Pop struct { + Val c.Uint32T + } + Link struct { + Val c.Uint32T + } + State struct { + Val c.Uint32T + } + SucEofDesAddr c.Uint32T + ErrEofDesAddr c.Uint32T + Dscr c.Uint32T + DscrBf0 c.Uint32T + DscrBf1 c.Uint32T + Weight struct { + Val c.Uint32T + } + Reserved40 c.Uint32T + Pri struct { + Val c.Uint32T + } + PeriSel struct { + Val c.Uint32T + } + Reserved4c c.Uint32T + Reserved50 c.Uint32T + Reserved54 c.Uint32T + Reserved58 c.Uint32T + Reserved5c c.Uint32T + } + Out struct { + Conf0 struct { + Val c.Uint32T + } + Conf1 struct { + Val c.Uint32T + } + IntRaw struct { + Val c.Uint32T + } + IntSt struct { + Val c.Uint32T + } + IntEna struct { + Val c.Uint32T + } + IntClr struct { + Val c.Uint32T + } + OutfifoStatus struct { + Val c.Uint32T + } + Push struct { + Val c.Uint32T + } + Link struct { + Val c.Uint32T + } + State struct { + Val c.Uint32T + } + EofDesAddr c.Uint32T + EofBfrDesAddr c.Uint32T + Dscr c.Uint32T + DscrBf0 c.Uint32T + DscrBf1 c.Uint32T + Weight struct { + Val c.Uint32T + } + ReservedA0 c.Uint32T + Pri struct { + Val c.Uint32T + } + PeriSel struct { + Val c.Uint32T + } + ReservedAc c.Uint32T + ReservedB0 c.Uint32T + ReservedB4 c.Uint32T + ReservedB8 c.Uint32T + ReservedBc c.Uint32T + } + } + AhbTest struct { + Val c.Uint32T + } + PdConf struct { + Val c.Uint32T + } + MiscConf struct { + Val c.Uint32T + } + SramSize [5]struct { + In struct { + Val c.Uint32T + } + Out struct { + Val c.Uint32T + } + } + ExtmemRejectAddr c.Uint32T + ExtmemRejectSt struct { + Val c.Uint32T + } + ExtmemRejectIntRaw struct { + Val c.Uint32T + } + ExtmemRejectIntSt struct { + Val c.Uint32T + } + ExtmemRejectIntEna struct { + Val c.Uint32T + } + ExtmemRejectIntClr struct { + Val c.Uint32T + } + Date c.Uint32T +} +type GdmaDevT GdmaDevS diff --git a/esp32/gdma_types.go b/esp32/gdma_types.go new file mode 100644 index 00000000..b0295af3 --- /dev/null +++ b/esp32/gdma_types.go @@ -0,0 +1,45 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type GdmaTriggerPeripheralT c.Int + +const ( + GDMA_TRIG_PERIPH_M2M GdmaTriggerPeripheralT = 0 + GDMA_TRIG_PERIPH_UHCI GdmaTriggerPeripheralT = 1 + GDMA_TRIG_PERIPH_SPI GdmaTriggerPeripheralT = 2 + GDMA_TRIG_PERIPH_I2S GdmaTriggerPeripheralT = 3 + GDMA_TRIG_PERIPH_AES GdmaTriggerPeripheralT = 4 + GDMA_TRIG_PERIPH_SHA GdmaTriggerPeripheralT = 5 + GDMA_TRIG_PERIPH_ADC GdmaTriggerPeripheralT = 6 + GDMA_TRIG_PERIPH_DAC GdmaTriggerPeripheralT = 7 + GDMA_TRIG_PERIPH_LCD GdmaTriggerPeripheralT = 8 + GDMA_TRIG_PERIPH_CAM GdmaTriggerPeripheralT = 9 + GDMA_TRIG_PERIPH_RMT GdmaTriggerPeripheralT = 10 + GDMA_TRIG_PERIPH_PARLIO GdmaTriggerPeripheralT = 11 + GDMA_TRIG_PERIPH_I3C GdmaTriggerPeripheralT = 12 +) + +type GdmaChannelDirectionT c.Int + +const ( + GDMA_CHANNEL_DIRECTION_TX GdmaChannelDirectionT = 0 + GDMA_CHANNEL_DIRECTION_RX GdmaChannelDirectionT = 1 +) + +type GdmaEtmEventTypeT c.Int + +const ( + GDMA_ETM_EVENT_EOF GdmaEtmEventTypeT = 0 + GDMA_ETM_EVENT_MAX GdmaEtmEventTypeT = 1 +) + +type GdmaEtmTaskTypeT c.Int + +const ( + GDMA_ETM_TASK_START GdmaEtmTaskTypeT = 0 + GDMA_ETM_TASK_MAX GdmaEtmTaskTypeT = 1 +) diff --git a/esp32/glitch_filter_types.go b/esp32/glitch_filter_types.go new file mode 100644 index 00000000..b52e6946 --- /dev/null +++ b/esp32/glitch_filter_types.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +type GlitchFilterClockSourceT SocPeriphGlitchFilterClkSrcT diff --git a/esp32/go.mod b/esp32/go.mod new file mode 100644 index 00000000..6622c18d --- /dev/null +++ b/esp32/go.mod @@ -0,0 +1,5 @@ +module freertos + +go 1.23.4 + +require github.com/goplus/lib v0.2.0 diff --git a/esp32/go.sum b/esp32/go.sum new file mode 100644 index 00000000..512980a5 --- /dev/null +++ b/esp32/go.sum @@ -0,0 +1,2 @@ +github.com/goplus/lib v0.2.0 h1:AjqkN1XK5H23wZMMlpaUYAMCDAdSBQ2NMFrLtSh7W4g= +github.com/goplus/lib v0.2.0/go.mod h1:SgJv3oPqLLHCu0gcL46ejOP3x7/2ry2Jtxu7ta32kp0= diff --git a/esp32/gpio.go b/esp32/gpio.go new file mode 100644 index 00000000..561bc06d --- /dev/null +++ b/esp32/gpio.go @@ -0,0 +1,189 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const GPIO_ID_PIN0 = 0 +const GPIO_FUNC_IN_HIGH = 0x38 +const GPIO_FUNC_IN_LOW = 0x3C + +type GPIOINTTYPE c.Int + +const ( + GPIO_PIN_INTR_DISABLE GPIOINTTYPE = 0 + GPIO_PIN_INTR_POSEDGE GPIOINTTYPE = 1 + GPIO_PIN_INTR_NEGEDGE GPIOINTTYPE = 2 + GPIO_PIN_INTR_ANYEDGE GPIOINTTYPE = 3 + GPIO_PIN_INTR_LOLEVEL GPIOINTTYPE = 4 + GPIO_PIN_INTR_HILEVEL GPIOINTTYPE = 5 +) + +/** + * @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0). + * There is no particular ordering guaranteed; so if the order of writes is significant, + * calling code should divide a single call into multiple calls. + * + * @param uint32_t set_mask : the gpios that need high level. + * + * @param uint32_t clear_mask : the gpios that need low level. + * + * @param uint32_t enable_mask : the gpios that need be changed. + * + * @param uint32_t disable_mask : the gpios that need disable output. + * + * @return None + */ +//go:linkname GpioOutputSet C.gpio_output_set +func GpioOutputSet(set_mask c.Uint32T, clear_mask c.Uint32T, enable_mask c.Uint32T, disable_mask c.Uint32T) + +/** + * @brief Sample the value of GPIO input pins(0-31) and returns a bitmask. + * + * @param None + * + * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0. + */ +//go:linkname GpioInputGet C.gpio_input_get +func GpioInputGet() c.Uint32T + +/** + * @brief Set GPIO to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param uint32_t i: gpio number. + * + * @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used + * + * @return None + */ +//go:linkname GpioPinWakeupEnable C.gpio_pin_wakeup_enable +func GpioPinWakeupEnable(i c.Uint32T, intr_state GPIOINTTYPE) + +/** + * @brief disable GPIOs to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +//go:linkname GpioPinWakeupDisable C.gpio_pin_wakeup_disable +func GpioPinWakeupDisable() + +/** + * @brief set gpio input to a signal, one gpio can input to several signals. + * + * @param uint32_t gpio : gpio number, 0~0x2f + * gpio == 0x3C, input 0 to signal + * gpio == 0x3A, input nothing to signal + * gpio == 0x38, input 1 to signal + * + * @param uint32_t signal_idx : signal index. + * + * @param bool inv : the signal is inv or not + * + * @return None + */ +//go:linkname GpioMatrixIn C.gpio_matrix_in +func GpioMatrixIn(gpio c.Uint32T, signal_idx c.Uint32T, inv bool) + +/** + * @brief set signal output to gpio, one signal can output to several gpios. + * + * @param uint32_t gpio : gpio number, 0~0x2f + * + * @param uint32_t signal_idx : signal index. + * signal_idx == 0x100, cancel output put to the gpio + * + * @param bool out_inv : the signal output is invert or not + * + * @param bool oen_inv : the signal output enable is invert or not + * + * @return None + */ +//go:linkname GpioMatrixOut C.gpio_matrix_out +func GpioMatrixOut(gpio c.Uint32T, signal_idx c.Uint32T, out_inv bool, oen_inv bool) + +/** + * @brief Select pad as a gpio function from IOMUX. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +//go:linkname GpioPadSelectGpio C.gpio_pad_select_gpio +func GpioPadSelectGpio(gpio_num c.Uint32T) + +/** + * @brief Set pad driver capability. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @param uint32_t drv : 0-3 + * + * @return None + */ +//go:linkname GpioPadSetDrv C.gpio_pad_set_drv +func GpioPadSetDrv(gpio_num c.Uint32T, drv c.Uint32T) + +/** + * @brief Pull up the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +//go:linkname GpioPadPullup C.gpio_pad_pullup +func GpioPadPullup(gpio_num c.Uint32T) + +/** + * @brief Pull down the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +//go:linkname GpioPadPulldown C.gpio_pad_pulldown +func GpioPadPulldown(gpio_num c.Uint32T) + +/** + * @brief Unhold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +//go:linkname GpioPadUnhold C.gpio_pad_unhold +func GpioPadUnhold(gpio_num c.Uint32T) + +/** + * @brief Hold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +//go:linkname GpioPadHold C.gpio_pad_hold +func GpioPadHold(gpio_num c.Uint32T) + +/** + * @brief enable gpio pad input. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +//go:linkname GpioPadInputEnable C.gpio_pad_input_enable +func GpioPadInputEnable(gpio_num c.Uint32T) + +/** + * @brief disable gpio pad input. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +//go:linkname GpioPadInputDisable C.gpio_pad_input_disable +func GpioPadInputDisable(gpio_num c.Uint32T) diff --git a/esp32/gpio_hal.go b/esp32/gpio_hal.go new file mode 100644 index 00000000..98af2bcb --- /dev/null +++ b/esp32/gpio_hal.go @@ -0,0 +1,46 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Context that should be maintained by both the driver and the HAL + */ + +type GpioHalContextT struct { + Dev *GpioDevT +} + +/** + * @brief Enable GPIO module interrupt signal + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param core_id Interrupt enabled CPU to corresponding ID + */ +// llgo:link (*GpioHalContextT).GpioHalIntrEnableOnCore C.gpio_hal_intr_enable_on_core +func (recv_ *GpioHalContextT) GpioHalIntrEnableOnCore(gpio_num c.Uint32T, core_id c.Uint32T) { +} + +/** + * @brief Disable GPIO module interrupt signal + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +// llgo:link (*GpioHalContextT).GpioHalIntrDisable C.gpio_hal_intr_disable +func (recv_ *GpioHalContextT) GpioHalIntrDisable(gpio_num c.Uint32T) { +} + +/** + * @brief Helper function to disconnect internal circuits from an GPIO in sleep mode. + * This function disables input, output, pullup, pulldown for an GPIO in sleep mode. + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number + */ +// llgo:link (*GpioHalContextT).GpioHalIsolateInSleep C.gpio_hal_isolate_in_sleep +func (recv_ *GpioHalContextT) GpioHalIsolateInSleep(gpio_num c.Uint32T) { +} diff --git a/esp32/gpio_ll.go b/esp32/gpio_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/gpio_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/gpio_num.go b/esp32/gpio_num.go new file mode 100644 index 00000000..b2eea667 --- /dev/null +++ b/esp32/gpio_num.go @@ -0,0 +1,58 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type GpioNumT c.Int + +const ( + GPIO_NUM_NC GpioNumT = -1 + GPIO_NUM_0 GpioNumT = 0 + GPIO_NUM_1 GpioNumT = 1 + GPIO_NUM_2 GpioNumT = 2 + GPIO_NUM_3 GpioNumT = 3 + GPIO_NUM_4 GpioNumT = 4 + GPIO_NUM_5 GpioNumT = 5 + GPIO_NUM_6 GpioNumT = 6 + GPIO_NUM_7 GpioNumT = 7 + GPIO_NUM_8 GpioNumT = 8 + GPIO_NUM_9 GpioNumT = 9 + GPIO_NUM_10 GpioNumT = 10 + GPIO_NUM_11 GpioNumT = 11 + GPIO_NUM_12 GpioNumT = 12 + GPIO_NUM_13 GpioNumT = 13 + GPIO_NUM_14 GpioNumT = 14 + GPIO_NUM_15 GpioNumT = 15 + GPIO_NUM_16 GpioNumT = 16 + GPIO_NUM_17 GpioNumT = 17 + GPIO_NUM_18 GpioNumT = 18 + GPIO_NUM_19 GpioNumT = 19 + GPIO_NUM_20 GpioNumT = 20 + GPIO_NUM_21 GpioNumT = 21 + GPIO_NUM_26 GpioNumT = 26 + GPIO_NUM_27 GpioNumT = 27 + GPIO_NUM_28 GpioNumT = 28 + GPIO_NUM_29 GpioNumT = 29 + GPIO_NUM_30 GpioNumT = 30 + GPIO_NUM_31 GpioNumT = 31 + GPIO_NUM_32 GpioNumT = 32 + GPIO_NUM_33 GpioNumT = 33 + GPIO_NUM_34 GpioNumT = 34 + GPIO_NUM_35 GpioNumT = 35 + GPIO_NUM_36 GpioNumT = 36 + GPIO_NUM_37 GpioNumT = 37 + GPIO_NUM_38 GpioNumT = 38 + GPIO_NUM_39 GpioNumT = 39 + GPIO_NUM_40 GpioNumT = 40 + GPIO_NUM_41 GpioNumT = 41 + GPIO_NUM_42 GpioNumT = 42 + GPIO_NUM_43 GpioNumT = 43 + GPIO_NUM_44 GpioNumT = 44 + GPIO_NUM_45 GpioNumT = 45 + GPIO_NUM_46 GpioNumT = 46 + GPIO_NUM_47 GpioNumT = 47 + GPIO_NUM_48 GpioNumT = 48 + GPIO_NUM_MAX GpioNumT = 49 +) diff --git a/esp32/gpio_pins.go b/esp32/gpio_pins.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/gpio_pins.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/gpio_reg.go b/esp32/gpio_reg.go new file mode 100644 index 00000000..ef89803d --- /dev/null +++ b/esp32/gpio_reg.go @@ -0,0 +1,3420 @@ +package freertos + +import _ "unsafe" + +const GPIO_PIN_CONFIG_MSB = 12 +const GPIO_PIN_CONFIG_LSB = 11 +const GPIO_PIN_CONFIG_MASK = 0x00001800 +const GPIO_WAKEUP_ENABLE = 1 +const GPIO_PIN_WAKEUP_ENABLE_MSB = 10 +const GPIO_PIN_WAKEUP_ENABLE_LSB = 10 +const GPIO_PIN_WAKEUP_ENABLE_MASK = 0x00000400 +const GPIO_PIN_INT_TYPE_MASK = 0x380 +const GPIO_PIN_INT_TYPE_MSB = 9 +const GPIO_PIN_INT_TYPE_LSB = 7 +const GPIO_PAD_DRIVER_ENABLE = 1 +const GPIO_PIN_PAD_DRIVER_MSB = 2 +const GPIO_PIN_PAD_DRIVER_LSB = 2 +const GPIO_PIN_PAD_DRIVER_MASK = 0x00000004 +const GPIO_BT_SEL = 0xFFFFFFFF +const GPIO_BT_SEL_V = 0xFFFFFFFF +const GPIO_BT_SEL_S = 0 +const GPIO_OUT_DATA = 0xFFFFFFFF +const GPIO_OUT_DATA_V = 0xFFFFFFFF +const GPIO_OUT_DATA_S = 0 +const GPIO_OUT_W1TS = 0xFFFFFFFF +const GPIO_OUT_W1TS_V = 0xFFFFFFFF +const GPIO_OUT_W1TS_S = 0 +const GPIO_OUT_W1TC = 0xFFFFFFFF +const GPIO_OUT_W1TC_V = 0xFFFFFFFF +const GPIO_OUT_W1TC_S = 0 +const GPIO_OUT1_DATA = 0x003FFFFF +const GPIO_OUT1_DATA_V = 0x3FFFFF +const GPIO_OUT1_DATA_S = 0 +const GPIO_OUT1_W1TS = 0x003FFFFF +const GPIO_OUT1_W1TS_V = 0x3FFFFF +const GPIO_OUT1_W1TS_S = 0 +const GPIO_OUT1_W1TC = 0x003FFFFF +const GPIO_OUT1_W1TC_V = 0x3FFFFF +const GPIO_OUT1_W1TC_S = 0 +const GPIO_SDIO_SEL = 0x000000FF +const GPIO_SDIO_SEL_V = 0xFF +const GPIO_SDIO_SEL_S = 0 +const GPIO_ENABLE_DATA = 0xFFFFFFFF +const GPIO_ENABLE_DATA_V = 0xFFFFFFFF +const GPIO_ENABLE_DATA_S = 0 +const GPIO_ENABLE_W1TS = 0xFFFFFFFF +const GPIO_ENABLE_W1TS_V = 0xFFFFFFFF +const GPIO_ENABLE_W1TS_S = 0 +const GPIO_ENABLE_W1TC = 0xFFFFFFFF +const GPIO_ENABLE_W1TC_V = 0xFFFFFFFF +const GPIO_ENABLE_W1TC_S = 0 +const GPIO_ENABLE1_DATA = 0x003FFFFF +const GPIO_ENABLE1_DATA_V = 0x3FFFFF +const GPIO_ENABLE1_DATA_S = 0 +const GPIO_ENABLE1_W1TS = 0x003FFFFF +const GPIO_ENABLE1_W1TS_V = 0x3FFFFF +const GPIO_ENABLE1_W1TS_S = 0 +const GPIO_ENABLE1_W1TC = 0x003FFFFF +const GPIO_ENABLE1_W1TC_V = 0x3FFFFF +const GPIO_ENABLE1_W1TC_S = 0 +const GPIO_STRAPPING = 0x0000FFFF +const GPIO_STRAPPING_V = 0xFFFF +const GPIO_STRAPPING_S = 0 +const GPIO_IN_DATA = 0xFFFFFFFF +const GPIO_IN_DATA_V = 0xFFFFFFFF +const GPIO_IN_DATA_S = 0 +const GPIO_IN1_DATA = 0x003FFFFF +const GPIO_IN1_DATA_V = 0x3FFFFF +const GPIO_IN1_DATA_S = 0 +const GPIO_STATUS_INT = 0xFFFFFFFF +const GPIO_STATUS_INT_V = 0xFFFFFFFF +const GPIO_STATUS_INT_S = 0 +const GPIO_STATUS_W1TS = 0xFFFFFFFF +const GPIO_STATUS_W1TS_V = 0xFFFFFFFF +const GPIO_STATUS_W1TS_S = 0 +const GPIO_STATUS_W1TC = 0xFFFFFFFF +const GPIO_STATUS_W1TC_V = 0xFFFFFFFF +const GPIO_STATUS_W1TC_S = 0 +const GPIO_STATUS1_INT = 0x003FFFFF +const GPIO_STATUS1_INT_V = 0x3FFFFF +const GPIO_STATUS1_INT_S = 0 +const GPIO_STATUS1_W1TS = 0x003FFFFF +const GPIO_STATUS1_W1TS_V = 0x3FFFFF +const GPIO_STATUS1_W1TS_S = 0 +const GPIO_STATUS1_W1TC = 0x003FFFFF +const GPIO_STATUS1_W1TC_V = 0x3FFFFF +const GPIO_STATUS1_W1TC_S = 0 +const GPIO_PROCPU_INT = 0xFFFFFFFF +const GPIO_PROCPU_INT_V = 0xFFFFFFFF +const GPIO_PROCPU_INT_S = 0 +const GPIO_PROCPU_NMI_INT = 0xFFFFFFFF +const GPIO_PROCPU_NMI_INT_V = 0xFFFFFFFF +const GPIO_PROCPU_NMI_INT_S = 0 +const GPIO_SDIO_INT = 0xFFFFFFFF +const GPIO_SDIO_INT_V = 0xFFFFFFFF +const GPIO_SDIO_INT_S = 0 +const GPIO_PROCPU_INT_H = 0x003FFFFF +const GPIO_PROCPU_INT_H_V = 0x3FFFFF +const GPIO_PROCPU_INT_H_S = 0 +const GPIO_PROCPU_NMI_INT_H = 0x003FFFFF +const GPIO_PROCPU_NMI_INT_H_V = 0x3FFFFF +const GPIO_PROCPU_NMI_INT_H_S = 0 +const GPIO_SDIO_INT_H = 0x003FFFFF +const GPIO_SDIO_INT_H_V = 0x3FFFFF +const GPIO_SDIO_INT_H_S = 0 +const GPIO_PIN0_INT_ENA = 0x0000001F +const GPIO_PIN0_INT_ENA_V = 0x1F +const GPIO_PIN0_INT_ENA_S = 13 +const GPIO_PIN0_CONFIG = 0x00000003 +const GPIO_PIN0_CONFIG_V = 0x3 +const GPIO_PIN0_CONFIG_S = 11 +const GPIO_PIN0_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN0_WAKEUP_ENABLE_S = 10 +const GPIO_PIN0_INT_TYPE = 0x00000007 +const GPIO_PIN0_INT_TYPE_V = 0x7 +const GPIO_PIN0_INT_TYPE_S = 7 +const GPIO_PIN0_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN0_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN0_SYNC1_BYPASS_S = 3 +const GPIO_PIN0_PAD_DRIVER_V = 0x1 +const GPIO_PIN0_PAD_DRIVER_S = 2 +const GPIO_PIN0_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN0_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN0_SYNC2_BYPASS_S = 0 +const GPIO_PIN1_INT_ENA = 0x0000001F +const GPIO_PIN1_INT_ENA_V = 0x1F +const GPIO_PIN1_INT_ENA_S = 13 +const GPIO_PIN1_CONFIG = 0x00000003 +const GPIO_PIN1_CONFIG_V = 0x3 +const GPIO_PIN1_CONFIG_S = 11 +const GPIO_PIN1_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN1_WAKEUP_ENABLE_S = 10 +const GPIO_PIN1_INT_TYPE = 0x00000007 +const GPIO_PIN1_INT_TYPE_V = 0x7 +const GPIO_PIN1_INT_TYPE_S = 7 +const GPIO_PIN1_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN1_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN1_SYNC1_BYPASS_S = 3 +const GPIO_PIN1_PAD_DRIVER_V = 0x1 +const GPIO_PIN1_PAD_DRIVER_S = 2 +const GPIO_PIN1_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN1_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN1_SYNC2_BYPASS_S = 0 +const GPIO_PIN2_INT_ENA = 0x0000001F +const GPIO_PIN2_INT_ENA_V = 0x1F +const GPIO_PIN2_INT_ENA_S = 13 +const GPIO_PIN2_CONFIG = 0x00000003 +const GPIO_PIN2_CONFIG_V = 0x3 +const GPIO_PIN2_CONFIG_S = 11 +const GPIO_PIN2_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN2_WAKEUP_ENABLE_S = 10 +const GPIO_PIN2_INT_TYPE = 0x00000007 +const GPIO_PIN2_INT_TYPE_V = 0x7 +const GPIO_PIN2_INT_TYPE_S = 7 +const GPIO_PIN2_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN2_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN2_SYNC1_BYPASS_S = 3 +const GPIO_PIN2_PAD_DRIVER_V = 0x1 +const GPIO_PIN2_PAD_DRIVER_S = 2 +const GPIO_PIN2_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN2_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN2_SYNC2_BYPASS_S = 0 +const GPIO_PIN3_INT_ENA = 0x0000001F +const GPIO_PIN3_INT_ENA_V = 0x1F +const GPIO_PIN3_INT_ENA_S = 13 +const GPIO_PIN3_CONFIG = 0x00000003 +const GPIO_PIN3_CONFIG_V = 0x3 +const GPIO_PIN3_CONFIG_S = 11 +const GPIO_PIN3_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN3_WAKEUP_ENABLE_S = 10 +const GPIO_PIN3_INT_TYPE = 0x00000007 +const GPIO_PIN3_INT_TYPE_V = 0x7 +const GPIO_PIN3_INT_TYPE_S = 7 +const GPIO_PIN3_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN3_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN3_SYNC1_BYPASS_S = 3 +const GPIO_PIN3_PAD_DRIVER_V = 0x1 +const GPIO_PIN3_PAD_DRIVER_S = 2 +const GPIO_PIN3_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN3_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN3_SYNC2_BYPASS_S = 0 +const GPIO_PIN4_INT_ENA = 0x0000001F +const GPIO_PIN4_INT_ENA_V = 0x1F +const GPIO_PIN4_INT_ENA_S = 13 +const GPIO_PIN4_CONFIG = 0x00000003 +const GPIO_PIN4_CONFIG_V = 0x3 +const GPIO_PIN4_CONFIG_S = 11 +const GPIO_PIN4_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN4_WAKEUP_ENABLE_S = 10 +const GPIO_PIN4_INT_TYPE = 0x00000007 +const GPIO_PIN4_INT_TYPE_V = 0x7 +const GPIO_PIN4_INT_TYPE_S = 7 +const GPIO_PIN4_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN4_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN4_SYNC1_BYPASS_S = 3 +const GPIO_PIN4_PAD_DRIVER_V = 0x1 +const GPIO_PIN4_PAD_DRIVER_S = 2 +const GPIO_PIN4_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN4_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN4_SYNC2_BYPASS_S = 0 +const GPIO_PIN5_INT_ENA = 0x0000001F +const GPIO_PIN5_INT_ENA_V = 0x1F +const GPIO_PIN5_INT_ENA_S = 13 +const GPIO_PIN5_CONFIG = 0x00000003 +const GPIO_PIN5_CONFIG_V = 0x3 +const GPIO_PIN5_CONFIG_S = 11 +const GPIO_PIN5_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN5_WAKEUP_ENABLE_S = 10 +const GPIO_PIN5_INT_TYPE = 0x00000007 +const GPIO_PIN5_INT_TYPE_V = 0x7 +const GPIO_PIN5_INT_TYPE_S = 7 +const GPIO_PIN5_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN5_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN5_SYNC1_BYPASS_S = 3 +const GPIO_PIN5_PAD_DRIVER_V = 0x1 +const GPIO_PIN5_PAD_DRIVER_S = 2 +const GPIO_PIN5_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN5_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN5_SYNC2_BYPASS_S = 0 +const GPIO_PIN6_INT_ENA = 0x0000001F +const GPIO_PIN6_INT_ENA_V = 0x1F +const GPIO_PIN6_INT_ENA_S = 13 +const GPIO_PIN6_CONFIG = 0x00000003 +const GPIO_PIN6_CONFIG_V = 0x3 +const GPIO_PIN6_CONFIG_S = 11 +const GPIO_PIN6_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN6_WAKEUP_ENABLE_S = 10 +const GPIO_PIN6_INT_TYPE = 0x00000007 +const GPIO_PIN6_INT_TYPE_V = 0x7 +const GPIO_PIN6_INT_TYPE_S = 7 +const GPIO_PIN6_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN6_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN6_SYNC1_BYPASS_S = 3 +const GPIO_PIN6_PAD_DRIVER_V = 0x1 +const GPIO_PIN6_PAD_DRIVER_S = 2 +const GPIO_PIN6_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN6_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN6_SYNC2_BYPASS_S = 0 +const GPIO_PIN7_INT_ENA = 0x0000001F +const GPIO_PIN7_INT_ENA_V = 0x1F +const GPIO_PIN7_INT_ENA_S = 13 +const GPIO_PIN7_CONFIG = 0x00000003 +const GPIO_PIN7_CONFIG_V = 0x3 +const GPIO_PIN7_CONFIG_S = 11 +const GPIO_PIN7_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN7_WAKEUP_ENABLE_S = 10 +const GPIO_PIN7_INT_TYPE = 0x00000007 +const GPIO_PIN7_INT_TYPE_V = 0x7 +const GPIO_PIN7_INT_TYPE_S = 7 +const GPIO_PIN7_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN7_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN7_SYNC1_BYPASS_S = 3 +const GPIO_PIN7_PAD_DRIVER_V = 0x1 +const GPIO_PIN7_PAD_DRIVER_S = 2 +const GPIO_PIN7_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN7_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN7_SYNC2_BYPASS_S = 0 +const GPIO_PIN8_INT_ENA = 0x0000001F +const GPIO_PIN8_INT_ENA_V = 0x1F +const GPIO_PIN8_INT_ENA_S = 13 +const GPIO_PIN8_CONFIG = 0x00000003 +const GPIO_PIN8_CONFIG_V = 0x3 +const GPIO_PIN8_CONFIG_S = 11 +const GPIO_PIN8_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN8_WAKEUP_ENABLE_S = 10 +const GPIO_PIN8_INT_TYPE = 0x00000007 +const GPIO_PIN8_INT_TYPE_V = 0x7 +const GPIO_PIN8_INT_TYPE_S = 7 +const GPIO_PIN8_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN8_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN8_SYNC1_BYPASS_S = 3 +const GPIO_PIN8_PAD_DRIVER_V = 0x1 +const GPIO_PIN8_PAD_DRIVER_S = 2 +const GPIO_PIN8_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN8_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN8_SYNC2_BYPASS_S = 0 +const GPIO_PIN9_INT_ENA = 0x0000001F +const GPIO_PIN9_INT_ENA_V = 0x1F +const GPIO_PIN9_INT_ENA_S = 13 +const GPIO_PIN9_CONFIG = 0x00000003 +const GPIO_PIN9_CONFIG_V = 0x3 +const GPIO_PIN9_CONFIG_S = 11 +const GPIO_PIN9_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN9_WAKEUP_ENABLE_S = 10 +const GPIO_PIN9_INT_TYPE = 0x00000007 +const GPIO_PIN9_INT_TYPE_V = 0x7 +const GPIO_PIN9_INT_TYPE_S = 7 +const GPIO_PIN9_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN9_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN9_SYNC1_BYPASS_S = 3 +const GPIO_PIN9_PAD_DRIVER_V = 0x1 +const GPIO_PIN9_PAD_DRIVER_S = 2 +const GPIO_PIN9_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN9_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN9_SYNC2_BYPASS_S = 0 +const GPIO_PIN10_INT_ENA = 0x0000001F +const GPIO_PIN10_INT_ENA_V = 0x1F +const GPIO_PIN10_INT_ENA_S = 13 +const GPIO_PIN10_CONFIG = 0x00000003 +const GPIO_PIN10_CONFIG_V = 0x3 +const GPIO_PIN10_CONFIG_S = 11 +const GPIO_PIN10_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN10_WAKEUP_ENABLE_S = 10 +const GPIO_PIN10_INT_TYPE = 0x00000007 +const GPIO_PIN10_INT_TYPE_V = 0x7 +const GPIO_PIN10_INT_TYPE_S = 7 +const GPIO_PIN10_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN10_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN10_SYNC1_BYPASS_S = 3 +const GPIO_PIN10_PAD_DRIVER_V = 0x1 +const GPIO_PIN10_PAD_DRIVER_S = 2 +const GPIO_PIN10_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN10_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN10_SYNC2_BYPASS_S = 0 +const GPIO_PIN11_INT_ENA = 0x0000001F +const GPIO_PIN11_INT_ENA_V = 0x1F +const GPIO_PIN11_INT_ENA_S = 13 +const GPIO_PIN11_CONFIG = 0x00000003 +const GPIO_PIN11_CONFIG_V = 0x3 +const GPIO_PIN11_CONFIG_S = 11 +const GPIO_PIN11_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN11_WAKEUP_ENABLE_S = 10 +const GPIO_PIN11_INT_TYPE = 0x00000007 +const GPIO_PIN11_INT_TYPE_V = 0x7 +const GPIO_PIN11_INT_TYPE_S = 7 +const GPIO_PIN11_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN11_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN11_SYNC1_BYPASS_S = 3 +const GPIO_PIN11_PAD_DRIVER_V = 0x1 +const GPIO_PIN11_PAD_DRIVER_S = 2 +const GPIO_PIN11_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN11_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN11_SYNC2_BYPASS_S = 0 +const GPIO_PIN12_INT_ENA = 0x0000001F +const GPIO_PIN12_INT_ENA_V = 0x1F +const GPIO_PIN12_INT_ENA_S = 13 +const GPIO_PIN12_CONFIG = 0x00000003 +const GPIO_PIN12_CONFIG_V = 0x3 +const GPIO_PIN12_CONFIG_S = 11 +const GPIO_PIN12_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN12_WAKEUP_ENABLE_S = 10 +const GPIO_PIN12_INT_TYPE = 0x00000007 +const GPIO_PIN12_INT_TYPE_V = 0x7 +const GPIO_PIN12_INT_TYPE_S = 7 +const GPIO_PIN12_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN12_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN12_SYNC1_BYPASS_S = 3 +const GPIO_PIN12_PAD_DRIVER_V = 0x1 +const GPIO_PIN12_PAD_DRIVER_S = 2 +const GPIO_PIN12_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN12_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN12_SYNC2_BYPASS_S = 0 +const GPIO_PIN13_INT_ENA = 0x0000001F +const GPIO_PIN13_INT_ENA_V = 0x1F +const GPIO_PIN13_INT_ENA_S = 13 +const GPIO_PIN13_CONFIG = 0x00000003 +const GPIO_PIN13_CONFIG_V = 0x3 +const GPIO_PIN13_CONFIG_S = 11 +const GPIO_PIN13_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN13_WAKEUP_ENABLE_S = 10 +const GPIO_PIN13_INT_TYPE = 0x00000007 +const GPIO_PIN13_INT_TYPE_V = 0x7 +const GPIO_PIN13_INT_TYPE_S = 7 +const GPIO_PIN13_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN13_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN13_SYNC1_BYPASS_S = 3 +const GPIO_PIN13_PAD_DRIVER_V = 0x1 +const GPIO_PIN13_PAD_DRIVER_S = 2 +const GPIO_PIN13_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN13_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN13_SYNC2_BYPASS_S = 0 +const GPIO_PIN14_INT_ENA = 0x0000001F +const GPIO_PIN14_INT_ENA_V = 0x1F +const GPIO_PIN14_INT_ENA_S = 13 +const GPIO_PIN14_CONFIG = 0x00000003 +const GPIO_PIN14_CONFIG_V = 0x3 +const GPIO_PIN14_CONFIG_S = 11 +const GPIO_PIN14_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN14_WAKEUP_ENABLE_S = 10 +const GPIO_PIN14_INT_TYPE = 0x00000007 +const GPIO_PIN14_INT_TYPE_V = 0x7 +const GPIO_PIN14_INT_TYPE_S = 7 +const GPIO_PIN14_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN14_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN14_SYNC1_BYPASS_S = 3 +const GPIO_PIN14_PAD_DRIVER_V = 0x1 +const GPIO_PIN14_PAD_DRIVER_S = 2 +const GPIO_PIN14_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN14_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN14_SYNC2_BYPASS_S = 0 +const GPIO_PIN15_INT_ENA = 0x0000001F +const GPIO_PIN15_INT_ENA_V = 0x1F +const GPIO_PIN15_INT_ENA_S = 13 +const GPIO_PIN15_CONFIG = 0x00000003 +const GPIO_PIN15_CONFIG_V = 0x3 +const GPIO_PIN15_CONFIG_S = 11 +const GPIO_PIN15_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN15_WAKEUP_ENABLE_S = 10 +const GPIO_PIN15_INT_TYPE = 0x00000007 +const GPIO_PIN15_INT_TYPE_V = 0x7 +const GPIO_PIN15_INT_TYPE_S = 7 +const GPIO_PIN15_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN15_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN15_SYNC1_BYPASS_S = 3 +const GPIO_PIN15_PAD_DRIVER_V = 0x1 +const GPIO_PIN15_PAD_DRIVER_S = 2 +const GPIO_PIN15_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN15_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN15_SYNC2_BYPASS_S = 0 +const GPIO_PIN16_INT_ENA = 0x0000001F +const GPIO_PIN16_INT_ENA_V = 0x1F +const GPIO_PIN16_INT_ENA_S = 13 +const GPIO_PIN16_CONFIG = 0x00000003 +const GPIO_PIN16_CONFIG_V = 0x3 +const GPIO_PIN16_CONFIG_S = 11 +const GPIO_PIN16_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN16_WAKEUP_ENABLE_S = 10 +const GPIO_PIN16_INT_TYPE = 0x00000007 +const GPIO_PIN16_INT_TYPE_V = 0x7 +const GPIO_PIN16_INT_TYPE_S = 7 +const GPIO_PIN16_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN16_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN16_SYNC1_BYPASS_S = 3 +const GPIO_PIN16_PAD_DRIVER_V = 0x1 +const GPIO_PIN16_PAD_DRIVER_S = 2 +const GPIO_PIN16_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN16_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN16_SYNC2_BYPASS_S = 0 +const GPIO_PIN17_INT_ENA = 0x0000001F +const GPIO_PIN17_INT_ENA_V = 0x1F +const GPIO_PIN17_INT_ENA_S = 13 +const GPIO_PIN17_CONFIG = 0x00000003 +const GPIO_PIN17_CONFIG_V = 0x3 +const GPIO_PIN17_CONFIG_S = 11 +const GPIO_PIN17_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN17_WAKEUP_ENABLE_S = 10 +const GPIO_PIN17_INT_TYPE = 0x00000007 +const GPIO_PIN17_INT_TYPE_V = 0x7 +const GPIO_PIN17_INT_TYPE_S = 7 +const GPIO_PIN17_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN17_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN17_SYNC1_BYPASS_S = 3 +const GPIO_PIN17_PAD_DRIVER_V = 0x1 +const GPIO_PIN17_PAD_DRIVER_S = 2 +const GPIO_PIN17_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN17_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN17_SYNC2_BYPASS_S = 0 +const GPIO_PIN18_INT_ENA = 0x0000001F +const GPIO_PIN18_INT_ENA_V = 0x1F +const GPIO_PIN18_INT_ENA_S = 13 +const GPIO_PIN18_CONFIG = 0x00000003 +const GPIO_PIN18_CONFIG_V = 0x3 +const GPIO_PIN18_CONFIG_S = 11 +const GPIO_PIN18_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN18_WAKEUP_ENABLE_S = 10 +const GPIO_PIN18_INT_TYPE = 0x00000007 +const GPIO_PIN18_INT_TYPE_V = 0x7 +const GPIO_PIN18_INT_TYPE_S = 7 +const GPIO_PIN18_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN18_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN18_SYNC1_BYPASS_S = 3 +const GPIO_PIN18_PAD_DRIVER_V = 0x1 +const GPIO_PIN18_PAD_DRIVER_S = 2 +const GPIO_PIN18_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN18_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN18_SYNC2_BYPASS_S = 0 +const GPIO_PIN19_INT_ENA = 0x0000001F +const GPIO_PIN19_INT_ENA_V = 0x1F +const GPIO_PIN19_INT_ENA_S = 13 +const GPIO_PIN19_CONFIG = 0x00000003 +const GPIO_PIN19_CONFIG_V = 0x3 +const GPIO_PIN19_CONFIG_S = 11 +const GPIO_PIN19_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN19_WAKEUP_ENABLE_S = 10 +const GPIO_PIN19_INT_TYPE = 0x00000007 +const GPIO_PIN19_INT_TYPE_V = 0x7 +const GPIO_PIN19_INT_TYPE_S = 7 +const GPIO_PIN19_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN19_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN19_SYNC1_BYPASS_S = 3 +const GPIO_PIN19_PAD_DRIVER_V = 0x1 +const GPIO_PIN19_PAD_DRIVER_S = 2 +const GPIO_PIN19_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN19_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN19_SYNC2_BYPASS_S = 0 +const GPIO_PIN20_INT_ENA = 0x0000001F +const GPIO_PIN20_INT_ENA_V = 0x1F +const GPIO_PIN20_INT_ENA_S = 13 +const GPIO_PIN20_CONFIG = 0x00000003 +const GPIO_PIN20_CONFIG_V = 0x3 +const GPIO_PIN20_CONFIG_S = 11 +const GPIO_PIN20_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN20_WAKEUP_ENABLE_S = 10 +const GPIO_PIN20_INT_TYPE = 0x00000007 +const GPIO_PIN20_INT_TYPE_V = 0x7 +const GPIO_PIN20_INT_TYPE_S = 7 +const GPIO_PIN20_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN20_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN20_SYNC1_BYPASS_S = 3 +const GPIO_PIN20_PAD_DRIVER_V = 0x1 +const GPIO_PIN20_PAD_DRIVER_S = 2 +const GPIO_PIN20_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN20_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN20_SYNC2_BYPASS_S = 0 +const GPIO_PIN21_INT_ENA = 0x0000001F +const GPIO_PIN21_INT_ENA_V = 0x1F +const GPIO_PIN21_INT_ENA_S = 13 +const GPIO_PIN21_CONFIG = 0x00000003 +const GPIO_PIN21_CONFIG_V = 0x3 +const GPIO_PIN21_CONFIG_S = 11 +const GPIO_PIN21_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN21_WAKEUP_ENABLE_S = 10 +const GPIO_PIN21_INT_TYPE = 0x00000007 +const GPIO_PIN21_INT_TYPE_V = 0x7 +const GPIO_PIN21_INT_TYPE_S = 7 +const GPIO_PIN21_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN21_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN21_SYNC1_BYPASS_S = 3 +const GPIO_PIN21_PAD_DRIVER_V = 0x1 +const GPIO_PIN21_PAD_DRIVER_S = 2 +const GPIO_PIN21_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN21_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN21_SYNC2_BYPASS_S = 0 +const GPIO_PIN22_INT_ENA = 0x0000001F +const GPIO_PIN22_INT_ENA_V = 0x1F +const GPIO_PIN22_INT_ENA_S = 13 +const GPIO_PIN22_CONFIG = 0x00000003 +const GPIO_PIN22_CONFIG_V = 0x3 +const GPIO_PIN22_CONFIG_S = 11 +const GPIO_PIN22_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN22_WAKEUP_ENABLE_S = 10 +const GPIO_PIN22_INT_TYPE = 0x00000007 +const GPIO_PIN22_INT_TYPE_V = 0x7 +const GPIO_PIN22_INT_TYPE_S = 7 +const GPIO_PIN22_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN22_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN22_SYNC1_BYPASS_S = 3 +const GPIO_PIN22_PAD_DRIVER_V = 0x1 +const GPIO_PIN22_PAD_DRIVER_S = 2 +const GPIO_PIN22_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN22_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN22_SYNC2_BYPASS_S = 0 +const GPIO_PIN23_INT_ENA = 0x0000001F +const GPIO_PIN23_INT_ENA_V = 0x1F +const GPIO_PIN23_INT_ENA_S = 13 +const GPIO_PIN23_CONFIG = 0x00000003 +const GPIO_PIN23_CONFIG_V = 0x3 +const GPIO_PIN23_CONFIG_S = 11 +const GPIO_PIN23_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN23_WAKEUP_ENABLE_S = 10 +const GPIO_PIN23_INT_TYPE = 0x00000007 +const GPIO_PIN23_INT_TYPE_V = 0x7 +const GPIO_PIN23_INT_TYPE_S = 7 +const GPIO_PIN23_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN23_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN23_SYNC1_BYPASS_S = 3 +const GPIO_PIN23_PAD_DRIVER_V = 0x1 +const GPIO_PIN23_PAD_DRIVER_S = 2 +const GPIO_PIN23_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN23_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN23_SYNC2_BYPASS_S = 0 +const GPIO_PIN24_INT_ENA = 0x0000001F +const GPIO_PIN24_INT_ENA_V = 0x1F +const GPIO_PIN24_INT_ENA_S = 13 +const GPIO_PIN24_CONFIG = 0x00000003 +const GPIO_PIN24_CONFIG_V = 0x3 +const GPIO_PIN24_CONFIG_S = 11 +const GPIO_PIN24_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN24_WAKEUP_ENABLE_S = 10 +const GPIO_PIN24_INT_TYPE = 0x00000007 +const GPIO_PIN24_INT_TYPE_V = 0x7 +const GPIO_PIN24_INT_TYPE_S = 7 +const GPIO_PIN24_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN24_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN24_SYNC1_BYPASS_S = 3 +const GPIO_PIN24_PAD_DRIVER_V = 0x1 +const GPIO_PIN24_PAD_DRIVER_S = 2 +const GPIO_PIN24_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN24_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN24_SYNC2_BYPASS_S = 0 +const GPIO_PIN25_INT_ENA = 0x0000001F +const GPIO_PIN25_INT_ENA_V = 0x1F +const GPIO_PIN25_INT_ENA_S = 13 +const GPIO_PIN25_CONFIG = 0x00000003 +const GPIO_PIN25_CONFIG_V = 0x3 +const GPIO_PIN25_CONFIG_S = 11 +const GPIO_PIN25_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN25_WAKEUP_ENABLE_S = 10 +const GPIO_PIN25_INT_TYPE = 0x00000007 +const GPIO_PIN25_INT_TYPE_V = 0x7 +const GPIO_PIN25_INT_TYPE_S = 7 +const GPIO_PIN25_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN25_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN25_SYNC1_BYPASS_S = 3 +const GPIO_PIN25_PAD_DRIVER_V = 0x1 +const GPIO_PIN25_PAD_DRIVER_S = 2 +const GPIO_PIN25_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN25_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN25_SYNC2_BYPASS_S = 0 +const GPIO_PIN26_INT_ENA = 0x0000001F +const GPIO_PIN26_INT_ENA_V = 0x1F +const GPIO_PIN26_INT_ENA_S = 13 +const GPIO_PIN26_CONFIG = 0x00000003 +const GPIO_PIN26_CONFIG_V = 0x3 +const GPIO_PIN26_CONFIG_S = 11 +const GPIO_PIN26_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN26_WAKEUP_ENABLE_S = 10 +const GPIO_PIN26_INT_TYPE = 0x00000007 +const GPIO_PIN26_INT_TYPE_V = 0x7 +const GPIO_PIN26_INT_TYPE_S = 7 +const GPIO_PIN26_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN26_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN26_SYNC1_BYPASS_S = 3 +const GPIO_PIN26_PAD_DRIVER_V = 0x1 +const GPIO_PIN26_PAD_DRIVER_S = 2 +const GPIO_PIN26_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN26_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN26_SYNC2_BYPASS_S = 0 +const GPIO_PIN27_INT_ENA = 0x0000001F +const GPIO_PIN27_INT_ENA_V = 0x1F +const GPIO_PIN27_INT_ENA_S = 13 +const GPIO_PIN27_CONFIG = 0x00000003 +const GPIO_PIN27_CONFIG_V = 0x3 +const GPIO_PIN27_CONFIG_S = 11 +const GPIO_PIN27_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN27_WAKEUP_ENABLE_S = 10 +const GPIO_PIN27_INT_TYPE = 0x00000007 +const GPIO_PIN27_INT_TYPE_V = 0x7 +const GPIO_PIN27_INT_TYPE_S = 7 +const GPIO_PIN27_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN27_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN27_SYNC1_BYPASS_S = 3 +const GPIO_PIN27_PAD_DRIVER_V = 0x1 +const GPIO_PIN27_PAD_DRIVER_S = 2 +const GPIO_PIN27_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN27_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN27_SYNC2_BYPASS_S = 0 +const GPIO_PIN28_INT_ENA = 0x0000001F +const GPIO_PIN28_INT_ENA_V = 0x1F +const GPIO_PIN28_INT_ENA_S = 13 +const GPIO_PIN28_CONFIG = 0x00000003 +const GPIO_PIN28_CONFIG_V = 0x3 +const GPIO_PIN28_CONFIG_S = 11 +const GPIO_PIN28_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN28_WAKEUP_ENABLE_S = 10 +const GPIO_PIN28_INT_TYPE = 0x00000007 +const GPIO_PIN28_INT_TYPE_V = 0x7 +const GPIO_PIN28_INT_TYPE_S = 7 +const GPIO_PIN28_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN28_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN28_SYNC1_BYPASS_S = 3 +const GPIO_PIN28_PAD_DRIVER_V = 0x1 +const GPIO_PIN28_PAD_DRIVER_S = 2 +const GPIO_PIN28_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN28_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN28_SYNC2_BYPASS_S = 0 +const GPIO_PIN29_INT_ENA = 0x0000001F +const GPIO_PIN29_INT_ENA_V = 0x1F +const GPIO_PIN29_INT_ENA_S = 13 +const GPIO_PIN29_CONFIG = 0x00000003 +const GPIO_PIN29_CONFIG_V = 0x3 +const GPIO_PIN29_CONFIG_S = 11 +const GPIO_PIN29_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN29_WAKEUP_ENABLE_S = 10 +const GPIO_PIN29_INT_TYPE = 0x00000007 +const GPIO_PIN29_INT_TYPE_V = 0x7 +const GPIO_PIN29_INT_TYPE_S = 7 +const GPIO_PIN29_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN29_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN29_SYNC1_BYPASS_S = 3 +const GPIO_PIN29_PAD_DRIVER_V = 0x1 +const GPIO_PIN29_PAD_DRIVER_S = 2 +const GPIO_PIN29_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN29_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN29_SYNC2_BYPASS_S = 0 +const GPIO_PIN30_INT_ENA = 0x0000001F +const GPIO_PIN30_INT_ENA_V = 0x1F +const GPIO_PIN30_INT_ENA_S = 13 +const GPIO_PIN30_CONFIG = 0x00000003 +const GPIO_PIN30_CONFIG_V = 0x3 +const GPIO_PIN30_CONFIG_S = 11 +const GPIO_PIN30_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN30_WAKEUP_ENABLE_S = 10 +const GPIO_PIN30_INT_TYPE = 0x00000007 +const GPIO_PIN30_INT_TYPE_V = 0x7 +const GPIO_PIN30_INT_TYPE_S = 7 +const GPIO_PIN30_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN30_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN30_SYNC1_BYPASS_S = 3 +const GPIO_PIN30_PAD_DRIVER_V = 0x1 +const GPIO_PIN30_PAD_DRIVER_S = 2 +const GPIO_PIN30_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN30_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN30_SYNC2_BYPASS_S = 0 +const GPIO_PIN31_INT_ENA = 0x0000001F +const GPIO_PIN31_INT_ENA_V = 0x1F +const GPIO_PIN31_INT_ENA_S = 13 +const GPIO_PIN31_CONFIG = 0x00000003 +const GPIO_PIN31_CONFIG_V = 0x3 +const GPIO_PIN31_CONFIG_S = 11 +const GPIO_PIN31_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN31_WAKEUP_ENABLE_S = 10 +const GPIO_PIN31_INT_TYPE = 0x00000007 +const GPIO_PIN31_INT_TYPE_V = 0x7 +const GPIO_PIN31_INT_TYPE_S = 7 +const GPIO_PIN31_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN31_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN31_SYNC1_BYPASS_S = 3 +const GPIO_PIN31_PAD_DRIVER_V = 0x1 +const GPIO_PIN31_PAD_DRIVER_S = 2 +const GPIO_PIN31_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN31_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN31_SYNC2_BYPASS_S = 0 +const GPIO_PIN32_INT_ENA = 0x0000001F +const GPIO_PIN32_INT_ENA_V = 0x1F +const GPIO_PIN32_INT_ENA_S = 13 +const GPIO_PIN32_CONFIG = 0x00000003 +const GPIO_PIN32_CONFIG_V = 0x3 +const GPIO_PIN32_CONFIG_S = 11 +const GPIO_PIN32_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN32_WAKEUP_ENABLE_S = 10 +const GPIO_PIN32_INT_TYPE = 0x00000007 +const GPIO_PIN32_INT_TYPE_V = 0x7 +const GPIO_PIN32_INT_TYPE_S = 7 +const GPIO_PIN32_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN32_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN32_SYNC1_BYPASS_S = 3 +const GPIO_PIN32_PAD_DRIVER_V = 0x1 +const GPIO_PIN32_PAD_DRIVER_S = 2 +const GPIO_PIN32_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN32_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN32_SYNC2_BYPASS_S = 0 +const GPIO_PIN33_INT_ENA = 0x0000001F +const GPIO_PIN33_INT_ENA_V = 0x1F +const GPIO_PIN33_INT_ENA_S = 13 +const GPIO_PIN33_CONFIG = 0x00000003 +const GPIO_PIN33_CONFIG_V = 0x3 +const GPIO_PIN33_CONFIG_S = 11 +const GPIO_PIN33_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN33_WAKEUP_ENABLE_S = 10 +const GPIO_PIN33_INT_TYPE = 0x00000007 +const GPIO_PIN33_INT_TYPE_V = 0x7 +const GPIO_PIN33_INT_TYPE_S = 7 +const GPIO_PIN33_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN33_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN33_SYNC1_BYPASS_S = 3 +const GPIO_PIN33_PAD_DRIVER_V = 0x1 +const GPIO_PIN33_PAD_DRIVER_S = 2 +const GPIO_PIN33_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN33_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN33_SYNC2_BYPASS_S = 0 +const GPIO_PIN34_INT_ENA = 0x0000001F +const GPIO_PIN34_INT_ENA_V = 0x1F +const GPIO_PIN34_INT_ENA_S = 13 +const GPIO_PIN34_CONFIG = 0x00000003 +const GPIO_PIN34_CONFIG_V = 0x3 +const GPIO_PIN34_CONFIG_S = 11 +const GPIO_PIN34_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN34_WAKEUP_ENABLE_S = 10 +const GPIO_PIN34_INT_TYPE = 0x00000007 +const GPIO_PIN34_INT_TYPE_V = 0x7 +const GPIO_PIN34_INT_TYPE_S = 7 +const GPIO_PIN34_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN34_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN34_SYNC1_BYPASS_S = 3 +const GPIO_PIN34_PAD_DRIVER_V = 0x1 +const GPIO_PIN34_PAD_DRIVER_S = 2 +const GPIO_PIN34_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN34_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN34_SYNC2_BYPASS_S = 0 +const GPIO_PIN35_INT_ENA = 0x0000001F +const GPIO_PIN35_INT_ENA_V = 0x1F +const GPIO_PIN35_INT_ENA_S = 13 +const GPIO_PIN35_CONFIG = 0x00000003 +const GPIO_PIN35_CONFIG_V = 0x3 +const GPIO_PIN35_CONFIG_S = 11 +const GPIO_PIN35_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN35_WAKEUP_ENABLE_S = 10 +const GPIO_PIN35_INT_TYPE = 0x00000007 +const GPIO_PIN35_INT_TYPE_V = 0x7 +const GPIO_PIN35_INT_TYPE_S = 7 +const GPIO_PIN35_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN35_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN35_SYNC1_BYPASS_S = 3 +const GPIO_PIN35_PAD_DRIVER_V = 0x1 +const GPIO_PIN35_PAD_DRIVER_S = 2 +const GPIO_PIN35_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN35_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN35_SYNC2_BYPASS_S = 0 +const GPIO_PIN36_INT_ENA = 0x0000001F +const GPIO_PIN36_INT_ENA_V = 0x1F +const GPIO_PIN36_INT_ENA_S = 13 +const GPIO_PIN36_CONFIG = 0x00000003 +const GPIO_PIN36_CONFIG_V = 0x3 +const GPIO_PIN36_CONFIG_S = 11 +const GPIO_PIN36_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN36_WAKEUP_ENABLE_S = 10 +const GPIO_PIN36_INT_TYPE = 0x00000007 +const GPIO_PIN36_INT_TYPE_V = 0x7 +const GPIO_PIN36_INT_TYPE_S = 7 +const GPIO_PIN36_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN36_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN36_SYNC1_BYPASS_S = 3 +const GPIO_PIN36_PAD_DRIVER_V = 0x1 +const GPIO_PIN36_PAD_DRIVER_S = 2 +const GPIO_PIN36_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN36_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN36_SYNC2_BYPASS_S = 0 +const GPIO_PIN37_INT_ENA = 0x0000001F +const GPIO_PIN37_INT_ENA_V = 0x1F +const GPIO_PIN37_INT_ENA_S = 13 +const GPIO_PIN37_CONFIG = 0x00000003 +const GPIO_PIN37_CONFIG_V = 0x3 +const GPIO_PIN37_CONFIG_S = 11 +const GPIO_PIN37_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN37_WAKEUP_ENABLE_S = 10 +const GPIO_PIN37_INT_TYPE = 0x00000007 +const GPIO_PIN37_INT_TYPE_V = 0x7 +const GPIO_PIN37_INT_TYPE_S = 7 +const GPIO_PIN37_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN37_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN37_SYNC1_BYPASS_S = 3 +const GPIO_PIN37_PAD_DRIVER_V = 0x1 +const GPIO_PIN37_PAD_DRIVER_S = 2 +const GPIO_PIN37_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN37_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN37_SYNC2_BYPASS_S = 0 +const GPIO_PIN38_INT_ENA = 0x0000001F +const GPIO_PIN38_INT_ENA_V = 0x1F +const GPIO_PIN38_INT_ENA_S = 13 +const GPIO_PIN38_CONFIG = 0x00000003 +const GPIO_PIN38_CONFIG_V = 0x3 +const GPIO_PIN38_CONFIG_S = 11 +const GPIO_PIN38_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN38_WAKEUP_ENABLE_S = 10 +const GPIO_PIN38_INT_TYPE = 0x00000007 +const GPIO_PIN38_INT_TYPE_V = 0x7 +const GPIO_PIN38_INT_TYPE_S = 7 +const GPIO_PIN38_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN38_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN38_SYNC1_BYPASS_S = 3 +const GPIO_PIN38_PAD_DRIVER_V = 0x1 +const GPIO_PIN38_PAD_DRIVER_S = 2 +const GPIO_PIN38_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN38_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN38_SYNC2_BYPASS_S = 0 +const GPIO_PIN39_INT_ENA = 0x0000001F +const GPIO_PIN39_INT_ENA_V = 0x1F +const GPIO_PIN39_INT_ENA_S = 13 +const GPIO_PIN39_CONFIG = 0x00000003 +const GPIO_PIN39_CONFIG_V = 0x3 +const GPIO_PIN39_CONFIG_S = 11 +const GPIO_PIN39_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN39_WAKEUP_ENABLE_S = 10 +const GPIO_PIN39_INT_TYPE = 0x00000007 +const GPIO_PIN39_INT_TYPE_V = 0x7 +const GPIO_PIN39_INT_TYPE_S = 7 +const GPIO_PIN39_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN39_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN39_SYNC1_BYPASS_S = 3 +const GPIO_PIN39_PAD_DRIVER_V = 0x1 +const GPIO_PIN39_PAD_DRIVER_S = 2 +const GPIO_PIN39_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN39_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN39_SYNC2_BYPASS_S = 0 +const GPIO_PIN40_INT_ENA = 0x0000001F +const GPIO_PIN40_INT_ENA_V = 0x1F +const GPIO_PIN40_INT_ENA_S = 13 +const GPIO_PIN40_CONFIG = 0x00000003 +const GPIO_PIN40_CONFIG_V = 0x3 +const GPIO_PIN40_CONFIG_S = 11 +const GPIO_PIN40_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN40_WAKEUP_ENABLE_S = 10 +const GPIO_PIN40_INT_TYPE = 0x00000007 +const GPIO_PIN40_INT_TYPE_V = 0x7 +const GPIO_PIN40_INT_TYPE_S = 7 +const GPIO_PIN40_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN40_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN40_SYNC1_BYPASS_S = 3 +const GPIO_PIN40_PAD_DRIVER_V = 0x1 +const GPIO_PIN40_PAD_DRIVER_S = 2 +const GPIO_PIN40_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN40_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN40_SYNC2_BYPASS_S = 0 +const GPIO_PIN41_INT_ENA = 0x0000001F +const GPIO_PIN41_INT_ENA_V = 0x1F +const GPIO_PIN41_INT_ENA_S = 13 +const GPIO_PIN41_CONFIG = 0x00000003 +const GPIO_PIN41_CONFIG_V = 0x3 +const GPIO_PIN41_CONFIG_S = 11 +const GPIO_PIN41_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN41_WAKEUP_ENABLE_S = 10 +const GPIO_PIN41_INT_TYPE = 0x00000007 +const GPIO_PIN41_INT_TYPE_V = 0x7 +const GPIO_PIN41_INT_TYPE_S = 7 +const GPIO_PIN41_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN41_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN41_SYNC1_BYPASS_S = 3 +const GPIO_PIN41_PAD_DRIVER_V = 0x1 +const GPIO_PIN41_PAD_DRIVER_S = 2 +const GPIO_PIN41_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN41_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN41_SYNC2_BYPASS_S = 0 +const GPIO_PIN42_INT_ENA = 0x0000001F +const GPIO_PIN42_INT_ENA_V = 0x1F +const GPIO_PIN42_INT_ENA_S = 13 +const GPIO_PIN42_CONFIG = 0x00000003 +const GPIO_PIN42_CONFIG_V = 0x3 +const GPIO_PIN42_CONFIG_S = 11 +const GPIO_PIN42_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN42_WAKEUP_ENABLE_S = 10 +const GPIO_PIN42_INT_TYPE = 0x00000007 +const GPIO_PIN42_INT_TYPE_V = 0x7 +const GPIO_PIN42_INT_TYPE_S = 7 +const GPIO_PIN42_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN42_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN42_SYNC1_BYPASS_S = 3 +const GPIO_PIN42_PAD_DRIVER_V = 0x1 +const GPIO_PIN42_PAD_DRIVER_S = 2 +const GPIO_PIN42_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN42_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN42_SYNC2_BYPASS_S = 0 +const GPIO_PIN43_INT_ENA = 0x0000001F +const GPIO_PIN43_INT_ENA_V = 0x1F +const GPIO_PIN43_INT_ENA_S = 13 +const GPIO_PIN43_CONFIG = 0x00000003 +const GPIO_PIN43_CONFIG_V = 0x3 +const GPIO_PIN43_CONFIG_S = 11 +const GPIO_PIN43_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN43_WAKEUP_ENABLE_S = 10 +const GPIO_PIN43_INT_TYPE = 0x00000007 +const GPIO_PIN43_INT_TYPE_V = 0x7 +const GPIO_PIN43_INT_TYPE_S = 7 +const GPIO_PIN43_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN43_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN43_SYNC1_BYPASS_S = 3 +const GPIO_PIN43_PAD_DRIVER_V = 0x1 +const GPIO_PIN43_PAD_DRIVER_S = 2 +const GPIO_PIN43_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN43_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN43_SYNC2_BYPASS_S = 0 +const GPIO_PIN44_INT_ENA = 0x0000001F +const GPIO_PIN44_INT_ENA_V = 0x1F +const GPIO_PIN44_INT_ENA_S = 13 +const GPIO_PIN44_CONFIG = 0x00000003 +const GPIO_PIN44_CONFIG_V = 0x3 +const GPIO_PIN44_CONFIG_S = 11 +const GPIO_PIN44_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN44_WAKEUP_ENABLE_S = 10 +const GPIO_PIN44_INT_TYPE = 0x00000007 +const GPIO_PIN44_INT_TYPE_V = 0x7 +const GPIO_PIN44_INT_TYPE_S = 7 +const GPIO_PIN44_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN44_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN44_SYNC1_BYPASS_S = 3 +const GPIO_PIN44_PAD_DRIVER_V = 0x1 +const GPIO_PIN44_PAD_DRIVER_S = 2 +const GPIO_PIN44_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN44_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN44_SYNC2_BYPASS_S = 0 +const GPIO_PIN45_INT_ENA = 0x0000001F +const GPIO_PIN45_INT_ENA_V = 0x1F +const GPIO_PIN45_INT_ENA_S = 13 +const GPIO_PIN45_CONFIG = 0x00000003 +const GPIO_PIN45_CONFIG_V = 0x3 +const GPIO_PIN45_CONFIG_S = 11 +const GPIO_PIN45_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN45_WAKEUP_ENABLE_S = 10 +const GPIO_PIN45_INT_TYPE = 0x00000007 +const GPIO_PIN45_INT_TYPE_V = 0x7 +const GPIO_PIN45_INT_TYPE_S = 7 +const GPIO_PIN45_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN45_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN45_SYNC1_BYPASS_S = 3 +const GPIO_PIN45_PAD_DRIVER_V = 0x1 +const GPIO_PIN45_PAD_DRIVER_S = 2 +const GPIO_PIN45_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN45_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN45_SYNC2_BYPASS_S = 0 +const GPIO_PIN46_INT_ENA = 0x0000001F +const GPIO_PIN46_INT_ENA_V = 0x1F +const GPIO_PIN46_INT_ENA_S = 13 +const GPIO_PIN46_CONFIG = 0x00000003 +const GPIO_PIN46_CONFIG_V = 0x3 +const GPIO_PIN46_CONFIG_S = 11 +const GPIO_PIN46_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN46_WAKEUP_ENABLE_S = 10 +const GPIO_PIN46_INT_TYPE = 0x00000007 +const GPIO_PIN46_INT_TYPE_V = 0x7 +const GPIO_PIN46_INT_TYPE_S = 7 +const GPIO_PIN46_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN46_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN46_SYNC1_BYPASS_S = 3 +const GPIO_PIN46_PAD_DRIVER_V = 0x1 +const GPIO_PIN46_PAD_DRIVER_S = 2 +const GPIO_PIN46_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN46_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN46_SYNC2_BYPASS_S = 0 +const GPIO_PIN47_INT_ENA = 0x0000001F +const GPIO_PIN47_INT_ENA_V = 0x1F +const GPIO_PIN47_INT_ENA_S = 13 +const GPIO_PIN47_CONFIG = 0x00000003 +const GPIO_PIN47_CONFIG_V = 0x3 +const GPIO_PIN47_CONFIG_S = 11 +const GPIO_PIN47_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN47_WAKEUP_ENABLE_S = 10 +const GPIO_PIN47_INT_TYPE = 0x00000007 +const GPIO_PIN47_INT_TYPE_V = 0x7 +const GPIO_PIN47_INT_TYPE_S = 7 +const GPIO_PIN47_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN47_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN47_SYNC1_BYPASS_S = 3 +const GPIO_PIN47_PAD_DRIVER_V = 0x1 +const GPIO_PIN47_PAD_DRIVER_S = 2 +const GPIO_PIN47_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN47_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN47_SYNC2_BYPASS_S = 0 +const GPIO_PIN48_INT_ENA = 0x0000001F +const GPIO_PIN48_INT_ENA_V = 0x1F +const GPIO_PIN48_INT_ENA_S = 13 +const GPIO_PIN48_CONFIG = 0x00000003 +const GPIO_PIN48_CONFIG_V = 0x3 +const GPIO_PIN48_CONFIG_S = 11 +const GPIO_PIN48_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN48_WAKEUP_ENABLE_S = 10 +const GPIO_PIN48_INT_TYPE = 0x00000007 +const GPIO_PIN48_INT_TYPE_V = 0x7 +const GPIO_PIN48_INT_TYPE_S = 7 +const GPIO_PIN48_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN48_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN48_SYNC1_BYPASS_S = 3 +const GPIO_PIN48_PAD_DRIVER_V = 0x1 +const GPIO_PIN48_PAD_DRIVER_S = 2 +const GPIO_PIN48_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN48_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN48_SYNC2_BYPASS_S = 0 +const GPIO_PIN49_INT_ENA = 0x0000001F +const GPIO_PIN49_INT_ENA_V = 0x1F +const GPIO_PIN49_INT_ENA_S = 13 +const GPIO_PIN49_CONFIG = 0x00000003 +const GPIO_PIN49_CONFIG_V = 0x3 +const GPIO_PIN49_CONFIG_S = 11 +const GPIO_PIN49_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN49_WAKEUP_ENABLE_S = 10 +const GPIO_PIN49_INT_TYPE = 0x00000007 +const GPIO_PIN49_INT_TYPE_V = 0x7 +const GPIO_PIN49_INT_TYPE_S = 7 +const GPIO_PIN49_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN49_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN49_SYNC1_BYPASS_S = 3 +const GPIO_PIN49_PAD_DRIVER_V = 0x1 +const GPIO_PIN49_PAD_DRIVER_S = 2 +const GPIO_PIN49_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN49_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN49_SYNC2_BYPASS_S = 0 +const GPIO_PIN50_INT_ENA = 0x0000001F +const GPIO_PIN50_INT_ENA_V = 0x1F +const GPIO_PIN50_INT_ENA_S = 13 +const GPIO_PIN50_CONFIG = 0x00000003 +const GPIO_PIN50_CONFIG_V = 0x3 +const GPIO_PIN50_CONFIG_S = 11 +const GPIO_PIN50_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN50_WAKEUP_ENABLE_S = 10 +const GPIO_PIN50_INT_TYPE = 0x00000007 +const GPIO_PIN50_INT_TYPE_V = 0x7 +const GPIO_PIN50_INT_TYPE_S = 7 +const GPIO_PIN50_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN50_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN50_SYNC1_BYPASS_S = 3 +const GPIO_PIN50_PAD_DRIVER_V = 0x1 +const GPIO_PIN50_PAD_DRIVER_S = 2 +const GPIO_PIN50_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN50_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN50_SYNC2_BYPASS_S = 0 +const GPIO_PIN51_INT_ENA = 0x0000001F +const GPIO_PIN51_INT_ENA_V = 0x1F +const GPIO_PIN51_INT_ENA_S = 13 +const GPIO_PIN51_CONFIG = 0x00000003 +const GPIO_PIN51_CONFIG_V = 0x3 +const GPIO_PIN51_CONFIG_S = 11 +const GPIO_PIN51_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN51_WAKEUP_ENABLE_S = 10 +const GPIO_PIN51_INT_TYPE = 0x00000007 +const GPIO_PIN51_INT_TYPE_V = 0x7 +const GPIO_PIN51_INT_TYPE_S = 7 +const GPIO_PIN51_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN51_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN51_SYNC1_BYPASS_S = 3 +const GPIO_PIN51_PAD_DRIVER_V = 0x1 +const GPIO_PIN51_PAD_DRIVER_S = 2 +const GPIO_PIN51_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN51_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN51_SYNC2_BYPASS_S = 0 +const GPIO_PIN52_INT_ENA = 0x0000001F +const GPIO_PIN52_INT_ENA_V = 0x1F +const GPIO_PIN52_INT_ENA_S = 13 +const GPIO_PIN52_CONFIG = 0x00000003 +const GPIO_PIN52_CONFIG_V = 0x3 +const GPIO_PIN52_CONFIG_S = 11 +const GPIO_PIN52_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN52_WAKEUP_ENABLE_S = 10 +const GPIO_PIN52_INT_TYPE = 0x00000007 +const GPIO_PIN52_INT_TYPE_V = 0x7 +const GPIO_PIN52_INT_TYPE_S = 7 +const GPIO_PIN52_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN52_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN52_SYNC1_BYPASS_S = 3 +const GPIO_PIN52_PAD_DRIVER_V = 0x1 +const GPIO_PIN52_PAD_DRIVER_S = 2 +const GPIO_PIN52_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN52_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN52_SYNC2_BYPASS_S = 0 +const GPIO_PIN53_INT_ENA = 0x0000001F +const GPIO_PIN53_INT_ENA_V = 0x1F +const GPIO_PIN53_INT_ENA_S = 13 +const GPIO_PIN53_CONFIG = 0x00000003 +const GPIO_PIN53_CONFIG_V = 0x3 +const GPIO_PIN53_CONFIG_S = 11 +const GPIO_PIN53_WAKEUP_ENABLE_V = 0x1 +const GPIO_PIN53_WAKEUP_ENABLE_S = 10 +const GPIO_PIN53_INT_TYPE = 0x00000007 +const GPIO_PIN53_INT_TYPE_V = 0x7 +const GPIO_PIN53_INT_TYPE_S = 7 +const GPIO_PIN53_SYNC1_BYPASS = 0x00000003 +const GPIO_PIN53_SYNC1_BYPASS_V = 0x3 +const GPIO_PIN53_SYNC1_BYPASS_S = 3 +const GPIO_PIN53_PAD_DRIVER_V = 0x1 +const GPIO_PIN53_PAD_DRIVER_S = 2 +const GPIO_PIN53_SYNC2_BYPASS = 0x00000003 +const GPIO_PIN53_SYNC2_BYPASS_V = 0x3 +const GPIO_PIN53_SYNC2_BYPASS_S = 0 +const GPIO_STATUS_INTERRUPT_NEXT = 0xFFFFFFFF +const GPIO_STATUS_INTERRUPT_NEXT_V = 0xFFFFFFFF +const GPIO_STATUS_INTERRUPT_NEXT_S = 0 +const GPIO_STATUS_INTERRUPT_NEXT1 = 0x003FFFFF +const GPIO_STATUS_INTERRUPT_NEXT1_V = 0x3FFFFF +const GPIO_STATUS_INTERRUPT_NEXT1_S = 0 +const GPIO_SIG0_IN_SEL_V = 0x1 +const GPIO_SIG0_IN_SEL_S = 7 +const GPIO_FUNC0_IN_INV_SEL_V = 0x1 +const GPIO_FUNC0_IN_INV_SEL_S = 6 +const GPIO_FUNC0_IN_SEL = 0x0000003F +const GPIO_FUNC0_IN_SEL_V = 0x3F +const GPIO_FUNC0_IN_SEL_S = 0 +const GPIO_SIG1_IN_SEL_V = 0x1 +const GPIO_SIG1_IN_SEL_S = 7 +const GPIO_FUNC1_IN_INV_SEL_V = 0x1 +const GPIO_FUNC1_IN_INV_SEL_S = 6 +const GPIO_FUNC1_IN_SEL = 0x0000003F +const GPIO_FUNC1_IN_SEL_V = 0x3F +const GPIO_FUNC1_IN_SEL_S = 0 +const GPIO_SIG2_IN_SEL_V = 0x1 +const GPIO_SIG2_IN_SEL_S = 7 +const GPIO_FUNC2_IN_INV_SEL_V = 0x1 +const GPIO_FUNC2_IN_INV_SEL_S = 6 +const GPIO_FUNC2_IN_SEL = 0x0000003F +const GPIO_FUNC2_IN_SEL_V = 0x3F +const GPIO_FUNC2_IN_SEL_S = 0 +const GPIO_SIG3_IN_SEL_V = 0x1 +const GPIO_SIG3_IN_SEL_S = 7 +const GPIO_FUNC3_IN_INV_SEL_V = 0x1 +const GPIO_FUNC3_IN_INV_SEL_S = 6 +const GPIO_FUNC3_IN_SEL = 0x0000003F +const GPIO_FUNC3_IN_SEL_V = 0x3F +const GPIO_FUNC3_IN_SEL_S = 0 +const GPIO_SIG4_IN_SEL_V = 0x1 +const GPIO_SIG4_IN_SEL_S = 7 +const GPIO_FUNC4_IN_INV_SEL_V = 0x1 +const GPIO_FUNC4_IN_INV_SEL_S = 6 +const GPIO_FUNC4_IN_SEL = 0x0000003F +const GPIO_FUNC4_IN_SEL_V = 0x3F +const GPIO_FUNC4_IN_SEL_S = 0 +const GPIO_SIG5_IN_SEL_V = 0x1 +const GPIO_SIG5_IN_SEL_S = 7 +const GPIO_FUNC5_IN_INV_SEL_V = 0x1 +const GPIO_FUNC5_IN_INV_SEL_S = 6 +const GPIO_FUNC5_IN_SEL = 0x0000003F +const GPIO_FUNC5_IN_SEL_V = 0x3F +const GPIO_FUNC5_IN_SEL_S = 0 +const GPIO_SIG6_IN_SEL_V = 0x1 +const GPIO_SIG6_IN_SEL_S = 7 +const GPIO_FUNC6_IN_INV_SEL_V = 0x1 +const GPIO_FUNC6_IN_INV_SEL_S = 6 +const GPIO_FUNC6_IN_SEL = 0x0000003F +const GPIO_FUNC6_IN_SEL_V = 0x3F +const GPIO_FUNC6_IN_SEL_S = 0 +const GPIO_SIG7_IN_SEL_V = 0x1 +const GPIO_SIG7_IN_SEL_S = 7 +const GPIO_FUNC7_IN_INV_SEL_V = 0x1 +const GPIO_FUNC7_IN_INV_SEL_S = 6 +const GPIO_FUNC7_IN_SEL = 0x0000003F +const GPIO_FUNC7_IN_SEL_V = 0x3F +const GPIO_FUNC7_IN_SEL_S = 0 +const GPIO_SIG8_IN_SEL_V = 0x1 +const GPIO_SIG8_IN_SEL_S = 7 +const GPIO_FUNC8_IN_INV_SEL_V = 0x1 +const GPIO_FUNC8_IN_INV_SEL_S = 6 +const GPIO_FUNC8_IN_SEL = 0x0000003F +const GPIO_FUNC8_IN_SEL_V = 0x3F +const GPIO_FUNC8_IN_SEL_S = 0 +const GPIO_SIG9_IN_SEL_V = 0x1 +const GPIO_SIG9_IN_SEL_S = 7 +const GPIO_FUNC9_IN_INV_SEL_V = 0x1 +const GPIO_FUNC9_IN_INV_SEL_S = 6 +const GPIO_FUNC9_IN_SEL = 0x0000003F +const GPIO_FUNC9_IN_SEL_V = 0x3F +const GPIO_FUNC9_IN_SEL_S = 0 +const GPIO_SIG10_IN_SEL_V = 0x1 +const GPIO_SIG10_IN_SEL_S = 7 +const GPIO_FUNC10_IN_INV_SEL_V = 0x1 +const GPIO_FUNC10_IN_INV_SEL_S = 6 +const GPIO_FUNC10_IN_SEL = 0x0000003F +const GPIO_FUNC10_IN_SEL_V = 0x3F +const GPIO_FUNC10_IN_SEL_S = 0 +const GPIO_SIG11_IN_SEL_V = 0x1 +const GPIO_SIG11_IN_SEL_S = 7 +const GPIO_FUNC11_IN_INV_SEL_V = 0x1 +const GPIO_FUNC11_IN_INV_SEL_S = 6 +const GPIO_FUNC11_IN_SEL = 0x0000003F +const GPIO_FUNC11_IN_SEL_V = 0x3F +const GPIO_FUNC11_IN_SEL_S = 0 +const GPIO_SIG12_IN_SEL_V = 0x1 +const GPIO_SIG12_IN_SEL_S = 7 +const GPIO_FUNC12_IN_INV_SEL_V = 0x1 +const GPIO_FUNC12_IN_INV_SEL_S = 6 +const GPIO_FUNC12_IN_SEL = 0x0000003F +const GPIO_FUNC12_IN_SEL_V = 0x3F +const GPIO_FUNC12_IN_SEL_S = 0 +const GPIO_SIG13_IN_SEL_V = 0x1 +const GPIO_SIG13_IN_SEL_S = 7 +const GPIO_FUNC13_IN_INV_SEL_V = 0x1 +const GPIO_FUNC13_IN_INV_SEL_S = 6 +const GPIO_FUNC13_IN_SEL = 0x0000003F +const GPIO_FUNC13_IN_SEL_V = 0x3F +const GPIO_FUNC13_IN_SEL_S = 0 +const GPIO_SIG14_IN_SEL_V = 0x1 +const GPIO_SIG14_IN_SEL_S = 7 +const GPIO_FUNC14_IN_INV_SEL_V = 0x1 +const GPIO_FUNC14_IN_INV_SEL_S = 6 +const GPIO_FUNC14_IN_SEL = 0x0000003F +const GPIO_FUNC14_IN_SEL_V = 0x3F +const GPIO_FUNC14_IN_SEL_S = 0 +const GPIO_SIG15_IN_SEL_V = 0x1 +const GPIO_SIG15_IN_SEL_S = 7 +const GPIO_FUNC15_IN_INV_SEL_V = 0x1 +const GPIO_FUNC15_IN_INV_SEL_S = 6 +const GPIO_FUNC15_IN_SEL = 0x0000003F +const GPIO_FUNC15_IN_SEL_V = 0x3F +const GPIO_FUNC15_IN_SEL_S = 0 +const GPIO_SIG16_IN_SEL_V = 0x1 +const GPIO_SIG16_IN_SEL_S = 7 +const GPIO_FUNC16_IN_INV_SEL_V = 0x1 +const GPIO_FUNC16_IN_INV_SEL_S = 6 +const GPIO_FUNC16_IN_SEL = 0x0000003F +const GPIO_FUNC16_IN_SEL_V = 0x3F +const GPIO_FUNC16_IN_SEL_S = 0 +const GPIO_SIG17_IN_SEL_V = 0x1 +const GPIO_SIG17_IN_SEL_S = 7 +const GPIO_FUNC17_IN_INV_SEL_V = 0x1 +const GPIO_FUNC17_IN_INV_SEL_S = 6 +const GPIO_FUNC17_IN_SEL = 0x0000003F +const GPIO_FUNC17_IN_SEL_V = 0x3F +const GPIO_FUNC17_IN_SEL_S = 0 +const GPIO_SIG18_IN_SEL_V = 0x1 +const GPIO_SIG18_IN_SEL_S = 7 +const GPIO_FUNC18_IN_INV_SEL_V = 0x1 +const GPIO_FUNC18_IN_INV_SEL_S = 6 +const GPIO_FUNC18_IN_SEL = 0x0000003F +const GPIO_FUNC18_IN_SEL_V = 0x3F +const GPIO_FUNC18_IN_SEL_S = 0 +const GPIO_SIG19_IN_SEL_V = 0x1 +const GPIO_SIG19_IN_SEL_S = 7 +const GPIO_FUNC19_IN_INV_SEL_V = 0x1 +const GPIO_FUNC19_IN_INV_SEL_S = 6 +const GPIO_FUNC19_IN_SEL = 0x0000003F +const GPIO_FUNC19_IN_SEL_V = 0x3F +const GPIO_FUNC19_IN_SEL_S = 0 +const GPIO_SIG20_IN_SEL_V = 0x1 +const GPIO_SIG20_IN_SEL_S = 7 +const GPIO_FUNC20_IN_INV_SEL_V = 0x1 +const GPIO_FUNC20_IN_INV_SEL_S = 6 +const GPIO_FUNC20_IN_SEL = 0x0000003F +const GPIO_FUNC20_IN_SEL_V = 0x3F +const GPIO_FUNC20_IN_SEL_S = 0 +const GPIO_SIG21_IN_SEL_V = 0x1 +const GPIO_SIG21_IN_SEL_S = 7 +const GPIO_FUNC21_IN_INV_SEL_V = 0x1 +const GPIO_FUNC21_IN_INV_SEL_S = 6 +const GPIO_FUNC21_IN_SEL = 0x0000003F +const GPIO_FUNC21_IN_SEL_V = 0x3F +const GPIO_FUNC21_IN_SEL_S = 0 +const GPIO_SIG22_IN_SEL_V = 0x1 +const GPIO_SIG22_IN_SEL_S = 7 +const GPIO_FUNC22_IN_INV_SEL_V = 0x1 +const GPIO_FUNC22_IN_INV_SEL_S = 6 +const GPIO_FUNC22_IN_SEL = 0x0000003F +const GPIO_FUNC22_IN_SEL_V = 0x3F +const GPIO_FUNC22_IN_SEL_S = 0 +const GPIO_SIG23_IN_SEL_V = 0x1 +const GPIO_SIG23_IN_SEL_S = 7 +const GPIO_FUNC23_IN_INV_SEL_V = 0x1 +const GPIO_FUNC23_IN_INV_SEL_S = 6 +const GPIO_FUNC23_IN_SEL = 0x0000003F +const GPIO_FUNC23_IN_SEL_V = 0x3F +const GPIO_FUNC23_IN_SEL_S = 0 +const GPIO_SIG24_IN_SEL_V = 0x1 +const GPIO_SIG24_IN_SEL_S = 7 +const GPIO_FUNC24_IN_INV_SEL_V = 0x1 +const GPIO_FUNC24_IN_INV_SEL_S = 6 +const GPIO_FUNC24_IN_SEL = 0x0000003F +const GPIO_FUNC24_IN_SEL_V = 0x3F +const GPIO_FUNC24_IN_SEL_S = 0 +const GPIO_SIG25_IN_SEL_V = 0x1 +const GPIO_SIG25_IN_SEL_S = 7 +const GPIO_FUNC25_IN_INV_SEL_V = 0x1 +const GPIO_FUNC25_IN_INV_SEL_S = 6 +const GPIO_FUNC25_IN_SEL = 0x0000003F +const GPIO_FUNC25_IN_SEL_V = 0x3F +const GPIO_FUNC25_IN_SEL_S = 0 +const GPIO_SIG26_IN_SEL_V = 0x1 +const GPIO_SIG26_IN_SEL_S = 7 +const GPIO_FUNC26_IN_INV_SEL_V = 0x1 +const GPIO_FUNC26_IN_INV_SEL_S = 6 +const GPIO_FUNC26_IN_SEL = 0x0000003F +const GPIO_FUNC26_IN_SEL_V = 0x3F +const GPIO_FUNC26_IN_SEL_S = 0 +const GPIO_SIG27_IN_SEL_V = 0x1 +const GPIO_SIG27_IN_SEL_S = 7 +const GPIO_FUNC27_IN_INV_SEL_V = 0x1 +const GPIO_FUNC27_IN_INV_SEL_S = 6 +const GPIO_FUNC27_IN_SEL = 0x0000003F +const GPIO_FUNC27_IN_SEL_V = 0x3F +const GPIO_FUNC27_IN_SEL_S = 0 +const GPIO_SIG28_IN_SEL_V = 0x1 +const GPIO_SIG28_IN_SEL_S = 7 +const GPIO_FUNC28_IN_INV_SEL_V = 0x1 +const GPIO_FUNC28_IN_INV_SEL_S = 6 +const GPIO_FUNC28_IN_SEL = 0x0000003F +const GPIO_FUNC28_IN_SEL_V = 0x3F +const GPIO_FUNC28_IN_SEL_S = 0 +const GPIO_SIG29_IN_SEL_V = 0x1 +const GPIO_SIG29_IN_SEL_S = 7 +const GPIO_FUNC29_IN_INV_SEL_V = 0x1 +const GPIO_FUNC29_IN_INV_SEL_S = 6 +const GPIO_FUNC29_IN_SEL = 0x0000003F +const GPIO_FUNC29_IN_SEL_V = 0x3F +const GPIO_FUNC29_IN_SEL_S = 0 +const GPIO_SIG30_IN_SEL_V = 0x1 +const GPIO_SIG30_IN_SEL_S = 7 +const GPIO_FUNC30_IN_INV_SEL_V = 0x1 +const GPIO_FUNC30_IN_INV_SEL_S = 6 +const GPIO_FUNC30_IN_SEL = 0x0000003F +const GPIO_FUNC30_IN_SEL_V = 0x3F +const GPIO_FUNC30_IN_SEL_S = 0 +const GPIO_SIG31_IN_SEL_V = 0x1 +const GPIO_SIG31_IN_SEL_S = 7 +const GPIO_FUNC31_IN_INV_SEL_V = 0x1 +const GPIO_FUNC31_IN_INV_SEL_S = 6 +const GPIO_FUNC31_IN_SEL = 0x0000003F +const GPIO_FUNC31_IN_SEL_V = 0x3F +const GPIO_FUNC31_IN_SEL_S = 0 +const GPIO_SIG32_IN_SEL_V = 0x1 +const GPIO_SIG32_IN_SEL_S = 7 +const GPIO_FUNC32_IN_INV_SEL_V = 0x1 +const GPIO_FUNC32_IN_INV_SEL_S = 6 +const GPIO_FUNC32_IN_SEL = 0x0000003F +const GPIO_FUNC32_IN_SEL_V = 0x3F +const GPIO_FUNC32_IN_SEL_S = 0 +const GPIO_SIG33_IN_SEL_V = 0x1 +const GPIO_SIG33_IN_SEL_S = 7 +const GPIO_FUNC33_IN_INV_SEL_V = 0x1 +const GPIO_FUNC33_IN_INV_SEL_S = 6 +const GPIO_FUNC33_IN_SEL = 0x0000003F +const GPIO_FUNC33_IN_SEL_V = 0x3F +const GPIO_FUNC33_IN_SEL_S = 0 +const GPIO_SIG34_IN_SEL_V = 0x1 +const GPIO_SIG34_IN_SEL_S = 7 +const GPIO_FUNC34_IN_INV_SEL_V = 0x1 +const GPIO_FUNC34_IN_INV_SEL_S = 6 +const GPIO_FUNC34_IN_SEL = 0x0000003F +const GPIO_FUNC34_IN_SEL_V = 0x3F +const GPIO_FUNC34_IN_SEL_S = 0 +const GPIO_SIG35_IN_SEL_V = 0x1 +const GPIO_SIG35_IN_SEL_S = 7 +const GPIO_FUNC35_IN_INV_SEL_V = 0x1 +const GPIO_FUNC35_IN_INV_SEL_S = 6 +const GPIO_FUNC35_IN_SEL = 0x0000003F +const GPIO_FUNC35_IN_SEL_V = 0x3F +const GPIO_FUNC35_IN_SEL_S = 0 +const GPIO_SIG36_IN_SEL_V = 0x1 +const GPIO_SIG36_IN_SEL_S = 7 +const GPIO_FUNC36_IN_INV_SEL_V = 0x1 +const GPIO_FUNC36_IN_INV_SEL_S = 6 +const GPIO_FUNC36_IN_SEL = 0x0000003F +const GPIO_FUNC36_IN_SEL_V = 0x3F +const GPIO_FUNC36_IN_SEL_S = 0 +const GPIO_SIG37_IN_SEL_V = 0x1 +const GPIO_SIG37_IN_SEL_S = 7 +const GPIO_FUNC37_IN_INV_SEL_V = 0x1 +const GPIO_FUNC37_IN_INV_SEL_S = 6 +const GPIO_FUNC37_IN_SEL = 0x0000003F +const GPIO_FUNC37_IN_SEL_V = 0x3F +const GPIO_FUNC37_IN_SEL_S = 0 +const GPIO_SIG38_IN_SEL_V = 0x1 +const GPIO_SIG38_IN_SEL_S = 7 +const GPIO_FUNC38_IN_INV_SEL_V = 0x1 +const GPIO_FUNC38_IN_INV_SEL_S = 6 +const GPIO_FUNC38_IN_SEL = 0x0000003F +const GPIO_FUNC38_IN_SEL_V = 0x3F +const GPIO_FUNC38_IN_SEL_S = 0 +const GPIO_SIG39_IN_SEL_V = 0x1 +const GPIO_SIG39_IN_SEL_S = 7 +const GPIO_FUNC39_IN_INV_SEL_V = 0x1 +const GPIO_FUNC39_IN_INV_SEL_S = 6 +const GPIO_FUNC39_IN_SEL = 0x0000003F +const GPIO_FUNC39_IN_SEL_V = 0x3F +const GPIO_FUNC39_IN_SEL_S = 0 +const GPIO_SIG40_IN_SEL_V = 0x1 +const GPIO_SIG40_IN_SEL_S = 7 +const GPIO_FUNC40_IN_INV_SEL_V = 0x1 +const GPIO_FUNC40_IN_INV_SEL_S = 6 +const GPIO_FUNC40_IN_SEL = 0x0000003F +const GPIO_FUNC40_IN_SEL_V = 0x3F +const GPIO_FUNC40_IN_SEL_S = 0 +const GPIO_SIG41_IN_SEL_V = 0x1 +const GPIO_SIG41_IN_SEL_S = 7 +const GPIO_FUNC41_IN_INV_SEL_V = 0x1 +const GPIO_FUNC41_IN_INV_SEL_S = 6 +const GPIO_FUNC41_IN_SEL = 0x0000003F +const GPIO_FUNC41_IN_SEL_V = 0x3F +const GPIO_FUNC41_IN_SEL_S = 0 +const GPIO_SIG42_IN_SEL_V = 0x1 +const GPIO_SIG42_IN_SEL_S = 7 +const GPIO_FUNC42_IN_INV_SEL_V = 0x1 +const GPIO_FUNC42_IN_INV_SEL_S = 6 +const GPIO_FUNC42_IN_SEL = 0x0000003F +const GPIO_FUNC42_IN_SEL_V = 0x3F +const GPIO_FUNC42_IN_SEL_S = 0 +const GPIO_SIG43_IN_SEL_V = 0x1 +const GPIO_SIG43_IN_SEL_S = 7 +const GPIO_FUNC43_IN_INV_SEL_V = 0x1 +const GPIO_FUNC43_IN_INV_SEL_S = 6 +const GPIO_FUNC43_IN_SEL = 0x0000003F +const GPIO_FUNC43_IN_SEL_V = 0x3F +const GPIO_FUNC43_IN_SEL_S = 0 +const GPIO_SIG44_IN_SEL_V = 0x1 +const GPIO_SIG44_IN_SEL_S = 7 +const GPIO_FUNC44_IN_INV_SEL_V = 0x1 +const GPIO_FUNC44_IN_INV_SEL_S = 6 +const GPIO_FUNC44_IN_SEL = 0x0000003F +const GPIO_FUNC44_IN_SEL_V = 0x3F +const GPIO_FUNC44_IN_SEL_S = 0 +const GPIO_SIG45_IN_SEL_V = 0x1 +const GPIO_SIG45_IN_SEL_S = 7 +const GPIO_FUNC45_IN_INV_SEL_V = 0x1 +const GPIO_FUNC45_IN_INV_SEL_S = 6 +const GPIO_FUNC45_IN_SEL = 0x0000003F +const GPIO_FUNC45_IN_SEL_V = 0x3F +const GPIO_FUNC45_IN_SEL_S = 0 +const GPIO_SIG46_IN_SEL_V = 0x1 +const GPIO_SIG46_IN_SEL_S = 7 +const GPIO_FUNC46_IN_INV_SEL_V = 0x1 +const GPIO_FUNC46_IN_INV_SEL_S = 6 +const GPIO_FUNC46_IN_SEL = 0x0000003F +const GPIO_FUNC46_IN_SEL_V = 0x3F +const GPIO_FUNC46_IN_SEL_S = 0 +const GPIO_SIG47_IN_SEL_V = 0x1 +const GPIO_SIG47_IN_SEL_S = 7 +const GPIO_FUNC47_IN_INV_SEL_V = 0x1 +const GPIO_FUNC47_IN_INV_SEL_S = 6 +const GPIO_FUNC47_IN_SEL = 0x0000003F +const GPIO_FUNC47_IN_SEL_V = 0x3F +const GPIO_FUNC47_IN_SEL_S = 0 +const GPIO_SIG48_IN_SEL_V = 0x1 +const GPIO_SIG48_IN_SEL_S = 7 +const GPIO_FUNC48_IN_INV_SEL_V = 0x1 +const GPIO_FUNC48_IN_INV_SEL_S = 6 +const GPIO_FUNC48_IN_SEL = 0x0000003F +const GPIO_FUNC48_IN_SEL_V = 0x3F +const GPIO_FUNC48_IN_SEL_S = 0 +const GPIO_SIG49_IN_SEL_V = 0x1 +const GPIO_SIG49_IN_SEL_S = 7 +const GPIO_FUNC49_IN_INV_SEL_V = 0x1 +const GPIO_FUNC49_IN_INV_SEL_S = 6 +const GPIO_FUNC49_IN_SEL = 0x0000003F +const GPIO_FUNC49_IN_SEL_V = 0x3F +const GPIO_FUNC49_IN_SEL_S = 0 +const GPIO_SIG50_IN_SEL_V = 0x1 +const GPIO_SIG50_IN_SEL_S = 7 +const GPIO_FUNC50_IN_INV_SEL_V = 0x1 +const GPIO_FUNC50_IN_INV_SEL_S = 6 +const GPIO_FUNC50_IN_SEL = 0x0000003F +const GPIO_FUNC50_IN_SEL_V = 0x3F +const GPIO_FUNC50_IN_SEL_S = 0 +const GPIO_SIG51_IN_SEL_V = 0x1 +const GPIO_SIG51_IN_SEL_S = 7 +const GPIO_FUNC51_IN_INV_SEL_V = 0x1 +const GPIO_FUNC51_IN_INV_SEL_S = 6 +const GPIO_FUNC51_IN_SEL = 0x0000003F +const GPIO_FUNC51_IN_SEL_V = 0x3F +const GPIO_FUNC51_IN_SEL_S = 0 +const GPIO_SIG52_IN_SEL_V = 0x1 +const GPIO_SIG52_IN_SEL_S = 7 +const GPIO_FUNC52_IN_INV_SEL_V = 0x1 +const GPIO_FUNC52_IN_INV_SEL_S = 6 +const GPIO_FUNC52_IN_SEL = 0x0000003F +const GPIO_FUNC52_IN_SEL_V = 0x3F +const GPIO_FUNC52_IN_SEL_S = 0 +const GPIO_SIG53_IN_SEL_V = 0x1 +const GPIO_SIG53_IN_SEL_S = 7 +const GPIO_FUNC53_IN_INV_SEL_V = 0x1 +const GPIO_FUNC53_IN_INV_SEL_S = 6 +const GPIO_FUNC53_IN_SEL = 0x0000003F +const GPIO_FUNC53_IN_SEL_V = 0x3F +const GPIO_FUNC53_IN_SEL_S = 0 +const GPIO_SIG54_IN_SEL_V = 0x1 +const GPIO_SIG54_IN_SEL_S = 7 +const GPIO_FUNC54_IN_INV_SEL_V = 0x1 +const GPIO_FUNC54_IN_INV_SEL_S = 6 +const GPIO_FUNC54_IN_SEL = 0x0000003F +const GPIO_FUNC54_IN_SEL_V = 0x3F +const GPIO_FUNC54_IN_SEL_S = 0 +const GPIO_SIG55_IN_SEL_V = 0x1 +const GPIO_SIG55_IN_SEL_S = 7 +const GPIO_FUNC55_IN_INV_SEL_V = 0x1 +const GPIO_FUNC55_IN_INV_SEL_S = 6 +const GPIO_FUNC55_IN_SEL = 0x0000003F +const GPIO_FUNC55_IN_SEL_V = 0x3F +const GPIO_FUNC55_IN_SEL_S = 0 +const GPIO_SIG56_IN_SEL_V = 0x1 +const GPIO_SIG56_IN_SEL_S = 7 +const GPIO_FUNC56_IN_INV_SEL_V = 0x1 +const GPIO_FUNC56_IN_INV_SEL_S = 6 +const GPIO_FUNC56_IN_SEL = 0x0000003F +const GPIO_FUNC56_IN_SEL_V = 0x3F +const GPIO_FUNC56_IN_SEL_S = 0 +const GPIO_SIG57_IN_SEL_V = 0x1 +const GPIO_SIG57_IN_SEL_S = 7 +const GPIO_FUNC57_IN_INV_SEL_V = 0x1 +const GPIO_FUNC57_IN_INV_SEL_S = 6 +const GPIO_FUNC57_IN_SEL = 0x0000003F +const GPIO_FUNC57_IN_SEL_V = 0x3F +const GPIO_FUNC57_IN_SEL_S = 0 +const GPIO_SIG58_IN_SEL_V = 0x1 +const GPIO_SIG58_IN_SEL_S = 7 +const GPIO_FUNC58_IN_INV_SEL_V = 0x1 +const GPIO_FUNC58_IN_INV_SEL_S = 6 +const GPIO_FUNC58_IN_SEL = 0x0000003F +const GPIO_FUNC58_IN_SEL_V = 0x3F +const GPIO_FUNC58_IN_SEL_S = 0 +const GPIO_SIG59_IN_SEL_V = 0x1 +const GPIO_SIG59_IN_SEL_S = 7 +const GPIO_FUNC59_IN_INV_SEL_V = 0x1 +const GPIO_FUNC59_IN_INV_SEL_S = 6 +const GPIO_FUNC59_IN_SEL = 0x0000003F +const GPIO_FUNC59_IN_SEL_V = 0x3F +const GPIO_FUNC59_IN_SEL_S = 0 +const GPIO_SIG60_IN_SEL_V = 0x1 +const GPIO_SIG60_IN_SEL_S = 7 +const GPIO_FUNC60_IN_INV_SEL_V = 0x1 +const GPIO_FUNC60_IN_INV_SEL_S = 6 +const GPIO_FUNC60_IN_SEL = 0x0000003F +const GPIO_FUNC60_IN_SEL_V = 0x3F +const GPIO_FUNC60_IN_SEL_S = 0 +const GPIO_SIG61_IN_SEL_V = 0x1 +const GPIO_SIG61_IN_SEL_S = 7 +const GPIO_FUNC61_IN_INV_SEL_V = 0x1 +const GPIO_FUNC61_IN_INV_SEL_S = 6 +const GPIO_FUNC61_IN_SEL = 0x0000003F +const GPIO_FUNC61_IN_SEL_V = 0x3F +const GPIO_FUNC61_IN_SEL_S = 0 +const GPIO_SIG62_IN_SEL_V = 0x1 +const GPIO_SIG62_IN_SEL_S = 7 +const GPIO_FUNC62_IN_INV_SEL_V = 0x1 +const GPIO_FUNC62_IN_INV_SEL_S = 6 +const GPIO_FUNC62_IN_SEL = 0x0000003F +const GPIO_FUNC62_IN_SEL_V = 0x3F +const GPIO_FUNC62_IN_SEL_S = 0 +const GPIO_SIG63_IN_SEL_V = 0x1 +const GPIO_SIG63_IN_SEL_S = 7 +const GPIO_FUNC63_IN_INV_SEL_V = 0x1 +const GPIO_FUNC63_IN_INV_SEL_S = 6 +const GPIO_FUNC63_IN_SEL = 0x0000003F +const GPIO_FUNC63_IN_SEL_V = 0x3F +const GPIO_FUNC63_IN_SEL_S = 0 +const GPIO_SIG64_IN_SEL_V = 0x1 +const GPIO_SIG64_IN_SEL_S = 7 +const GPIO_FUNC64_IN_INV_SEL_V = 0x1 +const GPIO_FUNC64_IN_INV_SEL_S = 6 +const GPIO_FUNC64_IN_SEL = 0x0000003F +const GPIO_FUNC64_IN_SEL_V = 0x3F +const GPIO_FUNC64_IN_SEL_S = 0 +const GPIO_SIG65_IN_SEL_V = 0x1 +const GPIO_SIG65_IN_SEL_S = 7 +const GPIO_FUNC65_IN_INV_SEL_V = 0x1 +const GPIO_FUNC65_IN_INV_SEL_S = 6 +const GPIO_FUNC65_IN_SEL = 0x0000003F +const GPIO_FUNC65_IN_SEL_V = 0x3F +const GPIO_FUNC65_IN_SEL_S = 0 +const GPIO_SIG66_IN_SEL_V = 0x1 +const GPIO_SIG66_IN_SEL_S = 7 +const GPIO_FUNC66_IN_INV_SEL_V = 0x1 +const GPIO_FUNC66_IN_INV_SEL_S = 6 +const GPIO_FUNC66_IN_SEL = 0x0000003F +const GPIO_FUNC66_IN_SEL_V = 0x3F +const GPIO_FUNC66_IN_SEL_S = 0 +const GPIO_SIG67_IN_SEL_V = 0x1 +const GPIO_SIG67_IN_SEL_S = 7 +const GPIO_FUNC67_IN_INV_SEL_V = 0x1 +const GPIO_FUNC67_IN_INV_SEL_S = 6 +const GPIO_FUNC67_IN_SEL = 0x0000003F +const GPIO_FUNC67_IN_SEL_V = 0x3F +const GPIO_FUNC67_IN_SEL_S = 0 +const GPIO_SIG68_IN_SEL_V = 0x1 +const GPIO_SIG68_IN_SEL_S = 7 +const GPIO_FUNC68_IN_INV_SEL_V = 0x1 +const GPIO_FUNC68_IN_INV_SEL_S = 6 +const GPIO_FUNC68_IN_SEL = 0x0000003F +const GPIO_FUNC68_IN_SEL_V = 0x3F +const GPIO_FUNC68_IN_SEL_S = 0 +const GPIO_SIG69_IN_SEL_V = 0x1 +const GPIO_SIG69_IN_SEL_S = 7 +const GPIO_FUNC69_IN_INV_SEL_V = 0x1 +const GPIO_FUNC69_IN_INV_SEL_S = 6 +const GPIO_FUNC69_IN_SEL = 0x0000003F +const GPIO_FUNC69_IN_SEL_V = 0x3F +const GPIO_FUNC69_IN_SEL_S = 0 +const GPIO_SIG70_IN_SEL_V = 0x1 +const GPIO_SIG70_IN_SEL_S = 7 +const GPIO_FUNC70_IN_INV_SEL_V = 0x1 +const GPIO_FUNC70_IN_INV_SEL_S = 6 +const GPIO_FUNC70_IN_SEL = 0x0000003F +const GPIO_FUNC70_IN_SEL_V = 0x3F +const GPIO_FUNC70_IN_SEL_S = 0 +const GPIO_SIG71_IN_SEL_V = 0x1 +const GPIO_SIG71_IN_SEL_S = 7 +const GPIO_FUNC71_IN_INV_SEL_V = 0x1 +const GPIO_FUNC71_IN_INV_SEL_S = 6 +const GPIO_FUNC71_IN_SEL = 0x0000003F +const GPIO_FUNC71_IN_SEL_V = 0x3F +const GPIO_FUNC71_IN_SEL_S = 0 +const GPIO_SIG72_IN_SEL_V = 0x1 +const GPIO_SIG72_IN_SEL_S = 7 +const GPIO_FUNC72_IN_INV_SEL_V = 0x1 +const GPIO_FUNC72_IN_INV_SEL_S = 6 +const GPIO_FUNC72_IN_SEL = 0x0000003F +const GPIO_FUNC72_IN_SEL_V = 0x3F +const GPIO_FUNC72_IN_SEL_S = 0 +const GPIO_SIG73_IN_SEL_V = 0x1 +const GPIO_SIG73_IN_SEL_S = 7 +const GPIO_FUNC73_IN_INV_SEL_V = 0x1 +const GPIO_FUNC73_IN_INV_SEL_S = 6 +const GPIO_FUNC73_IN_SEL = 0x0000003F +const GPIO_FUNC73_IN_SEL_V = 0x3F +const GPIO_FUNC73_IN_SEL_S = 0 +const GPIO_SIG74_IN_SEL_V = 0x1 +const GPIO_SIG74_IN_SEL_S = 7 +const GPIO_FUNC74_IN_INV_SEL_V = 0x1 +const GPIO_FUNC74_IN_INV_SEL_S = 6 +const GPIO_FUNC74_IN_SEL = 0x0000003F +const GPIO_FUNC74_IN_SEL_V = 0x3F +const GPIO_FUNC74_IN_SEL_S = 0 +const GPIO_SIG75_IN_SEL_V = 0x1 +const GPIO_SIG75_IN_SEL_S = 7 +const GPIO_FUNC75_IN_INV_SEL_V = 0x1 +const GPIO_FUNC75_IN_INV_SEL_S = 6 +const GPIO_FUNC75_IN_SEL = 0x0000003F +const GPIO_FUNC75_IN_SEL_V = 0x3F +const GPIO_FUNC75_IN_SEL_S = 0 +const GPIO_SIG76_IN_SEL_V = 0x1 +const GPIO_SIG76_IN_SEL_S = 7 +const GPIO_FUNC76_IN_INV_SEL_V = 0x1 +const GPIO_FUNC76_IN_INV_SEL_S = 6 +const GPIO_FUNC76_IN_SEL = 0x0000003F +const GPIO_FUNC76_IN_SEL_V = 0x3F +const GPIO_FUNC76_IN_SEL_S = 0 +const GPIO_SIG77_IN_SEL_V = 0x1 +const GPIO_SIG77_IN_SEL_S = 7 +const GPIO_FUNC77_IN_INV_SEL_V = 0x1 +const GPIO_FUNC77_IN_INV_SEL_S = 6 +const GPIO_FUNC77_IN_SEL = 0x0000003F +const GPIO_FUNC77_IN_SEL_V = 0x3F +const GPIO_FUNC77_IN_SEL_S = 0 +const GPIO_SIG78_IN_SEL_V = 0x1 +const GPIO_SIG78_IN_SEL_S = 7 +const GPIO_FUNC78_IN_INV_SEL_V = 0x1 +const GPIO_FUNC78_IN_INV_SEL_S = 6 +const GPIO_FUNC78_IN_SEL = 0x0000003F +const GPIO_FUNC78_IN_SEL_V = 0x3F +const GPIO_FUNC78_IN_SEL_S = 0 +const GPIO_SIG79_IN_SEL_V = 0x1 +const GPIO_SIG79_IN_SEL_S = 7 +const GPIO_FUNC79_IN_INV_SEL_V = 0x1 +const GPIO_FUNC79_IN_INV_SEL_S = 6 +const GPIO_FUNC79_IN_SEL = 0x0000003F +const GPIO_FUNC79_IN_SEL_V = 0x3F +const GPIO_FUNC79_IN_SEL_S = 0 +const GPIO_SIG80_IN_SEL_V = 0x1 +const GPIO_SIG80_IN_SEL_S = 7 +const GPIO_FUNC80_IN_INV_SEL_V = 0x1 +const GPIO_FUNC80_IN_INV_SEL_S = 6 +const GPIO_FUNC80_IN_SEL = 0x0000003F +const GPIO_FUNC80_IN_SEL_V = 0x3F +const GPIO_FUNC80_IN_SEL_S = 0 +const GPIO_SIG81_IN_SEL_V = 0x1 +const GPIO_SIG81_IN_SEL_S = 7 +const GPIO_FUNC81_IN_INV_SEL_V = 0x1 +const GPIO_FUNC81_IN_INV_SEL_S = 6 +const GPIO_FUNC81_IN_SEL = 0x0000003F +const GPIO_FUNC81_IN_SEL_V = 0x3F +const GPIO_FUNC81_IN_SEL_S = 0 +const GPIO_SIG82_IN_SEL_V = 0x1 +const GPIO_SIG82_IN_SEL_S = 7 +const GPIO_FUNC82_IN_INV_SEL_V = 0x1 +const GPIO_FUNC82_IN_INV_SEL_S = 6 +const GPIO_FUNC82_IN_SEL = 0x0000003F +const GPIO_FUNC82_IN_SEL_V = 0x3F +const GPIO_FUNC82_IN_SEL_S = 0 +const GPIO_SIG83_IN_SEL_V = 0x1 +const GPIO_SIG83_IN_SEL_S = 7 +const GPIO_FUNC83_IN_INV_SEL_V = 0x1 +const GPIO_FUNC83_IN_INV_SEL_S = 6 +const GPIO_FUNC83_IN_SEL = 0x0000003F +const GPIO_FUNC83_IN_SEL_V = 0x3F +const GPIO_FUNC83_IN_SEL_S = 0 +const GPIO_SIG84_IN_SEL_V = 0x1 +const GPIO_SIG84_IN_SEL_S = 7 +const GPIO_FUNC84_IN_INV_SEL_V = 0x1 +const GPIO_FUNC84_IN_INV_SEL_S = 6 +const GPIO_FUNC84_IN_SEL = 0x0000003F +const GPIO_FUNC84_IN_SEL_V = 0x3F +const GPIO_FUNC84_IN_SEL_S = 0 +const GPIO_SIG85_IN_SEL_V = 0x1 +const GPIO_SIG85_IN_SEL_S = 7 +const GPIO_FUNC85_IN_INV_SEL_V = 0x1 +const GPIO_FUNC85_IN_INV_SEL_S = 6 +const GPIO_FUNC85_IN_SEL = 0x0000003F +const GPIO_FUNC85_IN_SEL_V = 0x3F +const GPIO_FUNC85_IN_SEL_S = 0 +const GPIO_SIG86_IN_SEL_V = 0x1 +const GPIO_SIG86_IN_SEL_S = 7 +const GPIO_FUNC86_IN_INV_SEL_V = 0x1 +const GPIO_FUNC86_IN_INV_SEL_S = 6 +const GPIO_FUNC86_IN_SEL = 0x0000003F +const GPIO_FUNC86_IN_SEL_V = 0x3F +const GPIO_FUNC86_IN_SEL_S = 0 +const GPIO_SIG87_IN_SEL_V = 0x1 +const GPIO_SIG87_IN_SEL_S = 7 +const GPIO_FUNC87_IN_INV_SEL_V = 0x1 +const GPIO_FUNC87_IN_INV_SEL_S = 6 +const GPIO_FUNC87_IN_SEL = 0x0000003F +const GPIO_FUNC87_IN_SEL_V = 0x3F +const GPIO_FUNC87_IN_SEL_S = 0 +const GPIO_SIG88_IN_SEL_V = 0x1 +const GPIO_SIG88_IN_SEL_S = 7 +const GPIO_FUNC88_IN_INV_SEL_V = 0x1 +const GPIO_FUNC88_IN_INV_SEL_S = 6 +const GPIO_FUNC88_IN_SEL = 0x0000003F +const GPIO_FUNC88_IN_SEL_V = 0x3F +const GPIO_FUNC88_IN_SEL_S = 0 +const GPIO_SIG89_IN_SEL_V = 0x1 +const GPIO_SIG89_IN_SEL_S = 7 +const GPIO_FUNC89_IN_INV_SEL_V = 0x1 +const GPIO_FUNC89_IN_INV_SEL_S = 6 +const GPIO_FUNC89_IN_SEL = 0x0000003F +const GPIO_FUNC89_IN_SEL_V = 0x3F +const GPIO_FUNC89_IN_SEL_S = 0 +const GPIO_SIG90_IN_SEL_V = 0x1 +const GPIO_SIG90_IN_SEL_S = 7 +const GPIO_FUNC90_IN_INV_SEL_V = 0x1 +const GPIO_FUNC90_IN_INV_SEL_S = 6 +const GPIO_FUNC90_IN_SEL = 0x0000003F +const GPIO_FUNC90_IN_SEL_V = 0x3F +const GPIO_FUNC90_IN_SEL_S = 0 +const GPIO_SIG91_IN_SEL_V = 0x1 +const GPIO_SIG91_IN_SEL_S = 7 +const GPIO_FUNC91_IN_INV_SEL_V = 0x1 +const GPIO_FUNC91_IN_INV_SEL_S = 6 +const GPIO_FUNC91_IN_SEL = 0x0000003F +const GPIO_FUNC91_IN_SEL_V = 0x3F +const GPIO_FUNC91_IN_SEL_S = 0 +const GPIO_SIG92_IN_SEL_V = 0x1 +const GPIO_SIG92_IN_SEL_S = 7 +const GPIO_FUNC92_IN_INV_SEL_V = 0x1 +const GPIO_FUNC92_IN_INV_SEL_S = 6 +const GPIO_FUNC92_IN_SEL = 0x0000003F +const GPIO_FUNC92_IN_SEL_V = 0x3F +const GPIO_FUNC92_IN_SEL_S = 0 +const GPIO_SIG93_IN_SEL_V = 0x1 +const GPIO_SIG93_IN_SEL_S = 7 +const GPIO_FUNC93_IN_INV_SEL_V = 0x1 +const GPIO_FUNC93_IN_INV_SEL_S = 6 +const GPIO_FUNC93_IN_SEL = 0x0000003F +const GPIO_FUNC93_IN_SEL_V = 0x3F +const GPIO_FUNC93_IN_SEL_S = 0 +const GPIO_SIG94_IN_SEL_V = 0x1 +const GPIO_SIG94_IN_SEL_S = 7 +const GPIO_FUNC94_IN_INV_SEL_V = 0x1 +const GPIO_FUNC94_IN_INV_SEL_S = 6 +const GPIO_FUNC94_IN_SEL = 0x0000003F +const GPIO_FUNC94_IN_SEL_V = 0x3F +const GPIO_FUNC94_IN_SEL_S = 0 +const GPIO_SIG95_IN_SEL_V = 0x1 +const GPIO_SIG95_IN_SEL_S = 7 +const GPIO_FUNC95_IN_INV_SEL_V = 0x1 +const GPIO_FUNC95_IN_INV_SEL_S = 6 +const GPIO_FUNC95_IN_SEL = 0x0000003F +const GPIO_FUNC95_IN_SEL_V = 0x3F +const GPIO_FUNC95_IN_SEL_S = 0 +const GPIO_SIG96_IN_SEL_V = 0x1 +const GPIO_SIG96_IN_SEL_S = 7 +const GPIO_FUNC96_IN_INV_SEL_V = 0x1 +const GPIO_FUNC96_IN_INV_SEL_S = 6 +const GPIO_FUNC96_IN_SEL = 0x0000003F +const GPIO_FUNC96_IN_SEL_V = 0x3F +const GPIO_FUNC96_IN_SEL_S = 0 +const GPIO_SIG97_IN_SEL_V = 0x1 +const GPIO_SIG97_IN_SEL_S = 7 +const GPIO_FUNC97_IN_INV_SEL_V = 0x1 +const GPIO_FUNC97_IN_INV_SEL_S = 6 +const GPIO_FUNC97_IN_SEL = 0x0000003F +const GPIO_FUNC97_IN_SEL_V = 0x3F +const GPIO_FUNC97_IN_SEL_S = 0 +const GPIO_SIG98_IN_SEL_V = 0x1 +const GPIO_SIG98_IN_SEL_S = 7 +const GPIO_FUNC98_IN_INV_SEL_V = 0x1 +const GPIO_FUNC98_IN_INV_SEL_S = 6 +const GPIO_FUNC98_IN_SEL = 0x0000003F +const GPIO_FUNC98_IN_SEL_V = 0x3F +const GPIO_FUNC98_IN_SEL_S = 0 +const GPIO_SIG99_IN_SEL_V = 0x1 +const GPIO_SIG99_IN_SEL_S = 7 +const GPIO_FUNC99_IN_INV_SEL_V = 0x1 +const GPIO_FUNC99_IN_INV_SEL_S = 6 +const GPIO_FUNC99_IN_SEL = 0x0000003F +const GPIO_FUNC99_IN_SEL_V = 0x3F +const GPIO_FUNC99_IN_SEL_S = 0 +const GPIO_SIG100_IN_SEL_V = 0x1 +const GPIO_SIG100_IN_SEL_S = 7 +const GPIO_FUNC100_IN_INV_SEL_V = 0x1 +const GPIO_FUNC100_IN_INV_SEL_S = 6 +const GPIO_FUNC100_IN_SEL = 0x0000003F +const GPIO_FUNC100_IN_SEL_V = 0x3F +const GPIO_FUNC100_IN_SEL_S = 0 +const GPIO_SIG101_IN_SEL_V = 0x1 +const GPIO_SIG101_IN_SEL_S = 7 +const GPIO_FUNC101_IN_INV_SEL_V = 0x1 +const GPIO_FUNC101_IN_INV_SEL_S = 6 +const GPIO_FUNC101_IN_SEL = 0x0000003F +const GPIO_FUNC101_IN_SEL_V = 0x3F +const GPIO_FUNC101_IN_SEL_S = 0 +const GPIO_SIG102_IN_SEL_V = 0x1 +const GPIO_SIG102_IN_SEL_S = 7 +const GPIO_FUNC102_IN_INV_SEL_V = 0x1 +const GPIO_FUNC102_IN_INV_SEL_S = 6 +const GPIO_FUNC102_IN_SEL = 0x0000003F +const GPIO_FUNC102_IN_SEL_V = 0x3F +const GPIO_FUNC102_IN_SEL_S = 0 +const GPIO_SIG103_IN_SEL_V = 0x1 +const GPIO_SIG103_IN_SEL_S = 7 +const GPIO_FUNC103_IN_INV_SEL_V = 0x1 +const GPIO_FUNC103_IN_INV_SEL_S = 6 +const GPIO_FUNC103_IN_SEL = 0x0000003F +const GPIO_FUNC103_IN_SEL_V = 0x3F +const GPIO_FUNC103_IN_SEL_S = 0 +const GPIO_SIG104_IN_SEL_V = 0x1 +const GPIO_SIG104_IN_SEL_S = 7 +const GPIO_FUNC104_IN_INV_SEL_V = 0x1 +const GPIO_FUNC104_IN_INV_SEL_S = 6 +const GPIO_FUNC104_IN_SEL = 0x0000003F +const GPIO_FUNC104_IN_SEL_V = 0x3F +const GPIO_FUNC104_IN_SEL_S = 0 +const GPIO_SIG105_IN_SEL_V = 0x1 +const GPIO_SIG105_IN_SEL_S = 7 +const GPIO_FUNC105_IN_INV_SEL_V = 0x1 +const GPIO_FUNC105_IN_INV_SEL_S = 6 +const GPIO_FUNC105_IN_SEL = 0x0000003F +const GPIO_FUNC105_IN_SEL_V = 0x3F +const GPIO_FUNC105_IN_SEL_S = 0 +const GPIO_SIG106_IN_SEL_V = 0x1 +const GPIO_SIG106_IN_SEL_S = 7 +const GPIO_FUNC106_IN_INV_SEL_V = 0x1 +const GPIO_FUNC106_IN_INV_SEL_S = 6 +const GPIO_FUNC106_IN_SEL = 0x0000003F +const GPIO_FUNC106_IN_SEL_V = 0x3F +const GPIO_FUNC106_IN_SEL_S = 0 +const GPIO_SIG107_IN_SEL_V = 0x1 +const GPIO_SIG107_IN_SEL_S = 7 +const GPIO_FUNC107_IN_INV_SEL_V = 0x1 +const GPIO_FUNC107_IN_INV_SEL_S = 6 +const GPIO_FUNC107_IN_SEL = 0x0000003F +const GPIO_FUNC107_IN_SEL_V = 0x3F +const GPIO_FUNC107_IN_SEL_S = 0 +const GPIO_SIG108_IN_SEL_V = 0x1 +const GPIO_SIG108_IN_SEL_S = 7 +const GPIO_FUNC108_IN_INV_SEL_V = 0x1 +const GPIO_FUNC108_IN_INV_SEL_S = 6 +const GPIO_FUNC108_IN_SEL = 0x0000003F +const GPIO_FUNC108_IN_SEL_V = 0x3F +const GPIO_FUNC108_IN_SEL_S = 0 +const GPIO_SIG109_IN_SEL_V = 0x1 +const GPIO_SIG109_IN_SEL_S = 7 +const GPIO_FUNC109_IN_INV_SEL_V = 0x1 +const GPIO_FUNC109_IN_INV_SEL_S = 6 +const GPIO_FUNC109_IN_SEL = 0x0000003F +const GPIO_FUNC109_IN_SEL_V = 0x3F +const GPIO_FUNC109_IN_SEL_S = 0 +const GPIO_SIG110_IN_SEL_V = 0x1 +const GPIO_SIG110_IN_SEL_S = 7 +const GPIO_FUNC110_IN_INV_SEL_V = 0x1 +const GPIO_FUNC110_IN_INV_SEL_S = 6 +const GPIO_FUNC110_IN_SEL = 0x0000003F +const GPIO_FUNC110_IN_SEL_V = 0x3F +const GPIO_FUNC110_IN_SEL_S = 0 +const GPIO_SIG111_IN_SEL_V = 0x1 +const GPIO_SIG111_IN_SEL_S = 7 +const GPIO_FUNC111_IN_INV_SEL_V = 0x1 +const GPIO_FUNC111_IN_INV_SEL_S = 6 +const GPIO_FUNC111_IN_SEL = 0x0000003F +const GPIO_FUNC111_IN_SEL_V = 0x3F +const GPIO_FUNC111_IN_SEL_S = 0 +const GPIO_SIG112_IN_SEL_V = 0x1 +const GPIO_SIG112_IN_SEL_S = 7 +const GPIO_FUNC112_IN_INV_SEL_V = 0x1 +const GPIO_FUNC112_IN_INV_SEL_S = 6 +const GPIO_FUNC112_IN_SEL = 0x0000003F +const GPIO_FUNC112_IN_SEL_V = 0x3F +const GPIO_FUNC112_IN_SEL_S = 0 +const GPIO_SIG113_IN_SEL_V = 0x1 +const GPIO_SIG113_IN_SEL_S = 7 +const GPIO_FUNC113_IN_INV_SEL_V = 0x1 +const GPIO_FUNC113_IN_INV_SEL_S = 6 +const GPIO_FUNC113_IN_SEL = 0x0000003F +const GPIO_FUNC113_IN_SEL_V = 0x3F +const GPIO_FUNC113_IN_SEL_S = 0 +const GPIO_SIG114_IN_SEL_V = 0x1 +const GPIO_SIG114_IN_SEL_S = 7 +const GPIO_FUNC114_IN_INV_SEL_V = 0x1 +const GPIO_FUNC114_IN_INV_SEL_S = 6 +const GPIO_FUNC114_IN_SEL = 0x0000003F +const GPIO_FUNC114_IN_SEL_V = 0x3F +const GPIO_FUNC114_IN_SEL_S = 0 +const GPIO_SIG115_IN_SEL_V = 0x1 +const GPIO_SIG115_IN_SEL_S = 7 +const GPIO_FUNC115_IN_INV_SEL_V = 0x1 +const GPIO_FUNC115_IN_INV_SEL_S = 6 +const GPIO_FUNC115_IN_SEL = 0x0000003F +const GPIO_FUNC115_IN_SEL_V = 0x3F +const GPIO_FUNC115_IN_SEL_S = 0 +const GPIO_SIG116_IN_SEL_V = 0x1 +const GPIO_SIG116_IN_SEL_S = 7 +const GPIO_FUNC116_IN_INV_SEL_V = 0x1 +const GPIO_FUNC116_IN_INV_SEL_S = 6 +const GPIO_FUNC116_IN_SEL = 0x0000003F +const GPIO_FUNC116_IN_SEL_V = 0x3F +const GPIO_FUNC116_IN_SEL_S = 0 +const GPIO_SIG117_IN_SEL_V = 0x1 +const GPIO_SIG117_IN_SEL_S = 7 +const GPIO_FUNC117_IN_INV_SEL_V = 0x1 +const GPIO_FUNC117_IN_INV_SEL_S = 6 +const GPIO_FUNC117_IN_SEL = 0x0000003F +const GPIO_FUNC117_IN_SEL_V = 0x3F +const GPIO_FUNC117_IN_SEL_S = 0 +const GPIO_SIG118_IN_SEL_V = 0x1 +const GPIO_SIG118_IN_SEL_S = 7 +const GPIO_FUNC118_IN_INV_SEL_V = 0x1 +const GPIO_FUNC118_IN_INV_SEL_S = 6 +const GPIO_FUNC118_IN_SEL = 0x0000003F +const GPIO_FUNC118_IN_SEL_V = 0x3F +const GPIO_FUNC118_IN_SEL_S = 0 +const GPIO_SIG119_IN_SEL_V = 0x1 +const GPIO_SIG119_IN_SEL_S = 7 +const GPIO_FUNC119_IN_INV_SEL_V = 0x1 +const GPIO_FUNC119_IN_INV_SEL_S = 6 +const GPIO_FUNC119_IN_SEL = 0x0000003F +const GPIO_FUNC119_IN_SEL_V = 0x3F +const GPIO_FUNC119_IN_SEL_S = 0 +const GPIO_SIG120_IN_SEL_V = 0x1 +const GPIO_SIG120_IN_SEL_S = 7 +const GPIO_FUNC120_IN_INV_SEL_V = 0x1 +const GPIO_FUNC120_IN_INV_SEL_S = 6 +const GPIO_FUNC120_IN_SEL = 0x0000003F +const GPIO_FUNC120_IN_SEL_V = 0x3F +const GPIO_FUNC120_IN_SEL_S = 0 +const GPIO_SIG121_IN_SEL_V = 0x1 +const GPIO_SIG121_IN_SEL_S = 7 +const GPIO_FUNC121_IN_INV_SEL_V = 0x1 +const GPIO_FUNC121_IN_INV_SEL_S = 6 +const GPIO_FUNC121_IN_SEL = 0x0000003F +const GPIO_FUNC121_IN_SEL_V = 0x3F +const GPIO_FUNC121_IN_SEL_S = 0 +const GPIO_SIG122_IN_SEL_V = 0x1 +const GPIO_SIG122_IN_SEL_S = 7 +const GPIO_FUNC122_IN_INV_SEL_V = 0x1 +const GPIO_FUNC122_IN_INV_SEL_S = 6 +const GPIO_FUNC122_IN_SEL = 0x0000003F +const GPIO_FUNC122_IN_SEL_V = 0x3F +const GPIO_FUNC122_IN_SEL_S = 0 +const GPIO_SIG123_IN_SEL_V = 0x1 +const GPIO_SIG123_IN_SEL_S = 7 +const GPIO_FUNC123_IN_INV_SEL_V = 0x1 +const GPIO_FUNC123_IN_INV_SEL_S = 6 +const GPIO_FUNC123_IN_SEL = 0x0000003F +const GPIO_FUNC123_IN_SEL_V = 0x3F +const GPIO_FUNC123_IN_SEL_S = 0 +const GPIO_SIG124_IN_SEL_V = 0x1 +const GPIO_SIG124_IN_SEL_S = 7 +const GPIO_FUNC124_IN_INV_SEL_V = 0x1 +const GPIO_FUNC124_IN_INV_SEL_S = 6 +const GPIO_FUNC124_IN_SEL = 0x0000003F +const GPIO_FUNC124_IN_SEL_V = 0x3F +const GPIO_FUNC124_IN_SEL_S = 0 +const GPIO_SIG125_IN_SEL_V = 0x1 +const GPIO_SIG125_IN_SEL_S = 7 +const GPIO_FUNC125_IN_INV_SEL_V = 0x1 +const GPIO_FUNC125_IN_INV_SEL_S = 6 +const GPIO_FUNC125_IN_SEL = 0x0000003F +const GPIO_FUNC125_IN_SEL_V = 0x3F +const GPIO_FUNC125_IN_SEL_S = 0 +const GPIO_SIG126_IN_SEL_V = 0x1 +const GPIO_SIG126_IN_SEL_S = 7 +const GPIO_FUNC126_IN_INV_SEL_V = 0x1 +const GPIO_FUNC126_IN_INV_SEL_S = 6 +const GPIO_FUNC126_IN_SEL = 0x0000003F +const GPIO_FUNC126_IN_SEL_V = 0x3F +const GPIO_FUNC126_IN_SEL_S = 0 +const GPIO_SIG127_IN_SEL_V = 0x1 +const GPIO_SIG127_IN_SEL_S = 7 +const GPIO_FUNC127_IN_INV_SEL_V = 0x1 +const GPIO_FUNC127_IN_INV_SEL_S = 6 +const GPIO_FUNC127_IN_SEL = 0x0000003F +const GPIO_FUNC127_IN_SEL_V = 0x3F +const GPIO_FUNC127_IN_SEL_S = 0 +const GPIO_SIG128_IN_SEL_V = 0x1 +const GPIO_SIG128_IN_SEL_S = 7 +const GPIO_FUNC128_IN_INV_SEL_V = 0x1 +const GPIO_FUNC128_IN_INV_SEL_S = 6 +const GPIO_FUNC128_IN_SEL = 0x0000003F +const GPIO_FUNC128_IN_SEL_V = 0x3F +const GPIO_FUNC128_IN_SEL_S = 0 +const GPIO_SIG129_IN_SEL_V = 0x1 +const GPIO_SIG129_IN_SEL_S = 7 +const GPIO_FUNC129_IN_INV_SEL_V = 0x1 +const GPIO_FUNC129_IN_INV_SEL_S = 6 +const GPIO_FUNC129_IN_SEL = 0x0000003F +const GPIO_FUNC129_IN_SEL_V = 0x3F +const GPIO_FUNC129_IN_SEL_S = 0 +const GPIO_SIG130_IN_SEL_V = 0x1 +const GPIO_SIG130_IN_SEL_S = 7 +const GPIO_FUNC130_IN_INV_SEL_V = 0x1 +const GPIO_FUNC130_IN_INV_SEL_S = 6 +const GPIO_FUNC130_IN_SEL = 0x0000003F +const GPIO_FUNC130_IN_SEL_V = 0x3F +const GPIO_FUNC130_IN_SEL_S = 0 +const GPIO_SIG131_IN_SEL_V = 0x1 +const GPIO_SIG131_IN_SEL_S = 7 +const GPIO_FUNC131_IN_INV_SEL_V = 0x1 +const GPIO_FUNC131_IN_INV_SEL_S = 6 +const GPIO_FUNC131_IN_SEL = 0x0000003F +const GPIO_FUNC131_IN_SEL_V = 0x3F +const GPIO_FUNC131_IN_SEL_S = 0 +const GPIO_SIG132_IN_SEL_V = 0x1 +const GPIO_SIG132_IN_SEL_S = 7 +const GPIO_FUNC132_IN_INV_SEL_V = 0x1 +const GPIO_FUNC132_IN_INV_SEL_S = 6 +const GPIO_FUNC132_IN_SEL = 0x0000003F +const GPIO_FUNC132_IN_SEL_V = 0x3F +const GPIO_FUNC132_IN_SEL_S = 0 +const GPIO_SIG133_IN_SEL_V = 0x1 +const GPIO_SIG133_IN_SEL_S = 7 +const GPIO_FUNC133_IN_INV_SEL_V = 0x1 +const GPIO_FUNC133_IN_INV_SEL_S = 6 +const GPIO_FUNC133_IN_SEL = 0x0000003F +const GPIO_FUNC133_IN_SEL_V = 0x3F +const GPIO_FUNC133_IN_SEL_S = 0 +const GPIO_SIG134_IN_SEL_V = 0x1 +const GPIO_SIG134_IN_SEL_S = 7 +const GPIO_FUNC134_IN_INV_SEL_V = 0x1 +const GPIO_FUNC134_IN_INV_SEL_S = 6 +const GPIO_FUNC134_IN_SEL = 0x0000003F +const GPIO_FUNC134_IN_SEL_V = 0x3F +const GPIO_FUNC134_IN_SEL_S = 0 +const GPIO_SIG135_IN_SEL_V = 0x1 +const GPIO_SIG135_IN_SEL_S = 7 +const GPIO_FUNC135_IN_INV_SEL_V = 0x1 +const GPIO_FUNC135_IN_INV_SEL_S = 6 +const GPIO_FUNC135_IN_SEL = 0x0000003F +const GPIO_FUNC135_IN_SEL_V = 0x3F +const GPIO_FUNC135_IN_SEL_S = 0 +const GPIO_SIG136_IN_SEL_V = 0x1 +const GPIO_SIG136_IN_SEL_S = 7 +const GPIO_FUNC136_IN_INV_SEL_V = 0x1 +const GPIO_FUNC136_IN_INV_SEL_S = 6 +const GPIO_FUNC136_IN_SEL = 0x0000003F +const GPIO_FUNC136_IN_SEL_V = 0x3F +const GPIO_FUNC136_IN_SEL_S = 0 +const GPIO_SIG137_IN_SEL_V = 0x1 +const GPIO_SIG137_IN_SEL_S = 7 +const GPIO_FUNC137_IN_INV_SEL_V = 0x1 +const GPIO_FUNC137_IN_INV_SEL_S = 6 +const GPIO_FUNC137_IN_SEL = 0x0000003F +const GPIO_FUNC137_IN_SEL_V = 0x3F +const GPIO_FUNC137_IN_SEL_S = 0 +const GPIO_SIG138_IN_SEL_V = 0x1 +const GPIO_SIG138_IN_SEL_S = 7 +const GPIO_FUNC138_IN_INV_SEL_V = 0x1 +const GPIO_FUNC138_IN_INV_SEL_S = 6 +const GPIO_FUNC138_IN_SEL = 0x0000003F +const GPIO_FUNC138_IN_SEL_V = 0x3F +const GPIO_FUNC138_IN_SEL_S = 0 +const GPIO_SIG139_IN_SEL_V = 0x1 +const GPIO_SIG139_IN_SEL_S = 7 +const GPIO_FUNC139_IN_INV_SEL_V = 0x1 +const GPIO_FUNC139_IN_INV_SEL_S = 6 +const GPIO_FUNC139_IN_SEL = 0x0000003F +const GPIO_FUNC139_IN_SEL_V = 0x3F +const GPIO_FUNC139_IN_SEL_S = 0 +const GPIO_SIG140_IN_SEL_V = 0x1 +const GPIO_SIG140_IN_SEL_S = 7 +const GPIO_FUNC140_IN_INV_SEL_V = 0x1 +const GPIO_FUNC140_IN_INV_SEL_S = 6 +const GPIO_FUNC140_IN_SEL = 0x0000003F +const GPIO_FUNC140_IN_SEL_V = 0x3F +const GPIO_FUNC140_IN_SEL_S = 0 +const GPIO_SIG141_IN_SEL_V = 0x1 +const GPIO_SIG141_IN_SEL_S = 7 +const GPIO_FUNC141_IN_INV_SEL_V = 0x1 +const GPIO_FUNC141_IN_INV_SEL_S = 6 +const GPIO_FUNC141_IN_SEL = 0x0000003F +const GPIO_FUNC141_IN_SEL_V = 0x3F +const GPIO_FUNC141_IN_SEL_S = 0 +const GPIO_SIG142_IN_SEL_V = 0x1 +const GPIO_SIG142_IN_SEL_S = 7 +const GPIO_FUNC142_IN_INV_SEL_V = 0x1 +const GPIO_FUNC142_IN_INV_SEL_S = 6 +const GPIO_FUNC142_IN_SEL = 0x0000003F +const GPIO_FUNC142_IN_SEL_V = 0x3F +const GPIO_FUNC142_IN_SEL_S = 0 +const GPIO_SIG143_IN_SEL_V = 0x1 +const GPIO_SIG143_IN_SEL_S = 7 +const GPIO_FUNC143_IN_INV_SEL_V = 0x1 +const GPIO_FUNC143_IN_INV_SEL_S = 6 +const GPIO_FUNC143_IN_SEL = 0x0000003F +const GPIO_FUNC143_IN_SEL_V = 0x3F +const GPIO_FUNC143_IN_SEL_S = 0 +const GPIO_SIG144_IN_SEL_V = 0x1 +const GPIO_SIG144_IN_SEL_S = 7 +const GPIO_FUNC144_IN_INV_SEL_V = 0x1 +const GPIO_FUNC144_IN_INV_SEL_S = 6 +const GPIO_FUNC144_IN_SEL = 0x0000003F +const GPIO_FUNC144_IN_SEL_V = 0x3F +const GPIO_FUNC144_IN_SEL_S = 0 +const GPIO_SIG145_IN_SEL_V = 0x1 +const GPIO_SIG145_IN_SEL_S = 7 +const GPIO_FUNC145_IN_INV_SEL_V = 0x1 +const GPIO_FUNC145_IN_INV_SEL_S = 6 +const GPIO_FUNC145_IN_SEL = 0x0000003F +const GPIO_FUNC145_IN_SEL_V = 0x3F +const GPIO_FUNC145_IN_SEL_S = 0 +const GPIO_SIG146_IN_SEL_V = 0x1 +const GPIO_SIG146_IN_SEL_S = 7 +const GPIO_FUNC146_IN_INV_SEL_V = 0x1 +const GPIO_FUNC146_IN_INV_SEL_S = 6 +const GPIO_FUNC146_IN_SEL = 0x0000003F +const GPIO_FUNC146_IN_SEL_V = 0x3F +const GPIO_FUNC146_IN_SEL_S = 0 +const GPIO_SIG147_IN_SEL_V = 0x1 +const GPIO_SIG147_IN_SEL_S = 7 +const GPIO_FUNC147_IN_INV_SEL_V = 0x1 +const GPIO_FUNC147_IN_INV_SEL_S = 6 +const GPIO_FUNC147_IN_SEL = 0x0000003F +const GPIO_FUNC147_IN_SEL_V = 0x3F +const GPIO_FUNC147_IN_SEL_S = 0 +const GPIO_SIG148_IN_SEL_V = 0x1 +const GPIO_SIG148_IN_SEL_S = 7 +const GPIO_FUNC148_IN_INV_SEL_V = 0x1 +const GPIO_FUNC148_IN_INV_SEL_S = 6 +const GPIO_FUNC148_IN_SEL = 0x0000003F +const GPIO_FUNC148_IN_SEL_V = 0x3F +const GPIO_FUNC148_IN_SEL_S = 0 +const GPIO_SIG149_IN_SEL_V = 0x1 +const GPIO_SIG149_IN_SEL_S = 7 +const GPIO_FUNC149_IN_INV_SEL_V = 0x1 +const GPIO_FUNC149_IN_INV_SEL_S = 6 +const GPIO_FUNC149_IN_SEL = 0x0000003F +const GPIO_FUNC149_IN_SEL_V = 0x3F +const GPIO_FUNC149_IN_SEL_S = 0 +const GPIO_SIG150_IN_SEL_V = 0x1 +const GPIO_SIG150_IN_SEL_S = 7 +const GPIO_FUNC150_IN_INV_SEL_V = 0x1 +const GPIO_FUNC150_IN_INV_SEL_S = 6 +const GPIO_FUNC150_IN_SEL = 0x0000003F +const GPIO_FUNC150_IN_SEL_V = 0x3F +const GPIO_FUNC150_IN_SEL_S = 0 +const GPIO_SIG151_IN_SEL_V = 0x1 +const GPIO_SIG151_IN_SEL_S = 7 +const GPIO_FUNC151_IN_INV_SEL_V = 0x1 +const GPIO_FUNC151_IN_INV_SEL_S = 6 +const GPIO_FUNC151_IN_SEL = 0x0000003F +const GPIO_FUNC151_IN_SEL_V = 0x3F +const GPIO_FUNC151_IN_SEL_S = 0 +const GPIO_SIG152_IN_SEL_V = 0x1 +const GPIO_SIG152_IN_SEL_S = 7 +const GPIO_FUNC152_IN_INV_SEL_V = 0x1 +const GPIO_FUNC152_IN_INV_SEL_S = 6 +const GPIO_FUNC152_IN_SEL = 0x0000003F +const GPIO_FUNC152_IN_SEL_V = 0x3F +const GPIO_FUNC152_IN_SEL_S = 0 +const GPIO_SIG153_IN_SEL_V = 0x1 +const GPIO_SIG153_IN_SEL_S = 7 +const GPIO_FUNC153_IN_INV_SEL_V = 0x1 +const GPIO_FUNC153_IN_INV_SEL_S = 6 +const GPIO_FUNC153_IN_SEL = 0x0000003F +const GPIO_FUNC153_IN_SEL_V = 0x3F +const GPIO_FUNC153_IN_SEL_S = 0 +const GPIO_SIG154_IN_SEL_V = 0x1 +const GPIO_SIG154_IN_SEL_S = 7 +const GPIO_FUNC154_IN_INV_SEL_V = 0x1 +const GPIO_FUNC154_IN_INV_SEL_S = 6 +const GPIO_FUNC154_IN_SEL = 0x0000003F +const GPIO_FUNC154_IN_SEL_V = 0x3F +const GPIO_FUNC154_IN_SEL_S = 0 +const GPIO_SIG155_IN_SEL_V = 0x1 +const GPIO_SIG155_IN_SEL_S = 7 +const GPIO_FUNC155_IN_INV_SEL_V = 0x1 +const GPIO_FUNC155_IN_INV_SEL_S = 6 +const GPIO_FUNC155_IN_SEL = 0x0000003F +const GPIO_FUNC155_IN_SEL_V = 0x3F +const GPIO_FUNC155_IN_SEL_S = 0 +const GPIO_SIG156_IN_SEL_V = 0x1 +const GPIO_SIG156_IN_SEL_S = 7 +const GPIO_FUNC156_IN_INV_SEL_V = 0x1 +const GPIO_FUNC156_IN_INV_SEL_S = 6 +const GPIO_FUNC156_IN_SEL = 0x0000003F +const GPIO_FUNC156_IN_SEL_V = 0x3F +const GPIO_FUNC156_IN_SEL_S = 0 +const GPIO_SIG157_IN_SEL_V = 0x1 +const GPIO_SIG157_IN_SEL_S = 7 +const GPIO_FUNC157_IN_INV_SEL_V = 0x1 +const GPIO_FUNC157_IN_INV_SEL_S = 6 +const GPIO_FUNC157_IN_SEL = 0x0000003F +const GPIO_FUNC157_IN_SEL_V = 0x3F +const GPIO_FUNC157_IN_SEL_S = 0 +const GPIO_SIG158_IN_SEL_V = 0x1 +const GPIO_SIG158_IN_SEL_S = 7 +const GPIO_FUNC158_IN_INV_SEL_V = 0x1 +const GPIO_FUNC158_IN_INV_SEL_S = 6 +const GPIO_FUNC158_IN_SEL = 0x0000003F +const GPIO_FUNC158_IN_SEL_V = 0x3F +const GPIO_FUNC158_IN_SEL_S = 0 +const GPIO_SIG159_IN_SEL_V = 0x1 +const GPIO_SIG159_IN_SEL_S = 7 +const GPIO_FUNC159_IN_INV_SEL_V = 0x1 +const GPIO_FUNC159_IN_INV_SEL_S = 6 +const GPIO_FUNC159_IN_SEL = 0x0000003F +const GPIO_FUNC159_IN_SEL_V = 0x3F +const GPIO_FUNC159_IN_SEL_S = 0 +const GPIO_SIG160_IN_SEL_V = 0x1 +const GPIO_SIG160_IN_SEL_S = 7 +const GPIO_FUNC160_IN_INV_SEL_V = 0x1 +const GPIO_FUNC160_IN_INV_SEL_S = 6 +const GPIO_FUNC160_IN_SEL = 0x0000003F +const GPIO_FUNC160_IN_SEL_V = 0x3F +const GPIO_FUNC160_IN_SEL_S = 0 +const GPIO_SIG161_IN_SEL_V = 0x1 +const GPIO_SIG161_IN_SEL_S = 7 +const GPIO_FUNC161_IN_INV_SEL_V = 0x1 +const GPIO_FUNC161_IN_INV_SEL_S = 6 +const GPIO_FUNC161_IN_SEL = 0x0000003F +const GPIO_FUNC161_IN_SEL_V = 0x3F +const GPIO_FUNC161_IN_SEL_S = 0 +const GPIO_SIG162_IN_SEL_V = 0x1 +const GPIO_SIG162_IN_SEL_S = 7 +const GPIO_FUNC162_IN_INV_SEL_V = 0x1 +const GPIO_FUNC162_IN_INV_SEL_S = 6 +const GPIO_FUNC162_IN_SEL = 0x0000003F +const GPIO_FUNC162_IN_SEL_V = 0x3F +const GPIO_FUNC162_IN_SEL_S = 0 +const GPIO_SIG163_IN_SEL_V = 0x1 +const GPIO_SIG163_IN_SEL_S = 7 +const GPIO_FUNC163_IN_INV_SEL_V = 0x1 +const GPIO_FUNC163_IN_INV_SEL_S = 6 +const GPIO_FUNC163_IN_SEL = 0x0000003F +const GPIO_FUNC163_IN_SEL_V = 0x3F +const GPIO_FUNC163_IN_SEL_S = 0 +const GPIO_SIG164_IN_SEL_V = 0x1 +const GPIO_SIG164_IN_SEL_S = 7 +const GPIO_FUNC164_IN_INV_SEL_V = 0x1 +const GPIO_FUNC164_IN_INV_SEL_S = 6 +const GPIO_FUNC164_IN_SEL = 0x0000003F +const GPIO_FUNC164_IN_SEL_V = 0x3F +const GPIO_FUNC164_IN_SEL_S = 0 +const GPIO_SIG165_IN_SEL_V = 0x1 +const GPIO_SIG165_IN_SEL_S = 7 +const GPIO_FUNC165_IN_INV_SEL_V = 0x1 +const GPIO_FUNC165_IN_INV_SEL_S = 6 +const GPIO_FUNC165_IN_SEL = 0x0000003F +const GPIO_FUNC165_IN_SEL_V = 0x3F +const GPIO_FUNC165_IN_SEL_S = 0 +const GPIO_SIG166_IN_SEL_V = 0x1 +const GPIO_SIG166_IN_SEL_S = 7 +const GPIO_FUNC166_IN_INV_SEL_V = 0x1 +const GPIO_FUNC166_IN_INV_SEL_S = 6 +const GPIO_FUNC166_IN_SEL = 0x0000003F +const GPIO_FUNC166_IN_SEL_V = 0x3F +const GPIO_FUNC166_IN_SEL_S = 0 +const GPIO_SIG167_IN_SEL_V = 0x1 +const GPIO_SIG167_IN_SEL_S = 7 +const GPIO_FUNC167_IN_INV_SEL_V = 0x1 +const GPIO_FUNC167_IN_INV_SEL_S = 6 +const GPIO_FUNC167_IN_SEL = 0x0000003F +const GPIO_FUNC167_IN_SEL_V = 0x3F +const GPIO_FUNC167_IN_SEL_S = 0 +const GPIO_SIG168_IN_SEL_V = 0x1 +const GPIO_SIG168_IN_SEL_S = 7 +const GPIO_FUNC168_IN_INV_SEL_V = 0x1 +const GPIO_FUNC168_IN_INV_SEL_S = 6 +const GPIO_FUNC168_IN_SEL = 0x0000003F +const GPIO_FUNC168_IN_SEL_V = 0x3F +const GPIO_FUNC168_IN_SEL_S = 0 +const GPIO_SIG169_IN_SEL_V = 0x1 +const GPIO_SIG169_IN_SEL_S = 7 +const GPIO_FUNC169_IN_INV_SEL_V = 0x1 +const GPIO_FUNC169_IN_INV_SEL_S = 6 +const GPIO_FUNC169_IN_SEL = 0x0000003F +const GPIO_FUNC169_IN_SEL_V = 0x3F +const GPIO_FUNC169_IN_SEL_S = 0 +const GPIO_SIG170_IN_SEL_V = 0x1 +const GPIO_SIG170_IN_SEL_S = 7 +const GPIO_FUNC170_IN_INV_SEL_V = 0x1 +const GPIO_FUNC170_IN_INV_SEL_S = 6 +const GPIO_FUNC170_IN_SEL = 0x0000003F +const GPIO_FUNC170_IN_SEL_V = 0x3F +const GPIO_FUNC170_IN_SEL_S = 0 +const GPIO_SIG171_IN_SEL_V = 0x1 +const GPIO_SIG171_IN_SEL_S = 7 +const GPIO_FUNC171_IN_INV_SEL_V = 0x1 +const GPIO_FUNC171_IN_INV_SEL_S = 6 +const GPIO_FUNC171_IN_SEL = 0x0000003F +const GPIO_FUNC171_IN_SEL_V = 0x3F +const GPIO_FUNC171_IN_SEL_S = 0 +const GPIO_SIG172_IN_SEL_V = 0x1 +const GPIO_SIG172_IN_SEL_S = 7 +const GPIO_FUNC172_IN_INV_SEL_V = 0x1 +const GPIO_FUNC172_IN_INV_SEL_S = 6 +const GPIO_FUNC172_IN_SEL = 0x0000003F +const GPIO_FUNC172_IN_SEL_V = 0x3F +const GPIO_FUNC172_IN_SEL_S = 0 +const GPIO_SIG173_IN_SEL_V = 0x1 +const GPIO_SIG173_IN_SEL_S = 7 +const GPIO_FUNC173_IN_INV_SEL_V = 0x1 +const GPIO_FUNC173_IN_INV_SEL_S = 6 +const GPIO_FUNC173_IN_SEL = 0x0000003F +const GPIO_FUNC173_IN_SEL_V = 0x3F +const GPIO_FUNC173_IN_SEL_S = 0 +const GPIO_SIG174_IN_SEL_V = 0x1 +const GPIO_SIG174_IN_SEL_S = 7 +const GPIO_FUNC174_IN_INV_SEL_V = 0x1 +const GPIO_FUNC174_IN_INV_SEL_S = 6 +const GPIO_FUNC174_IN_SEL = 0x0000003F +const GPIO_FUNC174_IN_SEL_V = 0x3F +const GPIO_FUNC174_IN_SEL_S = 0 +const GPIO_SIG175_IN_SEL_V = 0x1 +const GPIO_SIG175_IN_SEL_S = 7 +const GPIO_FUNC175_IN_INV_SEL_V = 0x1 +const GPIO_FUNC175_IN_INV_SEL_S = 6 +const GPIO_FUNC175_IN_SEL = 0x0000003F +const GPIO_FUNC175_IN_SEL_V = 0x3F +const GPIO_FUNC175_IN_SEL_S = 0 +const GPIO_SIG176_IN_SEL_V = 0x1 +const GPIO_SIG176_IN_SEL_S = 7 +const GPIO_FUNC176_IN_INV_SEL_V = 0x1 +const GPIO_FUNC176_IN_INV_SEL_S = 6 +const GPIO_FUNC176_IN_SEL = 0x0000003F +const GPIO_FUNC176_IN_SEL_V = 0x3F +const GPIO_FUNC176_IN_SEL_S = 0 +const GPIO_SIG177_IN_SEL_V = 0x1 +const GPIO_SIG177_IN_SEL_S = 7 +const GPIO_FUNC177_IN_INV_SEL_V = 0x1 +const GPIO_FUNC177_IN_INV_SEL_S = 6 +const GPIO_FUNC177_IN_SEL = 0x0000003F +const GPIO_FUNC177_IN_SEL_V = 0x3F +const GPIO_FUNC177_IN_SEL_S = 0 +const GPIO_SIG178_IN_SEL_V = 0x1 +const GPIO_SIG178_IN_SEL_S = 7 +const GPIO_FUNC178_IN_INV_SEL_V = 0x1 +const GPIO_FUNC178_IN_INV_SEL_S = 6 +const GPIO_FUNC178_IN_SEL = 0x0000003F +const GPIO_FUNC178_IN_SEL_V = 0x3F +const GPIO_FUNC178_IN_SEL_S = 0 +const GPIO_SIG179_IN_SEL_V = 0x1 +const GPIO_SIG179_IN_SEL_S = 7 +const GPIO_FUNC179_IN_INV_SEL_V = 0x1 +const GPIO_FUNC179_IN_INV_SEL_S = 6 +const GPIO_FUNC179_IN_SEL = 0x0000003F +const GPIO_FUNC179_IN_SEL_V = 0x3F +const GPIO_FUNC179_IN_SEL_S = 0 +const GPIO_SIG180_IN_SEL_V = 0x1 +const GPIO_SIG180_IN_SEL_S = 7 +const GPIO_FUNC180_IN_INV_SEL_V = 0x1 +const GPIO_FUNC180_IN_INV_SEL_S = 6 +const GPIO_FUNC180_IN_SEL = 0x0000003F +const GPIO_FUNC180_IN_SEL_V = 0x3F +const GPIO_FUNC180_IN_SEL_S = 0 +const GPIO_SIG181_IN_SEL_V = 0x1 +const GPIO_SIG181_IN_SEL_S = 7 +const GPIO_FUNC181_IN_INV_SEL_V = 0x1 +const GPIO_FUNC181_IN_INV_SEL_S = 6 +const GPIO_FUNC181_IN_SEL = 0x0000003F +const GPIO_FUNC181_IN_SEL_V = 0x3F +const GPIO_FUNC181_IN_SEL_S = 0 +const GPIO_SIG182_IN_SEL_V = 0x1 +const GPIO_SIG182_IN_SEL_S = 7 +const GPIO_FUNC182_IN_INV_SEL_V = 0x1 +const GPIO_FUNC182_IN_INV_SEL_S = 6 +const GPIO_FUNC182_IN_SEL = 0x0000003F +const GPIO_FUNC182_IN_SEL_V = 0x3F +const GPIO_FUNC182_IN_SEL_S = 0 +const GPIO_SIG183_IN_SEL_V = 0x1 +const GPIO_SIG183_IN_SEL_S = 7 +const GPIO_FUNC183_IN_INV_SEL_V = 0x1 +const GPIO_FUNC183_IN_INV_SEL_S = 6 +const GPIO_FUNC183_IN_SEL = 0x0000003F +const GPIO_FUNC183_IN_SEL_V = 0x3F +const GPIO_FUNC183_IN_SEL_S = 0 +const GPIO_SIG184_IN_SEL_V = 0x1 +const GPIO_SIG184_IN_SEL_S = 7 +const GPIO_FUNC184_IN_INV_SEL_V = 0x1 +const GPIO_FUNC184_IN_INV_SEL_S = 6 +const GPIO_FUNC184_IN_SEL = 0x0000003F +const GPIO_FUNC184_IN_SEL_V = 0x3F +const GPIO_FUNC184_IN_SEL_S = 0 +const GPIO_SIG185_IN_SEL_V = 0x1 +const GPIO_SIG185_IN_SEL_S = 7 +const GPIO_FUNC185_IN_INV_SEL_V = 0x1 +const GPIO_FUNC185_IN_INV_SEL_S = 6 +const GPIO_FUNC185_IN_SEL = 0x0000003F +const GPIO_FUNC185_IN_SEL_V = 0x3F +const GPIO_FUNC185_IN_SEL_S = 0 +const GPIO_SIG186_IN_SEL_V = 0x1 +const GPIO_SIG186_IN_SEL_S = 7 +const GPIO_FUNC186_IN_INV_SEL_V = 0x1 +const GPIO_FUNC186_IN_INV_SEL_S = 6 +const GPIO_FUNC186_IN_SEL = 0x0000003F +const GPIO_FUNC186_IN_SEL_V = 0x3F +const GPIO_FUNC186_IN_SEL_S = 0 +const GPIO_SIG187_IN_SEL_V = 0x1 +const GPIO_SIG187_IN_SEL_S = 7 +const GPIO_FUNC187_IN_INV_SEL_V = 0x1 +const GPIO_FUNC187_IN_INV_SEL_S = 6 +const GPIO_FUNC187_IN_SEL = 0x0000003F +const GPIO_FUNC187_IN_SEL_V = 0x3F +const GPIO_FUNC187_IN_SEL_S = 0 +const GPIO_SIG188_IN_SEL_V = 0x1 +const GPIO_SIG188_IN_SEL_S = 7 +const GPIO_FUNC188_IN_INV_SEL_V = 0x1 +const GPIO_FUNC188_IN_INV_SEL_S = 6 +const GPIO_FUNC188_IN_SEL = 0x0000003F +const GPIO_FUNC188_IN_SEL_V = 0x3F +const GPIO_FUNC188_IN_SEL_S = 0 +const GPIO_SIG189_IN_SEL_V = 0x1 +const GPIO_SIG189_IN_SEL_S = 7 +const GPIO_FUNC189_IN_INV_SEL_V = 0x1 +const GPIO_FUNC189_IN_INV_SEL_S = 6 +const GPIO_FUNC189_IN_SEL = 0x0000003F +const GPIO_FUNC189_IN_SEL_V = 0x3F +const GPIO_FUNC189_IN_SEL_S = 0 +const GPIO_SIG190_IN_SEL_V = 0x1 +const GPIO_SIG190_IN_SEL_S = 7 +const GPIO_FUNC190_IN_INV_SEL_V = 0x1 +const GPIO_FUNC190_IN_INV_SEL_S = 6 +const GPIO_FUNC190_IN_SEL = 0x0000003F +const GPIO_FUNC190_IN_SEL_V = 0x3F +const GPIO_FUNC190_IN_SEL_S = 0 +const GPIO_SIG191_IN_SEL_V = 0x1 +const GPIO_SIG191_IN_SEL_S = 7 +const GPIO_FUNC191_IN_INV_SEL_V = 0x1 +const GPIO_FUNC191_IN_INV_SEL_S = 6 +const GPIO_FUNC191_IN_SEL = 0x0000003F +const GPIO_FUNC191_IN_SEL_V = 0x3F +const GPIO_FUNC191_IN_SEL_S = 0 +const GPIO_SIG192_IN_SEL_V = 0x1 +const GPIO_SIG192_IN_SEL_S = 7 +const GPIO_FUNC192_IN_INV_SEL_V = 0x1 +const GPIO_FUNC192_IN_INV_SEL_S = 6 +const GPIO_FUNC192_IN_SEL = 0x0000003F +const GPIO_FUNC192_IN_SEL_V = 0x3F +const GPIO_FUNC192_IN_SEL_S = 0 +const GPIO_SIG193_IN_SEL_V = 0x1 +const GPIO_SIG193_IN_SEL_S = 7 +const GPIO_FUNC193_IN_INV_SEL_V = 0x1 +const GPIO_FUNC193_IN_INV_SEL_S = 6 +const GPIO_FUNC193_IN_SEL = 0x0000003F +const GPIO_FUNC193_IN_SEL_V = 0x3F +const GPIO_FUNC193_IN_SEL_S = 0 +const GPIO_SIG194_IN_SEL_V = 0x1 +const GPIO_SIG194_IN_SEL_S = 7 +const GPIO_FUNC194_IN_INV_SEL_V = 0x1 +const GPIO_FUNC194_IN_INV_SEL_S = 6 +const GPIO_FUNC194_IN_SEL = 0x0000003F +const GPIO_FUNC194_IN_SEL_V = 0x3F +const GPIO_FUNC194_IN_SEL_S = 0 +const GPIO_SIG195_IN_SEL_V = 0x1 +const GPIO_SIG195_IN_SEL_S = 7 +const GPIO_FUNC195_IN_INV_SEL_V = 0x1 +const GPIO_FUNC195_IN_INV_SEL_S = 6 +const GPIO_FUNC195_IN_SEL = 0x0000003F +const GPIO_FUNC195_IN_SEL_V = 0x3F +const GPIO_FUNC195_IN_SEL_S = 0 +const GPIO_SIG196_IN_SEL_V = 0x1 +const GPIO_SIG196_IN_SEL_S = 7 +const GPIO_FUNC196_IN_INV_SEL_V = 0x1 +const GPIO_FUNC196_IN_INV_SEL_S = 6 +const GPIO_FUNC196_IN_SEL = 0x0000003F +const GPIO_FUNC196_IN_SEL_V = 0x3F +const GPIO_FUNC196_IN_SEL_S = 0 +const GPIO_SIG197_IN_SEL_V = 0x1 +const GPIO_SIG197_IN_SEL_S = 7 +const GPIO_FUNC197_IN_INV_SEL_V = 0x1 +const GPIO_FUNC197_IN_INV_SEL_S = 6 +const GPIO_FUNC197_IN_SEL = 0x0000003F +const GPIO_FUNC197_IN_SEL_V = 0x3F +const GPIO_FUNC197_IN_SEL_S = 0 +const GPIO_SIG198_IN_SEL_V = 0x1 +const GPIO_SIG198_IN_SEL_S = 7 +const GPIO_FUNC198_IN_INV_SEL_V = 0x1 +const GPIO_FUNC198_IN_INV_SEL_S = 6 +const GPIO_FUNC198_IN_SEL = 0x0000003F +const GPIO_FUNC198_IN_SEL_V = 0x3F +const GPIO_FUNC198_IN_SEL_S = 0 +const GPIO_SIG199_IN_SEL_V = 0x1 +const GPIO_SIG199_IN_SEL_S = 7 +const GPIO_FUNC199_IN_INV_SEL_V = 0x1 +const GPIO_FUNC199_IN_INV_SEL_S = 6 +const GPIO_FUNC199_IN_SEL = 0x0000003F +const GPIO_FUNC199_IN_SEL_V = 0x3F +const GPIO_FUNC199_IN_SEL_S = 0 +const GPIO_SIG200_IN_SEL_V = 0x1 +const GPIO_SIG200_IN_SEL_S = 7 +const GPIO_FUNC200_IN_INV_SEL_V = 0x1 +const GPIO_FUNC200_IN_INV_SEL_S = 6 +const GPIO_FUNC200_IN_SEL = 0x0000003F +const GPIO_FUNC200_IN_SEL_V = 0x3F +const GPIO_FUNC200_IN_SEL_S = 0 +const GPIO_SIG201_IN_SEL_V = 0x1 +const GPIO_SIG201_IN_SEL_S = 7 +const GPIO_FUNC201_IN_INV_SEL_V = 0x1 +const GPIO_FUNC201_IN_INV_SEL_S = 6 +const GPIO_FUNC201_IN_SEL = 0x0000003F +const GPIO_FUNC201_IN_SEL_V = 0x3F +const GPIO_FUNC201_IN_SEL_S = 0 +const GPIO_SIG202_IN_SEL_V = 0x1 +const GPIO_SIG202_IN_SEL_S = 7 +const GPIO_FUNC202_IN_INV_SEL_V = 0x1 +const GPIO_FUNC202_IN_INV_SEL_S = 6 +const GPIO_FUNC202_IN_SEL = 0x0000003F +const GPIO_FUNC202_IN_SEL_V = 0x3F +const GPIO_FUNC202_IN_SEL_S = 0 +const GPIO_SIG203_IN_SEL_V = 0x1 +const GPIO_SIG203_IN_SEL_S = 7 +const GPIO_FUNC203_IN_INV_SEL_V = 0x1 +const GPIO_FUNC203_IN_INV_SEL_S = 6 +const GPIO_FUNC203_IN_SEL = 0x0000003F +const GPIO_FUNC203_IN_SEL_V = 0x3F +const GPIO_FUNC203_IN_SEL_S = 0 +const GPIO_SIG204_IN_SEL_V = 0x1 +const GPIO_SIG204_IN_SEL_S = 7 +const GPIO_FUNC204_IN_INV_SEL_V = 0x1 +const GPIO_FUNC204_IN_INV_SEL_S = 6 +const GPIO_FUNC204_IN_SEL = 0x0000003F +const GPIO_FUNC204_IN_SEL_V = 0x3F +const GPIO_FUNC204_IN_SEL_S = 0 +const GPIO_SIG205_IN_SEL_V = 0x1 +const GPIO_SIG205_IN_SEL_S = 7 +const GPIO_FUNC205_IN_INV_SEL_V = 0x1 +const GPIO_FUNC205_IN_INV_SEL_S = 6 +const GPIO_FUNC205_IN_SEL = 0x0000003F +const GPIO_FUNC205_IN_SEL_V = 0x3F +const GPIO_FUNC205_IN_SEL_S = 0 +const GPIO_SIG206_IN_SEL_V = 0x1 +const GPIO_SIG206_IN_SEL_S = 7 +const GPIO_FUNC206_IN_INV_SEL_V = 0x1 +const GPIO_FUNC206_IN_INV_SEL_S = 6 +const GPIO_FUNC206_IN_SEL = 0x0000003F +const GPIO_FUNC206_IN_SEL_V = 0x3F +const GPIO_FUNC206_IN_SEL_S = 0 +const GPIO_SIG207_IN_SEL_V = 0x1 +const GPIO_SIG207_IN_SEL_S = 7 +const GPIO_FUNC207_IN_INV_SEL_V = 0x1 +const GPIO_FUNC207_IN_INV_SEL_S = 6 +const GPIO_FUNC207_IN_SEL = 0x0000003F +const GPIO_FUNC207_IN_SEL_V = 0x3F +const GPIO_FUNC207_IN_SEL_S = 0 +const GPIO_SIG208_IN_SEL_V = 0x1 +const GPIO_SIG208_IN_SEL_S = 7 +const GPIO_FUNC208_IN_INV_SEL_V = 0x1 +const GPIO_FUNC208_IN_INV_SEL_S = 6 +const GPIO_FUNC208_IN_SEL = 0x0000003F +const GPIO_FUNC208_IN_SEL_V = 0x3F +const GPIO_FUNC208_IN_SEL_S = 0 +const GPIO_SIG209_IN_SEL_V = 0x1 +const GPIO_SIG209_IN_SEL_S = 7 +const GPIO_FUNC209_IN_INV_SEL_V = 0x1 +const GPIO_FUNC209_IN_INV_SEL_S = 6 +const GPIO_FUNC209_IN_SEL = 0x0000003F +const GPIO_FUNC209_IN_SEL_V = 0x3F +const GPIO_FUNC209_IN_SEL_S = 0 +const GPIO_SIG210_IN_SEL_V = 0x1 +const GPIO_SIG210_IN_SEL_S = 7 +const GPIO_FUNC210_IN_INV_SEL_V = 0x1 +const GPIO_FUNC210_IN_INV_SEL_S = 6 +const GPIO_FUNC210_IN_SEL = 0x0000003F +const GPIO_FUNC210_IN_SEL_V = 0x3F +const GPIO_FUNC210_IN_SEL_S = 0 +const GPIO_SIG211_IN_SEL_V = 0x1 +const GPIO_SIG211_IN_SEL_S = 7 +const GPIO_FUNC211_IN_INV_SEL_V = 0x1 +const GPIO_FUNC211_IN_INV_SEL_S = 6 +const GPIO_FUNC211_IN_SEL = 0x0000003F +const GPIO_FUNC211_IN_SEL_V = 0x3F +const GPIO_FUNC211_IN_SEL_S = 0 +const GPIO_SIG212_IN_SEL_V = 0x1 +const GPIO_SIG212_IN_SEL_S = 7 +const GPIO_FUNC212_IN_INV_SEL_V = 0x1 +const GPIO_FUNC212_IN_INV_SEL_S = 6 +const GPIO_FUNC212_IN_SEL = 0x0000003F +const GPIO_FUNC212_IN_SEL_V = 0x3F +const GPIO_FUNC212_IN_SEL_S = 0 +const GPIO_SIG213_IN_SEL_V = 0x1 +const GPIO_SIG213_IN_SEL_S = 7 +const GPIO_FUNC213_IN_INV_SEL_V = 0x1 +const GPIO_FUNC213_IN_INV_SEL_S = 6 +const GPIO_FUNC213_IN_SEL = 0x0000003F +const GPIO_FUNC213_IN_SEL_V = 0x3F +const GPIO_FUNC213_IN_SEL_S = 0 +const GPIO_SIG214_IN_SEL_V = 0x1 +const GPIO_SIG214_IN_SEL_S = 7 +const GPIO_FUNC214_IN_INV_SEL_V = 0x1 +const GPIO_FUNC214_IN_INV_SEL_S = 6 +const GPIO_FUNC214_IN_SEL = 0x0000003F +const GPIO_FUNC214_IN_SEL_V = 0x3F +const GPIO_FUNC214_IN_SEL_S = 0 +const GPIO_SIG215_IN_SEL_V = 0x1 +const GPIO_SIG215_IN_SEL_S = 7 +const GPIO_FUNC215_IN_INV_SEL_V = 0x1 +const GPIO_FUNC215_IN_INV_SEL_S = 6 +const GPIO_FUNC215_IN_SEL = 0x0000003F +const GPIO_FUNC215_IN_SEL_V = 0x3F +const GPIO_FUNC215_IN_SEL_S = 0 +const GPIO_SIG216_IN_SEL_V = 0x1 +const GPIO_SIG216_IN_SEL_S = 7 +const GPIO_FUNC216_IN_INV_SEL_V = 0x1 +const GPIO_FUNC216_IN_INV_SEL_S = 6 +const GPIO_FUNC216_IN_SEL = 0x0000003F +const GPIO_FUNC216_IN_SEL_V = 0x3F +const GPIO_FUNC216_IN_SEL_S = 0 +const GPIO_SIG217_IN_SEL_V = 0x1 +const GPIO_SIG217_IN_SEL_S = 7 +const GPIO_FUNC217_IN_INV_SEL_V = 0x1 +const GPIO_FUNC217_IN_INV_SEL_S = 6 +const GPIO_FUNC217_IN_SEL = 0x0000003F +const GPIO_FUNC217_IN_SEL_V = 0x3F +const GPIO_FUNC217_IN_SEL_S = 0 +const GPIO_SIG218_IN_SEL_V = 0x1 +const GPIO_SIG218_IN_SEL_S = 7 +const GPIO_FUNC218_IN_INV_SEL_V = 0x1 +const GPIO_FUNC218_IN_INV_SEL_S = 6 +const GPIO_FUNC218_IN_SEL = 0x0000003F +const GPIO_FUNC218_IN_SEL_V = 0x3F +const GPIO_FUNC218_IN_SEL_S = 0 +const GPIO_SIG219_IN_SEL_V = 0x1 +const GPIO_SIG219_IN_SEL_S = 7 +const GPIO_FUNC219_IN_INV_SEL_V = 0x1 +const GPIO_FUNC219_IN_INV_SEL_S = 6 +const GPIO_FUNC219_IN_SEL = 0x0000003F +const GPIO_FUNC219_IN_SEL_V = 0x3F +const GPIO_FUNC219_IN_SEL_S = 0 +const GPIO_SIG220_IN_SEL_V = 0x1 +const GPIO_SIG220_IN_SEL_S = 7 +const GPIO_FUNC220_IN_INV_SEL_V = 0x1 +const GPIO_FUNC220_IN_INV_SEL_S = 6 +const GPIO_FUNC220_IN_SEL = 0x0000003F +const GPIO_FUNC220_IN_SEL_V = 0x3F +const GPIO_FUNC220_IN_SEL_S = 0 +const GPIO_SIG221_IN_SEL_V = 0x1 +const GPIO_SIG221_IN_SEL_S = 7 +const GPIO_FUNC221_IN_INV_SEL_V = 0x1 +const GPIO_FUNC221_IN_INV_SEL_S = 6 +const GPIO_FUNC221_IN_SEL = 0x0000003F +const GPIO_FUNC221_IN_SEL_V = 0x3F +const GPIO_FUNC221_IN_SEL_S = 0 +const GPIO_SIG222_IN_SEL_V = 0x1 +const GPIO_SIG222_IN_SEL_S = 7 +const GPIO_FUNC222_IN_INV_SEL_V = 0x1 +const GPIO_FUNC222_IN_INV_SEL_S = 6 +const GPIO_FUNC222_IN_SEL = 0x0000003F +const GPIO_FUNC222_IN_SEL_V = 0x3F +const GPIO_FUNC222_IN_SEL_S = 0 +const GPIO_SIG223_IN_SEL_V = 0x1 +const GPIO_SIG223_IN_SEL_S = 7 +const GPIO_FUNC223_IN_INV_SEL_V = 0x1 +const GPIO_FUNC223_IN_INV_SEL_S = 6 +const GPIO_FUNC223_IN_SEL = 0x0000003F +const GPIO_FUNC223_IN_SEL_V = 0x3F +const GPIO_FUNC223_IN_SEL_S = 0 +const GPIO_SIG224_IN_SEL_V = 0x1 +const GPIO_SIG224_IN_SEL_S = 7 +const GPIO_FUNC224_IN_INV_SEL_V = 0x1 +const GPIO_FUNC224_IN_INV_SEL_S = 6 +const GPIO_FUNC224_IN_SEL = 0x0000003F +const GPIO_FUNC224_IN_SEL_V = 0x3F +const GPIO_FUNC224_IN_SEL_S = 0 +const GPIO_SIG225_IN_SEL_V = 0x1 +const GPIO_SIG225_IN_SEL_S = 7 +const GPIO_FUNC225_IN_INV_SEL_V = 0x1 +const GPIO_FUNC225_IN_INV_SEL_S = 6 +const GPIO_FUNC225_IN_SEL = 0x0000003F +const GPIO_FUNC225_IN_SEL_V = 0x3F +const GPIO_FUNC225_IN_SEL_S = 0 +const GPIO_SIG226_IN_SEL_V = 0x1 +const GPIO_SIG226_IN_SEL_S = 7 +const GPIO_FUNC226_IN_INV_SEL_V = 0x1 +const GPIO_FUNC226_IN_INV_SEL_S = 6 +const GPIO_FUNC226_IN_SEL = 0x0000003F +const GPIO_FUNC226_IN_SEL_V = 0x3F +const GPIO_FUNC226_IN_SEL_S = 0 +const GPIO_SIG227_IN_SEL_V = 0x1 +const GPIO_SIG227_IN_SEL_S = 7 +const GPIO_FUNC227_IN_INV_SEL_V = 0x1 +const GPIO_FUNC227_IN_INV_SEL_S = 6 +const GPIO_FUNC227_IN_SEL = 0x0000003F +const GPIO_FUNC227_IN_SEL_V = 0x3F +const GPIO_FUNC227_IN_SEL_S = 0 +const GPIO_SIG228_IN_SEL_V = 0x1 +const GPIO_SIG228_IN_SEL_S = 7 +const GPIO_FUNC228_IN_INV_SEL_V = 0x1 +const GPIO_FUNC228_IN_INV_SEL_S = 6 +const GPIO_FUNC228_IN_SEL = 0x0000003F +const GPIO_FUNC228_IN_SEL_V = 0x3F +const GPIO_FUNC228_IN_SEL_S = 0 +const GPIO_SIG229_IN_SEL_V = 0x1 +const GPIO_SIG229_IN_SEL_S = 7 +const GPIO_FUNC229_IN_INV_SEL_V = 0x1 +const GPIO_FUNC229_IN_INV_SEL_S = 6 +const GPIO_FUNC229_IN_SEL = 0x0000003F +const GPIO_FUNC229_IN_SEL_V = 0x3F +const GPIO_FUNC229_IN_SEL_S = 0 +const GPIO_SIG230_IN_SEL_V = 0x1 +const GPIO_SIG230_IN_SEL_S = 7 +const GPIO_FUNC230_IN_INV_SEL_V = 0x1 +const GPIO_FUNC230_IN_INV_SEL_S = 6 +const GPIO_FUNC230_IN_SEL = 0x0000003F +const GPIO_FUNC230_IN_SEL_V = 0x3F +const GPIO_FUNC230_IN_SEL_S = 0 +const GPIO_SIG231_IN_SEL_V = 0x1 +const GPIO_SIG231_IN_SEL_S = 7 +const GPIO_FUNC231_IN_INV_SEL_V = 0x1 +const GPIO_FUNC231_IN_INV_SEL_S = 6 +const GPIO_FUNC231_IN_SEL = 0x0000003F +const GPIO_FUNC231_IN_SEL_V = 0x3F +const GPIO_FUNC231_IN_SEL_S = 0 +const GPIO_SIG232_IN_SEL_V = 0x1 +const GPIO_SIG232_IN_SEL_S = 7 +const GPIO_FUNC232_IN_INV_SEL_V = 0x1 +const GPIO_FUNC232_IN_INV_SEL_S = 6 +const GPIO_FUNC232_IN_SEL = 0x0000003F +const GPIO_FUNC232_IN_SEL_V = 0x3F +const GPIO_FUNC232_IN_SEL_S = 0 +const GPIO_SIG233_IN_SEL_V = 0x1 +const GPIO_SIG233_IN_SEL_S = 7 +const GPIO_FUNC233_IN_INV_SEL_V = 0x1 +const GPIO_FUNC233_IN_INV_SEL_S = 6 +const GPIO_FUNC233_IN_SEL = 0x0000003F +const GPIO_FUNC233_IN_SEL_V = 0x3F +const GPIO_FUNC233_IN_SEL_S = 0 +const GPIO_SIG234_IN_SEL_V = 0x1 +const GPIO_SIG234_IN_SEL_S = 7 +const GPIO_FUNC234_IN_INV_SEL_V = 0x1 +const GPIO_FUNC234_IN_INV_SEL_S = 6 +const GPIO_FUNC234_IN_SEL = 0x0000003F +const GPIO_FUNC234_IN_SEL_V = 0x3F +const GPIO_FUNC234_IN_SEL_S = 0 +const GPIO_SIG235_IN_SEL_V = 0x1 +const GPIO_SIG235_IN_SEL_S = 7 +const GPIO_FUNC235_IN_INV_SEL_V = 0x1 +const GPIO_FUNC235_IN_INV_SEL_S = 6 +const GPIO_FUNC235_IN_SEL = 0x0000003F +const GPIO_FUNC235_IN_SEL_V = 0x3F +const GPIO_FUNC235_IN_SEL_S = 0 +const GPIO_SIG236_IN_SEL_V = 0x1 +const GPIO_SIG236_IN_SEL_S = 7 +const GPIO_FUNC236_IN_INV_SEL_V = 0x1 +const GPIO_FUNC236_IN_INV_SEL_S = 6 +const GPIO_FUNC236_IN_SEL = 0x0000003F +const GPIO_FUNC236_IN_SEL_V = 0x3F +const GPIO_FUNC236_IN_SEL_S = 0 +const GPIO_SIG237_IN_SEL_V = 0x1 +const GPIO_SIG237_IN_SEL_S = 7 +const GPIO_FUNC237_IN_INV_SEL_V = 0x1 +const GPIO_FUNC237_IN_INV_SEL_S = 6 +const GPIO_FUNC237_IN_SEL = 0x0000003F +const GPIO_FUNC237_IN_SEL_V = 0x3F +const GPIO_FUNC237_IN_SEL_S = 0 +const GPIO_SIG238_IN_SEL_V = 0x1 +const GPIO_SIG238_IN_SEL_S = 7 +const GPIO_FUNC238_IN_INV_SEL_V = 0x1 +const GPIO_FUNC238_IN_INV_SEL_S = 6 +const GPIO_FUNC238_IN_SEL = 0x0000003F +const GPIO_FUNC238_IN_SEL_V = 0x3F +const GPIO_FUNC238_IN_SEL_S = 0 +const GPIO_SIG239_IN_SEL_V = 0x1 +const GPIO_SIG239_IN_SEL_S = 7 +const GPIO_FUNC239_IN_INV_SEL_V = 0x1 +const GPIO_FUNC239_IN_INV_SEL_S = 6 +const GPIO_FUNC239_IN_SEL = 0x0000003F +const GPIO_FUNC239_IN_SEL_V = 0x3F +const GPIO_FUNC239_IN_SEL_S = 0 +const GPIO_SIG240_IN_SEL_V = 0x1 +const GPIO_SIG240_IN_SEL_S = 7 +const GPIO_FUNC240_IN_INV_SEL_V = 0x1 +const GPIO_FUNC240_IN_INV_SEL_S = 6 +const GPIO_FUNC240_IN_SEL = 0x0000003F +const GPIO_FUNC240_IN_SEL_V = 0x3F +const GPIO_FUNC240_IN_SEL_S = 0 +const GPIO_SIG241_IN_SEL_V = 0x1 +const GPIO_SIG241_IN_SEL_S = 7 +const GPIO_FUNC241_IN_INV_SEL_V = 0x1 +const GPIO_FUNC241_IN_INV_SEL_S = 6 +const GPIO_FUNC241_IN_SEL = 0x0000003F +const GPIO_FUNC241_IN_SEL_V = 0x3F +const GPIO_FUNC241_IN_SEL_S = 0 +const GPIO_SIG242_IN_SEL_V = 0x1 +const GPIO_SIG242_IN_SEL_S = 7 +const GPIO_FUNC242_IN_INV_SEL_V = 0x1 +const GPIO_FUNC242_IN_INV_SEL_S = 6 +const GPIO_FUNC242_IN_SEL = 0x0000003F +const GPIO_FUNC242_IN_SEL_V = 0x3F +const GPIO_FUNC242_IN_SEL_S = 0 +const GPIO_SIG243_IN_SEL_V = 0x1 +const GPIO_SIG243_IN_SEL_S = 7 +const GPIO_FUNC243_IN_INV_SEL_V = 0x1 +const GPIO_FUNC243_IN_INV_SEL_S = 6 +const GPIO_FUNC243_IN_SEL = 0x0000003F +const GPIO_FUNC243_IN_SEL_V = 0x3F +const GPIO_FUNC243_IN_SEL_S = 0 +const GPIO_SIG244_IN_SEL_V = 0x1 +const GPIO_SIG244_IN_SEL_S = 7 +const GPIO_FUNC244_IN_INV_SEL_V = 0x1 +const GPIO_FUNC244_IN_INV_SEL_S = 6 +const GPIO_FUNC244_IN_SEL = 0x0000003F +const GPIO_FUNC244_IN_SEL_V = 0x3F +const GPIO_FUNC244_IN_SEL_S = 0 +const GPIO_SIG245_IN_SEL_V = 0x1 +const GPIO_SIG245_IN_SEL_S = 7 +const GPIO_FUNC245_IN_INV_SEL_V = 0x1 +const GPIO_FUNC245_IN_INV_SEL_S = 6 +const GPIO_FUNC245_IN_SEL = 0x0000003F +const GPIO_FUNC245_IN_SEL_V = 0x3F +const GPIO_FUNC245_IN_SEL_S = 0 +const GPIO_SIG246_IN_SEL_V = 0x1 +const GPIO_SIG246_IN_SEL_S = 7 +const GPIO_FUNC246_IN_INV_SEL_V = 0x1 +const GPIO_FUNC246_IN_INV_SEL_S = 6 +const GPIO_FUNC246_IN_SEL = 0x0000003F +const GPIO_FUNC246_IN_SEL_V = 0x3F +const GPIO_FUNC246_IN_SEL_S = 0 +const GPIO_SIG247_IN_SEL_V = 0x1 +const GPIO_SIG247_IN_SEL_S = 7 +const GPIO_FUNC247_IN_INV_SEL_V = 0x1 +const GPIO_FUNC247_IN_INV_SEL_S = 6 +const GPIO_FUNC247_IN_SEL = 0x0000003F +const GPIO_FUNC247_IN_SEL_V = 0x3F +const GPIO_FUNC247_IN_SEL_S = 0 +const GPIO_SIG248_IN_SEL_V = 0x1 +const GPIO_SIG248_IN_SEL_S = 7 +const GPIO_FUNC248_IN_INV_SEL_V = 0x1 +const GPIO_FUNC248_IN_INV_SEL_S = 6 +const GPIO_FUNC248_IN_SEL = 0x0000003F +const GPIO_FUNC248_IN_SEL_V = 0x3F +const GPIO_FUNC248_IN_SEL_S = 0 +const GPIO_SIG249_IN_SEL_V = 0x1 +const GPIO_SIG249_IN_SEL_S = 7 +const GPIO_FUNC249_IN_INV_SEL_V = 0x1 +const GPIO_FUNC249_IN_INV_SEL_S = 6 +const GPIO_FUNC249_IN_SEL = 0x0000003F +const GPIO_FUNC249_IN_SEL_V = 0x3F +const GPIO_FUNC249_IN_SEL_S = 0 +const GPIO_SIG250_IN_SEL_V = 0x1 +const GPIO_SIG250_IN_SEL_S = 7 +const GPIO_FUNC250_IN_INV_SEL_V = 0x1 +const GPIO_FUNC250_IN_INV_SEL_S = 6 +const GPIO_FUNC250_IN_SEL = 0x0000003F +const GPIO_FUNC250_IN_SEL_V = 0x3F +const GPIO_FUNC250_IN_SEL_S = 0 +const GPIO_SIG251_IN_SEL_V = 0x1 +const GPIO_SIG251_IN_SEL_S = 7 +const GPIO_FUNC251_IN_INV_SEL_V = 0x1 +const GPIO_FUNC251_IN_INV_SEL_S = 6 +const GPIO_FUNC251_IN_SEL = 0x0000003F +const GPIO_FUNC251_IN_SEL_V = 0x3F +const GPIO_FUNC251_IN_SEL_S = 0 +const GPIO_SIG252_IN_SEL_V = 0x1 +const GPIO_SIG252_IN_SEL_S = 7 +const GPIO_FUNC252_IN_INV_SEL_V = 0x1 +const GPIO_FUNC252_IN_INV_SEL_S = 6 +const GPIO_FUNC252_IN_SEL = 0x0000003F +const GPIO_FUNC252_IN_SEL_V = 0x3F +const GPIO_FUNC252_IN_SEL_S = 0 +const GPIO_SIG253_IN_SEL_V = 0x1 +const GPIO_SIG253_IN_SEL_S = 7 +const GPIO_FUNC253_IN_INV_SEL_V = 0x1 +const GPIO_FUNC253_IN_INV_SEL_S = 6 +const GPIO_FUNC253_IN_SEL = 0x0000003F +const GPIO_FUNC253_IN_SEL_V = 0x3F +const GPIO_FUNC253_IN_SEL_S = 0 +const GPIO_SIG254_IN_SEL_V = 0x1 +const GPIO_SIG254_IN_SEL_S = 7 +const GPIO_FUNC254_IN_INV_SEL_V = 0x1 +const GPIO_FUNC254_IN_INV_SEL_S = 6 +const GPIO_FUNC254_IN_SEL = 0x0000003F +const GPIO_FUNC254_IN_SEL_V = 0x3F +const GPIO_FUNC254_IN_SEL_S = 0 +const GPIO_SIG255_IN_SEL_V = 0x1 +const GPIO_SIG255_IN_SEL_S = 7 +const GPIO_FUNC255_IN_INV_SEL_V = 0x1 +const GPIO_FUNC255_IN_INV_SEL_S = 6 +const GPIO_FUNC255_IN_SEL = 0x0000003F +const GPIO_FUNC255_IN_SEL_V = 0x3F +const GPIO_FUNC255_IN_SEL_S = 0 +const GPIO_FUNC0_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC0_OEN_INV_SEL_S = 11 +const GPIO_FUNC0_OEN_SEL_V = 0x1 +const GPIO_FUNC0_OEN_SEL_S = 10 +const GPIO_FUNC0_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC0_OUT_INV_SEL_S = 9 +const GPIO_FUNC0_OUT_SEL = 0x000001FF +const GPIO_FUNC0_OUT_SEL_V = 0x1FF +const GPIO_FUNC0_OUT_SEL_S = 0 +const GPIO_FUNC1_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC1_OEN_INV_SEL_S = 11 +const GPIO_FUNC1_OEN_SEL_V = 0x1 +const GPIO_FUNC1_OEN_SEL_S = 10 +const GPIO_FUNC1_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC1_OUT_INV_SEL_S = 9 +const GPIO_FUNC1_OUT_SEL = 0x000001FF +const GPIO_FUNC1_OUT_SEL_V = 0x1FF +const GPIO_FUNC1_OUT_SEL_S = 0 +const GPIO_FUNC2_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC2_OEN_INV_SEL_S = 11 +const GPIO_FUNC2_OEN_SEL_V = 0x1 +const GPIO_FUNC2_OEN_SEL_S = 10 +const GPIO_FUNC2_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC2_OUT_INV_SEL_S = 9 +const GPIO_FUNC2_OUT_SEL = 0x000001FF +const GPIO_FUNC2_OUT_SEL_V = 0x1FF +const GPIO_FUNC2_OUT_SEL_S = 0 +const GPIO_FUNC3_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC3_OEN_INV_SEL_S = 11 +const GPIO_FUNC3_OEN_SEL_V = 0x1 +const GPIO_FUNC3_OEN_SEL_S = 10 +const GPIO_FUNC3_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC3_OUT_INV_SEL_S = 9 +const GPIO_FUNC3_OUT_SEL = 0x000001FF +const GPIO_FUNC3_OUT_SEL_V = 0x1FF +const GPIO_FUNC3_OUT_SEL_S = 0 +const GPIO_FUNC4_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC4_OEN_INV_SEL_S = 11 +const GPIO_FUNC4_OEN_SEL_V = 0x1 +const GPIO_FUNC4_OEN_SEL_S = 10 +const GPIO_FUNC4_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC4_OUT_INV_SEL_S = 9 +const GPIO_FUNC4_OUT_SEL = 0x000001FF +const GPIO_FUNC4_OUT_SEL_V = 0x1FF +const GPIO_FUNC4_OUT_SEL_S = 0 +const GPIO_FUNC5_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC5_OEN_INV_SEL_S = 11 +const GPIO_FUNC5_OEN_SEL_V = 0x1 +const GPIO_FUNC5_OEN_SEL_S = 10 +const GPIO_FUNC5_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC5_OUT_INV_SEL_S = 9 +const GPIO_FUNC5_OUT_SEL = 0x000001FF +const GPIO_FUNC5_OUT_SEL_V = 0x1FF +const GPIO_FUNC5_OUT_SEL_S = 0 +const GPIO_FUNC6_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC6_OEN_INV_SEL_S = 11 +const GPIO_FUNC6_OEN_SEL_V = 0x1 +const GPIO_FUNC6_OEN_SEL_S = 10 +const GPIO_FUNC6_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC6_OUT_INV_SEL_S = 9 +const GPIO_FUNC6_OUT_SEL = 0x000001FF +const GPIO_FUNC6_OUT_SEL_V = 0x1FF +const GPIO_FUNC6_OUT_SEL_S = 0 +const GPIO_FUNC7_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC7_OEN_INV_SEL_S = 11 +const GPIO_FUNC7_OEN_SEL_V = 0x1 +const GPIO_FUNC7_OEN_SEL_S = 10 +const GPIO_FUNC7_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC7_OUT_INV_SEL_S = 9 +const GPIO_FUNC7_OUT_SEL = 0x000001FF +const GPIO_FUNC7_OUT_SEL_V = 0x1FF +const GPIO_FUNC7_OUT_SEL_S = 0 +const GPIO_FUNC8_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC8_OEN_INV_SEL_S = 11 +const GPIO_FUNC8_OEN_SEL_V = 0x1 +const GPIO_FUNC8_OEN_SEL_S = 10 +const GPIO_FUNC8_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC8_OUT_INV_SEL_S = 9 +const GPIO_FUNC8_OUT_SEL = 0x000001FF +const GPIO_FUNC8_OUT_SEL_V = 0x1FF +const GPIO_FUNC8_OUT_SEL_S = 0 +const GPIO_FUNC9_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC9_OEN_INV_SEL_S = 11 +const GPIO_FUNC9_OEN_SEL_V = 0x1 +const GPIO_FUNC9_OEN_SEL_S = 10 +const GPIO_FUNC9_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC9_OUT_INV_SEL_S = 9 +const GPIO_FUNC9_OUT_SEL = 0x000001FF +const GPIO_FUNC9_OUT_SEL_V = 0x1FF +const GPIO_FUNC9_OUT_SEL_S = 0 +const GPIO_FUNC10_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC10_OEN_INV_SEL_S = 11 +const GPIO_FUNC10_OEN_SEL_V = 0x1 +const GPIO_FUNC10_OEN_SEL_S = 10 +const GPIO_FUNC10_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC10_OUT_INV_SEL_S = 9 +const GPIO_FUNC10_OUT_SEL = 0x000001FF +const GPIO_FUNC10_OUT_SEL_V = 0x1FF +const GPIO_FUNC10_OUT_SEL_S = 0 +const GPIO_FUNC11_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC11_OEN_INV_SEL_S = 11 +const GPIO_FUNC11_OEN_SEL_V = 0x1 +const GPIO_FUNC11_OEN_SEL_S = 10 +const GPIO_FUNC11_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC11_OUT_INV_SEL_S = 9 +const GPIO_FUNC11_OUT_SEL = 0x000001FF +const GPIO_FUNC11_OUT_SEL_V = 0x1FF +const GPIO_FUNC11_OUT_SEL_S = 0 +const GPIO_FUNC12_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC12_OEN_INV_SEL_S = 11 +const GPIO_FUNC12_OEN_SEL_V = 0x1 +const GPIO_FUNC12_OEN_SEL_S = 10 +const GPIO_FUNC12_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC12_OUT_INV_SEL_S = 9 +const GPIO_FUNC12_OUT_SEL = 0x000001FF +const GPIO_FUNC12_OUT_SEL_V = 0x1FF +const GPIO_FUNC12_OUT_SEL_S = 0 +const GPIO_FUNC13_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC13_OEN_INV_SEL_S = 11 +const GPIO_FUNC13_OEN_SEL_V = 0x1 +const GPIO_FUNC13_OEN_SEL_S = 10 +const GPIO_FUNC13_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC13_OUT_INV_SEL_S = 9 +const GPIO_FUNC13_OUT_SEL = 0x000001FF +const GPIO_FUNC13_OUT_SEL_V = 0x1FF +const GPIO_FUNC13_OUT_SEL_S = 0 +const GPIO_FUNC14_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC14_OEN_INV_SEL_S = 11 +const GPIO_FUNC14_OEN_SEL_V = 0x1 +const GPIO_FUNC14_OEN_SEL_S = 10 +const GPIO_FUNC14_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC14_OUT_INV_SEL_S = 9 +const GPIO_FUNC14_OUT_SEL = 0x000001FF +const GPIO_FUNC14_OUT_SEL_V = 0x1FF +const GPIO_FUNC14_OUT_SEL_S = 0 +const GPIO_FUNC15_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC15_OEN_INV_SEL_S = 11 +const GPIO_FUNC15_OEN_SEL_V = 0x1 +const GPIO_FUNC15_OEN_SEL_S = 10 +const GPIO_FUNC15_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC15_OUT_INV_SEL_S = 9 +const GPIO_FUNC15_OUT_SEL = 0x000001FF +const GPIO_FUNC15_OUT_SEL_V = 0x1FF +const GPIO_FUNC15_OUT_SEL_S = 0 +const GPIO_FUNC16_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC16_OEN_INV_SEL_S = 11 +const GPIO_FUNC16_OEN_SEL_V = 0x1 +const GPIO_FUNC16_OEN_SEL_S = 10 +const GPIO_FUNC16_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC16_OUT_INV_SEL_S = 9 +const GPIO_FUNC16_OUT_SEL = 0x000001FF +const GPIO_FUNC16_OUT_SEL_V = 0x1FF +const GPIO_FUNC16_OUT_SEL_S = 0 +const GPIO_FUNC17_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC17_OEN_INV_SEL_S = 11 +const GPIO_FUNC17_OEN_SEL_V = 0x1 +const GPIO_FUNC17_OEN_SEL_S = 10 +const GPIO_FUNC17_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC17_OUT_INV_SEL_S = 9 +const GPIO_FUNC17_OUT_SEL = 0x000001FF +const GPIO_FUNC17_OUT_SEL_V = 0x1FF +const GPIO_FUNC17_OUT_SEL_S = 0 +const GPIO_FUNC18_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC18_OEN_INV_SEL_S = 11 +const GPIO_FUNC18_OEN_SEL_V = 0x1 +const GPIO_FUNC18_OEN_SEL_S = 10 +const GPIO_FUNC18_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC18_OUT_INV_SEL_S = 9 +const GPIO_FUNC18_OUT_SEL = 0x000001FF +const GPIO_FUNC18_OUT_SEL_V = 0x1FF +const GPIO_FUNC18_OUT_SEL_S = 0 +const GPIO_FUNC19_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC19_OEN_INV_SEL_S = 11 +const GPIO_FUNC19_OEN_SEL_V = 0x1 +const GPIO_FUNC19_OEN_SEL_S = 10 +const GPIO_FUNC19_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC19_OUT_INV_SEL_S = 9 +const GPIO_FUNC19_OUT_SEL = 0x000001FF +const GPIO_FUNC19_OUT_SEL_V = 0x1FF +const GPIO_FUNC19_OUT_SEL_S = 0 +const GPIO_FUNC20_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC20_OEN_INV_SEL_S = 11 +const GPIO_FUNC20_OEN_SEL_V = 0x1 +const GPIO_FUNC20_OEN_SEL_S = 10 +const GPIO_FUNC20_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC20_OUT_INV_SEL_S = 9 +const GPIO_FUNC20_OUT_SEL = 0x000001FF +const GPIO_FUNC20_OUT_SEL_V = 0x1FF +const GPIO_FUNC20_OUT_SEL_S = 0 +const GPIO_FUNC21_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC21_OEN_INV_SEL_S = 11 +const GPIO_FUNC21_OEN_SEL_V = 0x1 +const GPIO_FUNC21_OEN_SEL_S = 10 +const GPIO_FUNC21_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC21_OUT_INV_SEL_S = 9 +const GPIO_FUNC21_OUT_SEL = 0x000001FF +const GPIO_FUNC21_OUT_SEL_V = 0x1FF +const GPIO_FUNC21_OUT_SEL_S = 0 +const GPIO_FUNC22_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC22_OEN_INV_SEL_S = 11 +const GPIO_FUNC22_OEN_SEL_V = 0x1 +const GPIO_FUNC22_OEN_SEL_S = 10 +const GPIO_FUNC22_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC22_OUT_INV_SEL_S = 9 +const GPIO_FUNC22_OUT_SEL = 0x000001FF +const GPIO_FUNC22_OUT_SEL_V = 0x1FF +const GPIO_FUNC22_OUT_SEL_S = 0 +const GPIO_FUNC23_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC23_OEN_INV_SEL_S = 11 +const GPIO_FUNC23_OEN_SEL_V = 0x1 +const GPIO_FUNC23_OEN_SEL_S = 10 +const GPIO_FUNC23_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC23_OUT_INV_SEL_S = 9 +const GPIO_FUNC23_OUT_SEL = 0x000001FF +const GPIO_FUNC23_OUT_SEL_V = 0x1FF +const GPIO_FUNC23_OUT_SEL_S = 0 +const GPIO_FUNC24_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC24_OEN_INV_SEL_S = 11 +const GPIO_FUNC24_OEN_SEL_V = 0x1 +const GPIO_FUNC24_OEN_SEL_S = 10 +const GPIO_FUNC24_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC24_OUT_INV_SEL_S = 9 +const GPIO_FUNC24_OUT_SEL = 0x000001FF +const GPIO_FUNC24_OUT_SEL_V = 0x1FF +const GPIO_FUNC24_OUT_SEL_S = 0 +const GPIO_FUNC25_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC25_OEN_INV_SEL_S = 11 +const GPIO_FUNC25_OEN_SEL_V = 0x1 +const GPIO_FUNC25_OEN_SEL_S = 10 +const GPIO_FUNC25_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC25_OUT_INV_SEL_S = 9 +const GPIO_FUNC25_OUT_SEL = 0x000001FF +const GPIO_FUNC25_OUT_SEL_V = 0x1FF +const GPIO_FUNC25_OUT_SEL_S = 0 +const GPIO_FUNC26_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC26_OEN_INV_SEL_S = 11 +const GPIO_FUNC26_OEN_SEL_V = 0x1 +const GPIO_FUNC26_OEN_SEL_S = 10 +const GPIO_FUNC26_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC26_OUT_INV_SEL_S = 9 +const GPIO_FUNC26_OUT_SEL = 0x000001FF +const GPIO_FUNC26_OUT_SEL_V = 0x1FF +const GPIO_FUNC26_OUT_SEL_S = 0 +const GPIO_FUNC27_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC27_OEN_INV_SEL_S = 11 +const GPIO_FUNC27_OEN_SEL_V = 0x1 +const GPIO_FUNC27_OEN_SEL_S = 10 +const GPIO_FUNC27_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC27_OUT_INV_SEL_S = 9 +const GPIO_FUNC27_OUT_SEL = 0x000001FF +const GPIO_FUNC27_OUT_SEL_V = 0x1FF +const GPIO_FUNC27_OUT_SEL_S = 0 +const GPIO_FUNC28_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC28_OEN_INV_SEL_S = 11 +const GPIO_FUNC28_OEN_SEL_V = 0x1 +const GPIO_FUNC28_OEN_SEL_S = 10 +const GPIO_FUNC28_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC28_OUT_INV_SEL_S = 9 +const GPIO_FUNC28_OUT_SEL = 0x000001FF +const GPIO_FUNC28_OUT_SEL_V = 0x1FF +const GPIO_FUNC28_OUT_SEL_S = 0 +const GPIO_FUNC29_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC29_OEN_INV_SEL_S = 11 +const GPIO_FUNC29_OEN_SEL_V = 0x1 +const GPIO_FUNC29_OEN_SEL_S = 10 +const GPIO_FUNC29_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC29_OUT_INV_SEL_S = 9 +const GPIO_FUNC29_OUT_SEL = 0x000001FF +const GPIO_FUNC29_OUT_SEL_V = 0x1FF +const GPIO_FUNC29_OUT_SEL_S = 0 +const GPIO_FUNC30_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC30_OEN_INV_SEL_S = 11 +const GPIO_FUNC30_OEN_SEL_V = 0x1 +const GPIO_FUNC30_OEN_SEL_S = 10 +const GPIO_FUNC30_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC30_OUT_INV_SEL_S = 9 +const GPIO_FUNC30_OUT_SEL = 0x000001FF +const GPIO_FUNC30_OUT_SEL_V = 0x1FF +const GPIO_FUNC30_OUT_SEL_S = 0 +const GPIO_FUNC31_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC31_OEN_INV_SEL_S = 11 +const GPIO_FUNC31_OEN_SEL_V = 0x1 +const GPIO_FUNC31_OEN_SEL_S = 10 +const GPIO_FUNC31_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC31_OUT_INV_SEL_S = 9 +const GPIO_FUNC31_OUT_SEL = 0x000001FF +const GPIO_FUNC31_OUT_SEL_V = 0x1FF +const GPIO_FUNC31_OUT_SEL_S = 0 +const GPIO_FUNC32_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC32_OEN_INV_SEL_S = 11 +const GPIO_FUNC32_OEN_SEL_V = 0x1 +const GPIO_FUNC32_OEN_SEL_S = 10 +const GPIO_FUNC32_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC32_OUT_INV_SEL_S = 9 +const GPIO_FUNC32_OUT_SEL = 0x000001FF +const GPIO_FUNC32_OUT_SEL_V = 0x1FF +const GPIO_FUNC32_OUT_SEL_S = 0 +const GPIO_FUNC33_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC33_OEN_INV_SEL_S = 11 +const GPIO_FUNC33_OEN_SEL_V = 0x1 +const GPIO_FUNC33_OEN_SEL_S = 10 +const GPIO_FUNC33_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC33_OUT_INV_SEL_S = 9 +const GPIO_FUNC33_OUT_SEL = 0x000001FF +const GPIO_FUNC33_OUT_SEL_V = 0x1FF +const GPIO_FUNC33_OUT_SEL_S = 0 +const GPIO_FUNC34_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC34_OEN_INV_SEL_S = 11 +const GPIO_FUNC34_OEN_SEL_V = 0x1 +const GPIO_FUNC34_OEN_SEL_S = 10 +const GPIO_FUNC34_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC34_OUT_INV_SEL_S = 9 +const GPIO_FUNC34_OUT_SEL = 0x000001FF +const GPIO_FUNC34_OUT_SEL_V = 0x1FF +const GPIO_FUNC34_OUT_SEL_S = 0 +const GPIO_FUNC35_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC35_OEN_INV_SEL_S = 11 +const GPIO_FUNC35_OEN_SEL_V = 0x1 +const GPIO_FUNC35_OEN_SEL_S = 10 +const GPIO_FUNC35_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC35_OUT_INV_SEL_S = 9 +const GPIO_FUNC35_OUT_SEL = 0x000001FF +const GPIO_FUNC35_OUT_SEL_V = 0x1FF +const GPIO_FUNC35_OUT_SEL_S = 0 +const GPIO_FUNC36_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC36_OEN_INV_SEL_S = 11 +const GPIO_FUNC36_OEN_SEL_V = 0x1 +const GPIO_FUNC36_OEN_SEL_S = 10 +const GPIO_FUNC36_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC36_OUT_INV_SEL_S = 9 +const GPIO_FUNC36_OUT_SEL = 0x000001FF +const GPIO_FUNC36_OUT_SEL_V = 0x1FF +const GPIO_FUNC36_OUT_SEL_S = 0 +const GPIO_FUNC37_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC37_OEN_INV_SEL_S = 11 +const GPIO_FUNC37_OEN_SEL_V = 0x1 +const GPIO_FUNC37_OEN_SEL_S = 10 +const GPIO_FUNC37_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC37_OUT_INV_SEL_S = 9 +const GPIO_FUNC37_OUT_SEL = 0x000001FF +const GPIO_FUNC37_OUT_SEL_V = 0x1FF +const GPIO_FUNC37_OUT_SEL_S = 0 +const GPIO_FUNC38_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC38_OEN_INV_SEL_S = 11 +const GPIO_FUNC38_OEN_SEL_V = 0x1 +const GPIO_FUNC38_OEN_SEL_S = 10 +const GPIO_FUNC38_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC38_OUT_INV_SEL_S = 9 +const GPIO_FUNC38_OUT_SEL = 0x000001FF +const GPIO_FUNC38_OUT_SEL_V = 0x1FF +const GPIO_FUNC38_OUT_SEL_S = 0 +const GPIO_FUNC39_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC39_OEN_INV_SEL_S = 11 +const GPIO_FUNC39_OEN_SEL_V = 0x1 +const GPIO_FUNC39_OEN_SEL_S = 10 +const GPIO_FUNC39_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC39_OUT_INV_SEL_S = 9 +const GPIO_FUNC39_OUT_SEL = 0x000001FF +const GPIO_FUNC39_OUT_SEL_V = 0x1FF +const GPIO_FUNC39_OUT_SEL_S = 0 +const GPIO_FUNC40_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC40_OEN_INV_SEL_S = 11 +const GPIO_FUNC40_OEN_SEL_V = 0x1 +const GPIO_FUNC40_OEN_SEL_S = 10 +const GPIO_FUNC40_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC40_OUT_INV_SEL_S = 9 +const GPIO_FUNC40_OUT_SEL = 0x000001FF +const GPIO_FUNC40_OUT_SEL_V = 0x1FF +const GPIO_FUNC40_OUT_SEL_S = 0 +const GPIO_FUNC41_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC41_OEN_INV_SEL_S = 11 +const GPIO_FUNC41_OEN_SEL_V = 0x1 +const GPIO_FUNC41_OEN_SEL_S = 10 +const GPIO_FUNC41_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC41_OUT_INV_SEL_S = 9 +const GPIO_FUNC41_OUT_SEL = 0x000001FF +const GPIO_FUNC41_OUT_SEL_V = 0x1FF +const GPIO_FUNC41_OUT_SEL_S = 0 +const GPIO_FUNC42_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC42_OEN_INV_SEL_S = 11 +const GPIO_FUNC42_OEN_SEL_V = 0x1 +const GPIO_FUNC42_OEN_SEL_S = 10 +const GPIO_FUNC42_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC42_OUT_INV_SEL_S = 9 +const GPIO_FUNC42_OUT_SEL = 0x000001FF +const GPIO_FUNC42_OUT_SEL_V = 0x1FF +const GPIO_FUNC42_OUT_SEL_S = 0 +const GPIO_FUNC43_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC43_OEN_INV_SEL_S = 11 +const GPIO_FUNC43_OEN_SEL_V = 0x1 +const GPIO_FUNC43_OEN_SEL_S = 10 +const GPIO_FUNC43_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC43_OUT_INV_SEL_S = 9 +const GPIO_FUNC43_OUT_SEL = 0x000001FF +const GPIO_FUNC43_OUT_SEL_V = 0x1FF +const GPIO_FUNC43_OUT_SEL_S = 0 +const GPIO_FUNC44_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC44_OEN_INV_SEL_S = 11 +const GPIO_FUNC44_OEN_SEL_V = 0x1 +const GPIO_FUNC44_OEN_SEL_S = 10 +const GPIO_FUNC44_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC44_OUT_INV_SEL_S = 9 +const GPIO_FUNC44_OUT_SEL = 0x000001FF +const GPIO_FUNC44_OUT_SEL_V = 0x1FF +const GPIO_FUNC44_OUT_SEL_S = 0 +const GPIO_FUNC45_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC45_OEN_INV_SEL_S = 11 +const GPIO_FUNC45_OEN_SEL_V = 0x1 +const GPIO_FUNC45_OEN_SEL_S = 10 +const GPIO_FUNC45_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC45_OUT_INV_SEL_S = 9 +const GPIO_FUNC45_OUT_SEL = 0x000001FF +const GPIO_FUNC45_OUT_SEL_V = 0x1FF +const GPIO_FUNC45_OUT_SEL_S = 0 +const GPIO_FUNC46_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC46_OEN_INV_SEL_S = 11 +const GPIO_FUNC46_OEN_SEL_V = 0x1 +const GPIO_FUNC46_OEN_SEL_S = 10 +const GPIO_FUNC46_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC46_OUT_INV_SEL_S = 9 +const GPIO_FUNC46_OUT_SEL = 0x000001FF +const GPIO_FUNC46_OUT_SEL_V = 0x1FF +const GPIO_FUNC46_OUT_SEL_S = 0 +const GPIO_FUNC47_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC47_OEN_INV_SEL_S = 11 +const GPIO_FUNC47_OEN_SEL_V = 0x1 +const GPIO_FUNC47_OEN_SEL_S = 10 +const GPIO_FUNC47_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC47_OUT_INV_SEL_S = 9 +const GPIO_FUNC47_OUT_SEL = 0x000001FF +const GPIO_FUNC47_OUT_SEL_V = 0x1FF +const GPIO_FUNC47_OUT_SEL_S = 0 +const GPIO_FUNC48_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC48_OEN_INV_SEL_S = 11 +const GPIO_FUNC48_OEN_SEL_V = 0x1 +const GPIO_FUNC48_OEN_SEL_S = 10 +const GPIO_FUNC48_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC48_OUT_INV_SEL_S = 9 +const GPIO_FUNC48_OUT_SEL = 0x000001FF +const GPIO_FUNC48_OUT_SEL_V = 0x1FF +const GPIO_FUNC48_OUT_SEL_S = 0 +const GPIO_FUNC49_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC49_OEN_INV_SEL_S = 11 +const GPIO_FUNC49_OEN_SEL_V = 0x1 +const GPIO_FUNC49_OEN_SEL_S = 10 +const GPIO_FUNC49_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC49_OUT_INV_SEL_S = 9 +const GPIO_FUNC49_OUT_SEL = 0x000001FF +const GPIO_FUNC49_OUT_SEL_V = 0x1FF +const GPIO_FUNC49_OUT_SEL_S = 0 +const GPIO_FUNC50_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC50_OEN_INV_SEL_S = 11 +const GPIO_FUNC50_OEN_SEL_V = 0x1 +const GPIO_FUNC50_OEN_SEL_S = 10 +const GPIO_FUNC50_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC50_OUT_INV_SEL_S = 9 +const GPIO_FUNC50_OUT_SEL = 0x000001FF +const GPIO_FUNC50_OUT_SEL_V = 0x1FF +const GPIO_FUNC50_OUT_SEL_S = 0 +const GPIO_FUNC51_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC51_OEN_INV_SEL_S = 11 +const GPIO_FUNC51_OEN_SEL_V = 0x1 +const GPIO_FUNC51_OEN_SEL_S = 10 +const GPIO_FUNC51_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC51_OUT_INV_SEL_S = 9 +const GPIO_FUNC51_OUT_SEL = 0x000001FF +const GPIO_FUNC51_OUT_SEL_V = 0x1FF +const GPIO_FUNC51_OUT_SEL_S = 0 +const GPIO_FUNC52_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC52_OEN_INV_SEL_S = 11 +const GPIO_FUNC52_OEN_SEL_V = 0x1 +const GPIO_FUNC52_OEN_SEL_S = 10 +const GPIO_FUNC52_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC52_OUT_INV_SEL_S = 9 +const GPIO_FUNC52_OUT_SEL = 0x000001FF +const GPIO_FUNC52_OUT_SEL_V = 0x1FF +const GPIO_FUNC52_OUT_SEL_S = 0 +const GPIO_FUNC53_OEN_INV_SEL_V = 0x1 +const GPIO_FUNC53_OEN_INV_SEL_S = 11 +const GPIO_FUNC53_OEN_SEL_V = 0x1 +const GPIO_FUNC53_OEN_SEL_S = 10 +const GPIO_FUNC53_OUT_INV_SEL_V = 0x1 +const GPIO_FUNC53_OUT_INV_SEL_S = 9 +const GPIO_FUNC53_OUT_SEL = 0x000001FF +const GPIO_FUNC53_OUT_SEL_V = 0x1FF +const GPIO_FUNC53_OUT_SEL_S = 0 +const GPIO_CLK_EN_V = 0x1 +const GPIO_CLK_EN_S = 0 +const GPIO_DATE = 0x0FFFFFFF +const GPIO_DATE_V = 0xFFFFFFF +const GPIO_DATE_S = 0 diff --git a/esp32/gpio_sd_reg.go b/esp32/gpio_sd_reg.go new file mode 100644 index 00000000..98f5aa2b --- /dev/null +++ b/esp32/gpio_sd_reg.go @@ -0,0 +1,61 @@ +package freertos + +import _ "unsafe" + +const GPIO_SD0_PRESCALE = 0x000000FF +const GPIO_SD0_PRESCALE_V = 0xFF +const GPIO_SD0_PRESCALE_S = 8 +const GPIO_SD0_IN = 0x000000FF +const GPIO_SD0_IN_V = 0xFF +const GPIO_SD0_IN_S = 0 +const GPIO_SD1_PRESCALE = 0x000000FF +const GPIO_SD1_PRESCALE_V = 0xFF +const GPIO_SD1_PRESCALE_S = 8 +const GPIO_SD1_IN = 0x000000FF +const GPIO_SD1_IN_V = 0xFF +const GPIO_SD1_IN_S = 0 +const GPIO_SD2_PRESCALE = 0x000000FF +const GPIO_SD2_PRESCALE_V = 0xFF +const GPIO_SD2_PRESCALE_S = 8 +const GPIO_SD2_IN = 0x000000FF +const GPIO_SD2_IN_V = 0xFF +const GPIO_SD2_IN_S = 0 +const GPIO_SD3_PRESCALE = 0x000000FF +const GPIO_SD3_PRESCALE_V = 0xFF +const GPIO_SD3_PRESCALE_S = 8 +const GPIO_SD3_IN = 0x000000FF +const GPIO_SD3_IN_V = 0xFF +const GPIO_SD3_IN_S = 0 +const GPIO_SD4_PRESCALE = 0x000000FF +const GPIO_SD4_PRESCALE_V = 0xFF +const GPIO_SD4_PRESCALE_S = 8 +const GPIO_SD4_IN = 0x000000FF +const GPIO_SD4_IN_V = 0xFF +const GPIO_SD4_IN_S = 0 +const GPIO_SD5_PRESCALE = 0x000000FF +const GPIO_SD5_PRESCALE_V = 0xFF +const GPIO_SD5_PRESCALE_S = 8 +const GPIO_SD5_IN = 0x000000FF +const GPIO_SD5_IN_V = 0xFF +const GPIO_SD5_IN_S = 0 +const GPIO_SD6_PRESCALE = 0x000000FF +const GPIO_SD6_PRESCALE_V = 0xFF +const GPIO_SD6_PRESCALE_S = 8 +const GPIO_SD6_IN = 0x000000FF +const GPIO_SD6_IN_V = 0xFF +const GPIO_SD6_IN_S = 0 +const GPIO_SD7_PRESCALE = 0x000000FF +const GPIO_SD7_PRESCALE_V = 0xFF +const GPIO_SD7_PRESCALE_S = 8 +const GPIO_SD7_IN = 0x000000FF +const GPIO_SD7_IN_V = 0xFF +const GPIO_SD7_IN_S = 0 +const GPIO_SD_CLK_EN_V = 0x1 +const GPIO_SD_CLK_EN_S = 31 +const GPIO_SPI_SWAP_V = 0x1 +const GPIO_SPI_SWAP_S = 31 +const GPIO_FUNCTION_CLK_EN_V = 0x1 +const GPIO_FUNCTION_CLK_EN_S = 30 +const GPIO_SD_DATE = 0x0FFFFFFF +const GPIO_SD_DATE_V = 0xFFFFFFF +const GPIO_SD_DATE_S = 0 diff --git a/esp32/gpio_sd_struct.go b/esp32/gpio_sd_struct.go new file mode 100644 index 00000000..7cdde734 --- /dev/null +++ b/esp32/gpio_sd_struct.go @@ -0,0 +1,21 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type GpioSdDevT struct { + Channel [8]struct { + Val c.Uint32T + } + Cg struct { + Val c.Uint32T + } + Misc struct { + Val c.Uint32T + } + Version struct { + Val c.Uint32T + } +} diff --git a/esp32/gpio_sig_map.go b/esp32/gpio_sig_map.go new file mode 100644 index 00000000..a97daf66 --- /dev/null +++ b/esp32/gpio_sig_map.go @@ -0,0 +1,445 @@ +package freertos + +import _ "unsafe" + +const SPIQ_IN_IDX = 0 +const SPIQ_OUT_IDX = 0 +const SPID_IN_IDX = 1 +const SPID_OUT_IDX = 1 +const SPIHD_IN_IDX = 2 +const SPIHD_OUT_IDX = 2 +const SPIWP_IN_IDX = 3 +const SPIWP_OUT_IDX = 3 +const SPICLK_OUT_IDX = 4 +const SPICS0_OUT_IDX = 5 +const SPICS1_OUT_IDX = 6 +const SPID4_IN_IDX = 7 +const SPID4_OUT_IDX = 7 +const SPID5_IN_IDX = 8 +const SPID5_OUT_IDX = 8 +const SPID6_IN_IDX = 9 +const SPID6_OUT_IDX = 9 +const SPID7_IN_IDX = 10 +const SPID7_OUT_IDX = 10 +const SPIDQS_IN_IDX = 11 +const SPIDQS_OUT_IDX = 11 +const U0RXD_IN_IDX = 12 +const U0TXD_OUT_IDX = 12 +const U0CTS_IN_IDX = 13 +const U0RTS_OUT_IDX = 13 +const U0DSR_IN_IDX = 14 +const U0DTR_OUT_IDX = 14 +const U1RXD_IN_IDX = 15 +const U1TXD_OUT_IDX = 15 +const U1CTS_IN_IDX = 16 +const U1RTS_OUT_IDX = 16 +const U1DSR_IN_IDX = 17 +const U1DTR_OUT_IDX = 17 +const U2RXD_IN_IDX = 18 +const U2TXD_OUT_IDX = 18 +const U2CTS_IN_IDX = 19 +const U2RTS_OUT_IDX = 19 +const U2DSR_IN_IDX = 20 +const U2DTR_OUT_IDX = 20 +const I2S1_MCLK_IN_IDX = 21 +const I2S1_MCLK_OUT_IDX = 21 +const I2S0O_BCK_IN_IDX = 22 +const I2S0O_BCK_OUT_IDX = 22 +const I2S0_MCLK_IN_IDX = 23 +const I2S0_MCLK_OUT_IDX = 23 +const I2S0O_WS_IN_IDX = 24 +const I2S0O_WS_OUT_IDX = 24 +const I2S0I_SD_IN_IDX = 25 +const I2S0O_SD_OUT_IDX = 25 +const I2S0I_BCK_IN_IDX = 26 +const I2S0I_BCK_OUT_IDX = 26 +const I2S0I_WS_IN_IDX = 27 +const I2S0I_WS_OUT_IDX = 27 +const I2S1O_BCK_IN_IDX = 28 +const I2S1O_BCK_OUT_IDX = 28 +const I2S1O_WS_IN_IDX = 29 +const I2S1O_WS_OUT_IDX = 29 +const I2S1I_SD_IN_IDX = 30 +const I2S1O_SD_OUT_IDX = 30 +const I2S1I_BCK_IN_IDX = 31 +const I2S1I_BCK_OUT_IDX = 31 +const I2S1I_WS_IN_IDX = 32 +const I2S1I_WS_OUT_IDX = 32 +const PCNT_SIG_CH0_IN0_IDX = 33 +const GPIO_WLAN_PRIO_IDX = 33 +const PCNT_SIG_CH1_IN0_IDX = 34 +const GPIO_WLAN_ACTIVE_IDX = 34 +const PCNT_CTRL_CH0_IN0_IDX = 35 +const BB_DIAG0_IDX = 35 +const PCNT_CTRL_CH1_IN0_IDX = 36 +const BB_DIAG1_IDX = 36 +const PCNT_SIG_CH0_IN1_IDX = 37 +const BB_DIAG2_IDX = 37 +const PCNT_SIG_CH1_IN1_IDX = 38 +const BB_DIAG3_IDX = 38 +const PCNT_CTRL_CH0_IN1_IDX = 39 +const BB_DIAG4_IDX = 39 +const PCNT_CTRL_CH1_IN1_IDX = 40 +const BB_DIAG5_IDX = 40 +const PCNT_SIG_CH0_IN2_IDX = 41 +const BB_DIAG6_IDX = 41 +const PCNT_SIG_CH1_IN2_IDX = 42 +const BB_DIAG7_IDX = 42 +const PCNT_CTRL_CH0_IN2_IDX = 43 +const BB_DIAG8_IDX = 43 +const PCNT_CTRL_CH1_IN2_IDX = 44 +const BB_DIAG9_IDX = 44 +const PCNT_SIG_CH0_IN3_IDX = 45 +const BB_DIAG10_IDX = 45 +const PCNT_SIG_CH1_IN3_IDX = 46 +const BB_DIAG11_IDX = 46 +const PCNT_CTRL_CH0_IN3_IDX = 47 +const BB_DIAG12_IDX = 47 +const PCNT_CTRL_CH1_IN3_IDX = 48 +const BB_DIAG13_IDX = 48 +const GPIO_BT_ACTIVE_IDX = 49 +const BB_DIAG14_IDX = 49 +const GPIO_BT_PRIORITY_IDX = 50 +const BB_DIAG15_IDX = 50 +const I2S0I_SD1_IN_IDX = 51 +const BB_DIAG16_IDX = 51 +const I2S0I_SD2_IN_IDX = 52 +const BB_DIAG17_IDX = 52 +const I2S0I_SD3_IN_IDX = 53 +const BB_DIAG18_IDX = 53 +const CORE1_GPIO_IN7_IDX = 54 +const CORE1_GPIO_OUT7_IDX = 54 +const USB_EXTPHY_VP_IDX = 55 +const USB_EXTPHY_OEN_IDX = 55 +const USB_EXTPHY_VM_IDX = 56 +const USB_EXTPHY_SPEED_IDX = 56 +const USB_EXTPHY_RCV_IDX = 57 +const USB_EXTPHY_VPO_IDX = 57 +const USB_OTG_IDDIG_IN_IDX = 58 +const USB_EXTPHY_VMO_IDX = 58 +const USB_OTG_AVALID_IN_IDX = 59 +const USB_EXTPHY_SUSPND_IDX = 59 +const USB_SRP_BVALID_IN_IDX = 60 +const USB_OTG_IDPULLUP_IDX = 60 +const USB_OTG_VBUSVALID_IN_IDX = 61 +const USB_OTG_DPPULLDOWN_IDX = 61 +const USB_SRP_SESSEND_IN_IDX = 62 +const USB_OTG_DMPULLDOWN_IDX = 62 +const USB_OTG_DRVVBUS_IDX = 63 +const USB_SRP_CHRGVBUS_IDX = 64 +const USB_SRP_DISCHRGVBUS_IDX = 65 +const SPI3_CLK_IN_IDX = 66 +const SPI3_CLK_OUT_IDX = 66 +const SPI3_Q_IN_IDX = 67 +const SPI3_Q_OUT_IDX = 67 +const SPI3_D_IN_IDX = 68 +const SPI3_D_OUT_IDX = 68 +const SPI3_HD_IN_IDX = 69 +const SPI3_HD_OUT_IDX = 69 +const SPI3_WP_IN_IDX = 70 +const SPI3_WP_OUT_IDX = 70 +const SPI3_CS0_IN_IDX = 71 +const SPI3_CS0_OUT_IDX = 71 +const SPI3_CS1_OUT_IDX = 72 +const EXT_ADC_START_IDX = 73 +const LEDC_LS_SIG_OUT0_IDX = 73 +const LEDC_LS_SIG_OUT1_IDX = 74 +const LEDC_LS_SIG_OUT2_IDX = 75 +const LEDC_LS_SIG_OUT3_IDX = 76 +const LEDC_LS_SIG_OUT4_IDX = 77 +const LEDC_LS_SIG_OUT5_IDX = 78 +const LEDC_LS_SIG_OUT6_IDX = 79 +const LEDC_LS_SIG_OUT7_IDX = 80 +const RMT_SIG_IN0_IDX = 81 +const RMT_SIG_OUT0_IDX = 81 +const RMT_SIG_IN1_IDX = 82 +const RMT_SIG_OUT1_IDX = 82 +const RMT_SIG_IN2_IDX = 83 +const RMT_SIG_OUT2_IDX = 83 +const RMT_SIG_IN3_IDX = 84 +const RMT_SIG_OUT3_IDX = 84 +const USB_JTAG_TCK_IDX = 85 +const USB_JTAG_TMS_IDX = 86 +const USB_JTAG_TDI_IDX = 87 +const USB_JTAG_TDO_IDX = 88 +const I2CEXT0_SCL_IN_IDX = 89 +const I2CEXT0_SCL_OUT_IDX = 89 +const I2CEXT0_SDA_IN_IDX = 90 +const I2CEXT0_SDA_OUT_IDX = 90 +const I2CEXT1_SCL_IN_IDX = 91 +const I2CEXT1_SCL_OUT_IDX = 91 +const I2CEXT1_SDA_IN_IDX = 92 +const I2CEXT1_SDA_OUT_IDX = 92 +const GPIO_SD0_OUT_IDX = 93 +const GPIO_SD1_OUT_IDX = 94 +const GPIO_SD2_OUT_IDX = 95 +const GPIO_SD3_OUT_IDX = 96 +const GPIO_SD4_OUT_IDX = 97 +const GPIO_SD5_OUT_IDX = 98 +const GPIO_SD6_OUT_IDX = 99 +const GPIO_SD7_OUT_IDX = 100 +const FSPICLK_IN_IDX = 101 +const FSPICLK_OUT_IDX = 101 +const FSPIQ_IN_IDX = 102 +const FSPIQ_OUT_IDX = 102 +const FSPID_IN_IDX = 103 +const FSPID_OUT_IDX = 103 +const FSPIHD_IN_IDX = 104 +const FSPIHD_OUT_IDX = 104 +const FSPIWP_IN_IDX = 105 +const FSPIWP_OUT_IDX = 105 +const FSPIIO4_IN_IDX = 106 +const FSPIIO4_OUT_IDX = 106 +const FSPIIO5_IN_IDX = 107 +const FSPIIO5_OUT_IDX = 107 +const FSPIIO6_IN_IDX = 108 +const FSPIIO6_OUT_IDX = 108 +const FSPIIO7_IN_IDX = 109 +const FSPIIO7_OUT_IDX = 109 +const FSPICS0_IN_IDX = 110 +const FSPICS0_OUT_IDX = 110 +const FSPICS1_OUT_IDX = 111 +const FSPICS2_OUT_IDX = 112 +const FSPICS3_OUT_IDX = 113 +const FSPICS4_OUT_IDX = 114 +const FSPICS5_OUT_IDX = 115 +const TWAI_RX_IDX = 116 +const TWAI_TX_IDX = 116 +const TWAI_BUS_OFF_ON_IDX = 117 +const TWAI_CLKOUT_IDX = 118 +const SUBSPICLK_OUT_IDX = 119 +const SUBSPIQ_IN_IDX = 120 +const SUBSPIQ_OUT_IDX = 120 +const SUBSPID_IN_IDX = 121 +const SUBSPID_OUT_IDX = 121 +const SUBSPIHD_IN_IDX = 122 +const SUBSPIHD_OUT_IDX = 122 +const SUBSPIWP_IN_IDX = 123 +const SUBSPIWP_OUT_IDX = 123 +const SUBSPICS0_OUT_IDX = 124 +const SUBSPICS1_OUT_IDX = 125 +const FSPIDQS_OUT_IDX = 126 +const SPI3_CS2_OUT_IDX = 127 +const I2S0O_SD1_OUT_IDX = 128 +const CORE1_GPIO_IN0_IDX = 129 +const CORE1_GPIO_OUT0_IDX = 129 +const CORE1_GPIO_IN1_IDX = 130 +const CORE1_GPIO_OUT1_IDX = 130 +const CORE1_GPIO_IN2_IDX = 131 +const CORE1_GPIO_OUT2_IDX = 131 +const LCD_CS_IDX = 132 +const CAM_DATA_IN0_IDX = 133 +const LCD_DATA_OUT0_IDX = 133 +const CAM_DATA_IN1_IDX = 134 +const LCD_DATA_OUT1_IDX = 134 +const CAM_DATA_IN2_IDX = 135 +const LCD_DATA_OUT2_IDX = 135 +const CAM_DATA_IN3_IDX = 136 +const LCD_DATA_OUT3_IDX = 136 +const CAM_DATA_IN4_IDX = 137 +const LCD_DATA_OUT4_IDX = 137 +const CAM_DATA_IN5_IDX = 138 +const LCD_DATA_OUT5_IDX = 138 +const CAM_DATA_IN6_IDX = 139 +const LCD_DATA_OUT6_IDX = 139 +const CAM_DATA_IN7_IDX = 140 +const LCD_DATA_OUT7_IDX = 140 +const CAM_DATA_IN8_IDX = 141 +const LCD_DATA_OUT8_IDX = 141 +const CAM_DATA_IN9_IDX = 142 +const LCD_DATA_OUT9_IDX = 142 +const CAM_DATA_IN10_IDX = 143 +const LCD_DATA_OUT10_IDX = 143 +const CAM_DATA_IN11_IDX = 144 +const LCD_DATA_OUT11_IDX = 144 +const CAM_DATA_IN12_IDX = 145 +const LCD_DATA_OUT12_IDX = 145 +const CAM_DATA_IN13_IDX = 146 +const LCD_DATA_OUT13_IDX = 146 +const CAM_DATA_IN14_IDX = 147 +const LCD_DATA_OUT14_IDX = 147 +const CAM_DATA_IN15_IDX = 148 +const LCD_DATA_OUT15_IDX = 148 +const CAM_PCLK_IDX = 149 +const CAM_CLK_IDX = 149 +const CAM_H_ENABLE_IDX = 150 +const LCD_H_ENABLE_IDX = 150 +const CAM_H_SYNC_IDX = 151 +const LCD_H_SYNC_IDX = 151 +const CAM_V_SYNC_IDX = 152 +const LCD_V_SYNC_IDX = 152 +const LCD_DC_IDX = 153 +const LCD_PCLK_IDX = 154 +const SUBSPID4_IN_IDX = 155 +const SUBSPID4_OUT_IDX = 155 +const SUBSPID5_IN_IDX = 156 +const SUBSPID5_OUT_IDX = 156 +const SUBSPID6_IN_IDX = 157 +const SUBSPID6_OUT_IDX = 157 +const SUBSPID7_IN_IDX = 158 +const SUBSPID7_OUT_IDX = 158 +const SUBSPIDQS_IN_IDX = 159 +const SUBSPIDQS_OUT_IDX = 159 +const PWM0_SYNC0_IN_IDX = 160 +const PWM0_OUT0A_IDX = 160 +const PWM0_SYNC1_IN_IDX = 161 +const PWM0_OUT0B_IDX = 161 +const PWM0_SYNC2_IN_IDX = 162 +const PWM0_OUT1A_IDX = 162 +const PWM0_F0_IN_IDX = 163 +const PWM0_OUT1B_IDX = 163 +const PWM0_F1_IN_IDX = 164 +const PWM0_OUT2A_IDX = 164 +const PWM0_F2_IN_IDX = 165 +const PWM0_OUT2B_IDX = 165 +const PWM0_CAP0_IN_IDX = 166 +const PWM1_OUT0A_IDX = 166 +const PWM0_CAP1_IN_IDX = 167 +const PWM1_OUT0B_IDX = 167 +const PWM0_CAP2_IN_IDX = 168 +const PWM1_OUT1A_IDX = 168 +const PWM1_SYNC0_IN_IDX = 169 +const PWM1_OUT1B_IDX = 169 +const PWM1_SYNC1_IN_IDX = 170 +const PWM1_OUT2A_IDX = 170 +const PWM1_SYNC2_IN_IDX = 171 +const PWM1_OUT2B_IDX = 171 +const PWM1_F0_IN_IDX = 172 +const SDHOST_CCLK_OUT_1_IDX = 172 +const PWM1_F1_IN_IDX = 173 +const SDHOST_CCLK_OUT_2_IDX = 173 +const PWM1_F2_IN_IDX = 174 +const SDHOST_RST_N_1_IDX = 174 +const PWM1_CAP0_IN_IDX = 175 +const SDHOST_RST_N_2_IDX = 175 +const PWM1_CAP1_IN_IDX = 176 +const PWM1_CAP2_IN_IDX = 177 +const SDIO_TOHOST_INT_OUT_IDX = 177 +const SDHOST_CCMD_IN_1_IDX = 178 +const SDHOST_CCMD_OUT_1_IDX = 178 +const SDHOST_CCMD_IN_2_IDX = 179 +const SDHOST_CCMD_OUT_2_IDX = 179 +const SDHOST_CDATA_IN_10_IDX = 180 +const SDHOST_CDATA_OUT_10_IDX = 180 +const SDHOST_CDATA_IN_11_IDX = 181 +const SDHOST_CDATA_OUT_11_IDX = 181 +const SDHOST_CDATA_IN_12_IDX = 182 +const SDHOST_CDATA_OUT_12_IDX = 182 +const SDHOST_CDATA_IN_13_IDX = 183 +const SDHOST_CDATA_OUT_13_IDX = 183 +const SDHOST_CDATA_IN_14_IDX = 184 +const SDHOST_CDATA_OUT_14_IDX = 184 +const SDHOST_CDATA_IN_15_IDX = 185 +const SDHOST_CDATA_OUT_15_IDX = 185 +const SDHOST_CDATA_IN_16_IDX = 186 +const SDHOST_CDATA_OUT_16_IDX = 186 +const SDHOST_CDATA_IN_17_IDX = 187 +const SDHOST_CDATA_OUT_17_IDX = 187 +const PCMFSYNC_IN_IDX = 188 +const BT_AUDIO0_IRQ_IDX = 188 +const PCMCLK_IN_IDX = 189 +const BT_AUDIO1_IRQ_IDX = 189 +const PCMDIN_IDX = 190 +const BT_AUDIO2_IRQ_IDX = 190 +const RW_WAKEUP_REQ_IDX = 191 +const BLE_AUDIO0_IRQ_IDX = 191 +const SDHOST_DATA_STROBE_1_IDX = 192 +const BLE_AUDIO1_IRQ_IDX = 192 +const SDHOST_DATA_STROBE_2_IDX = 193 +const BLE_AUDIO2_IRQ_IDX = 193 +const SDHOST_CARD_DETECT_N_1_IDX = 194 +const PCMFSYNC_OUT_IDX = 194 +const SDHOST_CARD_DETECT_N_2_IDX = 195 +const PCMCLK_OUT_IDX = 195 +const SDHOST_CARD_WRITE_PRT_1_IDX = 196 +const PCMDOUT_IDX = 196 +const SDHOST_CARD_WRITE_PRT_2_IDX = 197 +const BLE_AUDIO_SYNC0_P_IDX = 197 +const SDHOST_CARD_INT_N_1_IDX = 198 +const BLE_AUDIO_SYNC1_P_IDX = 198 +const SDHOST_CARD_INT_N_2_IDX = 199 +const BLE_AUDIO_SYNC2_P_IDX = 199 +const ANT_SEL0_IDX = 200 +const ANT_SEL1_IDX = 201 +const ANT_SEL2_IDX = 202 +const ANT_SEL3_IDX = 203 +const ANT_SEL4_IDX = 204 +const ANT_SEL5_IDX = 205 +const ANT_SEL6_IDX = 206 +const ANT_SEL7_IDX = 207 +const SIG_IN_FUNC_208_IDX = 208 +const SIG_IN_FUNC208_IDX = 208 +const SIG_IN_FUNC_209_IDX = 209 +const SIG_IN_FUNC209_IDX = 209 +const SIG_IN_FUNC_210_IDX = 210 +const SIG_IN_FUNC210_IDX = 210 +const SIG_IN_FUNC_211_IDX = 211 +const SIG_IN_FUNC211_IDX = 211 +const SIG_IN_FUNC_212_IDX = 212 +const SIG_IN_FUNC212_IDX = 212 +const SDHOST_CDATA_IN_20_IDX = 213 +const SDHOST_CDATA_OUT_20_IDX = 213 +const SDHOST_CDATA_IN_21_IDX = 214 +const SDHOST_CDATA_OUT_21_IDX = 214 +const SDHOST_CDATA_IN_22_IDX = 215 +const SDHOST_CDATA_OUT_22_IDX = 215 +const SDHOST_CDATA_IN_23_IDX = 216 +const SDHOST_CDATA_OUT_23_IDX = 216 +const SDHOST_CDATA_IN_24_IDX = 217 +const SDHOST_CDATA_OUT_24_IDX = 217 +const SDHOST_CDATA_IN_25_IDX = 218 +const SDHOST_CDATA_OUT_25_IDX = 218 +const SDHOST_CDATA_IN_26_IDX = 219 +const SDHOST_CDATA_OUT_26_IDX = 219 +const SDHOST_CDATA_IN_27_IDX = 220 +const SDHOST_CDATA_OUT_27_IDX = 220 +const PRO_ALONEGPIO_IN0_IDX = 221 +const PRO_ALONEGPIO_OUT0_IDX = 221 +const PRO_ALONEGPIO_IN1_IDX = 222 +const PRO_ALONEGPIO_OUT1_IDX = 222 +const PRO_ALONEGPIO_IN2_IDX = 223 +const PRO_ALONEGPIO_OUT2_IDX = 223 +const PRO_ALONEGPIO_IN3_IDX = 224 +const PRO_ALONEGPIO_OUT3_IDX = 224 +const PRO_ALONEGPIO_IN4_IDX = 225 +const PRO_ALONEGPIO_OUT4_IDX = 225 +const PRO_ALONEGPIO_IN5_IDX = 226 +const PRO_ALONEGPIO_OUT5_IDX = 226 +const PRO_ALONEGPIO_IN6_IDX = 227 +const PRO_ALONEGPIO_OUT6_IDX = 227 +const PRO_ALONEGPIO_IN7_IDX = 228 +const PRO_ALONEGPIO_OUT7_IDX = 228 +const SYNCERR_IDX = 229 +const SYNCFOUND_FLAG_IDX = 230 +const EVT_CNTL_IMMEDIATE_ABORT_IDX = 231 +const LINKLBL_IDX = 232 +const DATA_EN_IDX = 233 +const DATA_IDX = 234 +const PKT_TX_ON_IDX = 235 +const PKT_RX_ON_IDX = 236 +const RW_TX_ON_IDX = 237 +const RW_RX_ON_IDX = 238 +const EVT_REQ_P_IDX = 239 +const EVT_STOP_P_IDX = 240 +const BT_MODE_ON_IDX = 241 +const GPIO_LC_DIAG0_IDX = 242 +const GPIO_LC_DIAG1_IDX = 243 +const GPIO_LC_DIAG2_IDX = 244 +const CH_IDX_IDX = 245 +const RX_WINDOW_IDX = 246 +const UPDATE_RX_IDX = 247 +const RX_STATUS_IDX = 248 +const CLK_GPIO_IDX = 249 +const NBT_BLE_IDX = 250 +const USB_JTAG_TDO_BRIDGE_IDX = 251 +const USB_JTAG_TRST_IDX = 251 +const CORE1_GPIO_IN3_IDX = 252 +const CORE1_GPIO_OUT3_IDX = 252 +const CORE1_GPIO_IN4_IDX = 253 +const CORE1_GPIO_OUT4_IDX = 253 +const CORE1_GPIO_IN5_IDX = 254 +const CORE1_GPIO_OUT5_IDX = 254 +const CORE1_GPIO_IN6_IDX = 255 +const CORE1_GPIO_OUT6_IDX = 255 +const SIG_GPIO_OUT_IDX = 256 +const GPIO_MAP_DATE_IDX = 0x1907040 diff --git a/esp32/gpio_struct.go b/esp32/gpio_struct.go new file mode 100644 index 00000000..fc2f493a --- /dev/null +++ b/esp32/gpio_struct.go @@ -0,0 +1,139 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type GpioDevS struct { + BtSelect c.Uint32T + Out c.Uint32T + OutW1ts c.Uint32T + OutW1tc c.Uint32T + Out1 struct { + Val c.Uint32T + } + Out1W1ts struct { + Val c.Uint32T + } + Out1W1tc struct { + Val c.Uint32T + } + SdioSelect struct { + Val c.Uint32T + } + Enable c.Uint32T + EnableW1ts c.Uint32T + EnableW1tc c.Uint32T + Enable1 struct { + Val c.Uint32T + } + Enable1W1ts struct { + Val c.Uint32T + } + Enable1W1tc struct { + Val c.Uint32T + } + Strap struct { + Val c.Uint32T + } + In c.Uint32T + In1 struct { + Val c.Uint32T + } + Status c.Uint32T + StatusW1ts c.Uint32T + StatusW1tc c.Uint32T + Status1 struct { + Val c.Uint32T + } + Status1W1ts struct { + Val c.Uint32T + } + Status1W1tc struct { + Val c.Uint32T + } + PcpuInt c.Uint32T + PcpuNmiInt c.Uint32T + CpusdioInt c.Uint32T + PcpuInt1 struct { + Val c.Uint32T + } + PcpuNmiInt1 struct { + Val c.Uint32T + } + CpusdioInt1 struct { + Val c.Uint32T + } + Pin [54]struct { + Val c.Uint32T + } + StatusNext c.Uint32T + StatusNext1 struct { + Val c.Uint32T + } + FuncInSelCfg [256]struct { + Val c.Uint32T + } + FuncOutSelCfg [54]struct { + Val c.Uint32T + } + ClockGate struct { + Val c.Uint32T + } + Reserved630 c.Uint32T + Reserved634 c.Uint32T + Reserved638 c.Uint32T + Reserved63c c.Uint32T + Reserved640 c.Uint32T + Reserved644 c.Uint32T + Reserved648 c.Uint32T + Reserved64c c.Uint32T + Reserved650 c.Uint32T + Reserved654 c.Uint32T + Reserved658 c.Uint32T + Reserved65c c.Uint32T + Reserved660 c.Uint32T + Reserved664 c.Uint32T + Reserved668 c.Uint32T + Reserved66c c.Uint32T + Reserved670 c.Uint32T + Reserved674 c.Uint32T + Reserved678 c.Uint32T + Reserved67c c.Uint32T + Reserved680 c.Uint32T + Reserved684 c.Uint32T + Reserved688 c.Uint32T + Reserved68c c.Uint32T + Reserved690 c.Uint32T + Reserved694 c.Uint32T + Reserved698 c.Uint32T + Reserved69c c.Uint32T + Reserved6a0 c.Uint32T + Reserved6a4 c.Uint32T + Reserved6a8 c.Uint32T + Reserved6ac c.Uint32T + Reserved6b0 c.Uint32T + Reserved6b4 c.Uint32T + Reserved6b8 c.Uint32T + Reserved6bc c.Uint32T + Reserved6c0 c.Uint32T + Reserved6c4 c.Uint32T + Reserved6c8 c.Uint32T + Reserved6cc c.Uint32T + Reserved6d0 c.Uint32T + Reserved6d4 c.Uint32T + Reserved6d8 c.Uint32T + Reserved6dc c.Uint32T + Reserved6e0 c.Uint32T + Reserved6e4 c.Uint32T + Reserved6e8 c.Uint32T + Reserved6ec c.Uint32T + Reserved6f0 c.Uint32T + Reserved6f4 c.Uint32T + Reserved6f8 c.Uint32T + Date struct { + Val c.Uint32T + } +} +type GpioDevT GpioDevS diff --git a/esp32/gpio_types.go b/esp32/gpio_types.go new file mode 100644 index 00000000..2e388d27 --- /dev/null +++ b/esp32/gpio_types.go @@ -0,0 +1,70 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type GpioPortT c.Int + +const ( + GPIO_PORT_0 GpioPortT = 0 + GPIO_PORT_MAX GpioPortT = 1 +) + +type GpioIntTypeT c.Int + +const ( + GPIO_INTR_DISABLE GpioIntTypeT = 0 + GPIO_INTR_POSEDGE GpioIntTypeT = 1 + GPIO_INTR_NEGEDGE GpioIntTypeT = 2 + GPIO_INTR_ANYEDGE GpioIntTypeT = 3 + GPIO_INTR_LOW_LEVEL GpioIntTypeT = 4 + GPIO_INTR_HIGH_LEVEL GpioIntTypeT = 5 + GPIO_INTR_MAX GpioIntTypeT = 6 +) + +type GpioModeT c.Int + +const ( + GPIO_MODE_DISABLE GpioModeT = 0 + GPIO_MODE_INPUT GpioModeT = 1 + GPIO_MODE_OUTPUT GpioModeT = 2 + GPIO_MODE_OUTPUT_OD GpioModeT = 6 + GPIO_MODE_INPUT_OUTPUT_OD GpioModeT = 7 + GPIO_MODE_INPUT_OUTPUT GpioModeT = 3 +) + +type GpioPullupT c.Int + +const ( + GPIO_PULLUP_DISABLE GpioPullupT = 0 + GPIO_PULLUP_ENABLE GpioPullupT = 1 +) + +type GpioPulldownT c.Int + +const ( + GPIO_PULLDOWN_DISABLE GpioPulldownT = 0 + GPIO_PULLDOWN_ENABLE GpioPulldownT = 1 +) + +type GpioPullModeT c.Int + +const ( + GPIO_PULLUP_ONLY GpioPullModeT = 0 + GPIO_PULLDOWN_ONLY GpioPullModeT = 1 + GPIO_PULLUP_PULLDOWN GpioPullModeT = 2 + GPIO_FLOATING GpioPullModeT = 3 +) + +type GpioDriveCapT c.Int + +const ( + GPIO_DRIVE_CAP_0 GpioDriveCapT = 0 + GPIO_DRIVE_CAP_1 GpioDriveCapT = 1 + GPIO_DRIVE_CAP_2 GpioDriveCapT = 2 + GPIO_DRIVE_CAP_DEFAULT GpioDriveCapT = 2 + GPIO_DRIVE_CAP_3 GpioDriveCapT = 3 + GPIO_DRIVE_CAP_MAX GpioDriveCapT = 4 +) diff --git a/esp32/hal.go b/esp32/hal.go new file mode 100644 index 00000000..483ac99e --- /dev/null +++ b/esp32/hal.go @@ -0,0 +1,747 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const XTHAL_RELEASE_MAJOR = 12000 +const XTHAL_RELEASE_MINOR = 9 +const XTHAL_RELEASE_NAME = "12.0.9" +const XTHAL_REL_12 = 1 +const XTHAL_REL_12_0 = 1 +const XTHAL_REL_12_0_9 = 1 +const XTHAL_MAX_CPS = 8 +const XTHAL_LITTLEENDIAN = 0 +const XTHAL_BIGENDIAN = 1 +const XTHAL_PREFETCH_DISABLE = 0xFFFF0000 +const XTHAL_DCACHE_PREFETCH_L1_OFF = 0x90000000 +const XTHAL_DCACHE_PREFETCH_L1 = 0x90001000 +const XTHAL_ICACHE_PREFETCH_L1_OFF = 0xA0000000 +const XTHAL_ICACHE_PREFETCH_L1 = 0xA0002000 +const XTHAL_DISASM_BUFSIZE = 80 +const XTHAL_DISASM_OPT_ADDR = 0x0001 +const XTHAL_DISASM_OPT_OPHEX = 0x0002 +const XTHAL_DISASM_OPT_OPCODE = 0x0004 +const XTHAL_DISASM_OPT_PARMS = 0x0008 +const XTHAL_DISASM_OPT_ALL = 0x0FFF +const XTHAL_MAX_INTERRUPTS = 32 +const XTHAL_MAX_INTLEVELS = 16 +const XTHAL_MAX_TIMERS = 4 +const XTHAL_INTTYPE_UNCONFIGURED = 0 +const XTHAL_INTTYPE_SOFTWARE = 1 +const XTHAL_INTTYPE_EXTERN_EDGE = 2 +const XTHAL_INTTYPE_EXTERN_LEVEL = 3 +const XTHAL_INTTYPE_TIMER = 4 +const XTHAL_INTTYPE_NMI = 5 +const XTHAL_INTTYPE_WRITE_ERROR = 6 +const XTHAL_INTTYPE_PROFILING = 7 +const XTHAL_INTTYPE_IDMA_DONE = 8 +const XTHAL_INTTYPE_IDMA_ERR = 9 +const XTHAL_INTTYPE_GS_ERR = 10 +const XTHAL_INTTYPE_SG_ERR = 10 +const XTHAL_MAX_INTTYPES = 11 +const XTHAL_MEMEP_PARITY = 1 +const XTHAL_MEMEP_ECC = 2 +const XTHAL_MEMEP_F_LOCAL = 0 +const XTHAL_MEMEP_F_DCACHE_DATA = 4 +const XTHAL_MEMEP_F_DCACHE_TAG = 5 +const XTHAL_MEMEP_F_ICACHE_DATA = 6 +const XTHAL_MEMEP_F_ICACHE_TAG = 7 +const XTHAL_MEMEP_F_CORRECTABLE = 16 +const XTHAL_AMB_EXCEPTION = 0 +const XTHAL_AMB_HITCACHE = 1 +const XTHAL_AMB_ALLOCATE = 2 +const XTHAL_AMB_WRITETHRU = 3 +const XTHAL_AMB_ISOLATE = 4 +const XTHAL_AMB_GUARD = 5 +const XTHAL_AMB_COHERENT = 6 +const XTHAL_FAM_EXCEPTION = 0x001 +const XTHAL_FAM_BYPASS = 0x000 +const XTHAL_FAM_CACHED = 0x006 +const XTHAL_LAM_EXCEPTION = 0x001 +const XTHAL_LAM_ISOLATE = 0x012 +const XTHAL_LAM_BYPASS = 0x000 +const XTHAL_LAM_BYPASSG = 0x020 +const XTHAL_LAM_CACHED_NOALLOC = 0x002 +const XTHAL_LAM_NACACHEDG = 0x022 +const XTHAL_LAM_CACHED = 0x006 +const XTHAL_LAM_COHCACHED = 0x046 +const XTHAL_SAM_EXCEPTION = 0x001 +const XTHAL_SAM_ISOLATE = 0x032 +const XTHAL_SAM_BYPASS = 0x028 +const XTHAL_SAM_WRITETHRU = 0x02A +const XTHAL_SAM_WRITEBACK = 0x026 +const XTHAL_SAM_WRITEBACK_NOALLOC = 0x022 +const XTHAL_SAM_COHWRITEBACK = 0x066 +const XTHAL_PAM_BYPASS = 0x000 +const XTHAL_PAM_BYPASS_BUF = 0x010 +const XTHAL_PAM_CACHED_NOALLOC = 0x030 +const XTHAL_PAM_WRITETHRU = 0x0B0 +const XTHAL_PAM_WRITEBACK_NOALLOC = 0x0F0 +const XTHAL_PAM_WRITEBACK = 0x1F0 +const XTHAL_CAFLAG_EXPAND = 0x000100 +const XTHAL_CAFLAG_EXACT = 0x000200 +const XTHAL_CAFLAG_NO_PARTIAL = 0x000400 +const XTHAL_CAFLAG_NO_AUTO_WB = 0x000800 +const XTHAL_CAFLAG_NO_AUTO_INV = 0x001000 +const XTHAL_SUCCESS = 0 +const XTHAL_AR_NONE = 0 +const XTHAL_AR_R = 4 +const XTHAL_AR_RX = 5 +const XTHAL_AR_RW = 6 +const XTHAL_AR_RWX = 7 +const XTHAL_AR_Ww = 8 +const XTHAL_AR_RWrwx = 9 +const XTHAL_AR_RWr = 10 +const XTHAL_AR_RWXrx = 11 +const XTHAL_AR_Rr = 12 +const XTHAL_AR_RXrx = 13 +const XTHAL_AR_RWrw = 14 +const XTHAL_AR_RWXrwx = 15 +const XTHAL_AR_WIDTH = 4 +const XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS = 0x00002000 +const XTHAL_MPU_USE_EXISTING_MEMORY_TYPE = 0x00004000 +const XTHAL_MEM_DEVICE = 0x00008000 +const XTHAL_MEM_NON_CACHEABLE = 0x00090000 +const XTHAL_MEM_WRITETHRU_NOALLOC = 0x00080000 +const XTHAL_MEM_WRITETHRU = 0x00040000 +const XTHAL_MEM_WRITETHRU_WRITEALLOC = 0x00060000 +const XTHAL_MEM_WRITEBACK_NOALLOC = 0x00050000 +const XTHAL_MEM_WRITEBACK = 0x00070000 +const XTHAL_MEM_INTERRUPTIBLE = 0x08000000 +const XTHAL_MEM_BUFFERABLE = 0x01000000 +const XTHAL_MEM_NON_SHAREABLE = 0x00000000 +const XTHAL_MEM_INNER_SHAREABLE = 0x02000000 +const XTHAL_MEM_OUTER_SHAREABLE = 0x04000000 +const XTHAL_MEM_SYSTEM_SHAREABLE = 0x06000000 +const X_XTHAL_SYSTEM_CACHE_BITS = 0x000f0000 +const X_XTHAL_LOCAL_CACHE_BITS = 0x00f00000 +const X_XTHAL_MEM_SYSTEM_RWC_MASK = 0x00070000 +const X_XTHAL_MEM_LOCAL_RWC_MASK = 0x00700000 +const X_XTHAL_SHIFT_RWC = 16 +const XTHAL_MEM_SW_SHAREABLE = 0 + +/* save & restore the extra processor state */ +//go:linkname XthalSaveExtra C.xthal_save_extra +func XthalSaveExtra(base c.Pointer) + +//go:linkname XthalRestoreExtra C.xthal_restore_extra +func XthalRestoreExtra(base c.Pointer) + +//go:linkname XthalSaveCpregs C.xthal_save_cpregs +func XthalSaveCpregs(base c.Pointer, __llgo_arg_1 c.Int) + +//go:linkname XthalRestoreCpregs C.xthal_restore_cpregs +func XthalRestoreCpregs(base c.Pointer, __llgo_arg_1 c.Int) + +/* versions specific to each coprocessor id */ +//go:linkname XthalSaveCp0 C.xthal_save_cp0 +func XthalSaveCp0(base c.Pointer) + +//go:linkname XthalSaveCp1 C.xthal_save_cp1 +func XthalSaveCp1(base c.Pointer) + +//go:linkname XthalSaveCp2 C.xthal_save_cp2 +func XthalSaveCp2(base c.Pointer) + +//go:linkname XthalSaveCp3 C.xthal_save_cp3 +func XthalSaveCp3(base c.Pointer) + +//go:linkname XthalSaveCp4 C.xthal_save_cp4 +func XthalSaveCp4(base c.Pointer) + +//go:linkname XthalSaveCp5 C.xthal_save_cp5 +func XthalSaveCp5(base c.Pointer) + +//go:linkname XthalSaveCp6 C.xthal_save_cp6 +func XthalSaveCp6(base c.Pointer) + +//go:linkname XthalSaveCp7 C.xthal_save_cp7 +func XthalSaveCp7(base c.Pointer) + +//go:linkname XthalRestoreCp0 C.xthal_restore_cp0 +func XthalRestoreCp0(base c.Pointer) + +//go:linkname XthalRestoreCp1 C.xthal_restore_cp1 +func XthalRestoreCp1(base c.Pointer) + +//go:linkname XthalRestoreCp2 C.xthal_restore_cp2 +func XthalRestoreCp2(base c.Pointer) + +//go:linkname XthalRestoreCp3 C.xthal_restore_cp3 +func XthalRestoreCp3(base c.Pointer) + +//go:linkname XthalRestoreCp4 C.xthal_restore_cp4 +func XthalRestoreCp4(base c.Pointer) + +//go:linkname XthalRestoreCp5 C.xthal_restore_cp5 +func XthalRestoreCp5(base c.Pointer) + +//go:linkname XthalRestoreCp6 C.xthal_restore_cp6 +func XthalRestoreCp6(base c.Pointer) + +//go:linkname XthalRestoreCp7 C.xthal_restore_cp7 +func XthalRestoreCp7(base c.Pointer) + +/* initialize the extra processor */ +//go:linkname XthalInitMemExtra C.xthal_init_mem_extra +func XthalInitMemExtra(c.Pointer) + +/* initialize the TIE coprocessor */ +//go:linkname XthalInitMemCp C.xthal_init_mem_cp +func XthalInitMemCp(c.Pointer, c.Int) + +/* cache region operations*/ +//go:linkname XthalIcacheRegionInvalidate C.xthal_icache_region_invalidate +func XthalIcacheRegionInvalidate(addr c.Pointer, size c.Uint) + +//go:linkname XthalDcacheRegionInvalidate C.xthal_dcache_region_invalidate +func XthalDcacheRegionInvalidate(addr c.Pointer, size c.Uint) + +//go:linkname XthalDcacheRegionWriteback C.xthal_dcache_region_writeback +func XthalDcacheRegionWriteback(addr c.Pointer, size c.Uint) + +//go:linkname XthalDcacheRegionWritebackInv C.xthal_dcache_region_writeback_inv +func XthalDcacheRegionWritebackInv(addr c.Pointer, size c.Uint) + +/* cache line operations*/ +//go:linkname XthalIcacheLineInvalidate C.xthal_icache_line_invalidate +func XthalIcacheLineInvalidate(addr c.Pointer) + +//go:linkname XthalDcacheLineInvalidate C.xthal_dcache_line_invalidate +func XthalDcacheLineInvalidate(addr c.Pointer) + +//go:linkname XthalDcacheLineWriteback C.xthal_dcache_line_writeback +func XthalDcacheLineWriteback(addr c.Pointer) + +//go:linkname XthalDcacheLineWritebackInv C.xthal_dcache_line_writeback_inv +func XthalDcacheLineWritebackInv(addr c.Pointer) + +/* sync icache and memory */ +//go:linkname XthalIcacheSync C.xthal_icache_sync +func XthalIcacheSync() + +/* sync dcache and memory */ +//go:linkname XthalDcacheSync C.xthal_dcache_sync +func XthalDcacheSync() + +/* get/set number of icache ways enabled */ +//go:linkname XthalIcacheGetWays C.xthal_icache_get_ways +func XthalIcacheGetWays() c.Uint + +//go:linkname XthalIcacheSetWays C.xthal_icache_set_ways +func XthalIcacheSetWays(ways c.Uint) + +/* get/set number of dcache ways enabled */ +//go:linkname XthalDcacheGetWays C.xthal_dcache_get_ways +func XthalDcacheGetWays() c.Uint + +//go:linkname XthalDcacheSetWays C.xthal_dcache_set_ways +func XthalDcacheSetWays(ways c.Uint) + +/* coherency (low-level -- not normally called directly) */ +//go:linkname XthalCacheCoherenceOn C.xthal_cache_coherence_on +func XthalCacheCoherenceOn() + +//go:linkname XthalCacheCoherenceOff C.xthal_cache_coherence_off +func XthalCacheCoherenceOff() + +/* coherency (high-level) */ +//go:linkname XthalCacheCoherenceOptin C.xthal_cache_coherence_optin +func XthalCacheCoherenceOptin() + +//go:linkname XthalCacheCoherenceOptout C.xthal_cache_coherence_optout +func XthalCacheCoherenceOptout() + +//go:linkname XthalGetCachePrefetch C.xthal_get_cache_prefetch +func XthalGetCachePrefetch() c.Int + +//go:linkname XthalSetCachePrefetch C.xthal_set_cache_prefetch +func XthalSetCachePrefetch(c.Int) c.Int + +//go:linkname XthalSetCachePrefetchLong C.xthal_set_cache_prefetch_long +func XthalSetCachePrefetchLong(c.UlongLong) c.Int + +/* Set (plant) and remove software breakpoint, both synchronizing cache: */ +//go:linkname XthalSetSoftBreak C.xthal_set_soft_break +func XthalSetSoftBreak(addr c.Pointer) c.Uint + +//go:linkname XthalRemoveSoftBreak C.xthal_remove_soft_break +func XthalRemoveSoftBreak(addr c.Pointer, __llgo_arg_1 c.Uint) + +/* routine to get a string for the disassembled instruction */ +//go:linkname XthalDisassemble C.xthal_disassemble +func XthalDisassemble(instr_buf *c.Char, tgt_addr c.Pointer, buffer *c.Char, buflen c.Uint, options c.Uint) c.Int + +/* routine to get the size of the next instruction. Returns 0 for + illegal instruction */ +//go:linkname XthalDisassembleSize C.xthal_disassemble_size +func XthalDisassembleSize(instr_buf *c.Char) c.Int + +/*---------------------------------------------------------------------- + Instruction/Data RAM/ROM Access + ----------------------------------------------------------------------*/ +//go:linkname XthalMemcpy C.xthal_memcpy +func XthalMemcpy(dst c.Pointer, src c.Pointer, len c.Uint) c.Pointer + +//go:linkname XthalBcopy C.xthal_bcopy +func XthalBcopy(src c.Pointer, dst c.Pointer, len c.Uint) c.Pointer + +/*---------------------------------------------------------------------- + MP Synchronization +----------------------------------------------------------------------*/ +//go:linkname XthalCompareAndSet C.xthal_compare_and_set +func XthalCompareAndSet(addr *c.Int, test_val c.Int, compare_val c.Int) c.Int + +/* Clear any remnant code-dependent state (i.e. clear loop count regs). */ +//go:linkname XthalClearRegcachedCode C.xthal_clear_regcached_code +func XthalClearRegcachedCode() + +/* This spill any live register windows (other than the caller's): + * (NOTE: current implementation require privileged code, but + * a user-callable implementation is possible.) */ +//go:linkname XthalWindowSpill C.xthal_window_spill +func XthalWindowSpill() + +/* validate & invalidate the TIE register file */ +//go:linkname XthalValidateCp C.xthal_validate_cp +func XthalValidateCp(c.Int) + +//go:linkname XthalInvalidateCp C.xthal_invalidate_cp +func XthalInvalidateCp(c.Int) + +/* read and write cpenable register */ +//go:linkname XthalSetCpenable C.xthal_set_cpenable +func XthalSetCpenable(c.Uint) + +//go:linkname XthalGetCpenable C.xthal_get_cpenable +func XthalGetCpenable() c.Uint + +/* INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions: */ +//go:linkname XthalGetIntenable C.xthal_get_intenable +func XthalGetIntenable() c.Uint + +//go:linkname XthalSetIntenable C.xthal_set_intenable +func XthalSetIntenable(c.Uint) + +//go:linkname XthalGetInterrupt C.xthal_get_interrupt +func XthalGetInterrupt() c.Uint + +/* These two functions are deprecated. Use the newer functions + xthal_interrupt_trigger and xthal_interrupt_clear instead. */ +//go:linkname XthalSetIntset C.xthal_set_intset +func XthalSetIntset(c.Uint) + +//go:linkname XthalSetIntclear C.xthal_set_intclear +func XthalSetIntclear(c.Uint) + +/* get CCOUNT register (if not present return 0) */ +//go:linkname XthalGetCcount C.xthal_get_ccount +func XthalGetCcount() c.Uint + +/* set and get CCOMPAREn registers (if not present, get returns 0) */ +//go:linkname XthalSetCcompare C.xthal_set_ccompare +func XthalSetCcompare(c.Int, c.Uint) + +//go:linkname XthalGetCcompare C.xthal_get_ccompare +func XthalGetCcompare(c.Int) c.Uint + +//go:linkname XthalGetPrid C.xthal_get_prid +func XthalGetPrid() c.Uint + +/* Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities: */ +//go:linkname XthalVpriToIntlevel C.xthal_vpri_to_intlevel +func XthalVpriToIntlevel(vpri c.Uint) c.Uint + +//go:linkname XthalIntlevelToVpri C.xthal_intlevel_to_vpri +func XthalIntlevelToVpri(intlevel c.Uint) c.Uint + +/* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */ +/* These functions are deprecated. Use xthal_interrupt_enable and xthal_interrupt_disable instead. */ +//go:linkname XthalIntEnable C.xthal_int_enable +func XthalIntEnable(c.Uint) c.Uint + +//go:linkname XthalIntDisable C.xthal_int_disable +func XthalIntDisable(c.Uint) c.Uint + +/* Set/get virtual priority of an interrupt: */ +//go:linkname XthalSetIntVpri C.xthal_set_int_vpri +func XthalSetIntVpri(intnum c.Int, vpri c.Int) c.Int + +//go:linkname XthalGetIntVpri C.xthal_get_int_vpri +func XthalGetIntVpri(intnum c.Int) c.Int + +/* Set/get interrupt lockout level for exclusive access to virtual priority data structures: */ +//go:linkname XthalSetVpriLocklevel C.xthal_set_vpri_locklevel +func XthalSetVpriLocklevel(intlevel c.Uint) + +//go:linkname XthalGetVpriLocklevel C.xthal_get_vpri_locklevel +func XthalGetVpriLocklevel() c.Uint + +/* Set/get current virtual interrupt priority: */ +//go:linkname XthalSetVpri C.xthal_set_vpri +func XthalSetVpri(vpri c.Uint) c.Uint + +//go:linkname XthalGetVpri C.xthal_get_vpri +func XthalGetVpri() c.Uint + +//go:linkname XthalSetVpriIntlevel C.xthal_set_vpri_intlevel +func XthalSetVpriIntlevel(intlevel c.Uint) c.Uint + +//go:linkname XthalSetVpriLock C.xthal_set_vpri_lock +func XthalSetVpriLock() c.Uint + +// llgo:type C +type XtHalVoidFunc func() + +/* Trampoline support functions: */ +//go:linkname XthalTramPendingToService C.xthal_tram_pending_to_service +func XthalTramPendingToService() c.Uint + +//go:linkname XthalTramDone C.xthal_tram_done +func XthalTramDone(serviced_mask c.Uint) + +//go:linkname XthalTramSetSync C.xthal_tram_set_sync +func XthalTramSetSync(intnum c.Int, sync c.Int) c.Int + +// llgo:link (*XtHalVoidFunc).XthalSetTramTriggerFunc C.xthal_set_tram_trigger_func +func (recv_ *XtHalVoidFunc) XthalSetTramTriggerFunc() XtHalVoidFunc { + return nil +} + +/* cache attribute register control (used by other HAL routines) */ +//go:linkname XthalGetCacheattr C.xthal_get_cacheattr +func XthalGetCacheattr() c.Uint + +//go:linkname XthalGetIcacheattr C.xthal_get_icacheattr +func XthalGetIcacheattr() c.Uint + +//go:linkname XthalGetDcacheattr C.xthal_get_dcacheattr +func XthalGetDcacheattr() c.Uint + +//go:linkname XthalSetCacheattr C.xthal_set_cacheattr +func XthalSetCacheattr(c.Uint) + +//go:linkname XthalSetIcacheattr C.xthal_set_icacheattr +func XthalSetIcacheattr(c.Uint) + +//go:linkname XthalSetDcacheattr C.xthal_set_dcacheattr +func XthalSetDcacheattr(c.Uint) + +/* set cache attribute (access modes) for a range of memory */ +//go:linkname XthalSetRegionAttribute C.xthal_set_region_attribute +func XthalSetRegionAttribute(addr c.Pointer, size c.Uint, cattr c.Uint, flags c.Uint) c.Int + +/* enable caches */ +//go:linkname XthalIcacheEnable C.xthal_icache_enable +func XthalIcacheEnable() + +//go:linkname XthalDcacheEnable C.xthal_dcache_enable +func XthalDcacheEnable() + +/* disable caches */ +//go:linkname XthalIcacheDisable C.xthal_icache_disable +func XthalIcacheDisable() + +//go:linkname XthalDcacheDisable C.xthal_dcache_disable +func XthalDcacheDisable() + +/* whole cache operations (privileged) */ +//go:linkname XthalIcacheAllInvalidate C.xthal_icache_all_invalidate +func XthalIcacheAllInvalidate() + +//go:linkname XthalDcacheAllInvalidate C.xthal_dcache_all_invalidate +func XthalDcacheAllInvalidate() + +//go:linkname XthalDcacheAllWriteback C.xthal_dcache_all_writeback +func XthalDcacheAllWriteback() + +//go:linkname XthalDcacheAllWritebackInv C.xthal_dcache_all_writeback_inv +func XthalDcacheAllWritebackInv() + +//go:linkname XthalIcacheAllUnlock C.xthal_icache_all_unlock +func XthalIcacheAllUnlock() + +//go:linkname XthalDcacheAllUnlock C.xthal_dcache_all_unlock +func XthalDcacheAllUnlock() + +/* address-range cache operations (privileged) */ +/* prefetch and lock specified memory range into cache */ +//go:linkname XthalIcacheRegionLock C.xthal_icache_region_lock +func XthalIcacheRegionLock(addr c.Pointer, size c.Uint) + +//go:linkname XthalDcacheRegionLock C.xthal_dcache_region_lock +func XthalDcacheRegionLock(addr c.Pointer, size c.Uint) + +/* unlock from cache */ +//go:linkname XthalIcacheRegionUnlock C.xthal_icache_region_unlock +func XthalIcacheRegionUnlock(addr c.Pointer, size c.Uint) + +//go:linkname XthalDcacheRegionUnlock C.xthal_dcache_region_unlock +func XthalDcacheRegionUnlock(addr c.Pointer, size c.Uint) + +/* huge-range cache operations (privileged) (EXPERIMENTAL) */ +//go:linkname XthalIcacheHugerangeInvalidate C.xthal_icache_hugerange_invalidate +func XthalIcacheHugerangeInvalidate(addr c.Pointer, size c.Uint) + +//go:linkname XthalIcacheHugerangeUnlock C.xthal_icache_hugerange_unlock +func XthalIcacheHugerangeUnlock(addr c.Pointer, size c.Uint) + +//go:linkname XthalDcacheHugerangeInvalidate C.xthal_dcache_hugerange_invalidate +func XthalDcacheHugerangeInvalidate(addr c.Pointer, size c.Uint) + +//go:linkname XthalDcacheHugerangeUnlock C.xthal_dcache_hugerange_unlock +func XthalDcacheHugerangeUnlock(addr c.Pointer, size c.Uint) + +//go:linkname XthalDcacheHugerangeWriteback C.xthal_dcache_hugerange_writeback +func XthalDcacheHugerangeWriteback(addr c.Pointer, size c.Uint) + +//go:linkname XthalDcacheHugerangeWritebackInv C.xthal_dcache_hugerange_writeback_inv +func XthalDcacheHugerangeWritebackInv(addr c.Pointer, size c.Uint) + +/* cache line operations (privileged) */ +//go:linkname XthalIcacheLineLock C.xthal_icache_line_lock +func XthalIcacheLineLock(addr c.Pointer) + +//go:linkname XthalDcacheLineLock C.xthal_dcache_line_lock +func XthalDcacheLineLock(addr c.Pointer) + +//go:linkname XthalIcacheLineUnlock C.xthal_icache_line_unlock +func XthalIcacheLineUnlock(addr c.Pointer) + +//go:linkname XthalDcacheLineUnlock C.xthal_dcache_line_unlock +func XthalDcacheLineUnlock(addr c.Pointer) + +/* Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx: */ +//go:linkname XthalMemepInjectError C.xthal_memep_inject_error +func XthalMemepInjectError(addr c.Pointer, size c.Int, flags c.Int) + +/* Convert between virtual and physical addresses (through static maps only) + * WARNING: these two functions may go away in a future release; + * don't depend on them! + */ +//go:linkname XthalStaticV2p C.xthal_static_v2p +func XthalStaticV2p(vaddr c.Uint, paddrp *c.Uint) c.Int + +//go:linkname XthalStaticP2v C.xthal_static_p2v +func XthalStaticP2v(paddr c.Uint, vaddrp *c.Uint, cached c.Uint) c.Int + +//go:linkname XthalSetRegionTranslation C.xthal_set_region_translation +func XthalSetRegionTranslation(vaddr c.Pointer, paddr c.Pointer, size c.Uint, cache_atr c.Uint, flags c.Uint) c.Int + +//go:linkname XthalV2p C.xthal_v2p +func XthalV2p(c.Pointer, *c.Pointer, *c.Uint, *c.Uint) c.Int + +//go:linkname XthalInvalidateRegion C.xthal_invalidate_region +func XthalInvalidateRegion(addr c.Pointer) c.Int + +//go:linkname XthalSetRegionTranslationRaw C.xthal_set_region_translation_raw +func XthalSetRegionTranslationRaw(vaddr c.Pointer, paddr c.Pointer, cattr c.Uint) c.Int + +/* + * This structure is used to represent each MPU entry (both foreground and + * background). The internal representation of the structure is subject to + * change, so it should only be accessed by the XTHAL_MPU_ENTRY_... macros + * below. + */ + +type XthalMPUEntry struct { + As c.Uint32T + At c.Uint32T +} + +/* + * These functions accept encoded access rights, and return 1 if the + * supplied memory type has the property specified by the function name, + * otherwise they return 0. + */ +//go:linkname XthalIsKernelReadable C.xthal_is_kernel_readable +func XthalIsKernelReadable(accessRights c.Uint32T) c.Int32T + +//go:linkname XthalIsKernelWriteable C.xthal_is_kernel_writeable +func XthalIsKernelWriteable(accessRights c.Uint32T) c.Int32T + +//go:linkname XthalIsKernelExecutable C.xthal_is_kernel_executable +func XthalIsKernelExecutable(accessRights c.Uint32T) c.Int32T + +//go:linkname XthalIsUserReadable C.xthal_is_user_readable +func XthalIsUserReadable(accessRights c.Uint32T) c.Int32T + +//go:linkname XthalIsUserWriteable C.xthal_is_user_writeable +func XthalIsUserWriteable(accessRights c.Uint32T) c.Int32T + +//go:linkname XthalIsUserExecutable C.xthal_is_user_executable +func XthalIsUserExecutable(accessRights c.Uint32T) c.Int32T + +/* + * This function converts a bit-wise combination of the XTHAL_MEM_.. constants + * to the corresponding MPU memory type (9-bits). + * + * If none of the XTHAL_MEM_.. bits are present in the argument, then + * bits 4-12 (9-bits) are returned ... this supports using an already encoded + * memoryType (perhaps obtained from an xthal_MPU_entry structure) as input + * to xthal_set_region_attribute(). + * + * This function first checks that the supplied constants are a valid and + * supported combination. If not, it returns XTHAL_BAD_MEMORY_TYPE. + */ +//go:linkname XthalEncodeMemoryType C.xthal_encode_memory_type +func XthalEncodeMemoryType(x c.Uint32T) c.Int + +/* + * This function accepts a 9-bit memory type value (such as returned by + * XTHAL_MEM_ENTRY_GET_MEMORY_TYPE() or xthal_encode_memory_type(). They + * return 1 if the memoryType has the property specified in the function + * name and 0 otherwise. + */ +//go:linkname XthalIsCacheable C.xthal_is_cacheable +func XthalIsCacheable(memoryType c.Uint32T) c.Int32T + +//go:linkname XthalIsWriteback C.xthal_is_writeback +func XthalIsWriteback(memoryType c.Uint32T) c.Int32T + +//go:linkname XthalIsDevice C.xthal_is_device +func XthalIsDevice(memoryType c.Uint32T) c.Int32T + +/* + * Copies the current MPU entry list into 'entries' which + * must point to available memory of at least + * sizeof(struct xthal_MPU_entry) * XCHAL_MPU_ENTRIES. + * + * This function returns XTHAL_SUCCESS. + * XTHAL_INVALID, or + * XTHAL_UNSUPPORTED. + */ +// llgo:link (*XthalMPUEntry).XthalReadMap C.xthal_read_map +func (recv_ *XthalMPUEntry) XthalReadMap() c.Int32T { + return 0 +} + +/* + * Writes the map pointed to by 'entries' to the MPU. Before updating + * the map, it commits any uncommitted + * cache writes, and invalidates the cache if necessary. + * + * This function does not check for the correctness of the map. Generally + * xthal_check_map() should be called first to check the map. + * + * If n == 0 then the existing map is cleared, and no new map is written + * (useful for returning to reset state) + * + * If (n > 0 && n < XCHAL_MPU_ENTRIES) then a new map is written with + * (XCHAL_MPU_ENTRIES-n) padding entries added to ensure a properly ordered + * map. The resulting foreground map will be equivalent to the map vector + * fg, but the position of the padding entries should not be relied upon. + * + * If n == XCHAL_MPU_ENTRIES then the complete map as specified by fg is + * written. + * + * The CACHEADRDIS register will be set to enable caching any 512MB region + * that is overlapped by an MPU region with a cacheable memory type. + * Caching will be disabled if none of the 512 MB region is cacheable. + * + * xthal_write_map() disables the MPU foreground map during the MPU + * update and relies on the background map. + * + * As a result any interrupt that does not meet the following conditions + * must be disabled before calling xthal_write_map(): + * 1) All code and data needed for the interrupt must be + * mapped by the background map with sufficient access rights. + * 2) The interrupt code must not access the MPU. + * + */ +// llgo:link (*XthalMPUEntry).XthalWriteMap C.xthal_write_map +func (recv_ *XthalMPUEntry) XthalWriteMap(n c.Uint32T) { +} + +/* + * Checks if entry vector 'entries' of length 'n' is a valid MPU access map. + * Returns: + * XTHAL_SUCCESS if valid, + * XTHAL_OUT_OF_ENTRIES + * XTHAL_MAP_NOT_ALIGNED, + * XTHAL_BAD_ACCESS_RIGHTS, + * XTHAL_OUT_OF_ORDER_MAP, or + * XTHAL_UNSUPPORTED if config doesn't have an MPU. + */ +// llgo:link (*XthalMPUEntry).XthalCheckMap C.xthal_check_map +func (recv_ *XthalMPUEntry) XthalCheckMap(n c.Uint32T) c.Int { + return 0 +} + +/* + * Returns the MPU entry that maps 'vaddr'. If 'infgmap' is non-NULL then + * *infgmap is set to 1 if 'vaddr' is mapped by the foreground map, and + * *infgmap is set to 0 if 'vaddr' is mapped by the background map. + */ +//go:linkname XthalGetEntryForAddress C.xthal_get_entry_for_address +func XthalGetEntryForAddress(vaddr c.Pointer, infgmap *c.Int32T) XthalMPUEntry + +/* + * Scans the supplied MPU map and returns a value suitable for writing to + * the CACHEADRDIS register: + * Bits 0-7 -> 1 if there are no cacheable areas in the corresponding 512MB + * region and 0 otherwise. + * Bits 8-31 -> undefined. + * This function can accept a partial memory map in the same manner + * xthal_write_map() does, */ +// llgo:link (*XthalMPUEntry).XthalCalcCacheadrdis C.xthal_calc_cacheadrdis +func (recv_ *XthalMPUEntry) XthalCalcCacheadrdis(n c.Uint32T) c.Uint32T { + return 0 +} + +/* + * This function is intended as an MPU specific version of + * xthal_set_region_attributes(). xthal_set_region_attributes() calls + * this function for MPU configurations. + * + * This function sets the attributes for the region [vaddr, vaddr+size) + * in the MPU. + * + * Depending on the state of the MPU this function will require from + * 0 to 3 unused MPU entries. + * + * This function typically will move, add, and subtract entries from + * the MPU map during execution, so that the resulting map may + * be quite different than when the function was called. + * + * This function does make the following guarantees: + * 1) The MPU access map remains in a valid state at all times + * during its execution. + * 2) At all points during (and after) completion the memoryType + * and accessRights remain the same for all addresses + * that are not in the range [vaddr, vaddr+size). + * 3) If XTHAL_SUCCESS is returned, then the range + * [vaddr, vaddr+size) will have the accessRights and memoryType + * specified. + * 4) The CACHEADRDIS register will be set to enable caching any 512MB region + * that is overlapped by an MPU region with a cacheable memory type. + * Caching will be disabled if none of the 512 MB region is cacheable. + * + * The accessRights parameter should be either a 4-bit value corresponding + * to an MPU access mode (as defined by the XTHAL_AR_.. constants), or + * XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS. + * + * The memoryType parameter should be either a bit-wise or-ing of XTHAL_MEM_.. + * constants that represent a valid MPU memoryType, a 9-bit MPU memoryType + * value, or XTHAL_MPU_USE_EXISTING_MEMORY_TYPE. + * + * In addition to the error codes that xthal_set_region_attribute() + * returns, this function can also return: XTHAL_BAD_ACCESS_RIGHTS + * (if the access rights bits map to an unsupported combination), or + * XTHAL_OUT_OF_MAP_ENTRIES (if there are not enough unused MPU entries) + * + * If this function is called with an invalid MPU map, then this function + * will return one of the codes that is returned by xthal_check_map(). + * + * The flag, XTHAL_CAFLAG_EXPAND, is not supported + * + */ +//go:linkname XthalMpuSetRegionAttribute C.xthal_mpu_set_region_attribute +func XthalMpuSetRegionAttribute(vaddr c.Pointer, size c.SizeT, accessRights c.Int32T, memoryType c.Int32T, flags c.Uint32T) c.Int + +// llgo:link (*XthalMPUEntry).XthalReadBackgroundMap C.xthal_read_background_map +func (recv_ *XthalMPUEntry) XthalReadBackgroundMap() c.Int32T { + return 0 +} diff --git a/esp32/hal_utils.go b/esp32/hal_utils.go new file mode 100644 index 00000000..0a7b5214 --- /dev/null +++ b/esp32/hal_utils.go @@ -0,0 +1,116 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type HalUtilsDivRoundOptT c.Int + +const ( + HAL_DIV_ROUND_DOWN HalUtilsDivRoundOptT = 0 + HAL_DIV_ROUND_UP HalUtilsDivRoundOptT = 1 + HAL_DIV_ROUND HalUtilsDivRoundOptT = 2 +) + +/** + * @brief Clock information + * + */ + +type HalUtilsClkInfoT struct { + SrcFreqHz c.Uint32T + ExpFreqHz c.Uint32T + MaxInteg c.Uint32T + MinInteg c.Uint32T +} + +/** + * @brief Members of clock division + * + */ + +type HalUtilsClkDivT struct { + Integer c.Uint32T + Denominator c.Uint32T + Numerator c.Uint32T +} + +/** + * @brief Calculate the clock division with fractal part fast + * @note Speed first algorithm, Time complexity O(log n). + * About 8~10 times faster than the accurate algorithm + * + * @param[in] clk_info The clock information + * @param[out] clk_div The clock division with integral and fractal part + * @return + * - 0: Failed to get the result because the division is out of range + * - others: The real output clock frequency + */ +// llgo:link (*HalUtilsClkInfoT).HalUtilsCalcClkDivFracFast C.hal_utils_calc_clk_div_frac_fast +func (recv_ *HalUtilsClkInfoT) HalUtilsCalcClkDivFracFast(clk_div *HalUtilsClkDivT) c.Uint32T { + return 0 +} + +/** + * @brief Calculate the clock division with fractal part accurately + * @note Accuracy first algorithm, Time complexity O(n). + * About 1~hundreds times more accurate than the fast algorithm + * + * @param[in] clk_info The clock information + * @param[out] clk_div The clock division with integral and fractal part + * @return + * - 0: Failed to get the result because the division is out of range + * - others: The real output clock frequency + */ +// llgo:link (*HalUtilsClkInfoT).HalUtilsCalcClkDivFracAccurate C.hal_utils_calc_clk_div_frac_accurate +func (recv_ *HalUtilsClkInfoT) HalUtilsCalcClkDivFracAccurate(clk_div *HalUtilsClkDivT) c.Uint32T { + return 0 +} + +/** + * @brief Calculate the clock division without fractal part + * + * @param[in] clk_info The clock information + * @param[out] int_div The clock integral division + * @return + * - 0: Failed to get the result because the division is out of range, + * but parameter `int_div` will still be assigned to min/max division that given in `clk_info`, + * in case the caller still want to use the min/max division in this case. + * - others: The real output clock frequency + */ +// llgo:link (*HalUtilsClkInfoT).HalUtilsCalcClkDivInteger C.hal_utils_calc_clk_div_integer +func (recv_ *HalUtilsClkInfoT) HalUtilsCalcClkDivInteger(int_div *c.Uint32T) c.Uint32T { + return 0 +} + +/** + * @brief Fixed-point data configuration + * + */ + +type HalUtilsFixedPointT struct { + IntBit c.Uint32T + FracBit c.Uint32T + Saturation bool +} + +/** + * @brief Convert the float type to fixed point type + * @note The supported data format: + * - [input] float (IEEE 754): + * sign(1bit) + exponent(8bit) + mantissa(23bit) (32 bit in total) + * - [output] fixed-point: + * sign(1bit) + integer(int_bit) + fraction(frac_bit) (less or equal to 32 bit) + * + * @param[in] flt IEEE 754 float type data + * @param[in] fp_cfg Fixed-point data configuration + * @param[out] fp_out The output fixed-point data + * @return + * 0: Success + * -1: Fixed point data overflow, `fp_out` will still be assigned + * -2: Float is NaN + * -3: Invalid configuration + */ +//go:linkname HalUtilsFloatToFixedPoint32b C.hal_utils_float_to_fixed_point_32b +func HalUtilsFloatToFixedPoint32b(flt c.Float, fp_cfg *HalUtilsFixedPointT, fp_out *c.Uint32T) c.Int diff --git a/esp32/heap_memory_layout.go b/esp32/heap_memory_layout.go new file mode 100644 index 00000000..babc179e --- /dev/null +++ b/esp32/heap_memory_layout.go @@ -0,0 +1,73 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const SOC_MEMORY_TYPE_NO_PRIOS = 3 + +/* Type descriptor holds a description for a particular type of memory on a particular SoC. + */ + +type SocMemoryTypeDescT struct { + Name *c.Char + Caps [3]c.Uint32T +} + +/* Region descriptor holds a description for a particular region of memory on a particular SoC. + */ + +type SocMemoryRegionT struct { + Start c.IntptrT + Size c.SizeT + Type c.SizeT + IramAddress c.IntptrT + StartupStack bool +} + +/* +Region descriptor holds a description for a particular region of + + memory reserved on this SoC for a particular use (ie not available + for stack/heap usage.) +*/ +type SocReservedRegionT struct { + Start c.IntptrT + End c.IntptrT +} + +/* Return available memory regions for this SoC. Each available memory + * region is a contiguous piece of memory which is not being used by + * static data, used by ROM code, or reserved by a component using + * the SOC_RESERVE_MEMORY_REGION() macro. + * + * This result is soc_memory_regions[] minus all regions reserved + * via the SOC_RESERVE_MEMORY_REGION() macro (which may also split + * some regions up.) + * + * At startup, all available memory returned by this function is + * registered as heap space. + * + * @note OS-level startup function only, not recommended to call from + * app code. + * + * @param regions Pointer to an array for reading available regions into. + * Size of the array should be at least the result of + * soc_get_available_memory_region_max_count(). Entries in the array + * will be ordered by memory address. + * + * @return Number of entries copied to 'regions'. Will be no greater than + * the result of soc_get_available_memory_region_max_count(). + */ +// llgo:link (*SocMemoryRegionT).SocGetAvailableMemoryRegions C.soc_get_available_memory_regions +func (recv_ *SocMemoryRegionT) SocGetAvailableMemoryRegions() c.SizeT { + return 0 +} + +/* Return the maximum number of available memory regions which could be + * returned by soc_get_available_memory_regions(). Used to size the + * array passed to that function. + */ +//go:linkname SocGetAvailableMemoryRegionMaxCount C.soc_get_available_memory_region_max_count +func SocGetAvailableMemoryRegionMaxCount() c.SizeT diff --git a/esp32/hinf_reg.go b/esp32/hinf_reg.go new file mode 100644 index 00000000..4d3b870d --- /dev/null +++ b/esp32/hinf_reg.go @@ -0,0 +1,88 @@ +package freertos + +import _ "unsafe" + +const HINF_DEVICE_ID_FN1 = 0x0000FFFF +const HINF_DEVICE_ID_FN1_V = 0xFFFF +const HINF_DEVICE_ID_FN1_S = 16 +const HINF_USER_ID_FN1 = 0x0000FFFF +const HINF_USER_ID_FN1_V = 0xFFFF +const HINF_USER_ID_FN1_S = 0 +const HINF_SDIO20_CONF1 = 0x00000007 +const HINF_SDIO20_CONF1_V = 0x7 +const HINF_SDIO20_CONF1_S = 29 +const HINF_FUNC2_EPS_V = 0x1 +const HINF_FUNC2_EPS_S = 28 +const HINF_SDIO_VER = 0x00000FFF +const HINF_SDIO_VER_V = 0xFFF +const HINF_SDIO_VER_S = 16 +const HINF_SDIO20_CONF0 = 0x0000000F +const HINF_SDIO20_CONF0_V = 0xF +const HINF_SDIO20_CONF0_S = 12 +const HINF_IOENABLE1_V = 0x1 +const HINF_IOENABLE1_S = 11 +const HINF_EMP_V = 0x1 +const HINF_EMP_S = 10 +const HINF_FUNC1_EPS_V = 0x1 +const HINF_FUNC1_EPS_S = 9 +const HINF_CD_DISABLE_V = 0x1 +const HINF_CD_DISABLE_S = 8 +const HINF_IOENABLE2_V = 0x1 +const HINF_IOENABLE2_S = 7 +const HINF_SDIO_INT_MASK_V = 0x1 +const HINF_SDIO_INT_MASK_S = 6 +const HINF_SDIO_IOREADY2_V = 0x1 +const HINF_SDIO_IOREADY2_S = 5 +const HINF_SDIO_CD_ENABLE_V = 0x1 +const HINF_SDIO_CD_ENABLE_S = 4 +const HINF_HIGHSPEED_MODE_V = 0x1 +const HINF_HIGHSPEED_MODE_S = 3 +const HINF_HIGHSPEED_ENABLE_V = 0x1 +const HINF_HIGHSPEED_ENABLE_S = 2 +const HINF_SDIO_IOREADY1_V = 0x1 +const HINF_SDIO_IOREADY1_S = 1 +const HINF_SDIO_ENABLE_V = 0x1 +const HINF_SDIO_ENABLE_S = 0 +const HINF_SDIO_IOREADY0_V = 0x1 +const HINF_SDIO_IOREADY0_S = 17 +const HINF_SDIO_RST_V = 0x1 +const HINF_SDIO_RST_S = 16 +const HINF_CHIP_STATE = 0x000000FF +const HINF_CHIP_STATE_V = 0xFF +const HINF_CHIP_STATE_S = 8 +const HINF_PIN_STATE = 0x000000FF +const HINF_PIN_STATE_V = 0xFF +const HINF_PIN_STATE_S = 0 +const HINF_CIS_CONF_W0 = 0xFFFFFFFF +const HINF_CIS_CONF_W0_V = 0xFFFFFFFF +const HINF_CIS_CONF_W0_S = 0 +const HINF_CIS_CONF_W1 = 0xFFFFFFFF +const HINF_CIS_CONF_W1_V = 0xFFFFFFFF +const HINF_CIS_CONF_W1_S = 0 +const HINF_CIS_CONF_W2 = 0xFFFFFFFF +const HINF_CIS_CONF_W2_V = 0xFFFFFFFF +const HINF_CIS_CONF_W2_S = 0 +const HINF_CIS_CONF_W3 = 0xFFFFFFFF +const HINF_CIS_CONF_W3_V = 0xFFFFFFFF +const HINF_CIS_CONF_W3_S = 0 +const HINF_CIS_CONF_W4 = 0xFFFFFFFF +const HINF_CIS_CONF_W4_V = 0xFFFFFFFF +const HINF_CIS_CONF_W4_S = 0 +const HINF_CIS_CONF_W5 = 0xFFFFFFFF +const HINF_CIS_CONF_W5_V = 0xFFFFFFFF +const HINF_CIS_CONF_W5_S = 0 +const HINF_CIS_CONF_W6 = 0xFFFFFFFF +const HINF_CIS_CONF_W6_V = 0xFFFFFFFF +const HINF_CIS_CONF_W6_S = 0 +const HINF_CIS_CONF_W7 = 0xFFFFFFFF +const HINF_CIS_CONF_W7_V = 0xFFFFFFFF +const HINF_CIS_CONF_W7_S = 0 +const HINF_DEVICE_ID_FN2 = 0x0000FFFF +const HINF_DEVICE_ID_FN2_V = 0xFFFF +const HINF_DEVICE_ID_FN2_S = 16 +const HINF_USER_ID_FN2 = 0x0000FFFF +const HINF_USER_ID_FN2_V = 0xFFFF +const HINF_USER_ID_FN2_S = 0 +const HINF_SDIO_DATE = 0xFFFFFFFF +const HINF_SDIO_DATE_V = 0xFFFFFFFF +const HINF_SDIO_DATE_S = 0 diff --git a/esp32/hinf_struct.go b/esp32/hinf_struct.go new file mode 100644 index 00000000..54bc74ec --- /dev/null +++ b/esp32/hinf_struct.go @@ -0,0 +1,82 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type HinfDevS struct { + CfgData0 struct { + Val c.Uint32T + } + CfgData1 struct { + Val c.Uint32T + } + Reserved8 c.Uint32T + ReservedC c.Uint32T + Reserved10 c.Uint32T + Reserved14 c.Uint32T + Reserved18 c.Uint32T + CfgData7 struct { + Val c.Uint32T + } + CisConf0 c.Uint32T + CisConf1 c.Uint32T + CisConf2 c.Uint32T + CisConf3 c.Uint32T + CisConf4 c.Uint32T + CisConf5 c.Uint32T + CisConf6 c.Uint32T + CisConf7 c.Uint32T + CfgData16 struct { + Val c.Uint32T + } + Reserved44 c.Uint32T + Reserved48 c.Uint32T + Reserved4c c.Uint32T + Reserved50 c.Uint32T + Reserved54 c.Uint32T + Reserved58 c.Uint32T + Reserved5c c.Uint32T + Reserved60 c.Uint32T + Reserved64 c.Uint32T + Reserved68 c.Uint32T + Reserved6c c.Uint32T + Reserved70 c.Uint32T + Reserved74 c.Uint32T + Reserved78 c.Uint32T + Reserved7c c.Uint32T + Reserved80 c.Uint32T + Reserved84 c.Uint32T + Reserved88 c.Uint32T + Reserved8c c.Uint32T + Reserved90 c.Uint32T + Reserved94 c.Uint32T + Reserved98 c.Uint32T + Reserved9c c.Uint32T + ReservedA0 c.Uint32T + ReservedA4 c.Uint32T + ReservedA8 c.Uint32T + ReservedAc c.Uint32T + ReservedB0 c.Uint32T + ReservedB4 c.Uint32T + ReservedB8 c.Uint32T + ReservedBc c.Uint32T + ReservedC0 c.Uint32T + ReservedC4 c.Uint32T + ReservedC8 c.Uint32T + ReservedCc c.Uint32T + ReservedD0 c.Uint32T + ReservedD4 c.Uint32T + ReservedD8 c.Uint32T + ReservedDc c.Uint32T + ReservedE0 c.Uint32T + ReservedE4 c.Uint32T + ReservedE8 c.Uint32T + ReservedEc c.Uint32T + ReservedF0 c.Uint32T + ReservedF4 c.Uint32T + ReservedF8 c.Uint32T + Date c.Uint32T +} +type HinfDevT HinfDevS diff --git a/esp32/hmac.go b/esp32/hmac.go new file mode 100644 index 00000000..d74e2495 --- /dev/null +++ b/esp32/hmac.go @@ -0,0 +1,50 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +//go:linkname EtsHmacEnable C.ets_hmac_enable +func EtsHmacEnable() + +//go:linkname EtsHmacDisable C.ets_hmac_disable +func EtsHmacDisable() + +/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP) + to digest a message. +*/ +// llgo:link EtsEfuseBlockT.EtsHmacCalculateMessage C.ets_hmac_calculate_message +func (recv_ EtsEfuseBlockT) EtsHmacCalculateMessage(message c.Pointer, message_len c.SizeT, hmac *c.Uint8T) c.Int { + return 0 +} + +/* Calculate a downstream HMAC message to temporarily enable JTAG, or + to generate a Digital Signature data decryption key. + + - purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE + or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG + + - key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6. + This efuse block must have the corresponding purpose set in "purpose", or + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL. + + The result of this HMAC calculation is only made available "downstream" to the + corresponding hardware module, and cannot be accessed by software. +*/ +// llgo:link EtsEfuseBlockT.EtsHmacCalculateDownstream C.ets_hmac_calculate_downstream +func (recv_ EtsEfuseBlockT) EtsHmacCalculateDownstream(purpose EtsEfusePurposeT) c.Int { + return 0 +} + +/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream(). + * + * - purpose must match a previous call to ets_hmac_calculate_downstream(). + * + * After this function is called, the corresponding internal operation (JTAG or DS) will no longer + * have access to the generated key. + */ +// llgo:link EtsEfusePurposeT.EtsHmacInvalidateDownstream C.ets_hmac_invalidate_downstream +func (recv_ EtsEfusePurposeT) EtsHmacInvalidateDownstream() c.Int { + return 0 +} diff --git a/esp32/hmac_hal.go b/esp32/hmac_hal.go new file mode 100644 index 00000000..d070aa43 --- /dev/null +++ b/esp32/hmac_hal.go @@ -0,0 +1,82 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Make the peripheral ready for use. + * + * This triggers any further steps necessary after enabling the device + */ +//go:linkname HmacHalStart C.hmac_hal_start +func HmacHalStart() + +/** + * @brief Configure which hardware key slot should be used and configure the target of the HMAC output. + * + * @note Writing out-of-range values is undefined behavior. The user has to ensure that the parameters are in range. + * + * @param config The target of the HMAC. Possible targets are described in \c hmac_hal_output_t. + * See the TRM of your target chip for more details. + * @param key_id The ID of the hardware key slot to be used. + * + * @return 0 if the configuration was successful, non-zero if not. + * An unsuccessful configuration means that the purpose value in the eFuse of the corresponding key slot + * doesn't match to supplied value of \c config. + */ +// llgo:link HmacHalOutputT.HmacHalConfigure C.hmac_hal_configure +func (recv_ HmacHalOutputT) HmacHalConfigure(key_id c.Uint32T) c.Uint32T { + return 0 +} + +/** + * @brief Write a padded single-block message of 512 bits to the HMAC peripheral. + * + * The message must not be longer than one block (512 bits) and the padding has to be applied by software before + * writing. The padding has to be able to fit into the block after the message. + * For more information on HMAC padding, see the TRM of your target chip. + */ +//go:linkname HmacHalWriteOneBlock512 C.hmac_hal_write_one_block_512 +func HmacHalWriteOneBlock512(block c.Pointer) + +/** + * @brief Write a message block of 512 bits to the HMAC peripheral. + * + * This function must be used incombination with \c hmac_hal_next_block_normal() or \c hmac_hal_next_block_padding(). + * The first message block is written without any prerequisite. + * All message blocks which are not the last one, need a call to \c hmac_hal_next_block_normal() before, indicating + * to the hardware that a "normal", i.e. non-padded block will follow. This is even the case for a block which begins + * padding already but where the padding doesn't fit in (remaining message size > (block size - padding size)). + * Before writing the last block which contains the padding, a call to \c hmac_hal_next_block_padding() is necessary + * to indicate to the hardware that a block with padding will be written. + * + * For more information on HMAC padding, see the TRM of your target chip for more details. + */ +//go:linkname HmacHalWriteBlock512 C.hmac_hal_write_block_512 +func HmacHalWriteBlock512(block c.Pointer) + +/** + * @brief Indicate to the hardware that a normal block will be written. + */ +//go:linkname HmacHalNextBlockNormal C.hmac_hal_next_block_normal +func HmacHalNextBlockNormal() + +/** + * @brief Indicate to the hardware that a block with padding will be written. + */ +//go:linkname HmacHalNextBlockPadding C.hmac_hal_next_block_padding +func HmacHalNextBlockPadding() + +/** + * @brief Read the 256 bit HMAC result from the hardware. + */ +//go:linkname HmacHalReadResult256 C.hmac_hal_read_result_256 +func HmacHalReadResult256(result c.Pointer) + +/** + * @brief Clear (invalidate) the HMAC result provided to other hardware. + */ +//go:linkname HmacHalClean C.hmac_hal_clean +func HmacHalClean() diff --git a/esp32/hmac_ll.go b/esp32/hmac_ll.go new file mode 100644 index 00000000..76e35759 --- /dev/null +++ b/esp32/hmac_ll.go @@ -0,0 +1,10 @@ +package freertos + +import _ "unsafe" + +const SHA256_BLOCK_SZ = 64 +const SHA256_DIGEST_SZ = 32 +const HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_JTAG = 6 +const HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_DIGITAL_SIGNATURE = 7 +const HMAC_LL_EFUSE_KEY_PURPOSE_UP = 8 +const HMAC_LL_EFUSE_KEY_PURPOSE_DOWN_ALL = 5 diff --git a/esp32/hmac_types.go b/esp32/hmac_types.go new file mode 100644 index 00000000..5f19b9f9 --- /dev/null +++ b/esp32/hmac_types.go @@ -0,0 +1,15 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type HmacHalOutputT c.Int + +const ( + HMAC_OUTPUT_USER HmacHalOutputT = 0 + HMAC_OUTPUT_DS HmacHalOutputT = 1 + HMAC_OUTPUT_JTAG_ENABLE HmacHalOutputT = 2 + HMAC_OUTPUT_ALL HmacHalOutputT = 3 +) diff --git a/esp32/host_reg.go b/esp32/host_reg.go new file mode 100644 index 00000000..4b4b941f --- /dev/null +++ b/esp32/host_reg.go @@ -0,0 +1,672 @@ +package freertos + +import _ "unsafe" + +const HOST_SLC_FUNC1_MDSTAT_V = 0x1 +const HOST_SLC_FUNC1_MDSTAT_S = 0 +const HOST_GPIO_SDIO_INT0 = 0xFFFFFFFF +const HOST_GPIO_SDIO_INT0_V = 0xFFFFFFFF +const HOST_GPIO_SDIO_INT0_S = 0 +const HOST_GPIO_SDIO_INT1 = 0x003FFFFF +const HOST_GPIO_SDIO_INT1_V = 0x3FFFFF +const HOST_GPIO_SDIO_INT1_S = 0 +const HOST_GPIO_SDIO_IN0 = 0xFFFFFFFF +const HOST_GPIO_SDIO_IN0_V = 0xFFFFFFFF +const HOST_GPIO_SDIO_IN0_S = 0 +const HOST_GPIO_SDIO_IN1 = 0x003FFFFF +const HOST_GPIO_SDIO_IN1_V = 0x3FFFFF +const HOST_GPIO_SDIO_IN1_S = 0 +const HOST_SLC0_RX_PF_EOF = 0x0000000F +const HOST_SLC0_RX_PF_EOF_V = 0xF +const HOST_SLC0_RX_PF_EOF_S = 28 +const HOST_HOSTSLC0_TOKEN1 = 0x00000FFF +const HOST_HOSTSLC0_TOKEN1_V = 0xFFF +const HOST_HOSTSLC0_TOKEN1_S = 16 +const HOST_SLC0_RX_PF_VALID_V = 0x1 +const HOST_SLC0_RX_PF_VALID_S = 12 +const HOST_SLC0_TOKEN0 = 0x00000FFF +const HOST_SLC0_TOKEN0_V = 0xFFF +const HOST_SLC0_TOKEN0_S = 0 +const HOST_SLC0_PF_DATA = 0xFFFFFFFF +const HOST_SLC0_PF_DATA_V = 0xFFFFFFFF +const HOST_SLC0_PF_DATA_S = 0 +const HOST_GPIO_SDIO_INT_RAW_V = 0x1 +const HOST_GPIO_SDIO_INT_RAW_S = 25 +const HOST_SLC0_HOST_RD_RETRY_INT_RAW_V = 0x1 +const HOST_SLC0_HOST_RD_RETRY_INT_RAW_S = 24 +const HOST_SLC0_RX_NEW_PACKET_INT_RAW_V = 0x1 +const HOST_SLC0_RX_NEW_PACKET_INT_RAW_S = 23 +const HOST_SLC0_EXT_BIT3_INT_RAW_V = 0x1 +const HOST_SLC0_EXT_BIT3_INT_RAW_S = 22 +const HOST_SLC0_EXT_BIT2_INT_RAW_V = 0x1 +const HOST_SLC0_EXT_BIT2_INT_RAW_S = 21 +const HOST_SLC0_EXT_BIT1_INT_RAW_V = 0x1 +const HOST_SLC0_EXT_BIT1_INT_RAW_S = 20 +const HOST_SLC0_EXT_BIT0_INT_RAW_V = 0x1 +const HOST_SLC0_EXT_BIT0_INT_RAW_S = 19 +const HOST_SLC0_RX_PF_VALID_INT_RAW_V = 0x1 +const HOST_SLC0_RX_PF_VALID_INT_RAW_S = 18 +const HOST_SLC0_TX_OVF_INT_RAW_V = 0x1 +const HOST_SLC0_TX_OVF_INT_RAW_S = 17 +const HOST_SLC0_RX_UDF_INT_RAW_V = 0x1 +const HOST_SLC0_RX_UDF_INT_RAW_S = 16 +const HOST_SLC0HOST_TX_START_INT_RAW_V = 0x1 +const HOST_SLC0HOST_TX_START_INT_RAW_S = 15 +const HOST_SLC0HOST_RX_START_INT_RAW_V = 0x1 +const HOST_SLC0HOST_RX_START_INT_RAW_S = 14 +const HOST_SLC0HOST_RX_EOF_INT_RAW_V = 0x1 +const HOST_SLC0HOST_RX_EOF_INT_RAW_S = 13 +const HOST_SLC0HOST_RX_SOF_INT_RAW_V = 0x1 +const HOST_SLC0HOST_RX_SOF_INT_RAW_S = 12 +const HOST_SLC0_TOKEN1_0TO1_INT_RAW_V = 0x1 +const HOST_SLC0_TOKEN1_0TO1_INT_RAW_S = 11 +const HOST_SLC0_TOKEN0_0TO1_INT_RAW_V = 0x1 +const HOST_SLC0_TOKEN0_0TO1_INT_RAW_S = 10 +const HOST_SLC0_TOKEN1_1TO0_INT_RAW_V = 0x1 +const HOST_SLC0_TOKEN1_1TO0_INT_RAW_S = 9 +const HOST_SLC0_TOKEN0_1TO0_INT_RAW_V = 0x1 +const HOST_SLC0_TOKEN0_1TO0_INT_RAW_S = 8 +const HOST_SLC0_TOHOST_BIT7_INT_RAW_V = 0x1 +const HOST_SLC0_TOHOST_BIT7_INT_RAW_S = 7 +const HOST_SLC0_TOHOST_BIT6_INT_RAW_V = 0x1 +const HOST_SLC0_TOHOST_BIT6_INT_RAW_S = 6 +const HOST_SLC0_TOHOST_BIT5_INT_RAW_V = 0x1 +const HOST_SLC0_TOHOST_BIT5_INT_RAW_S = 5 +const HOST_SLC0_TOHOST_BIT4_INT_RAW_V = 0x1 +const HOST_SLC0_TOHOST_BIT4_INT_RAW_S = 4 +const HOST_SLC0_TOHOST_BIT3_INT_RAW_V = 0x1 +const HOST_SLC0_TOHOST_BIT3_INT_RAW_S = 3 +const HOST_SLC0_TOHOST_BIT2_INT_RAW_V = 0x1 +const HOST_SLC0_TOHOST_BIT2_INT_RAW_S = 2 +const HOST_SLC0_TOHOST_BIT1_INT_RAW_V = 0x1 +const HOST_SLC0_TOHOST_BIT1_INT_RAW_S = 1 +const HOST_SLC0_TOHOST_BIT0_INT_RAW_V = 0x1 +const HOST_SLC0_TOHOST_BIT0_INT_RAW_S = 0 +const HOST_GPIO_SDIO_INT_ST_V = 0x1 +const HOST_GPIO_SDIO_INT_ST_S = 25 +const HOST_SLC0_HOST_RD_RETRY_INT_ST_V = 0x1 +const HOST_SLC0_HOST_RD_RETRY_INT_ST_S = 24 +const HOST_SLC0_RX_NEW_PACKET_INT_ST_V = 0x1 +const HOST_SLC0_RX_NEW_PACKET_INT_ST_S = 23 +const HOST_SLC0_EXT_BIT3_INT_ST_V = 0x1 +const HOST_SLC0_EXT_BIT3_INT_ST_S = 22 +const HOST_SLC0_EXT_BIT2_INT_ST_V = 0x1 +const HOST_SLC0_EXT_BIT2_INT_ST_S = 21 +const HOST_SLC0_EXT_BIT1_INT_ST_V = 0x1 +const HOST_SLC0_EXT_BIT1_INT_ST_S = 20 +const HOST_SLC0_EXT_BIT0_INT_ST_V = 0x1 +const HOST_SLC0_EXT_BIT0_INT_ST_S = 19 +const HOST_SLC0_RX_PF_VALID_INT_ST_V = 0x1 +const HOST_SLC0_RX_PF_VALID_INT_ST_S = 18 +const HOST_SLC0_TX_OVF_INT_ST_V = 0x1 +const HOST_SLC0_TX_OVF_INT_ST_S = 17 +const HOST_SLC0_RX_UDF_INT_ST_V = 0x1 +const HOST_SLC0_RX_UDF_INT_ST_S = 16 +const HOST_SLC0HOST_TX_START_INT_ST_V = 0x1 +const HOST_SLC0HOST_TX_START_INT_ST_S = 15 +const HOST_SLC0HOST_RX_START_INT_ST_V = 0x1 +const HOST_SLC0HOST_RX_START_INT_ST_S = 14 +const HOST_SLC0HOST_RX_EOF_INT_ST_V = 0x1 +const HOST_SLC0HOST_RX_EOF_INT_ST_S = 13 +const HOST_SLC0HOST_RX_SOF_INT_ST_V = 0x1 +const HOST_SLC0HOST_RX_SOF_INT_ST_S = 12 +const HOST_SLC0_TOKEN1_0TO1_INT_ST_V = 0x1 +const HOST_SLC0_TOKEN1_0TO1_INT_ST_S = 11 +const HOST_SLC0_TOKEN0_0TO1_INT_ST_V = 0x1 +const HOST_SLC0_TOKEN0_0TO1_INT_ST_S = 10 +const HOST_SLC0_TOKEN1_1TO0_INT_ST_V = 0x1 +const HOST_SLC0_TOKEN1_1TO0_INT_ST_S = 9 +const HOST_SLC0_TOKEN0_1TO0_INT_ST_V = 0x1 +const HOST_SLC0_TOKEN0_1TO0_INT_ST_S = 8 +const HOST_SLC0_TOHOST_BIT7_INT_ST_V = 0x1 +const HOST_SLC0_TOHOST_BIT7_INT_ST_S = 7 +const HOST_SLC0_TOHOST_BIT6_INT_ST_V = 0x1 +const HOST_SLC0_TOHOST_BIT6_INT_ST_S = 6 +const HOST_SLC0_TOHOST_BIT5_INT_ST_V = 0x1 +const HOST_SLC0_TOHOST_BIT5_INT_ST_S = 5 +const HOST_SLC0_TOHOST_BIT4_INT_ST_V = 0x1 +const HOST_SLC0_TOHOST_BIT4_INT_ST_S = 4 +const HOST_SLC0_TOHOST_BIT3_INT_ST_V = 0x1 +const HOST_SLC0_TOHOST_BIT3_INT_ST_S = 3 +const HOST_SLC0_TOHOST_BIT2_INT_ST_V = 0x1 +const HOST_SLC0_TOHOST_BIT2_INT_ST_S = 2 +const HOST_SLC0_TOHOST_BIT1_INT_ST_V = 0x1 +const HOST_SLC0_TOHOST_BIT1_INT_ST_S = 1 +const HOST_SLC0_TOHOST_BIT0_INT_ST_V = 0x1 +const HOST_SLC0_TOHOST_BIT0_INT_ST_S = 0 +const HOST_HOSTSLC0_LEN_CHECK = 0x00000FFF +const HOST_HOSTSLC0_LEN_CHECK_V = 0xFFF +const HOST_HOSTSLC0_LEN_CHECK_S = 20 +const HOST_HOSTSLC0_LEN = 0x000FFFFF +const HOST_HOSTSLC0_LEN_V = 0xFFFFF +const HOST_HOSTSLC0_LEN_S = 0 +const HOST_SLCHOST_STATE3 = 0x000000FF +const HOST_SLCHOST_STATE3_V = 0xFF +const HOST_SLCHOST_STATE3_S = 24 +const HOST_SLCHOST_STATE2 = 0x000000FF +const HOST_SLCHOST_STATE2_V = 0xFF +const HOST_SLCHOST_STATE2_S = 16 +const HOST_SLCHOST_STATE1 = 0x000000FF +const HOST_SLCHOST_STATE1_V = 0xFF +const HOST_SLCHOST_STATE1_S = 8 +const HOST_SLCHOST_STATE0 = 0x000000FF +const HOST_SLCHOST_STATE0_V = 0xFF +const HOST_SLCHOST_STATE0_S = 0 +const HOST_SLCHOST_STATE7 = 0x000000FF +const HOST_SLCHOST_STATE7_V = 0xFF +const HOST_SLCHOST_STATE7_S = 24 +const HOST_SLCHOST_STATE6 = 0x000000FF +const HOST_SLCHOST_STATE6_V = 0xFF +const HOST_SLCHOST_STATE6_S = 16 +const HOST_SLCHOST_STATE5 = 0x000000FF +const HOST_SLCHOST_STATE5_V = 0xFF +const HOST_SLCHOST_STATE5_S = 8 +const HOST_SLCHOST_STATE4 = 0x000000FF +const HOST_SLCHOST_STATE4_V = 0xFF +const HOST_SLCHOST_STATE4_S = 0 +const HOST_SLCHOST_CONF3 = 0x000000FF +const HOST_SLCHOST_CONF3_V = 0xFF +const HOST_SLCHOST_CONF3_S = 24 +const HOST_SLCHOST_CONF2 = 0x000000FF +const HOST_SLCHOST_CONF2_V = 0xFF +const HOST_SLCHOST_CONF2_S = 16 +const HOST_SLCHOST_CONF1 = 0x000000FF +const HOST_SLCHOST_CONF1_V = 0xFF +const HOST_SLCHOST_CONF1_S = 8 +const HOST_SLCHOST_CONF0 = 0x000000FF +const HOST_SLCHOST_CONF0_V = 0xFF +const HOST_SLCHOST_CONF0_S = 0 +const HOST_SLCHOST_CONF7 = 0x000000FF +const HOST_SLCHOST_CONF7_V = 0xFF +const HOST_SLCHOST_CONF7_S = 24 +const HOST_SLCHOST_CONF6 = 0x000000FF +const HOST_SLCHOST_CONF6_V = 0xFF +const HOST_SLCHOST_CONF6_S = 16 +const HOST_SLCHOST_CONF5 = 0x000000FF +const HOST_SLCHOST_CONF5_V = 0xFF +const HOST_SLCHOST_CONF5_S = 8 +const HOST_SLCHOST_CONF4 = 0x000000FF +const HOST_SLCHOST_CONF4_V = 0xFF +const HOST_SLCHOST_CONF4_S = 0 +const HOST_SLCHOST_CONF11 = 0x000000FF +const HOST_SLCHOST_CONF11_V = 0xFF +const HOST_SLCHOST_CONF11_S = 24 +const HOST_SLCHOST_CONF10 = 0x000000FF +const HOST_SLCHOST_CONF10_V = 0xFF +const HOST_SLCHOST_CONF10_S = 16 +const HOST_SLCHOST_CONF9 = 0x000000FF +const HOST_SLCHOST_CONF9_V = 0xFF +const HOST_SLCHOST_CONF9_S = 8 +const HOST_SLCHOST_CONF8 = 0x000000FF +const HOST_SLCHOST_CONF8_V = 0xFF +const HOST_SLCHOST_CONF8_S = 0 +const HOST_SLCHOST_CONF15 = 0x000000FF +const HOST_SLCHOST_CONF15_V = 0xFF +const HOST_SLCHOST_CONF15_S = 24 +const HOST_SLCHOST_CONF14 = 0x000000FF +const HOST_SLCHOST_CONF14_V = 0xFF +const HOST_SLCHOST_CONF14_S = 16 +const HOST_SLCHOST_CONF13 = 0x000000FF +const HOST_SLCHOST_CONF13_V = 0xFF +const HOST_SLCHOST_CONF13_S = 8 +const HOST_SLCHOST_CONF12 = 0x000000FF +const HOST_SLCHOST_CONF12_V = 0xFF +const HOST_SLCHOST_CONF12_S = 0 +const HOST_SLCHOST_CONF19 = 0x000000FF +const HOST_SLCHOST_CONF19_V = 0xFF +const HOST_SLCHOST_CONF19_S = 24 +const HOST_SLCHOST_CONF18 = 0x000000FF +const HOST_SLCHOST_CONF18_V = 0xFF +const HOST_SLCHOST_CONF18_S = 16 +const HOST_SLCHOST_CONF17 = 0x000000FF +const HOST_SLCHOST_CONF17_V = 0xFF +const HOST_SLCHOST_CONF17_S = 8 +const HOST_SLCHOST_CONF16 = 0x000000FF +const HOST_SLCHOST_CONF16_V = 0xFF +const HOST_SLCHOST_CONF16_S = 0 +const HOST_SLCHOST_CONF23 = 0x000000FF +const HOST_SLCHOST_CONF23_V = 0xFF +const HOST_SLCHOST_CONF23_S = 24 +const HOST_SLCHOST_CONF22 = 0x000000FF +const HOST_SLCHOST_CONF22_V = 0xFF +const HOST_SLCHOST_CONF22_S = 16 +const HOST_SLCHOST_CONF21 = 0x000000FF +const HOST_SLCHOST_CONF21_V = 0xFF +const HOST_SLCHOST_CONF21_S = 8 +const HOST_SLCHOST_CONF20 = 0x000000FF +const HOST_SLCHOST_CONF20_V = 0xFF +const HOST_SLCHOST_CONF20_S = 0 +const HOST_SLCHOST_WIN_CMD = 0x0000FFFF +const HOST_SLCHOST_WIN_CMD_V = 0xFFFF +const HOST_SLCHOST_WIN_CMD_S = 0 +const HOST_SLCHOST_CONF27 = 0x000000FF +const HOST_SLCHOST_CONF27_V = 0xFF +const HOST_SLCHOST_CONF27_S = 24 +const HOST_SLCHOST_CONF26 = 0x000000FF +const HOST_SLCHOST_CONF26_V = 0xFF +const HOST_SLCHOST_CONF26_S = 16 +const HOST_SLCHOST_CONF25 = 0x000000FF +const HOST_SLCHOST_CONF25_V = 0xFF +const HOST_SLCHOST_CONF25_S = 8 +const HOST_SLCHOST_CONF24 = 0x000000FF +const HOST_SLCHOST_CONF24_V = 0xFF +const HOST_SLCHOST_CONF24_S = 0 +const HOST_SLCHOST_CONF31 = 0x000000FF +const HOST_SLCHOST_CONF31_V = 0xFF +const HOST_SLCHOST_CONF31_S = 24 +const HOST_SLCHOST_CONF30 = 0x000000FF +const HOST_SLCHOST_CONF30_V = 0xFF +const HOST_SLCHOST_CONF30_S = 16 +const HOST_SLCHOST_CONF29 = 0x000000FF +const HOST_SLCHOST_CONF29_V = 0xFF +const HOST_SLCHOST_CONF29_S = 8 +const HOST_SLCHOST_CONF28 = 0x000000FF +const HOST_SLCHOST_CONF28_V = 0xFF +const HOST_SLCHOST_CONF28_S = 0 +const HOST_HOSTSLC0_LEN0_CHECK = 0x00000FFF +const HOST_HOSTSLC0_LEN0_CHECK_V = 0xFFF +const HOST_HOSTSLC0_LEN0_CHECK_S = 20 +const HOST_HOSTSLC0_LEN0 = 0x000FFFFF +const HOST_HOSTSLC0_LEN0_V = 0xFFFFF +const HOST_HOSTSLC0_LEN0_S = 0 +const HOST_HOSTSLC0_LEN1_CHECK = 0x00000FFF +const HOST_HOSTSLC0_LEN1_CHECK_V = 0xFFF +const HOST_HOSTSLC0_LEN1_CHECK_S = 20 +const HOST_HOSTSLC0_LEN1 = 0x000FFFFF +const HOST_HOSTSLC0_LEN1_V = 0xFFFFF +const HOST_HOSTSLC0_LEN1_S = 0 +const HOST_HOSTSLC0_LEN2_CHECK = 0x00000FFF +const HOST_HOSTSLC0_LEN2_CHECK_V = 0xFFF +const HOST_HOSTSLC0_LEN2_CHECK_S = 20 +const HOST_HOSTSLC0_LEN2 = 0x000FFFFF +const HOST_HOSTSLC0_LEN2_V = 0xFFFFF +const HOST_HOSTSLC0_LEN2_S = 0 +const HOST_SLCHOST_CONF35 = 0x000000FF +const HOST_SLCHOST_CONF35_V = 0xFF +const HOST_SLCHOST_CONF35_S = 24 +const HOST_SLCHOST_CONF34 = 0x000000FF +const HOST_SLCHOST_CONF34_V = 0xFF +const HOST_SLCHOST_CONF34_S = 16 +const HOST_SLCHOST_CONF33 = 0x000000FF +const HOST_SLCHOST_CONF33_V = 0xFF +const HOST_SLCHOST_CONF33_S = 8 +const HOST_SLCHOST_CONF32 = 0x000000FF +const HOST_SLCHOST_CONF32_V = 0xFF +const HOST_SLCHOST_CONF32_S = 0 +const HOST_SLCHOST_CONF39 = 0x000000FF +const HOST_SLCHOST_CONF39_V = 0xFF +const HOST_SLCHOST_CONF39_S = 24 +const HOST_SLCHOST_CONF38 = 0x000000FF +const HOST_SLCHOST_CONF38_V = 0xFF +const HOST_SLCHOST_CONF38_S = 16 +const HOST_SLCHOST_CONF37 = 0x000000FF +const HOST_SLCHOST_CONF37_V = 0xFF +const HOST_SLCHOST_CONF37_S = 8 +const HOST_SLCHOST_CONF36 = 0x000000FF +const HOST_SLCHOST_CONF36_V = 0xFF +const HOST_SLCHOST_CONF36_S = 0 +const HOST_SLCHOST_CONF43 = 0x000000FF +const HOST_SLCHOST_CONF43_V = 0xFF +const HOST_SLCHOST_CONF43_S = 24 +const HOST_SLCHOST_CONF42 = 0x000000FF +const HOST_SLCHOST_CONF42_V = 0xFF +const HOST_SLCHOST_CONF42_S = 16 +const HOST_SLCHOST_CONF41 = 0x000000FF +const HOST_SLCHOST_CONF41_V = 0xFF +const HOST_SLCHOST_CONF41_S = 8 +const HOST_SLCHOST_CONF40 = 0x000000FF +const HOST_SLCHOST_CONF40_V = 0xFF +const HOST_SLCHOST_CONF40_S = 0 +const HOST_SLCHOST_CONF47 = 0x000000FF +const HOST_SLCHOST_CONF47_V = 0xFF +const HOST_SLCHOST_CONF47_S = 24 +const HOST_SLCHOST_CONF46 = 0x000000FF +const HOST_SLCHOST_CONF46_V = 0xFF +const HOST_SLCHOST_CONF46_S = 16 +const HOST_SLCHOST_CONF45 = 0x000000FF +const HOST_SLCHOST_CONF45_V = 0xFF +const HOST_SLCHOST_CONF45_S = 8 +const HOST_SLCHOST_CONF44 = 0x000000FF +const HOST_SLCHOST_CONF44_V = 0xFF +const HOST_SLCHOST_CONF44_S = 0 +const HOST_SLCHOST_CONF51 = 0x000000FF +const HOST_SLCHOST_CONF51_V = 0xFF +const HOST_SLCHOST_CONF51_S = 24 +const HOST_SLCHOST_CONF50 = 0x000000FF +const HOST_SLCHOST_CONF50_V = 0xFF +const HOST_SLCHOST_CONF50_S = 16 +const HOST_SLCHOST_CONF49 = 0x000000FF +const HOST_SLCHOST_CONF49_V = 0xFF +const HOST_SLCHOST_CONF49_S = 8 +const HOST_SLCHOST_CONF48 = 0x000000FF +const HOST_SLCHOST_CONF48_V = 0xFF +const HOST_SLCHOST_CONF48_S = 0 +const HOST_SLCHOST_CONF55 = 0x000000FF +const HOST_SLCHOST_CONF55_V = 0xFF +const HOST_SLCHOST_CONF55_S = 24 +const HOST_SLCHOST_CONF54 = 0x000000FF +const HOST_SLCHOST_CONF54_V = 0xFF +const HOST_SLCHOST_CONF54_S = 16 +const HOST_SLCHOST_CONF53 = 0x000000FF +const HOST_SLCHOST_CONF53_V = 0xFF +const HOST_SLCHOST_CONF53_S = 8 +const HOST_SLCHOST_CONF52 = 0x000000FF +const HOST_SLCHOST_CONF52_V = 0xFF +const HOST_SLCHOST_CONF52_S = 0 +const HOST_SLCHOST_CONF59 = 0x000000FF +const HOST_SLCHOST_CONF59_V = 0xFF +const HOST_SLCHOST_CONF59_S = 24 +const HOST_SLCHOST_CONF58 = 0x000000FF +const HOST_SLCHOST_CONF58_V = 0xFF +const HOST_SLCHOST_CONF58_S = 16 +const HOST_SLCHOST_CONF57 = 0x000000FF +const HOST_SLCHOST_CONF57_V = 0xFF +const HOST_SLCHOST_CONF57_S = 8 +const HOST_SLCHOST_CONF56 = 0x000000FF +const HOST_SLCHOST_CONF56_V = 0xFF +const HOST_SLCHOST_CONF56_S = 0 +const HOST_SLCHOST_CONF63 = 0x000000FF +const HOST_SLCHOST_CONF63_V = 0xFF +const HOST_SLCHOST_CONF63_S = 24 +const HOST_SLCHOST_CONF62 = 0x000000FF +const HOST_SLCHOST_CONF62_V = 0xFF +const HOST_SLCHOST_CONF62_S = 16 +const HOST_SLCHOST_CONF61 = 0x000000FF +const HOST_SLCHOST_CONF61_V = 0xFF +const HOST_SLCHOST_CONF61_S = 8 +const HOST_SLCHOST_CONF60 = 0x000000FF +const HOST_SLCHOST_CONF60_V = 0xFF +const HOST_SLCHOST_CONF60_S = 0 +const HOST_SLCHOST_CHECK_SUM0 = 0xFFFFFFFF +const HOST_SLCHOST_CHECK_SUM0_V = 0xFFFFFFFF +const HOST_SLCHOST_CHECK_SUM0_S = 0 +const HOST_SLCHOST_CHECK_SUM1 = 0xFFFFFFFF +const HOST_SLCHOST_CHECK_SUM1_V = 0xFFFFFFFF +const HOST_SLCHOST_CHECK_SUM1_S = 0 +const HOST_SLC0HOST_TOKEN1_WD = 0x00000FFF +const HOST_SLC0HOST_TOKEN1_WD_V = 0xFFF +const HOST_SLC0HOST_TOKEN1_WD_S = 16 +const HOST_SLC0HOST_TOKEN0_WD = 0x00000FFF +const HOST_SLC0HOST_TOKEN0_WD_V = 0xFFF +const HOST_SLC0HOST_TOKEN0_WD_S = 0 +const HOST_SLC0HOST_LEN_WR_V = 0x1 +const HOST_SLC0HOST_LEN_WR_S = 8 +const HOST_SLC0HOST_TOKEN1_WR_V = 0x1 +const HOST_SLC0HOST_TOKEN1_WR_S = 3 +const HOST_SLC0HOST_TOKEN0_WR_V = 0x1 +const HOST_SLC0HOST_TOKEN0_WR_S = 2 +const HOST_SLC0HOST_TOKEN1_DEC_V = 0x1 +const HOST_SLC0HOST_TOKEN1_DEC_S = 1 +const HOST_SLC0HOST_TOKEN0_DEC_V = 0x1 +const HOST_SLC0HOST_TOKEN0_DEC_S = 0 +const HOST_GPIO_SDIO_INT_CLR_V = 0x1 +const HOST_GPIO_SDIO_INT_CLR_S = 25 +const HOST_SLC0_HOST_RD_RETRY_INT_CLR_V = 0x1 +const HOST_SLC0_HOST_RD_RETRY_INT_CLR_S = 24 +const HOST_SLC0_RX_NEW_PACKET_INT_CLR_V = 0x1 +const HOST_SLC0_RX_NEW_PACKET_INT_CLR_S = 23 +const HOST_SLC0_EXT_BIT3_INT_CLR_V = 0x1 +const HOST_SLC0_EXT_BIT3_INT_CLR_S = 22 +const HOST_SLC0_EXT_BIT2_INT_CLR_V = 0x1 +const HOST_SLC0_EXT_BIT2_INT_CLR_S = 21 +const HOST_SLC0_EXT_BIT1_INT_CLR_V = 0x1 +const HOST_SLC0_EXT_BIT1_INT_CLR_S = 20 +const HOST_SLC0_EXT_BIT0_INT_CLR_V = 0x1 +const HOST_SLC0_EXT_BIT0_INT_CLR_S = 19 +const HOST_SLC0_RX_PF_VALID_INT_CLR_V = 0x1 +const HOST_SLC0_RX_PF_VALID_INT_CLR_S = 18 +const HOST_SLC0_TX_OVF_INT_CLR_V = 0x1 +const HOST_SLC0_TX_OVF_INT_CLR_S = 17 +const HOST_SLC0_RX_UDF_INT_CLR_V = 0x1 +const HOST_SLC0_RX_UDF_INT_CLR_S = 16 +const HOST_SLC0HOST_TX_START_INT_CLR_V = 0x1 +const HOST_SLC0HOST_TX_START_INT_CLR_S = 15 +const HOST_SLC0HOST_RX_START_INT_CLR_V = 0x1 +const HOST_SLC0HOST_RX_START_INT_CLR_S = 14 +const HOST_SLC0HOST_RX_EOF_INT_CLR_V = 0x1 +const HOST_SLC0HOST_RX_EOF_INT_CLR_S = 13 +const HOST_SLC0HOST_RX_SOF_INT_CLR_V = 0x1 +const HOST_SLC0HOST_RX_SOF_INT_CLR_S = 12 +const HOST_SLC0_TOKEN1_0TO1_INT_CLR_V = 0x1 +const HOST_SLC0_TOKEN1_0TO1_INT_CLR_S = 11 +const HOST_SLC0_TOKEN0_0TO1_INT_CLR_V = 0x1 +const HOST_SLC0_TOKEN0_0TO1_INT_CLR_S = 10 +const HOST_SLC0_TOKEN1_1TO0_INT_CLR_V = 0x1 +const HOST_SLC0_TOKEN1_1TO0_INT_CLR_S = 9 +const HOST_SLC0_TOKEN0_1TO0_INT_CLR_V = 0x1 +const HOST_SLC0_TOKEN0_1TO0_INT_CLR_S = 8 +const HOST_SLC0_TOHOST_BIT7_INT_CLR_V = 0x1 +const HOST_SLC0_TOHOST_BIT7_INT_CLR_S = 7 +const HOST_SLC0_TOHOST_BIT6_INT_CLR_V = 0x1 +const HOST_SLC0_TOHOST_BIT6_INT_CLR_S = 6 +const HOST_SLC0_TOHOST_BIT5_INT_CLR_V = 0x1 +const HOST_SLC0_TOHOST_BIT5_INT_CLR_S = 5 +const HOST_SLC0_TOHOST_BIT4_INT_CLR_V = 0x1 +const HOST_SLC0_TOHOST_BIT4_INT_CLR_S = 4 +const HOST_SLC0_TOHOST_BIT3_INT_CLR_V = 0x1 +const HOST_SLC0_TOHOST_BIT3_INT_CLR_S = 3 +const HOST_SLC0_TOHOST_BIT2_INT_CLR_V = 0x1 +const HOST_SLC0_TOHOST_BIT2_INT_CLR_S = 2 +const HOST_SLC0_TOHOST_BIT1_INT_CLR_V = 0x1 +const HOST_SLC0_TOHOST_BIT1_INT_CLR_S = 1 +const HOST_SLC0_TOHOST_BIT0_INT_CLR_V = 0x1 +const HOST_SLC0_TOHOST_BIT0_INT_CLR_S = 0 +const HOST_FN1_GPIO_SDIO_INT_ENA_V = 0x1 +const HOST_FN1_GPIO_SDIO_INT_ENA_S = 25 +const HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S = 24 +const HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S = 23 +const HOST_FN1_SLC0_EXT_BIT3_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_EXT_BIT3_INT_ENA_S = 22 +const HOST_FN1_SLC0_EXT_BIT2_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_EXT_BIT2_INT_ENA_S = 21 +const HOST_FN1_SLC0_EXT_BIT1_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_EXT_BIT1_INT_ENA_S = 20 +const HOST_FN1_SLC0_EXT_BIT0_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_EXT_BIT0_INT_ENA_S = 19 +const HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S = 18 +const HOST_FN1_SLC0_TX_OVF_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_TX_OVF_INT_ENA_S = 17 +const HOST_FN1_SLC0_RX_UDF_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_RX_UDF_INT_ENA_S = 16 +const HOST_FN1_SLC0HOST_TX_START_INT_ENA_V = 0x1 +const HOST_FN1_SLC0HOST_TX_START_INT_ENA_S = 15 +const HOST_FN1_SLC0HOST_RX_START_INT_ENA_V = 0x1 +const HOST_FN1_SLC0HOST_RX_START_INT_ENA_S = 14 +const HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V = 0x1 +const HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S = 13 +const HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V = 0x1 +const HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S = 12 +const HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S = 11 +const HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S = 10 +const HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S = 9 +const HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S = 8 +const HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S = 7 +const HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S = 6 +const HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S = 5 +const HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S = 4 +const HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S = 3 +const HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S = 2 +const HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S = 1 +const HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V = 0x1 +const HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S = 0 +const HOST_GPIO_SDIO_INT_ENA_V = 0x1 +const HOST_GPIO_SDIO_INT_ENA_S = 25 +const HOST_SLC0_HOST_RD_RETRY_INT_ENA_V = 0x1 +const HOST_SLC0_HOST_RD_RETRY_INT_ENA_S = 24 +const HOST_SLC0_RX_NEW_PACKET_INT_ENA_V = 0x1 +const HOST_SLC0_RX_NEW_PACKET_INT_ENA_S = 23 +const HOST_SLC0_EXT_BIT3_INT_ENA_V = 0x1 +const HOST_SLC0_EXT_BIT3_INT_ENA_S = 22 +const HOST_SLC0_EXT_BIT2_INT_ENA_V = 0x1 +const HOST_SLC0_EXT_BIT2_INT_ENA_S = 21 +const HOST_SLC0_EXT_BIT1_INT_ENA_V = 0x1 +const HOST_SLC0_EXT_BIT1_INT_ENA_S = 20 +const HOST_SLC0_EXT_BIT0_INT_ENA_V = 0x1 +const HOST_SLC0_EXT_BIT0_INT_ENA_S = 19 +const HOST_SLC0_RX_PF_VALID_INT_ENA_V = 0x1 +const HOST_SLC0_RX_PF_VALID_INT_ENA_S = 18 +const HOST_SLC0_TX_OVF_INT_ENA_V = 0x1 +const HOST_SLC0_TX_OVF_INT_ENA_S = 17 +const HOST_SLC0_RX_UDF_INT_ENA_V = 0x1 +const HOST_SLC0_RX_UDF_INT_ENA_S = 16 +const HOST_SLC0HOST_TX_START_INT_ENA_V = 0x1 +const HOST_SLC0HOST_TX_START_INT_ENA_S = 15 +const HOST_SLC0HOST_RX_START_INT_ENA_V = 0x1 +const HOST_SLC0HOST_RX_START_INT_ENA_S = 14 +const HOST_SLC0HOST_RX_EOF_INT_ENA_V = 0x1 +const HOST_SLC0HOST_RX_EOF_INT_ENA_S = 13 +const HOST_SLC0HOST_RX_SOF_INT_ENA_V = 0x1 +const HOST_SLC0HOST_RX_SOF_INT_ENA_S = 12 +const HOST_SLC0_TOKEN1_0TO1_INT_ENA_V = 0x1 +const HOST_SLC0_TOKEN1_0TO1_INT_ENA_S = 11 +const HOST_SLC0_TOKEN0_0TO1_INT_ENA_V = 0x1 +const HOST_SLC0_TOKEN0_0TO1_INT_ENA_S = 10 +const HOST_SLC0_TOKEN1_1TO0_INT_ENA_V = 0x1 +const HOST_SLC0_TOKEN1_1TO0_INT_ENA_S = 9 +const HOST_SLC0_TOKEN0_1TO0_INT_ENA_V = 0x1 +const HOST_SLC0_TOKEN0_1TO0_INT_ENA_S = 8 +const HOST_SLC0_TOHOST_BIT7_INT_ENA_V = 0x1 +const HOST_SLC0_TOHOST_BIT7_INT_ENA_S = 7 +const HOST_SLC0_TOHOST_BIT6_INT_ENA_V = 0x1 +const HOST_SLC0_TOHOST_BIT6_INT_ENA_S = 6 +const HOST_SLC0_TOHOST_BIT5_INT_ENA_V = 0x1 +const HOST_SLC0_TOHOST_BIT5_INT_ENA_S = 5 +const HOST_SLC0_TOHOST_BIT4_INT_ENA_V = 0x1 +const HOST_SLC0_TOHOST_BIT4_INT_ENA_S = 4 +const HOST_SLC0_TOHOST_BIT3_INT_ENA_V = 0x1 +const HOST_SLC0_TOHOST_BIT3_INT_ENA_S = 3 +const HOST_SLC0_TOHOST_BIT2_INT_ENA_V = 0x1 +const HOST_SLC0_TOHOST_BIT2_INT_ENA_S = 2 +const HOST_SLC0_TOHOST_BIT1_INT_ENA_V = 0x1 +const HOST_SLC0_TOHOST_BIT1_INT_ENA_S = 1 +const HOST_SLC0_TOHOST_BIT0_INT_ENA_V = 0x1 +const HOST_SLC0_TOHOST_BIT0_INT_ENA_S = 0 +const HOST_SLC0HOST_RX_INFOR = 0x000FFFFF +const HOST_SLC0HOST_RX_INFOR_V = 0xFFFFF +const HOST_SLC0HOST_RX_INFOR_S = 0 +const HOST_SLC0HOST_LEN_WD = 0xFFFFFFFF +const HOST_SLC0HOST_LEN_WD_V = 0xFFFFFFFF +const HOST_SLC0HOST_LEN_WD_S = 0 +const HOST_SLC_APBWIN_WDATA = 0xFFFFFFFF +const HOST_SLC_APBWIN_WDATA_V = 0xFFFFFFFF +const HOST_SLC_APBWIN_WDATA_S = 0 +const HOST_SLC_APBWIN_BUS_V = 0x1 +const HOST_SLC_APBWIN_BUS_S = 30 +const HOST_SLC_APBWIN_START_V = 0x1 +const HOST_SLC_APBWIN_START_S = 29 +const HOST_SLC_APBWIN_WR_V = 0x1 +const HOST_SLC_APBWIN_WR_S = 28 +const HOST_SLC_APBWIN_ADDR = 0x0FFFFFFF +const HOST_SLC_APBWIN_ADDR_V = 0xFFFFFFF +const HOST_SLC_APBWIN_ADDR_S = 0 +const HOST_SLC_APBWIN_RDATA = 0xFFFFFFFF +const HOST_SLC_APBWIN_RDATA_V = 0xFFFFFFFF +const HOST_SLC_APBWIN_RDATA_S = 0 +const HOST_SLCHOST_SLC0_BIT6_CLRADDR = 0x000001FF +const HOST_SLCHOST_SLC0_BIT6_CLRADDR_V = 0x1FF +const HOST_SLCHOST_SLC0_BIT6_CLRADDR_S = 9 +const HOST_SLCHOST_SLC0_BIT7_CLRADDR = 0x000001FF +const HOST_SLCHOST_SLC0_BIT7_CLRADDR_V = 0x1FF +const HOST_SLCHOST_SLC0_BIT7_CLRADDR_S = 0 +const HOST_GPIO_SDIO_INT_ENA1_V = 0x1 +const HOST_GPIO_SDIO_INT_ENA1_S = 25 +const HOST_SLC0_HOST_RD_RETRY_INT_ENA1_V = 0x1 +const HOST_SLC0_HOST_RD_RETRY_INT_ENA1_S = 24 +const HOST_SLC0_RX_NEW_PACKET_INT_ENA1_V = 0x1 +const HOST_SLC0_RX_NEW_PACKET_INT_ENA1_S = 23 +const HOST_SLC0_EXT_BIT3_INT_ENA1_V = 0x1 +const HOST_SLC0_EXT_BIT3_INT_ENA1_S = 22 +const HOST_SLC0_EXT_BIT2_INT_ENA1_V = 0x1 +const HOST_SLC0_EXT_BIT2_INT_ENA1_S = 21 +const HOST_SLC0_EXT_BIT1_INT_ENA1_V = 0x1 +const HOST_SLC0_EXT_BIT1_INT_ENA1_S = 20 +const HOST_SLC0_EXT_BIT0_INT_ENA1_V = 0x1 +const HOST_SLC0_EXT_BIT0_INT_ENA1_S = 19 +const HOST_SLC0_RX_PF_VALID_INT_ENA1_V = 0x1 +const HOST_SLC0_RX_PF_VALID_INT_ENA1_S = 18 +const HOST_SLC0_TX_OVF_INT_ENA1_V = 0x1 +const HOST_SLC0_TX_OVF_INT_ENA1_S = 17 +const HOST_SLC0_RX_UDF_INT_ENA1_V = 0x1 +const HOST_SLC0_RX_UDF_INT_ENA1_S = 16 +const HOST_SLC0HOST_TX_START_INT_ENA1_V = 0x1 +const HOST_SLC0HOST_TX_START_INT_ENA1_S = 15 +const HOST_SLC0HOST_RX_START_INT_ENA1_V = 0x1 +const HOST_SLC0HOST_RX_START_INT_ENA1_S = 14 +const HOST_SLC0HOST_RX_EOF_INT_ENA1_V = 0x1 +const HOST_SLC0HOST_RX_EOF_INT_ENA1_S = 13 +const HOST_SLC0HOST_RX_SOF_INT_ENA1_V = 0x1 +const HOST_SLC0HOST_RX_SOF_INT_ENA1_S = 12 +const HOST_SLC0_TOKEN1_0TO1_INT_ENA1_V = 0x1 +const HOST_SLC0_TOKEN1_0TO1_INT_ENA1_S = 11 +const HOST_SLC0_TOKEN0_0TO1_INT_ENA1_V = 0x1 +const HOST_SLC0_TOKEN0_0TO1_INT_ENA1_S = 10 +const HOST_SLC0_TOKEN1_1TO0_INT_ENA1_V = 0x1 +const HOST_SLC0_TOKEN1_1TO0_INT_ENA1_S = 9 +const HOST_SLC0_TOKEN0_1TO0_INT_ENA1_V = 0x1 +const HOST_SLC0_TOKEN0_1TO0_INT_ENA1_S = 8 +const HOST_SLC0_TOHOST_BIT7_INT_ENA1_V = 0x1 +const HOST_SLC0_TOHOST_BIT7_INT_ENA1_S = 7 +const HOST_SLC0_TOHOST_BIT6_INT_ENA1_V = 0x1 +const HOST_SLC0_TOHOST_BIT6_INT_ENA1_S = 6 +const HOST_SLC0_TOHOST_BIT5_INT_ENA1_V = 0x1 +const HOST_SLC0_TOHOST_BIT5_INT_ENA1_S = 5 +const HOST_SLC0_TOHOST_BIT4_INT_ENA1_V = 0x1 +const HOST_SLC0_TOHOST_BIT4_INT_ENA1_S = 4 +const HOST_SLC0_TOHOST_BIT3_INT_ENA1_V = 0x1 +const HOST_SLC0_TOHOST_BIT3_INT_ENA1_S = 3 +const HOST_SLC0_TOHOST_BIT2_INT_ENA1_V = 0x1 +const HOST_SLC0_TOHOST_BIT2_INT_ENA1_S = 2 +const HOST_SLC0_TOHOST_BIT1_INT_ENA1_V = 0x1 +const HOST_SLC0_TOHOST_BIT1_INT_ENA1_S = 1 +const HOST_SLC0_TOHOST_BIT0_INT_ENA1_V = 0x1 +const HOST_SLC0_TOHOST_BIT0_INT_ENA1_S = 0 +const HOST_SLCHOST_DATE = 0xFFFFFFFF +const HOST_SLCHOST_DATE_V = 0xFFFFFFFF +const HOST_SLCHOST_DATE_S = 0 +const HOST_SLCHOST_ID = 0xFFFFFFFF +const HOST_SLCHOST_ID_V = 0xFFFFFFFF +const HOST_SLCHOST_ID_S = 0 +const HOST_HSPEED_CON_EN_V = 0x1 +const HOST_HSPEED_CON_EN_S = 27 +const HOST_SDIO_PAD_PULLUP_V = 0x1 +const HOST_SDIO_PAD_PULLUP_S = 26 +const HOST_SDIO20_INT_DELAY_V = 0x1 +const HOST_SDIO20_INT_DELAY_S = 25 +const HOST_FRC_QUICK_IN = 0x0000001F +const HOST_FRC_QUICK_IN_V = 0x1F +const HOST_FRC_QUICK_IN_S = 20 +const HOST_FRC_POS_SAMP = 0x0000001F +const HOST_FRC_POS_SAMP_V = 0x1F +const HOST_FRC_POS_SAMP_S = 15 +const HOST_FRC_NEG_SAMP = 0x0000001F +const HOST_FRC_NEG_SAMP_V = 0x1F +const HOST_FRC_NEG_SAMP_S = 10 +const HOST_FRC_SDIO20 = 0x0000001F +const HOST_FRC_SDIO20_V = 0x1F +const HOST_FRC_SDIO20_S = 5 +const HOST_FRC_SDIO11 = 0x0000001F +const HOST_FRC_SDIO11_V = 0x1F +const HOST_FRC_SDIO11_S = 0 +const HOST_SDIO_QUICK_IN = 0x0000001F +const HOST_SDIO_QUICK_IN_V = 0x1F +const HOST_SDIO_QUICK_IN_S = 10 +const HOST_SDIO_NEG_SAMP = 0x0000001F +const HOST_SDIO_NEG_SAMP_V = 0x1F +const HOST_SDIO_NEG_SAMP_S = 5 +const HOST_SDIO20_MODE = 0x0000001F +const HOST_SDIO20_MODE_V = 0x1F +const HOST_SDIO20_MODE_S = 0 diff --git a/esp32/host_struct.go b/esp32/host_struct.go new file mode 100644 index 00000000..32864841 --- /dev/null +++ b/esp32/host_struct.go @@ -0,0 +1,216 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type HostDevS struct { + Reserved0 c.Uint32T + Reserved4 c.Uint32T + Reserved8 c.Uint32T + ReservedC c.Uint32T + Reserved10 c.Uint32T + Reserved14 c.Uint32T + Reserved18 c.Uint32T + Reserved1c c.Uint32T + Func22 struct { + Val c.Uint32T + } + Reserved24 c.Uint32T + Reserved28 c.Uint32T + Reserved2c c.Uint32T + Reserved30 c.Uint32T + GpioStatus0 c.Uint32T + GpioStatus1 struct { + Val c.Uint32T + } + GpioIn0 c.Uint32T + GpioIn1 struct { + Val c.Uint32T + } + Slc0TokenRdata struct { + Val c.Uint32T + } + Slc0Pf c.Uint32T + Reserved4c c.Uint32T + Slc0IntRaw struct { + Val c.Uint32T + } + Reserved54 c.Uint32T + Slc0IntSt struct { + Val c.Uint32T + } + Reserved5c c.Uint32T + PktLen struct { + Val c.Uint32T + } + StateW0 struct { + Val c.Uint32T + } + StateW1 struct { + Val c.Uint32T + } + ConfW0 struct { + Val c.Uint32T + } + ConfW1 struct { + Val c.Uint32T + } + ConfW2 struct { + Val c.Uint32T + } + ConfW3 struct { + Val c.Uint32T + } + ConfW4 struct { + Val c.Uint32T + } + ConfW5 struct { + Val c.Uint32T + } + WinCmd struct { + Val c.Uint32T + } + ConfW6 struct { + Val c.Uint32T + } + ConfW7 struct { + Val c.Uint32T + } + PktLen0 struct { + Val c.Uint32T + } + PktLen1 struct { + Val c.Uint32T + } + PktLen2 struct { + Val c.Uint32T + } + ConfW8 struct { + Val c.Uint32T + } + ConfW9 struct { + Val c.Uint32T + } + ConfW10 struct { + Val c.Uint32T + } + ConfW11 struct { + Val c.Uint32T + } + ConfW12 struct { + Val c.Uint32T + } + ConfW13 struct { + Val c.Uint32T + } + ConfW14 struct { + Val c.Uint32T + } + ConfW15 struct { + Val c.Uint32T + } + CheckSum0 c.Uint32T + CheckSum1 c.Uint32T + ReservedC4 c.Uint32T + Slc0TokenWdata struct { + Val c.Uint32T + } + ReservedCc c.Uint32T + TokenCon struct { + Val c.Uint32T + } + Slc0IntClr struct { + Val c.Uint32T + } + ReservedD8 c.Uint32T + Slc0Func1IntEna struct { + Val c.Uint32T + } + ReservedE0 c.Uint32T + ReservedE4 c.Uint32T + ReservedE8 c.Uint32T + Slc0IntEna struct { + Val c.Uint32T + } + ReservedF0 c.Uint32T + Slc0RxInfor struct { + Val c.Uint32T + } + ReservedF8 c.Uint32T + Slc0LenWd c.Uint32T + ApbwinWdata c.Uint32T + ApbwinConf struct { + Val c.Uint32T + } + ApbwinRdata c.Uint32T + Slc0Rdclr struct { + Val c.Uint32T + } + Reserved110 c.Uint32T + Slc0IntEna1 struct { + Val c.Uint32T + } + Reserved118 c.Uint32T + Reserved11c c.Uint32T + Reserved120 c.Uint32T + Reserved124 c.Uint32T + Reserved128 c.Uint32T + Reserved12c c.Uint32T + Reserved130 c.Uint32T + Reserved134 c.Uint32T + Reserved138 c.Uint32T + Reserved13c c.Uint32T + Reserved140 c.Uint32T + Reserved144 c.Uint32T + Reserved148 c.Uint32T + Reserved14c c.Uint32T + Reserved150 c.Uint32T + Reserved154 c.Uint32T + Reserved158 c.Uint32T + Reserved15c c.Uint32T + Reserved160 c.Uint32T + Reserved164 c.Uint32T + Reserved168 c.Uint32T + Reserved16c c.Uint32T + Reserved170 c.Uint32T + Reserved174 c.Uint32T + Date c.Uint32T + Id c.Uint32T + Reserved180 c.Uint32T + Reserved184 c.Uint32T + Reserved188 c.Uint32T + Reserved18c c.Uint32T + Reserved190 c.Uint32T + Reserved194 c.Uint32T + Reserved198 c.Uint32T + Reserved19c c.Uint32T + Reserved1a0 c.Uint32T + Reserved1a4 c.Uint32T + Reserved1a8 c.Uint32T + Reserved1ac c.Uint32T + Reserved1b0 c.Uint32T + Reserved1b4 c.Uint32T + Reserved1b8 c.Uint32T + Reserved1bc c.Uint32T + Reserved1c0 c.Uint32T + Reserved1c4 c.Uint32T + Reserved1c8 c.Uint32T + Reserved1cc c.Uint32T + Reserved1d0 c.Uint32T + Reserved1d4 c.Uint32T + Reserved1d8 c.Uint32T + Reserved1dc c.Uint32T + Reserved1e0 c.Uint32T + Reserved1e4 c.Uint32T + Reserved1e8 c.Uint32T + Reserved1ec c.Uint32T + Conf struct { + Val c.Uint32T + } + InfSt struct { + Val c.Uint32T + } +} +type HostDevT HostDevS diff --git a/esp32/hw_stack_guard.go b/esp32/hw_stack_guard.go new file mode 100644 index 00000000..9acba925 --- /dev/null +++ b/esp32/hw_stack_guard.go @@ -0,0 +1,26 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* The functions below are designed to be used in interrupt/panic handler + * In case using them in user's code put them into critical section.*/ +//go:linkname EspHwStackGuardMonitorStart C.esp_hw_stack_guard_monitor_start +func EspHwStackGuardMonitorStart() + +//go:linkname EspHwStackGuardMonitorStop C.esp_hw_stack_guard_monitor_stop +func EspHwStackGuardMonitorStop() + +//go:linkname EspHwStackGuardSetBounds C.esp_hw_stack_guard_set_bounds +func EspHwStackGuardSetBounds(sp_min c.Uint32T, sp_max c.Uint32T) + +//go:linkname EspHwStackGuardGetBounds C.esp_hw_stack_guard_get_bounds +func EspHwStackGuardGetBounds(core_id c.Uint32T, sp_min *c.Uint32T, sp_max *c.Uint32T) + +//go:linkname EspHwStackGuardGetFiredCpu C.esp_hw_stack_guard_get_fired_cpu +func EspHwStackGuardGetFiredCpu() c.Uint32T + +//go:linkname EspHwStackGuardGetPc C.esp_hw_stack_guard_get_pc +func EspHwStackGuardGetPc(core_id c.Uint32T) c.Uint32T diff --git a/esp32/hwcrypto_reg.go b/esp32/hwcrypto_reg.go new file mode 100644 index 00000000..569a36ec --- /dev/null +++ b/esp32/hwcrypto_reg.go @@ -0,0 +1,10 @@ +package freertos + +import _ "unsafe" + +const AES_BLOCK_MODE_ECB = 0 +const AES_BLOCK_MODE_CBC = 1 +const AES_BLOCK_MODE_OFB = 2 +const AES_BLOCK_MODE_CTR = 3 +const AES_BLOCK_MODE_CFB8 = 4 +const AES_BLOCK_MODE_CFB128 = 5 diff --git a/esp32/i2c_hal.go b/esp32/i2c_hal.go new file mode 100644 index 00000000..0dc312c0 --- /dev/null +++ b/esp32/i2c_hal.go @@ -0,0 +1,174 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief I2C hal Context definition + */ + +type I2cHalContextT struct { + Dev *I2cDevT +} + +/** + * @brief I2C hal clock configurations + */ + +type I2cHalSclkInfoT struct { + ClkSel c.Uint8T + ClkActive c.Uint8T + ClkDiv HalUtilsClkDivT +} + +/** + * @brief Timing configuration structure. Used for I2C reset internally. + */ + +type I2cHalTimingConfigT struct { + HighPeriod c.Int + LowPeriod c.Int + WaitHighPeriod c.Int + RstartSetup c.Int + StartHold c.Int + StopSetup c.Int + StopHold c.Int + SdaSample c.Int + SdaHold c.Int + Timeout c.Int + ClkCfg I2cHalSclkInfoT +} + +/** + * @brief Init the I2C slave. + * + * @param hal Context of the HAL layer + * @param i2c_num I2C port number + * + * @return None + */ +// llgo:link (*I2cHalContextT).I2cHalSlaveInit C.i2c_hal_slave_init +func (recv_ *I2cHalContextT) I2cHalSlaveInit() { +} + +/** + * @brief Init the I2C master. + * + * @param hal Context of the HAL layer + * @param i2c_num I2C port number + * + * @return None + */ +// llgo:link (*I2cHalContextT).I2cHalMasterInit C.i2c_hal_master_init +func (recv_ *I2cHalContextT) I2cHalMasterInit() { +} + +/** + * @brief Set I2C bus timing with the given frequency + * + * @param hal Context of the HAL layer + * @param scl_freq The scl frequency to be set + * @param src_clk The source clock of I2C + * @param source_freq Source clock frequency of I2C + * + * @return None + */ +// llgo:link (*I2cHalContextT).X_i2cHalSetBusTiming C._i2c_hal_set_bus_timing +func (recv_ *I2cHalContextT) X_i2cHalSetBusTiming(scl_freq c.Int, src_clk I2cClockSourceT, source_freq c.Int) { +} + +/** + * @brief I2C hardware FSM reset + * + * @param hal Context of the HAL layer + * + * @return None + */ +// llgo:link (*I2cHalContextT).I2cHalMasterFsmRst C.i2c_hal_master_fsm_rst +func (recv_ *I2cHalContextT) I2cHalMasterFsmRst() { +} + +/** + * @brief I2C master handle tx interrupt event + * + * @param hal Context of the HAL layer + * @param event Pointer to accept the interrupt event + * + * @return None + */ +// llgo:link (*I2cHalContextT).I2cHalMasterHandleTxEvent C.i2c_hal_master_handle_tx_event +func (recv_ *I2cHalContextT) I2cHalMasterHandleTxEvent(event *I2cIntrEventT) { +} + +/** + * @brief I2C master handle rx interrupt event + * + * @param hal Context of the HAL layer + * @param event Pointer to accept the interrupt event + * + * @return None + */ +// llgo:link (*I2cHalContextT).I2cHalMasterHandleRxEvent C.i2c_hal_master_handle_rx_event +func (recv_ *I2cHalContextT) I2cHalMasterHandleRxEvent(event *I2cIntrEventT) { +} + +/** + * @brief Set scl timeout reg value according to given timeout us and source clock frequency + * + * @param hal Context of the HAL layer + * @param timeout_us timeout us + * @param sclk_clock_hz source clock hz + */ +// llgo:link (*I2cHalContextT).I2cHalMasterSetSclTimeoutVal C.i2c_hal_master_set_scl_timeout_val +func (recv_ *I2cHalContextT) I2cHalMasterSetSclTimeoutVal(timeout_us c.Uint32T, sclk_clock_hz c.Uint32T) { +} + +/** + * @brief Init I2C hal layer + * + * @param hal Context of the HAL + * @param i2c_port I2C port number. + */ +// llgo:link (*I2cHalContextT).X_i2cHalInit C._i2c_hal_init +func (recv_ *I2cHalContextT) X_i2cHalInit(i2c_port c.Int) { +} + +/** + * @brief Deinit I2C hal layer + * + * @param hal Context of the HAL + */ +// llgo:link (*I2cHalContextT).X_i2cHalDeinit C._i2c_hal_deinit +func (recv_ *I2cHalContextT) X_i2cHalDeinit() { +} + +/** + * @brief Start I2C master transaction + * + * @param hal Context of the HAL + */ +// llgo:link (*I2cHalContextT).I2cHalMasterTransStart C.i2c_hal_master_trans_start +func (recv_ *I2cHalContextT) I2cHalMasterTransStart() { +} + +/** + * @brief Get timing configuration + * + * @param hal Context of the HAL + * @param timing_config Pointer to timing config structure. + */ +// llgo:link (*I2cHalContextT).I2cHalGetTimingConfig C.i2c_hal_get_timing_config +func (recv_ *I2cHalContextT) I2cHalGetTimingConfig(timing_config *I2cHalTimingConfigT) { +} + +/** + * @brief Set timing configuration + * + * @param hal Context of the HAL + * @param timing_config Timing config structure. + */ +// llgo:link (*I2cHalContextT).I2cHalSetTimingConfig C.i2c_hal_set_timing_config +func (recv_ *I2cHalContextT) I2cHalSetTimingConfig(timing_config *I2cHalTimingConfigT) { +} diff --git a/esp32/i2c_ll.go b/esp32/i2c_ll.go new file mode 100644 index 00000000..2f2fedbf --- /dev/null +++ b/esp32/i2c_ll.go @@ -0,0 +1,55 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const I2C_LL_CMD_RESTART = 6 +const I2C_LL_CMD_WRITE = 1 +const I2C_LL_CMD_READ = 3 +const I2C_LL_CMD_STOP = 2 +const I2C_LL_CMD_END = 4 + +/** + * @brief I2C hardware cmd register fields. + */ + +type I2cLlHwCmdT struct { + Val c.Uint32T +} +type I2cLlMasterIntrT c.Int + +const ( + I2C_INTR_MST_TXFIFO_WM I2cLlMasterIntrT = 2 + I2C_INTR_MST_RXFIFO_WM I2cLlMasterIntrT = 1 + I2C_LL_INTR_NACK I2cLlMasterIntrT = 1024 + I2C_LL_INTR_TIMEOUT I2cLlMasterIntrT = 256 + I2C_LL_INTR_MST_COMPLETE I2cLlMasterIntrT = 128 + I2C_LL_INTR_ARBITRATION I2cLlMasterIntrT = 32 + I2C_LL_INTR_END_DETECT I2cLlMasterIntrT = 8 + I2C_LL_INTR_ST_TO I2cLlMasterIntrT = 8192 +) + +type I2cLlSlaveIntrT c.Int + +const ( + I2C_INTR_SLV_TXFIFO_WM I2cLlSlaveIntrT = 2 + I2C_INTR_SLV_RXFIFO_WM I2cLlSlaveIntrT = 1 + I2C_INTR_SLV_COMPLETE I2cLlSlaveIntrT = 128 + I2C_INTR_START I2cLlSlaveIntrT = 32768 + I2C_INTR_STRETCH I2cLlSlaveIntrT = 65536 +) + +type I2cIntrEventT c.Int + +const ( + I2C_INTR_EVENT_ERR I2cIntrEventT = 0 + I2C_INTR_EVENT_ARBIT_LOST I2cIntrEventT = 1 + I2C_INTR_EVENT_NACK I2cIntrEventT = 2 + I2C_INTR_EVENT_TOUT I2cIntrEventT = 3 + I2C_INTR_EVENT_END_DET I2cIntrEventT = 4 + I2C_INTR_EVENT_TRANS_DONE I2cIntrEventT = 5 + I2C_INTR_EVENT_RXFIFO_FULL I2cIntrEventT = 6 + I2C_INTR_EVENT_TXFIFO_EMPTY I2cIntrEventT = 7 +) diff --git a/esp32/i2c_periph.go b/esp32/i2c_periph.go new file mode 100644 index 00000000..45e7723d --- /dev/null +++ b/esp32/i2c_periph.go @@ -0,0 +1,15 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type I2cSignalConnT struct { + SdaOutSig c.Uint8T + SdaInSig c.Uint8T + SclOutSig c.Uint8T + SclInSig c.Uint8T + IomuxFunc c.Uint8T + Irq c.Uint8T +} diff --git a/esp32/i2c_reg.go b/esp32/i2c_reg.go new file mode 100644 index 00000000..f2498c4f --- /dev/null +++ b/esp32/i2c_reg.go @@ -0,0 +1,166 @@ +package freertos + +import _ "unsafe" + +const I2C_SCL_LOW_PERIOD_S = 0 +const I2C_SDA_FORCE_OUT_S = 0 +const I2C_SCL_FORCE_OUT_S = 1 +const I2C_SAMPLE_SCL_LEVEL_S = 2 +const I2C_RX_FULL_ACK_LEVEL_S = 3 +const I2C_MS_MODE_S = 4 +const I2C_TRANS_START_S = 5 +const I2C_TX_LSB_FIRST_S = 6 +const I2C_RX_LSB_FIRST_S = 7 +const I2C_CLK_EN_S = 8 +const I2C_ARBITRATION_EN_S = 9 +const I2C_FSM_RST_S = 10 +const I2C_CONF_UPGATE_S = 11 +const I2C_SLV_TX_AUTO_START_EN_S = 12 +const I2C_ADDR_10BIT_RW_CHECK_EN_S = 13 +const I2C_ADDR_BROADCASTING_EN_S = 14 +const I2C_RESP_REC_S = 0 +const I2C_SLAVE_RW_S = 1 +const I2C_ARB_LOST_S = 3 +const I2C_BUS_BUSY_S = 4 +const I2C_SLAVE_ADDRESSED_S = 5 +const I2C_RXFIFO_CNT_S = 8 +const I2C_STRETCH_CAUSE_S = 14 +const I2C_TXFIFO_CNT_S = 18 +const I2C_SCL_MAIN_STATE_LAST_S = 24 +const I2C_SCL_STATE_LAST_S = 28 +const I2C_TIME_OUT_VALUE_S = 0 +const I2C_TIME_OUT_EN_S = 5 +const I2C_SLAVE_ADDR_S = 0 +const I2C_ADDR_10BIT_EN_S = 31 +const I2C_RXFIFO_RADDR_S = 0 +const I2C_RXFIFO_WADDR_S = 5 +const I2C_TXFIFO_RADDR_S = 10 +const I2C_TXFIFO_WADDR_S = 15 +const I2C_SLAVE_RW_POINT_S = 22 +const I2C_RXFIFO_WM_THRHD_S = 0 +const I2C_TXFIFO_WM_THRHD_S = 5 +const I2C_NONFIFO_EN_S = 10 +const I2C_FIFO_ADDR_CFG_EN_S = 11 +const I2C_RX_FIFO_RST_S = 12 +const I2C_TX_FIFO_RST_S = 13 +const I2C_FIFO_PRT_EN_S = 14 +const I2C_FIFO_RDATA_S = 0 +const I2C_RXFIFO_WM_INT_RAW_S = 0 +const I2C_TXFIFO_WM_INT_RAW_S = 1 +const I2C_RXFIFO_OVF_INT_RAW_S = 2 +const I2C_END_DETECT_INT_RAW_S = 3 +const I2C_BYTE_TRANS_DONE_INT_RAW_S = 4 +const I2C_ARBITRATION_LOST_INT_RAW_S = 5 +const I2C_MST_TXFIFO_UDF_INT_RAW_S = 6 +const I2C_TRANS_COMPLETE_INT_RAW_S = 7 +const I2C_TIME_OUT_INT_RAW_S = 8 +const I2C_TRANS_START_INT_RAW_S = 9 +const I2C_NACK_INT_RAW_S = 10 +const I2C_TXFIFO_OVF_INT_RAW_S = 11 +const I2C_RXFIFO_UDF_INT_RAW_S = 12 +const I2C_SCL_ST_TO_INT_RAW_S = 13 +const I2C_SCL_MAIN_ST_TO_INT_RAW_S = 14 +const I2C_DET_START_INT_RAW_S = 15 +const I2C_SLAVE_STRETCH_INT_RAW_S = 16 +const I2C_GENERAL_CALL_INT_RAW_S = 17 +const I2C_RXFIFO_WM_INT_CLR_S = 0 +const I2C_TXFIFO_WM_INT_CLR_S = 1 +const I2C_RXFIFO_OVF_INT_CLR_S = 2 +const I2C_END_DETECT_INT_CLR_S = 3 +const I2C_BYTE_TRANS_DONE_INT_CLR_S = 4 +const I2C_ARBITRATION_LOST_INT_CLR_S = 5 +const I2C_MST_TXFIFO_UDF_INT_CLR_S = 6 +const I2C_TRANS_COMPLETE_INT_CLR_S = 7 +const I2C_TIME_OUT_INT_CLR_S = 8 +const I2C_TRANS_START_INT_CLR_S = 9 +const I2C_NACK_INT_CLR_S = 10 +const I2C_TXFIFO_OVF_INT_CLR_S = 11 +const I2C_RXFIFO_UDF_INT_CLR_S = 12 +const I2C_SCL_ST_TO_INT_CLR_S = 13 +const I2C_SCL_MAIN_ST_TO_INT_CLR_S = 14 +const I2C_DET_START_INT_CLR_S = 15 +const I2C_SLAVE_STRETCH_INT_CLR_S = 16 +const I2C_GENERAL_CALL_INT_CLR_S = 17 +const I2C_RXFIFO_WM_INT_ENA_S = 0 +const I2C_TXFIFO_WM_INT_ENA_S = 1 +const I2C_RXFIFO_OVF_INT_ENA_S = 2 +const I2C_END_DETECT_INT_ENA_S = 3 +const I2C_BYTE_TRANS_DONE_INT_ENA_S = 4 +const I2C_ARBITRATION_LOST_INT_ENA_S = 5 +const I2C_MST_TXFIFO_UDF_INT_ENA_S = 6 +const I2C_TRANS_COMPLETE_INT_ENA_S = 7 +const I2C_TIME_OUT_INT_ENA_S = 8 +const I2C_TRANS_START_INT_ENA_S = 9 +const I2C_NACK_INT_ENA_S = 10 +const I2C_TXFIFO_OVF_INT_ENA_S = 11 +const I2C_RXFIFO_UDF_INT_ENA_S = 12 +const I2C_SCL_ST_TO_INT_ENA_S = 13 +const I2C_SCL_MAIN_ST_TO_INT_ENA_S = 14 +const I2C_DET_START_INT_ENA_S = 15 +const I2C_SLAVE_STRETCH_INT_ENA_S = 16 +const I2C_GENERAL_CALL_INT_ENA_S = 17 +const I2C_RXFIFO_WM_INT_ST_S = 0 +const I2C_TXFIFO_WM_INT_ST_S = 1 +const I2C_RXFIFO_OVF_INT_ST_S = 2 +const I2C_END_DETECT_INT_ST_S = 3 +const I2C_BYTE_TRANS_DONE_INT_ST_S = 4 +const I2C_ARBITRATION_LOST_INT_ST_S = 5 +const I2C_MST_TXFIFO_UDF_INT_ST_S = 6 +const I2C_TRANS_COMPLETE_INT_ST_S = 7 +const I2C_TIME_OUT_INT_ST_S = 8 +const I2C_TRANS_START_INT_ST_S = 9 +const I2C_NACK_INT_ST_S = 10 +const I2C_TXFIFO_OVF_INT_ST_S = 11 +const I2C_RXFIFO_UDF_INT_ST_S = 12 +const I2C_SCL_ST_TO_INT_ST_S = 13 +const I2C_SCL_MAIN_ST_TO_INT_ST_S = 14 +const I2C_DET_START_INT_ST_S = 15 +const I2C_SLAVE_STRETCH_INT_ST_S = 16 +const I2C_GENERAL_CALL_INT_ST_S = 17 +const I2C_SDA_HOLD_TIME_S = 0 +const I2C_SDA_SAMPLE_TIME_S = 0 +const I2C_SCL_HIGH_PERIOD_S = 0 +const I2C_SCL_WAIT_HIGH_PERIOD_S = 9 +const I2C_SCL_START_HOLD_TIME_S = 0 +const I2C_SCL_RSTART_SETUP_TIME_S = 0 +const I2C_SCL_STOP_HOLD_TIME_S = 0 +const I2C_SCL_STOP_SETUP_TIME_S = 0 +const I2C_SCL_FILTER_THRES_S = 0 +const I2C_SDA_FILTER_THRES_S = 4 +const I2C_SCL_FILTER_EN_S = 8 +const I2C_SDA_FILTER_EN_S = 9 +const I2C_SCLK_DIV_NUM_S = 0 +const I2C_SCLK_DIV_A_S = 8 +const I2C_SCLK_DIV_B_S = 14 +const I2C_SCLK_SEL_S = 20 +const I2C_SCLK_ACTIVE_S = 21 +const I2C_COMMAND0_S = 0 +const I2C_COMMAND0_DONE_S = 31 +const I2C_COMMAND1_S = 0 +const I2C_COMMAND1_DONE_S = 31 +const I2C_COMMAND2_S = 0 +const I2C_COMMAND2_DONE_S = 31 +const I2C_COMMAND3_S = 0 +const I2C_COMMAND3_DONE_S = 31 +const I2C_COMMAND4_S = 0 +const I2C_COMMAND4_DONE_S = 31 +const I2C_COMMAND5_S = 0 +const I2C_COMMAND5_DONE_S = 31 +const I2C_COMMAND6_S = 0 +const I2C_COMMAND6_DONE_S = 31 +const I2C_COMMAND7_S = 0 +const I2C_COMMAND7_DONE_S = 31 +const I2C_SCL_ST_TO_I2C_S = 0 +const I2C_SCL_MAIN_ST_TO_I2C_S = 0 +const I2C_SCL_RST_SLV_EN_S = 0 +const I2C_SCL_RST_SLV_NUM_S = 1 +const I2C_SCL_PD_EN_S = 6 +const I2C_SDA_PD_EN_S = 7 +const I2C_STRETCH_PROTECT_NUM_S = 0 +const I2C_SLAVE_SCL_STRETCH_EN_S = 10 +const I2C_SLAVE_SCL_STRETCH_CLR_S = 11 +const I2C_SLAVE_BYTE_ACK_CTL_EN_S = 12 +const I2C_SLAVE_BYTE_ACK_LVL_S = 13 +const I2C_DATE_S = 0 +const I2C_TXFIFO_START_ADDR_S = 0 +const I2C_RXFIFO_START_ADDR_S = 0 diff --git a/esp32/i2c_struct.go b/esp32/i2c_struct.go new file mode 100644 index 00000000..4df6ab3a --- /dev/null +++ b/esp32/i2c_struct.go @@ -0,0 +1,267 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** Group: Timing registers */ +/** Type of scl_low_period register + * Configures the low level width of the SCL + * Clock + */ + +type I2cSclLowPeriodRegT struct { + Val c.Uint32T +} + +/** Type of sda_hold register + * Configures the hold time after a negative SCL edge. + */ + +type I2cSdaHoldRegT struct { + Val c.Uint32T +} + +/** Type of sda_sample register + * Configures the sample time after a positive SCL edge. + */ + +type I2cSdaSampleRegT struct { + Val c.Uint32T +} + +/** Type of scl_high_period register + * Configures the high level width of SCL + */ + +type I2cSclHighPeriodRegT struct { + Val c.Uint32T +} + +/** Type of scl_start_hold register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ + +type I2cSclStartHoldRegT struct { + Val c.Uint32T +} + +/** Type of scl_rstart_setup register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ + +type I2cSclRstartSetupRegT struct { + Val c.Uint32T +} + +/** Type of scl_stop_hold register + * Configures the delay after the SCL clock + * edge for a stop condition + */ + +type I2cSclStopHoldRegT struct { + Val c.Uint32T +} + +/** Type of scl_stop_setup register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ + +type I2cSclStopSetupRegT struct { + Val c.Uint32T +} + +/** Type of scl_st_time_out register + * SCL status time out register + */ + +type I2cSclStTimeOutRegT struct { + Val c.Uint32T +} + +/** Type of scl_main_st_time_out register + * SCL main status time out register + */ + +type I2cSclMainStTimeOutRegT struct { + Val c.Uint32T +} + +/** Group: Configuration registers */ +/** Type of ctr register + * Transmission setting + */ + +type I2cCtrRegT struct { + Val c.Uint32T +} + +/** Type of to register + * Setting time out control for receiving data. + */ + +type I2cToRegT struct { + Val c.Uint32T +} + +/** Type of slave_addr register + * Local slave address setting + */ + +type I2cSlaveAddrRegT struct { + Val c.Uint32T +} + +/** Type of fifo_conf register + * FIFO configuration register. + */ + +type I2cFifoConfRegT struct { + Val c.Uint32T +} + +/** Type of filter_cfg register + * SCL and SDA filter configuration register + */ + +type I2cFilterCfgRegT struct { + Val c.Uint32T +} + +/** Type of clk_conf register + * I2C CLK configuration register + */ + +type I2cClkConfRegT struct { + Val c.Uint32T +} + +/** Type of scl_sp_conf register + * Power configuration register + */ + +type I2cSclSpConfRegT struct { + Val c.Uint32T +} + +/** Type of scl_stretch_conf register + * Set SCL stretch of I2C slave + */ + +type I2cSclStretchConfRegT struct { + Val c.Uint32T +} + +/** Group: Status registers */ +/** Type of sr register + * Describe I2C work status. + */ + +type I2cSrRegT struct { + Val c.Uint32T +} + +/** Type of fifo_st register + * FIFO status register. + */ + +type I2cFifoStRegT struct { + Val c.Uint32T +} + +/** Type of data register + * Rx FIFO read data. + */ + +type I2cDataRegT struct { + Val c.Uint32T +} + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ + +type I2cIntRawRegT struct { + Val c.Uint32T +} + +/** Type of int_clr register + * Interrupt clear bits + */ + +type I2cIntClrRegT struct { + Val c.Uint32T +} + +/** Type of int_ena register + * Interrupt enable bits + */ + +type I2cIntEnaRegT struct { + Val c.Uint32T +} + +/** Type of int_status register + * Status of captured I2C communication events + */ + +type I2cIntStatusRegT struct { + Val c.Uint32T +} + +/** Group: Command registers */ +/** Type of command register + * I2C command register + */ + +type I2cComdRegT struct { + Val c.Uint32T +} + +/** Group: Version register */ +/** Type of date register + * Version register + */ + +type I2cDateRegT struct { + Val c.Uint32T +} + +type I2cDevT struct { + SclLowPeriod I2cSclLowPeriodRegT + Ctr I2cCtrRegT + Sr I2cSrRegT + To I2cToRegT + SlaveAddr I2cSlaveAddrRegT + FifoSt I2cFifoStRegT + FifoConf I2cFifoConfRegT + Data I2cDataRegT + IntRaw I2cIntRawRegT + IntClr I2cIntClrRegT + IntEna I2cIntEnaRegT + IntStatus I2cIntStatusRegT + SdaHold I2cSdaHoldRegT + SdaSample I2cSdaSampleRegT + SclHighPeriod I2cSclHighPeriodRegT + Reserved03c c.Uint32T + SclStartHold I2cSclStartHoldRegT + SclRstartSetup I2cSclRstartSetupRegT + SclStopHold I2cSclStopHoldRegT + SclStopSetup I2cSclStopSetupRegT + FilterCfg I2cFilterCfgRegT + ClkConf I2cClkConfRegT + Comd [8]I2cComdRegT + SclStTimeOut I2cSclStTimeOutRegT + SclMainStTimeOut I2cSclMainStTimeOutRegT + SclSpConf I2cSclSpConfRegT + SclStretchConf I2cSclStretchConfRegT + Reserved088 [28]c.Uint32T + Date I2cDateRegT + Reserved0fc c.Uint32T + TxfifoMem [32]c.Uint32T + RxfifoMem [32]c.Uint32T +} diff --git a/esp32/i2c_types.go b/esp32/i2c_types.go new file mode 100644 index 00000000..11b12646 --- /dev/null +++ b/esp32/i2c_types.go @@ -0,0 +1,101 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type I2cPortT c.Int + +const ( + I2C_NUM_0 I2cPortT = 0 + I2C_NUM_1 I2cPortT = 1 + I2C_NUM_MAX I2cPortT = 2 +) + +type I2cAddrBitLenT c.Int + +const ( + I2C_ADDR_BIT_LEN_7 I2cAddrBitLenT = 0 + I2C_ADDR_BIT_LEN_10 I2cAddrBitLenT = 1 +) + +/** + * @brief Data structure for calculating I2C bus timing. + */ + +type I2cHalClkConfigT struct { + ClkmDiv c.Uint16T + SclLow c.Uint16T + SclHigh c.Uint16T + SclWaitHigh c.Uint16T + SdaHold c.Uint16T + SdaSample c.Uint16T + Setup c.Uint16T + Hold c.Uint16T + Tout c.Uint16T +} +type I2cModeT c.Int + +const ( + I2C_MODE_SLAVE I2cModeT = 0 + I2C_MODE_MASTER I2cModeT = 1 + I2C_MODE_MAX I2cModeT = 2 +) + +type I2cRwT c.Int + +const ( + I2C_MASTER_WRITE I2cRwT = 0 + I2C_MASTER_READ I2cRwT = 1 +) + +type I2cTransModeT c.Int + +const ( + I2C_DATA_MODE_MSB_FIRST I2cTransModeT = 0 + I2C_DATA_MODE_LSB_FIRST I2cTransModeT = 1 + I2C_DATA_MODE_MAX I2cTransModeT = 2 +) + +type I2cAddrModeT c.Int + +const ( + I2C_ADDR_BIT_7 I2cAddrModeT = 0 + I2C_ADDR_BIT_10 I2cAddrModeT = 1 + I2C_ADDR_BIT_MAX I2cAddrModeT = 2 +) + +type I2cAckTypeT c.Int + +const ( + I2C_MASTER_ACK I2cAckTypeT = 0 + I2C_MASTER_NACK I2cAckTypeT = 1 + I2C_MASTER_LAST_NACK I2cAckTypeT = 2 + I2C_MASTER_ACK_MAX I2cAckTypeT = 3 +) + +type I2cSlaveStretchCauseT c.Int + +const ( + I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH I2cSlaveStretchCauseT = 0 + I2C_SLAVE_STRETCH_CAUSE_TX_EMPTY I2cSlaveStretchCauseT = 1 + I2C_SLAVE_STRETCH_CAUSE_RX_FULL I2cSlaveStretchCauseT = 2 + I2C_SLAVE_STRETCH_CAUSE_SENDING_ACK I2cSlaveStretchCauseT = 3 +) + +type I2cSlaveReadWriteStatusT c.Int + +const ( + I2C_SLAVE_WRITE_BY_MASTER I2cSlaveReadWriteStatusT = 0 + I2C_SLAVE_READ_BY_MASTER I2cSlaveReadWriteStatusT = 1 +) + +type I2cBusModeT c.Int + +const ( + I2C_BUS_MODE_MASTER I2cBusModeT = 0 + I2C_BUS_MODE_SLAVE I2cBusModeT = 1 +) + +type I2cClockSourceT SocPeriphI2cClkSrcT diff --git a/esp32/i2s_hal.go b/esp32/i2s_hal.go new file mode 100644 index 00000000..95a2f860 --- /dev/null +++ b/esp32/i2s_hal.go @@ -0,0 +1,202 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief General slot configuration information + * @note It is a general purpose struct, not supposed to be used directly by user + */ + +type I2sHalSlotConfigT struct { + DataBitWidth I2sDataBitWidthT + SlotBitWidth I2sSlotBitWidthT + SlotMode I2sSlotModeT +} + +/** + * @brief I2S clock configuration + */ + +type I2sHalClockInfoT struct { + Sclk c.Uint32T + Mclk c.Uint32T + Bclk c.Uint32T + MclkDiv c.Uint16T + BclkDiv c.Uint16T +} + +/** + * Context that should be maintained by both the driver and the HAL + */ + +type I2sHalContextT struct { + Dev *I2sDevT +} + +/** + * @brief Init I2S hal context + * + * @param hal Context of the HAL layer + * @param port_id The I2S port number, the max port number is (SOC_I2S_NUM -1) + */ +// llgo:link (*I2sHalContextT).I2sHalInit C.i2s_hal_init +func (recv_ *I2sHalContextT) I2sHalInit(port_id c.Int) { +} + +/** + * @brief Helper function for calculating the precise mclk division by sclk and mclk + * + * @param sclk system clock + * @param mclk module clock + * @param mclk_div mclk division coefficients, including integer part and decimal part + */ +//go:linkname I2sHalCalcMclkPreciseDivision C.i2s_hal_calc_mclk_precise_division +func I2sHalCalcMclkPreciseDivision(sclk c.Uint32T, mclk c.Uint32T, mclk_div *HalUtilsClkDivT) + +/** + * @brief Set tx channel clock + * + * @param hal Context of the HAL layer + * @param clk_info clock information, if it is NULL, only set the clock source + * @param clk_src clock source + */ +// llgo:link (*I2sHalContextT).I2sHalSetTxClock C.i2s_hal_set_tx_clock +func (recv_ *I2sHalContextT) I2sHalSetTxClock(clk_info *I2sHalClockInfoT, clk_src I2sClockSrcT) { +} + +/** + * @brief Set rx channel clock + * + * @param hal Context of the HAL layer + * @param clk_info clock information, if it is NULL, only set the clock source + * @param clk_src clock source + */ +// llgo:link (*I2sHalContextT).X_i2sHalSetRxClock C._i2s_hal_set_rx_clock +func (recv_ *I2sHalContextT) X_i2sHalSetRxClock(clk_info *I2sHalClockInfoT, clk_src I2sClockSrcT) { +} + +/*------------------------------------------------------------------------- +| STD configuration | +-------------------------------------------------------------------------*/ +/** + * @brief Set tx slot to standard mode + * + * @param hal Context of the HAL layer + * @param is_slave If is slave role + * @param slot_config General slot configuration pointer, but will specified to i2s standard mode + */ +// llgo:link (*I2sHalContextT).I2sHalStdSetTxSlot C.i2s_hal_std_set_tx_slot +func (recv_ *I2sHalContextT) I2sHalStdSetTxSlot(is_slave bool, slot_cfg *I2sHalSlotConfigT) { +} + +/** + * @brief Set rx slot to standard mode + * + * @param hal Context of the HAL layer + * @param is_slave If is slave role + * @param slot_config General slot configuration pointer, but will specified to i2s standard mode + */ +// llgo:link (*I2sHalContextT).I2sHalStdSetRxSlot C.i2s_hal_std_set_rx_slot +func (recv_ *I2sHalContextT) I2sHalStdSetRxSlot(is_slave bool, slot_cfg *I2sHalSlotConfigT) { +} + +/** + * @brief Enable tx channel as standard mode + * + * @param hal Context of the HAL layer + */ +// llgo:link (*I2sHalContextT).I2sHalStdEnableTxChannel C.i2s_hal_std_enable_tx_channel +func (recv_ *I2sHalContextT) I2sHalStdEnableTxChannel() { +} + +/** + * @brief Enable rx channel as standard mode + * + * @param hal Context of the HAL layer + */ +// llgo:link (*I2sHalContextT).I2sHalStdEnableRxChannel C.i2s_hal_std_enable_rx_channel +func (recv_ *I2sHalContextT) I2sHalStdEnableRxChannel() { +} + +/** + * @brief Set tx slot to pdm mode + * + * @param hal Context of the HAL layer + * @param is_slave If is slave role + * @param slot_config General slot configuration pointer, but will specified to i2s pdm tx mode + */ +// llgo:link (*I2sHalContextT).I2sHalPdmSetTxSlot C.i2s_hal_pdm_set_tx_slot +func (recv_ *I2sHalContextT) I2sHalPdmSetTxSlot(is_slave bool, slot_cfg *I2sHalSlotConfigT) { +} + +/** + * @brief Enable tx channel as pdm mode + * + * @param hal Context of the HAL layer + */ +// llgo:link (*I2sHalContextT).I2sHalPdmEnableTxChannel C.i2s_hal_pdm_enable_tx_channel +func (recv_ *I2sHalContextT) I2sHalPdmEnableTxChannel() { +} + +/** + * @brief Set rx slot to pdm mode + * + * @param hal Context of the HAL layer + * @param is_slave If is slave role + * @param slot_config General slot configuration pointer, but will specified to i2s pdm rx mode + */ +// llgo:link (*I2sHalContextT).I2sHalPdmSetRxSlot C.i2s_hal_pdm_set_rx_slot +func (recv_ *I2sHalContextT) I2sHalPdmSetRxSlot(is_slave bool, slot_cfg *I2sHalSlotConfigT) { +} + +/** + * @brief Enable rx channel as pdm mode + * + * @param hal Context of the HAL layer + */ +// llgo:link (*I2sHalContextT).I2sHalPdmEnableRxChannel C.i2s_hal_pdm_enable_rx_channel +func (recv_ *I2sHalContextT) I2sHalPdmEnableRxChannel() { +} + +/** + * @brief Set tx slot to tdm mode + * + * @param hal Context of the HAL layer + * @param is_slave If is slave role + * @param slot_config General slot configuration pointer, but will specified to i2s tdm mode + */ +// llgo:link (*I2sHalContextT).I2sHalTdmSetTxSlot C.i2s_hal_tdm_set_tx_slot +func (recv_ *I2sHalContextT) I2sHalTdmSetTxSlot(is_slave bool, slot_cfg *I2sHalSlotConfigT) { +} + +/** + * @brief Set rx slot to tdm mode + * + * @param hal Context of the HAL layer + * @param is_slave If is slave role + * @param slot_config General slot configuration pointer, but will specified to i2s tdm mode + */ +// llgo:link (*I2sHalContextT).I2sHalTdmSetRxSlot C.i2s_hal_tdm_set_rx_slot +func (recv_ *I2sHalContextT) I2sHalTdmSetRxSlot(is_slave bool, slot_cfg *I2sHalSlotConfigT) { +} + +/** + * @brief Enable tx channel as tdm mode + * + * @param hal Context of the HAL layer + */ +// llgo:link (*I2sHalContextT).I2sHalTdmEnableTxChannel C.i2s_hal_tdm_enable_tx_channel +func (recv_ *I2sHalContextT) I2sHalTdmEnableTxChannel() { +} + +/** + * @brief Enable rx channel as tdm mode + * + * @param hal Context of the HAL layer + */ +// llgo:link (*I2sHalContextT).I2sHalTdmEnableRxChannel C.i2s_hal_tdm_enable_rx_channel +func (recv_ *I2sHalContextT) I2sHalTdmEnableRxChannel() { +} diff --git a/esp32/i2s_ll.go b/esp32/i2s_ll.go new file mode 100644 index 00000000..645df1a4 --- /dev/null +++ b/esp32/i2s_ll.go @@ -0,0 +1,7 @@ +package freertos + +import _ "unsafe" + +const I2S_LL_CLK_FRAC_DIV_N_MAX = 256 +const I2S_LL_CLK_FRAC_DIV_AB_MAX = 512 +const I2S_LL_SLOT_FRAME_BIT_MAX = 128 diff --git a/esp32/i2s_periph.go b/esp32/i2s_periph.go new file mode 100644 index 00000000..546eb665 --- /dev/null +++ b/esp32/i2s_periph.go @@ -0,0 +1,23 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* +Stores a bunch of per-I2S-peripheral data. +*/ +type I2sSignalConnT struct { + MckOutSig c.Uint8T + MckInSig c.Uint8T + MTxBckSig c.Uint8T + MRxBckSig c.Uint8T + MTxWsSig c.Uint8T + MRxWsSig c.Uint8T + STxBckSig c.Uint8T + SRxBckSig c.Uint8T + STxWsSig c.Uint8T + SRxWsSig c.Uint8T + Irq c.Uint8T +} diff --git a/esp32/i2s_reg.go b/esp32/i2s_reg.go new file mode 100644 index 00000000..4d8ef83f --- /dev/null +++ b/esp32/i2s_reg.go @@ -0,0 +1,371 @@ +package freertos + +import _ "unsafe" + +const I2S_TX_HUNG_INT_RAW_V = 0x1 +const I2S_TX_HUNG_INT_RAW_S = 3 +const I2S_RX_HUNG_INT_RAW_V = 0x1 +const I2S_RX_HUNG_INT_RAW_S = 2 +const I2S_TX_DONE_INT_RAW_V = 0x1 +const I2S_TX_DONE_INT_RAW_S = 1 +const I2S_RX_DONE_INT_RAW_V = 0x1 +const I2S_RX_DONE_INT_RAW_S = 0 +const I2S_TX_HUNG_INT_ST_V = 0x1 +const I2S_TX_HUNG_INT_ST_S = 3 +const I2S_RX_HUNG_INT_ST_V = 0x1 +const I2S_RX_HUNG_INT_ST_S = 2 +const I2S_TX_DONE_INT_ST_V = 0x1 +const I2S_TX_DONE_INT_ST_S = 1 +const I2S_RX_DONE_INT_ST_V = 0x1 +const I2S_RX_DONE_INT_ST_S = 0 +const I2S_TX_HUNG_INT_ENA_V = 0x1 +const I2S_TX_HUNG_INT_ENA_S = 3 +const I2S_RX_HUNG_INT_ENA_V = 0x1 +const I2S_RX_HUNG_INT_ENA_S = 2 +const I2S_TX_DONE_INT_ENA_V = 0x1 +const I2S_TX_DONE_INT_ENA_S = 1 +const I2S_RX_DONE_INT_ENA_V = 0x1 +const I2S_RX_DONE_INT_ENA_S = 0 +const I2S_TX_HUNG_INT_CLR_V = 0x1 +const I2S_TX_HUNG_INT_CLR_S = 3 +const I2S_RX_HUNG_INT_CLR_V = 0x1 +const I2S_RX_HUNG_INT_CLR_S = 2 +const I2S_TX_DONE_INT_CLR_V = 0x1 +const I2S_TX_DONE_INT_CLR_S = 1 +const I2S_RX_DONE_INT_CLR_V = 0x1 +const I2S_RX_DONE_INT_CLR_S = 0 +const I2S_RX_PDM_SINC_DSR_16_EN_V = 0x1 +const I2S_RX_PDM_SINC_DSR_16_EN_S = 22 +const I2S_RX_PDM2PCM_EN_V = 0x1 +const I2S_RX_PDM2PCM_EN_S = 21 +const I2S_RX_PDM_EN_V = 0x1 +const I2S_RX_PDM_EN_S = 20 +const I2S_RX_TDM_EN_V = 0x1 +const I2S_RX_TDM_EN_S = 19 +const I2S_RX_BIT_ORDER_V = 0x1 +const I2S_RX_BIT_ORDER_S = 18 +const I2S_RX_WS_IDLE_POL_V = 0x1 +const I2S_RX_WS_IDLE_POL_S = 17 +const I2S_RX_24_FILL_EN_V = 0x1 +const I2S_RX_24_FILL_EN_S = 16 +const I2S_RX_LEFT_ALIGN_V = 0x1 +const I2S_RX_LEFT_ALIGN_S = 15 +const I2S_RX_STOP_MODE = 0x00000003 +const I2S_RX_STOP_MODE_V = 0x3 +const I2S_RX_STOP_MODE_S = 13 +const I2S_RX_PCM_BYPASS_V = 0x1 +const I2S_RX_PCM_BYPASS_S = 12 +const I2S_RX_PCM_CONF = 0x00000003 +const I2S_RX_PCM_CONF_V = 0x3 +const I2S_RX_PCM_CONF_S = 10 +const I2S_RX_MONO_FST_VLD_V = 0x1 +const I2S_RX_MONO_FST_VLD_S = 9 +const I2S_RX_UPDATE_V = 0x1 +const I2S_RX_UPDATE_S = 8 +const I2S_RX_BIG_ENDIAN_V = 0x1 +const I2S_RX_BIG_ENDIAN_S = 7 +const I2S_RX_MONO_V = 0x1 +const I2S_RX_MONO_S = 5 +const I2S_RX_SLAVE_MOD_V = 0x1 +const I2S_RX_SLAVE_MOD_S = 3 +const I2S_RX_START_V = 0x1 +const I2S_RX_START_S = 2 +const I2S_RX_FIFO_RESET_V = 0x1 +const I2S_RX_FIFO_RESET_S = 1 +const I2S_RX_RESET_V = 0x1 +const I2S_RX_RESET_S = 0 +const I2S_SIG_LOOPBACK_V = 0x1 +const I2S_SIG_LOOPBACK_S = 27 +const I2S_TX_CHAN_MOD = 0x00000007 +const I2S_TX_CHAN_MOD_V = 0x7 +const I2S_TX_CHAN_MOD_S = 24 +const I2S_TX_PDM_EN_V = 0x1 +const I2S_TX_PDM_EN_S = 20 +const I2S_TX_TDM_EN_V = 0x1 +const I2S_TX_TDM_EN_S = 19 +const I2S_TX_BIT_ORDER_V = 0x1 +const I2S_TX_BIT_ORDER_S = 18 +const I2S_TX_WS_IDLE_POL_V = 0x1 +const I2S_TX_WS_IDLE_POL_S = 17 +const I2S_TX_24_FILL_EN_V = 0x1 +const I2S_TX_24_FILL_EN_S = 16 +const I2S_TX_LEFT_ALIGN_V = 0x1 +const I2S_TX_LEFT_ALIGN_S = 15 +const I2S_TX_STOP_EN_V = 0x1 +const I2S_TX_STOP_EN_S = 13 +const I2S_TX_PCM_BYPASS_V = 0x1 +const I2S_TX_PCM_BYPASS_S = 12 +const I2S_TX_PCM_CONF = 0x00000003 +const I2S_TX_PCM_CONF_V = 0x3 +const I2S_TX_PCM_CONF_S = 10 +const I2S_TX_MONO_FST_VLD_V = 0x1 +const I2S_TX_MONO_FST_VLD_S = 9 +const I2S_TX_UPDATE_V = 0x1 +const I2S_TX_UPDATE_S = 8 +const I2S_TX_BIG_ENDIAN_V = 0x1 +const I2S_TX_BIG_ENDIAN_S = 7 +const I2S_TX_CHAN_EQUAL_V = 0x1 +const I2S_TX_CHAN_EQUAL_S = 6 +const I2S_TX_MONO_V = 0x1 +const I2S_TX_MONO_S = 5 +const I2S_TX_SLAVE_MOD_V = 0x1 +const I2S_TX_SLAVE_MOD_S = 3 +const I2S_TX_START_V = 0x1 +const I2S_TX_START_S = 2 +const I2S_TX_FIFO_RESET_V = 0x1 +const I2S_TX_FIFO_RESET_S = 1 +const I2S_TX_RESET_V = 0x1 +const I2S_TX_RESET_S = 0 +const I2S_RX_MSB_SHIFT_V = 0x1 +const I2S_RX_MSB_SHIFT_S = 29 +const I2S_RX_TDM_CHAN_BITS = 0x0000001F +const I2S_RX_TDM_CHAN_BITS_V = 0x1F +const I2S_RX_TDM_CHAN_BITS_S = 24 +const I2S_RX_HALF_SAMPLE_BITS = 0x0000003F +const I2S_RX_HALF_SAMPLE_BITS_V = 0x3F +const I2S_RX_HALF_SAMPLE_BITS_S = 18 +const I2S_RX_BITS_MOD = 0x0000001F +const I2S_RX_BITS_MOD_V = 0x1F +const I2S_RX_BITS_MOD_S = 13 +const I2S_RX_BCK_DIV_NUM = 0x0000003F +const I2S_RX_BCK_DIV_NUM_V = 0x3F +const I2S_RX_BCK_DIV_NUM_S = 7 +const I2S_RX_TDM_WS_WIDTH = 0x0000007F +const I2S_RX_TDM_WS_WIDTH_V = 0x7F +const I2S_RX_TDM_WS_WIDTH_S = 0 +const I2S_TX_BCK_NO_DLY_V = 0x1 +const I2S_TX_BCK_NO_DLY_S = 30 +const I2S_TX_MSB_SHIFT_V = 0x1 +const I2S_TX_MSB_SHIFT_S = 29 +const I2S_TX_TDM_CHAN_BITS = 0x0000001F +const I2S_TX_TDM_CHAN_BITS_V = 0x1F +const I2S_TX_TDM_CHAN_BITS_S = 24 +const I2S_TX_HALF_SAMPLE_BITS = 0x0000003F +const I2S_TX_HALF_SAMPLE_BITS_V = 0x3F +const I2S_TX_HALF_SAMPLE_BITS_S = 18 +const I2S_TX_BITS_MOD = 0x0000001F +const I2S_TX_BITS_MOD_V = 0x1F +const I2S_TX_BITS_MOD_S = 13 +const I2S_TX_BCK_DIV_NUM = 0x0000003F +const I2S_TX_BCK_DIV_NUM_V = 0x3F +const I2S_TX_BCK_DIV_NUM_S = 7 +const I2S_TX_TDM_WS_WIDTH = 0x0000007F +const I2S_TX_TDM_WS_WIDTH_V = 0x7F +const I2S_TX_TDM_WS_WIDTH_S = 0 +const I2S_MCLK_SEL_V = 0x1 +const I2S_MCLK_SEL_S = 29 +const I2S_RX_CLK_SEL = 0x00000003 +const I2S_RX_CLK_SEL_V = 0x3 +const I2S_RX_CLK_SEL_S = 27 +const I2S_RX_CLK_ACTIVE_V = 0x1 +const I2S_RX_CLK_ACTIVE_S = 26 +const I2S_RX_CLKM_DIV_NUM = 0x000000FF +const I2S_RX_CLKM_DIV_NUM_V = 0xFF +const I2S_RX_CLKM_DIV_NUM_S = 0 +const I2S_CLK_EN_V = 0x1 +const I2S_CLK_EN_S = 29 +const I2S_TX_CLK_SEL = 0x00000003 +const I2S_TX_CLK_SEL_V = 0x3 +const I2S_TX_CLK_SEL_S = 27 +const I2S_TX_CLK_ACTIVE_V = 0x1 +const I2S_TX_CLK_ACTIVE_S = 26 +const I2S_TX_CLKM_DIV_NUM = 0x000000FF +const I2S_TX_CLKM_DIV_NUM_V = 0xFF +const I2S_TX_CLKM_DIV_NUM_S = 0 +const I2S_RX_CLKM_DIV_YN1_V = 0x1 +const I2S_RX_CLKM_DIV_YN1_S = 27 +const I2S_RX_CLKM_DIV_X = 0x000001FF +const I2S_RX_CLKM_DIV_X_V = 0x1FF +const I2S_RX_CLKM_DIV_X_S = 18 +const I2S_RX_CLKM_DIV_Y = 0x000001FF +const I2S_RX_CLKM_DIV_Y_V = 0x1FF +const I2S_RX_CLKM_DIV_Y_S = 9 +const I2S_RX_CLKM_DIV_Z = 0x000001FF +const I2S_RX_CLKM_DIV_Z_V = 0x1FF +const I2S_RX_CLKM_DIV_Z_S = 0 +const I2S_TX_CLKM_DIV_YN1_V = 0x1 +const I2S_TX_CLKM_DIV_YN1_S = 27 +const I2S_TX_CLKM_DIV_X = 0x000001FF +const I2S_TX_CLKM_DIV_X_V = 0x1FF +const I2S_TX_CLKM_DIV_X_S = 18 +const I2S_TX_CLKM_DIV_Y = 0x000001FF +const I2S_TX_CLKM_DIV_Y_V = 0x1FF +const I2S_TX_CLKM_DIV_Y_S = 9 +const I2S_TX_CLKM_DIV_Z = 0x000001FF +const I2S_TX_CLKM_DIV_Z_V = 0x1FF +const I2S_TX_CLKM_DIV_Z_S = 0 +const I2S_PCM2PDM_CONV_EN_V = 0x1 +const I2S_PCM2PDM_CONV_EN_S = 25 +const I2S_TX_PDM_DAC_MODE_EN_V = 0x1 +const I2S_TX_PDM_DAC_MODE_EN_S = 24 +const I2S_TX_PDM_DAC_2OUT_EN_V = 0x1 +const I2S_TX_PDM_DAC_2OUT_EN_S = 23 +const I2S_TX_PDM_SIGMADELTA_DITHER_V = 0x1 +const I2S_TX_PDM_SIGMADELTA_DITHER_S = 22 +const I2S_TX_PDM_SIGMADELTA_DITHER2_V = 0x1 +const I2S_TX_PDM_SIGMADELTA_DITHER2_S = 21 +const I2S_TX_PDM_SIGMADELTA_IN_SHIFT = 0x00000003 +const I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V = 0x3 +const I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S = 19 +const I2S_TX_PDM_SINC_IN_SHIFT = 0x00000003 +const I2S_TX_PDM_SINC_IN_SHIFT_V = 0x3 +const I2S_TX_PDM_SINC_IN_SHIFT_S = 17 +const I2S_TX_PDM_LP_IN_SHIFT = 0x00000003 +const I2S_TX_PDM_LP_IN_SHIFT_V = 0x3 +const I2S_TX_PDM_LP_IN_SHIFT_S = 15 +const I2S_TX_PDM_HP_IN_SHIFT = 0x00000003 +const I2S_TX_PDM_HP_IN_SHIFT_V = 0x3 +const I2S_TX_PDM_HP_IN_SHIFT_S = 13 +const I2S_TX_PDM_PRESCALE = 0x000000FF +const I2S_TX_PDM_PRESCALE_V = 0xFF +const I2S_TX_PDM_PRESCALE_S = 5 +const I2S_TX_PDM_SINC_OSR2 = 0x0000000F +const I2S_TX_PDM_SINC_OSR2_V = 0xF +const I2S_TX_PDM_SINC_OSR2_S = 1 +const I2S_TX_PDM_HP_BYPASS_V = 0x1 +const I2S_TX_PDM_HP_BYPASS_S = 0 +const I2S_TX_IIR_HP_MULT12_0 = 0x00000007 +const I2S_TX_IIR_HP_MULT12_0_V = 0x7 +const I2S_TX_IIR_HP_MULT12_0_S = 23 +const I2S_TX_IIR_HP_MULT12_5 = 0x00000007 +const I2S_TX_IIR_HP_MULT12_5_V = 0x7 +const I2S_TX_IIR_HP_MULT12_5_S = 20 +const I2S_TX_PDM_FS = 0x000003FF +const I2S_TX_PDM_FS_V = 0x3FF +const I2S_TX_PDM_FS_S = 10 +const I2S_TX_PDM_FP = 0x000003FF +const I2S_TX_PDM_FP_V = 0x3FF +const I2S_TX_PDM_FP_S = 0 +const I2S_RX_TDM_TOT_CHAN_NUM = 0x0000000F +const I2S_RX_TDM_TOT_CHAN_NUM_V = 0xF +const I2S_RX_TDM_TOT_CHAN_NUM_S = 16 +const I2S_RX_TDM_CHAN15_EN_V = 0x1 +const I2S_RX_TDM_CHAN15_EN_S = 15 +const I2S_RX_TDM_CHAN14_EN_V = 0x1 +const I2S_RX_TDM_CHAN14_EN_S = 14 +const I2S_RX_TDM_CHAN13_EN_V = 0x1 +const I2S_RX_TDM_CHAN13_EN_S = 13 +const I2S_RX_TDM_CHAN12_EN_V = 0x1 +const I2S_RX_TDM_CHAN12_EN_S = 12 +const I2S_RX_TDM_CHAN11_EN_V = 0x1 +const I2S_RX_TDM_CHAN11_EN_S = 11 +const I2S_RX_TDM_CHAN10_EN_V = 0x1 +const I2S_RX_TDM_CHAN10_EN_S = 10 +const I2S_RX_TDM_CHAN9_EN_V = 0x1 +const I2S_RX_TDM_CHAN9_EN_S = 9 +const I2S_RX_TDM_CHAN8_EN_V = 0x1 +const I2S_RX_TDM_CHAN8_EN_S = 8 +const I2S_RX_TDM_PDM_CHAN7_EN_V = 0x1 +const I2S_RX_TDM_PDM_CHAN7_EN_S = 7 +const I2S_RX_TDM_PDM_CHAN6_EN_V = 0x1 +const I2S_RX_TDM_PDM_CHAN6_EN_S = 6 +const I2S_RX_TDM_PDM_CHAN5_EN_V = 0x1 +const I2S_RX_TDM_PDM_CHAN5_EN_S = 5 +const I2S_RX_TDM_PDM_CHAN4_EN_V = 0x1 +const I2S_RX_TDM_PDM_CHAN4_EN_S = 4 +const I2S_RX_TDM_PDM_CHAN3_EN_V = 0x1 +const I2S_RX_TDM_PDM_CHAN3_EN_S = 3 +const I2S_RX_TDM_PDM_CHAN2_EN_V = 0x1 +const I2S_RX_TDM_PDM_CHAN2_EN_S = 2 +const I2S_RX_TDM_PDM_CHAN1_EN_V = 0x1 +const I2S_RX_TDM_PDM_CHAN1_EN_S = 1 +const I2S_RX_TDM_PDM_CHAN0_EN_V = 0x1 +const I2S_RX_TDM_PDM_CHAN0_EN_S = 0 +const I2S_TX_TDM_SKIP_MSK_EN_V = 0x1 +const I2S_TX_TDM_SKIP_MSK_EN_S = 20 +const I2S_TX_TDM_TOT_CHAN_NUM = 0x0000000F +const I2S_TX_TDM_TOT_CHAN_NUM_V = 0xF +const I2S_TX_TDM_TOT_CHAN_NUM_S = 16 +const I2S_TX_TDM_CHAN15_EN_V = 0x1 +const I2S_TX_TDM_CHAN15_EN_S = 15 +const I2S_TX_TDM_CHAN14_EN_V = 0x1 +const I2S_TX_TDM_CHAN14_EN_S = 14 +const I2S_TX_TDM_CHAN13_EN_V = 0x1 +const I2S_TX_TDM_CHAN13_EN_S = 13 +const I2S_TX_TDM_CHAN12_EN_V = 0x1 +const I2S_TX_TDM_CHAN12_EN_S = 12 +const I2S_TX_TDM_CHAN11_EN_V = 0x1 +const I2S_TX_TDM_CHAN11_EN_S = 11 +const I2S_TX_TDM_CHAN10_EN_V = 0x1 +const I2S_TX_TDM_CHAN10_EN_S = 10 +const I2S_TX_TDM_CHAN9_EN_V = 0x1 +const I2S_TX_TDM_CHAN9_EN_S = 9 +const I2S_TX_TDM_CHAN8_EN_V = 0x1 +const I2S_TX_TDM_CHAN8_EN_S = 8 +const I2S_TX_TDM_CHAN7_EN_V = 0x1 +const I2S_TX_TDM_CHAN7_EN_S = 7 +const I2S_TX_TDM_CHAN6_EN_V = 0x1 +const I2S_TX_TDM_CHAN6_EN_S = 6 +const I2S_TX_TDM_CHAN5_EN_V = 0x1 +const I2S_TX_TDM_CHAN5_EN_S = 5 +const I2S_TX_TDM_CHAN4_EN_V = 0x1 +const I2S_TX_TDM_CHAN4_EN_S = 4 +const I2S_TX_TDM_CHAN3_EN_V = 0x1 +const I2S_TX_TDM_CHAN3_EN_S = 3 +const I2S_TX_TDM_CHAN2_EN_V = 0x1 +const I2S_TX_TDM_CHAN2_EN_S = 2 +const I2S_TX_TDM_CHAN1_EN_V = 0x1 +const I2S_TX_TDM_CHAN1_EN_S = 1 +const I2S_TX_TDM_CHAN0_EN_V = 0x1 +const I2S_TX_TDM_CHAN0_EN_S = 0 +const I2S_RX_BCK_IN_DM = 0x00000003 +const I2S_RX_BCK_IN_DM_V = 0x3 +const I2S_RX_BCK_IN_DM_S = 28 +const I2S_RX_WS_IN_DM = 0x00000003 +const I2S_RX_WS_IN_DM_V = 0x3 +const I2S_RX_WS_IN_DM_S = 24 +const I2S_RX_BCK_OUT_DM = 0x00000003 +const I2S_RX_BCK_OUT_DM_V = 0x3 +const I2S_RX_BCK_OUT_DM_S = 20 +const I2S_RX_WS_OUT_DM = 0x00000003 +const I2S_RX_WS_OUT_DM_V = 0x3 +const I2S_RX_WS_OUT_DM_S = 16 +const I2S_RX_SD3_IN_DM = 0x00000003 +const I2S_RX_SD3_IN_DM_V = 0x3 +const I2S_RX_SD3_IN_DM_S = 12 +const I2S_RX_SD2_IN_DM = 0x00000003 +const I2S_RX_SD2_IN_DM_V = 0x3 +const I2S_RX_SD2_IN_DM_S = 8 +const I2S_RX_SD1_IN_DM = 0x00000003 +const I2S_RX_SD1_IN_DM_V = 0x3 +const I2S_RX_SD1_IN_DM_S = 4 +const I2S_RX_SD_IN_DM = 0x00000003 +const I2S_RX_SD_IN_DM_V = 0x3 +const I2S_RX_SD_IN_DM_S = 0 +const I2S_TX_BCK_IN_DM = 0x00000003 +const I2S_TX_BCK_IN_DM_V = 0x3 +const I2S_TX_BCK_IN_DM_S = 28 +const I2S_TX_WS_IN_DM = 0x00000003 +const I2S_TX_WS_IN_DM_V = 0x3 +const I2S_TX_WS_IN_DM_S = 24 +const I2S_TX_BCK_OUT_DM = 0x00000003 +const I2S_TX_BCK_OUT_DM_V = 0x3 +const I2S_TX_BCK_OUT_DM_S = 20 +const I2S_TX_WS_OUT_DM = 0x00000003 +const I2S_TX_WS_OUT_DM_V = 0x3 +const I2S_TX_WS_OUT_DM_S = 16 +const I2S_TX_SD1_OUT_DM = 0x00000003 +const I2S_TX_SD1_OUT_DM_V = 0x3 +const I2S_TX_SD1_OUT_DM_S = 4 +const I2S_TX_SD_OUT_DM = 0x00000003 +const I2S_TX_SD_OUT_DM_V = 0x3 +const I2S_TX_SD_OUT_DM_S = 0 +const I2S_LC_FIFO_TIMEOUT_ENA_V = 0x1 +const I2S_LC_FIFO_TIMEOUT_ENA_S = 11 +const I2S_LC_FIFO_TIMEOUT_SHIFT = 0x00000007 +const I2S_LC_FIFO_TIMEOUT_SHIFT_V = 0x7 +const I2S_LC_FIFO_TIMEOUT_SHIFT_S = 8 +const I2S_LC_FIFO_TIMEOUT = 0x000000FF +const I2S_LC_FIFO_TIMEOUT_V = 0xFF +const I2S_LC_FIFO_TIMEOUT_S = 0 +const I2S_RX_EOF_NUM = 0x00000FFF +const I2S_RX_EOF_NUM_V = 0xFFF +const I2S_RX_EOF_NUM_S = 0 +const I2S_SINGLE_DATA = 0xFFFFFFFF +const I2S_SINGLE_DATA_V = 0xFFFFFFFF +const I2S_SINGLE_DATA_S = 0 +const I2S_TX_IDLE_V = 0x1 +const I2S_TX_IDLE_S = 0 +const I2S_DATE = 0x0FFFFFFF +const I2S_DATE_V = 0xFFFFFFF +const I2S_DATE_S = 0 diff --git a/esp32/i2s_struct.go b/esp32/i2s_struct.go new file mode 100644 index 00000000..6641fbff --- /dev/null +++ b/esp32/i2s_struct.go @@ -0,0 +1,87 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type I2sDevS struct { + Reserved0 c.Uint32T + Reserved4 c.Uint32T + Reserved8 c.Uint32T + IntRaw struct { + Val c.Uint32T + } + IntSt struct { + Val c.Uint32T + } + IntEna struct { + Val c.Uint32T + } + IntClr struct { + Val c.Uint32T + } + Reserved1c c.Uint32T + RxConf struct { + Val c.Uint32T + } + TxConf struct { + Val c.Uint32T + } + RxConf1 struct { + Val c.Uint32T + } + TxConf1 struct { + Val c.Uint32T + } + RxClkmConf struct { + Val c.Uint32T + } + TxClkmConf struct { + Val c.Uint32T + } + RxClkmDivConf struct { + Val c.Uint32T + } + TxClkmDivConf struct { + Val c.Uint32T + } + TxPcm2pdmConf struct { + Val c.Uint32T + } + TxPcm2pdmConf1 struct { + Val c.Uint32T + } + Reserved48 c.Uint32T + Reserved4c c.Uint32T + RxTdmCtrl struct { + Val c.Uint32T + } + TxTdmCtrl struct { + Val c.Uint32T + } + RxTiming struct { + Val c.Uint32T + } + TxTiming struct { + Val c.Uint32T + } + LcHungConf struct { + Val c.Uint32T + } + RxEofNum struct { + Val c.Uint32T + } + ConfSingleData c.Uint32T + State struct { + Val c.Uint32T + } + Reserved70 c.Uint32T + Reserved74 c.Uint32T + Reserved78 c.Uint32T + Reserved7c c.Uint32T + Date struct { + Val c.Uint32T + } +} +type I2sDevT I2sDevS diff --git a/esp32/i2s_types.go b/esp32/i2s_types.go new file mode 100644 index 00000000..ae14ce34 --- /dev/null +++ b/esp32/i2s_types.go @@ -0,0 +1,144 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type I2sSlotModeT c.Int + +const ( + I2S_SLOT_MODE_MONO I2sSlotModeT = 1 + I2S_SLOT_MODE_STEREO I2sSlotModeT = 2 +) + +type I2sDirT c.Int + +const ( + I2S_DIR_RX I2sDirT = 1 + I2S_DIR_TX I2sDirT = 2 +) + +type I2sRoleT c.Int + +const ( + I2S_ROLE_MASTER I2sRoleT = 0 + I2S_ROLE_SLAVE I2sRoleT = 1 +) + +type I2sDataBitWidthT c.Int + +const ( + I2S_DATA_BIT_WIDTH_8BIT I2sDataBitWidthT = 8 + I2S_DATA_BIT_WIDTH_16BIT I2sDataBitWidthT = 16 + I2S_DATA_BIT_WIDTH_24BIT I2sDataBitWidthT = 24 + I2S_DATA_BIT_WIDTH_32BIT I2sDataBitWidthT = 32 +) + +type I2sSlotBitWidthT c.Int + +const ( + I2S_SLOT_BIT_WIDTH_AUTO I2sSlotBitWidthT = 0 + I2S_SLOT_BIT_WIDTH_8BIT I2sSlotBitWidthT = 8 + I2S_SLOT_BIT_WIDTH_16BIT I2sSlotBitWidthT = 16 + I2S_SLOT_BIT_WIDTH_24BIT I2sSlotBitWidthT = 24 + I2S_SLOT_BIT_WIDTH_32BIT I2sSlotBitWidthT = 32 +) + +type I2sClockSrcT SocPeriphI2sClkSrcT +type I2sPcmCompressT c.Int + +const ( + I2S_PCM_DISABLE I2sPcmCompressT = 0 + I2S_PCM_A_DECOMPRESS I2sPcmCompressT = 1 + I2S_PCM_A_COMPRESS I2sPcmCompressT = 2 + I2S_PCM_U_DECOMPRESS I2sPcmCompressT = 3 + I2S_PCM_U_COMPRESS I2sPcmCompressT = 4 +) + +type I2sPdmDsrT c.Int + +const ( + I2S_PDM_DSR_8S I2sPdmDsrT = 0 + I2S_PDM_DSR_16S I2sPdmDsrT = 1 + I2S_PDM_DSR_MAX I2sPdmDsrT = 2 +) + +type I2sPdmSigScaleT c.Int + +const ( + I2S_PDM_SIG_SCALING_DIV_2 I2sPdmSigScaleT = 0 + I2S_PDM_SIG_SCALING_MUL_1 I2sPdmSigScaleT = 1 + I2S_PDM_SIG_SCALING_MUL_2 I2sPdmSigScaleT = 2 + I2S_PDM_SIG_SCALING_MUL_4 I2sPdmSigScaleT = 3 +) + +type I2sPdmTxLineModeT c.Int + +const ( + I2S_PDM_TX_ONE_LINE_CODEC I2sPdmTxLineModeT = 0 + I2S_PDM_TX_ONE_LINE_DAC I2sPdmTxLineModeT = 1 + I2S_PDM_TX_TWO_LINE_DAC I2sPdmTxLineModeT = 2 +) + +type I2sStdSlotMaskT c.Int + +const ( + I2S_STD_SLOT_LEFT I2sStdSlotMaskT = 1 + I2S_STD_SLOT_RIGHT I2sStdSlotMaskT = 2 + I2S_STD_SLOT_BOTH I2sStdSlotMaskT = 3 +) + +type I2sPdmSlotMaskT c.Int + +const ( + I2S_PDM_SLOT_RIGHT I2sPdmSlotMaskT = 1 + I2S_PDM_SLOT_LEFT I2sPdmSlotMaskT = 2 + I2S_PDM_SLOT_BOTH I2sPdmSlotMaskT = 3 + I2S_PDM_RX_LINE0_SLOT_RIGHT I2sPdmSlotMaskT = 1 + I2S_PDM_RX_LINE0_SLOT_LEFT I2sPdmSlotMaskT = 2 + I2S_PDM_RX_LINE1_SLOT_RIGHT I2sPdmSlotMaskT = 4 + I2S_PDM_RX_LINE1_SLOT_LEFT I2sPdmSlotMaskT = 8 + I2S_PDM_RX_LINE2_SLOT_RIGHT I2sPdmSlotMaskT = 16 + I2S_PDM_RX_LINE2_SLOT_LEFT I2sPdmSlotMaskT = 32 + I2S_PDM_RX_LINE3_SLOT_RIGHT I2sPdmSlotMaskT = 64 + I2S_PDM_RX_LINE3_SLOT_LEFT I2sPdmSlotMaskT = 128 + I2S_PDM_LINE_SLOT_ALL I2sPdmSlotMaskT = 255 +) + +type I2sTdmSlotMaskT c.Int + +const ( + I2S_TDM_SLOT0 I2sTdmSlotMaskT = 1 + I2S_TDM_SLOT1 I2sTdmSlotMaskT = 2 + I2S_TDM_SLOT2 I2sTdmSlotMaskT = 4 + I2S_TDM_SLOT3 I2sTdmSlotMaskT = 8 + I2S_TDM_SLOT4 I2sTdmSlotMaskT = 16 + I2S_TDM_SLOT5 I2sTdmSlotMaskT = 32 + I2S_TDM_SLOT6 I2sTdmSlotMaskT = 64 + I2S_TDM_SLOT7 I2sTdmSlotMaskT = 128 + I2S_TDM_SLOT8 I2sTdmSlotMaskT = 256 + I2S_TDM_SLOT9 I2sTdmSlotMaskT = 512 + I2S_TDM_SLOT10 I2sTdmSlotMaskT = 1024 + I2S_TDM_SLOT11 I2sTdmSlotMaskT = 2048 + I2S_TDM_SLOT12 I2sTdmSlotMaskT = 4096 + I2S_TDM_SLOT13 I2sTdmSlotMaskT = 8192 + I2S_TDM_SLOT14 I2sTdmSlotMaskT = 16384 + I2S_TDM_SLOT15 I2sTdmSlotMaskT = 32768 +) + +type I2sEtmEventTypeT c.Int + +const ( + I2S_ETM_EVENT_DONE I2sEtmEventTypeT = 0 + I2S_ETM_EVENT_REACH_THRESH I2sEtmEventTypeT = 1 + I2S_ETM_EVENT_MAX I2sEtmEventTypeT = 2 +) + +type I2sEtmTaskTypeT c.Int + +const ( + I2S_ETM_TASK_START I2sEtmTaskTypeT = 0 + I2S_ETM_TASK_STOP I2sEtmTaskTypeT = 1 + I2S_ETM_TASK_MAX I2sEtmTaskTypeT = 2 +) diff --git a/esp32/idf_additions.go b/esp32/idf_additions.go new file mode 100644 index 00000000..3115aa0b --- /dev/null +++ b/esp32/idf_additions.go @@ -0,0 +1,275 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Create a new task that is pinned to a particular core + * + * This function is similar to xTaskCreate(), but allows the creation of a pinned + * task. The task's pinned core is specified by the xCoreID argument. If xCoreID + * is set to tskNO_AFFINITY, then the task is unpinned and can run on any core. + * + * @note If ( configNUMBER_OF_CORES == 1 ), setting xCoreID to tskNO_AFFINITY will be + * be treated as 0. + * + * @param pxTaskCode Pointer to the task entry function. + * @param pcName A descriptive name for the task. + * @param ulStackDepth The size of the task stack specified as the NUMBER OF + * BYTES. Note that this differs from vanilla FreeRTOS. + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * @param uxPriority The priority at which the task should run. + * @param pxCreatedTask Used to pass back a handle by which the created task can + * be referenced. + * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if + * the task has no core affinity. + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + */ +//go:linkname XTaskCreatePinnedToCore C.xTaskCreatePinnedToCore +func XTaskCreatePinnedToCore(pxTaskCode c.Int, pcName *c.Char, ulStackDepth c.Uint32T, pvParameters c.Pointer, uxPriority UBaseTypeT, pxCreatedTask *TaskHandleT, xCoreID BaseTypeT) BaseTypeT + +/** + * @brief Create a new static task that is pinned to a particular core + * + * This function is similar to xTaskCreateStatic(), but allows the creation of a + * pinned task. The task's pinned core is specified by the xCoreID argument. If + * xCoreID is set to tskNO_AFFINITY, then the task is unpinned and can run on any + * core. + * + * @note If ( configNUMBER_OF_CORES == 1 ), setting xCoreID to tskNO_AFFINITY will be + * be treated as 0. + * + * @param pxTaskCode Pointer to the task entry function. + * @param pcName A descriptive name for the task. + * @param ulStackDepth The size of the task stack specified as the NUMBER OF + * BYTES. Note that this differs from vanilla FreeRTOS. + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * @param uxPriority The priority at which the task should run. + * @param puxStackBuffer Must point to a StackType_t array that has at least + * ulStackDepth indexes + * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will + * then be used to hold the task's data structures, + * @param xCoreID The core to which the task is pinned to, or tskNO_AFFINITY if + * the task has no core affinity. + * @return The task handle if the task was created, NULL otherwise. + */ +//go:linkname XTaskCreateStaticPinnedToCore C.xTaskCreateStaticPinnedToCore +func XTaskCreateStaticPinnedToCore(pxTaskCode c.Int, pcName *c.Char, ulStackDepth c.Uint32T, pvParameters c.Pointer, uxPriority UBaseTypeT, puxStackBuffer *StackTypeT, pxTaskBuffer *StaticTaskT, xCoreID BaseTypeT) TaskHandleT + +/** + * @brief Get the current core ID of a particular task + * + * Helper function to get the core ID of a particular task. If the task is + * pinned to a particular core, the core ID is returned. If the task is not + * pinned to a particular core, tskNO_AFFINITY is returned. + * + * If CONFIG_FREERTOS_UNICORE is enabled, this function simply returns 0. + * + * [refactor-todo] See if this needs to be deprecated (IDF-8145)(IDF-8164) + * + * @note If CONFIG_FREERTOS_SMP is enabled, please call vTaskCoreAffinityGet() + * instead. + * @note In IDF FreerTOS when configNUMBER_OF_CORES == 1, this function will + * always return 0, + * @param xTask The task to query + * @return The task's core ID or tskNO_AFFINITY + */ +//go:linkname XTaskGetCoreID C.xTaskGetCoreID +func XTaskGetCoreID(xTask TaskHandleT) BaseTypeT + +/** + * @brief Get the handle of idle task for the given core. + * + * [refactor-todo] See if this needs to be deprecated (IDF-8145) + * + * @param xCoreID The core to query + * @return Handle of the idle task for the queried core + */ +// llgo:link BaseTypeT.XTaskGetIdleTaskHandleForCore C.xTaskGetIdleTaskHandleForCore +func (recv_ BaseTypeT) XTaskGetIdleTaskHandleForCore() TaskHandleT { + return nil +} + +/** + * @brief Get the handle of the task currently running on a certain core + * + * Because of the nature of SMP processing, there is no guarantee that this + * value will still be valid on return and should only be used for debugging + * purposes. + * + * [refactor-todo] See if this needs to be deprecated (IDF-8145) + * + * @param xCoreID The core to query + * @return Handle of the current task running on the queried core + */ +// llgo:link BaseTypeT.XTaskGetCurrentTaskHandleForCore C.xTaskGetCurrentTaskHandleForCore +func (recv_ BaseTypeT) XTaskGetCurrentTaskHandleForCore() TaskHandleT { + return nil +} + +/** + * Returns the start of the stack associated with xTask. + * + * Returns the lowest stack memory address, regardless of whether the stack + * grows up or down. + * + * [refactor-todo] Change return type to StackType_t (IDF-8158) + * + * @param xTask Handle of the task associated with the stack returned. + * Set xTask to NULL to return the stack of the calling task. + * + * @return A pointer to the start of the stack. + */ +//go:linkname PxTaskGetStackStart C.pxTaskGetStackStart +func PxTaskGetStackStart(xTask TaskHandleT) *c.Uint8T + +// llgo:type C +type TlsDeleteCallbackFunctionT func(c.Int, c.Pointer) + +/** + * Set local storage pointer and deletion callback. + * + * Each task contains an array of pointers that is dimensioned by the + * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. The + * kernel does not use the pointers itself, so the application writer can use + * the pointers for any purpose they wish. + * + * Local storage pointers set for a task can reference dynamically allocated + * resources. This function is similar to vTaskSetThreadLocalStoragePointer, but + * provides a way to release these resources when the task gets deleted. For + * each pointer, a callback function can be set. This function will be called + * when task is deleted, with the local storage pointer index and value as + * arguments. + * + * @param xTaskToSet Task to set thread local storage pointer for + * @param xIndex The index of the pointer to set, from 0 to + * configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1. + * @param pvValue Pointer value to set. + * @param pvDelCallback Function to call to dispose of the local storage + * pointer when the task is deleted. + */ +//go:linkname VTaskSetThreadLocalStoragePointerAndDelCallback C.vTaskSetThreadLocalStoragePointerAndDelCallback +func VTaskSetThreadLocalStoragePointerAndDelCallback(xTaskToSet TaskHandleT, xIndex BaseTypeT, pvValue c.Pointer, pvDelCallback TlsDeleteCallbackFunctionT) + +/** + * @brief Creates a pinned task where its stack has specific memory capabilities + * + * This function is similar to xTaskCreatePinnedToCore(), except that it allows + * the memory allocated for the task's stack to have specific capabilities + * (e.g., MALLOC_CAP_SPIRAM). + * + * However, the specified capabilities will NOT apply to the task's TCB as a TCB + * must always be in internal RAM. + * + * @param pvTaskCode Pointer to the task entry function + * @param pcName A descriptive name for the task + * @param usStackDepth The size of the task stack specified as the number of + * bytes + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * @param uxPriority The priority at which the task should run. + * @param pvCreatedTask Used to pass back a handle by which the created task can + * be referenced. + * @param xCoreID Core to which the task is pinned to, or tskNO_AFFINITY if + * unpinned. + * @param uxMemoryCaps Memory capabilities of the task stack's memory (see + * esp_heap_caps.h) + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + */ +//go:linkname XTaskCreatePinnedToCoreWithCaps C.xTaskCreatePinnedToCoreWithCaps +func XTaskCreatePinnedToCoreWithCaps(pvTaskCode c.Int, pcName *c.Char, usStackDepth c.Uint32T, pvParameters c.Pointer, uxPriority UBaseTypeT, pvCreatedTask *TaskHandleT, xCoreID BaseTypeT, uxMemoryCaps UBaseTypeT) BaseTypeT + +/** + * @brief Deletes a task previously created using xTaskCreateWithCaps() or + * xTaskCreatePinnedToCoreWithCaps() + * + * @note It is recommended to use this API to delete tasks from another task's + * context, rather than self-deletion. When the task is being deleted, it is vital + * to ensure that it is not running on another core. This API must not be called + * from an interrupt context. + * + * @param xTaskToDelete A handle to the task to be deleted + */ +//go:linkname VTaskDeleteWithCaps C.vTaskDeleteWithCaps +func VTaskDeleteWithCaps(xTaskToDelete TaskHandleT) + +/** + * @brief Creates a queue with specific memory capabilities + * + * This function is similar to xQueueCreate(), except that it allows the memory + * allocated for the queue to have specific capabilities (e.g., + * MALLOC_CAP_INTERNAL). + * + * @note A queue created using this function must only be deleted using + * vQueueDeleteWithCaps() + * @param uxQueueLength The maximum number of items that the queue can contain. + * @param uxItemSize The number of bytes each item in the queue will require. + * @param uxMemoryCaps Memory capabilities of the queue's memory (see + * esp_heap_caps.h) + * @return Handle to the created queue or NULL on failure. + */ +// llgo:link UBaseTypeT.XQueueCreateWithCaps C.xQueueCreateWithCaps +func (recv_ UBaseTypeT) XQueueCreateWithCaps(uxItemSize UBaseTypeT, uxMemoryCaps UBaseTypeT) QueueHandleT { + return nil +} + +/** + * @brief Deletes a queue previously created using xQueueCreateWithCaps() + * + * @param xQueue A handle to the queue to be deleted. + */ +//go:linkname VQueueDeleteWithCaps C.vQueueDeleteWithCaps +func VQueueDeleteWithCaps(xQueue QueueHandleT) + +// llgo:link UBaseTypeT.XSemaphoreCreateGenericWithCaps C.xSemaphoreCreateGenericWithCaps +func (recv_ UBaseTypeT) XSemaphoreCreateGenericWithCaps(uxInitialCount UBaseTypeT, ucQueueType c.Uint8T, uxMemoryCaps UBaseTypeT) SemaphoreHandleT { + return nil +} + +/** + * @brief Deletes a semaphore previously created using one of the + * xSemaphoreCreate...WithCaps() functions + * + * @param xSemaphore A handle to the semaphore to be deleted. + */ +//go:linkname VSemaphoreDeleteWithCaps C.vSemaphoreDeleteWithCaps +func VSemaphoreDeleteWithCaps(xSemaphore SemaphoreHandleT) + +//go:linkname XStreamBufferGenericCreateWithCaps C.xStreamBufferGenericCreateWithCaps +func XStreamBufferGenericCreateWithCaps(xBufferSizeBytes c.SizeT, xTriggerLevelBytes c.SizeT, xIsMessageBuffer BaseTypeT, uxMemoryCaps UBaseTypeT) StreamBufferHandleT + +//go:linkname VStreamBufferGenericDeleteWithCaps C.vStreamBufferGenericDeleteWithCaps +func VStreamBufferGenericDeleteWithCaps(xStreamBuffer StreamBufferHandleT, xIsMessageBuffer BaseTypeT) + +/** + * @brief Creates an event group with specific memory capabilities + * + * This function is similar to xEventGroupCreate(), except that it allows the + * memory allocated for the event group to have specific capabilities (e.g., + * MALLOC_CAP_INTERNAL). + * + * @note An event group created using this function must only be deleted using + * vEventGroupDeleteWithCaps() + * @param uxMemoryCaps Memory capabilities of the event group's memory (see + * esp_heap_caps.h) + * @return Handle to the created event group or NULL on failure. + */ +// llgo:link UBaseTypeT.XEventGroupCreateWithCaps C.xEventGroupCreateWithCaps +func (recv_ UBaseTypeT) XEventGroupCreateWithCaps() EventGroupHandleT { + return nil +} + +/** + * @brief Deletes an event group previously created using + * xEventGroupCreateWithCaps() + * + * @param xEventGroup A handle to the event group to be deleted. + */ +//go:linkname VEventGroupDeleteWithCaps C.vEventGroupDeleteWithCaps +func VEventGroupDeleteWithCaps(xEventGroup EventGroupHandleT) diff --git a/esp32/idmaasm.go b/esp32/idmaasm.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/idmaasm.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/ieee802154_periph.go b/esp32/ieee802154_periph.go new file mode 100644 index 00000000..29030e51 --- /dev/null +++ b/esp32/ieee802154_periph.go @@ -0,0 +1,11 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type Ieee802154ConnT struct { + Module PeriphModuleT + IrqId c.Int +} diff --git a/esp32/image_process.go b/esp32/image_process.go new file mode 100644 index 00000000..ec22e834 --- /dev/null +++ b/esp32/image_process.go @@ -0,0 +1,33 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type ImageProcessDriverS struct { + Unused [8]uint8 +} +type ImageProcessDriverT ImageProcessDriverS + +/** + * @brief Image process flow + * @note This API first reads the image header, then process the segments from the image header. + * This API can be further inserted with more steps about the image processing by registering + * more function pointer in `image_process_driver_t`. + * + * @return + * - ESP_OK + * - ESP_FAIL: image process flow fails + */ +//go:linkname ImageProcess C.image_process +func ImageProcess() EspErrT + +/** + * @brief get flash segments info, only available after image_process() has been called + * + * @param[out] out_drom_paddr_start drom paddr start + * @param[out] out_irom_paddr_start irom paddr start + */ +//go:linkname ImageProcessGetFlashSegmentsInfo C.image_process_get_flash_segments_info +func ImageProcessGetFlashSegmentsInfo(out_drom_paddr_start *c.Uint32T, out_irom_paddr_start *c.Uint32T) diff --git a/esp32/interrupt_controller_hal.go b/esp32/interrupt_controller_hal.go new file mode 100644 index 00000000..1fc4d54d --- /dev/null +++ b/esp32/interrupt_controller_hal.go @@ -0,0 +1,31 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type IntDescFlagT c.Int + +const ( + INTDESC_NORMAL IntDescFlagT = 0 + INTDESC_RESVD IntDescFlagT = 1 + INTDESC_SPECIAL IntDescFlagT = 2 +) + +type IntTypeT c.Int + +const ( + INTTP_LEVEL IntTypeT = 0 + INTTP_EDGE IntTypeT = 1 + INTTP_NA IntTypeT = 2 +) + +type IntDescT struct { + Level c.Int + Type IntTypeT + Cpuflags [2]IntDescFlagT +} + +// llgo:type C +type InterruptHandlerT func(c.Pointer) diff --git a/esp32/interrupt_core0_reg.go b/esp32/interrupt_core0_reg.go new file mode 100644 index 00000000..f5412c13 --- /dev/null +++ b/esp32/interrupt_core0_reg.go @@ -0,0 +1,318 @@ +package freertos + +import _ "unsafe" + +const INTERRUPT_CORE0_MAC_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_MAC_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_MAC_INTR_MAP_S = 0 +const INTERRUPT_CORE0_MAC_NMI_MAP = 0x0000001F +const INTERRUPT_CORE0_MAC_NMI_MAP_V = 0x1F +const INTERRUPT_CORE0_MAC_NMI_MAP_S = 0 +const INTERRUPT_CORE0_PWR_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_PWR_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_PWR_INTR_MAP_S = 0 +const INTERRUPT_CORE0_BB_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_BB_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_BB_INT_MAP_S = 0 +const INTERRUPT_CORE0_BT_MAC_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_BT_MAC_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_BT_MAC_INT_MAP_S = 0 +const INTERRUPT_CORE0_BT_BB_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_BT_BB_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_BT_BB_INT_MAP_S = 0 +const INTERRUPT_CORE0_BT_BB_NMI_MAP = 0x0000001F +const INTERRUPT_CORE0_BT_BB_NMI_MAP_V = 0x1F +const INTERRUPT_CORE0_BT_BB_NMI_MAP_S = 0 +const INTERRUPT_CORE0_RWBT_IRQ_MAP = 0x0000001F +const INTERRUPT_CORE0_RWBT_IRQ_MAP_V = 0x1F +const INTERRUPT_CORE0_RWBT_IRQ_MAP_S = 0 +const INTERRUPT_CORE0_RWBLE_IRQ_MAP = 0x0000001F +const INTERRUPT_CORE0_RWBLE_IRQ_MAP_V = 0x1F +const INTERRUPT_CORE0_RWBLE_IRQ_MAP_S = 0 +const INTERRUPT_CORE0_RWBT_NMI_MAP = 0x0000001F +const INTERRUPT_CORE0_RWBT_NMI_MAP_V = 0x1F +const INTERRUPT_CORE0_RWBT_NMI_MAP_S = 0 +const INTERRUPT_CORE0_RWBLE_NMI_MAP = 0x0000001F +const INTERRUPT_CORE0_RWBLE_NMI_MAP_V = 0x1F +const INTERRUPT_CORE0_RWBLE_NMI_MAP_S = 0 +const INTERRUPT_CORE0_I2C_MST_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_I2C_MST_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_I2C_MST_INT_MAP_S = 0 +const INTERRUPT_CORE0_SLC0_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_SLC0_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_SLC0_INTR_MAP_S = 0 +const INTERRUPT_CORE0_SLC1_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_SLC1_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_SLC1_INTR_MAP_S = 0 +const INTERRUPT_CORE0_UHCI0_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_UHCI0_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_UHCI0_INTR_MAP_S = 0 +const INTERRUPT_CORE0_UHCI1_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_UHCI1_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_UHCI1_INTR_MAP_S = 0 +const INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP = 0x0000001F +const INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V = 0x1F +const INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S = 0 +const INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP = 0x0000001F +const INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V = 0x1F +const INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S = 0 +const INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP = 0x0000001F +const INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V = 0x1F +const INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S = 0 +const INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP = 0x0000001F +const INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V = 0x1F +const INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S = 0 +const INTERRUPT_CORE0_SPI_INTR_1_MAP = 0x0000001F +const INTERRUPT_CORE0_SPI_INTR_1_MAP_V = 0x1F +const INTERRUPT_CORE0_SPI_INTR_1_MAP_S = 0 +const INTERRUPT_CORE0_SPI_INTR_2_MAP = 0x0000001F +const INTERRUPT_CORE0_SPI_INTR_2_MAP_V = 0x1F +const INTERRUPT_CORE0_SPI_INTR_2_MAP_S = 0 +const INTERRUPT_CORE0_SPI_INTR_3_MAP = 0x0000001F +const INTERRUPT_CORE0_SPI_INTR_3_MAP_V = 0x1F +const INTERRUPT_CORE0_SPI_INTR_3_MAP_S = 0 +const INTERRUPT_CORE0_SPI_INTR_4_MAP = 0x0000001F +const INTERRUPT_CORE0_SPI_INTR_4_MAP_V = 0x1F +const INTERRUPT_CORE0_SPI_INTR_4_MAP_S = 0 +const INTERRUPT_CORE0_LCD_CAM_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_LCD_CAM_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_LCD_CAM_INT_MAP_S = 0 +const INTERRUPT_CORE0_I2S0_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_I2S0_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_I2S0_INT_MAP_S = 0 +const INTERRUPT_CORE0_I2S1_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_I2S1_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_I2S1_INT_MAP_S = 0 +const INTERRUPT_CORE0_UART_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_UART_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_UART_INTR_MAP_S = 0 +const INTERRUPT_CORE0_UART1_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_UART1_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_UART1_INTR_MAP_S = 0 +const INTERRUPT_CORE0_UART2_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_UART2_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_UART2_INTR_MAP_S = 0 +const INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP = 0x0000001F +const INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V = 0x1F +const INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S = 0 +const INTERRUPT_CORE0_PWM0_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_PWM0_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_PWM0_INTR_MAP_S = 0 +const INTERRUPT_CORE0_PWM1_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_PWM1_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_PWM1_INTR_MAP_S = 0 +const INTERRUPT_CORE0_PWM2_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_PWM2_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_PWM2_INTR_MAP_S = 0 +const INTERRUPT_CORE0_PWM3_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_PWM3_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_PWM3_INTR_MAP_S = 0 +const INTERRUPT_CORE0_LEDC_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_LEDC_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_LEDC_INT_MAP_S = 0 +const INTERRUPT_CORE0_EFUSE_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_EFUSE_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_EFUSE_INT_MAP_S = 0 +const INTERRUPT_CORE0_CAN_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_CAN_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_CAN_INT_MAP_S = 0 +const INTERRUPT_CORE0_USB_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_USB_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_USB_INTR_MAP_S = 0 +const INTERRUPT_CORE0_RTC_CORE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S = 0 +const INTERRUPT_CORE0_RMT_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_RMT_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_RMT_INTR_MAP_S = 0 +const INTERRUPT_CORE0_PCNT_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_PCNT_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_PCNT_INTR_MAP_S = 0 +const INTERRUPT_CORE0_I2C_EXT0_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S = 0 +const INTERRUPT_CORE0_I2C_EXT1_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S = 0 +const INTERRUPT_CORE0_SPI2_DMA_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S = 0 +const INTERRUPT_CORE0_SPI3_DMA_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S = 0 +const INTERRUPT_CORE0_SPI4_DMA_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S = 0 +const INTERRUPT_CORE0_WDG_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_WDG_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_WDG_INT_MAP_S = 0 +const INTERRUPT_CORE0_TIMER_INT1_MAP = 0x0000001F +const INTERRUPT_CORE0_TIMER_INT1_MAP_V = 0x1F +const INTERRUPT_CORE0_TIMER_INT1_MAP_S = 0 +const INTERRUPT_CORE0_TIMER_INT2_MAP = 0x0000001F +const INTERRUPT_CORE0_TIMER_INT2_MAP_V = 0x1F +const INTERRUPT_CORE0_TIMER_INT2_MAP_S = 0 +const INTERRUPT_CORE0_TG_T0_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_TG_T0_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_TG_T0_INT_MAP_S = 0 +const INTERRUPT_CORE0_TG_T1_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_TG_T1_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_TG_T1_INT_MAP_S = 0 +const INTERRUPT_CORE0_TG_WDT_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_TG_WDT_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_TG_WDT_INT_MAP_S = 0 +const INTERRUPT_CORE0_TG1_T0_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_TG1_T0_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_TG1_T0_INT_MAP_S = 0 +const INTERRUPT_CORE0_TG1_T1_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_TG1_T1_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_TG1_T1_INT_MAP_S = 0 +const INTERRUPT_CORE0_TG1_WDT_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_TG1_WDT_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_TG1_WDT_INT_MAP_S = 0 +const INTERRUPT_CORE0_CACHE_IA_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_CACHE_IA_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_CACHE_IA_INT_MAP_S = 0 +const INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S = 0 +const INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S = 0 +const INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S = 0 +const INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S = 0 +const INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S = 0 +const INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S = 0 +const INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S = 0 +const INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S = 0 +const INTERRUPT_CORE0_APB_ADC_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_APB_ADC_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_APB_ADC_INT_MAP_S = 0 +const INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_S = 0 +const INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_S = 0 +const INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_S = 0 +const INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_S = 0 +const INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_S = 0 +const INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_S = 0 +const INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_S = 0 +const INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_S = 0 +const INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_S = 0 +const INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_S = 0 +const INTERRUPT_CORE0_RSA_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_RSA_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_RSA_INT_MAP_S = 0 +const INTERRUPT_CORE0_AES_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_AES_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_AES_INT_MAP_S = 0 +const INTERRUPT_CORE0_SHA_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_SHA_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_SHA_INT_MAP_S = 0 +const INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP = 0x0000001F +const INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V = 0x1F +const INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S = 0 +const INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP = 0x0000001F +const INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V = 0x1F +const INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S = 0 +const INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP = 0x0000001F +const INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V = 0x1F +const INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S = 0 +const INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP = 0x0000001F +const INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V = 0x1F +const INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S = 0 +const INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S = 0 +const INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S = 0 +const INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S = 0 +const INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S = 0 +const INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S = 0 +const INTERRUPT_CORE0_USB_DEVICE_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S = 0 +const INTERRUPT_CORE0_PERI_BACKUP_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_S = 0 +const INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP = 0x0000001F +const INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_V = 0x1F +const INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_S = 0 +const INTERRUPT_CORE0_INTR_STATUS_0 = 0xFFFFFFFF +const INTERRUPT_CORE0_INTR_STATUS_0_V = 0xFFFFFFFF +const INTERRUPT_CORE0_INTR_STATUS_0_S = 0 +const INTERRUPT_CORE0_INTR_STATUS_1 = 0xFFFFFFFF +const INTERRUPT_CORE0_INTR_STATUS_1_V = 0xFFFFFFFF +const INTERRUPT_CORE0_INTR_STATUS_1_S = 0 +const INTERRUPT_CORE0_INTR_STATUS_2 = 0xFFFFFFFF +const INTERRUPT_CORE0_INTR_STATUS_2_V = 0xFFFFFFFF +const INTERRUPT_CORE0_INTR_STATUS_2_S = 0 +const INTERRUPT_CORE0_INTR_STATUS_3 = 0xFFFFFFFF +const INTERRUPT_CORE0_INTR_STATUS_3_V = 0xFFFFFFFF +const INTERRUPT_CORE0_INTR_STATUS_3_S = 0 +const INTERRUPT_CORE0_CLK_EN_V = 0x1 +const INTERRUPT_CORE0_CLK_EN_S = 0 +const INTERRUPT_CORE0_INTERRUPT_DATE = 0x0FFFFFFF +const INTERRUPT_CORE0_INTERRUPT_DATE_V = 0xFFFFFFF +const INTERRUPT_CORE0_INTERRUPT_DATE_S = 0 diff --git a/esp32/interrupt_core0_struct.go b/esp32/interrupt_core0_struct.go new file mode 100644 index 00000000..f9b90e76 --- /dev/null +++ b/esp32/interrupt_core0_struct.go @@ -0,0 +1,724 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type InterruptCore0DevS struct { + Core0MacIntrMap struct { + Val c.Uint32T + } + Core0MacNmiMap struct { + Val c.Uint32T + } + Core0PwrIntrMap struct { + Val c.Uint32T + } + Core0BbIntMap struct { + Val c.Uint32T + } + Core0BtMacIntMap struct { + Val c.Uint32T + } + Core0BtBbIntMap struct { + Val c.Uint32T + } + Core0BtBbNmiMap struct { + Val c.Uint32T + } + Core0RwbtIrqMap struct { + Val c.Uint32T + } + Core0RwbleIrqMap struct { + Val c.Uint32T + } + Core0RwbtNmiMap struct { + Val c.Uint32T + } + Core0RwbleNmiMap struct { + Val c.Uint32T + } + Core0I2cMstIntMap struct { + Val c.Uint32T + } + Core0Slc0IntrMap struct { + Val c.Uint32T + } + Core0Slc1IntrMap struct { + Val c.Uint32T + } + Core0Uhci0IntrMap struct { + Val c.Uint32T + } + Core0Uhci1IntrMap struct { + Val c.Uint32T + } + Core0GpioInterruptProMap struct { + Val c.Uint32T + } + Core0GpioInterruptProNmiMap struct { + Val c.Uint32T + } + Core0GpioInterruptAppMap struct { + Val c.Uint32T + } + Core0GpioInterruptAppNmiMap struct { + Val c.Uint32T + } + Core0SpiIntr1Map struct { + Val c.Uint32T + } + Core0SpiIntr2Map struct { + Val c.Uint32T + } + Core0SpiIntr3Map struct { + Val c.Uint32T + } + Core0SpiIntr4Map struct { + Val c.Uint32T + } + Core0LcdCamIntMap struct { + Val c.Uint32T + } + Core0I2s0IntMap struct { + Val c.Uint32T + } + Core0I2s1IntMap struct { + Val c.Uint32T + } + Core0UartIntrMap struct { + Val c.Uint32T + } + Core0Uart1IntrMap struct { + Val c.Uint32T + } + Core0Uart2IntrMap struct { + Val c.Uint32T + } + Core0SdioHostInterruptMap struct { + Val c.Uint32T + } + Core0Pwm0IntrMap struct { + Val c.Uint32T + } + Core0Pwm1IntrMap struct { + Val c.Uint32T + } + Core0Pwm2IntrMap struct { + Val c.Uint32T + } + Core0Pwm3IntrMap struct { + Val c.Uint32T + } + Core0LedcIntMap struct { + Val c.Uint32T + } + Core0EfuseIntMap struct { + Val c.Uint32T + } + Core0CanIntMap struct { + Val c.Uint32T + } + Core0UsbIntrMap struct { + Val c.Uint32T + } + Core0RtcCoreIntrMap struct { + Val c.Uint32T + } + Core0RmtIntrMap struct { + Val c.Uint32T + } + Core0PcntIntrMap struct { + Val c.Uint32T + } + Core0I2cExt0IntrMap struct { + Val c.Uint32T + } + Core0I2cExt1IntrMap struct { + Val c.Uint32T + } + Core0Spi2DmaIntMap struct { + Val c.Uint32T + } + Core0Spi3DmaIntMap struct { + Val c.Uint32T + } + Core0Spi4DmaIntMap struct { + Val c.Uint32T + } + Core0WdgIntMap struct { + Val c.Uint32T + } + Core0TimerInt1Map struct { + Val c.Uint32T + } + Core0TimerInt2Map struct { + Val c.Uint32T + } + Core0TgT0IntMap struct { + Val c.Uint32T + } + Core0TgT1IntMap struct { + Val c.Uint32T + } + Core0TgWdtIntMap struct { + Val c.Uint32T + } + Core0Tg1T0IntMap struct { + Val c.Uint32T + } + Core0Tg1T1IntMap struct { + Val c.Uint32T + } + Core0Tg1WdtIntMap struct { + Val c.Uint32T + } + Core0CacheIaIntMap struct { + Val c.Uint32T + } + Core0SystimerTarget0IntMap struct { + Val c.Uint32T + } + Core0SystimerTarget1IntMap struct { + Val c.Uint32T + } + Core0SystimerTarget2IntMap struct { + Val c.Uint32T + } + Core0SpiMemRejectIntrMap struct { + Val c.Uint32T + } + Core0DcachePreloadIntMap struct { + Val c.Uint32T + } + Core0IcachePreloadIntMap struct { + Val c.Uint32T + } + Core0DcacheSyncIntMap struct { + Val c.Uint32T + } + Core0IcacheSyncIntMap struct { + Val c.Uint32T + } + Core0ApbAdcIntMap struct { + Val c.Uint32T + } + Core0DmaInCh0IntMap struct { + Val c.Uint32T + } + Core0DmaInCh1IntMap struct { + Val c.Uint32T + } + Core0DmaInCh2IntMap struct { + Val c.Uint32T + } + Core0DmaInCh3IntMap struct { + Val c.Uint32T + } + Core0DmaInCh4IntMap struct { + Val c.Uint32T + } + Core0DmaOutCh0IntMap struct { + Val c.Uint32T + } + Core0DmaOutCh1IntMap struct { + Val c.Uint32T + } + Core0DmaOutCh2IntMap struct { + Val c.Uint32T + } + Core0DmaOutCh3IntMap struct { + Val c.Uint32T + } + Core0DmaOutCh4IntMap struct { + Val c.Uint32T + } + Core0RsaIntMap struct { + Val c.Uint32T + } + Core0AesIntMap struct { + Val c.Uint32T + } + Core0ShaIntMap struct { + Val c.Uint32T + } + Core0CpuIntrFromCpu0Map struct { + Val c.Uint32T + } + Core0CpuIntrFromCpu1Map struct { + Val c.Uint32T + } + Core0CpuIntrFromCpu2Map struct { + Val c.Uint32T + } + Core0CpuIntrFromCpu3Map struct { + Val c.Uint32T + } + Core0AssistDebugIntrMap struct { + Val c.Uint32T + } + Core0DmaApbperiPmsMonitorViolateIntrMap struct { + Val c.Uint32T + } + Core0Core0Iram0PmsMonitorViolateIntrMap struct { + Val c.Uint32T + } + Core0Core0Dram0PmsMonitorViolateIntrMap struct { + Val c.Uint32T + } + Core0Core0PifPmsMonitorViolateIntrMap struct { + Val c.Uint32T + } + Core0Core0PifPmsMonitorViolateSizeIntrMap struct { + Val c.Uint32T + } + Core0Core1Iram0PmsMonitorViolateIntrMap struct { + Val c.Uint32T + } + Core0Core1Dram0PmsMonitorViolateIntrMap struct { + Val c.Uint32T + } + Core0Core1PifPmsMonitorViolateIntrMap struct { + Val c.Uint32T + } + Core0Core1PifPmsMonitorViolateSizeIntrMap struct { + Val c.Uint32T + } + Core0BackupPmsViolateIntrMap struct { + Val c.Uint32T + } + Core0CacheCore0AcsIntMap struct { + Val c.Uint32T + } + Core0CacheCore1AcsIntMap struct { + Val c.Uint32T + } + Core0UsbDeviceIntMap struct { + Val c.Uint32T + } + Core0PeriBackupIntMap struct { + Val c.Uint32T + } + Core0DmaExtmemRejectIntMap struct { + Val c.Uint32T + } + Core0IntrStatus0 c.Uint32T + Core0IntrStatus1 c.Uint32T + Core0IntrStatus2 c.Uint32T + Core0IntrStatus3 c.Uint32T + Core0ClockGate struct { + Val c.Uint32T + } + Reserved1a0 c.Uint32T + Reserved1a4 c.Uint32T + Reserved1a8 c.Uint32T + Reserved1ac c.Uint32T + Reserved1b0 c.Uint32T + Reserved1b4 c.Uint32T + Reserved1b8 c.Uint32T + Reserved1bc c.Uint32T + Reserved1c0 c.Uint32T + Reserved1c4 c.Uint32T + Reserved1c8 c.Uint32T + Reserved1cc c.Uint32T + Reserved1d0 c.Uint32T + Reserved1d4 c.Uint32T + Reserved1d8 c.Uint32T + Reserved1dc c.Uint32T + Reserved1e0 c.Uint32T + Reserved1e4 c.Uint32T + Reserved1e8 c.Uint32T + Reserved1ec c.Uint32T + Reserved1f0 c.Uint32T + Reserved1f4 c.Uint32T + Reserved1f8 c.Uint32T + Reserved1fc c.Uint32T + Reserved200 c.Uint32T + Reserved204 c.Uint32T + Reserved208 c.Uint32T + Reserved20c c.Uint32T + Reserved210 c.Uint32T + Reserved214 c.Uint32T + Reserved218 c.Uint32T + Reserved21c c.Uint32T + Reserved220 c.Uint32T + Reserved224 c.Uint32T + Reserved228 c.Uint32T + Reserved22c c.Uint32T + Reserved230 c.Uint32T + Reserved234 c.Uint32T + Reserved238 c.Uint32T + Reserved23c c.Uint32T + Reserved240 c.Uint32T + Reserved244 c.Uint32T + Reserved248 c.Uint32T + Reserved24c c.Uint32T + Reserved250 c.Uint32T + Reserved254 c.Uint32T + Reserved258 c.Uint32T + Reserved25c c.Uint32T + Reserved260 c.Uint32T + Reserved264 c.Uint32T + Reserved268 c.Uint32T + Reserved26c c.Uint32T + Reserved270 c.Uint32T + Reserved274 c.Uint32T + Reserved278 c.Uint32T + Reserved27c c.Uint32T + Reserved280 c.Uint32T + Reserved284 c.Uint32T + Reserved288 c.Uint32T + Reserved28c c.Uint32T + Reserved290 c.Uint32T + Reserved294 c.Uint32T + Reserved298 c.Uint32T + Reserved29c c.Uint32T + Reserved2a0 c.Uint32T + Reserved2a4 c.Uint32T + Reserved2a8 c.Uint32T + Reserved2ac c.Uint32T + Reserved2b0 c.Uint32T + Reserved2b4 c.Uint32T + Reserved2b8 c.Uint32T + Reserved2bc c.Uint32T + Reserved2c0 c.Uint32T + Reserved2c4 c.Uint32T + Reserved2c8 c.Uint32T + Reserved2cc c.Uint32T + Reserved2d0 c.Uint32T + Reserved2d4 c.Uint32T + Reserved2d8 c.Uint32T + Reserved2dc c.Uint32T + Reserved2e0 c.Uint32T + Reserved2e4 c.Uint32T + Reserved2e8 c.Uint32T + Reserved2ec c.Uint32T + Reserved2f0 c.Uint32T + Reserved2f4 c.Uint32T + Reserved2f8 c.Uint32T + Reserved2fc c.Uint32T + Reserved300 c.Uint32T + Reserved304 c.Uint32T + Reserved308 c.Uint32T + Reserved30c c.Uint32T + Reserved310 c.Uint32T + Reserved314 c.Uint32T + Reserved318 c.Uint32T + Reserved31c c.Uint32T + Reserved320 c.Uint32T + Reserved324 c.Uint32T + Reserved328 c.Uint32T + Reserved32c c.Uint32T + Reserved330 c.Uint32T + Reserved334 c.Uint32T + Reserved338 c.Uint32T + Reserved33c c.Uint32T + Reserved340 c.Uint32T + Reserved344 c.Uint32T + Reserved348 c.Uint32T + Reserved34c c.Uint32T + Reserved350 c.Uint32T + Reserved354 c.Uint32T + Reserved358 c.Uint32T + Reserved35c c.Uint32T + Reserved360 c.Uint32T + Reserved364 c.Uint32T + Reserved368 c.Uint32T + Reserved36c c.Uint32T + Reserved370 c.Uint32T + Reserved374 c.Uint32T + Reserved378 c.Uint32T + Reserved37c c.Uint32T + Reserved380 c.Uint32T + Reserved384 c.Uint32T + Reserved388 c.Uint32T + Reserved38c c.Uint32T + Reserved390 c.Uint32T + Reserved394 c.Uint32T + Reserved398 c.Uint32T + Reserved39c c.Uint32T + Reserved3a0 c.Uint32T + Reserved3a4 c.Uint32T + Reserved3a8 c.Uint32T + Reserved3ac c.Uint32T + Reserved3b0 c.Uint32T + Reserved3b4 c.Uint32T + Reserved3b8 c.Uint32T + Reserved3bc c.Uint32T + Reserved3c0 c.Uint32T + Reserved3c4 c.Uint32T + Reserved3c8 c.Uint32T + Reserved3cc c.Uint32T + Reserved3d0 c.Uint32T + Reserved3d4 c.Uint32T + Reserved3d8 c.Uint32T + Reserved3dc c.Uint32T + Reserved3e0 c.Uint32T + Reserved3e4 c.Uint32T + Reserved3e8 c.Uint32T + Reserved3ec c.Uint32T + Reserved3f0 c.Uint32T + Reserved3f4 c.Uint32T + Reserved3f8 c.Uint32T + Reserved3fc c.Uint32T + Reserved400 c.Uint32T + Reserved404 c.Uint32T + Reserved408 c.Uint32T + Reserved40c c.Uint32T + Reserved410 c.Uint32T + Reserved414 c.Uint32T + Reserved418 c.Uint32T + Reserved41c c.Uint32T + Reserved420 c.Uint32T + Reserved424 c.Uint32T + Reserved428 c.Uint32T + Reserved42c c.Uint32T + Reserved430 c.Uint32T + Reserved434 c.Uint32T + Reserved438 c.Uint32T + Reserved43c c.Uint32T + Reserved440 c.Uint32T + Reserved444 c.Uint32T + Reserved448 c.Uint32T + Reserved44c c.Uint32T + Reserved450 c.Uint32T + Reserved454 c.Uint32T + Reserved458 c.Uint32T + Reserved45c c.Uint32T + Reserved460 c.Uint32T + Reserved464 c.Uint32T + Reserved468 c.Uint32T + Reserved46c c.Uint32T + Reserved470 c.Uint32T + Reserved474 c.Uint32T + Reserved478 c.Uint32T + Reserved47c c.Uint32T + Reserved480 c.Uint32T + Reserved484 c.Uint32T + Reserved488 c.Uint32T + Reserved48c c.Uint32T + Reserved490 c.Uint32T + Reserved494 c.Uint32T + Reserved498 c.Uint32T + Reserved49c c.Uint32T + Reserved4a0 c.Uint32T + Reserved4a4 c.Uint32T + Reserved4a8 c.Uint32T + Reserved4ac c.Uint32T + Reserved4b0 c.Uint32T + Reserved4b4 c.Uint32T + Reserved4b8 c.Uint32T + Reserved4bc c.Uint32T + Reserved4c0 c.Uint32T + Reserved4c4 c.Uint32T + Reserved4c8 c.Uint32T + Reserved4cc c.Uint32T + Reserved4d0 c.Uint32T + Reserved4d4 c.Uint32T + Reserved4d8 c.Uint32T + Reserved4dc c.Uint32T + Reserved4e0 c.Uint32T + Reserved4e4 c.Uint32T + Reserved4e8 c.Uint32T + Reserved4ec c.Uint32T + Reserved4f0 c.Uint32T + Reserved4f4 c.Uint32T + Reserved4f8 c.Uint32T + Reserved4fc c.Uint32T + Reserved500 c.Uint32T + Reserved504 c.Uint32T + Reserved508 c.Uint32T + Reserved50c c.Uint32T + Reserved510 c.Uint32T + Reserved514 c.Uint32T + Reserved518 c.Uint32T + Reserved51c c.Uint32T + Reserved520 c.Uint32T + Reserved524 c.Uint32T + Reserved528 c.Uint32T + Reserved52c c.Uint32T + Reserved530 c.Uint32T + Reserved534 c.Uint32T + Reserved538 c.Uint32T + Reserved53c c.Uint32T + Reserved540 c.Uint32T + Reserved544 c.Uint32T + Reserved548 c.Uint32T + Reserved54c c.Uint32T + Reserved550 c.Uint32T + Reserved554 c.Uint32T + Reserved558 c.Uint32T + Reserved55c c.Uint32T + Reserved560 c.Uint32T + Reserved564 c.Uint32T + Reserved568 c.Uint32T + Reserved56c c.Uint32T + Reserved570 c.Uint32T + Reserved574 c.Uint32T + Reserved578 c.Uint32T + Reserved57c c.Uint32T + Reserved580 c.Uint32T + Reserved584 c.Uint32T + Reserved588 c.Uint32T + Reserved58c c.Uint32T + Reserved590 c.Uint32T + Reserved594 c.Uint32T + Reserved598 c.Uint32T + Reserved59c c.Uint32T + Reserved5a0 c.Uint32T + Reserved5a4 c.Uint32T + Reserved5a8 c.Uint32T + Reserved5ac c.Uint32T + Reserved5b0 c.Uint32T + Reserved5b4 c.Uint32T + Reserved5b8 c.Uint32T + Reserved5bc c.Uint32T + Reserved5c0 c.Uint32T + Reserved5c4 c.Uint32T + Reserved5c8 c.Uint32T + Reserved5cc c.Uint32T + Reserved5d0 c.Uint32T + Reserved5d4 c.Uint32T + Reserved5d8 c.Uint32T + Reserved5dc c.Uint32T + Reserved5e0 c.Uint32T + Reserved5e4 c.Uint32T + Reserved5e8 c.Uint32T + Reserved5ec c.Uint32T + Reserved5f0 c.Uint32T + Reserved5f4 c.Uint32T + Reserved5f8 c.Uint32T + Reserved5fc c.Uint32T + Reserved600 c.Uint32T + Reserved604 c.Uint32T + Reserved608 c.Uint32T + Reserved60c c.Uint32T + Reserved610 c.Uint32T + Reserved614 c.Uint32T + Reserved618 c.Uint32T + Reserved61c c.Uint32T + Reserved620 c.Uint32T + Reserved624 c.Uint32T + Reserved628 c.Uint32T + Reserved62c c.Uint32T + Reserved630 c.Uint32T + Reserved634 c.Uint32T + Reserved638 c.Uint32T + Reserved63c c.Uint32T + Reserved640 c.Uint32T + Reserved644 c.Uint32T + Reserved648 c.Uint32T + Reserved64c c.Uint32T + Reserved650 c.Uint32T + Reserved654 c.Uint32T + Reserved658 c.Uint32T + Reserved65c c.Uint32T + Reserved660 c.Uint32T + Reserved664 c.Uint32T + Reserved668 c.Uint32T + Reserved66c c.Uint32T + Reserved670 c.Uint32T + Reserved674 c.Uint32T + Reserved678 c.Uint32T + Reserved67c c.Uint32T + Reserved680 c.Uint32T + Reserved684 c.Uint32T + Reserved688 c.Uint32T + Reserved68c c.Uint32T + Reserved690 c.Uint32T + Reserved694 c.Uint32T + Reserved698 c.Uint32T + Reserved69c c.Uint32T + Reserved6a0 c.Uint32T + Reserved6a4 c.Uint32T + Reserved6a8 c.Uint32T + Reserved6ac c.Uint32T + Reserved6b0 c.Uint32T + Reserved6b4 c.Uint32T + Reserved6b8 c.Uint32T + Reserved6bc c.Uint32T + Reserved6c0 c.Uint32T + Reserved6c4 c.Uint32T + Reserved6c8 c.Uint32T + Reserved6cc c.Uint32T + Reserved6d0 c.Uint32T + Reserved6d4 c.Uint32T + Reserved6d8 c.Uint32T + Reserved6dc c.Uint32T + Reserved6e0 c.Uint32T + Reserved6e4 c.Uint32T + Reserved6e8 c.Uint32T + Reserved6ec c.Uint32T + Reserved6f0 c.Uint32T + Reserved6f4 c.Uint32T + Reserved6f8 c.Uint32T + Reserved6fc c.Uint32T + Reserved700 c.Uint32T + Reserved704 c.Uint32T + Reserved708 c.Uint32T + Reserved70c c.Uint32T + Reserved710 c.Uint32T + Reserved714 c.Uint32T + Reserved718 c.Uint32T + Reserved71c c.Uint32T + Reserved720 c.Uint32T + Reserved724 c.Uint32T + Reserved728 c.Uint32T + Reserved72c c.Uint32T + Reserved730 c.Uint32T + Reserved734 c.Uint32T + Reserved738 c.Uint32T + Reserved73c c.Uint32T + Reserved740 c.Uint32T + Reserved744 c.Uint32T + Reserved748 c.Uint32T + Reserved74c c.Uint32T + Reserved750 c.Uint32T + Reserved754 c.Uint32T + Reserved758 c.Uint32T + Reserved75c c.Uint32T + Reserved760 c.Uint32T + Reserved764 c.Uint32T + Reserved768 c.Uint32T + Reserved76c c.Uint32T + Reserved770 c.Uint32T + Reserved774 c.Uint32T + Reserved778 c.Uint32T + Reserved77c c.Uint32T + Reserved780 c.Uint32T + Reserved784 c.Uint32T + Reserved788 c.Uint32T + Reserved78c c.Uint32T + Reserved790 c.Uint32T + Reserved794 c.Uint32T + Reserved798 c.Uint32T + Reserved79c c.Uint32T + Reserved7a0 c.Uint32T + Reserved7a4 c.Uint32T + Reserved7a8 c.Uint32T + Reserved7ac c.Uint32T + Reserved7b0 c.Uint32T + Reserved7b4 c.Uint32T + Reserved7b8 c.Uint32T + Reserved7bc c.Uint32T + Reserved7c0 c.Uint32T + Reserved7c4 c.Uint32T + Reserved7c8 c.Uint32T + Reserved7cc c.Uint32T + Reserved7d0 c.Uint32T + Reserved7d4 c.Uint32T + Reserved7d8 c.Uint32T + Reserved7dc c.Uint32T + Reserved7e0 c.Uint32T + Reserved7e4 c.Uint32T + Reserved7e8 c.Uint32T + Reserved7ec c.Uint32T + Reserved7f0 c.Uint32T + Reserved7f4 c.Uint32T + Reserved7f8 c.Uint32T + Core0InterruptDate struct { + Val c.Uint32T + } +} +type InterruptCore0DevT InterruptCore0DevS diff --git a/esp32/interrupt_core1_reg.go b/esp32/interrupt_core1_reg.go new file mode 100644 index 00000000..dbb41cca --- /dev/null +++ b/esp32/interrupt_core1_reg.go @@ -0,0 +1,318 @@ +package freertos + +import _ "unsafe" + +const INTERRUPT_CORE1_MAC_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_MAC_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_MAC_INTR_MAP_S = 0 +const INTERRUPT_CORE1_MAC_NMI_MAP = 0x0000001F +const INTERRUPT_CORE1_MAC_NMI_MAP_V = 0x1F +const INTERRUPT_CORE1_MAC_NMI_MAP_S = 0 +const INTERRUPT_CORE1_PWR_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_PWR_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_PWR_INTR_MAP_S = 0 +const INTERRUPT_CORE1_BB_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_BB_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_BB_INT_MAP_S = 0 +const INTERRUPT_CORE1_BT_MAC_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_BT_MAC_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_BT_MAC_INT_MAP_S = 0 +const INTERRUPT_CORE1_BT_BB_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_BT_BB_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_BT_BB_INT_MAP_S = 0 +const INTERRUPT_CORE1_BT_BB_NMI_MAP = 0x0000001F +const INTERRUPT_CORE1_BT_BB_NMI_MAP_V = 0x1F +const INTERRUPT_CORE1_BT_BB_NMI_MAP_S = 0 +const INTERRUPT_CORE1_RWBT_IRQ_MAP = 0x0000001F +const INTERRUPT_CORE1_RWBT_IRQ_MAP_V = 0x1F +const INTERRUPT_CORE1_RWBT_IRQ_MAP_S = 0 +const INTERRUPT_CORE1_RWBLE_IRQ_MAP = 0x0000001F +const INTERRUPT_CORE1_RWBLE_IRQ_MAP_V = 0x1F +const INTERRUPT_CORE1_RWBLE_IRQ_MAP_S = 0 +const INTERRUPT_CORE1_RWBT_NMI_MAP = 0x0000001F +const INTERRUPT_CORE1_RWBT_NMI_MAP_V = 0x1F +const INTERRUPT_CORE1_RWBT_NMI_MAP_S = 0 +const INTERRUPT_CORE1_RWBLE_NMI_MAP = 0x0000001F +const INTERRUPT_CORE1_RWBLE_NMI_MAP_V = 0x1F +const INTERRUPT_CORE1_RWBLE_NMI_MAP_S = 0 +const INTERRUPT_CORE1_I2C_MST_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_I2C_MST_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_I2C_MST_INT_MAP_S = 0 +const INTERRUPT_CORE1_SLC0_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_SLC0_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_SLC0_INTR_MAP_S = 0 +const INTERRUPT_CORE1_SLC1_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_SLC1_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_SLC1_INTR_MAP_S = 0 +const INTERRUPT_CORE1_UHCI0_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_UHCI0_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_UHCI0_INTR_MAP_S = 0 +const INTERRUPT_CORE1_UHCI1_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_UHCI1_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_UHCI1_INTR_MAP_S = 0 +const INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP = 0x0000001F +const INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_V = 0x1F +const INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_S = 0 +const INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP = 0x0000001F +const INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_V = 0x1F +const INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_S = 0 +const INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP = 0x0000001F +const INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_V = 0x1F +const INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_S = 0 +const INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP = 0x0000001F +const INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_V = 0x1F +const INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_S = 0 +const INTERRUPT_CORE1_SPI_INTR_1_MAP = 0x0000001F +const INTERRUPT_CORE1_SPI_INTR_1_MAP_V = 0x1F +const INTERRUPT_CORE1_SPI_INTR_1_MAP_S = 0 +const INTERRUPT_CORE1_SPI_INTR_2_MAP = 0x0000001F +const INTERRUPT_CORE1_SPI_INTR_2_MAP_V = 0x1F +const INTERRUPT_CORE1_SPI_INTR_2_MAP_S = 0 +const INTERRUPT_CORE1_SPI_INTR_3_MAP = 0x0000001F +const INTERRUPT_CORE1_SPI_INTR_3_MAP_V = 0x1F +const INTERRUPT_CORE1_SPI_INTR_3_MAP_S = 0 +const INTERRUPT_CORE1_SPI_INTR_4_MAP = 0x0000001F +const INTERRUPT_CORE1_SPI_INTR_4_MAP_V = 0x1F +const INTERRUPT_CORE1_SPI_INTR_4_MAP_S = 0 +const INTERRUPT_CORE1_LCD_CAM_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_LCD_CAM_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_LCD_CAM_INT_MAP_S = 0 +const INTERRUPT_CORE1_I2S0_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_I2S0_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_I2S0_INT_MAP_S = 0 +const INTERRUPT_CORE1_I2S1_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_I2S1_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_I2S1_INT_MAP_S = 0 +const INTERRUPT_CORE1_UART_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_UART_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_UART_INTR_MAP_S = 0 +const INTERRUPT_CORE1_UART1_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_UART1_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_UART1_INTR_MAP_S = 0 +const INTERRUPT_CORE1_UART2_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_UART2_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_UART2_INTR_MAP_S = 0 +const INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP = 0x0000001F +const INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_V = 0x1F +const INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_S = 0 +const INTERRUPT_CORE1_PWM0_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_PWM0_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_PWM0_INTR_MAP_S = 0 +const INTERRUPT_CORE1_PWM1_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_PWM1_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_PWM1_INTR_MAP_S = 0 +const INTERRUPT_CORE1_PWM2_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_PWM2_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_PWM2_INTR_MAP_S = 0 +const INTERRUPT_CORE1_PWM3_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_PWM3_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_PWM3_INTR_MAP_S = 0 +const INTERRUPT_CORE1_LEDC_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_LEDC_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_LEDC_INT_MAP_S = 0 +const INTERRUPT_CORE1_EFUSE_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_EFUSE_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_EFUSE_INT_MAP_S = 0 +const INTERRUPT_CORE1_CAN_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_CAN_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_CAN_INT_MAP_S = 0 +const INTERRUPT_CORE1_USB_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_USB_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_USB_INTR_MAP_S = 0 +const INTERRUPT_CORE1_RTC_CORE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_RTC_CORE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_RTC_CORE_INTR_MAP_S = 0 +const INTERRUPT_CORE1_RMT_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_RMT_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_RMT_INTR_MAP_S = 0 +const INTERRUPT_CORE1_PCNT_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_PCNT_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_PCNT_INTR_MAP_S = 0 +const INTERRUPT_CORE1_I2C_EXT0_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_S = 0 +const INTERRUPT_CORE1_I2C_EXT1_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_S = 0 +const INTERRUPT_CORE1_SPI2_DMA_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_SPI2_DMA_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_SPI2_DMA_INT_MAP_S = 0 +const INTERRUPT_CORE1_SPI3_DMA_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_SPI3_DMA_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_SPI3_DMA_INT_MAP_S = 0 +const INTERRUPT_CORE1_SPI4_DMA_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_SPI4_DMA_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_SPI4_DMA_INT_MAP_S = 0 +const INTERRUPT_CORE1_WDG_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_WDG_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_WDG_INT_MAP_S = 0 +const INTERRUPT_CORE1_TIMER_INT1_MAP = 0x0000001F +const INTERRUPT_CORE1_TIMER_INT1_MAP_V = 0x1F +const INTERRUPT_CORE1_TIMER_INT1_MAP_S = 0 +const INTERRUPT_CORE1_TIMER_INT2_MAP = 0x0000001F +const INTERRUPT_CORE1_TIMER_INT2_MAP_V = 0x1F +const INTERRUPT_CORE1_TIMER_INT2_MAP_S = 0 +const INTERRUPT_CORE1_TG_T0_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_TG_T0_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_TG_T0_INT_MAP_S = 0 +const INTERRUPT_CORE1_TG_T1_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_TG_T1_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_TG_T1_INT_MAP_S = 0 +const INTERRUPT_CORE1_TG_WDT_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_TG_WDT_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_TG_WDT_INT_MAP_S = 0 +const INTERRUPT_CORE1_TG1_T0_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_TG1_T0_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_TG1_T0_INT_MAP_S = 0 +const INTERRUPT_CORE1_TG1_T1_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_TG1_T1_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_TG1_T1_INT_MAP_S = 0 +const INTERRUPT_CORE1_TG1_WDT_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_TG1_WDT_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_TG1_WDT_INT_MAP_S = 0 +const INTERRUPT_CORE1_CACHE_IA_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_CACHE_IA_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_CACHE_IA_INT_MAP_S = 0 +const INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S = 0 +const INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S = 0 +const INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S = 0 +const INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_S = 0 +const INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_S = 0 +const INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_S = 0 +const INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_S = 0 +const INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_S = 0 +const INTERRUPT_CORE1_APB_ADC_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_APB_ADC_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_APB_ADC_INT_MAP_S = 0 +const INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_S = 0 +const INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_S = 0 +const INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_S = 0 +const INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_S = 0 +const INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_S = 0 +const INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_S = 0 +const INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_S = 0 +const INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_S = 0 +const INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_S = 0 +const INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_S = 0 +const INTERRUPT_CORE1_RSA_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_RSA_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_RSA_INT_MAP_S = 0 +const INTERRUPT_CORE1_AES_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_AES_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_AES_INT_MAP_S = 0 +const INTERRUPT_CORE1_SHA_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_SHA_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_SHA_INT_MAP_S = 0 +const INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP = 0x0000001F +const INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_V = 0x1F +const INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_S = 0 +const INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP = 0x0000001F +const INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_V = 0x1F +const INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_S = 0 +const INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP = 0x0000001F +const INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_V = 0x1F +const INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_S = 0 +const INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP = 0x0000001F +const INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_V = 0x1F +const INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_S = 0 +const INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_S = 0 +const INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S = 0 +const INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S = 0 +const INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP = 0x0000001F +const INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_V = 0x1F +const INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_S = 0 +const INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_S = 0 +const INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_S = 0 +const INTERRUPT_CORE1_USB_DEVICE_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S = 0 +const INTERRUPT_CORE1_PERI_BACKUP_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_S = 0 +const INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP = 0x0000001F +const INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_V = 0x1F +const INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_S = 0 +const INTERRUPT_CORE1_INTR_STATUS_0 = 0xFFFFFFFF +const INTERRUPT_CORE1_INTR_STATUS_0_V = 0xFFFFFFFF +const INTERRUPT_CORE1_INTR_STATUS_0_S = 0 +const INTERRUPT_CORE1_INTR_STATUS_1 = 0xFFFFFFFF +const INTERRUPT_CORE1_INTR_STATUS_1_V = 0xFFFFFFFF +const INTERRUPT_CORE1_INTR_STATUS_1_S = 0 +const INTERRUPT_CORE1_INTR_STATUS_2 = 0xFFFFFFFF +const INTERRUPT_CORE1_INTR_STATUS_2_V = 0xFFFFFFFF +const INTERRUPT_CORE1_INTR_STATUS_2_S = 0 +const INTERRUPT_CORE1_INTR_STATUS_3 = 0xFFFFFFFF +const INTERRUPT_CORE1_INTR_STATUS_3_V = 0xFFFFFFFF +const INTERRUPT_CORE1_INTR_STATUS_3_S = 0 +const INTERRUPT_CORE1_CLK_EN_V = 0x1 +const INTERRUPT_CORE1_CLK_EN_S = 0 +const INTERRUPT_CORE1_INTERRUPT_DATE = 0x0FFFFFFF +const INTERRUPT_CORE1_INTERRUPT_DATE_V = 0xFFFFFFF +const INTERRUPT_CORE1_INTERRUPT_DATE_S = 0 diff --git a/esp32/interrupt_core1_struct.go b/esp32/interrupt_core1_struct.go new file mode 100644 index 00000000..9b1faaa9 --- /dev/null +++ b/esp32/interrupt_core1_struct.go @@ -0,0 +1,1236 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type InterruptCore1DevS struct { + Reserved0 c.Uint32T + Reserved4 c.Uint32T + Reserved8 c.Uint32T + ReservedC c.Uint32T + Reserved10 c.Uint32T + Reserved14 c.Uint32T + Reserved18 c.Uint32T + Reserved1c c.Uint32T + Reserved20 c.Uint32T + Reserved24 c.Uint32T + Reserved28 c.Uint32T + Reserved2c c.Uint32T + Reserved30 c.Uint32T + Reserved34 c.Uint32T + Reserved38 c.Uint32T + Reserved3c c.Uint32T + Reserved40 c.Uint32T + Reserved44 c.Uint32T + Reserved48 c.Uint32T + Reserved4c c.Uint32T + Reserved50 c.Uint32T + Reserved54 c.Uint32T + Reserved58 c.Uint32T + Reserved5c c.Uint32T + Reserved60 c.Uint32T + Reserved64 c.Uint32T + Reserved68 c.Uint32T + Reserved6c c.Uint32T + Reserved70 c.Uint32T + Reserved74 c.Uint32T + Reserved78 c.Uint32T + Reserved7c c.Uint32T + Reserved80 c.Uint32T + Reserved84 c.Uint32T + Reserved88 c.Uint32T + Reserved8c c.Uint32T + Reserved90 c.Uint32T + Reserved94 c.Uint32T + Reserved98 c.Uint32T + Reserved9c c.Uint32T + ReservedA0 c.Uint32T + ReservedA4 c.Uint32T + ReservedA8 c.Uint32T + ReservedAc c.Uint32T + ReservedB0 c.Uint32T + ReservedB4 c.Uint32T + ReservedB8 c.Uint32T + ReservedBc c.Uint32T + ReservedC0 c.Uint32T + ReservedC4 c.Uint32T + ReservedC8 c.Uint32T + ReservedCc c.Uint32T + ReservedD0 c.Uint32T + ReservedD4 c.Uint32T + ReservedD8 c.Uint32T + ReservedDc c.Uint32T + ReservedE0 c.Uint32T + ReservedE4 c.Uint32T + ReservedE8 c.Uint32T + ReservedEc c.Uint32T + ReservedF0 c.Uint32T + ReservedF4 c.Uint32T + ReservedF8 c.Uint32T + ReservedFc c.Uint32T + Reserved100 c.Uint32T + Reserved104 c.Uint32T + Reserved108 c.Uint32T + Reserved10c c.Uint32T + Reserved110 c.Uint32T + Reserved114 c.Uint32T + Reserved118 c.Uint32T + Reserved11c c.Uint32T + Reserved120 c.Uint32T + Reserved124 c.Uint32T + Reserved128 c.Uint32T + Reserved12c c.Uint32T + Reserved130 c.Uint32T + Reserved134 c.Uint32T + Reserved138 c.Uint32T + Reserved13c c.Uint32T + Reserved140 c.Uint32T + Reserved144 c.Uint32T + Reserved148 c.Uint32T + Reserved14c c.Uint32T + Reserved150 c.Uint32T + Reserved154 c.Uint32T + Reserved158 c.Uint32T + Reserved15c c.Uint32T + Reserved160 c.Uint32T + Reserved164 c.Uint32T + Reserved168 c.Uint32T + Reserved16c c.Uint32T + Reserved170 c.Uint32T + Reserved174 c.Uint32T + Reserved178 c.Uint32T + Reserved17c c.Uint32T + Reserved180 c.Uint32T + Reserved184 c.Uint32T + Reserved188 c.Uint32T + Reserved18c c.Uint32T + Reserved190 c.Uint32T + Reserved194 c.Uint32T + Reserved198 c.Uint32T + Reserved19c c.Uint32T + Reserved1a0 c.Uint32T + Reserved1a4 c.Uint32T + Reserved1a8 c.Uint32T + Reserved1ac c.Uint32T + Reserved1b0 c.Uint32T + Reserved1b4 c.Uint32T + Reserved1b8 c.Uint32T + Reserved1bc c.Uint32T + Reserved1c0 c.Uint32T + Reserved1c4 c.Uint32T + Reserved1c8 c.Uint32T + Reserved1cc c.Uint32T + Reserved1d0 c.Uint32T + Reserved1d4 c.Uint32T + Reserved1d8 c.Uint32T + Reserved1dc c.Uint32T + Reserved1e0 c.Uint32T + Reserved1e4 c.Uint32T + Reserved1e8 c.Uint32T + Reserved1ec c.Uint32T + Reserved1f0 c.Uint32T + Reserved1f4 c.Uint32T + Reserved1f8 c.Uint32T + Reserved1fc c.Uint32T + Reserved200 c.Uint32T + Reserved204 c.Uint32T + Reserved208 c.Uint32T + Reserved20c c.Uint32T + Reserved210 c.Uint32T + Reserved214 c.Uint32T + Reserved218 c.Uint32T + Reserved21c c.Uint32T + Reserved220 c.Uint32T + Reserved224 c.Uint32T + Reserved228 c.Uint32T + Reserved22c c.Uint32T + Reserved230 c.Uint32T + Reserved234 c.Uint32T + Reserved238 c.Uint32T + Reserved23c c.Uint32T + Reserved240 c.Uint32T + Reserved244 c.Uint32T + Reserved248 c.Uint32T + Reserved24c c.Uint32T + Reserved250 c.Uint32T + Reserved254 c.Uint32T + Reserved258 c.Uint32T + Reserved25c c.Uint32T + Reserved260 c.Uint32T + Reserved264 c.Uint32T + Reserved268 c.Uint32T + Reserved26c c.Uint32T + Reserved270 c.Uint32T + Reserved274 c.Uint32T + Reserved278 c.Uint32T + Reserved27c c.Uint32T + Reserved280 c.Uint32T + Reserved284 c.Uint32T + Reserved288 c.Uint32T + Reserved28c c.Uint32T + Reserved290 c.Uint32T + Reserved294 c.Uint32T + Reserved298 c.Uint32T + Reserved29c c.Uint32T + Reserved2a0 c.Uint32T + Reserved2a4 c.Uint32T + Reserved2a8 c.Uint32T + Reserved2ac c.Uint32T + Reserved2b0 c.Uint32T + Reserved2b4 c.Uint32T + Reserved2b8 c.Uint32T + Reserved2bc c.Uint32T + Reserved2c0 c.Uint32T + Reserved2c4 c.Uint32T + Reserved2c8 c.Uint32T + Reserved2cc c.Uint32T + Reserved2d0 c.Uint32T + Reserved2d4 c.Uint32T + Reserved2d8 c.Uint32T + Reserved2dc c.Uint32T + Reserved2e0 c.Uint32T + Reserved2e4 c.Uint32T + Reserved2e8 c.Uint32T + Reserved2ec c.Uint32T + Reserved2f0 c.Uint32T + Reserved2f4 c.Uint32T + Reserved2f8 c.Uint32T + Reserved2fc c.Uint32T + Reserved300 c.Uint32T + Reserved304 c.Uint32T + Reserved308 c.Uint32T + Reserved30c c.Uint32T + Reserved310 c.Uint32T + Reserved314 c.Uint32T + Reserved318 c.Uint32T + Reserved31c c.Uint32T + Reserved320 c.Uint32T + Reserved324 c.Uint32T + Reserved328 c.Uint32T + Reserved32c c.Uint32T + Reserved330 c.Uint32T + Reserved334 c.Uint32T + Reserved338 c.Uint32T + Reserved33c c.Uint32T + Reserved340 c.Uint32T + Reserved344 c.Uint32T + Reserved348 c.Uint32T + Reserved34c c.Uint32T + Reserved350 c.Uint32T + Reserved354 c.Uint32T + Reserved358 c.Uint32T + Reserved35c c.Uint32T + Reserved360 c.Uint32T + Reserved364 c.Uint32T + Reserved368 c.Uint32T + Reserved36c c.Uint32T + Reserved370 c.Uint32T + Reserved374 c.Uint32T + Reserved378 c.Uint32T + Reserved37c c.Uint32T + Reserved380 c.Uint32T + Reserved384 c.Uint32T + Reserved388 c.Uint32T + Reserved38c c.Uint32T + Reserved390 c.Uint32T + Reserved394 c.Uint32T + Reserved398 c.Uint32T + Reserved39c c.Uint32T + Reserved3a0 c.Uint32T + Reserved3a4 c.Uint32T + Reserved3a8 c.Uint32T + Reserved3ac c.Uint32T + Reserved3b0 c.Uint32T + Reserved3b4 c.Uint32T + Reserved3b8 c.Uint32T + Reserved3bc c.Uint32T + Reserved3c0 c.Uint32T + Reserved3c4 c.Uint32T + Reserved3c8 c.Uint32T + Reserved3cc c.Uint32T + Reserved3d0 c.Uint32T + Reserved3d4 c.Uint32T + Reserved3d8 c.Uint32T + Reserved3dc c.Uint32T + Reserved3e0 c.Uint32T + Reserved3e4 c.Uint32T + Reserved3e8 c.Uint32T + Reserved3ec c.Uint32T + Reserved3f0 c.Uint32T + Reserved3f4 c.Uint32T + Reserved3f8 c.Uint32T + Reserved3fc c.Uint32T + Reserved400 c.Uint32T + Reserved404 c.Uint32T + Reserved408 c.Uint32T + Reserved40c c.Uint32T + Reserved410 c.Uint32T + Reserved414 c.Uint32T + Reserved418 c.Uint32T + Reserved41c c.Uint32T + Reserved420 c.Uint32T + Reserved424 c.Uint32T + Reserved428 c.Uint32T + Reserved42c c.Uint32T + Reserved430 c.Uint32T + Reserved434 c.Uint32T + Reserved438 c.Uint32T + Reserved43c c.Uint32T + Reserved440 c.Uint32T + Reserved444 c.Uint32T + Reserved448 c.Uint32T + Reserved44c c.Uint32T + Reserved450 c.Uint32T + Reserved454 c.Uint32T + Reserved458 c.Uint32T + Reserved45c c.Uint32T + Reserved460 c.Uint32T + Reserved464 c.Uint32T + Reserved468 c.Uint32T + Reserved46c c.Uint32T + Reserved470 c.Uint32T + Reserved474 c.Uint32T + Reserved478 c.Uint32T + Reserved47c c.Uint32T + Reserved480 c.Uint32T + Reserved484 c.Uint32T + Reserved488 c.Uint32T + Reserved48c c.Uint32T + Reserved490 c.Uint32T + Reserved494 c.Uint32T + Reserved498 c.Uint32T + Reserved49c c.Uint32T + Reserved4a0 c.Uint32T + Reserved4a4 c.Uint32T + Reserved4a8 c.Uint32T + Reserved4ac c.Uint32T + Reserved4b0 c.Uint32T + Reserved4b4 c.Uint32T + Reserved4b8 c.Uint32T + Reserved4bc c.Uint32T + Reserved4c0 c.Uint32T + Reserved4c4 c.Uint32T + Reserved4c8 c.Uint32T + Reserved4cc c.Uint32T + Reserved4d0 c.Uint32T + Reserved4d4 c.Uint32T + Reserved4d8 c.Uint32T + Reserved4dc c.Uint32T + Reserved4e0 c.Uint32T + Reserved4e4 c.Uint32T + Reserved4e8 c.Uint32T + Reserved4ec c.Uint32T + Reserved4f0 c.Uint32T + Reserved4f4 c.Uint32T + Reserved4f8 c.Uint32T + Reserved4fc c.Uint32T + Reserved500 c.Uint32T + Reserved504 c.Uint32T + Reserved508 c.Uint32T + Reserved50c c.Uint32T + Reserved510 c.Uint32T + Reserved514 c.Uint32T + Reserved518 c.Uint32T + Reserved51c c.Uint32T + Reserved520 c.Uint32T + Reserved524 c.Uint32T + Reserved528 c.Uint32T + Reserved52c c.Uint32T + Reserved530 c.Uint32T + Reserved534 c.Uint32T + Reserved538 c.Uint32T + Reserved53c c.Uint32T + Reserved540 c.Uint32T + Reserved544 c.Uint32T + Reserved548 c.Uint32T + Reserved54c c.Uint32T + Reserved550 c.Uint32T + Reserved554 c.Uint32T + Reserved558 c.Uint32T + Reserved55c c.Uint32T + Reserved560 c.Uint32T + Reserved564 c.Uint32T + Reserved568 c.Uint32T + Reserved56c c.Uint32T + Reserved570 c.Uint32T + Reserved574 c.Uint32T + Reserved578 c.Uint32T + Reserved57c c.Uint32T + Reserved580 c.Uint32T + Reserved584 c.Uint32T + Reserved588 c.Uint32T + Reserved58c c.Uint32T + Reserved590 c.Uint32T + Reserved594 c.Uint32T + Reserved598 c.Uint32T + Reserved59c c.Uint32T + Reserved5a0 c.Uint32T + Reserved5a4 c.Uint32T + Reserved5a8 c.Uint32T + Reserved5ac c.Uint32T + Reserved5b0 c.Uint32T + Reserved5b4 c.Uint32T + Reserved5b8 c.Uint32T + Reserved5bc c.Uint32T + Reserved5c0 c.Uint32T + Reserved5c4 c.Uint32T + Reserved5c8 c.Uint32T + Reserved5cc c.Uint32T + Reserved5d0 c.Uint32T + Reserved5d4 c.Uint32T + Reserved5d8 c.Uint32T + Reserved5dc c.Uint32T + Reserved5e0 c.Uint32T + Reserved5e4 c.Uint32T + Reserved5e8 c.Uint32T + Reserved5ec c.Uint32T + Reserved5f0 c.Uint32T + Reserved5f4 c.Uint32T + Reserved5f8 c.Uint32T + Reserved5fc c.Uint32T + Reserved600 c.Uint32T + Reserved604 c.Uint32T + Reserved608 c.Uint32T + Reserved60c c.Uint32T + Reserved610 c.Uint32T + Reserved614 c.Uint32T + Reserved618 c.Uint32T + Reserved61c c.Uint32T + Reserved620 c.Uint32T + Reserved624 c.Uint32T + Reserved628 c.Uint32T + Reserved62c c.Uint32T + Reserved630 c.Uint32T + Reserved634 c.Uint32T + Reserved638 c.Uint32T + Reserved63c c.Uint32T + Reserved640 c.Uint32T + Reserved644 c.Uint32T + Reserved648 c.Uint32T + Reserved64c c.Uint32T + Reserved650 c.Uint32T + Reserved654 c.Uint32T + Reserved658 c.Uint32T + Reserved65c c.Uint32T + Reserved660 c.Uint32T + Reserved664 c.Uint32T + Reserved668 c.Uint32T + Reserved66c c.Uint32T + Reserved670 c.Uint32T + Reserved674 c.Uint32T + Reserved678 c.Uint32T + Reserved67c c.Uint32T + Reserved680 c.Uint32T + Reserved684 c.Uint32T + Reserved688 c.Uint32T + Reserved68c c.Uint32T + Reserved690 c.Uint32T + Reserved694 c.Uint32T + Reserved698 c.Uint32T + Reserved69c c.Uint32T + Reserved6a0 c.Uint32T + Reserved6a4 c.Uint32T + Reserved6a8 c.Uint32T + Reserved6ac c.Uint32T + Reserved6b0 c.Uint32T + Reserved6b4 c.Uint32T + Reserved6b8 c.Uint32T + Reserved6bc c.Uint32T + Reserved6c0 c.Uint32T + Reserved6c4 c.Uint32T + Reserved6c8 c.Uint32T + Reserved6cc c.Uint32T + Reserved6d0 c.Uint32T + Reserved6d4 c.Uint32T + Reserved6d8 c.Uint32T + Reserved6dc c.Uint32T + Reserved6e0 c.Uint32T + Reserved6e4 c.Uint32T + Reserved6e8 c.Uint32T + Reserved6ec c.Uint32T + Reserved6f0 c.Uint32T + Reserved6f4 c.Uint32T + Reserved6f8 c.Uint32T + Reserved6fc c.Uint32T + Reserved700 c.Uint32T + Reserved704 c.Uint32T + Reserved708 c.Uint32T + Reserved70c c.Uint32T + Reserved710 c.Uint32T + Reserved714 c.Uint32T + Reserved718 c.Uint32T + Reserved71c c.Uint32T + Reserved720 c.Uint32T + Reserved724 c.Uint32T + Reserved728 c.Uint32T + Reserved72c c.Uint32T + Reserved730 c.Uint32T + Reserved734 c.Uint32T + Reserved738 c.Uint32T + Reserved73c c.Uint32T + Reserved740 c.Uint32T + Reserved744 c.Uint32T + Reserved748 c.Uint32T + Reserved74c c.Uint32T + Reserved750 c.Uint32T + Reserved754 c.Uint32T + Reserved758 c.Uint32T + Reserved75c c.Uint32T + Reserved760 c.Uint32T + Reserved764 c.Uint32T + Reserved768 c.Uint32T + Reserved76c c.Uint32T + Reserved770 c.Uint32T + Reserved774 c.Uint32T + Reserved778 c.Uint32T + Reserved77c c.Uint32T + Reserved780 c.Uint32T + Reserved784 c.Uint32T + Reserved788 c.Uint32T + Reserved78c c.Uint32T + Reserved790 c.Uint32T + Reserved794 c.Uint32T + Reserved798 c.Uint32T + Reserved79c c.Uint32T + Reserved7a0 c.Uint32T + Reserved7a4 c.Uint32T + Reserved7a8 c.Uint32T + Reserved7ac c.Uint32T + Reserved7b0 c.Uint32T + Reserved7b4 c.Uint32T + Reserved7b8 c.Uint32T + Reserved7bc c.Uint32T + Reserved7c0 c.Uint32T + Reserved7c4 c.Uint32T + Reserved7c8 c.Uint32T + Reserved7cc c.Uint32T + Reserved7d0 c.Uint32T + Reserved7d4 c.Uint32T + Reserved7d8 c.Uint32T + Reserved7dc c.Uint32T + Reserved7e0 c.Uint32T + Reserved7e4 c.Uint32T + Reserved7e8 c.Uint32T + Reserved7ec c.Uint32T + Reserved7f0 c.Uint32T + Reserved7f4 c.Uint32T + Reserved7f8 c.Uint32T + Reserved7fc c.Uint32T + Core1MacIntrMap struct { + Val c.Uint32T + } + Core1MacNmiMap struct { + Val c.Uint32T + } + Core1PwrIntrMap struct { + Val c.Uint32T + } + Core1BbIntMap struct { + Val c.Uint32T + } + Core1BtMacIntMap struct { + Val c.Uint32T + } + Core1BtBbIntMap struct { + Val c.Uint32T + } + Core1BtBbNmiMap struct { + Val c.Uint32T + } + Core1RwbtIrqMap struct { + Val c.Uint32T + } + Core1RwbleIrqMap struct { + Val c.Uint32T + } + Core1RwbtNmiMap struct { + Val c.Uint32T + } + Core1RwbleNmiMap struct { + Val c.Uint32T + } + Core1I2cMstIntMap struct { + Val c.Uint32T + } + Core1Slc0IntrMap struct { + Val c.Uint32T + } + Core1Slc1IntrMap struct { + Val c.Uint32T + } + Core1Uhci0IntrMap struct { + Val c.Uint32T + } + Core1Uhci1IntrMap struct { + Val c.Uint32T + } + Core1GpioInterruptProMap struct { + Val c.Uint32T + } + Core1GpioInterruptProNmiMap struct { + Val c.Uint32T + } + Core1GpioInterruptAppMap struct { + Val c.Uint32T + } + Core1GpioInterruptAppNmiMap struct { + Val c.Uint32T + } + Core1SpiIntr1Map struct { + Val c.Uint32T + } + Core1SpiIntr2Map struct { + Val c.Uint32T + } + Core1SpiIntr3Map struct { + Val c.Uint32T + } + Core1SpiIntr4Map struct { + Val c.Uint32T + } + Core1LcdCamIntMap struct { + Val c.Uint32T + } + Core1I2s0IntMap struct { + Val c.Uint32T + } + Core1I2s1IntMap struct { + Val c.Uint32T + } + Core1UartIntrMap struct { + Val c.Uint32T + } + Core1Uart1IntrMap struct { + Val c.Uint32T + } + Core1Uart2IntrMap struct { + Val c.Uint32T + } + Core1SdioHostInterruptMap struct { + Val c.Uint32T + } + Core1Pwm0IntrMap struct { + Val c.Uint32T + } + Core1Pwm1IntrMap struct { + Val c.Uint32T + } + Core1Pwm2IntrMap struct { + Val c.Uint32T + } + Core1Pwm3IntrMap struct { + Val c.Uint32T + } + Core1LedcIntMap struct { + Val c.Uint32T + } + Core1EfuseIntMap struct { + Val c.Uint32T + } + Core1CanIntMap struct { + Val c.Uint32T + } + Core1UsbIntrMap struct { + Val c.Uint32T + } + Core1RtcCoreIntrMap struct { + Val c.Uint32T + } + Core1RmtIntrMap struct { + Val c.Uint32T + } + Core1PcntIntrMap struct { + Val c.Uint32T + } + Core1I2cExt0IntrMap struct { + Val c.Uint32T + } + Core1I2cExt1IntrMap struct { + Val c.Uint32T + } + Core1Spi2DmaIntMap struct { + Val c.Uint32T + } + Core1Spi3DmaIntMap struct { + Val c.Uint32T + } + Core1Spi4DmaIntMap struct { + Val c.Uint32T + } + Core1WdgIntMap struct { + Val c.Uint32T + } + Core1TimerInt1Map struct { + Val c.Uint32T + } + Core1TimerInt2Map struct { + Val c.Uint32T + } + Core1TgT0IntMap struct { + Val c.Uint32T + } + Core1TgT1IntMap struct { + Val c.Uint32T + } + Core1TgWdtIntMap struct { + Val c.Uint32T + } + Core1Tg1T0IntMap struct { + Val c.Uint32T + } + Core1Tg1T1IntMap struct { + Val c.Uint32T + } + Core1Tg1WdtIntMap struct { + Val c.Uint32T + } + Core1CacheIaIntMap struct { + Val c.Uint32T + } + Core1SystimerTarget0IntMap struct { + Val c.Uint32T + } + Core1SystimerTarget1IntMap struct { + Val c.Uint32T + } + Core1SystimerTarget2IntMap struct { + Val c.Uint32T + } + Core1SpiMemRejectIntrMap struct { + Val c.Uint32T + } + Core1DcachePreloadIntMap struct { + Val c.Uint32T + } + Core1IcachePreloadIntMap struct { + Val c.Uint32T + } + Core1DcacheSyncIntMap struct { + Val c.Uint32T + } + Core1IcacheSyncIntMap struct { + Val c.Uint32T + } + Core1ApbAdcIntMap struct { + Val c.Uint32T + } + Core1DmaInCh0IntMap struct { + Val c.Uint32T + } + Core1DmaInCh1IntMap struct { + Val c.Uint32T + } + Core1DmaInCh2IntMap struct { + Val c.Uint32T + } + Core1DmaInCh3IntMap struct { + Val c.Uint32T + } + Core1DmaInCh4IntMap struct { + Val c.Uint32T + } + Core1DmaOutCh0IntMap struct { + Val c.Uint32T + } + Core1DmaOutCh1IntMap struct { + Val c.Uint32T + } + Core1DmaOutCh2IntMap struct { + Val c.Uint32T + } + Core1DmaOutCh3IntMap struct { + Val c.Uint32T + } + Core1DmaOutCh4IntMap struct { + Val c.Uint32T + } + Core1RsaIntMap struct { + Val c.Uint32T + } + Core1AesIntMap struct { + Val c.Uint32T + } + Core1ShaIntMap struct { + Val c.Uint32T + } + Core1CpuIntrFromCpu0Map struct { + Val c.Uint32T + } + Core1CpuIntrFromCpu1Map struct { + Val c.Uint32T + } + Core1CpuIntrFromCpu2Map struct { + Val c.Uint32T + } + Core1CpuIntrFromCpu3Map struct { + Val c.Uint32T + } + Core1AssistDebugIntrMap struct { + Val c.Uint32T + } + Core1DmaApbperiPmsMonitorViolateIntrMap struct { + Val c.Uint32T + } + Core1Core0Iram0PmsMonitorViolateIntrMap struct { + Val c.Uint32T + } + Core1Core0Dram0PmsMonitorViolateIntrMap struct { + Val c.Uint32T + } + Core1Core0PifPmsMonitorViolateIntrMap struct { + Val c.Uint32T + } + Core1Core0PifPmsMonitorViolateSizeIntrMap struct { + Val c.Uint32T + } + Core1Core1Iram0PmsMonitorViolateIntrMap struct { + Val c.Uint32T + } + Core1Core1Dram0PmsMonitorViolateIntrMap struct { + Val c.Uint32T + } + Core1Core1PifPmsMonitorViolateIntrMap struct { + Val c.Uint32T + } + Core1Core1PifPmsMonitorViolateSizeIntrMap struct { + Val c.Uint32T + } + Core1BackupPmsViolateIntrMap struct { + Val c.Uint32T + } + Core1CacheCore0AcsIntMap struct { + Val c.Uint32T + } + Core1CacheCore1AcsIntMap struct { + Val c.Uint32T + } + Core1UsbDeviceIntMap struct { + Val c.Uint32T + } + Core1PeriBackupIntMap struct { + Val c.Uint32T + } + Core1DmaExtmemRejectIntMap struct { + Val c.Uint32T + } + Core1IntrStatus0 c.Uint32T + Core1IntrStatus1 c.Uint32T + Core1IntrStatus2 c.Uint32T + Core1IntrStatus3 c.Uint32T + Core1ClockGate struct { + Val c.Uint32T + } + Reserved9a0 c.Uint32T + Reserved9a4 c.Uint32T + Reserved9a8 c.Uint32T + Reserved9ac c.Uint32T + Reserved9b0 c.Uint32T + Reserved9b4 c.Uint32T + Reserved9b8 c.Uint32T + Reserved9bc c.Uint32T + Reserved9c0 c.Uint32T + Reserved9c4 c.Uint32T + Reserved9c8 c.Uint32T + Reserved9cc c.Uint32T + Reserved9d0 c.Uint32T + Reserved9d4 c.Uint32T + Reserved9d8 c.Uint32T + Reserved9dc c.Uint32T + Reserved9e0 c.Uint32T + Reserved9e4 c.Uint32T + Reserved9e8 c.Uint32T + Reserved9ec c.Uint32T + Reserved9f0 c.Uint32T + Reserved9f4 c.Uint32T + Reserved9f8 c.Uint32T + Reserved9fc c.Uint32T + ReservedA00 c.Uint32T + ReservedA04 c.Uint32T + ReservedA08 c.Uint32T + ReservedA0c c.Uint32T + ReservedA10 c.Uint32T + ReservedA14 c.Uint32T + ReservedA18 c.Uint32T + ReservedA1c c.Uint32T + ReservedA20 c.Uint32T + ReservedA24 c.Uint32T + ReservedA28 c.Uint32T + ReservedA2c c.Uint32T + ReservedA30 c.Uint32T + ReservedA34 c.Uint32T + ReservedA38 c.Uint32T + ReservedA3c c.Uint32T + ReservedA40 c.Uint32T + ReservedA44 c.Uint32T + ReservedA48 c.Uint32T + ReservedA4c c.Uint32T + ReservedA50 c.Uint32T + ReservedA54 c.Uint32T + ReservedA58 c.Uint32T + ReservedA5c c.Uint32T + ReservedA60 c.Uint32T + ReservedA64 c.Uint32T + ReservedA68 c.Uint32T + ReservedA6c c.Uint32T + ReservedA70 c.Uint32T + ReservedA74 c.Uint32T + ReservedA78 c.Uint32T + ReservedA7c c.Uint32T + ReservedA80 c.Uint32T + ReservedA84 c.Uint32T + ReservedA88 c.Uint32T + ReservedA8c c.Uint32T + ReservedA90 c.Uint32T + ReservedA94 c.Uint32T + ReservedA98 c.Uint32T + ReservedA9c c.Uint32T + ReservedAa0 c.Uint32T + ReservedAa4 c.Uint32T + ReservedAa8 c.Uint32T + ReservedAac c.Uint32T + ReservedAb0 c.Uint32T + ReservedAb4 c.Uint32T + ReservedAb8 c.Uint32T + ReservedAbc c.Uint32T + ReservedAc0 c.Uint32T + ReservedAc4 c.Uint32T + ReservedAc8 c.Uint32T + ReservedAcc c.Uint32T + ReservedAd0 c.Uint32T + ReservedAd4 c.Uint32T + ReservedAd8 c.Uint32T + ReservedAdc c.Uint32T + ReservedAe0 c.Uint32T + ReservedAe4 c.Uint32T + ReservedAe8 c.Uint32T + ReservedAec c.Uint32T + ReservedAf0 c.Uint32T + ReservedAf4 c.Uint32T + ReservedAf8 c.Uint32T + ReservedAfc c.Uint32T + ReservedB00 c.Uint32T + ReservedB04 c.Uint32T + ReservedB08 c.Uint32T + ReservedB0c c.Uint32T + ReservedB10 c.Uint32T + ReservedB14 c.Uint32T + ReservedB18 c.Uint32T + ReservedB1c c.Uint32T + ReservedB20 c.Uint32T + ReservedB24 c.Uint32T + ReservedB28 c.Uint32T + ReservedB2c c.Uint32T + ReservedB30 c.Uint32T + ReservedB34 c.Uint32T + ReservedB38 c.Uint32T + ReservedB3c c.Uint32T + ReservedB40 c.Uint32T + ReservedB44 c.Uint32T + ReservedB48 c.Uint32T + ReservedB4c c.Uint32T + ReservedB50 c.Uint32T + ReservedB54 c.Uint32T + ReservedB58 c.Uint32T + ReservedB5c c.Uint32T + ReservedB60 c.Uint32T + ReservedB64 c.Uint32T + ReservedB68 c.Uint32T + ReservedB6c c.Uint32T + ReservedB70 c.Uint32T + ReservedB74 c.Uint32T + ReservedB78 c.Uint32T + ReservedB7c c.Uint32T + ReservedB80 c.Uint32T + ReservedB84 c.Uint32T + ReservedB88 c.Uint32T + ReservedB8c c.Uint32T + ReservedB90 c.Uint32T + ReservedB94 c.Uint32T + ReservedB98 c.Uint32T + ReservedB9c c.Uint32T + ReservedBa0 c.Uint32T + ReservedBa4 c.Uint32T + ReservedBa8 c.Uint32T + ReservedBac c.Uint32T + ReservedBb0 c.Uint32T + ReservedBb4 c.Uint32T + ReservedBb8 c.Uint32T + ReservedBbc c.Uint32T + ReservedBc0 c.Uint32T + ReservedBc4 c.Uint32T + ReservedBc8 c.Uint32T + ReservedBcc c.Uint32T + ReservedBd0 c.Uint32T + ReservedBd4 c.Uint32T + ReservedBd8 c.Uint32T + ReservedBdc c.Uint32T + ReservedBe0 c.Uint32T + ReservedBe4 c.Uint32T + ReservedBe8 c.Uint32T + ReservedBec c.Uint32T + ReservedBf0 c.Uint32T + ReservedBf4 c.Uint32T + ReservedBf8 c.Uint32T + ReservedBfc c.Uint32T + ReservedC00 c.Uint32T + ReservedC04 c.Uint32T + ReservedC08 c.Uint32T + ReservedC0c c.Uint32T + ReservedC10 c.Uint32T + ReservedC14 c.Uint32T + ReservedC18 c.Uint32T + ReservedC1c c.Uint32T + ReservedC20 c.Uint32T + ReservedC24 c.Uint32T + ReservedC28 c.Uint32T + ReservedC2c c.Uint32T + ReservedC30 c.Uint32T + ReservedC34 c.Uint32T + ReservedC38 c.Uint32T + ReservedC3c c.Uint32T + ReservedC40 c.Uint32T + ReservedC44 c.Uint32T + ReservedC48 c.Uint32T + ReservedC4c c.Uint32T + ReservedC50 c.Uint32T + ReservedC54 c.Uint32T + ReservedC58 c.Uint32T + ReservedC5c c.Uint32T + ReservedC60 c.Uint32T + ReservedC64 c.Uint32T + ReservedC68 c.Uint32T + ReservedC6c c.Uint32T + ReservedC70 c.Uint32T + ReservedC74 c.Uint32T + ReservedC78 c.Uint32T + ReservedC7c c.Uint32T + ReservedC80 c.Uint32T + ReservedC84 c.Uint32T + ReservedC88 c.Uint32T + ReservedC8c c.Uint32T + ReservedC90 c.Uint32T + ReservedC94 c.Uint32T + ReservedC98 c.Uint32T + ReservedC9c c.Uint32T + ReservedCa0 c.Uint32T + ReservedCa4 c.Uint32T + ReservedCa8 c.Uint32T + ReservedCac c.Uint32T + ReservedCb0 c.Uint32T + ReservedCb4 c.Uint32T + ReservedCb8 c.Uint32T + ReservedCbc c.Uint32T + ReservedCc0 c.Uint32T + ReservedCc4 c.Uint32T + ReservedCc8 c.Uint32T + ReservedCcc c.Uint32T + ReservedCd0 c.Uint32T + ReservedCd4 c.Uint32T + ReservedCd8 c.Uint32T + ReservedCdc c.Uint32T + ReservedCe0 c.Uint32T + ReservedCe4 c.Uint32T + ReservedCe8 c.Uint32T + ReservedCec c.Uint32T + ReservedCf0 c.Uint32T + ReservedCf4 c.Uint32T + ReservedCf8 c.Uint32T + ReservedCfc c.Uint32T + ReservedD00 c.Uint32T + ReservedD04 c.Uint32T + ReservedD08 c.Uint32T + ReservedD0c c.Uint32T + ReservedD10 c.Uint32T + ReservedD14 c.Uint32T + ReservedD18 c.Uint32T + ReservedD1c c.Uint32T + ReservedD20 c.Uint32T + ReservedD24 c.Uint32T + ReservedD28 c.Uint32T + ReservedD2c c.Uint32T + ReservedD30 c.Uint32T + ReservedD34 c.Uint32T + ReservedD38 c.Uint32T + ReservedD3c c.Uint32T + ReservedD40 c.Uint32T + ReservedD44 c.Uint32T + ReservedD48 c.Uint32T + ReservedD4c c.Uint32T + ReservedD50 c.Uint32T + ReservedD54 c.Uint32T + ReservedD58 c.Uint32T + ReservedD5c c.Uint32T + ReservedD60 c.Uint32T + ReservedD64 c.Uint32T + ReservedD68 c.Uint32T + ReservedD6c c.Uint32T + ReservedD70 c.Uint32T + ReservedD74 c.Uint32T + ReservedD78 c.Uint32T + ReservedD7c c.Uint32T + ReservedD80 c.Uint32T + ReservedD84 c.Uint32T + ReservedD88 c.Uint32T + ReservedD8c c.Uint32T + ReservedD90 c.Uint32T + ReservedD94 c.Uint32T + ReservedD98 c.Uint32T + ReservedD9c c.Uint32T + ReservedDa0 c.Uint32T + ReservedDa4 c.Uint32T + ReservedDa8 c.Uint32T + ReservedDac c.Uint32T + ReservedDb0 c.Uint32T + ReservedDb4 c.Uint32T + ReservedDb8 c.Uint32T + ReservedDbc c.Uint32T + ReservedDc0 c.Uint32T + ReservedDc4 c.Uint32T + ReservedDc8 c.Uint32T + ReservedDcc c.Uint32T + ReservedDd0 c.Uint32T + ReservedDd4 c.Uint32T + ReservedDd8 c.Uint32T + ReservedDdc c.Uint32T + ReservedDe0 c.Uint32T + ReservedDe4 c.Uint32T + ReservedDe8 c.Uint32T + ReservedDec c.Uint32T + ReservedDf0 c.Uint32T + ReservedDf4 c.Uint32T + ReservedDf8 c.Uint32T + ReservedDfc c.Uint32T + ReservedE00 c.Uint32T + ReservedE04 c.Uint32T + ReservedE08 c.Uint32T + ReservedE0c c.Uint32T + ReservedE10 c.Uint32T + ReservedE14 c.Uint32T + ReservedE18 c.Uint32T + ReservedE1c c.Uint32T + ReservedE20 c.Uint32T + ReservedE24 c.Uint32T + ReservedE28 c.Uint32T + ReservedE2c c.Uint32T + ReservedE30 c.Uint32T + ReservedE34 c.Uint32T + ReservedE38 c.Uint32T + ReservedE3c c.Uint32T + ReservedE40 c.Uint32T + ReservedE44 c.Uint32T + ReservedE48 c.Uint32T + ReservedE4c c.Uint32T + ReservedE50 c.Uint32T + ReservedE54 c.Uint32T + ReservedE58 c.Uint32T + ReservedE5c c.Uint32T + ReservedE60 c.Uint32T + ReservedE64 c.Uint32T + ReservedE68 c.Uint32T + ReservedE6c c.Uint32T + ReservedE70 c.Uint32T + ReservedE74 c.Uint32T + ReservedE78 c.Uint32T + ReservedE7c c.Uint32T + ReservedE80 c.Uint32T + ReservedE84 c.Uint32T + ReservedE88 c.Uint32T + ReservedE8c c.Uint32T + ReservedE90 c.Uint32T + ReservedE94 c.Uint32T + ReservedE98 c.Uint32T + ReservedE9c c.Uint32T + ReservedEa0 c.Uint32T + ReservedEa4 c.Uint32T + ReservedEa8 c.Uint32T + ReservedEac c.Uint32T + ReservedEb0 c.Uint32T + ReservedEb4 c.Uint32T + ReservedEb8 c.Uint32T + ReservedEbc c.Uint32T + ReservedEc0 c.Uint32T + ReservedEc4 c.Uint32T + ReservedEc8 c.Uint32T + ReservedEcc c.Uint32T + ReservedEd0 c.Uint32T + ReservedEd4 c.Uint32T + ReservedEd8 c.Uint32T + ReservedEdc c.Uint32T + ReservedEe0 c.Uint32T + ReservedEe4 c.Uint32T + ReservedEe8 c.Uint32T + ReservedEec c.Uint32T + ReservedEf0 c.Uint32T + ReservedEf4 c.Uint32T + ReservedEf8 c.Uint32T + ReservedEfc c.Uint32T + ReservedF00 c.Uint32T + ReservedF04 c.Uint32T + ReservedF08 c.Uint32T + ReservedF0c c.Uint32T + ReservedF10 c.Uint32T + ReservedF14 c.Uint32T + ReservedF18 c.Uint32T + ReservedF1c c.Uint32T + ReservedF20 c.Uint32T + ReservedF24 c.Uint32T + ReservedF28 c.Uint32T + ReservedF2c c.Uint32T + ReservedF30 c.Uint32T + ReservedF34 c.Uint32T + ReservedF38 c.Uint32T + ReservedF3c c.Uint32T + ReservedF40 c.Uint32T + ReservedF44 c.Uint32T + ReservedF48 c.Uint32T + ReservedF4c c.Uint32T + ReservedF50 c.Uint32T + ReservedF54 c.Uint32T + ReservedF58 c.Uint32T + ReservedF5c c.Uint32T + ReservedF60 c.Uint32T + ReservedF64 c.Uint32T + ReservedF68 c.Uint32T + ReservedF6c c.Uint32T + ReservedF70 c.Uint32T + ReservedF74 c.Uint32T + ReservedF78 c.Uint32T + ReservedF7c c.Uint32T + ReservedF80 c.Uint32T + ReservedF84 c.Uint32T + ReservedF88 c.Uint32T + ReservedF8c c.Uint32T + ReservedF90 c.Uint32T + ReservedF94 c.Uint32T + ReservedF98 c.Uint32T + ReservedF9c c.Uint32T + ReservedFa0 c.Uint32T + ReservedFa4 c.Uint32T + ReservedFa8 c.Uint32T + ReservedFac c.Uint32T + ReservedFb0 c.Uint32T + ReservedFb4 c.Uint32T + ReservedFb8 c.Uint32T + ReservedFbc c.Uint32T + ReservedFc0 c.Uint32T + ReservedFc4 c.Uint32T + ReservedFc8 c.Uint32T + ReservedFcc c.Uint32T + ReservedFd0 c.Uint32T + ReservedFd4 c.Uint32T + ReservedFd8 c.Uint32T + ReservedFdc c.Uint32T + ReservedFe0 c.Uint32T + ReservedFe4 c.Uint32T + ReservedFe8 c.Uint32T + ReservedFec c.Uint32T + ReservedFf0 c.Uint32T + ReservedFf4 c.Uint32T + ReservedFf8 c.Uint32T + Core1InterruptDate struct { + Val c.Uint32T + } +} +type InterruptCore1DevT InterruptCore1DevS diff --git a/esp32/interrupt_reg.go b/esp32/interrupt_reg.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/interrupt_reg.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/interrupt_struct.go b/esp32/interrupt_struct.go new file mode 100644 index 00000000..ed82a132 --- /dev/null +++ b/esp32/interrupt_struct.go @@ -0,0 +1,8 @@ +package freertos + +import _ "unsafe" + +type InterruptDevS struct { + Unused [8]uint8 +} +type InterruptDevT InterruptDevS diff --git a/esp32/interrupts.go b/esp32/interrupts.go new file mode 100644 index 00000000..b83bf835 --- /dev/null +++ b/esp32/interrupts.go @@ -0,0 +1,110 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type PeriphInterrputT c.Int + +const ( + ETS_WIFI_MAC_INTR_SOURCE PeriphInterrputT = 0 + ETS_WIFI_MAC_NMI_SOURCE PeriphInterrputT = 1 + ETS_WIFI_PWR_INTR_SOURCE PeriphInterrputT = 2 + ETS_WIFI_BB_INTR_SOURCE PeriphInterrputT = 3 + ETS_BT_MAC_INTR_SOURCE PeriphInterrputT = 4 + ETS_BT_BB_INTR_SOURCE PeriphInterrputT = 5 + ETS_BT_BB_NMI_SOURCE PeriphInterrputT = 6 + ETS_RWBT_INTR_SOURCE PeriphInterrputT = 7 + ETS_RWBLE_INTR_SOURCE PeriphInterrputT = 8 + ETS_RWBT_NMI_SOURCE PeriphInterrputT = 9 + ETS_RWBLE_NMI_SOURCE PeriphInterrputT = 10 + ETS_I2C_MASTER_SOURCE PeriphInterrputT = 11 + ETS_SLC0_INTR_SOURCE PeriphInterrputT = 12 + ETS_SLC1_INTR_SOURCE PeriphInterrputT = 13 + ETS_UHCI0_INTR_SOURCE PeriphInterrputT = 14 + ETS_UHCI1_INTR_SOURCE PeriphInterrputT = 15 + ETS_GPIO_INTR_SOURCE PeriphInterrputT = 16 + ETS_GPIO_NMI_SOURCE PeriphInterrputT = 17 + ETS_GPIO_INTR_SOURCE2 PeriphInterrputT = 18 + ETS_GPIO_NMI_SOURCE2 PeriphInterrputT = 19 + ETS_SPI1_INTR_SOURCE PeriphInterrputT = 20 + ETS_SPI2_INTR_SOURCE PeriphInterrputT = 21 + ETS_SPI3_INTR_SOURCE PeriphInterrputT = 22 + ETS_LCD_CAM_INTR_SOURCE PeriphInterrputT = 24 + ETS_I2S0_INTR_SOURCE PeriphInterrputT = 25 + ETS_I2S1_INTR_SOURCE PeriphInterrputT = 26 + ETS_UART0_INTR_SOURCE PeriphInterrputT = 27 + ETS_UART1_INTR_SOURCE PeriphInterrputT = 28 + ETS_UART2_INTR_SOURCE PeriphInterrputT = 29 + ETS_SDIO_HOST_INTR_SOURCE PeriphInterrputT = 30 + ETS_PWM0_INTR_SOURCE PeriphInterrputT = 31 + ETS_PWM1_INTR_SOURCE PeriphInterrputT = 32 + ETS_LEDC_INTR_SOURCE PeriphInterrputT = 35 + ETS_EFUSE_INTR_SOURCE PeriphInterrputT = 36 + ETS_TWAI_INTR_SOURCE PeriphInterrputT = 37 + ETS_USB_INTR_SOURCE PeriphInterrputT = 38 + ETS_RTC_CORE_INTR_SOURCE PeriphInterrputT = 39 + ETS_RMT_INTR_SOURCE PeriphInterrputT = 40 + ETS_PCNT_INTR_SOURCE PeriphInterrputT = 41 + ETS_I2C_EXT0_INTR_SOURCE PeriphInterrputT = 42 + ETS_I2C_EXT1_INTR_SOURCE PeriphInterrputT = 43 + ETS_SPI2_DMA_INTR_SOURCE PeriphInterrputT = 44 + ETS_SPI3_DMA_INTR_SOURCE PeriphInterrputT = 45 + ETS_WDT_INTR_SOURCE PeriphInterrputT = 47 + ETS_TIMER1_INTR_SOURCE PeriphInterrputT = 48 + ETS_TIMER2_INTR_SOURCE PeriphInterrputT = 49 + ETS_TG0_T0_LEVEL_INTR_SOURCE PeriphInterrputT = 50 + ETS_TG0_T1_LEVEL_INTR_SOURCE PeriphInterrputT = 51 + ETS_TG0_WDT_LEVEL_INTR_SOURCE PeriphInterrputT = 52 + ETS_TG1_T0_LEVEL_INTR_SOURCE PeriphInterrputT = 53 + ETS_TG1_T1_LEVEL_INTR_SOURCE PeriphInterrputT = 54 + ETS_TG1_WDT_LEVEL_INTR_SOURCE PeriphInterrputT = 55 + ETS_CACHE_IA_INTR_SOURCE PeriphInterrputT = 56 + ETS_SYSTIMER_TARGET0_INTR_SOURCE PeriphInterrputT = 57 + ETS_SYSTIMER_TARGET1_INTR_SOURCE PeriphInterrputT = 58 + ETS_SYSTIMER_TARGET2_INTR_SOURCE PeriphInterrputT = 59 + ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE PeriphInterrputT = 57 + ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE PeriphInterrputT = 58 + ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE PeriphInterrputT = 59 + ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE PeriphInterrputT = 60 + ETS_DCACHE_PRELOAD0_INTR_SOURCE PeriphInterrputT = 61 + ETS_ICACHE_PRELOAD0_INTR_SOURCE PeriphInterrputT = 62 + ETS_DCACHE_SYNC0_INTR_SOURCE PeriphInterrputT = 63 + ETS_ICACHE_SYNC0_INTR_SOURCE PeriphInterrputT = 64 + ETS_APB_ADC_INTR_SOURCE PeriphInterrputT = 65 + ETS_DMA_IN_CH0_INTR_SOURCE PeriphInterrputT = 66 + ETS_DMA_IN_CH1_INTR_SOURCE PeriphInterrputT = 67 + ETS_DMA_IN_CH2_INTR_SOURCE PeriphInterrputT = 68 + ETS_DMA_IN_CH3_INTR_SOURCE PeriphInterrputT = 69 + ETS_DMA_IN_CH4_INTR_SOURCE PeriphInterrputT = 70 + ETS_DMA_OUT_CH0_INTR_SOURCE PeriphInterrputT = 71 + ETS_DMA_OUT_CH1_INTR_SOURCE PeriphInterrputT = 72 + ETS_DMA_OUT_CH2_INTR_SOURCE PeriphInterrputT = 73 + ETS_DMA_OUT_CH3_INTR_SOURCE PeriphInterrputT = 74 + ETS_DMA_OUT_CH4_INTR_SOURCE PeriphInterrputT = 75 + ETS_RSA_INTR_SOURCE PeriphInterrputT = 76 + ETS_AES_INTR_SOURCE PeriphInterrputT = 77 + ETS_SHA_INTR_SOURCE PeriphInterrputT = 78 + ETS_FROM_CPU_INTR0_SOURCE PeriphInterrputT = 79 + ETS_FROM_CPU_INTR1_SOURCE PeriphInterrputT = 80 + ETS_FROM_CPU_INTR2_SOURCE PeriphInterrputT = 81 + ETS_FROM_CPU_INTR3_SOURCE PeriphInterrputT = 82 + ETS_ASSIST_DEBUG_INTR_SOURCE PeriphInterrputT = 83 + ETS_DMA_APBPERI_PMS_INTR_SOURCE PeriphInterrputT = 84 + ETS_CORE0_IRAM0_PMS_INTR_SOURCE PeriphInterrputT = 85 + ETS_CORE0_DRAM0_PMS_INTR_SOURCE PeriphInterrputT = 86 + ETS_CORE0_PIF_PMS_INTR_SOURCE PeriphInterrputT = 87 + ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE PeriphInterrputT = 88 + ETS_CORE1_IRAM0_PMS_INTR_SOURCE PeriphInterrputT = 89 + ETS_CORE1_DRAM0_PMS_INTR_SOURCE PeriphInterrputT = 90 + ETS_CORE1_PIF_PMS_INTR_SOURCE PeriphInterrputT = 91 + ETS_CORE1_PIF_PMS_SIZE_INTR_SOURCE PeriphInterrputT = 92 + ETS_BACKUP_PMS_VIOLATE_INTR_SOURCE PeriphInterrputT = 93 + ETS_CACHE_CORE0_ACS_INTR_SOURCE PeriphInterrputT = 94 + ETS_CACHE_CORE1_ACS_INTR_SOURCE PeriphInterrputT = 95 + ETS_USB_SERIAL_JTAG_INTR_SOURCE PeriphInterrputT = 96 + ETS_PERI_BACKUP_INTR_SOURCE PeriphInterrputT = 97 + ETS_DMA_EXTMEM_REJECT_SOURCE PeriphInterrputT = 98 + ETS_MAX_INTR_SOURCE PeriphInterrputT = 99 +) diff --git a/esp32/intr_types.go b/esp32/intr_types.go new file mode 100644 index 00000000..b9d4270e --- /dev/null +++ b/esp32/intr_types.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +type IntrCpuIdT EspIntrCpuAffinityT diff --git a/esp32/inttypes_ext.go b/esp32/inttypes_ext.go new file mode 100644 index 00000000..9116a3fa --- /dev/null +++ b/esp32/inttypes_ext.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +const PRIuSIZE = "lu" diff --git a/esp32/io_mux.go b/esp32/io_mux.go new file mode 100644 index 00000000..3940ffbb --- /dev/null +++ b/esp32/io_mux.go @@ -0,0 +1,45 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Set the clock source for IO MUX + * + * @note IO MUX clock is shared by submodules like SDM, Glitch Filter. + * The submodule drivers should call this function to detect if the user set the clock differently. + * + * @param clk_src The clock source for IO MUX + * @return + * - ESP_OK: Success + * - ESP_ERR_INVALID_STATE: The IO MUX has been set to another clock source + */ +// llgo:link SocModuleClkT.IoMuxSetClockSource C.io_mux_set_clock_source +func (recv_ SocModuleClkT) IoMuxSetClockSource() EspErrT { + return 0 +} + +type RtcIoStatusT struct { + RtcIoEnabledCnt [22]c.Uint8T + RtcIoUsingMask c.Uint32T +} + +/** + * @brief Enable/Disable LP_IO peripheral clock + * + * @param gpio_num GPIO number + * @param enable true to enable the clock / false to disable the clock + */ +// llgo:link GpioNumT.IoMuxEnableLpIoClock C.io_mux_enable_lp_io_clock +func (recv_ GpioNumT) IoMuxEnableLpIoClock(enable bool) { +} + +/** + * Force disable one LP_IO to clock dependency + * @param gpio_num GPIO number + */ +// llgo:link GpioNumT.IoMuxForceDisableLpIoClock C.io_mux_force_disable_lp_io_clock +func (recv_ GpioNumT) IoMuxForceDisableLpIoClock() { +} diff --git a/esp32/io_mux_reg.go b/esp32/io_mux_reg.go new file mode 100644 index 00000000..f151c2c2 --- /dev/null +++ b/esp32/io_mux_reg.go @@ -0,0 +1,213 @@ +package freertos + +import _ "unsafe" + +const SLP_OE_V = 1 +const SLP_OE_S = 0 +const SLP_SEL_V = 1 +const SLP_SEL_S = 1 +const SLP_PD_V = 1 +const SLP_PD_S = 2 +const SLP_PU_V = 1 +const SLP_PU_S = 3 +const SLP_IE_V = 1 +const SLP_IE_S = 4 +const SLP_DRV = 0x3 +const SLP_DRV_V = 0x3 +const SLP_DRV_S = 5 +const FUN_PD_V = 1 +const FUN_PD_S = 7 +const FUN_PU_V = 1 +const FUN_PU_S = 8 +const FUN_IE_V = 1 +const FUN_IE_S = 9 +const FUN_DRV = 0x3 +const FUN_DRV_V = 0x3 +const FUN_DRV_S = 10 +const MCU_SEL = 0x7 +const MCU_SEL_V = 0x7 +const MCU_SEL_S = 12 +const FILTER_EN_V = 1 +const FILTER_EN_S = 15 +const PIN_FUNC_GPIO = 1 +const SPI_CS1_GPIO_NUM = 26 +const SPI_HD_GPIO_NUM = 27 +const SPI_WP_GPIO_NUM = 28 +const SPI_CS0_GPIO_NUM = 29 +const SPI_CLK_GPIO_NUM = 30 +const SPI_Q_GPIO_NUM = 31 +const SPI_D_GPIO_NUM = 32 +const SPI_D4_GPIO_NUM = 33 +const SPI_D5_GPIO_NUM = 34 +const SPI_D6_GPIO_NUM = 35 +const SPI_D7_GPIO_NUM = 36 +const SPI_DQS_GPIO_NUM = 37 +const SD_CLK_GPIO_NUM = 12 +const SD_CMD_GPIO_NUM = 11 +const SD_DATA0_GPIO_NUM = 13 +const SD_DATA1_GPIO_NUM = 14 +const SD_DATA2_GPIO_NUM = 9 +const SD_DATA3_GPIO_NUM = 10 +const USB_INT_PHY0_DM_GPIO_NUM = 19 +const USB_INT_PHY0_DP_GPIO_NUM = 20 +const XTAL32K_P_GPIO_NUM = 15 +const XTAL32K_N_GPIO_NUM = 16 +const MAX_RTC_GPIO_NUM = 21 +const MAX_PAD_GPIO_NUM = 48 +const MAX_GPIO_NUM = 53 +const PAD_POWER_SEL_V = 0x1 +const PAD_POWER_SEL_S = 15 +const PAD_POWER_SWITCH_DELAY = 0x7 +const PAD_POWER_SWITCH_DELAY_V = 0x7 +const PAD_POWER_SWITCH_DELAY_S = 12 +const CLK_OUT3 = 0xf +const CLK_OUT3_S = 8 +const CLK_OUT2 = 0xf +const CLK_OUT2_S = 4 +const CLK_OUT1 = 0xf +const CLK_OUT1_S = 0 +const FUNC_GPIO0_GPIO0 = 1 +const FUNC_GPIO0_GPIO0_0 = 0 +const FUNC_GPIO1_GPIO1 = 1 +const FUNC_GPIO1_GPIO1_0 = 0 +const FUNC_GPIO2_GPIO2 = 1 +const FUNC_GPIO2_GPIO2_0 = 0 +const FUNC_GPIO3_GPIO3 = 1 +const FUNC_GPIO3_GPIO3_0 = 0 +const FUNC_GPIO4_GPIO4 = 1 +const FUNC_GPIO4_GPIO4_0 = 0 +const FUNC_GPIO5_GPIO5 = 1 +const FUNC_GPIO5_GPIO5_0 = 0 +const FUNC_GPIO6_GPIO6 = 1 +const FUNC_GPIO6_GPIO6_0 = 0 +const FUNC_GPIO7_GPIO7 = 1 +const FUNC_GPIO7_GPIO7_0 = 0 +const FUNC_GPIO8_SUBSPICS1 = 3 +const FUNC_GPIO8_GPIO8 = 1 +const FUNC_GPIO8_GPIO8_0 = 0 +const FUNC_GPIO9_FSPIHD = 4 +const FUNC_GPIO9_SUBSPIHD = 3 +const FUNC_GPIO9_GPIO9 = 1 +const FUNC_GPIO9_GPIO9_0 = 0 +const FUNC_GPIO10_FSPICS0 = 4 +const FUNC_GPIO10_SUBSPICS0 = 3 +const FUNC_GPIO10_FSPIIO4 = 2 +const FUNC_GPIO10_GPIO10 = 1 +const FUNC_GPIO10_GPIO10_0 = 0 +const FUNC_GPIO11_FSPID = 4 +const FUNC_GPIO11_SUBSPID = 3 +const FUNC_GPIO11_FSPIIO5 = 2 +const FUNC_GPIO11_GPIO11 = 1 +const FUNC_GPIO11_GPIO11_0 = 0 +const FUNC_GPIO12_FSPICLK = 4 +const FUNC_GPIO12_SUBSPICLK = 3 +const FUNC_GPIO12_FSPIIO6 = 2 +const FUNC_GPIO12_GPIO12 = 1 +const FUNC_GPIO12_GPIO12_0 = 0 +const FUNC_GPIO13_FSPIQ = 4 +const FUNC_GPIO13_SUBSPIQ = 3 +const FUNC_GPIO13_FSPIIO7 = 2 +const FUNC_GPIO13_GPIO13 = 1 +const FUNC_GPIO13_GPIO13_0 = 0 +const FUNC_GPIO14_FSPIWP = 4 +const FUNC_GPIO14_SUBSPIWP = 3 +const FUNC_GPIO14_FSPIDQS = 2 +const FUNC_GPIO14_GPIO14 = 1 +const FUNC_GPIO14_GPIO14_0 = 0 +const FUNC_XTAL_32K_P_U0RTS = 2 +const FUNC_XTAL_32K_P_GPIO15 = 1 +const FUNC_XTAL_32K_P_GPIO15_0 = 0 +const FUNC_XTAL_32K_N_U0CTS = 2 +const FUNC_XTAL_32K_N_GPIO16 = 1 +const FUNC_XTAL_32K_N_GPIO16_0 = 0 +const FUNC_DAC_1_U1TXD = 2 +const FUNC_DAC_1_GPIO17 = 1 +const FUNC_DAC_1_GPIO17_0 = 0 +const FUNC_DAC_2_CLK_OUT3 = 3 +const FUNC_DAC_2_U1RXD = 2 +const FUNC_DAC_2_GPIO18 = 1 +const FUNC_DAC_2_GPIO18_0 = 0 +const FUNC_GPIO19_CLK_OUT2 = 3 +const FUNC_GPIO19_U1RTS = 2 +const FUNC_GPIO19_GPIO19 = 1 +const FUNC_GPIO19_GPIO19_0 = 0 +const FUNC_GPIO20_CLK_OUT1 = 3 +const FUNC_GPIO20_U1CTS = 2 +const FUNC_GPIO20_GPIO20 = 1 +const FUNC_GPIO20_GPIO20_0 = 0 +const FUNC_GPIO21_GPIO21 = 1 +const FUNC_GPIO21_GPIO21_0 = 0 +const FUNC_SPICS1_GPIO26 = 1 +const FUNC_SPICS1_SPICS1 = 0 +const FUNC_SPIHD_GPIO27 = 1 +const FUNC_SPIHD_SPIHD = 0 +const FUNC_SPIWP_GPIO28 = 1 +const FUNC_SPIWP_SPIWP = 0 +const FUNC_SPICS0_GPIO29 = 1 +const FUNC_SPICS0_SPICS0 = 0 +const FUNC_SPICLK_GPIO30 = 1 +const FUNC_SPICLK_SPICLK = 0 +const FUNC_SPIQ_GPIO31 = 1 +const FUNC_SPIQ_SPIQ = 0 +const FUNC_SPID_GPIO32 = 1 +const FUNC_SPID_SPID = 0 +const FUNC_GPIO33_SPIIO4 = 4 +const FUNC_GPIO33_SUBSPIHD = 3 +const FUNC_GPIO33_FSPIHD = 2 +const FUNC_GPIO33_GPIO33 = 1 +const FUNC_GPIO33_GPIO33_0 = 0 +const FUNC_GPIO34_SPIIO5 = 4 +const FUNC_GPIO34_SUBSPICS0 = 3 +const FUNC_GPIO34_FSPICS0 = 2 +const FUNC_GPIO34_GPIO34 = 1 +const FUNC_GPIO34_GPIO34_0 = 0 +const FUNC_GPIO35_SPIIO6 = 4 +const FUNC_GPIO35_SUBSPID = 3 +const FUNC_GPIO35_FSPID = 2 +const FUNC_GPIO35_GPIO35 = 1 +const FUNC_GPIO35_GPIO35_0 = 0 +const FUNC_GPIO36_SPIIO7 = 4 +const FUNC_GPIO36_SUBSPICLK = 3 +const FUNC_GPIO36_FSPICLK = 2 +const FUNC_GPIO36_GPIO36 = 1 +const FUNC_GPIO36_GPIO36_0 = 0 +const FUNC_GPIO37_SPIDQS = 4 +const FUNC_GPIO37_SUBSPIQ = 3 +const FUNC_GPIO37_FSPIQ = 2 +const FUNC_GPIO37_GPIO37 = 1 +const FUNC_GPIO37_GPIO37_0 = 0 +const FUNC_GPIO38_SUBSPIWP = 3 +const FUNC_GPIO38_FSPIWP = 2 +const FUNC_GPIO38_GPIO38 = 1 +const FUNC_GPIO38_GPIO38_0 = 0 +const FUNC_MTCK_SUBSPICS1 = 3 +const FUNC_MTCK_CLK_OUT3 = 2 +const FUNC_MTCK_GPIO39 = 1 +const FUNC_MTCK_MTCK = 0 +const FUNC_MTDO_CLK_OUT2 = 2 +const FUNC_MTDO_GPIO40 = 1 +const FUNC_MTDO_MTDO = 0 +const FUNC_MTDI_CLK_OUT1 = 2 +const FUNC_MTDI_GPIO41 = 1 +const FUNC_MTDI_MTDI = 0 +const FUNC_MTMS_GPIO42 = 1 +const FUNC_MTMS_MTMS = 0 +const FUNC_U0TXD_CLK_OUT1 = 2 +const FUNC_U0TXD_GPIO43 = 1 +const FUNC_U0TXD_U0TXD = 0 +const FUNC_U0RXD_CLK_OUT2 = 2 +const FUNC_U0RXD_GPIO44 = 1 +const FUNC_U0RXD_U0RXD = 0 +const FUNC_GPIO45_GPIO45 = 1 +const FUNC_GPIO45_GPIO45_0 = 0 +const FUNC_GPIO46_GPIO46 = 1 +const FUNC_GPIO46_GPIO46_0 = 0 +const FUNC_SPICLK_P_SUBSPICLK_DIFF = 2 +const FUNC_SPICLK_P_GPIO47 = 1 +const FUNC_SPICLK_P_SPICLK_DIFF = 0 +const FUNC_SPICLK_N_SUBSPICLK_DIFF = 2 +const FUNC_SPICLK_N_GPIO48 = 1 +const FUNC_SPICLK_N_SPICLK_DIFF = 0 +const IO_MUX_DATE = 0xFFFFFFFF +const IO_MUX_DATE_S = 0 +const IO_MUX_DATE_VERSION = 0x1907160 diff --git a/esp32/isp_hal.go b/esp32/isp_hal.go new file mode 100644 index 00000000..42c16362 --- /dev/null +++ b/esp32/isp_hal.go @@ -0,0 +1,260 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief BF configurations + */ + +type IspHalBfCfgT struct { + PaddingMode IspBfEdgePaddingModeT + PaddingData c.Uint8T + BfTemplate [0][0]c.Uint8T + DenoisingLevel c.Uint8T + PaddingLineTailValidStartPixel c.Uint8T + PaddingLineTailValidEndPixel c.Uint8T +} + +/** + * @brief Demosaic configurations + */ + +type IspHalDemosaicCfgT struct { + GradRatio IspDemosaicGradRatioT + PaddingMode IspDemosaicEdgePaddingModeT + PaddingData c.Uint8T + PaddingLineTailValidStartPixel c.Uint8T + PaddingLineTailValidEndPixel c.Uint8T +} + +/** + * @brief Sharpen configurations + */ + +type IspHalSharpenCfgT struct { + HFreqCoeff IspSharpenHFreqCoeffT + MFreqCoeff IspSharpenMFreqCoeff + HThresh c.Uint8T + LThresh c.Uint8T + PaddingMode IspSharpenEdgePaddingModeT + PaddingData c.Uint8T + SharpenTemplate [0][0]c.Uint8T + PaddingLineTailValidStartPixel c.Uint8T + PaddingLineTailValidEndPixel c.Uint8T +} + +/** + * @brief Context that should be maintained by both the driver and the HAL + */ + +type IspHalContextT struct { + Hw c.Pointer + BfCfg IspHalBfCfgT +} + +/** + * @brief Init the ISP hal and set the ISP to the default configuration. + * + * @note This function should be called first before other hal layer function is called. + * + * @param[in] hal Context of the HAL layer + * @param[in] isp_id ISP ID + */ +// llgo:link (*IspHalContextT).IspHalInit C.isp_hal_init +func (recv_ *IspHalContextT) IspHalInit(isp_id c.Int) { +} + +/** + * @brief Color configurations + */ + +type IspHalColorCfgT struct { + ColorContrast IspColorContrastT + ColorSaturation IspColorSaturationT + ColorHue c.Uint32T + ColorBrightness c.Int +} + +/*--------------------------------------------------------------- + AF +---------------------------------------------------------------*/ +/** + * @brief Configure AF window + * + * @param[in] hal Context of the HAL layer + * @param[in] window_id Window ID + * @param[in] window Window info, see `isp_window_t` + */ +// llgo:link (*IspHalContextT).IspHalAfWindowConfig C.isp_hal_af_window_config +func (recv_ *IspHalContextT) IspHalAfWindowConfig(window_id c.Int, window *IspWindowT) { +} + +/*--------------------------------------------------------------- + AE +---------------------------------------------------------------*/ +/** + * @brief Configure AE window + * + * @param[in] hal Context of the HAL layer + * @param[in] window Window info, see `isp_window_t` + */ +// llgo:link (*IspHalContextT).IspHalAeWindowConfig C.isp_hal_ae_window_config +func (recv_ *IspHalContextT) IspHalAeWindowConfig(window *IspWindowT) { +} + +/*--------------------------------------------------------------- + AWB +---------------------------------------------------------------*/ +/** + * @brief Set the window of the AWB + * + * @param[in] hal Context of the HAL layer + * @param[in] win Pointer to the window of the AWB + * @return + * - true Set success + * - false Invalid arg + */ +// llgo:link (*IspHalContextT).IspHalAwbSetWindowRange C.isp_hal_awb_set_window_range +func (recv_ *IspHalContextT) IspHalAwbSetWindowRange(win *IspWindowT) bool { + return false +} + +/** + * @brief Set the luminance range of the white patch + * + * @param[in] hal Context of the HAL layer + * @param[in] lum_min Minimum luminance + * @param[in] lum_max Maximum luminance + * @return + * - true Set success + * - false Invalid arg + */ +// llgo:link (*IspHalContextT).IspHalAwbSetLuminanceRange C.isp_hal_awb_set_luminance_range +func (recv_ *IspHalContextT) IspHalAwbSetLuminanceRange(lum_min c.Uint32T, lum_max c.Uint32T) bool { + return false +} + +/** + * @brief Set the R/G ratio of the white patch + * + * @param[in] hal Context of the HAL layer + * @param[in] rg_ratio_range Range of Red to Green ratio + * @return + * - true Set success + * - false Invalid arg + */ +// llgo:link (*IspHalContextT).IspHalAwbSetRgRatioRange C.isp_hal_awb_set_rg_ratio_range +func (recv_ *IspHalContextT) IspHalAwbSetRgRatioRange(rg_min c.Float, rg_max c.Float) bool { + return false +} + +/** + * @brief Set the B/R ratio of the white patch + * + * @param[in] hal Context of the HAL layer + * @param[in] bg_ratio_range Range of Blue to Green ratio + * @return + * - true Set success + * - false Invalid arg + */ +// llgo:link (*IspHalContextT).IspHalAwbSetBgRatioRange C.isp_hal_awb_set_bg_ratio_range +func (recv_ *IspHalContextT) IspHalAwbSetBgRatioRange(bg_min c.Float, bg_max c.Float) bool { + return false +} + +/*--------------------------------------------------------------- + BF +---------------------------------------------------------------*/ +/** + * @brief Configure ISP BF + * + * @param[in] hal Context of the HAL layer + * @param[in] config BF config, set NULL to de-config the ISP BF + */ +// llgo:link (*IspHalContextT).IspHalBfConfig C.isp_hal_bf_config +func (recv_ *IspHalContextT) IspHalBfConfig(config *IspHalBfCfgT) { +} + +/*--------------------------------------------------------------- + Color Correction Matrix +---------------------------------------------------------------*/ +/** + * @brief Set Color Correction Matrix + * + * @param[in] hal Context of the HAL layer + * @param[in] saturation Whether to enable saturation when float data overflow + * @param[in] flt_matrix 3x3 RGB correction matrix + * @return + * - true Set success + * - false Invalid argument + */ +// llgo:link (*IspHalContextT).IspHalCcmSetMatrix C.isp_hal_ccm_set_matrix +func (recv_ *IspHalContextT) IspHalCcmSetMatrix(saturation bool, flt_matrix **c.Float) bool { + return false +} + +/*--------------------------------------------------------------- + Demosaic +---------------------------------------------------------------*/ +/** + * @brief Configure ISP Demosaic + * + * @param[in] hal Context of the HAL layer + * @param[in] config Demosaic config, set NULL to de-config the ISP Demosaic + */ +// llgo:link (*IspHalContextT).IspHalDemosaicConfig C.isp_hal_demosaic_config +func (recv_ *IspHalContextT) IspHalDemosaicConfig(config *IspHalDemosaicCfgT) { +} + +/*--------------------------------------------------------------- + INTR +---------------------------------------------------------------*/ +/** + * @brief Clear ISP HW intr event + * + * @param[in] hal Context of the HAL layer + * @param[in] mask HW event mask + */ +// llgo:link (*IspHalContextT).IspHalCheckClearIntrEvent C.isp_hal_check_clear_intr_event +func (recv_ *IspHalContextT) IspHalCheckClearIntrEvent(mask c.Uint32T) c.Uint32T { + return 0 +} + +/*--------------------------------------------------------------- + Sharpness +---------------------------------------------------------------*/ +/** + * @brief Configure ISP sharpeness + * + * @param[in] hal Context of the HAL layer + * @param[in] config Sharpness config, set NULL to de-config the ISP sharpness + */ +// llgo:link (*IspHalContextT).IspHalSharpenConfig C.isp_hal_sharpen_config +func (recv_ *IspHalContextT) IspHalSharpenConfig(config *IspHalSharpenCfgT) { +} + +/*--------------------------------------------------------------- + Histogram +---------------------------------------------------------------*/ +/** + * @brief Configure Histogram window + * + * @param[in] hal Context of the HAL layer + * @param[in] window Window info, see `isp_window_t` + */ +// llgo:link (*IspHalContextT).IspHalHistWindowConfig C.isp_hal_hist_window_config +func (recv_ *IspHalContextT) IspHalHistWindowConfig(window *IspWindowT) { +} + +/** + * @brief Set the color config + * + * @param[in] hal Context of the HAL layer + * @param[in] config Color config, set NULL to de-config the ISP color + */ +// llgo:link (*IspHalContextT).IspHalColorConfig C.isp_hal_color_config +func (recv_ *IspHalContextT) IspHalColorConfig(config *IspHalColorCfgT) { +} diff --git a/esp32/isp_types.go b/esp32/isp_types.go new file mode 100644 index 00000000..37b63d27 --- /dev/null +++ b/esp32/isp_types.go @@ -0,0 +1,239 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ISP_AE_BLOCK_X_NUM = 0 +const ISP_AE_BLOCK_Y_NUM = 0 +const ISP_AF_WINDOW_NUM = 0 +const ISP_BF_TEMPLATE_X_NUMS = 0 +const ISP_BF_TEMPLATE_Y_NUMS = 0 +const ISP_CCM_DIMENSION = 0 +const ISP_DEMOSAIC_GRAD_RATIO_INT_BITS = 8 +const ISP_DEMOSAIC_GRAD_RATIO_DEC_BITS = 8 +const ISP_DEMOSAIC_GRAD_RATIO_RES_BITS = 16 +const ISP_DVP_DATA_SIG_NUM = 0 +const ISP_SHARPEN_TEMPLATE_X_NUMS = 0 +const ISP_SHARPEN_TEMPLATE_Y_NUMS = 0 +const ISP_SHARPEN_H_FREQ_COEF_INT_BITS = 8 +const ISP_SHARPEN_H_FREQ_COEF_DEC_BITS = 8 +const ISP_SHARPEN_H_FREQ_COEF_RES_BITS = 16 +const ISP_SHARPEN_M_FREQ_COEF_INT_BITS = 8 +const ISP_SHARPEN_M_FREQ_COEF_DEC_BITS = 8 +const ISP_SHARPEN_M_FREQ_COEF_RES_BITS = 16 +const ISP_GAMMA_CURVE_POINTS_NUM = 16 +const ISP_HIST_BLOCK_X_NUM = 0 +const ISP_HIST_BLOCK_Y_NUM = 0 +const ISP_HIST_SEGMENT_NUMS = 0 +const ISP_HIST_INTERVAL_NUMS = 0 +const ISP_HIST_WEIGHT_INT_BITS = 8 +const ISP_HIST_WEIGHT_DEC_BITS = 7 +const ISP_HIST_WEIGHT_RES_BITS = 17 +const ISP_HIST_COEFF_INT_BITS = 8 +const ISP_HIST_COEFF_DEC_BITS = 7 +const ISP_HIST_COEFF_RES_BITS = 17 +const ISP_COLOR_CONTRAST_INT_BITS = 1 +const ISP_COLOR_CONTRAST_DEC_BITS = 7 +const ISP_COLOR_CONTRAST_RES_BITS = 24 +const ISP_COLOR_SATURATION_INT_BITS = 1 +const ISP_COLOR_SATURATION_DEC_BITS = 7 +const ISP_COLOR_SATURATION_RES_BITS = 24 +const ISP_LSC_GRAD_RATIO_INT_BITS = 2 +const ISP_LSC_GRAD_RATIO_DEC_BITS = 8 +const ISP_LSC_GRAD_RATIO_RES_BITS = 22 + +type IspClkSrcT c.Int + +/** + * @brief ISP coordinate type + * + */ + +type IspCoordinateT struct { + X c.Uint32T + Y c.Uint32T +} + +/** + * @brief The top left and bottom right coordinates of ISP full window + */ + +type IspWindowT struct { + TopLeft IspCoordinateT + BtmRight IspCoordinateT +} +type IspInputDataSourceT c.Int + +const ( + ISP_INPUT_DATA_SOURCE_CSI IspInputDataSourceT = 0 + ISP_INPUT_DATA_SOURCE_DVP IspInputDataSourceT = 1 + ISP_INPUT_DATA_SOURCE_DWGDMA IspInputDataSourceT = 2 +) + +type IspColorT c.Int + +const ( + ISP_COLOR_RAW8 IspColorT = 16777216 + ISP_COLOR_RAW10 IspColorT = 16777217 + ISP_COLOR_RAW12 IspColorT = 16777218 + ISP_COLOR_RGB888 IspColorT = 33554432 + ISP_COLOR_RGB565 IspColorT = 33554434 + ISP_COLOR_YUV422 IspColorT = 50331649 + ISP_COLOR_YUV420 IspColorT = 50331650 +) + +type IspColorRangeT c.Int + +const ( + ISP_COLOR_RANGE_LIMIT IspColorRangeT = 0 + ISP_COLOR_RANGE_FULL IspColorRangeT = 1 +) + +type IspYuvConvStdT c.Int + +const ( + ISP_YUV_CONV_STD_BT601 IspYuvConvStdT = 0 + ISP_YUV_CONV_STD_BT709 IspYuvConvStdT = 1 +) + +type IspAeSamplePointT c.Int + +const ( + ISP_AE_SAMPLE_POINT_AFTER_DEMOSAIC IspAeSamplePointT = 0 + ISP_AE_SAMPLE_POINT_AFTER_GAMMA IspAeSamplePointT = 1 +) + +type IspAwbSamplePointT c.Int + +const ( + ISP_AWB_SAMPLE_POINT_BEFORE_CCM IspAwbSamplePointT = 0 + ISP_AWB_SAMPLE_POINT_AFTER_CCM IspAwbSamplePointT = 1 +) + +type IspBfEdgePaddingModeT c.Int + +const ( + ISP_BF_EDGE_PADDING_MODE_SRND_DATA IspBfEdgePaddingModeT = 0 + ISP_BF_EDGE_PADDING_MODE_CUSTOM_DATA IspBfEdgePaddingModeT = 1 +) + +/** + * @brief Gradient ratio + */ + +type IspDemosaicGradRatioT struct { + Val c.Uint32T +} +type IspDemosaicEdgePaddingModeT c.Int + +const ( + ISP_DEMOSAIC_EDGE_PADDING_MODE_SRND_DATA IspDemosaicEdgePaddingModeT = 0 + ISP_DEMOSAIC_EDGE_PADDING_MODE_CUSTOM_DATA IspDemosaicEdgePaddingModeT = 1 +) + +/** + * @brief High freq pixel sharpeness coeff + */ + +type IspSharpenHFreqCoeffT struct { + Val c.Uint32T +} + +/** + * @brief Medium freq pixel sharpeness coeff + */ + +type IspSharpenMFreqCoeff struct { + Val c.Uint32T +} +type IspSharpenEdgePaddingModeT c.Int + +const ( + ISP_SHARPEN_EDGE_PADDING_MODE_SRND_DATA IspSharpenEdgePaddingModeT = 0 + ISP_SHARPEN_EDGE_PADDING_MODE_CUSTOM_DATA IspSharpenEdgePaddingModeT = 1 +) + +/** + * @brief Structure that declares the points on an ISP gamma curve + * + * Constraint on pt[n].x: + * When n = 0, pt[n].x = 2 ^ a[n] + * When 0 < n < ISP_GAMMA_CURVE_POINTS_NUM-1, pt[n].x - pt[n-1].x = 2 ^ a[n] + * When n = ISP_GAMMA_CURVE_POINTS_NUM-1, pt[n].x = 255, (pt[n].x + 1) - pt[n-1].x = 2 ^ a[n] + * a[n] within [0, 7] + */ + +type IspGammaCurvePointsT struct { + Pt [16]struct { + X c.Uint8T + Y c.Uint8T + } +} +type IspHistSamplingModeT c.Int + +const ( + ISP_HIST_SAMPLING_RAW_B IspHistSamplingModeT = 0 + ISP_HIST_SAMPLING_RAW_GB IspHistSamplingModeT = 1 + ISP_HIST_SAMPLING_RAW_GR IspHistSamplingModeT = 2 + ISP_HIST_SAMPLING_RAW_R IspHistSamplingModeT = 3 + ISP_HIST_SAMPLING_RGB IspHistSamplingModeT = 4 + ISP_HIST_SAMPLING_YUV_Y IspHistSamplingModeT = 5 + ISP_HIST_SAMPLING_YUV_U IspHistSamplingModeT = 6 + ISP_HIST_SAMPLING_YUV_V IspHistSamplingModeT = 7 +) + +/** + * @brief ISP histogram weight value + */ +type IspHistWeightT struct { + Val c.Uint32T +} + +/** + * @brief ISP histogram coefficient value + */ +type IspHistCoeffT struct { + Val c.Uint32T +} + +/** + * @brief ISP histogram r,g,b coefficient + */ +type IspHistRgbCoefficientT struct { + CoeffR IspHistCoeffT + CoeffG IspHistCoeffT + CoeffB IspHistCoeffT +} + +/** + * @brief ISP histogram result. + */ +type IspHistResultT struct { + HistValue [0]c.Uint32T +} + +/** + * @brief Color contrast value + */ + +type IspColorContrastT struct { + Val c.Uint32T +} + +/** + * @brief Color saturation value + */ + +type IspColorSaturationT struct { + Val c.Uint32T +} + +/** + * @brief LSC gain + */ + +type IspLscGainT struct { + Val c.Uint32T +} diff --git a/esp32/jpeg_defs.go b/esp32/jpeg_defs.go new file mode 100644 index 00000000..a159c1a7 --- /dev/null +++ b/esp32/jpeg_defs.go @@ -0,0 +1,64 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type JpegMarkerCodeT c.Int + +const ( + JPEG_M_SOF0 JpegMarkerCodeT = 65472 + JPEG_M_SOF1 JpegMarkerCodeT = 65473 + JPEG_M_SOF2 JpegMarkerCodeT = 65474 + JPEG_M_SOF3 JpegMarkerCodeT = 65475 + JPEG_M_SOF5 JpegMarkerCodeT = 65477 + JPEG_M_SOF6 JpegMarkerCodeT = 65478 + JPEG_M_SOF7 JpegMarkerCodeT = 65479 + JPEG_M_JPG JpegMarkerCodeT = 65480 + JPEG_M_SOF9 JpegMarkerCodeT = 65481 + JPEG_M_SOF10 JpegMarkerCodeT = 65482 + JPEG_M_SOF11 JpegMarkerCodeT = 65483 + JPEG_M_SOF13 JpegMarkerCodeT = 65485 + JPEG_M_SOF14 JpegMarkerCodeT = 65486 + JPEG_M_SOF15 JpegMarkerCodeT = 65487 + JPEG_M_DHT JpegMarkerCodeT = 65476 + JPEG_M_DAC JpegMarkerCodeT = 65484 + JPEG_M_RST0 JpegMarkerCodeT = 65488 + JPEG_M_RST1 JpegMarkerCodeT = 65489 + JPEG_M_RST2 JpegMarkerCodeT = 65490 + JPEG_M_RST3 JpegMarkerCodeT = 65491 + JPEG_M_RST4 JpegMarkerCodeT = 65492 + JPEG_M_RST5 JpegMarkerCodeT = 65493 + JPEG_M_RST6 JpegMarkerCodeT = 65494 + JPEG_M_RST7 JpegMarkerCodeT = 65495 + JPEG_M_SOI JpegMarkerCodeT = 65496 + JPEG_M_EOI JpegMarkerCodeT = 65497 + JPEG_M_SOS JpegMarkerCodeT = 65498 + JPEG_M_DQT JpegMarkerCodeT = 65499 + JPEG_M_DNL JpegMarkerCodeT = 65500 + JPEG_M_DRI JpegMarkerCodeT = 65501 + JPEG_M_DHP JpegMarkerCodeT = 65502 + JPEG_M_EXP JpegMarkerCodeT = 65503 + JPEG_M_APP0 JpegMarkerCodeT = 65504 + JPEG_M_APP1 JpegMarkerCodeT = 65505 + JPEG_M_APP2 JpegMarkerCodeT = 65506 + JPEG_M_APP3 JpegMarkerCodeT = 65507 + JPEG_M_APP4 JpegMarkerCodeT = 65508 + JPEG_M_APP5 JpegMarkerCodeT = 65509 + JPEG_M_APP6 JpegMarkerCodeT = 65510 + JPEG_M_APP7 JpegMarkerCodeT = 65511 + JPEG_M_APP8 JpegMarkerCodeT = 65512 + JPEG_M_APP9 JpegMarkerCodeT = 65513 + JPEG_M_APP10 JpegMarkerCodeT = 65514 + JPEG_M_APP11 JpegMarkerCodeT = 65515 + JPEG_M_APP12 JpegMarkerCodeT = 65516 + JPEG_M_APP13 JpegMarkerCodeT = 65517 + JPEG_M_APP14 JpegMarkerCodeT = 65518 + JPEG_M_APP15 JpegMarkerCodeT = 65519 + JPEG_M_JPG0 JpegMarkerCodeT = 65520 + JPEG_M_JPG13 JpegMarkerCodeT = 65533 + JPEG_M_COM JpegMarkerCodeT = 65534 + JPEG_M_TEM JpegMarkerCodeT = 65281 + JPEG_M_INV JpegMarkerCodeT = 65535 +) diff --git a/esp32/jpeg_hal.go b/esp32/jpeg_hal.go new file mode 100644 index 00000000..c3d506ff --- /dev/null +++ b/esp32/jpeg_hal.go @@ -0,0 +1,57 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type JpegDevT struct { + Unused [8]uint8 +} +type JpegSocHandleT *JpegDevT + +/** + * Context that should be maintained by both the driver and the HAL + */ + +type JpegHalContextT struct { + Dev JpegSocHandleT +} + +/** + * @brief Initialize the JPEG codec HAL driver + * + * @param hal: JPEG codec HAL context + */ +// llgo:link (*JpegHalContextT).JpegHalInit C.jpeg_hal_init +func (recv_ *JpegHalContextT) JpegHalInit() { +} + +/** + * @brief Deinitialize the JPEG codec HAL driver + * + * @param hal: JPEG codec HAL context + */ +// llgo:link (*JpegHalContextT).JpegHalDeinit C.jpeg_hal_deinit +func (recv_ *JpegHalContextT) JpegHalDeinit() { +} + +// llgo:type C +type JpegConfigDhtTableT func(*JpegHalContextT, *c.Uint8T, *c.Uint8T, *c.Uint32T) + +// llgo:type C +type JpegConfigFrameInfoT func(JpegSocHandleT, c.Uint8T, c.Uint8T, c.Uint8T, c.Uint8T) + +// llgo:type C +type JpegConfigQuantizationCoefficientT func(JpegSocHandleT, *c.Uint32T) + +/** + * Set the quantization coefficients for luminance and chrominance in the JPEG hardware accelerator context. + * + * @param hal Pointer to the JPEG hardware accelerator context. + * @param lqnr Pointer to an array of luminance quantization coefficients. + * @param cqnr Pointer to an array of chrominance quantization coefficients. + */ +// llgo:link (*JpegHalContextT).JpegHalSetQuantizationCoefficient C.jpeg_hal_set_quantization_coefficient +func (recv_ *JpegHalContextT) JpegHalSetQuantizationCoefficient(lqnr *c.Uint32T, cqnr *c.Uint32T) { +} diff --git a/esp32/jpeg_types.go b/esp32/jpeg_types.go new file mode 100644 index 00000000..cb4e3080 --- /dev/null +++ b/esp32/jpeg_types.go @@ -0,0 +1,54 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type JpegCodecModeT c.Int + +const ( + JPEG_CODEC_ENCODER JpegCodecModeT = 0 + JPEG_CODEC_DECODER JpegCodecModeT = 1 +) + +/** + * @brief Structure for recording factor of component. + */ + +type JpegComponentFactorT struct { + Horizontal c.Uint32T + Vertical c.Uint32T +} +type JpegSampleModeT c.Int + +const ( + JPEG_SAMPLE_MODE_YUV444 JpegSampleModeT = 50331648 + JPEG_SAMPLE_MODE_YUV422 JpegSampleModeT = 50331649 + JPEG_SAMPLE_MODE_YUV420 JpegSampleModeT = 50331650 +) + +/** + * @brief Structure for huffman information + */ + +type JpegHuffmanTableInfoT struct { + Info c.Uint8T +} +type JpegDownSamplingTypeT c.Int + +const ( + JPEG_DOWN_SAMPLING_YUV444 JpegDownSamplingTypeT = 50331648 + JPEG_DOWN_SAMPLING_YUV422 JpegDownSamplingTypeT = 50331649 + JPEG_DOWN_SAMPLING_YUV420 JpegDownSamplingTypeT = 50331650 + JPEG_DOWN_SAMPLING_GRAY JpegDownSamplingTypeT = 67108865 +) + +type JpegEncSrcTypeT c.Int + +const ( + JPEG_ENC_SRC_RGB888 JpegEncSrcTypeT = 33554432 + JPEG_ENC_SRC_YUV422 JpegEncSrcTypeT = 50331649 + JPEG_ENC_SRC_RGB565 JpegEncSrcTypeT = 33554434 + JPEG_ENC_SRC_GRAY JpegEncSrcTypeT = 67108865 +) diff --git a/esp32/key_mgr_types.go b/esp32/key_mgr_types.go new file mode 100644 index 00000000..5b4db43e --- /dev/null +++ b/esp32/key_mgr_types.go @@ -0,0 +1,92 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const KEY_MGR_ASSIST_INFO_LEN = 64 +const HUK_INFO_LEN = 384 +const KEY_INFO_LEN = 64 +const KEY_HUK_SECTOR_MAGIC = 0xDEA5CE5A + +type EspKeyMgrStateT c.Int + +const ( + ESP_KEY_MGR_STATE_IDLE EspKeyMgrStateT = 0 + ESP_KEY_MGR_STATE_LOAD EspKeyMgrStateT = 1 + ESP_KEY_MGR_STATE_GAIN EspKeyMgrStateT = 2 + ESP_KEY_MGR_STATE_BUSY EspKeyMgrStateT = 3 +) + +type EspKeyMgrXtsAesKeyLenT c.Int + +const ( + ESP_KEY_MGR_XTS_AES_LEN_256 EspKeyMgrXtsAesKeyLenT = 0 + ESP_KEY_MGR_XTS_AES_LEN_512 EspKeyMgrXtsAesKeyLenT = 1 +) + +type EspKeyMgrKeyTypeT c.Int + +const ( + ESP_KEY_MGR_ECDSA_KEY EspKeyMgrKeyTypeT = 0 + ESP_KEY_MGR_XTS_AES_128_KEY EspKeyMgrKeyTypeT = 1 + ESP_KEY_MGR_XTS_AES_256_KEY EspKeyMgrKeyTypeT = 2 +) + +type EspKeyMgrKeyUsageT c.Int + +const ( + ESP_KEY_MGR_USE_OWN_KEY EspKeyMgrKeyUsageT = 0 + ESP_KEY_MGR_USE_EFUSE_KEY EspKeyMgrKeyUsageT = 1 + ESP_KEY_MGR_USAGE_INVALID EspKeyMgrKeyUsageT = 2 +) + +type EspKeyMgrKeyPurposeT c.Int + +const ( + ESP_KEY_MGR_KEY_PURPOSE_ECDSA EspKeyMgrKeyPurposeT = 1 + ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1 EspKeyMgrKeyPurposeT = 2 + ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 EspKeyMgrKeyPurposeT = 3 + ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_128 EspKeyMgrKeyPurposeT = 4 +) + +type EspKeyMgrKeyGeneratorModeT c.Int + +const ( + ESP_KEY_MGR_KEYGEN_MODE_RANDOM EspKeyMgrKeyGeneratorModeT = 0 + ESP_KEY_MGR_KEYGEN_MODE_AES EspKeyMgrKeyGeneratorModeT = 1 + ESP_KEY_MGR_KEYGEN_MODE_ECDH0 EspKeyMgrKeyGeneratorModeT = 2 + ESP_KEY_MGR_KEYGEN_MODE_ECDH1 EspKeyMgrKeyGeneratorModeT = 3 + ESP_KEY_MGR_KEYGEN_MODE_RECOVER EspKeyMgrKeyGeneratorModeT = 4 + ESP_KEY_MGR_KEYGEN_MODE_EXPORT EspKeyMgrKeyGeneratorModeT = 5 +) + +type EspKeyMgrInterruptTypeT c.Int + +const ( + ESP_KEY_MGR_INT_PREP_DONE EspKeyMgrInterruptTypeT = 1 + ESP_KEY_MGR_INT_PROC_DONE EspKeyMgrInterruptTypeT = 2 + ESP_KEY_MGR_INT_POST_DONE EspKeyMgrInterruptTypeT = 3 +) + +// store huk info, occupy 96 words +type EspKeyMgrHukInfoT struct { + Info [384]c.Uint8T + Crc c.Uint32T +} + +// store key info, occupy 512 bits +type EspKeyMgrKeyInfoT struct { + Info [64]c.Uint8T + Crc c.Uint32T +} + +type EspKeyMgrKeyRecoveryInfoT struct { + Magic c.Uint32T + Version c.Uint32T + KeyType c.Uint8T + Reserved [15]c.Uint8T + HukInfo EspKeyMgrHukInfoT + KeyInfo [2]EspKeyMgrKeyInfoT +} diff --git a/esp32/lcd_cam_reg.go b/esp32/lcd_cam_reg.go new file mode 100644 index 00000000..aadbdc99 --- /dev/null +++ b/esp32/lcd_cam_reg.go @@ -0,0 +1,131 @@ +package freertos + +import _ "unsafe" + +const LCD_CAM_LCD_CLKCNT_N_S = 0 +const LCD_CAM_LCD_CLK_EQU_SYSCLK_S = 6 +const LCD_CAM_LCD_CK_IDLE_EDGE_S = 7 +const LCD_CAM_LCD_CK_OUT_EDGE_S = 8 +const LCD_CAM_LCD_CLKM_DIV_NUM_S = 9 +const LCD_CAM_LCD_CLKM_DIV_B_S = 17 +const LCD_CAM_LCD_CLKM_DIV_A_S = 23 +const LCD_CAM_LCD_CLK_SEL_S = 29 +const LCD_CAM_CLK_EN_S = 31 +const LCD_CAM_CAM_STOP_EN_S = 0 +const LCD_CAM_CAM_VSYNC_FILTER_THRES_S = 1 +const LCD_CAM_CAM_UPDATE_S = 4 +const LCD_CAM_CAM_BYTE_ORDER_S = 5 +const LCD_CAM_CAM_BIT_ORDER_S = 6 +const LCD_CAM_CAM_LINE_INT_EN_S = 7 +const LCD_CAM_CAM_VS_EOF_EN_S = 8 +const LCD_CAM_CAM_CLKM_DIV_NUM_S = 9 +const LCD_CAM_CAM_CLKM_DIV_B_S = 17 +const LCD_CAM_CAM_CLKM_DIV_A_S = 23 +const LCD_CAM_CAM_CLK_SEL_S = 29 +const LCD_CAM_CAM_REC_DATA_BYTELEN_S = 0 +const LCD_CAM_CAM_LINE_INT_NUM_S = 16 +const LCD_CAM_CAM_CLK_INV_S = 22 +const LCD_CAM_CAM_VSYNC_FILTER_EN_S = 23 +const LCD_CAM_CAM_2BYTE_EN_S = 24 +const LCD_CAM_CAM_DE_INV_S = 25 +const LCD_CAM_CAM_HSYNC_INV_S = 26 +const LCD_CAM_CAM_VSYNC_INV_S = 27 +const LCD_CAM_CAM_VH_DE_MODE_EN_S = 28 +const LCD_CAM_CAM_START_S = 29 +const LCD_CAM_CAM_RESET_S = 30 +const LCD_CAM_CAM_AFIFO_RESET_S = 31 +const LCD_CAM_CAM_CONV_8BITS_DATA_INV_S = 21 +const LCD_CAM_CAM_CONV_YUV2YUV_MODE_S = 22 +const LCD_CAM_CAM_CONV_YUV_MODE_S = 24 +const LCD_CAM_CAM_CONV_PROTOCOL_MODE_S = 26 +const LCD_CAM_CAM_CONV_DATA_OUT_MODE_S = 27 +const LCD_CAM_CAM_CONV_DATA_IN_MODE_S = 28 +const LCD_CAM_CAM_CONV_MODE_8BITS_ON_S = 29 +const LCD_CAM_CAM_CONV_TRANS_MODE_S = 30 +const LCD_CAM_CAM_CONV_BYPASS_S = 31 +const LCD_CAM_LCD_CONV_8BITS_DATA_INV_S = 20 +const LCD_CAM_LCD_CONV_TXTORX_S = 21 +const LCD_CAM_LCD_CONV_YUV2YUV_MODE_S = 22 +const LCD_CAM_LCD_CONV_YUV_MODE_S = 24 +const LCD_CAM_LCD_CONV_PROTOCOL_MODE_S = 26 +const LCD_CAM_LCD_CONV_DATA_OUT_MODE_S = 27 +const LCD_CAM_LCD_CONV_DATA_IN_MODE_S = 28 +const LCD_CAM_LCD_CONV_MODE_8BITS_ON_S = 29 +const LCD_CAM_LCD_CONV_TRANS_MODE_S = 30 +const LCD_CAM_LCD_CONV_BYPASS_S = 31 +const LCD_CAM_LCD_DOUT_CYCLELEN_S = 0 +const LCD_CAM_LCD_ALWAYS_OUT_EN_S = 13 +const LCD_CAM_LCD_8BITS_ORDER_S = 19 +const LCD_CAM_LCD_UPDATE_S = 20 +const LCD_CAM_LCD_BIT_ORDER_S = 21 +const LCD_CAM_LCD_BYTE_ORDER_S = 22 +const LCD_CAM_LCD_2BYTE_EN_S = 23 +const LCD_CAM_LCD_DOUT_S = 24 +const LCD_CAM_LCD_DUMMY_S = 25 +const LCD_CAM_LCD_CMD_S = 26 +const LCD_CAM_LCD_START_S = 27 +const LCD_CAM_LCD_RESET_S = 28 +const LCD_CAM_LCD_DUMMY_CYCLELEN_S = 29 +const LCD_CAM_LCD_CMD_2_CYCLE_EN_S = 31 +const LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S = 1 +const LCD_CAM_LCD_VFK_CYCLELEN_S = 6 +const LCD_CAM_LCD_VBK_CYCLELEN_S = 12 +const LCD_CAM_LCD_NEXT_FRAME_EN_S = 25 +const LCD_CAM_LCD_BK_EN_S = 26 +const LCD_CAM_LCD_AFIFO_RESET_S = 27 +const LCD_CAM_LCD_CD_DATA_SET_S = 28 +const LCD_CAM_LCD_CD_DUMMY_SET_S = 29 +const LCD_CAM_LCD_CD_CMD_SET_S = 30 +const LCD_CAM_LCD_CD_IDLE_EDGE_S = 31 +const LCD_CAM_LCD_HB_FRONT_S = 0 +const LCD_CAM_LCD_VA_HEIGHT_S = 11 +const LCD_CAM_LCD_VT_HEIGHT_S = 21 +const LCD_CAM_LCD_RGB_MODE_EN_S = 31 +const LCD_CAM_LCD_VB_FRONT_S = 0 +const LCD_CAM_LCD_HA_WIDTH_S = 8 +const LCD_CAM_LCD_HT_WIDTH_S = 20 +const LCD_CAM_LCD_VSYNC_WIDTH_S = 0 +const LCD_CAM_LCD_VSYNC_IDLE_POL_S = 7 +const LCD_CAM_LCD_DE_IDLE_POL_S = 8 +const LCD_CAM_LCD_HS_BLANK_EN_S = 9 +const LCD_CAM_LCD_HSYNC_WIDTH_S = 16 +const LCD_CAM_LCD_HSYNC_IDLE_POL_S = 23 +const LCD_CAM_LCD_HSYNC_POSITION_S = 24 +const LCD_CAM_LCD_CMD_VALUE_S = 0 +const LCD_CAM_LCD_CD_MODE_S = 0 +const LCD_CAM_LCD_DE_MODE_S = 2 +const LCD_CAM_LCD_HSYNC_MODE_S = 4 +const LCD_CAM_LCD_VSYNC_MODE_S = 6 +const LCD_CAM_DOUT0_MODE_S = 0 +const LCD_CAM_DOUT1_MODE_S = 2 +const LCD_CAM_DOUT2_MODE_S = 4 +const LCD_CAM_DOUT3_MODE_S = 6 +const LCD_CAM_DOUT4_MODE_S = 8 +const LCD_CAM_DOUT5_MODE_S = 10 +const LCD_CAM_DOUT6_MODE_S = 12 +const LCD_CAM_DOUT7_MODE_S = 14 +const LCD_CAM_DOUT8_MODE_S = 16 +const LCD_CAM_DOUT9_MODE_S = 18 +const LCD_CAM_DOUT10_MODE_S = 20 +const LCD_CAM_DOUT11_MODE_S = 22 +const LCD_CAM_DOUT12_MODE_S = 24 +const LCD_CAM_DOUT13_MODE_S = 26 +const LCD_CAM_DOUT14_MODE_S = 28 +const LCD_CAM_DOUT15_MODE_S = 30 +const LCD_CAM_LCD_VSYNC_INT_ENA_S = 0 +const LCD_CAM_LCD_TRANS_DONE_INT_ENA_S = 1 +const LCD_CAM_CAM_VSYNC_INT_ENA_S = 2 +const LCD_CAM_CAM_HS_INT_ENA_S = 3 +const LCD_CAM_LCD_VSYNC_INT_RAW_S = 0 +const LCD_CAM_LCD_TRANS_DONE_INT_RAW_S = 1 +const LCD_CAM_CAM_VSYNC_INT_RAW_S = 2 +const LCD_CAM_CAM_HS_INT_RAW_S = 3 +const LCD_CAM_LCD_VSYNC_INT_ST_S = 0 +const LCD_CAM_LCD_TRANS_DONE_INT_ST_S = 1 +const LCD_CAM_CAM_VSYNC_INT_ST_S = 2 +const LCD_CAM_CAM_HS_INT_ST_S = 3 +const LCD_CAM_LCD_VSYNC_INT_CLR_S = 0 +const LCD_CAM_LCD_TRANS_DONE_INT_CLR_S = 1 +const LCD_CAM_CAM_VSYNC_INT_CLR_S = 2 +const LCD_CAM_CAM_HS_INT_CLR_S = 3 +const LCD_CAM_LC_DATE_S = 0 diff --git a/esp32/lcd_cam_struct.go b/esp32/lcd_cam_struct.go new file mode 100644 index 00000000..2d6d8f2c --- /dev/null +++ b/esp32/lcd_cam_struct.go @@ -0,0 +1,179 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** Group: LCD configuration registers */ +/** Type of lcd_clock register + * LCD clock configuration register + */ + +type LcdCamLcdClockRegT struct { + Val c.Uint32T +} + +/** Type of lcd_rgb_yuv register + * LCD data format conversion register + */ + +type LcdCamLcdRgbYuvRegT struct { + Val c.Uint32T +} + +/** Type of lcd_user register + * LCD user configuration register + */ + +type LcdCamLcdUserRegT struct { + Val c.Uint32T +} + +/** Type of lcd_misc register + * LCD MISC configuration register + */ + +type LcdCamLcdMiscRegT struct { + Val c.Uint32T +} + +/** Type of lcd_ctrl register + * LCD signal configuration register + */ + +type LcdCamLcdCtrlRegT struct { + Val c.Uint32T +} + +/** Type of lcd_ctrl1 register + * LCD signal configuration register 1 + */ + +type LcdCamLcdCtrl1RegT struct { + Val c.Uint32T +} + +/** Type of lcd_ctrl2 register + * LCD signal configuration register 2 + */ + +type LcdCamLcdCtrl2RegT struct { + Val c.Uint32T +} + +/** Type of lcd_cmd_val register + * LCD command value configuration register + */ + +type LcdCamLcdCmdValRegT struct { + Val c.Uint32T +} + +/** Type of lcd_dly_mode register + * LCD signal delay configuration register + */ + +type LcdCamLcdDlyModeRegT struct { + Val c.Uint32T +} + +/** Type of lcd_data_dout_mode register + * LCD data delay configuration register + */ + +type LcdCamLcdDataDoutModeRegT struct { + Val c.Uint32T +} + +/** Group: Camera configuration registers */ +/** Type of cam_ctrl register + * Camera clock configuration register + */ + +type LcdCamCamCtrlRegT struct { + Val c.Uint32T +} + +/** Type of cam_ctrl1 register + * Camera control register + */ + +type LcdCamCamCtrl1RegT struct { + Val c.Uint32T +} + +/** Type of cam_rgb_yuv register + * Camera data format conversion register + */ + +type LcdCamCamRgbYuvRegT struct { + Val c.Uint32T +} + +/** Group: Interrupt registers */ +/** Type of lc_dma_int_ena register + * LCD_CAM GDMA interrupt enable register + */ + +type LcdCamLcDmaIntEnaRegT struct { + Val c.Uint32T +} + +/** Type of lc_dma_int_raw register + * LCD_CAM GDMA raw interrupt status register + */ + +type LcdCamLcDmaIntRawRegT struct { + Val c.Uint32T +} + +/** Type of lc_dma_int_st register + * LCD_CAM GDMA masked interrupt status register + */ + +type LcdCamLcDmaIntStRegT struct { + Val c.Uint32T +} + +/** Type of lc_dma_int_clr register + * LCD_CAM GDMA interrupt clear register + */ + +type LcdCamLcDmaIntClrRegT struct { + Val c.Uint32T +} + +/** Group: Version register */ +/** Type of lc_reg_date register + * Version control register + */ + +type LcdCamLcRegDateRegT struct { + Val c.Uint32T +} + +type LcdCamDevT struct { + LcdClock LcdCamLcdClockRegT + CamCtrl LcdCamCamCtrlRegT + CamCtrl1 LcdCamCamCtrl1RegT + CamRgbYuv LcdCamCamRgbYuvRegT + LcdRgbYuv LcdCamLcdRgbYuvRegT + LcdUser LcdCamLcdUserRegT + LcdMisc LcdCamLcdMiscRegT + LcdCtrl LcdCamLcdCtrlRegT + LcdCtrl1 LcdCamLcdCtrl1RegT + LcdCtrl2 LcdCamLcdCtrl2RegT + LcdCmdVal LcdCamLcdCmdValRegT + Reserved02c c.Uint32T + LcdDlyMode LcdCamLcdDlyModeRegT + Reserved034 c.Uint32T + LcdDataDoutMode LcdCamLcdDataDoutModeRegT + Reserved03c [10]c.Uint32T + LcDmaIntEna LcdCamLcDmaIntEnaRegT + LcDmaIntRaw LcdCamLcDmaIntRawRegT + LcDmaIntSt LcdCamLcDmaIntStRegT + LcDmaIntClr LcdCamLcDmaIntClrRegT + Reserved074 [34]c.Uint32T + LcRegDate LcdCamLcRegDateRegT +} diff --git a/esp32/lcd_hal.go b/esp32/lcd_hal.go new file mode 100644 index 00000000..5fdd5090 --- /dev/null +++ b/esp32/lcd_hal.go @@ -0,0 +1,41 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type LcdSocHandleT *LcdCamDevT + +/** + * @brief LCD HAL layer context + */ + +type LcdHalContextT struct { + Dev LcdSocHandleT +} + +/** + * @brief LCD HAL layer initialization + * + * @param hal LCD HAL layer context + * @param id LCD peripheral ID + */ +// llgo:link (*LcdHalContextT).LcdHalInit C.lcd_hal_init +func (recv_ *LcdHalContextT) LcdHalInit(id c.Int) { +} + +/** + * @brief LCD PCLK clock calculation + * @note Currently this function is only used by RGB LCD driver, I80 driver still uses a fixed clock division + * + * @param hal LCD HAL layer context + * @param src_freq_hz LCD source clock frequency in Hz + * @param expect_pclk_freq_hz Expected LCD PCLK frequency in Hz + * @param lcd_clk_div Returned LCD clock divider parameter + * @return Actual LCD PCLK frequency in Hz + */ +// llgo:link (*LcdHalContextT).LcdHalCalPclkFreq C.lcd_hal_cal_pclk_freq +func (recv_ *LcdHalContextT) LcdHalCalPclkFreq(src_freq_hz c.Uint32T, expect_pclk_freq_hz c.Uint32T, lcd_clk_div *HalUtilsClkDivT) c.Uint32T { + return 0 +} diff --git a/esp32/lcd_ll.go b/esp32/lcd_ll.go new file mode 100644 index 00000000..f410b9bc --- /dev/null +++ b/esp32/lcd_ll.go @@ -0,0 +1,15 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const LCD_LL_CLK_FRAC_DIV_N_MAX = 256 +const LCD_LL_CLK_FRAC_DIV_AB_MAX = 64 +const LCD_LL_PCLK_DIV_MAX = 64 +const LCD_LL_FIFO_DEPTH = 16 + +type LcdLlSwizzleModeT c.Int + +const LCD_LL_SWIZZLE_AB2BA LcdLlSwizzleModeT = 0 diff --git a/esp32/lcd_periph.go b/esp32/lcd_periph.go new file mode 100644 index 00000000..1c4fcfea --- /dev/null +++ b/esp32/lcd_periph.go @@ -0,0 +1,29 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type LcdI80SignalConnT struct { + Buses [1]struct { + Module PeriphModuleT + IrqId c.Int + DataSigs [16]c.Int + CsSig c.Int + DcSig c.Int + WrSig c.Int + } +} + +type LcdRgbSignalConnT struct { + Panels [1]struct { + Module PeriphModuleT + IrqId c.Int + DataSigs [16]c.Int + HsyncSig c.Int + VsyncSig c.Int + PclkSig c.Int + DeSig c.Int + } +} diff --git a/esp32/lcd_types.go b/esp32/lcd_types.go new file mode 100644 index 00000000..34744526 --- /dev/null +++ b/esp32/lcd_types.go @@ -0,0 +1,69 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type LcdClockSourceT SocPeriphLcdClkSrcT +type LcdRgbDataEndianT c.Int + +const ( + LCD_RGB_DATA_ENDIAN_BIG LcdRgbDataEndianT = 0 + LCD_RGB_DATA_ENDIAN_LITTLE LcdRgbDataEndianT = 1 +) + +type LcdColorSpaceT c.Int + +const ( + LCD_COLOR_SPACE_RGB LcdColorSpaceT = 2 + LCD_COLOR_SPACE_YUV LcdColorSpaceT = 3 +) + +type LcdColorRgbPixelFormatT c.Int + +const ( + LCD_COLOR_PIXEL_FORMAT_RGB565 LcdColorRgbPixelFormatT = 2 + LCD_COLOR_PIXEL_FORMAT_RGB666 LcdColorRgbPixelFormatT = 1 + LCD_COLOR_PIXEL_FORMAT_RGB888 LcdColorRgbPixelFormatT = 0 +) + +type LcdColorFormatT c.Int + +const ( + LCD_COLOR_FMT_RGB565 LcdColorFormatT = 33554434 + LCD_COLOR_FMT_RGB666 LcdColorFormatT = 33554433 + LCD_COLOR_FMT_RGB888 LcdColorFormatT = 33554432 + LCD_COLOR_FMT_YUV422 LcdColorFormatT = 50331649 +) + +type LcdColorRangeT c.Int + +const ( + LCD_COLOR_RANGE_LIMIT LcdColorRangeT = 0 + LCD_COLOR_RANGE_FULL LcdColorRangeT = 1 +) + +type LcdYuvSampleT c.Int + +const ( + LCD_YUV_SAMPLE_422 LcdYuvSampleT = 1 + LCD_YUV_SAMPLE_420 LcdYuvSampleT = 2 + LCD_YUV_SAMPLE_411 LcdYuvSampleT = 3 +) + +type LcdYuvConvStdT c.Int + +const ( + LCD_YUV_CONV_STD_BT601 LcdYuvConvStdT = 0 + LCD_YUV_CONV_STD_BT709 LcdYuvConvStdT = 1 +) + +type LcdYuv422PackOrderT c.Int + +const ( + LCD_YUV422_PACK_ORDER_YUYV LcdYuv422PackOrderT = 0 + LCD_YUV422_PACK_ORDER_YVYU LcdYuv422PackOrderT = 1 + LCD_YUV422_PACK_ORDER_UYVY LcdYuv422PackOrderT = 2 + LCD_YUV422_PACK_ORDER_VYUY LcdYuv422PackOrderT = 3 +) diff --git a/esp32/ldo_types.go b/esp32/ldo_types.go new file mode 100644 index 00000000..6f7ac015 --- /dev/null +++ b/esp32/ldo_types.go @@ -0,0 +1,15 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type LdoUnitT c.Int + +const ( + LDO_UNIT_1 LdoUnitT = 1 + LDO_UNIT_2 LdoUnitT = 2 + LDO_UNIT_3 LdoUnitT = 3 + LDO_UNIT_4 LdoUnitT = 4 +) diff --git a/esp32/ledc_hal.go b/esp32/ledc_hal.go new file mode 100644 index 00000000..164151f2 --- /dev/null +++ b/esp32/ledc_hal.go @@ -0,0 +1,146 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Context that should be maintained by both the driver and the HAL + */ + +type LedcHalContextT struct { + Dev *LedcDevT + SpeedMode LedcModeT +} + +/** + * @brief Init the LEDC hal. This function should be called first before other hal layer function is called + * + * @param hal Context of the HAL layer + * @param speed_mode speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mod + * + * @return None + */ +// llgo:link (*LedcHalContextT).LedcHalInit C.ledc_hal_init +func (recv_ *LedcHalContextT) LedcHalInit(speed_mode LedcModeT) { +} + +/** + * @brief Update channel configure when select low speed mode + * + * @param hal Context of the HAL layer + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * + * @return None + */ +// llgo:link (*LedcHalContextT).LedcHalLsChannelUpdate C.ledc_hal_ls_channel_update +func (recv_ *LedcHalContextT) LedcHalLsChannelUpdate(channel_num LedcChannelT) { +} + +/** + * @brief Set the duty start + * + * @param hal Context of the HAL layer + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param duty_start The duty start + * + * @return None + */ +// llgo:link (*LedcHalContextT).LedcHalSetDutyStart C.ledc_hal_set_duty_start +func (recv_ *LedcHalContextT) LedcHalSetDutyStart(channel_num LedcChannelT, duty_start bool) { +} + +/** + * @brief Set LEDC the integer part of duty value + * + * @param hal Context of the HAL layer + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param duty_val LEDC duty value, the range of duty setting is [0, (2**duty_resolution)] + * + * @return None + */ +// llgo:link (*LedcHalContextT).LedcHalSetDutyIntPart C.ledc_hal_set_duty_int_part +func (recv_ *LedcHalContextT) LedcHalSetDutyIntPart(channel_num LedcChannelT, duty_val c.Uint32T) { +} + +/** + * @brief Set LEDC hpoint value + * + * @param hal Context of the HAL layer + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param hpoint_val LEDC hpoint value(max: 0xfffff) + * + * @return None + */ +// llgo:link (*LedcHalContextT).LedcHalSetHpoint C.ledc_hal_set_hpoint +func (recv_ *LedcHalContextT) LedcHalSetHpoint(channel_num LedcChannelT, hpoint_val c.Uint32T) { +} + +/** + * @brief Get LEDC duty value + * + * @param hal Context of the HAL layer + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param duty_val Pointer to accept the LEDC duty value + * + * @return None + */ +// llgo:link (*LedcHalContextT).LedcHalGetDuty C.ledc_hal_get_duty +func (recv_ *LedcHalContextT) LedcHalGetDuty(channel_num LedcChannelT, duty_val *c.Uint32T) { +} + +/** + * @brief Function to set fade parameters all-in-one + * + * @param hal Context of the HAL layer + * @param channel_num LEDC channel index, select from ledc_channel_t + * @param range Range index + * @param dir LEDC duty change direction, increase or decrease + * @param cycle The duty cycles + * @param scale The step scale + * @param step The number of increased or decreased times + * + * @return None + */ +// llgo:link (*LedcHalContextT).LedcHalSetFadeParam C.ledc_hal_set_fade_param +func (recv_ *LedcHalContextT) LedcHalSetFadeParam(channel_num LedcChannelT, range_ c.Uint32T, dir c.Uint32T, cycle c.Uint32T, scale c.Uint32T, step c.Uint32T) { +} + +/** + * @brief Get interrupt status of the specified channel + * + * @param hal Context of the HAL layer + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * @param intr_status Pointer to accept the interrupt status + * + * @return None + */ +// llgo:link (*LedcHalContextT).LedcHalGetFadeEndIntrStatus C.ledc_hal_get_fade_end_intr_status +func (recv_ *LedcHalContextT) LedcHalGetFadeEndIntrStatus(intr_status *c.Uint32T) { +} + +/** + * @brief Clear interrupt status of the specified channel + * + * @param hal Context of the HAL layer + * @param channel_num LEDC channel index (0-7), select from ledc_channel_t + * + * @return None + */ +// llgo:link (*LedcHalContextT).LedcHalClearFadeEndIntrStatus C.ledc_hal_clear_fade_end_intr_status +func (recv_ *LedcHalContextT) LedcHalClearFadeEndIntrStatus(channel_num LedcChannelT) { +} + +/** + * @brief Get clock config of LEDC timer + * + * @param hal Context of the HAL layer + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param clk_cfg Pointer to accept clock config + * + * @return None + */ +// llgo:link (*LedcHalContextT).LedcHalGetClkCfg C.ledc_hal_get_clk_cfg +func (recv_ *LedcHalContextT) LedcHalGetClkCfg(timer_sel LedcTimerT, clk_cfg *LedcClkCfgT) { +} diff --git a/esp32/ledc_ll.go b/esp32/ledc_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/ledc_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/ledc_periph.go b/esp32/ledc_periph.go new file mode 100644 index 00000000..bae2e800 --- /dev/null +++ b/esp32/ledc_periph.go @@ -0,0 +1,13 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* +Stores a bunch of per-ledc-peripheral data. +*/ +type LedcSignalConnT struct { + SigOut0Idx c.Uint8T +} diff --git a/esp32/ledc_reg.go b/esp32/ledc_reg.go new file mode 100644 index 00000000..4d9d53a9 --- /dev/null +++ b/esp32/ledc_reg.go @@ -0,0 +1,536 @@ +package freertos + +import _ "unsafe" + +const LEDC_OVF_CNT_RESET_ST_LSCH0_V = 0x1 +const LEDC_OVF_CNT_RESET_ST_LSCH0_S = 17 +const LEDC_OVF_CNT_RESET_LSCH0_V = 0x1 +const LEDC_OVF_CNT_RESET_LSCH0_S = 16 +const LEDC_OVF_CNT_EN_LSCH0_V = 0x1 +const LEDC_OVF_CNT_EN_LSCH0_S = 15 +const LEDC_OVF_NUM_LSCH0 = 0x000003FF +const LEDC_OVF_NUM_LSCH0_V = 0x3FF +const LEDC_OVF_NUM_LSCH0_S = 5 +const LEDC_PARA_UP_LSCH0_V = 0x1 +const LEDC_PARA_UP_LSCH0_S = 4 +const LEDC_IDLE_LV_LSCH0_V = 0x1 +const LEDC_IDLE_LV_LSCH0_S = 3 +const LEDC_SIG_OUT_EN_LSCH0_V = 0x1 +const LEDC_SIG_OUT_EN_LSCH0_S = 2 +const LEDC_TIMER_SEL_LSCH0 = 0x00000003 +const LEDC_TIMER_SEL_LSCH0_V = 0x3 +const LEDC_TIMER_SEL_LSCH0_S = 0 +const LEDC_HPOINT_LSCH0 = 0x00003FFF +const LEDC_HPOINT_LSCH0_V = 0x3FFF +const LEDC_HPOINT_LSCH0_S = 0 +const LEDC_DUTY_LSCH0 = 0x0007FFFF +const LEDC_DUTY_LSCH0_V = 0x7FFFF +const LEDC_DUTY_LSCH0_S = 0 +const LEDC_DUTY_START_LSCH0_V = 0x1 +const LEDC_DUTY_START_LSCH0_S = 31 +const LEDC_DUTY_INC_LSCH0_V = 0x1 +const LEDC_DUTY_INC_LSCH0_S = 30 +const LEDC_DUTY_NUM_LSCH0 = 0x000003FF +const LEDC_DUTY_NUM_LSCH0_V = 0x3FF +const LEDC_DUTY_NUM_LSCH0_S = 20 +const LEDC_DUTY_CYCLE_LSCH0 = 0x000003FF +const LEDC_DUTY_CYCLE_LSCH0_V = 0x3FF +const LEDC_DUTY_CYCLE_LSCH0_S = 10 +const LEDC_DUTY_SCALE_LSCH0 = 0x000003FF +const LEDC_DUTY_SCALE_LSCH0_V = 0x3FF +const LEDC_DUTY_SCALE_LSCH0_S = 0 +const LEDC_OVF_CNT_RESET_ST_LSCH1_V = 0x1 +const LEDC_OVF_CNT_RESET_ST_LSCH1_S = 17 +const LEDC_OVF_CNT_RESET_LSCH1_V = 0x1 +const LEDC_OVF_CNT_RESET_LSCH1_S = 16 +const LEDC_OVF_CNT_EN_LSCH1_V = 0x1 +const LEDC_OVF_CNT_EN_LSCH1_S = 15 +const LEDC_OVF_NUM_LSCH1 = 0x000003FF +const LEDC_OVF_NUM_LSCH1_V = 0x3FF +const LEDC_OVF_NUM_LSCH1_S = 5 +const LEDC_PARA_UP_LSCH1_V = 0x1 +const LEDC_PARA_UP_LSCH1_S = 4 +const LEDC_IDLE_LV_LSCH1_V = 0x1 +const LEDC_IDLE_LV_LSCH1_S = 3 +const LEDC_SIG_OUT_EN_LSCH1_V = 0x1 +const LEDC_SIG_OUT_EN_LSCH1_S = 2 +const LEDC_TIMER_SEL_LSCH1 = 0x00000003 +const LEDC_TIMER_SEL_LSCH1_V = 0x3 +const LEDC_TIMER_SEL_LSCH1_S = 0 +const LEDC_HPOINT_LSCH1 = 0x00003FFF +const LEDC_HPOINT_LSCH1_V = 0x3FFF +const LEDC_HPOINT_LSCH1_S = 0 +const LEDC_DUTY_LSCH1 = 0x0007FFFF +const LEDC_DUTY_LSCH1_V = 0x7FFFF +const LEDC_DUTY_LSCH1_S = 0 +const LEDC_DUTY_START_LSCH1_V = 0x1 +const LEDC_DUTY_START_LSCH1_S = 31 +const LEDC_DUTY_INC_LSCH1_V = 0x1 +const LEDC_DUTY_INC_LSCH1_S = 30 +const LEDC_DUTY_NUM_LSCH1 = 0x000003FF +const LEDC_DUTY_NUM_LSCH1_V = 0x3FF +const LEDC_DUTY_NUM_LSCH1_S = 20 +const LEDC_DUTY_CYCLE_LSCH1 = 0x000003FF +const LEDC_DUTY_CYCLE_LSCH1_V = 0x3FF +const LEDC_DUTY_CYCLE_LSCH1_S = 10 +const LEDC_DUTY_SCALE_LSCH1 = 0x000003FF +const LEDC_DUTY_SCALE_LSCH1_V = 0x3FF +const LEDC_DUTY_SCALE_LSCH1_S = 0 +const LEDC_OVF_CNT_RESET_ST_LSCH2_V = 0x1 +const LEDC_OVF_CNT_RESET_ST_LSCH2_S = 17 +const LEDC_OVF_CNT_RESET_LSCH2_V = 0x1 +const LEDC_OVF_CNT_RESET_LSCH2_S = 16 +const LEDC_OVF_CNT_EN_LSCH2_V = 0x1 +const LEDC_OVF_CNT_EN_LSCH2_S = 15 +const LEDC_OVF_NUM_LSCH2 = 0x000003FF +const LEDC_OVF_NUM_LSCH2_V = 0x3FF +const LEDC_OVF_NUM_LSCH2_S = 5 +const LEDC_PARA_UP_LSCH2_V = 0x1 +const LEDC_PARA_UP_LSCH2_S = 4 +const LEDC_IDLE_LV_LSCH2_V = 0x1 +const LEDC_IDLE_LV_LSCH2_S = 3 +const LEDC_SIG_OUT_EN_LSCH2_V = 0x1 +const LEDC_SIG_OUT_EN_LSCH2_S = 2 +const LEDC_TIMER_SEL_LSCH2 = 0x00000003 +const LEDC_TIMER_SEL_LSCH2_V = 0x3 +const LEDC_TIMER_SEL_LSCH2_S = 0 +const LEDC_HPOINT_LSCH2 = 0x00003FFF +const LEDC_HPOINT_LSCH2_V = 0x3FFF +const LEDC_HPOINT_LSCH2_S = 0 +const LEDC_DUTY_LSCH2 = 0x0007FFFF +const LEDC_DUTY_LSCH2_V = 0x7FFFF +const LEDC_DUTY_LSCH2_S = 0 +const LEDC_DUTY_START_LSCH2_V = 0x1 +const LEDC_DUTY_START_LSCH2_S = 31 +const LEDC_DUTY_INC_LSCH2_V = 0x1 +const LEDC_DUTY_INC_LSCH2_S = 30 +const LEDC_DUTY_NUM_LSCH2 = 0x000003FF +const LEDC_DUTY_NUM_LSCH2_V = 0x3FF +const LEDC_DUTY_NUM_LSCH2_S = 20 +const LEDC_DUTY_CYCLE_LSCH2 = 0x000003FF +const LEDC_DUTY_CYCLE_LSCH2_V = 0x3FF +const LEDC_DUTY_CYCLE_LSCH2_S = 10 +const LEDC_DUTY_SCALE_LSCH2 = 0x000003FF +const LEDC_DUTY_SCALE_LSCH2_V = 0x3FF +const LEDC_DUTY_SCALE_LSCH2_S = 0 +const LEDC_OVF_CNT_RESET_ST_LSCH3_V = 0x1 +const LEDC_OVF_CNT_RESET_ST_LSCH3_S = 17 +const LEDC_OVF_CNT_RESET_LSCH3_V = 0x1 +const LEDC_OVF_CNT_RESET_LSCH3_S = 16 +const LEDC_OVF_CNT_EN_LSCH3_V = 0x1 +const LEDC_OVF_CNT_EN_LSCH3_S = 15 +const LEDC_OVF_NUM_LSCH3 = 0x000003FF +const LEDC_OVF_NUM_LSCH3_V = 0x3FF +const LEDC_OVF_NUM_LSCH3_S = 5 +const LEDC_PARA_UP_LSCH3_V = 0x1 +const LEDC_PARA_UP_LSCH3_S = 4 +const LEDC_IDLE_LV_LSCH3_V = 0x1 +const LEDC_IDLE_LV_LSCH3_S = 3 +const LEDC_SIG_OUT_EN_LSCH3_V = 0x1 +const LEDC_SIG_OUT_EN_LSCH3_S = 2 +const LEDC_TIMER_SEL_LSCH3 = 0x00000003 +const LEDC_TIMER_SEL_LSCH3_V = 0x3 +const LEDC_TIMER_SEL_LSCH3_S = 0 +const LEDC_HPOINT_LSCH3 = 0x00003FFF +const LEDC_HPOINT_LSCH3_V = 0x3FFF +const LEDC_HPOINT_LSCH3_S = 0 +const LEDC_DUTY_LSCH3 = 0x0007FFFF +const LEDC_DUTY_LSCH3_V = 0x7FFFF +const LEDC_DUTY_LSCH3_S = 0 +const LEDC_DUTY_START_LSCH3_V = 0x1 +const LEDC_DUTY_START_LSCH3_S = 31 +const LEDC_DUTY_INC_LSCH3_V = 0x1 +const LEDC_DUTY_INC_LSCH3_S = 30 +const LEDC_DUTY_NUM_LSCH3 = 0x000003FF +const LEDC_DUTY_NUM_LSCH3_V = 0x3FF +const LEDC_DUTY_NUM_LSCH3_S = 20 +const LEDC_DUTY_CYCLE_LSCH3 = 0x000003FF +const LEDC_DUTY_CYCLE_LSCH3_V = 0x3FF +const LEDC_DUTY_CYCLE_LSCH3_S = 10 +const LEDC_DUTY_SCALE_LSCH3 = 0x000003FF +const LEDC_DUTY_SCALE_LSCH3_V = 0x3FF +const LEDC_DUTY_SCALE_LSCH3_S = 0 +const LEDC_OVF_CNT_RESET_ST_LSCH4_V = 0x1 +const LEDC_OVF_CNT_RESET_ST_LSCH4_S = 17 +const LEDC_OVF_CNT_RESET_LSCH4_V = 0x1 +const LEDC_OVF_CNT_RESET_LSCH4_S = 16 +const LEDC_OVF_CNT_EN_LSCH4_V = 0x1 +const LEDC_OVF_CNT_EN_LSCH4_S = 15 +const LEDC_OVF_NUM_LSCH4 = 0x000003FF +const LEDC_OVF_NUM_LSCH4_V = 0x3FF +const LEDC_OVF_NUM_LSCH4_S = 5 +const LEDC_PARA_UP_LSCH4_V = 0x1 +const LEDC_PARA_UP_LSCH4_S = 4 +const LEDC_IDLE_LV_LSCH4_V = 0x1 +const LEDC_IDLE_LV_LSCH4_S = 3 +const LEDC_SIG_OUT_EN_LSCH4_V = 0x1 +const LEDC_SIG_OUT_EN_LSCH4_S = 2 +const LEDC_TIMER_SEL_LSCH4 = 0x00000003 +const LEDC_TIMER_SEL_LSCH4_V = 0x3 +const LEDC_TIMER_SEL_LSCH4_S = 0 +const LEDC_HPOINT_LSCH4 = 0x00003FFF +const LEDC_HPOINT_LSCH4_V = 0x3FFF +const LEDC_HPOINT_LSCH4_S = 0 +const LEDC_DUTY_LSCH4 = 0x0007FFFF +const LEDC_DUTY_LSCH4_V = 0x7FFFF +const LEDC_DUTY_LSCH4_S = 0 +const LEDC_DUTY_START_LSCH4_V = 0x1 +const LEDC_DUTY_START_LSCH4_S = 31 +const LEDC_DUTY_INC_LSCH4_V = 0x1 +const LEDC_DUTY_INC_LSCH4_S = 30 +const LEDC_DUTY_NUM_LSCH4 = 0x000003FF +const LEDC_DUTY_NUM_LSCH4_V = 0x3FF +const LEDC_DUTY_NUM_LSCH4_S = 20 +const LEDC_DUTY_CYCLE_LSCH4 = 0x000003FF +const LEDC_DUTY_CYCLE_LSCH4_V = 0x3FF +const LEDC_DUTY_CYCLE_LSCH4_S = 10 +const LEDC_DUTY_SCALE_LSCH4 = 0x000003FF +const LEDC_DUTY_SCALE_LSCH4_V = 0x3FF +const LEDC_DUTY_SCALE_LSCH4_S = 0 +const LEDC_OVF_CNT_RESET_ST_LSCH5_V = 0x1 +const LEDC_OVF_CNT_RESET_ST_LSCH5_S = 17 +const LEDC_OVF_CNT_RESET_LSCH5_V = 0x1 +const LEDC_OVF_CNT_RESET_LSCH5_S = 16 +const LEDC_OVF_CNT_EN_LSCH5_V = 0x1 +const LEDC_OVF_CNT_EN_LSCH5_S = 15 +const LEDC_OVF_NUM_LSCH5 = 0x000003FF +const LEDC_OVF_NUM_LSCH5_V = 0x3FF +const LEDC_OVF_NUM_LSCH5_S = 5 +const LEDC_PARA_UP_LSCH5_V = 0x1 +const LEDC_PARA_UP_LSCH5_S = 4 +const LEDC_IDLE_LV_LSCH5_V = 0x1 +const LEDC_IDLE_LV_LSCH5_S = 3 +const LEDC_SIG_OUT_EN_LSCH5_V = 0x1 +const LEDC_SIG_OUT_EN_LSCH5_S = 2 +const LEDC_TIMER_SEL_LSCH5 = 0x00000003 +const LEDC_TIMER_SEL_LSCH5_V = 0x3 +const LEDC_TIMER_SEL_LSCH5_S = 0 +const LEDC_HPOINT_LSCH5 = 0x00003FFF +const LEDC_HPOINT_LSCH5_V = 0x3FFF +const LEDC_HPOINT_LSCH5_S = 0 +const LEDC_DUTY_LSCH5 = 0x0007FFFF +const LEDC_DUTY_LSCH5_V = 0x7FFFF +const LEDC_DUTY_LSCH5_S = 0 +const LEDC_DUTY_START_LSCH5_V = 0x1 +const LEDC_DUTY_START_LSCH5_S = 31 +const LEDC_DUTY_INC_LSCH5_V = 0x1 +const LEDC_DUTY_INC_LSCH5_S = 30 +const LEDC_DUTY_NUM_LSCH5 = 0x000003FF +const LEDC_DUTY_NUM_LSCH5_V = 0x3FF +const LEDC_DUTY_NUM_LSCH5_S = 20 +const LEDC_DUTY_CYCLE_LSCH5 = 0x000003FF +const LEDC_DUTY_CYCLE_LSCH5_V = 0x3FF +const LEDC_DUTY_CYCLE_LSCH5_S = 10 +const LEDC_DUTY_SCALE_LSCH5 = 0x000003FF +const LEDC_DUTY_SCALE_LSCH5_V = 0x3FF +const LEDC_DUTY_SCALE_LSCH5_S = 0 +const LEDC_OVF_CNT_RESET_ST_LSCH6_V = 0x1 +const LEDC_OVF_CNT_RESET_ST_LSCH6_S = 17 +const LEDC_OVF_CNT_RESET_LSCH6_V = 0x1 +const LEDC_OVF_CNT_RESET_LSCH6_S = 16 +const LEDC_OVF_CNT_EN_LSCH6_V = 0x1 +const LEDC_OVF_CNT_EN_LSCH6_S = 15 +const LEDC_OVF_NUM_LSCH6 = 0x000003FF +const LEDC_OVF_NUM_LSCH6_V = 0x3FF +const LEDC_OVF_NUM_LSCH6_S = 5 +const LEDC_PARA_UP_LSCH6_V = 0x1 +const LEDC_PARA_UP_LSCH6_S = 4 +const LEDC_IDLE_LV_LSCH6_V = 0x1 +const LEDC_IDLE_LV_LSCH6_S = 3 +const LEDC_SIG_OUT_EN_LSCH6_V = 0x1 +const LEDC_SIG_OUT_EN_LSCH6_S = 2 +const LEDC_TIMER_SEL_LSCH6 = 0x00000003 +const LEDC_TIMER_SEL_LSCH6_V = 0x3 +const LEDC_TIMER_SEL_LSCH6_S = 0 +const LEDC_HPOINT_LSCH6 = 0x00003FFF +const LEDC_HPOINT_LSCH6_V = 0x3FFF +const LEDC_HPOINT_LSCH6_S = 0 +const LEDC_DUTY_LSCH6 = 0x0007FFFF +const LEDC_DUTY_LSCH6_V = 0x7FFFF +const LEDC_DUTY_LSCH6_S = 0 +const LEDC_DUTY_START_LSCH6_V = 0x1 +const LEDC_DUTY_START_LSCH6_S = 31 +const LEDC_DUTY_INC_LSCH6_V = 0x1 +const LEDC_DUTY_INC_LSCH6_S = 30 +const LEDC_DUTY_NUM_LSCH6 = 0x000003FF +const LEDC_DUTY_NUM_LSCH6_V = 0x3FF +const LEDC_DUTY_NUM_LSCH6_S = 20 +const LEDC_DUTY_CYCLE_LSCH6 = 0x000003FF +const LEDC_DUTY_CYCLE_LSCH6_V = 0x3FF +const LEDC_DUTY_CYCLE_LSCH6_S = 10 +const LEDC_DUTY_SCALE_LSCH6 = 0x000003FF +const LEDC_DUTY_SCALE_LSCH6_V = 0x3FF +const LEDC_DUTY_SCALE_LSCH6_S = 0 +const LEDC_OVF_CNT_RESET_ST_LSCH7_V = 0x1 +const LEDC_OVF_CNT_RESET_ST_LSCH7_S = 17 +const LEDC_OVF_CNT_RESET_LSCH7_V = 0x1 +const LEDC_OVF_CNT_RESET_LSCH7_S = 16 +const LEDC_OVF_CNT_EN_LSCH7_V = 0x1 +const LEDC_OVF_CNT_EN_LSCH7_S = 15 +const LEDC_OVF_NUM_LSCH7 = 0x000003FF +const LEDC_OVF_NUM_LSCH7_V = 0x3FF +const LEDC_OVF_NUM_LSCH7_S = 5 +const LEDC_PARA_UP_LSCH7_V = 0x1 +const LEDC_PARA_UP_LSCH7_S = 4 +const LEDC_IDLE_LV_LSCH7_V = 0x1 +const LEDC_IDLE_LV_LSCH7_S = 3 +const LEDC_SIG_OUT_EN_LSCH7_V = 0x1 +const LEDC_SIG_OUT_EN_LSCH7_S = 2 +const LEDC_TIMER_SEL_LSCH7 = 0x00000003 +const LEDC_TIMER_SEL_LSCH7_V = 0x3 +const LEDC_TIMER_SEL_LSCH7_S = 0 +const LEDC_HPOINT_LSCH7 = 0x00003FFF +const LEDC_HPOINT_LSCH7_V = 0x3FFF +const LEDC_HPOINT_LSCH7_S = 0 +const LEDC_DUTY_LSCH7 = 0x0007FFFF +const LEDC_DUTY_LSCH7_V = 0x7FFFF +const LEDC_DUTY_LSCH7_S = 0 +const LEDC_DUTY_START_LSCH7_V = 0x1 +const LEDC_DUTY_START_LSCH7_S = 31 +const LEDC_DUTY_INC_LSCH7_V = 0x1 +const LEDC_DUTY_INC_LSCH7_S = 30 +const LEDC_DUTY_NUM_LSCH7 = 0x000003FF +const LEDC_DUTY_NUM_LSCH7_V = 0x3FF +const LEDC_DUTY_NUM_LSCH7_S = 20 +const LEDC_DUTY_CYCLE_LSCH7 = 0x000003FF +const LEDC_DUTY_CYCLE_LSCH7_V = 0x3FF +const LEDC_DUTY_CYCLE_LSCH7_S = 10 +const LEDC_DUTY_SCALE_LSCH7 = 0x000003FF +const LEDC_DUTY_SCALE_LSCH7_V = 0x3FF +const LEDC_DUTY_SCALE_LSCH7_S = 0 +const LEDC_LSTIMER0_PARA_UP_V = 0x1 +const LEDC_LSTIMER0_PARA_UP_S = 25 +const LEDC_TICK_SEL_LSTIMER0_V = 0x1 +const LEDC_TICK_SEL_LSTIMER0_S = 24 +const LEDC_LSTIMER0_RST_V = 0x1 +const LEDC_LSTIMER0_RST_S = 23 +const LEDC_LSTIMER0_PAUSE_V = 0x1 +const LEDC_LSTIMER0_PAUSE_S = 22 +const LEDC_CLK_DIV_LSTIMER0 = 0x0003FFFF +const LEDC_CLK_DIV_LSTIMER0_V = 0x3FFFF +const LEDC_CLK_DIV_LSTIMER0_S = 4 +const LEDC_LSTIMER0_DUTY_RES = 0x0000000F +const LEDC_LSTIMER0_DUTY_RES_V = 0xF +const LEDC_LSTIMER0_DUTY_RES_S = 0 +const LEDC_LSTIMER0_CNT = 0x00003FFF +const LEDC_LSTIMER0_CNT_V = 0x3FFF +const LEDC_LSTIMER0_CNT_S = 0 +const LEDC_LSTIMER1_PARA_UP_V = 0x1 +const LEDC_LSTIMER1_PARA_UP_S = 25 +const LEDC_TICK_SEL_LSTIMER1_V = 0x1 +const LEDC_TICK_SEL_LSTIMER1_S = 24 +const LEDC_LSTIMER1_RST_V = 0x1 +const LEDC_LSTIMER1_RST_S = 23 +const LEDC_LSTIMER1_PAUSE_V = 0x1 +const LEDC_LSTIMER1_PAUSE_S = 22 +const LEDC_CLK_DIV_LSTIMER1 = 0x0003FFFF +const LEDC_CLK_DIV_LSTIMER1_V = 0x3FFFF +const LEDC_CLK_DIV_LSTIMER1_S = 4 +const LEDC_LSTIMER1_DUTY_RES = 0x0000000F +const LEDC_LSTIMER1_DUTY_RES_V = 0xF +const LEDC_LSTIMER1_DUTY_RES_S = 0 +const LEDC_LSTIMER1_CNT = 0x00003FFF +const LEDC_LSTIMER1_CNT_V = 0x3FFF +const LEDC_LSTIMER1_CNT_S = 0 +const LEDC_LSTIMER2_PARA_UP_V = 0x1 +const LEDC_LSTIMER2_PARA_UP_S = 25 +const LEDC_TICK_SEL_LSTIMER2_V = 0x1 +const LEDC_TICK_SEL_LSTIMER2_S = 24 +const LEDC_LSTIMER2_RST_V = 0x1 +const LEDC_LSTIMER2_RST_S = 23 +const LEDC_LSTIMER2_PAUSE_V = 0x1 +const LEDC_LSTIMER2_PAUSE_S = 22 +const LEDC_CLK_DIV_LSTIMER2 = 0x0003FFFF +const LEDC_CLK_DIV_LSTIMER2_V = 0x3FFFF +const LEDC_CLK_DIV_LSTIMER2_S = 4 +const LEDC_LSTIMER2_DUTY_RES = 0x0000000F +const LEDC_LSTIMER2_DUTY_RES_V = 0xF +const LEDC_LSTIMER2_DUTY_RES_S = 0 +const LEDC_LSTIMER2_CNT = 0x00003FFF +const LEDC_LSTIMER2_CNT_V = 0x3FFF +const LEDC_LSTIMER2_CNT_S = 0 +const LEDC_LSTIMER3_PARA_UP_V = 0x1 +const LEDC_LSTIMER3_PARA_UP_S = 25 +const LEDC_TICK_SEL_LSTIMER3_V = 0x1 +const LEDC_TICK_SEL_LSTIMER3_S = 24 +const LEDC_LSTIMER3_RST_V = 0x1 +const LEDC_LSTIMER3_RST_S = 23 +const LEDC_LSTIMER3_PAUSE_V = 0x1 +const LEDC_LSTIMER3_PAUSE_S = 22 +const LEDC_CLK_DIV_LSTIMER3 = 0x0003FFFF +const LEDC_CLK_DIV_LSTIMER3_V = 0x3FFFF +const LEDC_CLK_DIV_LSTIMER3_S = 4 +const LEDC_LSTIMER3_DUTY_RES = 0x0000000F +const LEDC_LSTIMER3_DUTY_RES_V = 0xF +const LEDC_LSTIMER3_DUTY_RES_S = 0 +const LEDC_LSTIMER3_CNT = 0x00003FFF +const LEDC_LSTIMER3_CNT_V = 0x3FFF +const LEDC_LSTIMER3_CNT_S = 0 +const LEDC_OVF_CNT_LSCH7_INT_RAW_V = 0x1 +const LEDC_OVF_CNT_LSCH7_INT_RAW_S = 19 +const LEDC_OVF_CNT_LSCH6_INT_RAW_V = 0x1 +const LEDC_OVF_CNT_LSCH6_INT_RAW_S = 18 +const LEDC_OVF_CNT_LSCH5_INT_RAW_V = 0x1 +const LEDC_OVF_CNT_LSCH5_INT_RAW_S = 17 +const LEDC_OVF_CNT_LSCH4_INT_RAW_V = 0x1 +const LEDC_OVF_CNT_LSCH4_INT_RAW_S = 16 +const LEDC_OVF_CNT_LSCH3_INT_RAW_V = 0x1 +const LEDC_OVF_CNT_LSCH3_INT_RAW_S = 15 +const LEDC_OVF_CNT_LSCH2_INT_RAW_V = 0x1 +const LEDC_OVF_CNT_LSCH2_INT_RAW_S = 14 +const LEDC_OVF_CNT_LSCH1_INT_RAW_V = 0x1 +const LEDC_OVF_CNT_LSCH1_INT_RAW_S = 13 +const LEDC_OVF_CNT_LSCH0_INT_RAW_V = 0x1 +const LEDC_OVF_CNT_LSCH0_INT_RAW_S = 12 +const LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S = 11 +const LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S = 10 +const LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S = 9 +const LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S = 8 +const LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S = 7 +const LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S = 6 +const LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S = 5 +const LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S = 4 +const LEDC_LSTIMER3_OVF_INT_RAW_V = 0x1 +const LEDC_LSTIMER3_OVF_INT_RAW_S = 3 +const LEDC_LSTIMER2_OVF_INT_RAW_V = 0x1 +const LEDC_LSTIMER2_OVF_INT_RAW_S = 2 +const LEDC_LSTIMER1_OVF_INT_RAW_V = 0x1 +const LEDC_LSTIMER1_OVF_INT_RAW_S = 1 +const LEDC_LSTIMER0_OVF_INT_RAW_V = 0x1 +const LEDC_LSTIMER0_OVF_INT_RAW_S = 0 +const LEDC_OVF_CNT_LSCH7_INT_ST_V = 0x1 +const LEDC_OVF_CNT_LSCH7_INT_ST_S = 19 +const LEDC_OVF_CNT_LSCH6_INT_ST_V = 0x1 +const LEDC_OVF_CNT_LSCH6_INT_ST_S = 18 +const LEDC_OVF_CNT_LSCH5_INT_ST_V = 0x1 +const LEDC_OVF_CNT_LSCH5_INT_ST_S = 17 +const LEDC_OVF_CNT_LSCH4_INT_ST_V = 0x1 +const LEDC_OVF_CNT_LSCH4_INT_ST_S = 16 +const LEDC_OVF_CNT_LSCH3_INT_ST_V = 0x1 +const LEDC_OVF_CNT_LSCH3_INT_ST_S = 15 +const LEDC_OVF_CNT_LSCH2_INT_ST_V = 0x1 +const LEDC_OVF_CNT_LSCH2_INT_ST_S = 14 +const LEDC_OVF_CNT_LSCH1_INT_ST_V = 0x1 +const LEDC_OVF_CNT_LSCH1_INT_ST_S = 13 +const LEDC_OVF_CNT_LSCH0_INT_ST_V = 0x1 +const LEDC_OVF_CNT_LSCH0_INT_ST_S = 12 +const LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S = 11 +const LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S = 10 +const LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S = 9 +const LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S = 8 +const LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S = 7 +const LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S = 6 +const LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S = 5 +const LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S = 4 +const LEDC_LSTIMER3_OVF_INT_ST_V = 0x1 +const LEDC_LSTIMER3_OVF_INT_ST_S = 3 +const LEDC_LSTIMER2_OVF_INT_ST_V = 0x1 +const LEDC_LSTIMER2_OVF_INT_ST_S = 2 +const LEDC_LSTIMER1_OVF_INT_ST_V = 0x1 +const LEDC_LSTIMER1_OVF_INT_ST_S = 1 +const LEDC_LSTIMER0_OVF_INT_ST_V = 0x1 +const LEDC_LSTIMER0_OVF_INT_ST_S = 0 +const LEDC_OVF_CNT_LSCH7_INT_ENA_V = 0x1 +const LEDC_OVF_CNT_LSCH7_INT_ENA_S = 19 +const LEDC_OVF_CNT_LSCH6_INT_ENA_V = 0x1 +const LEDC_OVF_CNT_LSCH6_INT_ENA_S = 18 +const LEDC_OVF_CNT_LSCH5_INT_ENA_V = 0x1 +const LEDC_OVF_CNT_LSCH5_INT_ENA_S = 17 +const LEDC_OVF_CNT_LSCH4_INT_ENA_V = 0x1 +const LEDC_OVF_CNT_LSCH4_INT_ENA_S = 16 +const LEDC_OVF_CNT_LSCH3_INT_ENA_V = 0x1 +const LEDC_OVF_CNT_LSCH3_INT_ENA_S = 15 +const LEDC_OVF_CNT_LSCH2_INT_ENA_V = 0x1 +const LEDC_OVF_CNT_LSCH2_INT_ENA_S = 14 +const LEDC_OVF_CNT_LSCH1_INT_ENA_V = 0x1 +const LEDC_OVF_CNT_LSCH1_INT_ENA_S = 13 +const LEDC_OVF_CNT_LSCH0_INT_ENA_V = 0x1 +const LEDC_OVF_CNT_LSCH0_INT_ENA_S = 12 +const LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S = 11 +const LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S = 10 +const LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S = 9 +const LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S = 8 +const LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S = 7 +const LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S = 6 +const LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S = 5 +const LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S = 4 +const LEDC_LSTIMER3_OVF_INT_ENA_V = 0x1 +const LEDC_LSTIMER3_OVF_INT_ENA_S = 3 +const LEDC_LSTIMER2_OVF_INT_ENA_V = 0x1 +const LEDC_LSTIMER2_OVF_INT_ENA_S = 2 +const LEDC_LSTIMER1_OVF_INT_ENA_V = 0x1 +const LEDC_LSTIMER1_OVF_INT_ENA_S = 1 +const LEDC_LSTIMER0_OVF_INT_ENA_V = 0x1 +const LEDC_LSTIMER0_OVF_INT_ENA_S = 0 +const LEDC_OVF_CNT_LSCH7_INT_CLR_V = 0x1 +const LEDC_OVF_CNT_LSCH7_INT_CLR_S = 19 +const LEDC_OVF_CNT_LSCH6_INT_CLR_V = 0x1 +const LEDC_OVF_CNT_LSCH6_INT_CLR_S = 18 +const LEDC_OVF_CNT_LSCH5_INT_CLR_V = 0x1 +const LEDC_OVF_CNT_LSCH5_INT_CLR_S = 17 +const LEDC_OVF_CNT_LSCH4_INT_CLR_V = 0x1 +const LEDC_OVF_CNT_LSCH4_INT_CLR_S = 16 +const LEDC_OVF_CNT_LSCH3_INT_CLR_V = 0x1 +const LEDC_OVF_CNT_LSCH3_INT_CLR_S = 15 +const LEDC_OVF_CNT_LSCH2_INT_CLR_V = 0x1 +const LEDC_OVF_CNT_LSCH2_INT_CLR_S = 14 +const LEDC_OVF_CNT_LSCH1_INT_CLR_V = 0x1 +const LEDC_OVF_CNT_LSCH1_INT_CLR_S = 13 +const LEDC_OVF_CNT_LSCH0_INT_CLR_V = 0x1 +const LEDC_OVF_CNT_LSCH0_INT_CLR_S = 12 +const LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S = 11 +const LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S = 10 +const LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S = 9 +const LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S = 8 +const LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S = 7 +const LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S = 6 +const LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S = 5 +const LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V = 0x1 +const LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S = 4 +const LEDC_LSTIMER3_OVF_INT_CLR_V = 0x1 +const LEDC_LSTIMER3_OVF_INT_CLR_S = 3 +const LEDC_LSTIMER2_OVF_INT_CLR_V = 0x1 +const LEDC_LSTIMER2_OVF_INT_CLR_S = 2 +const LEDC_LSTIMER1_OVF_INT_CLR_V = 0x1 +const LEDC_LSTIMER1_OVF_INT_CLR_S = 1 +const LEDC_LSTIMER0_OVF_INT_CLR_V = 0x1 +const LEDC_LSTIMER0_OVF_INT_CLR_S = 0 +const LEDC_CLK_EN_V = 0x1 +const LEDC_CLK_EN_S = 31 +const LEDC_APB_CLK_SEL = 0x00000003 +const LEDC_APB_CLK_SEL_V = 0x3 +const LEDC_APB_CLK_SEL_S = 0 +const LEDC_DATE = 0xFFFFFFFF +const LEDC_DATE_V = 0xFFFFFFFF +const LEDC_DATE_S = 0 diff --git a/esp32/ledc_struct.go b/esp32/ledc_struct.go new file mode 100644 index 00000000..d4c1078f --- /dev/null +++ b/esp32/ledc_struct.go @@ -0,0 +1,65 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type LedcDevS struct { + ChannelGroup [1]struct { + Channel [8]struct { + Conf0 struct { + Val c.Uint32T + } + Hpoint struct { + Val c.Uint32T + } + Duty struct { + Val c.Uint32T + } + Conf1 struct { + Val c.Uint32T + } + DutyRd struct { + Val c.Uint32T + } + } + } + TimerGroup [1]struct { + Timer [4]struct { + Conf struct { + Val c.Uint32T + } + Value struct { + Val c.Uint32T + } + } + } + IntRaw struct { + Val c.Uint32T + } + IntSt struct { + Val c.Uint32T + } + IntEna struct { + Val c.Uint32T + } + IntClr struct { + Val c.Uint32T + } + Conf struct { + Val c.Uint32T + } + ReservedD4 c.Uint32T + ReservedD8 c.Uint32T + ReservedDc c.Uint32T + ReservedE0 c.Uint32T + ReservedE4 c.Uint32T + ReservedE8 c.Uint32T + ReservedEc c.Uint32T + ReservedF0 c.Uint32T + ReservedF4 c.Uint32T + ReservedF8 c.Uint32T + Date c.Uint32T +} +type LedcDevT LedcDevS diff --git a/esp32/ledc_types.go b/esp32/ledc_types.go new file mode 100644 index 00000000..0f5ded4c --- /dev/null +++ b/esp32/ledc_types.go @@ -0,0 +1,98 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type LedcModeT c.Int + +const ( + LEDC_LOW_SPEED_MODE LedcModeT = 0 + LEDC_SPEED_MODE_MAX LedcModeT = 1 +) + +type LedcIntrTypeT c.Int + +const ( + LEDC_INTR_DISABLE LedcIntrTypeT = 0 + LEDC_INTR_FADE_END LedcIntrTypeT = 1 + LEDC_INTR_MAX LedcIntrTypeT = 2 +) + +type LedcDutyDirectionT c.Int + +const ( + LEDC_DUTY_DIR_DECREASE LedcDutyDirectionT = 0 + LEDC_DUTY_DIR_INCREASE LedcDutyDirectionT = 1 + LEDC_DUTY_DIR_MAX LedcDutyDirectionT = 2 +) + +type LedcSlowClkSelT c.Int + +const ( + LEDC_SLOW_CLK_RC_FAST LedcSlowClkSelT = 9 + LEDC_SLOW_CLK_APB LedcSlowClkSelT = 4 + LEDC_SLOW_CLK_XTAL LedcSlowClkSelT = 11 + LEDC_SLOW_CLK_RTC8M LedcSlowClkSelT = 9 +) + +type LedcClkCfgT SocPeriphLedcClkSrcLegacyT +type LedcClkSrcT c.Int + +const ( + LEDC_APB_CLK LedcClkSrcT = 4 + LEDC_SCLK LedcClkSrcT = 4 +) + +type LedcTimerT c.Int + +const ( + LEDC_TIMER_0 LedcTimerT = 0 + LEDC_TIMER_1 LedcTimerT = 1 + LEDC_TIMER_2 LedcTimerT = 2 + LEDC_TIMER_3 LedcTimerT = 3 + LEDC_TIMER_MAX LedcTimerT = 4 +) + +type LedcChannelT c.Int + +const ( + LEDC_CHANNEL_0 LedcChannelT = 0 + LEDC_CHANNEL_1 LedcChannelT = 1 + LEDC_CHANNEL_2 LedcChannelT = 2 + LEDC_CHANNEL_3 LedcChannelT = 3 + LEDC_CHANNEL_4 LedcChannelT = 4 + LEDC_CHANNEL_5 LedcChannelT = 5 + LEDC_CHANNEL_6 LedcChannelT = 6 + LEDC_CHANNEL_7 LedcChannelT = 7 + LEDC_CHANNEL_MAX LedcChannelT = 8 +) + +type LedcTimerBitT c.Int + +const ( + LEDC_TIMER_1_BIT LedcTimerBitT = 1 + LEDC_TIMER_2_BIT LedcTimerBitT = 2 + LEDC_TIMER_3_BIT LedcTimerBitT = 3 + LEDC_TIMER_4_BIT LedcTimerBitT = 4 + LEDC_TIMER_5_BIT LedcTimerBitT = 5 + LEDC_TIMER_6_BIT LedcTimerBitT = 6 + LEDC_TIMER_7_BIT LedcTimerBitT = 7 + LEDC_TIMER_8_BIT LedcTimerBitT = 8 + LEDC_TIMER_9_BIT LedcTimerBitT = 9 + LEDC_TIMER_10_BIT LedcTimerBitT = 10 + LEDC_TIMER_11_BIT LedcTimerBitT = 11 + LEDC_TIMER_12_BIT LedcTimerBitT = 12 + LEDC_TIMER_13_BIT LedcTimerBitT = 13 + LEDC_TIMER_14_BIT LedcTimerBitT = 14 + LEDC_TIMER_BIT_MAX LedcTimerBitT = 15 +) + +type LedcFadeModeT c.Int + +const ( + LEDC_FADE_NO_WAIT LedcFadeModeT = 0 + LEDC_FADE_WAIT_DONE LedcFadeModeT = 1 + LEDC_FADE_MAX LedcFadeModeT = 2 +) diff --git a/esp32/list.go b/esp32/list.go new file mode 100644 index 00000000..572dbfd7 --- /dev/null +++ b/esp32/list.go @@ -0,0 +1,116 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* + * Definition of the only type of object that a list can contain. + */ + +type XLIST struct { + UxNumberOfItems UBaseTypeT + PxIndex *ListItemT + XListEnd MiniListItemT +} + +type XLISTITEM struct { + XItemValue TickTypeT + PxNext *XLISTITEM + PxPrevious *XLISTITEM + PvOwner c.Pointer + PxContainer *XLIST +} +type ListItemT XLISTITEM + +type XMINILISTITEM struct { + XItemValue TickTypeT + PxNext *XLISTITEM + PxPrevious *XLISTITEM +} +type MiniListItemT XMINILISTITEM +type ListT XLIST + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +// llgo:link (*ListT).VListInitialise C.vListInitialise +func (recv_ *ListT) VListInitialise() { +} + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +// llgo:link (*ListItemT).VListInitialiseItem C.vListInitialiseItem +func (recv_ *ListItemT) VListInitialiseItem() { +} + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (ascending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +// llgo:link (*ListT).VListInsert C.vListInsert +func (recv_ *ListT) VListInsert(pxNewListItem *ListItemT) { +} + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +// llgo:link (*ListT).VListInsertEnd C.vListInsertEnd +func (recv_ *ListT) VListInsertEnd(pxNewListItem *ListItemT) { +} + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +// llgo:link (*ListItemT).UxListRemove C.uxListRemove +func (recv_ *ListItemT) UxListRemove() UBaseTypeT { + return 0 +} diff --git a/esp32/llcppg.cfg b/esp32/llcppg.cfg new file mode 100644 index 00000000..387c8be7 --- /dev/null +++ b/esp32/llcppg.cfg @@ -0,0 +1,674 @@ +{ + "name": "esp32", + "cflags": "-I{{esp-idf-path}/esp-idf/examples/get-started/blink/build/bootloader/config -I{{esp-idf-path}/esp-idf/components/freertos/config/include/freertos -I{{esp-idf-path}/esp-idf/components/freertos/config/xtensa/include -I{{esp-idf-path}/esp-idf/components/xtensa/include -I{{esp-idf-path}/esp-idf/components/xtensa/include/xtensa -I{{esp-idf-path}/esp-idf/components/xtensa/esp32s3/include -I{{esp-idf-path}/esp-idf/components/newlib/platform_include -I{{esp-idf-path}/esp-idf/components/freertos/FreeRTOS-Kernel/include/freertos -I{{esp-idf-path}/esp-idf/examples/get-started/blink/config -I{{esp-idf-path}/esp-idf/components/freertos/config/include -I{{esp-idf-path}/esp-idf/components/freertos/config/include/freertos -I{{esp-idf-path}/esp-idf/components/freertos/config/xtensa/include -I{{esp-idf-path}/esp-idf/components/freertos/FreeRTOS-Kernel/include -I{{esp-idf-path}/esp-idf/components/freertos/FreeRTOS-Kernel/portable/xtensa/include -I{{esp-idf-path}/esp-idf/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos -I{{esp-idf-path}/esp-idf/components/freertos/esp_additions/include -I{{esp-idf-path}/esp-idf/components/freertos -I{{esp-idf-path}/esp-idf/components/freertos/FreeRTOS-Kernel/include/freertos -I{{esp-idf-path}/esp-idf/components/freertos/esp_additions -I{{esp-idf-path}/esp-idf/components/newlib/platform_include -I{{esp-idf-path}/esp-idf/components/esp_hw_support/include -I{{esp-idf-path}/esp-idf/components/esp_hw_support/include/soc -I{{esp-idf-path}/esp-idf/components/esp_hw_support/include/soc/esp32s3 -I{{esp-idf-path}/esp-idf/components/esp_hw_support/dma/include -I{{esp-idf-path}/esp-idf/components/esp_hw_support/ldo/include -I{{esp-idf-path}/esp-idf/components/esp_hw_support/debug_probe/include -I{{esp-idf-path}/esp-idf/components/esp_hw_support/port/esp32s3/. -I{{esp-idf-path}/esp-idf/components/esp_hw_support/port/esp32s3/include -I{{esp-idf-path}/esp-idf/components/heap/include -I{{esp-idf-path}/esp-idf/components/heap/tlsf -I{{esp-idf-path}/esp-idf/components/log/include -I{{esp-idf-path}/esp-idf/components/soc/include -I{{esp-idf-path}/esp-idf/components/soc/esp32s3 -I{{esp-idf-path}/esp-idf/components/soc/esp32s3/include -I{{esp-idf-path}/esp-idf/components/soc/esp32s3/register -I{{esp-idf-path}/esp-idf/components/hal/platform_port/include -I{{esp-idf-path}/esp-idf/components/hal/esp32s3/include -I{{esp-idf-path}/esp-idf/components/hal/include -I{{esp-idf-path}/esp-idf/components/esp_rom/include -I{{esp-idf-path}/esp-idf/components/esp_rom/esp32s3/include -I{{esp-idf-path}/esp-idf/components/esp_rom/esp32s3/include/esp32s3 -I{{esp-idf-path}/esp-idf/components/esp_rom/esp32s3 -I{{esp-idf-path}/esp-idf/components/esp_common/include -I{{esp-idf-path}/esp-idf/components/esp_system/include -I{{esp-idf-path}/esp-idf/components/esp_system/port/soc -I{{esp-idf-path}/esp-idf/components/esp_system/port/include/private -I{{esp-idf-path}/esp-idf/components/xtensa/esp32s3/include -I{{esp-idf-path}/esp-idf/components/xtensa/include -I{{esp-idf-path}/esp-idf/components/xtensa/deprecated_include -I{{esp-idf-path}/esp-idf/components/lwip/include -I{{esp-idf-path}/esp-idf/components/lwip/include/apps -I{{esp-idf-path}/esp-idf/components/lwip/include/apps/sntp -I{{esp-idf-path}/esp-idf/components/lwip/lwip/src/include -I{{esp-idf-path}/esp-idf/components/lwip/port/include -I{{esp-idf-path}/esp-idf/components/lwip/port/freertos/include -I{{esp-idf-path}/esp-idf/components/lwip/port/esp32xx/include -I{{esp-idf-path}/esp-idf/components/lwip/port/esp32xx/include/arch -I{{esp-idf-path}/esp-idf/components/lwip/port/esp32xx/include/sys", + "include": [ + "xt_utils.h", + "xtensa_timer.h", + "xtensa/cacheasm.h", + "xt_instr_macros.h", + "xtensa_config.h", + "xtensa/cacheattrasm.h", + "xtensa_api.h", + "xtensa/coreasm.h", + "xtensa/xtruntime.h", + "xtensa_context.h", + "xtensa/xtruntime-core-state.h", + "xtensa/xtensa-xer.h", + "xtensa/xt_perf_consts.h", + "xtensa/mpuasm.h", + "xtensa/core-macros.h", + "xtensa/xtruntime-frames.h", + "xt_trax.h", + "xtensa-debug-module.h", + "xtensa/xtensa-versions.h", + "xtensa/xtensa-libdb-macros.h", + "xtensa/idmaasm.h", + "eri.h", + "xtensa/hal.h", + "xtensa/xdm-regs.h", + "xtensa/corebits.h", + "xtensa/traxreg.h", + "xtensa/specreg.h", + "xtensa/semihosting.h", + "esp_private/panic_reason.h", + "esp_cpu_utils.h", + "xtensa/config/core.h", + "xtensa/config/specreg.h", + "xtensa/config/core-isa.h", + "xtensa/config/core-matmap.h", + "xtensa/config/defs.h", + "xtensa/config/extreg.h", + "xtensa/config/system.h", + "xtensa/config/tie-asm.h", + "xtensa/config/tie.h", + "FreeRTOS.h", + "portable.h", + "StackMacros.h", + "deprecated_definitions.h", + "mpu_prototypes.h", + "mpu_wrappers.h", + "projdefs.h", + "stack_macros.h", + "freertos/portmacro.h", + "freertos/xtensa_rtos.h", + "freertos/portbenchmark.h", + "freertos/idf_additions.h", + "freertos/task_snapshot.h", + "esp_private/freertos_debug.h", + "esp_private/freertos_idf_additions_priv.h", + "esp_additions/freertos_tasks_c_additions.h", + "FreeRTOS-Kernel/portable/linux/include/freertos/portmacro_idf.h", + "test_apps/freertos/kernel/freertos_test_utils.h", + "FreeRTOS-Kernel-SMP/include/freertos/portable.h", + "FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h", + "FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/portmacro.h", + "FreeRTOS-Kernel-SMP/portable/riscv/include/freertos/portmacro.h", + "FreeRTOS-Kernel-SMP/portable/linux/include/freertos/portmacro.h", + "FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/xtensa_rtos.h", + "FreeRTOS-Kernel-SMP/portable/linux/utils/wait_for_event.h", + "config/riscv/include/freertos/FreeRTOSConfig_arch.h", + "config/linux/include/freertos/FreeRTOSConfig_arch.h", + "FreeRTOS-Kernel/portable/linux/utils/wait_for_event.h", + "FreeRTOS-Kernel-SMP/include/freertos/StackMacros.h", + "FreeRTOS-Kernel-SMP/include/freertos/deprecated_definitions.h", + "FreeRTOS-Kernel-SMP/include/freertos/projdefs.h", + "FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/portbenchmark.h", + "FreeRTOS-Kernel-SMP/include/freertos/mpu_syscall_numbers.h", + "FreeRTOS-Kernel/portable/linux/include/spinlock.h", + "FreeRTOS-Kernel-SMP/include/freertos/stack_macros.h", + "FreeRTOS-Kernel-SMP/portable/linux/include/spinlock.h", + "FreeRTOS-Kernel-SMP/include/freertos/mpu_prototypes.h", + "port_systick.h", + "FreeRTOS-Kernel-SMP/include/freertos/mpu_wrappers.h", + "esp_private/spi_share_hw_ctrl.h", + "esp_private/esp_memprot_internal.h", + "spinlock.h", + "esp_private/sleep_clock.h", + "esp_memprot.h", + "soc/esp32s3/soc_memprot_types.h", + "esp_wake_stub.h", + "rtc_wdt.h", + "esp_private/io_mux.h", + "esp_private/esp_sleep_internal.h", + "esp_private/sleep_cpu.h", + "esp_private/sleep_modem.h", + "esp_sleep.h", + "hal/soc_hal.h", + "esp_private/esp_cpu_internal.h", + "esp_private/esp_modem_clock.h", + "hal/cpu_hal.h", + "hal/interrupt_controller_hal.h", + "hal/cpu_ll.h", + "esp_private/esp_regdma.h", + "hal/soc_ll.h", + "soc/soc_memory_types.h", + "esp_memory_utils.h", + "esp_private/adc_share_hw_ctrl.h", + "esp_cpu.h", + "esp_ds.h", + "esp_private/esp_clk_utils.h", + "esp_private/esp_clk_tree_common.h", + "esp_private/esp_pau.h", + "esp_async_memcpy.h", + "esp_private/esp_crypto_lock_internal.h", + "esp_private/uart_share_hw_ctrl.h", + "clk_ctrl_os.h", + "esp_hmac.h", + "esp_private/rtc_ctrl.h", + "esp_intr_alloc.h", + "soc/esp32s2/memprot.h", + "esp_clk_tree.h", + "esp_memprot_err.h", + "esp_private/mipi_csi_share_hw_ctrl.h", + "esp_mac.h", + "esp_private/sleep_event.h", + "esp_private/etm_interface.h", + "esp_etm.h", + "esp_private/gdma_sleep_retention.h", + "esp_private/regi2c_ctrl.h", + "esp_private/regdma_link.h", + "esp_private/periph_ctrl.h", + "esp_fault.h", + "esp_private/sleep_usb.h", + "esp_private/esp_pmu.h", + "esp_private/sleep_retention.h", + "esp_private/rtc_clk.h", + "esp_crypto_lock.h", + "esp_chip_info.h", + "dport_access.h", + "esp_private/esp_riscv_intr.h", + "esp_private/sleep_console.h", + "esp_private/esp_gpio_reserve.h", + "esp_private/systimer.h", + "esp_private/mspi_timing_config.h", + "esp_crc.h", + "esp_private/sleep_sys_periph.h", + "esp_private/sleep_gpio.h", + "intr_types.h", + "soc/esp32/rtc.h", + "soc/esp32c6/rtc.h", + "esp_private/sar_periph_ctrl.h", + "esp_ds_err.h", + "esp_intr_types.h", + "esp_dpa_protection.h", + "esp_memprot_types.h", + "soc/esp32c2/rtc.h", + "soc/esp32c3/rtc.h", + "soc/esp32c3/soc_memprot_types.h", + "soc/esp32c5/rtc.h", + "esp_interface.h", + "soc/esp32c61/rtc.h", + "soc/esp32h2/rtc.h", + "soc/esp32p4/rtc.h", + "esp_private/mspi_timing_types.h", + "soc/esp32s2/rtc.h", + "soc/esp32s2/soc_memprot_types.h", + "soc/esp32s3/rtc.h", + "esp_random.h", + "esp_private/mspi_timing_tuning.h", + "esp_private/esp_clk.h", + "esp_private/dma2d.h", + "esp_dma_utils.h", + "esp_private/gdma.h", + "esp_private/dw_gdma.h", + "esp_private/esp_dma_utils.h", + "esp_private/gdma_link.h", + "esp_ldo_regulator.h", + "esp_private/debug_probe.h", + "esp_private/debug_probe_types.h", + "include/soc/rtc.h", + "soc/soc_memory_layout.h", + "esp_heap_caps_init.h", + "esp_heap_caps.h", + "esp_heap_trace.h", + "esp_heap_task_info.h", + "heap_memory_layout.h", + "multi_heap.h", + "esp_log.h", + "esp_log_internal.h", + "esp_log_buffer.h", + "esp_private/log_level.h", + "esp_log_color.h", + "esp_log_level.h", + "esp_log_timestamp.h", + "esp_private/log_lock.h", + "esp_private/log_timestamp.h", + "esp_private/log_util.h", + "inttypes_ext.h", + "soc/sdmmc_periph.h", + "soc/spi_periph.h", + "soc/uart_periph.h", + "soc/rtc_periph.h", + "soc/wdt_periph.h", + "soc/timer_periph.h", + "soc/i2c_periph.h", + "soc/gpio_periph.h", + "soc/i2s_periph.h", + "soc/rtc_cntl_periph.h", + "soc/dedic_gpio_periph.h", + "soc/ledc_periph.h", + "soc/efuse_periph.h", + "soc/rtc_io_periph.h", + "soc/adc_periph.h", + "soc/pcnt_periph.h", + "soc/hwcrypto_periph.h", + "soc/rmt_periph.h", + "soc/parlio_periph.h", + "soc/mcpwm_periph.h", + "soc/usb_periph.h", + "soc/sens_periph.h", + "soc/sdio_slave_periph.h", + "soc/etm_periph.h", + "soc/temperature_sensor_periph.h", + "soc/regdma.h", + "soc/usb_otg_periph.h", + "soc/isp_periph.h", + "soc/emac_periph.h", + "soc/twai_periph.h", + "soc/lcd_periph.h", + "soc/ieee802154_periph.h", + "soc/gdma_periph.h", + "soc/usb_dwc_periph.h", + "soc/cam_periph.h", + "soc/ana_cmpr_periph.h", + "soc/sdm_periph.h", + "soc/mpi_periph.h", + "soc/touch_sensor_periph.h", + "soc/uhci_periph.h", + "soc/dma2d_periph.h", + "soc/debug_probe_periph.h", + "soc/dac_periph.h", + "soc/lldesc.h", + "soc/mipi_dsi_periph.h", + "soc/mipi_csi_periph.h", + "soc/chip_revision.h", + "include/soc/dport_reg.h", + "include/soc/clkout_channel.h", + "include/soc/interrupt_reg.h", + "register/soc/efuse_reg.h", + "include/soc/uart_pins.h", + "include/soc/mmu.h", + "register/soc/rtc_io_reg.h", + "register/soc/usb_reg.h", + "register/soc/rtc_cntl_reg.h", + "include/soc/fe_reg.h", + "register/soc/rmt_reg.h", + "register/soc/uhci_reg.h", + "register/soc/uart_reg.h", + "register/soc/timer_group_reg.h", + "include/soc/hwcrypto_reg.h", + "register/soc/usb_serial_jtag_struct.h", + "register/soc/systimer_reg.h", + "register/soc/system_reg.h", + "register/soc/syscon_reg.h", + "register/soc/usb_wrap_reg.h", + "register/soc/spi_reg.h", + "register/soc/peri_backup_reg.h", + "register/soc/gdma_reg.h", + "register/soc/spi_mem_reg.h", + "register/soc/sensitive_reg.h", + "register/soc/world_controller_reg.h", + "register/soc/sens_reg.h", + "register/soc/sdmmc_reg.h", + "register/soc/extmem_reg.h", + "register/soc/rtc_i2c_reg.h", + "register/soc/gpio_reg.h", + "register/soc/usb_serial_jtag_reg.h", + "include/soc/nrx_reg.h", + "register/soc/assist_debug_reg.h", + "register/soc/gpio_sd_reg.h", + "register/soc/apb_saradc_reg.h", + "register/soc/pcnt_reg.h", + "register/soc/mcpwm_reg.h", + "register/soc/ledc_reg.h", + "register/soc/lcd_cam_reg.h", + "register/soc/io_mux_reg.h", + "register/soc/interrupt_core1_reg.h", + "register/soc/interrupt_core0_reg.h", + "include/soc/boot_mode.h", + "register/soc/i2s_reg.h", + "register/soc/i2c_reg.h", + "register/soc/host_reg.h", + "include/soc/wdev_reg.h", + "register/soc/apb_ctrl_reg.h", + "register/soc/hinf_reg.h", + "include/soc/soc_pins.h", + "include/soc/soc.h", + "include/soc/soc_caps.h", + "include/soc/ext_mem_defs.h", + "include/soc/regi2c_defs.h", + "include/soc/periph_defs.h", + "include/soc/rtc_io_channel.h", + "register/soc/rtc_cntl_struct.h", + "register/soc/efuse_struct.h", + "register/soc/gdma_struct.h", + "register/soc/assist_debug_struct.h", + "register/soc/apb_saradc_struct.h", + "register/soc/gpio_sd_struct.h", + "register/soc/gpio_struct.h", + "register/soc/apb_ctrl_struct.h", + "register/soc/hinf_struct.h", + "include/soc/usb_pins.h", + "register/soc/host_struct.h", + "include/soc/usb_dwc_struct.h", + "register/soc/i2c_struct.h", + "include/soc/usb_dwc_cfg.h", + "register/soc/i2s_struct.h", + "include/soc/uart_channel.h", + "register/soc/interrupt_core0_struct.h", + "include/soc/tracemem_config.h", + "register/soc/interrupt_core1_struct.h", + "include/soc/touch_sensor_pins.h", + "include/soc/touch_sensor_channel.h", + "register/soc/lcd_cam_struct.h", + "include/soc/touch_channel.h", + "register/soc/ledc_struct.h", + "include/soc/spi_pins.h", + "register/soc/mcpwm_struct.h", + "include/soc/soc_ulp.h", + "register/soc/pcnt_struct.h", + "include/soc/sdmmc_pins.h", + "register/soc/peri_backup_struct.h", + "register/soc/reg_base.h", + "include/soc/adc_channel.h", + "register/soc/rmt_struct.h", + "include/soc/reset_reasons.h", + "register/soc/extmem_struct.h", + "include/soc/regi2c_ulp.h", + "register/soc/rtc_i2c_struct.h", + "include/soc/regi2c_saradc.h", + "register/soc/rtc_io_struct.h", + "include/soc/regi2c_lp_bias.h", + "register/soc/sdmmc_struct.h", + "include/soc/regi2c_dig_reg.h", + "include/soc/regi2c_brownout.h", + "register/soc/sensitive_struct.h", + "include/soc/regi2c_bbpll.h", + "register/soc/spi_mem_struct.h", + "include/soc/mpu_caps.h", + "register/soc/spi_struct.h", + "include/soc/memprot_defs.h", + "register/soc/syscon_struct.h", + "include/soc/interrupts.h", + "register/soc/system_struct.h", + "include/soc/interrupt_struct.h", + "register/soc/systimer_struct.h", + "include/soc/gpio_sig_map.h", + "register/soc/timer_group_struct.h", + "register/soc/twai_struct.h", + "include/soc/gpio_pins.h", + "register/soc/uart_struct.h", + "include/soc/gpio_num.h", + "register/soc/uhci_struct.h", + "include/soc/gdma_channel.h", + "include/soc/efuse_defs.h", + "include/soc/dport_access.h", + "register/soc/usb_struct.h", + "include/soc/clk_tree_defs.h", + "register/soc/usb_wrap_struct.h", + "include/soc/bb_reg.h", + "register/soc/world_controller_struct.h", + "hal/log.h", + "hal/regi2c_ctrl.h", + "hal/check.h", + "hal/assert.h", + "hal/misc.h", + "hal/adc_ll.h", + "hal/spimem_flash_ll.h", + "hal/spi_ll.h", + "hal/clk_tree_ll.h", + "hal/mpi_ll.h", + "hal/i2c_ll.h", + "hal/rtc_io_ll.h", + "hal/mwdt_ll.h", + "hal/i2s_ll.h", + "hal/temperature_sensor_ll.h", + "hal/dedic_gpio_cpu_ll.h", + "hal/sha_ll.h", + "hal/gpio_ll.h", + "hal/rwdt_ll.h", + "hal/uart_ll.h", + "hal/psram_ctrlr_ll.h", + "hal/efuse_hal.h", + "hal/lcd_ll.h", + "hal/ledc_ll.h", + "hal/sdmmc_ll.h", + "hal/usb_serial_jtag_ll.h", + "hal/clk_gate_ll.h", + "hal/twai_ll.h", + "hal/memprot_ll.h", + "hal/trace_ll.h", + "hal/mpu_ll.h", + "hal/usb_wrap_ll.h", + "hal/touch_sensor_hal.h", + "hal/efuse_ll.h", + "hal/ds_ll.h", + "hal/mmu_ll.h", + "hal/touch_sensor_ll.h", + "hal/cache_ll.h", + "hal/gdma_ll.h", + "hal/xt_wdt_ll.h", + "hal/rtc_cntl_ll.h", + "hal/sdm_ll.h", + "hal/cpu_utility_ll.h", + "hal/timer_ll.h", + "hal/mspi_timing_tuning_ll.h", + "hal/hmac_ll.h", + "hal/aes_ll.h", + "hal/mcpwm_ll.h", + "hal/rmt_ll.h", + "hal/brownout_ll.h", + "hal/crosscore_int_ll.h", + "hal/regi2c_ctrl_ll.h", + "hal/sar_ctrl_ll.h", + "hal/systimer_ll.h", + "hal/usb_dwc_ll.h", + "hal/uhci_ll.h", + "hal/pcnt_ll.h", + "hal/dedic_gpio_ll.h", + "hal/adc_hal.h", + "hal/spi_slave_hd_hal.h", + "hal/spi_hal.h", + "hal/spi_slave_hal.h", + "hal/rtc_hal.h", + "hal/wdt_hal.h", + "hal/rtc_io_hal.h", + "hal/i2c_hal.h", + "hal/i2s_hal.h", + "hal/uart_hal.h", + "hal/gpio_hal.h", + "hal/ledc_hal.h", + "hal/usb_serial_jtag_hal.h", + "hal/twai_hal.h", + "hal/usb_wrap_hal.h", + "hal/sha_hal.h", + "hal/clk_tree_hal.h", + "hal/aes_hal.h", + "hal/xt_wdt_hal.h", + "hal/interrupt_clic_ll.h", + "hal/interrupt_plic_ll.h", + "hal/interrupt_intc_ll.h", + "hal/memprot_types.h", + "hal/usb_dwc_hal.h", + "hal/mipi_dsi_hal.h", + "hal/mipi_csi_hal.h", + "hal/emac_hal.h", + "hal/mipi_csi_types.h", + "hal/sha_types.h", + "hal/lp_timer_hal.h", + "hal/adc_oneshot_hal.h", + "hal/systimer_hal.h", + "hal/ppa_types.h", + "hal/adc_hal_common.h", + "hal/pau_types.h", + "hal/mpu_hal.h", + "hal/uart_types.h", + "hal/cam_hal.h", + "hal/apm_hal.h", + "hal/spi_types.h", + "hal/sdio_slave_hal.h", + "hal/dma2d_types.h", + "hal/isp_hal.h", + "hal/gdma_hal_axi.h", + "hal/gdma_hal_ahb.h", + "hal/mmu_hal.h", + "hal/adc_types.h", + "hal/cam_types.h", + "hal/touch_sensor_types.h", + "hal/systimer_types.h", + "hal/twai_types.h", + "hal/parlio_hal.h", + "hal/esp_flash_err.h", + "hal/ecdsa_hal.h", + "hal/gpio_types.h", + "hal/isp_types.h", + "hal/i2s_types.h", + "hal/jpeg_hal.h", + "hal/mipi_dsi_types.h", + "hal/assist_debug_hal.h", + "hal/cache_hal.h", + "hal/i2c_types.h", + "hal/lcd_types.h", + "hal/gdma_hal.h", + "hal/timer_types.h", + "hal/dma_types.h", + "hal/modem_clock_hal.h", + "hal/parlio_types.h", + "hal/sdm_types.h", + "hal/pmu_types.h", + "hal/ledc_types.h", + "hal/mcpwm_types.h", + "hal/temperature_sensor_types.h", + "hal/rmt_types.h", + "hal/cam_ctlr_types.h", + "hal/glitch_filter_types.h", + "hal/jpeg_types.h", + "hal/ecc_hal.h", + "hal/sd_types.h", + "hal/usb_wrap_types.h", + "hal/mpu_types.h", + "hal/lp_timer_types.h", + "hal/lp_i2s_hal.h", + "hal/pau_hal.h", + "hal/lp_core_types.h", + "hal/huk_hal.h", + "hal/huk_types.h", + "hal/efuse_hal.h", + "hal/usb_utmi_hal.h", + "hal/usb_serial_jtag_types.h", + "hal/brownout_hal.h", + "hal/ieee802154_common_ll.h", + "hal/mpi_hal.h", + "hal/key_mgr_hal.h", + "hal/key_mgr_types.h", + "hal/ecdsa_types.h", + "hal/mmu_types.h", + "hal/ds_hal.h", + "hal/lcd_hal.h", + "hal/color_hal.h", + "hal/hmac_hal.h", + "hal/cache_types.h", + "hal/wdt_types.h", + "hal/sdio_slave_types.h", + "hal/hal_utils.h", + "hal/touch_sensor_hal.h", + "hal/sdmmc_hal.h", + "hal/hmac_types.h", + "hal/rtc_io_types.h", + "hal/jpeg_defs.h", + "hal/gdma_types.h", + "hal/etm_hal.h", + "hal/eth_types.h", + "hal/rmt_hal.h", + "hal/psram_types.h", + "hal/ecc_types.h", + "hal/dw_gdma_types.h", + "hal/dw_gdma_hal.h", + "hal/ds_types.h", + "hal/timer_hal.h", + "hal/psdet_types.h", + "hal/sdm_hal.h", + "hal/dma2d_hal.h", + "hal/debug_probe_types.h", + "hal/dac_types.h", + "hal/color_types.h", + "hal/ppa_hal.h", + "hal/uhci_types.h", + "hal/ldo_types.h", + "hal/usb_dwc_types.h", + "hal/usb_phy_types.h", + "hal/pcnt_types.h", + "hal/pcnt_hal.h", + "hal/mcpwm_hal.h", + "hal/apm_types.h", + "hal/mpi_types.h", + "hal/aes_types.h", + "hal/modem_clock_types.h", + "hal/adc_types_private.h", + "esp_rom_uart.h", + "esp_rom_spiflash.h", + "esp_rom_efuse.h", + "esp_rom_sys.h", + "esp_rom_gpio.h", + "miniz.h", + "esp_rom_md5.h", + "esp_rom_lldesc.h", + "esp_rom_spiflash_defs.h", + "esp_rom_regi2c.h", + "esp_rom_tlsf.h", + "esp_rom_multi_heap.h", + "esp_rom_crc.h", + "esp32s3/rom/rtc.h", + "esp32s3/rom/uart.h", + "esp32s3/rom/secure_boot.h", + "esp32s3/rom/gpio.h", + "esp32s3/rom/sha.h", + "esp32s3/rom/ets_sys.h", + "esp32s3/rom/opi_flash.h", + "esp32s3/rom/usb/usb_dfu.h", + "esp32s3/rom/usb/usb_device.h", + "esp32s3/rom/hmac.h", + "esp32s3/rom/lldesc.h", + "esp32s3/rom/usb/cdc_acm.h", + "esp32s3/rom/tjpgd.h", + "esp32s3/rom/cache.h", + "esp32s3/rom/bigint.h", + "esp32s3/rom/digital_signature.h", + "esp32s3/rom/crc.h", + "esp32s3/rom/rsa_pss.h", + "esp32s3/rom/apb_backup_dma.h", + "esp32s3/rom/rom_layout.h", + "esp32s3/rom/usb/chip_usb_dw_wrapper.h", + "esp32s3/rom/usb/cpio.h", + "esp32s3/rom/usb/usb_cdc.h", + "esp32s3/rom/usb/usb_dc.h", + "esp32s3/rom/usb/usb_descriptor.h", + "esp32s3/rom/aes.h", + "esp32s3/rom/efuse.h", + "esp32s3/rom/usb/usb_os_glue.h", + "esp32s3/rom/usb/usb_persist.h", + "esp_rom_caps.h", + "esp_check.h", + "esp_macros.h", + "esp_err.h", + "esp_assert.h", + "esp_attr.h", + "esp_compiler.h", + "esp_bit_defs.h", + "esp_idf_version.h", + "esp_types.h", + "esp_expression_with_stack.h", + "esp_private/esp_task_wdt_impl.h", + "esp_task_wdt.h", + "esp_task.h", + "esp_private/critical_section.h", + "esp_freertos_hooks.h", + "esp_debug_helpers.h", + "esp_private/startup_internal.h", + "esp_private/system_internal.h", + "esp_system.h", + "esp_private/panic_internal.h", + "esp_xt_wdt.h", + "esp_systick_etm.h", + "esp_private/esp_ipc.h", + "esp_private/esp_task_wdt.h", + "esp_ipc.h", + "esp_private/usb_console.h", + "esp_private/crosscore_int.h", + "esp_ipc_isr.h", + "esp_private/esp_ipc_isr.h", + "esp_private/eh_frame_parser.h", + "esp_private/esp_int_wdt.h", + "esp_private/trax.h", + "esp_private/image_process.h", + "esp_private/esp_ipc_isr_port.h", + "esp_private/hw_stack_guard.h", + "esp_private/brownout.h", + "esp_private/cache_err_int.h", + "freertos/xtensa_timer.h", + "xtensa/xtensa_timer.h", + "freertos/xtensa_api.h", + "xtensa/xtensa_api.h", + "freertos/xtensa_context.h", + "xtensa/xtensa_context.h", + "arch/cc.h", + "sys/reent.h", + "atomic.h", + "event_groups.h", + "list.h", + "message_buffer.h", + "queue.h", + "semphr.h", + "stream_buffer.h", + "task.h", + "timers.h" + ], + "headerOnly": true, + "deps": [ + "c/os", + "c/time" + ], + "symMap": { + "__sinit": "-" + } +} diff --git a/esp32/llcppg.pub b/esp32/llcppg.pub new file mode 100644 index 00000000..b384cb0e --- /dev/null +++ b/esp32/llcppg.pub @@ -0,0 +1,1544 @@ +AES_BITS AESBITS +AES_TYPE AESTYPE +BYTE +BaseType_t BaseTypeT +CHAR +DWORD +ETSEvent +ETSEventTag +ETSParam +ETSSignal +ETSTask +ETSTimer +ETSTimerFunc +ETS_STATUS ETSSTATUS +EventBits_t EventBitsT +EventGroupDef_t EventGroupDefT +EventGroupHandle_t EventGroupHandleT +GPIO_INT_TYPE GPIOINTTYPE +HeapRegion +HeapRegion_t HeapRegionT +HeapStats_t HeapStatsT +INT +JDEC +JRECT +JRESULT +KernelFrame +LONG +ListItem_t ListItemT +List_t ListT +MD5Context +MemoryRegion_t MemoryRegionT +MessageBufferHandle_t MessageBufferHandleT +MiniListItem_t MiniListItemT +PendedFunction_t PendedFunctionT +QueueDefinition +QueueHandle_t QueueHandleT +QueueSetHandle_t QueueSetHandleT +QueueSetMemberHandle_t QueueSetMemberHandleT +RESET_REASON RESETREASON +RcvMsgBuff +RcvMsgBuffState +RcvMsgState +SHAContext +SHA_CTX SHACTX +SHA_TYPE SHATYPE +SHORT +SLEEP_MODE SLEEPMODE +SemaphoreHandle_t SemaphoreHandleT +StackType_t StackTypeT +StaticEventGroup_t StaticEventGroupT +StaticListItem_t StaticListItemT +StaticList_t StaticListT +StaticMessageBuffer_t StaticMessageBufferT +StaticMiniListItem_t StaticMiniListItemT +StaticQueue_t StaticQueueT +StaticSemaphore_t StaticSemaphoreT +StaticStreamBuffer_t StaticStreamBufferT +StaticTask_t StaticTaskT +StaticTimer_t StaticTimerT +StreamBufferCallbackFunction_t StreamBufferCallbackFunctionT +StreamBufferDef_t StreamBufferDefT +StreamBufferHandle_t StreamBufferHandleT +TaskHandle_t TaskHandleT +TaskHookFunction_t TaskHookFunctionT +TaskIterator +TaskIterator_t TaskIteratorT +TaskParameters_t TaskParametersT +TaskSnapshot_t TaskSnapshotT +TaskStatus_t TaskStatusT +TestFunction_t TestFunctionT +TickType_t TickTypeT +TimeOut_t TimeOutT +TimerCallbackFunction_t TimerCallbackFunctionT +TimerHandle_t TimerHandleT +TlsDeleteCallbackFunction_t TlsDeleteCallbackFunctionT +TrxMsgBuff +UBaseType_t UBaseTypeT +UCHAR +UINT +ULONG +USHORT +UartBautRate +UartBitsNum4Char +UartDevice +UartExistParity +UartFlowCtrl +UartIntType +UartParityMode +UartRcvFifoTrgLvl +UartStopBitsNum +UserFrame +WAKEUP_ENABLE WAKEUPENABLE +WAKEUP_REASON WAKEUPREASON +WCHAR +WORD +XT_INTEXC_HOOK XTINTEXCHOOK +XtExcFrame +XtHalVoidFunc +XtSolFrame +XtosCoreState +adc_arbiter_mode_t AdcArbiterModeT +adc_arbiter_t AdcArbiterT +adc_atten_t AdcAttenT +adc_bitwidth_t AdcBitwidthT +adc_channel_t AdcChannelT +adc_continuous_clk_src_t AdcContinuousClkSrcT +adc_digi_convert_mode_t AdcDigiConvertModeT +adc_digi_iir_filter_coeff_t AdcDigiIirFilterCoeffT +adc_digi_iir_filter_t AdcDigiIirFilterT +adc_digi_output_data_t AdcDigiOutputDataT +adc_digi_output_format_t AdcDigiOutputFormatT +adc_digi_pattern_config_t AdcDigiPatternConfigT +adc_hal_digi_ctrlr_cfg_t AdcHalDigiCtrlrCfgT +adc_hal_dma_config_t AdcHalDmaConfigT +adc_hal_dma_ctx_t AdcHalDmaCtxT +adc_hal_dma_desc_status_t AdcHalDmaDescStatusT +adc_hal_work_mode_t AdcHalWorkModeT +adc_ll_controller_t AdcLlControllerT +adc_ll_digi_convert_mode_t AdcLlDigiConvertModeT +adc_ll_digi_pattern_table_t AdcLlDigiPatternTableT +adc_ll_power_t AdcLlPowerT +adc_ll_rtc_output_data_t AdcLlRtcOutputDataT +adc_ll_rtc_raw_data_t AdcLlRtcRawDataT +adc_monitor_id_t AdcMonitorIdT +adc_monitor_mode_t AdcMonitorModeT +adc_oneshot_clk_src_t AdcOneshotClkSrcT +adc_oneshot_hal_cfg_t AdcOneshotHalCfgT +adc_oneshot_hal_chan_cfg_t AdcOneshotHalChanCfgT +adc_oneshot_hal_ctx_t AdcOneshotHalCtxT +adc_oneshot_soc_handle_t AdcOneshotSocHandleT +adc_ulp_mode_t AdcUlpModeT +adc_unit_t AdcUnitT +apb_ctrl_dev_s ApbCtrlDevS +apb_ctrl_dev_t ApbCtrlDevT +apb_saradc_dev_s ApbSaradcDevS +apb_saradc_dev_t ApbSaradcDevT +apm_region_pms_t ApmRegionPmsT +assist_debug_dev_s AssistDebugDevS +assist_debug_dev_t AssistDebugDevT +async_memcpy_config_t AsyncMemcpyConfigT +async_memcpy_context_t AsyncMemcpyContextT +async_memcpy_event_t AsyncMemcpyEventT +async_memcpy_handle_t AsyncMemcpyHandleT +async_memcpy_isr_cb_t AsyncMemcpyIsrCbT +async_memcpy_t AsyncMemcpyT +autoload_config AutoloadConfig +autoload_region_config AutoloadRegionConfig +bg_ctrl_func_t BgCtrlFuncT +brownout_hal_config_t BrownoutHalConfigT +brownout_reset_level_t BrownoutResetLevelT +cache_array_t CacheArrayT +cache_autoload_order_t CacheAutoloadOrderT +cache_autoload_region_t CacheAutoloadRegionT +cache_autoload_trigger_t CacheAutoloadTriggerT +cache_bus_mask_t CacheBusMaskT +cache_freeze_mode_t CacheFreezeModeT +cache_internal_stub_table CacheInternalStubTable +cache_line_size_t CacheLineSizeT +cache_mode CacheMode +cache_op_cb_t CacheOpCbT +cache_op_end CacheOpEnd +cache_op_start CacheOpStart +cache_size_t CacheSizeT +cache_t CacheT +cache_type_t CacheTypeT +cache_ways_t CacheWaysT +cam_clock_source_t CamClockSourceT +cam_ctlr_color_t CamCtlrColorT +cam_ctlr_data_width_t CamCtlrDataWidthT +cam_dev_t CamDevT +cam_hal_config CamHalConfig +cam_hal_config_t CamHalConfigT +cam_hal_context CamHalContext +cam_hal_context_t CamHalContextT +cdc_acm_descriptor CdcAcmDescriptor +cdc_acm_device CdcAcmDevice +cdc_acm_line_coding CdcAcmLineCoding +cdc_acm_notification CdcAcmNotification +cdc_cm_descriptor CdcCmDescriptor +cdc_ecm_descriptor CdcEcmDescriptor +cdc_header_descriptor CdcHeaderDescriptor +cdc_union_descriptor CdcUnionDescriptor +clk_ll_xtal32k_config_t ClkLlXtal32kConfigT +clk_ll_xtal32k_enable_mode_t ClkLlXtal32kEnableModeT +clock_out_channel ClockOutChannel +clock_out_channel_t ClockOutChannelT +color_component_t ColorComponentT +color_conv_std_rgb_yuv_t ColorConvStdRgbYuvT +color_pixel_alpha_format_t ColorPixelAlphaFormatT +color_pixel_argb8888_data_t ColorPixelArgb8888DataT +color_pixel_argb_format_t ColorPixelArgbFormatT +color_pixel_clut_format_t ColorPixelClutFormatT +color_pixel_gray_format_t ColorPixelGrayFormatT +color_pixel_raw_format_t ColorPixelRawFormatT +color_pixel_rgb565_data_t ColorPixelRgb565DataT +color_pixel_rgb888_data_t ColorPixelRgb888DataT +color_pixel_rgb_format_t ColorPixelRgbFormatT +color_pixel_yuv_format_t ColorPixelYuvFormatT +color_range_t ColorRangeT +color_raw_element_order_t ColorRawElementOrderT +color_rgb_element_order_t ColorRgbElementOrderT +color_space_pixel_format_t ColorSpacePixelFormatT +color_space_t ColorSpaceT +color_yuv422_pack_order_t ColorYuv422PackOrderT +constrain_reg_fields_t ConstrainRegFieldsT +cpio_callback_reason_t CpioCallbackReasonT +cpio_callback_t CpioCallbackT +cpio_file_t CpioFileT +cpio_handle_data_t CpioHandleDataT +cpio_handle_t CpioHandleT +cpio_ret_t CpioRetT +csi_brg_dev_t CsiBrgDevT +csi_host_dev_t CsiHostDevT +dac_channel_t DacChannelT +dac_cosine_atten_t DacCosineAttenT +dac_cosine_phase_t DacCosinePhaseT +dcache_tag_item DcacheTagItem +debug_probe_channel_config_t DebugProbeChannelConfigT +debug_probe_channel_handle_t DebugProbeChannelHandleT +debug_probe_channel_t DebugProbeChannelT +debug_probe_split_u16_t DebugProbeSplitU16T +debug_probe_target_t DebugProbeTargetT +debug_probe_unit_config_t DebugProbeUnitConfigT +debug_probe_unit_handle_t DebugProbeUnitHandleT +debug_probe_unit_t DebugProbeUnitT +dedic_gpio_signal_conn_t DedicGpioSignalConnT +dfu_runtime_descriptor DfuRuntimeDescriptor +dfu_state DfuState +dfu_status DfuStatus +dma2d_channel_direction_t Dma2dChannelDirectionT +dma2d_channel_handle_t Dma2dChannelHandleT +dma2d_channel_t Dma2dChannelT +dma2d_csc_config_t Dma2dCscConfigT +dma2d_csc_rx_option_t Dma2dCscRxOptionT +dma2d_csc_tx_option_t Dma2dCscTxOptionT +dma2d_data_burst_length_t Dma2dDataBurstLengthT +dma2d_descriptor_align8_s Dma2dDescriptorAlign8S +dma2d_descriptor_align8_t Dma2dDescriptorAlign8T +dma2d_descriptor_t Dma2dDescriptorT +dma2d_dev_t Dma2dDevT +dma2d_dscr_port_mode_config_t Dma2dDscrPortModeConfigT +dma2d_event_callback_t Dma2dEventCallbackT +dma2d_event_data_t Dma2dEventDataT +dma2d_group_t Dma2dGroupT +dma2d_hal_context_t Dma2dHalContextT +dma2d_macro_block_size_t Dma2dMacroBlockSizeT +dma2d_pool_config_t Dma2dPoolConfigT +dma2d_pool_handle_t Dma2dPoolHandleT +dma2d_rx_event_callbacks_t Dma2dRxEventCallbacksT +dma2d_scramble_order_t Dma2dScrambleOrderT +dma2d_soc_handle_t Dma2dSocHandleT +dma2d_strategy_config_t Dma2dStrategyConfigT +dma2d_trans_channel_info_t Dma2dTransChannelInfoT +dma2d_trans_config_t Dma2dTransConfigT +dma2d_trans_on_picked_callback_t Dma2dTransOnPickedCallbackT +dma2d_trans_s Dma2dTransS +dma2d_trans_t Dma2dTransT +dma2d_transfer_ability_t Dma2dTransferAbilityT +dma2d_trigger_peripheral_t Dma2dTriggerPeripheralT +dma2d_trigger_t Dma2dTriggerT +dma2d_tx_event_callbacks_t Dma2dTxEventCallbacksT +dma_alignment_info_t DmaAlignmentInfoT +dma_buffer_split_array_t DmaBufferSplitArrayT +dma_buffer_split_info_t DmaBufferSplitInfoT +dma_descriptor_align4_t DmaDescriptorAlign4T +dma_descriptor_align8_s DmaDescriptorAlign8S +dma_descriptor_align8_t DmaDescriptorAlign8T +dma_descriptor_s DmaDescriptorS +dma_descriptor_t DmaDescriptorT +ds_key_check_t DsKeyCheckT +ds_signature_check_t DsSignatureCheckT +dsi_brg_dev_t DsiBrgDevT +dsi_host_dev_t DsiHostDevT +dw_gdma_block_markers_t DwGdmaBlockMarkersT +dw_gdma_block_transfer_config_t DwGdmaBlockTransferConfigT +dw_gdma_block_transfer_type_t DwGdmaBlockTransferTypeT +dw_gdma_break_event_callback_t DwGdmaBreakEventCallbackT +dw_gdma_break_event_data_t DwGdmaBreakEventDataT +dw_gdma_burst_items_t DwGdmaBurstItemsT +dw_gdma_burst_mode_t DwGdmaBurstModeT +dw_gdma_channel_alloc_config_t DwGdmaChannelAllocConfigT +dw_gdma_channel_dynamic_config_t DwGdmaChannelDynamicConfigT +dw_gdma_channel_handle_t DwGdmaChannelHandleT +dw_gdma_channel_static_config_t DwGdmaChannelStaticConfigT +dw_gdma_channel_t DwGdmaChannelT +dw_gdma_dev_t DwGdmaDevT +dw_gdma_event_callbacks_t DwGdmaEventCallbacksT +dw_gdma_flow_controller_t DwGdmaFlowControllerT +dw_gdma_hal_config_t DwGdmaHalConfigT +dw_gdma_hal_context_t DwGdmaHalContextT +dw_gdma_handshake_type_t DwGdmaHandshakeTypeT +dw_gdma_link_list_config_t DwGdmaLinkListConfigT +dw_gdma_link_list_handle_t DwGdmaLinkListHandleT +dw_gdma_link_list_item_t DwGdmaLinkListItemT +dw_gdma_link_list_t DwGdmaLinkListT +dw_gdma_link_list_type_t DwGdmaLinkListTypeT +dw_gdma_lli_handle_t DwGdmaLliHandleT +dw_gdma_lock_level_t DwGdmaLockLevelT +dw_gdma_role_t DwGdmaRoleT +dw_gdma_soc_handle_t DwGdmaSocHandleT +dw_gdma_trans_done_event_callback_t DwGdmaTransDoneEventCallbackT +dw_gdma_trans_done_event_data_t DwGdmaTransDoneEventDataT +dw_gdma_transfer_width_t DwGdmaTransferWidthT +eNotifyAction ENotifyAction +eSleepModeStatus ESleepModeStatus +eTaskState ETaskState +ecc_curve_t EccCurveT +ecc_mod_base_t EccModBaseT +ecc_mode_t EccModeT +ecdsa_curve_t EcdsaCurveT +ecdsa_hal_config_t EcdsaHalConfigT +ecdsa_mode_t EcdsaModeT +ecdsa_sha_mode_t EcdsaShaModeT +ecdsa_sign_type_t EcdsaSignTypeT +efuse_clk_reg_t EfuseClkRegT +efuse_cmd_reg_t EfuseCmdRegT +efuse_conf_reg_t EfuseConfRegT +efuse_dac_conf_reg_t EfuseDacConfRegT +efuse_date_reg_t EfuseDateRegT +efuse_dev_t EfuseDevT +efuse_int_clr_reg_t EfuseIntClrRegT +efuse_int_ena_reg_t EfuseIntEnaRegT +efuse_int_raw_reg_t EfuseIntRawRegT +efuse_int_st_reg_t EfuseIntStRegT +efuse_pgm_check_value0_reg_t EfusePgmCheckValue0RegT +efuse_pgm_check_value1_reg_t EfusePgmCheckValue1RegT +efuse_pgm_check_value2_reg_t EfusePgmCheckValue2RegT +efuse_pgm_data0_reg_t EfusePgmData0RegT +efuse_pgm_data1_reg_t EfusePgmData1RegT +efuse_pgm_data2_reg_t EfusePgmData2RegT +efuse_pgm_data3_reg_t EfusePgmData3RegT +efuse_pgm_data4_reg_t EfusePgmData4RegT +efuse_pgm_data5_reg_t EfusePgmData5RegT +efuse_pgm_data6_reg_t EfusePgmData6RegT +efuse_pgm_data7_reg_t EfusePgmData7RegT +efuse_rd_key0_data0_reg_t EfuseRdKey0Data0RegT +efuse_rd_key0_data1_reg_t EfuseRdKey0Data1RegT +efuse_rd_key0_data2_reg_t EfuseRdKey0Data2RegT +efuse_rd_key0_data3_reg_t EfuseRdKey0Data3RegT +efuse_rd_key0_data4_reg_t EfuseRdKey0Data4RegT +efuse_rd_key0_data5_reg_t EfuseRdKey0Data5RegT +efuse_rd_key0_data6_reg_t EfuseRdKey0Data6RegT +efuse_rd_key0_data7_reg_t EfuseRdKey0Data7RegT +efuse_rd_key1_data0_reg_t EfuseRdKey1Data0RegT +efuse_rd_key1_data1_reg_t EfuseRdKey1Data1RegT +efuse_rd_key1_data2_reg_t EfuseRdKey1Data2RegT +efuse_rd_key1_data3_reg_t EfuseRdKey1Data3RegT +efuse_rd_key1_data4_reg_t EfuseRdKey1Data4RegT +efuse_rd_key1_data5_reg_t EfuseRdKey1Data5RegT +efuse_rd_key1_data6_reg_t EfuseRdKey1Data6RegT +efuse_rd_key1_data7_reg_t EfuseRdKey1Data7RegT +efuse_rd_key2_data0_reg_t EfuseRdKey2Data0RegT +efuse_rd_key2_data1_reg_t EfuseRdKey2Data1RegT +efuse_rd_key2_data2_reg_t EfuseRdKey2Data2RegT +efuse_rd_key2_data3_reg_t EfuseRdKey2Data3RegT +efuse_rd_key2_data4_reg_t EfuseRdKey2Data4RegT +efuse_rd_key2_data5_reg_t EfuseRdKey2Data5RegT +efuse_rd_key2_data6_reg_t EfuseRdKey2Data6RegT +efuse_rd_key2_data7_reg_t EfuseRdKey2Data7RegT +efuse_rd_key3_data0_reg_t EfuseRdKey3Data0RegT +efuse_rd_key3_data1_reg_t EfuseRdKey3Data1RegT +efuse_rd_key3_data2_reg_t EfuseRdKey3Data2RegT +efuse_rd_key3_data3_reg_t EfuseRdKey3Data3RegT +efuse_rd_key3_data4_reg_t EfuseRdKey3Data4RegT +efuse_rd_key3_data5_reg_t EfuseRdKey3Data5RegT +efuse_rd_key3_data6_reg_t EfuseRdKey3Data6RegT +efuse_rd_key3_data7_reg_t EfuseRdKey3Data7RegT +efuse_rd_key4_data0_reg_t EfuseRdKey4Data0RegT +efuse_rd_key4_data1_reg_t EfuseRdKey4Data1RegT +efuse_rd_key4_data2_reg_t EfuseRdKey4Data2RegT +efuse_rd_key4_data3_reg_t EfuseRdKey4Data3RegT +efuse_rd_key4_data4_reg_t EfuseRdKey4Data4RegT +efuse_rd_key4_data5_reg_t EfuseRdKey4Data5RegT +efuse_rd_key4_data6_reg_t EfuseRdKey4Data6RegT +efuse_rd_key4_data7_reg_t EfuseRdKey4Data7RegT +efuse_rd_key5_data0_reg_t EfuseRdKey5Data0RegT +efuse_rd_key5_data1_reg_t EfuseRdKey5Data1RegT +efuse_rd_key5_data2_reg_t EfuseRdKey5Data2RegT +efuse_rd_key5_data3_reg_t EfuseRdKey5Data3RegT +efuse_rd_key5_data4_reg_t EfuseRdKey5Data4RegT +efuse_rd_key5_data5_reg_t EfuseRdKey5Data5RegT +efuse_rd_key5_data6_reg_t EfuseRdKey5Data6RegT +efuse_rd_key5_data7_reg_t EfuseRdKey5Data7RegT +efuse_rd_mac_spi_sys_0_reg_t EfuseRdMacSpiSys0RegT +efuse_rd_mac_spi_sys_1_reg_t EfuseRdMacSpiSys1RegT +efuse_rd_mac_spi_sys_2_reg_t EfuseRdMacSpiSys2RegT +efuse_rd_mac_spi_sys_3_reg_t EfuseRdMacSpiSys3RegT +efuse_rd_mac_spi_sys_4_reg_t EfuseRdMacSpiSys4RegT +efuse_rd_mac_spi_sys_5_reg_t EfuseRdMacSpiSys5RegT +efuse_rd_repeat_data0_reg_t EfuseRdRepeatData0RegT +efuse_rd_repeat_data1_reg_t EfuseRdRepeatData1RegT +efuse_rd_repeat_data2_reg_t EfuseRdRepeatData2RegT +efuse_rd_repeat_data3_reg_t EfuseRdRepeatData3RegT +efuse_rd_repeat_data4_reg_t EfuseRdRepeatData4RegT +efuse_rd_repeat_err0_reg_t EfuseRdRepeatErr0RegT +efuse_rd_repeat_err1_reg_t EfuseRdRepeatErr1RegT +efuse_rd_repeat_err2_reg_t EfuseRdRepeatErr2RegT +efuse_rd_repeat_err3_reg_t EfuseRdRepeatErr3RegT +efuse_rd_repeat_err4_reg_t EfuseRdRepeatErr4RegT +efuse_rd_rs_err0_reg_t EfuseRdRsErr0RegT +efuse_rd_rs_err1_reg_t EfuseRdRsErr1RegT +efuse_rd_sys_part1_data0_reg_t EfuseRdSysPart1Data0RegT +efuse_rd_sys_part1_data1_reg_t EfuseRdSysPart1Data1RegT +efuse_rd_sys_part1_data2_reg_t EfuseRdSysPart1Data2RegT +efuse_rd_sys_part1_data3_reg_t EfuseRdSysPart1Data3RegT +efuse_rd_sys_part1_data4_reg_t EfuseRdSysPart1Data4RegT +efuse_rd_sys_part1_data5_reg_t EfuseRdSysPart1Data5RegT +efuse_rd_sys_part1_data6_reg_t EfuseRdSysPart1Data6RegT +efuse_rd_sys_part1_data7_reg_t EfuseRdSysPart1Data7RegT +efuse_rd_sys_part2_data0_reg_t EfuseRdSysPart2Data0RegT +efuse_rd_sys_part2_data1_reg_t EfuseRdSysPart2Data1RegT +efuse_rd_sys_part2_data2_reg_t EfuseRdSysPart2Data2RegT +efuse_rd_sys_part2_data3_reg_t EfuseRdSysPart2Data3RegT +efuse_rd_sys_part2_data4_reg_t EfuseRdSysPart2Data4RegT +efuse_rd_sys_part2_data5_reg_t EfuseRdSysPart2Data5RegT +efuse_rd_sys_part2_data6_reg_t EfuseRdSysPart2Data6RegT +efuse_rd_sys_part2_data7_reg_t EfuseRdSysPart2Data7RegT +efuse_rd_tim_conf_reg_t EfuseRdTimConfRegT +efuse_rd_usr_data0_reg_t EfuseRdUsrData0RegT +efuse_rd_usr_data1_reg_t EfuseRdUsrData1RegT +efuse_rd_usr_data2_reg_t EfuseRdUsrData2RegT +efuse_rd_usr_data3_reg_t EfuseRdUsrData3RegT +efuse_rd_usr_data4_reg_t EfuseRdUsrData4RegT +efuse_rd_usr_data5_reg_t EfuseRdUsrData5RegT +efuse_rd_usr_data6_reg_t EfuseRdUsrData6RegT +efuse_rd_usr_data7_reg_t EfuseRdUsrData7RegT +efuse_rd_wr_dis_reg_t EfuseRdWrDisRegT +efuse_status_reg_t EfuseStatusRegT +efuse_wr_tim_conf1_reg_t EfuseWrTimConf1RegT +efuse_wr_tim_conf2_reg_t EfuseWrTimConf2RegT +esp_aes_mode_t EspAesModeT +esp_aes_state_t EspAesStateT +esp_alloc_failed_hook_t EspAllocFailedHookT +esp_backtrace_frame_t EspBacktraceFrameT +esp_chip_info_t EspChipInfoT +esp_chip_model_t EspChipModelT +esp_clk_tree_src_freq_precision_t EspClkTreeSrcFreqPrecisionT +esp_cpu_cycle_count_t EspCpuCycleCountT +esp_cpu_frame_t EspCpuFrameT +esp_cpu_intr_desc_t EspCpuIntrDescT +esp_cpu_intr_handler_t EspCpuIntrHandlerT +esp_cpu_intr_type_t EspCpuIntrTypeT +esp_cpu_watchpoint_trigger_t EspCpuWatchpointTriggerT +esp_crypto_dpa_sec_level_t EspCryptoDpaSecLevelT +esp_deep_sleep_cb_t EspDeepSleepCbT +esp_deep_sleep_wake_stub_fn_t EspDeepSleepWakeStubFnT +esp_digital_signature_data EspDigitalSignatureData +esp_digital_signature_length_t EspDigitalSignatureLengthT +esp_dma_buf_location_t EspDmaBufLocationT +esp_dma_mem_info_t EspDmaMemInfoT +esp_ds_context EspDsContext +esp_ds_context_t EspDsContextT +esp_ds_data_t EspDsDataT +esp_ds_p_data_t EspDsPDataT +esp_err_t EspErrT +esp_etm_channel_config_t EspEtmChannelConfigT +esp_etm_channel_handle_t EspEtmChannelHandleT +esp_etm_channel_t EspEtmChannelT +esp_etm_event_handle_t EspEtmEventHandleT +esp_etm_event_t EspEtmEventT +esp_etm_task_handle_t EspEtmTaskHandleT +esp_etm_task_t EspEtmTaskT +esp_freertos_idle_cb_t EspFreertosIdleCbT +esp_freertos_tick_cb_t EspFreertosTickCbT +esp_interface_t EspInterfaceT +esp_intr_cpu_affinity_t EspIntrCpuAffinityT +esp_ipc_func_t EspIpcFuncT +esp_ipc_isr_func_t EspIpcIsrFuncT +esp_key_mgr_huk_info_t EspKeyMgrHukInfoT +esp_key_mgr_interrupt_type_t EspKeyMgrInterruptTypeT +esp_key_mgr_key_generator_mode_t EspKeyMgrKeyGeneratorModeT +esp_key_mgr_key_info_t EspKeyMgrKeyInfoT +esp_key_mgr_key_purpose_t EspKeyMgrKeyPurposeT +esp_key_mgr_key_recovery_info_t EspKeyMgrKeyRecoveryInfoT +esp_key_mgr_key_type_t EspKeyMgrKeyTypeT +esp_key_mgr_key_usage_t EspKeyMgrKeyUsageT +esp_key_mgr_state_t EspKeyMgrStateT +esp_key_mgr_xts_aes_key_len_t EspKeyMgrXtsAesKeyLenT +esp_ldo_channel_config_t EspLdoChannelConfigT +esp_ldo_channel_handle_t EspLdoChannelHandleT +esp_log_level_t EspLogLevelT +esp_mac_type_t EspMacTypeT +esp_memp_config_t EspMempConfigT +esp_memp_intr_source_t EspMempIntrSourceT +esp_mprot_mem_t EspMprotMemT +esp_mprot_pms_area_t EspMprotPmsAreaT +esp_mprot_pms_world_t EspMprotPmsWorldT +esp_mprot_split_addr_t EspMprotSplitAddrT +esp_os_spinlock_t EspOsSpinlockT +esp_reset_reason_t EspResetReasonT +esp_rom_opiflash_cmd_t EspRomOpiflashCmdT +esp_rom_opiflash_def_t EspRomOpiflashDefT +esp_rom_opiflash_spi0rd_t EspRomOpiflashSpi0rdT +esp_rom_spi_cmd_t EspRomSpiCmdT +esp_rom_spiflash_chip_t EspRomSpiflashChipT +esp_rom_spiflash_legacy_data_t EspRomSpiflashLegacyDataT +esp_rom_spiflash_read_mode_t EspRomSpiflashReadModeT +esp_rom_spiflash_result_t EspRomSpiflashResultT +esp_rom_uart_num_t EspRomUartNumT +esp_rom_wake_func_t EspRomWakeFuncT +esp_sha_type EspShaType +esp_sleep_event_cb_config_t EspSleepEventCbConfigT +esp_sleep_event_cb_index_t EspSleepEventCbIndexT +esp_sleep_event_cb_t EspSleepEventCbT +esp_sleep_event_cbs_config_t EspSleepEventCbsConfigT +esp_sleep_ext1_wakeup_mode_t EspSleepExt1WakeupModeT +esp_sleep_mode_t EspSleepModeT +esp_sleep_pd_domain_t EspSleepPdDomainT +esp_sleep_pd_option_t EspSleepPdOptionT +esp_sleep_source_t EspSleepSourceT +esp_sleep_sub_mode_t EspSleepSubModeT +esp_sleep_wakeup_cause_t EspSleepWakeupCauseT +esp_system_init_fn_t EspSystemInitFnT +esp_task_wdt_config_t EspTaskWdtConfigT +esp_task_wdt_user_handle_s EspTaskWdtUserHandleS +esp_task_wdt_user_handle_t EspTaskWdtUserHandleT +esp_usb_console_cb_t EspUsbConsoleCbT +esp_xt_callback_t EspXtCallbackT +esp_xt_wdt_config_t EspXtWdtConfigT +eth_checksum_t EthChecksumT +eth_data_interface_t EthDataInterfaceT +eth_duplex_t EthDuplexT +eth_link_t EthLinkT +eth_mac_dma_burst_len_t EthMacDmaBurstLenT +eth_speed_t EthSpeedT +etm_hal_context_t EtmHalContextT +etm_soc_handle_t EtmSocHandleT +etm_trigger_peripheral_t EtmTriggerPeripheralT +ets_ds_data_t EtsDsDataT +ets_ds_key_t EtsDsKeyT +ets_ds_p_data_t EtsDsPDataT +ets_ds_result_t EtsDsResultT +ets_efuse_block_t EtsEfuseBlockT +ets_efuse_purpose_t EtsEfusePurposeT +ets_idle_cb_t EtsIdleCbT +ets_isr_t EtsIsrT +ets_rom_layout_t EtsRomLayoutT +ets_rsa_pubkey_t EtsRsaPubkeyT +ets_secure_boot_key_digests EtsSecureBootKeyDigests +ets_secure_boot_key_digests_t EtsSecureBootKeyDigestsT +ets_secure_boot_sig_block EtsSecureBootSigBlock +ets_secure_boot_sig_block_t EtsSecureBootSigBlockT +ets_secure_boot_signature EtsSecureBootSignature +ets_secure_boot_signature_t EtsSecureBootSignatureT +ets_status_t EtsStatusT +event Event +extmem_dev_s ExtmemDevS +extmem_dev_t ExtmemDevT +gdma_buffer_mount_config_t GdmaBufferMountConfigT +gdma_channel_alloc_config_t GdmaChannelAllocConfigT +gdma_channel_direction_t GdmaChannelDirectionT +gdma_channel_handle_t GdmaChannelHandleT +gdma_channel_t GdmaChannelT +gdma_dev_s GdmaDevS +gdma_dev_t GdmaDevT +gdma_etm_event_type_t GdmaEtmEventTypeT +gdma_etm_task_type_t GdmaEtmTaskTypeT +gdma_event_callback_t GdmaEventCallbackT +gdma_event_data_t GdmaEventDataT +gdma_hal_config_t GdmaHalConfigT +gdma_hal_context_t GdmaHalContextT +gdma_hal_crc_config_t GdmaHalCrcConfigT +gdma_hal_priv_data_t GdmaHalPrivDataT +gdma_link_list_config_t GdmaLinkListConfigT +gdma_link_list_handle_t GdmaLinkListHandleT +gdma_link_list_t GdmaLinkListT +gdma_lli_owner_t GdmaLliOwnerT +gdma_rx_event_callbacks_t GdmaRxEventCallbacksT +gdma_signal_conn_t GdmaSignalConnT +gdma_strategy_config_t GdmaStrategyConfigT +gdma_transfer_ability_t GdmaTransferAbilityT +gdma_transfer_config_t GdmaTransferConfigT +gdma_trigger_peripheral_t GdmaTriggerPeripheralT +gdma_trigger_t GdmaTriggerT +gdma_tx_event_callbacks_t GdmaTxEventCallbacksT +glitch_filter_clock_source_t GlitchFilterClockSourceT +gpio_dev_s GpioDevS +gpio_dev_t GpioDevT +gpio_drive_cap_t GpioDriveCapT +gpio_hal_context_t GpioHalContextT +gpio_int_type_t GpioIntTypeT +gpio_mode_t GpioModeT +gpio_num_t GpioNumT +gpio_port_t GpioPortT +gpio_pull_mode_t GpioPullModeT +gpio_pulldown_t GpioPulldownT +gpio_pullup_t GpioPullupT +gpio_sd_dev_t GpioSdDevT +gptimer_clock_source_t GptimerClockSourceT +gptimer_count_direction_t GptimerCountDirectionT +gptimer_soc_handle_t GptimerSocHandleT +hal_utils_clk_div_t HalUtilsClkDivT +hal_utils_clk_info_t HalUtilsClkInfoT +hal_utils_div_round_opt_t HalUtilsDivRoundOptT +hal_utils_fixed_point_t HalUtilsFixedPointT +heap_caps_walker_cb_t HeapCapsWalkerCbT +heap_trace_mode_t HeapTraceModeT +heap_trace_record_t HeapTraceRecordT +heap_trace_summary_t HeapTraceSummaryT +hinf_dev_s HinfDevS +hinf_dev_t HinfDevT +hmac_hal_output_t HmacHalOutputT +hmac_key_id_t HmacKeyIdT +host_dev_s HostDevS +host_dev_t HostDevT +i2c_ack_type_t I2cAckTypeT +i2c_addr_bit_len_t I2cAddrBitLenT +i2c_addr_mode_t I2cAddrModeT +i2c_bus_mode_t I2cBusModeT +i2c_clk_conf_reg_t I2cClkConfRegT +i2c_clock_source_t I2cClockSourceT +i2c_comd_reg_t I2cComdRegT +i2c_ctr_reg_t I2cCtrRegT +i2c_data_reg_t I2cDataRegT +i2c_date_reg_t I2cDateRegT +i2c_dev_t I2cDevT +i2c_fifo_conf_reg_t I2cFifoConfRegT +i2c_fifo_st_reg_t I2cFifoStRegT +i2c_filter_cfg_reg_t I2cFilterCfgRegT +i2c_hal_clk_config_t I2cHalClkConfigT +i2c_hal_context_t I2cHalContextT +i2c_hal_sclk_info_t I2cHalSclkInfoT +i2c_hal_timing_config_t I2cHalTimingConfigT +i2c_int_clr_reg_t I2cIntClrRegT +i2c_int_ena_reg_t I2cIntEnaRegT +i2c_int_raw_reg_t I2cIntRawRegT +i2c_int_status_reg_t I2cIntStatusRegT +i2c_intr_event_t I2cIntrEventT +i2c_ll_hw_cmd_t I2cLlHwCmdT +i2c_ll_master_intr_t I2cLlMasterIntrT +i2c_ll_slave_intr_t I2cLlSlaveIntrT +i2c_mode_t I2cModeT +i2c_port_t I2cPortT +i2c_rw_t I2cRwT +i2c_scl_high_period_reg_t I2cSclHighPeriodRegT +i2c_scl_low_period_reg_t I2cSclLowPeriodRegT +i2c_scl_main_st_time_out_reg_t I2cSclMainStTimeOutRegT +i2c_scl_rstart_setup_reg_t I2cSclRstartSetupRegT +i2c_scl_sp_conf_reg_t I2cSclSpConfRegT +i2c_scl_st_time_out_reg_t I2cSclStTimeOutRegT +i2c_scl_start_hold_reg_t I2cSclStartHoldRegT +i2c_scl_stop_hold_reg_t I2cSclStopHoldRegT +i2c_scl_stop_setup_reg_t I2cSclStopSetupRegT +i2c_scl_stretch_conf_reg_t I2cSclStretchConfRegT +i2c_sda_hold_reg_t I2cSdaHoldRegT +i2c_sda_sample_reg_t I2cSdaSampleRegT +i2c_signal_conn_t I2cSignalConnT +i2c_slave_addr_reg_t I2cSlaveAddrRegT +i2c_slave_read_write_status_t I2cSlaveReadWriteStatusT +i2c_slave_stretch_cause_t I2cSlaveStretchCauseT +i2c_sr_reg_t I2cSrRegT +i2c_to_reg_t I2cToRegT +i2c_trans_mode_t I2cTransModeT +i2s_clock_src_t I2sClockSrcT +i2s_data_bit_width_t I2sDataBitWidthT +i2s_dev_s I2sDevS +i2s_dev_t I2sDevT +i2s_dir_t I2sDirT +i2s_etm_event_type_t I2sEtmEventTypeT +i2s_etm_task_type_t I2sEtmTaskTypeT +i2s_hal_clock_info_t I2sHalClockInfoT +i2s_hal_context_t I2sHalContextT +i2s_hal_slot_config_t I2sHalSlotConfigT +i2s_pcm_compress_t I2sPcmCompressT +i2s_pdm_dsr_t I2sPdmDsrT +i2s_pdm_sig_scale_t I2sPdmSigScaleT +i2s_pdm_slot_mask_t I2sPdmSlotMaskT +i2s_pdm_tx_line_mode_t I2sPdmTxLineModeT +i2s_role_t I2sRoleT +i2s_signal_conn_t I2sSignalConnT +i2s_slot_bit_width_t I2sSlotBitWidthT +i2s_slot_mode_t I2sSlotModeT +i2s_std_slot_mask_t I2sStdSlotMaskT +i2s_tdm_slot_mask_t I2sTdmSlotMaskT +icache_tag_item IcacheTagItem +ieee802154_conn_t Ieee802154ConnT +image_process_driver_s ImageProcessDriverS +image_process_driver_t ImageProcessDriverT +inform_out_light_sleep_overhead_cb_t InformOutLightSleepOverheadCbT +int_desc_flag_t IntDescFlagT +int_desc_t IntDescT +int_type_t IntTypeT +interrupt_core0_dev_s InterruptCore0DevS +interrupt_core0_dev_t InterruptCore0DevT +interrupt_core1_dev_s InterruptCore1DevS +interrupt_core1_dev_t InterruptCore1DevT +interrupt_dev_s InterruptDevS +interrupt_dev_t InterruptDevT +interrupt_handler_t InterruptHandlerT +intr_cpu_id_t IntrCpuIdT +intr_handle_data_t IntrHandleDataT +intr_handle_t IntrHandleT +intr_handler_t IntrHandlerT +isp_ae_sample_point_t IspAeSamplePointT +isp_awb_sample_point_t IspAwbSamplePointT +isp_bf_edge_padding_mode_t IspBfEdgePaddingModeT +isp_clk_src_t IspClkSrcT +isp_color_contrast_t IspColorContrastT +isp_color_range_t IspColorRangeT +isp_color_saturation_t IspColorSaturationT +isp_color_t IspColorT +isp_coordinate_t IspCoordinateT +isp_demosaic_edge_padding_mode_t IspDemosaicEdgePaddingModeT +isp_demosaic_grad_ratio_t IspDemosaicGradRatioT +isp_gamma_curve_points_t IspGammaCurvePointsT +isp_hal_bf_cfg_t IspHalBfCfgT +isp_hal_color_cfg_t IspHalColorCfgT +isp_hal_context_t IspHalContextT +isp_hal_demosaic_cfg_t IspHalDemosaicCfgT +isp_hal_sharpen_cfg_t IspHalSharpenCfgT +isp_hist_coeff_t IspHistCoeffT +isp_hist_result_t IspHistResultT +isp_hist_rgb_coefficient_t IspHistRgbCoefficientT +isp_hist_sampling_mode_t IspHistSamplingModeT +isp_hist_weight_t IspHistWeightT +isp_input_data_source_t IspInputDataSourceT +isp_lsc_gain_t IspLscGainT +isp_sharpen_edge_padding_mode_t IspSharpenEdgePaddingModeT +isp_sharpen_h_freq_coeff_t IspSharpenHFreqCoeffT +isp_sharpen_m_freq_coeff IspSharpenMFreqCoeff +isp_window_t IspWindowT +isp_yuv_conv_std_t IspYuvConvStdT +jpeg_codec_mode_t JpegCodecModeT +jpeg_component_factor_t JpegComponentFactorT +jpeg_config_dht_table_t JpegConfigDhtTableT +jpeg_config_frame_info_t JpegConfigFrameInfoT +jpeg_config_quantization_coefficient_t JpegConfigQuantizationCoefficientT +jpeg_dev_t JpegDevT +jpeg_down_sampling_type_t JpegDownSamplingTypeT +jpeg_enc_src_type_t JpegEncSrcTypeT +jpeg_hal_context_t JpegHalContextT +jpeg_huffman_table_info_t JpegHuffmanTableInfoT +jpeg_marker_code_t JpegMarkerCodeT +jpeg_sample_mode_t JpegSampleModeT +jpeg_soc_handle_t JpegSocHandleT +lcd_cam_cam_ctrl1_reg_t LcdCamCamCtrl1RegT +lcd_cam_cam_ctrl_reg_t LcdCamCamCtrlRegT +lcd_cam_cam_rgb_yuv_reg_t LcdCamCamRgbYuvRegT +lcd_cam_dev_t LcdCamDevT +lcd_cam_lc_dma_int_clr_reg_t LcdCamLcDmaIntClrRegT +lcd_cam_lc_dma_int_ena_reg_t LcdCamLcDmaIntEnaRegT +lcd_cam_lc_dma_int_raw_reg_t LcdCamLcDmaIntRawRegT +lcd_cam_lc_dma_int_st_reg_t LcdCamLcDmaIntStRegT +lcd_cam_lc_reg_date_reg_t LcdCamLcRegDateRegT +lcd_cam_lcd_clock_reg_t LcdCamLcdClockRegT +lcd_cam_lcd_cmd_val_reg_t LcdCamLcdCmdValRegT +lcd_cam_lcd_ctrl1_reg_t LcdCamLcdCtrl1RegT +lcd_cam_lcd_ctrl2_reg_t LcdCamLcdCtrl2RegT +lcd_cam_lcd_ctrl_reg_t LcdCamLcdCtrlRegT +lcd_cam_lcd_data_dout_mode_reg_t LcdCamLcdDataDoutModeRegT +lcd_cam_lcd_dly_mode_reg_t LcdCamLcdDlyModeRegT +lcd_cam_lcd_misc_reg_t LcdCamLcdMiscRegT +lcd_cam_lcd_rgb_yuv_reg_t LcdCamLcdRgbYuvRegT +lcd_cam_lcd_user_reg_t LcdCamLcdUserRegT +lcd_clock_source_t LcdClockSourceT +lcd_color_format_t LcdColorFormatT +lcd_color_range_t LcdColorRangeT +lcd_color_rgb_pixel_format_t LcdColorRgbPixelFormatT +lcd_color_space_t LcdColorSpaceT +lcd_hal_context_t LcdHalContextT +lcd_i80_signal_conn_t LcdI80SignalConnT +lcd_ll_swizzle_mode_t LcdLlSwizzleModeT +lcd_rgb_data_endian_t LcdRgbDataEndianT +lcd_rgb_signal_conn_t LcdRgbSignalConnT +lcd_soc_handle_t LcdSocHandleT +lcd_yuv422_pack_order_t LcdYuv422PackOrderT +lcd_yuv_conv_std_t LcdYuvConvStdT +lcd_yuv_sample_t LcdYuvSampleT +ldo_regulator_channel_t LdoRegulatorChannelT +ldo_unit_t LdoUnitT +ledc_channel_t LedcChannelT +ledc_clk_cfg_t LedcClkCfgT +ledc_clk_src_t LedcClkSrcT +ledc_dev_s LedcDevS +ledc_dev_t LedcDevT +ledc_duty_direction_t LedcDutyDirectionT +ledc_fade_mode_t LedcFadeModeT +ledc_hal_context_t LedcHalContextT +ledc_intr_type_t LedcIntrTypeT +ledc_mode_t LedcModeT +ledc_signal_conn_t LedcSignalConnT +ledc_slow_clk_sel_t LedcSlowClkSelT +ledc_timer_bit_t LedcTimerBitT +ledc_timer_t LedcTimerT +lldesc_chain_s LldescChainS +lldesc_chain_t LldescChainT +lldesc_s LldescS +lldesc_t LldescT +lock_config LockConfig +lp_i2s_hal_context_t LpI2sHalContextT +lp_i2s_soc_handle_t LpI2sSocHandleT +mcpwm_cap_chn_cfg_reg_t McpwmCapChnCfgRegT +mcpwm_cap_chn_reg_t McpwmCapChnRegT +mcpwm_cap_status_reg_t McpwmCapStatusRegT +mcpwm_cap_timer_cfg_reg_t McpwmCapTimerCfgRegT +mcpwm_cap_timer_phase_reg_t McpwmCapTimerPhaseRegT +mcpwm_capture_clock_source_t McpwmCaptureClockSourceT +mcpwm_capture_edge_t McpwmCaptureEdgeT +mcpwm_carrier_cfg_reg_t McpwmCarrierCfgRegT +mcpwm_carrier_clock_source_t McpwmCarrierClockSourceT +mcpwm_clk_cfg_reg_t McpwmClkCfgRegT +mcpwm_clk_reg_t McpwmClkRegT +mcpwm_comparator_etm_event_type_t McpwmComparatorEtmEventTypeT +mcpwm_dev_t McpwmDevT +mcpwm_dt_cfg_reg_t McpwmDtCfgRegT +mcpwm_dt_fed_cfg_reg_t McpwmDtFedCfgRegT +mcpwm_dt_red_cfg_reg_t McpwmDtRedCfgRegT +mcpwm_fault_detect_reg_t McpwmFaultDetectRegT +mcpwm_fh_cfg0_reg_t McpwmFhCfg0RegT +mcpwm_fh_cfg1_reg_t McpwmFhCfg1RegT +mcpwm_fh_status_reg_t McpwmFhStatusRegT +mcpwm_gen_cfg0_reg_t McpwmGenCfg0RegT +mcpwm_gen_force_reg_t McpwmGenForceRegT +mcpwm_gen_reg_t McpwmGenRegT +mcpwm_gen_stmp_cfg_reg_t McpwmGenStmpCfgRegT +mcpwm_gen_tstmp_reg_t McpwmGenTstmpRegT +mcpwm_generator_action_t McpwmGeneratorActionT +mcpwm_hal_context_t McpwmHalContextT +mcpwm_hal_init_config_t McpwmHalInitConfigT +mcpwm_int_clr_reg_t McpwmIntClrRegT +mcpwm_int_ena_reg_t McpwmIntEnaRegT +mcpwm_int_raw_reg_t McpwmIntRawRegT +mcpwm_int_st_reg_t McpwmIntStRegT +mcpwm_ll_deadtime_clock_src_t McpwmLlDeadtimeClockSrcT +mcpwm_operator_brake_mode_t McpwmOperatorBrakeModeT +mcpwm_operator_reg_t McpwmOperatorRegT +mcpwm_operator_timersel_reg_t McpwmOperatorTimerselRegT +mcpwm_signal_conn_t McpwmSignalConnT +mcpwm_soc_handle_t McpwmSocHandleT +mcpwm_timer_cfg0_reg_t McpwmTimerCfg0RegT +mcpwm_timer_cfg1_reg_t McpwmTimerCfg1RegT +mcpwm_timer_clock_source_t McpwmTimerClockSourceT +mcpwm_timer_count_mode_t McpwmTimerCountModeT +mcpwm_timer_direction_t McpwmTimerDirectionT +mcpwm_timer_event_t McpwmTimerEventT +mcpwm_timer_regs_t McpwmTimerRegsT +mcpwm_timer_start_stop_cmd_t McpwmTimerStartStopCmdT +mcpwm_timer_status_reg_t McpwmTimerStatusRegT +mcpwm_timer_sync_reg_t McpwmTimerSyncRegT +mcpwm_timer_synci_cfg_reg_t McpwmTimerSynciCfgRegT +mcpwm_update_cfg_reg_t McpwmUpdateCfgRegT +mcpwm_version_reg_t McpwmVersionRegT +md5_context_t Md5ContextT +mem_type_prot_t MemTypeProtT +memprot_hal_area_t MemprotHalAreaT +memprot_hal_err_t MemprotHalErrT +memprot_hal_world_t MemprotHalWorldT +mipi_csi_brg_user_t MipiCsiBrgUserT +mipi_csi_bridge_soc_handle_t MipiCsiBridgeSocHandleT +mipi_csi_hal_config_t MipiCsiHalConfigT +mipi_csi_hal_context_t MipiCsiHalContextT +mipi_csi_host_soc_handle_t MipiCsiHostSocHandleT +mipi_csi_phy_clock_source_t MipiCsiPhyClockSourceT +mipi_dsi_bridge_soc_handle_t MipiDsiBridgeSocHandleT +mipi_dsi_data_type_t MipiDsiDataTypeT +mipi_dsi_dpi_clock_source_t MipiDsiDpiClockSourceT +mipi_dsi_hal_config_t MipiDsiHalConfigT +mipi_dsi_hal_context_t MipiDsiHalContextT +mipi_dsi_host_soc_handle_t MipiDsiHostSocHandleT +mipi_dsi_pattern_type_t MipiDsiPatternTypeT +mipi_dsi_phy_clock_source_t MipiDsiPhyClockSourceT +mmu_mem_caps_t MmuMemCapsT +mmu_page_size_t MmuPageSizeT +mmu_table_id_t MmuTableIdT +mmu_target_t MmuTargetT +mmu_vaddr_t MmuVaddrT +modem_clock_domain_t ModemClockDomainT +modem_clock_lpclk_src_t ModemClockLpclkSrcT +mpi_op_t MpiOpT +mpi_param_t MpiParamT +mpu_access_t MpuAccessT +mspi_timing_ll_flash_mode_t MspiTimingLlFlashModeT +mspi_timing_speed_mode_t MspiTimingSpeedModeT +multi_heap_handle_t MultiHeapHandleT +multi_heap_info MultiHeapInfo +multi_heap_info_t MultiHeapInfoT +multi_heap_walker_cb_t MultiHeapWalkerCbT +mwdt_clock_source_t MwdtClockSourceT +mz_bool MzBool +mz_int16 MzInt16 +mz_int64 MzInt64 +mz_uint MzUint +mz_uint16 MzUint16 +mz_uint32 MzUint32 +mz_uint64 MzUint64 +mz_uint8 MzUint8 +mz_ulong MzUlong +panic_exception_t PanicExceptionT +panic_info_dump_fn_t PanicInfoDumpFnT +panic_info_t PanicInfoT +parl_io_dev_t ParlIoDevT +parlio_bit_pack_order_t ParlioBitPackOrderT +parlio_clock_source_t ParlioClockSourceT +parlio_hal_context_t ParlioHalContextT +parlio_sample_edge_t ParlioSampleEdgeT +parlio_soc_handle_t ParlioSocHandleT +pcnt_channel_edge_action_t PcntChannelEdgeActionT +pcnt_channel_level_action_t PcntChannelLevelActionT +pcnt_ctrl_reg_t PcntCtrlRegT +pcnt_date_reg_t PcntDateRegT +pcnt_dev_t PcntDevT +pcnt_hal_context_t PcntHalContextT +pcnt_int_clr_reg_t PcntIntClrRegT +pcnt_int_ena_reg_t PcntIntEnaRegT +pcnt_int_raw_reg_t PcntIntRawRegT +pcnt_int_st_reg_t PcntIntStRegT +pcnt_ll_watch_event_id_t PcntLlWatchEventIdT +pcnt_signal_conn_t PcntSignalConnT +pcnt_soc_handle_t PcntSocHandleT +pcnt_un_cnt_reg_t PcntUnCntRegT +pcnt_un_conf0_reg_t PcntUnConf0RegT +pcnt_un_conf1_reg_t PcntUnConf1RegT +pcnt_un_conf2_reg_t PcntUnConf2RegT +pcnt_un_status_reg_t PcntUnStatusRegT +pcnt_unit_zero_cross_mode_t PcntUnitZeroCrossModeT +peri_backup_dev_s PeriBackupDevS +peri_backup_dev_t PeriBackupDevT +periph_interrput_t PeriphInterrputT +periph_module_t PeriphModuleT +pmu_hp_icg_modem_mode_t PmuHpIcgModemModeT +pmu_hp_mode_t PmuHpModeT +pmu_hp_power_domain_t PmuHpPowerDomainT +pmu_lp_mode_t PmuLpModeT +poison_check_pfunc_t PoisonCheckPfuncT +poison_fill_pfunc_t PoisonFillPfuncT +portMUX_TYPE PortMUXTYPE +ppa_alpha_update_mode_t PpaAlphaUpdateModeT +ppa_blend_color_mode_t PpaBlendColorModeT +ppa_color_conv_std_rgb_yuv_t PpaColorConvStdRgbYuvT +ppa_color_range_t PpaColorRangeT +ppa_data_burst_length_t PpaDataBurstLengthT +ppa_dev_t PpaDevT +ppa_engine_type_t PpaEngineTypeT +ppa_fill_color_mode_t PpaFillColorModeT +ppa_hal_context_t PpaHalContextT +ppa_soc_handle_t PpaSocHandleT +ppa_srm_color_mode_t PpaSrmColorModeT +ppa_srm_rotation_angle_t PpaSrmRotationAngleT +prvTaskSavedPriority_t PrvTaskSavedPriorityT +psram_hal_cmd_mode_t PsramHalCmdModeT +psram_ll_cs_id_t PsramLlCsIdT +rmt_chm_rx_carrier_rm_reg_t RmtChmRxCarrierRmRegT +rmt_chm_rx_lim_reg_t RmtChmRxLimRegT +rmt_chmconf0_reg_t RmtChmconf0RegT +rmt_chmconf1_reg_t RmtChmconf1RegT +rmt_chmdata_reg_t RmtChmdataRegT +rmt_chmstatus_reg_t RmtChmstatusRegT +rmt_chn_tx_lim_reg_t RmtChnTxLimRegT +rmt_chncarrier_duty_reg_t RmtChncarrierDutyRegT +rmt_chnconf0_reg_t RmtChnconf0RegT +rmt_chndata_reg_t RmtChndataRegT +rmt_chnstatus_reg_t RmtChnstatusRegT +rmt_clock_source_t RmtClockSourceT +rmt_date_reg_t RmtDateRegT +rmt_dev_t RmtDevT +rmt_hal_context_t RmtHalContextT +rmt_int_clr_reg_t RmtIntClrRegT +rmt_int_ena_reg_t RmtIntEnaRegT +rmt_int_raw_reg_t RmtIntRawRegT +rmt_int_st_reg_t RmtIntStRegT +rmt_ll_mem_owner_t RmtLlMemOwnerT +rmt_ref_cnt_rst_reg_t RmtRefCntRstRegT +rmt_signal_conn_t RmtSignalConnT +rmt_soc_handle_t RmtSocHandleT +rmt_symbol_word_t RmtSymbolWordT +rmt_sys_conf_reg_t RmtSysConfRegT +rmt_tx_sim_reg_t RmtTxSimRegT +rtc_cal_sel_t RtcCalSelT +rtc_clk_config_t RtcClkConfigT +rtc_cntl_dev_s RtcCntlDevS +rtc_cntl_dev_t RtcCntlDevT +rtc_cntl_sleep_cache_tag_retent RtcCntlSleepCacheTagRetent +rtc_cntl_sleep_cache_tag_retent_t RtcCntlSleepCacheTagRetentT +rtc_cntl_sleep_retent RtcCntlSleepRetent +rtc_cntl_sleep_retent_t RtcCntlSleepRetentT +rtc_config_t RtcConfigT +rtc_cpu_freq_config_s RtcCpuFreqConfigS +rtc_cpu_freq_config_t RtcCpuFreqConfigT +rtc_cpu_freq_src_t RtcCpuFreqSrcT +rtc_fast_freq_t RtcFastFreqT +rtc_gpio_mode_t RtcGpioModeT +rtc_i2c_cmd_reg_t RtcI2cCmdRegT +rtc_i2c_ctrl_reg_t RtcI2cCtrlRegT +rtc_i2c_data_reg_t RtcI2cDataRegT +rtc_i2c_date_reg_t RtcI2cDateRegT +rtc_i2c_dev_t RtcI2cDevT +rtc_i2c_int_clr_reg_t RtcI2cIntClrRegT +rtc_i2c_int_ena_reg_t RtcI2cIntEnaRegT +rtc_i2c_int_raw_reg_t RtcI2cIntRawRegT +rtc_i2c_int_st_reg_t RtcI2cIntStRegT +rtc_i2c_scl_high_reg_t RtcI2cSclHighRegT +rtc_i2c_scl_low_reg_t RtcI2cSclLowRegT +rtc_i2c_scl_start_period_reg_t RtcI2cSclStartPeriodRegT +rtc_i2c_scl_stop_period_reg_t RtcI2cSclStopPeriodRegT +rtc_i2c_sda_duty_reg_t RtcI2cSdaDutyRegT +rtc_i2c_slave_addr_reg_t RtcI2cSlaveAddrRegT +rtc_i2c_status_reg_t RtcI2cStatusRegT +rtc_i2c_to_reg_t RtcI2cToRegT +rtc_init_config_t RtcInitConfigT +rtc_io_desc_t RtcIoDescT +rtc_io_dev_s RtcIoDevS +rtc_io_dev_t RtcIoDevT +rtc_io_status_t RtcIoStatusT +rtc_sleep_config_t RtcSleepConfigT +rtc_sleep_pu_config_t RtcSleepPuConfigT +rtc_slow_freq_t RtcSlowFreqT +rtc_vddsdio_config_t RtcVddsdioConfigT +rtc_xtal_freq_t RtcXtalFreqT +rtcio_ll_func_t RtcioLlFuncT +rtcio_ll_out_mode_t RtcioLlOutModeT +rtcio_ll_wake_type_t RtcioLlWakeTypeT +rwdt_dev_t RwdtDevT +s16_t S16T +s32_t S32T +s8_t S8T +sar_ctrl_ll_power_t SarCtrlLlPowerT +sd_bus_width_t SdBusWidthT +sdio_slave_hostint_t SdioSlaveHostintT +sdio_slave_sending_mode_t SdioSlaveSendingModeT +sdio_slave_slot_info_t SdioSlaveSlotInfoT +sdio_slave_timing_t SdioSlaveTimingT +sdm_clock_source_t SdmClockSourceT +sdm_hal_context_t SdmHalContextT +sdm_soc_handle_t SdmSocHandleT +sdmmc_desc_s SdmmcDescS +sdmmc_desc_t SdmmcDescT +sdmmc_dev_t SdmmcDevT +sdmmc_hal_context_t SdmmcHalContextT +sdmmc_hw_cmd_s SdmmcHwCmdS +sdmmc_hw_cmd_t SdmmcHwCmdT +sdmmc_ll_delay_phase_t SdmmcLlDelayPhaseT +sdmmc_slot_info_t SdmmcSlotInfoT +sdmmc_slot_io_info_t SdmmcSlotIoInfoT +sdmmc_soc_handle_t SdmmcSocHandleT +secure_boot_status_t SecureBootStatusT +sens_dev_t Sens_Dev_________ +sensitive_dev_s SensitiveDevS +sensitive_dev_t SensitiveDevT +shared_stack_function SharedStackFunction +shutdown_handler_t ShutdownHandlerT +sigma_delta_signal_conn_t SigmaDeltaSignalConnT +sleep_console_usj_enable_state_t SleepConsoleUsjEnableStateT +soc_clkout_sig_id_t SocClkoutSigIdT +soc_cpu_clk_src_t SocCpuClkSrcT +soc_etm_dev_t SocEtmDevT +soc_memory_region_t SocMemoryRegionT +soc_memory_type_desc_t SocMemoryTypeDescT +soc_mipi_csi_phy_pll_freq_range_t SocMipiCsiPhyPllFreqRangeT +soc_mipi_dsi_phy_pll_freq_range_t SocMipiDsiPhyPllFreqRangeT +soc_module_clk_t SocModuleClkT +soc_periph_adc_digi_clk_src_t SocPeriphAdcDigiClkSrcT +soc_periph_adc_rtc_clk_src_t SocPeriphAdcRtcClkSrcT +soc_periph_glitch_filter_clk_src_t SocPeriphGlitchFilterClkSrcT +soc_periph_gptimer_clk_src_t SocPeriphGptimerClkSrcT +soc_periph_i2c_clk_src_t SocPeriphI2cClkSrcT +soc_periph_i2s_clk_src_t SocPeriphI2sClkSrcT +soc_periph_lcd_clk_src_t SocPeriphLcdClkSrcT +soc_periph_ledc_clk_src_legacy_t SocPeriphLedcClkSrcLegacyT +soc_periph_mcpwm_capture_clk_src_t SocPeriphMcpwmCaptureClkSrcT +soc_periph_mcpwm_carrier_clk_src_t SocPeriphMcpwmCarrierClkSrcT +soc_periph_mcpwm_timer_clk_src_t SocPeriphMcpwmTimerClkSrcT +soc_periph_mwdt_clk_src_t SocPeriphMwdtClkSrcT +soc_periph_rmt_clk_src_legacy_t SocPeriphRmtClkSrcLegacyT +soc_periph_rmt_clk_src_t SocPeriphRmtClkSrcT +soc_periph_sdm_clk_src_t SocPeriphSdmClkSrcT +soc_periph_sdmmc_clk_src_t SocPeriphSdmmcClkSrcT +soc_periph_spi_clk_src_t SocPeriphSpiClkSrcT +soc_periph_systimer_clk_src_t SocPeriphSystimerClkSrcT +soc_periph_temperature_sensor_clk_src_t SocPeriphTemperatureSensorClkSrcT +soc_periph_tg_clk_src_legacy_t SocPeriphTgClkSrcLegacyT +soc_periph_twai_clk_src_t SocPeriphTwaiClkSrcT +soc_periph_uart_clk_src_legacy_t SocPeriphUartClkSrcLegacyT +soc_reserved_region_t SocReservedRegionT +soc_reset_reason_t SocResetReasonT +soc_root_clk_t SocRootClkT +soc_rtc_fast_clk_src_t SocRtcFastClkSrcT +soc_rtc_slow_clk_src_t SocRtcSlowClkSrcT +soc_xtal_freq_t SocXtalFreqT +spi_bus_lock_config_t SpiBusLockConfigT +spi_bus_lock_dev_config_t SpiBusLockDevConfigT +spi_bus_lock_dev_handle_t SpiBusLockDevHandleT +spi_bus_lock_dev_t SpiBusLockDevT +spi_bus_lock_handle_t SpiBusLockHandleT +spi_bus_lock_t SpiBusLockT +spi_clock_source_t SpiClockSourceT +spi_command_t SpiCommandT +spi_dev_s SpiDevS +spi_dev_t SpiDevT +spi_dma_desc_t SpiDmaDescT +spi_dma_dev_t SpiDmaDevT +spi_event_t SpiEventT +spi_hal_context_t SpiHalContextT +spi_hal_dev_config_t SpiHalDevConfigT +spi_hal_seg_config_t SpiHalSegConfigT +spi_hal_timing_conf_t SpiHalTimingConfT +spi_hal_timing_param_t SpiHalTimingParamT +spi_hal_trans_config_t SpiHalTransConfigT +spi_host_device_t SpiHostDeviceT +spi_line_mode_t SpiLineModeT +spi_ll_base_command_t SpiLlBaseCommandT +spi_ll_clock_val_t SpiLlClockValT +spi_ll_intr_t SpiLlIntrT +spi_ll_trans_len_cond_t SpiLlTransLenCondT +spi_mem_dev_s SpiMemDevS +spi_mem_dev_t SpiMemDevT +spi_sampling_point_t SpiSamplingPointT +spi_signal_conn_t SpiSignalConnT +spi_slave_hal_config_t SpiSlaveHalConfigT +spi_slave_hal_context_t SpiSlaveHalContextT +spi_slave_hd_hal_config_t SpiSlaveHdHalConfigT +spi_slave_hd_hal_context_t SpiSlaveHdHalContextT +spi_slave_hd_hal_desc_append_t SpiSlaveHdHalDescAppendT +spinlock_t SpinlockT +sys_prot_t SysProtT +sys_startup_fn_t SysStartupFnT +syscon_dev_s SysconDevS +syscon_dev_t SysconDevT +system_dev_s SystemDevS +system_dev_t SystemDevT +systimer_alarm_mode_t SystimerAlarmModeT +systimer_clock_source_t SystimerClockSourceT +systimer_comp_load_reg_t SystimerCompLoadRegT +systimer_conf_reg_t SystimerConfRegT +systimer_counter_value_t SystimerCounterValueT +systimer_date_reg_t SystimerDateRegT +systimer_dev_t SystimerDevT +systimer_hal_context_t SystimerHalContextT +systimer_hal_tick_rate_ops_t SystimerHalTickRateOpsT +systimer_int_clr_reg_t SystimerIntClrRegT +systimer_int_ena_reg_t SystimerIntEnaRegT +systimer_int_raw_reg_t SystimerIntRawRegT +systimer_int_st_reg_t SystimerIntStRegT +systimer_real_target_val_reg_t SystimerRealTargetValRegT +systimer_soc_handle_t SystimerSocHandleT +systimer_target_conf_reg_t SystimerTargetConfRegT +systimer_target_val_reg_t SystimerTargetValRegT +systimer_unit_load_reg_t SystimerUnitLoadRegT +systimer_unit_load_val_reg_t SystimerUnitLoadValRegT +systimer_unit_op_reg_t SystimerUnitOpRegT +systimer_unit_value_reg_t SystimerUnitValueRegT +tag_group_info TagGroupInfo +task_wdt_msg_handler TaskWdtMsgHandler +tdefl_compressor TdeflCompressor +tdefl_flush TdeflFlush +tdefl_put_buf_func_ptr TdeflPutBufFuncPtr +tdefl_status TdeflStatus +temperature_sensor_attribute_t TemperatureSensorAttributeT +temperature_sensor_clk_src_t TemperatureSensorClkSrcT +temperature_sensor_etm_event_type_t TemperatureSensorEtmEventTypeT +temperature_sensor_etm_task_type_t TemperatureSensorEtmTaskTypeT +ticks_to_us_func_t TicksToUsFuncT +timer_group_signal_conn_t TimerGroupSignalConnT +timer_hal_context_t TimerHalContextT +timg_dev_t TimgDevT +timg_hwtimer_reg_t TimgHwtimerRegT +timg_int_clr_timers_reg_t TimgIntClrTimersRegT +timg_int_ena_timers_reg_t TimgIntEnaTimersRegT +timg_int_raw_timers_reg_t TimgIntRawTimersRegT +timg_int_st_timers_reg_t TimgIntStTimersRegT +timg_ntimers_date_reg_t TimgNtimersDateRegT +timg_regclk_reg_t TimgRegclkRegT +timg_rtccalicfg1_reg_t TimgRtccalicfg1RegT +timg_rtccalicfg2_reg_t TimgRtccalicfg2RegT +timg_rtccalicfg_reg_t TimgRtccalicfgRegT +timg_tnalarmhi_reg_t TimgTnalarmhiRegT +timg_tnalarmlo_reg_t TimgTnalarmloRegT +timg_tnconfig_reg_t TimgTnconfigRegT +timg_tnhi_reg_t TimgTnhiRegT +timg_tnlo_reg_t TimgTnloRegT +timg_tnload_reg_t TimgTnloadRegT +timg_tnloadhi_reg_t TimgTnloadhiRegT +timg_tnloadlo_reg_t TimgTnloadloRegT +timg_tnupdate_reg_t TimgTnupdateRegT +timg_wdtconfig0_reg_t TimgWdtconfig0RegT +timg_wdtconfig1_reg_t TimgWdtconfig1RegT +timg_wdtconfig2_reg_t TimgWdtconfig2RegT +timg_wdtconfig3_reg_t TimgWdtconfig3RegT +timg_wdtconfig4_reg_t TimgWdtconfig4RegT +timg_wdtconfig5_reg_t TimgWdtconfig5RegT +timg_wdtfeed_reg_t TimgWdtfeedRegT +timg_wdtwprotect_reg_t TimgWdtwprotectRegT +tinfl_bit_buf_t TinflBitBufT +tinfl_decompressor TinflDecompressor +tinfl_decompressor_tag TinflDecompressorTag +tinfl_huff_table TinflHuffTable +tinfl_put_buf_func_ptr TinflPutBufFuncPtr +tinfl_status TinflStatus +tmrTimerControl TmrTimerControl +touch_cnt_slope_t TouchCntSlopeT +touch_filter_config TouchFilterConfig +touch_filter_config_t TouchFilterConfigT +touch_filter_mode_t TouchFilterModeT +touch_fsm_mode_t TouchFsmModeT +touch_high_volt_t TouchHighVoltT +touch_low_volt_t TouchLowVoltT +touch_pad_conn_type_t TouchPadConnTypeT +touch_pad_denoise TouchPadDenoise +touch_pad_denoise_cap_t TouchPadDenoiseCapT +touch_pad_denoise_grade_t TouchPadDenoiseGradeT +touch_pad_denoise_t TouchPadDenoiseT +touch_pad_intr_mask_t TouchPadIntrMaskT +touch_pad_shield_driver_t TouchPadShieldDriverT +touch_pad_sleep_channel_t TouchPadSleepChannelT +touch_pad_t TouchPadT +touch_pad_waterproof TouchPadWaterproof +touch_pad_waterproof_t TouchPadWaterproofT +touch_smooth_mode_t TouchSmoothModeT +touch_tie_opt_t TouchTieOptT +touch_trigger_mode_t TouchTriggerModeT +touch_trigger_src_t TouchTriggerSrcT +touch_volt_atten_t TouchVoltAttenT +trax_downcount_unit_t TraxDowncountUnitT +trax_ena_select_t TraxEnaSelectT +tskTaskControlBlock TskTaskControlBlock +twai_clock_source_t TwaiClockSourceT +twai_controller_signal_conn_t TwaiControllerSignalConnT +twai_dev_s TwaiDevS +twai_dev_t TwaiDevT +twai_filter_config_t TwaiFilterConfigT +twai_hal_config_t TwaiHalConfigT +twai_hal_context_t TwaiHalContextT +twai_hal_frame_t TwaiHalFrameT +twai_ll_frame_buffer_t TwaiLlFrameBufferT +twai_message_t TwaiMessageT +twai_mode_t TwaiModeT +twai_timing_config_t TwaiTimingConfigT +twdt_ctx_t TwdtCtxT +twdt_isr_callback TwdtIsrCallback +tx_ampdu_entry_s TxAmpduEntryS +tx_ampdu_entry_t TxAmpduEntryT +u16_t U16T +u32_t U32T +u8_t U8T +uart_at_cmd_char_reg_t UartAtCmdCharRegT +uart_at_cmd_gaptout_reg_t UartAtCmdGaptoutRegT +uart_at_cmd_postcnt_reg_t UartAtCmdPostcntRegT +uart_at_cmd_precnt_reg_t UartAtCmdPrecntRegT +uart_at_cmd_t UartAtCmdT +uart_clk_conf_reg_t UartClkConfRegT +uart_clkdiv_reg_t UartClkdivRegT +uart_conf0_reg_t UartConf0RegT +uart_conf1_reg_t UartConf1RegT +uart_date_reg_t UartDateRegT +uart_dev_t UartDevT +uart_fifo_reg_t UartFifoRegT +uart_flow_conf_reg_t UartFlowConfRegT +uart_fsm_status_reg_t UartFsmStatusRegT +uart_hal_context_t UartHalContextT +uart_highpulse_reg_t UartHighpulseRegT +uart_hw_flowcontrol_t UartHwFlowcontrolT +uart_id_reg_t UartIdRegT +uart_idle_conf_reg_t UartIdleConfRegT +uart_int_clr_reg_t UartIntClrRegT +uart_int_ena_reg_t UartIntEnaRegT +uart_int_raw_reg_t UartIntRawRegT +uart_int_st_reg_t UartIntStRegT +uart_intr_t UartIntrT +uart_irq_callback_t UartIrqCallbackT +uart_lowpulse_reg_t UartLowpulseRegT +uart_mem_conf_reg_t UartMemConfRegT +uart_mem_rx_status_reg_t UartMemRxStatusRegT +uart_mem_tx_status_reg_t UartMemTxStatusRegT +uart_mode_t UartModeT +uart_negpulse_reg_t UartNegpulseRegT +uart_parity_t UartParityT +uart_periph_sig_t UartPeriphSigT +uart_port_t UartPortT +uart_pospulse_reg_t UartPospulseRegT +uart_rs485_conf_reg_t UartRs485ConfRegT +uart_rx_filt_reg_t UartRxFiltRegT +uart_rxd_cnt_reg_t UartRxdCntRegT +uart_sclk_t UartSclkT +uart_signal_conn_t UartSignalConnT +uart_signal_inv_t UartSignalInvT +uart_sleep_conf_reg_t UartSleepConfRegT +uart_status_reg_t UartStatusRegT +uart_stop_bits_t UartStopBitsT +uart_sw_flowctrl_t UartSwFlowctrlT +uart_swfc_conf0_reg_t UartSwfcConf0RegT +uart_swfc_conf1_reg_t UartSwfcConf1RegT +uart_txbrk_conf_reg_t UartTxbrkConfRegT +uart_word_length_t UartWordLengthT +uhci_dev_s UhciDevS +uhci_dev_t UhciDevT +uhci_rxeof_cfg_t UhciRxeofCfgT +uhci_seper_chr_t UhciSeperChrT +uhci_swflow_ctrl_sub_chr_t UhciSwflowCtrlSubChrT +update_light_sleep_default_params_config_cb_t UpdateLightSleepDefaultParamsConfigCbT +us_to_ticks_func_t UsToTicksFuncT +usb_cfg_data UsbCfgData +usb_dc_ep_callback UsbDcEpCallback +usb_dc_ep_cb_status_code UsbDcEpCbStatusCode +usb_dc_ep_cfg_data UsbDcEpCfgData +usb_dc_ep_type UsbDcEpType +usb_dc_status_callback UsbDcStatusCallback +usb_dc_status_code UsbDcStatusCode +usb_dev_t UsbDevT +usb_dfu_detach_routine_t UsbDfuDetachRoutineT +usb_dwc_daint_reg_t UsbDwcDaintRegT +usb_dwc_daintmsk_reg_t UsbDwcDaintmskRegT +usb_dwc_dcfg_reg_t UsbDwcDcfgRegT +usb_dwc_dctl_reg_t UsbDwcDctlRegT +usb_dwc_dev_t UsbDwcDevT +usb_dwc_diepctl0_reg_t UsbDwcDiepctl0RegT +usb_dwc_diepctl_reg_t UsbDwcDiepctlRegT +usb_dwc_diepdma0_reg_t UsbDwcDiepdma0RegT +usb_dwc_diepdma_reg_t UsbDwcDiepdmaRegT +usb_dwc_diepdmab0_reg_t UsbDwcDiepdmab0RegT +usb_dwc_diepdmab_reg_t UsbDwcDiepdmabRegT +usb_dwc_diepempmsk_reg_t UsbDwcDiepempmskRegT +usb_dwc_diepint0_reg_t UsbDwcDiepint0RegT +usb_dwc_diepint_reg_t UsbDwcDiepintRegT +usb_dwc_diepmsk_reg_t UsbDwcDiepmskRegT +usb_dwc_dieptsiz0_reg_t UsbDwcDieptsiz0RegT +usb_dwc_dieptsiz_reg_t UsbDwcDieptsizRegT +usb_dwc_dieptxfi_reg_t UsbDwcDieptxfiRegT +usb_dwc_doepctl0_reg_t UsbDwcDoepctl0RegT +usb_dwc_doepctl_reg_t UsbDwcDoepctlRegT +usb_dwc_doepdma0_reg_t UsbDwcDoepdma0RegT +usb_dwc_doepdma_reg_t UsbDwcDoepdmaRegT +usb_dwc_doepdmab0_reg_t UsbDwcDoepdmab0RegT +usb_dwc_doepdmab_reg_t UsbDwcDoepdmabRegT +usb_dwc_doepint0_reg_t UsbDwcDoepint0RegT +usb_dwc_doepint_reg_t UsbDwcDoepintRegT +usb_dwc_doepmsk_reg_t UsbDwcDoepmskRegT +usb_dwc_doeptsiz0_reg_t UsbDwcDoeptsiz0RegT +usb_dwc_doeptsiz_reg_t UsbDwcDoeptsizRegT +usb_dwc_dsts_reg_t UsbDwcDstsRegT +usb_dwc_dthrctl_reg_t UsbDwcDthrctlRegT +usb_dwc_dtxfsts0_reg_t UsbDwcDtxfsts0RegT +usb_dwc_dtxfsts_reg_t UsbDwcDtxfstsRegT +usb_dwc_dvbusdis_reg_t UsbDwcDvbusdisRegT +usb_dwc_dvbuspulse_reg_t UsbDwcDvbuspulseRegT +usb_dwc_gahbcfg_reg_t UsbDwcGahbcfgRegT +usb_dwc_gdfifocfg_reg_t UsbDwcGdfifocfgRegT +usb_dwc_ghwcfg1_reg_t UsbDwcGhwcfg1RegT +usb_dwc_ghwcfg2_reg_t UsbDwcGhwcfg2RegT +usb_dwc_ghwcfg3_reg_t UsbDwcGhwcfg3RegT +usb_dwc_ghwcfg4_reg_t UsbDwcGhwcfg4RegT +usb_dwc_gintmsk_reg_t UsbDwcGintmskRegT +usb_dwc_gintsts_reg_t UsbDwcGintstsRegT +usb_dwc_gnptxfsiz_reg_t UsbDwcGnptxfsizRegT +usb_dwc_gnptxsts_reg_t UsbDwcGnptxstsRegT +usb_dwc_gotgctl_reg_t UsbDwcGotgctlRegT +usb_dwc_gotgint_reg_t UsbDwcGotgintRegT +usb_dwc_grstctl_reg_t UsbDwcGrstctlRegT +usb_dwc_grxfsiz_reg_t UsbDwcGrxfsizRegT +usb_dwc_grxstsp_reg_t UsbDwcGrxstspRegT +usb_dwc_grxstsr_reg_t UsbDwcGrxstsrRegT +usb_dwc_gsnpsid_reg_t UsbDwcGsnpsidRegT +usb_dwc_gusbcfg_reg_t UsbDwcGusbcfgRegT +usb_dwc_haint_reg_t UsbDwcHaintRegT +usb_dwc_haintmsk_reg_t UsbDwcHaintmskRegT +usb_dwc_hal_chan_error_t UsbDwcHalChanErrorT +usb_dwc_hal_chan_event_t UsbDwcHalChanEventT +usb_dwc_hal_chan_t UsbDwcHalChanT +usb_dwc_hal_context_t UsbDwcHalContextT +usb_dwc_hal_ep_char_t UsbDwcHalEpCharT +usb_dwc_hal_fifo_config_t UsbDwcHalFifoConfigT +usb_dwc_hal_port_event_t UsbDwcHalPortEventT +usb_dwc_hcchar_reg_t UsbDwcHccharRegT +usb_dwc_hcdma_reg_t UsbDwcHcdmaRegT +usb_dwc_hcdmab_reg_t UsbDwcHcdmabRegT +usb_dwc_hcfg_reg_t UsbDwcHcfgRegT +usb_dwc_hcint_reg_t UsbDwcHcintRegT +usb_dwc_hcintmsk_reg_t UsbDwcHcintmskRegT +usb_dwc_hctsiz_reg_t UsbDwcHctsizRegT +usb_dwc_hfir_reg_t UsbDwcHfirRegT +usb_dwc_hflbaddr_reg_t UsbDwcHflbaddrRegT +usb_dwc_hfnum_reg_t UsbDwcHfnumRegT +usb_dwc_host_chan_regs_t UsbDwcHostChanRegsT +usb_dwc_hprt_reg_t UsbDwcHprtRegT +usb_dwc_hptxfsiz_reg_t UsbDwcHptxfsizRegT +usb_dwc_hptxsts_reg_t UsbDwcHptxstsRegT +usb_dwc_in_ep_regs_t UsbDwcInEpRegsT +usb_dwc_info_t UsbDwcInfoT +usb_dwc_ll_dma_qtd_t UsbDwcLlDmaQtdT +usb_dwc_out_ep_regs_t UsbDwcOutEpRegsT +usb_dwc_pcgcctl_reg_t UsbDwcPcgcctlRegT +usb_dwc_speed_t UsbDwcSpeedT +usb_dwc_xfer_type_t UsbDwcXferTypeT +usb_ep_callback UsbEpCallback +usb_ep_cfg_data UsbEpCfgData +usb_fsls_serial_signal_conn_t UsbFslsSerialSignalConnT +usb_hal_fifo_bias_t UsbHalFifoBiasT +usb_hal_fifo_mps_limits_t UsbHalFifoMpsLimitsT +usb_hal_frame_list_len_t UsbHalFrameListLenT +usb_in_endpoint_t UsbInEndpointT +usb_in_ep_reg UsbInEpReg +usb_interface_cfg_data UsbInterfaceCfgData +usb_interface_config UsbInterfaceConfig +usb_internal_phy_io_t UsbInternalPhyIoT +usb_iopin_dsc_t UsbIopinDscT +usb_osglue_data_t UsbOsglueDataT +usb_osglue_intdisena_routine_t UsbOsglueIntdisenaRoutineT +usb_osglue_wait_routine_t UsbOsglueWaitRoutineT +usb_otg_mode_t UsbOtgModeT +usb_otg_signal_conn_t UsbOtgSignalConnT +usb_out_endpoint_t UsbOutEndpointT +usb_out_ep_reg UsbOutEpReg +usb_phy_controller_t UsbPhyControllerT +usb_phy_inst_t UsbPhyInstT +usb_phy_signal_conn_t UsbPhySignalConnT +usb_phy_speed_t UsbPhySpeedT +usb_phy_target_t UsbPhyTargetT +usb_reg UsbReg +usb_request_handler UsbRequestHandler +usb_serial_jtag_dev_s UsbSerialJtagDevS +usb_serial_jtag_dev_t UsbSerialJtagDevT +usb_serial_jtag_hal_context_t UsbSerialJtagHalContextT +usb_serial_jtag_intr_t UsbSerialJtagIntrT +usb_serial_jtag_pull_override_vals_t UsbSerialJtagPullOverrideValsT +usb_setup_packet UsbSetupPacket +usb_status_callback UsbStatusCallback +usb_transfer_callback UsbTransferCallback +usb_wrap_date_reg_t UsbWrapDateRegT +usb_wrap_dev_t UsbWrapDevT +usb_wrap_hal_context_t UsbWrapHalContextT +usb_wrap_otg_conf_reg_t UsbWrapOtgConfRegT +usb_wrap_pull_override_vals_t UsbWrapPullOverrideValsT +usb_wrap_test_conf_reg_t UsbWrapTestConfRegT +usb_wrap_test_mode_vals_t UsbWrapTestModeValsT +usbdc_testament_t UsbdcTestamentT +vprintf_like_t VprintfLikeT +walker_block_info WalkerBlockInfo +walker_block_info_t WalkerBlockInfoT +walker_heap_info WalkerHeapInfo +walker_heap_into_t WalkerHeapIntoT +watchpoint_trigger_t WatchpointTriggerT +wcl_core_0_entry_10_addr_reg_t WclCore0Entry10AddrRegT +wcl_core_0_entry_11_addr_reg_t WclCore0Entry11AddrRegT +wcl_core_0_entry_12_addr_reg_t WclCore0Entry12AddrRegT +wcl_core_0_entry_13_addr_reg_t WclCore0Entry13AddrRegT +wcl_core_0_entry_1_addr_reg_t WclCore0Entry1AddrRegT +wcl_core_0_entry_2_addr_reg_t WclCore0Entry2AddrRegT +wcl_core_0_entry_3_addr_reg_t WclCore0Entry3AddrRegT +wcl_core_0_entry_4_addr_reg_t WclCore0Entry4AddrRegT +wcl_core_0_entry_5_addr_reg_t WclCore0Entry5AddrRegT +wcl_core_0_entry_6_addr_reg_t WclCore0Entry6AddrRegT +wcl_core_0_entry_7_addr_reg_t WclCore0Entry7AddrRegT +wcl_core_0_entry_8_addr_reg_t WclCore0Entry8AddrRegT +wcl_core_0_entry_9_addr_reg_t WclCore0Entry9AddrRegT +wcl_core_0_entry_check_reg_t WclCore0EntryCheckRegT +wcl_core_0_message_addr_reg_t WclCore0MessageAddrRegT +wcl_core_0_message_max_reg_t WclCore0MessageMaxRegT +wcl_core_0_message_phase_reg_t WclCore0MessagePhaseRegT +wcl_core_0_nmi_mask_cancle_reg_t WclCore0NmiMaskCancleRegT +wcl_core_0_nmi_mask_disable_reg_t WclCore0NmiMaskDisableRegT +wcl_core_0_nmi_mask_enable_reg_t WclCore0NmiMaskEnableRegT +wcl_core_0_nmi_mask_phase_reg_t WclCore0NmiMaskPhaseRegT +wcl_core_0_nmi_mask_reg_t WclCore0NmiMaskRegT +wcl_core_0_nmi_mask_trigger_addr_reg_t WclCore0NmiMaskTriggerAddrRegT +wcl_core_0_statustable10_reg_t WclCore0Statustable10RegT +wcl_core_0_statustable11_reg_t WclCore0Statustable11RegT +wcl_core_0_statustable12_reg_t WclCore0Statustable12RegT +wcl_core_0_statustable13_reg_t WclCore0Statustable13RegT +wcl_core_0_statustable1_reg_t WclCore0Statustable1RegT +wcl_core_0_statustable2_reg_t WclCore0Statustable2RegT +wcl_core_0_statustable3_reg_t WclCore0Statustable3RegT +wcl_core_0_statustable4_reg_t WclCore0Statustable4RegT +wcl_core_0_statustable5_reg_t WclCore0Statustable5RegT +wcl_core_0_statustable6_reg_t WclCore0Statustable6RegT +wcl_core_0_statustable7_reg_t WclCore0Statustable7RegT +wcl_core_0_statustable8_reg_t WclCore0Statustable8RegT +wcl_core_0_statustable9_reg_t WclCore0Statustable9RegT +wcl_core_0_statustable_current_reg_t WclCore0StatustableCurrentRegT +wcl_core_0_world_cancel_reg_t WclCore0WorldCancelRegT +wcl_core_0_world_dram0_pif_reg_t WclCore0WorldDram0PifRegT +wcl_core_0_world_iram0_reg_t WclCore0WorldIram0RegT +wcl_core_0_world_phase_reg_t WclCore0WorldPhaseRegT +wcl_core_0_world_prepare_reg_t WclCore0WorldPrepareRegT +wcl_core_0_world_trigger_addr_reg_t WclCore0WorldTriggerAddrRegT +wcl_core_0_world_update_reg_t WclCore0WorldUpdateRegT +wcl_core_1_entry_10_addr_reg_t WclCore1Entry10AddrRegT +wcl_core_1_entry_11_addr_reg_t WclCore1Entry11AddrRegT +wcl_core_1_entry_12_addr_reg_t WclCore1Entry12AddrRegT +wcl_core_1_entry_13_addr_reg_t WclCore1Entry13AddrRegT +wcl_core_1_entry_1_addr_reg_t WclCore1Entry1AddrRegT +wcl_core_1_entry_2_addr_reg_t WclCore1Entry2AddrRegT +wcl_core_1_entry_3_addr_reg_t WclCore1Entry3AddrRegT +wcl_core_1_entry_4_addr_reg_t WclCore1Entry4AddrRegT +wcl_core_1_entry_5_addr_reg_t WclCore1Entry5AddrRegT +wcl_core_1_entry_6_addr_reg_t WclCore1Entry6AddrRegT +wcl_core_1_entry_7_addr_reg_t WclCore1Entry7AddrRegT +wcl_core_1_entry_8_addr_reg_t WclCore1Entry8AddrRegT +wcl_core_1_entry_9_addr_reg_t WclCore1Entry9AddrRegT +wcl_core_1_entry_check_reg_t WclCore1EntryCheckRegT +wcl_core_1_message_addr_reg_t WclCore1MessageAddrRegT +wcl_core_1_message_max_reg_t WclCore1MessageMaxRegT +wcl_core_1_message_phase_reg_t WclCore1MessagePhaseRegT +wcl_core_1_nmi_mask_cancle_reg_t WclCore1NmiMaskCancleRegT +wcl_core_1_nmi_mask_disable_reg_t WclCore1NmiMaskDisableRegT +wcl_core_1_nmi_mask_enable_reg_t WclCore1NmiMaskEnableRegT +wcl_core_1_nmi_mask_phase_reg_t WclCore1NmiMaskPhaseRegT +wcl_core_1_nmi_mask_reg_t WclCore1NmiMaskRegT +wcl_core_1_nmi_mask_trigger_addr_reg_t WclCore1NmiMaskTriggerAddrRegT +wcl_core_1_statustable10_reg_t WclCore1Statustable10RegT +wcl_core_1_statustable11_reg_t WclCore1Statustable11RegT +wcl_core_1_statustable12_reg_t WclCore1Statustable12RegT +wcl_core_1_statustable13_reg_t WclCore1Statustable13RegT +wcl_core_1_statustable1_reg_t WclCore1Statustable1RegT +wcl_core_1_statustable2_reg_t WclCore1Statustable2RegT +wcl_core_1_statustable3_reg_t WclCore1Statustable3RegT +wcl_core_1_statustable4_reg_t WclCore1Statustable4RegT +wcl_core_1_statustable5_reg_t WclCore1Statustable5RegT +wcl_core_1_statustable6_reg_t WclCore1Statustable6RegT +wcl_core_1_statustable7_reg_t WclCore1Statustable7RegT +wcl_core_1_statustable8_reg_t WclCore1Statustable8RegT +wcl_core_1_statustable9_reg_t WclCore1Statustable9RegT +wcl_core_1_statustable_current_reg_t WclCore1StatustableCurrentRegT +wcl_core_1_world_cancel_reg_t WclCore1WorldCancelRegT +wcl_core_1_world_dram0_pif_reg_t WclCore1WorldDram0PifRegT +wcl_core_1_world_iram0_reg_t WclCore1WorldIram0RegT +wcl_core_1_world_phase_reg_t WclCore1WorldPhaseRegT +wcl_core_1_world_prepare_reg_t WclCore1WorldPrepareRegT +wcl_core_1_world_trigger_addr_reg_t WclCore1WorldTriggerAddrRegT +wcl_core_1_world_update_reg_t WclCore1WorldUpdateRegT +wcl_dev_t WclDevT +wdt_hal_context_t WdtHalContextT +wdt_inst_t WdtInstT +wdt_reset_sig_length_t WdtResetSigLengthT +wdt_stage_action_t WdtStageActionT +wdt_stage_t WdtStageT +xHeapStats XHeapStats +xLIST XLIST +xLIST_ITEM XLISTITEM +xMEMORY_REGION XMEMORYREGION +xMINI_LIST_ITEM XMINILISTITEM +xSTATIC_EVENT_GROUP XSTATICEVENTGROUP +xSTATIC_LIST XSTATICLIST +xSTATIC_LIST_ITEM XSTATICLISTITEM +xSTATIC_MINI_LIST_ITEM XSTATICMINILISTITEM +xSTATIC_QUEUE XSTATICQUEUE +xSTATIC_STREAM_BUFFER XSTATICSTREAMBUFFER +xSTATIC_TCB XSTATICTCB +xSTATIC_TIMER XSTATICTIMER +xTASK_PARAMETERS XTASKPARAMETERS +xTASK_SNAPSHOT XTASKSNAPSHOT +xTASK_STATUS XTASKSTATUS +xTIME_OUT XTIMEOUT +xt_exc_handler XtExcHandler +xt_wdt_hal_config_t XtWdtHalConfigT +xt_wdt_hal_context_t XtWdtHalContextT +xthal_MPU_entry XthalMPUEntry \ No newline at end of file diff --git a/esp32/lldesc.go b/esp32/lldesc.go new file mode 100644 index 00000000..b1a10b94 --- /dev/null +++ b/esp32/lldesc.go @@ -0,0 +1,75 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const LLDESC_TX_MBLK_SIZE = 268 +const LLDESC_RX_SMBLK_SIZE = 64 +const LLDESC_RX_MBLK_SIZE = 524 +const LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE = 64 +const LLDESC_RX_AMPDU_LEN_MBLK_SIZE = 256 +const LLDESC_TX_MBLK_NUM = 10 +const LLDESC_RX_MBLK_NUM = 10 +const LLDESC_RX_AMPDU_ENTRY_MBLK_NUM = 4 +const LLDESC_RX_AMPDU_LEN_MLBK_NUM = 8 +const LLDESC_OWNER_MASK = 0x80000000 +const LLDESC_OWNER_SHIFT = 31 +const LLDESC_SW_OWNED = 0 +const LLDESC_HW_OWNED = 1 +const LLDESC_EOF_MASK = 0x40000000 +const LLDESC_EOF_SHIFT = 30 +const LLDESC_SOSF_MASK = 0x20000000 +const LLDESC_SOSF_SHIFT = 29 +const LLDESC_LENGTH_MASK = 0x00fff000 +const LLDESC_LENGTH_SHIFT = 12 +const LLDESC_SIZE_MASK = 0x00000fff +const LLDESC_SIZE_SHIFT = 0 +const LLDESC_ADDR_MASK = 0x000fffff + +/** + * Generate a linked list pointing to a (huge) buffer in an descriptor array. + * + * The caller should ensure there is enough size to hold the array, by calling + * ``lldesc_get_required_num_constrained`` with the same max_desc_size argument. + * + * @param[out] out_desc_array Output of a descriptor array, the head should be fed to the DMA. + * @param buffer Buffer for the descriptors to point to. + * @param size Size (or length for TX) of the buffer + * @param max_desc_size Maximum length of each descriptor + * @param isrx The RX DMA may require the buffer to be word-aligned, set to true for a RX link, otherwise false. + */ +// llgo:link (*LldescT).LldescSetupLinkConstrained C.lldesc_setup_link_constrained +func (recv_ *LldescT) LldescSetupLinkConstrained(buffer c.Pointer, size c.Int, max_desc_size c.Int, isrx bool) { +} + +/** + * @brief Get the received length of a linked list, until end of the link or eof. + * + * @param head The head of the linked list. + * @param[out] out_next Output of the next descriptor of the EOF descriptor. Return NULL if there's no + * EOF. Can be set to NULL if next descriptor is not needed. + * @return The accumulation of the `len` field of all descriptors until EOF or the end of the link. + */ +// llgo:link (*LldescT).LldescGetReceivedLen C.lldesc_get_received_len +func (recv_ *LldescT) LldescGetReceivedLen(out_next **LldescT) c.Int { + return 0 +} + +type TxAmpduEntryS struct { + SubLen c.Uint32T + DiliNum c.Uint32T + c.Uint32T + NullByte c.Uint32T + Data c.Uint32T + Enc c.Uint32T + Seq c.Uint32T +} +type TxAmpduEntryT TxAmpduEntryS + +type LldescChainS struct { + Head *LldescT + Tail *LldescT +} +type LldescChainT LldescChainS diff --git a/esp32/llpkg.cfg b/esp32/llpkg.cfg new file mode 100644 index 00000000..f291745f --- /dev/null +++ b/esp32/llpkg.cfg @@ -0,0 +1,8 @@ +{ + "upstream": { + "package": { + "name": "esp32", + "version": "5.4.2" + } + } +} diff --git a/esp32/log.go b/esp32/log.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/log.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/log_level.go b/esp32/log_level.go new file mode 100644 index 00000000..152687d3 --- /dev/null +++ b/esp32/log_level.go @@ -0,0 +1,35 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Set the default log level. + * + * This function sets the default log level used by the ESP-IDF log library. + * The default log level is used by the definition of ESP_LOGx macros and + * can be overridden for specific tags using `esp_log_level_set("*", level)`. + * This is for internal use only. + * + * If CONFIG_LOG_DYNAMIC_LEVEL_CONTROL is not set, this function does not change the default log level. + * + * @param level The new default log level to set. + */ +// llgo:link EspLogLevelT.EspLogSetDefaultLevel C.esp_log_set_default_level +func (recv_ EspLogLevelT) EspLogSetDefaultLevel() { +} + +/** + * @brief Get log level for a given tag, can be used to avoid expensive log statements + * + * The function takes the lock before checking the tag level, + * if the lock wait time exceeds 10 ms (default), then ESP_LOG_NONE is returned. + * + * @param tag Tag of the log to query current level. Must be a zero terminated string. + * If tag is NULL then the default log level is returned (see esp_log_get_default_level()). + * @return The current log level for the given tag. + */ +//go:linkname EspLogLevelGetTimeout C.esp_log_level_get_timeout +func EspLogLevelGetTimeout(tag *c.Char) EspLogLevelT diff --git a/esp32/log_lock.go b/esp32/log_lock.go new file mode 100644 index 00000000..372e7575 --- /dev/null +++ b/esp32/log_lock.go @@ -0,0 +1,12 @@ +package freertos + +import _ "unsafe" + +//go:linkname EspLogImplLock C.esp_log_impl_lock +func EspLogImplLock() + +//go:linkname EspLogImplLockTimeout C.esp_log_impl_lock_timeout +func EspLogImplLockTimeout() bool + +//go:linkname EspLogImplUnlock C.esp_log_impl_unlock +func EspLogImplUnlock() diff --git a/esp32/log_timestamp.go b/esp32/log_timestamp.go new file mode 100644 index 00000000..5872fbf5 --- /dev/null +++ b/esp32/log_timestamp.go @@ -0,0 +1,47 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Get the timestamp in milliseconds for logging. + * + * This function retrieves the timestamp in milliseconds for logging purposes. + * + * @param[in] critical Flag indicating whether the timestamp is needed for a critical log. + * If this flag is true, it means the function is called in one of the following states: + * - early stage, when the Freertos scheduler is not running, + * - ISR, + * - CACHE is disabled. + * + * If the critical flag is set then uint32 timestamp is returned due to cpu ticks being used for this case. + * For some applications this uint32 timestamp may overflow after 4294967295/1000/86400 = 49 days of operation. + * + * @return The uint64 timestamp in milliseconds. + */ +//go:linkname EspLogTimestamp64 C.esp_log_timestamp64 +func EspLogTimestamp64(critical bool) c.Uint64T + +/** + * @brief Convert the uint64 timestamp to a string representation. + * + * This function converts the uint64 timestamp in milliseconds to a string representation. + * The string representation depends on Kconfig options: + * - Milliseconds since boot, + * - Date and time, + * - Time. + * + * @param[in] critical Flag indicating whether the timestamp is critical. If this flag is true, + * it means the function is called in one of the following states: + * - early stage, when the Freertos scheduler is not running, + * - ISR, + * - CACHE is disabled. + * @param[in] timestamp_ms The timestamp to convert, in milliseconds. + * @param[out] buffer Pointer to the buffer where the string representation will be stored. + * + * @return Pointer to the buffer containing the string representation of the timestamp. + */ +//go:linkname EspLogTimestampStr C.esp_log_timestamp_str +func EspLogTimestampStr(critical bool, timestamp_ms c.Uint64T, buffer *c.Char) *c.Char diff --git a/esp32/log_util.go b/esp32/log_util.go new file mode 100644 index 00000000..03493d18 --- /dev/null +++ b/esp32/log_util.go @@ -0,0 +1,63 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Convert an unsigned integer value to a string representation in the specified radix. + * + * This function converts the given unsigned integer value to a string representation in the specified radix. + * The resulting string is stored in the provided character buffer `buf`. + * + * @param[in] val The unsigned integer value to be converted. + * @param[in] radix The base of the numeral system to be used for the conversion. + * It determines the number of unique digits in the numeral system + * (e.g., 2 for binary, 10 for decimal, 16 for hexadecimal). + * @param[in] pad The optional padding width (0 - unused) for the resulting string. It adds zero-padding. + * (val=123, pad=6 -> result=000123). + * @param[in] digits Pointer to a character array representing the digits of the + * numeral system. The array must contain characters in the order of increasing + * values, corresponding to the digits of the radix. For example, "0123456789ABCDEF" + * or hexadecimal. + * @param[out] buf Pointer to the character buffer where the resulting string will + * be stored. The buffer must have enough space to accommodate the entire converted + * string, including the null-terminator. + * + * @return The length of the resulting string (excluding the null-terminator). + * + * @note The buffer `buf` must have sufficient space to hold the entire converted string, including the null-terminator. + * The caller is responsible for ensuring the buffer's size is large enough to prevent buffer overflow. + * @note The provided `digits` array must have enough elements to cover the entire radix used for conversion. Otherwise, undefined behavior may occur. + */ +//go:linkname EspLogUtilCvt C.esp_log_util_cvt +func EspLogUtilCvt(val c.UlongLong, radix c.Long, pad c.Int, digits *c.Char, buf *c.Char) c.Int + +/** + * @brief Convert an unsigned integer to a hexadecimal string with optional padding. + * + * This function converts an unsigned integer value to a hexadecimal string representation. + * This function calls esp_log_util_cvt(val, 16, pad, "0123456789abcdef", buf) inside. + * + * @param val The unsigned integer value to be converted. + * @param pad The optional padding width for the resulting string. + * @param buf The buffer to store the hexadecimal string. + * @return The length of the converted string. + */ +//go:linkname EspLogUtilCvtHex C.esp_log_util_cvt_hex +func EspLogUtilCvtHex(val c.UlongLong, pad c.Int, buf *c.Char) c.Int + +/** + * @brief Convert an unsigned integer to a decimal string with optional padding. + * + * This function converts an unsigned integer value to a decimal string representation. + * This function calls esp_log_util_cvt(val, 10, pad, "0123456789", buf) inside. + * + * @param val The unsigned integer value to be converted. + * @param pad The optional padding width for the resulting string. + * @param buf The buffer to store the decimal string. + * @return The length of the converted string. + */ +//go:linkname EspLogUtilCvtDec C.esp_log_util_cvt_dec +func EspLogUtilCvtDec(val c.UlongLong, pad c.Int, buf *c.Char) c.Int diff --git a/esp32/lp_i2s_hal.go b/esp32/lp_i2s_hal.go new file mode 100644 index 00000000..6a22a07c --- /dev/null +++ b/esp32/lp_i2s_hal.go @@ -0,0 +1,27 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type LpI2sSocHandleT *c.Uint32T + +/** + * Context that should be maintained by both the driver and the HAL + */ + +type LpI2sHalContextT struct { + Dev LpI2sSocHandleT +} + +/** + * @brief Init the LP I2S hal and set the LP I2S to the default configuration. + * @note This function should be called first before other hal layer function is called. + * + * @param hal Context of the HAL layer + * @param group_id LP I2S group ID + */ +// llgo:link (*LpI2sHalContextT).LpI2sHalInit C.lp_i2s_hal_init +func (recv_ *LpI2sHalContextT) LpI2sHalInit(group_id c.Int) { +} diff --git a/esp32/mcpwm_hal.go b/esp32/mcpwm_hal.go new file mode 100644 index 00000000..9a007f42 --- /dev/null +++ b/esp32/mcpwm_hal.go @@ -0,0 +1,74 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type McpwmSocHandleT *McpwmDevT + +/** + * @brief HAL layer configuration + */ + +type McpwmHalInitConfigT struct { + GroupId c.Int +} + +/** + * Context that should be maintained by both the driver and the HAL + */ + +type McpwmHalContextT struct { + Dev McpwmSocHandleT +} + +/** + * @brief Initialize the internal state of the HAL. + * + * @param hal Context of the HAL layer. + * @param init_config Configuration for the HAL to be used only once. + */ +// llgo:link (*McpwmHalContextT).McpwmHalInit C.mcpwm_hal_init +func (recv_ *McpwmHalContextT) McpwmHalInit(init_config *McpwmHalInitConfigT) { +} + +/** + * @brief Deinitialize the HAL driver. + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*McpwmHalContextT).McpwmHalDeinit C.mcpwm_hal_deinit +func (recv_ *McpwmHalContextT) McpwmHalDeinit() { +} + +/** + * @brief Reset MCPWM timer + * + * @param hal Context of the HAL layer. + * @param timer_id Timer ID + */ +// llgo:link (*McpwmHalContextT).McpwmHalTimerReset C.mcpwm_hal_timer_reset +func (recv_ *McpwmHalContextT) McpwmHalTimerReset(timer_id c.Int) { +} + +/** + * @brief Reset MCPWM operator + * + * @param hal Context of the HAL layer. + * @param oper_id Operator ID + */ +// llgo:link (*McpwmHalContextT).McpwmHalOperatorReset C.mcpwm_hal_operator_reset +func (recv_ *McpwmHalContextT) McpwmHalOperatorReset(oper_id c.Int) { +} + +/** + * @brief Reset MCPWM generator + * + * @param hal Context of the HAL layer. + * @param oper_id Operator ID + * @param gen_id Generator ID + */ +// llgo:link (*McpwmHalContextT).McpwmHalGeneratorReset C.mcpwm_hal_generator_reset +func (recv_ *McpwmHalContextT) McpwmHalGeneratorReset(oper_id c.Int, gen_id c.Int) { +} diff --git a/esp32/mcpwm_ll.go b/esp32/mcpwm_ll.go new file mode 100644 index 00000000..106c7eef --- /dev/null +++ b/esp32/mcpwm_ll.go @@ -0,0 +1,22 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const MCPWM_LL_MAX_GROUP_PRESCALE = 256 +const MCPWM_LL_MAX_TIMER_PRESCALE = 256 +const MCPWM_LL_MAX_CARRIER_PRESCALE = 16 +const MCPWM_LL_MAX_CARRIER_ONESHOT = 16 +const MCPWM_LL_MAX_CAPTURE_PRESCALE = 256 +const MCPWM_LL_MAX_CAPTURE_TIMER_PRESCALE = 1 +const MCPWM_LL_MAX_DEAD_DELAY = 65536 +const MCPWM_LL_MAX_COUNT_VALUE = 65536 + +type McpwmLlDeadtimeClockSrcT c.Int + +const ( + MCPWM_LL_DEADTIME_CLK_SRC_GROUP McpwmLlDeadtimeClockSrcT = 0 + MCPWM_LL_DEADTIME_CLK_SRC_TIMER McpwmLlDeadtimeClockSrcT = 1 +) diff --git a/esp32/mcpwm_periph.go b/esp32/mcpwm_periph.go new file mode 100644 index 00000000..952af20f --- /dev/null +++ b/esp32/mcpwm_periph.go @@ -0,0 +1,27 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type McpwmSignalConnT struct { + Groups [2]struct { + Module PeriphModuleT + IrqId c.Int + Operators [3]struct { + Generators [2]struct { + PwmSig c.Uint32T + } + } + GpioFaults [3]struct { + FaultSig c.Uint32T + } + Captures [3]struct { + CapSig c.Uint32T + } + GpioSynchros [3]struct { + SyncSig c.Uint32T + } + } +} diff --git a/esp32/mcpwm_reg.go b/esp32/mcpwm_reg.go new file mode 100644 index 00000000..e9641099 --- /dev/null +++ b/esp32/mcpwm_reg.go @@ -0,0 +1,461 @@ +package freertos + +import _ "unsafe" + +const MCPWM_CLK_PRESCALE_S = 0 +const MCPWM_TIMER0_PRESCALE_S = 0 +const MCPWM_TIMER0_PERIOD_S = 8 +const MCPWM_TIMER0_PERIOD_UPMETHOD_S = 24 +const MCPWM_TIMER0_START_S = 0 +const MCPWM_TIMER0_MOD_S = 3 +const MCPWM_TIMER0_SYNCI_EN_S = 0 +const MCPWM_TIMER0_SYNC_SW_S = 1 +const MCPWM_TIMER0_SYNCO_SEL_S = 2 +const MCPWM_TIMER0_PHASE_S = 4 +const MCPWM_TIMER0_PHASE_DIRECTION_S = 20 +const MCPWM_TIMER0_VALUE_S = 0 +const MCPWM_TIMER0_DIRECTION_S = 16 +const MCPWM_TIMER1_PRESCALE_S = 0 +const MCPWM_TIMER1_PERIOD_S = 8 +const MCPWM_TIMER1_PERIOD_UPMETHOD_S = 24 +const MCPWM_TIMER1_START_S = 0 +const MCPWM_TIMER1_MOD_S = 3 +const MCPWM_TIMER1_SYNCI_EN_S = 0 +const MCPWM_TIMER1_SYNC_SW_S = 1 +const MCPWM_TIMER1_SYNCO_SEL_S = 2 +const MCPWM_TIMER1_PHASE_S = 4 +const MCPWM_TIMER1_PHASE_DIRECTION_S = 20 +const MCPWM_TIMER1_VALUE_S = 0 +const MCPWM_TIMER1_DIRECTION_S = 16 +const MCPWM_TIMER2_PRESCALE_S = 0 +const MCPWM_TIMER2_PERIOD_S = 8 +const MCPWM_TIMER2_PERIOD_UPMETHOD_S = 24 +const MCPWM_TIMER2_START_S = 0 +const MCPWM_TIMER2_MOD_S = 3 +const MCPWM_TIMER2_SYNCI_EN_S = 0 +const MCPWM_TIMER2_SYNC_SW_S = 1 +const MCPWM_TIMER2_SYNCO_SEL_S = 2 +const MCPWM_TIMER2_PHASE_S = 4 +const MCPWM_TIMER2_PHASE_DIRECTION_S = 20 +const MCPWM_TIMER2_VALUE_S = 0 +const MCPWM_TIMER2_DIRECTION_S = 16 +const MCPWM_TIMER0_SYNCISEL_S = 0 +const MCPWM_TIMER1_SYNCISEL_S = 3 +const MCPWM_TIMER2_SYNCISEL_S = 6 +const MCPWM_EXTERNAL_SYNCI0_INVERT_S = 9 +const MCPWM_EXTERNAL_SYNCI1_INVERT_S = 10 +const MCPWM_EXTERNAL_SYNCI2_INVERT_S = 11 +const MCPWM_OPERATOR0_TIMERSEL_S = 0 +const MCPWM_OPERATOR1_TIMERSEL_S = 2 +const MCPWM_OPERATOR2_TIMERSEL_S = 4 +const MCPWM_GEN0_A_UPMETHOD_S = 0 +const MCPWM_GEN0_B_UPMETHOD_S = 4 +const MCPWM_GEN0_A_SHDW_FULL_S = 8 +const MCPWM_GEN0_B_SHDW_FULL_S = 9 +const MCPWM_GEN0_A_S = 0 +const MCPWM_GEN0_B_S = 0 +const MCPWM_GEN0_CFG_UPMETHOD_S = 0 +const MCPWM_GEN0_T0_SEL_S = 4 +const MCPWM_GEN0_T1_SEL_S = 7 +const MCPWM_GEN0_CNTUFORCE_UPMETHOD_S = 0 +const MCPWM_GEN0_A_CNTUFORCE_MODE_S = 6 +const MCPWM_GEN0_B_CNTUFORCE_MODE_S = 8 +const MCPWM_GEN0_A_NCIFORCE_S = 10 +const MCPWM_GEN0_A_NCIFORCE_MODE_S = 11 +const MCPWM_GEN0_B_NCIFORCE_S = 13 +const MCPWM_GEN0_B_NCIFORCE_MODE_S = 14 +const MCPWM_GEN0_A_UTEZ_S = 0 +const MCPWM_GEN0_A_UTEP_S = 2 +const MCPWM_GEN0_A_UTEA_S = 4 +const MCPWM_GEN0_A_UTEB_S = 6 +const MCPWM_GEN0_A_UT0_S = 8 +const MCPWM_GEN0_A_UT1_S = 10 +const MCPWM_GEN0_A_DTEZ_S = 12 +const MCPWM_GEN0_A_DTEP_S = 14 +const MCPWM_GEN0_A_DTEA_S = 16 +const MCPWM_GEN0_A_DTEB_S = 18 +const MCPWM_GEN0_A_DT0_S = 20 +const MCPWM_GEN0_A_DT1_S = 22 +const MCPWM_GEN0_B_UTEZ_S = 0 +const MCPWM_GEN0_B_UTEP_S = 2 +const MCPWM_GEN0_B_UTEA_S = 4 +const MCPWM_GEN0_B_UTEB_S = 6 +const MCPWM_GEN0_B_UT0_S = 8 +const MCPWM_GEN0_B_UT1_S = 10 +const MCPWM_GEN0_B_DTEZ_S = 12 +const MCPWM_GEN0_B_DTEP_S = 14 +const MCPWM_GEN0_B_DTEA_S = 16 +const MCPWM_GEN0_B_DTEB_S = 18 +const MCPWM_GEN0_B_DT0_S = 20 +const MCPWM_GEN0_B_DT1_S = 22 +const MCPWM_DT0_FED_UPMETHOD_S = 0 +const MCPWM_DT0_RED_UPMETHOD_S = 4 +const MCPWM_DT0_DEB_MODE_S = 8 +const MCPWM_DT0_A_OUTSWAP_S = 9 +const MCPWM_DT0_B_OUTSWAP_S = 10 +const MCPWM_DT0_RED_INSEL_S = 11 +const MCPWM_DT0_FED_INSEL_S = 12 +const MCPWM_DT0_RED_OUTINVERT_S = 13 +const MCPWM_DT0_FED_OUTINVERT_S = 14 +const MCPWM_DT0_A_OUTBYPASS_S = 15 +const MCPWM_DT0_B_OUTBYPASS_S = 16 +const MCPWM_DT0_CLK_SEL_S = 17 +const MCPWM_DT0_FED_S = 0 +const MCPWM_DT0_RED_S = 0 +const MCPWM_CARRIER0_EN_S = 0 +const MCPWM_CARRIER0_PRESCALE_S = 1 +const MCPWM_CARRIER0_DUTY_S = 5 +const MCPWM_CARRIER0_OSHTWTH_S = 8 +const MCPWM_CARRIER0_OUT_INVERT_S = 12 +const MCPWM_CARRIER0_IN_INVERT_S = 13 +const MCPWM_FH0_SW_CBC_S = 0 +const MCPWM_FH0_F2_CBC_S = 1 +const MCPWM_FH0_F1_CBC_S = 2 +const MCPWM_FH0_F0_CBC_S = 3 +const MCPWM_FH0_SW_OST_S = 4 +const MCPWM_FH0_F2_OST_S = 5 +const MCPWM_FH0_F1_OST_S = 6 +const MCPWM_FH0_F0_OST_S = 7 +const MCPWM_FH0_A_CBC_D_S = 8 +const MCPWM_FH0_A_CBC_U_S = 10 +const MCPWM_FH0_A_OST_D_S = 12 +const MCPWM_FH0_A_OST_U_S = 14 +const MCPWM_FH0_B_CBC_D_S = 16 +const MCPWM_FH0_B_CBC_U_S = 18 +const MCPWM_FH0_B_OST_D_S = 20 +const MCPWM_FH0_B_OST_U_S = 22 +const MCPWM_FH0_CLR_OST_S = 0 +const MCPWM_FH0_CBCPULSE_S = 1 +const MCPWM_FH0_FORCE_CBC_S = 3 +const MCPWM_FH0_FORCE_OST_S = 4 +const MCPWM_FH0_CBC_ON_S = 0 +const MCPWM_FH0_OST_ON_S = 1 +const MCPWM_GEN1_A_UPMETHOD_S = 0 +const MCPWM_GEN1_B_UPMETHOD_S = 4 +const MCPWM_GEN1_A_SHDW_FULL_S = 8 +const MCPWM_GEN1_B_SHDW_FULL_S = 9 +const MCPWM_GEN1_A_S = 0 +const MCPWM_GEN1_B_S = 0 +const MCPWM_GEN1_CFG_UPMETHOD_S = 0 +const MCPWM_GEN1_T0_SEL_S = 4 +const MCPWM_GEN1_T1_SEL_S = 7 +const MCPWM_GEN1_CNTUFORCE_UPMETHOD_S = 0 +const MCPWM_GEN1_A_CNTUFORCE_MODE_S = 6 +const MCPWM_GEN1_B_CNTUFORCE_MODE_S = 8 +const MCPWM_GEN1_A_NCIFORCE_S = 10 +const MCPWM_GEN1_A_NCIFORCE_MODE_S = 11 +const MCPWM_GEN1_B_NCIFORCE_S = 13 +const MCPWM_GEN1_B_NCIFORCE_MODE_S = 14 +const MCPWM_GEN1_A_UTEZ_S = 0 +const MCPWM_GEN1_A_UTEP_S = 2 +const MCPWM_GEN1_A_UTEA_S = 4 +const MCPWM_GEN1_A_UTEB_S = 6 +const MCPWM_GEN1_A_UT0_S = 8 +const MCPWM_GEN1_A_UT1_S = 10 +const MCPWM_GEN1_A_DTEZ_S = 12 +const MCPWM_GEN1_A_DTEP_S = 14 +const MCPWM_GEN1_A_DTEA_S = 16 +const MCPWM_GEN1_A_DTEB_S = 18 +const MCPWM_GEN1_A_DT0_S = 20 +const MCPWM_GEN1_A_DT1_S = 22 +const MCPWM_GEN1_B_UTEZ_S = 0 +const MCPWM_GEN1_B_UTEP_S = 2 +const MCPWM_GEN1_B_UTEA_S = 4 +const MCPWM_GEN1_B_UTEB_S = 6 +const MCPWM_GEN1_B_UT0_S = 8 +const MCPWM_GEN1_B_UT1_S = 10 +const MCPWM_GEN1_B_DTEZ_S = 12 +const MCPWM_GEN1_B_DTEP_S = 14 +const MCPWM_GEN1_B_DTEA_S = 16 +const MCPWM_GEN1_B_DTEB_S = 18 +const MCPWM_GEN1_B_DT0_S = 20 +const MCPWM_GEN1_B_DT1_S = 22 +const MCPWM_DT1_FED_UPMETHOD_S = 0 +const MCPWM_DT1_RED_UPMETHOD_S = 4 +const MCPWM_DT1_DEB_MODE_S = 8 +const MCPWM_DT1_A_OUTSWAP_S = 9 +const MCPWM_DT1_B_OUTSWAP_S = 10 +const MCPWM_DT1_RED_INSEL_S = 11 +const MCPWM_DT1_FED_INSEL_S = 12 +const MCPWM_DT1_RED_OUTINVERT_S = 13 +const MCPWM_DT1_FED_OUTINVERT_S = 14 +const MCPWM_DT1_A_OUTBYPASS_S = 15 +const MCPWM_DT1_B_OUTBYPASS_S = 16 +const MCPWM_DT1_CLK_SEL_S = 17 +const MCPWM_DT1_FED_S = 0 +const MCPWM_DT1_RED_S = 0 +const MCPWM_CARRIER1_EN_S = 0 +const MCPWM_CARRIER1_PRESCALE_S = 1 +const MCPWM_CARRIER1_DUTY_S = 5 +const MCPWM_CARRIER1_OSHTWTH_S = 8 +const MCPWM_CARRIER1_OUT_INVERT_S = 12 +const MCPWM_CARRIER1_IN_INVERT_S = 13 +const MCPWM_FH1_SW_CBC_S = 0 +const MCPWM_FH1_F2_CBC_S = 1 +const MCPWM_FH1_F1_CBC_S = 2 +const MCPWM_FH1_F0_CBC_S = 3 +const MCPWM_FH1_SW_OST_S = 4 +const MCPWM_FH1_F2_OST_S = 5 +const MCPWM_FH1_F1_OST_S = 6 +const MCPWM_FH1_F0_OST_S = 7 +const MCPWM_FH1_A_CBC_D_S = 8 +const MCPWM_FH1_A_CBC_U_S = 10 +const MCPWM_FH1_A_OST_D_S = 12 +const MCPWM_FH1_A_OST_U_S = 14 +const MCPWM_FH1_B_CBC_D_S = 16 +const MCPWM_FH1_B_CBC_U_S = 18 +const MCPWM_FH1_B_OST_D_S = 20 +const MCPWM_FH1_B_OST_U_S = 22 +const MCPWM_FH1_CLR_OST_S = 0 +const MCPWM_FH1_CBCPULSE_S = 1 +const MCPWM_FH1_FORCE_CBC_S = 3 +const MCPWM_FH1_FORCE_OST_S = 4 +const MCPWM_FH1_CBC_ON_S = 0 +const MCPWM_FH1_OST_ON_S = 1 +const MCPWM_GEN2_A_UPMETHOD_S = 0 +const MCPWM_GEN2_B_UPMETHOD_S = 4 +const MCPWM_GEN2_A_SHDW_FULL_S = 8 +const MCPWM_GEN2_B_SHDW_FULL_S = 9 +const MCPWM_GEN2_A_S = 0 +const MCPWM_GEN2_B_S = 0 +const MCPWM_GEN2_CFG_UPMETHOD_S = 0 +const MCPWM_GEN2_T0_SEL_S = 4 +const MCPWM_GEN2_T1_SEL_S = 7 +const MCPWM_GEN2_CNTUFORCE_UPMETHOD_S = 0 +const MCPWM_GEN2_A_CNTUFORCE_MODE_S = 6 +const MCPWM_GEN2_B_CNTUFORCE_MODE_S = 8 +const MCPWM_GEN2_A_NCIFORCE_S = 10 +const MCPWM_GEN2_A_NCIFORCE_MODE_S = 11 +const MCPWM_GEN2_B_NCIFORCE_S = 13 +const MCPWM_GEN2_B_NCIFORCE_MODE_S = 14 +const MCPWM_GEN2_A_UTEZ_S = 0 +const MCPWM_GEN2_A_UTEP_S = 2 +const MCPWM_GEN2_A_UTEA_S = 4 +const MCPWM_GEN2_A_UTEB_S = 6 +const MCPWM_GEN2_A_UT0_S = 8 +const MCPWM_GEN2_A_UT1_S = 10 +const MCPWM_GEN2_A_DTEZ_S = 12 +const MCPWM_GEN2_A_DTEP_S = 14 +const MCPWM_GEN2_A_DTEA_S = 16 +const MCPWM_GEN2_A_DTEB_S = 18 +const MCPWM_GEN2_A_DT0_S = 20 +const MCPWM_GEN2_A_DT1_S = 22 +const MCPWM_GEN2_B_UTEZ_S = 0 +const MCPWM_GEN2_B_UTEP_S = 2 +const MCPWM_GEN2_B_UTEA_S = 4 +const MCPWM_GEN2_B_UTEB_S = 6 +const MCPWM_GEN2_B_UT0_S = 8 +const MCPWM_GEN2_B_UT1_S = 10 +const MCPWM_GEN2_B_DTEZ_S = 12 +const MCPWM_GEN2_B_DTEP_S = 14 +const MCPWM_GEN2_B_DTEA_S = 16 +const MCPWM_GEN2_B_DTEB_S = 18 +const MCPWM_GEN2_B_DT0_S = 20 +const MCPWM_GEN2_B_DT1_S = 22 +const MCPWM_DT2_FED_UPMETHOD_S = 0 +const MCPWM_DT2_RED_UPMETHOD_S = 4 +const MCPWM_DT2_DEB_MODE_S = 8 +const MCPWM_DT2_A_OUTSWAP_S = 9 +const MCPWM_DT2_B_OUTSWAP_S = 10 +const MCPWM_DT2_RED_INSEL_S = 11 +const MCPWM_DT2_FED_INSEL_S = 12 +const MCPWM_DT2_RED_OUTINVERT_S = 13 +const MCPWM_DT2_FED_OUTINVERT_S = 14 +const MCPWM_DT2_A_OUTBYPASS_S = 15 +const MCPWM_DT2_B_OUTBYPASS_S = 16 +const MCPWM_DT2_CLK_SEL_S = 17 +const MCPWM_DT2_FED_S = 0 +const MCPWM_DT2_RED_S = 0 +const MCPWM_CARRIER2_EN_S = 0 +const MCPWM_CARRIER2_PRESCALE_S = 1 +const MCPWM_CARRIER2_DUTY_S = 5 +const MCPWM_CARRIER2_OSHTWTH_S = 8 +const MCPWM_CARRIER2_OUT_INVERT_S = 12 +const MCPWM_CARRIER2_IN_INVERT_S = 13 +const MCPWM_FH2_SW_CBC_S = 0 +const MCPWM_FH2_F2_CBC_S = 1 +const MCPWM_FH2_F1_CBC_S = 2 +const MCPWM_FH2_F0_CBC_S = 3 +const MCPWM_FH2_SW_OST_S = 4 +const MCPWM_FH2_F2_OST_S = 5 +const MCPWM_FH2_F1_OST_S = 6 +const MCPWM_FH2_F0_OST_S = 7 +const MCPWM_FH2_A_CBC_D_S = 8 +const MCPWM_FH2_A_CBC_U_S = 10 +const MCPWM_FH2_A_OST_D_S = 12 +const MCPWM_FH2_A_OST_U_S = 14 +const MCPWM_FH2_B_CBC_D_S = 16 +const MCPWM_FH2_B_CBC_U_S = 18 +const MCPWM_FH2_B_OST_D_S = 20 +const MCPWM_FH2_B_OST_U_S = 22 +const MCPWM_FH2_CLR_OST_S = 0 +const MCPWM_FH2_CBCPULSE_S = 1 +const MCPWM_FH2_FORCE_CBC_S = 3 +const MCPWM_FH2_FORCE_OST_S = 4 +const MCPWM_FH2_CBC_ON_S = 0 +const MCPWM_FH2_OST_ON_S = 1 +const MCPWM_F0_EN_S = 0 +const MCPWM_F1_EN_S = 1 +const MCPWM_F2_EN_S = 2 +const MCPWM_F0_POLE_S = 3 +const MCPWM_F1_POLE_S = 4 +const MCPWM_F2_POLE_S = 5 +const MCPWM_EVENT_F0_S = 6 +const MCPWM_EVENT_F1_S = 7 +const MCPWM_EVENT_F2_S = 8 +const MCPWM_CAP_TIMER_EN_S = 0 +const MCPWM_CAP_SYNCI_EN_S = 1 +const MCPWM_CAP_SYNCI_SEL_S = 2 +const MCPWM_CAP_SYNC_SW_S = 5 +const MCPWM_CAP_TIMER_PHASE_S = 0 +const MCPWM_CAP0_EN_S = 0 +const MCPWM_CAP0_MODE_S = 1 +const MCPWM_CAP0_PRESCALE_S = 3 +const MCPWM_CAP0_IN_INVERT_S = 11 +const MCPWM_CAP0_SW_S = 12 +const MCPWM_CAP1_EN_S = 0 +const MCPWM_CAP1_MODE_S = 1 +const MCPWM_CAP1_PRESCALE_S = 3 +const MCPWM_CAP1_IN_INVERT_S = 11 +const MCPWM_CAP1_SW_S = 12 +const MCPWM_CAP2_EN_S = 0 +const MCPWM_CAP2_MODE_S = 1 +const MCPWM_CAP2_PRESCALE_S = 3 +const MCPWM_CAP2_IN_INVERT_S = 11 +const MCPWM_CAP2_SW_S = 12 +const MCPWM_CAP0_VALUE_S = 0 +const MCPWM_CAP1_VALUE_S = 0 +const MCPWM_CAP2_VALUE_S = 0 +const MCPWM_CAP0_EDGE_S = 0 +const MCPWM_CAP1_EDGE_S = 1 +const MCPWM_CAP2_EDGE_S = 2 +const MCPWM_GLOBAL_UP_EN_S = 0 +const MCPWM_GLOBAL_FORCE_UP_S = 1 +const MCPWM_OP0_UP_EN_S = 2 +const MCPWM_OP0_FORCE_UP_S = 3 +const MCPWM_OP1_UP_EN_S = 4 +const MCPWM_OP1_FORCE_UP_S = 5 +const MCPWM_OP2_UP_EN_S = 6 +const MCPWM_OP2_FORCE_UP_S = 7 +const MCPWM_TIMER0_STOP_INT_ENA_S = 0 +const MCPWM_TIMER1_STOP_INT_ENA_S = 1 +const MCPWM_TIMER2_STOP_INT_ENA_S = 2 +const MCPWM_TIMER0_TEZ_INT_ENA_S = 3 +const MCPWM_TIMER1_TEZ_INT_ENA_S = 4 +const MCPWM_TIMER2_TEZ_INT_ENA_S = 5 +const MCPWM_TIMER0_TEP_INT_ENA_S = 6 +const MCPWM_TIMER1_TEP_INT_ENA_S = 7 +const MCPWM_TIMER2_TEP_INT_ENA_S = 8 +const MCPWM_FAULT0_INT_ENA_S = 9 +const MCPWM_FAULT1_INT_ENA_S = 10 +const MCPWM_FAULT2_INT_ENA_S = 11 +const MCPWM_FAULT0_CLR_INT_ENA_S = 12 +const MCPWM_FAULT1_CLR_INT_ENA_S = 13 +const MCPWM_FAULT2_CLR_INT_ENA_S = 14 +const MCPWM_OP0_TEA_INT_ENA_S = 15 +const MCPWM_OP1_TEA_INT_ENA_S = 16 +const MCPWM_OP2_TEA_INT_ENA_S = 17 +const MCPWM_OP0_TEB_INT_ENA_S = 18 +const MCPWM_OP1_TEB_INT_ENA_S = 19 +const MCPWM_OP2_TEB_INT_ENA_S = 20 +const MCPWM_FH0_CBC_INT_ENA_S = 21 +const MCPWM_FH1_CBC_INT_ENA_S = 22 +const MCPWM_FH2_CBC_INT_ENA_S = 23 +const MCPWM_FH0_OST_INT_ENA_S = 24 +const MCPWM_FH1_OST_INT_ENA_S = 25 +const MCPWM_FH2_OST_INT_ENA_S = 26 +const MCPWM_CAP0_INT_ENA_S = 27 +const MCPWM_CAP1_INT_ENA_S = 28 +const MCPWM_CAP2_INT_ENA_S = 29 +const MCPWM_TIMER0_STOP_INT_RAW_S = 0 +const MCPWM_TIMER1_STOP_INT_RAW_S = 1 +const MCPWM_TIMER2_STOP_INT_RAW_S = 2 +const MCPWM_TIMER0_TEZ_INT_RAW_S = 3 +const MCPWM_TIMER1_TEZ_INT_RAW_S = 4 +const MCPWM_TIMER2_TEZ_INT_RAW_S = 5 +const MCPWM_TIMER0_TEP_INT_RAW_S = 6 +const MCPWM_TIMER1_TEP_INT_RAW_S = 7 +const MCPWM_TIMER2_TEP_INT_RAW_S = 8 +const MCPWM_FAULT0_INT_RAW_S = 9 +const MCPWM_FAULT1_INT_RAW_S = 10 +const MCPWM_FAULT2_INT_RAW_S = 11 +const MCPWM_FAULT0_CLR_INT_RAW_S = 12 +const MCPWM_FAULT1_CLR_INT_RAW_S = 13 +const MCPWM_FAULT2_CLR_INT_RAW_S = 14 +const MCPWM_OP0_TEA_INT_RAW_S = 15 +const MCPWM_OP1_TEA_INT_RAW_S = 16 +const MCPWM_OP2_TEA_INT_RAW_S = 17 +const MCPWM_OP0_TEB_INT_RAW_S = 18 +const MCPWM_OP1_TEB_INT_RAW_S = 19 +const MCPWM_OP2_TEB_INT_RAW_S = 20 +const MCPWM_FH0_CBC_INT_RAW_S = 21 +const MCPWM_FH1_CBC_INT_RAW_S = 22 +const MCPWM_FH2_CBC_INT_RAW_S = 23 +const MCPWM_FH0_OST_INT_RAW_S = 24 +const MCPWM_FH1_OST_INT_RAW_S = 25 +const MCPWM_FH2_OST_INT_RAW_S = 26 +const MCPWM_CAP0_INT_RAW_S = 27 +const MCPWM_CAP1_INT_RAW_S = 28 +const MCPWM_CAP2_INT_RAW_S = 29 +const MCPWM_TIMER0_STOP_INT_ST_S = 0 +const MCPWM_TIMER1_STOP_INT_ST_S = 1 +const MCPWM_TIMER2_STOP_INT_ST_S = 2 +const MCPWM_TIMER0_TEZ_INT_ST_S = 3 +const MCPWM_TIMER1_TEZ_INT_ST_S = 4 +const MCPWM_TIMER2_TEZ_INT_ST_S = 5 +const MCPWM_TIMER0_TEP_INT_ST_S = 6 +const MCPWM_TIMER1_TEP_INT_ST_S = 7 +const MCPWM_TIMER2_TEP_INT_ST_S = 8 +const MCPWM_FAULT0_INT_ST_S = 9 +const MCPWM_FAULT1_INT_ST_S = 10 +const MCPWM_FAULT2_INT_ST_S = 11 +const MCPWM_FAULT0_CLR_INT_ST_S = 12 +const MCPWM_FAULT1_CLR_INT_ST_S = 13 +const MCPWM_FAULT2_CLR_INT_ST_S = 14 +const MCPWM_OP0_TEA_INT_ST_S = 15 +const MCPWM_OP1_TEA_INT_ST_S = 16 +const MCPWM_OP2_TEA_INT_ST_S = 17 +const MCPWM_OP0_TEB_INT_ST_S = 18 +const MCPWM_OP1_TEB_INT_ST_S = 19 +const MCPWM_OP2_TEB_INT_ST_S = 20 +const MCPWM_FH0_CBC_INT_ST_S = 21 +const MCPWM_FH1_CBC_INT_ST_S = 22 +const MCPWM_FH2_CBC_INT_ST_S = 23 +const MCPWM_FH0_OST_INT_ST_S = 24 +const MCPWM_FH1_OST_INT_ST_S = 25 +const MCPWM_FH2_OST_INT_ST_S = 26 +const MCPWM_CAP0_INT_ST_S = 27 +const MCPWM_CAP1_INT_ST_S = 28 +const MCPWM_CAP2_INT_ST_S = 29 +const MCPWM_TIMER0_STOP_INT_CLR_S = 0 +const MCPWM_TIMER1_STOP_INT_CLR_S = 1 +const MCPWM_TIMER2_STOP_INT_CLR_S = 2 +const MCPWM_TIMER0_TEZ_INT_CLR_S = 3 +const MCPWM_TIMER1_TEZ_INT_CLR_S = 4 +const MCPWM_TIMER2_TEZ_INT_CLR_S = 5 +const MCPWM_TIMER0_TEP_INT_CLR_S = 6 +const MCPWM_TIMER1_TEP_INT_CLR_S = 7 +const MCPWM_TIMER2_TEP_INT_CLR_S = 8 +const MCPWM_FAULT0_INT_CLR_S = 9 +const MCPWM_FAULT1_INT_CLR_S = 10 +const MCPWM_FAULT2_INT_CLR_S = 11 +const MCPWM_FAULT0_CLR_INT_CLR_S = 12 +const MCPWM_FAULT1_CLR_INT_CLR_S = 13 +const MCPWM_FAULT2_CLR_INT_CLR_S = 14 +const MCPWM_OP0_TEA_INT_CLR_S = 15 +const MCPWM_OP1_TEA_INT_CLR_S = 16 +const MCPWM_OP2_TEA_INT_CLR_S = 17 +const MCPWM_OP0_TEB_INT_CLR_S = 18 +const MCPWM_OP1_TEB_INT_CLR_S = 19 +const MCPWM_OP2_TEB_INT_CLR_S = 20 +const MCPWM_FH0_CBC_INT_CLR_S = 21 +const MCPWM_FH1_CBC_INT_CLR_S = 22 +const MCPWM_FH2_CBC_INT_CLR_S = 23 +const MCPWM_FH0_OST_INT_CLR_S = 24 +const MCPWM_FH1_OST_INT_CLR_S = 25 +const MCPWM_FH2_OST_INT_CLR_S = 26 +const MCPWM_CAP0_INT_CLR_S = 27 +const MCPWM_CAP1_INT_CLR_S = 28 +const MCPWM_CAP2_INT_CLR_S = 29 +const MCPWM_CLK_EN_S = 0 +const MCPWM_DATE_S = 0 diff --git a/esp32/mcpwm_struct.go b/esp32/mcpwm_struct.go new file mode 100644 index 00000000..40d2df4c --- /dev/null +++ b/esp32/mcpwm_struct.go @@ -0,0 +1,315 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** Group: Prescaler configuration */ +/** Type of clk_cfg register + * PWM clock prescaler register. + */ + +type McpwmClkCfgRegT struct { + Val c.Uint32T +} + +/** Group: MCPWM Timer Configuration and status */ +/** Type of timer_cfg0 register + * PWM timer period and update method configuration register. + */ + +type McpwmTimerCfg0RegT struct { + Val c.Uint32T +} + +/** Type of timer_cfg1 register + * PWM timer working mode and start/stop control configuration register. + */ + +type McpwmTimerCfg1RegT struct { + Val c.Uint32T +} + +/** Type of timer_sync register + * PWM timer sync function configuration register. + */ + +type McpwmTimerSyncRegT struct { + Val c.Uint32T +} + +/** Type of timer_status register + * PWM timer status register. + */ + +type McpwmTimerStatusRegT struct { + Val c.Uint32T +} + +/** Group: Common configuration for MCPWM timers */ +/** Type of timer_synci_cfg register + * Synchronization input selection for three PWM timers. + */ + +type McpwmTimerSynciCfgRegT struct { + Val c.Uint32T +} + +/** Type of operator_timersel register + * Select specific timer for PWM operators. + */ + +type McpwmOperatorTimerselRegT struct { + Val c.Uint32T +} + +/** Group: MCPWM Operator Configuration and Status */ +/** Type of gen_stmp_cfg register + * Transfer status and update method for time stamp registers A and B + */ + +type McpwmGenStmpCfgRegT struct { + Val c.Uint32T +} + +/** Type of gen_tstmp register + * PWM generator shadow register for timer stamp + */ + +type McpwmGenTstmpRegT struct { + Val c.Uint32T +} + +/** Type of gen_cfg0 register + * PWM generator event T0 and T1 handling + */ + +type McpwmGenCfg0RegT struct { + Val c.Uint32T +} + +/** Type of gen_force register + * Permissives to force PWM0A and PWM0B outputs by software + */ + +type McpwmGenForceRegT struct { + Val c.Uint32T +} + +/** Type of generator register + * Actions triggered by events on PWM0A + */ + +type McpwmGenRegT struct { + Val c.Uint32T +} + +/** Type of dt_cfg register + * PWM generator dead time type selection and configuration + */ + +type McpwmDtCfgRegT struct { + Val c.Uint32T +} + +/** Type of dt_fed_cfg register + * PWM generator shadow register for falling edge delay (FED). + */ + +type McpwmDtFedCfgRegT struct { + Val c.Uint32T +} + +/** Type of dt_red_cfg register + * PWM generator shadow register for rising edge delay (RED). + */ + +type McpwmDtRedCfgRegT struct { + Val c.Uint32T +} + +/** Type of carrier_cfg register + * PWM generator carrier enable and configuration + */ + +type McpwmCarrierCfgRegT struct { + Val c.Uint32T +} + +/** Type of fh_cfg0 register + * Actions on PWM0A and PWM0B trip events + */ + +type McpwmFhCfg0RegT struct { + Val c.Uint32T +} + +/** Type of fh_cfg1 register + * Software triggers for fault handler actions + */ + +type McpwmFhCfg1RegT struct { + Val c.Uint32T +} + +/** Type of fh_status register + * Status of fault events. + */ + +type McpwmFhStatusRegT struct { + Val c.Uint32T +} + +/** Group: Fault Detection Configuration and Status */ +/** Type of fault_detect register + * Fault detection configuration and status + */ + +type McpwmFaultDetectRegT struct { + Val c.Uint32T +} + +/** Group: Capture Configuration and Status */ +/** Type of cap_timer_cfg register + * Configure capture timer + */ + +type McpwmCapTimerCfgRegT struct { + Val c.Uint32T +} + +/** Type of cap_timer_phase register + * Phase for capture timer sync + */ + +type McpwmCapTimerPhaseRegT struct { + Val c.Uint32T +} + +/** Type of cap_chn_cfg register + * Capture channel 0 configuration and enable + */ + +type McpwmCapChnCfgRegT struct { + Val c.Uint32T +} + +/** Type of cap_chn register + * chn capture value status register + */ + +type McpwmCapChnRegT struct { + Val c.Uint32T +} + +/** Type of cap_status register + * Edge of last capture trigger + */ + +type McpwmCapStatusRegT struct { + Val c.Uint32T +} + +/** Group: Enable update of active registers */ +/** Type of update_cfg register + * Enable update. + */ + +type McpwmUpdateCfgRegT struct { + Val c.Uint32T +} + +/** Group: Manage Interrupts */ +/** Type of int_ena register + * Interrupt enable bits + */ + +type McpwmIntEnaRegT struct { + Val c.Uint32T +} + +/** Type of int_raw register + * Raw interrupt status + */ + +type McpwmIntRawRegT struct { + Val c.Uint32T +} + +/** Type of int_st register + * Masked interrupt status + */ + +type McpwmIntStRegT struct { + Val c.Uint32T +} + +/** Type of int_clr register + * Interrupt clear bits + */ + +type McpwmIntClrRegT struct { + Val c.Uint32T +} + +/** Group: MCMCPWM APB configuration register */ +/** Type of clk register + * MCPWM APB configuration register + */ + +type McpwmClkRegT struct { + Val c.Uint32T +} + +/** Group: Version Register */ +/** Type of version register + * Version register. + */ + +type McpwmVersionRegT struct { + Val c.Uint32T +} + +type McpwmTimerRegsT struct { + TimerCfg0 McpwmTimerCfg0RegT + TimerCfg1 McpwmTimerCfg1RegT + TimerSync McpwmTimerSyncRegT + TimerStatus McpwmTimerStatusRegT +} + +type McpwmOperatorRegT struct { + GenStmpCfg McpwmGenStmpCfgRegT + Timestamp [2]McpwmGenTstmpRegT + GenCfg0 McpwmGenCfg0RegT + GenForce McpwmGenForceRegT + Generator [2]McpwmGenRegT + DtCfg McpwmDtCfgRegT + DtFedCfg McpwmDtFedCfgRegT + DtRedCfg McpwmDtRedCfgRegT + CarrierCfg McpwmCarrierCfgRegT + FhCfg0 McpwmFhCfg0RegT + FhCfg1 McpwmFhCfg1RegT + FhStatus McpwmFhStatusRegT +} + +type McpwmDevT struct { + ClkCfg McpwmClkCfgRegT + Timer [3]McpwmTimerRegsT + TimerSynciCfg McpwmTimerSynciCfgRegT + OperatorTimersel McpwmOperatorTimerselRegT + Operators [3]McpwmOperatorRegT + FaultDetect McpwmFaultDetectRegT + CapTimerCfg McpwmCapTimerCfgRegT + CapTimerPhase McpwmCapTimerPhaseRegT + CapChnCfg [3]McpwmCapChnCfgRegT + CapChn [3]McpwmCapChnRegT + CapStatus McpwmCapStatusRegT + UpdateCfg McpwmUpdateCfgRegT + IntEna McpwmIntEnaRegT + IntRaw McpwmIntRawRegT + IntSt McpwmIntStRegT + IntClr McpwmIntClrRegT + Clk McpwmClkRegT + Version McpwmVersionRegT +} diff --git a/esp32/mcpwm_types.go b/esp32/mcpwm_types.go new file mode 100644 index 00000000..d0d87fe5 --- /dev/null +++ b/esp32/mcpwm_types.go @@ -0,0 +1,74 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type McpwmTimerClockSourceT SocPeriphMcpwmTimerClkSrcT +type McpwmCaptureClockSourceT SocPeriphMcpwmCaptureClkSrcT +type McpwmCarrierClockSourceT SocPeriphMcpwmCarrierClkSrcT +type McpwmTimerDirectionT c.Int + +const ( + MCPWM_TIMER_DIRECTION_UP McpwmTimerDirectionT = 0 + MCPWM_TIMER_DIRECTION_DOWN McpwmTimerDirectionT = 1 +) + +type McpwmTimerEventT c.Int + +const ( + MCPWM_TIMER_EVENT_EMPTY McpwmTimerEventT = 0 + MCPWM_TIMER_EVENT_FULL McpwmTimerEventT = 1 + MCPWM_TIMER_EVENT_INVALID McpwmTimerEventT = 2 +) + +type McpwmTimerCountModeT c.Int + +const ( + MCPWM_TIMER_COUNT_MODE_PAUSE McpwmTimerCountModeT = 0 + MCPWM_TIMER_COUNT_MODE_UP McpwmTimerCountModeT = 1 + MCPWM_TIMER_COUNT_MODE_DOWN McpwmTimerCountModeT = 2 + MCPWM_TIMER_COUNT_MODE_UP_DOWN McpwmTimerCountModeT = 3 +) + +type McpwmTimerStartStopCmdT c.Int + +const ( + MCPWM_TIMER_STOP_EMPTY McpwmTimerStartStopCmdT = 0 + MCPWM_TIMER_STOP_FULL McpwmTimerStartStopCmdT = 1 + MCPWM_TIMER_START_NO_STOP McpwmTimerStartStopCmdT = 2 + MCPWM_TIMER_START_STOP_EMPTY McpwmTimerStartStopCmdT = 3 + MCPWM_TIMER_START_STOP_FULL McpwmTimerStartStopCmdT = 4 +) + +type McpwmGeneratorActionT c.Int + +const ( + MCPWM_GEN_ACTION_KEEP McpwmGeneratorActionT = 0 + MCPWM_GEN_ACTION_LOW McpwmGeneratorActionT = 1 + MCPWM_GEN_ACTION_HIGH McpwmGeneratorActionT = 2 + MCPWM_GEN_ACTION_TOGGLE McpwmGeneratorActionT = 3 +) + +type McpwmOperatorBrakeModeT c.Int + +const ( + MCPWM_OPER_BRAKE_MODE_CBC McpwmOperatorBrakeModeT = 0 + MCPWM_OPER_BRAKE_MODE_OST McpwmOperatorBrakeModeT = 1 + MCPWM_OPER_BRAKE_MODE_INVALID McpwmOperatorBrakeModeT = 2 +) + +type McpwmCaptureEdgeT c.Int + +const ( + MCPWM_CAP_EDGE_POS McpwmCaptureEdgeT = 0 + MCPWM_CAP_EDGE_NEG McpwmCaptureEdgeT = 1 +) + +type McpwmComparatorEtmEventTypeT c.Int + +const ( + MCPWM_CMPR_ETM_EVENT_EQUAL McpwmComparatorEtmEventTypeT = 0 + MCPWM_CMPR_ETM_EVENT_MAX McpwmComparatorEtmEventTypeT = 1 +) diff --git a/esp32/memprot.go b/esp32/memprot.go new file mode 100644 index 00000000..3fbdaa24 --- /dev/null +++ b/esp32/memprot.go @@ -0,0 +1,658 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type MemTypeProtT c.Int + +const ( + MEMPROT_NONE MemTypeProtT = 0 + MEMPROT_IRAM0_SRAM MemTypeProtT = 1 + MEMPROT_DRAM0_SRAM MemTypeProtT = 2 + MEMPROT_IRAM0_RTCFAST MemTypeProtT = 4 + MEMPROT_DRAM0_RTCFAST MemTypeProtT = 8 + MEMPROT_PERI1_RTCSLOW MemTypeProtT = 16 + MEMPROT_PERI2_RTCSLOW_0 MemTypeProtT = 32 + MEMPROT_PERI2_RTCSLOW_1 MemTypeProtT = 64 + MEMPROT_ALL MemTypeProtT = -1 +) + +/** + * @brief Returns splitting address for required memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * + * @return Splitting address for the memory region required. + * The address is given by region-specific global symbol exported from linker script, + * it is not read out from related configuration register. + */ +// llgo:link MemTypeProtT.EspMemprotGetSplitAddr C.esp_memprot_get_split_addr +func (recv_ MemTypeProtT) EspMemprotGetSplitAddr() *c.Uint32T { + return nil +} + +/** + * @brief Initializes illegal memory access control for required memory section. + * + * All memory access interrupts share ETS_MEMACCESS_ERR_INUM input channel, it is caller's + * responsibility to properly detect actual intr. source as well as possible prioritization in case + * of multiple source reported during one intr.handling routine run + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum)\ + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotIntrInit C.esp_memprot_intr_init +func (recv_ MemTypeProtT) EspMemprotIntrInit() EspErrT { + return 0 +} + +/** + * @brief Enable/disable the memory protection interrupt + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param enable enable/disable + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotIntrEna C.esp_memprot_intr_ena +func (recv_ MemTypeProtT) EspMemprotIntrEna(enable bool) EspErrT { + return 0 +} + +/** + * @brief Sets a request for clearing interrupt-on flag for specified memory region (register write) + * + * @note When called without actual interrupt-on flag set, subsequent occurrence of related interrupt is ignored. + * Should be used only after the real interrupt appears, typically as the last step in interrupt handler's routine. + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotClearIntr C.esp_memprot_clear_intr +func (recv_ MemTypeProtT) EspMemprotClearIntr() EspErrT { + return 0 +} + +/** + * @brief Detects which memory protection interrupt is active + * + * @note Check order + * MEMPROT_IRAM0_SRAM + * MEMPROT_IRAM0_RTCFAST + * MEMPROT_DRAM0_SRAM + * MEMPROT_DRAM0_RTCFAST + * + * @return Memory protection area type (see mem_type_prot_t enum) + */ +//go:linkname EspMemprotGetActiveIntrMemtype C.esp_memprot_get_active_intr_memtype +func EspMemprotGetActiveIntrMemtype() MemTypeProtT + +/** + * @brief Gets interrupt status register contents for specified memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param fault_reg_val Contents of status register + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetFaultReg C.esp_memprot_get_fault_reg +func (recv_ MemTypeProtT) EspMemprotGetFaultReg(fault_reg_val *c.Uint32T) EspErrT { + return 0 +} + +/** + * @brief Get details of given interrupt status + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param faulting_address Faulting address causing the interrupt [out] + * @param op_type Operation being processed at the faulting address [out] + * IRAM0: 0 - read, 1 - write + * DRAM0: 0 - read, 1 - write + * @param op_subtype Additional info for op_type [out] + * IRAM0: 0 - instruction segment access, 1 - data segment access + * DRAM0: 0 - non-atomic operation, 1 - atomic operation + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetFaultStatus C.esp_memprot_get_fault_status +func (recv_ MemTypeProtT) EspMemprotGetFaultStatus(faulting_address **c.Uint32T, op_type *c.Uint32T, op_subtype *c.Uint32T) EspErrT { + return 0 +} + +/** + * @brief Gets string representation of required memory region identifier + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * + * @return mem_type as string + */ +// llgo:link MemTypeProtT.EspMemprotTypeToStr C.esp_memprot_type_to_str +func (recv_ MemTypeProtT) EspMemprotTypeToStr() *c.Char { + return nil +} + +/** + * @brief Detects whether any of the interrupt locks is active (requires digital system reset to unlock) + * + * @return true/false + */ +//go:linkname EspMemprotIsLockedAny C.esp_memprot_is_locked_any +func EspMemprotIsLockedAny() bool + +/** + * @brief Sets lock for specified memory region. + * + * Locks can be unlocked only by digital system reset + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotSetLock C.esp_memprot_set_lock +func (recv_ MemTypeProtT) EspMemprotSetLock() EspErrT { + return 0 +} + +/** + * @brief Gets lock status for required memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param locked Settings locked: true/false (locked/unlocked) + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetLock C.esp_memprot_get_lock +func (recv_ MemTypeProtT) EspMemprotGetLock(locked *bool) EspErrT { + return 0 +} + +/** + * @brief Gets permission control configuration register contents for required memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param conf_reg_val Permission control register contents + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetConfReg C.esp_memprot_get_conf_reg +func (recv_ MemTypeProtT) EspMemprotGetConfReg(conf_reg_val *c.Uint32T) EspErrT { + return 0 +} + +/** + * @brief Gets interrupt permission settings for unified management block + * + * Gets interrupt permission settings register contents for required memory region, returns settings for unified management blocks + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param perm_reg Permission settings register contents + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetPermUniReg C.esp_memprot_get_perm_uni_reg +func (recv_ MemTypeProtT) EspMemprotGetPermUniReg(perm_reg *c.Uint32T) EspErrT { + return 0 +} + +/** + * @brief Gets interrupt permission settings for split management block + * + * Gets interrupt permission settings register contents for required memory region (unified management blocks) + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @return split_reg Unified management settings register contents + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetPermSplitReg C.esp_memprot_get_perm_split_reg +func (recv_ MemTypeProtT) EspMemprotGetPermSplitReg(split_reg *c.Uint32T) EspErrT { + return 0 +} + +/** + * @brief Detects whether any of the memory protection interrupts is enabled + * + * @return true/false + */ +//go:linkname EspMemprotIsIntrEnaAny C.esp_memprot_is_intr_ena_any +func EspMemprotIsIntrEnaAny() bool + +/** + * @brief Gets interrupt-enabled flag for given memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param enable_bit Interrupt-enabled flag + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetIntrEnaBit C.esp_memprot_get_intr_ena_bit +func (recv_ MemTypeProtT) EspMemprotGetIntrEnaBit(enable_bit *c.Uint32T) EspErrT { + return 0 +} + +/** + * @brief Gets interrupt-active flag for given memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param intr_on_bit Interrupt-active flag + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure */ +// llgo:link MemTypeProtT.EspMemprotGetIntrOnBit C.esp_memprot_get_intr_on_bit +func (recv_ MemTypeProtT) EspMemprotGetIntrOnBit(intr_on_bit *c.Uint32T) EspErrT { + return 0 +} + +/** + * @brief Gets interrupt-clear request flag for given memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param clear_bit Interrupt-clear request flag + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetIntrClrBit C.esp_memprot_get_intr_clr_bit +func (recv_ MemTypeProtT) EspMemprotGetIntrClrBit(clear_bit *c.Uint32T) EspErrT { + return 0 +} + +/** + * @brief Gets read permission value for specified block and memory region + * + * Returns read permission bit value for required unified-management block (0-3) in given memory region. + * Applicable to all memory types. + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param block Memory block identifier (0-3) + * @param read_bit Read permission value for required block + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetUniBlockReadBit C.esp_memprot_get_uni_block_read_bit +func (recv_ MemTypeProtT) EspMemprotGetUniBlockReadBit(block c.Uint32T, read_bit *c.Uint32T) EspErrT { + return 0 +} + +/** + * @brief Gets write permission value for specified block and memory region + * + * Returns write permission bit value for required unified-management block (0-3) in given memory region. + * Applicable to all memory types. + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param block Memory block identifier (0-3) + * @param write_bit Write permission value for required block + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetUniBlockWriteBit C.esp_memprot_get_uni_block_write_bit +func (recv_ MemTypeProtT) EspMemprotGetUniBlockWriteBit(block c.Uint32T, write_bit *c.Uint32T) EspErrT { + return 0 +} + +/** + * @brief Gets execute permission value for specified block and memory region + * + * Returns execute permission bit value for required unified-management block (0-3) in given memory region. + * Applicable only to IRAM memory types + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param block Memory block identifier (0-3) + * @param exec_bit Execute permission value for required block + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetUniBlockExecBit C.esp_memprot_get_uni_block_exec_bit +func (recv_ MemTypeProtT) EspMemprotGetUniBlockExecBit(block c.Uint32T, exec_bit *c.Uint32T) EspErrT { + return 0 +} + +/** + * @brief Sets permissions for specified block in DRAM region + * + * Sets Read and Write permission for specified unified-management block (0-3) in given memory region. + * Applicable only to DRAM memory types + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param block Memory block identifier (0-3) + * @param write_perm Write permission flag + * @param read_perm Read permission flag + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotSetUniBlockPermDram C.esp_memprot_set_uni_block_perm_dram +func (recv_ MemTypeProtT) EspMemprotSetUniBlockPermDram(block c.Uint32T, write_perm bool, read_perm bool) EspErrT { + return 0 +} + +/** + * @brief Sets permissions for high and low memory segment in DRAM region + * + * Sets Read and Write permission for both low and high memory segments given by splitting address. + * The splitting address must be equal to or higher then beginning of block 5 + * Applicable only to DRAM memory types + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param split_addr Address to split the memory region to lower and higher segment + * @param lw Low segment Write permission flag + * @param lr Low segment Read permission flag + * @param hw High segment Write permission flag + * @param hr High segment Read permission flag + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotSetProtDram C.esp_memprot_set_prot_dram +func (recv_ MemTypeProtT) EspMemprotSetProtDram(split_addr *c.Uint32T, lw bool, lr bool, hw bool, hr bool) EspErrT { + return 0 +} + +/** + * @brief Sets permissions for specified block in IRAM region + * + * Sets Read, Write and Execute permission for specified unified-management block (0-3) in given memory region. + * Applicable only to IRAM memory types + * + * @param mem_type Memory protection area type (MEMPROT_IRAM0_SRAM) + * @param block Memory block identifier (0-3) + * @param write_perm Write permission flag + * @param read_perm Read permission flag + * @param exec_perm Execute permission flag + * + * @return ESP_OK on success + * ESP_ERR_NOT_SUPPORTED on invalid mem_type + * ESP_ERR_INVALID_ARG on incorrect block number + */ +// llgo:link MemTypeProtT.EspMemprotSetUniBlockPermIram C.esp_memprot_set_uni_block_perm_iram +func (recv_ MemTypeProtT) EspMemprotSetUniBlockPermIram(block c.Uint32T, write_perm bool, read_perm bool, exec_perm bool) EspErrT { + return 0 +} + +/** + * @brief Sets permissions for high and low memory segment in IRAM region + * + * Sets Read, Write and Execute permission for both low and high memory segments given by splitting address. + * The splitting address must be equal to or higher then beginning of block 5 + * Applicable only to IRAM memory types + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param split_addr Address to split the memory region to lower and higher segment + * @param lw Low segment Write permission flag + * @param lr Low segment Read permission flag + * @param lx Low segment Execute permission flag + * @param hw High segment Write permission flag + * @param hr High segment Read permission flag + * @param hx High segment Execute permission flag + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotSetProtIram C.esp_memprot_set_prot_iram +func (recv_ MemTypeProtT) EspMemprotSetProtIram(split_addr *c.Uint32T, lw bool, lr bool, lx bool, hw bool, hr bool, hx bool) EspErrT { + return 0 +} + +/** + * @brief Activates memory protection for all supported memory region types + * + * @note The feature is disabled when JTAG interface is connected + * + * @param invoke_panic_handler map mem.prot interrupt to ETS_MEMACCESS_ERR_INUM and thus invokes panic handler when fired ('true' not suitable for testing) + * @param lock_feature sets LOCK bit, see esp_memprot_set_lock() ('true' not suitable for testing) + * @param mem_type_mask holds a set of required memory protection types (bitmask built of mem_type_prot_t). NULL means default (MEMPROT_ALL in this version) + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +//go:linkname EspMemprotSetProt C.esp_memprot_set_prot +func EspMemprotSetProt(invoke_panic_handler bool, lock_feature bool, mem_type_mask *c.Uint32T) EspErrT + +/** + * @brief Get permission settings bits for IRAM0 split mgmt. Only IRAM0 memory types allowed + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lw Low segment Write permission flag + * @param lr Low segment Read permission flag + * @param lx Low segment Execute permission flag + * @param hw High segment Write permission flag + * @param hr High segment Read permission flag + * @param hx High segment Execute permission flag + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetPermSplitBitsIram C.esp_memprot_get_perm_split_bits_iram +func (recv_ MemTypeProtT) EspMemprotGetPermSplitBitsIram(lw *bool, lr *bool, lx *bool, hw *bool, hr *bool, hx *bool) EspErrT { + return 0 +} + +/** + * @brief Get permission settings bits for DRAM0 split mgmt. Only DRAM0 memory types allowed + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lw Low segment Write permission flag + * @param lr Low segment Read permission flag + * @param hw High segment Write permission flag + * @param hr High segment Read permission flag + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetPermSplitBitsDram C.esp_memprot_get_perm_split_bits_dram +func (recv_ MemTypeProtT) EspMemprotGetPermSplitBitsDram(lw *bool, lr *bool, hw *bool, hr *bool) EspErrT { + return 0 +} + +/** + * @brief Sets permissions for high and low memory segment in PERIBUS1 region + * + * Sets Read and Write permission for both low and high memory segments given by splitting address. + * Applicable only to PERIBUS1 memory types + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param split_addr Address to split the memory region to lower and higher segment + * @param lw Low segment Write permission flag + * @param lr Low segment Read permission flag + * @param hw High segment Write permission flag + * @param hr High segment Read permission flag + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotSetProtPeri1 C.esp_memprot_set_prot_peri1 +func (recv_ MemTypeProtT) EspMemprotSetProtPeri1(split_addr *c.Uint32T, lw bool, lr bool, hw bool, hr bool) EspErrT { + return 0 +} + +/** + * @brief Get permission settings bits for PERIBUS1 split mgmt. Only PERIBUS1 memory types allowed + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lw Low segment Write permission flag + * @param lr Low segment Read permission flag + * @param hw High segment Write permission flag + * @param hr High segment Read permission flag + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetPermSplitBitsPeri1 C.esp_memprot_get_perm_split_bits_peri1 +func (recv_ MemTypeProtT) EspMemprotGetPermSplitBitsPeri1(lw *bool, lr *bool, hw *bool, hr *bool) EspErrT { + return 0 +} + +/** + * @brief Get permission settings bits for PERIBUS2 split mgmt. Only PERIBUS2 memory types allowed + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lw Low segment Write permission flag + * @param lr Low segment Read permission flag + * @param lx Low segment Execute permission flag + * @param hw High segment Write permission flag + * @param hr High segment Read permission flag + * @param hx High segment Execute permission flag + * + * @return ESP_OK on success, ESP_ERR_INVALID_ARG on failure + */ +// llgo:link MemTypeProtT.EspMemprotGetPermSplitBitsPeri2 C.esp_memprot_get_perm_split_bits_peri2 +func (recv_ MemTypeProtT) EspMemprotGetPermSplitBitsPeri2(lw *bool, lr *bool, lx *bool, hw *bool, hr *bool, hx *bool) EspErrT { + return 0 +} + +/** + * @brief Configures the memory protection for high and low segment in PERIBUS2 region + * + * Sets Read Write permission for both low and high memory segments given by splitting address. + * Applicable only to PERIBUS2 memory types + * + * @param mem_type Memory protection area type (MEMPROT_PERI2_RTCSLOW_0, MEMPROT_PERI2_RTCSLOW_1) + * @param split_addr Address to split the memory region to lower and higher segment (32bit aligned) + * @param lw Low segment Write permission flag + * @param lr Low segment Read permission flag + * @param lx Low segment Execute permission flag + * @param hw High segment Write permission flag + * @param hr High segment Read permission flag + * @param hx High segment Execute permission flag + * + * @return ESP_OK on success + * ESP_ERR_NOT_SUPPORTED on invalid mem_type + * ESP_ERR_INVALID_STATE on splitting address out of PERIBUS2 range + * ESP_ERR_INVALID_SIZE on splitting address not 32-bit aligned + */ +// llgo:link MemTypeProtT.EspMemprotSetProtPeri2 C.esp_memprot_set_prot_peri2 +func (recv_ MemTypeProtT) EspMemprotSetProtPeri2(split_addr *c.Uint32T, lw bool, lr bool, lx bool, hw bool, hr bool, hx bool) EspErrT { + return 0 +} + +/** + * @brief Get permissions for specified memory type. Irrelevant bits are ignored + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lw Low segment Write permission flag + * @param lr Low segment Read permission flag + * @param lx Low segment Execute permission flag + * @param hw High segment Write permission flag + * @param hr High segment Read permission flag + * @param hx High segment Execute permission flag + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG on NULL lw/lr/lx/hw/hr/hx args + * ESP_ERR_NOT_SUPPORTED on invalid mem_type + */ +// llgo:link MemTypeProtT.EspMemprotGetPermissions C.esp_memprot_get_permissions +func (recv_ MemTypeProtT) EspMemprotGetPermissions(lw *bool, lr *bool, lx *bool, hw *bool, hr *bool, hx *bool) EspErrT { + return 0 +} + +/** + * @brief Get Read permission settings for low and high regions of given memory type + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lr Low segment Read permission flag + * @param hr High segment Read permission flag + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG on NULL lr/hr args + * ESP_ERR_NOT_SUPPORTED on invalid mem_type + */ +// llgo:link MemTypeProtT.EspMemprotGetPermRead C.esp_memprot_get_perm_read +func (recv_ MemTypeProtT) EspMemprotGetPermRead(lr *bool, hr *bool) EspErrT { + return 0 +} + +/** + * @brief Get Write permission settings for low and high regions of given memory type + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lr Low segment Write permission flag + * @param hr High segment Write permission flag + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG on NULL lw/hw args + * ESP_ERR_NOT_SUPPORTED on invalid mem_type + */ +// llgo:link MemTypeProtT.EspMemprotGetPermWrite C.esp_memprot_get_perm_write +func (recv_ MemTypeProtT) EspMemprotGetPermWrite(lw *bool, hw *bool) EspErrT { + return 0 +} + +/** + * @brief Get Execute permission settings for low and high regions of given memory type + * Applicable only to IBUS-compatible memory types + * + * @param mem_type Memory protection area type (MEMPROT_IRAM0_SRAM, MEMPROT_IRAM0_RTCFAST, MEMPROT_PERI2_RTCSLOW_0, MEMPROT_PERI2_RTCSLOW_1) + * @param lx Low segment Exec permission flag + * @param hx High segment Exec permission flag + * + * @return ESP_OK on success + * ESP_ERR_INVALID_ARG on NULL lx/hx args + * ESP_ERR_NOT_SUPPORTED on invalid mem_type + */ +// llgo:link MemTypeProtT.EspMemprotGetPermExec C.esp_memprot_get_perm_exec +func (recv_ MemTypeProtT) EspMemprotGetPermExec(lx *bool, hx *bool) EspErrT { + return 0 +} + +/** + * @brief Returns the lowest address in required memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * + * @return Required address or MEMPROT_INVALID_ADDRESS for invalid mem_type + */ +// llgo:link MemTypeProtT.EspMemprotGetLowLimit C.esp_memprot_get_low_limit +func (recv_ MemTypeProtT) EspMemprotGetLowLimit() c.Uint32T { + return 0 +} + +/** + * @brief Returns the highest address in required memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * + * @return Required address or MEMPROT_INVALID_ADDRESS for invalid mem_type + */ +// llgo:link MemTypeProtT.EspMemprotGetHighLimit C.esp_memprot_get_high_limit +func (recv_ MemTypeProtT) EspMemprotGetHighLimit() c.Uint32T { + return 0 +} + +/** + * @brief Sets READ permission bit for required memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lr Low segment Read permission flag + * @param hr High segment Read permission flag + * + * @return ESP_OK on success + * ESP_ERR_NOT_SUPPORTED on invalid mem_type + */ +// llgo:link MemTypeProtT.EspMemprotSetReadPerm C.esp_memprot_set_read_perm +func (recv_ MemTypeProtT) EspMemprotSetReadPerm(lr bool, hr bool) EspErrT { + return 0 +} + +/** + * @brief Sets WRITE permission bit for required memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lr Low segment Write permission flag + * @param hr High segment Write permission flag + * + * @return ESP_OK on success + * ESP_ERR_NOT_SUPPORTED on invalid mem_type + */ +// llgo:link MemTypeProtT.EspMemprotSetWritePerm C.esp_memprot_set_write_perm +func (recv_ MemTypeProtT) EspMemprotSetWritePerm(lw bool, hw bool) EspErrT { + return 0 +} + +/** + * @brief Sets EXECUTE permission bit for required memory region + * + * @param mem_type Memory protection area type (MEMPROT_IRAM0_SRAM, MEMPROT_IRAM0_RTCFAST, MEMPROT_PERI2_RTCSLOW_0, MEMPROT_PERI2_RTCSLOW_1) + * @param lr Low segment Exec permission flag + * @param hr High segment Exec permission flag + * + * @return ESP_OK on success + * ESP_ERR_NOT_SUPPORTED on invalid mem_type + */ +// llgo:link MemTypeProtT.EspMemprotSetExecPerm C.esp_memprot_set_exec_perm +func (recv_ MemTypeProtT) EspMemprotSetExecPerm(lx bool, hx bool) EspErrT { + return 0 +} diff --git a/esp32/memprot_defs.go b/esp32/memprot_defs.go new file mode 100644 index 00000000..d8c137e0 --- /dev/null +++ b/esp32/memprot_defs.go @@ -0,0 +1,39 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const I_D_SRAM_SEGMENT_SIZE = 0x10000 +const I_D_SPLIT_LINE_ALIGN = 0x100 +const I_D_SPLIT_LINE_SHIFT = 0x8 +const I_FAULT_ADDR_SHIFT = 0x2 +const D_FAULT_ADDR_SHIFT = 0x4 +const IRAM0_VIOLATE_STATUS_ADDR_OFFSET = 0x40000000 +const DRAM0_VIOLATE_STATUS_ADDR_OFFSET = 0x3C000000 +const SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_R = 0x1 +const SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_W = 0x2 +const SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_F = 0x4 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R = 0x1 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W = 0x2 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F = 0x4 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R = 0x1 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W = 0x2 +const SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W = 0x1 +const SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R = 0x2 +const SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F = 0x4 + +/* + * PMS register configuration structure for I/D splitting address. + * Category bits define the splitting address being below, inside or above specific memory level range: + * - for details of ESP32S3 memory layout, see 725_mem_map.* documents + * - for category bits settings, see MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS* + * (components/hal/include/hal/memprot_types.h) + * - for details on assembling full splitting address + * see function memprot_ll_get_split_addr_from_reg() (components/hal/esp32s3/include/hal/memprot_ll.h) + */ + +type ConstrainRegFieldsT struct { + Val c.Uint32T +} diff --git a/esp32/memprot_ll.go b/esp32/memprot_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/memprot_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/memprot_types.go b/esp32/memprot_types.go new file mode 100644 index 00000000..4c9bf3f5 --- /dev/null +++ b/esp32/memprot_types.go @@ -0,0 +1,40 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_BELOW_SA = 0x0 +const MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA = 0x2 +const MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA = 0x3 + +type MemprotHalErrT c.Int + +const ( + MEMP_HAL_OK MemprotHalErrT = 0 + MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE MemprotHalErrT = 2 + MEMP_HAL_ERR_SPLIT_ADDR_INVALID MemprotHalErrT = 2 + MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED MemprotHalErrT = 3 + MEMP_HAL_ERR_UNI_BLOCK_INVALID MemprotHalErrT = 4 + MEMP_HAL_ERR_AREA_INVALID MemprotHalErrT = 5 + MEMP_HAL_ERR_WORLD_INVALID MemprotHalErrT = 6 + MEMP_HAL_ERR_CORE_INVALID MemprotHalErrT = 7 + MEMP_HAL_FAIL MemprotHalErrT = -1 +) + +type MemprotHalWorldT c.Int + +const ( + MEMP_HAL_WORLD_NONE MemprotHalWorldT = 0 + MEMP_HAL_WORLD_0 MemprotHalWorldT = 1 + MEMP_HAL_WORLD_1 MemprotHalWorldT = 16 +) + +type MemprotHalAreaT c.Int + +const ( + MEMP_HAL_AREA_NONE MemprotHalAreaT = 0 + MEMP_HAL_AREA_LOW MemprotHalAreaT = 1 + MEMP_HAL_AREA_HIGH MemprotHalAreaT = 2 +) diff --git a/esp32/message_buffer.go b/esp32/message_buffer.go new file mode 100644 index 00000000..72ee83f1 --- /dev/null +++ b/esp32/message_buffer.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +type MessageBufferHandleT StreamBufferHandleT diff --git a/esp32/miniz.go b/esp32/miniz.go new file mode 100644 index 00000000..5945fd13 --- /dev/null +++ b/esp32/miniz.go @@ -0,0 +1,320 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const MINIZ_X86_OR_X64_CPU = 0 +const MINIZ_LITTLE_ENDIAN = 1 +const MINIZ_USE_UNALIGNED_LOADS_AND_STORES = 0 +const MINIZ_HAS_64BIT_REGISTERS = 0 +const TINFL_USE_64BIT_BITBUF = 0 +const MZ_DEFLATED = 8 +const TINFL_LZ_DICT_SIZE = 32768 +const TDEFL_LESS_MEMORY = 1 + +type MzUlong c.Ulong + +// mz_free() internally uses the MZ_FREE() macro (which by default calls free() unless you've modified the MZ_MALLOC macro) to release a block allocated from the heap. +// +//go:linkname MzFree C.mz_free +func MzFree(p c.Pointer) + +// mz_adler32() returns the initial adler-32 value to use when called with ptr==NULL. +// llgo:link MzUlong.MzAdler32 C.mz_adler32 +func (recv_ MzUlong) MzAdler32(ptr *c.Char, buf_len c.SizeT) MzUlong { + return 0 +} + +// mz_crc32() returns the initial CRC-32 value to use when called with ptr==NULL. +// llgo:link MzUlong.MzCrc32 C.mz_crc32 +func (recv_ MzUlong) MzCrc32(ptr *c.Char, buf_len c.SizeT) MzUlong { + return 0 +} + +const ( + MZ_DEFAULT_STRATEGY c.Int = 0 + MZ_FILTERED c.Int = 1 + MZ_HUFFMAN_ONLY c.Int = 2 + MZ_RLE c.Int = 3 + MZ_FIXED c.Int = 4 +) + +type MzUint8 c.Char +type MzInt16 int16 +type MzUint16 uint16 +type MzUint32 c.Uint +type MzUint c.Uint +type MzInt64 c.LongLong +type MzUint64 c.UlongLong +type MzBool c.Int + +const ( + TINFL_FLAG_PARSE_ZLIB_HEADER c.Int = 1 + TINFL_FLAG_HAS_MORE_INPUT c.Int = 2 + TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF c.Int = 4 + TINFL_FLAG_COMPUTE_ADLER32 c.Int = 8 +) + +// High level decompression functions: +// tinfl_decompress_mem_to_heap() decompresses a block in memory to a heap block allocated via malloc(). +// On entry: +// +// pSrc_buf, src_buf_len: Pointer and size of the Deflate or zlib source data to decompress. +// +// On return: +// +// Function returns a pointer to the decompressed data, or NULL on failure. +// *pOut_len will be set to the decompressed data's size, which could be larger than src_buf_len on uncompressible data. +// The caller must call mz_free() on the returned block when it's no longer needed. +// +//go:linkname TinflDecompressMemToHeap C.tinfl_decompress_mem_to_heap +func TinflDecompressMemToHeap(pSrc_buf c.Pointer, src_buf_len c.SizeT, pOut_len *c.SizeT, flags c.Int) c.Pointer + +//go:linkname TinflDecompressMemToMem C.tinfl_decompress_mem_to_mem +func TinflDecompressMemToMem(pOut_buf c.Pointer, out_buf_len c.SizeT, pSrc_buf c.Pointer, src_buf_len c.SizeT, flags c.Int) c.SizeT + +// llgo:type C +type TinflPutBufFuncPtr func(c.Pointer, c.Int, c.Pointer) c.Int + +//go:linkname TinflDecompressMemToCallback C.tinfl_decompress_mem_to_callback +func TinflDecompressMemToCallback(pIn_buf c.Pointer, pIn_buf_size *c.SizeT, pPut_buf_func TinflPutBufFuncPtr, pPut_buf_user c.Pointer, flags c.Int) c.Int + +type TinflDecompressorTag struct { + MState MzUint32 + MNumBits MzUint32 + MZhdr0 MzUint32 + MZhdr1 MzUint32 + MZAdler32 MzUint32 + MFinal MzUint32 + MType MzUint32 + MCheckAdler32 MzUint32 + MDist MzUint32 + MCounter MzUint32 + MNumExtra MzUint32 + MTableSizes [3]MzUint32 + MBitBuf TinflBitBufT + MDistFromOutBufStart c.SizeT + MTables [3]TinflHuffTable + MRawHeader [4]MzUint8 + MLenCodes [457]MzUint8 +} +type TinflDecompressor TinflDecompressorTag +type TinflStatus c.Int + +const ( + TINFL_STATUS_BAD_PARAM TinflStatus = -3 + TINFL_STATUS_ADLER32_MISMATCH TinflStatus = -2 + TINFL_STATUS_FAILED TinflStatus = -1 + TINFL_STATUS_DONE TinflStatus = 0 + TINFL_STATUS_NEEDS_MORE_INPUT TinflStatus = 1 + TINFL_STATUS_HAS_MORE_OUTPUT TinflStatus = 2 +) + +// Main low-level decompressor coroutine function. This is the only function actually needed for decompression. All the other functions are just high-level helpers for improved usability. +// This is a universal API, i.e. it can be used as a building block to build any desired higher level decompression API. In the limit case, it can be called once per every byte input or output. +// llgo:link (*TinflDecompressor).TinflDecompress C.tinfl_decompress +func (recv_ *TinflDecompressor) TinflDecompress(pIn_buf_next *MzUint8, pIn_buf_size *c.SizeT, pOut_buf_start *MzUint8, pOut_buf_next *MzUint8, pOut_buf_size *c.SizeT, decomp_flags MzUint32) TinflStatus { + return 0 +} + +const ( + TINFL_MAX_HUFF_TABLES c.Int = 3 + TINFL_MAX_HUFF_SYMBOLS_0 c.Int = 288 + TINFL_MAX_HUFF_SYMBOLS_1 c.Int = 32 + TINFL_MAX_HUFF_SYMBOLS_2 c.Int = 19 + TINFL_FAST_LOOKUP_BITS c.Int = 10 + TINFL_FAST_LOOKUP_SIZE c.Int = 1024 +) + +type TinflHuffTable struct { + MCodeSize [288]MzUint8 + MLookUp [1024]MzInt16 + MTree [576]MzInt16 +} +type TinflBitBufT MzUint64 + +const ( + TDEFL_HUFFMAN_ONLY c.Int = 0 + TDEFL_DEFAULT_MAX_PROBES c.Int = 128 + TDEFL_MAX_PROBES_MASK c.Int = 4095 +) +const ( + TDEFL_WRITE_ZLIB_HEADER c.Int = 4096 + TDEFL_COMPUTE_ADLER32 c.Int = 8192 + TDEFL_GREEDY_PARSING_FLAG c.Int = 16384 + TDEFL_NONDETERMINISTIC_PARSING_FLAG c.Int = 32768 + TDEFL_RLE_MATCHES c.Int = 65536 + TDEFL_FILTER_MATCHES c.Int = 131072 + TDEFL_FORCE_ALL_STATIC_BLOCKS c.Int = 262144 + TDEFL_FORCE_ALL_RAW_BLOCKS c.Int = 524288 +) + +// High level compression functions: +// tdefl_compress_mem_to_heap() compresses a block in memory to a heap block allocated via malloc(). +// On entry: +// +// pSrc_buf, src_buf_len: Pointer and size of source block to compress. +// flags: The max match finder probes (default is 128) logically OR'd against the above flags. Higher probes are slower but improve compression. +// +// On return: +// +// Function returns a pointer to the compressed data, or NULL on failure. +// *pOut_len will be set to the compressed data's size, which could be larger than src_buf_len on uncompressible data. +// The caller must free() the returned block when it's no longer needed. +// +//go:linkname TdeflCompressMemToHeap C.tdefl_compress_mem_to_heap +func TdeflCompressMemToHeap(pSrc_buf c.Pointer, src_buf_len c.SizeT, pOut_len *c.SizeT, flags c.Int) c.Pointer + +// tdefl_compress_mem_to_mem() compresses a block in memory to another block in memory. +// Returns 0 on failure. +// +//go:linkname TdeflCompressMemToMem C.tdefl_compress_mem_to_mem +func TdeflCompressMemToMem(pOut_buf c.Pointer, out_buf_len c.SizeT, pSrc_buf c.Pointer, src_buf_len c.SizeT, flags c.Int) c.SizeT + +// Compresses an image to a compressed PNG file in memory. +// On entry: +// +// pImage, w, h, and num_chans describe the image to compress. num_chans may be 1, 2, 3, or 4. +// The image pitch in bytes per scanline will be w*num_chans. The leftmost pixel on the top scanline is stored first in memory. +// level may range from [0,10], use MZ_NO_COMPRESSION, MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc. or a decent default is MZ_DEFAULT_LEVEL +// If flip is true, the image will be flipped on the Y axis (useful for OpenGL apps). +// +// On return: +// +// Function returns a pointer to the compressed data, or NULL on failure. +// *pLen_out will be set to the size of the PNG image file. +// The caller must mz_free() the returned heap block (which will typically be larger than *pLen_out) when it's no longer needed. +// +//go:linkname TdeflWriteImageToPngFileInMemoryEx C.tdefl_write_image_to_png_file_in_memory_ex +func TdeflWriteImageToPngFileInMemoryEx(pImage c.Pointer, w c.Int, h c.Int, num_chans c.Int, pLen_out *c.SizeT, level MzUint, flip MzBool) c.Pointer + +//go:linkname TdeflWriteImageToPngFileInMemory C.tdefl_write_image_to_png_file_in_memory +func TdeflWriteImageToPngFileInMemory(pImage c.Pointer, w c.Int, h c.Int, num_chans c.Int, pLen_out *c.SizeT) c.Pointer + +// llgo:type C +type TdeflPutBufFuncPtr func(c.Pointer, c.Int, c.Pointer) MzBool + +// tdefl_compress_mem_to_output() compresses a block to an output stream. The above helpers use this function internally. +// +//go:linkname TdeflCompressMemToOutput C.tdefl_compress_mem_to_output +func TdeflCompressMemToOutput(pBuf c.Pointer, buf_len c.SizeT, pPut_buf_func TdeflPutBufFuncPtr, pPut_buf_user c.Pointer, flags c.Int) MzBool + +const ( + TDEFL_MAX_HUFF_TABLES c.Int = 3 + TDEFL_MAX_HUFF_SYMBOLS_0 c.Int = 288 + TDEFL_MAX_HUFF_SYMBOLS_1 c.Int = 32 + TDEFL_MAX_HUFF_SYMBOLS_2 c.Int = 19 + TDEFL_LZ_DICT_SIZE c.Int = 32768 + TDEFL_LZ_DICT_SIZE_MASK c.Int = 32767 + TDEFL_MIN_MATCH_LEN c.Int = 3 + TDEFL_MAX_MATCH_LEN c.Int = 258 +) +const ( + TDEFL_LZ_CODE_BUF_SIZE c.Int = 24576 + TDEFL_OUT_BUF_SIZE c.Int = 31948 + TDEFL_MAX_HUFF_SYMBOLS c.Int = 288 + TDEFL_LZ_HASH_BITS c.Int = 12 + TDEFL_LEVEL1_HASH_SIZE_MASK c.Int = 4095 + TDEFL_LZ_HASH_SHIFT c.Int = 4 + TDEFL_LZ_HASH_SIZE c.Int = 4096 +) + +type TdeflStatus c.Int + +const ( + TDEFL_STATUS_BAD_PARAM TdeflStatus = -2 + TDEFL_STATUS_PUT_BUF_FAILED TdeflStatus = -1 + TDEFL_STATUS_OKAY TdeflStatus = 0 + TDEFL_STATUS_DONE TdeflStatus = 1 +) + +type TdeflFlush c.Int + +const ( + TDEFL_NO_FLUSH TdeflFlush = 0 + TDEFL_SYNC_FLUSH TdeflFlush = 2 + TDEFL_FULL_FLUSH TdeflFlush = 3 + TDEFL_FINISH TdeflFlush = 4 +) + +// tdefl's compression state structure. +type TdeflCompressor struct { + MPPutBufFunc TdeflPutBufFuncPtr + MPPutBufUser c.Pointer + MFlags MzUint + MMaxProbes [2]MzUint + MGreedyParsing c.Int + MAdler32 MzUint + MLookaheadPos MzUint + MLookaheadSize MzUint + MDictSize MzUint + MPLZCodeBuf *MzUint8 + MPLZFlags *MzUint8 + MPOutputBuf *MzUint8 + MPOutputBufEnd *MzUint8 + MNumFlagsLeft MzUint + MTotalLzBytes MzUint + MLzCodeBufDictPos MzUint + MBitsIn MzUint + MBitBuffer MzUint + MSavedMatchDist MzUint + MSavedMatchLen MzUint + MSavedLit MzUint + MOutputFlushOfs MzUint + MOutputFlushRemaining MzUint + MFinished MzUint + MBlockIndex MzUint + MWantsToFinish MzUint + MPrevReturnStatus TdeflStatus + MPInBuf c.Pointer + MPOutBuf c.Pointer + MPInBufSize *c.SizeT + MPOutBufSize *c.SizeT + MFlush TdeflFlush + MPSrc *MzUint8 + MSrcBufLeft c.SizeT + MOutBufOfs c.SizeT + MDict [33025]MzUint8 + MHuffCount [3][288]MzUint16 + MHuffCodes [3][288]MzUint16 + MHuffCodeSizes [3][288]MzUint8 + MLzCodeBuf [24576]MzUint8 + MNext [32768]MzUint16 + MHash [4096]MzUint16 + MOutputBuf [31948]MzUint8 +} + +// Initializes the compressor. +// There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory. +// pBut_buf_func: If **not** NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. +// If pBut_buf_func is NULL the user should always call the tdefl_compress() API. +// flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.) +// llgo:link (*TdeflCompressor).TdeflInit C.tdefl_init +func (recv_ *TdeflCompressor) TdeflInit(pPut_buf_func TdeflPutBufFuncPtr, pPut_buf_user c.Pointer, flags c.Int) TdeflStatus { + return 0 +} + +// Compresses a block of data, consuming as much of the specified input buffer as possible, and writing as much compressed data to the specified output buffer as possible. +// llgo:link (*TdeflCompressor).TdeflCompress C.tdefl_compress +func (recv_ *TdeflCompressor) TdeflCompress(pIn_buf c.Pointer, pIn_buf_size *c.SizeT, pOut_buf c.Pointer, pOut_buf_size *c.SizeT, flush TdeflFlush) TdeflStatus { + return 0 +} + +// tdefl_compress_buffer() is only usable when the tdefl_init() is called with a non-NULL tdefl_put_buf_func_ptr. +// tdefl_compress_buffer() always consumes the entire input buffer. +// llgo:link (*TdeflCompressor).TdeflCompressBuffer C.tdefl_compress_buffer +func (recv_ *TdeflCompressor) TdeflCompressBuffer(pIn_buf c.Pointer, in_buf_size c.SizeT, flush TdeflFlush) TdeflStatus { + return 0 +} + +// llgo:link (*TdeflCompressor).TdeflGetPrevReturnStatus C.tdefl_get_prev_return_status +func (recv_ *TdeflCompressor) TdeflGetPrevReturnStatus() TdeflStatus { + return 0 +} + +// llgo:link (*TdeflCompressor).TdeflGetAdler32 C.tdefl_get_adler32 +func (recv_ *TdeflCompressor) TdeflGetAdler32() MzUint32 { + return 0 +} diff --git a/esp32/mipi_csi_hal.go b/esp32/mipi_csi_hal.go new file mode 100644 index 00000000..f16f3894 --- /dev/null +++ b/esp32/mipi_csi_hal.go @@ -0,0 +1,49 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type CsiHostDevT struct { + Unused [8]uint8 +} +type MipiCsiHostSocHandleT *CsiHostDevT + +type CsiBrgDevT struct { + Unused [8]uint8 +} +type MipiCsiBridgeSocHandleT *CsiBrgDevT + +/** + * @brief MIPI CSI HAL driver context + */ + +type MipiCsiHalContextT struct { + HostDev MipiCsiHostSocHandleT + BridgeDev MipiCsiBridgeSocHandleT +} + +/** + * @brief MIPI CSI HAL driver configuration + */ + +type MipiCsiHalConfigT struct { + LanesNum c.Uint8T + FrameWidth c.Uint32T + FrameHeight c.Uint32T + InBpp c.Uint32T + OutBpp c.Uint32T + ByteSwapEn bool + LaneBitRateMbps c.Int +} + +/** + * @brief MIPI CSI HAL layer initialization + * + * @param hal Pointer to the HAL driver context + * @param config Pointer to the HAL configuration + */ +// llgo:link (*MipiCsiHalContextT).MipiCsiHalInit C.mipi_csi_hal_init +func (recv_ *MipiCsiHalContextT) MipiCsiHalInit(config *MipiCsiHalConfigT) { +} diff --git a/esp32/mipi_csi_periph.go b/esp32/mipi_csi_periph.go new file mode 100644 index 00000000..40cea383 --- /dev/null +++ b/esp32/mipi_csi_periph.go @@ -0,0 +1,16 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief MIPI CSI PHY PLL frequency range + */ + +type SocMipiCsiPhyPllFreqRangeT struct { + StartMbps c.Uint32T + EndMbps c.Uint32T + HsFreqRangeSel c.Uint8T +} diff --git a/esp32/mipi_csi_share_hw_ctrl.go b/esp32/mipi_csi_share_hw_ctrl.go new file mode 100644 index 00000000..4eecd543 --- /dev/null +++ b/esp32/mipi_csi_share_hw_ctrl.go @@ -0,0 +1,41 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type MipiCsiBrgUserT c.Int + +const ( + MIPI_CSI_BRG_USER_CSI MipiCsiBrgUserT = 0 + MIPI_CSI_BRG_USER_ISP_DVP MipiCsiBrgUserT = 1 + MIPI_CSI_BRG_USER_SHARE MipiCsiBrgUserT = 2 +) + +/** + * @brief Claim MIPI CSI Bridge peripheral + * + * @param[in] user CSI Bridge user + * @param[out] out_id ID of the CSI Bridge + * + * @return + * - ESP_OK + * - ESP_ERR_NOT_FOUND No free CSI Bridge + */ +// llgo:link MipiCsiBrgUserT.MipiCsiBrgClaim C.mipi_csi_brg_claim +func (recv_ MipiCsiBrgUserT) MipiCsiBrgClaim(out_id *c.Int) EspErrT { + return 0 +} + +/** + * @brief Declaim MIPI CSI Bridge peripheral + * + * @param[in] id ID of the CSI Bridge + * + * @return + * - ESP_OK + * - ESP_ERR_INVALID_STATE CSI Bridge isn't claimed yet + */ +//go:linkname MipiCsiBrgDeclaim C.mipi_csi_brg_declaim +func MipiCsiBrgDeclaim(id c.Int) EspErrT diff --git a/esp32/mipi_csi_types.go b/esp32/mipi_csi_types.go new file mode 100644 index 00000000..ef0344dd --- /dev/null +++ b/esp32/mipi_csi_types.go @@ -0,0 +1,8 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type MipiCsiPhyClockSourceT c.Int diff --git a/esp32/mipi_dsi_hal.go b/esp32/mipi_dsi_hal.go new file mode 100644 index 00000000..5c8f6a55 --- /dev/null +++ b/esp32/mipi_dsi_hal.go @@ -0,0 +1,202 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type DsiHostDevT struct { + Unused [8]uint8 +} +type MipiDsiHostSocHandleT *DsiHostDevT + +type DsiBrgDevT struct { + Unused [8]uint8 +} +type MipiDsiBridgeSocHandleT *DsiBrgDevT + +/** + * @brief MIPI DSI HAL driver context + */ + +type MipiDsiHalContextT struct { + Host MipiDsiHostSocHandleT + Bridge MipiDsiBridgeSocHandleT + LaneBitRateMbps c.Uint32T + DpiClockFreqMhz c.Uint32T +} + +/** + * @brief MIPI DSI HAL driver configuration + */ + +type MipiDsiHalConfigT struct { + BusId c.Int + LaneBitRateMbps c.Uint32T + NumDataLanes c.Uint8T +} + +/** + * @brief Initialize MIPI DSI Hal driver context + * + * @note Caller should malloc the memory for the hal context + * + * @param hal Pointer to the HAL driver context + * @param config Pointer to the HAL driver configuration + */ +// llgo:link (*MipiDsiHalContextT).MipiDsiHalInit C.mipi_dsi_hal_init +func (recv_ *MipiDsiHalContextT) MipiDsiHalInit(config *MipiDsiHalConfigT) { +} + +/** + * @brief Deinitialize MIPI DSI Hal driver context + * + * @param hal Pointer to the HAL driver context + */ +// llgo:link (*MipiDsiHalContextT).MipiDsiHalDeinit C.mipi_dsi_hal_deinit +func (recv_ *MipiDsiHalContextT) MipiDsiHalDeinit() { +} + +/** + * @brief Configure the PHY PLL + * + * @param hal Pointer to the HAL driver context + * @param phy_clk_src_freq_hz PHY clock source frequency in Hz + * @param lane_bit_rate_mbps Lane bit rate in Mbps + */ +// llgo:link (*MipiDsiHalContextT).MipiDsiHalConfigurePhyPll C.mipi_dsi_hal_configure_phy_pll +func (recv_ *MipiDsiHalContextT) MipiDsiHalConfigurePhyPll(phy_clk_src_freq_hz c.Uint32T, lane_bit_rate_mbps c.Uint32T) { +} + +/** + * @brief Write a value to a PHY register via internal bus (so-called test interface) + * + * @param hal Pointer to the HAL driver context + * @param reg_addr Address of the PHY register + * @param reg_val Value to be written to the PHY register + */ +// llgo:link (*MipiDsiHalContextT).MipiDsiHalPhyWriteRegister C.mipi_dsi_hal_phy_write_register +func (recv_ *MipiDsiHalContextT) MipiDsiHalPhyWriteRegister(reg_addr c.Uint8T, reg_val c.Uint8T) { +} + +/** + * @brief Send a DCS command with parameters via the generic interface + * + * @note The command itself and the parameters are sent in one packet. For simplicity, we use the same + * DCS_LONG_WRITE type to send all different commands. + * + * @param hal Pointer to the HAL driver context + * @param vc Virtual channel number + * @param command DCS command + * @param command_bytes Number of bytes of the command + * @param param Pointer to the parameters + * @param param_size Number of bytes of the parameters + */ +// llgo:link (*MipiDsiHalContextT).MipiDsiHalHostGenWriteDcsCommand C.mipi_dsi_hal_host_gen_write_dcs_command +func (recv_ *MipiDsiHalContextT) MipiDsiHalHostGenWriteDcsCommand(vc c.Uint8T, command c.Uint32T, command_bytes c.Uint32T, param c.Pointer, param_size c.Uint16T) { +} + +/** + * @brief Send a DCS command and return the associated parameters via the generic interface + * + * @param hal Pointer to the HAL driver context + * @param vc Virtual channel number + * @param command DCS command + * @param command_bytes Number of bytes of the command + * @param ret_param Pointer to the buffer to store the returned parameters + * @param param_buf_size Size of the buffer to store the returned parameters + */ +// llgo:link (*MipiDsiHalContextT).MipiDsiHalHostGenReadDcsCommand C.mipi_dsi_hal_host_gen_read_dcs_command +func (recv_ *MipiDsiHalContextT) MipiDsiHalHostGenReadDcsCommand(vc c.Uint8T, command c.Uint32T, command_bytes c.Uint32T, ret_param c.Pointer, param_buf_size c.Uint16T) { +} + +/** + * @brief Send a long packet via the generic interface + * + * @param hal Pointer to the HAL driver context + * @param vc Virtual channel number + * @param dt Data type + * @param buffer Pointer to the buffer + * @param buffer_size Number of bytes to be sent + */ +// llgo:link (*MipiDsiHalContextT).MipiDsiHalHostGenWriteLongPacket C.mipi_dsi_hal_host_gen_write_long_packet +func (recv_ *MipiDsiHalContextT) MipiDsiHalHostGenWriteLongPacket(vc c.Uint8T, dt MipiDsiDataTypeT, buffer c.Pointer, buffer_size c.Uint16T) { +} + +/** + * @brief Send a short packet via the generic interface + * + * @param hal Pointer to the HAL driver context + * @param vc Virtual channel number + * @param dt Data type + * @param header_data Data to be sent, filled into the DSI packet header + */ +// llgo:link (*MipiDsiHalContextT).MipiDsiHalHostGenWriteShortPacket C.mipi_dsi_hal_host_gen_write_short_packet +func (recv_ *MipiDsiHalContextT) MipiDsiHalHostGenWriteShortPacket(vc c.Uint8T, dt MipiDsiDataTypeT, header_data c.Uint16T) { +} + +/** + * @brief Send a short packet via the generic interface and return the associated data + * + * @param hal Pointer to the HAL driver context + * @param vc Virtual channel number + * @param dt Data type + * @param header_data Data to be filled into the DSI packet header + * @param ret_buffer Pointer to the buffer to store the returned data + * @param buffer_size Size of the buffer to store the returned data + */ +// llgo:link (*MipiDsiHalContextT).MipiDsiHalHostGenReadShortPacket C.mipi_dsi_hal_host_gen_read_short_packet +func (recv_ *MipiDsiHalContextT) MipiDsiHalHostGenReadShortPacket(vc c.Uint8T, dt MipiDsiDataTypeT, header_data c.Uint16T, ret_buffer c.Pointer, buffer_size c.Uint16T) { +} + +/** + * @brief Set DPI color coding + * + * @param hal Pointer to the HAL driver context + * @param color_coding Color coding + * @param sub_config Sub configuration + */ +// llgo:link (*MipiDsiHalContextT).MipiDsiHalHostDpiSetColorCoding C.mipi_dsi_hal_host_dpi_set_color_coding +func (recv_ *MipiDsiHalContextT) MipiDsiHalHostDpiSetColorCoding(color_coding LcdColorFormatT, sub_config c.Uint32T) { +} + +/** + * @brief Set horizontal timing parameters for DPI + * + * @param hal Pointer to the HAL driver context + * @param hsw Horizontal Synchronization Width + * @param hbp Horizontal Back Porch + * @param active_width Active Width + * @param hfp Horizontal Front Porch + */ +// llgo:link (*MipiDsiHalContextT).MipiDsiHalHostDpiSetHorizontalTiming C.mipi_dsi_hal_host_dpi_set_horizontal_timing +func (recv_ *MipiDsiHalContextT) MipiDsiHalHostDpiSetHorizontalTiming(hsw c.Uint32T, hbp c.Uint32T, active_width c.Uint32T, hfp c.Uint32T) { +} + +/** + * @brief Set vertical timing parameters for DPI + * + * @param hal Pointer to the HAL driver context + * @param vsw Vertical Synchronization Width + * @param vbp Vertical Back Porch + * @param active_height Active Height + * @param vfp Vertical Front Porch + */ +// llgo:link (*MipiDsiHalContextT).MipiDsiHalHostDpiSetVerticalTiming C.mipi_dsi_hal_host_dpi_set_vertical_timing +func (recv_ *MipiDsiHalContextT) MipiDsiHalHostDpiSetVerticalTiming(vsw c.Uint32T, vbp c.Uint32T, active_height c.Uint32T, vfp c.Uint32T) { +} + +/** + * @brief Calculate the divider for DPI clock + * + * @note This function will also update the real DPI clock frequency in the HAL context + * + * @param hal Pointer to the HAL driver context + * @param clk_src_mhz Clock source frequency in MHz + * @param expect_dpi_clk_mhz Expected DPI clock frequency in MHz + * @return Divider value + */ +// llgo:link (*MipiDsiHalContextT).MipiDsiHalHostDpiCalculateDivider C.mipi_dsi_hal_host_dpi_calculate_divider +func (recv_ *MipiDsiHalContextT) MipiDsiHalHostDpiCalculateDivider(clk_src_mhz c.Uint32T, expect_dpi_clk_mhz c.Uint32T) c.Uint32T { + return 0 +} diff --git a/esp32/mipi_dsi_periph.go b/esp32/mipi_dsi_periph.go new file mode 100644 index 00000000..a980eab4 --- /dev/null +++ b/esp32/mipi_dsi_periph.go @@ -0,0 +1,16 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief MIPI DSI PHY PLL frequency range + */ + +type SocMipiDsiPhyPllFreqRangeT struct { + StartMbps c.Uint32T + EndMbps c.Uint32T + HsFreqRangeSel c.Uint8T +} diff --git a/esp32/mipi_dsi_types.go b/esp32/mipi_dsi_types.go new file mode 100644 index 00000000..86ce5e70 --- /dev/null +++ b/esp32/mipi_dsi_types.go @@ -0,0 +1,50 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type MipiDsiDataTypeT c.Int + +const ( + MIPI_DSI_DT_VSYNC_START MipiDsiDataTypeT = 1 + MIPI_DSI_DT_VSYNC_END MipiDsiDataTypeT = 17 + MIPI_DSI_DT_HSYNC_START MipiDsiDataTypeT = 33 + MIPI_DSI_DT_HSYNC_END MipiDsiDataTypeT = 49 + MIPI_DSI_DT_EOT_PACKET MipiDsiDataTypeT = 8 + MIPI_DSI_DT_COLOR_MODE_OFF MipiDsiDataTypeT = 2 + MIPI_DSI_DT_COLOR_MODE_ON MipiDsiDataTypeT = 18 + MIPI_DSI_DT_SHUTDOWN_PERIPHERAL MipiDsiDataTypeT = 34 + MIPI_DSI_DT_TURN_ON_PERIPHERAL MipiDsiDataTypeT = 50 + MIPI_DSI_DT_GENERIC_SHORT_WRITE_0 MipiDsiDataTypeT = 3 + MIPI_DSI_DT_GENERIC_SHORT_WRITE_1 MipiDsiDataTypeT = 19 + MIPI_DSI_DT_GENERIC_SHORT_WRITE_2 MipiDsiDataTypeT = 35 + MIPI_DSI_DT_GENERIC_READ_REQUEST_0 MipiDsiDataTypeT = 4 + MIPI_DSI_DT_GENERIC_READ_REQUEST_1 MipiDsiDataTypeT = 20 + MIPI_DSI_DT_GENERIC_READ_REQUEST_2 MipiDsiDataTypeT = 36 + MIPI_DSI_DT_DCS_SHORT_WRITE_0 MipiDsiDataTypeT = 5 + MIPI_DSI_DT_DCS_SHORT_WRITE_1 MipiDsiDataTypeT = 21 + MIPI_DSI_DT_DCS_READ_0 MipiDsiDataTypeT = 6 + MIPI_DSI_DT_SET_MAXIMUM_RETURN_PKT MipiDsiDataTypeT = 55 + MIPI_DSI_DT_NULL_PACKET MipiDsiDataTypeT = 9 + MIPI_DSI_DT_BLANKING_PACKET MipiDsiDataTypeT = 25 + MIPI_DSI_DT_GENERIC_LONG_WRITE MipiDsiDataTypeT = 41 + MIPI_DSI_DT_DCS_LONG_WRITE MipiDsiDataTypeT = 57 + MIPI_DSI_DT_PACKED_PIXEL_STREAM_RGB_16 MipiDsiDataTypeT = 14 + MIPI_DSI_DT_PACKED_PIXEL_STREAM_RGB_18 MipiDsiDataTypeT = 30 + MIPI_DSI_DT_LOOSELY_PIXEL_STREAM_RGB_18 MipiDsiDataTypeT = 46 + MIPI_DSI_DT_PACKED_PIXEL_STREAM_RGB_24 MipiDsiDataTypeT = 62 +) + +type MipiDsiPatternTypeT c.Int + +const ( + MIPI_DSI_PATTERN_NONE MipiDsiPatternTypeT = 0 + MIPI_DSI_PATTERN_BAR_VERTICAL MipiDsiPatternTypeT = 1 + MIPI_DSI_PATTERN_BAR_HORIZONTAL MipiDsiPatternTypeT = 2 + MIPI_DSI_PATTERN_BER_VERTICAL MipiDsiPatternTypeT = 3 +) + +type MipiDsiPhyClockSourceT c.Int +type MipiDsiDpiClockSourceT c.Int diff --git a/esp32/misc.go b/esp32/misc.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/misc.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/mmu.go b/esp32/mmu.go new file mode 100644 index 00000000..f15bd6a9 --- /dev/null +++ b/esp32/mmu.go @@ -0,0 +1,6 @@ +package freertos + +import _ "unsafe" + +const SOC_MMU_REGIONS_COUNT = 2 +const SOC_MMU_PAGES_PER_REGION = 256 diff --git a/esp32/mmu_hal.go b/esp32/mmu_hal.go new file mode 100644 index 00000000..b3bac3bb --- /dev/null +++ b/esp32/mmu_hal.go @@ -0,0 +1,119 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * MMU Hal layer initialisation + */ +//go:linkname MmuHalInit C.mmu_hal_init +func MmuHalInit() + +/** + * Unmap all the MMU table. After this all external memory vaddr are not available + */ +//go:linkname MmuHalUnmapAll C.mmu_hal_unmap_all +func MmuHalUnmapAll() + +/** + * Helper functions to convert the MMU page numbers into bytes. e.g.: + * - When MMU page size is 16KB, page_num = 2 will be converted into 32KB + * - When MMU page size is 32KB, page_num = 2 will be converted into 64KB + * + * @param mmu_id MMU ID + * @param page_num page numbers + * + * @return + * length in byte + */ +//go:linkname MmuHalPagesToBytes C.mmu_hal_pages_to_bytes +func MmuHalPagesToBytes(mmu_id c.Uint32T, page_num c.Uint32T) c.Uint32T + +/** + * Helper functions to convert bytes into MMU page numbers. e.g.: + * - When MMU page size is 16KB, bytes = 64KB will be converted into 4 pages + * - When MMU page size is 32KB, bytes = 64KB will be converted into 2 pages + * + * @param mmu_id MMU ID + * @param bytes length in byte + * + * @return + * length in CONFIG_MMU_PAGE_SIZE + */ +//go:linkname MmuHalBytesToPages C.mmu_hal_bytes_to_pages +func MmuHalBytesToPages(mmu_id c.Uint32T, bytes c.Uint32T) c.Uint32T + +/** + * To map a virtual address block to a physical memory block + * + * @param mmu_id MMU ID + * @param mem_type physical memory type, see `mmu_target_t` + * @param vaddr start virtual address to be mapped + * @param paddr start physical address to be mapped + * @param len length to be mapped, in bytes + * @param[out] out_len actual mapped length + * + * @note vaddr and paddr should be aligned with the mmu page size, see CONFIG_MMU_PAGE_SIZE + */ +//go:linkname MmuHalMapRegion C.mmu_hal_map_region +func MmuHalMapRegion(mmu_id c.Uint32T, mem_type MmuTargetT, vaddr c.Uint32T, paddr c.Uint32T, len c.Uint32T, out_len *c.Uint32T) + +/** + * To unmap a virtual address block that is mapped to a physical memory block previously + * + * @param[in] mmu_id MMU ID + * @param[in] vaddr start virtual address + * @param[in] len length to be unmapped, in bytes + */ +//go:linkname MmuHalUnmapRegion C.mmu_hal_unmap_region +func MmuHalUnmapRegion(mmu_id c.Uint32T, vaddr c.Uint32T, len c.Uint32T) + +/** + * Convert virtual address to physical address + * + * @param mmu_id MMU ID + * @param vaddr virtual address + * @param[out] out_paddr physical address + * @param[out] out_target Indicating the vaddr/paddr is mapped on which target, see `mmu_target_t` + * + * @return + * - true: virtual address is valid + * - false: virtual address isn't valid + */ +//go:linkname MmuHalVaddrToPaddr C.mmu_hal_vaddr_to_paddr +func MmuHalVaddrToPaddr(mmu_id c.Uint32T, vaddr c.Uint32T, out_paddr *c.Uint32T, out_target *MmuTargetT) bool + +/** + * Convert physical address to virtual address + * + * @note This function can only find the first match virtual address. + * However it is possible that a physical address is mapped to multiple virtual addresses. + * + * @param mmu_id MMU ID + * @param paddr physical address + * @param target physical memory target, see `mmu_target_t` + * @param type virtual address type, could be instruction or data + * @param[out] out_vaddr virtual address + * + * @return + * - true: found a matched vaddr + * - false: not found a matched vaddr + */ +//go:linkname MmuHalPaddrToVaddr C.mmu_hal_paddr_to_vaddr +func MmuHalPaddrToVaddr(mmu_id c.Uint32T, paddr c.Uint32T, target MmuTargetT, type_ MmuVaddrT, out_vaddr *c.Uint32T) bool + +/** + * Check if the vaddr region is valid + * + * @param mmu_id MMU ID + * @param vaddr_start start of the virtual address + * @param len length, in bytes + * @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t` + * + * @return + * True for valid + */ +//go:linkname MmuHalCheckValidExtVaddrRegion C.mmu_hal_check_valid_ext_vaddr_region +func MmuHalCheckValidExtVaddrRegion(mmu_id c.Uint32T, vaddr_start c.Uint32T, len c.Uint32T, type_ MmuVaddrT) bool diff --git a/esp32/mmu_ll.go b/esp32/mmu_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/mmu_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/mmu_types.go b/esp32/mmu_types.go new file mode 100644 index 00000000..84334e05 --- /dev/null +++ b/esp32/mmu_types.go @@ -0,0 +1,46 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type MmuMemCapsT c.Int + +const ( + MMU_MEM_CAP_EXEC MmuMemCapsT = 1 + MMU_MEM_CAP_READ MmuMemCapsT = 2 + MMU_MEM_CAP_WRITE MmuMemCapsT = 4 + MMU_MEM_CAP_32BIT MmuMemCapsT = 8 + MMU_MEM_CAP_8BIT MmuMemCapsT = 16 +) + +type MmuPageSizeT c.Int + +const ( + MMU_PAGE_8KB MmuPageSizeT = 8192 + MMU_PAGE_16KB MmuPageSizeT = 16384 + MMU_PAGE_32KB MmuPageSizeT = 32768 + MMU_PAGE_64KB MmuPageSizeT = 65536 +) + +type MmuVaddrT c.Int + +const ( + MMU_VADDR_DATA MmuVaddrT = 1 + MMU_VADDR_INSTRUCTION MmuVaddrT = 2 +) + +type MmuTargetT c.Int + +const ( + MMU_TARGET_FLASH0 MmuTargetT = 1 + MMU_TARGET_PSRAM0 MmuTargetT = 2 +) + +type MmuTableIdT c.Int + +const ( + MMU_TABLE_CORE0 MmuTableIdT = 0 + MMU_TABLE_CORE1 MmuTableIdT = 1 +) diff --git a/esp32/modem_clock_types.go b/esp32/modem_clock_types.go new file mode 100644 index 00000000..cf942e26 --- /dev/null +++ b/esp32/modem_clock_types.go @@ -0,0 +1,35 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type ModemClockDomainT c.Int + +const ( + MODEM_CLOCK_DOMAIN_MODEM_APB ModemClockDomainT = 0 + MODEM_CLOCK_DOMAIN_MODEM_PERIPH ModemClockDomainT = 1 + MODEM_CLOCK_DOMAIN_WIFI ModemClockDomainT = 2 + MODEM_CLOCK_DOMAIN_BT ModemClockDomainT = 3 + MODEM_CLOCK_DOMAIN_MODEM_FE ModemClockDomainT = 4 + MODEM_CLOCK_DOMAIN_IEEE802154 ModemClockDomainT = 5 + MODEM_CLOCK_DOMAIN_LP_APB ModemClockDomainT = 6 + MODEM_CLOCK_DOMAIN_I2C_MASTER ModemClockDomainT = 7 + MODEM_CLOCK_DOMAIN_COEX ModemClockDomainT = 8 + MODEM_CLOCK_DOMAIN_WIFIPWR ModemClockDomainT = 9 + MODEM_CLOCK_DOMAIN_MAX ModemClockDomainT = 10 +) + +type ModemClockLpclkSrcT c.Int + +const ( + MODEM_CLOCK_LPCLK_SRC_INVALID ModemClockLpclkSrcT = -1 + MODEM_CLOCK_LPCLK_SRC_RC_SLOW ModemClockLpclkSrcT = 0 + MODEM_CLOCK_LPCLK_SRC_RC_FAST ModemClockLpclkSrcT = 1 + MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL ModemClockLpclkSrcT = 2 + MODEM_CLOCK_LPCLK_SRC_RC32K ModemClockLpclkSrcT = 3 + MODEM_CLOCK_LPCLK_SRC_XTAL32K ModemClockLpclkSrcT = 4 + MODEM_CLOCK_LPCLK_SRC_EXT32K ModemClockLpclkSrcT = 5 + MODEM_CLOCK_LPCLK_SRC_MAX ModemClockLpclkSrcT = 6 +) diff --git a/esp32/mpi_hal.go b/esp32/mpi_hal.go new file mode 100644 index 00000000..d5e002fd --- /dev/null +++ b/esp32/mpi_hal.go @@ -0,0 +1,142 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Calculate the number of words needed to represent the input word in hardware. + * + * @param words The number of words to be represented. + * @return size_t Number of words required. + */ +//go:linkname MpiHalCalcHardwareWords C.mpi_hal_calc_hardware_words +func MpiHalCalcHardwareWords(words c.SizeT) c.SizeT + +/** + * @brief Clear the MPI power control bit and intitialise the MPI hardware. + * + */ +//go:linkname MpiHalEnableHardwareHwOp C.mpi_hal_enable_hardware_hw_op +func MpiHalEnableHardwareHwOp() + +/** + * @brief Set the MPI power control bit to disable the MPI hardware. + * + */ +//go:linkname MpiHalDisableHardwareHwOp C.mpi_hal_disable_hardware_hw_op +func MpiHalDisableHardwareHwOp() + +/** + * @brief Enable/disables MPI operation complete interrupt. + * + * @param enable true: enable, false: disable. + */ +//go:linkname MpiHalInterruptEnable C.mpi_hal_interrupt_enable +func MpiHalInterruptEnable(enable bool) + +/** + * @brief Clears the MPI operation complete interrupt status. + * + */ +//go:linkname MpiHalClearInterrupt C.mpi_hal_clear_interrupt +func MpiHalClearInterrupt() + +/** + * @brief Configure RSA length. + * + * @param num_words Number of words representing the RSA length. + */ +//go:linkname MpiHalSetMode C.mpi_hal_set_mode +func MpiHalSetMode(num_words c.SizeT) + +/** + * @brief Copy the large number (array of words) representation of the parameter 'param' to hardware memory block. + * + * @param param Type of parameter (enum). + * @param offset Offset to copy in the memory from the base address of the parameter. + * @param p Pointer to large number (array of words) representation of the parameter. + * @param n Number of words needed to represent the large number as an array of words. + * @param num_words Maximum hardware words needed. + */ +// llgo:link MpiParamT.MpiHalWriteToMemBlock C.mpi_hal_write_to_mem_block +func (recv_ MpiParamT) MpiHalWriteToMemBlock(offset c.SizeT, p *c.Uint32T, n c.SizeT, num_words c.SizeT) { +} + +/** + * @brief Write a word-sized value to hardware memory block of a parameter. + * + * @param param Type of parameter (enum). + * @param offset Offset to copy in the memory from the base address of the parameter. + * @param value Value to be written in the memory. + */ +// llgo:link MpiParamT.MpiHalWriteAtOffset C.mpi_hal_write_at_offset +func (recv_ MpiParamT) MpiHalWriteAtOffset(offset c.Int, value c.Uint32T) { +} + +/** + * @brief Write the modular multiplicative inverse of M. + * + * @param Mprime Modular multiplicative inverse of M. + */ +//go:linkname MpiHalWriteMPrime C.mpi_hal_write_m_prime +func MpiHalWriteMPrime(Mprime c.Uint32T) + +/** + * @brief Write first word of the parametr Rinv. + * + * @param rinv Value of first word of rinv. + */ +//go:linkname MpiHalWriteRinv C.mpi_hal_write_rinv +func MpiHalWriteRinv(rinv c.Uint32T) + +/** + * @brief Enable/Disable constant time acceleration option. + * + * @param enable true: enable, false: disable. + */ +//go:linkname MpiHalEnableConstantTime C.mpi_hal_enable_constant_time +func MpiHalEnableConstantTime(enable bool) + +/** + * @brief Enable/Disable search time acceleration option. + * + * @param enable + */ +//go:linkname MpiHalEnableSearch C.mpi_hal_enable_search +func MpiHalEnableSearch(enable bool) + +/** + * @brief Configures the starting address to start search. + * + * @param position Address to start search. + */ +//go:linkname MpiHalSetSearchPosition C.mpi_hal_set_search_position +func MpiHalSetSearchPosition(position c.SizeT) + +/** + * @brief Begin an MPI operation. + * + * @param op Operation type (enum). + */ +// llgo:link MpiOpT.MpiHalStartOp C.mpi_hal_start_op +func (recv_ MpiOpT) MpiHalStartOp() { +} + +/** + * @brief Wait for an MPI operation to complete. + * + */ +//go:linkname MpiHalWaitOpComplete C.mpi_hal_wait_op_complete +func MpiHalWaitOpComplete() + +/** + * @brief Wait for an MPI operation to complete and Read result from last MPI operation into parameter Z. + * + * @param p Pointer to large number (array of words) representation of the parameter. + * @param n Number of words needed to represent the large number as an array of words. + * @param z_words Calculated number of words of parameter Z. + */ +//go:linkname MpiHalReadResultHwOp C.mpi_hal_read_result_hw_op +func MpiHalReadResultHwOp(p *c.Uint32T, n c.SizeT, z_words c.SizeT) diff --git a/esp32/mpi_ll.go b/esp32/mpi_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/mpi_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/mpi_types.go b/esp32/mpi_types.go new file mode 100644 index 00000000..1f8acad7 --- /dev/null +++ b/esp32/mpi_types.go @@ -0,0 +1,23 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type MpiOpT c.Int + +const ( + MPI_MULT MpiOpT = 0 + MPI_MODMULT MpiOpT = 1 + MPI_MODEXP MpiOpT = 2 +) + +type MpiParamT c.Int + +const ( + MPI_PARAM_X MpiParamT = 0 + MPI_PARAM_Y MpiParamT = 1 + MPI_PARAM_Z MpiParamT = 2 + MPI_PARAM_M MpiParamT = 3 +) diff --git a/esp32/mpu_caps.go b/esp32/mpu_caps.go new file mode 100644 index 00000000..4dd2290f --- /dev/null +++ b/esp32/mpu_caps.go @@ -0,0 +1,8 @@ +package freertos + +import _ "unsafe" + +const SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED = 0 +const SOC_MPU_REGIONS_MAX_NUM = 8 +const SOC_MPU_REGION_RO_SUPPORTED = 0 +const SOC_MPU_REGION_WO_SUPPORTED = 0 diff --git a/esp32/mpu_hal.go b/esp32/mpu_hal.go new file mode 100644 index 00000000..3520dea3 --- /dev/null +++ b/esp32/mpu_hal.go @@ -0,0 +1,16 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Specify the type of access allowed on a memory region. + * + * @param id index to the region table; on targets not SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED, + * the region divisions is predefined in hardware which is likely reflected in LL implementation. + * @param access type of access allowed + */ +//go:linkname MpuHalSetRegionAccess C.mpu_hal_set_region_access +func MpuHalSetRegionAccess(id c.Int, access MpuAccessT) diff --git a/esp32/mpu_prototypes.go b/esp32/mpu_prototypes.go new file mode 100644 index 00000000..288ce60e --- /dev/null +++ b/esp32/mpu_prototypes.go @@ -0,0 +1,347 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* MPU versions of task.h API functions. */ +//go:linkname MPUXTaskCreate C.MPU_xTaskCreate +func MPUXTaskCreate(pxTaskCode c.Int, pcName *c.Char, usStackDepth c.Uint16T, pvParameters c.Pointer, uxPriority UBaseTypeT, pxCreatedTask *c.Int) BaseTypeT + +//go:linkname MPUXTaskCreateStatic C.MPU_xTaskCreateStatic +func MPUXTaskCreateStatic(pxTaskCode c.Int, pcName *c.Char, ulStackDepth c.Uint32T, pvParameters c.Pointer, uxPriority UBaseTypeT, puxStackBuffer *StackTypeT, pxTaskBuffer *StaticTaskT) c.Int + +//go:linkname MPUVTaskDelete C.MPU_vTaskDelete +func MPUVTaskDelete(xTaskToDelete c.Int) + +// llgo:link TickTypeT.MPUVTaskDelay C.MPU_vTaskDelay +func (recv_ TickTypeT) MPUVTaskDelay() { +} + +// llgo:link (*TickTypeT).MPUXTaskDelayUntil C.MPU_xTaskDelayUntil +func (recv_ *TickTypeT) MPUXTaskDelayUntil(xTimeIncrement TickTypeT) BaseTypeT { + return 0 +} + +//go:linkname MPUXTaskAbortDelay C.MPU_xTaskAbortDelay +func MPUXTaskAbortDelay(xTask c.Int) BaseTypeT + +//go:linkname MPUUxTaskPriorityGet C.MPU_uxTaskPriorityGet +func MPUUxTaskPriorityGet(xTask c.Int) UBaseTypeT + +//go:linkname MPUETaskGetState C.MPU_eTaskGetState +func MPUETaskGetState(xTask c.Int) c.Int + +//go:linkname MPUVTaskGetInfo C.MPU_vTaskGetInfo +func MPUVTaskGetInfo(xTask c.Int, pxTaskStatus *c.Int, xGetFreeStackSpace BaseTypeT, eState c.Int) + +//go:linkname MPUVTaskPrioritySet C.MPU_vTaskPrioritySet +func MPUVTaskPrioritySet(xTask c.Int, uxNewPriority UBaseTypeT) + +//go:linkname MPUVTaskSuspend C.MPU_vTaskSuspend +func MPUVTaskSuspend(xTaskToSuspend c.Int) + +//go:linkname MPUVTaskResume C.MPU_vTaskResume +func MPUVTaskResume(xTaskToResume c.Int) + +//go:linkname MPUVTaskStartScheduler C.MPU_vTaskStartScheduler +func MPUVTaskStartScheduler() + +//go:linkname MPUVTaskSuspendAll C.MPU_vTaskSuspendAll +func MPUVTaskSuspendAll() + +//go:linkname MPUXTaskResumeAll C.MPU_xTaskResumeAll +func MPUXTaskResumeAll() BaseTypeT + +//go:linkname MPUXTaskGetTickCount C.MPU_xTaskGetTickCount +func MPUXTaskGetTickCount() TickTypeT + +//go:linkname MPUUxTaskGetNumberOfTasks C.MPU_uxTaskGetNumberOfTasks +func MPUUxTaskGetNumberOfTasks() UBaseTypeT + +//go:linkname MPUPcTaskGetName C.MPU_pcTaskGetName +func MPUPcTaskGetName(xTaskToQuery c.Int) *c.Char + +//go:linkname MPUXTaskGetHandle C.MPU_xTaskGetHandle +func MPUXTaskGetHandle(pcNameToQuery *c.Char) c.Int + +//go:linkname MPUUxTaskGetStackHighWaterMark C.MPU_uxTaskGetStackHighWaterMark +func MPUUxTaskGetStackHighWaterMark(xTask c.Int) UBaseTypeT + +//go:linkname MPUUxTaskGetStackHighWaterMark2 C.MPU_uxTaskGetStackHighWaterMark2 +func MPUUxTaskGetStackHighWaterMark2(xTask c.Int) c.Uint32T + +//go:linkname MPUVTaskSetApplicationTaskTag C.MPU_vTaskSetApplicationTaskTag +func MPUVTaskSetApplicationTaskTag(xTask c.Int, pxHookFunction c.Int) + +//go:linkname MPUXTaskGetApplicationTaskTag C.MPU_xTaskGetApplicationTaskTag +func MPUXTaskGetApplicationTaskTag(xTask c.Int) c.Int + +//go:linkname MPUVTaskSetThreadLocalStoragePointer C.MPU_vTaskSetThreadLocalStoragePointer +func MPUVTaskSetThreadLocalStoragePointer(xTaskToSet c.Int, xIndex BaseTypeT, pvValue c.Pointer) + +//go:linkname MPUPvTaskGetThreadLocalStoragePointer C.MPU_pvTaskGetThreadLocalStoragePointer +func MPUPvTaskGetThreadLocalStoragePointer(xTaskToQuery c.Int, xIndex BaseTypeT) c.Pointer + +//go:linkname MPUXTaskCallApplicationTaskHook C.MPU_xTaskCallApplicationTaskHook +func MPUXTaskCallApplicationTaskHook(xTask c.Int, pvParameter c.Pointer) BaseTypeT + +//go:linkname MPUXTaskGetIdleTaskHandle C.MPU_xTaskGetIdleTaskHandle +func MPUXTaskGetIdleTaskHandle() c.Int + +//go:linkname MPUUxTaskGetSystemState C.MPU_uxTaskGetSystemState +func MPUUxTaskGetSystemState(pxTaskStatusArray *c.Int, uxArraySize UBaseTypeT, pulTotalRunTime *c.Uint32T) UBaseTypeT + +//go:linkname MPUUlTaskGetIdleRunTimeCounter C.MPU_ulTaskGetIdleRunTimeCounter +func MPUUlTaskGetIdleRunTimeCounter() c.Uint32T + +//go:linkname MPUUlTaskGetIdleRunTimePercent C.MPU_ulTaskGetIdleRunTimePercent +func MPUUlTaskGetIdleRunTimePercent() c.Uint32T + +//go:linkname MPUVTaskList C.MPU_vTaskList +func MPUVTaskList(pcWriteBuffer *c.Char) + +//go:linkname MPUVTaskGetRunTimeStats C.MPU_vTaskGetRunTimeStats +func MPUVTaskGetRunTimeStats(pcWriteBuffer *c.Char) + +//go:linkname MPUXTaskGenericNotify C.MPU_xTaskGenericNotify +func MPUXTaskGenericNotify(xTaskToNotify c.Int, uxIndexToNotify UBaseTypeT, ulValue c.Uint32T, eAction c.Int, pulPreviousNotificationValue *c.Uint32T) BaseTypeT + +// llgo:link UBaseTypeT.MPUXTaskGenericNotifyWait C.MPU_xTaskGenericNotifyWait +func (recv_ UBaseTypeT) MPUXTaskGenericNotifyWait(ulBitsToClearOnEntry c.Uint32T, ulBitsToClearOnExit c.Uint32T, pulNotificationValue *c.Uint32T, xTicksToWait TickTypeT) BaseTypeT { + return 0 +} + +// llgo:link UBaseTypeT.MPUUlTaskGenericNotifyTake C.MPU_ulTaskGenericNotifyTake +func (recv_ UBaseTypeT) MPUUlTaskGenericNotifyTake(xClearCountOnExit BaseTypeT, xTicksToWait TickTypeT) c.Uint32T { + return 0 +} + +//go:linkname MPUXTaskGenericNotifyStateClear C.MPU_xTaskGenericNotifyStateClear +func MPUXTaskGenericNotifyStateClear(xTask c.Int, uxIndexToClear UBaseTypeT) BaseTypeT + +//go:linkname MPUUlTaskGenericNotifyValueClear C.MPU_ulTaskGenericNotifyValueClear +func MPUUlTaskGenericNotifyValueClear(xTask c.Int, uxIndexToClear UBaseTypeT, ulBitsToClear c.Uint32T) c.Uint32T + +//go:linkname MPUXTaskIncrementTick C.MPU_xTaskIncrementTick +func MPUXTaskIncrementTick() BaseTypeT + +//go:linkname MPUXTaskGetCurrentTaskHandle C.MPU_xTaskGetCurrentTaskHandle +func MPUXTaskGetCurrentTaskHandle() c.Int + +//go:linkname MPUVTaskSetTimeOutState C.MPU_vTaskSetTimeOutState +func MPUVTaskSetTimeOutState(pxTimeOut *c.Int) + +//go:linkname MPUXTaskCheckForTimeOut C.MPU_xTaskCheckForTimeOut +func MPUXTaskCheckForTimeOut(pxTimeOut *c.Int, pxTicksToWait *TickTypeT) BaseTypeT + +//go:linkname MPUVTaskMissedYield C.MPU_vTaskMissedYield +func MPUVTaskMissedYield() + +//go:linkname MPUXTaskGetSchedulerState C.MPU_xTaskGetSchedulerState +func MPUXTaskGetSchedulerState() BaseTypeT + +// llgo:link TickTypeT.MPUXTaskCatchUpTicks C.MPU_xTaskCatchUpTicks +func (recv_ TickTypeT) MPUXTaskCatchUpTicks() BaseTypeT { + return 0 +} + +/* MPU versions of queue.h API functions. */ +//go:linkname MPUXQueueGenericSend C.MPU_xQueueGenericSend +func MPUXQueueGenericSend(xQueue c.Int, pvItemToQueue c.Pointer, xTicksToWait TickTypeT, xCopyPosition BaseTypeT) BaseTypeT + +//go:linkname MPUXQueueReceive C.MPU_xQueueReceive +func MPUXQueueReceive(xQueue c.Int, pvBuffer c.Pointer, xTicksToWait TickTypeT) BaseTypeT + +//go:linkname MPUXQueuePeek C.MPU_xQueuePeek +func MPUXQueuePeek(xQueue c.Int, pvBuffer c.Pointer, xTicksToWait TickTypeT) BaseTypeT + +//go:linkname MPUXQueueSemaphoreTake C.MPU_xQueueSemaphoreTake +func MPUXQueueSemaphoreTake(xQueue c.Int, xTicksToWait TickTypeT) BaseTypeT + +//go:linkname MPUUxQueueMessagesWaiting C.MPU_uxQueueMessagesWaiting +func MPUUxQueueMessagesWaiting(xQueue c.Int) UBaseTypeT + +//go:linkname MPUUxQueueSpacesAvailable C.MPU_uxQueueSpacesAvailable +func MPUUxQueueSpacesAvailable(xQueue c.Int) UBaseTypeT + +//go:linkname MPUVQueueDelete C.MPU_vQueueDelete +func MPUVQueueDelete(xQueue c.Int) + +//go:linkname MPUXQueueCreateMutex C.MPU_xQueueCreateMutex +func MPUXQueueCreateMutex(ucQueueType c.Uint8T) c.Int + +//go:linkname MPUXQueueCreateMutexStatic C.MPU_xQueueCreateMutexStatic +func MPUXQueueCreateMutexStatic(ucQueueType c.Uint8T, pxStaticQueue *StaticQueueT) c.Int + +// llgo:link UBaseTypeT.MPUXQueueCreateCountingSemaphore C.MPU_xQueueCreateCountingSemaphore +func (recv_ UBaseTypeT) MPUXQueueCreateCountingSemaphore(uxInitialCount UBaseTypeT) c.Int { + return 0 +} + +// llgo:link UBaseTypeT.MPUXQueueCreateCountingSemaphoreStatic C.MPU_xQueueCreateCountingSemaphoreStatic +func (recv_ UBaseTypeT) MPUXQueueCreateCountingSemaphoreStatic(uxInitialCount UBaseTypeT, pxStaticQueue *StaticQueueT) c.Int { + return 0 +} + +//go:linkname MPUXQueueGetMutexHolder C.MPU_xQueueGetMutexHolder +func MPUXQueueGetMutexHolder(xSemaphore c.Int) c.Int + +//go:linkname MPUXQueueTakeMutexRecursive C.MPU_xQueueTakeMutexRecursive +func MPUXQueueTakeMutexRecursive(xMutex c.Int, xTicksToWait TickTypeT) BaseTypeT + +//go:linkname MPUXQueueGiveMutexRecursive C.MPU_xQueueGiveMutexRecursive +func MPUXQueueGiveMutexRecursive(pxMutex c.Int) BaseTypeT + +//go:linkname MPUVQueueAddToRegistry C.MPU_vQueueAddToRegistry +func MPUVQueueAddToRegistry(xQueue c.Int, pcName *c.Char) + +//go:linkname MPUVQueueUnregisterQueue C.MPU_vQueueUnregisterQueue +func MPUVQueueUnregisterQueue(xQueue c.Int) + +//go:linkname MPUPcQueueGetName C.MPU_pcQueueGetName +func MPUPcQueueGetName(xQueue c.Int) *c.Char + +// llgo:link UBaseTypeT.MPUXQueueGenericCreate C.MPU_xQueueGenericCreate +func (recv_ UBaseTypeT) MPUXQueueGenericCreate(uxItemSize UBaseTypeT, ucQueueType c.Uint8T) c.Int { + return 0 +} + +// llgo:link UBaseTypeT.MPUXQueueGenericCreateStatic C.MPU_xQueueGenericCreateStatic +func (recv_ UBaseTypeT) MPUXQueueGenericCreateStatic(uxItemSize UBaseTypeT, pucQueueStorage *c.Uint8T, pxStaticQueue *StaticQueueT, ucQueueType c.Uint8T) c.Int { + return 0 +} + +// llgo:link UBaseTypeT.MPUXQueueCreateSet C.MPU_xQueueCreateSet +func (recv_ UBaseTypeT) MPUXQueueCreateSet() c.Int { + return 0 +} + +//go:linkname MPUXQueueAddToSet C.MPU_xQueueAddToSet +func MPUXQueueAddToSet(xQueueOrSemaphore c.Int, xQueueSet c.Int) BaseTypeT + +//go:linkname MPUXQueueRemoveFromSet C.MPU_xQueueRemoveFromSet +func MPUXQueueRemoveFromSet(xQueueOrSemaphore c.Int, xQueueSet c.Int) BaseTypeT + +//go:linkname MPUXQueueSelectFromSet C.MPU_xQueueSelectFromSet +func MPUXQueueSelectFromSet(xQueueSet c.Int, xTicksToWait TickTypeT) c.Int + +//go:linkname MPUXQueueGenericReset C.MPU_xQueueGenericReset +func MPUXQueueGenericReset(xQueue c.Int, xNewQueue BaseTypeT) BaseTypeT + +//go:linkname MPUVQueueSetQueueNumber C.MPU_vQueueSetQueueNumber +func MPUVQueueSetQueueNumber(xQueue c.Int, uxQueueNumber UBaseTypeT) + +//go:linkname MPUUxQueueGetQueueNumber C.MPU_uxQueueGetQueueNumber +func MPUUxQueueGetQueueNumber(xQueue c.Int) UBaseTypeT + +//go:linkname MPUUcQueueGetQueueType C.MPU_ucQueueGetQueueType +func MPUUcQueueGetQueueType(xQueue c.Int) c.Uint8T + +/* MPU versions of timers.h API functions. */ +//go:linkname MPUXTimerCreate C.MPU_xTimerCreate +func MPUXTimerCreate(pcTimerName *c.Char, xTimerPeriodInTicks TickTypeT, uxAutoReload UBaseTypeT, pvTimerID c.Pointer, pxCallbackFunction c.Int) c.Int + +//go:linkname MPUXTimerCreateStatic C.MPU_xTimerCreateStatic +func MPUXTimerCreateStatic(pcTimerName *c.Char, xTimerPeriodInTicks TickTypeT, uxAutoReload UBaseTypeT, pvTimerID c.Pointer, pxCallbackFunction c.Int, pxTimerBuffer *StaticTimerT) c.Int + +//go:linkname MPUPvTimerGetTimerID C.MPU_pvTimerGetTimerID +func MPUPvTimerGetTimerID(xTimer c.Int) c.Pointer + +//go:linkname MPUVTimerSetTimerID C.MPU_vTimerSetTimerID +func MPUVTimerSetTimerID(xTimer c.Int, pvNewID c.Pointer) + +//go:linkname MPUXTimerIsTimerActive C.MPU_xTimerIsTimerActive +func MPUXTimerIsTimerActive(xTimer c.Int) BaseTypeT + +//go:linkname MPUXTimerGetTimerDaemonTaskHandle C.MPU_xTimerGetTimerDaemonTaskHandle +func MPUXTimerGetTimerDaemonTaskHandle() c.Int + +//go:linkname MPUXTimerPendFunctionCall C.MPU_xTimerPendFunctionCall +func MPUXTimerPendFunctionCall(xFunctionToPend c.Int, pvParameter1 c.Pointer, ulParameter2 c.Uint32T, xTicksToWait TickTypeT) BaseTypeT + +//go:linkname MPUPcTimerGetName C.MPU_pcTimerGetName +func MPUPcTimerGetName(xTimer c.Int) *c.Char + +//go:linkname MPUVTimerSetReloadMode C.MPU_vTimerSetReloadMode +func MPUVTimerSetReloadMode(xTimer c.Int, uxAutoReload UBaseTypeT) + +//go:linkname MPUUxTimerGetReloadMode C.MPU_uxTimerGetReloadMode +func MPUUxTimerGetReloadMode(xTimer c.Int) UBaseTypeT + +//go:linkname MPUXTimerGetPeriod C.MPU_xTimerGetPeriod +func MPUXTimerGetPeriod(xTimer c.Int) TickTypeT + +//go:linkname MPUXTimerGetExpiryTime C.MPU_xTimerGetExpiryTime +func MPUXTimerGetExpiryTime(xTimer c.Int) TickTypeT + +//go:linkname MPUXTimerCreateTimerTask C.MPU_xTimerCreateTimerTask +func MPUXTimerCreateTimerTask() BaseTypeT + +//go:linkname MPUXTimerGenericCommand C.MPU_xTimerGenericCommand +func MPUXTimerGenericCommand(xTimer c.Int, xCommandID BaseTypeT, xOptionalValue TickTypeT, pxHigherPriorityTaskWoken *BaseTypeT, xTicksToWait TickTypeT) BaseTypeT + +/* MPU versions of event_group.h API functions. */ +//go:linkname MPUXEventGroupCreate C.MPU_xEventGroupCreate +func MPUXEventGroupCreate() c.Int + +// llgo:link (*StaticEventGroupT).MPUXEventGroupCreateStatic C.MPU_xEventGroupCreateStatic +func (recv_ *StaticEventGroupT) MPUXEventGroupCreateStatic() c.Int { + return 0 +} + +//go:linkname MPUXEventGroupWaitBits C.MPU_xEventGroupWaitBits +func MPUXEventGroupWaitBits(xEventGroup c.Int, uxBitsToWaitFor c.Int, xClearOnExit BaseTypeT, xWaitForAllBits BaseTypeT, xTicksToWait TickTypeT) c.Int + +//go:linkname MPUXEventGroupClearBits C.MPU_xEventGroupClearBits +func MPUXEventGroupClearBits(xEventGroup c.Int, uxBitsToClear c.Int) c.Int + +//go:linkname MPUXEventGroupSetBits C.MPU_xEventGroupSetBits +func MPUXEventGroupSetBits(xEventGroup c.Int, uxBitsToSet c.Int) c.Int + +//go:linkname MPUXEventGroupSync C.MPU_xEventGroupSync +func MPUXEventGroupSync(xEventGroup c.Int, uxBitsToSet c.Int, uxBitsToWaitFor c.Int, xTicksToWait TickTypeT) c.Int + +//go:linkname MPUVEventGroupDelete C.MPU_vEventGroupDelete +func MPUVEventGroupDelete(xEventGroup c.Int) + +//go:linkname MPUUxEventGroupGetNumber C.MPU_uxEventGroupGetNumber +func MPUUxEventGroupGetNumber(xEventGroup c.Pointer) UBaseTypeT + +/* MPU versions of message/stream_buffer.h API functions. */ +//go:linkname MPUXStreamBufferSend C.MPU_xStreamBufferSend +func MPUXStreamBufferSend(xStreamBuffer c.Int, pvTxData c.Pointer, xDataLengthBytes c.SizeT, xTicksToWait TickTypeT) c.SizeT + +//go:linkname MPUXStreamBufferReceive C.MPU_xStreamBufferReceive +func MPUXStreamBufferReceive(xStreamBuffer c.Int, pvRxData c.Pointer, xBufferLengthBytes c.SizeT, xTicksToWait TickTypeT) c.SizeT + +//go:linkname MPUXStreamBufferNextMessageLengthBytes C.MPU_xStreamBufferNextMessageLengthBytes +func MPUXStreamBufferNextMessageLengthBytes(xStreamBuffer c.Int) c.SizeT + +//go:linkname MPUVStreamBufferDelete C.MPU_vStreamBufferDelete +func MPUVStreamBufferDelete(xStreamBuffer c.Int) + +//go:linkname MPUXStreamBufferIsFull C.MPU_xStreamBufferIsFull +func MPUXStreamBufferIsFull(xStreamBuffer c.Int) BaseTypeT + +//go:linkname MPUXStreamBufferIsEmpty C.MPU_xStreamBufferIsEmpty +func MPUXStreamBufferIsEmpty(xStreamBuffer c.Int) BaseTypeT + +//go:linkname MPUXStreamBufferReset C.MPU_xStreamBufferReset +func MPUXStreamBufferReset(xStreamBuffer c.Int) BaseTypeT + +//go:linkname MPUXStreamBufferSpacesAvailable C.MPU_xStreamBufferSpacesAvailable +func MPUXStreamBufferSpacesAvailable(xStreamBuffer c.Int) c.SizeT + +//go:linkname MPUXStreamBufferBytesAvailable C.MPU_xStreamBufferBytesAvailable +func MPUXStreamBufferBytesAvailable(xStreamBuffer c.Int) c.SizeT + +//go:linkname MPUXStreamBufferSetTriggerLevel C.MPU_xStreamBufferSetTriggerLevel +func MPUXStreamBufferSetTriggerLevel(xStreamBuffer c.Int, xTriggerLevel c.SizeT) BaseTypeT + +//go:linkname MPUXStreamBufferGenericCreate C.MPU_xStreamBufferGenericCreate +func MPUXStreamBufferGenericCreate(xBufferSizeBytes c.SizeT, xTriggerLevelBytes c.SizeT, xIsMessageBuffer BaseTypeT, pxSendCompletedCallback c.Int, pxReceiveCompletedCallback c.Int) c.Int + +//go:linkname MPUXStreamBufferGenericCreateStatic C.MPU_xStreamBufferGenericCreateStatic +func MPUXStreamBufferGenericCreateStatic(xBufferSizeBytes c.SizeT, xTriggerLevelBytes c.SizeT, xIsMessageBuffer BaseTypeT, pucStreamBufferStorageArea *c.Uint8T, pxStaticStreamBuffer *StaticStreamBufferT, pxSendCompletedCallback c.Int, pxReceiveCompletedCallback c.Int) c.Int diff --git a/esp32/mpu_syscall_numbers.go b/esp32/mpu_syscall_numbers.go new file mode 100644 index 00000000..f710fa70 --- /dev/null +++ b/esp32/mpu_syscall_numbers.go @@ -0,0 +1,75 @@ +package freertos + +import _ "unsafe" + +const SYSTEM_CALL_xTaskGenericNotify = 0 +const SYSTEM_CALL_xTaskGenericNotifyWait = 1 +const SYSTEM_CALL_xTimerGenericCommandFromTask = 2 +const SYSTEM_CALL_xEventGroupWaitBits = 3 +const SYSTEM_CALL_xTaskDelayUntil = 4 +const SYSTEM_CALL_xTaskAbortDelay = 5 +const SYSTEM_CALL_vTaskDelay = 6 +const SYSTEM_CALL_uxTaskPriorityGet = 7 +const SYSTEM_CALL_eTaskGetState = 8 +const SYSTEM_CALL_vTaskGetInfo = 9 +const SYSTEM_CALL_xTaskGetIdleTaskHandle = 10 +const SYSTEM_CALL_vTaskSuspend = 11 +const SYSTEM_CALL_vTaskResume = 12 +const SYSTEM_CALL_xTaskGetTickCount = 13 +const SYSTEM_CALL_uxTaskGetNumberOfTasks = 14 +const SYSTEM_CALL_ulTaskGetRunTimeCounter = 15 +const SYSTEM_CALL_ulTaskGetRunTimePercent = 16 +const SYSTEM_CALL_ulTaskGetIdleRunTimePercent = 17 +const SYSTEM_CALL_ulTaskGetIdleRunTimeCounter = 18 +const SYSTEM_CALL_vTaskSetApplicationTaskTag = 19 +const SYSTEM_CALL_xTaskGetApplicationTaskTag = 20 +const SYSTEM_CALL_vTaskSetThreadLocalStoragePointer = 21 +const SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer = 22 +const SYSTEM_CALL_uxTaskGetSystemState = 23 +const SYSTEM_CALL_uxTaskGetStackHighWaterMark = 24 +const SYSTEM_CALL_uxTaskGetStackHighWaterMark2 = 25 +const SYSTEM_CALL_xTaskGetCurrentTaskHandle = 26 +const SYSTEM_CALL_xTaskGetSchedulerState = 27 +const SYSTEM_CALL_vTaskSetTimeOutState = 28 +const SYSTEM_CALL_xTaskCheckForTimeOut = 29 +const SYSTEM_CALL_ulTaskGenericNotifyTake = 30 +const SYSTEM_CALL_xTaskGenericNotifyStateClear = 31 +const SYSTEM_CALL_ulTaskGenericNotifyValueClear = 32 +const SYSTEM_CALL_xQueueGenericSend = 33 +const SYSTEM_CALL_uxQueueMessagesWaiting = 34 +const SYSTEM_CALL_uxQueueSpacesAvailable = 35 +const SYSTEM_CALL_xQueueReceive = 36 +const SYSTEM_CALL_xQueuePeek = 37 +const SYSTEM_CALL_xQueueSemaphoreTake = 38 +const SYSTEM_CALL_xQueueGetMutexHolder = 39 +const SYSTEM_CALL_xQueueTakeMutexRecursive = 40 +const SYSTEM_CALL_xQueueGiveMutexRecursive = 41 +const SYSTEM_CALL_xQueueSelectFromSet = 42 +const SYSTEM_CALL_xQueueAddToSet = 43 +const SYSTEM_CALL_vQueueAddToRegistry = 44 +const SYSTEM_CALL_vQueueUnregisterQueue = 45 +const SYSTEM_CALL_pcQueueGetName = 46 +const SYSTEM_CALL_pvTimerGetTimerID = 47 +const SYSTEM_CALL_vTimerSetTimerID = 48 +const SYSTEM_CALL_xTimerIsTimerActive = 49 +const SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle = 50 +const SYSTEM_CALL_pcTimerGetName = 51 +const SYSTEM_CALL_vTimerSetReloadMode = 52 +const SYSTEM_CALL_xTimerGetReloadMode = 53 +const SYSTEM_CALL_uxTimerGetReloadMode = 54 +const SYSTEM_CALL_xTimerGetPeriod = 55 +const SYSTEM_CALL_xTimerGetExpiryTime = 56 +const SYSTEM_CALL_xEventGroupClearBits = 57 +const SYSTEM_CALL_xEventGroupSetBits = 58 +const SYSTEM_CALL_xEventGroupSync = 59 +const SYSTEM_CALL_uxEventGroupGetNumber = 60 +const SYSTEM_CALL_vEventGroupSetNumber = 61 +const SYSTEM_CALL_xStreamBufferSend = 62 +const SYSTEM_CALL_xStreamBufferReceive = 63 +const SYSTEM_CALL_xStreamBufferIsFull = 64 +const SYSTEM_CALL_xStreamBufferIsEmpty = 65 +const SYSTEM_CALL_xStreamBufferSpacesAvailable = 66 +const SYSTEM_CALL_xStreamBufferBytesAvailable = 67 +const SYSTEM_CALL_xStreamBufferSetTriggerLevel = 68 +const SYSTEM_CALL_xStreamBufferNextMessageLengthBytes = 69 +const NUM_SYSTEM_CALLS = 70 diff --git a/esp32/mpu_types.go b/esp32/mpu_types.go new file mode 100644 index 00000000..31e9779e --- /dev/null +++ b/esp32/mpu_types.go @@ -0,0 +1,15 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type MpuAccessT c.Int + +const ( + MPU_REGION_ILLEGAL MpuAccessT = 0 + MPU_REGION_RW MpuAccessT = 1 + MPU_REGION_X MpuAccessT = 2 + MPU_REGION_RWX MpuAccessT = 3 +) diff --git a/esp32/mpu_wrappers.go b/esp32/mpu_wrappers.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/mpu_wrappers.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/mpuasm.go b/esp32/mpuasm.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/mpuasm.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/mspi_timing_config.go b/esp32/mspi_timing_config.go new file mode 100644 index 00000000..efd40789 --- /dev/null +++ b/esp32/mspi_timing_config.go @@ -0,0 +1,29 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/*------------------------------------------------------------------------------------------------- + * Generic Config APIs + *-------------------------------------------------------------------------------------------------*/ +/** + * @brief Set Flash module clock + * + * @param flash_freq_mhz Flash clock frequency in MHz + * @param speed_mode Speed mode + * @param control_both_mspi Control SPI1 as well + */ +//go:linkname MspiTimingConfigSetFlashClock C.mspi_timing_config_set_flash_clock +func MspiTimingConfigSetFlashClock(flash_freq_mhz c.Uint32T, speed_mode MspiTimingSpeedModeT, control_both_mspi bool) + +/** + * @brief Set PSRAM module clock + * + * @param psram_freq_mhz PSRAM clock frequency in MHz + * @param speed_mode Speed mode + * @param control_both_mspi Not used, for compatibility + */ +//go:linkname MspiTimingConfigSetPsramClock C.mspi_timing_config_set_psram_clock +func MspiTimingConfigSetPsramClock(psram_freq_mhz c.Uint32T, speed_mode MspiTimingSpeedModeT, control_both_mspi bool) diff --git a/esp32/mspi_timing_tuning.go b/esp32/mspi_timing_tuning.go new file mode 100644 index 00000000..2c2637c4 --- /dev/null +++ b/esp32/mspi_timing_tuning.go @@ -0,0 +1,45 @@ +package freertos + +import _ "unsafe" + +/** + * @brief Make MSPI work under 20Mhz, remove the timing tuning required delays. + * @param control_spi1 Select whether to control SPI1. For tuning, we need to use SPI1. After tuning (during startup stage), let the flash driver to control SPI1 + */ +//go:linkname MspiTimingEnterLowSpeedMode C.mspi_timing_enter_low_speed_mode +func MspiTimingEnterLowSpeedMode(control_spi1 bool) + +/** + * @brief Make MSPI work under the frequency as users set, may add certain delays to MSPI RX direction to meet timing requirements. + * @param control_spi1 Select whether to control SPI1. For tuning, we need to use SPI1. After tuning (during startup stage), let the flash driver to control SPI1 + */ +//go:linkname MspiTimingEnterHighSpeedMode C.mspi_timing_enter_high_speed_mode +func MspiTimingEnterHighSpeedMode(control_spi1 bool) + +/** + * @brief Switch MSPI into low speed mode / high speed mode. + * @note This API is cache safe, it will freeze both D$ and I$ and restore them after MSPI is switched + * @note For some of the MSPI high frequency settings (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required. + * Certain delays will be added to the MSPI RX direction. When CPU clock switches from PLL to XTAL, should call + * this API first to enter MSPI low speed mode to remove the delays, and vice versa. + */ +//go:linkname MspiTimingChangeSpeedModeCacheSafe C.mspi_timing_change_speed_mode_cache_safe +func MspiTimingChangeSpeedModeCacheSafe(switch_down bool) + +/** + * @brief Tune MSPI flash timing to make it work under high frequency + */ +//go:linkname MspiTimingFlashTuning C.mspi_timing_flash_tuning +func MspiTimingFlashTuning() + +/** + * @brief Tune MSPI psram timing to make it work under high frequency + */ +//go:linkname MspiTimingPsramTuning C.mspi_timing_psram_tuning +func MspiTimingPsramTuning() + +/** + * @brief Set MSPI pin default pin drive + */ +//go:linkname MspiTimingSetPinDriveStrength C.mspi_timing_set_pin_drive_strength +func MspiTimingSetPinDriveStrength() diff --git a/esp32/mspi_timing_tuning_ll.go b/esp32/mspi_timing_tuning_ll.go new file mode 100644 index 00000000..d68b79a8 --- /dev/null +++ b/esp32/mspi_timing_tuning_ll.go @@ -0,0 +1,22 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const MSPI_TIMING_LL_FLASH_SLOW_MODE_MASK = 0 +const MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT = 80 +const MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED = 1 + +type MspiTimingLlFlashModeT c.Int + +const ( + MSPI_TIMING_LL_FLASH_OPI_MODE MspiTimingLlFlashModeT = 1 + MSPI_TIMING_LL_FLASH_QIO_MODE MspiTimingLlFlashModeT = 2 + MSPI_TIMING_LL_FLASH_QUAD_MODE MspiTimingLlFlashModeT = 4 + MSPI_TIMING_LL_FLASH_DIO_MODE MspiTimingLlFlashModeT = 8 + MSPI_TIMING_LL_FLASH_DUAL_MODE MspiTimingLlFlashModeT = 16 + MSPI_TIMING_LL_FLASH_FAST_MODE MspiTimingLlFlashModeT = 32 + MSPI_TIMING_LL_FLASH_SLOW_MODE MspiTimingLlFlashModeT = 64 +) diff --git a/esp32/mspi_timing_types.go b/esp32/mspi_timing_types.go new file mode 100644 index 00000000..0b517f58 --- /dev/null +++ b/esp32/mspi_timing_types.go @@ -0,0 +1,13 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type MspiTimingSpeedModeT c.Int + +const ( + MSPI_TIMING_SPEED_MODE_LOW_PERF MspiTimingSpeedModeT = 0 + MSPI_TIMING_SPEED_MODE_NORMAL_PERF MspiTimingSpeedModeT = 1 +) diff --git a/esp32/multi_heap.go b/esp32/multi_heap.go new file mode 100644 index 00000000..b0b43b18 --- /dev/null +++ b/esp32/multi_heap.go @@ -0,0 +1,225 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type MultiHeapInfo struct { + Unused [8]uint8 +} +type MultiHeapHandleT *MultiHeapInfo + +/** + * @brief allocate a chunk of memory with specific alignment + * + * @param heap Handle to a registered heap. + * @param size size in bytes of memory chunk + * @param alignment how the memory must be aligned + * + * @return pointer to the memory allocated, NULL on failure + */ +//go:linkname MultiHeapAlignedAlloc C.multi_heap_aligned_alloc +func MultiHeapAlignedAlloc(heap MultiHeapHandleT, size c.SizeT, alignment c.SizeT) c.Pointer + +/** @brief malloc() a buffer in a given heap + * + * Semantics are the same as standard malloc(), only the returned buffer will be allocated in the specified heap. + * + * @param heap Handle to a registered heap. + * @param size Size of desired buffer. + * + * @return Pointer to new memory, or NULL if allocation fails. + */ +//go:linkname MultiHeapMalloc C.multi_heap_malloc +func MultiHeapMalloc(heap MultiHeapHandleT, size c.SizeT) c.Pointer + +/** @brief free() a buffer aligned in a given heap. + * + * @param heap Handle to a registered heap. + * @param p NULL, or a pointer previously returned from multi_heap_aligned_alloc() for the same heap. + * @note This function is deprecated, consider using multi_heap_free() instead + */ +//go:linkname MultiHeapAlignedFree C.multi_heap_aligned_free +func MultiHeapAlignedFree(heap MultiHeapHandleT, p c.Pointer) + +/** @brief free() a buffer in a given heap. + * + * Semantics are the same as standard free(), only the argument 'p' must be NULL or have been allocated in the specified heap. + * + * @param heap Handle to a registered heap. + * @param p NULL, or a pointer previously returned from multi_heap_malloc() or multi_heap_realloc() for the same heap. + */ +//go:linkname MultiHeapFree C.multi_heap_free +func MultiHeapFree(heap MultiHeapHandleT, p c.Pointer) + +/** @brief realloc() a buffer in a given heap. + * + * Semantics are the same as standard realloc(), only the argument 'p' must be NULL or have been allocated in the specified heap. + * + * @param heap Handle to a registered heap. + * @param p NULL, or a pointer previously returned from multi_heap_malloc() or multi_heap_realloc() for the same heap. + * @param size Desired new size for buffer. + * + * @return New buffer of 'size' containing contents of 'p', or NULL if reallocation failed. + */ +//go:linkname MultiHeapRealloc C.multi_heap_realloc +func MultiHeapRealloc(heap MultiHeapHandleT, p c.Pointer, size c.SizeT) c.Pointer + +/** @brief Return the size that a particular pointer was allocated with. + * + * @param heap Handle to a registered heap. + * @param p Pointer, must have been previously returned from multi_heap_malloc() or multi_heap_realloc() for the same heap. + * + * @return Size of the memory allocated at this block. May be more than the original size argument, due + * to padding and minimum block sizes. + */ +//go:linkname MultiHeapGetAllocatedSize C.multi_heap_get_allocated_size +func MultiHeapGetAllocatedSize(heap MultiHeapHandleT, p c.Pointer) c.SizeT + +/** @brief Register a new heap for use + * + * This function initialises a heap at the specified address, and returns a handle for future heap operations. + * + * There is no equivalent function for deregistering a heap - if all blocks in the heap are free, you can immediately start using the memory for other purposes. + * + * @param start Start address of the memory to use for a new heap. + * @param size Size (in bytes) of the new heap. + * + * @return Handle of a new heap ready for use, or NULL if the heap region was too small to be initialised. + */ +//go:linkname MultiHeapRegister C.multi_heap_register +func MultiHeapRegister(start c.Pointer, size c.SizeT) MultiHeapHandleT + +/** @brief Associate a private lock pointer with a heap + * + * The lock argument is supplied to the MULTI_HEAP_LOCK() and MULTI_HEAP_UNLOCK() macros, defined in multi_heap_platform.h. + * + * The lock in question must be recursive. + * + * When the heap is first registered, the associated lock is NULL. + * + * @param heap Handle to a registered heap. + * @param lock Optional pointer to a locking structure to associate with this heap. + */ +//go:linkname MultiHeapSetLock C.multi_heap_set_lock +func MultiHeapSetLock(heap MultiHeapHandleT, lock c.Pointer) + +/** @brief Dump heap information to stdout + * + * For debugging purposes, this function dumps information about every block in the heap to stdout. + * + * @param heap Handle to a registered heap. + */ +//go:linkname MultiHeapDump C.multi_heap_dump +func MultiHeapDump(heap MultiHeapHandleT) + +/** @brief Check heap integrity + * + * Walks the heap and checks all heap data structures are valid. If any errors are detected, an error-specific message + * can be optionally printed to stderr. Print behaviour can be overridden at compile time by defining + * MULTI_CHECK_FAIL_PRINTF in multi_heap_platform.h. + * + * @note This function is not thread-safe as it sets a global variable with the value of print_errors. + * + * @param heap Handle to a registered heap. + * @param print_errors If true, errors will be printed to stderr. + * @return true if heap is valid, false otherwise. + */ +//go:linkname MultiHeapCheck C.multi_heap_check +func MultiHeapCheck(heap MultiHeapHandleT, print_errors bool) bool + +/** @brief Return free heap size + * + * Returns the number of bytes available in the heap. + * + * Equivalent to the total_free_bytes member returned by multi_heap_get_heap_info(). + * + * Note that the heap may be fragmented, so the actual maximum size for a single malloc() may be lower. To know this + * size, see the largest_free_block member returned by multi_heap_get_heap_info(). + * + * @param heap Handle to a registered heap. + * @return Number of free bytes. + */ +//go:linkname MultiHeapFreeSize C.multi_heap_free_size +func MultiHeapFreeSize(heap MultiHeapHandleT) c.SizeT + +/** @brief Return the lifetime minimum free heap size + * + * Equivalent to the minimum_free_bytes member returned by multi_heap_get_info(). + * + * Returns the lifetime "low watermark" of possible values returned from multi_free_heap_size(), for the specified + * heap. + * + * @param heap Handle to a registered heap. + * @return Number of free bytes. + */ +//go:linkname MultiHeapMinimumFreeSize C.multi_heap_minimum_free_size +func MultiHeapMinimumFreeSize(heap MultiHeapHandleT) c.SizeT + +/** @brief Structure to access heap metadata via multi_heap_get_info */ + +type MultiHeapInfoT struct { + TotalFreeBytes c.SizeT + TotalAllocatedBytes c.SizeT + LargestFreeBlock c.SizeT + MinimumFreeBytes c.SizeT + AllocatedBlocks c.SizeT + FreeBlocks c.SizeT + TotalBlocks c.SizeT +} + +/** @brief Return metadata about a given heap + * + * Fills a multi_heap_info_t structure with information about the specified heap. + * + * @param heap Handle to a registered heap. + * @param info Pointer to a structure to fill with heap metadata. + */ +//go:linkname MultiHeapGetInfo C.multi_heap_get_info +func MultiHeapGetInfo(heap MultiHeapHandleT, info *MultiHeapInfoT) + +/** + * @brief Perform an aligned allocation from the provided offset + * + * @param heap The heap in which to perform the allocation + * @param size The size of the allocation + * @param alignment How the memory must be aligned + * @param offset The offset at which the alignment should start + * @return void* The ptr to the allocated memory + */ +//go:linkname MultiHeapAlignedAllocOffs C.multi_heap_aligned_alloc_offs +func MultiHeapAlignedAllocOffs(heap MultiHeapHandleT, size c.SizeT, alignment c.SizeT, offset c.SizeT) c.Pointer + +/** + * @brief Reset the minimum_free_bytes value (setting it to free_bytes) and return the former value + * + * @param heap The heap in which the reset is taking place + * @return size_t the value of minimum_free_bytes before it is reset + */ +//go:linkname MultiHeapResetMinimumFreeBytes C.multi_heap_reset_minimum_free_bytes +func MultiHeapResetMinimumFreeBytes(heap MultiHeapHandleT) c.SizeT + +/** + * @brief Set the value of minimum_free_bytes to new_minimum_free_bytes_value or keep + * the current value of minimum_free_bytes if it is smaller than new_minimum_free_bytes_value + * + * @param heap The heap in which the restore is taking place + * @param new_minimum_free_bytes_value The value to restore the minimum_free_bytes to + */ +//go:linkname MultiHeapRestoreMinimumFreeBytes C.multi_heap_restore_minimum_free_bytes +func MultiHeapRestoreMinimumFreeBytes(heap MultiHeapHandleT, new_minimum_free_bytes_value c.SizeT) + +// llgo:type C +type MultiHeapWalkerCbT func(c.Pointer, c.SizeT, c.Int, c.Pointer) bool + +/** + * @brief Call the tlsf_walk_pool function of the heap given as parameter with + * the walker function passed as parameter + * + * @param heap The heap to traverse + * @param walker_func The walker to trigger on each block of the heap + * @param user_data Opaque pointer to user defined data + */ +//go:linkname MultiHeapWalk C.multi_heap_walk +func MultiHeapWalk(heap MultiHeapHandleT, walker_func MultiHeapWalkerCbT, user_data c.Pointer) diff --git a/esp32/mwdt_ll.go b/esp32/mwdt_ll.go new file mode 100644 index 00000000..e8619e62 --- /dev/null +++ b/esp32/mwdt_ll.go @@ -0,0 +1,18 @@ +package freertos + +import _ "unsafe" + +const MWDT_LL_DEFAULT_CLK_PRESCALER = 40000 +const MWDT_LL_WKEY_VALUE = 0x50D83AA1 +const MWDT_LL_STG_SEL_OFF = 0 +const MWDT_LL_STG_SEL_INT = 1 +const MWDT_LL_STG_SEL_RESET_CPU = 2 +const MWDT_LL_STG_SEL_RESET_SYSTEM = 3 +const MWDT_LL_RESET_LENGTH_100_NS = 0 +const MWDT_LL_RESET_LENGTH_200_NS = 1 +const MWDT_LL_RESET_LENGTH_300_NS = 2 +const MWDT_LL_RESET_LENGTH_400_NS = 3 +const MWDT_LL_RESET_LENGTH_500_NS = 4 +const MWDT_LL_RESET_LENGTH_800_NS = 5 +const MWDT_LL_RESET_LENGTH_1600_NS = 6 +const MWDT_LL_RESET_LENGTH_3200_NS = 7 diff --git a/esp32/nrx_reg.go b/esp32/nrx_reg.go new file mode 100644 index 00000000..1296ce72 --- /dev/null +++ b/esp32/nrx_reg.go @@ -0,0 +1,20 @@ +package freertos + +import _ "unsafe" + +const NRX_CHAN_EST_FORCE_PU_V = 1 +const NRX_CHAN_EST_FORCE_PU_S = 7 +const NRX_CHAN_EST_FORCE_PD_V = 1 +const NRX_CHAN_EST_FORCE_PD_S = 6 +const NRX_RX_ROT_FORCE_PU_V = 1 +const NRX_RX_ROT_FORCE_PU_S = 5 +const NRX_RX_ROT_FORCE_PD_V = 1 +const NRX_RX_ROT_FORCE_PD_S = 4 +const NRX_VIT_FORCE_PU_V = 1 +const NRX_VIT_FORCE_PU_S = 3 +const NRX_VIT_FORCE_PD_V = 1 +const NRX_VIT_FORCE_PD_S = 2 +const NRX_DEMAP_FORCE_PU_V = 1 +const NRX_DEMAP_FORCE_PU_S = 1 +const NRX_DEMAP_FORCE_PD_V = 1 +const NRX_DEMAP_FORCE_PD_S = 0 diff --git a/esp32/opi_flash.go b/esp32/opi_flash.go new file mode 100644 index 00000000..05a5d017 --- /dev/null +++ b/esp32/opi_flash.go @@ -0,0 +1,290 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const FLASH_OP_MODE_RDCMD_DOUT = 0x3B +const ESP_ROM_FLASH_SECTOR_SIZE = 0x1000 +const ESP_ROM_FLASH_BLOCK_SIZE_64K = 0x10000 +const ESP_ROM_FLASH_PAGE_SIZE = 256 +const ROM_FLASH_CMD_RDID = 0x9F +const ROM_FLASH_CMD_WRSR = 0x01 +const ROM_FLASH_CMD_WRSR2 = 0x31 +const ROM_FLASH_CMD_WREN = 0x06 +const ROM_FLASH_CMD_WRDI = 0x04 +const ROM_FLASH_CMD_RDSR = 0x05 +const ROM_FLASH_CMD_RDSR2 = 0x35 +const ROM_FLASH_CMD_ERASE_SEC = 0x20 +const ROM_FLASH_CMD_ERASE_BLK_32K = 0x52 +const ROM_FLASH_CMD_ERASE_BLK_64K = 0xD8 +const ROM_FLASH_CMD_OTPEN = 0x3A +const ROM_FLASH_CMD_RSTEN = 0x66 +const ROM_FLASH_CMD_RST = 0x99 +const ROM_FLASH_CMD_SE4B = 0x21 +const ROM_FLASH_CMD_SE4B_OCT = 0xDE21 +const ROM_FLASH_CMD_BE4B = 0xDC +const ROM_FLASH_CMD_BE4B_OCT = 0x23DC +const ROM_FLASH_CMD_RSTEN_OCT = 0x9966 +const ROM_FLASH_CMD_RST_OCT = 0x6699 +const ROM_FLASH_CMD_FSTRD4B_STR = 0x13EC +const ROM_FLASH_CMD_FSTRD4B_DTR = 0x11EE +const ROM_FLASH_CMD_FSTRD4B = 0x0C +const ROM_FLASH_CMD_PP4B = 0x12 +const ROM_FLASH_CMD_PP4B_OCT = 0xED12 +const ROM_FLASH_CMD_RDID_OCT = 0x609F +const ROM_FLASH_CMD_WREN_OCT = 0xF906 +const ROM_FLASH_CMD_RDSR_OCT = 0xFA05 +const ROM_FLASH_CMD_RDCR2 = 0x71 +const ROM_FLASH_CMD_RDCR2_OCT = 0x8E71 +const ROM_FLASH_CMD_WRCR2 = 0x72 +const ROM_FLASH_CMD_WRCR2_OCT = 0x8D72 +const ROM_FLASH_CMD_RDFSR_GD = 0x70 +const ROM_FLASH_CMD_RD_GD = 0x03 +const ROM_FLASH_CMD_RD4B_GD = 0x13 +const ROM_FLASH_CMD_FSTRD_GD = 0x0B +const ROM_FLASH_CMD_FSTRD4B_GD = 0x0C +const ROM_FLASH_CMD_FSTRD_OOUT_GD = 0x8B +const ROM_FLASH_CMD_FSTRD4B_OOUT_GD = 0x7C +const ROM_FLASH_CMD_FSTRD_OIOSTR_GD = 0xCB +const ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD = 0xCC +const ROM_FLASH_CMD_FSTRD4B_OIODTR_GD = 0xFD +const ROM_FLASH_CMD_PP_GD = 0x02 +const ROM_FLASH_CMD_PP4B_GD = 0x12 +const ROM_FLASH_CMD_PP_OOUT_GD = 0x82 +const ROM_FLASH_CMD_PP4B_OOUT_GD = 0x84 +const ROM_FLASH_CMD_PP_OIO_GD = 0xC2 +const ROM_FLASH_CMD_PP4B_OIOSTR_GD = 0x8E +const ROM_FLASH_CMD_SE_GD = 0x20 +const ROM_FLASH_CMD_SE4B_GD = 0x21 +const ROM_FLASH_CMD_BE32K_GD = 0x52 +const ROM_FLASH_CMD_BE32K4B_GD = 0x5C +const ROM_FLASH_CMD_BE64K_GD = 0xD8 +const ROM_FLASH_CMD_BE64K4B_GD = 0xDC +const ROM_FLASH_CMD_EN4B_GD = 0xB7 +const ROM_FLASH_CMD_DIS4B_GD = 0xE9 + +type EspRomOpiflashCmdT struct { + Mode c.Uint8T + CmdBitLen c.Uint8T + Cmd c.Uint16T + Addr c.Uint32T + AddrBitLen c.Uint8T + DummyBitLen c.Uint8T + DataBitLen c.Uint8T + CsSel c.Uint8T + IsPe c.Uint8T +} + +type EspRomOpiflashSpi0rdT struct { + AddrBitLen c.Uint8T + DummyBitLen c.Uint8T + Cmd c.Uint16T + CmdBitLen c.Uint8T + VarDummyEn c.Uint8T +} + +type EspRomOpiflashDefT struct { + Rdid EspRomOpiflashCmdT + Rdsr EspRomOpiflashCmdT + Wren EspRomOpiflashCmdT + Se EspRomOpiflashCmdT + Be64k EspRomOpiflashCmdT + Read EspRomOpiflashCmdT + Pp EspRomOpiflashCmdT + CacheRdCmd EspRomOpiflashSpi0rdT +} + +type EspRomSpiCmdT struct { + Cmd c.Uint16T + CmdBitLen c.Uint16T + Addr *c.Uint32T + AddrBitLen c.Uint32T + TxData *c.Uint32T + TxDataBitLen c.Uint32T + RxData *c.Uint32T + RxDataBitLen c.Uint32T + DummyBitLen c.Uint32T +} + +/** + * @brief init legacy driver for Octal Flash + */ +// llgo:link (*EspRomOpiflashDefT).EspRomOpiflashLegacyDriverInit C.esp_rom_opiflash_legacy_driver_init +func (recv_ *EspRomOpiflashDefT) EspRomOpiflashLegacyDriverInit() { +} + +// spi user mode command config +/** + * @brief Config the spi user command + * @param spi_num spi port + * @param pcmd pointer to accept the spi command struct + */ +//go:linkname EspRomSpiCmdConfig C.esp_rom_spi_cmd_config +func EspRomSpiCmdConfig(spi_num c.Int, pcmd *EspRomSpiCmdT) + +/** + * @brief Start a spi user command sequence + * @param spi_num spi port + * @param rx_buf buffer pointer to receive data + * @param rx_len receive data length in byte + * @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 + * @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission + */ +//go:linkname EspRomSpiCmdStart C.esp_rom_spi_cmd_start +func EspRomSpiCmdStart(spi_num c.Int, rx_buf *c.Uint8T, rx_len c.Uint16T, cs_en_mask c.Uint8T, is_write_erase bool) + +/** + * @brief Config opi flash pads according to efuse settings. + */ +//go:linkname EspRomOpiflashPinConfig C.esp_rom_opiflash_pin_config +func EspRomOpiflashPinConfig() + +// set SPI read/write mode +/** + * @brief Set SPI operation mode + * @param spi_num spi port + * @param mode Flash Read Mode + */ +//go:linkname EspRomSpiSetOpMode C.esp_rom_spi_set_op_mode +func EspRomSpiSetOpMode(spi_num c.Int, mode EspRomSpiflashReadModeT) + +/** + * @brief Set data swap mode in DTR(DDR) mode + * @param spi_num spi port + * @param wr_swap to decide whether to swap fifo data in dtr write operation + * @param rd_swap to decide whether to swap fifo data in dtr read operation + */ +//go:linkname EspRomSpiSetDtrSwapMode C.esp_rom_spi_set_dtr_swap_mode +func EspRomSpiSetDtrSwapMode(spi c.Int, wr_swap bool, rd_swap bool) + +/** + * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) + * @param spi_num spi port + */ +//go:linkname EspRomOpiflashModeReset C.esp_rom_opiflash_mode_reset +func EspRomOpiflashModeReset(spi_num c.Int) + +/** + * @brief To execute a flash operation command + * @param spi_num spi port + * @param mode Flash Read Mode + * @param cmd data to send in command field + * @param cmd_bit_len bit length of command field + * @param addr data to send in address field + * @param addr_bit_len bit length of address field + * @param dummy_bits bit length of dummy field + * @param mosi_data data buffer to be sent in mosi field + * @param mosi_bit_len bit length of data buffer to be sent in mosi field + * @param miso_data data buffer to accept data in miso field + * @param miso_bit_len bit length of data buffer to accept data in miso field + * @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1 + * @param is_write_erase_operation to indicate whether this a write or erase flash operation + */ +//go:linkname EspRomOpiflashExecCmd C.esp_rom_opiflash_exec_cmd +func EspRomOpiflashExecCmd(spi_num c.Int, mode EspRomSpiflashReadModeT, cmd c.Uint32T, cmd_bit_len c.Int, addr c.Uint32T, addr_bit_len c.Int, dummy_bits c.Int, mosi_data *c.Uint8T, mosi_bit_len c.Int, miso_data *c.Uint8T, miso_bit_len c.Int, cs_mask c.Uint32T, is_write_erase_operation bool) + +/** + * @brief send reset command to opi flash + * @param spi_num spi port + * @param mode Flash Operation Mode + */ +//go:linkname EspRomOpiflashSoftReset C.esp_rom_opiflash_soft_reset +func EspRomOpiflashSoftReset(spi_num c.Int, mode EspRomSpiflashReadModeT) + +/** + * @brief to read opi flash ID + * @note command format would be defined in initialization + * @param[out] out_id buffer to accept id + * @return flash operation result + */ +//go:linkname EspRomOpiflashReadId C.esp_rom_opiflash_read_id +func EspRomOpiflashReadId(out_id *c.Uint8T) EspRomSpiflashResultT + +/** + * @brief to read opi flash status register + * @note command format would be defined in initialization + * @return opi flash status value + */ +//go:linkname EspRomOpiflashRdsr C.esp_rom_opiflash_rdsr +func EspRomOpiflashRdsr() c.Uint8T + +/** + * @brief wait opi flash status register to be idle + * @note command format would be defined in initialization + * @return flash operation result + */ +//go:linkname EspRomOpiflashWaitIdle C.esp_rom_opiflash_wait_idle +func EspRomOpiflashWaitIdle() EspRomSpiflashResultT + +/** + * @brief to erase flash sector + * @note command format would be defined in initialization + * @param sector_num the sector to be erased + * @return flash operation result + */ +//go:linkname EspRomOpiflashEraseSector C.esp_rom_opiflash_erase_sector +func EspRomOpiflashEraseSector(sector_num c.Uint32T) EspRomSpiflashResultT + +/** + * @brief to erase flash block + * @note command format would be defined in initialization + * @param block_num the block to be erased + * @return flash operation result + */ +//go:linkname EspRomOpiflashEraseBlock64k C.esp_rom_opiflash_erase_block_64k +func EspRomOpiflashEraseBlock64k(block_num c.Uint32T) EspRomSpiflashResultT + +/** + * @brief to erase a flash area define by start address and length + * @note command format would be defined in initialization + * @param start_addr the start address to be erased + * @param area_len the erea length to be erased + * @return flash operation result + */ +//go:linkname EspRomOpiflashEraseArea C.esp_rom_opiflash_erase_area +func EspRomOpiflashEraseArea(start_addr c.Uint32T, area_len c.Uint32T) EspRomSpiflashResultT + +/** + * @brief to read data from opi flash + * @note command format would be defined in initialization + * @param flash_addr flash address to read data from + * @param data_addr data buffer to accept the data + * @param len data length to be read + * @return flash operation result + */ +//go:linkname EspRomOpiflashRead C.esp_rom_opiflash_read +func EspRomOpiflashRead(flash_addr c.Uint32T, data_addr c.Pointer, len c.Int) EspRomSpiflashResultT + +/** + * @brief to write data to opi flash + * @note command format would be defined in initialization + * @param flash_addr flash address to write data to + * @param data_addr data buffer to write to flash + * @param len data length to write + * @return flash operation result + */ +//go:linkname EspRomOpiflashWrite C.esp_rom_opiflash_write +func EspRomOpiflashWrite(flash_addr c.Uint32T, data_addr *c.Uint32T, len c.Int) EspRomSpiflashResultT + +/** + * @brief send WREN command + * @note command format would be defined in initialization + * @param arg not used, set to NULL + * @return flash operation result + */ +//go:linkname EspRomOpiflashWren C.esp_rom_opiflash_wren +func EspRomOpiflashWren(arg c.Pointer) EspRomSpiflashResultT + +/** + * @brief to configure SPI0 read flash command format for cache + * @note command format would be defined in initialization + * + */ +// llgo:link EspRomSpiflashReadModeT.EspRomOpiflashCacheModeConfig C.esp_rom_opiflash_cache_mode_config +func (recv_ EspRomSpiflashReadModeT) EspRomOpiflashCacheModeConfig(cache *EspRomOpiflashSpi0rdT) { +} + +//go:linkname EspRomOpiflashReadRaw C.esp_rom_opiflash_read_raw +func EspRomOpiflashReadRaw(flash_addr c.Uint32T, buf *c.Uint8T, len c.Int) EspRomSpiflashResultT diff --git a/esp32/panic_internal.go b/esp32/panic_internal.go new file mode 100644 index 00000000..79f874e1 --- /dev/null +++ b/esp32/panic_internal.go @@ -0,0 +1,75 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:type C +type PanicInfoDumpFnT func(c.Pointer) +type PanicExceptionT c.Int + +const ( + PANIC_EXCEPTION_DEBUG PanicExceptionT = 0 + PANIC_EXCEPTION_IWDT PanicExceptionT = 1 + PANIC_EXCEPTION_TWDT PanicExceptionT = 2 + PANIC_EXCEPTION_ABORT PanicExceptionT = 3 + PANIC_EXCEPTION_FAULT PanicExceptionT = 4 +) + +type PanicInfoT struct { + Core c.Int + Exception PanicExceptionT + Reason *c.Char + Description *c.Char + Details PanicInfoDumpFnT + State PanicInfoDumpFnT + Addr c.Pointer + Frame c.Pointer + PseudoExcause bool +} + +// Create own print functions, since printf might be broken, and can be silenced +// when CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT +// +//go:linkname PanicPrintChar C.panic_print_char +func PanicPrintChar(c c.Char) + +//go:linkname PanicPrintStr C.panic_print_str +func PanicPrintStr(str *c.Char) + +//go:linkname PanicPrintDec C.panic_print_dec +func PanicPrintDec(d c.Int) + +//go:linkname PanicPrintHex C.panic_print_hex +func PanicPrintHex(h c.Int) + +//go:linkname PanicAbort C.panic_abort +func PanicAbort(details *c.Char) + +//go:linkname PanicArchFillInfo C.panic_arch_fill_info +func PanicArchFillInfo(frame c.Pointer, info *PanicInfoT) + +//go:linkname PanicSocFillInfo C.panic_soc_fill_info +func PanicSocFillInfo(frame c.Pointer, info *PanicInfoT) + +//go:linkname PanicSocCheckPseudoCause C.panic_soc_check_pseudo_cause +func PanicSocCheckPseudoCause(f c.Pointer, info *PanicInfoT) bool + +//go:linkname PanicPrintRegisters C.panic_print_registers +func PanicPrintRegisters(frame c.Pointer, core c.Int) + +//go:linkname PanicPrintBacktrace C.panic_print_backtrace +func PanicPrintBacktrace(frame c.Pointer, core c.Int) + +//go:linkname PanicGetAddress C.panic_get_address +func PanicGetAddress(frame c.Pointer) c.Uint32T + +//go:linkname PanicSetAddress C.panic_set_address +func PanicSetAddress(frame c.Pointer, addr c.Uint32T) + +//go:linkname PanicGetCause C.panic_get_cause +func PanicGetCause(frame c.Pointer) c.Uint32T + +//go:linkname PanicPrepareFrameFromCtx C.panic_prepare_frame_from_ctx +func PanicPrepareFrameFromCtx(frame c.Pointer) diff --git a/esp32/panic_reason.go b/esp32/panic_reason.go new file mode 100644 index 00000000..b14e1c5c --- /dev/null +++ b/esp32/panic_reason.go @@ -0,0 +1,13 @@ +package freertos + +import _ "unsafe" + +const PANIC_RSN_NONE = 0 +const PANIC_RSN_DEBUGEXCEPTION = 1 +const PANIC_RSN_DOUBLEEXCEPTION = 2 +const PANIC_RSN_KERNELEXCEPTION = 3 +const PANIC_RSN_COPROCEXCEPTION = 4 +const PANIC_RSN_INTWDT_CPU0 = 5 +const PANIC_RSN_INTWDT_CPU1 = 6 +const PANIC_RSN_CACHEERR = 7 +const PANIC_RSN_MAX = 7 diff --git a/esp32/parlio_hal.go b/esp32/parlio_hal.go new file mode 100644 index 00000000..d47a9f25 --- /dev/null +++ b/esp32/parlio_hal.go @@ -0,0 +1,34 @@ +package freertos + +import _ "unsafe" + +type ParlIoDevT struct { + Unused [8]uint8 +} +type ParlioSocHandleT *ParlIoDevT + +/** + * @brief HAL context type of Parallel IO driver + */ + +type ParlioHalContextT struct { + Regs ParlioSocHandleT +} + +/** + * @brief Initialize the Parallel IO HAL driver + * + * @param hal: Parallel IO HAL context + */ +// llgo:link (*ParlioHalContextT).ParlioHalInit C.parlio_hal_init +func (recv_ *ParlioHalContextT) ParlioHalInit() { +} + +/** + * @brief Deinitialize the Parallel IO HAL driver + * + * @param hal: Parallel IO HAL context + */ +// llgo:link (*ParlioHalContextT).ParlioHalDeinit C.parlio_hal_deinit +func (recv_ *ParlioHalContextT) ParlioHalDeinit() { +} diff --git a/esp32/parlio_types.go b/esp32/parlio_types.go new file mode 100644 index 00000000..1f3a4a75 --- /dev/null +++ b/esp32/parlio_types.go @@ -0,0 +1,25 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const PARLIO_TX_UNIT_MAX_DATA_WIDTH = 0 +const PARLIO_RX_UNIT_MAX_DATA_WIDTH = 0 + +type ParlioSampleEdgeT c.Int + +const ( + PARLIO_SAMPLE_EDGE_NEG ParlioSampleEdgeT = 0 + PARLIO_SAMPLE_EDGE_POS ParlioSampleEdgeT = 1 +) + +type ParlioBitPackOrderT c.Int + +const ( + PARLIO_BIT_PACK_ORDER_LSB ParlioBitPackOrderT = 0 + PARLIO_BIT_PACK_ORDER_MSB ParlioBitPackOrderT = 1 +) + +type ParlioClockSourceT c.Int diff --git a/esp32/pcnt_hal.go b/esp32/pcnt_hal.go new file mode 100644 index 00000000..0a786c86 --- /dev/null +++ b/esp32/pcnt_hal.go @@ -0,0 +1,27 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type PcntSocHandleT *PcntDevT + +/** + * Context that should be maintained by both the driver and the HAL + */ + +type PcntHalContextT struct { + Dev PcntSocHandleT +} + +/** + * @brief Init the PCNT hal and set the PCNT to the default configuration. + * @note This function should be called first before other hal layer function is called. + * + * @param hal Context of the HAL layer + * @param group_id PCNT group ID + */ +// llgo:link (*PcntHalContextT).PcntHalInit C.pcnt_hal_init +func (recv_ *PcntHalContextT) PcntHalInit(group_id c.Int) { +} diff --git a/esp32/pcnt_ll.go b/esp32/pcnt_ll.go new file mode 100644 index 00000000..93543956 --- /dev/null +++ b/esp32/pcnt_ll.go @@ -0,0 +1,20 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const PCNT_LL_MAX_GLITCH_WIDTH = 1023 + +type PcntLlWatchEventIdT c.Int + +const ( + PCNT_LL_WATCH_EVENT_INVALID PcntLlWatchEventIdT = -1 + PCNT_LL_WATCH_EVENT_THRES1 PcntLlWatchEventIdT = 0 + PCNT_LL_WATCH_EVENT_THRES0 PcntLlWatchEventIdT = 1 + PCNT_LL_WATCH_EVENT_LOW_LIMIT PcntLlWatchEventIdT = 2 + PCNT_LL_WATCH_EVENT_HIGH_LIMIT PcntLlWatchEventIdT = 3 + PCNT_LL_WATCH_EVENT_ZERO_CROSS PcntLlWatchEventIdT = 4 + PCNT_LL_WATCH_EVENT_MAX PcntLlWatchEventIdT = 5 +) diff --git a/esp32/pcnt_periph.go b/esp32/pcnt_periph.go new file mode 100644 index 00000000..abdbe878 --- /dev/null +++ b/esp32/pcnt_periph.go @@ -0,0 +1,19 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type PcntSignalConnT struct { + Groups [1]struct { + Units [4]struct { + Channels [2]struct { + PulseSig c.Uint32T + ControlSig c.Uint32T + } + ClearSig c.Uint32T + } + Irq c.Uint32T + } +} diff --git a/esp32/pcnt_reg.go b/esp32/pcnt_reg.go new file mode 100644 index 00000000..8d31d623 --- /dev/null +++ b/esp32/pcnt_reg.go @@ -0,0 +1,134 @@ +package freertos + +import _ "unsafe" + +const PCNT_FILTER_THRES_U0_S = 0 +const PCNT_FILTER_EN_U0_S = 10 +const PCNT_THR_ZERO_EN_U0_S = 11 +const PCNT_THR_H_LIM_EN_U0_S = 12 +const PCNT_THR_L_LIM_EN_U0_S = 13 +const PCNT_THR_THRES0_EN_U0_S = 14 +const PCNT_THR_THRES1_EN_U0_S = 15 +const PCNT_CH0_NEG_MODE_U0_S = 16 +const PCNT_CH0_POS_MODE_U0_S = 18 +const PCNT_CH0_HCTRL_MODE_U0_S = 20 +const PCNT_CH0_LCTRL_MODE_U0_S = 22 +const PCNT_CH1_NEG_MODE_U0_S = 24 +const PCNT_CH1_POS_MODE_U0_S = 26 +const PCNT_CH1_HCTRL_MODE_U0_S = 28 +const PCNT_CH1_LCTRL_MODE_U0_S = 30 +const PCNT_CNT_THRES0_U0_S = 0 +const PCNT_CNT_THRES1_U0_S = 16 +const PCNT_CNT_H_LIM_U0_S = 0 +const PCNT_CNT_L_LIM_U0_S = 16 +const PCNT_FILTER_THRES_U1_S = 0 +const PCNT_FILTER_EN_U1_S = 10 +const PCNT_THR_ZERO_EN_U1_S = 11 +const PCNT_THR_H_LIM_EN_U1_S = 12 +const PCNT_THR_L_LIM_EN_U1_S = 13 +const PCNT_THR_THRES0_EN_U1_S = 14 +const PCNT_THR_THRES1_EN_U1_S = 15 +const PCNT_CH0_NEG_MODE_U1_S = 16 +const PCNT_CH0_POS_MODE_U1_S = 18 +const PCNT_CH0_HCTRL_MODE_U1_S = 20 +const PCNT_CH0_LCTRL_MODE_U1_S = 22 +const PCNT_CH1_NEG_MODE_U1_S = 24 +const PCNT_CH1_POS_MODE_U1_S = 26 +const PCNT_CH1_HCTRL_MODE_U1_S = 28 +const PCNT_CH1_LCTRL_MODE_U1_S = 30 +const PCNT_CNT_THRES0_U1_S = 0 +const PCNT_CNT_THRES1_U1_S = 16 +const PCNT_CNT_H_LIM_U1_S = 0 +const PCNT_CNT_L_LIM_U1_S = 16 +const PCNT_FILTER_THRES_U2_S = 0 +const PCNT_FILTER_EN_U2_S = 10 +const PCNT_THR_ZERO_EN_U2_S = 11 +const PCNT_THR_H_LIM_EN_U2_S = 12 +const PCNT_THR_L_LIM_EN_U2_S = 13 +const PCNT_THR_THRES0_EN_U2_S = 14 +const PCNT_THR_THRES1_EN_U2_S = 15 +const PCNT_CH0_NEG_MODE_U2_S = 16 +const PCNT_CH0_POS_MODE_U2_S = 18 +const PCNT_CH0_HCTRL_MODE_U2_S = 20 +const PCNT_CH0_LCTRL_MODE_U2_S = 22 +const PCNT_CH1_NEG_MODE_U2_S = 24 +const PCNT_CH1_POS_MODE_U2_S = 26 +const PCNT_CH1_HCTRL_MODE_U2_S = 28 +const PCNT_CH1_LCTRL_MODE_U2_S = 30 +const PCNT_CNT_THRES0_U2_S = 0 +const PCNT_CNT_THRES1_U2_S = 16 +const PCNT_CNT_H_LIM_U2_S = 0 +const PCNT_CNT_L_LIM_U2_S = 16 +const PCNT_FILTER_THRES_U3_S = 0 +const PCNT_FILTER_EN_U3_S = 10 +const PCNT_THR_ZERO_EN_U3_S = 11 +const PCNT_THR_H_LIM_EN_U3_S = 12 +const PCNT_THR_L_LIM_EN_U3_S = 13 +const PCNT_THR_THRES0_EN_U3_S = 14 +const PCNT_THR_THRES1_EN_U3_S = 15 +const PCNT_CH0_NEG_MODE_U3_S = 16 +const PCNT_CH0_POS_MODE_U3_S = 18 +const PCNT_CH0_HCTRL_MODE_U3_S = 20 +const PCNT_CH0_LCTRL_MODE_U3_S = 22 +const PCNT_CH1_NEG_MODE_U3_S = 24 +const PCNT_CH1_POS_MODE_U3_S = 26 +const PCNT_CH1_HCTRL_MODE_U3_S = 28 +const PCNT_CH1_LCTRL_MODE_U3_S = 30 +const PCNT_CNT_THRES0_U3_S = 0 +const PCNT_CNT_THRES1_U3_S = 16 +const PCNT_CNT_H_LIM_U3_S = 0 +const PCNT_CNT_L_LIM_U3_S = 16 +const PCNT_PULSE_CNT_U0_S = 0 +const PCNT_PULSE_CNT_U1_S = 0 +const PCNT_PULSE_CNT_U2_S = 0 +const PCNT_PULSE_CNT_U3_S = 0 +const PCNT_CNT_THR_EVENT_U0_INT_RAW_S = 0 +const PCNT_CNT_THR_EVENT_U1_INT_RAW_S = 1 +const PCNT_CNT_THR_EVENT_U2_INT_RAW_S = 2 +const PCNT_CNT_THR_EVENT_U3_INT_RAW_S = 3 +const PCNT_CNT_THR_EVENT_U0_INT_ST_S = 0 +const PCNT_CNT_THR_EVENT_U1_INT_ST_S = 1 +const PCNT_CNT_THR_EVENT_U2_INT_ST_S = 2 +const PCNT_CNT_THR_EVENT_U3_INT_ST_S = 3 +const PCNT_CNT_THR_EVENT_U0_INT_ENA_S = 0 +const PCNT_CNT_THR_EVENT_U1_INT_ENA_S = 1 +const PCNT_CNT_THR_EVENT_U2_INT_ENA_S = 2 +const PCNT_CNT_THR_EVENT_U3_INT_ENA_S = 3 +const PCNT_CNT_THR_EVENT_U0_INT_CLR_S = 0 +const PCNT_CNT_THR_EVENT_U1_INT_CLR_S = 1 +const PCNT_CNT_THR_EVENT_U2_INT_CLR_S = 2 +const PCNT_CNT_THR_EVENT_U3_INT_CLR_S = 3 +const PCNT_CNT_THR_ZERO_MODE_U0_S = 0 +const PCNT_CNT_THR_THRES1_LAT_U0_S = 2 +const PCNT_CNT_THR_THRES0_LAT_U0_S = 3 +const PCNT_CNT_THR_L_LIM_LAT_U0_S = 4 +const PCNT_CNT_THR_H_LIM_LAT_U0_S = 5 +const PCNT_CNT_THR_ZERO_LAT_U0_S = 6 +const PCNT_CNT_THR_ZERO_MODE_U1_S = 0 +const PCNT_CNT_THR_THRES1_LAT_U1_S = 2 +const PCNT_CNT_THR_THRES0_LAT_U1_S = 3 +const PCNT_CNT_THR_L_LIM_LAT_U1_S = 4 +const PCNT_CNT_THR_H_LIM_LAT_U1_S = 5 +const PCNT_CNT_THR_ZERO_LAT_U1_S = 6 +const PCNT_CNT_THR_ZERO_MODE_U2_S = 0 +const PCNT_CNT_THR_THRES1_LAT_U2_S = 2 +const PCNT_CNT_THR_THRES0_LAT_U2_S = 3 +const PCNT_CNT_THR_L_LIM_LAT_U2_S = 4 +const PCNT_CNT_THR_H_LIM_LAT_U2_S = 5 +const PCNT_CNT_THR_ZERO_LAT_U2_S = 6 +const PCNT_CNT_THR_ZERO_MODE_U3_S = 0 +const PCNT_CNT_THR_THRES1_LAT_U3_S = 2 +const PCNT_CNT_THR_THRES0_LAT_U3_S = 3 +const PCNT_CNT_THR_L_LIM_LAT_U3_S = 4 +const PCNT_CNT_THR_H_LIM_LAT_U3_S = 5 +const PCNT_CNT_THR_ZERO_LAT_U3_S = 6 +const PCNT_PULSE_CNT_RST_U0_S = 0 +const PCNT_CNT_PAUSE_U0_S = 1 +const PCNT_PULSE_CNT_RST_U1_S = 2 +const PCNT_CNT_PAUSE_U1_S = 3 +const PCNT_PULSE_CNT_RST_U2_S = 4 +const PCNT_CNT_PAUSE_U2_S = 5 +const PCNT_PULSE_CNT_RST_U3_S = 6 +const PCNT_CNT_PAUSE_U3_S = 7 +const PCNT_CLK_EN_S = 16 +const PCNT_DATE_S = 0 diff --git a/esp32/pcnt_struct.go b/esp32/pcnt_struct.go new file mode 100644 index 00000000..e548eaff --- /dev/null +++ b/esp32/pcnt_struct.go @@ -0,0 +1,115 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** Group: Configuration Register */ +/** Type of un_conf0 register + * Configuration register 0 for unit n + */ + +type PcntUnConf0RegT struct { + Val c.Uint32T +} + +/** Type of un_conf1 register + * Configuration register 1 for unit n + */ + +type PcntUnConf1RegT struct { + Val c.Uint32T +} + +/** Type of un_conf2 register + * Configuration register 2 for unit n + */ + +type PcntUnConf2RegT struct { + Val c.Uint32T +} + +/** Type of ctrl register + * Control register for all counters + */ + +type PcntCtrlRegT struct { + Val c.Uint32T +} + +/** Group: Status Register */ +/** Type of un_cnt register + * Counter value for unit n + */ + +type PcntUnCntRegT struct { + Val c.Uint32T +} + +/** Type of un_status register + * PNCT UNITn status register + */ + +type PcntUnStatusRegT struct { + Val c.Uint32T +} + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Interrupt raw status register + */ + +type PcntIntRawRegT struct { + Val c.Uint32T +} + +/** Type of int_st register + * Interrupt status register + */ + +type PcntIntStRegT struct { + Val c.Uint32T +} + +/** Type of int_ena register + * Interrupt enable register + */ + +type PcntIntEnaRegT struct { + Val c.Uint32T +} + +/** Type of int_clr register + * Interrupt clear register + */ + +type PcntIntClrRegT struct { + Val c.Uint32T +} + +/** Group: Version Register */ +/** Type of date register + * PCNT version control register + */ + +type PcntDateRegT struct { + Val c.Uint32T +} + +type PcntDevT struct { + ConfUnit [4]struct { + Conf0 PcntUnConf0RegT + Conf1 PcntUnConf1RegT + Conf2 PcntUnConf2RegT + } + CntUnit [4]PcntUnCntRegT + IntRaw PcntIntRawRegT + IntSt PcntIntStRegT + IntEna PcntIntEnaRegT + IntClr PcntIntClrRegT + StatusUnit [4]PcntUnStatusRegT + Ctrl PcntCtrlRegT + Reserved064 [38]c.Uint32T + Date PcntDateRegT +} diff --git a/esp32/pcnt_types.go b/esp32/pcnt_types.go new file mode 100644 index 00000000..5e6b6ba5 --- /dev/null +++ b/esp32/pcnt_types.go @@ -0,0 +1,32 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type PcntChannelLevelActionT c.Int + +const ( + PCNT_CHANNEL_LEVEL_ACTION_KEEP PcntChannelLevelActionT = 0 + PCNT_CHANNEL_LEVEL_ACTION_INVERSE PcntChannelLevelActionT = 1 + PCNT_CHANNEL_LEVEL_ACTION_HOLD PcntChannelLevelActionT = 2 +) + +type PcntChannelEdgeActionT c.Int + +const ( + PCNT_CHANNEL_EDGE_ACTION_HOLD PcntChannelEdgeActionT = 0 + PCNT_CHANNEL_EDGE_ACTION_INCREASE PcntChannelEdgeActionT = 1 + PCNT_CHANNEL_EDGE_ACTION_DECREASE PcntChannelEdgeActionT = 2 +) + +type PcntUnitZeroCrossModeT c.Int + +const ( + PCNT_UNIT_ZERO_CROSS_POS_ZERO PcntUnitZeroCrossModeT = 0 + PCNT_UNIT_ZERO_CROSS_NEG_ZERO PcntUnitZeroCrossModeT = 1 + PCNT_UNIT_ZERO_CROSS_NEG_POS PcntUnitZeroCrossModeT = 2 + PCNT_UNIT_ZERO_CROSS_POS_NEG PcntUnitZeroCrossModeT = 3 + PCNT_UNIT_ZERO_CROSS_INVALID PcntUnitZeroCrossModeT = 4 +) diff --git a/esp32/peri_backup_reg.go b/esp32/peri_backup_reg.go new file mode 100644 index 00000000..810ba3c4 --- /dev/null +++ b/esp32/peri_backup_reg.go @@ -0,0 +1,63 @@ +package freertos + +import _ "unsafe" + +const PERI_BACKUP_ENA_V = 0x1 +const PERI_BACKUP_ENA_S = 31 +const PERI_BACKUP_TO_MEM_V = 0x1 +const PERI_BACKUP_TO_MEM_S = 30 +const PERI_BACKUP_START_V = 0x1 +const PERI_BACKUP_START_S = 29 +const PERI_BACKUP_SIZE = 0x000003FF +const PERI_BACKUP_SIZE_V = 0x3FF +const PERI_BACKUP_SIZE_S = 19 +const PERI_BACKUP_TOUT_THRES = 0x000003FF +const PERI_BACKUP_TOUT_THRES_V = 0x3FF +const PERI_BACKUP_TOUT_THRES_S = 9 +const PERI_BACKUP_BURST_LIMIT = 0x0000001F +const PERI_BACKUP_BURST_LIMIT_V = 0x1F +const PERI_BACKUP_BURST_LIMIT_S = 4 +const PERI_BACKUP_ADDR_MAP_MODE_V = 0x1 +const PERI_BACKUP_ADDR_MAP_MODE_S = 3 +const PERI_BACKUP_FLOW_ERR = 0x00000007 +const PERI_BACKUP_FLOW_ERR_V = 0x7 +const PERI_BACKUP_FLOW_ERR_S = 0 +const PERI_BACKUP_APB_START_ADDR = 0xFFFFFFFF +const PERI_BACKUP_APB_START_ADDR_V = 0xFFFFFFFF +const PERI_BACKUP_APB_START_ADDR_S = 0 +const PERI_BACKUP_MEM_START_ADDR = 0xFFFFFFFF +const PERI_BACKUP_MEM_START_ADDR_V = 0xFFFFFFFF +const PERI_BACKUP_MEM_START_ADDR_S = 0 +const PERI_BACKUP_MAP0 = 0xFFFFFFFF +const PERI_BACKUP_MAP0_V = 0xFFFFFFFF +const PERI_BACKUP_MAP0_S = 0 +const PERI_BACKUP_MAP1 = 0xFFFFFFFF +const PERI_BACKUP_MAP1_V = 0xFFFFFFFF +const PERI_BACKUP_MAP1_S = 0 +const PERI_BACKUP_MAP2 = 0xFFFFFFFF +const PERI_BACKUP_MAP2_V = 0xFFFFFFFF +const PERI_BACKUP_MAP2_S = 0 +const PERI_BACKUP_MAP3 = 0xFFFFFFFF +const PERI_BACKUP_MAP3_V = 0xFFFFFFFF +const PERI_BACKUP_MAP3_S = 0 +const PERI_BACKUP_ERR_INT_RAW_V = 0x1 +const PERI_BACKUP_ERR_INT_RAW_S = 1 +const PERI_BACKUP_DONE_INT_RAW_V = 0x1 +const PERI_BACKUP_DONE_INT_RAW_S = 0 +const PERI_BACKUP_ERR_INT_ST_V = 0x1 +const PERI_BACKUP_ERR_INT_ST_S = 1 +const PERI_BACKUP_DONE_INT_ST_V = 0x1 +const PERI_BACKUP_DONE_INT_ST_S = 0 +const PERI_BACKUP_ERR_INT_ENA_V = 0x1 +const PERI_BACKUP_ERR_INT_ENA_S = 1 +const PERI_BACKUP_DONE_INT_ENA_V = 0x1 +const PERI_BACKUP_DONE_INT_ENA_S = 0 +const PERI_BACKUP_ERR_INT_CLR_V = 0x1 +const PERI_BACKUP_ERR_INT_CLR_S = 1 +const PERI_BACKUP_DONE_INT_CLR_V = 0x1 +const PERI_BACKUP_DONE_INT_CLR_S = 0 +const PERI_BACKUP_CLK_EN_V = 0x1 +const PERI_BACKUP_CLK_EN_S = 31 +const PERI_BACKUP_DATE = 0x0FFFFFFF +const PERI_BACKUP_DATE_V = 0xFFFFFFF +const PERI_BACKUP_DATE_S = 0 diff --git a/esp32/peri_backup_struct.go b/esp32/peri_backup_struct.go new file mode 100644 index 00000000..b768c7b1 --- /dev/null +++ b/esp32/peri_backup_struct.go @@ -0,0 +1,86 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type PeriBackupDevS struct { + Config struct { + Val c.Uint32T + } + ApbAddr c.Uint32T + MemAddr c.Uint32T + RegMap0 c.Uint32T + RegMap1 c.Uint32T + RegMap2 c.Uint32T + RegMap3 c.Uint32T + IntRaw struct { + Val c.Uint32T + } + IntSt struct { + Val c.Uint32T + } + IntEna struct { + Val c.Uint32T + } + IntClr struct { + Val c.Uint32T + } + Reserved2c c.Uint32T + Reserved30 c.Uint32T + Reserved34 c.Uint32T + Reserved38 c.Uint32T + Reserved3c c.Uint32T + Reserved40 c.Uint32T + Reserved44 c.Uint32T + Reserved48 c.Uint32T + Reserved4c c.Uint32T + Reserved50 c.Uint32T + Reserved54 c.Uint32T + Reserved58 c.Uint32T + Reserved5c c.Uint32T + Reserved60 c.Uint32T + Reserved64 c.Uint32T + Reserved68 c.Uint32T + Reserved6c c.Uint32T + Reserved70 c.Uint32T + Reserved74 c.Uint32T + Reserved78 c.Uint32T + Reserved7c c.Uint32T + Reserved80 c.Uint32T + Reserved84 c.Uint32T + Reserved88 c.Uint32T + Reserved8c c.Uint32T + Reserved90 c.Uint32T + Reserved94 c.Uint32T + Reserved98 c.Uint32T + Reserved9c c.Uint32T + ReservedA0 c.Uint32T + ReservedA4 c.Uint32T + ReservedA8 c.Uint32T + ReservedAc c.Uint32T + ReservedB0 c.Uint32T + ReservedB4 c.Uint32T + ReservedB8 c.Uint32T + ReservedBc c.Uint32T + ReservedC0 c.Uint32T + ReservedC4 c.Uint32T + ReservedC8 c.Uint32T + ReservedCc c.Uint32T + ReservedD0 c.Uint32T + ReservedD4 c.Uint32T + ReservedD8 c.Uint32T + ReservedDc c.Uint32T + ReservedE0 c.Uint32T + ReservedE4 c.Uint32T + ReservedE8 c.Uint32T + ReservedEc c.Uint32T + ReservedF0 c.Uint32T + ReservedF4 c.Uint32T + ReservedF8 c.Uint32T + Date struct { + Val c.Uint32T + } +} +type PeriBackupDevT PeriBackupDevS diff --git a/esp32/periph_ctrl.go b/esp32/periph_ctrl.go new file mode 100644 index 00000000..2aa1f9f9 --- /dev/null +++ b/esp32/periph_ctrl.go @@ -0,0 +1,105 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** @cond */ +// The following functions are not intended to be used directly by the developers +// llgo:link PeriphModuleT.PeriphRccAcquireEnter C.periph_rcc_acquire_enter +func (recv_ PeriphModuleT) PeriphRccAcquireEnter() c.Uint8T { + return 0 +} + +// llgo:link PeriphModuleT.PeriphRccAcquireExit C.periph_rcc_acquire_exit +func (recv_ PeriphModuleT) PeriphRccAcquireExit(ref_count c.Uint8T) { +} + +// llgo:link PeriphModuleT.PeriphRccReleaseEnter C.periph_rcc_release_enter +func (recv_ PeriphModuleT) PeriphRccReleaseEnter() c.Uint8T { + return 0 +} + +// llgo:link PeriphModuleT.PeriphRccReleaseExit C.periph_rcc_release_exit +func (recv_ PeriphModuleT) PeriphRccReleaseExit(ref_count c.Uint8T) { +} + +//go:linkname PeriphRccEnter C.periph_rcc_enter +func PeriphRccEnter() + +//go:linkname PeriphRccExit C.periph_rcc_exit +func PeriphRccExit() + +/** + * @brief Enable peripheral module by un-gating the clock and de-asserting the reset signal. + * + * @param[in] periph Peripheral module + * + * @note If @c periph_module_enable() is called a number of times, + * @c periph_module_disable() has to be called the same number of times, + * in order to put the peripheral into disabled state. + */ +// llgo:link PeriphModuleT.PeriphModuleEnable C.periph_module_enable +func (recv_ PeriphModuleT) PeriphModuleEnable() { +} + +/** + * @brief Disable peripheral module by gating the clock and asserting the reset signal. + * + * @param[in] periph Peripheral module + * + * @note If @c periph_module_enable() is called a number of times, + * @c periph_module_disable() has to be called the same number of times, + * in order to put the peripheral into disabled state. + */ +// llgo:link PeriphModuleT.PeriphModuleDisable C.periph_module_disable +func (recv_ PeriphModuleT) PeriphModuleDisable() { +} + +/** + * @brief Reset peripheral module by asserting and de-asserting the reset signal. + * + * @param[in] periph Peripheral module + * + * @note Calling this function does not enable or disable the clock for the module. + */ +// llgo:link PeriphModuleT.PeriphModuleReset C.periph_module_reset +func (recv_ PeriphModuleT) PeriphModuleReset() { +} + +/** + * @brief Enable Wi-Fi and BT common module + * + * @note If @c wifi_bt_common_module_enable() is called a number of times, + * @c wifi_bt_common_module_disable() has to be called the same number of times, + * in order to put the peripheral into disabled state. + */ +//go:linkname WifiBtCommonModuleEnable C.wifi_bt_common_module_enable +func WifiBtCommonModuleEnable() + +/** + * @brief Disable Wi-Fi and BT common module + * + * @note If @c wifi_bt_common_module_enable() is called a number of times, + * @c wifi_bt_common_module_disable() has to be called the same number of times, + * in order to put the peripheral into disabled state. + */ +//go:linkname WifiBtCommonModuleDisable C.wifi_bt_common_module_disable +func WifiBtCommonModuleDisable() + +/** + * @brief Enable Wi-Fi module + * + * @note Calling this function will only enable Wi-Fi module. + */ +//go:linkname WifiModuleEnable C.wifi_module_enable +func WifiModuleEnable() + +/** + * @brief Disable Wi-Fi module + * + * @note Calling this function will only disable Wi-Fi module. + */ +//go:linkname WifiModuleDisable C.wifi_module_disable +func WifiModuleDisable() diff --git a/esp32/periph_defs.go b/esp32/periph_defs.go new file mode 100644 index 00000000..9c38ba08 --- /dev/null +++ b/esp32/periph_defs.go @@ -0,0 +1,53 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type PeriphModuleT c.Int + +const ( + PERIPH_LEDC_MODULE PeriphModuleT = 0 + PERIPH_UART0_MODULE PeriphModuleT = 1 + PERIPH_UART1_MODULE PeriphModuleT = 2 + PERIPH_UART2_MODULE PeriphModuleT = 3 + PERIPH_USB_MODULE PeriphModuleT = 4 + PERIPH_I2C0_MODULE PeriphModuleT = 5 + PERIPH_I2C1_MODULE PeriphModuleT = 6 + PERIPH_I2S0_MODULE PeriphModuleT = 7 + PERIPH_I2S1_MODULE PeriphModuleT = 8 + PERIPH_LCD_CAM_MODULE PeriphModuleT = 9 + PERIPH_TIMG0_MODULE PeriphModuleT = 10 + PERIPH_TIMG1_MODULE PeriphModuleT = 11 + PERIPH_PWM0_MODULE PeriphModuleT = 12 + PERIPH_PWM1_MODULE PeriphModuleT = 13 + PERIPH_PWM2_MODULE PeriphModuleT = 14 + PERIPH_PWM3_MODULE PeriphModuleT = 15 + PERIPH_UHCI0_MODULE PeriphModuleT = 16 + PERIPH_UHCI1_MODULE PeriphModuleT = 17 + PERIPH_RMT_MODULE PeriphModuleT = 18 + PERIPH_PCNT_MODULE PeriphModuleT = 19 + PERIPH_SPI_MODULE PeriphModuleT = 20 + PERIPH_SPI2_MODULE PeriphModuleT = 21 + PERIPH_SPI3_MODULE PeriphModuleT = 22 + PERIPH_SDMMC_MODULE PeriphModuleT = 23 + PERIPH_TWAI_MODULE PeriphModuleT = 24 + PERIPH_RNG_MODULE PeriphModuleT = 25 + PERIPH_WIFI_MODULE PeriphModuleT = 26 + PERIPH_BT_MODULE PeriphModuleT = 27 + PERIPH_WIFI_BT_COMMON_MODULE PeriphModuleT = 28 + PERIPH_BT_BASEBAND_MODULE PeriphModuleT = 29 + PERIPH_BT_LC_MODULE PeriphModuleT = 30 + PERIPH_AES_MODULE PeriphModuleT = 31 + PERIPH_SHA_MODULE PeriphModuleT = 32 + PERIPH_HMAC_MODULE PeriphModuleT = 33 + PERIPH_DS_MODULE PeriphModuleT = 34 + PERIPH_RSA_MODULE PeriphModuleT = 35 + PERIPH_SYSTIMER_MODULE PeriphModuleT = 36 + PERIPH_GDMA_MODULE PeriphModuleT = 37 + PERIPH_DEDIC_GPIO_MODULE PeriphModuleT = 38 + PERIPH_SARADC_MODULE PeriphModuleT = 39 + PERIPH_TEMPSENSOR_MODULE PeriphModuleT = 40 + PERIPH_MODULE_MAX PeriphModuleT = 41 +) diff --git a/esp32/pmu_types.go b/esp32/pmu_types.go new file mode 100644 index 00000000..f0b2a353 --- /dev/null +++ b/esp32/pmu_types.go @@ -0,0 +1,32 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type PmuHpModeT c.Int + +const ( + PMU_MODE_HP_ACTIVE PmuHpModeT = 0 + PMU_MODE_HP_MODEM PmuHpModeT = 1 + PMU_MODE_HP_SLEEP PmuHpModeT = 2 + PMU_MODE_HP_MAX PmuHpModeT = 3 +) + +type PmuLpModeT c.Int + +const ( + PMU_MODE_LP_ACTIVE PmuLpModeT = 0 + PMU_MODE_LP_SLEEP PmuLpModeT = 1 + PMU_MODE_LP_MAX PmuLpModeT = 2 +) + +type PmuHpPowerDomainT c.Int + +const ( + PMU_HP_PD_TOP PmuHpPowerDomainT = 0 + PMU_HP_PD_CPU PmuHpPowerDomainT = 2 + PMU_HP_PD_RESERVED PmuHpPowerDomainT = 3 + PMU_HP_PD_WIFI PmuHpPowerDomainT = 4 +) diff --git a/esp32/port_systick.go b/esp32/port_systick.go new file mode 100644 index 00000000..de490a4d --- /dev/null +++ b/esp32/port_systick.go @@ -0,0 +1,9 @@ +package freertos + +import _ "unsafe" + +/** + * @brief Set up the SysTick interrupt + */ +//go:linkname VPortSetupTimer C.vPortSetupTimer +func VPortSetupTimer() diff --git a/esp32/portable.go b/esp32/portable.go new file mode 100644 index 00000000..1f63f732 --- /dev/null +++ b/esp32/portable.go @@ -0,0 +1,96 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const PortUSING_MPU_WRAPPERS = 0 +const PortNUM_CONFIGURABLE_REGIONS = 1 +const PortHAS_STACK_OVERFLOW_CHECKING = 0 + +// llgo:link (*StackTypeT).PxPortInitialiseStack C.pxPortInitialiseStack +func (recv_ *StackTypeT) PxPortInitialiseStack(pxCode c.Int, pvParameters c.Pointer) *StackTypeT { + return nil +} + +/* Used by heap_5.c to define the start address and size of each memory region + * that together comprise the total FreeRTOS heap space. */ + +type HeapRegion struct { + PucStartAddress *c.Uint8T + XSizeInBytes c.SizeT +} +type HeapRegionT HeapRegion + +/* Used to pass information about the heap out of vPortGetHeapStats(). */ + +type XHeapStats struct { + XAvailableHeapSpaceInBytes c.SizeT + XSizeOfLargestFreeBlockInBytes c.SizeT + XSizeOfSmallestFreeBlockInBytes c.SizeT + XNumberOfFreeBlocks c.SizeT + XMinimumEverFreeBytesRemaining c.SizeT + XNumberOfSuccessfulAllocations c.SizeT + XNumberOfSuccessfulFrees c.SizeT +} +type HeapStatsT XHeapStats + +/* + * Used to define multiple heap regions for use by heap_5.c. This function + * must be called before any calls to pvPortMalloc() - not creating a task, + * queue, semaphore, mutex, software timer, event group, etc. will result in + * pvPortMalloc being called. + * + * pxHeapRegions passes in an array of HeapRegion_t structures - each of which + * defines a region of memory that can be used as the heap. The array is + * terminated by a HeapRegions_t structure that has a size of 0. The region + * with the lowest start address must appear first in the array. + */ +// llgo:link (*HeapRegionT).VPortDefineHeapRegions C.vPortDefineHeapRegions +func (recv_ *HeapRegionT) VPortDefineHeapRegions() { +} + +/* + * Returns a HeapStats_t structure filled with information about the current + * heap state. + */ +// llgo:link (*HeapStatsT).VPortGetHeapStats C.vPortGetHeapStats +func (recv_ *HeapStatsT) VPortGetHeapStats() { +} + +/* + * Map to the memory management routines required for the port. + */ +//go:linkname PvPortMalloc C.pvPortMalloc +func PvPortMalloc(xSize c.SizeT) c.Pointer + +//go:linkname PvPortCalloc C.pvPortCalloc +func PvPortCalloc(xNum c.SizeT, xSize c.SizeT) c.Pointer + +//go:linkname VPortFree C.vPortFree +func VPortFree(pv c.Pointer) + +//go:linkname VPortInitialiseBlocks C.vPortInitialiseBlocks +func VPortInitialiseBlocks() + +//go:linkname XPortGetFreeHeapSize C.xPortGetFreeHeapSize +func XPortGetFreeHeapSize() c.SizeT + +//go:linkname XPortGetMinimumEverFreeHeapSize C.xPortGetMinimumEverFreeHeapSize +func XPortGetMinimumEverFreeHeapSize() c.SizeT + +/* + * Setup the hardware ready for the scheduler to take control. This generally + * sets up a tick interrupt and sets timers for the correct tick frequency. + */ +//go:linkname XPortStartScheduler C.xPortStartScheduler +func XPortStartScheduler() BaseTypeT + +/* + * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so + * the hardware is left in its original condition after the scheduler stops + * executing. + */ +//go:linkname VPortEndScheduler C.vPortEndScheduler +func VPortEndScheduler() diff --git a/esp32/portbenchmark.go b/esp32/portbenchmark.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/portbenchmark.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/portmacro.go b/esp32/portmacro.go new file mode 100644 index 00000000..c202aea5 --- /dev/null +++ b/esp32/portmacro.go @@ -0,0 +1,295 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const PortCRITICAL_NESTING_IN_TCB = 0 +const PortBYTE_ALIGNMENT = 16 +const PortTICK_TYPE_IS_ATOMIC = 1 +const PORT_OFFSET_PX_STACK = 0x30 + +type StackTypeT c.Uint8T +type BaseTypeT c.Int +type UBaseTypeT c.Uint +type TickTypeT c.Uint32T + +/** + * @brief Checks if the current core is in an ISR context + * + * - ISR context consist of Low/Mid priority ISR, or time tick ISR + * - High priority ISRs aren't detected here, but they normally cannot call C code, so that should not be an issue anyway. + * + * @note [refactor-todo] Check if this should be inlined + * @return + * - pdTRUE if in ISR + * - pdFALSE otherwise + */ +//go:linkname XPortInIsrContext C.xPortInIsrContext +func XPortInIsrContext() BaseTypeT + +/** + * @brief Assert if in ISR context + * + * - Asserts on xPortInIsrContext() internally + */ +//go:linkname VPortAssertIfInISR C.vPortAssertIfInISR +func VPortAssertIfInISR() + +/** + * @brief Check if in ISR context from High priority ISRs + * + * - Called from High priority ISR + * - Checks if the previous context (before high priority interrupt) was in ISR context (meaning low/med priority) + * + * @note [refactor-todo] Check if this should be inlined + * @return + * - pdTRUE if in previous in ISR context + * - pdFALSE otherwise + */ +//go:linkname XPortInterruptedFromISRContext C.xPortInterruptedFromISRContext +func XPortInterruptedFromISRContext() BaseTypeT + +type PortMUXTYPE SpinlockT + +/** + * @brief Enter a SMP critical section with a timeout + * + * This function enters an SMP critical section by disabling interrupts then + * taking a spinlock with a specified timeout. + * + * This function can be called in a nested manner. + * + * @note This function is made non-inline on purpose to reduce code size + * @param mux Spinlock + * @param timeout Timeout to wait for spinlock in number of CPU cycles. + * Use portMUX_NO_TIMEOUT to wait indefinitely + * Use portMUX_TRY_LOCK to only getting the spinlock a single time + * @retval pdPASS Critical section entered (spinlock taken) + * @retval pdFAIL If timed out waiting for spinlock (will not occur if using portMUX_NO_TIMEOUT) + */ +// llgo:link (*PortMUXTYPE).XPortEnterCriticalTimeout C.xPortEnterCriticalTimeout +func (recv_ *PortMUXTYPE) XPortEnterCriticalTimeout(timeout BaseTypeT) BaseTypeT { + return 0 +} + +/** + * @brief Enter a SMP critical section + * + * This function enters an SMP critical section by disabling interrupts then + * taking a spinlock with an unlimited timeout. + * + * This function can be called in a nested manner + * + * @param[in] mux Spinlock + */ +// llgo:link (*PortMUXTYPE).VPortEnterCritical C.vPortEnterCritical +func (recv_ *PortMUXTYPE) VPortEnterCritical() { +} + +/** + * @brief Exit a SMP critical section + * + * This function can be called in a nested manner. On the outer most level of nesting, this function will: + * + * - Release the spinlock + * - Restore the previous interrupt level before the critical section was entered + * + * If still nesting, this function simply decrements a critical nesting count + * + * @note This function is made non-inline on purpose to reduce code size + * @param[in] mux Spinlock + */ +// llgo:link (*PortMUXTYPE).VPortExitCritical C.vPortExitCritical +func (recv_ *PortMUXTYPE) VPortExitCritical() { +} + +/** + * @brief FreeRTOS Compliant version of xPortEnterCriticalTimeout() + * + * Compliant version of xPortEnterCriticalTimeout() will ensure that this is + * called from a task context only. An abort is called otherwise. + * + * @note This function is made non-inline on purpose to reduce code size + * + * @param mux Spinlock + * @param timeout Timeout + * @return BaseType_t + */ +// llgo:link (*PortMUXTYPE).XPortEnterCriticalTimeoutCompliance C.xPortEnterCriticalTimeoutCompliance +func (recv_ *PortMUXTYPE) XPortEnterCriticalTimeoutCompliance(timeout BaseTypeT) BaseTypeT { + return 0 +} + +/** + * @brief FreeRTOS compliant version of vPortExitCritical() + * + * Compliant version of vPortExitCritical() will ensure that this is + * called from a task context only. An abort is called otherwise. + * + * @note This function is made non-inline on purpose to reduce code size + * @param[in] mux Spinlock + */ +// llgo:link (*PortMUXTYPE).VPortExitCriticalCompliance C.vPortExitCriticalCompliance +func (recv_ *PortMUXTYPE) VPortExitCriticalCompliance() { +} + +/** + * @brief Perform a solicited context switch + * + * - Defined in portasm.S + * + * @note [refactor-todo] The rest of ESP-IDF should call taskYield() instead + */ +//go:linkname VPortYield C.vPortYield +func VPortYield() + +/** + * @brief Yields the other core + * + * - Send an interrupt to another core in order to make the task running on it yield for a higher-priority task. + * - Can be used to yield current core as well + * + * @note [refactor-todo] Put this into private macros as its only called from task.c and is not public API + * @param coreid ID of core to yield + */ +// llgo:link BaseTypeT.VPortYieldOtherCore C.vPortYieldOtherCore +func (recv_ BaseTypeT) VPortYieldOtherCore() { +} + +/** + * @brief Hook function called on entry to tickless idle + * + * - Implemented in pm_impl.c + * + * @param xExpectedIdleTime Expected idle time + */ +// llgo:link TickTypeT.VApplicationSleep C.vApplicationSleep +func (recv_ TickTypeT) VApplicationSleep() { +} + +/** + * @brief Get the tick rate per second + * + * @note [refactor-todo] make this inline + * @return uint32_t Tick rate in Hz + */ +//go:linkname XPortGetTickRateHz C.xPortGetTickRateHz +func XPortGetTickRateHz() c.Uint32T + +/** + * @brief Set a watchpoint to watch the last 32 bytes of the stack + * + * Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack watchpoint + * around. + * + * @param pxStackStart Pointer to the start of the stack + */ +//go:linkname VPortSetStackWatchpoint C.vPortSetStackWatchpoint +func VPortSetStackWatchpoint(pxStackStart c.Pointer) + +/** + * @brief TCB cleanup hook + * + * The portCLEAN_UP_TCB() macro is called in prvDeleteTCB() right before a + * deleted task's memory is freed. We map that macro to this internal function + * so that IDF FreeRTOS ports can inject some task pre-deletion operations. + * + * @note We can't use vPortCleanUpTCB() due to API compatibility issues. See + * CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP. Todo: IDF-8097 + */ +//go:linkname VPortTCBPreDeleteHook C.vPortTCBPreDeleteHook +func VPortTCBPreDeleteHook(pxTCB c.Pointer) + +//go:linkname X_frxtSetupSwitch C._frxt_setup_switch +func X_frxtSetupSwitch() + +/** + * @brief Checks if a given piece of memory can be used to store a FreeRTOS list + * + * - Defined in heap_idf.c + * + * @param ptr Pointer to memory + * @return true Memory can be used to store a List + * @return false Otherwise + */ +//go:linkname XPortCheckValidListMem C.xPortCheckValidListMem +func XPortCheckValidListMem(ptr c.Pointer) bool + +/** + * @brief Checks if a given piece of memory can be used to store a task's TCB + * + * - Defined in heap_idf.c + * + * @param ptr Pointer to memory + * @return true Memory can be used to store a TCB + * @return false Otherwise + */ +//go:linkname XPortCheckValidTCBMem C.xPortCheckValidTCBMem +func XPortCheckValidTCBMem(ptr c.Pointer) bool + +/** + * @brief Checks if a given piece of memory can be used to store a task's stack + * + * - Defined in heap_idf.c + * + * @param ptr Pointer to memory + * @return true Memory can be used to store a task stack + * @return false Otherwise + */ +//go:linkname XPortcheckValidStackMem C.xPortcheckValidStackMem +func XPortcheckValidStackMem(ptr c.Pointer) bool + +// ------------------ Critical Sections -------------------- +// +//go:linkname UxPortEnterCriticalFromISR C.uxPortEnterCriticalFromISR +func UxPortEnterCriticalFromISR() UBaseTypeT + +// llgo:link UBaseTypeT.VPortExitCriticalFromISR C.vPortExitCriticalFromISR +func (recv_ UBaseTypeT) VPortExitCriticalFromISR() { +} + +// llgo:link (*PortMUXTYPE).VPortTakeLock C.vPortTakeLock +func (recv_ *PortMUXTYPE) VPortTakeLock() { +} + +// llgo:link (*PortMUXTYPE).VPortReleaseLock C.vPortReleaseLock +func (recv_ *PortMUXTYPE) VPortReleaseLock() { +} + +// Critical sections used by FreeRTOS SMP +// +//go:linkname VTaskEnterCritical C.vTaskEnterCritical +func VTaskEnterCritical() + +//go:linkname VTaskExitCritical C.vTaskExitCritical +func VTaskExitCritical() + +//go:linkname VTaskEnterCriticalFromISR C.vTaskEnterCriticalFromISR +func VTaskEnterCriticalFromISR() UBaseTypeT + +// llgo:link UBaseTypeT.VTaskExitCriticalFromISR C.vTaskExitCriticalFromISR +func (recv_ UBaseTypeT) VTaskExitCriticalFromISR() { +} + +// llgo:link (*PortMUXTYPE).VPortExitCriticalIDF C.vPortExitCriticalIDF +func (recv_ *PortMUXTYPE) VPortExitCriticalIDF() { +} + +/** + * @brief Set interrupt mask and return current interrupt enable register + * + * @return UBaseType_t Current interrupt enable register before set + */ +//go:linkname UlPortSetInterruptMask C.ulPortSetInterruptMask +func UlPortSetInterruptMask() UBaseTypeT + +/** + * @brief Clear current interrupt mask and set given mask + * + * @param mask Interrupt mask + */ +// llgo:link UBaseTypeT.VPortClearInterruptMask C.vPortClearInterruptMask +func (recv_ UBaseTypeT) VPortClearInterruptMask() { +} diff --git a/esp32/portmacro_idf.go b/esp32/portmacro_idf.go new file mode 100644 index 00000000..516931d9 --- /dev/null +++ b/esp32/portmacro_idf.go @@ -0,0 +1,9 @@ +package freertos + +import _ "unsafe" + +//go:linkname VPortYieldFromISR C.vPortYieldFromISR +func VPortYieldFromISR() + +//go:linkname XPortCheckIfInISR C.xPortCheckIfInISR +func XPortCheckIfInISR() BaseTypeT diff --git a/esp32/ppa_hal.go b/esp32/ppa_hal.go new file mode 100644 index 00000000..4dc1a047 --- /dev/null +++ b/esp32/ppa_hal.go @@ -0,0 +1,34 @@ +package freertos + +import _ "unsafe" + +type PpaDevT struct { + Unused [8]uint8 +} +type PpaSocHandleT *PpaDevT + +/** + * Context that should be maintained by both the driver and the HAL + */ + +type PpaHalContextT struct { + Dev PpaSocHandleT +} + +/** + * @brief Init the PPA hal. This function should be called first before other hal layer function is called + * + * @param hal Context of the HAL layer + */ +// llgo:link (*PpaHalContextT).PpaHalInit C.ppa_hal_init +func (recv_ *PpaHalContextT) PpaHalInit() { +} + +/** + * @brief De-init the PPA hal + * + * @param hal Context of the HAL layer + */ +// llgo:link (*PpaHalContextT).PpaHalDeinit C.ppa_hal_deinit +func (recv_ *PpaHalContextT) PpaHalDeinit() { +} diff --git a/esp32/ppa_types.go b/esp32/ppa_types.go new file mode 100644 index 00000000..b9c13cba --- /dev/null +++ b/esp32/ppa_types.go @@ -0,0 +1,83 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type PpaEngineTypeT c.Int + +const ( + PPA_ENGINE_TYPE_SRM PpaEngineTypeT = 0 + PPA_ENGINE_TYPE_BLEND PpaEngineTypeT = 1 +) + +type PpaSrmRotationAngleT c.Int + +const ( + PPA_SRM_ROTATION_ANGLE_0 PpaSrmRotationAngleT = 0 + PPA_SRM_ROTATION_ANGLE_90 PpaSrmRotationAngleT = 1 + PPA_SRM_ROTATION_ANGLE_180 PpaSrmRotationAngleT = 2 + PPA_SRM_ROTATION_ANGLE_270 PpaSrmRotationAngleT = 3 +) + +type PpaSrmColorModeT c.Int + +const ( + PPA_SRM_COLOR_MODE_ARGB8888 PpaSrmColorModeT = 83886080 + PPA_SRM_COLOR_MODE_RGB888 PpaSrmColorModeT = 33554432 + PPA_SRM_COLOR_MODE_RGB565 PpaSrmColorModeT = 33554434 + PPA_SRM_COLOR_MODE_YUV420 PpaSrmColorModeT = 50331650 + PPA_SRM_COLOR_MODE_YUV444 PpaSrmColorModeT = 50331648 +) + +type PpaBlendColorModeT c.Int + +const ( + PPA_BLEND_COLOR_MODE_ARGB8888 PpaBlendColorModeT = 83886080 + PPA_BLEND_COLOR_MODE_RGB888 PpaBlendColorModeT = 33554432 + PPA_BLEND_COLOR_MODE_RGB565 PpaBlendColorModeT = 33554434 + PPA_BLEND_COLOR_MODE_A8 PpaBlendColorModeT = 100663297 + PPA_BLEND_COLOR_MODE_A4 PpaBlendColorModeT = 100663296 +) + +type PpaFillColorModeT c.Int + +const ( + PPA_FILL_COLOR_MODE_ARGB8888 PpaFillColorModeT = 83886080 + PPA_FILL_COLOR_MODE_RGB888 PpaFillColorModeT = 33554432 + PPA_FILL_COLOR_MODE_RGB565 PpaFillColorModeT = 33554434 +) + +type PpaAlphaUpdateModeT c.Int + +const ( + PPA_ALPHA_NO_CHANGE PpaAlphaUpdateModeT = 0 + PPA_ALPHA_FIX_VALUE PpaAlphaUpdateModeT = 1 + PPA_ALPHA_SCALE PpaAlphaUpdateModeT = 2 + PPA_ALPHA_INVERT PpaAlphaUpdateModeT = 3 +) + +type PpaColorConvStdRgbYuvT c.Int + +const ( + PPA_COLOR_CONV_STD_RGB_YUV_BT601 PpaColorConvStdRgbYuvT = 0 + PPA_COLOR_CONV_STD_RGB_YUV_BT709 PpaColorConvStdRgbYuvT = 1 +) + +type PpaColorRangeT c.Int + +const ( + PPA_COLOR_RANGE_LIMIT PpaColorRangeT = 0 + PPA_COLOR_RANGE_FULL PpaColorRangeT = 1 +) + +type PpaDataBurstLengthT c.Int + +const ( + PPA_DATA_BURST_LENGTH_8 PpaDataBurstLengthT = 1 + PPA_DATA_BURST_LENGTH_16 PpaDataBurstLengthT = 2 + PPA_DATA_BURST_LENGTH_32 PpaDataBurstLengthT = 3 + PPA_DATA_BURST_LENGTH_64 PpaDataBurstLengthT = 4 + PPA_DATA_BURST_LENGTH_128 PpaDataBurstLengthT = 5 +) diff --git a/esp32/projdefs.go b/esp32/projdefs.go new file mode 100644 index 00000000..38101298 --- /dev/null +++ b/esp32/projdefs.go @@ -0,0 +1,46 @@ +package freertos + +import _ "unsafe" + +const PdFREERTOS_ERRNO_NONE = 0 +const PdFREERTOS_ERRNO_ENOENT = 2 +const PdFREERTOS_ERRNO_EINTR = 4 +const PdFREERTOS_ERRNO_EIO = 5 +const PdFREERTOS_ERRNO_ENXIO = 6 +const PdFREERTOS_ERRNO_EBADF = 9 +const PdFREERTOS_ERRNO_EAGAIN = 11 +const PdFREERTOS_ERRNO_EWOULDBLOCK = 11 +const PdFREERTOS_ERRNO_ENOMEM = 12 +const PdFREERTOS_ERRNO_EACCES = 13 +const PdFREERTOS_ERRNO_EFAULT = 14 +const PdFREERTOS_ERRNO_EBUSY = 16 +const PdFREERTOS_ERRNO_EEXIST = 17 +const PdFREERTOS_ERRNO_EXDEV = 18 +const PdFREERTOS_ERRNO_ENODEV = 19 +const PdFREERTOS_ERRNO_ENOTDIR = 20 +const PdFREERTOS_ERRNO_EISDIR = 21 +const PdFREERTOS_ERRNO_EINVAL = 22 +const PdFREERTOS_ERRNO_ENOSPC = 28 +const PdFREERTOS_ERRNO_ESPIPE = 29 +const PdFREERTOS_ERRNO_EROFS = 30 +const PdFREERTOS_ERRNO_EUNATCH = 42 +const PdFREERTOS_ERRNO_EBADE = 50 +const PdFREERTOS_ERRNO_EFTYPE = 79 +const PdFREERTOS_ERRNO_ENMFILE = 89 +const PdFREERTOS_ERRNO_ENOTEMPTY = 90 +const PdFREERTOS_ERRNO_ENAMETOOLONG = 91 +const PdFREERTOS_ERRNO_EOPNOTSUPP = 95 +const PdFREERTOS_ERRNO_ENOBUFS = 105 +const PdFREERTOS_ERRNO_ENOPROTOOPT = 109 +const PdFREERTOS_ERRNO_EADDRINUSE = 112 +const PdFREERTOS_ERRNO_ETIMEDOUT = 116 +const PdFREERTOS_ERRNO_EINPROGRESS = 119 +const PdFREERTOS_ERRNO_EALREADY = 120 +const PdFREERTOS_ERRNO_EADDRNOTAVAIL = 125 +const PdFREERTOS_ERRNO_EISCONN = 127 +const PdFREERTOS_ERRNO_ENOTCONN = 128 +const PdFREERTOS_ERRNO_ENOMEDIUM = 135 +const PdFREERTOS_ERRNO_EILSEQ = 138 +const PdFREERTOS_ERRNO_ECANCELED = 140 +const PdFREERTOS_LITTLE_ENDIAN = 0 +const PdFREERTOS_BIG_ENDIAN = 1 diff --git a/esp32/psdet_types.go b/esp32/psdet_types.go new file mode 100644 index 00000000..7e10a259 --- /dev/null +++ b/esp32/psdet_types.go @@ -0,0 +1,13 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type BrownoutResetLevelT c.Int + +const ( + BROWNOUT_RESET_LEVEL_CHIP BrownoutResetLevelT = 0 + BROWNOUT_RESET_LEVEL_SYSTEM BrownoutResetLevelT = 1 +) diff --git a/esp32/psram_ctrlr_ll.go b/esp32/psram_ctrlr_ll.go new file mode 100644 index 00000000..36ed6e5c --- /dev/null +++ b/esp32/psram_ctrlr_ll.go @@ -0,0 +1,16 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const PSRAM_CTRLR_LL_MSPI_ID_0 = 0 +const PSRAM_CTRLR_LL_MSPI_ID_1 = 1 + +type PsramLlCsIdT c.Int + +const ( + PSRAM_LL_CS_ID_0 PsramLlCsIdT = 0 + PSRAM_LL_CS_ID_1 PsramLlCsIdT = 1 +) diff --git a/esp32/psram_types.go b/esp32/psram_types.go new file mode 100644 index 00000000..de0043a0 --- /dev/null +++ b/esp32/psram_types.go @@ -0,0 +1,13 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type PsramHalCmdModeT c.Int + +const ( + PSRAM_HAL_CMD_QPI PsramHalCmdModeT = 0 + PSRAM_HAL_CMD_SPI PsramHalCmdModeT = 1 +) diff --git a/esp32/queue.go b/esp32/queue.go new file mode 100644 index 00000000..1a7f254d --- /dev/null +++ b/esp32/queue.go @@ -0,0 +1,763 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Type by which queues are referenced. For example, a call to xQueueCreate() + * returns an QueueHandle_t variable that can then be used as a parameter to + * xQueueSend(), xQueueReceive(), etc. + */ + +type QueueDefinition struct { + Unused [8]uint8 +} +type QueueHandleT *QueueDefinition +type QueueSetHandleT *QueueDefinition +type QueueSetMemberHandleT *QueueDefinition + +/** + * + * It is preferred that the macros xQueueSend(), xQueueSendToFront() and + * xQueueSendToBack() are used in place of calling this function directly. + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * uint32_t ulVar = 10UL; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * + * // ... + * + * if( xQueue1 != 0 ) + * { + * // Send an uint32_t. Wait for 10 ticks for space to become + * // available if necessary. + * if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS ) + * { + * // Failed to post the message, even after 10 ticks. + * } + * } + * + * if( xQueue2 != 0 ) + * { + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK ); + * } + * + * // ... Rest of task code. + * } + * @endcode + * \ingroup QueueManagement + */ +//go:linkname XQueueGenericSend C.xQueueGenericSend +func XQueueGenericSend(xQueue QueueHandleT, pvItemToQueue c.Pointer, xTicksToWait TickTypeT, xCopyPosition BaseTypeT) BaseTypeT + +/** + * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * This macro must not be used in an interrupt service routine. See + * xQueuePeekFromISR() for an alternative that can be called from an interrupt + * service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue + * is empty. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * QueueHandle_t xQueue; + * + * // Task to create a queue and post a value. + * void vATask( void *pvParameters ) + * { + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * if( xQueue == 0 ) + * { + * // Failed to create the queue. + * } + * + * // ... + * + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * + * // ... Rest of task code. + * } + * + * // Task to peek the data from the queue. + * void vADifferentTask( void *pvParameters ) + * { + * struct AMessage *pxRxedMessage; + * + * if( xQueue != 0 ) + * { + * // Peek a message on the created queue. Block for 10 ticks if a + * // message is not immediately available. + * if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) ) + * { + * // pcRxedMessage now points to the struct AMessage variable posted + * // by vATask, but the item still remains on the queue. + * } + * } + * + * // ... Rest of task code. + * } + * @endcode + * \ingroup QueueManagement + */ +//go:linkname XQueuePeek C.xQueuePeek +func XQueuePeek(xQueue QueueHandleT, pvBuffer c.Pointer, xTicksToWait TickTypeT) BaseTypeT + +/** + * + * A version of xQueuePeek() that can be called from an interrupt service + * routine (ISR). + * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * \ingroup QueueManagement + */ +//go:linkname XQueuePeekFromISR C.xQueuePeekFromISR +func XQueuePeekFromISR(xQueue QueueHandleT, pvBuffer c.Pointer) BaseTypeT + +/** + * + * Receive an item from a queue. The item is received by copy so a buffer of + * adequate size must be provided. The number of bytes copied into the buffer + * was defined when the queue was created. + * + * Successfully received items are removed from the queue. + * + * This function must not be used in an interrupt service routine. See + * xQueueReceiveFromISR for an alternative that can. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. xQueueReceive() will return immediately if xTicksToWait + * is zero and the queue is empty. The time is defined in tick periods so the + * constant portTICK_PERIOD_MS should be used to convert to real time if this is + * required. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * QueueHandle_t xQueue; + * + * // Task to create a queue and post a value. + * void vATask( void *pvParameters ) + * { + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * if( xQueue == 0 ) + * { + * // Failed to create the queue. + * } + * + * // ... + * + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * + * // ... Rest of task code. + * } + * + * // Task to receive from the queue. + * void vADifferentTask( void *pvParameters ) + * { + * struct AMessage *pxRxedMessage; + * + * if( xQueue != 0 ) + * { + * // Receive a message on the created queue. Block for 10 ticks if a + * // message is not immediately available. + * if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) ) + * { + * // pcRxedMessage now points to the struct AMessage variable posted + * // by vATask. + * } + * } + * + * // ... Rest of task code. + * } + * @endcode + * \ingroup QueueManagement + */ +//go:linkname XQueueReceive C.xQueueReceive +func XQueueReceive(xQueue QueueHandleT, pvBuffer c.Pointer, xTicksToWait TickTypeT) BaseTypeT + +/** + * + * Return the number of messages stored in a queue. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of messages available in the queue. + * + * \ingroup QueueManagement + */ +//go:linkname UxQueueMessagesWaiting C.uxQueueMessagesWaiting +func UxQueueMessagesWaiting(xQueue QueueHandleT) UBaseTypeT + +/** + * + * Return the number of free spaces available in a queue. This is equal to the + * number of items that can be sent to the queue before the queue becomes full + * if no items are removed. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of spaces available in the queue. + * + * \ingroup QueueManagement + */ +//go:linkname UxQueueSpacesAvailable C.uxQueueSpacesAvailable +func UxQueueSpacesAvailable(xQueue QueueHandleT) UBaseTypeT + +/** + * + * Delete a queue - freeing all the memory allocated for storing of items + * placed on the queue. + * + * @param xQueue A handle to the queue to be deleted. + * + * \ingroup QueueManagement + */ +//go:linkname VQueueDelete C.vQueueDelete +func VQueueDelete(xQueue QueueHandleT) + +/** + * + * It is preferred that the macros xQueueSendFromISR(), + * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place + * of calling this function directly. xQueueGiveFromISR() is an + * equivalent for use by semaphores that don't actually copy any data. + * + * Post an item on a queue. It is safe to use this function from within an + * interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * @code{c} + * void vBufferISR( void ) + * { + * char cIn; + * BaseType_t xHigherPriorityTaskWokenByPost; + * + * // We have not woken a task at the start of the ISR. + * xHigherPriorityTaskWokenByPost = pdFALSE; + * + * // Loop until the buffer is empty. + * do + * { + * // Obtain a byte from the buffer. + * cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); + * + * // Post each byte. + * xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK ); + * + * } while( portINPUT_BYTE( BUFFER_COUNT ) ); + * + * // Now the buffer is empty we can switch context if necessary. Note that the + * // name of the yield function required is port specific. + * if( xHigherPriorityTaskWokenByPost ) + * { + * portYIELD_FROM_ISR(); + * } + * } + * @endcode + * + * \ingroup QueueManagement + */ +//go:linkname XQueueGenericSendFromISR C.xQueueGenericSendFromISR +func XQueueGenericSendFromISR(xQueue QueueHandleT, pvItemToQueue c.Pointer, pxHigherPriorityTaskWoken *BaseTypeT, xCopyPosition BaseTypeT) BaseTypeT + +//go:linkname XQueueGiveFromISR C.xQueueGiveFromISR +func XQueueGiveFromISR(xQueue QueueHandleT, pxHigherPriorityTaskWoken *BaseTypeT) BaseTypeT + +/** + * + * Receive an item from a queue. It is safe to use this function from within an + * interrupt service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param pxHigherPriorityTaskWoken A task may be blocked waiting for space to + * become available on the queue. If xQueueReceiveFromISR causes such a task to + * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will + * remain unchanged. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * @code{c} + * + * QueueHandle_t xQueue; + * + * // Function to create a queue and post some values. + * void vAFunction( void *pvParameters ) + * { + * char cValueToPost; + * const TickType_t xTicksToWait = ( TickType_t )0xff; + * + * // Create a queue capable of containing 10 characters. + * xQueue = xQueueCreate( 10, sizeof( char ) ); + * if( xQueue == 0 ) + * { + * // Failed to create the queue. + * } + * + * // ... + * + * // Post some characters that will be used within an ISR. If the queue + * // is full then this task will block for xTicksToWait ticks. + * cValueToPost = 'a'; + * xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait ); + * cValueToPost = 'b'; + * xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait ); + * + * // ... keep posting characters ... this task may block when the queue + * // becomes full. + * + * cValueToPost = 'c'; + * xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait ); + * } + * + * // ISR that outputs all the characters received on the queue. + * void vISR_Routine( void ) + * { + * BaseType_t xTaskWokenByReceive = pdFALSE; + * char cRxedChar; + * + * while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) ) + * { + * // A character was received. Output the character now. + * vOutputCharacter( cRxedChar ); + * + * // If removing the character from the queue woke the task that was + * // posting onto the queue xTaskWokenByReceive will have been set to + * // pdTRUE. No matter how many times this loop iterates only one + * // task will be woken. + * } + * + * if( xTaskWokenByReceive != ( char ) pdFALSE; + * { + * taskYIELD (); + * } + * } + * @endcode + * \ingroup QueueManagement + */ +//go:linkname XQueueReceiveFromISR C.xQueueReceiveFromISR +func XQueueReceiveFromISR(xQueue QueueHandleT, pvBuffer c.Pointer, pxHigherPriorityTaskWoken *BaseTypeT) BaseTypeT + +/** + * Queries a queue to determine if the queue is empty. This function should only be used in an ISR. + * + * @param xQueue The handle of the queue being queried + * @return pdFALSE if the queue is not empty, or pdTRUE if the queue is empty. + */ +//go:linkname XQueueIsQueueEmptyFromISR C.xQueueIsQueueEmptyFromISR +func XQueueIsQueueEmptyFromISR(xQueue QueueHandleT) BaseTypeT + +/** + * Queries a queue to determine if the queue is full. This function should only be used in an ISR. + * + * @param xQueue The handle of the queue being queried + * @return pdFALSE if the queue is not full, or pdTRUE if the queue is full. + */ +//go:linkname XQueueIsQueueFullFromISR C.xQueueIsQueueFullFromISR +func XQueueIsQueueFullFromISR(xQueue QueueHandleT) BaseTypeT + +/** + * A version of uxQueueMessagesWaiting() that can be called from an ISR. Return the number of messages stored in a queue. + * + * @param xQueue A handle to the queue being queried. + * @return The number of messages available in the queue. + */ +//go:linkname UxQueueMessagesWaitingFromISR C.uxQueueMessagesWaitingFromISR +func UxQueueMessagesWaitingFromISR(xQueue QueueHandleT) UBaseTypeT + +/* + * The functions defined above are for passing data to and from tasks. The + * functions below are the equivalents for passing data to and from + * co-routines. + * + * These functions are called from the co-routine macro implementation and + * should not be called directly from application code. Instead use the macro + * wrappers defined within croutine.h. + */ +//go:linkname XQueueCRSendFromISR C.xQueueCRSendFromISR +func XQueueCRSendFromISR(xQueue QueueHandleT, pvItemToQueue c.Pointer, xCoRoutinePreviouslyWoken BaseTypeT) BaseTypeT + +//go:linkname XQueueCRReceiveFromISR C.xQueueCRReceiveFromISR +func XQueueCRReceiveFromISR(xQueue QueueHandleT, pvBuffer c.Pointer, pxTaskWoken *BaseTypeT) BaseTypeT + +//go:linkname XQueueCRSend C.xQueueCRSend +func XQueueCRSend(xQueue QueueHandleT, pvItemToQueue c.Pointer, xTicksToWait TickTypeT) BaseTypeT + +//go:linkname XQueueCRReceive C.xQueueCRReceive +func XQueueCRReceive(xQueue QueueHandleT, pvBuffer c.Pointer, xTicksToWait TickTypeT) BaseTypeT + +/* + * For internal use only. Use xSemaphoreCreateMutex(), + * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling + * these functions directly. + */ +//go:linkname XQueueCreateMutex C.xQueueCreateMutex +func XQueueCreateMutex(ucQueueType c.Uint8T) QueueHandleT + +//go:linkname XQueueCreateMutexStatic C.xQueueCreateMutexStatic +func XQueueCreateMutexStatic(ucQueueType c.Uint8T, pxStaticQueue *StaticQueueT) QueueHandleT + +// llgo:link UBaseTypeT.XQueueCreateCountingSemaphore C.xQueueCreateCountingSemaphore +func (recv_ UBaseTypeT) XQueueCreateCountingSemaphore(uxInitialCount UBaseTypeT) QueueHandleT { + return nil +} + +// llgo:link UBaseTypeT.XQueueCreateCountingSemaphoreStatic C.xQueueCreateCountingSemaphoreStatic +func (recv_ UBaseTypeT) XQueueCreateCountingSemaphoreStatic(uxInitialCount UBaseTypeT, pxStaticQueue *StaticQueueT) QueueHandleT { + return nil +} + +//go:linkname XQueueSemaphoreTake C.xQueueSemaphoreTake +func XQueueSemaphoreTake(xQueue QueueHandleT, xTicksToWait TickTypeT) BaseTypeT + +//go:linkname XQueueGetMutexHolder C.xQueueGetMutexHolder +func XQueueGetMutexHolder(xSemaphore QueueHandleT) TaskHandleT + +//go:linkname XQueueGetMutexHolderFromISR C.xQueueGetMutexHolderFromISR +func XQueueGetMutexHolderFromISR(xSemaphore QueueHandleT) TaskHandleT + +/* + * For internal use only. Use xSemaphoreTakeMutexRecursive() or + * xSemaphoreGiveMutexRecursive() instead of calling these functions directly. + */ +//go:linkname XQueueTakeMutexRecursive C.xQueueTakeMutexRecursive +func XQueueTakeMutexRecursive(xMutex QueueHandleT, xTicksToWait TickTypeT) BaseTypeT + +//go:linkname XQueueGiveMutexRecursive C.xQueueGiveMutexRecursive +func XQueueGiveMutexRecursive(xMutex QueueHandleT) BaseTypeT + +/* + * Generic version of the function used to create a queue using dynamic memory + * allocation. This is called by other functions and macros that create other + * RTOS objects that use the queue structure as their base. + */ +// llgo:link UBaseTypeT.XQueueGenericCreate C.xQueueGenericCreate +func (recv_ UBaseTypeT) XQueueGenericCreate(uxItemSize UBaseTypeT, ucQueueType c.Uint8T) QueueHandleT { + return nil +} + +/* + * Generic version of the function used to create a queue using dynamic memory + * allocation. This is called by other functions and macros that create other + * RTOS objects that use the queue structure as their base. + */ +// llgo:link UBaseTypeT.XQueueGenericCreateStatic C.xQueueGenericCreateStatic +func (recv_ UBaseTypeT) XQueueGenericCreateStatic(uxItemSize UBaseTypeT, pucQueueStorage *c.Uint8T, pxStaticQueue *StaticQueueT, ucQueueType c.Uint8T) QueueHandleT { + return nil +} + +/* + * Generic version of the function used to retrieve the buffers of statically + * created queues. This is called by other functions and macros that retrieve + * the buffers of other statically created RTOS objects that use the queue + * structure as their base. + */ +//go:linkname XQueueGenericGetStaticBuffers C.xQueueGenericGetStaticBuffers +func XQueueGenericGetStaticBuffers(xQueue QueueHandleT, ppucQueueStorage **c.Uint8T, ppxStaticQueue **StaticQueueT) BaseTypeT + +/** + * Queue sets provide a mechanism to allow a task to block (pend) on a read + * operation from multiple queues or semaphores simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * A queue set must be explicitly created using a call to xQueueCreateSet() + * before it can be used. Once created, standard FreeRTOS queues and semaphores + * can be added to the set using calls to xQueueAddToSet(). + * xQueueSelectFromSet() is then used to determine which, if any, of the queues + * or semaphores contained in the set is in a state where a queue read or + * semaphore take operation would be successful. + * + * Note 1: See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: An additional 4 bytes of RAM is required for each space in a every + * queue added to a queue set. Therefore counting semaphores that have a high + * maximum count value should not be added to a queue set. + * + * Note 4: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param uxEventQueueLength Queue sets store events that occur on + * the queues and semaphores contained in the set. uxEventQueueLength specifies + * the maximum number of events that can be queued at once. To be absolutely + * certain that events are not lost uxEventQueueLength should be set to the + * total sum of the length of the queues added to the set, where binary + * semaphores and mutexes have a length of 1, and counting semaphores have a + * length set by their maximum count value. Examples: + * + If a queue set is to hold a queue of length 5, another queue of length 12, + * and a binary semaphore, then uxEventQueueLength should be set to + * (5 + 12 + 1), or 18. + * + If a queue set is to hold three binary semaphores then uxEventQueueLength + * should be set to (1 + 1 + 1 ), or 3. + * + If a queue set is to hold a counting semaphore that has a maximum count of + * 5, and a counting semaphore that has a maximum count of 3, then + * uxEventQueueLength should be set to (5 + 3), or 8. + * + * @return If the queue set is created successfully then a handle to the created + * queue set is returned. Otherwise NULL is returned. + */ +// llgo:link UBaseTypeT.XQueueCreateSet C.xQueueCreateSet +func (recv_ UBaseTypeT) XQueueCreateSet() QueueSetHandleT { + return nil +} + +/** + * Adds a queue or semaphore to a queue set that was previously created by a + * call to xQueueCreateSet(). + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being added to + * the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set to which the queue or semaphore + * is being added. + * + * @return If the queue or semaphore was successfully added to the queue set + * then pdPASS is returned. If the queue could not be successfully added to the + * queue set because it is already a member of a different queue set then pdFAIL + * is returned. + */ +//go:linkname XQueueAddToSet C.xQueueAddToSet +func XQueueAddToSet(xQueueOrSemaphore QueueSetMemberHandleT, xQueueSet QueueSetHandleT) BaseTypeT + +/** + * Removes a queue or semaphore from a queue set. A queue or semaphore can only + * be removed from a set if the queue or semaphore is empty. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being removed + * from the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set in which the queue or semaphore + * is included. + * + * @return If the queue or semaphore was successfully removed from the queue set + * then pdPASS is returned. If the queue was not in the queue set, or the + * queue (or semaphore) was not empty, then pdFAIL is returned. + */ +//go:linkname XQueueRemoveFromSet C.xQueueRemoveFromSet +func XQueueRemoveFromSet(xQueueOrSemaphore QueueSetMemberHandleT, xQueueSet QueueSetHandleT) BaseTypeT + +/** + * xQueueSelectFromSet() selects from the members of a queue set a queue or + * semaphore that either contains data (in the case of a queue) or is available + * to take (in the case of a semaphore). xQueueSelectFromSet() effectively + * allows a task to block (pend) on a read operation on all the queues and + * semaphores in a queue set simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueSet The queue set on which the task will (potentially) block. + * + * @param xTicksToWait The maximum time, in ticks, that the calling task will + * remain in the Blocked state (with other tasks executing) to wait for a member + * of the queue set to be ready for a successful queue read or semaphore take + * operation. + * + * @return xQueueSelectFromSet() will return the handle of a queue (cast to + * a QueueSetMemberHandle_t type) contained in the queue set that contains data, + * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained + * in the queue set that is available, or NULL if no such queue or semaphore + * exists before before the specified block time expires. + */ +//go:linkname XQueueSelectFromSet C.xQueueSelectFromSet +func XQueueSelectFromSet(xQueueSet QueueSetHandleT, xTicksToWait TickTypeT) QueueSetMemberHandleT + +/** + * A version of xQueueSelectFromSet() that can be used from an ISR. + */ +//go:linkname XQueueSelectFromSetFromISR C.xQueueSelectFromSetFromISR +func XQueueSelectFromSetFromISR(xQueueSet QueueSetHandleT) QueueSetMemberHandleT + +/* Not public API functions. */ +//go:linkname VQueueWaitForMessageRestricted C.vQueueWaitForMessageRestricted +func VQueueWaitForMessageRestricted(xQueue QueueHandleT, xTicksToWait TickTypeT, xWaitIndefinitely BaseTypeT) + +//go:linkname XQueueGenericReset C.xQueueGenericReset +func XQueueGenericReset(xQueue QueueHandleT, xNewQueue BaseTypeT) BaseTypeT + +//go:linkname VQueueSetQueueNumber C.vQueueSetQueueNumber +func VQueueSetQueueNumber(xQueue QueueHandleT, uxQueueNumber UBaseTypeT) + +//go:linkname UxQueueGetQueueNumber C.uxQueueGetQueueNumber +func UxQueueGetQueueNumber(xQueue QueueHandleT) UBaseTypeT + +//go:linkname UcQueueGetQueueType C.ucQueueGetQueueType +func UcQueueGetQueueType(xQueue QueueHandleT) c.Uint8T diff --git a/esp32/reent.go b/esp32/reent.go new file mode 100644 index 00000000..38613276 --- /dev/null +++ b/esp32/reent.go @@ -0,0 +1,11 @@ +package freertos + +import _ "unsafe" + +type X_glue struct { + Unused [8]uint8 +} + +type X_reent struct { + Unused [8]uint8 +} diff --git a/esp32/reg_base.go b/esp32/reg_base.go new file mode 100644 index 00000000..668582bf --- /dev/null +++ b/esp32/reg_base.go @@ -0,0 +1,63 @@ +package freertos + +import _ "unsafe" + +const DR_REG_UART_BASE = 0x60000000 +const DR_REG_SPI1_BASE = 0x60002000 +const DR_REG_SPI0_BASE = 0x60003000 +const DR_REG_GPIO_BASE = 0x60004000 +const DR_REG_GPIO_SD_BASE = 0x60004f00 +const DR_REG_FE2_BASE = 0x60005000 +const DR_REG_FE_BASE = 0x60006000 +const DR_REG_EFUSE_BASE = 0x60007000 +const DR_REG_RTCCNTL_BASE = 0x60008000 +const DR_REG_RTCIO_BASE = 0x60008400 +const DR_REG_SENS_BASE = 0x60008800 +const DR_REG_RTC_I2C_BASE = 0x60008C00 +const DR_REG_IO_MUX_BASE = 0x60009000 +const DR_REG_HINF_BASE = 0x6000B000 +const DR_REG_UHCI1_BASE = 0x6000C000 +const DR_REG_I2S_BASE = 0x6000F000 +const DR_REG_UART1_BASE = 0x60010000 +const DR_REG_BT_BASE = 0x60011000 +const DR_REG_I2C_EXT_BASE = 0x60013000 +const DR_REG_UHCI0_BASE = 0x60014000 +const DR_REG_SLCHOST_BASE = 0x60015000 +const DR_REG_RMT_BASE = 0x60016000 +const DR_REG_PCNT_BASE = 0x60017000 +const DR_REG_SLC_BASE = 0x60018000 +const DR_REG_LEDC_BASE = 0x60019000 +const DR_REG_NRX_BASE = 0x6001CC00 +const DR_REG_BB_BASE = 0x6001D000 +const DR_REG_PWM0_BASE = 0x6001E000 +const DR_REG_TIMERGROUP0_BASE = 0x6001F000 +const DR_REG_TIMERGROUP1_BASE = 0x60020000 +const DR_REG_RTC_SLOWMEM_BASE = 0x60021000 +const DR_REG_SYSTIMER_BASE = 0x60023000 +const DR_REG_SPI2_BASE = 0x60024000 +const DR_REG_SPI3_BASE = 0x60025000 +const DR_REG_SYSCON_BASE = 0x60026000 +const DR_REG_APB_CTRL_BASE = 0x60026000 +const DR_REG_I2C1_EXT_BASE = 0x60027000 +const DR_REG_SDMMC_BASE = 0x60028000 +const DR_REG_PERI_BACKUP_BASE = 0x6002A000 +const DR_REG_TWAI_BASE = 0x6002B000 +const DR_REG_PWM1_BASE = 0x6002C000 +const DR_REG_I2S1_BASE = 0x6002D000 +const DR_REG_UART2_BASE = 0x6002E000 +const DR_REG_USB_SERIAL_JTAG_BASE = 0x60038000 +const DR_REG_USB_WRAP_BASE = 0x60039000 +const DR_REG_AES_BASE = 0x6003A000 +const DR_REG_SHA_BASE = 0x6003B000 +const DR_REG_RSA_BASE = 0x6003C000 +const DR_REG_HMAC_BASE = 0x6003E000 +const DR_REG_DIGITAL_SIGNATURE_BASE = 0x6003D000 +const DR_REG_GDMA_BASE = 0x6003F000 +const DR_REG_APB_SARADC_BASE = 0x60040000 +const DR_REG_LCD_CAM_BASE = 0x60041000 +const DR_REG_SYSTEM_BASE = 0x600C0000 +const DR_REG_SENSITIVE_BASE = 0x600C1000 +const DR_REG_INTERRUPT_BASE = 0x600C2000 +const DR_REG_EXTMEM_BASE = 0x600C4000 +const DR_REG_ASSIST_DEBUG_BASE = 0x600CE000 +const DR_REG_WCL_BASE = 0x600D0000 diff --git a/esp32/regi2c_bbpll.go b/esp32/regi2c_bbpll.go new file mode 100644 index 00000000..5ba14388 --- /dev/null +++ b/esp32/regi2c_bbpll.go @@ -0,0 +1,123 @@ +package freertos + +import _ "unsafe" + +const I2C_BBPLL = 0x66 +const I2C_BBPLL_HOSTID = 1 +const I2C_BBPLL_IR_CAL_DELAY = 0 +const I2C_BBPLL_IR_CAL_DELAY_MSB = 3 +const I2C_BBPLL_IR_CAL_DELAY_LSB = 0 +const I2C_BBPLL_IR_CAL_CK_DIV = 0 +const I2C_BBPLL_IR_CAL_CK_DIV_MSB = 7 +const I2C_BBPLL_IR_CAL_CK_DIV_LSB = 4 +const I2C_BBPLL_IR_CAL_EXT_CAP = 1 +const I2C_BBPLL_IR_CAL_EXT_CAP_MSB = 3 +const I2C_BBPLL_IR_CAL_EXT_CAP_LSB = 0 +const I2C_BBPLL_IR_CAL_ENX_CAP = 1 +const I2C_BBPLL_IR_CAL_ENX_CAP_MSB = 4 +const I2C_BBPLL_IR_CAL_ENX_CAP_LSB = 4 +const I2C_BBPLL_IR_CAL_RSTB = 1 +const I2C_BBPLL_IR_CAL_RSTB_MSB = 5 +const I2C_BBPLL_IR_CAL_RSTB_LSB = 5 +const I2C_BBPLL_IR_CAL_START = 1 +const I2C_BBPLL_IR_CAL_START_MSB = 6 +const I2C_BBPLL_IR_CAL_START_LSB = 6 +const I2C_BBPLL_IR_CAL_UNSTOP = 1 +const I2C_BBPLL_IR_CAL_UNSTOP_MSB = 7 +const I2C_BBPLL_IR_CAL_UNSTOP_LSB = 7 +const I2C_BBPLL_OC_REF_DIV = 2 +const I2C_BBPLL_OC_REF_DIV_MSB = 3 +const I2C_BBPLL_OC_REF_DIV_LSB = 0 +const I2C_BBPLL_OC_DCHGP = 2 +const I2C_BBPLL_OC_DCHGP_MSB = 6 +const I2C_BBPLL_OC_DCHGP_LSB = 4 +const I2C_BBPLL_OC_ENB_FCAL = 2 +const I2C_BBPLL_OC_ENB_FCAL_MSB = 7 +const I2C_BBPLL_OC_ENB_FCAL_LSB = 7 +const I2C_BBPLL_OC_DIV_7_0 = 3 +const I2C_BBPLL_OC_DIV_7_0_MSB = 7 +const I2C_BBPLL_OC_DIV_7_0_LSB = 0 +const I2C_BBPLL_RSTB_DIV_ADC = 4 +const I2C_BBPLL_RSTB_DIV_ADC_MSB = 0 +const I2C_BBPLL_RSTB_DIV_ADC_LSB = 0 +const I2C_BBPLL_MODE_HF = 4 +const I2C_BBPLL_MODE_HF_MSB = 1 +const I2C_BBPLL_MODE_HF_LSB = 1 +const I2C_BBPLL_DIV_ADC = 4 +const I2C_BBPLL_DIV_ADC_MSB = 3 +const I2C_BBPLL_DIV_ADC_LSB = 2 +const I2C_BBPLL_DIV_DAC = 4 +const I2C_BBPLL_DIV_DAC_MSB = 4 +const I2C_BBPLL_DIV_DAC_LSB = 4 +const I2C_BBPLL_DIV_CPU = 4 +const I2C_BBPLL_DIV_CPU_MSB = 5 +const I2C_BBPLL_DIV_CPU_LSB = 5 +const I2C_BBPLL_OC_ENB_VCON = 4 +const I2C_BBPLL_OC_ENB_VCON_MSB = 6 +const I2C_BBPLL_OC_ENB_VCON_LSB = 6 +const I2C_BBPLL_OC_TSCHGP = 4 +const I2C_BBPLL_OC_TSCHGP_MSB = 7 +const I2C_BBPLL_OC_TSCHGP_LSB = 7 +const I2C_BBPLL_OC_DR1 = 5 +const I2C_BBPLL_OC_DR1_MSB = 2 +const I2C_BBPLL_OC_DR1_LSB = 0 +const I2C_BBPLL_OC_DR3 = 5 +const I2C_BBPLL_OC_DR3_MSB = 6 +const I2C_BBPLL_OC_DR3_LSB = 4 +const I2C_BBPLL_EN_USB = 5 +const I2C_BBPLL_EN_USB_MSB = 7 +const I2C_BBPLL_EN_USB_LSB = 7 +const I2C_BBPLL_OC_DCUR = 6 +const I2C_BBPLL_OC_DCUR_MSB = 2 +const I2C_BBPLL_OC_DCUR_LSB = 0 +const I2C_BBPLL_INC_CUR = 6 +const I2C_BBPLL_INC_CUR_MSB = 3 +const I2C_BBPLL_INC_CUR_LSB = 3 +const I2C_BBPLL_OC_DHREF_SEL = 6 +const I2C_BBPLL_OC_DHREF_SEL_MSB = 5 +const I2C_BBPLL_OC_DHREF_SEL_LSB = 4 +const I2C_BBPLL_OC_DLREF_SEL = 6 +const I2C_BBPLL_OC_DLREF_SEL_MSB = 7 +const I2C_BBPLL_OC_DLREF_SEL_LSB = 6 +const I2C_BBPLL_OR_CAL_CAP = 8 +const I2C_BBPLL_OR_CAL_CAP_MSB = 3 +const I2C_BBPLL_OR_CAL_CAP_LSB = 0 +const I2C_BBPLL_OR_CAL_UDF = 8 +const I2C_BBPLL_OR_CAL_UDF_MSB = 4 +const I2C_BBPLL_OR_CAL_UDF_LSB = 4 +const I2C_BBPLL_OR_CAL_OVF = 8 +const I2C_BBPLL_OR_CAL_OVF_MSB = 5 +const I2C_BBPLL_OR_CAL_OVF_LSB = 5 +const I2C_BBPLL_OR_CAL_END = 8 +const I2C_BBPLL_OR_CAL_END_MSB = 6 +const I2C_BBPLL_OR_CAL_END_LSB = 6 +const I2C_BBPLL_OR_LOCK = 8 +const I2C_BBPLL_OR_LOCK_MSB = 7 +const I2C_BBPLL_OR_LOCK_LSB = 7 +const I2C_BBPLL_OC_VCO_DBIAS = 9 +const I2C_BBPLL_OC_VCO_DBIAS_MSB = 1 +const I2C_BBPLL_OC_VCO_DBIAS_LSB = 0 +const I2C_BBPLL_BBADC_DELAY2 = 9 +const I2C_BBPLL_BBADC_DELAY2_MSB = 3 +const I2C_BBPLL_BBADC_DELAY2_LSB = 2 +const I2C_BBPLL_BBADC_DVDD = 9 +const I2C_BBPLL_BBADC_DVDD_MSB = 5 +const I2C_BBPLL_BBADC_DVDD_LSB = 4 +const I2C_BBPLL_BBADC_DREF = 9 +const I2C_BBPLL_BBADC_DREF_MSB = 7 +const I2C_BBPLL_BBADC_DREF_LSB = 6 +const I2C_BBPLL_BBADC_DCUR = 10 +const I2C_BBPLL_BBADC_DCUR_MSB = 1 +const I2C_BBPLL_BBADC_DCUR_LSB = 0 +const I2C_BBPLL_BBADC_INPUT_SHORT = 10 +const I2C_BBPLL_BBADC_INPUT_SHORT_MSB = 2 +const I2C_BBPLL_BBADC_INPUT_SHORT_LSB = 2 +const I2C_BBPLL_ENT_PLL = 10 +const I2C_BBPLL_ENT_PLL_MSB = 3 +const I2C_BBPLL_ENT_PLL_LSB = 3 +const I2C_BBPLL_DTEST = 10 +const I2C_BBPLL_DTEST_MSB = 5 +const I2C_BBPLL_DTEST_LSB = 4 +const I2C_BBPLL_ENT_ADC = 10 +const I2C_BBPLL_ENT_ADC_MSB = 7 +const I2C_BBPLL_ENT_ADC_LSB = 6 diff --git a/esp32/regi2c_brownout.go b/esp32/regi2c_brownout.go new file mode 100644 index 00000000..5cbe3528 --- /dev/null +++ b/esp32/regi2c_brownout.go @@ -0,0 +1,9 @@ +package freertos + +import _ "unsafe" + +const I2C_BOD = 0x61 +const I2C_BOD_HOSTID = 1 +const I2C_BOD_THRESHOLD = 0x5 +const I2C_BOD_THRESHOLD_MSB = 2 +const I2C_BOD_THRESHOLD_LSB = 0 diff --git a/esp32/regi2c_ctrl.go b/esp32/regi2c_ctrl.go new file mode 100644 index 00000000..d7ed5f89 --- /dev/null +++ b/esp32/regi2c_ctrl.go @@ -0,0 +1,46 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* Access internal registers, don't use in application */ +//go:linkname Regi2cCtrlReadReg C.regi2c_ctrl_read_reg +func Regi2cCtrlReadReg(block c.Uint8T, host_id c.Uint8T, reg_add c.Uint8T) c.Uint8T + +//go:linkname Regi2cCtrlReadRegMask C.regi2c_ctrl_read_reg_mask +func Regi2cCtrlReadRegMask(block c.Uint8T, host_id c.Uint8T, reg_add c.Uint8T, msb c.Uint8T, lsb c.Uint8T) c.Uint8T + +//go:linkname Regi2cCtrlWriteReg C.regi2c_ctrl_write_reg +func Regi2cCtrlWriteReg(block c.Uint8T, host_id c.Uint8T, reg_add c.Uint8T, data c.Uint8T) + +//go:linkname Regi2cCtrlWriteRegMask C.regi2c_ctrl_write_reg_mask +func Regi2cCtrlWriteRegMask(block c.Uint8T, host_id c.Uint8T, reg_add c.Uint8T, msb c.Uint8T, lsb c.Uint8T, data c.Uint8T) + +/* enter the critical section that protects internal registers. Don't use it in SDK. Use the functions above. */ +//go:linkname Regi2cEnterCritical C.regi2c_enter_critical +func Regi2cEnterCritical() + +//go:linkname Regi2cExitCritical C.regi2c_exit_critical +func Regi2cExitCritical() + +/** + * Restore regi2c analog calibration related configuration registers. + * This is a workaround, and is fixed on later chips + */ +//go:linkname Regi2cAnalogCaliRegRead C.regi2c_analog_cali_reg_read +func Regi2cAnalogCaliRegRead() + +//go:linkname Regi2cAnalogCaliRegWrite C.regi2c_analog_cali_reg_write +func Regi2cAnalogCaliRegWrite() + +/* Enable/Disable regi2c_saradc with calling these two functions. + With reference count protection inside. + Internal use only. +*/ +//go:linkname Regi2cSaradcEnable C.regi2c_saradc_enable +func Regi2cSaradcEnable() + +//go:linkname Regi2cSaradcDisable C.regi2c_saradc_disable +func Regi2cSaradcDisable() diff --git a/esp32/regi2c_defs.go b/esp32/regi2c_defs.go new file mode 100644 index 00000000..0bc3afff --- /dev/null +++ b/esp32/regi2c_defs.go @@ -0,0 +1,9 @@ +package freertos + +import _ "unsafe" + +const I2C_MST_ANA_CONF0_REG = 0x6000E040 +const ANA_CONFIG_REG = 0x6000E044 +const ANA_CONFIG2_REG = 0x6000E048 +const REGI2C_ANA_CALI_PD_WORKAROUND = 1 +const REGI2C_ANA_CALI_BYTE_NUM = 8 diff --git a/esp32/regi2c_dig_reg.go b/esp32/regi2c_dig_reg.go new file mode 100644 index 00000000..a786df3e --- /dev/null +++ b/esp32/regi2c_dig_reg.go @@ -0,0 +1,39 @@ +package freertos + +import _ "unsafe" + +const I2C_DIG_REG = 0x6D +const I2C_DIG_REG_HOSTID = 1 +const I2C_DIG_REG_EXT_RTC_DREG = 4 +const I2C_DIG_REG_EXT_RTC_DREG_MSB = 4 +const I2C_DIG_REG_EXT_RTC_DREG_LSB = 0 +const I2C_DIG_REG_ENX_RTC_DREG = 4 +const I2C_DIG_REG_ENX_RTC_DREG_MSB = 7 +const I2C_DIG_REG_ENX_RTC_DREG_LSB = 7 +const I2C_DIG_REG_EXT_RTC_DREG_SLEEP = 5 +const I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB = 4 +const I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB = 0 +const I2C_DIG_REG_ENX_RTC_DREG_SLEEP = 5 +const I2C_DIG_REG_ENX_RTC_DREG_SLEEP_MSB = 7 +const I2C_DIG_REG_ENX_RTC_DREG_SLEEP_LSB = 7 +const I2C_DIG_REG_EXT_DIG_DREG = 6 +const I2C_DIG_REG_EXT_DIG_DREG_MSB = 4 +const I2C_DIG_REG_EXT_DIG_DREG_LSB = 0 +const I2C_DIG_REG_ENX_DIG_DREG = 6 +const I2C_DIG_REG_ENX_DIG_DREG_MSB = 7 +const I2C_DIG_REG_ENX_DIG_DREG_LSB = 7 +const I2C_DIG_REG_EXT_DIG_DREG_SLEEP = 7 +const I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB = 4 +const I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB = 0 +const I2C_DIG_REG_ENX_DIG_DREG_SLEEP = 7 +const I2C_DIG_REG_ENX_DIG_DREG_SLEEP_MSB = 7 +const I2C_DIG_REG_ENX_DIG_DREG_SLEEP_LSB = 7 +const I2C_DIG_REG_OR_EN_CONT_CAL = 9 +const I2C_DIG_REG_OR_EN_CONT_CAL_MSB = 7 +const I2C_DIG_REG_OR_EN_CONT_CAL_LSB = 7 +const I2C_DIG_REG_XPD_RTC_REG = 13 +const I2C_DIG_REG_XPD_RTC_REG_MSB = 2 +const I2C_DIG_REG_XPD_RTC_REG_LSB = 2 +const I2C_DIG_REG_XPD_DIG_REG = 13 +const I2C_DIG_REG_XPD_DIG_REG_MSB = 3 +const I2C_DIG_REG_XPD_DIG_REG_LSB = 3 diff --git a/esp32/regi2c_lp_bias.go b/esp32/regi2c_lp_bias.go new file mode 100644 index 00000000..31580e90 --- /dev/null +++ b/esp32/regi2c_lp_bias.go @@ -0,0 +1,10 @@ +package freertos + +import _ "unsafe" + +const I2C_ULP_IR_FORCE_CODE = 5 +const I2C_ULP_IR_FORCE_CODE_MSB = 6 +const I2C_ULP_IR_FORCE_CODE_LSB = 6 +const I2C_ULP_EXT_CODE = 6 +const I2C_ULP_EXT_CODE_MSB = 7 +const I2C_ULP_EXT_CODE_LSB = 0 diff --git a/esp32/regi2c_saradc.go b/esp32/regi2c_saradc.go new file mode 100644 index 00000000..48bdaf29 --- /dev/null +++ b/esp32/regi2c_saradc.go @@ -0,0 +1,48 @@ +package freertos + +import _ "unsafe" + +const I2C_SAR_ADC = 0x69 +const I2C_SAR_ADC_HOSTID = 1 +const ADC_SAR1_ENCAL_GND_ADDR = 0x7 +const ADC_SAR1_ENCAL_GND_ADDR_MSB = 5 +const ADC_SAR1_ENCAL_GND_ADDR_LSB = 5 +const ADC_SAR2_ENCAL_GND_ADDR = 0x7 +const ADC_SAR2_ENCAL_GND_ADDR_MSB = 7 +const ADC_SAR2_ENCAL_GND_ADDR_LSB = 7 +const ADC_SAR1_INITIAL_CODE_HIGH_ADDR = 0x1 +const ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB = 0x3 +const ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB = 0x0 +const ADC_SAR1_INITIAL_CODE_LOW_ADDR = 0x0 +const ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB = 0x7 +const ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB = 0x0 +const ADC_SAR2_INITIAL_CODE_HIGH_ADDR = 0x4 +const ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB = 0x3 +const ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB = 0x0 +const ADC_SAR2_INITIAL_CODE_LOW_ADDR = 0x3 +const ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB = 0x7 +const ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB = 0x0 +const ADC_SAR1_DREF_ADDR = 0x2 +const ADC_SAR1_DREF_ADDR_MSB = 0x6 +const ADC_SAR1_DREF_ADDR_LSB = 0x4 +const ADC_SAR2_DREF_ADDR = 0x5 +const ADC_SAR2_DREF_ADDR_MSB = 0x6 +const ADC_SAR2_DREF_ADDR_LSB = 0x4 +const ADC_SAR1_SAMPLE_CYCLE_ADDR = 0x2 +const ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB = 0x2 +const ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB = 0x0 +const ADC_SARADC_DTEST_RTC_ADDR = 0x7 +const ADC_SARADC_DTEST_RTC_ADDR_MSB = 1 +const ADC_SARADC_DTEST_RTC_ADDR_LSB = 0 +const ADC_SARADC_ENT_TSENS_ADDR = 0x7 +const ADC_SARADC_ENT_TSENS_ADDR_MSB = 2 +const ADC_SARADC_ENT_TSENS_ADDR_LSB = 2 +const ADC_SARADC_ENT_RTC_ADDR = 0x7 +const ADC_SARADC_ENT_RTC_ADDR_MSB = 3 +const ADC_SARADC_ENT_RTC_ADDR_LSB = 3 +const ADC_SARADC_ENCAL_REF_ADDR = 0x7 +const ADC_SARADC_ENCAL_REF_ADDR_MSB = 4 +const ADC_SARADC_ENCAL_REF_ADDR_LSB = 4 +const I2C_SARADC_TSENS_DAC = 0x6 +const I2C_SARADC_TSENS_DAC_MSB = 3 +const I2C_SARADC_TSENS_DAC_LSB = 0 diff --git a/esp32/regi2c_ulp.go b/esp32/regi2c_ulp.go new file mode 100644 index 00000000..97dcf37a --- /dev/null +++ b/esp32/regi2c_ulp.go @@ -0,0 +1,15 @@ +package freertos + +import _ "unsafe" + +const I2C_ULP = 0x61 +const I2C_ULP_HOSTID = 1 +const I2C_ULP_IR_RESETB = 0 +const I2C_ULP_IR_RESETB_MSB = 0 +const I2C_ULP_IR_RESETB_LSB = 0 +const I2C_ULP_O_DONE_FLAG = 3 +const I2C_ULP_O_DONE_FLAG_MSB = 0 +const I2C_ULP_O_DONE_FLAG_LSB = 0 +const I2C_ULP_BG_O_DONE_FLAG = 3 +const I2C_ULP_BG_O_DONE_FLAG_MSB = 3 +const I2C_ULP_BG_O_DONE_FLAG_LSB = 3 diff --git a/esp32/reset_reasons.go b/esp32/reset_reasons.go new file mode 100644 index 00000000..4d2fff1f --- /dev/null +++ b/esp32/reset_reasons.go @@ -0,0 +1,35 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type SocResetReasonT c.Int + +const ( + RESET_REASON_CHIP_POWER_ON SocResetReasonT = 1 + RESET_REASON_CHIP_BROWN_OUT SocResetReasonT = 1 + RESET_REASON_CHIP_SUPER_WDT SocResetReasonT = 1 + RESET_REASON_CORE_SW SocResetReasonT = 3 + RESET_REASON_CORE_DEEP_SLEEP SocResetReasonT = 5 + RESET_REASON_CORE_MWDT0 SocResetReasonT = 7 + RESET_REASON_CORE_MWDT1 SocResetReasonT = 8 + RESET_REASON_CORE_RTC_WDT SocResetReasonT = 9 + RESET_REASON_CPU0_MWDT0 SocResetReasonT = 11 + RESET_REASON_CPU1_MWDT0 SocResetReasonT = 11 + RESET_REASON_CPU0_SW SocResetReasonT = 12 + RESET_REASON_CPU1_SW SocResetReasonT = 12 + RESET_REASON_CPU0_RTC_WDT SocResetReasonT = 13 + RESET_REASON_CPU1_RTC_WDT SocResetReasonT = 13 + RESET_REASON_SYS_BROWN_OUT SocResetReasonT = 15 + RESET_REASON_SYS_RTC_WDT SocResetReasonT = 16 + RESET_REASON_CPU0_MWDT1 SocResetReasonT = 17 + RESET_REASON_CPU1_MWDT1 SocResetReasonT = 17 + RESET_REASON_SYS_SUPER_WDT SocResetReasonT = 18 + RESET_REASON_SYS_CLK_GLITCH SocResetReasonT = 19 + RESET_REASON_CORE_EFUSE_CRC SocResetReasonT = 20 + RESET_REASON_CORE_USB_UART SocResetReasonT = 21 + RESET_REASON_CORE_USB_JTAG SocResetReasonT = 22 + RESET_REASON_CORE_PWR_GLITCH SocResetReasonT = 23 +) diff --git a/esp32/rmt_hal.go b/esp32/rmt_hal.go new file mode 100644 index 00000000..06ec90ec --- /dev/null +++ b/esp32/rmt_hal.go @@ -0,0 +1,54 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type RmtSocHandleT *RmtDevT + +/** + * @brief HAL context type of RMT driver + */ + +type RmtHalContextT struct { + Regs RmtSocHandleT +} + +/** + * @brief Initialize the RMT HAL driver + * + * @param hal: RMT HAL context + */ +// llgo:link (*RmtHalContextT).RmtHalInit C.rmt_hal_init +func (recv_ *RmtHalContextT) RmtHalInit() { +} + +/** + * @brief Deinitialize the RMT HAL driver + * + * @param hal: RMT HAL context + */ +// llgo:link (*RmtHalContextT).RmtHalDeinit C.rmt_hal_deinit +func (recv_ *RmtHalContextT) RmtHalDeinit() { +} + +/** + * @brief Reset RMT TX Channel + * + * @param hal: RMT HAL context + * @param channel: RMT channel number + */ +// llgo:link (*RmtHalContextT).RmtHalTxChannelReset C.rmt_hal_tx_channel_reset +func (recv_ *RmtHalContextT) RmtHalTxChannelReset(channel c.Uint32T) { +} + +/** + * @brief Reset RMT TX Channel + * + * @param hal: RMT HAL context + * @param channel: RMT channel number + */ +// llgo:link (*RmtHalContextT).RmtHalRxChannelReset C.rmt_hal_rx_channel_reset +func (recv_ *RmtHalContextT) RmtHalRxChannelReset(channel c.Uint32T) { +} diff --git a/esp32/rmt_ll.go b/esp32/rmt_ll.go new file mode 100644 index 00000000..3293c5b7 --- /dev/null +++ b/esp32/rmt_ll.go @@ -0,0 +1,20 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const RMT_LL_MAX_LOOP_COUNT_PER_BATCH = 1023 +const RMT_LL_MAX_FILTER_VALUE = 255 +const RMT_LL_MAX_IDLE_VALUE = 32767 +const RMT_LL_CHANNEL_CLOCK_MAX_PRESCALE = 256 +const RMT_LL_GROUP_CLOCK_MAX_INTEGER_PRESCALE = 256 +const RMT_LL_GROUP_CLOCK_MAX_FRACTAL_PRESCALE = 64 + +type RmtLlMemOwnerT c.Int + +const ( + RMT_LL_MEM_OWNER_SW RmtLlMemOwnerT = 0 + RMT_LL_MEM_OWNER_HW RmtLlMemOwnerT = 1 +) diff --git a/esp32/rmt_periph.go b/esp32/rmt_periph.go new file mode 100644 index 00000000..03c7ed18 --- /dev/null +++ b/esp32/rmt_periph.go @@ -0,0 +1,14 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type RmtSignalConnT struct { + Groups [1]struct { + Irq c.Int + Channels [8]struct { + } + } +} diff --git a/esp32/rmt_reg.go b/esp32/rmt_reg.go new file mode 100644 index 00000000..9191b5bd --- /dev/null +++ b/esp32/rmt_reg.go @@ -0,0 +1,356 @@ +package freertos + +import _ "unsafe" + +const RMT_CH0DATA_S = 0 +const RMT_CH1DATA_S = 0 +const RMT_CH2DATA_S = 0 +const RMT_CH3DATA_S = 0 +const RMT_CH4DATA_S = 0 +const RMT_CH5DATA_S = 0 +const RMT_CH6DATA_S = 0 +const RMT_CH7DATA_S = 0 +const RMT_TX_START_CH0_S = 0 +const RMT_MEM_RD_RST_CH0_S = 1 +const RMT_APB_MEM_RST_CH0_S = 2 +const RMT_TX_CONTI_MODE_CH0_S = 3 +const RMT_MEM_TX_WRAP_EN_CH0_S = 4 +const RMT_IDLE_OUT_LV_CH0_S = 5 +const RMT_IDLE_OUT_EN_CH0_S = 6 +const RMT_TX_STOP_CH0_S = 7 +const RMT_DIV_CNT_CH0_S = 8 +const RMT_MEM_SIZE_CH0_S = 16 +const RMT_CARRIER_EFF_EN_CH0_S = 20 +const RMT_CARRIER_EN_CH0_S = 21 +const RMT_CARRIER_OUT_LV_CH0_S = 22 +const RMT_AFIFO_RST_CH0_S = 23 +const RMT_CONF_UPDATE_CH0_S = 24 +const RMT_TX_START_CH1_S = 0 +const RMT_MEM_RD_RST_CH1_S = 1 +const RMT_APB_MEM_RST_CH1_S = 2 +const RMT_TX_CONTI_MODE_CH1_S = 3 +const RMT_MEM_TX_WRAP_EN_CH1_S = 4 +const RMT_IDLE_OUT_LV_CH1_S = 5 +const RMT_IDLE_OUT_EN_CH1_S = 6 +const RMT_TX_STOP_CH1_S = 7 +const RMT_DIV_CNT_CH1_S = 8 +const RMT_MEM_SIZE_CH1_S = 16 +const RMT_CARRIER_EFF_EN_CH1_S = 20 +const RMT_CARRIER_EN_CH1_S = 21 +const RMT_CARRIER_OUT_LV_CH1_S = 22 +const RMT_AFIFO_RST_CH1_S = 23 +const RMT_CONF_UPDATE_CH1_S = 24 +const RMT_TX_START_CH2_S = 0 +const RMT_MEM_RD_RST_CH2_S = 1 +const RMT_APB_MEM_RST_CH2_S = 2 +const RMT_TX_CONTI_MODE_CH2_S = 3 +const RMT_MEM_TX_WRAP_EN_CH2_S = 4 +const RMT_IDLE_OUT_LV_CH2_S = 5 +const RMT_IDLE_OUT_EN_CH2_S = 6 +const RMT_TX_STOP_CH2_S = 7 +const RMT_DIV_CNT_CH2_S = 8 +const RMT_MEM_SIZE_CH2_S = 16 +const RMT_CARRIER_EFF_EN_CH2_S = 20 +const RMT_CARRIER_EN_CH2_S = 21 +const RMT_CARRIER_OUT_LV_CH2_S = 22 +const RMT_AFIFO_RST_CH2_S = 23 +const RMT_CONF_UPDATE_CH2_S = 24 +const RMT_TX_START_CH3_S = 0 +const RMT_MEM_RD_RST_CH3_S = 1 +const RMT_APB_MEM_RST_CH3_S = 2 +const RMT_TX_CONTI_MODE_CH3_S = 3 +const RMT_MEM_TX_WRAP_EN_CH3_S = 4 +const RMT_IDLE_OUT_LV_CH3_S = 5 +const RMT_IDLE_OUT_EN_CH3_S = 6 +const RMT_TX_STOP_CH3_S = 7 +const RMT_DIV_CNT_CH3_S = 8 +const RMT_MEM_SIZE_CH3_S = 16 +const RMT_CARRIER_EFF_EN_CH3_S = 20 +const RMT_CARRIER_EN_CH3_S = 21 +const RMT_CARRIER_OUT_LV_CH3_S = 22 +const RMT_AFIFO_RST_CH3_S = 23 +const RMT_CONF_UPDATE_CH3_S = 24 +const RMT_DIV_CNT_CH4_S = 0 +const RMT_IDLE_THRES_CH4_S = 8 +const RMT_MEM_SIZE_CH4_S = 24 +const RMT_CARRIER_EN_CH4_S = 28 +const RMT_CARRIER_OUT_LV_CH4_S = 29 +const RMT_RX_EN_CH4_S = 0 +const RMT_MEM_WR_RST_CH4_S = 1 +const RMT_APB_MEM_RST_CH4_S = 2 +const RMT_MEM_OWNER_CH4_S = 3 +const RMT_RX_FILTER_EN_CH4_S = 4 +const RMT_RX_FILTER_THRES_CH4_S = 5 +const RMT_MEM_RX_WRAP_EN_CH4_S = 13 +const RMT_AFIFO_RST_CH4_S = 14 +const RMT_CONF_UPDATE_CH4_S = 15 +const RMT_DIV_CNT_CH5_S = 0 +const RMT_IDLE_THRES_CH5_S = 8 +const RMT_MEM_SIZE_CH5_S = 24 +const RMT_CARRIER_EN_CH5_S = 28 +const RMT_CARRIER_OUT_LV_CH5_S = 29 +const RMT_RX_EN_CH5_S = 0 +const RMT_MEM_WR_RST_CH5_S = 1 +const RMT_APB_MEM_RST_CH5_S = 2 +const RMT_MEM_OWNER_CH5_S = 3 +const RMT_RX_FILTER_EN_CH5_S = 4 +const RMT_RX_FILTER_THRES_CH5_S = 5 +const RMT_MEM_RX_WRAP_EN_CH5_S = 13 +const RMT_AFIFO_RST_CH5_S = 14 +const RMT_CONF_UPDATE_CH5_S = 15 +const RMT_DIV_CNT_CH6_S = 0 +const RMT_IDLE_THRES_CH6_S = 8 +const RMT_MEM_SIZE_CH6_S = 24 +const RMT_CARRIER_EN_CH6_S = 28 +const RMT_CARRIER_OUT_LV_CH6_S = 29 +const RMT_RX_EN_CH6_S = 0 +const RMT_MEM_WR_RST_CH6_S = 1 +const RMT_APB_MEM_RST_CH6_S = 2 +const RMT_MEM_OWNER_CH6_S = 3 +const RMT_RX_FILTER_EN_CH6_S = 4 +const RMT_RX_FILTER_THRES_CH6_S = 5 +const RMT_MEM_RX_WRAP_EN_CH6_S = 13 +const RMT_AFIFO_RST_CH6_S = 14 +const RMT_CONF_UPDATE_CH6_S = 15 +const RMT_DIV_CNT_CH7_S = 0 +const RMT_IDLE_THRES_CH7_S = 8 +const RMT_MEM_SIZE_CH7_S = 24 +const RMT_CARRIER_EN_CH7_S = 28 +const RMT_CARRIER_OUT_LV_CH7_S = 29 +const RMT_RX_EN_CH7_S = 0 +const RMT_MEM_WR_RST_CH7_S = 1 +const RMT_APB_MEM_RST_CH7_S = 2 +const RMT_MEM_OWNER_CH7_S = 3 +const RMT_RX_FILTER_EN_CH7_S = 4 +const RMT_RX_FILTER_THRES_CH7_S = 5 +const RMT_MEM_RX_WRAP_EN_CH7_S = 13 +const RMT_AFIFO_RST_CH7_S = 14 +const RMT_CONF_UPDATE_CH7_S = 15 +const RMT_MEM_RADDR_EX_CH0_S = 0 +const RMT_APB_MEM_WADDR_CH0_S = 11 +const RMT_STATE_CH0_S = 22 +const RMT_MEM_EMPTY_CH0_S = 25 +const RMT_APB_MEM_WR_ERR_CH0_S = 26 +const RMT_MEM_RADDR_EX_CH1_S = 0 +const RMT_APB_MEM_WADDR_CH1_S = 11 +const RMT_STATE_CH1_S = 22 +const RMT_MEM_EMPTY_CH1_S = 25 +const RMT_APB_MEM_WR_ERR_CH1_S = 26 +const RMT_MEM_RADDR_EX_CH2_S = 0 +const RMT_APB_MEM_WADDR_CH2_S = 11 +const RMT_STATE_CH2_S = 22 +const RMT_MEM_EMPTY_CH2_S = 25 +const RMT_APB_MEM_WR_ERR_CH2_S = 26 +const RMT_MEM_RADDR_EX_CH3_S = 0 +const RMT_APB_MEM_WADDR_CH3_S = 11 +const RMT_STATE_CH3_S = 22 +const RMT_MEM_EMPTY_CH3_S = 25 +const RMT_APB_MEM_WR_ERR_CH3_S = 26 +const RMT_MEM_WADDR_EX_CH4_S = 0 +const RMT_APB_MEM_RADDR_CH4_S = 11 +const RMT_STATE_CH4_S = 22 +const RMT_MEM_OWNER_ERR_CH4_S = 25 +const RMT_MEM_FULL_CH4_S = 26 +const RMT_APB_MEM_RD_ERR_CH4_S = 27 +const RMT_MEM_WADDR_EX_CH5_S = 0 +const RMT_APB_MEM_RADDR_CH5_S = 11 +const RMT_STATE_CH5_S = 22 +const RMT_MEM_OWNER_ERR_CH5_S = 25 +const RMT_MEM_FULL_CH5_S = 26 +const RMT_APB_MEM_RD_ERR_CH5_S = 27 +const RMT_MEM_WADDR_EX_CH6_S = 0 +const RMT_APB_MEM_RADDR_CH6_S = 11 +const RMT_STATE_CH6_S = 22 +const RMT_MEM_OWNER_ERR_CH6_S = 25 +const RMT_MEM_FULL_CH6_S = 26 +const RMT_APB_MEM_RD_ERR_CH6_S = 27 +const RMT_MEM_WADDR_EX_CH7_S = 0 +const RMT_APB_MEM_RADDR_CH7_S = 11 +const RMT_STATE_CH7_S = 22 +const RMT_MEM_OWNER_ERR_CH7_S = 25 +const RMT_MEM_FULL_CH7_S = 26 +const RMT_APB_MEM_RD_ERR_CH7_S = 27 +const RMT_CH0_TX_END_INT_RAW_S = 0 +const RMT_CH1_TX_END_INT_RAW_S = 1 +const RMT_CH2_TX_END_INT_RAW_S = 2 +const RMT_CH3_TX_END_INT_RAW_S = 3 +const RMT_CH0_ERR_INT_RAW_S = 4 +const RMT_CH1_ERR_INT_RAW_S = 5 +const RMT_CH2_ERR_INT_RAW_S = 6 +const RMT_CH3_ERR_INT_RAW_S = 7 +const RMT_CH0_TX_THR_EVENT_INT_RAW_S = 8 +const RMT_CH1_TX_THR_EVENT_INT_RAW_S = 9 +const RMT_CH2_TX_THR_EVENT_INT_RAW_S = 10 +const RMT_CH3_TX_THR_EVENT_INT_RAW_S = 11 +const RMT_CH0_TX_LOOP_INT_RAW_S = 12 +const RMT_CH1_TX_LOOP_INT_RAW_S = 13 +const RMT_CH2_TX_LOOP_INT_RAW_S = 14 +const RMT_CH3_TX_LOOP_INT_RAW_S = 15 +const RMT_CH4_RX_END_INT_RAW_S = 16 +const RMT_CH5_RX_END_INT_RAW_S = 17 +const RMT_CH6_RX_END_INT_RAW_S = 18 +const RMT_CH7_RX_END_INT_RAW_S = 19 +const RMT_CH4_ERR_INT_RAW_S = 20 +const RMT_CH5_ERR_INT_RAW_S = 21 +const RMT_CH6_ERR_INT_RAW_S = 22 +const RMT_CH7_ERR_INT_RAW_S = 23 +const RMT_CH4_RX_THR_EVENT_INT_RAW_S = 24 +const RMT_CH5_RX_THR_EVENT_INT_RAW_S = 25 +const RMT_CH6_RX_THR_EVENT_INT_RAW_S = 26 +const RMT_CH7_RX_THR_EVENT_INT_RAW_S = 27 +const RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_S = 28 +const RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_S = 29 +const RMT_CH0_TX_END_INT_ST_S = 0 +const RMT_CH1_TX_END_INT_ST_S = 1 +const RMT_CH2_TX_END_INT_ST_S = 2 +const RMT_CH3_TX_END_INT_ST_S = 3 +const RMT_CH0_ERR_INT_ST_S = 4 +const RMT_CH1_ERR_INT_ST_S = 5 +const RMT_CH2_ERR_INT_ST_S = 6 +const RMT_CH3_ERR_INT_ST_S = 7 +const RMT_CH0_TX_THR_EVENT_INT_ST_S = 8 +const RMT_CH1_TX_THR_EVENT_INT_ST_S = 9 +const RMT_CH2_TX_THR_EVENT_INT_ST_S = 10 +const RMT_CH3_TX_THR_EVENT_INT_ST_S = 11 +const RMT_CH0_TX_LOOP_INT_ST_S = 12 +const RMT_CH1_TX_LOOP_INT_ST_S = 13 +const RMT_CH2_TX_LOOP_INT_ST_S = 14 +const RMT_CH3_TX_LOOP_INT_ST_S = 15 +const RMT_CH4_RX_END_INT_ST_S = 16 +const RMT_CH5_RX_END_INT_ST_S = 17 +const RMT_CH6_RX_END_INT_ST_S = 18 +const RMT_CH7_RX_END_INT_ST_S = 19 +const RMT_CH4_ERR_INT_ST_S = 20 +const RMT_CH5_ERR_INT_ST_S = 21 +const RMT_CH6_ERR_INT_ST_S = 22 +const RMT_CH7_ERR_INT_ST_S = 23 +const RMT_CH4_RX_THR_EVENT_INT_ST_S = 24 +const RMT_CH5_RX_THR_EVENT_INT_ST_S = 25 +const RMT_CH6_RX_THR_EVENT_INT_ST_S = 26 +const RMT_CH7_RX_THR_EVENT_INT_ST_S = 27 +const RMT_CH3_DMA_ACCESS_FAIL_INT_ST_S = 28 +const RMT_CH7_DMA_ACCESS_FAIL_INT_ST_S = 29 +const RMT_CH0_TX_END_INT_ENA_S = 0 +const RMT_CH1_TX_END_INT_ENA_S = 1 +const RMT_CH2_TX_END_INT_ENA_S = 2 +const RMT_CH3_TX_END_INT_ENA_S = 3 +const RMT_CH0_ERR_INT_ENA_S = 4 +const RMT_CH1_ERR_INT_ENA_S = 5 +const RMT_CH2_ERR_INT_ENA_S = 6 +const RMT_CH3_ERR_INT_ENA_S = 7 +const RMT_CH0_TX_THR_EVENT_INT_ENA_S = 8 +const RMT_CH1_TX_THR_EVENT_INT_ENA_S = 9 +const RMT_CH2_TX_THR_EVENT_INT_ENA_S = 10 +const RMT_CH3_TX_THR_EVENT_INT_ENA_S = 11 +const RMT_CH0_TX_LOOP_INT_ENA_S = 12 +const RMT_CH1_TX_LOOP_INT_ENA_S = 13 +const RMT_CH2_TX_LOOP_INT_ENA_S = 14 +const RMT_CH3_TX_LOOP_INT_ENA_S = 15 +const RMT_CH4_RX_END_INT_ENA_S = 16 +const RMT_CH5_RX_END_INT_ENA_S = 17 +const RMT_CH6_RX_END_INT_ENA_S = 18 +const RMT_CH7_RX_END_INT_ENA_S = 19 +const RMT_CH4_ERR_INT_ENA_S = 20 +const RMT_CH5_ERR_INT_ENA_S = 21 +const RMT_CH6_ERR_INT_ENA_S = 22 +const RMT_CH7_ERR_INT_ENA_S = 23 +const RMT_CH4_RX_THR_EVENT_INT_ENA_S = 24 +const RMT_CH5_RX_THR_EVENT_INT_ENA_S = 25 +const RMT_CH6_RX_THR_EVENT_INT_ENA_S = 26 +const RMT_CH7_RX_THR_EVENT_INT_ENA_S = 27 +const RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_S = 28 +const RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_S = 29 +const RMT_CH0_TX_END_INT_CLR_S = 0 +const RMT_CH1_TX_END_INT_CLR_S = 1 +const RMT_CH2_TX_END_INT_CLR_S = 2 +const RMT_CH3_TX_END_INT_CLR_S = 3 +const RMT_CH0_ERR_INT_CLR_S = 4 +const RMT_CH1_ERR_INT_CLR_S = 5 +const RMT_CH2_ERR_INT_CLR_S = 6 +const RMT_CH3_ERR_INT_CLR_S = 7 +const RMT_CH0_TX_THR_EVENT_INT_CLR_S = 8 +const RMT_CH1_TX_THR_EVENT_INT_CLR_S = 9 +const RMT_CH2_TX_THR_EVENT_INT_CLR_S = 10 +const RMT_CH3_TX_THR_EVENT_INT_CLR_S = 11 +const RMT_CH0_TX_LOOP_INT_CLR_S = 12 +const RMT_CH1_TX_LOOP_INT_CLR_S = 13 +const RMT_CH2_TX_LOOP_INT_CLR_S = 14 +const RMT_CH3_TX_LOOP_INT_CLR_S = 15 +const RMT_CH4_RX_END_INT_CLR_S = 16 +const RMT_CH5_RX_END_INT_CLR_S = 17 +const RMT_CH6_RX_END_INT_CLR_S = 18 +const RMT_CH7_RX_END_INT_CLR_S = 19 +const RMT_CH4_ERR_INT_CLR_S = 20 +const RMT_CH5_ERR_INT_CLR_S = 21 +const RMT_CH6_ERR_INT_CLR_S = 22 +const RMT_CH7_ERR_INT_CLR_S = 23 +const RMT_CH4_RX_THR_EVENT_INT_CLR_S = 24 +const RMT_CH5_RX_THR_EVENT_INT_CLR_S = 25 +const RMT_CH6_RX_THR_EVENT_INT_CLR_S = 26 +const RMT_CH7_RX_THR_EVENT_INT_CLR_S = 27 +const RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_S = 28 +const RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_S = 29 +const RMT_CARRIER_LOW_CH0_S = 0 +const RMT_CARRIER_HIGH_CH0_S = 16 +const RMT_CARRIER_LOW_CH1_S = 0 +const RMT_CARRIER_HIGH_CH1_S = 16 +const RMT_CARRIER_LOW_CH2_S = 0 +const RMT_CARRIER_HIGH_CH2_S = 16 +const RMT_CARRIER_LOW_CH3_S = 0 +const RMT_CARRIER_HIGH_CH3_S = 16 +const RMT_CARRIER_LOW_THRES_CH4_S = 0 +const RMT_CARRIER_HIGH_THRES_CH4_S = 16 +const RMT_CARRIER_LOW_THRES_CH5_S = 0 +const RMT_CARRIER_HIGH_THRES_CH5_S = 16 +const RMT_CARRIER_LOW_THRES_CH6_S = 0 +const RMT_CARRIER_HIGH_THRES_CH6_S = 16 +const RMT_CARRIER_LOW_THRES_CH7_S = 0 +const RMT_CARRIER_HIGH_THRES_CH7_S = 16 +const RMT_TX_LIM_CH0_S = 0 +const RMT_TX_LOOP_NUM_CH0_S = 9 +const RMT_TX_LOOP_CNT_EN_CH0_S = 19 +const RMT_LOOP_COUNT_RESET_CH0_S = 20 +const RMT_LOOP_STOP_EN_CH0_S = 21 +const RMT_TX_LIM_CH1_S = 0 +const RMT_TX_LOOP_NUM_CH1_S = 9 +const RMT_TX_LOOP_CNT_EN_CH1_S = 19 +const RMT_LOOP_COUNT_RESET_CH1_S = 20 +const RMT_LOOP_STOP_EN_CH1_S = 21 +const RMT_TX_LIM_CH2_S = 0 +const RMT_TX_LOOP_NUM_CH2_S = 9 +const RMT_TX_LOOP_CNT_EN_CH2_S = 19 +const RMT_LOOP_COUNT_RESET_CH2_S = 20 +const RMT_LOOP_STOP_EN_CH2_S = 21 +const RMT_TX_LIM_CH3_S = 0 +const RMT_TX_LOOP_NUM_CH3_S = 9 +const RMT_TX_LOOP_CNT_EN_CH3_S = 19 +const RMT_LOOP_COUNT_RESET_CH3_S = 20 +const RMT_LOOP_STOP_EN_CH3_S = 21 +const RMT_RX_LIM_CH4_S = 0 +const RMT_RX_LIM_CH5_S = 0 +const RMT_RX_LIM_CH6_S = 0 +const RMT_RX_LIM_CH7_S = 0 +const RMT_APB_FIFO_MASK_S = 0 +const RMT_MEM_CLK_FORCE_ON_S = 1 +const RMT_MEM_FORCE_PD_S = 2 +const RMT_MEM_FORCE_PU_S = 3 +const RMT_SCLK_DIV_NUM_S = 4 +const RMT_SCLK_DIV_A_S = 12 +const RMT_SCLK_DIV_B_S = 18 +const RMT_SCLK_SEL_S = 24 +const RMT_SCLK_ACTIVE_S = 26 +const RMT_CLK_EN_S = 31 +const RMT_TX_SIM_CH0_S = 0 +const RMT_TX_SIM_CH1_S = 1 +const RMT_TX_SIM_CH2_S = 2 +const RMT_TX_SIM_CH3_S = 3 +const RMT_TX_SIM_EN_S = 4 +const RMT_REF_CNT_RST_CH0_S = 0 +const RMT_REF_CNT_RST_CH1_S = 1 +const RMT_REF_CNT_RST_CH2_S = 2 +const RMT_REF_CNT_RST_CH3_S = 3 +const RMT_REF_CNT_RST_CH4_S = 4 +const RMT_REF_CNT_RST_CH5_S = 5 +const RMT_REF_CNT_RST_CH6_S = 6 +const RMT_REF_CNT_RST_CH7_S = 7 +const RMT_DATE_S = 0 diff --git a/esp32/rmt_struct.go b/esp32/rmt_struct.go new file mode 100644 index 00000000..8cdce7c9 --- /dev/null +++ b/esp32/rmt_struct.go @@ -0,0 +1,190 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** Group: FIFO R/W registers */ +/** Type of chndata register + * The read and write data register for CHANNELn by apb fifo access. + */ + +type RmtChndataRegT struct { + Val c.Uint32T +} + +/** Type of chmdata register + * The read and write data register for CHANNEL$n by apb fifo access. + */ + +type RmtChmdataRegT struct { + Val c.Uint32T +} + +/** Group: Configuration registers */ +/** Type of chnconf0 register + * Channel n configure register 0 + */ + +type RmtChnconf0RegT struct { + Val c.Uint32T +} + +/** Type of chmconf0 register + * Channel m configure register 0 + */ + +type RmtChmconf0RegT struct { + Val c.Uint32T +} + +/** Type of chmconf1 register + * Channel m configure register 1 + */ + +type RmtChmconf1RegT struct { + Val c.Uint32T +} + +/** Type of chm_rx_carrier_rm register + * Channel m carrier remove register + */ + +type RmtChmRxCarrierRmRegT struct { + Val c.Uint32T +} + +/** Type of sys_conf register + * RMT apb configuration register + */ + +type RmtSysConfRegT struct { + Val c.Uint32T +} + +/** Type of ref_cnt_rst register + * RMT clock divider reset register + */ + +type RmtRefCntRstRegT struct { + Val c.Uint32T +} + +/** Group: Status registers */ +/** Type of chnstatus register + * Channel n status register + */ + +type RmtChnstatusRegT struct { + Val c.Uint32T +} + +/** Type of chmstatus register + * Channel m status register + */ + +type RmtChmstatusRegT struct { + Val c.Uint32T +} + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ + +type RmtIntRawRegT struct { + Val c.Uint32T +} + +/** Type of int_st register + * Masked interrupt status + */ + +type RmtIntStRegT struct { + Val c.Uint32T +} + +/** Type of int_ena register + * Interrupt enable bits + */ + +type RmtIntEnaRegT struct { + Val c.Uint32T +} + +/** Type of int_clr register + * Interrupt clear bits + */ + +type RmtIntClrRegT struct { + Val c.Uint32T +} + +/** Group: Carrier wave duty cycle registers */ +/** Type of chncarrier_duty register + * Channel n duty cycle configuration register + */ + +type RmtChncarrierDutyRegT struct { + Val c.Uint32T +} + +/** Group: Tx event configuration registers */ +/** Type of chn_tx_lim register + * Channel n Tx event configuration register + */ + +type RmtChnTxLimRegT struct { + Val c.Uint32T +} + +/** Type of tx_sim register + * RMT TX synchronous register + */ + +type RmtTxSimRegT struct { + Val c.Uint32T +} + +/** Group: Rx event configuration registers */ +/** Type of chm_rx_lim register + * Channel m Rx event configuration register + */ + +type RmtChmRxLimRegT struct { + Val c.Uint32T +} + +/** Group: Version register */ +/** Type of date register + * RMT version register + */ + +type RmtDateRegT struct { + Val c.Uint32T +} + +type RmtDevT struct { + Chndata [4]RmtChndataRegT + Chmdata [4]RmtChmdataRegT + Chnconf0 [4]RmtChnconf0RegT + Chmconf [4]struct { + Conf0 RmtChmconf0RegT + Conf1 RmtChmconf1RegT + } + Chnstatus [4]RmtChnstatusRegT + Chmstatus [4]RmtChmstatusRegT + IntRaw RmtIntRawRegT + IntSt RmtIntStRegT + IntEna RmtIntEnaRegT + IntClr RmtIntClrRegT + ChncarrierDuty [4]RmtChncarrierDutyRegT + ChmRxCarrierRm [4]RmtChmRxCarrierRmRegT + ChnTxLim [4]RmtChnTxLimRegT + ChmRxLim [4]RmtChmRxLimRegT + SysConf RmtSysConfRegT + TxSim RmtTxSimRegT + RefCntRst RmtRefCntRstRegT + Date RmtDateRegT +} diff --git a/esp32/rmt_types.go b/esp32/rmt_types.go new file mode 100644 index 00000000..bd1ab55d --- /dev/null +++ b/esp32/rmt_types.go @@ -0,0 +1,16 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type RmtClockSourceT SocPeriphRmtClkSrcT + +/** + * @brief The layout of RMT symbol stored in memory, which is decided by the hardware design + */ + +type RmtSymbolWordT struct { + Val c.Uint32T +} diff --git a/esp32/rom_layout.go b/esp32/rom_layout.go new file mode 100644 index 00000000..10b1502e --- /dev/null +++ b/esp32/rom_layout.go @@ -0,0 +1,58 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const SUPPORT_WIFI = 1 +const SUPPORT_BTDM = 1 +const SUPPORT_USB_DWCOTG = 1 + +/* Structure and functions for returning ROM global layout + * + * This is for address symbols defined in the linker script, which may change during ECOs. + */ + +type EtsRomLayoutT struct { + Dram0StackSharedMemStart c.Pointer + Dram0RtosReservedStart c.Pointer + StackSentry c.Pointer + Stack c.Pointer + StackSentryApp c.Pointer + StackApp c.Pointer + DataStartBtdm c.Pointer + DataEndBtdm c.Pointer + BssStartBtdm c.Pointer + BssEndBtdm c.Pointer + DataStartBtdmRom c.Pointer + DataEndBtdmRom c.Pointer + DataStartInterfaceBtdm c.Pointer + DataEndInterfaceBtdm c.Pointer + BssStartInterfaceBtdm c.Pointer + BssEndInterfaceBtdm c.Pointer + DramStartPhyrom c.Pointer + DramEndPhyrom c.Pointer + DramStartCoexist c.Pointer + DramEndCoexist c.Pointer + DramStartNet80211 c.Pointer + DramEndNet80211 c.Pointer + DramStartPp c.Pointer + DramEndPp c.Pointer + DataStartInterfaceCoexist c.Pointer + DataEndInterfaceCoexist c.Pointer + BssStartInterfaceCoexist c.Pointer + BssEndInterfaceCoexist c.Pointer + DataStartInterfaceNet80211 c.Pointer + DataEndInterfaceNet80211 c.Pointer + BssStartInterfaceNet80211 c.Pointer + BssEndInterfaceNet80211 c.Pointer + DataStartInterfacePp c.Pointer + DataEndInterfacePp c.Pointer + BssStartInterfacePp c.Pointer + BssEndInterfacePp c.Pointer + DramStartUsbDwcotgRom c.Pointer + DramEndUsbDwcotgRom c.Pointer + DramStartUartRom c.Pointer + DramEndUartRom c.Pointer +} diff --git a/esp32/rsa_pss.go b/esp32/rsa_pss.go new file mode 100644 index 00000000..90d9b64f --- /dev/null +++ b/esp32/rsa_pss.go @@ -0,0 +1,27 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ETS_SIG_LEN = 384 +const ETS_DIGEST_LEN = 32 + +type EtsRsaPubkeyT struct { + N [384]c.Uint8T + E c.Uint32T + Rinv [384]c.Uint8T + Mdash c.Uint32T +} + +// llgo:link (*EtsRsaPubkeyT).EtsRsaPssVerify C.ets_rsa_pss_verify +func (recv_ *EtsRsaPubkeyT) EtsRsaPssVerify(sig *c.Uint8T, digest *c.Uint8T, verified_digest *c.Uint8T) bool { + return false +} + +//go:linkname EtsMgf1Sha256 C.ets_mgf1_sha256 +func EtsMgf1Sha256(mgfSeed *c.Uint8T, seedLen c.SizeT, maskLen c.SizeT, mask *c.Uint8T) + +//go:linkname EtsEmsaPssVerify C.ets_emsa_pss_verify +func EtsEmsaPssVerify(encoded_message *c.Uint8T, mhash *c.Uint8T) bool diff --git a/esp32/rtc.go b/esp32/rtc.go new file mode 100644 index 00000000..3bd9ebf5 --- /dev/null +++ b/esp32/rtc.go @@ -0,0 +1,853 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const OTHER_BLOCKS_POWERUP = 1 +const OTHER_BLOCKS_WAIT = 1 +const RTC_CNTL_DBIAS_SLP = 5 +const RTC_CNTL_DBIAS_0V90 = 13 +const RTC_CNTL_DBIAS_0V95 = 16 +const RTC_CNTL_DBIAS_1V00 = 18 +const RTC_CNTL_DBIAS_1V05 = 20 +const RTC_CNTL_DBIAS_1V10 = 23 +const RTC_CNTL_DBIAS_1V15 = 25 +const RTC_CNTL_DBIAS_1V20 = 28 +const RTC_CNTL_DBIAS_1V25 = 30 +const RTC_CNTL_DBIAS_1V30 = 31 +const SOC_DELAY_RTC_FAST_CLK_SWITCH = 3 +const SOC_DELAY_RTC_SLOW_CLK_SWITCH = 300 +const SOC_DELAY_RC_FAST_ENABLE = 50 +const SOC_DELAY_RC_FAST_DIGI_SWITCH = 5 +const RTC_CNTL_PLL_BUF_WAIT_DEFAULT = 20 +const RTC_CNTL_XTL_BUF_WAIT_DEFAULT = 100 +const RTC_CNTL_CK8M_WAIT_DEFAULT = 20 +const RTC_CK8M_ENABLE_WAIT_DEFAULT = 5 +const RTC_CNTL_CK8M_DFREQ_DEFAULT = 100 +const RTC_CNTL_SCK_DCAP_DEFAULT = 255 +const RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT = 5 +const RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP = 0 +const RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT = 14 +const RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW = 15 +const RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP = 0 +const RTC_CNTL_BIASSLP_SLEEP_DEFAULT = 1 +const RTC_CNTL_BIASSLP_SLEEP_ON = 0 +const RTC_CNTL_PD_CUR_SLEEP_DEFAULT = 1 +const RTC_CNTL_PD_CUR_SLEEP_ON = 0 +const RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT = 0xf +const RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT = 0 +const RTC_CNTL_BIASSLP_MONITOR_DEFAULT = 1 +const RTC_CNTL_BIASSLP_MONITOR_ON = 0 +const RTC_CNTL_PD_CUR_MONITOR_DEFAULT = 1 +const RTC_CNTL_PD_CUR_MONITOR_ON = 0 +const K_RTC_MID_MUL10000 = 198 +const K_DIG_MID_MUL10000 = 211 +const V_RTC_MID_MUL10000 = 10181 +const V_DIG_MID_MUL10000 = 10841 +const DEFAULT_LDO_SLAVE = 0x7 +const RTC_CLK_CAL_FRACT = 19 +const RTC_VDDSDIO_TIEH_1_8V = 0 +const RTC_VDDSDIO_TIEH_3_3V = 1 + +/** + * @brief CPU clock configuration structure + */ + +type RtcCpuFreqConfigS struct { + Source SocCpuClkSrcT + SourceFreqMhz c.Uint32T + Div c.Uint32T + FreqMhz c.Uint32T +} +type RtcCpuFreqConfigT RtcCpuFreqConfigS +type RtcCalSelT c.Int + +const ( + RTC_CAL_RTC_MUX RtcCalSelT = 0 + RTC_CAL_8MD256 RtcCalSelT = 1 + RTC_CAL_32K_XTAL RtcCalSelT = 2 + RTC_CAL_INTERNAL_OSC RtcCalSelT = 3 +) + +/** + * Initialization parameters for rtc_clk_init + */ + +type RtcClkConfigT struct { + XtalFreq SocXtalFreqT + CpuFreqMhz c.Uint32T + FastClkSrc SocRtcFastClkSrcT + SlowClkSrc SocRtcSlowClkSrcT + ClkRtcClkDiv c.Uint32T + Clk8mClkDiv c.Uint32T + SlowClkDcap c.Uint32T + Clk8mDfreq c.Uint32T +} + +type RtcInitConfigT struct { + WifiPowerupCycles c.Uint16T + WifiWaitCycles c.Uint16T + BtPowerupCycles c.Uint16T + BtWaitCycles c.Uint16T + RtcPowerupCycles c.Uint16T + RtcWaitCycles c.Uint16T + CpuTopPowerupCycles c.Uint16T + CpuTopWaitCycles c.Uint16T + DgWrapPowerupCycles c.Uint16T + DgWrapWaitCycles c.Uint16T + DgPeriPowerupCycles c.Uint16T + DgPeriWaitCycles c.Uint16T + RtcMemPowerupCycles c.Uint16T + RtcMemWaitCycles c.Uint16T +} + +//go:linkname RtcClkDividerSet C.rtc_clk_divider_set +func RtcClkDividerSet(div c.Uint32T) + +//go:linkname RtcClk8mDividerSet C.rtc_clk_8m_divider_set +func RtcClk8mDividerSet(div c.Uint32T) + +/** + * Initialize clocks and set CPU frequency + * + * @param cfg clock configuration as rtc_clk_config_t + */ +// llgo:link RtcClkConfigT.RtcClkInit C.rtc_clk_init +func (recv_ RtcClkConfigT) RtcClkInit() { +} + +/** + * @brief Get main XTAL frequency + * + * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to + * rtc_clk_init function + * + * @return XTAL frequency, one of soc_xtal_freq_t + */ +//go:linkname RtcClkXtalFreqGet C.rtc_clk_xtal_freq_get +func RtcClkXtalFreqGet() SocXtalFreqT + +/** + * @brief Update XTAL frequency + * + * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored + * after startup. + * + * @param xtal_freq New frequency value + */ +// llgo:link SocXtalFreqT.RtcClkXtalFreqUpdate C.rtc_clk_xtal_freq_update +func (recv_ SocXtalFreqT) RtcClkXtalFreqUpdate() { +} + +/** + * @brief Enable or disable 32 kHz XTAL oscillator + * @param en true to enable, false to disable + */ +//go:linkname RtcClk32kEnable C.rtc_clk_32k_enable +func RtcClk32kEnable(en bool) + +/** + * @brief Configure 32 kHz XTAL oscillator to accept external clock signal + */ +//go:linkname RtcClk32kEnableExternal C.rtc_clk_32k_enable_external +func RtcClk32kEnableExternal() + +/** + * @brief Disable 32 kHz XTAL oscillator input. + */ +//go:linkname RtcClk32kDisableExternal C.rtc_clk_32k_disable_external +func RtcClk32kDisableExternal() + +/** + * @brief Get the state of 32k XTAL oscillators + * @return true if 32k XTAL oscillator has been enabled + */ +//go:linkname RtcClk32kEnabled C.rtc_clk_32k_enabled +func RtcClk32kEnabled() bool + +/** + * @brief Enable 32k oscillator, configuring it for fast startup time. + * Note: to achieve higher frequency stability, rtc_clk_32k_enable function + * must be called one the 32k XTAL oscillator has started up. This function + * will initially disable the 32k XTAL oscillator, so it should not be called + * when the system is using 32k XTAL as RTC_SLOW_CLK. + * + * @param cycle Number of 32kHz cycles to bootstrap external crystal. + * If 0, no square wave will be used to bootstrap crystal oscillation. + */ +//go:linkname RtcClk32kBootstrap C.rtc_clk_32k_bootstrap +func RtcClk32kBootstrap(cycle c.Uint32T) + +/** + * @brief Enable or disable 8 MHz internal oscillator + * + * Output from 8 MHz internal oscillator is passed into a configurable + * divider, which by default divides the input clock frequency by 256. + * Output of the divider may be used as RTC_SLOW_CLK source. + * Output of the divider is referred to in register descriptions and code as + * 8md256 or simply d256. Divider values other than 256 may be configured, but + * this facility is not currently needed, so is not exposed in the code. + * + * When 8MHz/256 divided output is not needed, the divider should be disabled + * to reduce power consumption. + * + * @param clk_8m_en true to enable 8MHz generator + * @param d256_en true to enable /256 divider + */ +//go:linkname RtcClk8mEnable C.rtc_clk_8m_enable +func RtcClk8mEnable(clk_8m_en bool, d256_en bool) + +/** + * @brief Get the state of 8 MHz internal oscillator + * @return true if the oscillator is enabled + */ +//go:linkname RtcClk8mEnabled C.rtc_clk_8m_enabled +func RtcClk8mEnabled() bool + +/** + * @brief Get the state of /256 divider which is applied to 8MHz clock + * @return true if the divided output is enabled + */ +//go:linkname RtcClk8md256Enabled C.rtc_clk_8md256_enabled +func RtcClk8md256Enabled() bool + +/** + * @brief Select source for RTC_SLOW_CLK + * @param clk_src clock source (one of soc_rtc_slow_clk_src_t values) + */ +// llgo:link SocRtcSlowClkSrcT.RtcClkSlowSrcSet C.rtc_clk_slow_src_set +func (recv_ SocRtcSlowClkSrcT) RtcClkSlowSrcSet() { +} + +/** + * @brief Get the RTC_SLOW_CLK source + * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) + */ +//go:linkname RtcClkSlowSrcGet C.rtc_clk_slow_src_get +func RtcClkSlowSrcGet() SocRtcSlowClkSrcT + +/** + * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz + * + * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000 + * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~68000 + * + * rtc_clk_cal function can be used to get more precise value by comparing + * RTC_SLOW_CLK frequency to the frequency of main XTAL. + * + * @return RTC_SLOW_CLK frequency, in Hz + */ +//go:linkname RtcClkSlowFreqGetHz C.rtc_clk_slow_freq_get_hz +func RtcClkSlowFreqGetHz() c.Uint32T + +/** + * @brief Select source for RTC_FAST_CLK + * @param clk_src clock source (one of soc_rtc_fast_clk_src_t values) + */ +// llgo:link SocRtcFastClkSrcT.RtcClkFastSrcSet C.rtc_clk_fast_src_set +func (recv_ SocRtcFastClkSrcT) RtcClkFastSrcSet() { +} + +/** + * @brief Get the RTC_FAST_CLK source + * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) + */ +//go:linkname RtcClkFastSrcGet C.rtc_clk_fast_src_get +func RtcClkFastSrcGet() SocRtcFastClkSrcT + +/** + * @brief Get CPU frequency config for a given frequency + * @param freq_mhz Frequency in MHz + * @param[out] out_config Output, CPU frequency configuration structure + * @return true if frequency can be obtained, false otherwise + */ +//go:linkname RtcClkCpuFreqMhzToConfig C.rtc_clk_cpu_freq_mhz_to_config +func RtcClkCpuFreqMhzToConfig(freq_mhz c.Uint32T, out_config *RtcCpuFreqConfigT) bool + +/** + * @brief Switch CPU frequency + * + * This function sets CPU frequency according to the given configuration + * structure. It enables PLLs, if necessary. + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +// llgo:link (*RtcCpuFreqConfigT).RtcClkCpuFreqSetConfig C.rtc_clk_cpu_freq_set_config +func (recv_ *RtcCpuFreqConfigT) RtcClkCpuFreqSetConfig() { +} + +/** + * @brief Switch CPU frequency (optimized for speed) + * + * This function is a faster equivalent of rtc_clk_cpu_freq_set_config. + * It works faster because it does not disable PLLs when switching from PLL to + * XTAL and does not enabled them when switching back. If PLL is not already + * enabled when this function is called to switch from XTAL to PLL frequency, + * or the PLL which is enabled is the wrong one, this function will fall back + * to calling rtc_clk_cpu_freq_set_config. + * + * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data, + * so it is less safe to use it e.g. from a panic handler (when memory might + * be corrupted). + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +// llgo:link (*RtcCpuFreqConfigT).RtcClkCpuFreqSetConfigFast C.rtc_clk_cpu_freq_set_config_fast +func (recv_ *RtcCpuFreqConfigT) RtcClkCpuFreqSetConfigFast() { +} + +/** + * @brief Get the currently used CPU frequency configuration + * @param[out] out_config Output, CPU frequency configuration structure + */ +// llgo:link (*RtcCpuFreqConfigT).RtcClkCpuFreqGetConfig C.rtc_clk_cpu_freq_get_config +func (recv_ *RtcCpuFreqConfigT) RtcClkCpuFreqGetConfig() { +} + +/** + * @brief Switch CPU clock source to XTAL + * + * Short form for filling in rtc_cpu_freq_config_t structure and calling + * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. + * Assumes that XTAL frequency has been determined — don't call in startup code. + * + * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose. + * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use, + * if so, then BBPLL will not be turned off. + */ +//go:linkname RtcClkCpuFreqSetXtal C.rtc_clk_cpu_freq_set_xtal +func RtcClkCpuFreqSetXtal() + +/** + * @brief Store new APB frequency value in RAM + * + * This function doesn't change any hardware clocks. + * + * Functions which perform frequency switching and change APB frequency call + * this function to update the value of APB frequency stored in RAM. + * (This should not normally be called from application code.) + * + * @param apb_freq new APB frequency, in Hz + */ +//go:linkname RtcClkApbFreqUpdate C.rtc_clk_apb_freq_update +func RtcClkApbFreqUpdate(apb_freq c.Uint32T) + +/** + * @brief Get the current stored APB frequency. + * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz. + */ +//go:linkname RtcClkApbFreqGet C.rtc_clk_apb_freq_get +func RtcClkApbFreqGet() c.Uint32T + +// llgo:link RtcCalSelT.RtcClkCalInternal C.rtc_clk_cal_internal +func (recv_ RtcCalSelT) RtcClkCalInternal(slowclk_cycles c.Uint32T) c.Uint32T { + return 0 +} + +/** + * @brief Measure RTC slow clock's period, based on main XTAL frequency + * + * This function will time out and return 0 if the time for the given number + * of cycles to be counted exceeds the expected time twice. This may happen if + * 32k XTAL is being calibrated, but the oscillator has not started up (due to + * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). + * + * @note When 32k CLK is being calibrated, this function will check the accuracy + * of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if + * the check fails, then consider this an invalid 32k clock and return 0. This + * check can filter some jamming signal. + * + * @param cal_clk clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average slow clock period in microseconds, Q13.19 fixed point format, + * or 0 if calibration has timed out + */ +// llgo:link RtcCalSelT.RtcClkCal C.rtc_clk_cal +func (recv_ RtcCalSelT) RtcClkCal(slow_clk_cycles c.Uint32T) c.Uint32T { + return 0 +} + +/** + * @brief Measure ratio between XTAL frequency and RTC slow clock frequency + * @param cal_clk slow clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average ratio between XTAL frequency and slow clock frequency, + * Q13.19 fixed point format, or 0 if calibration has timed out. + */ +// llgo:link RtcCalSelT.RtcClkCalRatio C.rtc_clk_cal_ratio +func (recv_ RtcCalSelT) RtcClkCalRatio(slow_clk_cycles c.Uint32T) c.Uint32T { + return 0 +} + +/** + * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles + * @param time_in_us Time interval in microseconds + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return number of slow clock cycles + */ +//go:linkname RtcTimeUsToSlowclk C.rtc_time_us_to_slowclk +func RtcTimeUsToSlowclk(time_in_us c.Uint64T, period c.Uint32T) c.Uint64T + +/** + * @brief Convert time interval from RTC_SLOW_CLK to microseconds + * @param time_in_us Time interval in RTC_SLOW_CLK cycles + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return time interval in microseconds + */ +//go:linkname RtcTimeSlowclkToUs C.rtc_time_slowclk_to_us +func RtcTimeSlowclkToUs(rtc_cycles c.Uint64T, period c.Uint32T) c.Uint64T + +/** + * @brief Get current value of RTC counter + * + * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK + * cycles. Counter value is not writable by software. The value is not adjusted + * when switching to a different RTC_SLOW_CLK source. + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter + */ +//go:linkname RtcTimeGet C.rtc_time_get +func RtcTimeGet() c.Uint64T + +/** + * @brief Busy loop until next RTC_SLOW_CLK cycle + * + * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. + * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return + * one RTC_SLOW_CLK cycle later. + */ +//go:linkname RtcClkWaitForSlowCycle C.rtc_clk_wait_for_slow_cycle +func RtcClkWaitForSlowCycle() + +/** + * @brief Enable the rtc digital 8M clock + * + * This function is used to enable the digital rtc 8M clock to support peripherals. + * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above. + */ +//go:linkname RtcDigClk8mEnable C.rtc_dig_clk8m_enable +func RtcDigClk8mEnable() + +/** + * @brief Disable the rtc digital 8M clock + * + * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals. + */ +//go:linkname RtcDigClk8mDisable C.rtc_dig_clk8m_disable +func RtcDigClk8mDisable() + +/** + * @brief Get whether the rtc digital 8M clock is enabled + */ +//go:linkname RtcDig8mEnabled C.rtc_dig_8m_enabled +func RtcDig8mEnabled() bool + +/** + * @brief Calculate the real clock value after the clock calibration + * + * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal` + * @return Frequency of the clock in Hz + */ +//go:linkname RtcClkFreqCal C.rtc_clk_freq_cal +func RtcClkFreqCal(cal_val c.Uint32T) c.Uint32T + +/** + * @brief Calculate the slow clock period value by slow clock frequency + * + * @param freq_hz Frequency of the slow clock in Hz + * @return Fixed point value of slow clock period in microseconds + */ +//go:linkname RtcClkFreqToPeriod C.rtc_clk_freq_to_period +func RtcClkFreqToPeriod(freq_hz c.Uint32T) c.Uint32T + +/** + * @brief Power up flags for rtc_sleep_pd function + */ + +type RtcSleepPuConfigT struct { + DigFpu c.Uint32T + RtcFpu c.Uint32T + CpuFpu c.Uint32T + I2sFpu c.Uint32T + BbFpu c.Uint32T + NrxFpu c.Uint32T + FeFpu c.Uint32T + SramFpu c.Uint32T + RomRamFpu c.Uint32T +} + +// llgo:link RtcSleepPuConfigT.RtcSleepPu C.rtc_sleep_pu +func (recv_ RtcSleepPuConfigT) RtcSleepPu() { +} + +/** + * @brief sleep configuration for rtc_sleep_init function + */ + +type RtcSleepConfigT struct { + LslpMemInfFpu c.Uint32T + RtcMemInfFollowCpu c.Uint32T + RtcFastmemPdEn c.Uint32T + RtcSlowmemPdEn c.Uint32T + RtcPeriPdEn c.Uint32T + ModemPdEn c.Uint32T + CpuPdEn c.Uint32T + Int8mPdEn c.Uint32T + DigPeriPdEn c.Uint32T + DeepSlp c.Uint32T + WdtFlashbootModEn c.Uint32T + DigDbiasSlp c.Uint32T + RtcDbiasSlp c.Uint32T + BiasSleepMonitor c.Uint32T + DbgAttenSlp c.Uint32T + BiasSleepSlp c.Uint32T + PdCurMonitor c.Uint32T + PdCurSlp c.Uint32T + VddsdioPdEn c.Uint32T + XtalFpu c.Uint32T + RtcRegulatorFpu c.Uint32T + DeepSlpReject c.Uint32T + LightSlpReject c.Uint32T +} + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +//go:linkname RtcSleepGetDefaultConfig C.rtc_sleep_get_default_config +func RtcSleepGetDefaultConfig(sleep_flags c.Uint32T, out_config *RtcSleepConfigT) + +/** + * @brief Prepare the chip to enter sleep mode + * + * This function configures various power control state machines to handle + * entry into light sleep or deep sleep mode, switches APB and CPU clock source + * (usually to XTAL), and sets bias voltages for digital and RTC power domains. + * + * This function does not actually enter sleep mode; this is done using + * rtc_sleep_start function. Software may do some other actions between + * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure + * wakeup sources. + * @param cfg sleep mode configuration + */ +// llgo:link RtcSleepConfigT.RtcSleepInit C.rtc_sleep_init +func (recv_ RtcSleepConfigT) RtcSleepInit() { +} + +/** + * @brief Low level initialize for rtc state machine waiting cycles after waking up + * + * This function configures the cycles chip need to wait for internal 8MHz + * oscillator and external 40MHz crystal. As we configure fixed time for waiting + * crystal, we need to pass period to calculate cycles. Now this function only + * used in lightsleep mode. + * + * @param slowclk_period re-calibrated slow clock period + * @param dslp true if initialize for deepsleep request + */ +//go:linkname RtcSleepLowInit C.rtc_sleep_low_init +func RtcSleepLowInit(slowclk_period c.Uint32T, dslp bool) + +/** + * @brief Enter deep or light sleep mode + * + * This function enters the sleep mode previously configured using rtc_sleep_init + * function. Before entering sleep, software should configure wake up sources + * appropriately (set up GPIO wakeup registers, timer wakeup registers, + * and so on). + * + * If deep sleep mode was configured using rtc_sleep_init, and sleep is not + * rejected by hardware (based on reject_opt flags), this function never returns. + * When the chip wakes up from deep sleep, CPU is reset and execution starts + * from ROM bootloader. + * + * If light sleep mode was configured using rtc_sleep_init, this function + * returns on wakeup, or if sleep is rejected by hardware. + * + * @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags + * combined with OR) + * @param reject_opt bit mask of sleep reject reasons: + * - RTC_CNTL_GPIO_REJECT_EN + * - RTC_CNTL_SDIO_REJECT_EN + * These flags are used to prevent entering sleep when e.g. + * an external host is communicating via SDIO slave + * @param lslp_mem_inf_fpu If non-zero then the low power config is restored + * immediately on wake. Recommended for light sleep, + * has no effect if the system goes into deep sleep. + * + * @return non-zero if sleep was rejected by hardware + */ +//go:linkname RtcSleepStart C.rtc_sleep_start +func RtcSleepStart(wakeup_opt c.Uint32T, reject_opt c.Uint32T, lslp_mem_inf_fpu c.Uint32T) c.Uint32T + +/** + * @brief Enter deep sleep mode + * + * Similar to rtc_sleep_start(), but additionally uses hardware to calculate the CRC value + * of RTC FAST memory. On wake, this CRC is used to determine if a deep sleep wake + * stub is valid to execute (if a wake address is set). + * + * No RAM is accessed while calculating the CRC and going into deep sleep, which makes + * this function safe to use even if the caller's stack is in RTC FAST memory. + * + * @note If no deep sleep wake stub address is set then calling rtc_sleep_start() will + * have the same effect and takes less time as CRC calculation is skipped. + * + * @note This function should only be called after rtc_sleep_init() has been called to + * configure the system for deep sleep. + * + * @param wakeup_opt - same as for rtc_sleep_start + * @param reject_opt - same as for rtc_sleep_start + * + * @return non-zero if sleep was rejected by hardware + */ +//go:linkname RtcDeepSleepStart C.rtc_deep_sleep_start +func RtcDeepSleepStart(wakeup_opt c.Uint32T, reject_opt c.Uint32T) c.Uint32T + +/** + * RTC power and clock control initialization settings + */ + +type RtcConfigT struct { + Ck8mWait c.Uint32T + XtalWait c.Uint32T + PllWait c.Uint32T + ClkctlInit c.Uint32T + PwrctlInit c.Uint32T + RtcDboostFpd c.Uint32T + XtalFpu c.Uint32T + BbpllFpu c.Uint32T + CpuWaitiClkGate c.Uint32T + CaliOcode c.Uint32T +} + +/** + * Initialize RTC clock and power control related functions + * @param cfg configuration options as rtc_config_t + */ +// llgo:link RtcConfigT.RtcInit C.rtc_init +func (recv_ RtcConfigT) RtcInit() { +} + +/** + * Structure describing vddsdio configuration + */ + +type RtcVddsdioConfigT struct { + Force c.Uint32T + Enable c.Uint32T + Tieh c.Uint32T + Drefh c.Uint32T + Drefm c.Uint32T + Drefl c.Uint32T +} + +/** + * Get current VDDSDIO configuration + * If VDDSDIO configuration is overridden by RTC, get values from RTC + * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE + * Otherwise, use default values and the level of MTDI bootstrapping pin. + * @return currently used VDDSDIO configuration + */ +//go:linkname RtcVddsdioGetConfig C.rtc_vddsdio_get_config +func RtcVddsdioGetConfig() RtcVddsdioConfigT + +/** + * Set new VDDSDIO configuration using RTC registers. + * If config.force == 1, this overrides configuration done using bootstrapping + * pins and EFUSE. + * + * @param config new VDDSDIO configuration + */ +// llgo:link RtcVddsdioConfigT.RtcVddsdioSetConfig C.rtc_vddsdio_set_config +func (recv_ RtcVddsdioConfigT) RtcVddsdioSetConfig() { +} + +type RtcCpuFreqSrcT SocCpuClkSrcT +type RtcSlowFreqT SocRtcSlowClkSrcT +type RtcFastFreqT SocRtcFastClkSrcT +type RtcXtalFreqT SocXtalFreqT + +/** + * @brief Get current value of RTC counter in microseconds + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter in microseconds + */ +//go:linkname EspRtcGetTimeUs C.esp_rtc_get_time_us +func EspRtcGetTimeUs() c.Uint64T + +type SLEEPMODE c.Int + +const ( + AWAKE SLEEPMODE = 0 + LIGHT_SLEEP SLEEPMODE = 1 + DEEP_SLEEP SLEEPMODE = 2 +) + +type RESETREASON c.Int + +const ( + NO_MEAN RESETREASON = 0 + POWERON_RESET RESETREASON = 1 + RTC_SW_SYS_RESET RESETREASON = 3 + DEEPSLEEP_RESET RESETREASON = 5 + TG0WDT_SYS_RESET RESETREASON = 7 + TG1WDT_SYS_RESET RESETREASON = 8 + RTCWDT_SYS_RESET RESETREASON = 9 + INTRUSION_RESET RESETREASON = 10 + TG0WDT_CPU_RESET RESETREASON = 11 + RTC_SW_CPU_RESET RESETREASON = 12 + RTCWDT_CPU_RESET RESETREASON = 13 + RTCWDT_BROWN_OUT_RESET RESETREASON = 15 + RTCWDT_RTC_RESET RESETREASON = 16 + TG1WDT_CPU_RESET RESETREASON = 17 + SUPER_WDT_RESET RESETREASON = 18 + GLITCH_RTC_RESET RESETREASON = 19 + EFUSE_RESET RESETREASON = 20 + USB_UART_CHIP_RESET RESETREASON = 21 + USB_JTAG_CHIP_RESET RESETREASON = 22 + POWER_GLITCH_RESET RESETREASON = 23 +) + +type WAKEUPREASON c.Int + +const ( + NO_SLEEP WAKEUPREASON = 0 + EXT_EVENT0_TRIG WAKEUPREASON = 1 + EXT_EVENT1_TRIG WAKEUPREASON = 2 + GPIO_TRIG WAKEUPREASON = 4 + TIMER_EXPIRE WAKEUPREASON = 8 + SDIO_TRIG WAKEUPREASON = 16 + MAC_TRIG WAKEUPREASON = 32 + UART0_TRIG WAKEUPREASON = 64 + UART1_TRIG WAKEUPREASON = 128 + TOUCH_TRIG WAKEUPREASON = 256 + SAR_TRIG WAKEUPREASON = 512 + BT_TRIG WAKEUPREASON = 1024 + RISCV_TRIG WAKEUPREASON = 2048 + XTAL_DEAD_TRIG WAKEUPREASON = 4096 + RISCV_TRAP_TRIG WAKEUPREASON = 8192 + USB_TRIG WAKEUPREASON = 16384 +) + +type WAKEUPENABLE c.Int + +const ( + DISEN_WAKEUP WAKEUPENABLE = 0 + EXT_EVENT0_TRIG_EN WAKEUPENABLE = 1 + EXT_EVENT1_TRIG_EN WAKEUPENABLE = 2 + GPIO_TRIG_EN WAKEUPENABLE = 4 + TIMER_EXPIRE_EN WAKEUPENABLE = 8 + SDIO_TRIG_EN WAKEUPENABLE = 16 + MAC_TRIG_EN WAKEUPENABLE = 32 + UART0_TRIG_EN WAKEUPENABLE = 64 + UART1_TRIG_EN WAKEUPENABLE = 128 + TOUCH_TRIG_EN WAKEUPENABLE = 256 + SAR_TRIG_EN WAKEUPENABLE = 512 + BT_TRIG_EN WAKEUPENABLE = 1024 + RISCV_TRIG_EN WAKEUPENABLE = 2048 + XTAL_DEAD_TRIG_EN WAKEUPENABLE = 4096 + RISCV_TRAP_TRIG_EN WAKEUPENABLE = 8192 + USB_TRIG_EN WAKEUPENABLE = 16384 +) + +/** + * @brief Get the reset reason for CPU. + * + * @param int cpu_no : CPU no. + * + * @return RESET_REASON + */ +//go:linkname RtcGetResetReason C.rtc_get_reset_reason +func RtcGetResetReason(cpu_no c.Int) RESETREASON + +/** + * @brief Get the wakeup cause for CPU. + * + * @param int cpu_no : CPU no. + * + * @return WAKEUP_REASON + */ +//go:linkname RtcGetWakeupCause C.rtc_get_wakeup_cause +func RtcGetWakeupCause() WAKEUPREASON + +// llgo:type C +type EspRomWakeFuncT func() + +/** + * @brief Read stored RTC wake function address + * + * Returns pointer to wake address if a value is set in RTC registers, and stored length & CRC all valid. + * valid means that both stored stub length and stored wake function address are four-byte aligned non-zero values + * and the crc check passes + * + * @param None + * + * @return esp_rom_wake_func_t : Returns pointer to wake address if a value is set in RTC registers + */ +//go:linkname EspRomGetRtcWakeAddr C.esp_rom_get_rtc_wake_addr +func EspRomGetRtcWakeAddr() EspRomWakeFuncT + +/** + * @brief Store new RTC wake function address + * + * Set a new RTC wake address function. If a non-NULL function pointer is set then the function + * memory is calculated and stored also. + * + * @param entry_addr Address of function. should be 4-bytes aligned otherwise it will not start from the stub after wake from deepsleep， + * if NULL length will be ignored and all registers are cleared to 0. + * + * @param length length of function in RTC fast memory. should be less than RTC Fast memory size and aligned to 4-bytes. + * otherwise all registers are cleared to 0. + * + * @return None + */ +//go:linkname EspRomSetRtcWakeAddr C.esp_rom_set_rtc_wake_addr +func EspRomSetRtcWakeAddr(entry_addr EspRomWakeFuncT, length c.SizeT) + +/** + * @brief Software Reset digital core. + * + * It is not recommended to use this function in esp-idf, use + * esp_restart() instead. + * + * @param None + * + * @return None + */ +//go:linkname SoftwareReset C.software_reset +func SoftwareReset() + +/** + * @brief Software Reset digital core. + * + * It is not recommended to use this function in esp-idf, use + * esp_restart() instead. + * + * @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU. + * + * @return None + */ +//go:linkname SoftwareResetCpu C.software_reset_cpu +func SoftwareResetCpu(cpu_no c.Int) diff --git a/esp32/rtc_clk.go b/esp32/rtc_clk.go new file mode 100644 index 00000000..d9e75ad8 --- /dev/null +++ b/esp32/rtc_clk.go @@ -0,0 +1,47 @@ +package freertos + +import _ "unsafe" + +/** + * @brief Switch CPU clock source to XTAL, and let cpu frequency equal to main XTAL frequency. + * + * This function does not disable CPU's source PLL. If the PLL requires to be disabled to save power, please call + * `rtc_clk_cpu_freq_set_xtal` instead. It will always disable the corresponding PLL after switching the CPU clock + * source to XTAL (except for S2). + * + * Currently, this function is only called in `esp_restart_noos` and `esp_restart_noos_dig` to switch the CPU + * clock source back to XTAL (by default) before reset. + */ +//go:linkname RtcClkCpuSetToDefaultConfig C.rtc_clk_cpu_set_to_default_config +func RtcClkCpuSetToDefaultConfig() + +/** + * @brief Switch CPU clock source to XTAL, the PLL has different processing methods for different chips. + * 1. For earlier chips without PMU, there is no PMU module that can turn off the CPU's PLL, so it has to be + * disabled at here to save the power consumption. Though ESP32C3/S3 has USB CDC device, it can not function + * properly during sleep due to the lack of APB clock (before C6, USJ relies on APB clock to work). Therefore, + * we will always disable CPU's PLL (i.e. BBPLL). + * 2. For PMU supported chips, CPU's PLL power can be turned off by PMU, so no need to disable the PLL at here. + * Leaving PLL on at this stage also helps USJ keep connection and retention operation (if they rely on this PLL). + * For ESP32P4, if the APB frequency is configured as the hardware default value (10MHz), this will cause the + * regdma backup/restore to not achieve optimal performance. The MEM/APB frequency divider needs to be configured + * to 40MHz to speed up the retention speed. + */ +//go:linkname RtcClkCpuFreqSetXtalForSleep C.rtc_clk_cpu_freq_set_xtal_for_sleep +func RtcClkCpuFreqSetXtalForSleep() + +/** + * @brief Notify that the BBPLL has a new in-use consumer + * + * Currently, this function is only used for tracking whether USB Serial/JTAG is using the 48MHz PHY clock + * + * Note: Calling this function only helps to not disable the BBPLL clock in `rtc_clk_cpu_freq_set_config`. + */ +//go:linkname RtcClkBbpllAddConsumer C.rtc_clk_bbpll_add_consumer +func RtcClkBbpllAddConsumer() + +/** + * @brief Notify that the BBPLL has lost a consumer + */ +//go:linkname RtcClkBbpllRemoveConsumer C.rtc_clk_bbpll_remove_consumer +func RtcClkBbpllRemoveConsumer() diff --git a/esp32/rtc_cntl_ll.go b/esp32/rtc_cntl_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/rtc_cntl_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/rtc_cntl_reg.go b/esp32/rtc_cntl_reg.go new file mode 100644 index 00000000..bc6e505c --- /dev/null +++ b/esp32/rtc_cntl_reg.go @@ -0,0 +1,1326 @@ +package freertos + +import _ "unsafe" + +const RTC_CNTL_SWD_WKEY_VALUE = 0x8F1D312A +const RTC_CNTL_SW_SYS_RST_V = 0x1 +const RTC_CNTL_SW_SYS_RST_S = 31 +const RTC_CNTL_DG_WRAP_FORCE_NORST_V = 0x1 +const RTC_CNTL_DG_WRAP_FORCE_NORST_S = 30 +const RTC_CNTL_DG_WRAP_FORCE_RST_V = 0x1 +const RTC_CNTL_DG_WRAP_FORCE_RST_S = 29 +const RTC_CNTL_ANALOG_FORCE_NOISO_V = 0x1 +const RTC_CNTL_ANALOG_FORCE_NOISO_S = 28 +const RTC_CNTL_PLL_FORCE_NOISO_V = 0x1 +const RTC_CNTL_PLL_FORCE_NOISO_S = 27 +const RTC_CNTL_XTL_FORCE_NOISO_V = 0x1 +const RTC_CNTL_XTL_FORCE_NOISO_S = 26 +const RTC_CNTL_ANALOG_FORCE_ISO_V = 0x1 +const RTC_CNTL_ANALOG_FORCE_ISO_S = 25 +const RTC_CNTL_PLL_FORCE_ISO_V = 0x1 +const RTC_CNTL_PLL_FORCE_ISO_S = 24 +const RTC_CNTL_XTL_FORCE_ISO_V = 0x1 +const RTC_CNTL_XTL_FORCE_ISO_S = 23 +const RTC_CNTL_XTL_EN_WAIT = 0x0000000F +const RTC_CNTL_XTL_EN_WAIT_V = 0xF +const RTC_CNTL_XTL_EN_WAIT_S = 14 +const RTC_CNTL_XTL_FORCE_PU_V = 0x1 +const RTC_CNTL_XTL_FORCE_PU_S = 13 +const RTC_CNTL_XTL_FORCE_PD_V = 0x1 +const RTC_CNTL_XTL_FORCE_PD_S = 12 +const RTC_CNTL_BBPLL_FORCE_PU_V = 0x1 +const RTC_CNTL_BBPLL_FORCE_PU_S = 11 +const RTC_CNTL_BBPLL_FORCE_PD_V = 0x1 +const RTC_CNTL_BBPLL_FORCE_PD_S = 10 +const RTC_CNTL_BBPLL_I2C_FORCE_PU_V = 0x1 +const RTC_CNTL_BBPLL_I2C_FORCE_PU_S = 9 +const RTC_CNTL_BBPLL_I2C_FORCE_PD_V = 0x1 +const RTC_CNTL_BBPLL_I2C_FORCE_PD_S = 8 +const RTC_CNTL_BB_I2C_FORCE_PU_V = 0x1 +const RTC_CNTL_BB_I2C_FORCE_PU_S = 7 +const RTC_CNTL_BB_I2C_FORCE_PD_V = 0x1 +const RTC_CNTL_BB_I2C_FORCE_PD_S = 6 +const RTC_CNTL_SW_PROCPU_RST_V = 0x1 +const RTC_CNTL_SW_PROCPU_RST_S = 5 +const RTC_CNTL_SW_APPCPU_RST_V = 0x1 +const RTC_CNTL_SW_APPCPU_RST_S = 4 +const RTC_CNTL_SW_STALL_PROCPU_C0 = 0x00000003 +const RTC_CNTL_SW_STALL_PROCPU_C0_V = 0x3 +const RTC_CNTL_SW_STALL_PROCPU_C0_S = 2 +const RTC_CNTL_SW_STALL_APPCPU_C0 = 0x00000003 +const RTC_CNTL_SW_STALL_APPCPU_C0_V = 0x3 +const RTC_CNTL_SW_STALL_APPCPU_C0_S = 0 +const RTC_CNTL_SLP_VAL_LO = 0xFFFFFFFF +const RTC_CNTL_SLP_VAL_LO_V = 0xFFFFFFFF +const RTC_CNTL_SLP_VAL_LO_S = 0 +const RTC_CNTL_MAIN_TIMER_ALARM_EN_V = 0x1 +const RTC_CNTL_MAIN_TIMER_ALARM_EN_S = 16 +const RTC_CNTL_SLP_VAL_HI = 0x0000FFFF +const RTC_CNTL_SLP_VAL_HI_V = 0xFFFF +const RTC_CNTL_SLP_VAL_HI_S = 0 +const RTC_CNTL_TIME_UPDATE_V = 0x1 +const RTC_CNTL_TIME_UPDATE_S = 31 +const RTC_CNTL_TIMER_SYS_RST_V = 0x1 +const RTC_CNTL_TIMER_SYS_RST_S = 29 +const RTC_CNTL_TIMER_XTL_OFF_V = 0x1 +const RTC_CNTL_TIMER_XTL_OFF_S = 28 +const RTC_CNTL_TIMER_SYS_STALL_V = 0x1 +const RTC_CNTL_TIMER_SYS_STALL_S = 27 +const RTC_CNTL_TIMER_VALUE0_LOW = 0xFFFFFFFF +const RTC_CNTL_TIMER_VALUE0_LOW_V = 0xFFFFFFFF +const RTC_CNTL_TIMER_VALUE0_LOW_S = 0 +const RTC_CNTL_TIMER_VALUE0_HIGH = 0x0000FFFF +const RTC_CNTL_TIMER_VALUE0_HIGH_V = 0xFFFF +const RTC_CNTL_TIMER_VALUE0_HIGH_S = 0 +const RTC_CNTL_SLEEP_EN_V = 0x1 +const RTC_CNTL_SLEEP_EN_S = 31 +const RTC_CNTL_SLP_REJECT_V = 0x1 +const RTC_CNTL_SLP_REJECT_S = 30 +const RTC_CNTL_SLP_WAKEUP_V = 0x1 +const RTC_CNTL_SLP_WAKEUP_S = 29 +const RTC_CNTL_SDIO_ACTIVE_IND_V = 0x1 +const RTC_CNTL_SDIO_ACTIVE_IND_S = 28 +const RTC_CNTL_APB2RTC_BRIDGE_SEL_V = 0x1 +const RTC_CNTL_APB2RTC_BRIDGE_SEL_S = 22 +const RTC_CNTL_SLP_REJECT_CAUSE_CLR_V = 0x1 +const RTC_CNTL_SLP_REJECT_CAUSE_CLR_S = 1 +const RTC_CNTL_SW_CPU_INT_V = 0x1 +const RTC_CNTL_SW_CPU_INT_S = 0 +const RTC_CNTL_PLL_BUF_WAIT = 0x000000FF +const RTC_CNTL_PLL_BUF_WAIT_V = 0xFF +const RTC_CNTL_PLL_BUF_WAIT_S = 24 +const RTC_CNTL_XTL_BUF_WAIT = 0x000003FF +const RTC_CNTL_XTL_BUF_WAIT_V = 0x3FF +const RTC_CNTL_XTL_BUF_WAIT_S = 14 +const RTC_CNTL_CK8M_WAIT = 0x000000FF +const RTC_CNTL_CK8M_WAIT_V = 0xFF +const RTC_CNTL_CK8M_WAIT_S = 6 +const RTC_CNTL_CPU_STALL_WAIT = 0x0000001F +const RTC_CNTL_CPU_STALL_WAIT_V = 0x1F +const RTC_CNTL_CPU_STALL_WAIT_S = 1 +const RTC_CNTL_CPU_STALL_EN_V = 0x1 +const RTC_CNTL_CPU_STALL_EN_S = 0 +const RTC_CNTL_MIN_TIME_CK8M_OFF = 0x000000FF +const RTC_CNTL_MIN_TIME_CK8M_OFF_V = 0xFF +const RTC_CNTL_MIN_TIME_CK8M_OFF_S = 24 +const RTC_CNTL_ULPCP_TOUCH_START_WAIT = 0x000001FF +const RTC_CNTL_ULPCP_TOUCH_START_WAIT_V = 0x1FF +const RTC_CNTL_ULPCP_TOUCH_START_WAIT_S = 15 +const RTC_CNTL_BT_POWERUP_TIMER = 0x0000007F +const RTC_CNTL_BT_POWERUP_TIMER_V = 0x7F +const RTC_CNTL_BT_POWERUP_TIMER_S = 25 +const RTC_CNTL_BT_WAIT_TIMER = 0x000001FF +const RTC_CNTL_BT_WAIT_TIMER_V = 0x1FF +const RTC_CNTL_BT_WAIT_TIMER_S = 16 +const RTC_CNTL_WIFI_POWERUP_TIMER = 0x0000007F +const RTC_CNTL_WIFI_POWERUP_TIMER_V = 0x7F +const RTC_CNTL_WIFI_POWERUP_TIMER_S = 9 +const RTC_CNTL_WIFI_WAIT_TIMER = 0x000001FF +const RTC_CNTL_WIFI_WAIT_TIMER_V = 0x1FF +const RTC_CNTL_WIFI_WAIT_TIMER_S = 0 +const RTC_CNTL_DG_WRAP_POWERUP_TIMER = 0x0000007F +const RTC_CNTL_DG_WRAP_POWERUP_TIMER_V = 0x7F +const RTC_CNTL_DG_WRAP_POWERUP_TIMER_S = 25 +const RTC_CNTL_DG_WRAP_WAIT_TIMER = 0x000001FF +const RTC_CNTL_DG_WRAP_WAIT_TIMER_V = 0x1FF +const RTC_CNTL_DG_WRAP_WAIT_TIMER_S = 16 +const RTC_CNTL_POWERUP_TIMER = 0x0000007F +const RTC_CNTL_POWERUP_TIMER_V = 0x7F +const RTC_CNTL_POWERUP_TIMER_S = 9 +const RTC_CNTL_WAIT_TIMER = 0x000001FF +const RTC_CNTL_WAIT_TIMER_V = 0x1FF +const RTC_CNTL_WAIT_TIMER_S = 0 +const RTC_CNTL_MIN_SLP_VAL = 0x000000FF +const RTC_CNTL_MIN_SLP_VAL_V = 0xFF +const RTC_CNTL_MIN_SLP_VAL_S = 8 +const RTC_CNTL_DG_PERI_POWERUP_TIMER = 0x0000007F +const RTC_CNTL_DG_PERI_POWERUP_TIMER_V = 0x7F +const RTC_CNTL_DG_PERI_POWERUP_TIMER_S = 25 +const RTC_CNTL_DG_PERI_WAIT_TIMER = 0x000001FF +const RTC_CNTL_DG_PERI_WAIT_TIMER_V = 0x1FF +const RTC_CNTL_DG_PERI_WAIT_TIMER_S = 16 +const RTC_CNTL_CPU_TOP_POWERUP_TIMER = 0x0000007F +const RTC_CNTL_CPU_TOP_POWERUP_TIMER_V = 0x7F +const RTC_CNTL_CPU_TOP_POWERUP_TIMER_S = 9 +const RTC_CNTL_CPU_TOP_WAIT_TIMER = 0x000001FF +const RTC_CNTL_CPU_TOP_WAIT_TIMER_V = 0x1FF +const RTC_CNTL_CPU_TOP_WAIT_TIMER_S = 0 +const RTC_CNTL_PLL_I2C_PU_V = 0x1 +const RTC_CNTL_PLL_I2C_PU_S = 31 +const RTC_CNTL_CKGEN_I2C_PU_V = 0x1 +const RTC_CNTL_CKGEN_I2C_PU_S = 30 +const RTC_CNTL_RFRX_PBUS_PU_V = 0x1 +const RTC_CNTL_RFRX_PBUS_PU_S = 28 +const RTC_CNTL_TXRF_I2C_PU_V = 0x1 +const RTC_CNTL_TXRF_I2C_PU_S = 27 +const RTC_CNTL_PVTMON_PU_V = 0x1 +const RTC_CNTL_PVTMON_PU_S = 26 +const RTC_CNTL_BBPLL_CAL_SLP_START_V = 0x1 +const RTC_CNTL_BBPLL_CAL_SLP_START_S = 25 +const RTC_CNTL_ANALOG_TOP_ISO_MONITOR_V = 0x1 +const RTC_CNTL_ANALOG_TOP_ISO_MONITOR_S = 24 +const RTC_CNTL_ANALOG_TOP_ISO_SLEEP_V = 0x1 +const RTC_CNTL_ANALOG_TOP_ISO_SLEEP_S = 23 +const RTC_CNTL_SAR_I2C_PU_V = 0x1 +const RTC_CNTL_SAR_I2C_PU_S = 22 +const RTC_CNTL_GLITCH_RST_EN_V = 0x1 +const RTC_CNTL_GLITCH_RST_EN_S = 20 +const RTC_CNTL_I2C_RESET_POR_FORCE_PU_V = 0x1 +const RTC_CNTL_I2C_RESET_POR_FORCE_PU_S = 19 +const RTC_CNTL_I2C_RESET_POR_FORCE_PD_V = 0x1 +const RTC_CNTL_I2C_RESET_POR_FORCE_PD_S = 18 +const RTC_CNTL_PRO_DRESET_MASK_V = 0x1 +const RTC_CNTL_PRO_DRESET_MASK_S = 25 +const RTC_CNTL_APP_DRESET_MASK_V = 0x1 +const RTC_CNTL_APP_DRESET_MASK_S = 24 +const RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V = 0x1 +const RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S = 23 +const RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V = 0x1 +const RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S = 22 +const RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V = 0x1 +const RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S = 21 +const RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V = 0x1 +const RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S = 20 +const RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V = 0x1 +const RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S = 19 +const RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V = 0x1 +const RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S = 18 +const RTC_CNTL_RESET_FLAG_APPCPU_CLR_V = 0x1 +const RTC_CNTL_RESET_FLAG_APPCPU_CLR_S = 17 +const RTC_CNTL_RESET_FLAG_PROCPU_CLR_V = 0x1 +const RTC_CNTL_RESET_FLAG_PROCPU_CLR_S = 16 +const RTC_CNTL_RESET_FLAG_APPCPU_V = 0x1 +const RTC_CNTL_RESET_FLAG_APPCPU_S = 15 +const RTC_CNTL_RESET_FLAG_PROCPU_V = 0x1 +const RTC_CNTL_RESET_FLAG_PROCPU_S = 14 +const RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V = 0x1 +const RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S = 13 +const RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V = 0x1 +const RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S = 12 +const RTC_CNTL_RESET_CAUSE_APPCPU = 0x0000003F +const RTC_CNTL_RESET_CAUSE_APPCPU_V = 0x3F +const RTC_CNTL_RESET_CAUSE_APPCPU_S = 6 +const RTC_CNTL_RESET_CAUSE_PROCPU = 0x0000003F +const RTC_CNTL_RESET_CAUSE_PROCPU_V = 0x3F +const RTC_CNTL_RESET_CAUSE_PROCPU_S = 0 +const RTC_CNTL_WAKEUP_ENA = 0x0001FFFF +const RTC_CNTL_WAKEUP_ENA_V = 0x1FFFF +const RTC_CNTL_WAKEUP_ENA_S = 15 +const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V = 0x1 +const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S = 20 +const RTC_CNTL_GLITCH_DET_INT_ENA_V = 0x1 +const RTC_CNTL_GLITCH_DET_INT_ENA_S = 19 +const RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V = 0x1 +const RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S = 18 +const RTC_CNTL_COCPU_TRAP_INT_ENA_V = 0x1 +const RTC_CNTL_COCPU_TRAP_INT_ENA_S = 17 +const RTC_CNTL_XTAL32K_DEAD_INT_ENA_V = 0x1 +const RTC_CNTL_XTAL32K_DEAD_INT_ENA_S = 16 +const RTC_CNTL_SWD_INT_ENA_V = 0x1 +const RTC_CNTL_SWD_INT_ENA_S = 15 +const RTC_CNTL_SARADC2_INT_ENA_V = 0x1 +const RTC_CNTL_SARADC2_INT_ENA_S = 14 +const RTC_CNTL_COCPU_INT_ENA_V = 0x1 +const RTC_CNTL_COCPU_INT_ENA_S = 13 +const RTC_CNTL_TSENS_INT_ENA_V = 0x1 +const RTC_CNTL_TSENS_INT_ENA_S = 12 +const RTC_CNTL_SARADC1_INT_ENA_V = 0x1 +const RTC_CNTL_SARADC1_INT_ENA_S = 11 +const RTC_CNTL_MAIN_TIMER_INT_ENA_V = 0x1 +const RTC_CNTL_MAIN_TIMER_INT_ENA_S = 10 +const RTC_CNTL_BROWN_OUT_INT_ENA_V = 0x1 +const RTC_CNTL_BROWN_OUT_INT_ENA_S = 9 +const RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V = 0x1 +const RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S = 8 +const RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V = 0x1 +const RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S = 7 +const RTC_CNTL_TOUCH_DONE_INT_ENA_V = 0x1 +const RTC_CNTL_TOUCH_DONE_INT_ENA_S = 6 +const RTC_CNTL_ULP_CP_INT_ENA_V = 0x1 +const RTC_CNTL_ULP_CP_INT_ENA_S = 5 +const RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V = 0x1 +const RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S = 4 +const RTC_CNTL_WDT_INT_ENA_V = 0x1 +const RTC_CNTL_WDT_INT_ENA_S = 3 +const RTC_CNTL_SDIO_IDLE_INT_ENA_V = 0x1 +const RTC_CNTL_SDIO_IDLE_INT_ENA_S = 2 +const RTC_CNTL_SLP_REJECT_INT_ENA_V = 0x1 +const RTC_CNTL_SLP_REJECT_INT_ENA_S = 1 +const RTC_CNTL_SLP_WAKEUP_INT_ENA_V = 0x1 +const RTC_CNTL_SLP_WAKEUP_INT_ENA_S = 0 +const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V = 0x1 +const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S = 20 +const RTC_CNTL_GLITCH_DET_INT_RAW_V = 0x1 +const RTC_CNTL_GLITCH_DET_INT_RAW_S = 19 +const RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V = 0x1 +const RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S = 18 +const RTC_CNTL_COCPU_TRAP_INT_RAW_V = 0x1 +const RTC_CNTL_COCPU_TRAP_INT_RAW_S = 17 +const RTC_CNTL_XTAL32K_DEAD_INT_RAW_V = 0x1 +const RTC_CNTL_XTAL32K_DEAD_INT_RAW_S = 16 +const RTC_CNTL_SWD_INT_RAW_V = 0x1 +const RTC_CNTL_SWD_INT_RAW_S = 15 +const RTC_CNTL_SARADC2_INT_RAW_V = 0x1 +const RTC_CNTL_SARADC2_INT_RAW_S = 14 +const RTC_CNTL_COCPU_INT_RAW_V = 0x1 +const RTC_CNTL_COCPU_INT_RAW_S = 13 +const RTC_CNTL_TSENS_INT_RAW_V = 0x1 +const RTC_CNTL_TSENS_INT_RAW_S = 12 +const RTC_CNTL_SARADC1_INT_RAW_V = 0x1 +const RTC_CNTL_SARADC1_INT_RAW_S = 11 +const RTC_CNTL_MAIN_TIMER_INT_RAW_V = 0x1 +const RTC_CNTL_MAIN_TIMER_INT_RAW_S = 10 +const RTC_CNTL_BROWN_OUT_INT_RAW_V = 0x1 +const RTC_CNTL_BROWN_OUT_INT_RAW_S = 9 +const RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V = 0x1 +const RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S = 8 +const RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V = 0x1 +const RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S = 7 +const RTC_CNTL_TOUCH_DONE_INT_RAW_V = 0x1 +const RTC_CNTL_TOUCH_DONE_INT_RAW_S = 6 +const RTC_CNTL_ULP_CP_INT_RAW_V = 0x1 +const RTC_CNTL_ULP_CP_INT_RAW_S = 5 +const RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V = 0x1 +const RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S = 4 +const RTC_CNTL_WDT_INT_RAW_V = 0x1 +const RTC_CNTL_WDT_INT_RAW_S = 3 +const RTC_CNTL_SDIO_IDLE_INT_RAW_V = 0x1 +const RTC_CNTL_SDIO_IDLE_INT_RAW_S = 2 +const RTC_CNTL_SLP_REJECT_INT_RAW_V = 0x1 +const RTC_CNTL_SLP_REJECT_INT_RAW_S = 1 +const RTC_CNTL_SLP_WAKEUP_INT_RAW_V = 0x1 +const RTC_CNTL_SLP_WAKEUP_INT_RAW_S = 0 +const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_V = 0x1 +const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_S = 20 +const RTC_CNTL_GLITCH_DET_INT_ST_V = 0x1 +const RTC_CNTL_GLITCH_DET_INT_ST_S = 19 +const RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V = 0x1 +const RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S = 18 +const RTC_CNTL_COCPU_TRAP_INT_ST_V = 0x1 +const RTC_CNTL_COCPU_TRAP_INT_ST_S = 17 +const RTC_CNTL_XTAL32K_DEAD_INT_ST_V = 0x1 +const RTC_CNTL_XTAL32K_DEAD_INT_ST_S = 16 +const RTC_CNTL_SWD_INT_ST_V = 0x1 +const RTC_CNTL_SWD_INT_ST_S = 15 +const RTC_CNTL_SARADC2_INT_ST_V = 0x1 +const RTC_CNTL_SARADC2_INT_ST_S = 14 +const RTC_CNTL_COCPU_INT_ST_V = 0x1 +const RTC_CNTL_COCPU_INT_ST_S = 13 +const RTC_CNTL_TSENS_INT_ST_V = 0x1 +const RTC_CNTL_TSENS_INT_ST_S = 12 +const RTC_CNTL_SARADC1_INT_ST_V = 0x1 +const RTC_CNTL_SARADC1_INT_ST_S = 11 +const RTC_CNTL_MAIN_TIMER_INT_ST_V = 0x1 +const RTC_CNTL_MAIN_TIMER_INT_ST_S = 10 +const RTC_CNTL_BROWN_OUT_INT_ST_V = 0x1 +const RTC_CNTL_BROWN_OUT_INT_ST_S = 9 +const RTC_CNTL_TOUCH_INACTIVE_INT_ST_V = 0x1 +const RTC_CNTL_TOUCH_INACTIVE_INT_ST_S = 8 +const RTC_CNTL_TOUCH_ACTIVE_INT_ST_V = 0x1 +const RTC_CNTL_TOUCH_ACTIVE_INT_ST_S = 7 +const RTC_CNTL_TOUCH_DONE_INT_ST_V = 0x1 +const RTC_CNTL_TOUCH_DONE_INT_ST_S = 6 +const RTC_CNTL_ULP_CP_INT_ST_V = 0x1 +const RTC_CNTL_ULP_CP_INT_ST_S = 5 +const RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V = 0x1 +const RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S = 4 +const RTC_CNTL_WDT_INT_ST_V = 0x1 +const RTC_CNTL_WDT_INT_ST_S = 3 +const RTC_CNTL_SDIO_IDLE_INT_ST_V = 0x1 +const RTC_CNTL_SDIO_IDLE_INT_ST_S = 2 +const RTC_CNTL_SLP_REJECT_INT_ST_V = 0x1 +const RTC_CNTL_SLP_REJECT_INT_ST_S = 1 +const RTC_CNTL_SLP_WAKEUP_INT_ST_V = 0x1 +const RTC_CNTL_SLP_WAKEUP_INT_ST_S = 0 +const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V = 0x1 +const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S = 20 +const RTC_CNTL_GLITCH_DET_INT_CLR_V = 0x1 +const RTC_CNTL_GLITCH_DET_INT_CLR_S = 19 +const RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V = 0x1 +const RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S = 18 +const RTC_CNTL_COCPU_TRAP_INT_CLR_V = 0x1 +const RTC_CNTL_COCPU_TRAP_INT_CLR_S = 17 +const RTC_CNTL_XTAL32K_DEAD_INT_CLR_V = 0x1 +const RTC_CNTL_XTAL32K_DEAD_INT_CLR_S = 16 +const RTC_CNTL_SWD_INT_CLR_V = 0x1 +const RTC_CNTL_SWD_INT_CLR_S = 15 +const RTC_CNTL_SARADC2_INT_CLR_V = 0x1 +const RTC_CNTL_SARADC2_INT_CLR_S = 14 +const RTC_CNTL_COCPU_INT_CLR_V = 0x1 +const RTC_CNTL_COCPU_INT_CLR_S = 13 +const RTC_CNTL_TSENS_INT_CLR_V = 0x1 +const RTC_CNTL_TSENS_INT_CLR_S = 12 +const RTC_CNTL_SARADC1_INT_CLR_V = 0x1 +const RTC_CNTL_SARADC1_INT_CLR_S = 11 +const RTC_CNTL_MAIN_TIMER_INT_CLR_V = 0x1 +const RTC_CNTL_MAIN_TIMER_INT_CLR_S = 10 +const RTC_CNTL_BROWN_OUT_INT_CLR_V = 0x1 +const RTC_CNTL_BROWN_OUT_INT_CLR_S = 9 +const RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V = 0x1 +const RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S = 8 +const RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V = 0x1 +const RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S = 7 +const RTC_CNTL_TOUCH_DONE_INT_CLR_V = 0x1 +const RTC_CNTL_TOUCH_DONE_INT_CLR_S = 6 +const RTC_CNTL_ULP_CP_INT_CLR_V = 0x1 +const RTC_CNTL_ULP_CP_INT_CLR_S = 5 +const RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V = 0x1 +const RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S = 4 +const RTC_CNTL_WDT_INT_CLR_V = 0x1 +const RTC_CNTL_WDT_INT_CLR_S = 3 +const RTC_CNTL_SDIO_IDLE_INT_CLR_V = 0x1 +const RTC_CNTL_SDIO_IDLE_INT_CLR_S = 2 +const RTC_CNTL_SLP_REJECT_INT_CLR_V = 0x1 +const RTC_CNTL_SLP_REJECT_INT_CLR_S = 1 +const RTC_CNTL_SLP_WAKEUP_INT_CLR_V = 0x1 +const RTC_CNTL_SLP_WAKEUP_INT_CLR_S = 0 +const RTC_CNTL_SCRATCH0 = 0xFFFFFFFF +const RTC_CNTL_SCRATCH0_V = 0xFFFFFFFF +const RTC_CNTL_SCRATCH0_S = 0 +const RTC_CNTL_SCRATCH1 = 0xFFFFFFFF +const RTC_CNTL_SCRATCH1_V = 0xFFFFFFFF +const RTC_CNTL_SCRATCH1_S = 0 +const RTC_CNTL_SCRATCH2 = 0xFFFFFFFF +const RTC_CNTL_SCRATCH2_V = 0xFFFFFFFF +const RTC_CNTL_SCRATCH2_S = 0 +const RTC_CNTL_SCRATCH3 = 0xFFFFFFFF +const RTC_CNTL_SCRATCH3_V = 0xFFFFFFFF +const RTC_CNTL_SCRATCH3_S = 0 +const RTC_CNTL_XTL_EXT_CTR_EN_V = 0x1 +const RTC_CNTL_XTL_EXT_CTR_EN_S = 31 +const RTC_CNTL_XTL_EXT_CTR_LV_V = 0x1 +const RTC_CNTL_XTL_EXT_CTR_LV_S = 30 +const RTC_CNTL_XTAL32K_GPIO_SEL_V = 0x1 +const RTC_CNTL_XTAL32K_GPIO_SEL_S = 23 +const RTC_CNTL_WDT_STATE = 0x00000007 +const RTC_CNTL_WDT_STATE_V = 0x7 +const RTC_CNTL_WDT_STATE_S = 20 +const RTC_CNTL_DAC_XTAL_32K = 0x00000007 +const RTC_CNTL_DAC_XTAL_32K_V = 0x7 +const RTC_CNTL_DAC_XTAL_32K_S = 17 +const RTC_CNTL_XPD_XTAL_32K_V = 0x1 +const RTC_CNTL_XPD_XTAL_32K_S = 16 +const RTC_CNTL_DRES_XTAL_32K = 0x00000007 +const RTC_CNTL_DRES_XTAL_32K_V = 0x7 +const RTC_CNTL_DRES_XTAL_32K_S = 13 +const RTC_CNTL_DGM_XTAL_32K = 0x00000007 +const RTC_CNTL_DGM_XTAL_32K_V = 0x7 +const RTC_CNTL_DGM_XTAL_32K_S = 10 +const RTC_CNTL_DBUF_XTAL_32K_V = 0x1 +const RTC_CNTL_DBUF_XTAL_32K_S = 9 +const RTC_CNTL_ENCKINIT_XTAL_32K_V = 0x1 +const RTC_CNTL_ENCKINIT_XTAL_32K_S = 8 +const RTC_CNTL_XTAL32K_XPD_FORCE_V = 0x1 +const RTC_CNTL_XTAL32K_XPD_FORCE_S = 7 +const RTC_CNTL_XTAL32K_AUTO_RETURN_V = 0x1 +const RTC_CNTL_XTAL32K_AUTO_RETURN_S = 6 +const RTC_CNTL_XTAL32K_AUTO_RESTART_V = 0x1 +const RTC_CNTL_XTAL32K_AUTO_RESTART_S = 5 +const RTC_CNTL_XTAL32K_AUTO_BACKUP_V = 0x1 +const RTC_CNTL_XTAL32K_AUTO_BACKUP_S = 4 +const RTC_CNTL_XTAL32K_EXT_CLK_FO_V = 0x1 +const RTC_CNTL_XTAL32K_EXT_CLK_FO_S = 3 +const RTC_CNTL_XTAL32K_WDT_RESET_V = 0x1 +const RTC_CNTL_XTAL32K_WDT_RESET_S = 2 +const RTC_CNTL_XTAL32K_WDT_CLK_FO_V = 0x1 +const RTC_CNTL_XTAL32K_WDT_CLK_FO_S = 1 +const RTC_CNTL_XTAL32K_WDT_EN_V = 0x1 +const RTC_CNTL_XTAL32K_WDT_EN_S = 0 +const RTC_CNTL_EXT_WAKEUP1_LV_V = 0x1 +const RTC_CNTL_EXT_WAKEUP1_LV_S = 31 +const RTC_CNTL_EXT_WAKEUP0_LV_V = 0x1 +const RTC_CNTL_EXT_WAKEUP0_LV_S = 30 +const RTC_CNTL_GPIO_WAKEUP_FILTER_V = 0x1 +const RTC_CNTL_GPIO_WAKEUP_FILTER_S = 29 +const RTC_CNTL_DEEP_SLP_REJECT_EN_V = 0x1 +const RTC_CNTL_DEEP_SLP_REJECT_EN_S = 31 +const RTC_CNTL_LIGHT_SLP_REJECT_EN_V = 0x1 +const RTC_CNTL_LIGHT_SLP_REJECT_EN_S = 30 +const RTC_CNTL_SLEEP_REJECT_ENA = 0x0003FFFF +const RTC_CNTL_SLEEP_REJECT_ENA_V = 0x3FFFF +const RTC_CNTL_SLEEP_REJECT_ENA_S = 12 +const RTC_CNTL_CPUPERIOD_SEL = 0x00000003 +const RTC_CNTL_CPUPERIOD_SEL_V = 0x3 +const RTC_CNTL_CPUPERIOD_SEL_S = 30 +const RTC_CNTL_CPUSEL_CONF_V = 0x1 +const RTC_CNTL_CPUSEL_CONF_S = 29 +const RTC_CNTL_SDIO_ACT_DNUM = 0x000003FF +const RTC_CNTL_SDIO_ACT_DNUM_V = 0x3FF +const RTC_CNTL_SDIO_ACT_DNUM_S = 22 +const RTC_CNTL_ANA_CLK_RTC_SEL = 0x00000003 +const RTC_CNTL_ANA_CLK_RTC_SEL_V = 0x3 +const RTC_CNTL_ANA_CLK_RTC_SEL_S = 30 +const RTC_CNTL_FAST_CLK_RTC_SEL_V = 0x1 +const RTC_CNTL_FAST_CLK_RTC_SEL_S = 29 +const RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V = 0x1 +const RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S = 28 +const RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V = 0x1 +const RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S = 27 +const RTC_CNTL_CK8M_FORCE_PU_V = 0x1 +const RTC_CNTL_CK8M_FORCE_PU_S = 26 +const RTC_CNTL_CK8M_FORCE_PD_V = 0x1 +const RTC_CNTL_CK8M_FORCE_PD_S = 25 +const RTC_CNTL_CK8M_DFREQ = 0x000000FF +const RTC_CNTL_CK8M_DFREQ_V = 0xFF +const RTC_CNTL_CK8M_DFREQ_S = 17 +const RTC_CNTL_CK8M_FORCE_NOGATING_V = 0x1 +const RTC_CNTL_CK8M_FORCE_NOGATING_S = 16 +const RTC_CNTL_XTAL_FORCE_NOGATING_V = 0x1 +const RTC_CNTL_XTAL_FORCE_NOGATING_S = 15 +const RTC_CNTL_CK8M_DIV_SEL = 0x00000007 +const RTC_CNTL_CK8M_DIV_SEL_V = 0x7 +const RTC_CNTL_CK8M_DIV_SEL_S = 12 +const RTC_CNTL_DIG_CLK8M_EN_V = 0x1 +const RTC_CNTL_DIG_CLK8M_EN_S = 10 +const RTC_CNTL_DIG_CLK8M_D256_EN_V = 0x1 +const RTC_CNTL_DIG_CLK8M_D256_EN_S = 9 +const RTC_CNTL_DIG_XTAL32K_EN_V = 0x1 +const RTC_CNTL_DIG_XTAL32K_EN_S = 8 +const RTC_CNTL_ENB_CK8M_DIV_V = 0x1 +const RTC_CNTL_ENB_CK8M_DIV_S = 7 +const RTC_CNTL_ENB_CK8M_V = 0x1 +const RTC_CNTL_ENB_CK8M_S = 6 +const RTC_CNTL_CK8M_DIV = 0x00000003 +const RTC_CNTL_CK8M_DIV_V = 0x3 +const RTC_CNTL_CK8M_DIV_S = 4 +const RTC_CNTL_CK8M_DIV_SEL_VLD_V = 0x1 +const RTC_CNTL_CK8M_DIV_SEL_VLD_S = 3 +const RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V = 0x1 +const RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S = 2 +const RTC_CNTL_EFUSE_CLK_FORCE_GATING_V = 0x1 +const RTC_CNTL_EFUSE_CLK_FORCE_GATING_S = 1 +const RTC_CNTL_SLOW_CLK_NEXT_EDGE_V = 0x1 +const RTC_CNTL_SLOW_CLK_NEXT_EDGE_S = 31 +const RTC_CNTL_ANA_CLK_DIV = 0x000000FF +const RTC_CNTL_ANA_CLK_DIV_V = 0xFF +const RTC_CNTL_ANA_CLK_DIV_S = 23 +const RTC_CNTL_ANA_CLK_DIV_VLD_V = 0x1 +const RTC_CNTL_ANA_CLK_DIV_VLD_S = 22 +const RTC_CNTL_XPD_SDIO_REG_V = 0x1 +const RTC_CNTL_XPD_SDIO_REG_S = 31 +const RTC_CNTL_DREFH_SDIO = 0x00000003 +const RTC_CNTL_DREFH_SDIO_V = 0x3 +const RTC_CNTL_DREFH_SDIO_S = 29 +const RTC_CNTL_DREFM_SDIO = 0x00000003 +const RTC_CNTL_DREFM_SDIO_V = 0x3 +const RTC_CNTL_DREFM_SDIO_S = 27 +const RTC_CNTL_DREFL_SDIO = 0x00000003 +const RTC_CNTL_DREFL_SDIO_V = 0x3 +const RTC_CNTL_DREFL_SDIO_S = 25 +const RTC_CNTL_REG1P8_READY_V = 0x1 +const RTC_CNTL_REG1P8_READY_S = 24 +const RTC_CNTL_SDIO_TIEH_V = 0x1 +const RTC_CNTL_SDIO_TIEH_S = 23 +const RTC_CNTL_SDIO_FORCE_V = 0x1 +const RTC_CNTL_SDIO_FORCE_S = 22 +const RTC_CNTL_SDIO_PD_EN_V = 0x1 +const RTC_CNTL_SDIO_PD_EN_S = 21 +const RTC_CNTL_SDIO_ENCURLIM_V = 0x1 +const RTC_CNTL_SDIO_ENCURLIM_S = 20 +const RTC_CNTL_SDIO_MODECURLIM_V = 0x1 +const RTC_CNTL_SDIO_MODECURLIM_S = 19 +const RTC_CNTL_SDIO_DCURLIM = 0x00000007 +const RTC_CNTL_SDIO_DCURLIM_V = 0x7 +const RTC_CNTL_SDIO_DCURLIM_S = 16 +const RTC_CNTL_SDIO_EN_INITI_V = 0x1 +const RTC_CNTL_SDIO_EN_INITI_S = 15 +const RTC_CNTL_SDIO_INITI = 0x00000003 +const RTC_CNTL_SDIO_INITI_V = 0x3 +const RTC_CNTL_SDIO_INITI_S = 13 +const RTC_CNTL_SDIO_DCAP = 0x00000003 +const RTC_CNTL_SDIO_DCAP_V = 0x3 +const RTC_CNTL_SDIO_DCAP_S = 11 +const RTC_CNTL_SDIO_DTHDRV = 0x00000003 +const RTC_CNTL_SDIO_DTHDRV_V = 0x3 +const RTC_CNTL_SDIO_DTHDRV_S = 9 +const RTC_CNTL_SDIO_TIMER_TARGET = 0x000000FF +const RTC_CNTL_SDIO_TIMER_TARGET_V = 0xFF +const RTC_CNTL_SDIO_TIMER_TARGET_S = 0 +const RTC_CNTL_DBG_ATTEN_WAKEUP = 0x0000000F +const RTC_CNTL_DBG_ATTEN_WAKEUP_V = 0xF +const RTC_CNTL_DBG_ATTEN_WAKEUP_S = 26 +const RTC_CNTL_DBG_ATTEN_MONITOR = 0x0000000F +const RTC_CNTL_DBG_ATTEN_MONITOR_V = 0xF +const RTC_CNTL_DBG_ATTEN_MONITOR_S = 22 +const RTC_CNTL_DBG_ATTEN_DEEP_SLP = 0x0000000F +const RTC_CNTL_DBG_ATTEN_DEEP_SLP_V = 0xF +const RTC_CNTL_DBG_ATTEN_DEEP_SLP_S = 18 +const RTC_CNTL_BIAS_SLEEP_MONITOR_V = 0x1 +const RTC_CNTL_BIAS_SLEEP_MONITOR_S = 17 +const RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V = 0x1 +const RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S = 16 +const RTC_CNTL_PD_CUR_MONITOR_V = 0x1 +const RTC_CNTL_PD_CUR_MONITOR_S = 15 +const RTC_CNTL_PD_CUR_DEEP_SLP_V = 0x1 +const RTC_CNTL_PD_CUR_DEEP_SLP_S = 14 +const RTC_CNTL_BIAS_BUF_MONITOR_V = 0x1 +const RTC_CNTL_BIAS_BUF_MONITOR_S = 13 +const RTC_CNTL_BIAS_BUF_DEEP_SLP_V = 0x1 +const RTC_CNTL_BIAS_BUF_DEEP_SLP_S = 12 +const RTC_CNTL_BIAS_BUF_WAKE_V = 0x1 +const RTC_CNTL_BIAS_BUF_WAKE_S = 11 +const RTC_CNTL_BIAS_BUF_IDLE_V = 0x1 +const RTC_CNTL_BIAS_BUF_IDLE_S = 10 +const RTC_CNTL_REGULATOR_FORCE_PU_V = 0x1 +const RTC_CNTL_REGULATOR_FORCE_PU_S = 31 +const RTC_CNTL_REGULATOR_FORCE_PD_V = 0x1 +const RTC_CNTL_REGULATOR_FORCE_PD_S = 30 +const RTC_CNTL_DBOOST_FORCE_PU_V = 0x1 +const RTC_CNTL_DBOOST_FORCE_PU_S = 29 +const RTC_CNTL_DBOOST_FORCE_PD_V = 0x1 +const RTC_CNTL_DBOOST_FORCE_PD_S = 28 +const RTC_CNTL_DIG_DBIAS_0V85 = 0 +const RTC_CNTL_DIG_DBIAS_0V90 = 1 +const RTC_CNTL_DIG_DBIAS_0V95 = 2 +const RTC_CNTL_DIG_DBIAS_1V00 = 3 +const RTC_CNTL_DIG_DBIAS_1V05 = 4 +const RTC_CNTL_DIG_DBIAS_1V10 = 5 +const RTC_CNTL_DIG_DBIAS_1V15 = 6 +const RTC_CNTL_DIG_DBIAS_1V20 = 7 +const RTC_CNTL_SCK_DCAP = 0x000000FF +const RTC_CNTL_SCK_DCAP_V = 0xFF +const RTC_CNTL_SCK_DCAP_S = 14 +const RTC_CNTL_DIG_CAL_EN_V = 0x1 +const RTC_CNTL_DIG_CAL_EN_S = 7 +const RTC_CNTL_PAD_FORCE_HOLD_V = 0x1 +const RTC_CNTL_PAD_FORCE_HOLD_S = 21 +const RTC_CNTL_PD_EN_V = 0x1 +const RTC_CNTL_PD_EN_S = 20 +const RTC_CNTL_FORCE_PU_V = 0x1 +const RTC_CNTL_FORCE_PU_S = 19 +const RTC_CNTL_FORCE_PD_V = 0x1 +const RTC_CNTL_FORCE_PD_S = 18 +const RTC_CNTL_SLOWMEM_FORCE_LPU_V = 0x1 +const RTC_CNTL_SLOWMEM_FORCE_LPU_S = 11 +const RTC_CNTL_SLOWMEM_FORCE_LPD_V = 0x1 +const RTC_CNTL_SLOWMEM_FORCE_LPD_S = 10 +const RTC_CNTL_SLOWMEM_FOLW_CPU_V = 0x1 +const RTC_CNTL_SLOWMEM_FOLW_CPU_S = 9 +const RTC_CNTL_FASTMEM_FORCE_LPU_V = 0x1 +const RTC_CNTL_FASTMEM_FORCE_LPU_S = 8 +const RTC_CNTL_FASTMEM_FORCE_LPD_V = 0x1 +const RTC_CNTL_FASTMEM_FORCE_LPD_S = 7 +const RTC_CNTL_FASTMEM_FOLW_CPU_V = 0x1 +const RTC_CNTL_FASTMEM_FOLW_CPU_S = 6 +const RTC_CNTL_FORCE_NOISO_V = 0x1 +const RTC_CNTL_FORCE_NOISO_S = 5 +const RTC_CNTL_FORCE_ISO_V = 0x1 +const RTC_CNTL_FORCE_ISO_S = 4 +const RTC_CNTL_SLOWMEM_FORCE_ISO_V = 0x1 +const RTC_CNTL_SLOWMEM_FORCE_ISO_S = 3 +const RTC_CNTL_SLOWMEM_FORCE_NOISO_V = 0x1 +const RTC_CNTL_SLOWMEM_FORCE_NOISO_S = 2 +const RTC_CNTL_FASTMEM_FORCE_ISO_V = 0x1 +const RTC_CNTL_FASTMEM_FORCE_ISO_S = 1 +const RTC_CNTL_FASTMEM_FORCE_NOISO_V = 0x1 +const RTC_CNTL_FASTMEM_FORCE_NOISO_S = 0 +const RTC_CNTL_DG_VDD_DRV_B_MONITOR = 0x000000FF +const RTC_CNTL_DG_VDD_DRV_B_MONITOR_V = 0xFF +const RTC_CNTL_DG_VDD_DRV_B_MONITOR_S = 20 +const RTC_CNTL_DG_VDD_DRV_B_SLP = 0x000000FF +const RTC_CNTL_DG_VDD_DRV_B_SLP_V = 0xFF +const RTC_CNTL_DG_VDD_DRV_B_SLP_S = 12 +const RTC_CNTL_REGULATOR_DRV_B_SLP = 0x0000003F +const RTC_CNTL_REGULATOR_DRV_B_SLP_V = 0x3F +const RTC_CNTL_REGULATOR_DRV_B_SLP_S = 6 +const RTC_CNTL_REGULATOR_DRV_B_MONITOR = 0x0000003F +const RTC_CNTL_REGULATOR_DRV_B_MONITOR_V = 0x3F +const RTC_CNTL_REGULATOR_DRV_B_MONITOR_S = 0 +const RTC_CNTL_DG_WRAP_PD_EN_V = 0x1 +const RTC_CNTL_DG_WRAP_PD_EN_S = 31 +const RTC_CNTL_WIFI_PD_EN_V = 0x1 +const RTC_CNTL_WIFI_PD_EN_S = 30 +const RTC_CNTL_CPU_TOP_PD_EN_V = 0x1 +const RTC_CNTL_CPU_TOP_PD_EN_S = 29 +const RTC_CNTL_DG_PERI_PD_EN_V = 0x1 +const RTC_CNTL_DG_PERI_PD_EN_S = 28 +const RTC_CNTL_CPU_TOP_FORCE_PU_V = 0x1 +const RTC_CNTL_CPU_TOP_FORCE_PU_S = 22 +const RTC_CNTL_CPU_TOP_FORCE_PD_V = 0x1 +const RTC_CNTL_CPU_TOP_FORCE_PD_S = 21 +const RTC_CNTL_DG_WRAP_FORCE_PU_V = 0x1 +const RTC_CNTL_DG_WRAP_FORCE_PU_S = 20 +const RTC_CNTL_DG_WRAP_FORCE_PD_V = 0x1 +const RTC_CNTL_DG_WRAP_FORCE_PD_S = 19 +const RTC_CNTL_WIFI_FORCE_PU_V = 0x1 +const RTC_CNTL_WIFI_FORCE_PU_S = 18 +const RTC_CNTL_WIFI_FORCE_PD_V = 0x1 +const RTC_CNTL_WIFI_FORCE_PD_S = 17 +const RTC_CNTL_DG_PERI_FORCE_PU_V = 0x1 +const RTC_CNTL_DG_PERI_FORCE_PU_S = 14 +const RTC_CNTL_DG_PERI_FORCE_PD_V = 0x1 +const RTC_CNTL_DG_PERI_FORCE_PD_S = 13 +const RTC_CNTL_BT_FORCE_PU_V = 0x1 +const RTC_CNTL_BT_FORCE_PU_S = 12 +const RTC_CNTL_BT_FORCE_PD_V = 0x1 +const RTC_CNTL_BT_FORCE_PD_S = 11 +const RTC_CNTL_LSLP_MEM_FORCE_PU_V = 0x1 +const RTC_CNTL_LSLP_MEM_FORCE_PU_S = 4 +const RTC_CNTL_LSLP_MEM_FORCE_PD_V = 0x1 +const RTC_CNTL_LSLP_MEM_FORCE_PD_S = 3 +const RTC_CNTL_DG_WRAP_FORCE_NOISO_V = 0x1 +const RTC_CNTL_DG_WRAP_FORCE_NOISO_S = 31 +const RTC_CNTL_DG_WRAP_FORCE_ISO_V = 0x1 +const RTC_CNTL_DG_WRAP_FORCE_ISO_S = 30 +const RTC_CNTL_WIFI_FORCE_NOISO_V = 0x1 +const RTC_CNTL_WIFI_FORCE_NOISO_S = 29 +const RTC_CNTL_WIFI_FORCE_ISO_V = 0x1 +const RTC_CNTL_WIFI_FORCE_ISO_S = 28 +const RTC_CNTL_CPU_TOP_FORCE_NOISO_V = 0x1 +const RTC_CNTL_CPU_TOP_FORCE_NOISO_S = 27 +const RTC_CNTL_CPU_TOP_FORCE_ISO_V = 0x1 +const RTC_CNTL_CPU_TOP_FORCE_ISO_S = 26 +const RTC_CNTL_DG_PERI_FORCE_NOISO_V = 0x1 +const RTC_CNTL_DG_PERI_FORCE_NOISO_S = 25 +const RTC_CNTL_DG_PERI_FORCE_ISO_V = 0x1 +const RTC_CNTL_DG_PERI_FORCE_ISO_S = 24 +const RTC_CNTL_BT_FORCE_NOISO_V = 0x1 +const RTC_CNTL_BT_FORCE_NOISO_S = 23 +const RTC_CNTL_BT_FORCE_ISO_V = 0x1 +const RTC_CNTL_BT_FORCE_ISO_S = 22 +const RTC_CNTL_DG_PAD_FORCE_HOLD_V = 0x1 +const RTC_CNTL_DG_PAD_FORCE_HOLD_S = 15 +const RTC_CNTL_DG_PAD_FORCE_UNHOLD_V = 0x1 +const RTC_CNTL_DG_PAD_FORCE_UNHOLD_S = 14 +const RTC_CNTL_DG_PAD_FORCE_ISO_V = 0x1 +const RTC_CNTL_DG_PAD_FORCE_ISO_S = 13 +const RTC_CNTL_DG_PAD_FORCE_NOISO_V = 0x1 +const RTC_CNTL_DG_PAD_FORCE_NOISO_S = 12 +const RTC_CNTL_DG_PAD_AUTOHOLD_EN_V = 0x1 +const RTC_CNTL_DG_PAD_AUTOHOLD_EN_S = 11 +const RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V = 0x1 +const RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S = 10 +const RTC_CNTL_DG_PAD_AUTOHOLD_V = 0x1 +const RTC_CNTL_DG_PAD_AUTOHOLD_S = 9 +const RTC_CNTL_DIG_ISO_FORCE_ON_V = 0x1 +const RTC_CNTL_DIG_ISO_FORCE_ON_S = 8 +const RTC_CNTL_DIG_ISO_FORCE_OFF_V = 0x1 +const RTC_CNTL_DIG_ISO_FORCE_OFF_S = 7 +const RTC_CNTL_WDT_EN_V = 0x1 +const RTC_CNTL_WDT_EN_S = 31 +const RTC_CNTL_WDT_STG0 = 0x00000007 +const RTC_CNTL_WDT_STG0_V = 0x7 +const RTC_CNTL_WDT_STG0_S = 28 +const RTC_CNTL_WDT_STG1 = 0x00000007 +const RTC_CNTL_WDT_STG1_V = 0x7 +const RTC_CNTL_WDT_STG1_S = 25 +const RTC_CNTL_WDT_STG2 = 0x00000007 +const RTC_CNTL_WDT_STG2_V = 0x7 +const RTC_CNTL_WDT_STG2_S = 22 +const RTC_CNTL_WDT_STG3 = 0x00000007 +const RTC_CNTL_WDT_STG3_V = 0x7 +const RTC_CNTL_WDT_STG3_S = 19 +const RTC_CNTL_WDT_CPU_RESET_LENGTH = 0x00000007 +const RTC_CNTL_WDT_CPU_RESET_LENGTH_V = 0x7 +const RTC_CNTL_WDT_CPU_RESET_LENGTH_S = 16 +const RTC_CNTL_WDT_SYS_RESET_LENGTH = 0x00000007 +const RTC_CNTL_WDT_SYS_RESET_LENGTH_V = 0x7 +const RTC_CNTL_WDT_SYS_RESET_LENGTH_S = 13 +const RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V = 0x1 +const RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S = 12 +const RTC_CNTL_WDT_PROCPU_RESET_EN_V = 0x1 +const RTC_CNTL_WDT_PROCPU_RESET_EN_S = 11 +const RTC_CNTL_WDT_APPCPU_RESET_EN_V = 0x1 +const RTC_CNTL_WDT_APPCPU_RESET_EN_S = 10 +const RTC_CNTL_WDT_PAUSE_IN_SLP_V = 0x1 +const RTC_CNTL_WDT_PAUSE_IN_SLP_S = 9 +const RTC_CNTL_WDT_CHIP_RESET_EN_V = 0x1 +const RTC_CNTL_WDT_CHIP_RESET_EN_S = 8 +const RTC_CNTL_WDT_CHIP_RESET_WIDTH = 0x000000FF +const RTC_CNTL_WDT_CHIP_RESET_WIDTH_V = 0xFF +const RTC_CNTL_WDT_CHIP_RESET_WIDTH_S = 0 +const RTC_CNTL_WDT_STG0_HOLD = 0xFFFFFFFF +const RTC_CNTL_WDT_STG0_HOLD_V = 0xFFFFFFFF +const RTC_CNTL_WDT_STG0_HOLD_S = 0 +const RTC_CNTL_WDT_STG1_HOLD = 0xFFFFFFFF +const RTC_CNTL_WDT_STG1_HOLD_V = 0xFFFFFFFF +const RTC_CNTL_WDT_STG1_HOLD_S = 0 +const RTC_CNTL_WDT_STG2_HOLD = 0xFFFFFFFF +const RTC_CNTL_WDT_STG2_HOLD_V = 0xFFFFFFFF +const RTC_CNTL_WDT_STG2_HOLD_S = 0 +const RTC_CNTL_WDT_STG3_HOLD = 0xFFFFFFFF +const RTC_CNTL_WDT_STG3_HOLD_V = 0xFFFFFFFF +const RTC_CNTL_WDT_STG3_HOLD_S = 0 +const RTC_CNTL_WDT_FEED_V = 0x1 +const RTC_CNTL_WDT_FEED_S = 31 +const RTC_CNTL_WDT_WKEY = 0xFFFFFFFF +const RTC_CNTL_WDT_WKEY_V = 0xFFFFFFFF +const RTC_CNTL_WDT_WKEY_S = 0 +const RTC_CNTL_SWD_AUTO_FEED_EN_V = 0x1 +const RTC_CNTL_SWD_AUTO_FEED_EN_S = 31 +const RTC_CNTL_SWD_DISABLE_V = 0x1 +const RTC_CNTL_SWD_DISABLE_S = 30 +const RTC_CNTL_SWD_FEED_V = 0x1 +const RTC_CNTL_SWD_FEED_S = 29 +const RTC_CNTL_SWD_RST_FLAG_CLR_V = 0x1 +const RTC_CNTL_SWD_RST_FLAG_CLR_S = 28 +const RTC_CNTL_SWD_SIGNAL_WIDTH = 0x000003FF +const RTC_CNTL_SWD_SIGNAL_WIDTH_V = 0x3FF +const RTC_CNTL_SWD_SIGNAL_WIDTH_S = 18 +const RTC_CNTL_SWD_BYPASS_RST_V = 0x1 +const RTC_CNTL_SWD_BYPASS_RST_S = 17 +const RTC_CNTL_SWD_FEED_INT_V = 0x1 +const RTC_CNTL_SWD_FEED_INT_S = 1 +const RTC_CNTL_SWD_RESET_FLAG_V = 0x1 +const RTC_CNTL_SWD_RESET_FLAG_S = 0 +const RTC_CNTL_SWD_WKEY = 0xFFFFFFFF +const RTC_CNTL_SWD_WKEY_V = 0xFFFFFFFF +const RTC_CNTL_SWD_WKEY_S = 0 +const RTC_CNTL_SW_STALL_PROCPU_C1 = 0x0000003F +const RTC_CNTL_SW_STALL_PROCPU_C1_V = 0x3F +const RTC_CNTL_SW_STALL_PROCPU_C1_S = 26 +const RTC_CNTL_SW_STALL_APPCPU_C1 = 0x0000003F +const RTC_CNTL_SW_STALL_APPCPU_C1_V = 0x3F +const RTC_CNTL_SW_STALL_APPCPU_C1_S = 20 +const RTC_CNTL_SCRATCH4 = 0xFFFFFFFF +const RTC_CNTL_SCRATCH4_V = 0xFFFFFFFF +const RTC_CNTL_SCRATCH4_S = 0 +const RTC_CNTL_SCRATCH5 = 0xFFFFFFFF +const RTC_CNTL_SCRATCH5_V = 0xFFFFFFFF +const RTC_CNTL_SCRATCH5_S = 0 +const RTC_CNTL_SCRATCH6 = 0xFFFFFFFF +const RTC_CNTL_SCRATCH6_V = 0xFFFFFFFF +const RTC_CNTL_SCRATCH6_S = 0 +const RTC_CNTL_SCRATCH7 = 0xFFFFFFFF +const RTC_CNTL_SCRATCH7_V = 0xFFFFFFFF +const RTC_CNTL_SCRATCH7_S = 0 +const RTC_CNTL_MAIN_STATE = 0x0000000F +const RTC_CNTL_MAIN_STATE_V = 0xF +const RTC_CNTL_MAIN_STATE_S = 28 +const RTC_CNTL_MAIN_STATE_IN_IDLE_V = 0x1 +const RTC_CNTL_MAIN_STATE_IN_IDLE_S = 27 +const RTC_CNTL_MAIN_STATE_IN_SLP_V = 0x1 +const RTC_CNTL_MAIN_STATE_IN_SLP_S = 26 +const RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V = 0x1 +const RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S = 25 +const RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V = 0x1 +const RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S = 24 +const RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V = 0x1 +const RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S = 23 +const RTC_CNTL_IN_LOW_POWER_STATE_V = 0x1 +const RTC_CNTL_IN_LOW_POWER_STATE_S = 22 +const RTC_CNTL_IN_WAKEUP_STATE_V = 0x1 +const RTC_CNTL_IN_WAKEUP_STATE_S = 21 +const RTC_CNTL_MAIN_STATE_WAIT_END_V = 0x1 +const RTC_CNTL_MAIN_STATE_WAIT_END_S = 20 +const RTC_CNTL_RDY_FOR_WAKEUP_V = 0x1 +const RTC_CNTL_RDY_FOR_WAKEUP_S = 19 +const RTC_CNTL_MAIN_STATE_PLL_ON_V = 0x1 +const RTC_CNTL_MAIN_STATE_PLL_ON_S = 18 +const RTC_CNTL_MAIN_STATE_XTAL_ISO_V = 0x1 +const RTC_CNTL_MAIN_STATE_XTAL_ISO_S = 17 +const RTC_CNTL_COCPU_STATE_DONE_V = 0x1 +const RTC_CNTL_COCPU_STATE_DONE_S = 16 +const RTC_CNTL_COCPU_STATE_SLP_V = 0x1 +const RTC_CNTL_COCPU_STATE_SLP_S = 15 +const RTC_CNTL_COCPU_STATE_SWITCH_V = 0x1 +const RTC_CNTL_COCPU_STATE_SWITCH_S = 14 +const RTC_CNTL_COCPU_STATE_START_V = 0x1 +const RTC_CNTL_COCPU_STATE_START_S = 13 +const RTC_CNTL_TOUCH_STATE_DONE_V = 0x1 +const RTC_CNTL_TOUCH_STATE_DONE_S = 12 +const RTC_CNTL_TOUCH_STATE_SLP_V = 0x1 +const RTC_CNTL_TOUCH_STATE_SLP_S = 11 +const RTC_CNTL_TOUCH_STATE_SWITCH_V = 0x1 +const RTC_CNTL_TOUCH_STATE_SWITCH_S = 10 +const RTC_CNTL_TOUCH_STATE_START_V = 0x1 +const RTC_CNTL_TOUCH_STATE_START_S = 9 +const RTC_CNTL_XPD_DIG_V = 0x1 +const RTC_CNTL_XPD_DIG_S = 8 +const RTC_CNTL_DIG_ISO_V = 0x1 +const RTC_CNTL_DIG_ISO_S = 7 +const RTC_CNTL_XPD_WIFI_V = 0x1 +const RTC_CNTL_XPD_WIFI_S = 6 +const RTC_CNTL_WIFI_ISO_V = 0x1 +const RTC_CNTL_WIFI_ISO_S = 5 +const RTC_CNTL_XPD_RTC_PERI_V = 0x1 +const RTC_CNTL_XPD_RTC_PERI_S = 4 +const RTC_CNTL_PERI_ISO_V = 0x1 +const RTC_CNTL_PERI_ISO_S = 3 +const RTC_CNTL_XPD_DIG_DCDC_V = 0x1 +const RTC_CNTL_XPD_DIG_DCDC_S = 2 +const RTC_CNTL_XPD_ROM0_V = 0x1 +const RTC_CNTL_XPD_ROM0_S = 0 +const RTC_CNTL_LOW_POWER_DIAG1 = 0xFFFFFFFF +const RTC_CNTL_LOW_POWER_DIAG1_V = 0xFFFFFFFF +const RTC_CNTL_LOW_POWER_DIAG1_S = 0 +const RTC_CNTL_PAD21_HOLD_V = 0x1 +const RTC_CNTL_PAD21_HOLD_S = 21 +const RTC_CNTL_PAD20_HOLD_V = 0x1 +const RTC_CNTL_PAD20_HOLD_S = 20 +const RTC_CNTL_PAD19_HOLD_V = 0x1 +const RTC_CNTL_PAD19_HOLD_S = 19 +const RTC_CNTL_PDAC2_HOLD_V = 0x1 +const RTC_CNTL_PDAC2_HOLD_S = 18 +const RTC_CNTL_PDAC1_HOLD_V = 0x1 +const RTC_CNTL_PDAC1_HOLD_S = 17 +const RTC_CNTL_X32N_HOLD_V = 0x1 +const RTC_CNTL_X32N_HOLD_S = 16 +const RTC_CNTL_X32P_HOLD_V = 0x1 +const RTC_CNTL_X32P_HOLD_S = 15 +const RTC_CNTL_TOUCH_PAD14_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD14_HOLD_S = 14 +const RTC_CNTL_TOUCH_PAD13_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD13_HOLD_S = 13 +const RTC_CNTL_TOUCH_PAD12_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD12_HOLD_S = 12 +const RTC_CNTL_TOUCH_PAD11_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD11_HOLD_S = 11 +const RTC_CNTL_TOUCH_PAD10_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD10_HOLD_S = 10 +const RTC_CNTL_TOUCH_PAD9_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD9_HOLD_S = 9 +const RTC_CNTL_TOUCH_PAD8_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD8_HOLD_S = 8 +const RTC_CNTL_TOUCH_PAD7_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD7_HOLD_S = 7 +const RTC_CNTL_TOUCH_PAD6_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD6_HOLD_S = 6 +const RTC_CNTL_TOUCH_PAD5_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD5_HOLD_S = 5 +const RTC_CNTL_TOUCH_PAD4_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD4_HOLD_S = 4 +const RTC_CNTL_TOUCH_PAD3_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD3_HOLD_S = 3 +const RTC_CNTL_TOUCH_PAD2_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD2_HOLD_S = 2 +const RTC_CNTL_TOUCH_PAD1_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD1_HOLD_S = 1 +const RTC_CNTL_TOUCH_PAD0_HOLD_V = 0x1 +const RTC_CNTL_TOUCH_PAD0_HOLD_S = 0 +const RTC_CNTL_DIG_PAD_HOLD = 0xFFFFFFFF +const RTC_CNTL_DIG_PAD_HOLD_V = 0xFFFFFFFF +const RTC_CNTL_DIG_PAD_HOLD_S = 0 +const RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V = 0x1 +const RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S = 22 +const RTC_CNTL_EXT_WAKEUP1_SEL = 0x003FFFFF +const RTC_CNTL_EXT_WAKEUP1_SEL_V = 0x3FFFFF +const RTC_CNTL_EXT_WAKEUP1_SEL_S = 0 +const RTC_CNTL_EXT_WAKEUP1_STATUS = 0x003FFFFF +const RTC_CNTL_EXT_WAKEUP1_STATUS_V = 0x3FFFFF +const RTC_CNTL_EXT_WAKEUP1_STATUS_S = 0 +const RTC_CNTL_BROWN_OUT_DET_V = 0x1 +const RTC_CNTL_BROWN_OUT_DET_S = 31 +const RTC_CNTL_BROWN_OUT_ENA_V = 0x1 +const RTC_CNTL_BROWN_OUT_ENA_S = 30 +const RTC_CNTL_BROWN_OUT_CNT_CLR_V = 0x1 +const RTC_CNTL_BROWN_OUT_CNT_CLR_S = 29 +const RTC_CNTL_BROWN_OUT_ANA_RST_EN_V = 0x1 +const RTC_CNTL_BROWN_OUT_ANA_RST_EN_S = 28 +const RTC_CNTL_BROWN_OUT_RST_SEL_V = 0x1 +const RTC_CNTL_BROWN_OUT_RST_SEL_S = 27 +const RTC_CNTL_BROWN_OUT_RST_ENA_V = 0x1 +const RTC_CNTL_BROWN_OUT_RST_ENA_S = 26 +const RTC_CNTL_BROWN_OUT_RST_WAIT = 0x000003FF +const RTC_CNTL_BROWN_OUT_RST_WAIT_V = 0x3FF +const RTC_CNTL_BROWN_OUT_RST_WAIT_S = 16 +const RTC_CNTL_BROWN_OUT_PD_RF_ENA_V = 0x1 +const RTC_CNTL_BROWN_OUT_PD_RF_ENA_S = 15 +const RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V = 0x1 +const RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S = 14 +const RTC_CNTL_BROWN_OUT_INT_WAIT = 0x000003FF +const RTC_CNTL_BROWN_OUT_INT_WAIT_V = 0x3FF +const RTC_CNTL_BROWN_OUT_INT_WAIT_S = 4 +const RTC_CNTL_TIMER_VALUE1_LOW = 0xFFFFFFFF +const RTC_CNTL_TIMER_VALUE1_LOW_V = 0xFFFFFFFF +const RTC_CNTL_TIMER_VALUE1_LOW_S = 0 +const RTC_CNTL_TIMER_VALUE1_HIGH = 0x0000FFFF +const RTC_CNTL_TIMER_VALUE1_HIGH_V = 0xFFFF +const RTC_CNTL_TIMER_VALUE1_HIGH_S = 0 +const RTC_CNTL_XTAL32K_CLK_FACTOR = 0xFFFFFFFF +const RTC_CNTL_XTAL32K_CLK_FACTOR_V = 0xFFFFFFFF +const RTC_CNTL_XTAL32K_CLK_FACTOR_S = 0 +const RTC_CNTL_XTAL32K_STABLE_THRES = 0x0000000F +const RTC_CNTL_XTAL32K_STABLE_THRES_V = 0xF +const RTC_CNTL_XTAL32K_STABLE_THRES_S = 28 +const RTC_CNTL_XTAL32K_WDT_TIMEOUT = 0x000000FF +const RTC_CNTL_XTAL32K_WDT_TIMEOUT_V = 0xFF +const RTC_CNTL_XTAL32K_WDT_TIMEOUT_S = 20 +const RTC_CNTL_XTAL32K_RESTART_WAIT = 0x0000FFFF +const RTC_CNTL_XTAL32K_RESTART_WAIT_V = 0xFFFF +const RTC_CNTL_XTAL32K_RESTART_WAIT_S = 4 +const RTC_CNTL_XTAL32K_RETURN_WAIT = 0x0000000F +const RTC_CNTL_XTAL32K_RETURN_WAIT_V = 0xF +const RTC_CNTL_XTAL32K_RETURN_WAIT_S = 0 +const RTC_CNTL_ULP_CP_SLP_TIMER_EN_V = 0x1 +const RTC_CNTL_ULP_CP_SLP_TIMER_EN_S = 31 +const RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V = 0x1 +const RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S = 30 +const RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V = 0x1 +const RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S = 29 +const RTC_CNTL_ULP_CP_PC_INIT = 0x000007FF +const RTC_CNTL_ULP_CP_PC_INIT_V = 0x7FF +const RTC_CNTL_ULP_CP_PC_INIT_S = 0 +const RTC_CNTL_ULP_CP_START_TOP_V = 0x1 +const RTC_CNTL_ULP_CP_START_TOP_S = 31 +const RTC_CNTL_ULP_CP_FORCE_START_TOP_V = 0x1 +const RTC_CNTL_ULP_CP_FORCE_START_TOP_S = 30 +const RTC_CNTL_ULP_CP_RESET_V = 0x1 +const RTC_CNTL_ULP_CP_RESET_S = 29 +const RTC_CNTL_ULP_CP_CLK_FO_V = 0x1 +const RTC_CNTL_ULP_CP_CLK_FO_S = 28 +const RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V = 0x1 +const RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S = 22 +const RTC_CNTL_ULP_CP_MEM_ADDR_SIZE = 0x000007FF +const RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V = 0x7FF +const RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S = 11 +const RTC_CNTL_ULP_CP_MEM_ADDR_INIT = 0x000007FF +const RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V = 0x7FF +const RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S = 0 +const RTC_CNTL_COCPU_CLKGATE_EN_V = 0x1 +const RTC_CNTL_COCPU_CLKGATE_EN_S = 27 +const RTC_CNTL_COCPU_SW_INT_TRIGGER_V = 0x1 +const RTC_CNTL_COCPU_SW_INT_TRIGGER_S = 26 +const RTC_CNTL_COCPU_DONE_V = 0x1 +const RTC_CNTL_COCPU_DONE_S = 25 +const RTC_CNTL_COCPU_DONE_FORCE_V = 0x1 +const RTC_CNTL_COCPU_DONE_FORCE_S = 24 +const RTC_CNTL_COCPU_SEL_V = 0x1 +const RTC_CNTL_COCPU_SEL_S = 23 +const RTC_CNTL_COCPU_SHUT_RESET_EN_V = 0x1 +const RTC_CNTL_COCPU_SHUT_RESET_EN_S = 22 +const RTC_CNTL_COCPU_SHUT_2_CLK_DIS = 0x000000FF +const RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V = 0xFF +const RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S = 14 +const RTC_CNTL_COCPU_SHUT_V = 0x1 +const RTC_CNTL_COCPU_SHUT_S = 13 +const RTC_CNTL_COCPU_START_2_INTR_EN = 0x0000003F +const RTC_CNTL_COCPU_START_2_INTR_EN_V = 0x3F +const RTC_CNTL_COCPU_START_2_INTR_EN_S = 7 +const RTC_CNTL_COCPU_START_2_RESET_DIS = 0x0000003F +const RTC_CNTL_COCPU_START_2_RESET_DIS_V = 0x3F +const RTC_CNTL_COCPU_START_2_RESET_DIS_S = 1 +const RTC_CNTL_COCPU_CLK_FO_V = 0x1 +const RTC_CNTL_COCPU_CLK_FO_S = 0 +const RTC_CNTL_TOUCH_MEAS_NUM = 0x0000FFFF +const RTC_CNTL_TOUCH_MEAS_NUM_V = 0xFFFF +const RTC_CNTL_TOUCH_MEAS_NUM_S = 16 +const RTC_CNTL_TOUCH_SLEEP_CYCLES = 0x0000FFFF +const RTC_CNTL_TOUCH_SLEEP_CYCLES_V = 0xFFFF +const RTC_CNTL_TOUCH_SLEEP_CYCLES_S = 0 +const RTC_CNTL_TOUCH_CLKGATE_EN_V = 0x1 +const RTC_CNTL_TOUCH_CLKGATE_EN_S = 31 +const RTC_CNTL_TOUCH_CLK_FO_V = 0x1 +const RTC_CNTL_TOUCH_CLK_FO_S = 30 +const RTC_CNTL_TOUCH_RESET_V = 0x1 +const RTC_CNTL_TOUCH_RESET_S = 29 +const RTC_CNTL_TOUCH_TIMER_FORCE_DONE = 0x00000003 +const RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V = 0x3 +const RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S = 27 +const RTC_CNTL_TOUCH_SLP_CYC_DIV = 0x00000003 +const RTC_CNTL_TOUCH_SLP_CYC_DIV_V = 0x3 +const RTC_CNTL_TOUCH_SLP_CYC_DIV_S = 25 +const RTC_CNTL_TOUCH_XPD_WAIT = 0x000000FF +const RTC_CNTL_TOUCH_XPD_WAIT_V = 0xFF +const RTC_CNTL_TOUCH_XPD_WAIT_S = 17 +const RTC_CNTL_TOUCH_START_FORCE_V = 0x1 +const RTC_CNTL_TOUCH_START_FORCE_S = 16 +const RTC_CNTL_TOUCH_START_EN_V = 0x1 +const RTC_CNTL_TOUCH_START_EN_S = 15 +const RTC_CNTL_TOUCH_START_FSM_EN_V = 0x1 +const RTC_CNTL_TOUCH_START_FSM_EN_S = 14 +const RTC_CNTL_TOUCH_SLP_TIMER_EN_V = 0x1 +const RTC_CNTL_TOUCH_SLP_TIMER_EN_S = 13 +const RTC_CNTL_TOUCH_DBIAS_V = 0x1 +const RTC_CNTL_TOUCH_DBIAS_S = 12 +const RTC_CNTL_TOUCH_REFC = 0x00000007 +const RTC_CNTL_TOUCH_REFC_V = 0x7 +const RTC_CNTL_TOUCH_REFC_S = 9 +const RTC_CNTL_TOUCH_XPD_BIAS_V = 0x1 +const RTC_CNTL_TOUCH_XPD_BIAS_S = 8 +const RTC_CNTL_TOUCH_DREFH = 0x00000003 +const RTC_CNTL_TOUCH_DREFH_V = 0x3 +const RTC_CNTL_TOUCH_DREFH_S = 6 +const RTC_CNTL_TOUCH_DREFL = 0x00000003 +const RTC_CNTL_TOUCH_DREFL_V = 0x3 +const RTC_CNTL_TOUCH_DREFL_S = 4 +const RTC_CNTL_TOUCH_DRANGE = 0x00000003 +const RTC_CNTL_TOUCH_DRANGE_V = 0x3 +const RTC_CNTL_TOUCH_DRANGE_S = 2 +const RTC_CNTL_TOUCH_OUT_RING = 0x0000000F +const RTC_CNTL_TOUCH_OUT_RING_V = 0xF +const RTC_CNTL_TOUCH_OUT_RING_S = 28 +const RTC_CNTL_TOUCH_BUFDRV = 0x00000007 +const RTC_CNTL_TOUCH_BUFDRV_V = 0x7 +const RTC_CNTL_TOUCH_BUFDRV_S = 25 +const RTC_CNTL_TOUCH_SCAN_PAD_MAP = 0x00007FFF +const RTC_CNTL_TOUCH_SCAN_PAD_MAP_V = 0x7FFF +const RTC_CNTL_TOUCH_SCAN_PAD_MAP_S = 10 +const RTC_CNTL_TOUCH_SHIELD_PAD_EN_V = 0x1 +const RTC_CNTL_TOUCH_SHIELD_PAD_EN_S = 9 +const RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V = 0x1 +const RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S = 8 +const RTC_CNTL_TOUCH_DENOISE_EN_V = 0x1 +const RTC_CNTL_TOUCH_DENOISE_EN_S = 2 +const RTC_CNTL_TOUCH_DENOISE_RES = 0x00000003 +const RTC_CNTL_TOUCH_DENOISE_RES_V = 0x3 +const RTC_CNTL_TOUCH_DENOISE_RES_S = 0 +const RTC_CNTL_TOUCH_SLP_PAD = 0x0000001F +const RTC_CNTL_TOUCH_SLP_PAD_V = 0x1F +const RTC_CNTL_TOUCH_SLP_PAD_S = 27 +const RTC_CNTL_TOUCH_SLP_APPROACH_EN_V = 0x1 +const RTC_CNTL_TOUCH_SLP_APPROACH_EN_S = 26 +const RTC_CNTL_TOUCH_SLP_TH = 0x003FFFFF +const RTC_CNTL_TOUCH_SLP_TH_V = 0x3FFFFF +const RTC_CNTL_TOUCH_SLP_TH_S = 0 +const RTC_CNTL_TOUCH_APPROACH_MEAS_TIME = 0x000000FF +const RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V = 0xFF +const RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S = 24 +const RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V = 0x1 +const RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S = 23 +const RTC_CNTL_TOUCH_FILTER_EN_V = 0x1 +const RTC_CNTL_TOUCH_FILTER_EN_S = 31 +const RTC_CNTL_TOUCH_FILTER_MODE = 0x00000007 +const RTC_CNTL_TOUCH_FILTER_MODE_V = 0x7 +const RTC_CNTL_TOUCH_FILTER_MODE_S = 28 +const RTC_CNTL_TOUCH_DEBOUNCE = 0x00000007 +const RTC_CNTL_TOUCH_DEBOUNCE_V = 0x7 +const RTC_CNTL_TOUCH_DEBOUNCE_S = 25 +const RTC_CNTL_TOUCH_CONFIG3 = 0x00000003 +const RTC_CNTL_TOUCH_CONFIG3_V = 0x3 +const RTC_CNTL_TOUCH_CONFIG3_S = 23 +const RTC_CNTL_TOUCH_NOISE_THRES = 0x00000003 +const RTC_CNTL_TOUCH_NOISE_THRES_V = 0x3 +const RTC_CNTL_TOUCH_NOISE_THRES_S = 21 +const RTC_CNTL_TOUCH_CONFIG2 = 0x00000003 +const RTC_CNTL_TOUCH_CONFIG2_V = 0x3 +const RTC_CNTL_TOUCH_CONFIG2_S = 19 +const RTC_CNTL_TOUCH_CONFIG1 = 0x0000000F +const RTC_CNTL_TOUCH_CONFIG1_V = 0xF +const RTC_CNTL_TOUCH_CONFIG1_S = 15 +const RTC_CNTL_TOUCH_JITTER_STEP = 0x0000000F +const RTC_CNTL_TOUCH_JITTER_STEP_V = 0xF +const RTC_CNTL_TOUCH_JITTER_STEP_S = 11 +const RTC_CNTL_TOUCH_SMOOTH_LVL = 0x00000003 +const RTC_CNTL_TOUCH_SMOOTH_LVL_V = 0x3 +const RTC_CNTL_TOUCH_SMOOTH_LVL_S = 9 +const RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V = 0x1 +const RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S = 8 +const RTC_CNTL_TOUCH_BYPASS_NEG_THRES_V = 0x1 +const RTC_CNTL_TOUCH_BYPASS_NEG_THRES_S = 7 +const RTC_CNTL_SW_HW_USB_PHY_SEL_V = 0x1 +const RTC_CNTL_SW_HW_USB_PHY_SEL_S = 20 +const RTC_CNTL_SW_USB_PHY_SEL_V = 0x1 +const RTC_CNTL_SW_USB_PHY_SEL_S = 19 +const RTC_CNTL_IO_MUX_RESET_DISABLE_V = 0x1 +const RTC_CNTL_IO_MUX_RESET_DISABLE_S = 18 +const RTC_CNTL_USB_RESET_DISABLE_V = 0x1 +const RTC_CNTL_USB_RESET_DISABLE_S = 17 +const RTC_CNTL_USB_TX_EN_OVERRIDE_V = 0x1 +const RTC_CNTL_USB_TX_EN_OVERRIDE_S = 16 +const RTC_CNTL_USB_TX_EN_V = 0x1 +const RTC_CNTL_USB_TX_EN_S = 15 +const RTC_CNTL_USB_TXP_V = 0x1 +const RTC_CNTL_USB_TXP_S = 14 +const RTC_CNTL_USB_TXM_V = 0x1 +const RTC_CNTL_USB_TXM_S = 13 +const RTC_CNTL_USB_PAD_ENABLE_V = 0x1 +const RTC_CNTL_USB_PAD_ENABLE_S = 12 +const RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V = 0x1 +const RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S = 11 +const RTC_CNTL_USB_PULLUP_VALUE_V = 0x1 +const RTC_CNTL_USB_PULLUP_VALUE_S = 10 +const RTC_CNTL_USB_DM_PULLDOWN_V = 0x1 +const RTC_CNTL_USB_DM_PULLDOWN_S = 9 +const RTC_CNTL_USB_DM_PULLUP_V = 0x1 +const RTC_CNTL_USB_DM_PULLUP_S = 8 +const RTC_CNTL_USB_DP_PULLDOWN_V = 0x1 +const RTC_CNTL_USB_DP_PULLDOWN_S = 7 +const RTC_CNTL_USB_DP_PULLUP_V = 0x1 +const RTC_CNTL_USB_DP_PULLUP_S = 6 +const RTC_CNTL_USB_PAD_PULL_OVERRIDE_V = 0x1 +const RTC_CNTL_USB_PAD_PULL_OVERRIDE_S = 5 +const RTC_CNTL_USB_VREF_OVERRIDE_V = 0x1 +const RTC_CNTL_USB_VREF_OVERRIDE_S = 4 +const RTC_CNTL_USB_VREFL = 0x00000003 +const RTC_CNTL_USB_VREFL_V = 0x3 +const RTC_CNTL_USB_VREFL_S = 2 +const RTC_CNTL_USB_VREFH = 0x00000003 +const RTC_CNTL_USB_VREFH_V = 0x3 +const RTC_CNTL_USB_VREFH_S = 0 +const RTC_CNTL_TOUCH_TIMEOUT_EN_V = 0x1 +const RTC_CNTL_TOUCH_TIMEOUT_EN_S = 22 +const RTC_CNTL_TOUCH_TIMEOUT_NUM = 0x003FFFFF +const RTC_CNTL_TOUCH_TIMEOUT_NUM_V = 0x3FFFFF +const RTC_CNTL_TOUCH_TIMEOUT_NUM_S = 0 +const RTC_CNTL_REJECT_CAUSE = 0x0003FFFF +const RTC_CNTL_REJECT_CAUSE_V = 0x3FFFF +const RTC_CNTL_REJECT_CAUSE_S = 0 +const RTC_CNTL_FORCE_DOWNLOAD_BOOT_V = 0x1 +const RTC_CNTL_FORCE_DOWNLOAD_BOOT_S = 0 +const RTC_CNTL_WAKEUP_CAUSE = 0x0001FFFF +const RTC_CNTL_WAKEUP_CAUSE_V = 0x1FFFF +const RTC_CNTL_WAKEUP_CAUSE_S = 0 +const RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE = 0x00FFFFFF +const RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V = 0xFFFFFF +const RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S = 8 +const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S = 20 +const RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S = 19 +const RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_S = 18 +const RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_S = 17 +const RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S = 16 +const RTC_CNTL_SWD_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_SWD_INT_ENA_W1TS_S = 15 +const RTC_CNTL_SARADC2_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_SARADC2_INT_ENA_W1TS_S = 14 +const RTC_CNTL_COCPU_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_COCPU_INT_ENA_W1TS_S = 13 +const RTC_CNTL_TSENS_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_TSENS_INT_ENA_W1TS_S = 12 +const RTC_CNTL_SARADC1_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_SARADC1_INT_ENA_W1TS_S = 11 +const RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S = 10 +const RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S = 9 +const RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_S = 8 +const RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_S = 7 +const RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_S = 6 +const RTC_CNTL_ULP_CP_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_ULP_CP_INT_ENA_W1TS_S = 5 +const RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_S = 4 +const RTC_CNTL_WDT_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_WDT_INT_ENA_W1TS_S = 3 +const RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S = 2 +const RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S = 1 +const RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V = 0x1 +const RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S = 0 +const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S = 20 +const RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S = 19 +const RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_S = 18 +const RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_S = 17 +const RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S = 16 +const RTC_CNTL_SWD_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_SWD_INT_ENA_W1TC_S = 15 +const RTC_CNTL_SARADC2_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_SARADC2_INT_ENA_W1TC_S = 14 +const RTC_CNTL_COCPU_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_COCPU_INT_ENA_W1TC_S = 13 +const RTC_CNTL_TSENS_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_TSENS_INT_ENA_W1TC_S = 12 +const RTC_CNTL_SARADC1_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_SARADC1_INT_ENA_W1TC_S = 11 +const RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S = 10 +const RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S = 9 +const RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_S = 8 +const RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_S = 7 +const RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_S = 6 +const RTC_CNTL_ULP_CP_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_ULP_CP_INT_ENA_W1TC_S = 5 +const RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_S = 4 +const RTC_CNTL_WDT_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_WDT_INT_ENA_W1TC_S = 3 +const RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S = 2 +const RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S = 1 +const RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V = 0x1 +const RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S = 0 +const RTC_CNTL_RETENTION_WAIT = 0x0000007F +const RTC_CNTL_RETENTION_WAIT_V = 0x7F +const RTC_CNTL_RETENTION_WAIT_S = 25 +const RTC_CNTL_RETENTION_EN_V = 0x1 +const RTC_CNTL_RETENTION_EN_S = 24 +const RTC_CNTL_RETENTION_CLKOFF_WAIT = 0x0000000F +const RTC_CNTL_RETENTION_CLKOFF_WAIT_V = 0xF +const RTC_CNTL_RETENTION_CLKOFF_WAIT_S = 20 +const RTC_CNTL_RETENTION_DONE_WAIT = 0x00000007 +const RTC_CNTL_RETENTION_DONE_WAIT_V = 0x7 +const RTC_CNTL_RETENTION_DONE_WAIT_S = 17 +const RTC_CNTL_RETENTION_CLK_SEL_V = 0x1 +const RTC_CNTL_RETENTION_CLK_SEL_S = 16 +const RTC_CNTL_RETENTION_TARGET = 0x00000003 +const RTC_CNTL_RETENTION_TARGET_V = 0x3 +const RTC_CNTL_RETENTION_TARGET_S = 14 +const RTC_CNTL_RETENTION_TAG_MODE = 0x0000000F +const RTC_CNTL_RETENTION_TAG_MODE_V = 0xF +const RTC_CNTL_RETENTION_TAG_MODE_S = 10 +const RTC_CNTL_POWER_GLITCH_EN_V = 0x1 +const RTC_CNTL_POWER_GLITCH_EN_S = 31 +const RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V = 0x1 +const RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S = 30 +const RTC_CNTL_POWER_GLITCH_FORCE_PU_V = 0x1 +const RTC_CNTL_POWER_GLITCH_FORCE_PU_S = 29 +const RTC_CNTL_POWER_GLITCH_FORCE_PD_V = 0x1 +const RTC_CNTL_POWER_GLITCH_FORCE_PD_S = 28 +const RTC_CNTL_POWER_GLITCH_DSENSE = 0x00000003 +const RTC_CNTL_POWER_GLITCH_DSENSE_V = 0x3 +const RTC_CNTL_POWER_GLITCH_DSENSE_S = 26 +const RTC_CNTL_FIB_SEL = 0x00000007 +const RTC_CNTL_FIB_SEL_V = 0x7 +const RTC_CNTL_FIB_SEL_S = 0 +const RTC_CNTL_TOUCH_PAD0_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD0_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD0_DAC_S = 29 +const RTC_CNTL_TOUCH_PAD1_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD1_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD1_DAC_S = 26 +const RTC_CNTL_TOUCH_PAD2_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD2_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD2_DAC_S = 23 +const RTC_CNTL_TOUCH_PAD3_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD3_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD3_DAC_S = 20 +const RTC_CNTL_TOUCH_PAD4_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD4_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD4_DAC_S = 17 +const RTC_CNTL_TOUCH_PAD5_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD5_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD5_DAC_S = 14 +const RTC_CNTL_TOUCH_PAD6_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD6_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD6_DAC_S = 11 +const RTC_CNTL_TOUCH_PAD7_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD7_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD7_DAC_S = 8 +const RTC_CNTL_TOUCH_PAD8_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD8_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD8_DAC_S = 5 +const RTC_CNTL_TOUCH_PAD9_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD9_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD9_DAC_S = 2 +const RTC_CNTL_TOUCH_PAD10_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD10_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD10_DAC_S = 29 +const RTC_CNTL_TOUCH_PAD11_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD11_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD11_DAC_S = 26 +const RTC_CNTL_TOUCH_PAD12_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD12_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD12_DAC_S = 23 +const RTC_CNTL_TOUCH_PAD13_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD13_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD13_DAC_S = 20 +const RTC_CNTL_TOUCH_PAD14_DAC = 0x00000007 +const RTC_CNTL_TOUCH_PAD14_DAC_V = 0x7 +const RTC_CNTL_TOUCH_PAD14_DAC_S = 17 +const RTC_CNTL_DISABLE_RTC_CPU_V = 0x1 +const RTC_CNTL_DISABLE_RTC_CPU_S = 31 +const RTC_CNTL_DATE = 0x0FFFFFFF +const RTC_CNTL_DATE_V = 0xFFFFFFF +const RTC_CNTL_DATE_S = 0 +const RTC_CNTL_SLAVE_PD = 0x0000003F +const RTC_CNTL_SLAVE_PD_V = 0x3F +const RTC_CNTL_SLAVE_PD_S = 13 diff --git a/esp32/rtc_cntl_struct.go b/esp32/rtc_cntl_struct.go new file mode 100644 index 00000000..75a2b6df --- /dev/null +++ b/esp32/rtc_cntl_struct.go @@ -0,0 +1,269 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type RtcCntlDevS struct { + Options0 struct { + Val c.Uint32T + } + SlpTimer0 c.Uint32T + SlpTimer1 struct { + Val c.Uint32T + } + TimeUpdate struct { + Val c.Uint32T + } + TimeLow0 c.Uint32T + TimeHigh0 struct { + Val c.Uint32T + } + State0 struct { + Val c.Uint32T + } + Timer1 struct { + Val c.Uint32T + } + Timer2 struct { + Val c.Uint32T + } + Timer3 struct { + Val c.Uint32T + } + Timer4 struct { + Val c.Uint32T + } + Timer5 struct { + Val c.Uint32T + } + Timer6 struct { + Val c.Uint32T + } + AnaConf struct { + Val c.Uint32T + } + ResetState struct { + Val c.Uint32T + } + WakeupState struct { + Val c.Uint32T + } + IntEna struct { + Val c.Uint32T + } + IntRaw struct { + Val c.Uint32T + } + IntSt struct { + Val c.Uint32T + } + IntClr struct { + Val c.Uint32T + } + Store [4]c.Uint32T + ExtXtlConf struct { + Val c.Uint32T + } + ExtWakeupConf struct { + Val c.Uint32T + } + SlpRejectConf struct { + Val c.Uint32T + } + CpuPeriodConf struct { + Val c.Uint32T + } + SdioActConf struct { + Val c.Uint32T + } + ClkConf struct { + Val c.Uint32T + } + SlowClkConf struct { + Val c.Uint32T + } + SdioConf struct { + Val c.Uint32T + } + BiasConf struct { + Val c.Uint32T + } + Rtc struct { + Val c.Uint32T + } + Pwc struct { + Val c.Uint32T + } + RegulatorDrvCtrl struct { + Val c.Uint32T + } + DigPwc struct { + Val c.Uint32T + } + DigIso struct { + Val c.Uint32T + } + WdtConfig0 struct { + Val c.Uint32T + } + WdtConfig1 c.Uint32T + WdtConfig2 c.Uint32T + WdtConfig3 c.Uint32T + WdtConfig4 c.Uint32T + WdtFeed struct { + Val c.Uint32T + } + WdtWprotect c.Uint32T + SwdConf struct { + Val c.Uint32T + } + SwdWprotect c.Uint32T + SwCpuStall struct { + Val c.Uint32T + } + Store4 c.Uint32T + Store5 c.Uint32T + Store6 c.Uint32T + Store7 c.Uint32T + LowPowerSt struct { + Val c.Uint32T + } + Diag0 c.Uint32T + PadHold struct { + Val c.Uint32T + } + DigPadHold c.Uint32T + ExtWakeup1 struct { + Val c.Uint32T + } + ExtWakeup1Status struct { + Val c.Uint32T + } + BrownOut struct { + Val c.Uint32T + } + TimeLow1 c.Uint32T + TimeHigh1 struct { + Val c.Uint32T + } + Xtal32kClkFactor c.Uint32T + Xtal32kConf struct { + Val c.Uint32T + } + UlpCpTimer struct { + Val c.Uint32T + } + UlpCpCtrl struct { + Val c.Uint32T + } + CocpuCtrl struct { + Val c.Uint32T + } + TouchCtrl1 struct { + Val c.Uint32T + } + TouchCtrl2 struct { + Val c.Uint32T + } + TouchScanCtrl struct { + Val c.Uint32T + } + TouchSlpThres struct { + Val c.Uint32T + } + TouchApproach struct { + Val c.Uint32T + } + TouchFilterCtrl struct { + Val c.Uint32T + } + UsbConf struct { + Val c.Uint32T + } + TouchTimeoutCtrl struct { + Val c.Uint32T + } + SlpRejectCause struct { + Val c.Uint32T + } + Option1 struct { + Val c.Uint32T + } + SlpWakeupCause struct { + Val c.Uint32T + } + UlpCpTimer1 struct { + Val c.Uint32T + } + IntEnaW1ts struct { + Val c.Uint32T + } + IntEnaW1tc struct { + Val c.Uint32T + } + RetentionCtrl struct { + Val c.Uint32T + } + PgCtrl struct { + Val c.Uint32T + } + FibSel struct { + Val c.Uint32T + } + TouchDac struct { + Val c.Uint32T + } + TouchDac1 struct { + Val c.Uint32T + } + CocpuDisable struct { + Val c.Uint32T + } + Reserved158 c.Uint32T + Reserved15c c.Uint32T + Reserved160 c.Uint32T + Reserved164 c.Uint32T + Reserved168 c.Uint32T + Reserved16c c.Uint32T + Reserved170 c.Uint32T + Reserved174 c.Uint32T + Reserved178 c.Uint32T + Reserved17c c.Uint32T + Reserved180 c.Uint32T + Reserved184 c.Uint32T + Reserved188 c.Uint32T + Reserved18c c.Uint32T + Reserved190 c.Uint32T + Reserved194 c.Uint32T + Reserved198 c.Uint32T + Reserved19c c.Uint32T + Reserved1a0 c.Uint32T + Reserved1a4 c.Uint32T + Reserved1a8 c.Uint32T + Reserved1ac c.Uint32T + Reserved1b0 c.Uint32T + Reserved1b4 c.Uint32T + Reserved1b8 c.Uint32T + Reserved1bc c.Uint32T + Reserved1c0 c.Uint32T + Reserved1c4 c.Uint32T + Reserved1c8 c.Uint32T + Reserved1cc c.Uint32T + Reserved1d0 c.Uint32T + Reserved1d4 c.Uint32T + Reserved1d8 c.Uint32T + Reserved1dc c.Uint32T + Reserved1e0 c.Uint32T + Reserved1e4 c.Uint32T + Reserved1e8 c.Uint32T + Reserved1ec c.Uint32T + Reserved1f0 c.Uint32T + Reserved1f4 c.Uint32T + Reserved1f8 c.Uint32T + Date struct { + Val c.Uint32T + } +} +type RtcCntlDevT RtcCntlDevS diff --git a/esp32/rtc_ctrl.go b/esp32/rtc_ctrl.go new file mode 100644 index 00000000..c8d06a75 --- /dev/null +++ b/esp32/rtc_ctrl.go @@ -0,0 +1,61 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Register a handler for specific RTC_CNTL interrupts + * + * Multiple handlers can be registered using this function. Whenever an + * RTC interrupt happens, all handlers with matching rtc_intr_mask values + * will be called. + * + * @param handler handler function to call + * @param handler_arg argument to be passed to the handler + * @param rtc_intr_mask combination of RTC_CNTL_*_INT_ENA bits indicating the + * sources to call the handler for + * @param flags An ORred mask of the RTC_INTR_FLAG_* defines. You can pass different + * flags to it to realize different purpose. If 0, the interrupt will + * not handle anything special. If you pass `RTC_INTR_FLAG_IRAM`, means + * the interrupt can be triggered with cache disabled. + * @return + * - ESP_OK on success + * - ESP_ERR_NO_MEM not enough memory to allocate handler structure + * - other errors returned by esp_intr_alloc + */ +//go:linkname RtcIsrRegister C.rtc_isr_register +func RtcIsrRegister(handler IntrHandlerT, handler_arg c.Pointer, rtc_intr_mask c.Uint32T, flags c.Uint32T) EspErrT + +/** + * @brief Deregister the handler previously registered using rtc_isr_register + * @param handler handler function to call (as passed to rtc_isr_register) + * @param handler_arg argument of the handler (as passed to rtc_isr_register) + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_STATE if a handler matching both handler and + * handler_arg isn't registered + */ +//go:linkname RtcIsrDeregister C.rtc_isr_deregister +func RtcIsrDeregister(handler IntrHandlerT, handler_arg c.Pointer) EspErrT + +/** + * @brief Disable the RTC interrupt that is allowed to be executed when cache is disabled. + * cache disabled. Internal interrupt handle function will call this function in interrupt + * handler function. Disable bits when `esp_intr_noniram_disable` is called. + * + * @param cpu CPU number. + */ +//go:linkname RtcIsrNoniramDisable C.rtc_isr_noniram_disable +func RtcIsrNoniramDisable(cpu c.Uint32T) + +/** + * @brief Enable the RTC interrupt that is allowed to be executed when cache is disabled. + * cache disabled. Internal interrupt handle function will call this function in interrupt + * handler function. Enable bits when `esp_intr_noniram_enable` is called. + * + * @param cpu CPU number. + */ +//go:linkname RtcIsrNoniramEnable C.rtc_isr_noniram_enable +func RtcIsrNoniramEnable(cpu c.Uint32T) diff --git a/esp32/rtc_hal.go b/esp32/rtc_hal.go new file mode 100644 index 00000000..584b94e7 --- /dev/null +++ b/esp32/rtc_hal.go @@ -0,0 +1,44 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type RtcCntlSleepCacheTagRetent struct { + LinkAddr c.Pointer + Icache struct { + StartPoint c.Uint32T + VldSize c.Uint32T + Size c.Uint32T + Enable c.Uint32T + } + Dcache struct { + StartPoint c.Uint32T + VldSize c.Uint32T + Size c.Uint32T + Enable c.Uint32T + } +} +type RtcCntlSleepCacheTagRetentT RtcCntlSleepCacheTagRetent + +type RtcCntlSleepRetent struct { + CpuPdMem c.Pointer + Tagmem RtcCntlSleepCacheTagRetentT +} +type RtcCntlSleepRetentT RtcCntlSleepRetent + +//go:linkname RtcCntlHalDmaLinkInit C.rtc_cntl_hal_dma_link_init +func RtcCntlHalDmaLinkInit(elem c.Pointer, buff c.Pointer, size c.Int, next c.Pointer) c.Pointer + +//go:linkname RtcCntlHalEnableCpuRetention C.rtc_cntl_hal_enable_cpu_retention +func RtcCntlHalEnableCpuRetention(addr c.Pointer) + +//go:linkname RtcCntlHalDisableCpuRetention C.rtc_cntl_hal_disable_cpu_retention +func RtcCntlHalDisableCpuRetention(addr c.Pointer) + +//go:linkname RtcCntlHalEnableTagmemRetention C.rtc_cntl_hal_enable_tagmem_retention +func RtcCntlHalEnableTagmemRetention(addr c.Pointer) + +//go:linkname RtcCntlHalDisableTagmemRetention C.rtc_cntl_hal_disable_tagmem_retention +func RtcCntlHalDisableTagmemRetention(addr c.Pointer) diff --git a/esp32/rtc_i2c_reg.go b/esp32/rtc_i2c_reg.go new file mode 100644 index 00000000..3e62dd9f --- /dev/null +++ b/esp32/rtc_i2c_reg.go @@ -0,0 +1,103 @@ +package freertos + +import _ "unsafe" + +const RTC_I2C_SCL_LOW_PERIOD_REG_S = 0 +const RTC_I2C_SDA_FORCE_OUT_S = 0 +const RTC_I2C_SCL_FORCE_OUT_S = 1 +const RTC_I2C_MS_MODE_S = 2 +const RTC_I2C_TRANS_START_S = 3 +const RTC_I2C_TX_LSB_FIRST_S = 4 +const RTC_I2C_RX_LSB_FIRST_S = 5 +const RTC_I2C_I2C_CTRL_CLK_GATE_EN_S = 29 +const RTC_I2C_I2C_RESET_S = 30 +const RTC_I2C_I2CCLK_EN_S = 31 +const RTC_I2C_ACK_REC_S = 0 +const RTC_I2C_SLAVE_RW_S = 1 +const RTC_I2C_ARB_LOST_S = 2 +const RTC_I2C_BUS_BUSY_S = 3 +const RTC_I2C_SLAVE_ADDRESSED_S = 4 +const RTC_I2C_BYTE_TRANS_S = 5 +const RTC_I2C_OP_CNT_S = 6 +const RTC_I2C_SHIFT_REG_S = 16 +const RTC_I2C_SCL_MAIN_STATE_LAST_S = 24 +const RTC_I2C_SCL_STATE_LAST_S = 28 +const RTC_I2C_TIME_OUT_REG_S = 0 +const RTC_I2C_SLAVE_ADDR_S = 0 +const RTC_I2C_ADDR_10BIT_EN_S = 31 +const RTC_I2C_SCL_HIGH_PERIOD_REG_S = 0 +const RTC_I2C_SDA_DUTY_NUM_S = 0 +const RTC_I2C_SCL_START_PERIOD_S = 0 +const RTC_I2C_SCL_STOP_PERIOD_S = 0 +const RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S = 0 +const RTC_I2C_ARBITRATION_LOST_INT_CLR_S = 1 +const RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S = 2 +const RTC_I2C_TRANS_COMPLETE_INT_CLR_S = 3 +const RTC_I2C_TIME_OUT_INT_CLR_S = 4 +const RTC_I2C_ACK_ERR_INT_CLR_S = 5 +const RTC_I2C_RX_DATA_INT_CLR_S = 6 +const RTC_I2C_TX_DATA_INT_CLR_S = 7 +const RTC_I2C_DETECT_START_INT_CLR_S = 8 +const RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S = 0 +const RTC_I2C_ARBITRATION_LOST_INT_RAW_S = 1 +const RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S = 2 +const RTC_I2C_TRANS_COMPLETE_INT_RAW_S = 3 +const RTC_I2C_TIME_OUT_INT_RAW_S = 4 +const RTC_I2C_ACK_ERR_INT_RAW_S = 5 +const RTC_I2C_RX_DATA_INT_RAW_S = 6 +const RTC_I2C_TX_DATA_INT_RAW_S = 7 +const RTC_I2C_DETECT_START_INT_RAW_S = 8 +const RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S = 0 +const RTC_I2C_ARBITRATION_LOST_INT_ST_S = 1 +const RTC_I2C_MASTER_TRAN_COMP_INT_ST_S = 2 +const RTC_I2C_TRANS_COMPLETE_INT_ST_S = 3 +const RTC_I2C_TIME_OUT_INT_ST_S = 4 +const RTC_I2C_ACK_ERR_INT_ST_S = 5 +const RTC_I2C_RX_DATA_INT_ST_S = 6 +const RTC_I2C_TX_DATA_INT_ST_S = 7 +const RTC_I2C_DETECT_START_INT_ST_S = 8 +const RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S = 0 +const RTC_I2C_ARBITRATION_LOST_INT_ENA_S = 1 +const RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S = 2 +const RTC_I2C_TRANS_COMPLETE_INT_ENA_S = 3 +const RTC_I2C_TIME_OUT_INT_ENA_S = 4 +const RTC_I2C_ACK_ERR_INT_ENA_S = 5 +const RTC_I2C_RX_DATA_INT_ENA_S = 6 +const RTC_I2C_TX_DATA_INT_ENA_S = 7 +const RTC_I2C_DETECT_START_INT_ENA_S = 8 +const RTC_I2C_I2C_RDATA_S = 0 +const RTC_I2C_SLAVE_TX_DATA_S = 8 +const RTC_I2C_I2C_DONE_S = 31 +const RTC_I2C_COMMAND0_S = 0 +const RTC_I2C_COMMAND0_DONE_S = 31 +const RTC_I2C_COMMAND1_S = 0 +const RTC_I2C_COMMAND1_DONE_S = 31 +const RTC_I2C_COMMAND2_S = 0 +const RTC_I2C_COMMAND2_DONE_S = 31 +const RTC_I2C_COMMAND3_S = 0 +const RTC_I2C_COMMAND3_DONE_S = 31 +const RTC_I2C_COMMAND4_S = 0 +const RTC_I2C_COMMAND4_DONE_S = 31 +const RTC_I2C_COMMAND5_S = 0 +const RTC_I2C_COMMAND5_DONE_S = 31 +const RTC_I2C_COMMAND6_S = 0 +const RTC_I2C_COMMAND6_DONE_S = 31 +const RTC_I2C_COMMAND7_S = 0 +const RTC_I2C_COMMAND7_DONE_S = 31 +const RTC_I2C_COMMAND8_S = 0 +const RTC_I2C_COMMAND8_DONE_S = 31 +const RTC_I2C_COMMAND9_S = 0 +const RTC_I2C_COMMAND9_DONE_S = 31 +const RTC_I2C_COMMAND10_S = 0 +const RTC_I2C_COMMAND10_DONE_S = 31 +const RTC_I2C_COMMAND11_S = 0 +const RTC_I2C_COMMAND11_DONE_S = 31 +const RTC_I2C_COMMAND12_S = 0 +const RTC_I2C_COMMAND12_DONE_S = 31 +const RTC_I2C_COMMAND13_S = 0 +const RTC_I2C_COMMAND13_DONE_S = 31 +const RTC_I2C_COMMAND14_S = 0 +const RTC_I2C_COMMAND14_DONE_S = 31 +const RTC_I2C_COMMAND15_S = 0 +const RTC_I2C_COMMAND15_DONE_S = 31 +const RTC_I2C_I2C_DATE_S = 0 diff --git a/esp32/rtc_i2c_struct.go b/esp32/rtc_i2c_struct.go new file mode 100644 index 00000000..f0af9db6 --- /dev/null +++ b/esp32/rtc_i2c_struct.go @@ -0,0 +1,158 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** Group: Configure Registers */ +/** Type of i2c_scl_low register + * configure low scl period + */ + +type RtcI2cSclLowRegT struct { + Val c.Uint32T +} + +/** Type of i2c_ctrl register + * configure i2c ctrl + */ + +type RtcI2cCtrlRegT struct { + Val c.Uint32T +} + +/** Type of i2c_to register + * configure time out + */ + +type RtcI2cToRegT struct { + Val c.Uint32T +} + +/** Type of i2c_slave_addr register + * configure slave id + */ + +type RtcI2cSlaveAddrRegT struct { + Val c.Uint32T +} + +/** Type of i2c_scl_high register + * configure high scl period + */ + +type RtcI2cSclHighRegT struct { + Val c.Uint32T +} + +/** Type of i2c_sda_duty register + * configure sda duty + */ + +type RtcI2cSdaDutyRegT struct { + Val c.Uint32T +} + +/** Type of i2c_scl_start_period register + * configure scl start period + */ + +type RtcI2cSclStartPeriodRegT struct { + Val c.Uint32T +} + +/** Type of i2c_scl_stop_period register + * configure scl stop period + */ + +type RtcI2cSclStopPeriodRegT struct { + Val c.Uint32T +} + +/** Type of i2c_data register + * get i2c data status + */ + +type RtcI2cDataRegT struct { + Val c.Uint32T +} + +/** Type of i2c_cmd register + * i2c command register + */ + +type RtcI2cCmdRegT struct { + Val c.Uint32T +} + +/** Group: status register */ +/** Type of i2c_status register + * get i2c status + */ + +type RtcI2cStatusRegT struct { + Val c.Uint32T +} + +/** Group: interrupt Register */ +/** Type of i2c_int_clr register + * interrupt clear register + */ + +type RtcI2cIntClrRegT struct { + Val c.Uint32T +} + +/** Type of i2c_int_raw register + * interrupt raw register + */ + +type RtcI2cIntRawRegT struct { + Val c.Uint32T +} + +/** Type of i2c_int_st register + * interrupt state register + */ + +type RtcI2cIntStRegT struct { + Val c.Uint32T +} + +/** Type of i2c_int_ena register + * interrupt enable register + */ + +type RtcI2cIntEnaRegT struct { + Val c.Uint32T +} + +/** Group: version Registers */ +/** Type of i2c_date register + * version register + */ + +type RtcI2cDateRegT struct { + Val c.Uint32T +} + +type RtcI2cDevT struct { + I2cSclLow RtcI2cSclLowRegT + I2cCtrl RtcI2cCtrlRegT + I2cStatus RtcI2cStatusRegT + I2cTo RtcI2cToRegT + I2cSlaveAddr RtcI2cSlaveAddrRegT + I2cSclHigh RtcI2cSclHighRegT + I2cSdaDuty RtcI2cSdaDutyRegT + I2cSclStartPeriod RtcI2cSclStartPeriodRegT + I2cSclStopPeriod RtcI2cSclStopPeriodRegT + I2cIntClr RtcI2cIntClrRegT + I2cIntRaw RtcI2cIntRawRegT + I2cIntSt RtcI2cIntStRegT + I2cIntEna RtcI2cIntEnaRegT + I2cData RtcI2cDataRegT + I2cCmd [16]RtcI2cCmdRegT + Reserved078 [33]c.Uint32T + I2cDate RtcI2cDateRegT +} diff --git a/esp32/rtc_io_channel.go b/esp32/rtc_io_channel.go new file mode 100644 index 00000000..8506b6bf --- /dev/null +++ b/esp32/rtc_io_channel.go @@ -0,0 +1,48 @@ +package freertos + +import _ "unsafe" + +const RTCIO_GPIO0_CHANNEL = 0 +const RTCIO_CHANNEL_0_GPIO_NUM = 0 +const RTCIO_GPIO1_CHANNEL = 1 +const RTCIO_CHANNEL_1_GPIO_NUM = 1 +const RTCIO_GPIO2_CHANNEL = 2 +const RTCIO_CHANNEL_2_GPIO_NUM = 2 +const RTCIO_GPIO3_CHANNEL = 3 +const RTCIO_CHANNEL_3_GPIO_NUM = 3 +const RTCIO_GPIO4_CHANNEL = 4 +const RTCIO_CHANNEL_4_GPIO_NUM = 4 +const RTCIO_GPIO5_CHANNEL = 5 +const RTCIO_CHANNEL_5_GPIO_NUM = 5 +const RTCIO_GPIO6_CHANNEL = 6 +const RTCIO_CHANNEL_6_GPIO_NUM = 6 +const RTCIO_GPIO7_CHANNEL = 7 +const RTCIO_CHANNEL_7_GPIO_NUM = 7 +const RTCIO_GPIO8_CHANNEL = 8 +const RTCIO_CHANNEL_8_GPIO_NUM = 8 +const RTCIO_GPIO9_CHANNEL = 9 +const RTCIO_CHANNEL_9_GPIO_NUM = 9 +const RTCIO_GPIO10_CHANNEL = 10 +const RTCIO_CHANNEL_10_GPIO_NUM = 10 +const RTCIO_GPIO11_CHANNEL = 11 +const RTCIO_CHANNEL_11_GPIO_NUM = 11 +const RTCIO_GPIO12_CHANNEL = 12 +const RTCIO_CHANNEL_12_GPIO_NUM = 12 +const RTCIO_GPIO13_CHANNEL = 13 +const RTCIO_CHANNEL_13_GPIO_NUM = 13 +const RTCIO_GPIO14_CHANNEL = 14 +const RTCIO_CHANNEL_14_GPIO_NUM = 14 +const RTCIO_GPIO15_CHANNEL = 15 +const RTCIO_CHANNEL_15_GPIO_NUM = 15 +const RTCIO_GPIO16_CHANNEL = 16 +const RTCIO_CHANNEL_16_GPIO_NUM = 16 +const RTCIO_GPIO17_CHANNEL = 17 +const RTCIO_CHANNEL_17_GPIO_NUM = 17 +const RTCIO_GPIO18_CHANNEL = 18 +const RTCIO_CHANNEL_18_GPIO_NUM = 18 +const RTCIO_GPIO19_CHANNEL = 19 +const RTCIO_CHANNEL_19_GPIO_NUM = 19 +const RTCIO_GPIO20_CHANNEL = 20 +const RTCIO_CHANNEL_20_GPIO_NUM = 20 +const RTCIO_GPIO21_CHANNEL = 21 +const RTCIO_CHANNEL_21_GPIO_NUM = 21 diff --git a/esp32/rtc_io_hal.go b/esp32/rtc_io_hal.go new file mode 100644 index 00000000..73cb1cb6 --- /dev/null +++ b/esp32/rtc_io_hal.go @@ -0,0 +1,46 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Set RTC IO direction. + * + * Configure RTC IO direction, such as output only, input only, + * output and input. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT. + * @param mode IO direction. + */ +//go:linkname RtcioHalSetDirection C.rtcio_hal_set_direction +func RtcioHalSetDirection(rtcio_num c.Int, mode RtcGpioModeT) + +/** + * Set RTC IO direction in deep sleep or disable sleep status. + * + * NOTE: ESP32 supports INPUT_ONLY mode. + * The rest targets support INPUT_ONLY, OUTPUT_ONLY, INPUT_OUTPUT mode. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT. + * @param mode IO direction. + */ +//go:linkname RtcioHalSetDirectionInSleep C.rtcio_hal_set_direction_in_sleep +func RtcioHalSetDirectionInSleep(rtcio_num c.Int, mode RtcGpioModeT) + +/** + * Helper function to disconnect internal circuits from an RTC IO + * This function disables input, output, pullup, pulldown, and enables + * hold feature for an RTC IO. + * Use this function if an RTC IO needs to be disconnected from internal + * circuits in deep sleep, to minimize leakage current. + * + * In particular, for ESP32-WROVER module, call + * rtc_gpio_isolate(GPIO_NUM_12) before entering deep sleep, to reduce + * deep sleep current. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT. + */ +//go:linkname RtcioHalIsolate C.rtcio_hal_isolate +func RtcioHalIsolate(rtc_num c.Int) diff --git a/esp32/rtc_io_ll.go b/esp32/rtc_io_ll.go new file mode 100644 index 00000000..259e6906 --- /dev/null +++ b/esp32/rtc_io_ll.go @@ -0,0 +1,30 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const RTCIO_LL_PIN_FUNC = 0 + +type RtcioLlFuncT c.Int + +const ( + RTCIO_LL_FUNC_RTC RtcioLlFuncT = 0 + RTCIO_LL_FUNC_DIGITAL RtcioLlFuncT = 1 +) + +type RtcioLlWakeTypeT c.Int + +const ( + RTCIO_LL_WAKEUP_DISABLE RtcioLlWakeTypeT = 0 + RTCIO_LL_WAKEUP_LOW_LEVEL RtcioLlWakeTypeT = 4 + RTCIO_LL_WAKEUP_HIGH_LEVEL RtcioLlWakeTypeT = 5 +) + +type RtcioLlOutModeT c.Int + +const ( + RTCIO_LL_OUTPUT_NORMAL RtcioLlOutModeT = 0 + RTCIO_LL_OUTPUT_OD RtcioLlOutModeT = 1 +) diff --git a/esp32/rtc_io_periph.go b/esp32/rtc_io_periph.go new file mode 100644 index 00000000..347afbcc --- /dev/null +++ b/esp32/rtc_io_periph.go @@ -0,0 +1,30 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Pin function information for a single RTCIO pad's. + * + * This is an internal function of the driver, and is not usually useful + * for external use. + */ + +type RtcIoDescT struct { + Reg c.Uint32T + Mux c.Uint32T + Func c.Uint32T + Ie c.Uint32T + Pullup c.Uint32T + Pulldown c.Uint32T + Slpsel c.Uint32T + Slpie c.Uint32T + Slpoe c.Uint32T + Hold c.Uint32T + HoldForce c.Uint32T + DrvV c.Uint32T + DrvS c.Uint32T + RtcNum c.Int +} diff --git a/esp32/rtc_io_reg.go b/esp32/rtc_io_reg.go new file mode 100644 index 00000000..d0bf27ad --- /dev/null +++ b/esp32/rtc_io_reg.go @@ -0,0 +1,772 @@ +package freertos + +import _ "unsafe" + +const RTC_GPIO_OUT_DATA = 0x003FFFFF +const RTC_GPIO_OUT_DATA_V = 0x3FFFFF +const RTC_GPIO_OUT_DATA_S = 10 +const RTC_GPIO_OUT_DATA_W1TS = 0x003FFFFF +const RTC_GPIO_OUT_DATA_W1TS_V = 0x3FFFFF +const RTC_GPIO_OUT_DATA_W1TS_S = 10 +const RTC_GPIO_OUT_DATA_W1TC = 0x003FFFFF +const RTC_GPIO_OUT_DATA_W1TC_V = 0x3FFFFF +const RTC_GPIO_OUT_DATA_W1TC_S = 10 +const RTC_GPIO_ENABLE = 0x003FFFFF +const RTC_GPIO_ENABLE_V = 0x3FFFFF +const RTC_GPIO_ENABLE_S = 10 +const RTC_GPIO_ENABLE_W1TS = 0x003FFFFF +const RTC_GPIO_ENABLE_W1TS_V = 0x3FFFFF +const RTC_GPIO_ENABLE_W1TS_S = 10 +const RTC_GPIO_ENABLE_W1TC = 0x003FFFFF +const RTC_GPIO_ENABLE_W1TC_V = 0x3FFFFF +const RTC_GPIO_ENABLE_W1TC_S = 10 +const RTC_GPIO_STATUS_INT = 0x003FFFFF +const RTC_GPIO_STATUS_INT_V = 0x3FFFFF +const RTC_GPIO_STATUS_INT_S = 10 +const RTC_GPIO_STATUS_INT_W1TS = 0x003FFFFF +const RTC_GPIO_STATUS_INT_W1TS_V = 0x3FFFFF +const RTC_GPIO_STATUS_INT_W1TS_S = 10 +const RTC_GPIO_STATUS_INT_W1TC = 0x003FFFFF +const RTC_GPIO_STATUS_INT_W1TC_V = 0x3FFFFF +const RTC_GPIO_STATUS_INT_W1TC_S = 10 +const RTC_GPIO_IN_NEXT = 0x003FFFFF +const RTC_GPIO_IN_NEXT_V = 0x3FFFFF +const RTC_GPIO_IN_NEXT_S = 10 +const RTC_GPIO_PIN0_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN0_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN0_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN0_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN0_INT_TYPE_S = 7 +const RTC_GPIO_PIN0_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN0_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN1_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN1_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN1_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN1_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN1_INT_TYPE_S = 7 +const RTC_GPIO_PIN1_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN1_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN2_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN2_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN2_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN2_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN2_INT_TYPE_S = 7 +const RTC_GPIO_PIN2_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN2_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN3_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN3_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN3_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN3_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN3_INT_TYPE_S = 7 +const RTC_GPIO_PIN3_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN3_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN4_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN4_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN4_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN4_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN4_INT_TYPE_S = 7 +const RTC_GPIO_PIN4_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN4_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN5_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN5_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN5_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN5_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN5_INT_TYPE_S = 7 +const RTC_GPIO_PIN5_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN5_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN6_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN6_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN6_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN6_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN6_INT_TYPE_S = 7 +const RTC_GPIO_PIN6_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN6_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN7_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN7_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN7_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN7_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN7_INT_TYPE_S = 7 +const RTC_GPIO_PIN7_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN7_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN8_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN8_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN8_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN8_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN8_INT_TYPE_S = 7 +const RTC_GPIO_PIN8_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN8_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN9_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN9_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN9_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN9_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN9_INT_TYPE_S = 7 +const RTC_GPIO_PIN9_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN9_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN10_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN10_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN10_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN10_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN10_INT_TYPE_S = 7 +const RTC_GPIO_PIN10_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN10_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN11_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN11_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN11_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN11_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN11_INT_TYPE_S = 7 +const RTC_GPIO_PIN11_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN11_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN12_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN12_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN12_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN12_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN12_INT_TYPE_S = 7 +const RTC_GPIO_PIN12_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN12_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN13_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN13_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN13_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN13_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN13_INT_TYPE_S = 7 +const RTC_GPIO_PIN13_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN13_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN14_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN14_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN14_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN14_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN14_INT_TYPE_S = 7 +const RTC_GPIO_PIN14_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN14_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN15_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN15_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN15_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN15_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN15_INT_TYPE_S = 7 +const RTC_GPIO_PIN15_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN15_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN16_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN16_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN16_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN16_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN16_INT_TYPE_S = 7 +const RTC_GPIO_PIN16_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN16_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN17_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN17_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN17_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN17_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN17_INT_TYPE_S = 7 +const RTC_GPIO_PIN17_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN17_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN18_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN18_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN18_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN18_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN18_INT_TYPE_S = 7 +const RTC_GPIO_PIN18_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN18_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN19_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN19_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN19_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN19_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN19_INT_TYPE_S = 7 +const RTC_GPIO_PIN19_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN19_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN20_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN20_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN20_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN20_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN20_INT_TYPE_S = 7 +const RTC_GPIO_PIN20_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN20_PAD_DRIVER_S = 2 +const RTC_GPIO_PIN21_WAKEUP_ENABLE_V = 0x1 +const RTC_GPIO_PIN21_WAKEUP_ENABLE_S = 10 +const RTC_GPIO_PIN21_INT_TYPE = 0x00000007 +const RTC_GPIO_PIN21_INT_TYPE_V = 0x7 +const RTC_GPIO_PIN21_INT_TYPE_S = 7 +const RTC_GPIO_PIN21_PAD_DRIVER_V = 0x1 +const RTC_GPIO_PIN21_PAD_DRIVER_S = 2 +const RTC_IO_DEBUG_12M_NO_GATING_V = 0x1 +const RTC_IO_DEBUG_12M_NO_GATING_S = 25 +const RTC_IO_DEBUG_SEL4 = 0x0000001F +const RTC_IO_DEBUG_SEL4_V = 0x1F +const RTC_IO_DEBUG_SEL4_S = 20 +const RTC_IO_DEBUG_SEL3 = 0x0000001F +const RTC_IO_DEBUG_SEL3_V = 0x1F +const RTC_IO_DEBUG_SEL3_S = 15 +const RTC_IO_DEBUG_SEL2 = 0x0000001F +const RTC_IO_DEBUG_SEL2_V = 0x1F +const RTC_IO_DEBUG_SEL2_S = 10 +const RTC_IO_DEBUG_SEL1 = 0x0000001F +const RTC_IO_DEBUG_SEL1_V = 0x1F +const RTC_IO_DEBUG_SEL1_S = 5 +const RTC_IO_DEBUG_SEL0 = 0x0000001F +const RTC_IO_DEBUG_SEL0_V = 0x1F +const RTC_IO_DEBUG_SEL0_S = 0 +const RTC_IO_TOUCH_PAD0_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD0_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD0_DRV_S = 29 +const RTC_IO_TOUCH_PAD0_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD0_RDE_S = 28 +const RTC_IO_TOUCH_PAD0_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD0_RUE_S = 27 +const RTC_IO_TOUCH_PAD0_START_V = 0x1 +const RTC_IO_TOUCH_PAD0_START_S = 22 +const RTC_IO_TOUCH_PAD0_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD0_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD0_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD0_XPD_S = 20 +const RTC_IO_TOUCH_PAD0_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD0_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD0_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD0_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD0_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD0_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD0_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD0_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD0_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD0_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD0_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD0_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD0_FUN_IE_S = 13 +const RTC_IO_TOUCH_PAD1_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD1_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD1_DRV_S = 29 +const RTC_IO_TOUCH_PAD1_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD1_RDE_S = 28 +const RTC_IO_TOUCH_PAD1_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD1_RUE_S = 27 +const RTC_IO_TOUCH_PAD1_START_V = 0x1 +const RTC_IO_TOUCH_PAD1_START_S = 22 +const RTC_IO_TOUCH_PAD1_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD1_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD1_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD1_XPD_S = 20 +const RTC_IO_TOUCH_PAD1_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD1_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD1_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD1_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD1_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD1_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD1_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD1_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD1_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD1_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD1_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD1_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD1_FUN_IE_S = 13 +const RTC_IO_TOUCH_PAD2_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD2_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD2_DRV_S = 29 +const RTC_IO_TOUCH_PAD2_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD2_RDE_S = 28 +const RTC_IO_TOUCH_PAD2_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD2_RUE_S = 27 +const RTC_IO_TOUCH_PAD2_START_V = 0x1 +const RTC_IO_TOUCH_PAD2_START_S = 22 +const RTC_IO_TOUCH_PAD2_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD2_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD2_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD2_XPD_S = 20 +const RTC_IO_TOUCH_PAD2_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD2_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD2_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD2_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD2_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD2_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD2_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD2_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD2_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD2_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD2_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD2_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD2_FUN_IE_S = 13 +const RTC_IO_TOUCH_PAD3_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD3_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD3_DRV_S = 29 +const RTC_IO_TOUCH_PAD3_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD3_RDE_S = 28 +const RTC_IO_TOUCH_PAD3_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD3_RUE_S = 27 +const RTC_IO_TOUCH_PAD3_START_V = 0x1 +const RTC_IO_TOUCH_PAD3_START_S = 22 +const RTC_IO_TOUCH_PAD3_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD3_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD3_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD3_XPD_S = 20 +const RTC_IO_TOUCH_PAD3_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD3_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD3_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD3_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD3_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD3_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD3_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD3_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD3_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD3_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD3_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD3_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD3_FUN_IE_S = 13 +const RTC_IO_TOUCH_PAD4_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD4_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD4_DRV_S = 29 +const RTC_IO_TOUCH_PAD4_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD4_RDE_S = 28 +const RTC_IO_TOUCH_PAD4_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD4_RUE_S = 27 +const RTC_IO_TOUCH_PAD4_START_V = 0x1 +const RTC_IO_TOUCH_PAD4_START_S = 22 +const RTC_IO_TOUCH_PAD4_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD4_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD4_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD4_XPD_S = 20 +const RTC_IO_TOUCH_PAD4_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD4_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD4_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD4_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD4_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD4_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD4_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD4_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD4_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD4_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD4_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD4_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD4_FUN_IE_S = 13 +const RTC_IO_TOUCH_PAD5_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD5_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD5_DRV_S = 29 +const RTC_IO_TOUCH_PAD5_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD5_RDE_S = 28 +const RTC_IO_TOUCH_PAD5_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD5_RUE_S = 27 +const RTC_IO_TOUCH_PAD5_START_V = 0x1 +const RTC_IO_TOUCH_PAD5_START_S = 22 +const RTC_IO_TOUCH_PAD5_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD5_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD5_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD5_XPD_S = 20 +const RTC_IO_TOUCH_PAD5_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD5_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD5_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD5_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD5_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD5_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD5_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD5_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD5_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD5_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD5_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD5_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD5_FUN_IE_S = 13 +const RTC_IO_TOUCH_PAD6_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD6_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD6_DRV_S = 29 +const RTC_IO_TOUCH_PAD6_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD6_RDE_S = 28 +const RTC_IO_TOUCH_PAD6_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD6_RUE_S = 27 +const RTC_IO_TOUCH_PAD6_START_V = 0x1 +const RTC_IO_TOUCH_PAD6_START_S = 22 +const RTC_IO_TOUCH_PAD6_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD6_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD6_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD6_XPD_S = 20 +const RTC_IO_TOUCH_PAD6_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD6_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD6_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD6_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD6_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD6_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD6_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD6_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD6_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD6_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD6_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD6_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD6_FUN_IE_S = 13 +const RTC_IO_TOUCH_PAD7_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD7_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD7_DRV_S = 29 +const RTC_IO_TOUCH_PAD7_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD7_RDE_S = 28 +const RTC_IO_TOUCH_PAD7_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD7_RUE_S = 27 +const RTC_IO_TOUCH_PAD7_START_V = 0x1 +const RTC_IO_TOUCH_PAD7_START_S = 22 +const RTC_IO_TOUCH_PAD7_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD7_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD7_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD7_XPD_S = 20 +const RTC_IO_TOUCH_PAD7_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD7_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD7_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD7_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD7_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD7_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD7_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD7_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD7_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD7_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD7_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD7_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD7_FUN_IE_S = 13 +const RTC_IO_TOUCH_PAD8_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD8_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD8_DRV_S = 29 +const RTC_IO_TOUCH_PAD8_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD8_RDE_S = 28 +const RTC_IO_TOUCH_PAD8_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD8_RUE_S = 27 +const RTC_IO_TOUCH_PAD8_START_V = 0x1 +const RTC_IO_TOUCH_PAD8_START_S = 22 +const RTC_IO_TOUCH_PAD8_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD8_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD8_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD8_XPD_S = 20 +const RTC_IO_TOUCH_PAD8_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD8_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD8_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD8_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD8_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD8_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD8_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD8_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD8_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD8_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD8_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD8_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD8_FUN_IE_S = 13 +const RTC_IO_TOUCH_PAD9_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD9_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD9_DRV_S = 29 +const RTC_IO_TOUCH_PAD9_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD9_RDE_S = 28 +const RTC_IO_TOUCH_PAD9_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD9_RUE_S = 27 +const RTC_IO_TOUCH_PAD9_START_V = 0x1 +const RTC_IO_TOUCH_PAD9_START_S = 22 +const RTC_IO_TOUCH_PAD9_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD9_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD9_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD9_XPD_S = 20 +const RTC_IO_TOUCH_PAD9_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD9_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD9_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD9_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD9_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD9_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD9_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD9_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD9_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD9_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD9_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD9_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD9_FUN_IE_S = 13 +const RTC_IO_TOUCH_PAD10_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD10_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD10_DRV_S = 29 +const RTC_IO_TOUCH_PAD10_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD10_RDE_S = 28 +const RTC_IO_TOUCH_PAD10_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD10_RUE_S = 27 +const RTC_IO_TOUCH_PAD10_START_V = 0x1 +const RTC_IO_TOUCH_PAD10_START_S = 22 +const RTC_IO_TOUCH_PAD10_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD10_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD10_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD10_XPD_S = 20 +const RTC_IO_TOUCH_PAD10_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD10_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD10_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD10_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD10_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD10_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD10_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD10_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD10_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD10_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD10_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD10_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD10_FUN_IE_S = 13 +const RTC_IO_TOUCH_PAD11_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD11_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD11_DRV_S = 29 +const RTC_IO_TOUCH_PAD11_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD11_RDE_S = 28 +const RTC_IO_TOUCH_PAD11_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD11_RUE_S = 27 +const RTC_IO_TOUCH_PAD11_START_V = 0x1 +const RTC_IO_TOUCH_PAD11_START_S = 22 +const RTC_IO_TOUCH_PAD11_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD11_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD11_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD11_XPD_S = 20 +const RTC_IO_TOUCH_PAD11_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD11_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD11_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD11_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD11_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD11_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD11_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD11_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD11_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD11_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD11_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD11_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD11_FUN_IE_S = 13 +const RTC_IO_TOUCH_PAD12_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD12_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD12_DRV_S = 29 +const RTC_IO_TOUCH_PAD12_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD12_RDE_S = 28 +const RTC_IO_TOUCH_PAD12_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD12_RUE_S = 27 +const RTC_IO_TOUCH_PAD12_START_V = 0x1 +const RTC_IO_TOUCH_PAD12_START_S = 22 +const RTC_IO_TOUCH_PAD12_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD12_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD12_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD12_XPD_S = 20 +const RTC_IO_TOUCH_PAD12_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD12_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD12_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD12_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD12_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD12_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD12_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD12_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD12_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD12_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD12_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD12_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD12_FUN_IE_S = 13 +const RTC_IO_TOUCH_PAD13_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD13_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD13_DRV_S = 29 +const RTC_IO_TOUCH_PAD13_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD13_RDE_S = 28 +const RTC_IO_TOUCH_PAD13_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD13_RUE_S = 27 +const RTC_IO_TOUCH_PAD13_START_V = 0x1 +const RTC_IO_TOUCH_PAD13_START_S = 22 +const RTC_IO_TOUCH_PAD13_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD13_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD13_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD13_XPD_S = 20 +const RTC_IO_TOUCH_PAD13_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD13_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD13_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD13_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD13_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD13_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD13_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD13_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD13_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD13_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD13_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD13_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD13_FUN_IE_S = 13 +const RTC_IO_TOUCH_PAD14_DRV = 0x00000003 +const RTC_IO_TOUCH_PAD14_DRV_V = 0x3 +const RTC_IO_TOUCH_PAD14_DRV_S = 29 +const RTC_IO_TOUCH_PAD14_RDE_V = 0x1 +const RTC_IO_TOUCH_PAD14_RDE_S = 28 +const RTC_IO_TOUCH_PAD14_RUE_V = 0x1 +const RTC_IO_TOUCH_PAD14_RUE_S = 27 +const RTC_IO_TOUCH_PAD14_START_V = 0x1 +const RTC_IO_TOUCH_PAD14_START_S = 22 +const RTC_IO_TOUCH_PAD14_TIE_OPT_V = 0x1 +const RTC_IO_TOUCH_PAD14_TIE_OPT_S = 21 +const RTC_IO_TOUCH_PAD14_XPD_V = 0x1 +const RTC_IO_TOUCH_PAD14_XPD_S = 20 +const RTC_IO_TOUCH_PAD14_MUX_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD14_MUX_SEL_S = 19 +const RTC_IO_TOUCH_PAD14_FUN_SEL = 0x00000003 +const RTC_IO_TOUCH_PAD14_FUN_SEL_V = 0x3 +const RTC_IO_TOUCH_PAD14_FUN_SEL_S = 17 +const RTC_IO_TOUCH_PAD14_SLP_SEL_V = 0x1 +const RTC_IO_TOUCH_PAD14_SLP_SEL_S = 16 +const RTC_IO_TOUCH_PAD14_SLP_IE_V = 0x1 +const RTC_IO_TOUCH_PAD14_SLP_IE_S = 15 +const RTC_IO_TOUCH_PAD14_SLP_OE_V = 0x1 +const RTC_IO_TOUCH_PAD14_SLP_OE_S = 14 +const RTC_IO_TOUCH_PAD14_FUN_IE_V = 0x1 +const RTC_IO_TOUCH_PAD14_FUN_IE_S = 13 +const RTC_IO_X32P_DRV = 0x00000003 +const RTC_IO_X32P_DRV_V = 0x3 +const RTC_IO_X32P_DRV_S = 29 +const RTC_IO_X32P_RDE_V = 0x1 +const RTC_IO_X32P_RDE_S = 28 +const RTC_IO_X32P_RUE_V = 0x1 +const RTC_IO_X32P_RUE_S = 27 +const RTC_IO_X32P_MUX_SEL_V = 0x1 +const RTC_IO_X32P_MUX_SEL_S = 19 +const RTC_IO_X32P_FUN_SEL = 0x00000003 +const RTC_IO_X32P_FUN_SEL_V = 0x3 +const RTC_IO_X32P_FUN_SEL_S = 17 +const RTC_IO_X32P_SLP_SEL_V = 0x1 +const RTC_IO_X32P_SLP_SEL_S = 16 +const RTC_IO_X32P_SLP_IE_V = 0x1 +const RTC_IO_X32P_SLP_IE_S = 15 +const RTC_IO_X32P_SLP_OE_V = 0x1 +const RTC_IO_X32P_SLP_OE_S = 14 +const RTC_IO_X32P_FUN_IE_V = 0x1 +const RTC_IO_X32P_FUN_IE_S = 13 +const RTC_IO_X32N_DRV = 0x00000003 +const RTC_IO_X32N_DRV_V = 0x3 +const RTC_IO_X32N_DRV_S = 29 +const RTC_IO_X32N_RDE_V = 0x1 +const RTC_IO_X32N_RDE_S = 28 +const RTC_IO_X32N_RUE_V = 0x1 +const RTC_IO_X32N_RUE_S = 27 +const RTC_IO_X32N_MUX_SEL_V = 0x1 +const RTC_IO_X32N_MUX_SEL_S = 19 +const RTC_IO_X32N_FUN_SEL = 0x00000003 +const RTC_IO_X32N_FUN_SEL_V = 0x3 +const RTC_IO_X32N_FUN_SEL_S = 17 +const RTC_IO_X32N_SLP_SEL_V = 0x1 +const RTC_IO_X32N_SLP_SEL_S = 16 +const RTC_IO_X32N_SLP_IE_V = 0x1 +const RTC_IO_X32N_SLP_IE_S = 15 +const RTC_IO_X32N_SLP_OE_V = 0x1 +const RTC_IO_X32N_SLP_OE_S = 14 +const RTC_IO_X32N_FUN_IE_V = 0x1 +const RTC_IO_X32N_FUN_IE_S = 13 +const RTC_IO_PDAC1_DRV = 0x00000003 +const RTC_IO_PDAC1_DRV_V = 0x3 +const RTC_IO_PDAC1_DRV_S = 29 +const RTC_IO_PDAC1_RDE_V = 0x1 +const RTC_IO_PDAC1_RDE_S = 28 +const RTC_IO_PDAC1_RUE_V = 0x1 +const RTC_IO_PDAC1_RUE_S = 27 +const RTC_IO_PDAC1_MUX_SEL_V = 0x1 +const RTC_IO_PDAC1_MUX_SEL_S = 19 +const RTC_IO_PDAC1_FUN_SEL = 0x00000003 +const RTC_IO_PDAC1_FUN_SEL_V = 0x3 +const RTC_IO_PDAC1_FUN_SEL_S = 17 +const RTC_IO_PDAC1_SLP_SEL_V = 0x1 +const RTC_IO_PDAC1_SLP_SEL_S = 16 +const RTC_IO_PDAC1_SLP_IE_V = 0x1 +const RTC_IO_PDAC1_SLP_IE_S = 15 +const RTC_IO_PDAC1_SLP_OE_V = 0x1 +const RTC_IO_PDAC1_SLP_OE_S = 14 +const RTC_IO_PDAC1_FUN_IE_V = 0x1 +const RTC_IO_PDAC1_FUN_IE_S = 13 +const RTC_IO_PDAC1_DAC_XPD_FORCE_V = 0x1 +const RTC_IO_PDAC1_DAC_XPD_FORCE_S = 12 +const RTC_IO_PDAC1_XPD_DAC_V = 0x1 +const RTC_IO_PDAC1_XPD_DAC_S = 11 +const RTC_IO_PDAC1_DAC = 0x000000FF +const RTC_IO_PDAC1_DAC_V = 0xFF +const RTC_IO_PDAC1_DAC_S = 3 +const RTC_IO_PDAC2_DRV = 0x00000003 +const RTC_IO_PDAC2_DRV_V = 0x3 +const RTC_IO_PDAC2_DRV_S = 29 +const RTC_IO_PDAC2_RDE_V = 0x1 +const RTC_IO_PDAC2_RDE_S = 28 +const RTC_IO_PDAC2_RUE_V = 0x1 +const RTC_IO_PDAC2_RUE_S = 27 +const RTC_IO_PDAC2_MUX_SEL_V = 0x1 +const RTC_IO_PDAC2_MUX_SEL_S = 19 +const RTC_IO_PDAC2_FUN_SEL = 0x00000003 +const RTC_IO_PDAC2_FUN_SEL_V = 0x3 +const RTC_IO_PDAC2_FUN_SEL_S = 17 +const RTC_IO_PDAC2_SLP_SEL_V = 0x1 +const RTC_IO_PDAC2_SLP_SEL_S = 16 +const RTC_IO_PDAC2_SLP_IE_V = 0x1 +const RTC_IO_PDAC2_SLP_IE_S = 15 +const RTC_IO_PDAC2_SLP_OE_V = 0x1 +const RTC_IO_PDAC2_SLP_OE_S = 14 +const RTC_IO_PDAC2_FUN_IE_V = 0x1 +const RTC_IO_PDAC2_FUN_IE_S = 13 +const RTC_IO_PDAC2_DAC_XPD_FORCE_V = 0x1 +const RTC_IO_PDAC2_DAC_XPD_FORCE_S = 12 +const RTC_IO_PDAC2_XPD_DAC_V = 0x1 +const RTC_IO_PDAC2_XPD_DAC_S = 11 +const RTC_IO_PDAC2_DAC = 0x000000FF +const RTC_IO_PDAC2_DAC_V = 0xFF +const RTC_IO_PDAC2_DAC_S = 3 +const RTC_IO_PAD19_DRV = 0x00000003 +const RTC_IO_PAD19_DRV_V = 0x3 +const RTC_IO_PAD19_DRV_S = 29 +const RTC_IO_PAD19_RDE_V = 0x1 +const RTC_IO_PAD19_RDE_S = 28 +const RTC_IO_PAD19_RUE_V = 0x1 +const RTC_IO_PAD19_RUE_S = 27 +const RTC_IO_PAD19_MUX_SEL_V = 0x1 +const RTC_IO_PAD19_MUX_SEL_S = 19 +const RTC_IO_PAD19_FUN_SEL = 0x00000003 +const RTC_IO_PAD19_FUN_SEL_V = 0x3 +const RTC_IO_PAD19_FUN_SEL_S = 17 +const RTC_IO_PAD19_SLP_SEL_V = 0x1 +const RTC_IO_PAD19_SLP_SEL_S = 16 +const RTC_IO_PAD19_SLP_IE_V = 0x1 +const RTC_IO_PAD19_SLP_IE_S = 15 +const RTC_IO_PAD19_SLP_OE_V = 0x1 +const RTC_IO_PAD19_SLP_OE_S = 14 +const RTC_IO_PAD19_FUN_IE_V = 0x1 +const RTC_IO_PAD19_FUN_IE_S = 13 +const RTC_IO_PAD20_DRV = 0x00000003 +const RTC_IO_PAD20_DRV_V = 0x3 +const RTC_IO_PAD20_DRV_S = 29 +const RTC_IO_PAD20_RDE_V = 0x1 +const RTC_IO_PAD20_RDE_S = 28 +const RTC_IO_PAD20_RUE_V = 0x1 +const RTC_IO_PAD20_RUE_S = 27 +const RTC_IO_PAD20_MUX_SEL_V = 0x1 +const RTC_IO_PAD20_MUX_SEL_S = 19 +const RTC_IO_PAD20_FUN_SEL = 0x00000003 +const RTC_IO_PAD20_FUN_SEL_V = 0x3 +const RTC_IO_PAD20_FUN_SEL_S = 17 +const RTC_IO_PAD20_SLP_SEL_V = 0x1 +const RTC_IO_PAD20_SLP_SEL_S = 16 +const RTC_IO_PAD20_SLP_IE_V = 0x1 +const RTC_IO_PAD20_SLP_IE_S = 15 +const RTC_IO_PAD20_SLP_OE_V = 0x1 +const RTC_IO_PAD20_SLP_OE_S = 14 +const RTC_IO_PAD20_FUN_IE_V = 0x1 +const RTC_IO_PAD20_FUN_IE_S = 13 +const RTC_IO_PAD21_DRV = 0x00000003 +const RTC_IO_PAD21_DRV_V = 0x3 +const RTC_IO_PAD21_DRV_S = 29 +const RTC_IO_PAD21_RDE_V = 0x1 +const RTC_IO_PAD21_RDE_S = 28 +const RTC_IO_PAD21_RUE_V = 0x1 +const RTC_IO_PAD21_RUE_S = 27 +const RTC_IO_PAD21_MUX_SEL_V = 0x1 +const RTC_IO_PAD21_MUX_SEL_S = 19 +const RTC_IO_PAD21_FUN_SEL = 0x00000003 +const RTC_IO_PAD21_FUN_SEL_V = 0x3 +const RTC_IO_PAD21_FUN_SEL_S = 17 +const RTC_IO_PAD21_SLP_SEL_V = 0x1 +const RTC_IO_PAD21_SLP_SEL_S = 16 +const RTC_IO_PAD21_SLP_IE_V = 0x1 +const RTC_IO_PAD21_SLP_IE_S = 15 +const RTC_IO_PAD21_SLP_OE_V = 0x1 +const RTC_IO_PAD21_SLP_OE_S = 14 +const RTC_IO_PAD21_FUN_IE_V = 0x1 +const RTC_IO_PAD21_FUN_IE_S = 13 +const RTC_IO_EXT_WAKEUP0_SEL = 0x0000001F +const RTC_IO_EXT_WAKEUP0_SEL_V = 0x1F +const RTC_IO_EXT_WAKEUP0_SEL_S = 27 +const RTC_IO_XTL_EXT_CTR_SEL = 0x0000001F +const RTC_IO_XTL_EXT_CTR_SEL_V = 0x1F +const RTC_IO_XTL_EXT_CTR_SEL_S = 27 +const RTC_IO_SAR_I2C_SDA_SEL = 0x00000003 +const RTC_IO_SAR_I2C_SDA_SEL_V = 0x3 +const RTC_IO_SAR_I2C_SDA_SEL_S = 30 +const RTC_IO_SAR_I2C_SCL_SEL = 0x00000003 +const RTC_IO_SAR_I2C_SCL_SEL_V = 0x3 +const RTC_IO_SAR_I2C_SCL_SEL_S = 28 +const RTC_IO_SAR_DEBUG_BIT_SEL = 0x0000001F +const RTC_IO_SAR_DEBUG_BIT_SEL_V = 0x1F +const RTC_IO_SAR_DEBUG_BIT_SEL_S = 23 +const RTC_IO_IO_TOUCH_BUFMODE_V = 0x1 +const RTC_IO_IO_TOUCH_BUFMODE_S = 4 +const RTC_IO_IO_TOUCH_BUFSEL = 0x0000000F +const RTC_IO_IO_TOUCH_BUFSEL_V = 0xF +const RTC_IO_IO_TOUCH_BUFSEL_S = 0 +const RTC_IO_DATE = 0x0FFFFFFF +const RTC_IO_DATE_V = 0xFFFFFFF +const RTC_IO_DATE_S = 0 diff --git a/esp32/rtc_io_struct.go b/esp32/rtc_io_struct.go new file mode 100644 index 00000000..d8232e10 --- /dev/null +++ b/esp32/rtc_io_struct.go @@ -0,0 +1,150 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type RtcIoDevS struct { + Out struct { + Val c.Uint32T + } + OutW1ts struct { + Val c.Uint32T + } + OutW1tc struct { + Val c.Uint32T + } + Enable struct { + Val c.Uint32T + } + EnableW1ts struct { + Val c.Uint32T + } + EnableW1tc struct { + Val c.Uint32T + } + Status struct { + Val c.Uint32T + } + StatusW1ts struct { + Val c.Uint32T + } + StatusW1tc struct { + Val c.Uint32T + } + InVal struct { + Val c.Uint32T + } + Pin [22]struct { + Val c.Uint32T + } + DebugSel struct { + Val c.Uint32T + } + TouchPad [15]struct { + Val c.Uint32T + } + Xtal32pPad struct { + Val c.Uint32T + } + Xtal32nPad struct { + Val c.Uint32T + } + PadDac [2]struct { + Val c.Uint32T + } + RtcPad19 struct { + Val c.Uint32T + } + RtcPad20 struct { + Val c.Uint32T + } + RtcPad21 struct { + Val c.Uint32T + } + ExtWakeup0 struct { + Val c.Uint32T + } + XtlExtCtr struct { + Val c.Uint32T + } + SarI2cIo struct { + Val c.Uint32T + } + TouchCtrl struct { + Val c.Uint32T + } + ReservedEc c.Uint32T + ReservedF0 c.Uint32T + ReservedF4 c.Uint32T + ReservedF8 c.Uint32T + ReservedFc c.Uint32T + Reserved100 c.Uint32T + Reserved104 c.Uint32T + Reserved108 c.Uint32T + Reserved10c c.Uint32T + Reserved110 c.Uint32T + Reserved114 c.Uint32T + Reserved118 c.Uint32T + Reserved11c c.Uint32T + Reserved120 c.Uint32T + Reserved124 c.Uint32T + Reserved128 c.Uint32T + Reserved12c c.Uint32T + Reserved130 c.Uint32T + Reserved134 c.Uint32T + Reserved138 c.Uint32T + Reserved13c c.Uint32T + Reserved140 c.Uint32T + Reserved144 c.Uint32T + Reserved148 c.Uint32T + Reserved14c c.Uint32T + Reserved150 c.Uint32T + Reserved154 c.Uint32T + Reserved158 c.Uint32T + Reserved15c c.Uint32T + Reserved160 c.Uint32T + Reserved164 c.Uint32T + Reserved168 c.Uint32T + Reserved16c c.Uint32T + Reserved170 c.Uint32T + Reserved174 c.Uint32T + Reserved178 c.Uint32T + Reserved17c c.Uint32T + Reserved180 c.Uint32T + Reserved184 c.Uint32T + Reserved188 c.Uint32T + Reserved18c c.Uint32T + Reserved190 c.Uint32T + Reserved194 c.Uint32T + Reserved198 c.Uint32T + Reserved19c c.Uint32T + Reserved1a0 c.Uint32T + Reserved1a4 c.Uint32T + Reserved1a8 c.Uint32T + Reserved1ac c.Uint32T + Reserved1b0 c.Uint32T + Reserved1b4 c.Uint32T + Reserved1b8 c.Uint32T + Reserved1bc c.Uint32T + Reserved1c0 c.Uint32T + Reserved1c4 c.Uint32T + Reserved1c8 c.Uint32T + Reserved1cc c.Uint32T + Reserved1d0 c.Uint32T + Reserved1d4 c.Uint32T + Reserved1d8 c.Uint32T + Reserved1dc c.Uint32T + Reserved1e0 c.Uint32T + Reserved1e4 c.Uint32T + Reserved1e8 c.Uint32T + Reserved1ec c.Uint32T + Reserved1f0 c.Uint32T + Reserved1f4 c.Uint32T + Reserved1f8 c.Uint32T + Date struct { + Val c.Uint32T + } +} +type RtcIoDevT RtcIoDevS diff --git a/esp32/rtc_io_types.go b/esp32/rtc_io_types.go new file mode 100644 index 00000000..b1587e56 --- /dev/null +++ b/esp32/rtc_io_types.go @@ -0,0 +1,17 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type RtcGpioModeT c.Int + +const ( + RTC_GPIO_MODE_INPUT_ONLY RtcGpioModeT = 0 + RTC_GPIO_MODE_OUTPUT_ONLY RtcGpioModeT = 1 + RTC_GPIO_MODE_INPUT_OUTPUT RtcGpioModeT = 2 + RTC_GPIO_MODE_DISABLED RtcGpioModeT = 3 + RTC_GPIO_MODE_OUTPUT_OD RtcGpioModeT = 4 + RTC_GPIO_MODE_INPUT_OUTPUT_OD RtcGpioModeT = 5 +) diff --git a/esp32/rwdt_ll.go b/esp32/rwdt_ll.go new file mode 100644 index 00000000..38ca19ec --- /dev/null +++ b/esp32/rwdt_ll.go @@ -0,0 +1,20 @@ +package freertos + +import _ "unsafe" + +const RWDT_LL_WDT_WKEY_VALUE = 0x50D83AA1 +const RWDT_LL_STG_SEL_OFF = 0 +const RWDT_LL_STG_SEL_INT = 1 +const RWDT_LL_STG_SEL_RESET_CPU = 2 +const RWDT_LL_STG_SEL_RESET_SYSTEM = 3 +const RWDT_LL_STG_SEL_RESET_RTC = 4 +const RWDT_LL_RESET_LENGTH_100_NS = 0 +const RWDT_LL_RESET_LENGTH_200_NS = 1 +const RWDT_LL_RESET_LENGTH_300_NS = 2 +const RWDT_LL_RESET_LENGTH_400_NS = 3 +const RWDT_LL_RESET_LENGTH_500_NS = 4 +const RWDT_LL_RESET_LENGTH_800_NS = 5 +const RWDT_LL_RESET_LENGTH_1600_NS = 6 +const RWDT_LL_RESET_LENGTH_3200_NS = 7 + +type RwdtDevT RtcCntlDevT diff --git a/esp32/sar_ctrl_ll.go b/esp32/sar_ctrl_ll.go new file mode 100644 index 00000000..6261a326 --- /dev/null +++ b/esp32/sar_ctrl_ll.go @@ -0,0 +1,16 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const PWDET_CONF_REG = 0x6000E060 + +type SarCtrlLlPowerT c.Int + +const ( + SAR_CTRL_LL_POWER_FSM SarCtrlLlPowerT = 0 + SAR_CTRL_LL_POWER_ON SarCtrlLlPowerT = 1 + SAR_CTRL_LL_POWER_OFF SarCtrlLlPowerT = 2 +) diff --git a/esp32/sar_periph_ctrl.go b/esp32/sar_periph_ctrl.go new file mode 100644 index 00000000..a3fbbf0a --- /dev/null +++ b/esp32/sar_periph_ctrl.go @@ -0,0 +1,98 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Initialise SAR related peripheral register settings + * Should only be used when running into app stage + */ +//go:linkname SarPeriphCtrlInit C.sar_periph_ctrl_init +func SarPeriphCtrlInit() + +/*------------------------------------------------------------------------------ +* ADC Power +*----------------------------------------------------------------------------*/ +/** + * @brief Acquire the ADC oneshot mode power + */ +//go:linkname SarPeriphCtrlAdcOneshotPowerAcquire C.sar_periph_ctrl_adc_oneshot_power_acquire +func SarPeriphCtrlAdcOneshotPowerAcquire() + +/** + * @brief Release the ADC oneshot mode power + */ +//go:linkname SarPeriphCtrlAdcOneshotPowerRelease C.sar_periph_ctrl_adc_oneshot_power_release +func SarPeriphCtrlAdcOneshotPowerRelease() + +/** + * @brief Acquire the ADC continuous mode power + */ +//go:linkname SarPeriphCtrlAdcContinuousPowerAcquire C.sar_periph_ctrl_adc_continuous_power_acquire +func SarPeriphCtrlAdcContinuousPowerAcquire() + +/** + * @brief Release the ADC ADC continuous mode power + */ +//go:linkname SarPeriphCtrlAdcContinuousPowerRelease C.sar_periph_ctrl_adc_continuous_power_release +func SarPeriphCtrlAdcContinuousPowerRelease() + +/*------------------------------------------------------------------------------ +* PWDET Power +*----------------------------------------------------------------------------*/ +/** + * @brief Acquire the PWDET Power + */ +//go:linkname SarPeriphCtrlPwdetPowerAcquire C.sar_periph_ctrl_pwdet_power_acquire +func SarPeriphCtrlPwdetPowerAcquire() + +/** + * @brief Release the PWDET Power + */ +//go:linkname SarPeriphCtrlPwdetPowerRelease C.sar_periph_ctrl_pwdet_power_release +func SarPeriphCtrlPwdetPowerRelease() + +/** + * @brief Acquire the temperature sensor power + */ +//go:linkname TemperatureSensorPowerAcquire C.temperature_sensor_power_acquire +func TemperatureSensorPowerAcquire() + +/** + * @brief Release the temperature sensor power + */ +//go:linkname TemperatureSensorPowerRelease C.temperature_sensor_power_release +func TemperatureSensorPowerRelease() + +/** + * @brief Get the temperature value and choose the temperature sensor range. Will be both used in phy and peripheral. + * + * @param range_changed Pointer to whether range has been changed here. If you don't need this param, you can + * set NULL directly. + * + * @return temperature sensor value. + */ +//go:linkname TempSensorGetRawValue C.temp_sensor_get_raw_value +func TempSensorGetRawValue(range_changed *bool) c.Int16T + +/** + * @brief Synchronize the tsens_idx between sar_periph and driver + * + * @param tsens_idx index value of temperature sensor attribute + */ +//go:linkname TempSensorSyncTsensIdx C.temp_sensor_sync_tsens_idx +func TempSensorSyncTsensIdx(tsens_idx c.Int) + +/** + * @brief Enable SAR power when system wakes up + */ +//go:linkname SarPeriphCtrlPowerEnable C.sar_periph_ctrl_power_enable +func SarPeriphCtrlPowerEnable() + +/** + * @brief Disable SAR power when system goes to sleep + */ +//go:linkname SarPeriphCtrlPowerDisable C.sar_periph_ctrl_power_disable +func SarPeriphCtrlPowerDisable() diff --git a/esp32/sd_types.go b/esp32/sd_types.go new file mode 100644 index 00000000..381ab528 --- /dev/null +++ b/esp32/sd_types.go @@ -0,0 +1,14 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type SdBusWidthT c.Int + +const ( + SD_BUS_WIDTH_1_BIT SdBusWidthT = 0 + SD_BUS_WIDTH_4_BIT SdBusWidthT = 1 + SD_BUS_WIDTH_8_BIT SdBusWidthT = 2 +) diff --git a/esp32/sdio_slave_periph.go b/esp32/sdio_slave_periph.go new file mode 100644 index 00000000..103e29b0 --- /dev/null +++ b/esp32/sdio_slave_periph.go @@ -0,0 +1,18 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** pin and signal information of each slot */ + +type SdioSlaveSlotInfoT struct { + ClkGpio c.Uint32T + CmdGpio c.Uint32T + D0Gpio c.Uint32T + D1Gpio c.Uint32T + D2Gpio c.Uint32T + D3Gpio c.Uint32T + Func c.Int +} diff --git a/esp32/sdio_slave_types.go b/esp32/sdio_slave_types.go new file mode 100644 index 00000000..90869e67 --- /dev/null +++ b/esp32/sdio_slave_types.go @@ -0,0 +1,36 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type SdioSlaveHostintT c.Int + +const ( + SDIO_SLAVE_HOSTINT_BIT0 SdioSlaveHostintT = 1 + SDIO_SLAVE_HOSTINT_BIT1 SdioSlaveHostintT = 2 + SDIO_SLAVE_HOSTINT_BIT2 SdioSlaveHostintT = 4 + SDIO_SLAVE_HOSTINT_BIT3 SdioSlaveHostintT = 8 + SDIO_SLAVE_HOSTINT_BIT4 SdioSlaveHostintT = 16 + SDIO_SLAVE_HOSTINT_BIT5 SdioSlaveHostintT = 32 + SDIO_SLAVE_HOSTINT_BIT6 SdioSlaveHostintT = 64 + SDIO_SLAVE_HOSTINT_BIT7 SdioSlaveHostintT = 128 + SDIO_SLAVE_HOSTINT_SEND_NEW_PACKET SdioSlaveHostintT = 8388608 +) + +type SdioSlaveTimingT c.Int + +const ( + SDIO_SLAVE_TIMING_PSEND_PSAMPLE SdioSlaveTimingT = 0 + SDIO_SLAVE_TIMING_NSEND_PSAMPLE SdioSlaveTimingT = 1 + SDIO_SLAVE_TIMING_PSEND_NSAMPLE SdioSlaveTimingT = 2 + SDIO_SLAVE_TIMING_NSEND_NSAMPLE SdioSlaveTimingT = 3 +) + +type SdioSlaveSendingModeT c.Int + +const ( + SDIO_SLAVE_SEND_STREAM SdioSlaveSendingModeT = 0 + SDIO_SLAVE_SEND_PACKET SdioSlaveSendingModeT = 1 +) diff --git a/esp32/sdm_hal.go b/esp32/sdm_hal.go new file mode 100644 index 00000000..69b83527 --- /dev/null +++ b/esp32/sdm_hal.go @@ -0,0 +1,26 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type SdmSocHandleT *GpioSdDevT + +/** + * HAL context type of Sigma-Delta driver + */ + +type SdmHalContextT struct { + Dev SdmSocHandleT +} + +/** + * @brief Initialize Sigma-Delta hal driver + * + * @param hal Context of the HAL layer + * @param group_id Sigma-Delta group number + */ +// llgo:link (*SdmHalContextT).SdmHalInit C.sdm_hal_init +func (recv_ *SdmHalContextT) SdmHalInit(group_id c.Int) { +} diff --git a/esp32/sdm_ll.go b/esp32/sdm_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/sdm_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/sdm_periph.go b/esp32/sdm_periph.go new file mode 100644 index 00000000..db3ac81c --- /dev/null +++ b/esp32/sdm_periph.go @@ -0,0 +1,12 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type SigmaDeltaSignalConnT struct { + Channels [8]struct { + SdSig c.Int + } +} diff --git a/esp32/sdm_types.go b/esp32/sdm_types.go new file mode 100644 index 00000000..4e590605 --- /dev/null +++ b/esp32/sdm_types.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +type SdmClockSourceT SocPeriphSdmClkSrcT diff --git a/esp32/sdmmc_hal.go b/esp32/sdmmc_hal.go new file mode 100644 index 00000000..2e090594 --- /dev/null +++ b/esp32/sdmmc_hal.go @@ -0,0 +1,22 @@ +package freertos + +import _ "unsafe" + +type SdmmcSocHandleT *SdmmcDevT + +/** + * @brief Context of the HAL + */ + +type SdmmcHalContextT struct { + Dev SdmmcSocHandleT +} + +/** + * @brief Init the sdmmc hal context. + * + * @param hal Context of the HAL + */ +// llgo:link (*SdmmcHalContextT).SdmmcHalInit C.sdmmc_hal_init +func (recv_ *SdmmcHalContextT) SdmmcHalInit() { +} diff --git a/esp32/sdmmc_ll.go b/esp32/sdmmc_ll.go new file mode 100644 index 00000000..02600dc3 --- /dev/null +++ b/esp32/sdmmc_ll.go @@ -0,0 +1,17 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const SDMMC_LL_EVENT_DMA_MASK = 0x1f + +type SdmmcLlDelayPhaseT c.Int + +const ( + SDMMC_LL_DELAY_PHASE_0 SdmmcLlDelayPhaseT = 0 + SDMMC_LL_DELAY_PHASE_1 SdmmcLlDelayPhaseT = 1 + SDMMC_LL_DELAY_PHASE_2 SdmmcLlDelayPhaseT = 2 + SDMMC_LL_DELAY_PHASE_3 SdmmcLlDelayPhaseT = 3 +) diff --git a/esp32/sdmmc_periph.go b/esp32/sdmmc_periph.go new file mode 100644 index 00000000..58785395 --- /dev/null +++ b/esp32/sdmmc_periph.go @@ -0,0 +1,27 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Common SDMMC slot info, doesn't depend on SOC_SDMMC_USE_{IOMUX,GPIO_MATRIX} + */ + +type SdmmcSlotInfoT struct { + Width c.Uint8T + CardDetect c.Uint8T + WriteProtect c.Uint8T + CardInt c.Uint8T +} + +/** + * This structure lists pin numbers (if SOC_SDMMC_USE_IOMUX is set) + * or GPIO Matrix signal numbers (if SOC_SDMMC_USE_GPIO_MATRIX is set) + * for the SD bus signals. Field names match SD bus signal names. + */ + +type SdmmcSlotIoInfoT struct { + Val [12]GpioNumT +} diff --git a/esp32/sdmmc_reg.go b/esp32/sdmmc_reg.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/sdmmc_reg.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/sdmmc_struct.go b/esp32/sdmmc_struct.go new file mode 100644 index 00000000..be2df2ed --- /dev/null +++ b/esp32/sdmmc_struct.go @@ -0,0 +1,134 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const SDMMC_DMA_MAX_BUF_LEN = 4096 + +type SdmmcDescS struct { + Buffer1Ptr c.Pointer +} +type SdmmcDescT SdmmcDescS + +type SdmmcHwCmdS struct { + CmdIndex c.Uint32T + ResponseExpect c.Uint32T + ResponseLong c.Uint32T + CheckResponseCrc c.Uint32T + DataExpected c.Uint32T + Rw c.Uint32T + StreamMode c.Uint32T + SendAutoStop c.Uint32T + WaitComplete c.Uint32T + StopAbortCmd c.Uint32T + SendInit c.Uint32T + CardNum c.Uint32T + UpdateClkReg c.Uint32T + ReadCeata c.Uint32T + CcsExpected c.Uint32T + EnableBoot c.Uint32T + ExpectBootAck c.Uint32T + DisableBoot c.Uint32T + BootMode c.Uint32T + VoltSwitch c.Uint32T + UseHoldReg c.Uint32T + Reserved c.Uint32T + StartCommand c.Uint32T +} +type SdmmcHwCmdT SdmmcHwCmdS + +type SdmmcDevT struct { + Ctrl struct { + Val c.Uint32T + } + Pwren c.Uint32T + Clkdiv struct { + Val c.Uint32T + } + Clksrc struct { + Val c.Uint32T + } + Clkena struct { + Val c.Uint32T + } + Tmout struct { + Val c.Uint32T + } + Ctype struct { + Val c.Uint32T + } + Blksiz struct { + Val c.Uint32T + } + Bytcnt c.Uint32T + Intmask struct { + Val c.Uint32T + } + Cmdarg c.Uint32T + Cmd SdmmcHwCmdT + Resp [4]c.Uint32T + Mintsts struct { + Val c.Uint32T + } + Rintsts struct { + Val c.Uint32T + } + Status struct { + Val c.Uint32T + } + Fifoth struct { + Val c.Uint32T + } + Cdetect struct { + Val c.Uint32T + } + Wrtprt struct { + Val c.Uint32T + } + Gpio c.Uint32T + Tcbcnt c.Uint32T + Tbbcnt c.Uint32T + Debnce struct { + } + Usrid c.Uint32T + Verid c.Uint32T + Hcon struct { + Val c.Uint32T + } + Uhs struct { + Val c.Uint32T + } + RstN struct { + } + Reserved7c c.Uint32T + Bmod struct { + Val c.Uint32T + } + Pldmnd c.Uint32T + Dbaddr *SdmmcDescT + Idsts struct { + Val c.Uint32T + } + Idinten struct { + Val c.Uint32T + } + Dscaddr c.Uint32T + Dscaddrl c.Uint32T + Dscaddru c.Uint32T + Bufaddrl c.Uint32T + Bufaddru c.Uint32T + ReservedA8 [22]c.Uint32T + Cardthrctl struct { + Val c.Uint32T + } + BackEndPower c.Uint32T + UhsRegExt c.Uint32T + EmmcDdrReg c.Uint32T + EnableShift c.Uint32T + Reserved114 [443]c.Uint32T + Clock struct { + Val c.Uint32T + } +} diff --git a/esp32/secure_boot.go b/esp32/secure_boot.go new file mode 100644 index 00000000..e3d34c11 --- /dev/null +++ b/esp32/secure_boot.go @@ -0,0 +1,75 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const CRC_SIGN_BLOCK_LEN = 1196 +const SIG_BLOCK_PADDING = 4096 +const ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC = 0xE7 +const SECURE_BOOT_NUM_BLOCKS = 3 +const MAX_KEY_DIGESTS = 3 + +type EtsSecureBootSigBlock struct { + MagicByte c.Uint8T + Version c.Uint8T + X_reserved1 c.Uint8T + X_reserved2 c.Uint8T + ImageDigest [32]c.Uint8T + Key EtsRsaPubkeyT + Signature [384]c.Uint8T + BlockCrc c.Uint32T + X_padding [16]c.Uint8T +} +type EtsSecureBootSigBlockT EtsSecureBootSigBlock + +type EtsSecureBootSignature struct { + Block [3]EtsSecureBootSigBlockT + X_padding [448]c.Uint8T +} +type EtsSecureBootSignatureT EtsSecureBootSignature + +type EtsSecureBootKeyDigests struct { + KeyDigests [3]c.Pointer + AllowKeyRevoke bool +} +type EtsSecureBootKeyDigestsT EtsSecureBootKeyDigests +type SecureBootStatusT c.Int + +const ( + SB_SUCCESS SecureBootStatusT = 978999973 + SB_FAILED SecureBootStatusT = 1966311518 +) + +/* Verify bootloader image (reconfigures cache to map), with + key digests provided as parameters.) + + Can be used to verify secure boot status before enabling + secure boot permanently. + + If result is ETS_OK, the "simple hash" of the bootloader is + copied into verified_hash. +*/ +//go:linkname EtsSecureBootVerifyBootloaderWithKeys C.ets_secure_boot_verify_bootloader_with_keys +func EtsSecureBootVerifyBootloaderWithKeys(verified_hash *c.Uint8T, trusted_keys *EtsSecureBootKeyDigestsT, stage_load bool) SecureBootStatusT + +/* Verify supplied signature against supplied digest, using + supplied trusted key digests. + + Doesn't reconfigure cache or any other hardware access. +*/ +// llgo:link (*EtsSecureBootSignatureT).EtsSecureBootVerifySignature C.ets_secure_boot_verify_signature +func (recv_ *EtsSecureBootSignatureT) EtsSecureBootVerifySignature(image_digest *c.Uint8T, trusted_keys *EtsSecureBootKeyDigestsT, verified_digest *c.Uint8T) SecureBootStatusT { + return 0 +} + +/* Read key digests from efuse. Any revoked/missing digests will be + marked as NULL + + Returns 0 if at least one valid digest was found. +*/ +// llgo:link (*EtsSecureBootKeyDigestsT).EtsSecureBootReadKeyDigests C.ets_secure_boot_read_key_digests +func (recv_ *EtsSecureBootKeyDigestsT) EtsSecureBootReadKeyDigests() ETSSTATUS { + return 0 +} diff --git a/esp32/semphr.go b/esp32/semphr.go new file mode 100644 index 00000000..0c16a44b --- /dev/null +++ b/esp32/semphr.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +type SemaphoreHandleT QueueHandleT diff --git a/esp32/sens_reg.go b/esp32/sens_reg.go new file mode 100644 index 00000000..121c8552 --- /dev/null +++ b/esp32/sens_reg.go @@ -0,0 +1,601 @@ +package freertos + +import _ "unsafe" + +const SENS_SAR1_INT_EN_V = 0x1 +const SENS_SAR1_INT_EN_S = 29 +const SENS_SAR1_DATA_INV_V = 0x1 +const SENS_SAR1_DATA_INV_S = 28 +const SENS_SAR1_SAMPLE_NUM = 0x000000FF +const SENS_SAR1_SAMPLE_NUM_V = 0xFF +const SENS_SAR1_SAMPLE_NUM_S = 19 +const SENS_SAR1_CLK_GATED_V = 0x1 +const SENS_SAR1_CLK_GATED_S = 18 +const SENS_SAR1_CLK_DIV = 0x000000FF +const SENS_SAR1_CLK_DIV_V = 0xFF +const SENS_SAR1_CLK_DIV_S = 0 +const SENS_SAR1_READER_STATUS = 0xFFFFFFFF +const SENS_SAR1_READER_STATUS_V = 0xFFFFFFFF +const SENS_SAR1_READER_STATUS_S = 0 +const SENS_AMP_SHORT_REF_GND_FORCE = 0x00000003 +const SENS_AMP_SHORT_REF_GND_FORCE_V = 0x3 +const SENS_AMP_SHORT_REF_GND_FORCE_S = 30 +const SENS_AMP_SHORT_REF_FORCE = 0x00000003 +const SENS_AMP_SHORT_REF_FORCE_V = 0x3 +const SENS_AMP_SHORT_REF_FORCE_S = 28 +const SENS_AMP_RST_FB_FORCE = 0x00000003 +const SENS_AMP_RST_FB_FORCE_V = 0x3 +const SENS_AMP_RST_FB_FORCE_S = 26 +const SENS_FORCE_XPD_AMP = 0x00000003 +const SENS_FORCE_XPD_AMP_V = 0x3 +const SENS_FORCE_XPD_AMP_S = 24 +const SENS_SAR1_EN_PAD_FORCE_V = 0x1 +const SENS_SAR1_EN_PAD_FORCE_S = 31 +const SENS_SAR1_EN_PAD = 0x00000FFF +const SENS_SAR1_EN_PAD_V = 0xFFF +const SENS_SAR1_EN_PAD_S = 19 +const SENS_MEAS1_START_FORCE_V = 0x1 +const SENS_MEAS1_START_FORCE_S = 18 +const SENS_MEAS1_START_SAR_V = 0x1 +const SENS_MEAS1_START_SAR_S = 17 +const SENS_MEAS1_DONE_SAR_V = 0x1 +const SENS_MEAS1_DONE_SAR_S = 16 +const SENS_MEAS1_DATA_SAR = 0x0000FFFF +const SENS_MEAS1_DATA_SAR_V = 0xFFFF +const SENS_MEAS1_DATA_SAR_S = 0 +const SENS_SAR1_DIG_FORCE_V = 0x1 +const SENS_SAR1_DIG_FORCE_S = 31 +const SENS_SAR1_ATTEN = 0xFFFFFFFF +const SENS_SAR1_ATTEN_V = 0xFFFFFFFF +const SENS_SAR1_ATTEN_S = 0 +const SENS_SAR_AMP_WAIT2 = 0x0000FFFF +const SENS_SAR_AMP_WAIT2_V = 0xFFFF +const SENS_SAR_AMP_WAIT2_S = 16 +const SENS_SAR_AMP_WAIT1 = 0x0000FFFF +const SENS_SAR_AMP_WAIT1_V = 0xFFFF +const SENS_SAR_AMP_WAIT1_S = 0 +const SENS_SAR_AMP_WAIT3 = 0x0000FFFF +const SENS_SAR_AMP_WAIT3_V = 0xFFFF +const SENS_SAR_AMP_WAIT3_S = 16 +const SENS_SAR_RSTB_FSM_IDLE_V = 0x1 +const SENS_SAR_RSTB_FSM_IDLE_S = 6 +const SENS_XPD_SAR_FSM_IDLE_V = 0x1 +const SENS_XPD_SAR_FSM_IDLE_S = 5 +const SENS_AMP_SHORT_REF_GND_FSM_IDLE_V = 0x1 +const SENS_AMP_SHORT_REF_GND_FSM_IDLE_S = 4 +const SENS_AMP_SHORT_REF_FSM_IDLE_V = 0x1 +const SENS_AMP_SHORT_REF_FSM_IDLE_S = 3 +const SENS_AMP_RST_FB_FSM_IDLE_V = 0x1 +const SENS_AMP_RST_FB_FSM_IDLE_S = 2 +const SENS_XPD_SAR_AMP_FSM_IDLE_V = 0x1 +const SENS_XPD_SAR_AMP_FSM_IDLE_S = 1 +const SENS_SAR1_DAC_XPD_FSM_IDLE_V = 0x1 +const SENS_SAR1_DAC_XPD_FSM_IDLE_S = 0 +const SENS_SAR_RSTB_FSM = 0x0000000F +const SENS_SAR_RSTB_FSM_V = 0xF +const SENS_SAR_RSTB_FSM_S = 24 +const SENS_XPD_SAR_FSM = 0x0000000F +const SENS_XPD_SAR_FSM_V = 0xF +const SENS_XPD_SAR_FSM_S = 20 +const SENS_AMP_SHORT_REF_GND_FSM = 0x0000000F +const SENS_AMP_SHORT_REF_GND_FSM_V = 0xF +const SENS_AMP_SHORT_REF_GND_FSM_S = 16 +const SENS_AMP_SHORT_REF_FSM = 0x0000000F +const SENS_AMP_SHORT_REF_FSM_V = 0xF +const SENS_AMP_SHORT_REF_FSM_S = 12 +const SENS_AMP_RST_FB_FSM = 0x0000000F +const SENS_AMP_RST_FB_FSM_V = 0xF +const SENS_AMP_RST_FB_FSM_S = 8 +const SENS_XPD_SAR_AMP_FSM = 0x0000000F +const SENS_XPD_SAR_AMP_FSM_V = 0xF +const SENS_XPD_SAR_AMP_FSM_S = 4 +const SENS_SAR1_DAC_XPD_FSM = 0x0000000F +const SENS_SAR1_DAC_XPD_FSM_V = 0xF +const SENS_SAR1_DAC_XPD_FSM_S = 0 +const SENS_SAR2_INT_EN_V = 0x1 +const SENS_SAR2_INT_EN_S = 30 +const SENS_SAR2_DATA_INV_V = 0x1 +const SENS_SAR2_DATA_INV_S = 29 +const SENS_SAR2_SAMPLE_NUM = 0x000000FF +const SENS_SAR2_SAMPLE_NUM_V = 0xFF +const SENS_SAR2_SAMPLE_NUM_S = 19 +const SENS_SAR2_CLK_GATED_V = 0x1 +const SENS_SAR2_CLK_GATED_S = 18 +const SENS_SAR2_WAIT_ARB_CYCLE = 0x00000003 +const SENS_SAR2_WAIT_ARB_CYCLE_V = 0x3 +const SENS_SAR2_WAIT_ARB_CYCLE_S = 16 +const SENS_SAR2_CLK_DIV = 0x000000FF +const SENS_SAR2_CLK_DIV_V = 0xFF +const SENS_SAR2_CLK_DIV_S = 0 +const SENS_SAR2_READER_STATUS = 0xFFFFFFFF +const SENS_SAR2_READER_STATUS_V = 0xFFFFFFFF +const SENS_SAR2_READER_STATUS_S = 0 +const SENS_SAR2_XPD_WAIT = 0x000000FF +const SENS_SAR2_XPD_WAIT_V = 0xFF +const SENS_SAR2_XPD_WAIT_S = 24 +const SENS_SAR2_RSTB_WAIT = 0x000000FF +const SENS_SAR2_RSTB_WAIT_V = 0xFF +const SENS_SAR2_RSTB_WAIT_S = 16 +const SENS_SAR2_STANDBY_WAIT = 0x000000FF +const SENS_SAR2_STANDBY_WAIT_V = 0xFF +const SENS_SAR2_STANDBY_WAIT_S = 8 +const SENS_SAR2_RSTB_FORCE = 0x00000003 +const SENS_SAR2_RSTB_FORCE_V = 0x3 +const SENS_SAR2_RSTB_FORCE_S = 6 +const SENS_SAR2_EN_TEST_V = 0x1 +const SENS_SAR2_EN_TEST_S = 5 +const SENS_SAR2_PKDET_CAL_EN_V = 0x1 +const SENS_SAR2_PKDET_CAL_EN_S = 4 +const SENS_SAR2_PWDET_CAL_EN_V = 0x1 +const SENS_SAR2_PWDET_CAL_EN_S = 3 +const SENS_SAR2_CNTL_STATE = 0x00000007 +const SENS_SAR2_CNTL_STATE_V = 0x7 +const SENS_SAR2_CNTL_STATE_S = 0 +const SENS_SAR2_EN_PAD_FORCE_V = 0x1 +const SENS_SAR2_EN_PAD_FORCE_S = 31 +const SENS_SAR2_EN_PAD = 0x00000FFF +const SENS_SAR2_EN_PAD_V = 0xFFF +const SENS_SAR2_EN_PAD_S = 19 +const SENS_MEAS2_START_FORCE_V = 0x1 +const SENS_MEAS2_START_FORCE_S = 18 +const SENS_MEAS2_START_SAR_V = 0x1 +const SENS_MEAS2_START_SAR_S = 17 +const SENS_MEAS2_DONE_SAR_V = 0x1 +const SENS_MEAS2_DONE_SAR_S = 16 +const SENS_MEAS2_DATA_SAR = 0x0000FFFF +const SENS_MEAS2_DATA_SAR_V = 0xFFFF +const SENS_MEAS2_DATA_SAR_S = 0 +const SENS_SAR2_RTC_FORCE_V = 0x1 +const SENS_SAR2_RTC_FORCE_S = 31 +const SENS_SAR2_PWDET_CCT = 0x00000007 +const SENS_SAR2_PWDET_CCT_V = 0x7 +const SENS_SAR2_PWDET_CCT_S = 28 +const SENS_SAR2_ATTEN = 0xFFFFFFFF +const SENS_SAR2_ATTEN_V = 0xFFFFFFFF +const SENS_SAR2_ATTEN_S = 0 +const SENS_SARCLK_EN_V = 0x1 +const SENS_SARCLK_EN_S = 31 +const SENS_FORCE_XPD_SAR = 0x00000003 +const SENS_FORCE_XPD_SAR_V = 0x3 +const SENS_FORCE_XPD_SAR_S = 29 +const SENS_SARADC_MEAS_STATUS = 0x000000FF +const SENS_SARADC_MEAS_STATUS_V = 0xFF +const SENS_SARADC_MEAS_STATUS_S = 22 +const SENS_I2C_SLAVE_ADDR0 = 0x000007FF +const SENS_I2C_SLAVE_ADDR0_V = 0x7FF +const SENS_I2C_SLAVE_ADDR0_S = 11 +const SENS_I2C_SLAVE_ADDR1 = 0x000007FF +const SENS_I2C_SLAVE_ADDR1_V = 0x7FF +const SENS_I2C_SLAVE_ADDR1_S = 0 +const SENS_I2C_SLAVE_ADDR2 = 0x000007FF +const SENS_I2C_SLAVE_ADDR2_V = 0x7FF +const SENS_I2C_SLAVE_ADDR2_S = 11 +const SENS_I2C_SLAVE_ADDR3 = 0x000007FF +const SENS_I2C_SLAVE_ADDR3_V = 0x7FF +const SENS_I2C_SLAVE_ADDR3_S = 0 +const SENS_I2C_SLAVE_ADDR4 = 0x000007FF +const SENS_I2C_SLAVE_ADDR4_V = 0x7FF +const SENS_I2C_SLAVE_ADDR4_S = 11 +const SENS_I2C_SLAVE_ADDR5 = 0x000007FF +const SENS_I2C_SLAVE_ADDR5_V = 0x7FF +const SENS_I2C_SLAVE_ADDR5_S = 0 +const SENS_I2C_SLAVE_ADDR6 = 0x000007FF +const SENS_I2C_SLAVE_ADDR6_V = 0x7FF +const SENS_I2C_SLAVE_ADDR6_S = 11 +const SENS_I2C_SLAVE_ADDR7 = 0x000007FF +const SENS_I2C_SLAVE_ADDR7_V = 0x7FF +const SENS_I2C_SLAVE_ADDR7_S = 0 +const SENS_TSENS_DUMP_OUT_V = 0x1 +const SENS_TSENS_DUMP_OUT_S = 24 +const SENS_TSENS_POWER_UP_FORCE_V = 0x1 +const SENS_TSENS_POWER_UP_FORCE_S = 23 +const SENS_TSENS_POWER_UP_V = 0x1 +const SENS_TSENS_POWER_UP_S = 22 +const SENS_TSENS_CLK_DIV = 0x000000FF +const SENS_TSENS_CLK_DIV_V = 0xFF +const SENS_TSENS_CLK_DIV_S = 14 +const SENS_TSENS_IN_INV_V = 0x1 +const SENS_TSENS_IN_INV_S = 13 +const SENS_TSENS_INT_EN_V = 0x1 +const SENS_TSENS_INT_EN_S = 12 +const SENS_TSENS_READY_V = 0x1 +const SENS_TSENS_READY_S = 8 +const SENS_TSENS_OUT = 0x000000FF +const SENS_TSENS_OUT_V = 0xFF +const SENS_TSENS_OUT_S = 0 +const SENS_TSENS_CLK_INV_V = 0x1 +const SENS_TSENS_CLK_INV_S = 14 +const SENS_TSENS_XPD_FORCE = 0x00000003 +const SENS_TSENS_XPD_FORCE_V = 0x3 +const SENS_TSENS_XPD_FORCE_S = 12 +const SENS_TSENS_XPD_WAIT = 0x00000FFF +const SENS_TSENS_XPD_WAIT_V = 0xFFF +const SENS_TSENS_XPD_WAIT_S = 0 +const SENS_SAR_I2C_START_FORCE_V = 0x1 +const SENS_SAR_I2C_START_FORCE_S = 29 +const SENS_SAR_I2C_START_V = 0x1 +const SENS_SAR_I2C_START_S = 28 +const SENS_SAR_I2C_CTRL = 0x0FFFFFFF +const SENS_SAR_I2C_CTRL_V = 0xFFFFFFF +const SENS_SAR_I2C_CTRL_S = 0 +const SENS_TOUCH_APPROACH_PAD0 = 0x0000000F +const SENS_TOUCH_APPROACH_PAD0_V = 0xF +const SENS_TOUCH_APPROACH_PAD0_S = 28 +const SENS_TOUCH_APPROACH_PAD1 = 0x0000000F +const SENS_TOUCH_APPROACH_PAD1_V = 0xF +const SENS_TOUCH_APPROACH_PAD1_S = 24 +const SENS_TOUCH_APPROACH_PAD2 = 0x0000000F +const SENS_TOUCH_APPROACH_PAD2_V = 0xF +const SENS_TOUCH_APPROACH_PAD2_S = 20 +const SENS_TOUCH_UNIT_END_V = 0x1 +const SENS_TOUCH_UNIT_END_S = 19 +const SENS_TOUCH_DENOISE_END_V = 0x1 +const SENS_TOUCH_DENOISE_END_S = 18 +const SENS_TOUCH_DATA_SEL = 0x00000003 +const SENS_TOUCH_DATA_SEL_V = 0x3 +const SENS_TOUCH_DATA_SEL_S = 16 +const SENS_TOUCH_STATUS_CLR_V = 0x1 +const SENS_TOUCH_STATUS_CLR_S = 15 +const SENS_TOUCH_OUTEN = 0x00007FFF +const SENS_TOUCH_OUTEN_V = 0x7FFF +const SENS_TOUCH_OUTEN_S = 0 +const SENS_TOUCH_DENOISE_DATA = 0x003FFFFF +const SENS_TOUCH_DENOISE_DATA_V = 0x3FFFFF +const SENS_TOUCH_DENOISE_DATA_S = 0 +const SENS_TOUCH_OUT_TH1 = 0x003FFFFF +const SENS_TOUCH_OUT_TH1_V = 0x3FFFFF +const SENS_TOUCH_OUT_TH1_S = 0 +const SENS_TOUCH_OUT_TH2 = 0x003FFFFF +const SENS_TOUCH_OUT_TH2_V = 0x3FFFFF +const SENS_TOUCH_OUT_TH2_S = 0 +const SENS_TOUCH_OUT_TH3 = 0x003FFFFF +const SENS_TOUCH_OUT_TH3_V = 0x3FFFFF +const SENS_TOUCH_OUT_TH3_S = 0 +const SENS_TOUCH_OUT_TH4 = 0x003FFFFF +const SENS_TOUCH_OUT_TH4_V = 0x3FFFFF +const SENS_TOUCH_OUT_TH4_S = 0 +const SENS_TOUCH_OUT_TH5 = 0x003FFFFF +const SENS_TOUCH_OUT_TH5_V = 0x3FFFFF +const SENS_TOUCH_OUT_TH5_S = 0 +const SENS_TOUCH_OUT_TH6 = 0x003FFFFF +const SENS_TOUCH_OUT_TH6_V = 0x3FFFFF +const SENS_TOUCH_OUT_TH6_S = 0 +const SENS_TOUCH_OUT_TH7 = 0x003FFFFF +const SENS_TOUCH_OUT_TH7_V = 0x3FFFFF +const SENS_TOUCH_OUT_TH7_S = 0 +const SENS_TOUCH_OUT_TH8 = 0x003FFFFF +const SENS_TOUCH_OUT_TH8_V = 0x3FFFFF +const SENS_TOUCH_OUT_TH8_S = 0 +const SENS_TOUCH_OUT_TH9 = 0x003FFFFF +const SENS_TOUCH_OUT_TH9_V = 0x3FFFFF +const SENS_TOUCH_OUT_TH9_S = 0 +const SENS_TOUCH_OUT_TH10 = 0x003FFFFF +const SENS_TOUCH_OUT_TH10_V = 0x3FFFFF +const SENS_TOUCH_OUT_TH10_S = 0 +const SENS_TOUCH_OUT_TH11 = 0x003FFFFF +const SENS_TOUCH_OUT_TH11_V = 0x3FFFFF +const SENS_TOUCH_OUT_TH11_S = 0 +const SENS_TOUCH_OUT_TH12 = 0x003FFFFF +const SENS_TOUCH_OUT_TH12_V = 0x3FFFFF +const SENS_TOUCH_OUT_TH12_S = 0 +const SENS_TOUCH_OUT_TH13 = 0x003FFFFF +const SENS_TOUCH_OUT_TH13_V = 0x3FFFFF +const SENS_TOUCH_OUT_TH13_S = 0 +const SENS_TOUCH_OUT_TH14 = 0x003FFFFF +const SENS_TOUCH_OUT_TH14_V = 0x3FFFFF +const SENS_TOUCH_OUT_TH14_S = 0 +const SENS_TOUCH_MEAS_DONE_V = 0x1 +const SENS_TOUCH_MEAS_DONE_S = 31 +const SENS_TOUCH_CHANNEL_CLR = 0x00007FFF +const SENS_TOUCH_CHANNEL_CLR_V = 0x7FFF +const SENS_TOUCH_CHANNEL_CLR_S = 15 +const SENS_TOUCH_PAD_ACTIVE = 0x00007FFF +const SENS_TOUCH_PAD_ACTIVE_V = 0x7FFF +const SENS_TOUCH_PAD_ACTIVE_S = 0 +const SENS_TOUCH_SCAN_CURR = 0x0000000F +const SENS_TOUCH_SCAN_CURR_V = 0xF +const SENS_TOUCH_SCAN_CURR_S = 22 +const SENS_TOUCH_PAD1_DEBOUNCE = 0x00000007 +const SENS_TOUCH_PAD1_DEBOUNCE_V = 0x7 +const SENS_TOUCH_PAD1_DEBOUNCE_S = 29 +const SENS_TOUCH_PAD1_DATA = 0x003FFFFF +const SENS_TOUCH_PAD1_DATA_V = 0x3FFFFF +const SENS_TOUCH_PAD1_DATA_S = 0 +const SENS_TOUCH_PAD2_DEBOUNCE = 0x00000007 +const SENS_TOUCH_PAD2_DEBOUNCE_V = 0x7 +const SENS_TOUCH_PAD2_DEBOUNCE_S = 29 +const SENS_TOUCH_PAD2_DATA = 0x003FFFFF +const SENS_TOUCH_PAD2_DATA_V = 0x3FFFFF +const SENS_TOUCH_PAD2_DATA_S = 0 +const SENS_TOUCH_PAD3_DEBOUNCE = 0x00000007 +const SENS_TOUCH_PAD3_DEBOUNCE_V = 0x7 +const SENS_TOUCH_PAD3_DEBOUNCE_S = 29 +const SENS_TOUCH_PAD3_DATA = 0x003FFFFF +const SENS_TOUCH_PAD3_DATA_V = 0x3FFFFF +const SENS_TOUCH_PAD3_DATA_S = 0 +const SENS_TOUCH_PAD4_DEBOUNCE = 0x00000007 +const SENS_TOUCH_PAD4_DEBOUNCE_V = 0x7 +const SENS_TOUCH_PAD4_DEBOUNCE_S = 29 +const SENS_TOUCH_PAD4_DATA = 0x003FFFFF +const SENS_TOUCH_PAD4_DATA_V = 0x3FFFFF +const SENS_TOUCH_PAD4_DATA_S = 0 +const SENS_TOUCH_PAD5_DEBOUNCE = 0x00000007 +const SENS_TOUCH_PAD5_DEBOUNCE_V = 0x7 +const SENS_TOUCH_PAD5_DEBOUNCE_S = 29 +const SENS_TOUCH_PAD5_DATA = 0x003FFFFF +const SENS_TOUCH_PAD5_DATA_V = 0x3FFFFF +const SENS_TOUCH_PAD5_DATA_S = 0 +const SENS_TOUCH_PAD6_DEBOUNCE = 0x00000007 +const SENS_TOUCH_PAD6_DEBOUNCE_V = 0x7 +const SENS_TOUCH_PAD6_DEBOUNCE_S = 29 +const SENS_TOUCH_PAD6_DATA = 0x003FFFFF +const SENS_TOUCH_PAD6_DATA_V = 0x3FFFFF +const SENS_TOUCH_PAD6_DATA_S = 0 +const SENS_TOUCH_PAD7_DEBOUNCE = 0x00000007 +const SENS_TOUCH_PAD7_DEBOUNCE_V = 0x7 +const SENS_TOUCH_PAD7_DEBOUNCE_S = 29 +const SENS_TOUCH_PAD7_DATA = 0x003FFFFF +const SENS_TOUCH_PAD7_DATA_V = 0x3FFFFF +const SENS_TOUCH_PAD7_DATA_S = 0 +const SENS_TOUCH_PAD8_DEBOUNCE = 0x00000007 +const SENS_TOUCH_PAD8_DEBOUNCE_V = 0x7 +const SENS_TOUCH_PAD8_DEBOUNCE_S = 29 +const SENS_TOUCH_PAD8_DATA = 0x003FFFFF +const SENS_TOUCH_PAD8_DATA_V = 0x3FFFFF +const SENS_TOUCH_PAD8_DATA_S = 0 +const SENS_TOUCH_PAD9_DEBOUNCE = 0x00000007 +const SENS_TOUCH_PAD9_DEBOUNCE_V = 0x7 +const SENS_TOUCH_PAD9_DEBOUNCE_S = 29 +const SENS_TOUCH_PAD9_DATA = 0x003FFFFF +const SENS_TOUCH_PAD9_DATA_V = 0x3FFFFF +const SENS_TOUCH_PAD9_DATA_S = 0 +const SENS_TOUCH_PAD10_DEBOUNCE = 0x00000007 +const SENS_TOUCH_PAD10_DEBOUNCE_V = 0x7 +const SENS_TOUCH_PAD10_DEBOUNCE_S = 29 +const SENS_TOUCH_PAD10_DATA = 0x003FFFFF +const SENS_TOUCH_PAD10_DATA_V = 0x3FFFFF +const SENS_TOUCH_PAD10_DATA_S = 0 +const SENS_TOUCH_PAD11_DEBOUNCE = 0x00000007 +const SENS_TOUCH_PAD11_DEBOUNCE_V = 0x7 +const SENS_TOUCH_PAD11_DEBOUNCE_S = 29 +const SENS_TOUCH_PAD11_DATA = 0x003FFFFF +const SENS_TOUCH_PAD11_DATA_V = 0x3FFFFF +const SENS_TOUCH_PAD11_DATA_S = 0 +const SENS_TOUCH_PAD12_DEBOUNCE = 0x00000007 +const SENS_TOUCH_PAD12_DEBOUNCE_V = 0x7 +const SENS_TOUCH_PAD12_DEBOUNCE_S = 29 +const SENS_TOUCH_PAD12_DATA = 0x003FFFFF +const SENS_TOUCH_PAD12_DATA_V = 0x3FFFFF +const SENS_TOUCH_PAD12_DATA_S = 0 +const SENS_TOUCH_PAD13_DEBOUNCE = 0x00000007 +const SENS_TOUCH_PAD13_DEBOUNCE_V = 0x7 +const SENS_TOUCH_PAD13_DEBOUNCE_S = 29 +const SENS_TOUCH_PAD13_DATA = 0x003FFFFF +const SENS_TOUCH_PAD13_DATA_V = 0x3FFFFF +const SENS_TOUCH_PAD13_DATA_S = 0 +const SENS_TOUCH_PAD14_DEBOUNCE = 0x00000007 +const SENS_TOUCH_PAD14_DEBOUNCE_V = 0x7 +const SENS_TOUCH_PAD14_DEBOUNCE_S = 29 +const SENS_TOUCH_PAD14_DATA = 0x003FFFFF +const SENS_TOUCH_PAD14_DATA_V = 0x3FFFFF +const SENS_TOUCH_PAD14_DATA_S = 0 +const SENS_TOUCH_SLP_DEBOUNCE = 0x00000007 +const SENS_TOUCH_SLP_DEBOUNCE_V = 0x7 +const SENS_TOUCH_SLP_DEBOUNCE_S = 29 +const SENS_TOUCH_SLP_DATA = 0x003FFFFF +const SENS_TOUCH_SLP_DATA_V = 0x3FFFFF +const SENS_TOUCH_SLP_DATA_S = 0 +const SENS_TOUCH_SLP_APPROACH_CNT = 0x000000FF +const SENS_TOUCH_SLP_APPROACH_CNT_V = 0xFF +const SENS_TOUCH_SLP_APPROACH_CNT_S = 24 +const SENS_TOUCH_APPROACH_PAD0_CNT = 0x000000FF +const SENS_TOUCH_APPROACH_PAD0_CNT_V = 0xFF +const SENS_TOUCH_APPROACH_PAD0_CNT_S = 16 +const SENS_TOUCH_APPROACH_PAD1_CNT = 0x000000FF +const SENS_TOUCH_APPROACH_PAD1_CNT_V = 0xFF +const SENS_TOUCH_APPROACH_PAD1_CNT_S = 8 +const SENS_TOUCH_APPROACH_PAD2_CNT = 0x000000FF +const SENS_TOUCH_APPROACH_PAD2_CNT_V = 0xFF +const SENS_TOUCH_APPROACH_PAD2_CNT_S = 0 +const SENS_COCPU_EBREAK_V = 0x1 +const SENS_COCPU_EBREAK_S = 30 +const SENS_COCPU_TRAP_V = 0x1 +const SENS_COCPU_TRAP_S = 29 +const SENS_COCPU_EOI_V = 0x1 +const SENS_COCPU_EOI_S = 28 +const SENS_COCPU_RESET_N_V = 0x1 +const SENS_COCPU_RESET_N_S = 27 +const SENS_COCPU_CLK_EN_ST_V = 0x1 +const SENS_COCPU_CLK_EN_ST_S = 26 +const SENS_COCPU_DBG_TRIGGER_V = 0x1 +const SENS_COCPU_DBG_TRIGGER_S = 25 +const SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_V = 0x1 +const SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_S = 11 +const SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V = 0x1 +const SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S = 10 +const SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_V = 0x1 +const SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_S = 9 +const SENS_COCPU_SWD_INT_RAW_V = 0x1 +const SENS_COCPU_SWD_INT_RAW_S = 8 +const SENS_COCPU_SW_INT_RAW_V = 0x1 +const SENS_COCPU_SW_INT_RAW_S = 7 +const SENS_COCPU_START_INT_RAW_V = 0x1 +const SENS_COCPU_START_INT_RAW_S = 6 +const SENS_COCPU_TSENS_INT_RAW_V = 0x1 +const SENS_COCPU_TSENS_INT_RAW_S = 5 +const SENS_COCPU_SARADC2_INT_RAW_V = 0x1 +const SENS_COCPU_SARADC2_INT_RAW_S = 4 +const SENS_COCPU_SARADC1_INT_RAW_V = 0x1 +const SENS_COCPU_SARADC1_INT_RAW_S = 3 +const SENS_COCPU_TOUCH_ACTIVE_INT_RAW_V = 0x1 +const SENS_COCPU_TOUCH_ACTIVE_INT_RAW_S = 2 +const SENS_COCPU_TOUCH_INACTIVE_INT_RAW_V = 0x1 +const SENS_COCPU_TOUCH_INACTIVE_INT_RAW_S = 1 +const SENS_COCPU_TOUCH_DONE_INT_RAW_V = 0x1 +const SENS_COCPU_TOUCH_DONE_INT_RAW_S = 0 +const SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_V = 0x1 +const SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_S = 11 +const SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V = 0x1 +const SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S = 10 +const SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_V = 0x1 +const SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_S = 9 +const SENS_COCPU_SWD_INT_ENA_V = 0x1 +const SENS_COCPU_SWD_INT_ENA_S = 8 +const SENS_COCPU_SW_INT_ENA_V = 0x1 +const SENS_COCPU_SW_INT_ENA_S = 7 +const SENS_COCPU_START_INT_ENA_V = 0x1 +const SENS_COCPU_START_INT_ENA_S = 6 +const SENS_COCPU_TSENS_INT_ENA_V = 0x1 +const SENS_COCPU_TSENS_INT_ENA_S = 5 +const SENS_COCPU_SARADC2_INT_ENA_V = 0x1 +const SENS_COCPU_SARADC2_INT_ENA_S = 4 +const SENS_COCPU_SARADC1_INT_ENA_V = 0x1 +const SENS_COCPU_SARADC1_INT_ENA_S = 3 +const SENS_COCPU_TOUCH_ACTIVE_INT_ENA_V = 0x1 +const SENS_COCPU_TOUCH_ACTIVE_INT_ENA_S = 2 +const SENS_COCPU_TOUCH_INACTIVE_INT_ENA_V = 0x1 +const SENS_COCPU_TOUCH_INACTIVE_INT_ENA_S = 1 +const SENS_COCPU_TOUCH_DONE_INT_ENA_V = 0x1 +const SENS_COCPU_TOUCH_DONE_INT_ENA_S = 0 +const SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_V = 0x1 +const SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_S = 11 +const SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_V = 0x1 +const SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_S = 10 +const SENS_COCPU_TOUCH_TIMEOUT_INT_ST_V = 0x1 +const SENS_COCPU_TOUCH_TIMEOUT_INT_ST_S = 9 +const SENS_COCPU_SWD_INT_ST_V = 0x1 +const SENS_COCPU_SWD_INT_ST_S = 8 +const SENS_COCPU_SW_INT_ST_V = 0x1 +const SENS_COCPU_SW_INT_ST_S = 7 +const SENS_COCPU_START_INT_ST_V = 0x1 +const SENS_COCPU_START_INT_ST_S = 6 +const SENS_COCPU_TSENS_INT_ST_V = 0x1 +const SENS_COCPU_TSENS_INT_ST_S = 5 +const SENS_COCPU_SARADC2_INT_ST_V = 0x1 +const SENS_COCPU_SARADC2_INT_ST_S = 4 +const SENS_COCPU_SARADC1_INT_ST_V = 0x1 +const SENS_COCPU_SARADC1_INT_ST_S = 3 +const SENS_COCPU_TOUCH_ACTIVE_INT_ST_V = 0x1 +const SENS_COCPU_TOUCH_ACTIVE_INT_ST_S = 2 +const SENS_COCPU_TOUCH_INACTIVE_INT_ST_V = 0x1 +const SENS_COCPU_TOUCH_INACTIVE_INT_ST_S = 1 +const SENS_COCPU_TOUCH_DONE_INT_ST_V = 0x1 +const SENS_COCPU_TOUCH_DONE_INT_ST_S = 0 +const SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_V = 0x1 +const SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_S = 11 +const SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V = 0x1 +const SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S = 10 +const SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_V = 0x1 +const SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_S = 9 +const SENS_COCPU_SWD_INT_CLR_V = 0x1 +const SENS_COCPU_SWD_INT_CLR_S = 8 +const SENS_COCPU_SW_INT_CLR_V = 0x1 +const SENS_COCPU_SW_INT_CLR_S = 7 +const SENS_COCPU_START_INT_CLR_V = 0x1 +const SENS_COCPU_START_INT_CLR_S = 6 +const SENS_COCPU_TSENS_INT_CLR_V = 0x1 +const SENS_COCPU_TSENS_INT_CLR_S = 5 +const SENS_COCPU_SARADC2_INT_CLR_V = 0x1 +const SENS_COCPU_SARADC2_INT_CLR_S = 4 +const SENS_COCPU_SARADC1_INT_CLR_V = 0x1 +const SENS_COCPU_SARADC1_INT_CLR_S = 3 +const SENS_COCPU_TOUCH_ACTIVE_INT_CLR_V = 0x1 +const SENS_COCPU_TOUCH_ACTIVE_INT_CLR_S = 2 +const SENS_COCPU_TOUCH_INACTIVE_INT_CLR_V = 0x1 +const SENS_COCPU_TOUCH_INACTIVE_INT_CLR_S = 1 +const SENS_COCPU_TOUCH_DONE_INT_CLR_V = 0x1 +const SENS_COCPU_TOUCH_DONE_INT_CLR_S = 0 +const SENS_COCPU_MEM_ADDR = 0x00001FFF +const SENS_COCPU_MEM_ADDR_V = 0x1FFF +const SENS_COCPU_MEM_ADDR_S = 19 +const SENS_COCPU_MEM_WEN = 0x0000000F +const SENS_COCPU_MEM_WEN_V = 0xF +const SENS_COCPU_MEM_WEN_S = 15 +const SENS_COCPU_MEM_RDY_V = 0x1 +const SENS_COCPU_MEM_RDY_S = 14 +const SENS_COCPU_MEM_VLD_V = 0x1 +const SENS_COCPU_MEM_VLD_S = 13 +const SENS_COCPU_PC = 0x00001FFF +const SENS_COCPU_PC_V = 0x1FFF +const SENS_COCPU_PC_S = 0 +const SENS_HALL_PHASE_FORCE_V = 0x1 +const SENS_HALL_PHASE_FORCE_S = 31 +const SENS_HALL_PHASE_V = 0x1 +const SENS_HALL_PHASE_S = 30 +const SENS_XPD_HALL_FORCE_V = 0x1 +const SENS_XPD_HALL_FORCE_S = 29 +const SENS_XPD_HALL_V = 0x1 +const SENS_XPD_HALL_S = 28 +const SENS_SAR_NOUSE = 0xFFFFFFFF +const SENS_SAR_NOUSE_V = 0xFFFFFFFF +const SENS_SAR_NOUSE_S = 0 +const SENS_IOMUX_CLK_EN_V = 0x1 +const SENS_IOMUX_CLK_EN_S = 31 +const SENS_SARADC_CLK_EN_V = 0x1 +const SENS_SARADC_CLK_EN_S = 30 +const SENS_TSENS_CLK_EN_V = 0x1 +const SENS_TSENS_CLK_EN_S = 29 +const SENS_RTC_I2C_CLK_EN_V = 0x1 +const SENS_RTC_I2C_CLK_EN_S = 27 +const SENS_SARADC_RESET_V = 0x1 +const SENS_SARADC_RESET_S = 30 +const SENS_TSENS_RESET_V = 0x1 +const SENS_TSENS_RESET_S = 29 +const SENS_RTC_I2C_RESET_V = 0x1 +const SENS_RTC_I2C_RESET_S = 27 +const SENS_COCPU_RESET_V = 0x1 +const SENS_COCPU_RESET_S = 25 +const SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_V = 0x1 +const SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_S = 11 +const SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V = 0x1 +const SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S = 10 +const SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_V = 0x1 +const SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_S = 9 +const SENS_COCPU_SWD_INT_ENA_W1TS_V = 0x1 +const SENS_COCPU_SWD_INT_ENA_W1TS_S = 8 +const SENS_COCPU_SW_INT_ENA_W1TS_V = 0x1 +const SENS_COCPU_SW_INT_ENA_W1TS_S = 7 +const SENS_COCPU_START_INT_ENA_W1TS_V = 0x1 +const SENS_COCPU_START_INT_ENA_W1TS_S = 6 +const SENS_COCPU_TSENS_INT_ENA_W1TS_V = 0x1 +const SENS_COCPU_TSENS_INT_ENA_W1TS_S = 5 +const SENS_COCPU_SARADC2_INT_ENA_W1TS_V = 0x1 +const SENS_COCPU_SARADC2_INT_ENA_W1TS_S = 4 +const SENS_COCPU_SARADC1_INT_ENA_W1TS_V = 0x1 +const SENS_COCPU_SARADC1_INT_ENA_W1TS_S = 3 +const SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_V = 0x1 +const SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_S = 2 +const SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_V = 0x1 +const SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_S = 1 +const SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_V = 0x1 +const SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_S = 0 +const SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_V = 0x1 +const SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_S = 11 +const SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V = 0x1 +const SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S = 10 +const SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_V = 0x1 +const SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_S = 9 +const SENS_COCPU_SWD_INT_ENA_W1TC_V = 0x1 +const SENS_COCPU_SWD_INT_ENA_W1TC_S = 8 +const SENS_COCPU_SW_INT_ENA_W1TC_V = 0x1 +const SENS_COCPU_SW_INT_ENA_W1TC_S = 7 +const SENS_COCPU_START_INT_ENA_W1TC_V = 0x1 +const SENS_COCPU_START_INT_ENA_W1TC_S = 6 +const SENS_COCPU_TSENS_INT_ENA_W1TC_V = 0x1 +const SENS_COCPU_TSENS_INT_ENA_W1TC_S = 5 +const SENS_COCPU_SARADC2_INT_ENA_W1TC_V = 0x1 +const SENS_COCPU_SARADC2_INT_ENA_W1TC_S = 4 +const SENS_COCPU_SARADC1_INT_ENA_W1TC_V = 0x1 +const SENS_COCPU_SARADC1_INT_ENA_W1TC_S = 3 +const SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_V = 0x1 +const SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_S = 2 +const SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_V = 0x1 +const SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_S = 1 +const SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_V = 0x1 +const SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_S = 0 +const SENS_DEBUG_BIT_SEL = 0x0000001F +const SENS_DEBUG_BIT_SEL_V = 0x1F +const SENS_DEBUG_BIT_SEL_S = 0 +const SENS_SAR_DATE = 0x0FFFFFFF +const SENS_SAR_DATE_V = 0xFFFFFFF +const SENS_SAR_DATE_S = 0 diff --git a/esp32/sensitive_reg.go b/esp32/sensitive_reg.go new file mode 100644 index 00000000..831079a6 --- /dev/null +++ b/esp32/sensitive_reg.go @@ -0,0 +1,2046 @@ +package freertos + +import _ "unsafe" + +const SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_V = 0x1 +const SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_S = 0 +const SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN = 0x000000FF +const SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V = 0xFF +const SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S = 0 +const SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V = 0x1 +const SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S = 0 +const SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V = 0x1 +const SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S = 0 +const SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V = 0x1 +const SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S = 0 +const SENSITIVE_INTERNAL_SRAM_CPU_USAGE = 0x0000007F +const SENSITIVE_INTERNAL_SRAM_CPU_USAGE_V = 0x7F +const SENSITIVE_INTERNAL_SRAM_CPU_USAGE_S = 4 +const SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE = 0x00000003 +const SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_V = 0x3 +const SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_S = 2 +const SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE = 0x00000003 +const SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_V = 0x3 +const SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_S = 0 +const SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC = 0x00000003 +const SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_V = 0x3 +const SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_S = 16 +const SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC = 0x00000003 +const SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_V = 0x3 +const SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_S = 14 +const SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE = 0x0000007F +const SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_V = 0x7F +const SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_S = 7 +const SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE = 0x0000007F +const SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_V = 0x7F +const SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_S = 0 +const SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE = 0x0000000F +const SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_V = 0xF +const SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_S = 0 +const SENSITIVE_INTERNAL_SRAM_LOG_USAGE = 0x0000007F +const SENSITIVE_INTERNAL_SRAM_LOG_USAGE_V = 0x7F +const SENSITIVE_INTERNAL_SRAM_LOG_USAGE_S = 0 +const SENSITIVE_RETENTION_DISABLE_V = 0x1 +const SENSITIVE_RETENTION_DISABLE_S = 0 +const SENSITIVE_CACHE_TAG_ACCESS_LOCK_V = 0x1 +const SENSITIVE_CACHE_TAG_ACCESS_LOCK_S = 0 +const SENSITIVE_PRO_D_TAG_WR_ACS_V = 0x1 +const SENSITIVE_PRO_D_TAG_WR_ACS_S = 3 +const SENSITIVE_PRO_D_TAG_RD_ACS_V = 0x1 +const SENSITIVE_PRO_D_TAG_RD_ACS_S = 2 +const SENSITIVE_PRO_I_TAG_WR_ACS_V = 0x1 +const SENSITIVE_PRO_I_TAG_WR_ACS_S = 1 +const SENSITIVE_PRO_I_TAG_RD_ACS_V = 0x1 +const SENSITIVE_PRO_I_TAG_RD_ACS_S = 0 +const SENSITIVE_CACHE_MMU_ACCESS_LOCK_V = 0x1 +const SENSITIVE_CACHE_MMU_ACCESS_LOCK_S = 0 +const SENSITIVE_PRO_MMU_WR_ACS_V = 0x1 +const SENSITIVE_PRO_MMU_WR_ACS_S = 1 +const SENSITIVE_PRO_MMU_RD_ACS_V = 0x1 +const SENSITIVE_PRO_MMU_RD_ACS_S = 0 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_V = 0x3 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_S = 6 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_V = 0x3 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_S = 4 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_V = 0x3 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_S = 2 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 = 0x00000003 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_V = 0x3 +const SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_S = 0 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V = 0x1 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S = 0 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V = 0x1 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S = 1 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V = 0x1 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S = 0 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR = 0x003FFFFF +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V = 0x3FFFFF +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S = 3 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD = 0x00000003 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V = 0x3 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S = 1 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V = 0x1 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S = 0 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN = 0x0000FFFF +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V = 0xFFFF +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S = 1 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V = 0x1 +const SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S = 0 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR = 0x000000FF +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V = 0xFF +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S = 14 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S = 12 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S = 10 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S = 8 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S = 6 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S = 4 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S = 2 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S = 0 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR = 0x000000FF +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V = 0xFF +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S = 14 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S = 12 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S = 10 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S = 8 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S = 6 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S = 4 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S = 2 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S = 0 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR = 0x000000FF +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V = 0xFF +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S = 14 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S = 12 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S = 10 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S = 8 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S = 6 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S = 4 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S = 2 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 = 0x00000003 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V = 0x3 +const SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S = 0 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR = 0x000000FF +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V = 0xFF +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S = 14 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S = 12 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S = 10 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S = 8 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S = 6 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S = 4 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S = 2 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S = 0 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR = 0x000000FF +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V = 0xFF +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S = 14 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S = 12 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S = 10 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S = 8 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S = 6 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S = 4 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S = 2 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S = 0 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS = 0x00000007 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V = 0x7 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S = 18 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 = 0x00000007 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V = 0x7 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S = 15 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 = 0x00000007 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V = 0x7 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S = 12 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 = 0x00000007 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V = 0x7 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S = 9 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 = 0x00000007 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V = 0x7 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S = 6 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 = 0x00000007 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V = 0x7 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S = 3 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 = 0x00000007 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V = 0x7 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S = 0 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS = 0x00000007 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V = 0x7 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S = 18 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 = 0x00000007 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V = 0x7 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S = 15 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 = 0x00000007 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V = 0x7 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S = 12 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 = 0x00000007 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V = 0x7 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S = 9 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 = 0x00000007 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V = 0x7 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S = 6 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 = 0x00000007 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V = 0x7 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S = 3 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 = 0x00000007 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V = 0x7 +const SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S = 0 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V = 0x1 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S = 0 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V = 0x1 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S = 1 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V = 0x1 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S = 0 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR = 0x00FFFFFF +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V = 0xFFFFFF +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S = 5 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD = 0x00000003 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V = 0x3 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S = 3 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V = 0x1 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S = 2 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V = 0x1 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S = 1 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V = 0x1 +const SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S = 0 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_V = 0x1 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_S = 0 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_V = 0x1 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_S = 1 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_V = 0x1 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_S = 0 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR = 0x00FFFFFF +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V = 0xFFFFFF +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S = 5 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD = 0x00000003 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V = 0x3 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S = 3 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V = 0x1 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S = 2 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V = 0x1 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S = 1 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_V = 0x1 +const SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_S = 0 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S = 26 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S = 24 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S = 22 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S = 20 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S = 18 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S = 16 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S = 14 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S = 12 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S = 10 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S = 8 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S = 6 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S = 4 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S = 2 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 = 0x00000003 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V = 0x3 +const SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S = 0 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V = 0x1 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S = 0 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V = 0x1 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S = 1 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V = 0x1 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S = 0 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR = 0x003FFFFF +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V = 0x3FFFFF +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S = 4 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD = 0x00000003 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V = 0x3 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S = 2 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V = 0x1 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S = 1 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V = 0x1 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S = 0 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN = 0x0000FFFF +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V = 0xFFFF +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S = 1 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V = 0x1 +const SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S = 0 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_V = 0x1 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_S = 0 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_V = 0x1 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_S = 1 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_V = 0x1 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_S = 0 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR = 0x003FFFFF +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V = 0x3FFFFF +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S = 4 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD = 0x00000003 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V = 0x3 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S = 2 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V = 0x1 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S = 1 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_V = 0x1 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_S = 0 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN = 0x0000FFFF +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V = 0xFFFF +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S = 1 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V = 0x1 +const SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S = 30 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S = 28 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S = 26 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S = 24 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S = 20 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S = 16 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S = 14 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S = 10 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S = 8 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S = 6 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S = 4 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S = 2 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S = 30 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S = 28 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S = 26 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S = 24 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S = 22 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S = 18 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S = 16 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S = 14 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S = 12 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S = 10 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S = 8 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S = 6 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S = 4 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S = 28 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S = 26 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S = 22 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S = 16 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S = 14 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S = 12 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S = 10 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S = 8 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S = 6 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S = 4 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S = 2 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S = 30 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S = 28 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S = 26 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S = 24 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S = 22 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S = 20 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S = 18 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S = 16 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S = 14 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S = 12 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S = 10 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S = 8 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S = 6 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S = 4 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S = 2 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S = 30 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S = 28 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S = 26 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S = 24 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S = 20 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S = 16 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S = 14 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S = 10 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S = 8 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S = 6 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S = 4 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S = 2 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S = 30 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S = 28 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S = 26 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S = 24 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S = 22 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S = 18 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S = 16 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S = 14 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S = 12 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S = 10 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S = 8 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S = 6 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S = 4 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S = 28 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S = 26 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S = 22 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S = 16 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S = 14 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S = 12 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S = 10 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S = 8 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S = 6 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S = 4 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S = 2 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S = 30 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S = 28 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S = 26 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S = 24 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S = 22 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S = 20 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S = 18 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S = 16 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S = 14 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S = 12 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S = 10 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S = 8 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S = 6 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S = 4 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S = 2 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 = 0x000007FF +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V = 0x7FF +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S = 11 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 = 0x000007FF +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V = 0x7FF +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H = 0x00000007 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V = 0x7 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S = 9 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L = 0x00000007 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V = 0x7 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S = 6 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H = 0x00000007 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V = 0x7 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S = 3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L = 0x00000007 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V = 0x7 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 = 0x000007FF +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V = 0x7FF +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S = 11 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 = 0x000007FF +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V = 0x7FF +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H = 0x00000007 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V = 0x7 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S = 9 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L = 0x00000007 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V = 0x7 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S = 6 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H = 0x00000007 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V = 0x7 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S = 3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L = 0x00000007 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V = 0x7 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 = 0x000007FF +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V = 0x7FF +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S = 11 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 = 0x000007FF +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V = 0x7FF +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H = 0x00000007 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V = 0x7 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S = 9 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L = 0x00000007 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V = 0x7 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S = 6 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H = 0x00000007 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V = 0x7 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S = 3 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L = 0x00000007 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V = 0x7 +const SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S = 20 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S = 18 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S = 16 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S = 14 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S = 12 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S = 10 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S = 8 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S = 6 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S = 4 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S = 2 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S = 20 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S = 18 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S = 16 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S = 14 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S = 12 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S = 10 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S = 8 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S = 6 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S = 4 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S = 2 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 = 0x00000003 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V = 0x3 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_V = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_V = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_V = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_V = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_V = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_V = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_V = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_V = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_V = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_V = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_V = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_S = 0 +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_V = 0x3FFFFFFF +const SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V = 0x1 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V = 0x1 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S = 1 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V = 0x1 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S = 6 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V = 0x1 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S = 5 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE = 0x00000007 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V = 0x7 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S = 2 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V = 0x1 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S = 1 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V = 0x1 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR = 0xFFFFFFFF +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V = 0xFFFFFFFF +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V = 0x1 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S = 1 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V = 0x1 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S = 3 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE = 0x00000003 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V = 0x3 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S = 1 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V = 0x1 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S = 0 +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR = 0xFFFFFFFF +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V = 0xFFFFFFFF +const SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S = 0 +const SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_V = 0x1 +const SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_S = 0 +const SENSITIVE_CORE_0_VECBASE_WORLD_MASK_V = 0x1 +const SENSITIVE_CORE_0_VECBASE_WORLD_MASK_S = 0 +const SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL = 0x00000003 +const SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V = 0x3 +const SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S = 22 +const SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE = 0x003FFFFF +const SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_V = 0x3FFFFF +const SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_S = 0 +const SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE = 0x003FFFFF +const SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_V = 0x3FFFFF +const SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_S = 0 +const SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V = 0x1 +const SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S = 0 +const SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_V = 0x1 +const SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S = 30 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S = 28 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S = 26 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S = 24 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S = 20 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S = 16 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S = 14 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S = 10 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S = 8 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S = 6 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S = 4 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S = 2 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S = 30 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S = 28 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S = 26 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S = 24 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S = 22 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S = 18 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S = 16 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S = 14 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S = 12 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S = 10 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S = 8 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S = 6 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S = 4 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S = 28 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S = 26 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S = 22 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S = 16 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S = 14 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S = 12 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S = 10 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S = 8 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S = 6 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S = 4 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S = 2 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S = 30 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S = 28 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S = 26 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S = 24 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S = 22 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S = 20 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S = 18 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S = 16 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S = 14 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S = 12 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S = 10 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S = 8 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S = 6 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S = 4 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S = 2 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S = 30 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S = 28 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S = 26 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S = 24 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S = 20 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S = 16 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S = 14 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S = 10 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S = 8 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S = 6 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S = 4 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S = 2 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S = 30 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S = 28 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S = 26 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S = 24 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S = 22 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S = 18 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S = 16 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S = 14 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S = 12 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S = 10 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S = 8 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S = 6 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S = 4 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S = 28 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S = 26 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S = 22 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S = 16 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S = 14 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S = 12 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S = 10 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S = 8 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S = 6 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S = 4 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S = 2 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S = 30 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S = 28 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S = 26 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S = 24 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S = 22 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S = 20 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S = 18 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S = 16 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S = 14 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S = 12 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S = 10 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S = 8 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S = 6 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S = 4 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S = 2 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 = 0x000007FF +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V = 0x7FF +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S = 11 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 = 0x000007FF +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V = 0x7FF +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H = 0x00000007 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V = 0x7 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S = 9 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L = 0x00000007 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V = 0x7 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S = 6 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H = 0x00000007 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V = 0x7 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S = 3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L = 0x00000007 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V = 0x7 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 = 0x000007FF +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V = 0x7FF +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S = 11 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 = 0x000007FF +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V = 0x7FF +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H = 0x00000007 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V = 0x7 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S = 9 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L = 0x00000007 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V = 0x7 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S = 6 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H = 0x00000007 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V = 0x7 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S = 3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L = 0x00000007 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V = 0x7 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 = 0x000007FF +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V = 0x7FF +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S = 11 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 = 0x000007FF +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V = 0x7FF +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H = 0x00000007 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V = 0x7 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S = 9 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L = 0x00000007 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V = 0x7 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S = 6 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H = 0x00000007 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V = 0x7 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S = 3 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L = 0x00000007 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V = 0x7 +const SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S = 20 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S = 18 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S = 16 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S = 14 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S = 12 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S = 10 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S = 8 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S = 6 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S = 4 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S = 2 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S = 20 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S = 18 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S = 16 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S = 14 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S = 12 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S = 10 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S = 8 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S = 6 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S = 4 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S = 2 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 = 0x00000003 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V = 0x3 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_V = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_V = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_V = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_V = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_V = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_V = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_V = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_V = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_V = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_V = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_V = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_S = 0 +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_V = 0x3FFFFFFF +const SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_V = 0x1 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_V = 0x1 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_S = 1 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_V = 0x1 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S = 6 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V = 0x1 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S = 5 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE = 0x00000007 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V = 0x7 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S = 2 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V = 0x1 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S = 1 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_V = 0x1 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR = 0xFFFFFFFF +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V = 0xFFFFFFFF +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V = 0x1 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S = 1 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V = 0x1 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S = 3 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE = 0x00000003 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V = 0x3 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S = 1 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V = 0x1 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S = 0 +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR = 0xFFFFFFFF +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V = 0xFFFFFFFF +const SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S = 0 +const SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_V = 0x1 +const SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_S = 0 +const SENSITIVE_CORE_1_VECBASE_WORLD_MASK_V = 0x1 +const SENSITIVE_CORE_1_VECBASE_WORLD_MASK_S = 0 +const SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL = 0x00000003 +const SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V = 0x3 +const SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S = 22 +const SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE = 0x003FFFFF +const SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_V = 0x3FFFFF +const SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_S = 0 +const SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE = 0x003FFFFF +const SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_V = 0x3FFFFF +const SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_S = 0 +const SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V = 0x1 +const SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S = 0 +const SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_V = 0x1 +const SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_S = 0 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V = 0x1 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S = 0 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S = 30 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S = 28 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S = 26 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S = 24 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_S = 20 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S = 16 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S = 14 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S = 10 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S = 8 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S = 6 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S = 4 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S = 2 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S = 0 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S = 30 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S = 28 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S = 26 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_S = 24 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S = 22 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_S = 18 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S = 16 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_S = 14 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_S = 12 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S = 10 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_S = 8 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S = 6 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S = 4 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S = 0 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S = 28 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S = 26 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S = 22 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_S = 16 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S = 14 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_S = 12 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S = 10 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_S = 8 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_S = 6 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S = 4 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_S = 2 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S = 0 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_S = 30 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_S = 28 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_S = 26 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_S = 24 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_S = 22 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_S = 20 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_S = 18 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_S = 16 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_S = 14 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S = 12 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_S = 10 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S = 8 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S = 6 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S = 4 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S = 2 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S = 0 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR = 0x000007FF +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_V = 0x7FF +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_S = 0 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H = 0x00000007 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_V = 0x7 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_S = 3 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L = 0x00000007 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_V = 0x7 +const SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_S = 0 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V = 0x1 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S = 0 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V = 0x1 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S = 1 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V = 0x1 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S = 0 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V = 0x1 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S = 6 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE = 0x00000007 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V = 0x7 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S = 3 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS = 0x00000003 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V = 0x3 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S = 1 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V = 0x1 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S = 0 +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR = 0xFFFFFFFF +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V = 0xFFFFFFFF +const SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S = 0 +const SENSITIVE_EDMA_BOUNDARY_LOCK_V = 0x1 +const SENSITIVE_EDMA_BOUNDARY_LOCK_S = 0 +const SENSITIVE_EDMA_BOUNDARY_0 = 0x00003FFF +const SENSITIVE_EDMA_BOUNDARY_0_V = 0x3FFF +const SENSITIVE_EDMA_BOUNDARY_0_S = 0 +const SENSITIVE_EDMA_BOUNDARY_1 = 0x00003FFF +const SENSITIVE_EDMA_BOUNDARY_1_V = 0x3FFF +const SENSITIVE_EDMA_BOUNDARY_1_S = 0 +const SENSITIVE_EDMA_BOUNDARY_2 = 0x00003FFF +const SENSITIVE_EDMA_BOUNDARY_2_V = 0x3FFF +const SENSITIVE_EDMA_BOUNDARY_2_S = 0 +const SENSITIVE_EDMA_PMS_SPI2_LOCK_V = 0x1 +const SENSITIVE_EDMA_PMS_SPI2_LOCK_S = 0 +const SENSITIVE_EDMA_PMS_SPI2_ATTR2 = 0x00000003 +const SENSITIVE_EDMA_PMS_SPI2_ATTR2_V = 0x3 +const SENSITIVE_EDMA_PMS_SPI2_ATTR2_S = 2 +const SENSITIVE_EDMA_PMS_SPI2_ATTR1 = 0x00000003 +const SENSITIVE_EDMA_PMS_SPI2_ATTR1_V = 0x3 +const SENSITIVE_EDMA_PMS_SPI2_ATTR1_S = 0 +const SENSITIVE_EDMA_PMS_SPI3_LOCK_V = 0x1 +const SENSITIVE_EDMA_PMS_SPI3_LOCK_S = 0 +const SENSITIVE_EDMA_PMS_SPI3_ATTR2 = 0x00000003 +const SENSITIVE_EDMA_PMS_SPI3_ATTR2_V = 0x3 +const SENSITIVE_EDMA_PMS_SPI3_ATTR2_S = 2 +const SENSITIVE_EDMA_PMS_SPI3_ATTR1 = 0x00000003 +const SENSITIVE_EDMA_PMS_SPI3_ATTR1_V = 0x3 +const SENSITIVE_EDMA_PMS_SPI3_ATTR1_S = 0 +const SENSITIVE_EDMA_PMS_UHCI0_LOCK_V = 0x1 +const SENSITIVE_EDMA_PMS_UHCI0_LOCK_S = 0 +const SENSITIVE_EDMA_PMS_UHCI0_ATTR2 = 0x00000003 +const SENSITIVE_EDMA_PMS_UHCI0_ATTR2_V = 0x3 +const SENSITIVE_EDMA_PMS_UHCI0_ATTR2_S = 2 +const SENSITIVE_EDMA_PMS_UHCI0_ATTR1 = 0x00000003 +const SENSITIVE_EDMA_PMS_UHCI0_ATTR1_V = 0x3 +const SENSITIVE_EDMA_PMS_UHCI0_ATTR1_S = 0 +const SENSITIVE_EDMA_PMS_I2S0_LOCK_V = 0x1 +const SENSITIVE_EDMA_PMS_I2S0_LOCK_S = 0 +const SENSITIVE_EDMA_PMS_I2S0_ATTR2 = 0x00000003 +const SENSITIVE_EDMA_PMS_I2S0_ATTR2_V = 0x3 +const SENSITIVE_EDMA_PMS_I2S0_ATTR2_S = 2 +const SENSITIVE_EDMA_PMS_I2S0_ATTR1 = 0x00000003 +const SENSITIVE_EDMA_PMS_I2S0_ATTR1_V = 0x3 +const SENSITIVE_EDMA_PMS_I2S0_ATTR1_S = 0 +const SENSITIVE_EDMA_PMS_I2S1_LOCK_V = 0x1 +const SENSITIVE_EDMA_PMS_I2S1_LOCK_S = 0 +const SENSITIVE_EDMA_PMS_I2S1_ATTR2 = 0x00000003 +const SENSITIVE_EDMA_PMS_I2S1_ATTR2_V = 0x3 +const SENSITIVE_EDMA_PMS_I2S1_ATTR2_S = 2 +const SENSITIVE_EDMA_PMS_I2S1_ATTR1 = 0x00000003 +const SENSITIVE_EDMA_PMS_I2S1_ATTR1_V = 0x3 +const SENSITIVE_EDMA_PMS_I2S1_ATTR1_S = 0 +const SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_V = 0x1 +const SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_S = 0 +const SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2 = 0x00000003 +const SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_V = 0x3 +const SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_S = 2 +const SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1 = 0x00000003 +const SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_V = 0x3 +const SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_S = 0 +const SENSITIVE_EDMA_PMS_AES_LOCK_V = 0x1 +const SENSITIVE_EDMA_PMS_AES_LOCK_S = 0 +const SENSITIVE_EDMA_PMS_AES_ATTR2 = 0x00000003 +const SENSITIVE_EDMA_PMS_AES_ATTR2_V = 0x3 +const SENSITIVE_EDMA_PMS_AES_ATTR2_S = 2 +const SENSITIVE_EDMA_PMS_AES_ATTR1 = 0x00000003 +const SENSITIVE_EDMA_PMS_AES_ATTR1_V = 0x3 +const SENSITIVE_EDMA_PMS_AES_ATTR1_S = 0 +const SENSITIVE_EDMA_PMS_SHA_LOCK_V = 0x1 +const SENSITIVE_EDMA_PMS_SHA_LOCK_S = 0 +const SENSITIVE_EDMA_PMS_SHA_ATTR2 = 0x00000003 +const SENSITIVE_EDMA_PMS_SHA_ATTR2_V = 0x3 +const SENSITIVE_EDMA_PMS_SHA_ATTR2_S = 2 +const SENSITIVE_EDMA_PMS_SHA_ATTR1 = 0x00000003 +const SENSITIVE_EDMA_PMS_SHA_ATTR1_V = 0x3 +const SENSITIVE_EDMA_PMS_SHA_ATTR1_S = 0 +const SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_V = 0x1 +const SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_S = 0 +const SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2 = 0x00000003 +const SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_V = 0x3 +const SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_S = 2 +const SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1 = 0x00000003 +const SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_V = 0x3 +const SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_S = 0 +const SENSITIVE_EDMA_PMS_RMT_LOCK_V = 0x1 +const SENSITIVE_EDMA_PMS_RMT_LOCK_S = 0 +const SENSITIVE_EDMA_PMS_RMT_ATTR2 = 0x00000003 +const SENSITIVE_EDMA_PMS_RMT_ATTR2_V = 0x3 +const SENSITIVE_EDMA_PMS_RMT_ATTR2_S = 2 +const SENSITIVE_EDMA_PMS_RMT_ATTR1 = 0x00000003 +const SENSITIVE_EDMA_PMS_RMT_ATTR1_V = 0x3 +const SENSITIVE_EDMA_PMS_RMT_ATTR1_S = 0 +const SENSITIVE_CLK_EN_V = 0x1 +const SENSITIVE_CLK_EN_S = 0 +const SENSITIVE_DIS_RTC_CPU_V = 0x1 +const SENSITIVE_DIS_RTC_CPU_S = 0 +const SENSITIVE_DATE = 0x0FFFFFFF +const SENSITIVE_DATE_V = 0xFFFFFFF +const SENSITIVE_DATE_S = 0 diff --git a/esp32/sensitive_struct.go b/esp32/sensitive_struct.go new file mode 100644 index 00000000..456237a3 --- /dev/null +++ b/esp32/sensitive_struct.go @@ -0,0 +1,1418 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type SensitiveDevS struct { + CacheDataarrayConnect0 struct { + Val c.Uint32T + } + CacheDataarrayConnect1 struct { + Val c.Uint32T + } + ApbPeripheralAccess0 struct { + Val c.Uint32T + } + ApbPeripheralAccess1 struct { + Val c.Uint32T + } + InternalSramUsage0 struct { + Val c.Uint32T + } + InternalSramUsage1 struct { + Val c.Uint32T + } + InternalSramUsage2 struct { + Val c.Uint32T + } + InternalSramUsage3 struct { + Val c.Uint32T + } + InternalSramUsage4 struct { + Val c.Uint32T + } + RetentionDisable struct { + Val c.Uint32T + } + CacheTagAccess0 struct { + Val c.Uint32T + } + CacheTagAccess1 struct { + Val c.Uint32T + } + CacheMmuAccess0 struct { + Val c.Uint32T + } + CacheMmuAccess1 struct { + Val c.Uint32T + } + DmaApbperiSpi2PmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiSpi2PmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiSpi3PmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiSpi3PmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiUhci0PmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiUhci0PmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiI2s0PmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiI2s0PmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiI2s1PmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiI2s1PmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiMacPmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiMacPmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiBackupPmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiBackupPmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiAesPmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiAesPmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiShaPmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiShaPmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiAdcDacPmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiAdcDacPmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiRmtPmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiRmtPmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiLcdCamPmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiLcdCamPmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiUsbPmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiUsbPmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiLcPmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiLcPmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiSdioPmsConstrain0 struct { + Val c.Uint32T + } + DmaApbperiSdioPmsConstrain1 struct { + Val c.Uint32T + } + DmaApbperiPmsMonitor0 struct { + Val c.Uint32T + } + DmaApbperiPmsMonitor1 struct { + Val c.Uint32T + } + DmaApbperiPmsMonitor2 struct { + Val c.Uint32T + } + DmaApbperiPmsMonitor3 struct { + Val c.Uint32T + } + CoreXIram0Dram0DmaSplitLineConstrain0 struct { + Val c.Uint32T + } + CoreXIram0Dram0DmaSplitLineConstrain1 struct { + Val c.Uint32T + } + CoreXIram0Dram0DmaSplitLineConstrain2 struct { + Val c.Uint32T + } + CoreXIram0Dram0DmaSplitLineConstrain3 struct { + Val c.Uint32T + } + CoreXIram0Dram0DmaSplitLineConstrain4 struct { + Val c.Uint32T + } + CoreXIram0Dram0DmaSplitLineConstrain5 struct { + Val c.Uint32T + } + CoreXIram0PmsConstrain0 struct { + Val c.Uint32T + } + CoreXIram0PmsConstrain1 struct { + Val c.Uint32T + } + CoreXIram0PmsConstrain2 struct { + Val c.Uint32T + } + Core0Iram0PmsMonitor0 struct { + Val c.Uint32T + } + Core0Iram0PmsMonitor1 struct { + Val c.Uint32T + } + Core0Iram0PmsMonitor2 struct { + Val c.Uint32T + } + Core1Iram0PmsMonitor0 struct { + Val c.Uint32T + } + Core1Iram0PmsMonitor1 struct { + Val c.Uint32T + } + Core1Iram0PmsMonitor2 struct { + Val c.Uint32T + } + CoreXDram0PmsConstrain0 struct { + Val c.Uint32T + } + CoreXDram0PmsConstrain1 struct { + Val c.Uint32T + } + Core0Dram0PmsMonitor0 struct { + Val c.Uint32T + } + Core0Dram0PmsMonitor1 struct { + Val c.Uint32T + } + Core0Dram0PmsMonitor2 struct { + Val c.Uint32T + } + Core0Dram0PmsMonitor3 struct { + Val c.Uint32T + } + Core1Dram0PmsMonitor0 struct { + Val c.Uint32T + } + Core1Dram0PmsMonitor1 struct { + Val c.Uint32T + } + Core1Dram0PmsMonitor2 struct { + Val c.Uint32T + } + Core1Dram0PmsMonitor3 struct { + Val c.Uint32T + } + Core0PifPmsConstrain0 struct { + Val c.Uint32T + } + Core0PifPmsConstrain1 struct { + Val c.Uint32T + } + Core0PifPmsConstrain2 struct { + Val c.Uint32T + } + Core0PifPmsConstrain3 struct { + Val c.Uint32T + } + Core0PifPmsConstrain4 struct { + Val c.Uint32T + } + Core0PifPmsConstrain5 struct { + Val c.Uint32T + } + Core0PifPmsConstrain6 struct { + Val c.Uint32T + } + Core0PifPmsConstrain7 struct { + Val c.Uint32T + } + Core0PifPmsConstrain8 struct { + Val c.Uint32T + } + Core0PifPmsConstrain9 struct { + Val c.Uint32T + } + Core0PifPmsConstrain10 struct { + Val c.Uint32T + } + Core0PifPmsConstrain11 struct { + Val c.Uint32T + } + Core0PifPmsConstrain12 struct { + Val c.Uint32T + } + Core0PifPmsConstrain13 struct { + Val c.Uint32T + } + Core0PifPmsConstrain14 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain0 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain1 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain2 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain3 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain4 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain5 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain6 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain7 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain8 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain9 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain10 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain11 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain12 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain13 struct { + Val c.Uint32T + } + Core0RegionPmsConstrain14 struct { + Val c.Uint32T + } + Core0PifPmsMonitor0 struct { + Val c.Uint32T + } + Core0PifPmsMonitor1 struct { + Val c.Uint32T + } + Core0PifPmsMonitor2 struct { + Val c.Uint32T + } + Core0PifPmsMonitor3 c.Uint32T + Core0PifPmsMonitor4 struct { + Val c.Uint32T + } + Core0PifPmsMonitor5 struct { + Val c.Uint32T + } + Core0PifPmsMonitor6 c.Uint32T + Core0VecbaseOverrideLock struct { + Val c.Uint32T + } + Core0VecbaseOverride0 struct { + Val c.Uint32T + } + Core0VecbaseOverride1 struct { + Val c.Uint32T + } + Core0VecbaseOverride2 struct { + Val c.Uint32T + } + Core0ToomanyexceptionsMOverride0 struct { + Val c.Uint32T + } + Core0ToomanyexceptionsMOverride1 struct { + Val c.Uint32T + } + Core1PifPmsConstrain0 struct { + Val c.Uint32T + } + Core1PifPmsConstrain1 struct { + Val c.Uint32T + } + Core1PifPmsConstrain2 struct { + Val c.Uint32T + } + Core1PifPmsConstrain3 struct { + Val c.Uint32T + } + Core1PifPmsConstrain4 struct { + Val c.Uint32T + } + Core1PifPmsConstrain5 struct { + Val c.Uint32T + } + Core1PifPmsConstrain6 struct { + Val c.Uint32T + } + Core1PifPmsConstrain7 struct { + Val c.Uint32T + } + Core1PifPmsConstrain8 struct { + Val c.Uint32T + } + Core1PifPmsConstrain9 struct { + Val c.Uint32T + } + Core1PifPmsConstrain10 struct { + Val c.Uint32T + } + Core1PifPmsConstrain11 struct { + Val c.Uint32T + } + Core1PifPmsConstrain12 struct { + Val c.Uint32T + } + Core1PifPmsConstrain13 struct { + Val c.Uint32T + } + Core1PifPmsConstrain14 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain0 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain1 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain2 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain3 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain4 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain5 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain6 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain7 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain8 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain9 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain10 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain11 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain12 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain13 struct { + Val c.Uint32T + } + Core1RegionPmsConstrain14 struct { + Val c.Uint32T + } + Core1PifPmsMonitor0 struct { + Val c.Uint32T + } + Core1PifPmsMonitor1 struct { + Val c.Uint32T + } + Core1PifPmsMonitor2 struct { + Val c.Uint32T + } + Core1PifPmsMonitor3 c.Uint32T + Core1PifPmsMonitor4 struct { + Val c.Uint32T + } + Core1PifPmsMonitor5 struct { + Val c.Uint32T + } + Core1PifPmsMonitor6 c.Uint32T + Core1VecbaseOverrideLock struct { + Val c.Uint32T + } + Core1VecbaseOverride0 struct { + Val c.Uint32T + } + Core1VecbaseOverride1 struct { + Val c.Uint32T + } + Core1VecbaseOverride2 struct { + Val c.Uint32T + } + Core1ToomanyexceptionsMOverride0 struct { + Val c.Uint32T + } + Core1ToomanyexceptionsMOverride1 struct { + Val c.Uint32T + } + BackupBusPmsConstrain0 struct { + Val c.Uint32T + } + BackupBusPmsConstrain1 struct { + Val c.Uint32T + } + BackupBusPmsConstrain2 struct { + Val c.Uint32T + } + BackupBusPmsConstrain3 struct { + Val c.Uint32T + } + BackupBusPmsConstrain4 struct { + Val c.Uint32T + } + BackupBusPmsConstrain5 struct { + Val c.Uint32T + } + BackupBusPmsConstrain6 struct { + Val c.Uint32T + } + BackupBusPmsMonitor0 struct { + Val c.Uint32T + } + BackupBusPmsMonitor1 struct { + Val c.Uint32T + } + BackupBusPmsMonitor2 struct { + Val c.Uint32T + } + BackupBusPmsMonitor3 c.Uint32T + EdmaBoundaryLock struct { + Val c.Uint32T + } + EdmaBoundary0 struct { + Val c.Uint32T + } + EdmaBoundary1 struct { + Val c.Uint32T + } + EdmaBoundary2 struct { + Val c.Uint32T + } + EdmaPmsSpi2Lock struct { + Val c.Uint32T + } + EdmaPmsSpi2 struct { + Val c.Uint32T + } + EdmaPmsSpi3Lock struct { + Val c.Uint32T + } + EdmaPmsSpi3 struct { + Val c.Uint32T + } + EdmaPmsUhci0Lock struct { + Val c.Uint32T + } + EdmaPmsUhci0 struct { + Val c.Uint32T + } + EdmaPmsI2s0Lock struct { + Val c.Uint32T + } + EdmaPmsI2s0 struct { + Val c.Uint32T + } + EdmaPmsI2s1Lock struct { + Val c.Uint32T + } + EdmaPmsI2s1 struct { + Val c.Uint32T + } + EdmaPmsLcdCamLock struct { + Val c.Uint32T + } + EdmaPmsLcdCam struct { + Val c.Uint32T + } + EdmaPmsAesLock struct { + Val c.Uint32T + } + EdmaPmsAes struct { + Val c.Uint32T + } + EdmaPmsShaLock struct { + Val c.Uint32T + } + EdmaPmsSha struct { + Val c.Uint32T + } + EdmaPmsAdcDacLock struct { + Val c.Uint32T + } + EdmaPmsAdcDac struct { + Val c.Uint32T + } + EdmaPmsRmtLock struct { + Val c.Uint32T + } + EdmaPmsRmt struct { + Val c.Uint32T + } + ClockGate struct { + Val c.Uint32T + } + RtcPms struct { + Val c.Uint32T + } + Reserved310 c.Uint32T + Reserved314 c.Uint32T + Reserved318 c.Uint32T + Reserved31c c.Uint32T + Reserved320 c.Uint32T + Reserved324 c.Uint32T + Reserved328 c.Uint32T + Reserved32c c.Uint32T + Reserved330 c.Uint32T + Reserved334 c.Uint32T + Reserved338 c.Uint32T + Reserved33c c.Uint32T + Reserved340 c.Uint32T + Reserved344 c.Uint32T + Reserved348 c.Uint32T + Reserved34c c.Uint32T + Reserved350 c.Uint32T + Reserved354 c.Uint32T + Reserved358 c.Uint32T + Reserved35c c.Uint32T + Reserved360 c.Uint32T + Reserved364 c.Uint32T + Reserved368 c.Uint32T + Reserved36c c.Uint32T + Reserved370 c.Uint32T + Reserved374 c.Uint32T + Reserved378 c.Uint32T + Reserved37c c.Uint32T + Reserved380 c.Uint32T + Reserved384 c.Uint32T + Reserved388 c.Uint32T + Reserved38c c.Uint32T + Reserved390 c.Uint32T + Reserved394 c.Uint32T + Reserved398 c.Uint32T + Reserved39c c.Uint32T + Reserved3a0 c.Uint32T + Reserved3a4 c.Uint32T + Reserved3a8 c.Uint32T + Reserved3ac c.Uint32T + Reserved3b0 c.Uint32T + Reserved3b4 c.Uint32T + Reserved3b8 c.Uint32T + Reserved3bc c.Uint32T + Reserved3c0 c.Uint32T + Reserved3c4 c.Uint32T + Reserved3c8 c.Uint32T + Reserved3cc c.Uint32T + Reserved3d0 c.Uint32T + Reserved3d4 c.Uint32T + Reserved3d8 c.Uint32T + Reserved3dc c.Uint32T + Reserved3e0 c.Uint32T + Reserved3e4 c.Uint32T + Reserved3e8 c.Uint32T + Reserved3ec c.Uint32T + Reserved3f0 c.Uint32T + Reserved3f4 c.Uint32T + Reserved3f8 c.Uint32T + Reserved3fc c.Uint32T + Reserved400 c.Uint32T + Reserved404 c.Uint32T + Reserved408 c.Uint32T + Reserved40c c.Uint32T + Reserved410 c.Uint32T + Reserved414 c.Uint32T + Reserved418 c.Uint32T + Reserved41c c.Uint32T + Reserved420 c.Uint32T + Reserved424 c.Uint32T + Reserved428 c.Uint32T + Reserved42c c.Uint32T + Reserved430 c.Uint32T + Reserved434 c.Uint32T + Reserved438 c.Uint32T + Reserved43c c.Uint32T + Reserved440 c.Uint32T + Reserved444 c.Uint32T + Reserved448 c.Uint32T + Reserved44c c.Uint32T + Reserved450 c.Uint32T + Reserved454 c.Uint32T + Reserved458 c.Uint32T + Reserved45c c.Uint32T + Reserved460 c.Uint32T + Reserved464 c.Uint32T + Reserved468 c.Uint32T + Reserved46c c.Uint32T + Reserved470 c.Uint32T + Reserved474 c.Uint32T + Reserved478 c.Uint32T + Reserved47c c.Uint32T + Reserved480 c.Uint32T + Reserved484 c.Uint32T + Reserved488 c.Uint32T + Reserved48c c.Uint32T + Reserved490 c.Uint32T + Reserved494 c.Uint32T + Reserved498 c.Uint32T + Reserved49c c.Uint32T + Reserved4a0 c.Uint32T + Reserved4a4 c.Uint32T + Reserved4a8 c.Uint32T + Reserved4ac c.Uint32T + Reserved4b0 c.Uint32T + Reserved4b4 c.Uint32T + Reserved4b8 c.Uint32T + Reserved4bc c.Uint32T + Reserved4c0 c.Uint32T + Reserved4c4 c.Uint32T + Reserved4c8 c.Uint32T + Reserved4cc c.Uint32T + Reserved4d0 c.Uint32T + Reserved4d4 c.Uint32T + Reserved4d8 c.Uint32T + Reserved4dc c.Uint32T + Reserved4e0 c.Uint32T + Reserved4e4 c.Uint32T + Reserved4e8 c.Uint32T + Reserved4ec c.Uint32T + Reserved4f0 c.Uint32T + Reserved4f4 c.Uint32T + Reserved4f8 c.Uint32T + Reserved4fc c.Uint32T + Reserved500 c.Uint32T + Reserved504 c.Uint32T + Reserved508 c.Uint32T + Reserved50c c.Uint32T + Reserved510 c.Uint32T + Reserved514 c.Uint32T + Reserved518 c.Uint32T + Reserved51c c.Uint32T + Reserved520 c.Uint32T + Reserved524 c.Uint32T + Reserved528 c.Uint32T + Reserved52c c.Uint32T + Reserved530 c.Uint32T + Reserved534 c.Uint32T + Reserved538 c.Uint32T + Reserved53c c.Uint32T + Reserved540 c.Uint32T + Reserved544 c.Uint32T + Reserved548 c.Uint32T + Reserved54c c.Uint32T + Reserved550 c.Uint32T + Reserved554 c.Uint32T + Reserved558 c.Uint32T + Reserved55c c.Uint32T + Reserved560 c.Uint32T + Reserved564 c.Uint32T + Reserved568 c.Uint32T + Reserved56c c.Uint32T + Reserved570 c.Uint32T + Reserved574 c.Uint32T + Reserved578 c.Uint32T + Reserved57c c.Uint32T + Reserved580 c.Uint32T + Reserved584 c.Uint32T + Reserved588 c.Uint32T + Reserved58c c.Uint32T + Reserved590 c.Uint32T + Reserved594 c.Uint32T + Reserved598 c.Uint32T + Reserved59c c.Uint32T + Reserved5a0 c.Uint32T + Reserved5a4 c.Uint32T + Reserved5a8 c.Uint32T + Reserved5ac c.Uint32T + Reserved5b0 c.Uint32T + Reserved5b4 c.Uint32T + Reserved5b8 c.Uint32T + Reserved5bc c.Uint32T + Reserved5c0 c.Uint32T + Reserved5c4 c.Uint32T + Reserved5c8 c.Uint32T + Reserved5cc c.Uint32T + Reserved5d0 c.Uint32T + Reserved5d4 c.Uint32T + Reserved5d8 c.Uint32T + Reserved5dc c.Uint32T + Reserved5e0 c.Uint32T + Reserved5e4 c.Uint32T + Reserved5e8 c.Uint32T + Reserved5ec c.Uint32T + Reserved5f0 c.Uint32T + Reserved5f4 c.Uint32T + Reserved5f8 c.Uint32T + Reserved5fc c.Uint32T + Reserved600 c.Uint32T + Reserved604 c.Uint32T + Reserved608 c.Uint32T + Reserved60c c.Uint32T + Reserved610 c.Uint32T + Reserved614 c.Uint32T + Reserved618 c.Uint32T + Reserved61c c.Uint32T + Reserved620 c.Uint32T + Reserved624 c.Uint32T + Reserved628 c.Uint32T + Reserved62c c.Uint32T + Reserved630 c.Uint32T + Reserved634 c.Uint32T + Reserved638 c.Uint32T + Reserved63c c.Uint32T + Reserved640 c.Uint32T + Reserved644 c.Uint32T + Reserved648 c.Uint32T + Reserved64c c.Uint32T + Reserved650 c.Uint32T + Reserved654 c.Uint32T + Reserved658 c.Uint32T + Reserved65c c.Uint32T + Reserved660 c.Uint32T + Reserved664 c.Uint32T + Reserved668 c.Uint32T + Reserved66c c.Uint32T + Reserved670 c.Uint32T + Reserved674 c.Uint32T + Reserved678 c.Uint32T + Reserved67c c.Uint32T + Reserved680 c.Uint32T + Reserved684 c.Uint32T + Reserved688 c.Uint32T + Reserved68c c.Uint32T + Reserved690 c.Uint32T + Reserved694 c.Uint32T + Reserved698 c.Uint32T + Reserved69c c.Uint32T + Reserved6a0 c.Uint32T + Reserved6a4 c.Uint32T + Reserved6a8 c.Uint32T + Reserved6ac c.Uint32T + Reserved6b0 c.Uint32T + Reserved6b4 c.Uint32T + Reserved6b8 c.Uint32T + Reserved6bc c.Uint32T + Reserved6c0 c.Uint32T + Reserved6c4 c.Uint32T + Reserved6c8 c.Uint32T + Reserved6cc c.Uint32T + Reserved6d0 c.Uint32T + Reserved6d4 c.Uint32T + Reserved6d8 c.Uint32T + Reserved6dc c.Uint32T + Reserved6e0 c.Uint32T + Reserved6e4 c.Uint32T + Reserved6e8 c.Uint32T + Reserved6ec c.Uint32T + Reserved6f0 c.Uint32T + Reserved6f4 c.Uint32T + Reserved6f8 c.Uint32T + Reserved6fc c.Uint32T + Reserved700 c.Uint32T + Reserved704 c.Uint32T + Reserved708 c.Uint32T + Reserved70c c.Uint32T + Reserved710 c.Uint32T + Reserved714 c.Uint32T + Reserved718 c.Uint32T + Reserved71c c.Uint32T + Reserved720 c.Uint32T + Reserved724 c.Uint32T + Reserved728 c.Uint32T + Reserved72c c.Uint32T + Reserved730 c.Uint32T + Reserved734 c.Uint32T + Reserved738 c.Uint32T + Reserved73c c.Uint32T + Reserved740 c.Uint32T + Reserved744 c.Uint32T + Reserved748 c.Uint32T + Reserved74c c.Uint32T + Reserved750 c.Uint32T + Reserved754 c.Uint32T + Reserved758 c.Uint32T + Reserved75c c.Uint32T + Reserved760 c.Uint32T + Reserved764 c.Uint32T + Reserved768 c.Uint32T + Reserved76c c.Uint32T + Reserved770 c.Uint32T + Reserved774 c.Uint32T + Reserved778 c.Uint32T + Reserved77c c.Uint32T + Reserved780 c.Uint32T + Reserved784 c.Uint32T + Reserved788 c.Uint32T + Reserved78c c.Uint32T + Reserved790 c.Uint32T + Reserved794 c.Uint32T + Reserved798 c.Uint32T + Reserved79c c.Uint32T + Reserved7a0 c.Uint32T + Reserved7a4 c.Uint32T + Reserved7a8 c.Uint32T + Reserved7ac c.Uint32T + Reserved7b0 c.Uint32T + Reserved7b4 c.Uint32T + Reserved7b8 c.Uint32T + Reserved7bc c.Uint32T + Reserved7c0 c.Uint32T + Reserved7c4 c.Uint32T + Reserved7c8 c.Uint32T + Reserved7cc c.Uint32T + Reserved7d0 c.Uint32T + Reserved7d4 c.Uint32T + Reserved7d8 c.Uint32T + Reserved7dc c.Uint32T + Reserved7e0 c.Uint32T + Reserved7e4 c.Uint32T + Reserved7e8 c.Uint32T + Reserved7ec c.Uint32T + Reserved7f0 c.Uint32T + Reserved7f4 c.Uint32T + Reserved7f8 c.Uint32T + Reserved7fc c.Uint32T + Reserved800 c.Uint32T + Reserved804 c.Uint32T + Reserved808 c.Uint32T + Reserved80c c.Uint32T + Reserved810 c.Uint32T + Reserved814 c.Uint32T + Reserved818 c.Uint32T + Reserved81c c.Uint32T + Reserved820 c.Uint32T + Reserved824 c.Uint32T + Reserved828 c.Uint32T + Reserved82c c.Uint32T + Reserved830 c.Uint32T + Reserved834 c.Uint32T + Reserved838 c.Uint32T + Reserved83c c.Uint32T + Reserved840 c.Uint32T + Reserved844 c.Uint32T + Reserved848 c.Uint32T + Reserved84c c.Uint32T + Reserved850 c.Uint32T + Reserved854 c.Uint32T + Reserved858 c.Uint32T + Reserved85c c.Uint32T + Reserved860 c.Uint32T + Reserved864 c.Uint32T + Reserved868 c.Uint32T + Reserved86c c.Uint32T + Reserved870 c.Uint32T + Reserved874 c.Uint32T + Reserved878 c.Uint32T + Reserved87c c.Uint32T + Reserved880 c.Uint32T + Reserved884 c.Uint32T + Reserved888 c.Uint32T + Reserved88c c.Uint32T + Reserved890 c.Uint32T + Reserved894 c.Uint32T + Reserved898 c.Uint32T + Reserved89c c.Uint32T + Reserved8a0 c.Uint32T + Reserved8a4 c.Uint32T + Reserved8a8 c.Uint32T + Reserved8ac c.Uint32T + Reserved8b0 c.Uint32T + Reserved8b4 c.Uint32T + Reserved8b8 c.Uint32T + Reserved8bc c.Uint32T + Reserved8c0 c.Uint32T + Reserved8c4 c.Uint32T + Reserved8c8 c.Uint32T + Reserved8cc c.Uint32T + Reserved8d0 c.Uint32T + Reserved8d4 c.Uint32T + Reserved8d8 c.Uint32T + Reserved8dc c.Uint32T + Reserved8e0 c.Uint32T + Reserved8e4 c.Uint32T + Reserved8e8 c.Uint32T + Reserved8ec c.Uint32T + Reserved8f0 c.Uint32T + Reserved8f4 c.Uint32T + Reserved8f8 c.Uint32T + Reserved8fc c.Uint32T + Reserved900 c.Uint32T + Reserved904 c.Uint32T + Reserved908 c.Uint32T + Reserved90c c.Uint32T + Reserved910 c.Uint32T + Reserved914 c.Uint32T + Reserved918 c.Uint32T + Reserved91c c.Uint32T + Reserved920 c.Uint32T + Reserved924 c.Uint32T + Reserved928 c.Uint32T + Reserved92c c.Uint32T + Reserved930 c.Uint32T + Reserved934 c.Uint32T + Reserved938 c.Uint32T + Reserved93c c.Uint32T + Reserved940 c.Uint32T + Reserved944 c.Uint32T + Reserved948 c.Uint32T + Reserved94c c.Uint32T + Reserved950 c.Uint32T + Reserved954 c.Uint32T + Reserved958 c.Uint32T + Reserved95c c.Uint32T + Reserved960 c.Uint32T + Reserved964 c.Uint32T + Reserved968 c.Uint32T + Reserved96c c.Uint32T + Reserved970 c.Uint32T + Reserved974 c.Uint32T + Reserved978 c.Uint32T + Reserved97c c.Uint32T + Reserved980 c.Uint32T + Reserved984 c.Uint32T + Reserved988 c.Uint32T + Reserved98c c.Uint32T + Reserved990 c.Uint32T + Reserved994 c.Uint32T + Reserved998 c.Uint32T + Reserved99c c.Uint32T + Reserved9a0 c.Uint32T + Reserved9a4 c.Uint32T + Reserved9a8 c.Uint32T + Reserved9ac c.Uint32T + Reserved9b0 c.Uint32T + Reserved9b4 c.Uint32T + Reserved9b8 c.Uint32T + Reserved9bc c.Uint32T + Reserved9c0 c.Uint32T + Reserved9c4 c.Uint32T + Reserved9c8 c.Uint32T + Reserved9cc c.Uint32T + Reserved9d0 c.Uint32T + Reserved9d4 c.Uint32T + Reserved9d8 c.Uint32T + Reserved9dc c.Uint32T + Reserved9e0 c.Uint32T + Reserved9e4 c.Uint32T + Reserved9e8 c.Uint32T + Reserved9ec c.Uint32T + Reserved9f0 c.Uint32T + Reserved9f4 c.Uint32T + Reserved9f8 c.Uint32T + Reserved9fc c.Uint32T + ReservedA00 c.Uint32T + ReservedA04 c.Uint32T + ReservedA08 c.Uint32T + ReservedA0c c.Uint32T + ReservedA10 c.Uint32T + ReservedA14 c.Uint32T + ReservedA18 c.Uint32T + ReservedA1c c.Uint32T + ReservedA20 c.Uint32T + ReservedA24 c.Uint32T + ReservedA28 c.Uint32T + ReservedA2c c.Uint32T + ReservedA30 c.Uint32T + ReservedA34 c.Uint32T + ReservedA38 c.Uint32T + ReservedA3c c.Uint32T + ReservedA40 c.Uint32T + ReservedA44 c.Uint32T + ReservedA48 c.Uint32T + ReservedA4c c.Uint32T + ReservedA50 c.Uint32T + ReservedA54 c.Uint32T + ReservedA58 c.Uint32T + ReservedA5c c.Uint32T + ReservedA60 c.Uint32T + ReservedA64 c.Uint32T + ReservedA68 c.Uint32T + ReservedA6c c.Uint32T + ReservedA70 c.Uint32T + ReservedA74 c.Uint32T + ReservedA78 c.Uint32T + ReservedA7c c.Uint32T + ReservedA80 c.Uint32T + ReservedA84 c.Uint32T + ReservedA88 c.Uint32T + ReservedA8c c.Uint32T + ReservedA90 c.Uint32T + ReservedA94 c.Uint32T + ReservedA98 c.Uint32T + ReservedA9c c.Uint32T + ReservedAa0 c.Uint32T + ReservedAa4 c.Uint32T + ReservedAa8 c.Uint32T + ReservedAac c.Uint32T + ReservedAb0 c.Uint32T + ReservedAb4 c.Uint32T + ReservedAb8 c.Uint32T + ReservedAbc c.Uint32T + ReservedAc0 c.Uint32T + ReservedAc4 c.Uint32T + ReservedAc8 c.Uint32T + ReservedAcc c.Uint32T + ReservedAd0 c.Uint32T + ReservedAd4 c.Uint32T + ReservedAd8 c.Uint32T + ReservedAdc c.Uint32T + ReservedAe0 c.Uint32T + ReservedAe4 c.Uint32T + ReservedAe8 c.Uint32T + ReservedAec c.Uint32T + ReservedAf0 c.Uint32T + ReservedAf4 c.Uint32T + ReservedAf8 c.Uint32T + ReservedAfc c.Uint32T + ReservedB00 c.Uint32T + ReservedB04 c.Uint32T + ReservedB08 c.Uint32T + ReservedB0c c.Uint32T + ReservedB10 c.Uint32T + ReservedB14 c.Uint32T + ReservedB18 c.Uint32T + ReservedB1c c.Uint32T + ReservedB20 c.Uint32T + ReservedB24 c.Uint32T + ReservedB28 c.Uint32T + ReservedB2c c.Uint32T + ReservedB30 c.Uint32T + ReservedB34 c.Uint32T + ReservedB38 c.Uint32T + ReservedB3c c.Uint32T + ReservedB40 c.Uint32T + ReservedB44 c.Uint32T + ReservedB48 c.Uint32T + ReservedB4c c.Uint32T + ReservedB50 c.Uint32T + ReservedB54 c.Uint32T + ReservedB58 c.Uint32T + ReservedB5c c.Uint32T + ReservedB60 c.Uint32T + ReservedB64 c.Uint32T + ReservedB68 c.Uint32T + ReservedB6c c.Uint32T + ReservedB70 c.Uint32T + ReservedB74 c.Uint32T + ReservedB78 c.Uint32T + ReservedB7c c.Uint32T + ReservedB80 c.Uint32T + ReservedB84 c.Uint32T + ReservedB88 c.Uint32T + ReservedB8c c.Uint32T + ReservedB90 c.Uint32T + ReservedB94 c.Uint32T + ReservedB98 c.Uint32T + ReservedB9c c.Uint32T + ReservedBa0 c.Uint32T + ReservedBa4 c.Uint32T + ReservedBa8 c.Uint32T + ReservedBac c.Uint32T + ReservedBb0 c.Uint32T + ReservedBb4 c.Uint32T + ReservedBb8 c.Uint32T + ReservedBbc c.Uint32T + ReservedBc0 c.Uint32T + ReservedBc4 c.Uint32T + ReservedBc8 c.Uint32T + ReservedBcc c.Uint32T + ReservedBd0 c.Uint32T + ReservedBd4 c.Uint32T + ReservedBd8 c.Uint32T + ReservedBdc c.Uint32T + ReservedBe0 c.Uint32T + ReservedBe4 c.Uint32T + ReservedBe8 c.Uint32T + ReservedBec c.Uint32T + ReservedBf0 c.Uint32T + ReservedBf4 c.Uint32T + ReservedBf8 c.Uint32T + ReservedBfc c.Uint32T + ReservedC00 c.Uint32T + ReservedC04 c.Uint32T + ReservedC08 c.Uint32T + ReservedC0c c.Uint32T + ReservedC10 c.Uint32T + ReservedC14 c.Uint32T + ReservedC18 c.Uint32T + ReservedC1c c.Uint32T + ReservedC20 c.Uint32T + ReservedC24 c.Uint32T + ReservedC28 c.Uint32T + ReservedC2c c.Uint32T + ReservedC30 c.Uint32T + ReservedC34 c.Uint32T + ReservedC38 c.Uint32T + ReservedC3c c.Uint32T + ReservedC40 c.Uint32T + ReservedC44 c.Uint32T + ReservedC48 c.Uint32T + ReservedC4c c.Uint32T + ReservedC50 c.Uint32T + ReservedC54 c.Uint32T + ReservedC58 c.Uint32T + ReservedC5c c.Uint32T + ReservedC60 c.Uint32T + ReservedC64 c.Uint32T + ReservedC68 c.Uint32T + ReservedC6c c.Uint32T + ReservedC70 c.Uint32T + ReservedC74 c.Uint32T + ReservedC78 c.Uint32T + ReservedC7c c.Uint32T + ReservedC80 c.Uint32T + ReservedC84 c.Uint32T + ReservedC88 c.Uint32T + ReservedC8c c.Uint32T + ReservedC90 c.Uint32T + ReservedC94 c.Uint32T + ReservedC98 c.Uint32T + ReservedC9c c.Uint32T + ReservedCa0 c.Uint32T + ReservedCa4 c.Uint32T + ReservedCa8 c.Uint32T + ReservedCac c.Uint32T + ReservedCb0 c.Uint32T + ReservedCb4 c.Uint32T + ReservedCb8 c.Uint32T + ReservedCbc c.Uint32T + ReservedCc0 c.Uint32T + ReservedCc4 c.Uint32T + ReservedCc8 c.Uint32T + ReservedCcc c.Uint32T + ReservedCd0 c.Uint32T + ReservedCd4 c.Uint32T + ReservedCd8 c.Uint32T + ReservedCdc c.Uint32T + ReservedCe0 c.Uint32T + ReservedCe4 c.Uint32T + ReservedCe8 c.Uint32T + ReservedCec c.Uint32T + ReservedCf0 c.Uint32T + ReservedCf4 c.Uint32T + ReservedCf8 c.Uint32T + ReservedCfc c.Uint32T + ReservedD00 c.Uint32T + ReservedD04 c.Uint32T + ReservedD08 c.Uint32T + ReservedD0c c.Uint32T + ReservedD10 c.Uint32T + ReservedD14 c.Uint32T + ReservedD18 c.Uint32T + ReservedD1c c.Uint32T + ReservedD20 c.Uint32T + ReservedD24 c.Uint32T + ReservedD28 c.Uint32T + ReservedD2c c.Uint32T + ReservedD30 c.Uint32T + ReservedD34 c.Uint32T + ReservedD38 c.Uint32T + ReservedD3c c.Uint32T + ReservedD40 c.Uint32T + ReservedD44 c.Uint32T + ReservedD48 c.Uint32T + ReservedD4c c.Uint32T + ReservedD50 c.Uint32T + ReservedD54 c.Uint32T + ReservedD58 c.Uint32T + ReservedD5c c.Uint32T + ReservedD60 c.Uint32T + ReservedD64 c.Uint32T + ReservedD68 c.Uint32T + ReservedD6c c.Uint32T + ReservedD70 c.Uint32T + ReservedD74 c.Uint32T + ReservedD78 c.Uint32T + ReservedD7c c.Uint32T + ReservedD80 c.Uint32T + ReservedD84 c.Uint32T + ReservedD88 c.Uint32T + ReservedD8c c.Uint32T + ReservedD90 c.Uint32T + ReservedD94 c.Uint32T + ReservedD98 c.Uint32T + ReservedD9c c.Uint32T + ReservedDa0 c.Uint32T + ReservedDa4 c.Uint32T + ReservedDa8 c.Uint32T + ReservedDac c.Uint32T + ReservedDb0 c.Uint32T + ReservedDb4 c.Uint32T + ReservedDb8 c.Uint32T + ReservedDbc c.Uint32T + ReservedDc0 c.Uint32T + ReservedDc4 c.Uint32T + ReservedDc8 c.Uint32T + ReservedDcc c.Uint32T + ReservedDd0 c.Uint32T + ReservedDd4 c.Uint32T + ReservedDd8 c.Uint32T + ReservedDdc c.Uint32T + ReservedDe0 c.Uint32T + ReservedDe4 c.Uint32T + ReservedDe8 c.Uint32T + ReservedDec c.Uint32T + ReservedDf0 c.Uint32T + ReservedDf4 c.Uint32T + ReservedDf8 c.Uint32T + ReservedDfc c.Uint32T + ReservedE00 c.Uint32T + ReservedE04 c.Uint32T + ReservedE08 c.Uint32T + ReservedE0c c.Uint32T + ReservedE10 c.Uint32T + ReservedE14 c.Uint32T + ReservedE18 c.Uint32T + ReservedE1c c.Uint32T + ReservedE20 c.Uint32T + ReservedE24 c.Uint32T + ReservedE28 c.Uint32T + ReservedE2c c.Uint32T + ReservedE30 c.Uint32T + ReservedE34 c.Uint32T + ReservedE38 c.Uint32T + ReservedE3c c.Uint32T + ReservedE40 c.Uint32T + ReservedE44 c.Uint32T + ReservedE48 c.Uint32T + ReservedE4c c.Uint32T + ReservedE50 c.Uint32T + ReservedE54 c.Uint32T + ReservedE58 c.Uint32T + ReservedE5c c.Uint32T + ReservedE60 c.Uint32T + ReservedE64 c.Uint32T + ReservedE68 c.Uint32T + ReservedE6c c.Uint32T + ReservedE70 c.Uint32T + ReservedE74 c.Uint32T + ReservedE78 c.Uint32T + ReservedE7c c.Uint32T + ReservedE80 c.Uint32T + ReservedE84 c.Uint32T + ReservedE88 c.Uint32T + ReservedE8c c.Uint32T + ReservedE90 c.Uint32T + ReservedE94 c.Uint32T + ReservedE98 c.Uint32T + ReservedE9c c.Uint32T + ReservedEa0 c.Uint32T + ReservedEa4 c.Uint32T + ReservedEa8 c.Uint32T + ReservedEac c.Uint32T + ReservedEb0 c.Uint32T + ReservedEb4 c.Uint32T + ReservedEb8 c.Uint32T + ReservedEbc c.Uint32T + ReservedEc0 c.Uint32T + ReservedEc4 c.Uint32T + ReservedEc8 c.Uint32T + ReservedEcc c.Uint32T + ReservedEd0 c.Uint32T + ReservedEd4 c.Uint32T + ReservedEd8 c.Uint32T + ReservedEdc c.Uint32T + ReservedEe0 c.Uint32T + ReservedEe4 c.Uint32T + ReservedEe8 c.Uint32T + ReservedEec c.Uint32T + ReservedEf0 c.Uint32T + ReservedEf4 c.Uint32T + ReservedEf8 c.Uint32T + ReservedEfc c.Uint32T + ReservedF00 c.Uint32T + ReservedF04 c.Uint32T + ReservedF08 c.Uint32T + ReservedF0c c.Uint32T + ReservedF10 c.Uint32T + ReservedF14 c.Uint32T + ReservedF18 c.Uint32T + ReservedF1c c.Uint32T + ReservedF20 c.Uint32T + ReservedF24 c.Uint32T + ReservedF28 c.Uint32T + ReservedF2c c.Uint32T + ReservedF30 c.Uint32T + ReservedF34 c.Uint32T + ReservedF38 c.Uint32T + ReservedF3c c.Uint32T + ReservedF40 c.Uint32T + ReservedF44 c.Uint32T + ReservedF48 c.Uint32T + ReservedF4c c.Uint32T + ReservedF50 c.Uint32T + ReservedF54 c.Uint32T + ReservedF58 c.Uint32T + ReservedF5c c.Uint32T + ReservedF60 c.Uint32T + ReservedF64 c.Uint32T + ReservedF68 c.Uint32T + ReservedF6c c.Uint32T + ReservedF70 c.Uint32T + ReservedF74 c.Uint32T + ReservedF78 c.Uint32T + ReservedF7c c.Uint32T + ReservedF80 c.Uint32T + ReservedF84 c.Uint32T + ReservedF88 c.Uint32T + ReservedF8c c.Uint32T + ReservedF90 c.Uint32T + ReservedF94 c.Uint32T + ReservedF98 c.Uint32T + ReservedF9c c.Uint32T + ReservedFa0 c.Uint32T + ReservedFa4 c.Uint32T + ReservedFa8 c.Uint32T + ReservedFac c.Uint32T + ReservedFb0 c.Uint32T + ReservedFb4 c.Uint32T + ReservedFb8 c.Uint32T + ReservedFbc c.Uint32T + ReservedFc0 c.Uint32T + ReservedFc4 c.Uint32T + ReservedFc8 c.Uint32T + ReservedFcc c.Uint32T + ReservedFd0 c.Uint32T + ReservedFd4 c.Uint32T + ReservedFd8 c.Uint32T + ReservedFdc c.Uint32T + ReservedFe0 c.Uint32T + ReservedFe4 c.Uint32T + ReservedFe8 c.Uint32T + ReservedFec c.Uint32T + ReservedFf0 c.Uint32T + ReservedFf4 c.Uint32T + ReservedFf8 c.Uint32T + RegDate struct { + Val c.Uint32T + } +} +type SensitiveDevT SensitiveDevS diff --git a/esp32/sha.go b/esp32/sha.go new file mode 100644 index 00000000..7bd789c6 --- /dev/null +++ b/esp32/sha.go @@ -0,0 +1,63 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type SHATYPE c.Int + +const ( + SHA1 SHATYPE = 0 + SHA2_224 SHATYPE = 1 + SHA2_256 SHATYPE = 2 + SHA2_384 SHATYPE = 3 + SHA2_512 SHATYPE = 4 + SHA2_512224 SHATYPE = 5 + SHA2_512256 SHATYPE = 6 + SHA2_512T SHATYPE = 7 + SHA_TYPE_MAX SHATYPE = 8 +) + +type SHAContext struct { + Start bool + InHardware bool + Type SHATYPE + State [16]c.Uint32T + Buffer [128]c.Char + TotalBits [4]c.Uint32T +} +type SHACTX SHAContext + +//go:linkname EtsShaEnable C.ets_sha_enable +func EtsShaEnable() + +//go:linkname EtsShaDisable C.ets_sha_disable +func EtsShaDisable() + +// llgo:link (*SHACTX).EtsShaInit C.ets_sha_init +func (recv_ *SHACTX) EtsShaInit(type_ SHATYPE) EtsStatusT { + return 0 +} + +// llgo:link (*SHACTX).EtsShaStarts C.ets_sha_starts +func (recv_ *SHACTX) EtsShaStarts(sha512_t c.Uint16T) EtsStatusT { + return 0 +} + +// llgo:link (*SHACTX).EtsShaGetState C.ets_sha_get_state +func (recv_ *SHACTX) EtsShaGetState() { +} + +// llgo:link (*SHACTX).EtsShaProcess C.ets_sha_process +func (recv_ *SHACTX) EtsShaProcess(input *c.Char) { +} + +// llgo:link (*SHACTX).EtsShaUpdate C.ets_sha_update +func (recv_ *SHACTX) EtsShaUpdate(input *c.Char, input_bytes c.Uint32T, update_ctx bool) { +} + +// llgo:link (*SHACTX).EtsShaFinish C.ets_sha_finish +func (recv_ *SHACTX) EtsShaFinish(output *c.Char) EtsStatusT { + return 0 +} diff --git a/esp32/sha_hal.go b/esp32/sha_hal.go new file mode 100644 index 00000000..ed4f6979 --- /dev/null +++ b/esp32/sha_hal.go @@ -0,0 +1,65 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Hashes a single message block + * + * @param sha_type SHA algorithm to hash with + * @param data_block Input message to be hashed + * @param block_word_len Length of the input message + * @param first_block Is this the first block in a message or a continuation? + */ +// llgo:link EspShaType.ShaHalHashBlock C.sha_hal_hash_block +func (recv_ EspShaType) ShaHalHashBlock(data_block c.Pointer, block_word_len c.SizeT, first_block bool) { +} + +/** + * @brief Polls and waits until the SHA engine is idle + * + */ +//go:linkname ShaHalWaitIdle C.sha_hal_wait_idle +func ShaHalWaitIdle() + +/** + * @brief Reads the current message digest from the SHA engine + * + * @param sha_type SHA algorithm used + * @param digest_state Output buffer to which to read message digest to + */ +// llgo:link EspShaType.ShaHalReadDigest C.sha_hal_read_digest +func (recv_ EspShaType) ShaHalReadDigest(digest_state c.Pointer) { +} + +/** + * @brief Writes the message digest to the SHA engine + * + * @param sha_type The SHA algorithm type + * @param digest_state Message digest to be written to SHA engine + */ +// llgo:link EspShaType.ShaHalWriteDigest C.sha_hal_write_digest +func (recv_ EspShaType) ShaHalWriteDigest(digest_state c.Pointer) { +} + +/** + * @brief Hashes a number of message blocks using DMA + * + * @param sha_type SHA algorithm to hash with + * @param num_blocks Number of blocks to hash + * @param first_block Is this the first block in a message or a continuation? + */ +// llgo:link EspShaType.ShaHalHashDma C.sha_hal_hash_dma +func (recv_ EspShaType) ShaHalHashDma(num_blocks c.SizeT, first_block bool) { +} + +/** + * @brief Calculates and sets the initial digiest for SHA512_t + * + * @param t_string + * @param t_len + */ +//go:linkname ShaHalSha512InitHash C.sha_hal_sha512_init_hash +func ShaHalSha512InitHash(t_string c.Uint32T, t_len c.Uint8T) diff --git a/esp32/sha_ll.go b/esp32/sha_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/sha_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/sha_types.go b/esp32/sha_types.go new file mode 100644 index 00000000..502b45c8 --- /dev/null +++ b/esp32/sha_types.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +type EspShaType SHATYPE diff --git a/esp32/sleep_clock.go b/esp32/sleep_clock.go new file mode 100644 index 00000000..1e7d90e5 --- /dev/null +++ b/esp32/sleep_clock.go @@ -0,0 +1,29 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Whether to allow the TOP power domain to be powered off. + * + * In light sleep mode, only when the system can provide enough memory + * for digital peripheral clock retention, the TOP power domain can be + * powered off. + * + * @return True to allow power off + */ +//go:linkname ClockDomainPdAllowed C.clock_domain_pd_allowed +func ClockDomainPdAllowed() bool + +/** + * @brief SoC system clock retention initialize. + * + * @return + * - ESP_OK on success + * - ESP_ERR_NO_MEM not enough memory for system clock retention + * - ESP_ERR_INVALID_ARG if either of the arguments is out of range + */ +//go:linkname SleepClockSystemRetentionInit C.sleep_clock_system_retention_init +func SleepClockSystemRetentionInit(arg c.Pointer) EspErrT diff --git a/esp32/sleep_console.go b/esp32/sleep_console.go new file mode 100644 index 00000000..3b1038e4 --- /dev/null +++ b/esp32/sleep_console.go @@ -0,0 +1,21 @@ +package freertos + +import _ "unsafe" + +type SleepConsoleUsjEnableStateT struct { + UsjClockEnabled bool + UsjPadEnabled bool +} + +/** + * @brief Disable usb-serial-jtag pad during light sleep to avoid current leakage and + * backup the enable state before light sleep + */ +//go:linkname SleepConsoleUsjPadBackupAndDisable C.sleep_console_usj_pad_backup_and_disable +func SleepConsoleUsjPadBackupAndDisable() + +/** + * @brief Restore initial usb-serial-jtag pad enable state when wakeup from light sleep + */ +//go:linkname SleepConsoleUsjPadRestore C.sleep_console_usj_pad_restore +func SleepConsoleUsjPadRestore() diff --git a/esp32/sleep_cpu.go b/esp32/sleep_cpu.go new file mode 100644 index 00000000..1e807ab2 --- /dev/null +++ b/esp32/sleep_cpu.go @@ -0,0 +1,59 @@ +package freertos + +import _ "unsafe" + +/** + * @brief Whether to allow the cpu power domain to be powered off. + * + * In light sleep mode, only when the system can provide enough memory + * for cpu retention, the cpu power domain can be powered off. + */ +//go:linkname CpuDomainPdAllowed C.cpu_domain_pd_allowed +func CpuDomainPdAllowed() bool + +/** + * @brief Configure the parameters of the CPU domain during the sleep process + * + * @param light_sleep_enable true for enable light sleep mode, false for disable light sleep mode + * + * @return + * - ESP_OK on success + */ +//go:linkname SleepCpuConfigure C.sleep_cpu_configure +func SleepCpuConfigure(light_sleep_enable bool) EspErrT + +/** + * @brief Enable cpu retention of some modules. + * + * In light sleep mode, before the system goes to sleep, enable the cpu + * retention of modules such as CPU and I/D-cache tag memory. + */ +//go:linkname SleepEnableCpuRetention C.sleep_enable_cpu_retention +func SleepEnableCpuRetention() + +/** + * @brief Disable cpu retention of some modules. + * + * In light sleep mode, after the system exits sleep, disable the cpu + * retention of modules such as CPU and I/D-cache tag memory. + */ +//go:linkname SleepDisableCpuRetention C.sleep_disable_cpu_retention +func SleepDisableCpuRetention() + +/** + * Do sleep prepare for other smp cores + */ +//go:linkname SleepSmpCpuSleepPrepare C.sleep_smp_cpu_sleep_prepare +func SleepSmpCpuSleepPrepare() + +/** + * Do wakeup prepare for other smp cores + */ +//go:linkname SleepSmpCpuWakeupPrepare C.sleep_smp_cpu_wakeup_prepare +func SleepSmpCpuWakeupPrepare() + +/** + * Notify the other core that this sleep does not require retention. + */ +//go:linkname EspSleepCpuSkipRetention C.esp_sleep_cpu_skip_retention +func EspSleepCpuSkipRetention() diff --git a/esp32/sleep_event.go b/esp32/sleep_event.go new file mode 100644 index 00000000..a8ae0e69 --- /dev/null +++ b/esp32/sleep_event.go @@ -0,0 +1,84 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EspSleepEventCbIndexT c.Int + +const ( + SLEEP_EVENT_HW_EXIT_SLEEP EspSleepEventCbIndexT = 0 + SLEEP_EVENT_SW_CLK_READY EspSleepEventCbIndexT = 1 + SLEEP_EVENT_SW_EXIT_SLEEP EspSleepEventCbIndexT = 2 + SLEEP_EVENT_SW_GOTO_SLEEP EspSleepEventCbIndexT = 3 + SLEEP_EVENT_HW_TIME_START EspSleepEventCbIndexT = 4 + SLEEP_EVENT_HW_GOTO_SLEEP EspSleepEventCbIndexT = 5 + SLEEP_EVENT_SW_CPU_TO_MEM_START EspSleepEventCbIndexT = 6 + SLEEP_EVENT_SW_CPU_TO_MEM_END EspSleepEventCbIndexT = 7 + SLEEP_EVENT_HW_PLL_EN_START EspSleepEventCbIndexT = 8 + SLEEP_EVENT_HW_PLL_EN_STOP EspSleepEventCbIndexT = 9 + SLEEP_EVENT_CB_INDEX_NUM EspSleepEventCbIndexT = 10 +) + +// llgo:type C +type EspSleepEventCbT func(c.Pointer, c.Pointer) EspErrT + +/** + * @brief Function entry parameter types for light sleep event callback functions (if CONFIG_FREERTOS_USE_TICKLESS_IDLE) + */ + +type X_espSleepEventCbConfigT struct { + Cb EspSleepEventCbT + UserArg c.Pointer + Prior c.Uint32T + Next *X_espSleepEventCbConfigT +} +type EspSleepEventCbConfigT X_espSleepEventCbConfigT + +type X_espSleepEventCbsConfigT struct { + SleepEventCbConfig [10]*EspSleepEventCbConfigT +} +type EspSleepEventCbsConfigT X_espSleepEventCbsConfigT + +/** + * @brief Register event callbacks for light sleep internal events (if CONFIG_FREERTOS_USE_TICKLESS_IDLE) + * @param event_id Designed to register the corresponding event_cb in g_sleep_event_cbs_config + * @param event_cb_conf Config struct containing event callback function and corresponding argument + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the input parameter event_cb_conf is NULL or event_id is out of range + * - ESP_ERR_NO_MEM if the remaining memory is insufficient to support malloc + * - ESP_FAIL if register the same function repeatedly + * + * @note Some of these callback functions are called from IDLE task context hence they cannot call any blocking functions + * @note Passing NULL value will not deregister the callbacks, it will silently ignore and return ESP_OK + */ +// llgo:link EspSleepEventCbIndexT.EspSleepRegisterEventCallback C.esp_sleep_register_event_callback +func (recv_ EspSleepEventCbIndexT) EspSleepRegisterEventCallback(event_cb_conf *EspSleepEventCbConfigT) EspErrT { + return 0 +} + +/** + * @brief Unregister event callbacks for light sleep internal events (if CONFIG_FREERTOS_USE_TICKLESS_IDLE) + * @param event_id Designed to unregister the corresponding event_cb in g_sleep_event_cbs_config + * @param event_cb_conf Config struct containing event callback function and corresponding argument + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if the input parameter cb is NULL or event_id is out of range + */ +// llgo:link EspSleepEventCbIndexT.EspSleepUnregisterEventCallback C.esp_sleep_unregister_event_callback +func (recv_ EspSleepEventCbIndexT) EspSleepUnregisterEventCallback(cb EspSleepEventCbT) EspErrT { + return 0 +} + +/** + * @brief Designed to execute functions in the esp_sleep_event_cb_config_t linked list + * + * @param event_id Designed to annotate the corresponding event_cb in g_sleep_event_cbs_config + * @param ext_arg Designed to pass external parameters + * @return None + */ +// llgo:link EspSleepEventCbIndexT.EspSleepExecuteEventCallbacks C.esp_sleep_execute_event_callbacks +func (recv_ EspSleepEventCbIndexT) EspSleepExecuteEventCallbacks(ext_arg c.Pointer) { +} diff --git a/esp32/sleep_gpio.go b/esp32/sleep_gpio.go new file mode 100644 index 00000000..e4aee8f0 --- /dev/null +++ b/esp32/sleep_gpio.go @@ -0,0 +1,9 @@ +package freertos + +import _ "unsafe" + +/** + * @brief Call once in startup to disable the wakeup IO pins and release their holding state after waking up from Deep-sleep + */ +//go:linkname EspDeepSleepWakeupIoReset C.esp_deep_sleep_wakeup_io_reset +func EspDeepSleepWakeupIoReset() diff --git a/esp32/sleep_modem.go b/esp32/sleep_modem.go new file mode 100644 index 00000000..1da99bae --- /dev/null +++ b/esp32/sleep_modem.go @@ -0,0 +1,105 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Whether the current target allows Modem or the TOP power domain to be powered off during light sleep + * + * During light sleep on some targets, it is possible to power OFF the Modem or TOP + * power domains in order to further lower power power consumption. However, this + * can only occur on targets that support REGDMA for modem (WiFi, Bluetooth, + * IEEE802.15.4) retention. + */ +//go:linkname ModemDomainPdAllowed C.modem_domain_pd_allowed +func ModemDomainPdAllowed() bool + +/** + * @brief Get the reject trigger signal of Modem system + * + * @return the reject trigger signal of Modem system. + */ +//go:linkname SleepModemRejectTriggers C.sleep_modem_reject_triggers +func SleepModemRejectTriggers() c.Uint32T + +/** + * @brief Configure the parameters of the modem subsystem during the sleep process + * + * In light sleep mode, the wake-up early time of the WiFi module and the TBTT + * interrupt early time (trigger enabling RF) are determined by the maximum and + * minimum frequency of system (higher system frequency means less time to wake + * up and enable RF). + * For the esp32c6 SOC, the modem state is strongly dependent on the light sleep + * mode, and the modem state will be enabled only when light sleep is enabled + * and the `CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP` is configured in menuconfig. + * + * @param max_freq_mhz the maximum frequency of system + * @param min_freq_mhz the minimum frequency of system + * @param light_sleep_enable true or false for enable or disable light sleep mode, respectively + * + * @return + * - ESP_OK on success + */ +//go:linkname SleepModemConfigure C.sleep_modem_configure +func SleepModemConfigure(max_freq_mhz c.Int, min_freq_mhz c.Int, light_sleep_enable bool) EspErrT + +// llgo:type C +type InformOutLightSleepOverheadCbT func(c.Uint32T) + +/** + * @brief Register informing peripherals light sleep wakeup overhead time callback + * + * This function allows you to register a callback that informs the peripherals of + * the wakeup overhead time of light sleep. + * @param cb function to inform time + * @return + * - ESP_OK on success + * - ESP_ERR_NO_MEM if no more callback slots are available + */ +//go:linkname EspPmRegisterInformOutLightSleepOverheadCallback C.esp_pm_register_inform_out_light_sleep_overhead_callback +func EspPmRegisterInformOutLightSleepOverheadCallback(cb InformOutLightSleepOverheadCbT) EspErrT + +/** + * @brief Unregister informing peripherals light sleep wakeup overhead time callback + * + * This function allows you to unregister a callback that informs the peripherals of + * the wakeup overhead time of light sleep. + * @param cb function to inform time + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_STATE if the given callback hasn't been registered before + */ +//go:linkname EspPmUnregisterInformOutLightSleepOverheadCallback C.esp_pm_unregister_inform_out_light_sleep_overhead_callback +func EspPmUnregisterInformOutLightSleepOverheadCallback(cb InformOutLightSleepOverheadCbT) EspErrT + +/** + * @brief A callback that informs the peripherals of the wakeup overhead time of light sleep + * + * @param out_light_sleep_time wakeup overhead time of light sleep + */ +//go:linkname PeriphInformOutLightSleepOverhead C.periph_inform_out_light_sleep_overhead +func PeriphInformOutLightSleepOverhead(out_light_sleep_time c.Uint32T) + +// llgo:type C +type UpdateLightSleepDefaultParamsConfigCbT func(c.Int, c.Int) + +/** + * @brief Register peripherals light sleep default parameters configure callback + * + * This function allows you to register a callback that configure the peripherals + * of default parameters of light sleep + * @param cb function to update default parameters + */ +//go:linkname EspPmRegisterLightSleepDefaultParamsConfigCallback C.esp_pm_register_light_sleep_default_params_config_callback +func EspPmRegisterLightSleepDefaultParamsConfigCallback(cb UpdateLightSleepDefaultParamsConfigCbT) + +/** + * @brief Unregister peripherals light sleep default parameters configure Callback + * + * This function allows you to unregister a callback that configure the peripherals + * of default parameters of light sleep + */ +//go:linkname EspPmUnregisterLightSleepDefaultParamsConfigCallback C.esp_pm_unregister_light_sleep_default_params_config_callback +func EspPmUnregisterLightSleepDefaultParamsConfigCallback() diff --git a/esp32/sleep_sys_periph.go b/esp32/sleep_sys_periph.go new file mode 100644 index 00000000..b666202d --- /dev/null +++ b/esp32/sleep_sys_periph.go @@ -0,0 +1,14 @@ +package freertos + +import _ "unsafe" + +/** + * @brief Whether to allow the TOP power domain to be powered off. + * + * In light sleep mode, only when the system can provide enough memory + * for digital peripheral retention, the TOP power domain can be powered off. + * + * @return True to allow power off + */ +//go:linkname PeripheralDomainPdAllowed C.peripheral_domain_pd_allowed +func PeripheralDomainPdAllowed() bool diff --git a/esp32/soc.go b/esp32/soc.go new file mode 100644 index 00000000..5a9308c0 --- /dev/null +++ b/esp32/soc.go @@ -0,0 +1,52 @@ +package freertos + +import _ "unsafe" + +const DR_REG_MMU_TABLE = 0x600C5000 +const DR_REG_ITAG_TABLE = 0x600C6000 +const DR_REG_DTAG_TABLE = 0x600C8000 +const DR_REG_EXT_MEM_ENC = 0x600CC000 +const SPI_CLK_DIV = 4 +const TICKS_PER_US_ROM = 40 +const SOC_DROM_LOW = 0x3C000000 +const SOC_DROM_HIGH = 0x3E000000 +const SOC_IROM_LOW = 0x42000000 +const SOC_IROM_HIGH = 0x44000000 +const SOC_IRAM_LOW = 0x40370000 +const SOC_IRAM_HIGH = 0x403E0000 +const SOC_DRAM_LOW = 0x3FC88000 +const SOC_DRAM_HIGH = 0x3FD00000 +const SOC_RTC_IRAM_LOW = 0x600FE000 +const SOC_RTC_IRAM_HIGH = 0x60100000 +const SOC_RTC_DRAM_LOW = 0x600FE000 +const SOC_RTC_DRAM_HIGH = 0x60100000 +const SOC_RTC_DATA_LOW = 0x50000000 +const SOC_RTC_DATA_HIGH = 0x50002000 +const SOC_EXTRAM_DATA_LOW = 0x3C000000 +const SOC_EXTRAM_DATA_HIGH = 0x3E000000 +const SOC_IROM_MASK_LOW = 0x40000000 +const SOC_IROM_MASK_HIGH = 0x40060000 +const SOC_DIRAM_IRAM_LOW = 0x40378000 +const SOC_DIRAM_IRAM_HIGH = 0x403E0000 +const SOC_DIRAM_DRAM_LOW = 0x3FC88000 +const SOC_DIRAM_DRAM_HIGH = 0x3FCF0000 +const SOC_DMA_LOW = 0x3FC88000 +const SOC_DMA_HIGH = 0x3FD00000 +const SOC_BYTE_ACCESSIBLE_LOW = 0x3FC88000 +const SOC_BYTE_ACCESSIBLE_HIGH = 0x3FD00000 +const SOC_MEM_INTERNAL_LOW = 0x3FC88000 +const SOC_MEM_INTERNAL_HIGH = 0x403E0000 +const SOC_ROM_STACK_START = 0x3fceb710 +const SOC_ROM_STACK_SIZE = 0x2000 +const ETS_WMAC_INUM = 0 +const ETS_WBB_INUM = 4 +const ETS_T1_WDT_INUM = 24 +const ETS_MEMACCESS_ERR_INUM = 25 +const ETS_IPC_ISR_INUM = 28 +const ETS_SLC_INUM = 1 +const ETS_UART0_INUM = 5 +const ETS_UART1_INUM = 5 +const ETS_SPI2_INUM = 1 +const ETS_FRC_TIMER2_INUM = 10 +const ETS_GPIO_INUM = 4 +const ETS_INVALID_INUM = 6 diff --git a/esp32/soc_caps.go b/esp32/soc_caps.go new file mode 100644 index 00000000..ce5ba81e --- /dev/null +++ b/esp32/soc_caps.go @@ -0,0 +1,175 @@ +package freertos + +import _ "unsafe" + +const SOC_ADC_SUPPORTED = 1 +const SOC_UART_SUPPORTED = 1 +const SOC_PCNT_SUPPORTED = 1 +const SOC_PHY_SUPPORTED = 1 +const SOC_WIFI_SUPPORTED = 1 +const SOC_TWAI_SUPPORTED = 1 +const SOC_GDMA_SUPPORTED = 1 +const SOC_AHB_GDMA_SUPPORTED = 1 +const SOC_GPTIMER_SUPPORTED = 1 +const SOC_LCDCAM_SUPPORTED = 1 +const SOC_LCDCAM_I80_LCD_SUPPORTED = 1 +const SOC_LCDCAM_RGB_LCD_SUPPORTED = 1 +const SOC_MCPWM_SUPPORTED = 1 +const SOC_DEDICATED_GPIO_SUPPORTED = 1 +const SOC_CACHE_SUPPORT_WRAP = 1 +const SOC_ULP_SUPPORTED = 1 +const SOC_ULP_FSM_SUPPORTED = 1 +const SOC_RISCV_COPROC_SUPPORTED = 1 +const SOC_BT_SUPPORTED = 1 +const SOC_USB_OTG_SUPPORTED = 1 +const SOC_USB_SERIAL_JTAG_SUPPORTED = 1 +const SOC_CCOMP_TIMER_SUPPORTED = 1 +const SOC_ASYNC_MEMCPY_SUPPORTED = 1 +const SOC_SUPPORTS_SECURE_DL_MODE = 1 +const SOC_EFUSE_KEY_PURPOSE_FIELD = 1 +const SOC_EFUSE_SUPPORTED = 1 +const SOC_SDMMC_HOST_SUPPORTED = 1 +const SOC_RTC_FAST_MEM_SUPPORTED = 1 +const SOC_RTC_SLOW_MEM_SUPPORTED = 1 +const SOC_RTC_MEM_SUPPORTED = 1 +const SOC_PSRAM_DMA_CAPABLE = 1 +const SOC_XT_WDT_SUPPORTED = 1 +const SOC_I2S_SUPPORTED = 1 +const SOC_RMT_SUPPORTED = 1 +const SOC_SDM_SUPPORTED = 1 +const SOC_GPSPI_SUPPORTED = 1 +const SOC_LEDC_SUPPORTED = 1 +const SOC_I2C_SUPPORTED = 1 +const SOC_SYSTIMER_SUPPORTED = 1 +const SOC_SUPPORT_COEXISTENCE = 1 +const SOC_TEMP_SENSOR_SUPPORTED = 1 +const SOC_AES_SUPPORTED = 1 +const SOC_MPI_SUPPORTED = 1 +const SOC_SHA_SUPPORTED = 1 +const SOC_HMAC_SUPPORTED = 1 +const SOC_DIG_SIGN_SUPPORTED = 1 +const SOC_FLASH_ENC_SUPPORTED = 1 +const SOC_SECURE_BOOT_SUPPORTED = 1 +const SOC_MEMPROT_SUPPORTED = 1 +const SOC_TOUCH_SENSOR_SUPPORTED = 1 +const SOC_BOD_SUPPORTED = 1 +const SOC_CLK_TREE_SUPPORTED = 1 +const SOC_MPU_SUPPORTED = 1 +const SOC_WDT_SUPPORTED = 1 +const SOC_SPI_FLASH_SUPPORTED = 1 +const SOC_RNG_SUPPORTED = 1 +const SOC_LIGHT_SLEEP_SUPPORTED = 1 +const SOC_DEEP_SLEEP_SUPPORTED = 1 +const SOC_LP_PERIPH_SHARE_INTERRUPT = 1 +const SOC_PM_SUPPORTED = 1 +const SOC_SIMD_INSTRUCTION_SUPPORTED = 1 +const SOC_XTAL_SUPPORT_40M = 1 +const SOC_ADC_RTC_CTRL_SUPPORTED = 1 +const SOC_ADC_DIG_CTRL_SUPPORTED = 1 +const SOC_ADC_ARBITER_SUPPORTED = 1 +const SOC_ADC_DIG_IIR_FILTER_SUPPORTED = 1 +const SOC_ADC_MONITOR_SUPPORTED = 1 +const SOC_ADC_DMA_SUPPORTED = 1 +const SOC_ADC_SAMPLE_FREQ_THRES_HIGH = 83333 +const SOC_ADC_SAMPLE_FREQ_THRES_LOW = 611 +const SOC_ADC_SHARED_POWER = 1 +const SOC_BROWNOUT_RESET_SUPPORTED = 1 +const SOC_CACHE_WRITEBACK_SUPPORTED = 1 +const SOC_CACHE_FREEZE_SUPPORTED = 1 +const SOC_CPU_CORES_NUM = 2 +const SOC_CPU_INTR_NUM = 32 +const SOC_CPU_HAS_FPU = 1 +const SOC_HP_CPU_HAS_MULTIPLE_CORES = 1 +const SOC_CPU_BREAKPOINTS_NUM = 2 +const SOC_CPU_WATCHPOINTS_NUM = 2 +const SOC_CPU_WATCHPOINT_MAX_REGION_SIZE = 64 +const SOC_SIMD_PREFERRED_DATA_ALIGNMENT = 16 +const SOC_GDMA_PAIRS_PER_GROUP = 5 +const SOC_GDMA_PAIRS_PER_GROUP_MAX = 5 +const SOC_AHB_GDMA_SUPPORT_PSRAM = 1 +const SOC_GPIO_PIN_COUNT = 49 +const SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER = 1 +const SOC_GPIO_FILTER_CLK_SUPPORT_APB = 1 +const SOC_GPIO_IN_RANGE_MAX = 48 +const SOC_GPIO_OUT_RANGE_MAX = 48 +const SOC_RMT_TX_CANDIDATES_PER_GROUP = 4 +const SOC_RMT_RX_CANDIDATES_PER_GROUP = 4 +const SOC_RMT_CHANNELS_PER_GROUP = 8 +const SOC_RMT_MEM_WORDS_PER_CHANNEL = 48 +const SOC_RMT_SUPPORT_RX_PINGPONG = 1 +const SOC_RMT_SUPPORT_RX_DEMODULATION = 1 +const SOC_RMT_SUPPORT_TX_ASYNC_STOP = 1 +const SOC_RMT_SUPPORT_TX_LOOP_COUNT = 1 +const SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP = 1 +const SOC_RMT_SUPPORT_TX_SYNCHRO = 1 +const SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY = 1 +const SOC_RMT_SUPPORT_XTAL = 1 +const SOC_RMT_SUPPORT_RC_FAST = 1 +const SOC_RMT_SUPPORT_APB = 1 +const SOC_RMT_SUPPORT_DMA = 1 +const SOC_RTCIO_PIN_COUNT = 22 +const SOC_RTCIO_INPUT_OUTPUT_SUPPORTED = 1 +const SOC_RTCIO_HOLD_SUPPORTED = 1 +const SOC_RTCIO_WAKE_SUPPORTED = 1 +const SOC_LP_IO_CLOCK_IS_INDEPENDENT = 1 +const SOC_SDM_GROUPS = 1 +const SOC_SDM_CHANNELS_PER_GROUP = 8 +const SOC_SDM_CLK_SUPPORT_APB = 1 +const SOC_SPI_PERIPH_NUM = 3 +const SOC_SPI_MAX_CS_NUM = 6 +const SOC_SPI_MAXIMUM_BUFFER_SIZE = 64 +const SOC_SPI_SUPPORT_DDRCLK = 1 +const SOC_SPI_SLAVE_SUPPORT_SEG_TRANS = 1 +const SOC_SPI_SUPPORT_CD_SIG = 1 +const SOC_SPI_SUPPORT_CONTINUOUS_TRANS = 1 +const SOC_SPI_SUPPORT_SLAVE_HD_VER2 = 1 +const SOC_SPI_SUPPORT_CLK_APB = 1 +const SOC_SPI_SUPPORT_CLK_XTAL = 1 +const SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT = 1 +const SOC_MEMSPI_IS_INDEPENDENT = 1 +const SOC_SPI_MAX_PRE_DIVIDER = 16 +const SOC_SPI_SUPPORT_OCT = 1 +const SOC_SPI_SCT_SUPPORTED = 1 +const SOC_SPI_SCT_REG_NUM = 14 +const SOC_SPI_SCT_CONF_BITLEN_MAX = 0x3FFFA +const SOC_MEMSPI_SRC_FREQ_120M = 1 +const SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED = 1 +const SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED = 1 +const SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED = 1 +const SOC_SPIRAM_SUPPORTED = 1 +const SOC_SPIRAM_XIP_SUPPORTED = 1 +const SOC_SYSTIMER_COUNTER_NUM = 2 +const SOC_SYSTIMER_ALARM_NUM = 3 +const SOC_SYSTIMER_BIT_WIDTH_LO = 32 +const SOC_SYSTIMER_BIT_WIDTH_HI = 20 +const SOC_SYSTIMER_FIXED_DIVIDER = 1 +const SOC_SYSTIMER_INT_LEVEL = 1 +const SOC_SYSTIMER_ALARM_MISS_COMPENSATE = 1 +const SOC_LP_TIMER_BIT_WIDTH_LO = 32 +const SOC_LP_TIMER_BIT_WIDTH_HI = 16 +const SOC_TWAI_CLK_SUPPORT_APB = 1 +const SOC_TWAI_BRP_MIN = 2 +const SOC_TWAI_BRP_MAX = 16384 +const SOC_TWAI_SUPPORTS_RX_STATUS = 1 +const SOC_EFUSE_DIS_DOWNLOAD_ICACHE = 1 +const SOC_EFUSE_DIS_DOWNLOAD_DCACHE = 1 +const SOC_EFUSE_HARD_DIS_JTAG = 1 +const SOC_EFUSE_DIS_USB_JTAG = 1 +const SOC_EFUSE_SOFT_DIS_JTAG = 1 +const SOC_EFUSE_DIS_DIRECT_BOOT = 1 +const SOC_EFUSE_DIS_ICACHE = 1 +const SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK = 1 +const SOC_SECURE_BOOT_V2_RSA = 1 +const SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS = 3 +const SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS = 1 +const SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY = 1 +const SOC_FLASH_ENCRYPTION_XTS_AES = 1 +const SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS = 1 +const SOC_FLASH_ENCRYPTION_XTS_AES_128 = 1 +const SOC_FLASH_ENCRYPTION_XTS_AES_256 = 1 +const SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE = 16 +const SOC_MEMPROT_MEM_ALIGN_SIZE = 256 +const SOC_SDMMC_USE_GPIO_MATRIX = 1 +const SOC_SDMMC_NUM_SLOTS = 2 +const SOC_SDMMC_SUPPORT_XTAL_CLOCK = 1 +const SOC_SDMMC_DELAY_PHASE_NUM = 4 diff --git a/esp32/soc_hal.go b/esp32/soc_hal.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/soc_hal.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/soc_memprot_types.go b/esp32/soc_memprot_types.go new file mode 100644 index 00000000..2c14454d --- /dev/null +++ b/esp32/soc_memprot_types.go @@ -0,0 +1,64 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type EspMprotMemT c.Int + +const ( + MEMPROT_TYPE_NONE EspMprotMemT = 0 + MEMPROT_TYPE_IRAM0_SRAM EspMprotMemT = 1 + MEMPROT_TYPE_DRAM0_SRAM EspMprotMemT = 2 + MEMPROT_TYPE_IRAM0_RTCFAST EspMprotMemT = 4 + MEMPROT_TYPE_ALL EspMprotMemT = 2147483647 + MEMPROT_TYPE_INVALID EspMprotMemT = -2147483648 + MEMPROT_TYPE_IRAM0_ANY EspMprotMemT = 5 +) + +type EspMprotSplitAddrT c.Int + +const ( + MEMPROT_SPLIT_ADDR_NONE EspMprotSplitAddrT = 0 + MEMPROT_SPLIT_ADDR_IRAM0_DRAM0 EspMprotSplitAddrT = 1 + MEMPROT_SPLIT_ADDR_IRAM0_LINE_0 EspMprotSplitAddrT = 2 + MEMPROT_SPLIT_ADDR_IRAM0_LINE_1 EspMprotSplitAddrT = 4 + MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_0 EspMprotSplitAddrT = 8 + MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_1 EspMprotSplitAddrT = 16 + MEMPROT_SPLIT_ADDR_ALL EspMprotSplitAddrT = 2147483647 + MEMPROT_SPLIT_ADDR_INVALID EspMprotSplitAddrT = -2147483648 + MEMPROT_SPLIT_ADDR_MAIN EspMprotSplitAddrT = 1 +) + +type EspMprotPmsAreaT c.Int + +const ( + MEMPROT_PMS_AREA_NONE EspMprotPmsAreaT = 0 + MEMPROT_PMS_AREA_IRAM0_0 EspMprotPmsAreaT = 1 + MEMPROT_PMS_AREA_IRAM0_1 EspMprotPmsAreaT = 2 + MEMPROT_PMS_AREA_IRAM0_2 EspMprotPmsAreaT = 4 + MEMPROT_PMS_AREA_IRAM0_3 EspMprotPmsAreaT = 8 + MEMPROT_PMS_AREA_DRAM0_0 EspMprotPmsAreaT = 16 + MEMPROT_PMS_AREA_DRAM0_1 EspMprotPmsAreaT = 32 + MEMPROT_PMS_AREA_DRAM0_2 EspMprotPmsAreaT = 64 + MEMPROT_PMS_AREA_DRAM0_3 EspMprotPmsAreaT = 128 + MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO EspMprotPmsAreaT = 256 + MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI EspMprotPmsAreaT = 512 + MEMPROT_PMS_AREA_ICACHE_0 EspMprotPmsAreaT = 1024 + MEMPROT_PMS_AREA_ICACHE_1 EspMprotPmsAreaT = 2048 + MEMPROT_PMS_AREA_ALL EspMprotPmsAreaT = 2147483647 + MEMPROT_PMS_AREA_INVALID EspMprotPmsAreaT = -2147483648 +) + +/** +* @brief Memory protection configuration + */ +type EspMempConfigT struct { + InvokePanicHandler bool + LockFeature bool + SplitAddr c.Pointer + MemTypeMask c.Uint32T + TargetCpuCount c.SizeT + TargetCpu [2]c.Int +} diff --git a/esp32/soc_ulp.go b/esp32/soc_ulp.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/soc_ulp.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/specreg.go b/esp32/specreg.go new file mode 100644 index 00000000..f6569432 --- /dev/null +++ b/esp32/specreg.go @@ -0,0 +1,81 @@ +package freertos + +import _ "unsafe" + +const LBEG = 0 +const LEND = 1 +const LCOUNT = 2 +const SAR = 3 +const BR = 4 +const SCOMPARE1 = 12 +const ACCLO = 16 +const ACCHI = 17 +const MR_0 = 32 +const MR_1 = 33 +const MR_2 = 34 +const MR_3 = 35 +const WINDOWBASE = 72 +const WINDOWSTART = 73 +const IBREAKENABLE = 96 +const MEMCTL = 97 +const ATOMCTL = 99 +const DDR = 104 +const IBREAKA_0 = 128 +const IBREAKA_1 = 129 +const DBREAKA_0 = 144 +const DBREAKA_1 = 145 +const DBREAKC_0 = 160 +const DBREAKC_1 = 161 +const CONFIGID0 = 176 +const EPC_1 = 177 +const EPC_2 = 178 +const EPC_3 = 179 +const EPC_4 = 180 +const EPC_5 = 181 +const EPC_6 = 182 +const EPC_7 = 183 +const DEPC = 192 +const EPS_2 = 194 +const EPS_3 = 195 +const EPS_4 = 196 +const EPS_5 = 197 +const EPS_6 = 198 +const EPS_7 = 199 +const CONFIGID1 = 208 +const EXCSAVE_1 = 209 +const EXCSAVE_2 = 210 +const EXCSAVE_3 = 211 +const EXCSAVE_4 = 212 +const EXCSAVE_5 = 213 +const EXCSAVE_6 = 214 +const EXCSAVE_7 = 215 +const CPENABLE = 224 +const INTERRUPT = 226 +const INTENABLE = 228 +const PS = 230 +const VECBASE = 231 +const EXCCAUSE = 232 +const DEBUGCAUSE = 233 +const CCOUNT = 234 +const PRID = 235 +const ICOUNT = 236 +const ICOUNTLEVEL = 237 +const EXCVADDR = 238 +const CCOMPARE_0 = 240 +const CCOMPARE_1 = 241 +const CCOMPARE_2 = 242 +const MISC_REG_0 = 244 +const MISC_REG_1 = 245 +const MISC_REG_2 = 246 +const MISC_REG_3 = 247 +const MR = 32 +const IBREAKA = 128 +const DBREAKA = 144 +const DBREAKC = 160 +const EPC = 176 +const EPS = 192 +const EXCSAVE = 208 +const CCOMPARE = 240 +const INTREAD = 226 +const INTSET = 226 +const INTCLEAR = 227 diff --git a/esp32/spi_hal.go b/esp32/spi_hal.go new file mode 100644 index 00000000..f9667aa8 --- /dev/null +++ b/esp32/spi_hal.go @@ -0,0 +1,331 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Input parameters to the ``spi_hal_cal_clock_conf`` to calculate the timing configuration + */ + +type SpiHalTimingParamT struct { + ClkSrcHz c.Uint32T + HalfDuplex c.Uint32T + NoCompensate c.Uint32T + ExpectedFreq c.Uint32T + DutyCycle c.Uint32T + InputDelayNs c.Uint32T + UseGpio bool +} + +/** + * Timing configuration structure that should be calculated by + * ``spi_hal_cal_clock_conf`` at initialization and hold. Filled into the + * ``timing_conf`` member of the context of HAL before setup a device. + */ + +type SpiHalTimingConfT struct { + ClockReg SpiLlClockValT + ClockSource SpiClockSourceT + SourcePreDiv c.Uint32T + RealFreq c.Int + TimingDummy c.Int + TimingMisoDelay c.Int + RxSamplePoint SpiSamplingPointT +} + +/** + * Transaction configuration structure, this should be assigned by driver each time. + * All these parameters will be updated to the peripheral every transaction. + */ + +type SpiHalTransConfigT struct { + Cmd c.Uint16T + CmdBits c.Int + AddrBits c.Int + DummyBits c.Int + TxBitlen c.Int + RxBitlen c.Int + Addr c.Uint64T + SendBuffer *c.Uint8T + RcvBuffer *c.Uint8T + LineMode SpiLineModeT + CsKeepActive c.Int +} + +/** + * Context that should be maintained by both the driver and the HAL. + */ + +type SpiHalContextT struct { + Hw *SpiDevT + DmaEnabled bool + TransConfig SpiHalTransConfigT +} + +/** + * Device configuration structure, this should be initialised by driver based on different devices respectively. + * All these parameters will be updated to the peripheral only when ``spi_hal_setup_device``. + * They may not get updated when ``spi_hal_setup_trans``. + */ + +type SpiHalDevConfigT struct { + Mode c.Int + CsSetup c.Int + CsHold c.Int + CsPinId c.Int + TimingConf SpiHalTimingConfT +} + +/** + * SCT mode required configurations, per segment + */ + +type SpiHalSegConfigT struct { + SegEnd bool + SegGapLen c.Uint32T + CsSetup c.Int + Cmd c.Uint16T + CmdBits c.Int + Addr c.Uint64T + AddrBits c.Int + DummyBits c.Int + TxBitlen c.Int + RxBitlen c.Int + CsHold c.Int +} + +/** + * Init the peripheral and the context. + * + * @param hal Context of the HAL layer. + * @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for SPI2 and 2 for SPI3. + */ +// llgo:link (*SpiHalContextT).SpiHalInit C.spi_hal_init +func (recv_ *SpiHalContextT) SpiHalInit(host_id c.Uint32T) { +} + +/** + * Config default output IO level when don't have transaction + * + * @param hal Context of the HAL layer. + * @param level IO level to config + */ +// llgo:link (*SpiHalContextT).SpiHalConfigIoDefaultLevel C.spi_hal_config_io_default_level +func (recv_ *SpiHalContextT) SpiHalConfigIoDefaultLevel(level bool) { +} + +/** + * Deinit the peripheral (and the context if needed). + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiHalContextT).SpiHalDeinit C.spi_hal_deinit +func (recv_ *SpiHalContextT) SpiHalDeinit() { +} + +/** + * Setup device-related configurations according to the settings in the context. + * + * @param hal Context of the HAL layer. + * @param hal_dev Device configuration + */ +// llgo:link (*SpiHalContextT).SpiHalSetupDevice C.spi_hal_setup_device +func (recv_ *SpiHalContextT) SpiHalSetupDevice(hal_dev *SpiHalDevConfigT) { +} + +/** + * Setup transaction related configurations according to the settings in the context. + * + * @param hal Context of the HAL layer. + * @param hal_dev Device configuration + * @param hal_trans Transaction configuration + */ +// llgo:link (*SpiHalContextT).SpiHalSetupTrans C.spi_hal_setup_trans +func (recv_ *SpiHalContextT) SpiHalSetupTrans(hal_dev *SpiHalDevConfigT, hal_trans *SpiHalTransConfigT) { +} + +/** + * Enable/Disable miso/mosi signals on peripheral side + * + * @param hw Beginning address of the peripheral registers. + * @param mosi_ena enable/disable mosi line + * @param miso_ena enable/disable miso line + */ +// llgo:link (*SpiDevT).SpiHalEnableDataLine C.spi_hal_enable_data_line +func (recv_ *SpiDevT) SpiHalEnableDataLine(mosi_ena bool, miso_ena bool) { +} + +/** + * Prepare tx hardware for a new DMA trans + * + * @param hw Beginning address of the peripheral registers. + */ +// llgo:link (*SpiDevT).SpiHalHwPrepareRx C.spi_hal_hw_prepare_rx +func (recv_ *SpiDevT) SpiHalHwPrepareRx() { +} + +/** + * Prepare tx hardware for a new DMA trans + * + * @param hw Beginning address of the peripheral registers. + */ +// llgo:link (*SpiDevT).SpiHalHwPrepareTx C.spi_hal_hw_prepare_tx +func (recv_ *SpiDevT) SpiHalHwPrepareTx() { +} + +/** + * Trigger start a user-defined transaction. + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiHalContextT).SpiHalUserStart C.spi_hal_user_start +func (recv_ *SpiHalContextT) SpiHalUserStart() { +} + +/** + * Check whether the transaction is done (trans_done is set). + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiHalContextT).SpiHalUsrIsDone C.spi_hal_usr_is_done +func (recv_ *SpiHalContextT) SpiHalUsrIsDone() bool { + return false +} + +/** + * Setup transaction operations, write tx buffer to HW registers + * + * @param hal Context of the HAL layer. + * @param hal_trans Transaction configuration. + */ +// llgo:link (*SpiHalContextT).SpiHalPushTxBuffer C.spi_hal_push_tx_buffer +func (recv_ *SpiHalContextT) SpiHalPushTxBuffer(hal_trans *SpiHalTransConfigT) { +} + +/** + * Post transaction operations, mainly fetch data from the buffer. + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiHalContextT).SpiHalFetchResult C.spi_hal_fetch_result +func (recv_ *SpiHalContextT) SpiHalFetchResult() { +} + +/*---------------------------------------------------------- + * Utils + * ---------------------------------------------------------*/ +/** + * Calculate the configuration of clock and timing. The configuration will be used when ``spi_hal_setup_device``. + * + * It is highly suggested to do this at initialization, since it takes long time. + * + * @param timing_param Input parameters to calculate timing configuration + * @param timing_conf Output of the timing configuration. + * + * @return ESP_OK if desired is available, otherwise fail. + */ +// llgo:link (*SpiHalTimingParamT).SpiHalCalClockConf C.spi_hal_cal_clock_conf +func (recv_ *SpiHalTimingParamT) SpiHalCalClockConf(timing_conf *SpiHalTimingConfT) EspErrT { + return 0 +} + +/** + * Get the frequency actual used. + * + * @param hal Context of the HAL layer. + * @param fapb APB clock frequency. + * @param hz Desired frequencyc. + * @param duty_cycle Desired duty cycle. + */ +//go:linkname SpiHalMasterCalClock C.spi_hal_master_cal_clock +func SpiHalMasterCalClock(fapb c.Int, hz c.Int, duty_cycle c.Int) c.Int + +/** + * Get the timing configuration for given parameters. + * + * @param source_freq_hz Clock freq of selected clock source for SPI in Hz. + * @param eff_clk Actual SPI clock frequency + * @param gpio_is_used true if the GPIO matrix is used, otherwise false. + * @param input_delay_ns Maximum delay between SPI launch clock and the data to + * be valid. This is used to compensate/calculate the maximum frequency + * allowed. Left 0 if not known. + * @param dummy_n Dummy cycles required to correctly read the data. + * @param miso_delay_n suggested delay on the MISO line, in APB clocks. + */ +//go:linkname SpiHalCalTiming C.spi_hal_cal_timing +func SpiHalCalTiming(source_freq_hz c.Int, eff_clk c.Int, gpio_is_used bool, input_delay_ns c.Int, dummy_n *c.Int, miso_delay_n *c.Int) + +/** + * Get the maximum frequency allowed to read if no compensation is used. + * + * @param gpio_is_used true if the GPIO matrix is used, otherwise false. + * @param input_delay_ns Maximum delay between SPI launch clock and the data to + * be valid. This is used to compensate/calculate the maximum frequency + * allowed. Left 0 if not known. + */ +//go:linkname SpiHalGetFreqLimit C.spi_hal_get_freq_limit +func SpiHalGetFreqLimit(gpio_is_used bool, input_delay_ns c.Int) c.Int + +/*---------------------------------------------------------- + * Segmented-Configure-Transfer (SCT) Mode + * ---------------------------------------------------------*/ +/** + * Initialise SCT mode required registers and hal states + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiHalContextT).SpiHalSctInit C.spi_hal_sct_init +func (recv_ *SpiHalContextT) SpiHalSctInit() { +} + +/** + * Initialise conf buffer, give it an initial value + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiHalContextT).SpiHalSctInitConfBuffer C.spi_hal_sct_init_conf_buffer +func (recv_ *SpiHalContextT) SpiHalSctInitConfBuffer(conf_buffer *c.Uint32T) { +} + +/** + * Format the conf buffer + * According to the `spi_hal_seg_config_t`, update the conf buffer + * + * @param hal Context of the HAL layer. + * @param config Conf buffer configuration, per segment. See `spi_hal_seg_config_t` to know what can be configured + * @param conf_buffer Conf buffer + */ +// llgo:link (*SpiHalContextT).SpiHalSctFormatConfBuffer C.spi_hal_sct_format_conf_buffer +func (recv_ *SpiHalContextT) SpiHalSctFormatConfBuffer(config *SpiHalSegConfigT, dev *SpiHalDevConfigT, conf_buffer *c.Uint32T) { +} + +/** + * Deinit SCT mode related registers and hal states + */ +// llgo:link (*SpiHalContextT).SpiHalSctDeinit C.spi_hal_sct_deinit +func (recv_ *SpiHalContextT) SpiHalSctDeinit() { +} + +/** + * Set conf_bitslen to HW for sct. + */ +// llgo:link (*SpiHalContextT).SpiHalSctSetConfBitsLen C.spi_hal_sct_set_conf_bits_len +func (recv_ *SpiHalContextT) SpiHalSctSetConfBitsLen(conf_len c.Uint32T) { +} + +/** + * Clear SPI interrupt bits by mask + */ +// llgo:link (*SpiHalContextT).SpiHalClearIntrMask C.spi_hal_clear_intr_mask +func (recv_ *SpiHalContextT) SpiHalClearIntrMask(mask c.Uint32T) { +} + +/** + * Get SPI interrupt bits status by mask + */ +// llgo:link (*SpiHalContextT).SpiHalGetIntrMask C.spi_hal_get_intr_mask +func (recv_ *SpiHalContextT) SpiHalGetIntrMask(mask c.Uint32T) bool { + return false +} diff --git a/esp32/spi_ll.go b/esp32/spi_ll.go new file mode 100644 index 00000000..823588a8 --- /dev/null +++ b/esp32/spi_ll.go @@ -0,0 +1,49 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const SPI_LL_MOSI_FREE_LEVEL = 1 + +type SpiLlClockValT c.Uint32T +type SpiDmaDevT SpiDevT +type SpiLlIntrT c.Int + +const ( + SPI_LL_INTR_TRANS_DONE SpiLlIntrT = 1 + SPI_LL_INTR_RDBUF SpiLlIntrT = 64 + SPI_LL_INTR_WRBUF SpiLlIntrT = 128 + SPI_LL_INTR_RDDMA SpiLlIntrT = 256 + SPI_LL_INTR_WRDMA SpiLlIntrT = 512 + SPI_LL_INTR_CMD7 SpiLlIntrT = 1024 + SPI_LL_INTR_CMD8 SpiLlIntrT = 2048 + SPI_LL_INTR_CMD9 SpiLlIntrT = 4096 + SPI_LL_INTR_CMDA SpiLlIntrT = 8192 + SPI_LL_INTR_SEG_DONE SpiLlIntrT = 16384 +) + +type SpiLlTransLenCondT c.Int + +const ( + SPI_LL_TRANS_LEN_COND_WRBUF SpiLlTransLenCondT = 1 + SPI_LL_TRANS_LEN_COND_RDBUF SpiLlTransLenCondT = 2 + SPI_LL_TRANS_LEN_COND_WRDMA SpiLlTransLenCondT = 4 + SPI_LL_TRANS_LEN_COND_RDDMA SpiLlTransLenCondT = 8 +) + +type SpiLlBaseCommandT c.Int + +const ( + SPI_LL_BASE_CMD_HD_WRBUF SpiLlBaseCommandT = 1 + SPI_LL_BASE_CMD_HD_RDBUF SpiLlBaseCommandT = 2 + SPI_LL_BASE_CMD_HD_WRDMA SpiLlBaseCommandT = 3 + SPI_LL_BASE_CMD_HD_RDDMA SpiLlBaseCommandT = 4 + SPI_LL_BASE_CMD_HD_SEG_END SpiLlBaseCommandT = 5 + SPI_LL_BASE_CMD_HD_EN_QPI SpiLlBaseCommandT = 6 + SPI_LL_BASE_CMD_HD_WR_END SpiLlBaseCommandT = 7 + SPI_LL_BASE_CMD_HD_INT0 SpiLlBaseCommandT = 8 + SPI_LL_BASE_CMD_HD_INT1 SpiLlBaseCommandT = 9 + SPI_LL_BASE_CMD_HD_INT2 SpiLlBaseCommandT = 10 +) diff --git a/esp32/spi_mem_reg.go b/esp32/spi_mem_reg.go new file mode 100644 index 00000000..3d542a6c --- /dev/null +++ b/esp32/spi_mem_reg.go @@ -0,0 +1,708 @@ +package freertos + +import _ "unsafe" + +const SPI_MEM_FLASH_READ_V = 0x1 +const SPI_MEM_FLASH_READ_S = 31 +const SPI_MEM_FLASH_WREN_V = 0x1 +const SPI_MEM_FLASH_WREN_S = 30 +const SPI_MEM_FLASH_WRDI_V = 0x1 +const SPI_MEM_FLASH_WRDI_S = 29 +const SPI_MEM_FLASH_RDID_V = 0x1 +const SPI_MEM_FLASH_RDID_S = 28 +const SPI_MEM_FLASH_RDSR_V = 0x1 +const SPI_MEM_FLASH_RDSR_S = 27 +const SPI_MEM_FLASH_WRSR_V = 0x1 +const SPI_MEM_FLASH_WRSR_S = 26 +const SPI_MEM_FLASH_PP_V = 0x1 +const SPI_MEM_FLASH_PP_S = 25 +const SPI_MEM_FLASH_SE_V = 0x1 +const SPI_MEM_FLASH_SE_S = 24 +const SPI_MEM_FLASH_BE_V = 0x1 +const SPI_MEM_FLASH_BE_S = 23 +const SPI_MEM_FLASH_CE_V = 0x1 +const SPI_MEM_FLASH_CE_S = 22 +const SPI_MEM_FLASH_DP_V = 0x1 +const SPI_MEM_FLASH_DP_S = 21 +const SPI_MEM_FLASH_RES_V = 0x1 +const SPI_MEM_FLASH_RES_S = 20 +const SPI_MEM_FLASH_HPM_V = 0x1 +const SPI_MEM_FLASH_HPM_S = 19 +const SPI_MEM_USR_V = 0x1 +const SPI_MEM_USR_S = 18 +const SPI_MEM_FLASH_PE_V = 0x1 +const SPI_MEM_FLASH_PE_S = 17 +const SPI_MEM_USR_ADDR_VALUE = 0xFFFFFFFF +const SPI_MEM_USR_ADDR_VALUE_V = 0xFFFFFFFF +const SPI_MEM_USR_ADDR_VALUE_S = 0 +const SPI_MEM_FREAD_QIO_V = 0x1 +const SPI_MEM_FREAD_QIO_S = 24 +const SPI_MEM_FREAD_DIO_V = 0x1 +const SPI_MEM_FREAD_DIO_S = 23 +const SPI_MEM_WRSR_2B_V = 0x1 +const SPI_MEM_WRSR_2B_S = 22 +const SPI_MEM_WP_REG_V = 0x1 +const SPI_MEM_WP_REG_S = 21 +const SPI_MEM_FREAD_QUAD_V = 0x1 +const SPI_MEM_FREAD_QUAD_S = 20 +const SPI_MEM_D_POL_V = 0x1 +const SPI_MEM_D_POL_S = 19 +const SPI_MEM_Q_POL_V = 0x1 +const SPI_MEM_Q_POL_S = 18 +const SPI_MEM_RESANDRES_V = 0x1 +const SPI_MEM_RESANDRES_S = 15 +const SPI_MEM_FREAD_DUAL_V = 0x1 +const SPI_MEM_FREAD_DUAL_S = 14 +const SPI_MEM_FASTRD_MODE_V = 0x1 +const SPI_MEM_FASTRD_MODE_S = 13 +const SPI_MEM_TX_CRC_EN_V = 0x1 +const SPI_MEM_TX_CRC_EN_S = 11 +const SPI_MEM_FCS_CRC_EN_V = 0x1 +const SPI_MEM_FCS_CRC_EN_S = 10 +const SPI_MEM_FCMD_OCT_V = 0x1 +const SPI_MEM_FCMD_OCT_S = 9 +const SPI_MEM_FCMD_QUAD_V = 0x1 +const SPI_MEM_FCMD_QUAD_S = 8 +const SPI_MEM_FCMD_DUAL_V = 0x1 +const SPI_MEM_FCMD_DUAL_S = 7 +const SPI_MEM_FADDR_OCT_V = 0x1 +const SPI_MEM_FADDR_OCT_S = 6 +const SPI_MEM_FDIN_OCT_V = 0x1 +const SPI_MEM_FDIN_OCT_S = 5 +const SPI_MEM_FDOUT_OCT_V = 0x1 +const SPI_MEM_FDOUT_OCT_S = 4 +const SPI_MEM_FDUMMY_OUT_V = 0x1 +const SPI_MEM_FDUMMY_OUT_S = 3 +const SPI_MEM_RXFIFO_RST_V = 0x1 +const SPI_MEM_RXFIFO_RST_S = 30 +const SPI_MEM_CS_HOLD_DLY_RES = 0x000003FF +const SPI_MEM_CS_HOLD_DLY_RES_V = 0x3FF +const SPI_MEM_CS_HOLD_DLY_RES_S = 2 +const SPI_MEM_CLK_MODE = 0x00000003 +const SPI_MEM_CLK_MODE_V = 0x3 +const SPI_MEM_CLK_MODE_S = 0 +const SPI_MEM_SYNC_RESET_V = 0x1 +const SPI_MEM_SYNC_RESET_S = 31 +const SPI_MEM_CS_HOLD_DELAY = 0x0000003F +const SPI_MEM_CS_HOLD_DELAY_V = 0x3F +const SPI_MEM_CS_HOLD_DELAY_S = 25 +const SPI_MEM_ECC_16TO18_BYTE_EN_V = 0x1 +const SPI_MEM_ECC_16TO18_BYTE_EN_S = 14 +const SPI_MEM_ECC_SKIP_PAGE_CORNER_V = 0x1 +const SPI_MEM_ECC_SKIP_PAGE_CORNER_S = 13 +const SPI_MEM_ECC_CS_HOLD_TIME = 0x00000007 +const SPI_MEM_ECC_CS_HOLD_TIME_V = 0x7 +const SPI_MEM_ECC_CS_HOLD_TIME_S = 10 +const SPI_MEM_CS_HOLD_TIME = 0x0000001F +const SPI_MEM_CS_HOLD_TIME_V = 0x1F +const SPI_MEM_CS_HOLD_TIME_S = 5 +const SPI_MEM_CS_SETUP_TIME = 0x0000001F +const SPI_MEM_CS_SETUP_TIME_V = 0x1F +const SPI_MEM_CS_SETUP_TIME_S = 0 +const SPI_MEM_CLK_EQU_SYSCLK_V = 0x1 +const SPI_MEM_CLK_EQU_SYSCLK_S = 31 +const SPI_MEM_CLKCNT_N = 0x000000FF +const SPI_MEM_CLKCNT_N_V = 0xFF +const SPI_MEM_CLKCNT_N_S = 16 +const SPI_MEM_CLKCNT_H = 0x000000FF +const SPI_MEM_CLKCNT_H_V = 0xFF +const SPI_MEM_CLKCNT_H_S = 8 +const SPI_MEM_CLKCNT_L = 0x000000FF +const SPI_MEM_CLKCNT_L_V = 0xFF +const SPI_MEM_CLKCNT_L_S = 0 +const SPI_MEM_USR_COMMAND_V = 0x1 +const SPI_MEM_USR_COMMAND_S = 31 +const SPI_MEM_USR_ADDR_V = 0x1 +const SPI_MEM_USR_ADDR_S = 30 +const SPI_MEM_USR_DUMMY_V = 0x1 +const SPI_MEM_USR_DUMMY_S = 29 +const SPI_MEM_USR_MISO_V = 0x1 +const SPI_MEM_USR_MISO_S = 28 +const SPI_MEM_USR_MOSI_V = 0x1 +const SPI_MEM_USR_MOSI_S = 27 +const SPI_MEM_USR_DUMMY_IDLE_V = 0x1 +const SPI_MEM_USR_DUMMY_IDLE_S = 26 +const SPI_MEM_USR_MOSI_HIGHPART_V = 0x1 +const SPI_MEM_USR_MOSI_HIGHPART_S = 25 +const SPI_MEM_USR_MISO_HIGHPART_V = 0x1 +const SPI_MEM_USR_MISO_HIGHPART_S = 24 +const SPI_MEM_FWRITE_QIO_V = 0x1 +const SPI_MEM_FWRITE_QIO_S = 15 +const SPI_MEM_FWRITE_DIO_V = 0x1 +const SPI_MEM_FWRITE_DIO_S = 14 +const SPI_MEM_FWRITE_QUAD_V = 0x1 +const SPI_MEM_FWRITE_QUAD_S = 13 +const SPI_MEM_FWRITE_DUAL_V = 0x1 +const SPI_MEM_FWRITE_DUAL_S = 12 +const SPI_MEM_CK_OUT_EDGE_V = 0x1 +const SPI_MEM_CK_OUT_EDGE_S = 9 +const SPI_MEM_CS_SETUP_V = 0x1 +const SPI_MEM_CS_SETUP_S = 7 +const SPI_MEM_CS_HOLD_V = 0x1 +const SPI_MEM_CS_HOLD_S = 6 +const SPI_MEM_USR_ADDR_BITLEN = 0x0000003F +const SPI_MEM_USR_ADDR_BITLEN_V = 0x3F +const SPI_MEM_USR_ADDR_BITLEN_S = 26 +const SPI_MEM_USR_DUMMY_CYCLELEN = 0x0000003F +const SPI_MEM_USR_DUMMY_CYCLELEN_V = 0x3F +const SPI_MEM_USR_DUMMY_CYCLELEN_S = 0 +const SPI_MEM_USR_COMMAND_BITLEN = 0x0000000F +const SPI_MEM_USR_COMMAND_BITLEN_V = 0xF +const SPI_MEM_USR_COMMAND_BITLEN_S = 28 +const SPI_MEM_USR_COMMAND_VALUE = 0x0000FFFF +const SPI_MEM_USR_COMMAND_VALUE_V = 0xFFFF +const SPI_MEM_USR_COMMAND_VALUE_S = 0 +const SPI_MEM_USR_MOSI_DBITLEN = 0x000003FF +const SPI_MEM_USR_MOSI_DBITLEN_V = 0x3FF +const SPI_MEM_USR_MOSI_DBITLEN_S = 0 +const SPI_MEM_USR_MISO_DBITLEN = 0x000003FF +const SPI_MEM_USR_MISO_DBITLEN_V = 0x3FF +const SPI_MEM_USR_MISO_DBITLEN_S = 0 +const SPI_MEM_WB_MODE = 0x000000FF +const SPI_MEM_WB_MODE_V = 0xFF +const SPI_MEM_WB_MODE_S = 16 +const SPI_MEM_STATUS = 0x0000FFFF +const SPI_MEM_STATUS_V = 0xFFFF +const SPI_MEM_STATUS_S = 0 +const SPI_MEM_EXT_ADDR = 0xFFFFFFFF +const SPI_MEM_EXT_ADDR_V = 0xFFFFFFFF +const SPI_MEM_EXT_ADDR_S = 0 +const SPI_MEM_AUTO_PER_V = 0x1 +const SPI_MEM_AUTO_PER_S = 11 +const SPI_MEM_CS_KEEP_ACTIVE_V = 0x1 +const SPI_MEM_CS_KEEP_ACTIVE_S = 10 +const SPI_MEM_CK_IDLE_EDGE_V = 0x1 +const SPI_MEM_CK_IDLE_EDGE_S = 9 +const SPI_MEM_SSUB_PIN_V = 0x1 +const SPI_MEM_SSUB_PIN_S = 8 +const SPI_MEM_FSUB_PIN_V = 0x1 +const SPI_MEM_FSUB_PIN_S = 7 +const SPI_MEM_CS1_DIS_V = 0x1 +const SPI_MEM_CS1_DIS_S = 1 +const SPI_MEM_CS0_DIS_V = 0x1 +const SPI_MEM_CS0_DIS_S = 0 +const SPI_MEM_TX_CRC_DATA = 0xFFFFFFFF +const SPI_MEM_TX_CRC_DATA_V = 0xFFFFFFFF +const SPI_MEM_TX_CRC_DATA_S = 0 +const SPI_MEM_FADDR_QUAD_V = 0x1 +const SPI_MEM_FADDR_QUAD_S = 8 +const SPI_MEM_FDOUT_QUAD_V = 0x1 +const SPI_MEM_FDOUT_QUAD_S = 7 +const SPI_MEM_FDIN_QUAD_V = 0x1 +const SPI_MEM_FDIN_QUAD_S = 6 +const SPI_MEM_FADDR_DUAL_V = 0x1 +const SPI_MEM_FADDR_DUAL_S = 5 +const SPI_MEM_FDOUT_DUAL_V = 0x1 +const SPI_MEM_FDOUT_DUAL_S = 4 +const SPI_MEM_FDIN_DUAL_V = 0x1 +const SPI_MEM_FDIN_DUAL_S = 3 +const SPI_MEM_CACHE_FLASH_USR_CMD_V = 0x1 +const SPI_MEM_CACHE_FLASH_USR_CMD_S = 2 +const SPI_MEM_CACHE_USR_CMD_4BYTE_V = 0x1 +const SPI_MEM_CACHE_USR_CMD_4BYTE_S = 1 +const SPI_MEM_CACHE_REQ_EN_V = 0x1 +const SPI_MEM_CACHE_REQ_EN_S = 0 +const SPI_MEM_SRAM_WDUMMY_CYCLELEN = 0x0000003F +const SPI_MEM_SRAM_WDUMMY_CYCLELEN_V = 0x3F +const SPI_MEM_SRAM_WDUMMY_CYCLELEN_S = 22 +const SPI_MEM_SRAM_OCT_V = 0x1 +const SPI_MEM_SRAM_OCT_S = 21 +const SPI_MEM_CACHE_SRAM_USR_WCMD_V = 0x1 +const SPI_MEM_CACHE_SRAM_USR_WCMD_S = 20 +const SPI_MEM_SRAM_ADDR_BITLEN = 0x0000003F +const SPI_MEM_SRAM_ADDR_BITLEN_V = 0x3F +const SPI_MEM_SRAM_ADDR_BITLEN_S = 14 +const SPI_MEM_SRAM_RDUMMY_CYCLELEN = 0x0000003F +const SPI_MEM_SRAM_RDUMMY_CYCLELEN_V = 0x3F +const SPI_MEM_SRAM_RDUMMY_CYCLELEN_S = 6 +const SPI_MEM_CACHE_SRAM_USR_RCMD_V = 0x1 +const SPI_MEM_CACHE_SRAM_USR_RCMD_S = 5 +const SPI_MEM_USR_RD_SRAM_DUMMY_V = 0x1 +const SPI_MEM_USR_RD_SRAM_DUMMY_S = 4 +const SPI_MEM_USR_WR_SRAM_DUMMY_V = 0x1 +const SPI_MEM_USR_WR_SRAM_DUMMY_S = 3 +const SPI_MEM_USR_SRAM_QIO_V = 0x1 +const SPI_MEM_USR_SRAM_QIO_S = 2 +const SPI_MEM_USR_SRAM_DIO_V = 0x1 +const SPI_MEM_USR_SRAM_DIO_S = 1 +const SPI_MEM_CACHE_USR_SCMD_4BYTE_V = 0x1 +const SPI_MEM_CACHE_USR_SCMD_4BYTE_S = 0 +const SPI_MEM_SDUMMY_OUT_V = 0x1 +const SPI_MEM_SDUMMY_OUT_S = 22 +const SPI_MEM_SCMD_OCT_V = 0x1 +const SPI_MEM_SCMD_OCT_S = 21 +const SPI_MEM_SADDR_OCT_V = 0x1 +const SPI_MEM_SADDR_OCT_S = 20 +const SPI_MEM_SDOUT_OCT_V = 0x1 +const SPI_MEM_SDOUT_OCT_S = 19 +const SPI_MEM_SDIN_OCT_V = 0x1 +const SPI_MEM_SDIN_OCT_S = 18 +const SPI_MEM_SCMD_QUAD_V = 0x1 +const SPI_MEM_SCMD_QUAD_S = 17 +const SPI_MEM_SADDR_QUAD_V = 0x1 +const SPI_MEM_SADDR_QUAD_S = 16 +const SPI_MEM_SDOUT_QUAD_V = 0x1 +const SPI_MEM_SDOUT_QUAD_S = 15 +const SPI_MEM_SDIN_QUAD_V = 0x1 +const SPI_MEM_SDIN_QUAD_S = 14 +const SPI_MEM_SCMD_DUAL_V = 0x1 +const SPI_MEM_SCMD_DUAL_S = 13 +const SPI_MEM_SADDR_DUAL_V = 0x1 +const SPI_MEM_SADDR_DUAL_S = 12 +const SPI_MEM_SDOUT_DUAL_V = 0x1 +const SPI_MEM_SDOUT_DUAL_S = 11 +const SPI_MEM_SDIN_DUAL_V = 0x1 +const SPI_MEM_SDIN_DUAL_S = 10 +const SPI_MEM_SWB_MODE = 0x000000FF +const SPI_MEM_SWB_MODE_V = 0xFF +const SPI_MEM_SWB_MODE_S = 2 +const SPI_MEM_SCLK_MODE = 0x00000003 +const SPI_MEM_SCLK_MODE_V = 0x3 +const SPI_MEM_SCLK_MODE_S = 0 +const SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN = 0x0000000F +const SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V = 0xF +const SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S = 28 +const SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE = 0x0000FFFF +const SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V = 0xFFFF +const SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S = 0 +const SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN = 0x0000000F +const SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V = 0xF +const SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S = 28 +const SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE = 0x0000FFFF +const SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V = 0xFFFF +const SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S = 0 +const SPI_MEM_SCLK_EQU_SYSCLK_V = 0x1 +const SPI_MEM_SCLK_EQU_SYSCLK_S = 31 +const SPI_MEM_SCLKCNT_N = 0x000000FF +const SPI_MEM_SCLKCNT_N_V = 0xFF +const SPI_MEM_SCLKCNT_N_S = 16 +const SPI_MEM_SCLKCNT_H = 0x000000FF +const SPI_MEM_SCLKCNT_H_V = 0xFF +const SPI_MEM_SCLKCNT_H_S = 8 +const SPI_MEM_SCLKCNT_L = 0x000000FF +const SPI_MEM_SCLKCNT_L_V = 0xFF +const SPI_MEM_SCLKCNT_L_S = 0 +const SPI_MEM_ST = 0x00000007 +const SPI_MEM_ST_V = 0x7 +const SPI_MEM_ST_S = 0 +const SPI_MEM_BUF0 = 0xFFFFFFFF +const SPI_MEM_BUF0_V = 0xFFFFFFFF +const SPI_MEM_BUF0_S = 0 +const SPI_MEM_BUF1 = 0xFFFFFFFF +const SPI_MEM_BUF1_V = 0xFFFFFFFF +const SPI_MEM_BUF1_S = 0 +const SPI_MEM_BUF2 = 0xFFFFFFFF +const SPI_MEM_BUF2_V = 0xFFFFFFFF +const SPI_MEM_BUF2_S = 0 +const SPI_MEM_BUF3 = 0xFFFFFFFF +const SPI_MEM_BUF3_V = 0xFFFFFFFF +const SPI_MEM_BUF3_S = 0 +const SPI_MEM_BUF4 = 0xFFFFFFFF +const SPI_MEM_BUF4_V = 0xFFFFFFFF +const SPI_MEM_BUF4_S = 0 +const SPI_MEM_BUF5 = 0xFFFFFFFF +const SPI_MEM_BUF5_V = 0xFFFFFFFF +const SPI_MEM_BUF5_S = 0 +const SPI_MEM_BUF6 = 0xFFFFFFFF +const SPI_MEM_BUF6_V = 0xFFFFFFFF +const SPI_MEM_BUF6_S = 0 +const SPI_MEM_BUF7 = 0xFFFFFFFF +const SPI_MEM_BUF7_V = 0xFFFFFFFF +const SPI_MEM_BUF7_S = 0 +const SPI_MEM_BUF8 = 0xFFFFFFFF +const SPI_MEM_BUF8_V = 0xFFFFFFFF +const SPI_MEM_BUF8_S = 0 +const SPI_MEM_BUF9 = 0xFFFFFFFF +const SPI_MEM_BUF9_V = 0xFFFFFFFF +const SPI_MEM_BUF9_S = 0 +const SPI_MEM_BUF10 = 0xFFFFFFFF +const SPI_MEM_BUF10_V = 0xFFFFFFFF +const SPI_MEM_BUF10_S = 0 +const SPI_MEM_BUF11 = 0xFFFFFFFF +const SPI_MEM_BUF11_V = 0xFFFFFFFF +const SPI_MEM_BUF11_S = 0 +const SPI_MEM_BUF12 = 0xFFFFFFFF +const SPI_MEM_BUF12_V = 0xFFFFFFFF +const SPI_MEM_BUF12_S = 0 +const SPI_MEM_BUF13 = 0xFFFFFFFF +const SPI_MEM_BUF13_V = 0xFFFFFFFF +const SPI_MEM_BUF13_S = 0 +const SPI_MEM_BUF14 = 0xFFFFFFFF +const SPI_MEM_BUF14_V = 0xFFFFFFFF +const SPI_MEM_BUF14_S = 0 +const SPI_MEM_BUF15 = 0xFFFFFFFF +const SPI_MEM_BUF15_V = 0xFFFFFFFF +const SPI_MEM_BUF15_S = 0 +const SPI_MEM_WAITI_DUMMY_CYCLELEN = 0x0000003F +const SPI_MEM_WAITI_DUMMY_CYCLELEN_V = 0x3F +const SPI_MEM_WAITI_DUMMY_CYCLELEN_S = 10 +const SPI_MEM_WAITI_CMD = 0x000000FF +const SPI_MEM_WAITI_CMD_V = 0xFF +const SPI_MEM_WAITI_CMD_S = 2 +const SPI_MEM_WAITI_DUMMY_V = 0x1 +const SPI_MEM_WAITI_DUMMY_S = 1 +const SPI_MEM_WAITI_EN_V = 0x1 +const SPI_MEM_WAITI_EN_S = 0 +const SPI_MEM_PESR_IDLE_EN_V = 0x1 +const SPI_MEM_PESR_IDLE_EN_S = 5 +const SPI_MEM_PES_PER_EN_V = 0x1 +const SPI_MEM_PES_PER_EN_S = 4 +const SPI_MEM_FLASH_PES_WAIT_EN_V = 0x1 +const SPI_MEM_FLASH_PES_WAIT_EN_S = 3 +const SPI_MEM_FLASH_PER_WAIT_EN_V = 0x1 +const SPI_MEM_FLASH_PER_WAIT_EN_S = 2 +const SPI_MEM_FLASH_PES_V = 0x1 +const SPI_MEM_FLASH_PES_S = 1 +const SPI_MEM_FLASH_PER_V = 0x1 +const SPI_MEM_FLASH_PER_S = 0 +const SPI_MEM_FLASH_PES_COMMAND = 0x000000FF +const SPI_MEM_FLASH_PES_COMMAND_V = 0xFF +const SPI_MEM_FLASH_PES_COMMAND_S = 9 +const SPI_MEM_FLASH_PER_COMMAND = 0x000000FF +const SPI_MEM_FLASH_PER_COMMAND_V = 0xFF +const SPI_MEM_FLASH_PER_COMMAND_S = 1 +const SPI_MEM_FLASH_PES_EN_V = 0x1 +const SPI_MEM_FLASH_PES_EN_S = 0 +const SPI_MEM_FLASH_PES_DLY_256_V = 0x1 +const SPI_MEM_FLASH_PES_DLY_256_S = 6 +const SPI_MEM_FLASH_PER_DLY_256_V = 0x1 +const SPI_MEM_FLASH_PER_DLY_256_S = 5 +const SPI_MEM_FLASH_DP_DLY_256_V = 0x1 +const SPI_MEM_FLASH_DP_DLY_256_S = 4 +const SPI_MEM_FLASH_RES_DLY_256_V = 0x1 +const SPI_MEM_FLASH_RES_DLY_256_S = 3 +const SPI_MEM_FLASH_HPM_DLY_256_V = 0x1 +const SPI_MEM_FLASH_HPM_DLY_256_S = 2 +const SPI_MEM_FLASH_SUS_V = 0x1 +const SPI_MEM_FLASH_SUS_S = 0 +const SPI_MEM_EXTRA_DUMMY_CYCLELEN = 0x00000007 +const SPI_MEM_EXTRA_DUMMY_CYCLELEN_V = 0x7 +const SPI_MEM_EXTRA_DUMMY_CYCLELEN_S = 2 +const SPI_MEM_TIMING_CALI_V = 0x1 +const SPI_MEM_TIMING_CALI_S = 1 +const SPI_MEM_TIMING_CLK_ENA_V = 0x1 +const SPI_MEM_TIMING_CLK_ENA_S = 0 +const SPI_MEM_DINS_MODE = 0x00000007 +const SPI_MEM_DINS_MODE_V = 0x7 +const SPI_MEM_DINS_MODE_S = 24 +const SPI_MEM_DIN7_MODE = 0x00000007 +const SPI_MEM_DIN7_MODE_V = 0x7 +const SPI_MEM_DIN7_MODE_S = 21 +const SPI_MEM_DIN6_MODE = 0x00000007 +const SPI_MEM_DIN6_MODE_V = 0x7 +const SPI_MEM_DIN6_MODE_S = 18 +const SPI_MEM_DIN5_MODE = 0x00000007 +const SPI_MEM_DIN5_MODE_V = 0x7 +const SPI_MEM_DIN5_MODE_S = 15 +const SPI_MEM_DIN4_MODE = 0x00000007 +const SPI_MEM_DIN4_MODE_V = 0x7 +const SPI_MEM_DIN4_MODE_S = 12 +const SPI_MEM_DIN3_MODE = 0x00000007 +const SPI_MEM_DIN3_MODE_V = 0x7 +const SPI_MEM_DIN3_MODE_S = 9 +const SPI_MEM_DIN2_MODE = 0x00000007 +const SPI_MEM_DIN2_MODE_V = 0x7 +const SPI_MEM_DIN2_MODE_S = 6 +const SPI_MEM_DIN1_MODE = 0x00000007 +const SPI_MEM_DIN1_MODE_V = 0x7 +const SPI_MEM_DIN1_MODE_S = 3 +const SPI_MEM_DIN0_MODE = 0x00000007 +const SPI_MEM_DIN0_MODE_V = 0x7 +const SPI_MEM_DIN0_MODE_S = 0 +const SPI_MEM_DINS_NUM = 0x00000003 +const SPI_MEM_DINS_NUM_V = 0x3 +const SPI_MEM_DINS_NUM_S = 16 +const SPI_MEM_DIN7_NUM = 0x00000003 +const SPI_MEM_DIN7_NUM_V = 0x3 +const SPI_MEM_DIN7_NUM_S = 14 +const SPI_MEM_DIN6_NUM = 0x00000003 +const SPI_MEM_DIN6_NUM_V = 0x3 +const SPI_MEM_DIN6_NUM_S = 12 +const SPI_MEM_DIN5_NUM = 0x00000003 +const SPI_MEM_DIN5_NUM_V = 0x3 +const SPI_MEM_DIN5_NUM_S = 10 +const SPI_MEM_DIN4_NUM = 0x00000003 +const SPI_MEM_DIN4_NUM_V = 0x3 +const SPI_MEM_DIN4_NUM_S = 8 +const SPI_MEM_DIN3_NUM = 0x00000003 +const SPI_MEM_DIN3_NUM_V = 0x3 +const SPI_MEM_DIN3_NUM_S = 6 +const SPI_MEM_DIN2_NUM = 0x00000003 +const SPI_MEM_DIN2_NUM_V = 0x3 +const SPI_MEM_DIN2_NUM_S = 4 +const SPI_MEM_DIN1_NUM = 0x00000003 +const SPI_MEM_DIN1_NUM_V = 0x3 +const SPI_MEM_DIN1_NUM_S = 2 +const SPI_MEM_DIN0_NUM = 0x00000003 +const SPI_MEM_DIN0_NUM_V = 0x3 +const SPI_MEM_DIN0_NUM_S = 0 +const SPI_MEM_DOUTS_MODE_V = 0x1 +const SPI_MEM_DOUTS_MODE_S = 8 +const SPI_MEM_DOUT7_MODE_V = 0x1 +const SPI_MEM_DOUT7_MODE_S = 7 +const SPI_MEM_DOUT6_MODE_V = 0x1 +const SPI_MEM_DOUT6_MODE_S = 6 +const SPI_MEM_DOUT5_MODE_V = 0x1 +const SPI_MEM_DOUT5_MODE_S = 5 +const SPI_MEM_DOUT4_MODE_V = 0x1 +const SPI_MEM_DOUT4_MODE_S = 4 +const SPI_MEM_DOUT3_MODE_V = 0x1 +const SPI_MEM_DOUT3_MODE_S = 3 +const SPI_MEM_DOUT2_MODE_V = 0x1 +const SPI_MEM_DOUT2_MODE_S = 2 +const SPI_MEM_DOUT1_MODE_V = 0x1 +const SPI_MEM_DOUT1_MODE_S = 1 +const SPI_MEM_DOUT0_MODE_V = 0x1 +const SPI_MEM_DOUT0_MODE_S = 0 +const SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN = 0x00000007 +const SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V = 0x7 +const SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S = 2 +const SPI_MEM_SPI_SMEM_TIMING_CALI_V = 0x1 +const SPI_MEM_SPI_SMEM_TIMING_CALI_S = 1 +const SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V = 0x1 +const SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S = 0 +const SPI_MEM_SPI_SMEM_DINS_MODE = 0x00000007 +const SPI_MEM_SPI_SMEM_DINS_MODE_V = 0x7 +const SPI_MEM_SPI_SMEM_DINS_MODE_S = 24 +const SPI_MEM_SPI_SMEM_DIN7_MODE = 0x00000007 +const SPI_MEM_SPI_SMEM_DIN7_MODE_V = 0x7 +const SPI_MEM_SPI_SMEM_DIN7_MODE_S = 21 +const SPI_MEM_SPI_SMEM_DIN6_MODE = 0x00000007 +const SPI_MEM_SPI_SMEM_DIN6_MODE_V = 0x7 +const SPI_MEM_SPI_SMEM_DIN6_MODE_S = 18 +const SPI_MEM_SPI_SMEM_DIN5_MODE = 0x00000007 +const SPI_MEM_SPI_SMEM_DIN5_MODE_V = 0x7 +const SPI_MEM_SPI_SMEM_DIN5_MODE_S = 15 +const SPI_MEM_SPI_SMEM_DIN4_MODE = 0x00000007 +const SPI_MEM_SPI_SMEM_DIN4_MODE_V = 0x7 +const SPI_MEM_SPI_SMEM_DIN4_MODE_S = 12 +const SPI_MEM_SPI_SMEM_DIN3_MODE = 0x00000007 +const SPI_MEM_SPI_SMEM_DIN3_MODE_V = 0x7 +const SPI_MEM_SPI_SMEM_DIN3_MODE_S = 9 +const SPI_MEM_SPI_SMEM_DIN2_MODE = 0x00000007 +const SPI_MEM_SPI_SMEM_DIN2_MODE_V = 0x7 +const SPI_MEM_SPI_SMEM_DIN2_MODE_S = 6 +const SPI_MEM_SPI_SMEM_DIN1_MODE = 0x00000007 +const SPI_MEM_SPI_SMEM_DIN1_MODE_V = 0x7 +const SPI_MEM_SPI_SMEM_DIN1_MODE_S = 3 +const SPI_MEM_SPI_SMEM_DIN0_MODE = 0x00000007 +const SPI_MEM_SPI_SMEM_DIN0_MODE_V = 0x7 +const SPI_MEM_SPI_SMEM_DIN0_MODE_S = 0 +const SPI_MEM_SPI_SMEM_DINS_NUM = 0x00000003 +const SPI_MEM_SPI_SMEM_DINS_NUM_V = 0x3 +const SPI_MEM_SPI_SMEM_DINS_NUM_S = 16 +const SPI_MEM_SPI_SMEM_DIN7_NUM = 0x00000003 +const SPI_MEM_SPI_SMEM_DIN7_NUM_V = 0x3 +const SPI_MEM_SPI_SMEM_DIN7_NUM_S = 14 +const SPI_MEM_SPI_SMEM_DIN6_NUM = 0x00000003 +const SPI_MEM_SPI_SMEM_DIN6_NUM_V = 0x3 +const SPI_MEM_SPI_SMEM_DIN6_NUM_S = 12 +const SPI_MEM_SPI_SMEM_DIN5_NUM = 0x00000003 +const SPI_MEM_SPI_SMEM_DIN5_NUM_V = 0x3 +const SPI_MEM_SPI_SMEM_DIN5_NUM_S = 10 +const SPI_MEM_SPI_SMEM_DIN4_NUM = 0x00000003 +const SPI_MEM_SPI_SMEM_DIN4_NUM_V = 0x3 +const SPI_MEM_SPI_SMEM_DIN4_NUM_S = 8 +const SPI_MEM_SPI_SMEM_DIN3_NUM = 0x00000003 +const SPI_MEM_SPI_SMEM_DIN3_NUM_V = 0x3 +const SPI_MEM_SPI_SMEM_DIN3_NUM_S = 6 +const SPI_MEM_SPI_SMEM_DIN2_NUM = 0x00000003 +const SPI_MEM_SPI_SMEM_DIN2_NUM_V = 0x3 +const SPI_MEM_SPI_SMEM_DIN2_NUM_S = 4 +const SPI_MEM_SPI_SMEM_DIN1_NUM = 0x00000003 +const SPI_MEM_SPI_SMEM_DIN1_NUM_V = 0x3 +const SPI_MEM_SPI_SMEM_DIN1_NUM_S = 2 +const SPI_MEM_SPI_SMEM_DIN0_NUM = 0x00000003 +const SPI_MEM_SPI_SMEM_DIN0_NUM_V = 0x3 +const SPI_MEM_SPI_SMEM_DIN0_NUM_S = 0 +const SPI_MEM_SPI_SMEM_DOUTS_MODE_V = 0x1 +const SPI_MEM_SPI_SMEM_DOUTS_MODE_S = 8 +const SPI_MEM_SPI_SMEM_DOUT7_MODE_V = 0x1 +const SPI_MEM_SPI_SMEM_DOUT7_MODE_S = 7 +const SPI_MEM_SPI_SMEM_DOUT6_MODE_V = 0x1 +const SPI_MEM_SPI_SMEM_DOUT6_MODE_S = 6 +const SPI_MEM_SPI_SMEM_DOUT5_MODE_V = 0x1 +const SPI_MEM_SPI_SMEM_DOUT5_MODE_S = 5 +const SPI_MEM_SPI_SMEM_DOUT4_MODE_V = 0x1 +const SPI_MEM_SPI_SMEM_DOUT4_MODE_S = 4 +const SPI_MEM_SPI_SMEM_DOUT3_MODE_V = 0x1 +const SPI_MEM_SPI_SMEM_DOUT3_MODE_S = 3 +const SPI_MEM_SPI_SMEM_DOUT2_MODE_V = 0x1 +const SPI_MEM_SPI_SMEM_DOUT2_MODE_S = 2 +const SPI_MEM_SPI_SMEM_DOUT1_MODE_V = 0x1 +const SPI_MEM_SPI_SMEM_DOUT1_MODE_S = 1 +const SPI_MEM_SPI_SMEM_DOUT0_MODE_V = 0x1 +const SPI_MEM_SPI_SMEM_DOUT0_MODE_S = 0 +const SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_V = 0x1 +const SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_S = 8 +const SPI_MEM_ECC_ERR_INT_NUM = 0x000000FF +const SPI_MEM_ECC_ERR_INT_NUM_V = 0xFF +const SPI_MEM_ECC_ERR_INT_NUM_S = 0 +const SPI_MEM_ECC_ERR_ADDR = 0xFFFFFFFF +const SPI_MEM_ECC_ERR_ADDR_V = 0xFFFFFFFF +const SPI_MEM_ECC_ERR_ADDR_S = 0 +const SPI_MEM_ECC_ERR_CNT = 0x000000FF +const SPI_MEM_ECC_ERR_CNT_V = 0xFF +const SPI_MEM_ECC_ERR_CNT_S = 17 +const SPI_MEM_ECC_BYTE_ERR_V = 0x1 +const SPI_MEM_ECC_BYTE_ERR_S = 16 +const SPI_MEM_ECC_CHK_ERR_BIT = 0x00000007 +const SPI_MEM_ECC_CHK_ERR_BIT_V = 0x7 +const SPI_MEM_ECC_CHK_ERR_BIT_S = 13 +const SPI_MEM_ECC_DATA_ERR_BIT = 0x0000007F +const SPI_MEM_ECC_DATA_ERR_BIT_V = 0x7F +const SPI_MEM_ECC_DATA_ERR_BIT_S = 6 +const SPI_MEM_SPI_SMEM_CS_HOLD_DELAY = 0x0000003F +const SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V = 0x3F +const SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S = 25 +const SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_V = 0x1 +const SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_S = 24 +const SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V = 0x1 +const SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S = 16 +const SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V = 0x1 +const SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S = 15 +const SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME = 0x00000007 +const SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V = 0x7 +const SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S = 12 +const SPI_MEM_SPI_SMEM_CS_HOLD_TIME = 0x0000001F +const SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V = 0x1F +const SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S = 7 +const SPI_MEM_SPI_SMEM_CS_SETUP_TIME = 0x0000001F +const SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V = 0x1F +const SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S = 2 +const SPI_MEM_SPI_SMEM_CS_HOLD_V = 0x1 +const SPI_MEM_SPI_SMEM_CS_HOLD_S = 1 +const SPI_MEM_SPI_SMEM_CS_SETUP_V = 0x1 +const SPI_MEM_SPI_SMEM_CS_SETUP_S = 0 +const SPI_MEM_SPI_FMEM_HYPERBUS_CA_V = 0x1 +const SPI_MEM_SPI_FMEM_HYPERBUS_CA_S = 30 +const SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V = 0x1 +const SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S = 29 +const SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V = 0x1 +const SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S = 28 +const SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V = 0x1 +const SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S = 27 +const SPI_MEM_SPI_FMEM_DQS_CA_IN_V = 0x1 +const SPI_MEM_SPI_FMEM_DQS_CA_IN_S = 26 +const SPI_MEM_SPI_FMEM_HYPERBUS_MODE_V = 0x1 +const SPI_MEM_SPI_FMEM_HYPERBUS_MODE_S = 25 +const SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V = 0x1 +const SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S = 24 +const SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V = 0x1 +const SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S = 22 +const SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V = 0x1 +const SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S = 21 +const SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD = 0x0000007F +const SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V = 0x7F +const SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S = 14 +const SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V = 0x1 +const SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S = 13 +const SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V = 0x1 +const SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S = 12 +const SPI_MEM_SPI_FMEM_OUTMINBYTELEN = 0x0000007F +const SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V = 0x7F +const SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S = 5 +const SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V = 0x1 +const SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S = 4 +const SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V = 0x1 +const SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S = 3 +const SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V = 0x1 +const SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S = 2 +const SPI_MEM_SPI_FMEM_VAR_DUMMY_V = 0x1 +const SPI_MEM_SPI_FMEM_VAR_DUMMY_S = 1 +const SPI_MEM_SPI_FMEM_DDR_EN_V = 0x1 +const SPI_MEM_SPI_FMEM_DDR_EN_S = 0 +const SPI_MEM_SPI_SMEM_HYPERBUS_CA_V = 0x1 +const SPI_MEM_SPI_SMEM_HYPERBUS_CA_S = 30 +const SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V = 0x1 +const SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S = 29 +const SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V = 0x1 +const SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S = 28 +const SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V = 0x1 +const SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S = 27 +const SPI_MEM_SPI_SMEM_DQS_CA_IN_V = 0x1 +const SPI_MEM_SPI_SMEM_DQS_CA_IN_S = 26 +const SPI_MEM_SPI_SMEM_HYPERBUS_MODE_V = 0x1 +const SPI_MEM_SPI_SMEM_HYPERBUS_MODE_S = 25 +const SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V = 0x1 +const SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S = 24 +const SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V = 0x1 +const SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S = 22 +const SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V = 0x1 +const SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S = 21 +const SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD = 0x0000007F +const SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V = 0x7F +const SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S = 14 +const SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V = 0x1 +const SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S = 13 +const SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V = 0x1 +const SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S = 12 +const SPI_MEM_SPI_SMEM_OUTMINBYTELEN = 0x0000007F +const SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V = 0x7F +const SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S = 5 +const SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V = 0x1 +const SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S = 4 +const SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V = 0x1 +const SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S = 3 +const SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V = 0x1 +const SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S = 2 +const SPI_MEM_SPI_SMEM_VAR_DUMMY_V = 0x1 +const SPI_MEM_SPI_SMEM_VAR_DUMMY_S = 1 +const SPI_MEM_SPI_SMEM_DDR_EN_V = 0x1 +const SPI_MEM_SPI_SMEM_DDR_EN_S = 0 +const SPI_MEM_CLK_EN_V = 0x1 +const SPI_MEM_CLK_EN_S = 0 +const SPI_MEM_CORE_CLK_SEL = 0x00000003 +const SPI_MEM_CORE_CLK_SEL_V = 0x3 +const SPI_MEM_CORE_CLK_SEL_S = 0 +const SPI_MEM_ECC_ERR_INT_ENA_V = 0x1 +const SPI_MEM_ECC_ERR_INT_ENA_S = 4 +const SPI_MEM_BROWN_OUT_INT_ENA_V = 0x1 +const SPI_MEM_BROWN_OUT_INT_ENA_S = 3 +const SPI_MEM_TOTAL_TRANS_END_INT_ENA_V = 0x1 +const SPI_MEM_TOTAL_TRANS_END_INT_ENA_S = 2 +const SPI_MEM_PES_END_INT_ENA_V = 0x1 +const SPI_MEM_PES_END_INT_ENA_S = 1 +const SPI_MEM_PER_END_INT_ENA_V = 0x1 +const SPI_MEM_PER_END_INT_ENA_S = 0 +const SPI_MEM_ECC_ERR_INT_CLR_V = 0x1 +const SPI_MEM_ECC_ERR_INT_CLR_S = 4 +const SPI_MEM_BROWN_OUT_INT_CLR_V = 0x1 +const SPI_MEM_BROWN_OUT_INT_CLR_S = 3 +const SPI_MEM_TOTAL_TRANS_END_INT_CLR_V = 0x1 +const SPI_MEM_TOTAL_TRANS_END_INT_CLR_S = 2 +const SPI_MEM_PES_END_INT_CLR_V = 0x1 +const SPI_MEM_PES_END_INT_CLR_S = 1 +const SPI_MEM_PER_END_INT_CLR_V = 0x1 +const SPI_MEM_PER_END_INT_CLR_S = 0 +const SPI_MEM_ECC_ERR_INT_RAW_V = 0x1 +const SPI_MEM_ECC_ERR_INT_RAW_S = 4 +const SPI_MEM_BROWN_OUT_INT_RAW_V = 0x1 +const SPI_MEM_BROWN_OUT_INT_RAW_S = 3 +const SPI_MEM_TOTAL_TRANS_END_INT_RAW_V = 0x1 +const SPI_MEM_TOTAL_TRANS_END_INT_RAW_S = 2 +const SPI_MEM_PES_END_INT_RAW_V = 0x1 +const SPI_MEM_PES_END_INT_RAW_S = 1 +const SPI_MEM_PER_END_INT_RAW_V = 0x1 +const SPI_MEM_PER_END_INT_RAW_S = 0 +const SPI_MEM_ECC_ERR_INT_ST_V = 0x1 +const SPI_MEM_ECC_ERR_INT_ST_S = 4 +const SPI_MEM_BROWN_OUT_INT_ST_V = 0x1 +const SPI_MEM_BROWN_OUT_INT_ST_S = 3 +const SPI_MEM_TOTAL_TRANS_END_INT_ST_V = 0x1 +const SPI_MEM_TOTAL_TRANS_END_INT_ST_S = 2 +const SPI_MEM_PES_END_INT_ST_V = 0x1 +const SPI_MEM_PES_END_INT_ST_S = 1 +const SPI_MEM_PER_END_INT_ST_V = 0x1 +const SPI_MEM_PER_END_INT_ST_S = 0 +const SPI_MEM_DATE = 0x007FFFFF +const SPI_MEM_DATE_V = 0x7FFFFF +const SPI_MEM_DATE_S = 5 +const SPI_MEM_SPICLK_PAD_DRV_CTL_EN_V = 0x1 +const SPI_MEM_SPICLK_PAD_DRV_CTL_EN_S = 4 +const SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV = 0x00000003 +const SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V = 0x3 +const SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S = 2 +const SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV = 0x00000003 +const SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V = 0x3 +const SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S = 0 diff --git a/esp32/spi_mem_struct.go b/esp32/spi_mem_struct.go new file mode 100644 index 00000000..3ab76eac --- /dev/null +++ b/esp32/spi_mem_struct.go @@ -0,0 +1,337 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type SpiMemDevS struct { + Cmd struct { + Val c.Uint32T + } + Addr c.Uint32T + Ctrl struct { + Val c.Uint32T + } + Ctrl1 struct { + Val c.Uint32T + } + Ctrl2 struct { + Val c.Uint32T + } + Clock struct { + Val c.Uint32T + } + User struct { + Val c.Uint32T + } + User1 struct { + Val c.Uint32T + } + User2 struct { + Val c.Uint32T + } + MosiDlen struct { + Val c.Uint32T + } + MisoDlen struct { + Val c.Uint32T + } + RdStatus struct { + Val c.Uint32T + } + ExtAddr c.Uint32T + Misc struct { + Val c.Uint32T + } + TxCrc c.Uint32T + CacheFctrl struct { + Val c.Uint32T + } + CacheSctrl struct { + Val c.Uint32T + } + SramCmd struct { + Val c.Uint32T + } + SramDrdCmd struct { + Val c.Uint32T + } + SramDwrCmd struct { + Val c.Uint32T + } + SramClk struct { + Val c.Uint32T + } + Fsm struct { + Val c.Uint32T + } + DataBuf [16]c.Uint32T + FlashWaitiCtrl struct { + Val c.Uint32T + } + FlashSusCmd struct { + Val c.Uint32T + } + FlashSusCtrl struct { + Val c.Uint32T + } + SusStatus struct { + Val c.Uint32T + } + TimingCali struct { + Val c.Uint32T + } + DinMode struct { + Val c.Uint32T + } + DinNum struct { + Val c.Uint32T + } + DoutMode struct { + Val c.Uint32T + } + ReservedB8 c.Uint32T + SpiSmemTimingCali struct { + Val c.Uint32T + } + SpiSmemDinMode struct { + Val c.Uint32T + } + SpiSmemDinNum struct { + Val c.Uint32T + } + SpiSmemDoutMode struct { + Val c.Uint32T + } + EccCtrl struct { + Val c.Uint32T + } + EccErrAddr c.Uint32T + EccErrBit struct { + Val c.Uint32T + } + ReservedD8 c.Uint32T + SpiSmemAc struct { + Val c.Uint32T + } + Ddr struct { + Val c.Uint32T + } + SpiSmemDdr struct { + Val c.Uint32T + } + ClockGate struct { + Val c.Uint32T + } + CoreClkSel struct { + Val c.Uint32T + } + IntEna struct { + Val c.Uint32T + } + IntClr struct { + Val c.Uint32T + } + IntRaw struct { + Val c.Uint32T + } + IntSt struct { + Val c.Uint32T + } + Reserved100 c.Uint32T + Reserved104 c.Uint32T + Reserved108 c.Uint32T + Reserved10c c.Uint32T + Reserved110 c.Uint32T + Reserved114 c.Uint32T + Reserved118 c.Uint32T + Reserved11c c.Uint32T + Reserved120 c.Uint32T + Reserved124 c.Uint32T + Reserved128 c.Uint32T + Reserved12c c.Uint32T + Reserved130 c.Uint32T + Reserved134 c.Uint32T + Reserved138 c.Uint32T + Reserved13c c.Uint32T + Reserved140 c.Uint32T + Reserved144 c.Uint32T + Reserved148 c.Uint32T + Reserved14c c.Uint32T + Reserved150 c.Uint32T + Reserved154 c.Uint32T + Reserved158 c.Uint32T + Reserved15c c.Uint32T + Reserved160 c.Uint32T + Reserved164 c.Uint32T + Reserved168 c.Uint32T + Reserved16c c.Uint32T + Reserved170 c.Uint32T + Reserved174 c.Uint32T + Reserved178 c.Uint32T + Reserved17c c.Uint32T + Reserved180 c.Uint32T + Reserved184 c.Uint32T + Reserved188 c.Uint32T + Reserved18c c.Uint32T + Reserved190 c.Uint32T + Reserved194 c.Uint32T + Reserved198 c.Uint32T + Reserved19c c.Uint32T + Reserved1a0 c.Uint32T + Reserved1a4 c.Uint32T + Reserved1a8 c.Uint32T + Reserved1ac c.Uint32T + Reserved1b0 c.Uint32T + Reserved1b4 c.Uint32T + Reserved1b8 c.Uint32T + Reserved1bc c.Uint32T + Reserved1c0 c.Uint32T + Reserved1c4 c.Uint32T + Reserved1c8 c.Uint32T + Reserved1cc c.Uint32T + Reserved1d0 c.Uint32T + Reserved1d4 c.Uint32T + Reserved1d8 c.Uint32T + Reserved1dc c.Uint32T + Reserved1e0 c.Uint32T + Reserved1e4 c.Uint32T + Reserved1e8 c.Uint32T + Reserved1ec c.Uint32T + Reserved1f0 c.Uint32T + Reserved1f4 c.Uint32T + Reserved1f8 c.Uint32T + Reserved1fc c.Uint32T + Reserved200 c.Uint32T + Reserved204 c.Uint32T + Reserved208 c.Uint32T + Reserved20c c.Uint32T + Reserved210 c.Uint32T + Reserved214 c.Uint32T + Reserved218 c.Uint32T + Reserved21c c.Uint32T + Reserved220 c.Uint32T + Reserved224 c.Uint32T + Reserved228 c.Uint32T + Reserved22c c.Uint32T + Reserved230 c.Uint32T + Reserved234 c.Uint32T + Reserved238 c.Uint32T + Reserved23c c.Uint32T + Reserved240 c.Uint32T + Reserved244 c.Uint32T + Reserved248 c.Uint32T + Reserved24c c.Uint32T + Reserved250 c.Uint32T + Reserved254 c.Uint32T + Reserved258 c.Uint32T + Reserved25c c.Uint32T + Reserved260 c.Uint32T + Reserved264 c.Uint32T + Reserved268 c.Uint32T + Reserved26c c.Uint32T + Reserved270 c.Uint32T + Reserved274 c.Uint32T + Reserved278 c.Uint32T + Reserved27c c.Uint32T + Reserved280 c.Uint32T + Reserved284 c.Uint32T + Reserved288 c.Uint32T + Reserved28c c.Uint32T + Reserved290 c.Uint32T + Reserved294 c.Uint32T + Reserved298 c.Uint32T + Reserved29c c.Uint32T + Reserved2a0 c.Uint32T + Reserved2a4 c.Uint32T + Reserved2a8 c.Uint32T + Reserved2ac c.Uint32T + Reserved2b0 c.Uint32T + Reserved2b4 c.Uint32T + Reserved2b8 c.Uint32T + Reserved2bc c.Uint32T + Reserved2c0 c.Uint32T + Reserved2c4 c.Uint32T + Reserved2c8 c.Uint32T + Reserved2cc c.Uint32T + Reserved2d0 c.Uint32T + Reserved2d4 c.Uint32T + Reserved2d8 c.Uint32T + Reserved2dc c.Uint32T + Reserved2e0 c.Uint32T + Reserved2e4 c.Uint32T + Reserved2e8 c.Uint32T + Reserved2ec c.Uint32T + Reserved2f0 c.Uint32T + Reserved2f4 c.Uint32T + Reserved2f8 c.Uint32T + Reserved2fc c.Uint32T + Reserved300 c.Uint32T + Reserved304 c.Uint32T + Reserved308 c.Uint32T + Reserved30c c.Uint32T + Reserved310 c.Uint32T + Reserved314 c.Uint32T + Reserved318 c.Uint32T + Reserved31c c.Uint32T + Reserved320 c.Uint32T + Reserved324 c.Uint32T + Reserved328 c.Uint32T + Reserved32c c.Uint32T + Reserved330 c.Uint32T + Reserved334 c.Uint32T + Reserved338 c.Uint32T + Reserved33c c.Uint32T + Reserved340 c.Uint32T + Reserved344 c.Uint32T + Reserved348 c.Uint32T + Reserved34c c.Uint32T + Reserved350 c.Uint32T + Reserved354 c.Uint32T + Reserved358 c.Uint32T + Reserved35c c.Uint32T + Reserved360 c.Uint32T + Reserved364 c.Uint32T + Reserved368 c.Uint32T + Reserved36c c.Uint32T + Reserved370 c.Uint32T + Reserved374 c.Uint32T + Reserved378 c.Uint32T + Reserved37c c.Uint32T + Reserved380 c.Uint32T + Reserved384 c.Uint32T + Reserved388 c.Uint32T + Reserved38c c.Uint32T + Reserved390 c.Uint32T + Reserved394 c.Uint32T + Reserved398 c.Uint32T + Reserved39c c.Uint32T + Reserved3a0 c.Uint32T + Reserved3a4 c.Uint32T + Reserved3a8 c.Uint32T + Reserved3ac c.Uint32T + Reserved3b0 c.Uint32T + Reserved3b4 c.Uint32T + Reserved3b8 c.Uint32T + Reserved3bc c.Uint32T + Reserved3c0 c.Uint32T + Reserved3c4 c.Uint32T + Reserved3c8 c.Uint32T + Reserved3cc c.Uint32T + Reserved3d0 c.Uint32T + Reserved3d4 c.Uint32T + Reserved3d8 c.Uint32T + Reserved3dc c.Uint32T + Reserved3e0 c.Uint32T + Reserved3e4 c.Uint32T + Reserved3e8 c.Uint32T + Reserved3ec c.Uint32T + Reserved3f0 c.Uint32T + Reserved3f4 c.Uint32T + Reserved3f8 c.Uint32T + Date struct { + Val c.Uint32T + } +} +type SpiMemDevT SpiMemDevS diff --git a/esp32/spi_periph.go b/esp32/spi_periph.go new file mode 100644 index 00000000..7e795512 --- /dev/null +++ b/esp32/spi_periph.go @@ -0,0 +1,44 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* +Stores a bunch of per-spi-peripheral data. +*/ +type SpiSignalConnT struct { + SpiclkOut c.Uint8T + SpiclkIn c.Uint8T + SpidOut c.Uint8T + SpiqOut c.Uint8T + SpiwpOut c.Uint8T + SpihdOut c.Uint8T + Spid4Out c.Uint8T + Spid5Out c.Uint8T + Spid6Out c.Uint8T + Spid7Out c.Uint8T + SpidIn c.Uint8T + SpiqIn c.Uint8T + SpiwpIn c.Uint8T + SpihdIn c.Uint8T + Spid4In c.Uint8T + Spid5In c.Uint8T + Spid6In c.Uint8T + Spid7In c.Uint8T + SpicsOut [6]c.Uint8T + SpicsIn c.Uint8T + SpidqsOut c.Uint8T + SpicdOut c.Uint8T + SpiclkIomuxPin c.Uint8T + SpidIomuxPin c.Uint8T + SpiqIomuxPin c.Uint8T + SpiwpIomuxPin c.Uint8T + SpihdIomuxPin c.Uint8T + Spics0IomuxPin c.Uint8T + Irq c.Uint8T + IrqDma c.Uint8T + Func c.Int + Hw *SpiDevT +} diff --git a/esp32/spi_pins.go b/esp32/spi_pins.go new file mode 100644 index 00000000..0c9e2dfa --- /dev/null +++ b/esp32/spi_pins.go @@ -0,0 +1,35 @@ +package freertos + +import _ "unsafe" + +const MSPI_FUNC_NUM = 0 +const MSPI_IOMUX_PIN_NUM_CS1 = 26 +const MSPI_IOMUX_PIN_NUM_HD = 27 +const MSPI_IOMUX_PIN_NUM_WP = 28 +const MSPI_IOMUX_PIN_NUM_CS0 = 29 +const MSPI_IOMUX_PIN_NUM_CLK = 30 +const MSPI_IOMUX_PIN_NUM_MISO = 31 +const MSPI_IOMUX_PIN_NUM_MOSI = 32 +const MSPI_IOMUX_PIN_NUM_D4 = 33 +const MSPI_IOMUX_PIN_NUM_D5 = 34 +const MSPI_IOMUX_PIN_NUM_D6 = 35 +const MSPI_IOMUX_PIN_NUM_D7 = 36 +const MSPI_IOMUX_PIN_NUM_DQS = 37 +const SPI2_FUNC_NUM = 4 +const SPI2_IOMUX_PIN_NUM_HD = 9 +const SPI2_IOMUX_PIN_NUM_CS = 10 +const SPI2_IOMUX_PIN_NUM_MOSI = 11 +const SPI2_IOMUX_PIN_NUM_CLK = 12 +const SPI2_IOMUX_PIN_NUM_MISO = 13 +const SPI2_IOMUX_PIN_NUM_WP = 14 +const SPI2_FUNC_NUM_OCT = 2 +const SPI2_IOMUX_PIN_NUM_HD_OCT = 33 +const SPI2_IOMUX_PIN_NUM_CS_OCT = 34 +const SPI2_IOMUX_PIN_NUM_MOSI_OCT = 35 +const SPI2_IOMUX_PIN_NUM_CLK_OCT = 36 +const SPI2_IOMUX_PIN_NUM_MISO_OCT = 37 +const SPI2_IOMUX_PIN_NUM_WP_OCT = 38 +const SPI2_IOMUX_PIN_NUM_IO4_OCT = 10 +const SPI2_IOMUX_PIN_NUM_IO5_OCT = 11 +const SPI2_IOMUX_PIN_NUM_IO6_OCT = 12 +const SPI2_IOMUX_PIN_NUM_IO7_OCT = 13 diff --git a/esp32/spi_reg.go b/esp32/spi_reg.go new file mode 100644 index 00000000..61e7ed84 --- /dev/null +++ b/esp32/spi_reg.go @@ -0,0 +1,554 @@ +package freertos + +import _ "unsafe" + +const SPI_USR_V = 0x1 +const SPI_USR_S = 24 +const SPI_UPDATE_V = 0x1 +const SPI_UPDATE_S = 23 +const SPI_CONF_BITLEN = 0x0003FFFF +const SPI_CONF_BITLEN_V = 0x3FFFF +const SPI_CONF_BITLEN_S = 0 +const SPI_USR_ADDR_VALUE = 0xFFFFFFFF +const SPI_USR_ADDR_VALUE_V = 0xFFFFFFFF +const SPI_USR_ADDR_VALUE_S = 0 +const SPI_WR_BIT_ORDER = 0x00000003 +const SPI_WR_BIT_ORDER_V = 0x3 +const SPI_WR_BIT_ORDER_S = 25 +const SPI_RD_BIT_ORDER = 0x00000003 +const SPI_RD_BIT_ORDER_V = 0x3 +const SPI_RD_BIT_ORDER_S = 23 +const SPI_WP_POL_V = 0x1 +const SPI_WP_POL_S = 21 +const SPI_HOLD_POL_V = 0x1 +const SPI_HOLD_POL_S = 20 +const SPI_D_POL_V = 0x1 +const SPI_D_POL_S = 19 +const SPI_Q_POL_V = 0x1 +const SPI_Q_POL_S = 18 +const SPI_FREAD_OCT_V = 0x1 +const SPI_FREAD_OCT_S = 16 +const SPI_FREAD_QUAD_V = 0x1 +const SPI_FREAD_QUAD_S = 15 +const SPI_FREAD_DUAL_V = 0x1 +const SPI_FREAD_DUAL_S = 14 +const SPI_FCMD_OCT_V = 0x1 +const SPI_FCMD_OCT_S = 10 +const SPI_FCMD_QUAD_V = 0x1 +const SPI_FCMD_QUAD_S = 9 +const SPI_FCMD_DUAL_V = 0x1 +const SPI_FCMD_DUAL_S = 8 +const SPI_FADDR_OCT_V = 0x1 +const SPI_FADDR_OCT_S = 7 +const SPI_FADDR_QUAD_V = 0x1 +const SPI_FADDR_QUAD_S = 6 +const SPI_FADDR_DUAL_V = 0x1 +const SPI_FADDR_DUAL_S = 5 +const SPI_DUMMY_OUT_V = 0x1 +const SPI_DUMMY_OUT_S = 3 +const SPI_CLK_EQU_SYSCLK_V = 0x1 +const SPI_CLK_EQU_SYSCLK_S = 31 +const SPI_CLKDIV_PRE = 0x0000000F +const SPI_CLKDIV_PRE_V = 0xF +const SPI_CLKDIV_PRE_S = 18 +const SPI_CLKCNT_N = 0x0000003F +const SPI_CLKCNT_N_V = 0x3F +const SPI_CLKCNT_N_S = 12 +const SPI_CLKCNT_H = 0x0000003F +const SPI_CLKCNT_H_V = 0x3F +const SPI_CLKCNT_H_S = 6 +const SPI_CLKCNT_L = 0x0000003F +const SPI_CLKCNT_L_V = 0x3F +const SPI_CLKCNT_L_S = 0 +const SPI_USR_COMMAND_V = 0x1 +const SPI_USR_COMMAND_S = 31 +const SPI_USR_ADDR_V = 0x1 +const SPI_USR_ADDR_S = 30 +const SPI_USR_DUMMY_V = 0x1 +const SPI_USR_DUMMY_S = 29 +const SPI_USR_MISO_V = 0x1 +const SPI_USR_MISO_S = 28 +const SPI_USR_MOSI_V = 0x1 +const SPI_USR_MOSI_S = 27 +const SPI_USR_DUMMY_IDLE_V = 0x1 +const SPI_USR_DUMMY_IDLE_S = 26 +const SPI_USR_MOSI_HIGHPART_V = 0x1 +const SPI_USR_MOSI_HIGHPART_S = 25 +const SPI_USR_MISO_HIGHPART_V = 0x1 +const SPI_USR_MISO_HIGHPART_S = 24 +const SPI_SIO_V = 0x1 +const SPI_SIO_S = 17 +const SPI_USR_CONF_NXT_V = 0x1 +const SPI_USR_CONF_NXT_S = 15 +const SPI_FWRITE_OCT_V = 0x1 +const SPI_FWRITE_OCT_S = 14 +const SPI_FWRITE_QUAD_V = 0x1 +const SPI_FWRITE_QUAD_S = 13 +const SPI_FWRITE_DUAL_V = 0x1 +const SPI_FWRITE_DUAL_S = 12 +const SPI_CK_OUT_EDGE_V = 0x1 +const SPI_CK_OUT_EDGE_S = 9 +const SPI_RSCK_I_EDGE_V = 0x1 +const SPI_RSCK_I_EDGE_S = 8 +const SPI_CS_SETUP_V = 0x1 +const SPI_CS_SETUP_S = 7 +const SPI_CS_HOLD_V = 0x1 +const SPI_CS_HOLD_S = 6 +const SPI_TSCK_I_EDGE_V = 0x1 +const SPI_TSCK_I_EDGE_S = 5 +const SPI_OPI_MODE_V = 0x1 +const SPI_OPI_MODE_S = 4 +const SPI_QPI_MODE_V = 0x1 +const SPI_QPI_MODE_S = 3 +const SPI_DOUTDIN_V = 0x1 +const SPI_DOUTDIN_S = 0 +const SPI_USR_ADDR_BITLEN = 0x0000001F +const SPI_USR_ADDR_BITLEN_V = 0x1F +const SPI_USR_ADDR_BITLEN_S = 27 +const SPI_CS_HOLD_TIME = 0x0000001F +const SPI_CS_HOLD_TIME_V = 0x1F +const SPI_CS_HOLD_TIME_S = 22 +const SPI_CS_SETUP_TIME = 0x0000001F +const SPI_CS_SETUP_TIME_V = 0x1F +const SPI_CS_SETUP_TIME_S = 17 +const SPI_MST_WFULL_ERR_END_EN_V = 0x1 +const SPI_MST_WFULL_ERR_END_EN_S = 16 +const SPI_USR_DUMMY_CYCLELEN = 0x000000FF +const SPI_USR_DUMMY_CYCLELEN_V = 0xFF +const SPI_USR_DUMMY_CYCLELEN_S = 0 +const SPI_USR_COMMAND_BITLEN = 0x0000000F +const SPI_USR_COMMAND_BITLEN_V = 0xF +const SPI_USR_COMMAND_BITLEN_S = 28 +const SPI_MST_REMPTY_ERR_END_EN_V = 0x1 +const SPI_MST_REMPTY_ERR_END_EN_S = 27 +const SPI_USR_COMMAND_VALUE = 0x0000FFFF +const SPI_USR_COMMAND_VALUE_V = 0xFFFF +const SPI_USR_COMMAND_VALUE_S = 0 +const SPI_MS_DATA_BITLEN = 0x0003FFFF +const SPI_MS_DATA_BITLEN_V = 0x3FFFF +const SPI_MS_DATA_BITLEN_S = 0 +const SPI_QUAD_DIN_PIN_SWAP_V = 0x1 +const SPI_QUAD_DIN_PIN_SWAP_S = 31 +const SPI_CS_KEEP_ACTIVE_V = 0x1 +const SPI_CS_KEEP_ACTIVE_S = 30 +const SPI_CK_IDLE_EDGE_V = 0x1 +const SPI_CK_IDLE_EDGE_S = 29 +const SPI_DQS_IDLE_EDGE_V = 0x1 +const SPI_DQS_IDLE_EDGE_S = 24 +const SPI_SLAVE_CS_POL_V = 0x1 +const SPI_SLAVE_CS_POL_S = 23 +const SPI_CMD_DTR_EN_V = 0x1 +const SPI_CMD_DTR_EN_S = 19 +const SPI_ADDR_DTR_EN_V = 0x1 +const SPI_ADDR_DTR_EN_S = 18 +const SPI_DATA_DTR_EN_V = 0x1 +const SPI_DATA_DTR_EN_S = 17 +const SPI_CLK_DATA_DTR_EN_V = 0x1 +const SPI_CLK_DATA_DTR_EN_S = 16 +const SPI_MASTER_CS_POL = 0x0000003F +const SPI_MASTER_CS_POL_V = 0x3F +const SPI_MASTER_CS_POL_S = 7 +const SPI_CK_DIS_V = 0x1 +const SPI_CK_DIS_S = 6 +const SPI_CS5_DIS_V = 0x1 +const SPI_CS5_DIS_S = 5 +const SPI_CS4_DIS_V = 0x1 +const SPI_CS4_DIS_S = 4 +const SPI_CS3_DIS_V = 0x1 +const SPI_CS3_DIS_S = 3 +const SPI_CS2_DIS_V = 0x1 +const SPI_CS2_DIS_S = 2 +const SPI_CS1_DIS_V = 0x1 +const SPI_CS1_DIS_S = 1 +const SPI_CS0_DIS_V = 0x1 +const SPI_CS0_DIS_S = 0 +const SPI_TIMING_HCLK_ACTIVE_V = 0x1 +const SPI_TIMING_HCLK_ACTIVE_S = 16 +const SPI_DIN7_MODE = 0x00000003 +const SPI_DIN7_MODE_V = 0x3 +const SPI_DIN7_MODE_S = 14 +const SPI_DIN6_MODE = 0x00000003 +const SPI_DIN6_MODE_V = 0x3 +const SPI_DIN6_MODE_S = 12 +const SPI_DIN5_MODE = 0x00000003 +const SPI_DIN5_MODE_V = 0x3 +const SPI_DIN5_MODE_S = 10 +const SPI_DIN4_MODE = 0x00000003 +const SPI_DIN4_MODE_V = 0x3 +const SPI_DIN4_MODE_S = 8 +const SPI_DIN3_MODE = 0x00000003 +const SPI_DIN3_MODE_V = 0x3 +const SPI_DIN3_MODE_S = 6 +const SPI_DIN2_MODE = 0x00000003 +const SPI_DIN2_MODE_V = 0x3 +const SPI_DIN2_MODE_S = 4 +const SPI_DIN1_MODE = 0x00000003 +const SPI_DIN1_MODE_V = 0x3 +const SPI_DIN1_MODE_S = 2 +const SPI_DIN0_MODE = 0x00000003 +const SPI_DIN0_MODE_V = 0x3 +const SPI_DIN0_MODE_S = 0 +const SPI_DIN7_NUM = 0x00000003 +const SPI_DIN7_NUM_V = 0x3 +const SPI_DIN7_NUM_S = 14 +const SPI_DIN6_NUM = 0x00000003 +const SPI_DIN6_NUM_V = 0x3 +const SPI_DIN6_NUM_S = 12 +const SPI_DIN5_NUM = 0x00000003 +const SPI_DIN5_NUM_V = 0x3 +const SPI_DIN5_NUM_S = 10 +const SPI_DIN4_NUM = 0x00000003 +const SPI_DIN4_NUM_V = 0x3 +const SPI_DIN4_NUM_S = 8 +const SPI_DIN3_NUM = 0x00000003 +const SPI_DIN3_NUM_V = 0x3 +const SPI_DIN3_NUM_S = 6 +const SPI_DIN2_NUM = 0x00000003 +const SPI_DIN2_NUM_V = 0x3 +const SPI_DIN2_NUM_S = 4 +const SPI_DIN1_NUM = 0x00000003 +const SPI_DIN1_NUM_V = 0x3 +const SPI_DIN1_NUM_S = 2 +const SPI_DIN0_NUM = 0x00000003 +const SPI_DIN0_NUM_V = 0x3 +const SPI_DIN0_NUM_S = 0 +const SPI_D_DQS_MODE_V = 0x1 +const SPI_D_DQS_MODE_S = 8 +const SPI_DOUT7_MODE_V = 0x1 +const SPI_DOUT7_MODE_S = 7 +const SPI_DOUT6_MODE_V = 0x1 +const SPI_DOUT6_MODE_S = 6 +const SPI_DOUT5_MODE_V = 0x1 +const SPI_DOUT5_MODE_S = 5 +const SPI_DOUT4_MODE_V = 0x1 +const SPI_DOUT4_MODE_S = 4 +const SPI_DOUT3_MODE_V = 0x1 +const SPI_DOUT3_MODE_S = 3 +const SPI_DOUT2_MODE_V = 0x1 +const SPI_DOUT2_MODE_S = 2 +const SPI_DOUT1_MODE_V = 0x1 +const SPI_DOUT1_MODE_S = 1 +const SPI_DOUT0_MODE_V = 0x1 +const SPI_DOUT0_MODE_S = 0 +const SPI_DMA_AFIFO_RST_V = 0x1 +const SPI_DMA_AFIFO_RST_S = 31 +const SPI_BUF_AFIFO_RST_V = 0x1 +const SPI_BUF_AFIFO_RST_S = 30 +const SPI_RX_AFIFO_RST_V = 0x1 +const SPI_RX_AFIFO_RST_S = 29 +const SPI_DMA_TX_ENA_V = 0x1 +const SPI_DMA_TX_ENA_S = 28 +const SPI_DMA_RX_ENA_V = 0x1 +const SPI_DMA_RX_ENA_S = 27 +const SPI_RX_EOF_EN_V = 0x1 +const SPI_RX_EOF_EN_S = 21 +const SPI_SLV_TX_SEG_TRANS_CLR_EN_V = 0x1 +const SPI_SLV_TX_SEG_TRANS_CLR_EN_S = 20 +const SPI_SLV_RX_SEG_TRANS_CLR_EN_V = 0x1 +const SPI_SLV_RX_SEG_TRANS_CLR_EN_S = 19 +const SPI_DMA_SLV_SEG_TRANS_EN_V = 0x1 +const SPI_DMA_SLV_SEG_TRANS_EN_S = 18 +const SPI_DMA_INFIFO_FULL_V = 0x1 +const SPI_DMA_INFIFO_FULL_S = 1 +const SPI_DMA_OUTFIFO_EMPTY_V = 0x1 +const SPI_DMA_OUTFIFO_EMPTY_S = 0 +const SPI_APP1_INT_ENA_V = 0x1 +const SPI_APP1_INT_ENA_S = 20 +const SPI_APP2_INT_ENA_V = 0x1 +const SPI_APP2_INT_ENA_S = 19 +const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V = 0x1 +const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S = 18 +const SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V = 0x1 +const SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S = 17 +const SPI_SLV_CMD_ERR_INT_ENA_V = 0x1 +const SPI_SLV_CMD_ERR_INT_ENA_S = 16 +const SPI_SLV_BUF_ADDR_ERR_INT_ENA_V = 0x1 +const SPI_SLV_BUF_ADDR_ERR_INT_ENA_S = 15 +const SPI_SEG_MAGIC_ERR_INT_ENA_V = 0x1 +const SPI_SEG_MAGIC_ERR_INT_ENA_S = 14 +const SPI_DMA_SEG_TRANS_DONE_INT_ENA_V = 0x1 +const SPI_DMA_SEG_TRANS_DONE_INT_ENA_S = 13 +const SPI_TRANS_DONE_INT_ENA_V = 0x1 +const SPI_TRANS_DONE_INT_ENA_S = 12 +const SPI_SLV_WR_BUF_DONE_INT_ENA_V = 0x1 +const SPI_SLV_WR_BUF_DONE_INT_ENA_S = 11 +const SPI_SLV_RD_BUF_DONE_INT_ENA_V = 0x1 +const SPI_SLV_RD_BUF_DONE_INT_ENA_S = 10 +const SPI_SLV_WR_DMA_DONE_INT_ENA_V = 0x1 +const SPI_SLV_WR_DMA_DONE_INT_ENA_S = 9 +const SPI_SLV_RD_DMA_DONE_INT_ENA_V = 0x1 +const SPI_SLV_RD_DMA_DONE_INT_ENA_S = 8 +const SPI_SLV_CMDA_INT_ENA_V = 0x1 +const SPI_SLV_CMDA_INT_ENA_S = 7 +const SPI_SLV_CMD9_INT_ENA_V = 0x1 +const SPI_SLV_CMD9_INT_ENA_S = 6 +const SPI_SLV_CMD8_INT_ENA_V = 0x1 +const SPI_SLV_CMD8_INT_ENA_S = 5 +const SPI_SLV_CMD7_INT_ENA_V = 0x1 +const SPI_SLV_CMD7_INT_ENA_S = 4 +const SPI_SLV_EN_QPI_INT_ENA_V = 0x1 +const SPI_SLV_EN_QPI_INT_ENA_S = 3 +const SPI_SLV_EX_QPI_INT_ENA_V = 0x1 +const SPI_SLV_EX_QPI_INT_ENA_S = 2 +const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V = 0x1 +const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S = 1 +const SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V = 0x1 +const SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S = 0 +const SPI_APP1_INT_CLR_V = 0x1 +const SPI_APP1_INT_CLR_S = 20 +const SPI_APP2_INT_CLR_V = 0x1 +const SPI_APP2_INT_CLR_S = 19 +const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V = 0x1 +const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S = 18 +const SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V = 0x1 +const SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S = 17 +const SPI_SLV_CMD_ERR_INT_CLR_V = 0x1 +const SPI_SLV_CMD_ERR_INT_CLR_S = 16 +const SPI_SLV_BUF_ADDR_ERR_INT_CLR_V = 0x1 +const SPI_SLV_BUF_ADDR_ERR_INT_CLR_S = 15 +const SPI_SEG_MAGIC_ERR_INT_CLR_V = 0x1 +const SPI_SEG_MAGIC_ERR_INT_CLR_S = 14 +const SPI_DMA_SEG_TRANS_DONE_INT_CLR_V = 0x1 +const SPI_DMA_SEG_TRANS_DONE_INT_CLR_S = 13 +const SPI_TRANS_DONE_INT_CLR_V = 0x1 +const SPI_TRANS_DONE_INT_CLR_S = 12 +const SPI_SLV_WR_BUF_DONE_INT_CLR_V = 0x1 +const SPI_SLV_WR_BUF_DONE_INT_CLR_S = 11 +const SPI_SLV_RD_BUF_DONE_INT_CLR_V = 0x1 +const SPI_SLV_RD_BUF_DONE_INT_CLR_S = 10 +const SPI_SLV_WR_DMA_DONE_INT_CLR_V = 0x1 +const SPI_SLV_WR_DMA_DONE_INT_CLR_S = 9 +const SPI_SLV_RD_DMA_DONE_INT_CLR_V = 0x1 +const SPI_SLV_RD_DMA_DONE_INT_CLR_S = 8 +const SPI_SLV_CMDA_INT_CLR_V = 0x1 +const SPI_SLV_CMDA_INT_CLR_S = 7 +const SPI_SLV_CMD9_INT_CLR_V = 0x1 +const SPI_SLV_CMD9_INT_CLR_S = 6 +const SPI_SLV_CMD8_INT_CLR_V = 0x1 +const SPI_SLV_CMD8_INT_CLR_S = 5 +const SPI_SLV_CMD7_INT_CLR_V = 0x1 +const SPI_SLV_CMD7_INT_CLR_S = 4 +const SPI_SLV_EN_QPI_INT_CLR_V = 0x1 +const SPI_SLV_EN_QPI_INT_CLR_S = 3 +const SPI_SLV_EX_QPI_INT_CLR_V = 0x1 +const SPI_SLV_EX_QPI_INT_CLR_S = 2 +const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V = 0x1 +const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S = 1 +const SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V = 0x1 +const SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S = 0 +const SPI_APP1_INT_RAW_V = 0x1 +const SPI_APP1_INT_RAW_S = 20 +const SPI_APP2_INT_RAW_V = 0x1 +const SPI_APP2_INT_RAW_S = 19 +const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V = 0x1 +const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S = 18 +const SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V = 0x1 +const SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S = 17 +const SPI_SLV_CMD_ERR_INT_RAW_V = 0x1 +const SPI_SLV_CMD_ERR_INT_RAW_S = 16 +const SPI_SLV_BUF_ADDR_ERR_INT_RAW_V = 0x1 +const SPI_SLV_BUF_ADDR_ERR_INT_RAW_S = 15 +const SPI_SEG_MAGIC_ERR_INT_RAW_V = 0x1 +const SPI_SEG_MAGIC_ERR_INT_RAW_S = 14 +const SPI_DMA_SEG_TRANS_DONE_INT_RAW_V = 0x1 +const SPI_DMA_SEG_TRANS_DONE_INT_RAW_S = 13 +const SPI_TRANS_DONE_INT_RAW_V = 0x1 +const SPI_TRANS_DONE_INT_RAW_S = 12 +const SPI_SLV_WR_BUF_DONE_INT_RAW_V = 0x1 +const SPI_SLV_WR_BUF_DONE_INT_RAW_S = 11 +const SPI_SLV_RD_BUF_DONE_INT_RAW_V = 0x1 +const SPI_SLV_RD_BUF_DONE_INT_RAW_S = 10 +const SPI_SLV_WR_DMA_DONE_INT_RAW_V = 0x1 +const SPI_SLV_WR_DMA_DONE_INT_RAW_S = 9 +const SPI_SLV_RD_DMA_DONE_INT_RAW_V = 0x1 +const SPI_SLV_RD_DMA_DONE_INT_RAW_S = 8 +const SPI_SLV_CMDA_INT_RAW_V = 0x1 +const SPI_SLV_CMDA_INT_RAW_S = 7 +const SPI_SLV_CMD9_INT_RAW_V = 0x1 +const SPI_SLV_CMD9_INT_RAW_S = 6 +const SPI_SLV_CMD8_INT_RAW_V = 0x1 +const SPI_SLV_CMD8_INT_RAW_S = 5 +const SPI_SLV_CMD7_INT_RAW_V = 0x1 +const SPI_SLV_CMD7_INT_RAW_S = 4 +const SPI_SLV_EN_QPI_INT_RAW_V = 0x1 +const SPI_SLV_EN_QPI_INT_RAW_S = 3 +const SPI_SLV_EX_QPI_INT_RAW_V = 0x1 +const SPI_SLV_EX_QPI_INT_RAW_S = 2 +const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V = 0x1 +const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S = 1 +const SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V = 0x1 +const SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S = 0 +const SPI_APP1_INT_ST_V = 0x1 +const SPI_APP1_INT_ST_S = 20 +const SPI_APP2_INT_ST_V = 0x1 +const SPI_APP2_INT_ST_S = 19 +const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V = 0x1 +const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S = 18 +const SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V = 0x1 +const SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S = 17 +const SPI_SLV_CMD_ERR_INT_ST_V = 0x1 +const SPI_SLV_CMD_ERR_INT_ST_S = 16 +const SPI_SLV_BUF_ADDR_ERR_INT_ST_V = 0x1 +const SPI_SLV_BUF_ADDR_ERR_INT_ST_S = 15 +const SPI_SEG_MAGIC_ERR_INT_ST_V = 0x1 +const SPI_SEG_MAGIC_ERR_INT_ST_S = 14 +const SPI_DMA_SEG_TRANS_DONE_INT_ST_V = 0x1 +const SPI_DMA_SEG_TRANS_DONE_INT_ST_S = 13 +const SPI_TRANS_DONE_INT_ST_V = 0x1 +const SPI_TRANS_DONE_INT_ST_S = 12 +const SPI_SLV_WR_BUF_DONE_INT_ST_V = 0x1 +const SPI_SLV_WR_BUF_DONE_INT_ST_S = 11 +const SPI_SLV_RD_BUF_DONE_INT_ST_V = 0x1 +const SPI_SLV_RD_BUF_DONE_INT_ST_S = 10 +const SPI_SLV_WR_DMA_DONE_INT_ST_V = 0x1 +const SPI_SLV_WR_DMA_DONE_INT_ST_S = 9 +const SPI_SLV_RD_DMA_DONE_INT_ST_V = 0x1 +const SPI_SLV_RD_DMA_DONE_INT_ST_S = 8 +const SPI_SLV_CMDA_INT_ST_V = 0x1 +const SPI_SLV_CMDA_INT_ST_S = 7 +const SPI_SLV_CMD9_INT_ST_V = 0x1 +const SPI_SLV_CMD9_INT_ST_S = 6 +const SPI_SLV_CMD8_INT_ST_V = 0x1 +const SPI_SLV_CMD8_INT_ST_S = 5 +const SPI_SLV_CMD7_INT_ST_V = 0x1 +const SPI_SLV_CMD7_INT_ST_S = 4 +const SPI_SLV_EN_QPI_INT_ST_V = 0x1 +const SPI_SLV_EN_QPI_INT_ST_S = 3 +const SPI_SLV_EX_QPI_INT_ST_V = 0x1 +const SPI_SLV_EX_QPI_INT_ST_S = 2 +const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V = 0x1 +const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S = 1 +const SPI_DMA_INFIFO_FULL_ERR_INT_ST_V = 0x1 +const SPI_DMA_INFIFO_FULL_ERR_INT_ST_S = 0 +const SPI_APP1_INT_SET_V = 0x1 +const SPI_APP1_INT_SET_S = 20 +const SPI_APP2_INT_SET_V = 0x1 +const SPI_APP2_INT_SET_S = 19 +const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V = 0x1 +const SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S = 18 +const SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V = 0x1 +const SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S = 17 +const SPI_SLV_CMD_ERR_INT_SET_V = 0x1 +const SPI_SLV_CMD_ERR_INT_SET_S = 16 +const SPI_SLV_BUF_ADDR_ERR_INT_SET_V = 0x1 +const SPI_SLV_BUF_ADDR_ERR_INT_SET_S = 15 +const SPI_SEG_MAGIC_ERR_INT_SET_V = 0x1 +const SPI_SEG_MAGIC_ERR_INT_SET_S = 14 +const SPI_DMA_SEG_TRANS_DONE_INT_SET_V = 0x1 +const SPI_DMA_SEG_TRANS_DONE_INT_SET_S = 13 +const SPI_TRANS_DONE_INT_SET_V = 0x1 +const SPI_TRANS_DONE_INT_SET_S = 12 +const SPI_SLV_WR_BUF_DONE_INT_SET_V = 0x1 +const SPI_SLV_WR_BUF_DONE_INT_SET_S = 11 +const SPI_SLV_RD_BUF_DONE_INT_SET_V = 0x1 +const SPI_SLV_RD_BUF_DONE_INT_SET_S = 10 +const SPI_SLV_WR_DMA_DONE_INT_SET_V = 0x1 +const SPI_SLV_WR_DMA_DONE_INT_SET_S = 9 +const SPI_SLV_RD_DMA_DONE_INT_SET_V = 0x1 +const SPI_SLV_RD_DMA_DONE_INT_SET_S = 8 +const SPI_SLV_CMDA_INT_SET_V = 0x1 +const SPI_SLV_CMDA_INT_SET_S = 7 +const SPI_SLV_CMD9_INT_SET_V = 0x1 +const SPI_SLV_CMD9_INT_SET_S = 6 +const SPI_SLV_CMD8_INT_SET_V = 0x1 +const SPI_SLV_CMD8_INT_SET_S = 5 +const SPI_SLV_CMD7_INT_SET_V = 0x1 +const SPI_SLV_CMD7_INT_SET_S = 4 +const SPI_SLV_EN_QPI_INT_SET_V = 0x1 +const SPI_SLV_EN_QPI_INT_SET_S = 3 +const SPI_SLV_EX_QPI_INT_SET_V = 0x1 +const SPI_SLV_EX_QPI_INT_SET_S = 2 +const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V = 0x1 +const SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S = 1 +const SPI_DMA_INFIFO_FULL_ERR_INT_SET_V = 0x1 +const SPI_DMA_INFIFO_FULL_ERR_INT_SET_S = 0 +const SPI_BUF0 = 0xFFFFFFFF +const SPI_BUF0_V = 0xFFFFFFFF +const SPI_BUF0_S = 0 +const SPI_BUF1 = 0xFFFFFFFF +const SPI_BUF1_V = 0xFFFFFFFF +const SPI_BUF1_S = 0 +const SPI_BUF2 = 0xFFFFFFFF +const SPI_BUF2_V = 0xFFFFFFFF +const SPI_BUF2_S = 0 +const SPI_BUF3 = 0xFFFFFFFF +const SPI_BUF3_V = 0xFFFFFFFF +const SPI_BUF3_S = 0 +const SPI_BUF4 = 0xFFFFFFFF +const SPI_BUF4_V = 0xFFFFFFFF +const SPI_BUF4_S = 0 +const SPI_BUF5 = 0xFFFFFFFF +const SPI_BUF5_V = 0xFFFFFFFF +const SPI_BUF5_S = 0 +const SPI_BUF6 = 0xFFFFFFFF +const SPI_BUF6_V = 0xFFFFFFFF +const SPI_BUF6_S = 0 +const SPI_BUF7 = 0xFFFFFFFF +const SPI_BUF7_V = 0xFFFFFFFF +const SPI_BUF7_S = 0 +const SPI_BUF8 = 0xFFFFFFFF +const SPI_BUF8_V = 0xFFFFFFFF +const SPI_BUF8_S = 0 +const SPI_BUF9 = 0xFFFFFFFF +const SPI_BUF9_V = 0xFFFFFFFF +const SPI_BUF9_S = 0 +const SPI_BUF10 = 0xFFFFFFFF +const SPI_BUF10_V = 0xFFFFFFFF +const SPI_BUF10_S = 0 +const SPI_BUF11 = 0xFFFFFFFF +const SPI_BUF11_V = 0xFFFFFFFF +const SPI_BUF11_S = 0 +const SPI_BUF12 = 0xFFFFFFFF +const SPI_BUF12_V = 0xFFFFFFFF +const SPI_BUF12_S = 0 +const SPI_BUF13 = 0xFFFFFFFF +const SPI_BUF13_V = 0xFFFFFFFF +const SPI_BUF13_S = 0 +const SPI_BUF14 = 0xFFFFFFFF +const SPI_BUF14_V = 0xFFFFFFFF +const SPI_BUF14_S = 0 +const SPI_BUF15 = 0xFFFFFFFF +const SPI_BUF15_V = 0xFFFFFFFF +const SPI_BUF15_S = 0 +const SPI_USR_CONF_V = 0x1 +const SPI_USR_CONF_S = 28 +const SPI_SOFT_RESET_V = 0x1 +const SPI_SOFT_RESET_S = 27 +const SPI_SLAVE_MODE_V = 0x1 +const SPI_SLAVE_MODE_S = 26 +const SPI_DMA_SEG_MAGIC_VALUE = 0x0000000F +const SPI_DMA_SEG_MAGIC_VALUE_V = 0xF +const SPI_DMA_SEG_MAGIC_VALUE_S = 22 +const SPI_SLV_WRBUF_BITLEN_EN_V = 0x1 +const SPI_SLV_WRBUF_BITLEN_EN_S = 11 +const SPI_SLV_RDBUF_BITLEN_EN_V = 0x1 +const SPI_SLV_RDBUF_BITLEN_EN_S = 10 +const SPI_SLV_WRDMA_BITLEN_EN_V = 0x1 +const SPI_SLV_WRDMA_BITLEN_EN_S = 9 +const SPI_SLV_RDDMA_BITLEN_EN_V = 0x1 +const SPI_SLV_RDDMA_BITLEN_EN_S = 8 +const SPI_RSCK_DATA_OUT_V = 0x1 +const SPI_RSCK_DATA_OUT_S = 3 +const SPI_CLK_MODE_13_V = 0x1 +const SPI_CLK_MODE_13_S = 2 +const SPI_CLK_MODE = 0x00000003 +const SPI_CLK_MODE_V = 0x3 +const SPI_CLK_MODE_S = 0 +const SPI_SLV_LAST_ADDR = 0x0000003F +const SPI_SLV_LAST_ADDR_V = 0x3F +const SPI_SLV_LAST_ADDR_S = 26 +const SPI_SLV_LAST_COMMAND = 0x000000FF +const SPI_SLV_LAST_COMMAND_V = 0xFF +const SPI_SLV_LAST_COMMAND_S = 18 +const SPI_SLV_DATA_BITLEN = 0x0003FFFF +const SPI_SLV_DATA_BITLEN_V = 0x3FFFF +const SPI_SLV_DATA_BITLEN_S = 0 +const SPI_MST_CLK_SEL_V = 0x1 +const SPI_MST_CLK_SEL_S = 2 +const SPI_MST_CLK_ACTIVE_V = 0x1 +const SPI_MST_CLK_ACTIVE_S = 1 +const SPI_CLK_EN_V = 0x1 +const SPI_CLK_EN_S = 0 +const SPI_DATE = 0x0FFFFFFF +const SPI_DATE_V = 0xFFFFFFF +const SPI_DATE_S = 0 diff --git a/esp32/spi_share_hw_ctrl.go b/esp32/spi_share_hw_ctrl.go new file mode 100644 index 00000000..f9f53c2e --- /dev/null +++ b/esp32/spi_share_hw_ctrl.go @@ -0,0 +1,370 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const BUS_LOCK_DEBUG = 0 +const DEV_NUM_MAX = 6 + +type SpiBusLockT struct { + Unused [8]uint8 +} + +type SpiBusLockDevT struct { + Unused [8]uint8 +} +type SpiBusLockHandleT *SpiBusLockT +type SpiBusLockDevHandleT *SpiBusLockDevT + +// llgo:type C +type BgCtrlFuncT func(c.Pointer) + +/** + * @brief Try to claim a SPI peripheral + * + * Call this if your driver wants to manage a SPI peripheral. + * + * @param host Peripheral to claim + * @param source The caller indentification string. + * + * @return True if peripheral is claimed successfully; false if peripheral already is claimed. + */ +// llgo:link SpiHostDeviceT.SpicommonPeriphClaim C.spicommon_periph_claim +func (recv_ SpiHostDeviceT) SpicommonPeriphClaim(source *c.Char) bool { + return false +} + +/** + * @brief Check whether the spi periph is in use. + * + * @param host Peripheral to check. + * + * @return True if in use, otherwise false. + */ +// llgo:link SpiHostDeviceT.SpicommonPeriphInUse C.spicommon_periph_in_use +func (recv_ SpiHostDeviceT) SpicommonPeriphInUse() bool { + return false +} + +/** + * @brief Return the SPI peripheral so another driver can claim it. + * + * @param host Peripheral to return + * + * @return True if peripheral is returned successfully; false if peripheral was free to claim already. + */ +// llgo:link SpiHostDeviceT.SpicommonPeriphFree C.spicommon_periph_free +func (recv_ SpiHostDeviceT) SpicommonPeriphFree() bool { + return false +} + +// / Lock configuration struct +type SpiBusLockConfigT struct { + HostId c.Int + CsNum c.Int +} + +// / Child-lock configuration struct +type SpiBusLockDevConfigT struct { + Flags c.Uint32T +} + +/************* Common *********************/ +/** + * Initialize a lock for an SPI bus. + * + * @param out_lock Output of the handle to the lock + * @return + * - ESP_ERR_NO_MEM: if memory exhausted + * - ESP_OK: if success + */ +//go:linkname SpiBusInitLock C.spi_bus_init_lock +func SpiBusInitLock(out_lock *SpiBusLockHandleT, config *SpiBusLockConfigT) EspErrT + +/** + * Free the resources used by an SPI bus lock. + * + * @note All attached devices should have been unregistered before calling this + * funciton. + * + * @param lock Handle to the lock to free. + */ +//go:linkname SpiBusDeinitLock C.spi_bus_deinit_lock +func SpiBusDeinitLock(lock SpiBusLockHandleT) + +/** + * @brief Get the corresponding lock according to bus id. + * + * @param host_id The bus id to get the lock + * @return The lock handle + */ +// llgo:link SpiHostDeviceT.SpiBusLockGetById C.spi_bus_lock_get_by_id +func (recv_ SpiHostDeviceT) SpiBusLockGetById() SpiBusLockHandleT { + return nil +} + +/** + * @brief Configure how the SPI bus lock enable the background operation. + * + * @note The lock will not try to stop the background operations, but wait for + * The background operations finished indicated by `spi_bus_lock_bg_resume_acquired_dev`. + * + * @param lock Handle to the lock to set + * @param bg_enable The enabling function + * @param bg_disable The disabling function, set to NULL if not required + * @param arg Argument to pass to the enabling/disabling function. + */ +//go:linkname SpiBusLockSetBgControl C.spi_bus_lock_set_bg_control +func SpiBusLockSetBgControl(lock SpiBusLockHandleT, bg_enable BgCtrlFuncT, bg_disable BgCtrlFuncT, arg c.Pointer) + +/** + * Attach a device onto an SPI bus lock. The returning handle is used to perform + * following requests for the attached device. + * + * @param lock SPI bus lock to attach + * @param out_dev_handle Output handle corresponding to the device + * @param flags requirement of the device, bitwise OR of SPI_BUS_LOCK_FLAG_* flags + * + * @return + * - ESP_ERR_NOT_SUPPORTED: if there's no hardware resources for new devices. + * - ESP_ERR_NO_MEM: if memory exhausted + * - ESP_OK: if success + */ +//go:linkname SpiBusLockRegisterDev C.spi_bus_lock_register_dev +func SpiBusLockRegisterDev(lock SpiBusLockHandleT, config *SpiBusLockDevConfigT, out_dev_handle *SpiBusLockDevHandleT) EspErrT + +/** + * Detach a device from its bus and free the resources used + * + * @param dev_handle Handle to the device. + */ +//go:linkname SpiBusLockUnregisterDev C.spi_bus_lock_unregister_dev +func SpiBusLockUnregisterDev(dev_handle SpiBusLockDevHandleT) + +/** + * @brief Get the parent bus lock of the device + * + * @param dev_handle Handle to the device to get bus lock + * @return The bus lock handle + */ +//go:linkname SpiBusLockGetParent C.spi_bus_lock_get_parent +func SpiBusLockGetParent(dev_handle SpiBusLockDevHandleT) SpiBusLockHandleT + +/** + * @brief Get the device ID of a lock. + * + * The callers should allocate CS pins according to this ID. + * + * @param dev_handle Handle to the device to get ID + * @return ID of the device + */ +//go:linkname SpiBusLockGetDevId C.spi_bus_lock_get_dev_id +func SpiBusLockGetDevId(dev_handle SpiBusLockDevHandleT) c.Int + +/** + * @brief The device request to touch bus registers. Can only be called by the acquiring processor. + * + * Also check if the registers has been touched by other devices. + * + * @param dev_handle Handle to the device to operate the registers + * @return true if there has been other devices touching SPI registers. + * The caller may need to do a full-configuration. Otherwise return + * false. + */ +//go:linkname SpiBusLockTouch C.spi_bus_lock_touch +func SpiBusLockTouch(dev_handle SpiBusLockDevHandleT) bool + +/************* Acquiring service *********************/ +/** + * Acquiring the SPI bus for exclusive use. Will also wait for the BG to finish all requests of + * this device before it returns. + * + * After successfully return, the caller becomes the acquiring processor. + * + * @note For the main flash bus, `bg_disable` will be called to disable the cache. + * + * @param dev_handle Handle to the device request for acquiring. + * @param wait Time to wait until timeout or succeed, must be `portMAX_DELAY` for now. + * @return + * - ESP_OK: on success + * - ESP_ERR_INVALID_ARG: timeout is not portMAX_DELAY + */ +//go:linkname SpiBusLockAcquireStart C.spi_bus_lock_acquire_start +func SpiBusLockAcquireStart(dev_handle SpiBusLockDevHandleT, wait TickTypeT) EspErrT + +/** + * Release the bus acquired. Will pass the acquiring processor to other blocked + * processors (tasks or ISR), and cause them to be unblocked or invoked. + * + * The acquiring device may also become NULL if no device is asking for acquiring. + * In this case, the BG may be invoked if there is any BG requests. + * + * If the new acquiring device has BG requests, the BG will be invoked before the + * task is resumed later after the BG finishes all requests of the new acquiring + * device. Otherwise the task of the new acquiring device will be resumed immediately. + * + * @param dev_handle Handle to the device releasing the bus. + * @return + * - ESP_OK: on success + * - ESP_ERR_INVALID_STATE: the device hasn't acquired the lock yet + */ +//go:linkname SpiBusLockAcquireEnd C.spi_bus_lock_acquire_end +func SpiBusLockAcquireEnd(dev_handle SpiBusLockDevHandleT) EspErrT + +/** + * Get the device acquiring the bus. + * + * @note Return value is not stable as the acquiring processor may change + * when this function is called. + * + * @param lock Lock of SPI bus to get the acquiring device. + * @return The argument corresponding to the acquiring device, see + * `spi_bus_lock_register_dev`. + */ +//go:linkname SpiBusLockGetAcquiringDev C.spi_bus_lock_get_acquiring_dev +func SpiBusLockGetAcquiringDev(lock SpiBusLockHandleT) SpiBusLockDevHandleT + +/************* BG (Background, for ISR or cache) service *********************/ +/** + * Call by a device to request a BG operation. + * + * Depending on the bus lock state, the BG operations may be resumed by this + * call, or pending until BG operations allowed. + * + * Cleared by `spi_bus_lock_bg_clear_req` in the BG. + * + * @param dev_handle The device requesting BG operations. + * @return always ESP_OK + */ +//go:linkname SpiBusLockBgRequest C.spi_bus_lock_bg_request +func SpiBusLockBgRequest(dev_handle SpiBusLockDevHandleT) EspErrT + +/** + * Wait until the ISR has finished all the BG operations for the acquiring device. + * If any `spi_bus_lock_bg_request` for this device has been called after + * `spi_bus_lock_acquire_start`, this function must be called before any operation + * in the task. + * + * @note Can only be called when bus acquired by this device. + * + * @param dev_handle Handle to the device acquiring the bus. + * @param wait Time to wait until timeout or succeed, must be `portMAX_DELAY` for now. + * @return + * - ESP_OK: on success + * - ESP_ERR_INVALID_STATE: The device is not the acquiring bus. + * - ESP_ERR_INVALID_ARG: Timeout is not portMAX_DELAY. + */ +//go:linkname SpiBusLockWaitBgDone C.spi_bus_lock_wait_bg_done +func SpiBusLockWaitBgDone(dev_handle SpiBusLockDevHandleT, wait TickTypeT) EspErrT + +/** + * Handle interrupt and closure of last operation. Should be called at the beginning of the ISR, + * when the ISR is acting as the acquiring processor. + * + * @param lock The SPI bus lock + * + * @return false if the ISR has already touched the HW, should run closure of the + * last operation first; otherwise true if the ISR just start operating + * on the HW, closure should be skipped. + */ +//go:linkname SpiBusLockBgEntry C.spi_bus_lock_bg_entry +func SpiBusLockBgEntry(lock SpiBusLockHandleT) bool + +/** + * Handle the scheduling of other acquiring devices, and control of HW operation + * status. + * + * If no BG request is found, call with `wip=false`. This function will return false, + * indicating there is incoming BG requests for the current acquiring device (or + * for all devices if there is no acquiring device) and the ISR needs retry. + * Otherwise may schedule a new acquiring processor (unblock the task) if there + * is, and return true. + * + * Otherwise if a BG request is started in this ISR, call with `wip=true` and the + * function will enable the interrupt to make the ISR be called again when the + * request is done. + * + * This function is safe and should still be called when the ISR just lost its acquiring processor + * role, but hasn't quit. + * + * @note This function will not change acquiring device. The ISR call + * `spi_bus_lock_bg_update_acquiring` to check for new acquiring device, + * when acquiring devices need to be served before other devices. + * + * @param lock The SPI bus lock. + * @param wip Whether an operation is being executed when quitting the ISR. + * @param do_yield[out] Not touched when no yielding required, otherwise set + * to pdTRUE. + * @return false if retry is required, indicating that there is pending BG request. + * otherwise true and quit ISR is allowed. + */ +//go:linkname SpiBusLockBgExit C.spi_bus_lock_bg_exit +func SpiBusLockBgExit(lock SpiBusLockHandleT, wip bool, do_yield *BaseTypeT) bool + +/** + * Check whether there is device asking for the acquiring device, and the desired + * device for the next operation is also recommended. + * + * @note Must be called when the ISR is acting as the acquiring processor, and + * there is no acquiring device. + * + * @param lock The SPI bus lock. + * @param out_dev_lock The recommended device for hte next operation. It's the new + * acquiring device when found, otherwise a device that has active BG request. + * + * @return true if the ISR need to quit (new acquiring device has no active BG + * request, or no active BG requests for all devices when there is no + * acquiring device), otherwise false. + */ +//go:linkname SpiBusLockBgCheckDevAcq C.spi_bus_lock_bg_check_dev_acq +func SpiBusLockBgCheckDevAcq(lock SpiBusLockHandleT, out_dev_lock *SpiBusLockDevHandleT) bool + +/** + * Check if the device has BG requests. Must be called when the ISR is acting as + * the acquiring processor. + * + * @note This is not stable, may become true again when a task request for BG + * operation (by `spi_bus_lock_bg_request`). + * + * @param dev_lock The device to check. + * @return true if the device has BG requests, otherwise false. + */ +//go:linkname SpiBusLockBgCheckDevReq C.spi_bus_lock_bg_check_dev_req +func SpiBusLockBgCheckDevReq(dev_lock SpiBusLockDevHandleT) bool + +/** + * Clear the pending BG operation request of a device after served. Must be + * called when the ISR is acting as the acquiring processor. + * + * @note When the return value is true, the ISR will lost the acquiring processor role. Then + * `spi_bus_lock_bg_exit` must be called and checked before calling all other functions that + * require to be called when the ISR is the acquiring processor again. + * + * @param dev_handle The device whose request is served. + * @return True if no pending requests for the acquiring device, or for all devices + * if there is no acquiring device. Otherwise false. When the return value is + * true, the ISR is no longer the acquiring processor. + */ +//go:linkname SpiBusLockBgClearReq C.spi_bus_lock_bg_clear_req +func SpiBusLockBgClearReq(dev_lock SpiBusLockDevHandleT) bool + +/** + * Check if there is any active BG requests. + * + * @param lock The SPI bus lock. + * @return true if any device has active BG requst, otherwise false. + */ +//go:linkname SpiBusLockBgReqExist C.spi_bus_lock_bg_req_exist +func SpiBusLockBgReqExist(lock SpiBusLockHandleT) bool + +/** + * @brief Initialize the main flash device, called during chip startup. + * + * @return + * - ESP_OK: if success + * - ESP_ERR_NO_MEM: memory exhausted + */ +//go:linkname SpiBusLockInitMainDev C.spi_bus_lock_init_main_dev +func SpiBusLockInitMainDev() EspErrT diff --git a/esp32/spi_slave_hal.go b/esp32/spi_slave_hal.go new file mode 100644 index 00000000..2924e3b5 --- /dev/null +++ b/esp32/spi_slave_hal.go @@ -0,0 +1,160 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Context that should be maintained by both the driver and the HAL. + */ + +type SpiSlaveHalContextT struct { + Hw *SpiDevT + DmadescRx *SpiDmaDescT + DmadescTx *SpiDmaDescT + DmadescN c.Int + Mode c.Int + Bitlen c.Uint32T + TxBuffer c.Pointer + RxBuffer c.Pointer + RcvBitlen c.Uint32T +} + +type SpiSlaveHalConfigT struct { + HostId c.Uint32T +} + +/** + * Init the peripheral and the context. + * + * @param hal Context of the HAL layer. + * @param hal_config Configuration of the HAL + */ +// llgo:link (*SpiSlaveHalContextT).SpiSlaveHalInit C.spi_slave_hal_init +func (recv_ *SpiSlaveHalContextT) SpiSlaveHalInit(hal_config *SpiSlaveHalConfigT) { +} + +/** + * Deinit the peripheral (and the context if needed). + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiSlaveHalContextT).SpiSlaveHalDeinit C.spi_slave_hal_deinit +func (recv_ *SpiSlaveHalContextT) SpiSlaveHalDeinit() { +} + +/** + * Setup device-related configurations according to the settings in the context. + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiSlaveHalContextT).SpiSlaveHalSetupDevice C.spi_slave_hal_setup_device +func (recv_ *SpiSlaveHalContextT) SpiSlaveHalSetupDevice() { +} + +/** + * Prepare rx hardware for a new DMA trans + * + * @param hw Beginning address of the peripheral registers. + */ +// llgo:link (*SpiDevT).SpiSlaveHalHwPrepareRx C.spi_slave_hal_hw_prepare_rx +func (recv_ *SpiDevT) SpiSlaveHalHwPrepareRx() { +} + +/** + * Prepare tx hardware for a new DMA trans + * + * @param hw Beginning address of the peripheral registers. + */ +// llgo:link (*SpiDevT).SpiSlaveHalHwPrepareTx C.spi_slave_hal_hw_prepare_tx +func (recv_ *SpiDevT) SpiSlaveHalHwPrepareTx() { +} + +/** + * Rest peripheral registers to default value + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiSlaveHalContextT).SpiSlaveHalHwReset C.spi_slave_hal_hw_reset +func (recv_ *SpiSlaveHalContextT) SpiSlaveHalHwReset() { +} + +/** + * Rest hw fifo in peripheral, for a CPU controlled trans + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiSlaveHalContextT).SpiSlaveHalHwFifoReset C.spi_slave_hal_hw_fifo_reset +func (recv_ *SpiSlaveHalContextT) SpiSlaveHalHwFifoReset(tx_rst bool, rx_rst bool) { +} + +/** + * Push data needed to be transmit into hw fifo + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiSlaveHalContextT).SpiSlaveHalPushTxBuffer C.spi_slave_hal_push_tx_buffer +func (recv_ *SpiSlaveHalContextT) SpiSlaveHalPushTxBuffer() { +} + +/** + * Config transaction bit length for slave + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiSlaveHalContextT).SpiSlaveHalSetTransBitlen C.spi_slave_hal_set_trans_bitlen +func (recv_ *SpiSlaveHalContextT) SpiSlaveHalSetTransBitlen() { +} + +/** + * Enable/Disable miso/mosi signals in peripheral + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiSlaveHalContextT).SpiSlaveHalEnableDataLine C.spi_slave_hal_enable_data_line +func (recv_ *SpiSlaveHalContextT) SpiSlaveHalEnableDataLine() { +} + +/** + * Trigger start a user-defined transaction. + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiSlaveHalContextT).SpiSlaveHalUserStart C.spi_slave_hal_user_start +func (recv_ *SpiSlaveHalContextT) SpiSlaveHalUserStart() { +} + +/** + * Check whether the transaction is done (trans_done is set). + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiSlaveHalContextT).SpiSlaveHalUsrIsDone C.spi_slave_hal_usr_is_done +func (recv_ *SpiSlaveHalContextT) SpiSlaveHalUsrIsDone() bool { + return false +} + +/** + * Post transaction operations, fetch data from the buffer and recorded the length. + * + * @param hal Context of the HAL layer. + */ +// llgo:link (*SpiSlaveHalContextT).SpiSlaveHalStoreResult C.spi_slave_hal_store_result +func (recv_ *SpiSlaveHalContextT) SpiSlaveHalStoreResult() { +} + +/** + * Get the length of last transaction, in bits. Should be called after ``spi_slave_hal_store_result``. + * + * Note that if last transaction is longer than configured before, the return + * value still the actual length. + * + * @param hal Context of the HAL layer. + * + * @return Length of the last transaction, in bits. + */ +// llgo:link (*SpiSlaveHalContextT).SpiSlaveHalGetRcvBitlen C.spi_slave_hal_get_rcv_bitlen +func (recv_ *SpiSlaveHalContextT) SpiSlaveHalGetRcvBitlen() c.Uint32T { + return 0 +} diff --git a/esp32/spi_slave_hd_hal.go b/esp32/spi_slave_hd_hal.go new file mode 100644 index 00000000..d7dca252 --- /dev/null +++ b/esp32/spi_slave_hd_hal.go @@ -0,0 +1,292 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type SpiDmaDescT DmaDescriptorAlign4T + +/** + * @brief Type of dma descriptor with appended members + * this structure inherits DMA descriptor, with a pointer to the transaction descriptor passed from users. + */ + +type SpiSlaveHdHalDescAppendT struct { + Desc *SpiDmaDescT + Arg c.Pointer +} + +// / Configuration of the HAL +type SpiSlaveHdHalConfigT struct { + HostId c.Uint32T + DmaEnabled bool + AppendMode bool + SpicsIoNum c.Uint32T + Mode c.Uint8T + CommandBits c.Uint32T + AddressBits c.Uint32T + DummyBits c.Uint32T +} + +// / Context of the HAL, initialized by :cpp:func:`spi_slave_hd_hal_init`. +type SpiSlaveHdHalContextT struct { + DmadescTx *SpiSlaveHdHalDescAppendT + DmadescRx *SpiSlaveHdHalDescAppendT + Dev *SpiDevT + DmaEnabled bool + AppendMode bool + DmaDescNum c.Uint32T + CurrentEofAddr c.Uint32T + TxCurDesc *SpiSlaveHdHalDescAppendT + TxDmaHead *SpiSlaveHdHalDescAppendT + TxDmaTail *SpiSlaveHdHalDescAppendT + TxUsedDescCnt c.Uint32T + TxRecycledDescCnt c.Uint32T + RxCurDesc *SpiSlaveHdHalDescAppendT + RxDmaHead *SpiSlaveHdHalDescAppendT + RxDmaTail *SpiSlaveHdHalDescAppendT + RxUsedDescCnt c.Uint32T + RxRecycledDescCnt c.Uint32T + IntrNotTriggered c.Uint32T + TxDmaStarted bool + RxDmaStarted bool +} + +/** + * @brief Initialize the hardware and part of the context + * + * @param hal Context of the HAL layer + * @param hal_config Configuration of the HAL + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalInit C.spi_slave_hd_hal_init +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalInit(hal_config *SpiSlaveHdHalConfigT) { +} + +/** + * @brief Check and clear signal of one event + * + * @param hal Context of the HAL layer + * @param ev Event to check + * @return True if event triggered, otherwise false + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalCheckClearEvent C.spi_slave_hd_hal_check_clear_event +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalCheckClearEvent(ev SpiEventT) bool { + return false +} + +/** + * @brief Check and clear the interrupt of one event. + * + * @note The event source will be kept, so that the interrupt can be invoked by + * :cpp:func:`spi_slave_hd_hal_invoke_event_intr`. If event not triggered, its interrupt source + * will not be disabled either. + * + * @param hal Context of the HAL layer + * @param ev Event to check and disable + * @return True if event triggered, otherwise false + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalCheckDisableEvent C.spi_slave_hd_hal_check_disable_event +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalCheckDisableEvent(ev SpiEventT) bool { + return false +} + +/** + * @brief Enable to involve the ISR of corresponding event. + * + * @note The function, compared with :cpp:func:`spi_slave_hd_hal_enable_event_intr`, contains a + * workaround to force trigger the interrupt, even if the interrupt source cannot be initialized + * correctly. + * + * @param hal Context of the HAL layer + * @param ev Event (reason) to invoke the ISR + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalInvokeEventIntr C.spi_slave_hd_hal_invoke_event_intr +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalInvokeEventIntr(ev SpiEventT) { +} + +/** + * @brief Enable the interrupt source of corresponding event. + * + * @param hal Context of the HAL layer + * @param ev Event whose corresponding interrupt source should be enabled. + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalEnableEventIntr C.spi_slave_hd_hal_enable_event_intr +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalEnableEventIntr(ev SpiEventT) { +} + +//////////////////////////////////////////////////////////////////////////////// +// RX DMA +//////////////////////////////////////////////////////////////////////////////// +/** + * @brief Start the RX DMA operation to the specified buffer. + * + * @param hal Context of the HAL layer + * @param[out] out_buf Buffer to receive the data + * @param len Maximul length to receive + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalRxdma C.spi_slave_hd_hal_rxdma +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalRxdma() { +} + +/** + * @brief Get the length of total received data + * + * @param hal Context of the HAL layer + * @return The received length + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalRxdmaSegGetLen C.spi_slave_hd_hal_rxdma_seg_get_len +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalRxdmaSegGetLen() c.Int { + return 0 +} + +/** + * @brief Prepare hardware for a new dma rx trans + * + * @param hal Context of the HAL layer + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalHwPrepareRx C.spi_slave_hd_hal_hw_prepare_rx +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalHwPrepareRx() { +} + +//////////////////////////////////////////////////////////////////////////////// +// TX DMA +//////////////////////////////////////////////////////////////////////////////// +/** + * @brief Start the TX DMA operation with the specified buffer + * + * @param hal Context of the HAL layer + * @param data Buffer of data to send + * @param len Size of the buffer, also the maximum length to send + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalTxdma C.spi_slave_hd_hal_txdma +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalTxdma() { +} + +/** + * @brief Prepare hardware for a new dma tx trans + * + * @param hal Context of the HAL layer + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalHwPrepareTx C.spi_slave_hd_hal_hw_prepare_tx +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalHwPrepareTx() { +} + +//////////////////////////////////////////////////////////////////////////////// +// Shared buffer +//////////////////////////////////////////////////////////////////////////////// +/** + * @brief Read from the shared register buffer + * + * @param hal Context of the HAL layer + * @param addr Address of the shared register to read + * @param out_data Buffer to store the read data + * @param len Length to read from the shared buffer + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalReadBuffer C.spi_slave_hd_hal_read_buffer +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalReadBuffer(addr c.Int, out_data *c.Uint8T, len c.SizeT) { +} + +/** + * @brief Write the shared register buffer + * + * @param hal Context of the HAL layer + * @param addr Address of the shared register to write + * @param data Buffer of the data to write + * @param len Length to write into the shared buffer + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalWriteBuffer C.spi_slave_hd_hal_write_buffer +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalWriteBuffer(addr c.Int, data *c.Uint8T, len c.SizeT) { +} + +/** + * @brief Get the length of previous transaction. + * + * @param hal Context of the HAL layer + * @return The length of previous transaction + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalGetRxlen C.spi_slave_hd_hal_get_rxlen +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalGetRxlen() c.Int { + return 0 +} + +/** + * @brief Get the address of last transaction + * + * @param hal Context of the HAL layer + * @return The address of last transaction + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalGetLastAddr C.spi_slave_hd_hal_get_last_addr +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalGetLastAddr() c.Int { + return 0 +} + +//////////////////////////////////////////////////////////////////////////////// +// Append Mode +//////////////////////////////////////////////////////////////////////////////// +/** + * @brief Return the finished TX transaction + * + * @note This API is based on this assumption: the hardware behaviour of current transaction completion is only modified by the its own caller layer. + * This means if some other code changed the hardware behaviour (e.g. clear intr raw bit), or the caller call this API without noticing the HW behaviour, + * this API will go wrong. + * + * @param hal Context of the HAL layer + * @param out_trans Pointer to the caller-defined transaction + * @param real_buff_addr Actually data buffer head the HW used + * @return 1: Transaction is finished; 0: Transaction is not finished + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalGetTxFinishedTrans C.spi_slave_hd_hal_get_tx_finished_trans +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalGetTxFinishedTrans(out_trans *c.Pointer, real_buff_addr *c.Pointer) bool { + return false +} + +/** + * @brief Return the finished RX transaction + * + * @note This API is based on this assumption: the hardware behaviour of current transaction completion is only modified by the its own caller layer. + * This means if some other code changed the hardware behaviour (e.g. clear intr raw bit), or the caller call this API without noticing the HW behaviour, + * this API will go wrong. + * + * @param hal Context of the HAL layer + * @param out_trans Pointer to the caller-defined transaction + * @param real_buff_addr Actually data buffer head the HW used + * @param out_len Actual number of bytes of received data + * @return 1: Transaction is finished; 0: Transaction is not finished + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalGetRxFinishedTrans C.spi_slave_hd_hal_get_rx_finished_trans +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalGetRxFinishedTrans(out_trans *c.Pointer, real_buff_addr *c.Pointer, out_len *c.SizeT) bool { + return false +} + +/** + * @brief Load the TX DMA descriptors without stopping the DMA + * + * @param hal Context of the HAL layer + * @param data Buffer of the transaction data + * @param len Length of the data + * @param arg Pointer used by the caller to indicate the transaction. Will be returned by ``spi_slave_hd_hal_get_tx_finished_trans`` when transaction is finished + * @return + * - ESP_OK: on success + * - ESP_ERR_INVALID_STATE: Function called in invalid state. + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalTxdmaAppend C.spi_slave_hd_hal_txdma_append +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalTxdmaAppend(data *c.Uint8T, len c.SizeT, arg c.Pointer) EspErrT { + return 0 +} + +/** + * @brief Load the RX DMA descriptors without stopping the DMA + * + * @param hal Context of the HAL layer + * @param data Buffer of the transaction data + * @param len Length of the data + * @param arg Pointer used by the caller to indicate the transaction. Will be returned by ``spi_slave_hd_hal_get_rx_finished_trans`` when transaction is finished + * @return + * - ESP_OK: on success + * - ESP_ERR_INVALID_STATE: Function called in invalid state. + */ +// llgo:link (*SpiSlaveHdHalContextT).SpiSlaveHdHalRxdmaAppend C.spi_slave_hd_hal_rxdma_append +func (recv_ *SpiSlaveHdHalContextT) SpiSlaveHdHalRxdmaAppend(data *c.Uint8T, len c.SizeT, arg c.Pointer) EspErrT { + return 0 +} diff --git a/esp32/spi_struct.go b/esp32/spi_struct.go new file mode 100644 index 00000000..e2938ba9 --- /dev/null +++ b/esp32/spi_struct.go @@ -0,0 +1,98 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type SpiDevS struct { + Cmd struct { + Val c.Uint32T + } + Addr c.Uint32T + Ctrl struct { + Val c.Uint32T + } + Clock struct { + Val c.Uint32T + } + User struct { + Val c.Uint32T + } + User1 struct { + Val c.Uint32T + } + User2 struct { + Val c.Uint32T + } + MsDlen struct { + Val c.Uint32T + } + Misc struct { + Val c.Uint32T + } + DinMode struct { + Val c.Uint32T + } + DinNum struct { + Val c.Uint32T + } + DoutMode struct { + Val c.Uint32T + } + DmaConf struct { + Val c.Uint32T + } + DmaIntEna struct { + Val c.Uint32T + } + DmaIntClr struct { + Val c.Uint32T + } + DmaIntRaw struct { + Val c.Uint32T + } + DmaIntSt struct { + Val c.Uint32T + } + DmaIntSet struct { + Val c.Uint32T + } + Reserved48 c.Uint32T + Reserved4c c.Uint32T + Reserved50 c.Uint32T + Reserved54 c.Uint32T + Reserved58 c.Uint32T + Reserved5c c.Uint32T + Reserved60 c.Uint32T + Reserved64 c.Uint32T + Reserved68 c.Uint32T + Reserved6c c.Uint32T + Reserved70 c.Uint32T + Reserved74 c.Uint32T + Reserved78 c.Uint32T + Reserved7c c.Uint32T + Reserved80 c.Uint32T + Reserved84 c.Uint32T + Reserved88 c.Uint32T + Reserved8c c.Uint32T + Reserved90 c.Uint32T + Reserved94 c.Uint32T + DataBuf [16]c.Uint32T + ReservedD8 c.Uint32T + ReservedDc c.Uint32T + Slave struct { + Val c.Uint32T + } + Slave1 struct { + Val c.Uint32T + } + ClkGate struct { + Val c.Uint32T + } + ReservedEc c.Uint32T + Date struct { + Val c.Uint32T + } +} +type SpiDevT SpiDevS diff --git a/esp32/spi_types.go b/esp32/spi_types.go new file mode 100644 index 00000000..89a19636 --- /dev/null +++ b/esp32/spi_types.go @@ -0,0 +1,61 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type SpiHostDeviceT c.Int + +const ( + SPI1_HOST SpiHostDeviceT = 0 + SPI2_HOST SpiHostDeviceT = 1 + SPI3_HOST SpiHostDeviceT = 2 + SPI_HOST_MAX SpiHostDeviceT = 3 +) + +type SpiClockSourceT SocPeriphSpiClkSrcT +type SpiEventT c.Int + +const ( + SPI_EV_BUF_TX SpiEventT = 1 + SPI_EV_BUF_RX SpiEventT = 2 + SPI_EV_SEND_DMA_READY SpiEventT = 4 + SPI_EV_SEND SpiEventT = 8 + SPI_EV_RECV_DMA_READY SpiEventT = 16 + SPI_EV_RECV SpiEventT = 32 + SPI_EV_CMD9 SpiEventT = 64 + SPI_EV_CMDA SpiEventT = 128 + SPI_EV_TRANS SpiEventT = 256 +) + +/** + * @brief Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ + +type SpiLineModeT struct { + CmdLines c.Uint8T + AddrLines c.Uint8T + DataLines c.Uint8T +} +type SpiCommandT c.Int + +const ( + SPI_CMD_HD_WRBUF SpiCommandT = 1 + SPI_CMD_HD_RDBUF SpiCommandT = 2 + SPI_CMD_HD_WRDMA SpiCommandT = 4 + SPI_CMD_HD_RDDMA SpiCommandT = 8 + SPI_CMD_HD_SEG_END SpiCommandT = 16 + SPI_CMD_HD_EN_QPI SpiCommandT = 32 + SPI_CMD_HD_WR_END SpiCommandT = 64 + SPI_CMD_HD_INT0 SpiCommandT = 128 + SPI_CMD_HD_INT1 SpiCommandT = 256 + SPI_CMD_HD_INT2 SpiCommandT = 512 +) + +type SpiSamplingPointT c.Int + +const ( + SPI_SAMPLING_POINT_PHASE_0 SpiSamplingPointT = 0 + SPI_SAMPLING_POINT_PHASE_1 SpiSamplingPointT = 1 +) diff --git a/esp32/spimem_flash_ll.go b/esp32/spimem_flash_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/spimem_flash_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/spinlock.go b/esp32/spinlock.go new file mode 100644 index 00000000..1b494791 --- /dev/null +++ b/esp32/spinlock.go @@ -0,0 +1,16 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const SPINLOCK_FREE = 0xB33FFFFF +const SPINLOCK_NO_WAIT = 0 +const SPINLOCK_OWNER_ID_0 = 0xCDCD +const SPINLOCK_OWNER_ID_1 = 0xABAB + +type SpinlockT struct { + Owner c.Uint32T + Count c.Uint32T +} diff --git a/esp32/stack_macros.go b/esp32/stack_macros.go new file mode 100644 index 00000000..5cf341ab --- /dev/null +++ b/esp32/stack_macros.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +const PortSTACK_LIMIT_PADDING = 0 diff --git a/esp32/startup_internal.go b/esp32/startup_internal.go new file mode 100644 index 00000000..1977ede1 --- /dev/null +++ b/esp32/startup_internal.go @@ -0,0 +1,25 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const ESP_SYSTEM_INIT_STAGE_CORE = 0 +const ESP_SYSTEM_INIT_STAGE_SECONDARY = 1 + +// llgo:type C +type SysStartupFnT func() + +//go:linkname StartupResumeOtherCores C.startup_resume_other_cores +func StartupResumeOtherCores() + +/** + * Internal structure describing ESP_SYSTEM_INIT_FN startup functions + */ + +type EspSystemInitFnT struct { + Fn c.Pointer + Cores c.Uint16T + Stage c.Uint16T +} diff --git a/esp32/stream_buffer.go b/esp32/stream_buffer.go new file mode 100644 index 00000000..c9829449 --- /dev/null +++ b/esp32/stream_buffer.go @@ -0,0 +1,579 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Type by which stream buffers are referenced. For example, a call to + * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can + * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(), + * etc. + */ + +type StreamBufferDefT struct { + Unused [8]uint8 +} +type StreamBufferHandleT *StreamBufferDefT + +// llgo:type C +type StreamBufferCallbackFunctionT func(StreamBufferHandleT, BaseTypeT, *BaseTypeT) + +/** + * + * Retrieve pointers to a statically created stream buffer's data structure + * buffer and storage area buffer. These are the same buffers that are supplied + * at the time of creation. + * + * @param xStreamBuffer The stream buffer for which to retrieve the buffers. + * + * @param ppucStreamBufferStorageArea Used to return a pointer to the stream + * buffer's storage area buffer. + * + * @param ppxStaticStreamBuffer Used to return a pointer to the stream + * buffer's data structure buffer. + * + * @return pdTRUE if buffers were retrieved, pdFALSE otherwise. + * + * \ingroup StreamBufferManagement + */ +//go:linkname XStreamBufferGetStaticBuffers C.xStreamBufferGetStaticBuffers +func XStreamBufferGetStaticBuffers(xStreamBuffer StreamBufferHandleT, ppucStreamBufferStorageArea **c.Uint8T, ppxStaticStreamBuffer **StaticStreamBufferT) BaseTypeT + +/** + * + * Sends bytes to a stream buffer. The bytes are copied into the stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferSend() to write to a stream buffer from a task. Use + * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt + * service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer to which a stream is + * being sent. + * + * @param pvTxData A pointer to the buffer that holds the bytes to be copied + * into the stream buffer. + * + * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData + * into the stream buffer. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for enough space to become available in the stream + * buffer, should the stream buffer contain too little space to hold the + * another xDataLengthBytes bytes. The block time is specified in tick periods, + * so the absolute time it represents is dependent on the tick frequency. The + * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds + * into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will + * cause the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. If a task times out + * before it can write all xDataLengthBytes into the buffer it will still write + * as many bytes as possible. A task does not use any CPU time when it is in + * the blocked state. + * + * @return The number of bytes written to the stream buffer. If a task times + * out before it can write all xDataLengthBytes into the buffer it will still + * write as many bytes as possible. + * + * Example use: + * @code{c} + * void vAFunction( StreamBufferHandle_t xStreamBuffer ) + * { + * size_t xBytesSent; + * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 }; + * char *pcStringToSend = "String to send"; + * const TickType_t x100ms = pdMS_TO_TICKS( 100 ); + * + * // Send an array to the stream buffer, blocking for a maximum of 100ms to + * // wait for enough space to be available in the stream buffer. + * xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms ); + * + * if( xBytesSent != sizeof( ucArrayToSend ) ) + * { + * // The call to xStreamBufferSend() times out before there was enough + * // space in the buffer for the data to be written, but it did + * // successfully write xBytesSent bytes. + * } + * + * // Send the string to the stream buffer. Return immediately if there is not + * // enough space in the buffer. + * xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 ); + * + * if( xBytesSent != strlen( pcStringToSend ) ) + * { + * // The entire string could not be added to the stream buffer because + * // there was not enough free space in the buffer, but xBytesSent bytes + * // were sent. Could try again to send the remaining bytes. + * } + * } + * @endcode + * \ingroup StreamBufferManagement + */ +//go:linkname XStreamBufferSend C.xStreamBufferSend +func XStreamBufferSend(xStreamBuffer StreamBufferHandleT, pvTxData c.Pointer, xDataLengthBytes c.SizeT, xTicksToWait TickTypeT) c.SizeT + +/** + * + * Interrupt safe version of the API function that sends a stream of bytes to + * the stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferSend() to write to a stream buffer from a task. Use + * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt + * service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer to which a stream is + * being sent. + * + * @param pvTxData A pointer to the data that is to be copied into the stream + * buffer. + * + * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData + * into the stream buffer. + * + * @param pxHigherPriorityTaskWoken It is possible that a stream buffer will + * have a task blocked on it waiting for data. Calling + * xStreamBufferSendFromISR() can make data available, and so cause a task that + * was waiting for data to leave the Blocked state. If calling + * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the + * unblocked task has a priority higher than the currently executing task (the + * task that was interrupted), then, internally, xStreamBufferSendFromISR() + * will set *pxHigherPriorityTaskWoken to pdTRUE. If + * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. This will + * ensure that the interrupt returns directly to the highest priority Ready + * state task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it + * is passed into the function. See the example code below for an example. + * + * @return The number of bytes actually written to the stream buffer, which will + * be less than xDataLengthBytes if the stream buffer didn't have enough free + * space for all the bytes to be written. + * + * Example use: + * @code{c} + * // A stream buffer that has already been created. + * StreamBufferHandle_t xStreamBuffer; + * + * void vAnInterruptServiceRoutine( void ) + * { + * size_t xBytesSent; + * char *pcStringToSend = "String to send"; + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. + * + * // Attempt to send the string to the stream buffer. + * xBytesSent = xStreamBufferSendFromISR( xStreamBuffer, + * ( void * ) pcStringToSend, + * strlen( pcStringToSend ), + * &xHigherPriorityTaskWoken ); + * + * if( xBytesSent != strlen( pcStringToSend ) ) + * { + * // There was not enough free space in the stream buffer for the entire + * // string to be written, ut xBytesSent bytes were written. + * } + * + * // If xHigherPriorityTaskWoken was set to pdTRUE inside + * // xStreamBufferSendFromISR() then a task that has a priority above the + * // priority of the currently executing task was unblocked and a context + * // switch should be performed to ensure the ISR returns to the unblocked + * // task. In most FreeRTOS ports this is done by simply passing + * // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the + * // variables value, and perform the context switch if necessary. Check the + * // documentation for the port in use for port specific instructions. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * @endcode + * \ingroup StreamBufferManagement + */ +//go:linkname XStreamBufferSendFromISR C.xStreamBufferSendFromISR +func XStreamBufferSendFromISR(xStreamBuffer StreamBufferHandleT, pvTxData c.Pointer, xDataLengthBytes c.SizeT, pxHigherPriorityTaskWoken *BaseTypeT) c.SizeT + +/** + * + * Receives bytes from a stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferReceive() to read from a stream buffer from a task. Use + * xStreamBufferReceiveFromISR() to read from a stream buffer from an + * interrupt service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer from which bytes are to + * be received. + * + * @param pvRxData A pointer to the buffer into which the received bytes will be + * copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the + * pvRxData parameter. This sets the maximum number of bytes to receive in one + * call. xStreamBufferReceive will return as many bytes as possible up to a + * maximum set by xBufferLengthBytes. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for data to become available if the stream buffer is + * empty. xStreamBufferReceive() will return immediately if xTicksToWait is + * zero. The block time is specified in tick periods, so the absolute time it + * represents is dependent on the tick frequency. The macro pdMS_TO_TICKS() can + * be used to convert a time specified in milliseconds into a time specified in + * ticks. Setting xTicksToWait to portMAX_DELAY will cause the task to wait + * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1 + * in FreeRTOSConfig.h. A task does not use any CPU time when it is in the + * Blocked state. + * + * @return The number of bytes actually read from the stream buffer, which will + * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed + * out before xBufferLengthBytes were available. + * + * Example use: + * @code{c} + * void vAFunction( StreamBuffer_t xStreamBuffer ) + * { + * uint8_t ucRxData[ 20 ]; + * size_t xReceivedBytes; + * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 ); + * + * // Receive up to another sizeof( ucRxData ) bytes from the stream buffer. + * // Wait in the Blocked state (so not using any CPU processing time) for a + * // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be + * // available. + * xReceivedBytes = xStreamBufferReceive( xStreamBuffer, + * ( void * ) ucRxData, + * sizeof( ucRxData ), + * xBlockTime ); + * + * if( xReceivedBytes > 0 ) + * { + * // A ucRxData contains another xReceivedBytes bytes of data, which can + * // be processed here.... + * } + * } + * @endcode + * \ingroup StreamBufferManagement + */ +//go:linkname XStreamBufferReceive C.xStreamBufferReceive +func XStreamBufferReceive(xStreamBuffer StreamBufferHandleT, pvRxData c.Pointer, xBufferLengthBytes c.SizeT, xTicksToWait TickTypeT) c.SizeT + +/** + * + * An interrupt safe version of the API function that receives bytes from a + * stream buffer. + * + * Use xStreamBufferReceive() to read bytes from a stream buffer from a task. + * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an + * interrupt service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer from which a stream + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received bytes are + * copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the + * pvRxData parameter. This sets the maximum number of bytes to receive in one + * call. xStreamBufferReceive will return as many bytes as possible up to a + * maximum set by xBufferLengthBytes. + * + * @param pxHigherPriorityTaskWoken It is possible that a stream buffer will + * have a task blocked on it waiting for space to become available. Calling + * xStreamBufferReceiveFromISR() can make space available, and so cause a task + * that is waiting for space to leave the Blocked state. If calling + * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and + * the unblocked task has a priority higher than the currently executing task + * (the task that was interrupted), then, internally, + * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE. + * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. That will + * ensure the interrupt returns directly to the highest priority Ready state + * task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it is + * passed into the function. See the code example below for an example. + * + * @return The number of bytes read from the stream buffer, if any. + * + * Example use: + * @code{c} + * // A stream buffer that has already been created. + * StreamBuffer_t xStreamBuffer; + * + * void vAnInterruptServiceRoutine( void ) + * { + * uint8_t ucRxData[ 20 ]; + * size_t xReceivedBytes; + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. + * + * // Receive the next stream from the stream buffer. + * xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer, + * ( void * ) ucRxData, + * sizeof( ucRxData ), + * &xHigherPriorityTaskWoken ); + * + * if( xReceivedBytes > 0 ) + * { + * // ucRxData contains xReceivedBytes read from the stream buffer. + * // Process the stream here.... + * } + * + * // If xHigherPriorityTaskWoken was set to pdTRUE inside + * // xStreamBufferReceiveFromISR() then a task that has a priority above the + * // priority of the currently executing task was unblocked and a context + * // switch should be performed to ensure the ISR returns to the unblocked + * // task. In most FreeRTOS ports this is done by simply passing + * // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the + * // variables value, and perform the context switch if necessary. Check the + * // documentation for the port in use for port specific instructions. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * @endcode + * \ingroup StreamBufferManagement + */ +//go:linkname XStreamBufferReceiveFromISR C.xStreamBufferReceiveFromISR +func XStreamBufferReceiveFromISR(xStreamBuffer StreamBufferHandleT, pvRxData c.Pointer, xBufferLengthBytes c.SizeT, pxHigherPriorityTaskWoken *BaseTypeT) c.SizeT + +/** + * + * Deletes a stream buffer that was previously created using a call to + * xStreamBufferCreate() or xStreamBufferCreateStatic(). If the stream + * buffer was created using dynamic memory (that is, by xStreamBufferCreate()), + * then the allocated memory is freed. + * + * A stream buffer handle must not be used after the stream buffer has been + * deleted. + * + * @param xStreamBuffer The handle of the stream buffer to be deleted. + * + * \ingroup StreamBufferManagement + */ +//go:linkname VStreamBufferDelete C.vStreamBufferDelete +func VStreamBufferDelete(xStreamBuffer StreamBufferHandleT) + +/** + * + * Queries a stream buffer to see if it is full. A stream buffer is full if it + * does not have any free space, and therefore cannot accept any more data. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return If the stream buffer is full then pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \ingroup StreamBufferManagement + */ +//go:linkname XStreamBufferIsFull C.xStreamBufferIsFull +func XStreamBufferIsFull(xStreamBuffer StreamBufferHandleT) BaseTypeT + +/** + * + * Queries a stream buffer to see if it is empty. A stream buffer is empty if + * it does not contain any data. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return If the stream buffer is empty then pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \ingroup StreamBufferManagement + */ +//go:linkname XStreamBufferIsEmpty C.xStreamBufferIsEmpty +func XStreamBufferIsEmpty(xStreamBuffer StreamBufferHandleT) BaseTypeT + +/** + * + * Resets a stream buffer to its initial, empty, state. Any data that was in + * the stream buffer is discarded. A stream buffer can only be reset if there + * are no tasks blocked waiting to either send to or receive from the stream + * buffer. + * + * @param xStreamBuffer The handle of the stream buffer being reset. + * + * @return If the stream buffer is reset then pdPASS is returned. If there was + * a task blocked waiting to send to or read from the stream buffer then the + * stream buffer is not reset and pdFAIL is returned. + * + * \ingroup StreamBufferManagement + */ +//go:linkname XStreamBufferReset C.xStreamBufferReset +func XStreamBufferReset(xStreamBuffer StreamBufferHandleT) BaseTypeT + +/** + * + * Queries a stream buffer to see how much free space it contains, which is + * equal to the amount of data that can be sent to the stream buffer before it + * is full. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return The number of bytes that can be written to the stream buffer before + * the stream buffer would be full. + * + * \ingroup StreamBufferManagement + */ +//go:linkname XStreamBufferSpacesAvailable C.xStreamBufferSpacesAvailable +func XStreamBufferSpacesAvailable(xStreamBuffer StreamBufferHandleT) c.SizeT + +/** + * + * Queries a stream buffer to see how much data it contains, which is equal to + * the number of bytes that can be read from the stream buffer before the stream + * buffer would be empty. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return The number of bytes that can be read from the stream buffer before + * the stream buffer would be empty. + * + * \ingroup StreamBufferManagement + */ +//go:linkname XStreamBufferBytesAvailable C.xStreamBufferBytesAvailable +func XStreamBufferBytesAvailable(xStreamBuffer StreamBufferHandleT) c.SizeT + +/** + * + * A stream buffer's trigger level is the number of bytes that must be in the + * stream buffer before a task that is blocked on the stream buffer to + * wait for data is moved out of the blocked state. For example, if a task is + * blocked on a read of an empty stream buffer that has a trigger level of 1 + * then the task will be unblocked when a single byte is written to the buffer + * or the task's block time expires. As another example, if a task is blocked + * on a read of an empty stream buffer that has a trigger level of 10 then the + * task will not be unblocked until the stream buffer contains at least 10 bytes + * or the task's block time expires. If a reading task's block time expires + * before the trigger level is reached then the task will still receive however + * many bytes are actually available. Setting a trigger level of 0 will result + * in a trigger level of 1 being used. It is not valid to specify a trigger + * level that is greater than the buffer size. + * + * A trigger level is set when the stream buffer is created, and can be modified + * using xStreamBufferSetTriggerLevel(). + * + * @param xStreamBuffer The handle of the stream buffer being updated. + * + * @param xTriggerLevel The new trigger level for the stream buffer. + * + * @return If xTriggerLevel was less than or equal to the stream buffer's length + * then the trigger level will be updated and pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \ingroup StreamBufferManagement + */ +//go:linkname XStreamBufferSetTriggerLevel C.xStreamBufferSetTriggerLevel +func XStreamBufferSetTriggerLevel(xStreamBuffer StreamBufferHandleT, xTriggerLevel c.SizeT) BaseTypeT + +/** + * + * For advanced users only. + * + * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is sent to a message buffer or stream buffer. If there was a task that + * was blocked on the message or stream buffer waiting for data to arrive then + * the sbSEND_COMPLETED() macro sends a notification to the task to remove it + * from the Blocked state. xStreamBufferSendCompletedFromISR() does the same + * thing. It is provided to enable application writers to implement their own + * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xStreamBuffer The handle of the stream buffer to which data was + * written. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xStreamBufferSendCompletedFromISR(). If calling + * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \ingroup StreamBufferManagement + */ +//go:linkname XStreamBufferSendCompletedFromISR C.xStreamBufferSendCompletedFromISR +func XStreamBufferSendCompletedFromISR(xStreamBuffer StreamBufferHandleT, pxHigherPriorityTaskWoken *BaseTypeT) BaseTypeT + +/** + * + * For advanced users only. + * + * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is read out of a message buffer or stream buffer. If there was a task + * that was blocked on the message or stream buffer waiting for data to arrive + * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to + * remove it from the Blocked state. xStreamBufferReceiveCompletedFromISR() + * does the same thing. It is provided to enable application writers to + * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT + * ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xStreamBuffer The handle of the stream buffer from which data was + * read. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xStreamBufferReceiveCompletedFromISR(). If calling + * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \ingroup StreamBufferManagement + */ +//go:linkname XStreamBufferReceiveCompletedFromISR C.xStreamBufferReceiveCompletedFromISR +func XStreamBufferReceiveCompletedFromISR(xStreamBuffer StreamBufferHandleT, pxHigherPriorityTaskWoken *BaseTypeT) BaseTypeT + +/* Functions below here are not part of the public API. */ +//go:linkname XStreamBufferGenericCreate C.xStreamBufferGenericCreate +func XStreamBufferGenericCreate(xBufferSizeBytes c.SizeT, xTriggerLevelBytes c.SizeT, xIsMessageBuffer BaseTypeT, pxSendCompletedCallback StreamBufferCallbackFunctionT, pxReceiveCompletedCallback StreamBufferCallbackFunctionT) StreamBufferHandleT + +//go:linkname XStreamBufferGenericCreateStatic C.xStreamBufferGenericCreateStatic +func XStreamBufferGenericCreateStatic(xBufferSizeBytes c.SizeT, xTriggerLevelBytes c.SizeT, xIsMessageBuffer BaseTypeT, pucStreamBufferStorageArea *c.Uint8T, pxStaticStreamBuffer *StaticStreamBufferT, pxSendCompletedCallback StreamBufferCallbackFunctionT, pxReceiveCompletedCallback StreamBufferCallbackFunctionT) StreamBufferHandleT + +//go:linkname XStreamBufferNextMessageLengthBytes C.xStreamBufferNextMessageLengthBytes +func XStreamBufferNextMessageLengthBytes(xStreamBuffer StreamBufferHandleT) c.SizeT diff --git a/esp32/syscon_reg.go b/esp32/syscon_reg.go new file mode 100644 index 00000000..a38e4f73 --- /dev/null +++ b/esp32/syscon_reg.go @@ -0,0 +1,247 @@ +package freertos + +import _ "unsafe" + +const SYSCON_RST_TICK_CNT_V = 0x1 +const SYSCON_RST_TICK_CNT_S = 12 +const SYSCON_CLK_EN_V = 0x1 +const SYSCON_CLK_EN_S = 11 +const SYSCON_CLK_320M_EN_V = 0x1 +const SYSCON_CLK_320M_EN_S = 10 +const SYSCON_PRE_DIV_CNT = 0x000003FF +const SYSCON_PRE_DIV_CNT_V = 0x3FF +const SYSCON_PRE_DIV_CNT_S = 0 +const SYSCON_TICK_ENABLE_V = 0x1 +const SYSCON_TICK_ENABLE_S = 16 +const SYSCON_CK8M_TICK_NUM = 0x000000FF +const SYSCON_CK8M_TICK_NUM_V = 0xFF +const SYSCON_CK8M_TICK_NUM_S = 8 +const SYSCON_XTAL_TICK_NUM = 0x000000FF +const SYSCON_XTAL_TICK_NUM_V = 0xFF +const SYSCON_XTAL_TICK_NUM_S = 0 +const SYSCON_CLK_XTAL_OEN_V = 0x1 +const SYSCON_CLK_XTAL_OEN_S = 10 +const SYSCON_CLK40X_BB_OEN_V = 0x1 +const SYSCON_CLK40X_BB_OEN_S = 9 +const SYSCON_CLK_DAC_CPU_OEN_V = 0x1 +const SYSCON_CLK_DAC_CPU_OEN_S = 8 +const SYSCON_CLK_ADC_INF_OEN_V = 0x1 +const SYSCON_CLK_ADC_INF_OEN_S = 7 +const SYSCON_CLK_320M_OEN_V = 0x1 +const SYSCON_CLK_320M_OEN_S = 6 +const SYSCON_CLK160_OEN_V = 0x1 +const SYSCON_CLK160_OEN_S = 5 +const SYSCON_CLK80_OEN_V = 0x1 +const SYSCON_CLK80_OEN_S = 4 +const SYSCON_CLK_BB_OEN_V = 0x1 +const SYSCON_CLK_BB_OEN_S = 3 +const SYSCON_CLK44_OEN_V = 0x1 +const SYSCON_CLK44_OEN_S = 2 +const SYSCON_CLK22_OEN_V = 0x1 +const SYSCON_CLK22_OEN_S = 1 +const SYSCON_CLK20_OEN_V = 0x1 +const SYSCON_CLK20_OEN_S = 0 +const SYSCON_WIFI_BB_CFG = 0xFFFFFFFF +const SYSCON_WIFI_BB_CFG_V = 0xFFFFFFFF +const SYSCON_WIFI_BB_CFG_S = 0 +const SYSCON_WIFI_BB_CFG_2 = 0xFFFFFFFF +const SYSCON_WIFI_BB_CFG_2_V = 0xFFFFFFFF +const SYSCON_WIFI_BB_CFG_2_S = 0 +const SYSCON_WIFI_CLK_EN = 0xFFFFFFFF +const SYSCON_WIFI_CLK_EN_V = 0xFFFFFFFF +const SYSCON_WIFI_CLK_EN_S = 0 +const SYSCON_WIFI_RST = 0xFFFFFFFF +const SYSCON_WIFI_RST_V = 0xFFFFFFFF +const SYSCON_WIFI_RST_S = 0 +const SYSTEM_WIFI_CLK_EN = 0x00FB9FCF +const SYSTEM_WIFI_CLK_EN_V = 0x00FB9FCF +const SYSTEM_WIFI_CLK_EN_S = 0 +const SYSTEM_WIFI_CLK_WIFI_EN = 0x0 +const SYSTEM_WIFI_CLK_WIFI_EN_V = 0x0 +const SYSTEM_WIFI_CLK_WIFI_EN_S = 0 +const SYSTEM_WIFI_CLK_BT_EN = 0x0 +const SYSTEM_WIFI_CLK_BT_EN_V = 0x0 +const SYSTEM_WIFI_CLK_BT_EN_S = 0 +const SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M = 0x78078F +const SYSTEM_WIFI_RST = 0xFFFFFFFF +const SYSTEM_WIFI_RST_V = 0xFFFFFFFF +const SYSTEM_WIFI_RST_S = 0 +const SYSCON_PERI_IO_SWAP = 0x000000FF +const SYSCON_PERI_IO_SWAP_V = 0xFF +const SYSCON_PERI_IO_SWAP_S = 0 +const SYSCON_EXT_MEM_PMS_LOCK_V = 0x1 +const SYSCON_EXT_MEM_PMS_LOCK_S = 0 +const SYSCON_WRITEBACK_BYPASS_V = 0x1 +const SYSCON_WRITEBACK_BYPASS_S = 0 +const SYSCON_FLASH_ACE0_ATTR = 0x000001FF +const SYSCON_FLASH_ACE0_ATTR_V = 0x1FF +const SYSCON_FLASH_ACE0_ATTR_S = 0 +const SYSCON_FLASH_ACE1_ATTR = 0x000001FF +const SYSCON_FLASH_ACE1_ATTR_V = 0x1FF +const SYSCON_FLASH_ACE1_ATTR_S = 0 +const SYSCON_FLASH_ACE2_ATTR = 0x000001FF +const SYSCON_FLASH_ACE2_ATTR_V = 0x1FF +const SYSCON_FLASH_ACE2_ATTR_S = 0 +const SYSCON_FLASH_ACE3_ATTR = 0x000001FF +const SYSCON_FLASH_ACE3_ATTR_V = 0x1FF +const SYSCON_FLASH_ACE3_ATTR_S = 0 +const SYSCON_FLASH_ACE0_ADDR_S = 0xFFFFFFFF +const SYSCON_FLASH_ACE0_ADDR_S_V = 0xFFFFFFFF +const SYSCON_FLASH_ACE0_ADDR_S_S = 0 +const SYSCON_FLASH_ACE1_ADDR_S = 0xFFFFFFFF +const SYSCON_FLASH_ACE1_ADDR_S_V = 0xFFFFFFFF +const SYSCON_FLASH_ACE1_ADDR_S_S = 0 +const SYSCON_FLASH_ACE2_ADDR_S = 0xFFFFFFFF +const SYSCON_FLASH_ACE2_ADDR_S_V = 0xFFFFFFFF +const SYSCON_FLASH_ACE2_ADDR_S_S = 0 +const SYSCON_FLASH_ACE3_ADDR_S = 0xFFFFFFFF +const SYSCON_FLASH_ACE3_ADDR_S_V = 0xFFFFFFFF +const SYSCON_FLASH_ACE3_ADDR_S_S = 0 +const SYSCON_FLASH_ACE0_SIZE = 0x0000FFFF +const SYSCON_FLASH_ACE0_SIZE_V = 0xFFFF +const SYSCON_FLASH_ACE0_SIZE_S = 0 +const SYSCON_FLASH_ACE1_SIZE = 0x0000FFFF +const SYSCON_FLASH_ACE1_SIZE_V = 0xFFFF +const SYSCON_FLASH_ACE1_SIZE_S = 0 +const SYSCON_FLASH_ACE2_SIZE = 0x0000FFFF +const SYSCON_FLASH_ACE2_SIZE_V = 0xFFFF +const SYSCON_FLASH_ACE2_SIZE_S = 0 +const SYSCON_FLASH_ACE3_SIZE = 0x0000FFFF +const SYSCON_FLASH_ACE3_SIZE_V = 0xFFFF +const SYSCON_FLASH_ACE3_SIZE_S = 0 +const SYSCON_SRAM_ACE0_ATTR = 0x000001FF +const SYSCON_SRAM_ACE0_ATTR_V = 0x1FF +const SYSCON_SRAM_ACE0_ATTR_S = 0 +const SYSCON_SRAM_ACE1_ATTR = 0x000001FF +const SYSCON_SRAM_ACE1_ATTR_V = 0x1FF +const SYSCON_SRAM_ACE1_ATTR_S = 0 +const SYSCON_SRAM_ACE2_ATTR = 0x000001FF +const SYSCON_SRAM_ACE2_ATTR_V = 0x1FF +const SYSCON_SRAM_ACE2_ATTR_S = 0 +const SYSCON_SRAM_ACE3_ATTR = 0x000001FF +const SYSCON_SRAM_ACE3_ATTR_V = 0x1FF +const SYSCON_SRAM_ACE3_ATTR_S = 0 +const SYSCON_SRAM_ACE0_ADDR_S = 0xFFFFFFFF +const SYSCON_SRAM_ACE0_ADDR_S_V = 0xFFFFFFFF +const SYSCON_SRAM_ACE0_ADDR_S_S = 0 +const SYSCON_SRAM_ACE1_ADDR_S = 0xFFFFFFFF +const SYSCON_SRAM_ACE1_ADDR_S_V = 0xFFFFFFFF +const SYSCON_SRAM_ACE1_ADDR_S_S = 0 +const SYSCON_SRAM_ACE2_ADDR_S = 0xFFFFFFFF +const SYSCON_SRAM_ACE2_ADDR_S_V = 0xFFFFFFFF +const SYSCON_SRAM_ACE2_ADDR_S_S = 0 +const SYSCON_SRAM_ACE3_ADDR_S = 0xFFFFFFFF +const SYSCON_SRAM_ACE3_ADDR_S_V = 0xFFFFFFFF +const SYSCON_SRAM_ACE3_ADDR_S_S = 0 +const SYSCON_SRAM_ACE0_SIZE = 0x0000FFFF +const SYSCON_SRAM_ACE0_SIZE_V = 0xFFFF +const SYSCON_SRAM_ACE0_SIZE_S = 0 +const SYSCON_SRAM_ACE1_SIZE = 0x0000FFFF +const SYSCON_SRAM_ACE1_SIZE_V = 0xFFFF +const SYSCON_SRAM_ACE1_SIZE_S = 0 +const SYSCON_SRAM_ACE2_SIZE = 0x0000FFFF +const SYSCON_SRAM_ACE2_SIZE_V = 0xFFFF +const SYSCON_SRAM_ACE2_SIZE_S = 0 +const SYSCON_SRAM_ACE3_SIZE = 0x0000FFFF +const SYSCON_SRAM_ACE3_SIZE_V = 0xFFFF +const SYSCON_SRAM_ACE3_SIZE_S = 0 +const SYSCON_SPI_MEM_REJECT_CDE = 0x0000001F +const SYSCON_SPI_MEM_REJECT_CDE_V = 0x1F +const SYSCON_SPI_MEM_REJECT_CDE_S = 2 +const SYSCON_SPI_MEM_REJECT_CLR_V = 0x1 +const SYSCON_SPI_MEM_REJECT_CLR_S = 1 +const SYSCON_SPI_MEM_REJECT_INT_V = 0x1 +const SYSCON_SPI_MEM_REJECT_INT_S = 0 +const SYSCON_SPI_MEM_REJECT_ADDR = 0xFFFFFFFF +const SYSCON_SPI_MEM_REJECT_ADDR_V = 0xFFFFFFFF +const SYSCON_SPI_MEM_REJECT_ADDR_S = 0 +const SYSCON_SDIO_WIN_ACCESS_EN_V = 0x1 +const SYSCON_SDIO_WIN_ACCESS_EN_S = 0 +const SYSCON_REDCY_ANDOR_V = 0x1 +const SYSCON_REDCY_ANDOR_S = 31 +const SYSCON_REDCY_SIG0 = 0x7FFFFFFF +const SYSCON_REDCY_SIG0_V = 0x7FFFFFFF +const SYSCON_REDCY_SIG0_S = 0 +const SYSCON_REDCY_NANDOR_V = 0x1 +const SYSCON_REDCY_NANDOR_S = 31 +const SYSCON_REDCY_SIG1 = 0x7FFFFFFF +const SYSCON_REDCY_SIG1_V = 0x7FFFFFFF +const SYSCON_REDCY_SIG1_S = 0 +const SYSCON_FREQ_MEM_FORCE_PD_V = 0x1 +const SYSCON_FREQ_MEM_FORCE_PD_S = 7 +const SYSCON_FREQ_MEM_FORCE_PU_V = 0x1 +const SYSCON_FREQ_MEM_FORCE_PU_S = 6 +const SYSCON_DC_MEM_FORCE_PD_V = 0x1 +const SYSCON_DC_MEM_FORCE_PD_S = 5 +const SYSCON_DC_MEM_FORCE_PU_V = 0x1 +const SYSCON_DC_MEM_FORCE_PU_S = 4 +const SYSCON_PBUS_MEM_FORCE_PD_V = 0x1 +const SYSCON_PBUS_MEM_FORCE_PD_S = 3 +const SYSCON_PBUS_MEM_FORCE_PU_V = 0x1 +const SYSCON_PBUS_MEM_FORCE_PU_S = 2 +const SYSCON_AGC_MEM_FORCE_PD_V = 0x1 +const SYSCON_AGC_MEM_FORCE_PD_S = 1 +const SYSCON_AGC_MEM_FORCE_PU_V = 0x1 +const SYSCON_AGC_MEM_FORCE_PU_S = 0 +const SYSCON_SRAM_PAGE_SIZE = 0x00000003 +const SYSCON_SRAM_PAGE_SIZE_V = 0x3 +const SYSCON_SRAM_PAGE_SIZE_S = 20 +const SYSCON_FLASH_PAGE_SIZE = 0x00000003 +const SYSCON_FLASH_PAGE_SIZE_V = 0x3 +const SYSCON_FLASH_PAGE_SIZE_S = 18 +const SYSCON_SRAM_CLKGATE_FORCE_ON = 0x000007FF +const SYSCON_SRAM_CLKGATE_FORCE_ON_V = 0x7FF +const SYSCON_SRAM_CLKGATE_FORCE_ON_S = 3 +const SYSCON_ROM_CLKGATE_FORCE_ON = 0x00000007 +const SYSCON_ROM_CLKGATE_FORCE_ON_V = 0x7 +const SYSCON_ROM_CLKGATE_FORCE_ON_S = 0 +const SYSCON_SRAM_POWER_DOWN = 0x000007FF +const SYSCON_SRAM_POWER_DOWN_V = 0x7FF +const SYSCON_SRAM_POWER_DOWN_S = 3 +const SYSCON_ROM_POWER_DOWN = 0x00000007 +const SYSCON_ROM_POWER_DOWN_V = 0x7 +const SYSCON_ROM_POWER_DOWN_S = 0 +const SYSCON_SRAM_POWER_UP = 0x000007FF +const SYSCON_SRAM_POWER_UP_V = 0x7FF +const SYSCON_SRAM_POWER_UP_S = 3 +const SYSCON_ROM_POWER_UP = 0x00000007 +const SYSCON_ROM_POWER_UP_V = 0x7 +const SYSCON_ROM_POWER_UP_S = 0 +const SYSCON_NOBYPASS_CPU_ISO_RST_V = 0x1 +const SYSCON_NOBYPASS_CPU_ISO_RST_S = 27 +const SYSCON_RETENTION_CPU_LINK_ADDR = 0x07FFFFFF +const SYSCON_RETENTION_CPU_LINK_ADDR_V = 0x7FFFFFF +const SYSCON_RETENTION_CPU_LINK_ADDR_S = 0 +const SYSCON_RETENTION_TAG_LINK_ADDR = 0x07FFFFFF +const SYSCON_RETENTION_TAG_LINK_ADDR_V = 0x7FFFFFF +const SYSCON_RETENTION_TAG_LINK_ADDR_S = 0 +const SYSCON_RET_ICACHE_ENABLE_V = 0x1 +const SYSCON_RET_ICACHE_ENABLE_S = 31 +const SYSCON_RET_ICACHE_START_POINT = 0x000000FF +const SYSCON_RET_ICACHE_START_POINT_V = 0xFF +const SYSCON_RET_ICACHE_START_POINT_S = 22 +const SYSCON_RET_ICACHE_VLD_SIZE = 0x000000FF +const SYSCON_RET_ICACHE_VLD_SIZE_V = 0xFF +const SYSCON_RET_ICACHE_VLD_SIZE_S = 13 +const SYSCON_RET_ICACHE_SIZE = 0x000000FF +const SYSCON_RET_ICACHE_SIZE_V = 0xFF +const SYSCON_RET_ICACHE_SIZE_S = 4 +const SYSCON_RET_DCACHE_ENABLE_V = 0x1 +const SYSCON_RET_DCACHE_ENABLE_S = 31 +const SYSCON_RET_DCACHE_START_POINT = 0x000001FF +const SYSCON_RET_DCACHE_START_POINT_V = 0x1FF +const SYSCON_RET_DCACHE_START_POINT_S = 22 +const SYSCON_RET_DCACHE_VLD_SIZE = 0x000001FF +const SYSCON_RET_DCACHE_VLD_SIZE_V = 0x1FF +const SYSCON_RET_DCACHE_VLD_SIZE_S = 13 +const SYSCON_RET_DCACHE_SIZE = 0x000001FF +const SYSCON_RET_DCACHE_SIZE_V = 0x1FF +const SYSCON_RET_DCACHE_SIZE_S = 4 +const SYSCON_RETENTION_INV_CFG = 0xFFFFFFFF +const SYSCON_RETENTION_INV_CFG_V = 0xFFFFFFFF +const SYSCON_RETENTION_INV_CFG_S = 0 +const SYSCON_RETENTION_DISABLE_V = 0x1 +const SYSCON_RETENTION_DISABLE_S = 0 +const SYSCON_DATE = 0xFFFFFFFF +const SYSCON_DATE_V = 0xFFFFFFFF +const SYSCON_DATE_S = 0 diff --git a/esp32/syscon_struct.go b/esp32/syscon_struct.go new file mode 100644 index 00000000..21c48a79 --- /dev/null +++ b/esp32/syscon_struct.go @@ -0,0 +1,338 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type SysconDevS struct { + ClkConf struct { + Val c.Uint32T + } + TickConf struct { + Val c.Uint32T + } + ClkOutEn struct { + Val c.Uint32T + } + WifiBbCfg c.Uint32T + WifiBbCfg2 c.Uint32T + WifiClkEn c.Uint32T + WifiRstEn c.Uint32T + HostInfSel struct { + Val c.Uint32T + } + ExtMemPmsLock struct { + Val c.Uint32T + } + ExtMemWritebackBypass struct { + Val c.Uint32T + } + FlashAce0Attr struct { + Val c.Uint32T + } + FlashAce1Attr struct { + Val c.Uint32T + } + FlashAce2Attr struct { + Val c.Uint32T + } + FlashAce3Attr struct { + Val c.Uint32T + } + FlashAce0Addr c.Uint32T + FlashAce1Addr c.Uint32T + FlashAce2Addr c.Uint32T + FlashAce3Addr c.Uint32T + FlashAce0Size struct { + Val c.Uint32T + } + FlashAce1Size struct { + Val c.Uint32T + } + FlashAce2Size struct { + Val c.Uint32T + } + FlashAce3Size struct { + Val c.Uint32T + } + SramAce0Attr struct { + Val c.Uint32T + } + SramAce1Attr struct { + Val c.Uint32T + } + SramAce2Attr struct { + Val c.Uint32T + } + SramAce3Attr struct { + Val c.Uint32T + } + SramAce0Addr c.Uint32T + SramAce1Addr c.Uint32T + SramAce2Addr c.Uint32T + SramAce3Addr c.Uint32T + SramAce0Size struct { + Val c.Uint32T + } + SramAce1Size struct { + Val c.Uint32T + } + SramAce2Size struct { + Val c.Uint32T + } + SramAce3Size struct { + Val c.Uint32T + } + SpiMemPmsCtrl struct { + Val c.Uint32T + } + SpiMemRejectAddr c.Uint32T + SdioCtrl struct { + Val c.Uint32T + } + RedcySig0 struct { + Val c.Uint32T + } + RedcySig1 struct { + Val c.Uint32T + } + FrontEndMemPd struct { + Val c.Uint32T + } + SpiMemEccCtrl struct { + Val c.Uint32T + } + ReservedA4 c.Uint32T + ClkgateForceOn struct { + Val c.Uint32T + } + MemPowerDown struct { + Val c.Uint32T + } + MemPowerUp struct { + Val c.Uint32T + } + RetentionCtrl struct { + Val c.Uint32T + } + RetentionCtrl1 struct { + Val c.Uint32T + } + RetentionCtrl2 struct { + Val c.Uint32T + } + RetentionCtrl3 struct { + Val c.Uint32T + } + RetentionCtrl4 c.Uint32T + RetentionCtrl5 struct { + Val c.Uint32T + } + ReservedCc c.Uint32T + ReservedD0 c.Uint32T + ReservedD4 c.Uint32T + ReservedD8 c.Uint32T + ReservedDc c.Uint32T + ReservedE0 c.Uint32T + ReservedE4 c.Uint32T + ReservedE8 c.Uint32T + ReservedEc c.Uint32T + ReservedF0 c.Uint32T + ReservedF4 c.Uint32T + ReservedF8 c.Uint32T + ReservedFc c.Uint32T + Reserved100 c.Uint32T + Reserved104 c.Uint32T + Reserved108 c.Uint32T + Reserved10c c.Uint32T + Reserved110 c.Uint32T + Reserved114 c.Uint32T + Reserved118 c.Uint32T + Reserved11c c.Uint32T + Reserved120 c.Uint32T + Reserved124 c.Uint32T + Reserved128 c.Uint32T + Reserved12c c.Uint32T + Reserved130 c.Uint32T + Reserved134 c.Uint32T + Reserved138 c.Uint32T + Reserved13c c.Uint32T + Reserved140 c.Uint32T + Reserved144 c.Uint32T + Reserved148 c.Uint32T + Reserved14c c.Uint32T + Reserved150 c.Uint32T + Reserved154 c.Uint32T + Reserved158 c.Uint32T + Reserved15c c.Uint32T + Reserved160 c.Uint32T + Reserved164 c.Uint32T + Reserved168 c.Uint32T + Reserved16c c.Uint32T + Reserved170 c.Uint32T + Reserved174 c.Uint32T + Reserved178 c.Uint32T + Reserved17c c.Uint32T + Reserved180 c.Uint32T + Reserved184 c.Uint32T + Reserved188 c.Uint32T + Reserved18c c.Uint32T + Reserved190 c.Uint32T + Reserved194 c.Uint32T + Reserved198 c.Uint32T + Reserved19c c.Uint32T + Reserved1a0 c.Uint32T + Reserved1a4 c.Uint32T + Reserved1a8 c.Uint32T + Reserved1ac c.Uint32T + Reserved1b0 c.Uint32T + Reserved1b4 c.Uint32T + Reserved1b8 c.Uint32T + Reserved1bc c.Uint32T + Reserved1c0 c.Uint32T + Reserved1c4 c.Uint32T + Reserved1c8 c.Uint32T + Reserved1cc c.Uint32T + Reserved1d0 c.Uint32T + Reserved1d4 c.Uint32T + Reserved1d8 c.Uint32T + Reserved1dc c.Uint32T + Reserved1e0 c.Uint32T + Reserved1e4 c.Uint32T + Reserved1e8 c.Uint32T + Reserved1ec c.Uint32T + Reserved1f0 c.Uint32T + Reserved1f4 c.Uint32T + Reserved1f8 c.Uint32T + Reserved1fc c.Uint32T + Reserved200 c.Uint32T + Reserved204 c.Uint32T + Reserved208 c.Uint32T + Reserved20c c.Uint32T + Reserved210 c.Uint32T + Reserved214 c.Uint32T + Reserved218 c.Uint32T + Reserved21c c.Uint32T + Reserved220 c.Uint32T + Reserved224 c.Uint32T + Reserved228 c.Uint32T + Reserved22c c.Uint32T + Reserved230 c.Uint32T + Reserved234 c.Uint32T + Reserved238 c.Uint32T + Reserved23c c.Uint32T + Reserved240 c.Uint32T + Reserved244 c.Uint32T + Reserved248 c.Uint32T + Reserved24c c.Uint32T + Reserved250 c.Uint32T + Reserved254 c.Uint32T + Reserved258 c.Uint32T + Reserved25c c.Uint32T + Reserved260 c.Uint32T + Reserved264 c.Uint32T + Reserved268 c.Uint32T + Reserved26c c.Uint32T + Reserved270 c.Uint32T + Reserved274 c.Uint32T + Reserved278 c.Uint32T + Reserved27c c.Uint32T + Reserved280 c.Uint32T + Reserved284 c.Uint32T + Reserved288 c.Uint32T + Reserved28c c.Uint32T + Reserved290 c.Uint32T + Reserved294 c.Uint32T + Reserved298 c.Uint32T + Reserved29c c.Uint32T + Reserved2a0 c.Uint32T + Reserved2a4 c.Uint32T + Reserved2a8 c.Uint32T + Reserved2ac c.Uint32T + Reserved2b0 c.Uint32T + Reserved2b4 c.Uint32T + Reserved2b8 c.Uint32T + Reserved2bc c.Uint32T + Reserved2c0 c.Uint32T + Reserved2c4 c.Uint32T + Reserved2c8 c.Uint32T + Reserved2cc c.Uint32T + Reserved2d0 c.Uint32T + Reserved2d4 c.Uint32T + Reserved2d8 c.Uint32T + Reserved2dc c.Uint32T + Reserved2e0 c.Uint32T + Reserved2e4 c.Uint32T + Reserved2e8 c.Uint32T + Reserved2ec c.Uint32T + Reserved2f0 c.Uint32T + Reserved2f4 c.Uint32T + Reserved2f8 c.Uint32T + Reserved2fc c.Uint32T + Reserved300 c.Uint32T + Reserved304 c.Uint32T + Reserved308 c.Uint32T + Reserved30c c.Uint32T + Reserved310 c.Uint32T + Reserved314 c.Uint32T + Reserved318 c.Uint32T + Reserved31c c.Uint32T + Reserved320 c.Uint32T + Reserved324 c.Uint32T + Reserved328 c.Uint32T + Reserved32c c.Uint32T + Reserved330 c.Uint32T + Reserved334 c.Uint32T + Reserved338 c.Uint32T + Reserved33c c.Uint32T + Reserved340 c.Uint32T + Reserved344 c.Uint32T + Reserved348 c.Uint32T + Reserved34c c.Uint32T + Reserved350 c.Uint32T + Reserved354 c.Uint32T + Reserved358 c.Uint32T + Reserved35c c.Uint32T + Reserved360 c.Uint32T + Reserved364 c.Uint32T + Reserved368 c.Uint32T + Reserved36c c.Uint32T + Reserved370 c.Uint32T + Reserved374 c.Uint32T + Reserved378 c.Uint32T + Reserved37c c.Uint32T + Reserved380 c.Uint32T + Reserved384 c.Uint32T + Reserved388 c.Uint32T + Reserved38c c.Uint32T + Reserved390 c.Uint32T + Reserved394 c.Uint32T + Reserved398 c.Uint32T + Reserved39c c.Uint32T + Reserved3a0 c.Uint32T + Reserved3a4 c.Uint32T + Reserved3a8 c.Uint32T + Reserved3ac c.Uint32T + Reserved3b0 c.Uint32T + Reserved3b4 c.Uint32T + Reserved3b8 c.Uint32T + Reserved3bc c.Uint32T + Reserved3c0 c.Uint32T + Reserved3c4 c.Uint32T + Reserved3c8 c.Uint32T + Reserved3cc c.Uint32T + Reserved3d0 c.Uint32T + Reserved3d4 c.Uint32T + Reserved3d8 c.Uint32T + Reserved3dc c.Uint32T + Reserved3e0 c.Uint32T + Reserved3e4 c.Uint32T + Reserved3e8 c.Uint32T + Reserved3ec c.Uint32T + Reserved3f0 c.Uint32T + Reserved3f4 c.Uint32T + Reserved3f8 c.Uint32T + Date c.Uint32T +} +type SysconDevT SysconDevS diff --git a/esp32/system.go b/esp32/system.go new file mode 100644 index 00000000..8570be95 --- /dev/null +++ b/esp32/system.go @@ -0,0 +1,85 @@ +package freertos + +import _ "unsafe" + +const XSHAL_USE_ABSOLUTE_LITERALS = 0 +const XSHAL_HAVE_TEXT_SECTION_LITERALS = 1 +const XTHAL_ABI_WINDOWED = 0 +const XTHAL_ABI_CALL0 = 1 +const XTHAL_CLIB_NEWLIB = 0 +const XTHAL_CLIB_UCLIBC = 1 +const XTHAL_CLIB_XCLIB = 2 +const XSHAL_USE_FLOATING_POINT = 1 +const XSHAL_FLOATING_POINT_ABI = 0 +const XSHAL_FUNC_SAFETY_ENABLED = 0 +const XSHAL_IOBLOCK_CACHED_VADDR = 0x70000000 +const XSHAL_IOBLOCK_CACHED_PADDR = 0x70000000 +const XSHAL_IOBLOCK_CACHED_SIZE = 0x0E000000 +const XSHAL_IOBLOCK_BYPASS_VADDR = 0x90000000 +const XSHAL_IOBLOCK_BYPASS_PADDR = 0x90000000 +const XSHAL_IOBLOCK_BYPASS_SIZE = 0x0E000000 +const XSHAL_ROM_VADDR = 0x50000000 +const XSHAL_ROM_PADDR = 0x50000000 +const XSHAL_ROM_SIZE = 0x01000000 +const XSHAL_ROM_AVAIL_VADDR = 0x50000000 +const XSHAL_ROM_AVAIL_VSIZE = 0x01000000 +const XSHAL_RAM_VADDR = 0x60000000 +const XSHAL_RAM_PADDR = 0x60000000 +const XSHAL_RAM_VSIZE = 0x20000000 +const XSHAL_RAM_PSIZE = 0x20000000 +const XSHAL_RAM_AVAIL_VADDR = 0x60000000 +const XSHAL_RAM_AVAIL_VSIZE = 0x20000000 +const XSHAL_RAM_BYPASS_VADDR = 0xA0000000 +const XSHAL_RAM_BYPASS_PADDR = 0xA0000000 +const XSHAL_RAM_BYPASS_PSIZE = 0x20000000 +const XSHAL_SIMIO_CACHED_VADDR = 0xC0000000 +const XSHAL_SIMIO_BYPASS_VADDR = 0xC0000000 +const XSHAL_SIMIO_PADDR = 0xC0000000 +const XSHAL_SIMIO_SIZE = 0x20000000 +const XSHAL_MAGIC_EXIT = 0x0 +const XSHAL_ALLVALID_CACHEATTR_WRITEBACK = 0x22221112 +const XSHAL_ALLVALID_CACHEATTR_WRITEALLOC = 0x22221112 +const XSHAL_ALLVALID_CACHEATTR_WRITETHRU = 0x22221112 +const XSHAL_ALLVALID_CACHEATTR_BYPASS = 0x22222222 +const XSHAL_STRICT_CACHEATTR_WRITEBACK = 0xFFFF111F +const XSHAL_STRICT_CACHEATTR_WRITEALLOC = 0xFFFF111F +const XSHAL_STRICT_CACHEATTR_WRITETHRU = 0xFFFF111F +const XSHAL_STRICT_CACHEATTR_BYPASS = 0xFFFF222F +const XSHAL_TRAPNULL_CACHEATTR_WRITEBACK = 0x2222111F +const XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC = 0x2222111F +const XSHAL_TRAPNULL_CACHEATTR_WRITETHRU = 0x2222111F +const XSHAL_TRAPNULL_CACHEATTR_BYPASS = 0x2222222F +const XSHAL_ISS_PIPE_REGIONS = 0 +const XSHAL_ISS_SDRAM_REGIONS = 0 +const XSHAL_XT2000_CACHEATTR_WRITEBACK = 0xFF22111F +const XSHAL_XT2000_CACHEATTR_WRITEALLOC = 0xFF22111F +const XSHAL_XT2000_CACHEATTR_WRITETHRU = 0xFF22111F +const XSHAL_XT2000_CACHEATTR_BYPASS = 0xFF22222F +const XSHAL_XT2000_PIPE_REGIONS = 0x00000000 +const XSHAL_XT2000_SDRAM_REGIONS = 0x00000440 +const XSHAL_VECTORS_PACKED = 0 +const XSHAL_STATIC_VECTOR_SELECT = 1 +const XSHAL_RESET_VECTOR_VADDR = 0x40000400 +const XSHAL_RESET_VECTOR_PADDR = 0x40000400 +const XSHAL_RESET_VECTOR_SIZE = 0x00000300 +const XSHAL_RESET_VECTOR_ISROM = 0 +const XSHAL_USER_VECTOR_SIZE = 0x00000038 +const XSHAL_USER_VECTOR_ISROM = 0 +const XSHAL_KERNEL_VECTOR_SIZE = 0x00000038 +const XSHAL_KERNEL_VECTOR_ISROM = 0 +const XSHAL_DOUBLEEXC_VECTOR_SIZE = 0x00000040 +const XSHAL_DOUBLEEXC_VECTOR_ISROM = 0 +const XSHAL_WINDOW_VECTORS_SIZE = 0x00000178 +const XSHAL_WINDOW_VECTORS_ISROM = 0 +const XSHAL_INTLEVEL2_VECTOR_SIZE = 0x00000038 +const XSHAL_INTLEVEL2_VECTOR_ISROM = 0 +const XSHAL_INTLEVEL3_VECTOR_SIZE = 0x00000038 +const XSHAL_INTLEVEL3_VECTOR_ISROM = 0 +const XSHAL_INTLEVEL4_VECTOR_SIZE = 0x00000038 +const XSHAL_INTLEVEL4_VECTOR_ISROM = 0 +const XSHAL_INTLEVEL5_VECTOR_SIZE = 0x00000038 +const XSHAL_INTLEVEL5_VECTOR_ISROM = 0 +const XSHAL_INTLEVEL6_VECTOR_SIZE = 0x00000038 +const XSHAL_INTLEVEL6_VECTOR_ISROM = 0 +const XSHAL_NMI_VECTOR_SIZE = 0x00000038 +const XSHAL_NMI_VECTOR_ISROM = 0 diff --git a/esp32/system_internal.go b/esp32/system_internal.go new file mode 100644 index 00000000..70bfe6f7 --- /dev/null +++ b/esp32/system_internal.go @@ -0,0 +1,78 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Internal function to restart PRO and APP CPUs. + * + * @note This function should not be called from FreeRTOS applications. + * Use esp_restart instead. + * + * This function executes a CPU reset (see TRM). + * + * CPU resets do not reset digital peripherals, but this function will + * manually reset a subset of digital peripherals (depending on target) before + * carrying out the CPU reset. + * + * Memory protection is also cleared by a CPU reset. + * + * This is an internal function called by esp_restart. It is called directly + * by the panic handler and brownout detector interrupt. + */ +//go:linkname EspRestartNoos C.esp_restart_noos +func EspRestartNoos() + +/** + * @brief Similar to esp_restart_noos, but resets all the digital peripherals. + */ +//go:linkname EspRestartNoosDig C.esp_restart_noos_dig +func EspRestartNoosDig() + +/** + * @brief Internal function to set reset reason hint + * + * The hint is used do distinguish different reset reasons when software reset + * is performed. + * + * The hint is stored in RTC store register, RTC_RESET_CAUSE_REG. + * + * @param hint Desired esp_reset_reason_t value for the real reset reason + */ +// llgo:link EspResetReasonT.EspResetReasonSetHint C.esp_reset_reason_set_hint +func (recv_ EspResetReasonT) EspResetReasonSetHint() { +} + +/** + * @brief Internal function to get the reset hint value + * @return - Reset hint value previously stored into RTC_RESET_CAUSE_REG using + * esp_reset_reason_set_hint function + * - ESP_RST_UNKNOWN if the value in RTC_RESET_CAUSE_REG is invalid + */ +//go:linkname EspResetReasonGetHint C.esp_reset_reason_get_hint +func EspResetReasonGetHint() EspResetReasonT + +/** + * @brief Get the time in microseconds since startup + * + * @returns time since g_startup_time; definition should be fixed by system time provider + * no matter the underlying timer used. + */ +//go:linkname EspSystemGetTime C.esp_system_get_time +func EspSystemGetTime() c.Int64T + +/** + * @brief Get the resolution of the time returned by `esp_system_get_time`. + * + * @returns the resolution in nanoseconds + */ +//go:linkname EspSystemGetTimeResolution C.esp_system_get_time_resolution +func EspSystemGetTimeResolution() c.Uint32T + +/** + * @brief Before the system exit (e.g. panic, brownout, restart, etc.), this function is to be called to reset all necessary peripherals. + */ +//go:linkname EspSystemResetModulesOnExit C.esp_system_reset_modules_on_exit +func EspSystemResetModulesOnExit() diff --git a/esp32/system_reg.go b/esp32/system_reg.go new file mode 100644 index 00000000..4b4ea8a1 --- /dev/null +++ b/esp32/system_reg.go @@ -0,0 +1,361 @@ +package freertos + +import _ "unsafe" + +const SYSTEM_CONTROL_CORE_1_RESETING_V = 0x1 +const SYSTEM_CONTROL_CORE_1_RESETING_S = 2 +const SYSTEM_CONTROL_CORE_1_CLKGATE_EN_V = 0x1 +const SYSTEM_CONTROL_CORE_1_CLKGATE_EN_S = 1 +const SYSTEM_CONTROL_CORE_1_RUNSTALL_V = 0x1 +const SYSTEM_CONTROL_CORE_1_RUNSTALL_S = 0 +const SYSTEM_CONTROL_CORE_1_MESSAGE = 0xFFFFFFFF +const SYSTEM_CONTROL_CORE_1_MESSAGE_V = 0xFFFFFFFF +const SYSTEM_CONTROL_CORE_1_MESSAGE_S = 0 +const SYSTEM_CLK_EN_DEDICATED_GPIO_V = 0x1 +const SYSTEM_CLK_EN_DEDICATED_GPIO_S = 7 +const SYSTEM_CLK_EN_ASSIST_DEBUG_V = 0x1 +const SYSTEM_CLK_EN_ASSIST_DEBUG_S = 6 +const SYSTEM_RST_EN_DEDICATED_GPIO_V = 0x1 +const SYSTEM_RST_EN_DEDICATED_GPIO_S = 7 +const SYSTEM_RST_EN_ASSIST_DEBUG_V = 0x1 +const SYSTEM_RST_EN_ASSIST_DEBUG_S = 6 +const SYSTEM_CPU_WAITI_DELAY_NUM = 0x0000000F +const SYSTEM_CPU_WAITI_DELAY_NUM_V = 0xF +const SYSTEM_CPU_WAITI_DELAY_NUM_S = 4 +const SYSTEM_CPU_WAIT_MODE_FORCE_ON_V = 0x1 +const SYSTEM_CPU_WAIT_MODE_FORCE_ON_S = 3 +const SYSTEM_PLL_FREQ_SEL_V = 0x1 +const SYSTEM_PLL_FREQ_SEL_S = 2 +const SYSTEM_CPUPERIOD_SEL = 0x00000003 +const SYSTEM_CPUPERIOD_SEL_V = 0x3 +const SYSTEM_CPUPERIOD_SEL_S = 0 +const SYSTEM_LSLP_MEM_PD_MASK_V = 0x1 +const SYSTEM_LSLP_MEM_PD_MASK_S = 0 +const SYSTEM_SPI4_CLK_EN_V = 0x1 +const SYSTEM_SPI4_CLK_EN_S = 31 +const SYSTEM_ADC2_ARB_CLK_EN_V = 0x1 +const SYSTEM_ADC2_ARB_CLK_EN_S = 30 +const SYSTEM_SYSTIMER_CLK_EN_V = 0x1 +const SYSTEM_SYSTIMER_CLK_EN_S = 29 +const SYSTEM_APB_SARADC_CLK_EN_V = 0x1 +const SYSTEM_APB_SARADC_CLK_EN_S = 28 +const SYSTEM_SPI3_DMA_CLK_EN_V = 0x1 +const SYSTEM_SPI3_DMA_CLK_EN_S = 27 +const SYSTEM_PWM3_CLK_EN_V = 0x1 +const SYSTEM_PWM3_CLK_EN_S = 26 +const SYSTEM_PWM2_CLK_EN_V = 0x1 +const SYSTEM_PWM2_CLK_EN_S = 25 +const SYSTEM_UART_MEM_CLK_EN_V = 0x1 +const SYSTEM_UART_MEM_CLK_EN_S = 24 +const SYSTEM_USB_CLK_EN_V = 0x1 +const SYSTEM_USB_CLK_EN_S = 23 +const SYSTEM_SPI2_DMA_CLK_EN_V = 0x1 +const SYSTEM_SPI2_DMA_CLK_EN_S = 22 +const SYSTEM_I2S1_CLK_EN_V = 0x1 +const SYSTEM_I2S1_CLK_EN_S = 21 +const SYSTEM_PWM1_CLK_EN_V = 0x1 +const SYSTEM_PWM1_CLK_EN_S = 20 +const SYSTEM_TWAI_CLK_EN_V = 0x1 +const SYSTEM_TWAI_CLK_EN_S = 19 +const SYSTEM_I2C_EXT1_CLK_EN_V = 0x1 +const SYSTEM_I2C_EXT1_CLK_EN_S = 18 +const SYSTEM_PWM0_CLK_EN_V = 0x1 +const SYSTEM_PWM0_CLK_EN_S = 17 +const SYSTEM_SPI3_CLK_EN_V = 0x1 +const SYSTEM_SPI3_CLK_EN_S = 16 +const SYSTEM_TIMERGROUP1_CLK_EN_V = 0x1 +const SYSTEM_TIMERGROUP1_CLK_EN_S = 15 +const SYSTEM_EFUSE_CLK_EN_V = 0x1 +const SYSTEM_EFUSE_CLK_EN_S = 14 +const SYSTEM_TIMERGROUP_CLK_EN_V = 0x1 +const SYSTEM_TIMERGROUP_CLK_EN_S = 13 +const SYSTEM_UHCI1_CLK_EN_V = 0x1 +const SYSTEM_UHCI1_CLK_EN_S = 12 +const SYSTEM_LEDC_CLK_EN_V = 0x1 +const SYSTEM_LEDC_CLK_EN_S = 11 +const SYSTEM_PCNT_CLK_EN_V = 0x1 +const SYSTEM_PCNT_CLK_EN_S = 10 +const SYSTEM_RMT_CLK_EN_V = 0x1 +const SYSTEM_RMT_CLK_EN_S = 9 +const SYSTEM_UHCI0_CLK_EN_V = 0x1 +const SYSTEM_UHCI0_CLK_EN_S = 8 +const SYSTEM_I2C_EXT0_CLK_EN_V = 0x1 +const SYSTEM_I2C_EXT0_CLK_EN_S = 7 +const SYSTEM_SPI2_CLK_EN_V = 0x1 +const SYSTEM_SPI2_CLK_EN_S = 6 +const SYSTEM_UART1_CLK_EN_V = 0x1 +const SYSTEM_UART1_CLK_EN_S = 5 +const SYSTEM_I2S0_CLK_EN_V = 0x1 +const SYSTEM_I2S0_CLK_EN_S = 4 +const SYSTEM_WDG_CLK_EN_V = 0x1 +const SYSTEM_WDG_CLK_EN_S = 3 +const SYSTEM_UART_CLK_EN_V = 0x1 +const SYSTEM_UART_CLK_EN_S = 2 +const SYSTEM_SPI01_CLK_EN_V = 0x1 +const SYSTEM_SPI01_CLK_EN_S = 1 +const SYSTEM_TIMERS_CLK_EN_V = 0x1 +const SYSTEM_TIMERS_CLK_EN_S = 0 +const SYSTEM_USB_DEVICE_CLK_EN_V = 0x1 +const SYSTEM_USB_DEVICE_CLK_EN_S = 10 +const SYSTEM_UART2_CLK_EN_V = 0x1 +const SYSTEM_UART2_CLK_EN_S = 9 +const SYSTEM_LCD_CAM_CLK_EN_V = 0x1 +const SYSTEM_LCD_CAM_CLK_EN_S = 8 +const SYSTEM_SDIO_HOST_CLK_EN_V = 0x1 +const SYSTEM_SDIO_HOST_CLK_EN_S = 7 +const SYSTEM_DMA_CLK_EN_V = 0x1 +const SYSTEM_DMA_CLK_EN_S = 6 +const SYSTEM_CRYPTO_HMAC_CLK_EN_V = 0x1 +const SYSTEM_CRYPTO_HMAC_CLK_EN_S = 5 +const SYSTEM_CRYPTO_DS_CLK_EN_V = 0x1 +const SYSTEM_CRYPTO_DS_CLK_EN_S = 4 +const SYSTEM_CRYPTO_RSA_CLK_EN_V = 0x1 +const SYSTEM_CRYPTO_RSA_CLK_EN_S = 3 +const SYSTEM_CRYPTO_SHA_CLK_EN_V = 0x1 +const SYSTEM_CRYPTO_SHA_CLK_EN_S = 2 +const SYSTEM_CRYPTO_AES_CLK_EN_V = 0x1 +const SYSTEM_CRYPTO_AES_CLK_EN_S = 1 +const SYSTEM_PERI_BACKUP_CLK_EN_V = 0x1 +const SYSTEM_PERI_BACKUP_CLK_EN_S = 0 +const SYSTEM_SPI4_RST_V = 0x1 +const SYSTEM_SPI4_RST_S = 31 +const SYSTEM_ADC2_ARB_RST_V = 0x1 +const SYSTEM_ADC2_ARB_RST_S = 30 +const SYSTEM_SYSTIMER_RST_V = 0x1 +const SYSTEM_SYSTIMER_RST_S = 29 +const SYSTEM_APB_SARADC_RST_V = 0x1 +const SYSTEM_APB_SARADC_RST_S = 28 +const SYSTEM_SPI3_DMA_RST_V = 0x1 +const SYSTEM_SPI3_DMA_RST_S = 27 +const SYSTEM_PWM3_RST_V = 0x1 +const SYSTEM_PWM3_RST_S = 26 +const SYSTEM_PWM2_RST_V = 0x1 +const SYSTEM_PWM2_RST_S = 25 +const SYSTEM_UART_MEM_RST_V = 0x1 +const SYSTEM_UART_MEM_RST_S = 24 +const SYSTEM_USB_RST_V = 0x1 +const SYSTEM_USB_RST_S = 23 +const SYSTEM_SPI2_DMA_RST_V = 0x1 +const SYSTEM_SPI2_DMA_RST_S = 22 +const SYSTEM_I2S1_RST_V = 0x1 +const SYSTEM_I2S1_RST_S = 21 +const SYSTEM_PWM1_RST_V = 0x1 +const SYSTEM_PWM1_RST_S = 20 +const SYSTEM_TWAI_RST_V = 0x1 +const SYSTEM_TWAI_RST_S = 19 +const SYSTEM_I2C_EXT1_RST_V = 0x1 +const SYSTEM_I2C_EXT1_RST_S = 18 +const SYSTEM_PWM0_RST_V = 0x1 +const SYSTEM_PWM0_RST_S = 17 +const SYSTEM_SPI3_RST_V = 0x1 +const SYSTEM_SPI3_RST_S = 16 +const SYSTEM_TIMERGROUP1_RST_V = 0x1 +const SYSTEM_TIMERGROUP1_RST_S = 15 +const SYSTEM_EFUSE_RST_V = 0x1 +const SYSTEM_EFUSE_RST_S = 14 +const SYSTEM_TIMERGROUP_RST_V = 0x1 +const SYSTEM_TIMERGROUP_RST_S = 13 +const SYSTEM_UHCI1_RST_V = 0x1 +const SYSTEM_UHCI1_RST_S = 12 +const SYSTEM_LEDC_RST_V = 0x1 +const SYSTEM_LEDC_RST_S = 11 +const SYSTEM_PCNT_RST_V = 0x1 +const SYSTEM_PCNT_RST_S = 10 +const SYSTEM_RMT_RST_V = 0x1 +const SYSTEM_RMT_RST_S = 9 +const SYSTEM_UHCI0_RST_V = 0x1 +const SYSTEM_UHCI0_RST_S = 8 +const SYSTEM_I2C_EXT0_RST_V = 0x1 +const SYSTEM_I2C_EXT0_RST_S = 7 +const SYSTEM_SPI2_RST_V = 0x1 +const SYSTEM_SPI2_RST_S = 6 +const SYSTEM_UART1_RST_V = 0x1 +const SYSTEM_UART1_RST_S = 5 +const SYSTEM_I2S0_RST_V = 0x1 +const SYSTEM_I2S0_RST_S = 4 +const SYSTEM_WDG_RST_V = 0x1 +const SYSTEM_WDG_RST_S = 3 +const SYSTEM_UART_RST_V = 0x1 +const SYSTEM_UART_RST_S = 2 +const SYSTEM_SPI01_RST_V = 0x1 +const SYSTEM_SPI01_RST_S = 1 +const SYSTEM_TIMERS_RST_V = 0x1 +const SYSTEM_TIMERS_RST_S = 0 +const SYSTEM_USB_DEVICE_RST_V = 0x1 +const SYSTEM_USB_DEVICE_RST_S = 10 +const SYSTEM_UART2_RST_V = 0x1 +const SYSTEM_UART2_RST_S = 9 +const SYSTEM_LCD_CAM_RST_V = 0x1 +const SYSTEM_LCD_CAM_RST_S = 8 +const SYSTEM_SDIO_HOST_RST_V = 0x1 +const SYSTEM_SDIO_HOST_RST_S = 7 +const SYSTEM_DMA_RST_V = 0x1 +const SYSTEM_DMA_RST_S = 6 +const SYSTEM_CRYPTO_HMAC_RST_V = 0x1 +const SYSTEM_CRYPTO_HMAC_RST_S = 5 +const SYSTEM_CRYPTO_DS_RST_V = 0x1 +const SYSTEM_CRYPTO_DS_RST_S = 4 +const SYSTEM_CRYPTO_RSA_RST_V = 0x1 +const SYSTEM_CRYPTO_RSA_RST_S = 3 +const SYSTEM_CRYPTO_SHA_RST_V = 0x1 +const SYSTEM_CRYPTO_SHA_RST_S = 2 +const SYSTEM_CRYPTO_AES_RST_V = 0x1 +const SYSTEM_CRYPTO_AES_RST_S = 1 +const SYSTEM_PERI_BACKUP_RST_V = 0x1 +const SYSTEM_PERI_BACKUP_RST_S = 0 +const SYSTEM_BT_LPCK_DIV_NUM = 0x00000FFF +const SYSTEM_BT_LPCK_DIV_NUM_V = 0xFFF +const SYSTEM_BT_LPCK_DIV_NUM_S = 0 +const SYSTEM_LPCLK_RTC_EN_V = 0x1 +const SYSTEM_LPCLK_RTC_EN_S = 28 +const SYSTEM_LPCLK_SEL_XTAL32K_V = 0x1 +const SYSTEM_LPCLK_SEL_XTAL32K_S = 27 +const SYSTEM_LPCLK_SEL_XTAL_V = 0x1 +const SYSTEM_LPCLK_SEL_XTAL_S = 26 +const SYSTEM_LPCLK_SEL_8M_V = 0x1 +const SYSTEM_LPCLK_SEL_8M_S = 25 +const SYSTEM_LPCLK_SEL_RTC_SLOW_V = 0x1 +const SYSTEM_LPCLK_SEL_RTC_SLOW_S = 24 +const SYSTEM_BT_LPCK_DIV_A = 0x00000FFF +const SYSTEM_BT_LPCK_DIV_A_V = 0xFFF +const SYSTEM_BT_LPCK_DIV_A_S = 12 +const SYSTEM_BT_LPCK_DIV_B = 0x00000FFF +const SYSTEM_BT_LPCK_DIV_B_V = 0xFFF +const SYSTEM_BT_LPCK_DIV_B_S = 0 +const SYSTEM_CPU_INTR_FROM_CPU_0_V = 0x1 +const SYSTEM_CPU_INTR_FROM_CPU_0_S = 0 +const SYSTEM_CPU_INTR_FROM_CPU_1_V = 0x1 +const SYSTEM_CPU_INTR_FROM_CPU_1_S = 0 +const SYSTEM_CPU_INTR_FROM_CPU_2_V = 0x1 +const SYSTEM_CPU_INTR_FROM_CPU_2_S = 0 +const SYSTEM_CPU_INTR_FROM_CPU_3_V = 0x1 +const SYSTEM_CPU_INTR_FROM_CPU_3_S = 0 +const SYSTEM_RSA_MEM_FORCE_PD_V = 0x1 +const SYSTEM_RSA_MEM_FORCE_PD_S = 2 +const SYSTEM_RSA_MEM_FORCE_PU_V = 0x1 +const SYSTEM_RSA_MEM_FORCE_PU_S = 1 +const SYSTEM_RSA_MEM_PD_V = 0x1 +const SYSTEM_RSA_MEM_PD_S = 0 +const SYSTEM_EDMA_RESET_V = 0x1 +const SYSTEM_EDMA_RESET_S = 1 +const SYSTEM_EDMA_CLK_ON_V = 0x1 +const SYSTEM_EDMA_CLK_ON_S = 0 +const SYSTEM_DCACHE_RESET_V = 0x1 +const SYSTEM_DCACHE_RESET_S = 3 +const SYSTEM_DCACHE_CLK_ON_V = 0x1 +const SYSTEM_DCACHE_CLK_ON_S = 2 +const SYSTEM_ICACHE_RESET_V = 0x1 +const SYSTEM_ICACHE_RESET_S = 1 +const SYSTEM_ICACHE_CLK_ON_V = 0x1 +const SYSTEM_ICACHE_CLK_ON_S = 0 +const SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V = 0x1 +const SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S = 3 +const SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V = 0x1 +const SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S = 2 +const SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V = 0x1 +const SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S = 1 +const SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V = 0x1 +const SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S = 0 +const SYSTEM_RTC_MEM_CRC_FINISH_V = 0x1 +const SYSTEM_RTC_MEM_CRC_FINISH_S = 31 +const SYSTEM_RTC_MEM_CRC_LEN = 0x000007FF +const SYSTEM_RTC_MEM_CRC_LEN_V = 0x7FF +const SYSTEM_RTC_MEM_CRC_LEN_S = 20 +const SYSTEM_RTC_MEM_CRC_ADDR = 0x000007FF +const SYSTEM_RTC_MEM_CRC_ADDR_V = 0x7FF +const SYSTEM_RTC_MEM_CRC_ADDR_S = 9 +const SYSTEM_RTC_MEM_CRC_START_V = 0x1 +const SYSTEM_RTC_MEM_CRC_START_S = 8 +const SYSTEM_RTC_MEM_CRC_RES = 0xFFFFFFFF +const SYSTEM_RTC_MEM_CRC_RES_V = 0xFFFFFFFF +const SYSTEM_RTC_MEM_CRC_RES_S = 0 +const SYSTEM_REDUNDANT_ECO_RESULT_V = 0x1 +const SYSTEM_REDUNDANT_ECO_RESULT_S = 1 +const SYSTEM_REDUNDANT_ECO_DRIVE_V = 0x1 +const SYSTEM_REDUNDANT_ECO_DRIVE_S = 0 +const SYSTEM_CLK_EN_V = 0x1 +const SYSTEM_CLK_EN_S = 0 +const SYSTEM_CLK_DIV_EN_V = 0x1 +const SYSTEM_CLK_DIV_EN_S = 19 +const SYSTEM_CLK_XTAL_FREQ = 0x0000007F +const SYSTEM_CLK_XTAL_FREQ_V = 0x7F +const SYSTEM_CLK_XTAL_FREQ_S = 12 +const SYSTEM_SOC_CLK_SEL = 0x00000003 +const SYSTEM_SOC_CLK_SEL_V = 0x3 +const SYSTEM_SOC_CLK_SEL_S = 10 +const SYSTEM_PRE_DIV_CNT = 0x000003FF +const SYSTEM_PRE_DIV_CNT_V = 0x3FF +const SYSTEM_PRE_DIV_CNT_S = 0 +const SYSTEM_MEM_VT_SEL = 0x00000003 +const SYSTEM_MEM_VT_SEL_V = 0x3 +const SYSTEM_MEM_VT_SEL_S = 22 +const SYSTEM_MEM_TIMING_ERR_CNT = 0x0000FFFF +const SYSTEM_MEM_TIMING_ERR_CNT_V = 0xFFFF +const SYSTEM_MEM_TIMING_ERR_CNT_S = 6 +const SYSTEM_MEM_PVT_MONITOR_EN_V = 0x1 +const SYSTEM_MEM_PVT_MONITOR_EN_S = 5 +const SYSTEM_MEM_ERR_CNT_CLR_V = 0x1 +const SYSTEM_MEM_ERR_CNT_CLR_S = 4 +const SYSTEM_MEM_PATH_LEN = 0x0000000F +const SYSTEM_MEM_PATH_LEN_V = 0xF +const SYSTEM_MEM_PATH_LEN_S = 0 +const SYSTEM_COMB_PVT_MONITOR_EN_LVT_V = 0x1 +const SYSTEM_COMB_PVT_MONITOR_EN_LVT_S = 6 +const SYSTEM_COMB_ERR_CNT_CLR_LVT_V = 0x1 +const SYSTEM_COMB_ERR_CNT_CLR_LVT_S = 5 +const SYSTEM_COMB_PATH_LEN_LVT = 0x0000001F +const SYSTEM_COMB_PATH_LEN_LVT_V = 0x1F +const SYSTEM_COMB_PATH_LEN_LVT_S = 0 +const SYSTEM_COMB_PVT_MONITOR_EN_NVT_V = 0x1 +const SYSTEM_COMB_PVT_MONITOR_EN_NVT_S = 6 +const SYSTEM_COMB_ERR_CNT_CLR_NVT_V = 0x1 +const SYSTEM_COMB_ERR_CNT_CLR_NVT_S = 5 +const SYSTEM_COMB_PATH_LEN_NVT = 0x0000001F +const SYSTEM_COMB_PATH_LEN_NVT_V = 0x1F +const SYSTEM_COMB_PATH_LEN_NVT_S = 0 +const SYSTEM_COMB_PVT_MONITOR_EN_HVT_V = 0x1 +const SYSTEM_COMB_PVT_MONITOR_EN_HVT_S = 6 +const SYSTEM_COMB_ERR_CNT_CLR_HVT_V = 0x1 +const SYSTEM_COMB_ERR_CNT_CLR_HVT_S = 5 +const SYSTEM_COMB_PATH_LEN_HVT = 0x0000001F +const SYSTEM_COMB_PATH_LEN_HVT_V = 0x1F +const SYSTEM_COMB_PATH_LEN_HVT_S = 0 +const SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 = 0x0000FFFF +const SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V = 0xFFFF +const SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S = 0 +const SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 = 0x0000FFFF +const SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V = 0xFFFF +const SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S = 0 +const SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 = 0x0000FFFF +const SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V = 0xFFFF +const SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S = 0 +const SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 = 0x0000FFFF +const SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V = 0xFFFF +const SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S = 0 +const SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 = 0x0000FFFF +const SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V = 0xFFFF +const SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S = 0 +const SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 = 0x0000FFFF +const SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V = 0xFFFF +const SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S = 0 +const SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 = 0x0000FFFF +const SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V = 0xFFFF +const SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S = 0 +const SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 = 0x0000FFFF +const SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V = 0xFFFF +const SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S = 0 +const SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 = 0x0000FFFF +const SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V = 0xFFFF +const SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S = 0 +const SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 = 0x0000FFFF +const SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V = 0xFFFF +const SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S = 0 +const SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 = 0x0000FFFF +const SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V = 0xFFFF +const SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S = 0 +const SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 = 0x0000FFFF +const SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V = 0xFFFF +const SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S = 0 +const SYSTEM_DATE = 0x0FFFFFFF +const SYSTEM_DATE_V = 0xFFFFFFF +const SYSTEM_DATE_S = 0 diff --git a/esp32/system_struct.go b/esp32/system_struct.go new file mode 100644 index 00000000..fad2d398 --- /dev/null +++ b/esp32/system_struct.go @@ -0,0 +1,1114 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type SystemDevS struct { + Core1Control0 struct { + Val c.Uint32T + } + Core1Control1 c.Uint32T + CpuPeriClkEn struct { + Val c.Uint32T + } + CpuPeriRstEn struct { + Val c.Uint32T + } + CpuPerConf struct { + Val c.Uint32T + } + MemPdMask struct { + Val c.Uint32T + } + PeripClkEn0 struct { + Val c.Uint32T + } + PeripClkEn1 struct { + Val c.Uint32T + } + PeripRstEn0 struct { + Val c.Uint32T + } + PeripRstEn1 struct { + Val c.Uint32T + } + BtLpckDivInt struct { + Val c.Uint32T + } + BtLpckDivFrac struct { + Val c.Uint32T + } + CpuIntrFromCpu0 struct { + Val c.Uint32T + } + CpuIntrFromCpu1 struct { + Val c.Uint32T + } + CpuIntrFromCpu2 struct { + Val c.Uint32T + } + CpuIntrFromCpu3 struct { + Val c.Uint32T + } + RsaPdCtrl struct { + Val c.Uint32T + } + EdmaCtrl struct { + Val c.Uint32T + } + CacheControl struct { + Val c.Uint32T + } + ExternalDeviceEncryptDecryptControl struct { + Val c.Uint32T + } + RtcFastmemConfig struct { + Val c.Uint32T + } + RtcFastmemCrc c.Uint32T + RedundantEcoCtrl struct { + Val c.Uint32T + } + ClockGate struct { + Val c.Uint32T + } + SysclkConf struct { + Val c.Uint32T + } + MemPvt struct { + Val c.Uint32T + } + CombPvtLvtConf struct { + Val c.Uint32T + } + CombPvtNvtConf struct { + Val c.Uint32T + } + CombPvtHvtConf struct { + Val c.Uint32T + } + CombPvtErrLvtSite0 struct { + Val c.Uint32T + } + CombPvtErrNvtSite0 struct { + Val c.Uint32T + } + CombPvtErrHvtSite0 struct { + Val c.Uint32T + } + CombPvtErrLvtSite1 struct { + Val c.Uint32T + } + CombPvtErrNvtSite1 struct { + Val c.Uint32T + } + CombPvtErrHvtSite1 struct { + Val c.Uint32T + } + CombPvtErrLvtSite2 struct { + Val c.Uint32T + } + CombPvtErrNvtSite2 struct { + Val c.Uint32T + } + CombPvtErrHvtSite2 struct { + Val c.Uint32T + } + CombPvtErrLvtSite3 struct { + Val c.Uint32T + } + CombPvtErrNvtSite3 struct { + Val c.Uint32T + } + CombPvtErrHvtSite3 struct { + Val c.Uint32T + } + ReservedA4 c.Uint32T + ReservedA8 c.Uint32T + ReservedAc c.Uint32T + ReservedB0 c.Uint32T + ReservedB4 c.Uint32T + ReservedB8 c.Uint32T + ReservedBc c.Uint32T + ReservedC0 c.Uint32T + ReservedC4 c.Uint32T + ReservedC8 c.Uint32T + ReservedCc c.Uint32T + ReservedD0 c.Uint32T + ReservedD4 c.Uint32T + ReservedD8 c.Uint32T + ReservedDc c.Uint32T + ReservedE0 c.Uint32T + ReservedE4 c.Uint32T + ReservedE8 c.Uint32T + ReservedEc c.Uint32T + ReservedF0 c.Uint32T + ReservedF4 c.Uint32T + ReservedF8 c.Uint32T + ReservedFc c.Uint32T + Reserved100 c.Uint32T + Reserved104 c.Uint32T + Reserved108 c.Uint32T + Reserved10c c.Uint32T + Reserved110 c.Uint32T + Reserved114 c.Uint32T + Reserved118 c.Uint32T + Reserved11c c.Uint32T + Reserved120 c.Uint32T + Reserved124 c.Uint32T + Reserved128 c.Uint32T + Reserved12c c.Uint32T + Reserved130 c.Uint32T + Reserved134 c.Uint32T + Reserved138 c.Uint32T + Reserved13c c.Uint32T + Reserved140 c.Uint32T + Reserved144 c.Uint32T + Reserved148 c.Uint32T + Reserved14c c.Uint32T + Reserved150 c.Uint32T + Reserved154 c.Uint32T + Reserved158 c.Uint32T + Reserved15c c.Uint32T + Reserved160 c.Uint32T + Reserved164 c.Uint32T + Reserved168 c.Uint32T + Reserved16c c.Uint32T + Reserved170 c.Uint32T + Reserved174 c.Uint32T + Reserved178 c.Uint32T + Reserved17c c.Uint32T + Reserved180 c.Uint32T + Reserved184 c.Uint32T + Reserved188 c.Uint32T + Reserved18c c.Uint32T + Reserved190 c.Uint32T + Reserved194 c.Uint32T + Reserved198 c.Uint32T + Reserved19c c.Uint32T + Reserved1a0 c.Uint32T + Reserved1a4 c.Uint32T + Reserved1a8 c.Uint32T + Reserved1ac c.Uint32T + Reserved1b0 c.Uint32T + Reserved1b4 c.Uint32T + Reserved1b8 c.Uint32T + Reserved1bc c.Uint32T + Reserved1c0 c.Uint32T + Reserved1c4 c.Uint32T + Reserved1c8 c.Uint32T + Reserved1cc c.Uint32T + Reserved1d0 c.Uint32T + Reserved1d4 c.Uint32T + Reserved1d8 c.Uint32T + Reserved1dc c.Uint32T + Reserved1e0 c.Uint32T + Reserved1e4 c.Uint32T + Reserved1e8 c.Uint32T + Reserved1ec c.Uint32T + Reserved1f0 c.Uint32T + Reserved1f4 c.Uint32T + Reserved1f8 c.Uint32T + Reserved1fc c.Uint32T + Reserved200 c.Uint32T + Reserved204 c.Uint32T + Reserved208 c.Uint32T + Reserved20c c.Uint32T + Reserved210 c.Uint32T + Reserved214 c.Uint32T + Reserved218 c.Uint32T + Reserved21c c.Uint32T + Reserved220 c.Uint32T + Reserved224 c.Uint32T + Reserved228 c.Uint32T + Reserved22c c.Uint32T + Reserved230 c.Uint32T + Reserved234 c.Uint32T + Reserved238 c.Uint32T + Reserved23c c.Uint32T + Reserved240 c.Uint32T + Reserved244 c.Uint32T + Reserved248 c.Uint32T + Reserved24c c.Uint32T + Reserved250 c.Uint32T + Reserved254 c.Uint32T + Reserved258 c.Uint32T + Reserved25c c.Uint32T + Reserved260 c.Uint32T + Reserved264 c.Uint32T + Reserved268 c.Uint32T + Reserved26c c.Uint32T + Reserved270 c.Uint32T + Reserved274 c.Uint32T + Reserved278 c.Uint32T + Reserved27c c.Uint32T + Reserved280 c.Uint32T + Reserved284 c.Uint32T + Reserved288 c.Uint32T + Reserved28c c.Uint32T + Reserved290 c.Uint32T + Reserved294 c.Uint32T + Reserved298 c.Uint32T + Reserved29c c.Uint32T + Reserved2a0 c.Uint32T + Reserved2a4 c.Uint32T + Reserved2a8 c.Uint32T + Reserved2ac c.Uint32T + Reserved2b0 c.Uint32T + Reserved2b4 c.Uint32T + Reserved2b8 c.Uint32T + Reserved2bc c.Uint32T + Reserved2c0 c.Uint32T + Reserved2c4 c.Uint32T + Reserved2c8 c.Uint32T + Reserved2cc c.Uint32T + Reserved2d0 c.Uint32T + Reserved2d4 c.Uint32T + Reserved2d8 c.Uint32T + Reserved2dc c.Uint32T + Reserved2e0 c.Uint32T + Reserved2e4 c.Uint32T + Reserved2e8 c.Uint32T + Reserved2ec c.Uint32T + Reserved2f0 c.Uint32T + Reserved2f4 c.Uint32T + Reserved2f8 c.Uint32T + Reserved2fc c.Uint32T + Reserved300 c.Uint32T + Reserved304 c.Uint32T + Reserved308 c.Uint32T + Reserved30c c.Uint32T + Reserved310 c.Uint32T + Reserved314 c.Uint32T + Reserved318 c.Uint32T + Reserved31c c.Uint32T + Reserved320 c.Uint32T + Reserved324 c.Uint32T + Reserved328 c.Uint32T + Reserved32c c.Uint32T + Reserved330 c.Uint32T + Reserved334 c.Uint32T + Reserved338 c.Uint32T + Reserved33c c.Uint32T + Reserved340 c.Uint32T + Reserved344 c.Uint32T + Reserved348 c.Uint32T + Reserved34c c.Uint32T + Reserved350 c.Uint32T + Reserved354 c.Uint32T + Reserved358 c.Uint32T + Reserved35c c.Uint32T + Reserved360 c.Uint32T + Reserved364 c.Uint32T + Reserved368 c.Uint32T + Reserved36c c.Uint32T + Reserved370 c.Uint32T + Reserved374 c.Uint32T + Reserved378 c.Uint32T + Reserved37c c.Uint32T + Reserved380 c.Uint32T + Reserved384 c.Uint32T + Reserved388 c.Uint32T + Reserved38c c.Uint32T + Reserved390 c.Uint32T + Reserved394 c.Uint32T + Reserved398 c.Uint32T + Reserved39c c.Uint32T + Reserved3a0 c.Uint32T + Reserved3a4 c.Uint32T + Reserved3a8 c.Uint32T + Reserved3ac c.Uint32T + Reserved3b0 c.Uint32T + Reserved3b4 c.Uint32T + Reserved3b8 c.Uint32T + Reserved3bc c.Uint32T + Reserved3c0 c.Uint32T + Reserved3c4 c.Uint32T + Reserved3c8 c.Uint32T + Reserved3cc c.Uint32T + Reserved3d0 c.Uint32T + Reserved3d4 c.Uint32T + Reserved3d8 c.Uint32T + Reserved3dc c.Uint32T + Reserved3e0 c.Uint32T + Reserved3e4 c.Uint32T + Reserved3e8 c.Uint32T + Reserved3ec c.Uint32T + Reserved3f0 c.Uint32T + Reserved3f4 c.Uint32T + Reserved3f8 c.Uint32T + Reserved3fc c.Uint32T + Reserved400 c.Uint32T + Reserved404 c.Uint32T + Reserved408 c.Uint32T + Reserved40c c.Uint32T + Reserved410 c.Uint32T + Reserved414 c.Uint32T + Reserved418 c.Uint32T + Reserved41c c.Uint32T + Reserved420 c.Uint32T + Reserved424 c.Uint32T + Reserved428 c.Uint32T + Reserved42c c.Uint32T + Reserved430 c.Uint32T + Reserved434 c.Uint32T + Reserved438 c.Uint32T + Reserved43c c.Uint32T + Reserved440 c.Uint32T + Reserved444 c.Uint32T + Reserved448 c.Uint32T + Reserved44c c.Uint32T + Reserved450 c.Uint32T + Reserved454 c.Uint32T + Reserved458 c.Uint32T + Reserved45c c.Uint32T + Reserved460 c.Uint32T + Reserved464 c.Uint32T + Reserved468 c.Uint32T + Reserved46c c.Uint32T + Reserved470 c.Uint32T + Reserved474 c.Uint32T + Reserved478 c.Uint32T + Reserved47c c.Uint32T + Reserved480 c.Uint32T + Reserved484 c.Uint32T + Reserved488 c.Uint32T + Reserved48c c.Uint32T + Reserved490 c.Uint32T + Reserved494 c.Uint32T + Reserved498 c.Uint32T + Reserved49c c.Uint32T + Reserved4a0 c.Uint32T + Reserved4a4 c.Uint32T + Reserved4a8 c.Uint32T + Reserved4ac c.Uint32T + Reserved4b0 c.Uint32T + Reserved4b4 c.Uint32T + Reserved4b8 c.Uint32T + Reserved4bc c.Uint32T + Reserved4c0 c.Uint32T + Reserved4c4 c.Uint32T + Reserved4c8 c.Uint32T + Reserved4cc c.Uint32T + Reserved4d0 c.Uint32T + Reserved4d4 c.Uint32T + Reserved4d8 c.Uint32T + Reserved4dc c.Uint32T + Reserved4e0 c.Uint32T + Reserved4e4 c.Uint32T + Reserved4e8 c.Uint32T + Reserved4ec c.Uint32T + Reserved4f0 c.Uint32T + Reserved4f4 c.Uint32T + Reserved4f8 c.Uint32T + Reserved4fc c.Uint32T + Reserved500 c.Uint32T + Reserved504 c.Uint32T + Reserved508 c.Uint32T + Reserved50c c.Uint32T + Reserved510 c.Uint32T + Reserved514 c.Uint32T + Reserved518 c.Uint32T + Reserved51c c.Uint32T + Reserved520 c.Uint32T + Reserved524 c.Uint32T + Reserved528 c.Uint32T + Reserved52c c.Uint32T + Reserved530 c.Uint32T + Reserved534 c.Uint32T + Reserved538 c.Uint32T + Reserved53c c.Uint32T + Reserved540 c.Uint32T + Reserved544 c.Uint32T + Reserved548 c.Uint32T + Reserved54c c.Uint32T + Reserved550 c.Uint32T + Reserved554 c.Uint32T + Reserved558 c.Uint32T + Reserved55c c.Uint32T + Reserved560 c.Uint32T + Reserved564 c.Uint32T + Reserved568 c.Uint32T + Reserved56c c.Uint32T + Reserved570 c.Uint32T + Reserved574 c.Uint32T + Reserved578 c.Uint32T + Reserved57c c.Uint32T + Reserved580 c.Uint32T + Reserved584 c.Uint32T + Reserved588 c.Uint32T + Reserved58c c.Uint32T + Reserved590 c.Uint32T + Reserved594 c.Uint32T + Reserved598 c.Uint32T + Reserved59c c.Uint32T + Reserved5a0 c.Uint32T + Reserved5a4 c.Uint32T + Reserved5a8 c.Uint32T + Reserved5ac c.Uint32T + Reserved5b0 c.Uint32T + Reserved5b4 c.Uint32T + Reserved5b8 c.Uint32T + Reserved5bc c.Uint32T + Reserved5c0 c.Uint32T + Reserved5c4 c.Uint32T + Reserved5c8 c.Uint32T + Reserved5cc c.Uint32T + Reserved5d0 c.Uint32T + Reserved5d4 c.Uint32T + Reserved5d8 c.Uint32T + Reserved5dc c.Uint32T + Reserved5e0 c.Uint32T + Reserved5e4 c.Uint32T + Reserved5e8 c.Uint32T + Reserved5ec c.Uint32T + Reserved5f0 c.Uint32T + Reserved5f4 c.Uint32T + Reserved5f8 c.Uint32T + Reserved5fc c.Uint32T + Reserved600 c.Uint32T + Reserved604 c.Uint32T + Reserved608 c.Uint32T + Reserved60c c.Uint32T + Reserved610 c.Uint32T + Reserved614 c.Uint32T + Reserved618 c.Uint32T + Reserved61c c.Uint32T + Reserved620 c.Uint32T + Reserved624 c.Uint32T + Reserved628 c.Uint32T + Reserved62c c.Uint32T + Reserved630 c.Uint32T + Reserved634 c.Uint32T + Reserved638 c.Uint32T + Reserved63c c.Uint32T + Reserved640 c.Uint32T + Reserved644 c.Uint32T + Reserved648 c.Uint32T + Reserved64c c.Uint32T + Reserved650 c.Uint32T + Reserved654 c.Uint32T + Reserved658 c.Uint32T + Reserved65c c.Uint32T + Reserved660 c.Uint32T + Reserved664 c.Uint32T + Reserved668 c.Uint32T + Reserved66c c.Uint32T + Reserved670 c.Uint32T + Reserved674 c.Uint32T + Reserved678 c.Uint32T + Reserved67c c.Uint32T + Reserved680 c.Uint32T + Reserved684 c.Uint32T + Reserved688 c.Uint32T + Reserved68c c.Uint32T + Reserved690 c.Uint32T + Reserved694 c.Uint32T + Reserved698 c.Uint32T + Reserved69c c.Uint32T + Reserved6a0 c.Uint32T + Reserved6a4 c.Uint32T + Reserved6a8 c.Uint32T + Reserved6ac c.Uint32T + Reserved6b0 c.Uint32T + Reserved6b4 c.Uint32T + Reserved6b8 c.Uint32T + Reserved6bc c.Uint32T + Reserved6c0 c.Uint32T + Reserved6c4 c.Uint32T + Reserved6c8 c.Uint32T + Reserved6cc c.Uint32T + Reserved6d0 c.Uint32T + Reserved6d4 c.Uint32T + Reserved6d8 c.Uint32T + Reserved6dc c.Uint32T + Reserved6e0 c.Uint32T + Reserved6e4 c.Uint32T + Reserved6e8 c.Uint32T + Reserved6ec c.Uint32T + Reserved6f0 c.Uint32T + Reserved6f4 c.Uint32T + Reserved6f8 c.Uint32T + Reserved6fc c.Uint32T + Reserved700 c.Uint32T + Reserved704 c.Uint32T + Reserved708 c.Uint32T + Reserved70c c.Uint32T + Reserved710 c.Uint32T + Reserved714 c.Uint32T + Reserved718 c.Uint32T + Reserved71c c.Uint32T + Reserved720 c.Uint32T + Reserved724 c.Uint32T + Reserved728 c.Uint32T + Reserved72c c.Uint32T + Reserved730 c.Uint32T + Reserved734 c.Uint32T + Reserved738 c.Uint32T + Reserved73c c.Uint32T + Reserved740 c.Uint32T + Reserved744 c.Uint32T + Reserved748 c.Uint32T + Reserved74c c.Uint32T + Reserved750 c.Uint32T + Reserved754 c.Uint32T + Reserved758 c.Uint32T + Reserved75c c.Uint32T + Reserved760 c.Uint32T + Reserved764 c.Uint32T + Reserved768 c.Uint32T + Reserved76c c.Uint32T + Reserved770 c.Uint32T + Reserved774 c.Uint32T + Reserved778 c.Uint32T + Reserved77c c.Uint32T + Reserved780 c.Uint32T + Reserved784 c.Uint32T + Reserved788 c.Uint32T + Reserved78c c.Uint32T + Reserved790 c.Uint32T + Reserved794 c.Uint32T + Reserved798 c.Uint32T + Reserved79c c.Uint32T + Reserved7a0 c.Uint32T + Reserved7a4 c.Uint32T + Reserved7a8 c.Uint32T + Reserved7ac c.Uint32T + Reserved7b0 c.Uint32T + Reserved7b4 c.Uint32T + Reserved7b8 c.Uint32T + Reserved7bc c.Uint32T + Reserved7c0 c.Uint32T + Reserved7c4 c.Uint32T + Reserved7c8 c.Uint32T + Reserved7cc c.Uint32T + Reserved7d0 c.Uint32T + Reserved7d4 c.Uint32T + Reserved7d8 c.Uint32T + Reserved7dc c.Uint32T + Reserved7e0 c.Uint32T + Reserved7e4 c.Uint32T + Reserved7e8 c.Uint32T + Reserved7ec c.Uint32T + Reserved7f0 c.Uint32T + Reserved7f4 c.Uint32T + Reserved7f8 c.Uint32T + Reserved7fc c.Uint32T + Reserved800 c.Uint32T + Reserved804 c.Uint32T + Reserved808 c.Uint32T + Reserved80c c.Uint32T + Reserved810 c.Uint32T + Reserved814 c.Uint32T + Reserved818 c.Uint32T + Reserved81c c.Uint32T + Reserved820 c.Uint32T + Reserved824 c.Uint32T + Reserved828 c.Uint32T + Reserved82c c.Uint32T + Reserved830 c.Uint32T + Reserved834 c.Uint32T + Reserved838 c.Uint32T + Reserved83c c.Uint32T + Reserved840 c.Uint32T + Reserved844 c.Uint32T + Reserved848 c.Uint32T + Reserved84c c.Uint32T + Reserved850 c.Uint32T + Reserved854 c.Uint32T + Reserved858 c.Uint32T + Reserved85c c.Uint32T + Reserved860 c.Uint32T + Reserved864 c.Uint32T + Reserved868 c.Uint32T + Reserved86c c.Uint32T + Reserved870 c.Uint32T + Reserved874 c.Uint32T + Reserved878 c.Uint32T + Reserved87c c.Uint32T + Reserved880 c.Uint32T + Reserved884 c.Uint32T + Reserved888 c.Uint32T + Reserved88c c.Uint32T + Reserved890 c.Uint32T + Reserved894 c.Uint32T + Reserved898 c.Uint32T + Reserved89c c.Uint32T + Reserved8a0 c.Uint32T + Reserved8a4 c.Uint32T + Reserved8a8 c.Uint32T + Reserved8ac c.Uint32T + Reserved8b0 c.Uint32T + Reserved8b4 c.Uint32T + Reserved8b8 c.Uint32T + Reserved8bc c.Uint32T + Reserved8c0 c.Uint32T + Reserved8c4 c.Uint32T + Reserved8c8 c.Uint32T + Reserved8cc c.Uint32T + Reserved8d0 c.Uint32T + Reserved8d4 c.Uint32T + Reserved8d8 c.Uint32T + Reserved8dc c.Uint32T + Reserved8e0 c.Uint32T + Reserved8e4 c.Uint32T + Reserved8e8 c.Uint32T + Reserved8ec c.Uint32T + Reserved8f0 c.Uint32T + Reserved8f4 c.Uint32T + Reserved8f8 c.Uint32T + Reserved8fc c.Uint32T + Reserved900 c.Uint32T + Reserved904 c.Uint32T + Reserved908 c.Uint32T + Reserved90c c.Uint32T + Reserved910 c.Uint32T + Reserved914 c.Uint32T + Reserved918 c.Uint32T + Reserved91c c.Uint32T + Reserved920 c.Uint32T + Reserved924 c.Uint32T + Reserved928 c.Uint32T + Reserved92c c.Uint32T + Reserved930 c.Uint32T + Reserved934 c.Uint32T + Reserved938 c.Uint32T + Reserved93c c.Uint32T + Reserved940 c.Uint32T + Reserved944 c.Uint32T + Reserved948 c.Uint32T + Reserved94c c.Uint32T + Reserved950 c.Uint32T + Reserved954 c.Uint32T + Reserved958 c.Uint32T + Reserved95c c.Uint32T + Reserved960 c.Uint32T + Reserved964 c.Uint32T + Reserved968 c.Uint32T + Reserved96c c.Uint32T + Reserved970 c.Uint32T + Reserved974 c.Uint32T + Reserved978 c.Uint32T + Reserved97c c.Uint32T + Reserved980 c.Uint32T + Reserved984 c.Uint32T + Reserved988 c.Uint32T + Reserved98c c.Uint32T + Reserved990 c.Uint32T + Reserved994 c.Uint32T + Reserved998 c.Uint32T + Reserved99c c.Uint32T + Reserved9a0 c.Uint32T + Reserved9a4 c.Uint32T + Reserved9a8 c.Uint32T + Reserved9ac c.Uint32T + Reserved9b0 c.Uint32T + Reserved9b4 c.Uint32T + Reserved9b8 c.Uint32T + Reserved9bc c.Uint32T + Reserved9c0 c.Uint32T + Reserved9c4 c.Uint32T + Reserved9c8 c.Uint32T + Reserved9cc c.Uint32T + Reserved9d0 c.Uint32T + Reserved9d4 c.Uint32T + Reserved9d8 c.Uint32T + Reserved9dc c.Uint32T + Reserved9e0 c.Uint32T + Reserved9e4 c.Uint32T + Reserved9e8 c.Uint32T + Reserved9ec c.Uint32T + Reserved9f0 c.Uint32T + Reserved9f4 c.Uint32T + Reserved9f8 c.Uint32T + Reserved9fc c.Uint32T + ReservedA00 c.Uint32T + ReservedA04 c.Uint32T + ReservedA08 c.Uint32T + ReservedA0c c.Uint32T + ReservedA10 c.Uint32T + ReservedA14 c.Uint32T + ReservedA18 c.Uint32T + ReservedA1c c.Uint32T + ReservedA20 c.Uint32T + ReservedA24 c.Uint32T + ReservedA28 c.Uint32T + ReservedA2c c.Uint32T + ReservedA30 c.Uint32T + ReservedA34 c.Uint32T + ReservedA38 c.Uint32T + ReservedA3c c.Uint32T + ReservedA40 c.Uint32T + ReservedA44 c.Uint32T + ReservedA48 c.Uint32T + ReservedA4c c.Uint32T + ReservedA50 c.Uint32T + ReservedA54 c.Uint32T + ReservedA58 c.Uint32T + ReservedA5c c.Uint32T + ReservedA60 c.Uint32T + ReservedA64 c.Uint32T + ReservedA68 c.Uint32T + ReservedA6c c.Uint32T + ReservedA70 c.Uint32T + ReservedA74 c.Uint32T + ReservedA78 c.Uint32T + ReservedA7c c.Uint32T + ReservedA80 c.Uint32T + ReservedA84 c.Uint32T + ReservedA88 c.Uint32T + ReservedA8c c.Uint32T + ReservedA90 c.Uint32T + ReservedA94 c.Uint32T + ReservedA98 c.Uint32T + ReservedA9c c.Uint32T + ReservedAa0 c.Uint32T + ReservedAa4 c.Uint32T + ReservedAa8 c.Uint32T + ReservedAac c.Uint32T + ReservedAb0 c.Uint32T + ReservedAb4 c.Uint32T + ReservedAb8 c.Uint32T + ReservedAbc c.Uint32T + ReservedAc0 c.Uint32T + ReservedAc4 c.Uint32T + ReservedAc8 c.Uint32T + ReservedAcc c.Uint32T + ReservedAd0 c.Uint32T + ReservedAd4 c.Uint32T + ReservedAd8 c.Uint32T + ReservedAdc c.Uint32T + ReservedAe0 c.Uint32T + ReservedAe4 c.Uint32T + ReservedAe8 c.Uint32T + ReservedAec c.Uint32T + ReservedAf0 c.Uint32T + ReservedAf4 c.Uint32T + ReservedAf8 c.Uint32T + ReservedAfc c.Uint32T + ReservedB00 c.Uint32T + ReservedB04 c.Uint32T + ReservedB08 c.Uint32T + ReservedB0c c.Uint32T + ReservedB10 c.Uint32T + ReservedB14 c.Uint32T + ReservedB18 c.Uint32T + ReservedB1c c.Uint32T + ReservedB20 c.Uint32T + ReservedB24 c.Uint32T + ReservedB28 c.Uint32T + ReservedB2c c.Uint32T + ReservedB30 c.Uint32T + ReservedB34 c.Uint32T + ReservedB38 c.Uint32T + ReservedB3c c.Uint32T + ReservedB40 c.Uint32T + ReservedB44 c.Uint32T + ReservedB48 c.Uint32T + ReservedB4c c.Uint32T + ReservedB50 c.Uint32T + ReservedB54 c.Uint32T + ReservedB58 c.Uint32T + ReservedB5c c.Uint32T + ReservedB60 c.Uint32T + ReservedB64 c.Uint32T + ReservedB68 c.Uint32T + ReservedB6c c.Uint32T + ReservedB70 c.Uint32T + ReservedB74 c.Uint32T + ReservedB78 c.Uint32T + ReservedB7c c.Uint32T + ReservedB80 c.Uint32T + ReservedB84 c.Uint32T + ReservedB88 c.Uint32T + ReservedB8c c.Uint32T + ReservedB90 c.Uint32T + ReservedB94 c.Uint32T + ReservedB98 c.Uint32T + ReservedB9c c.Uint32T + ReservedBa0 c.Uint32T + ReservedBa4 c.Uint32T + ReservedBa8 c.Uint32T + ReservedBac c.Uint32T + ReservedBb0 c.Uint32T + ReservedBb4 c.Uint32T + ReservedBb8 c.Uint32T + ReservedBbc c.Uint32T + ReservedBc0 c.Uint32T + ReservedBc4 c.Uint32T + ReservedBc8 c.Uint32T + ReservedBcc c.Uint32T + ReservedBd0 c.Uint32T + ReservedBd4 c.Uint32T + ReservedBd8 c.Uint32T + ReservedBdc c.Uint32T + ReservedBe0 c.Uint32T + ReservedBe4 c.Uint32T + ReservedBe8 c.Uint32T + ReservedBec c.Uint32T + ReservedBf0 c.Uint32T + ReservedBf4 c.Uint32T + ReservedBf8 c.Uint32T + ReservedBfc c.Uint32T + ReservedC00 c.Uint32T + ReservedC04 c.Uint32T + ReservedC08 c.Uint32T + ReservedC0c c.Uint32T + ReservedC10 c.Uint32T + ReservedC14 c.Uint32T + ReservedC18 c.Uint32T + ReservedC1c c.Uint32T + ReservedC20 c.Uint32T + ReservedC24 c.Uint32T + ReservedC28 c.Uint32T + ReservedC2c c.Uint32T + ReservedC30 c.Uint32T + ReservedC34 c.Uint32T + ReservedC38 c.Uint32T + ReservedC3c c.Uint32T + ReservedC40 c.Uint32T + ReservedC44 c.Uint32T + ReservedC48 c.Uint32T + ReservedC4c c.Uint32T + ReservedC50 c.Uint32T + ReservedC54 c.Uint32T + ReservedC58 c.Uint32T + ReservedC5c c.Uint32T + ReservedC60 c.Uint32T + ReservedC64 c.Uint32T + ReservedC68 c.Uint32T + ReservedC6c c.Uint32T + ReservedC70 c.Uint32T + ReservedC74 c.Uint32T + ReservedC78 c.Uint32T + ReservedC7c c.Uint32T + ReservedC80 c.Uint32T + ReservedC84 c.Uint32T + ReservedC88 c.Uint32T + ReservedC8c c.Uint32T + ReservedC90 c.Uint32T + ReservedC94 c.Uint32T + ReservedC98 c.Uint32T + ReservedC9c c.Uint32T + ReservedCa0 c.Uint32T + ReservedCa4 c.Uint32T + ReservedCa8 c.Uint32T + ReservedCac c.Uint32T + ReservedCb0 c.Uint32T + ReservedCb4 c.Uint32T + ReservedCb8 c.Uint32T + ReservedCbc c.Uint32T + ReservedCc0 c.Uint32T + ReservedCc4 c.Uint32T + ReservedCc8 c.Uint32T + ReservedCcc c.Uint32T + ReservedCd0 c.Uint32T + ReservedCd4 c.Uint32T + ReservedCd8 c.Uint32T + ReservedCdc c.Uint32T + ReservedCe0 c.Uint32T + ReservedCe4 c.Uint32T + ReservedCe8 c.Uint32T + ReservedCec c.Uint32T + ReservedCf0 c.Uint32T + ReservedCf4 c.Uint32T + ReservedCf8 c.Uint32T + ReservedCfc c.Uint32T + ReservedD00 c.Uint32T + ReservedD04 c.Uint32T + ReservedD08 c.Uint32T + ReservedD0c c.Uint32T + ReservedD10 c.Uint32T + ReservedD14 c.Uint32T + ReservedD18 c.Uint32T + ReservedD1c c.Uint32T + ReservedD20 c.Uint32T + ReservedD24 c.Uint32T + ReservedD28 c.Uint32T + ReservedD2c c.Uint32T + ReservedD30 c.Uint32T + ReservedD34 c.Uint32T + ReservedD38 c.Uint32T + ReservedD3c c.Uint32T + ReservedD40 c.Uint32T + ReservedD44 c.Uint32T + ReservedD48 c.Uint32T + ReservedD4c c.Uint32T + ReservedD50 c.Uint32T + ReservedD54 c.Uint32T + ReservedD58 c.Uint32T + ReservedD5c c.Uint32T + ReservedD60 c.Uint32T + ReservedD64 c.Uint32T + ReservedD68 c.Uint32T + ReservedD6c c.Uint32T + ReservedD70 c.Uint32T + ReservedD74 c.Uint32T + ReservedD78 c.Uint32T + ReservedD7c c.Uint32T + ReservedD80 c.Uint32T + ReservedD84 c.Uint32T + ReservedD88 c.Uint32T + ReservedD8c c.Uint32T + ReservedD90 c.Uint32T + ReservedD94 c.Uint32T + ReservedD98 c.Uint32T + ReservedD9c c.Uint32T + ReservedDa0 c.Uint32T + ReservedDa4 c.Uint32T + ReservedDa8 c.Uint32T + ReservedDac c.Uint32T + ReservedDb0 c.Uint32T + ReservedDb4 c.Uint32T + ReservedDb8 c.Uint32T + ReservedDbc c.Uint32T + ReservedDc0 c.Uint32T + ReservedDc4 c.Uint32T + ReservedDc8 c.Uint32T + ReservedDcc c.Uint32T + ReservedDd0 c.Uint32T + ReservedDd4 c.Uint32T + ReservedDd8 c.Uint32T + ReservedDdc c.Uint32T + ReservedDe0 c.Uint32T + ReservedDe4 c.Uint32T + ReservedDe8 c.Uint32T + ReservedDec c.Uint32T + ReservedDf0 c.Uint32T + ReservedDf4 c.Uint32T + ReservedDf8 c.Uint32T + ReservedDfc c.Uint32T + ReservedE00 c.Uint32T + ReservedE04 c.Uint32T + ReservedE08 c.Uint32T + ReservedE0c c.Uint32T + ReservedE10 c.Uint32T + ReservedE14 c.Uint32T + ReservedE18 c.Uint32T + ReservedE1c c.Uint32T + ReservedE20 c.Uint32T + ReservedE24 c.Uint32T + ReservedE28 c.Uint32T + ReservedE2c c.Uint32T + ReservedE30 c.Uint32T + ReservedE34 c.Uint32T + ReservedE38 c.Uint32T + ReservedE3c c.Uint32T + ReservedE40 c.Uint32T + ReservedE44 c.Uint32T + ReservedE48 c.Uint32T + ReservedE4c c.Uint32T + ReservedE50 c.Uint32T + ReservedE54 c.Uint32T + ReservedE58 c.Uint32T + ReservedE5c c.Uint32T + ReservedE60 c.Uint32T + ReservedE64 c.Uint32T + ReservedE68 c.Uint32T + ReservedE6c c.Uint32T + ReservedE70 c.Uint32T + ReservedE74 c.Uint32T + ReservedE78 c.Uint32T + ReservedE7c c.Uint32T + ReservedE80 c.Uint32T + ReservedE84 c.Uint32T + ReservedE88 c.Uint32T + ReservedE8c c.Uint32T + ReservedE90 c.Uint32T + ReservedE94 c.Uint32T + ReservedE98 c.Uint32T + ReservedE9c c.Uint32T + ReservedEa0 c.Uint32T + ReservedEa4 c.Uint32T + ReservedEa8 c.Uint32T + ReservedEac c.Uint32T + ReservedEb0 c.Uint32T + ReservedEb4 c.Uint32T + ReservedEb8 c.Uint32T + ReservedEbc c.Uint32T + ReservedEc0 c.Uint32T + ReservedEc4 c.Uint32T + ReservedEc8 c.Uint32T + ReservedEcc c.Uint32T + ReservedEd0 c.Uint32T + ReservedEd4 c.Uint32T + ReservedEd8 c.Uint32T + ReservedEdc c.Uint32T + ReservedEe0 c.Uint32T + ReservedEe4 c.Uint32T + ReservedEe8 c.Uint32T + ReservedEec c.Uint32T + ReservedEf0 c.Uint32T + ReservedEf4 c.Uint32T + ReservedEf8 c.Uint32T + ReservedEfc c.Uint32T + ReservedF00 c.Uint32T + ReservedF04 c.Uint32T + ReservedF08 c.Uint32T + ReservedF0c c.Uint32T + ReservedF10 c.Uint32T + ReservedF14 c.Uint32T + ReservedF18 c.Uint32T + ReservedF1c c.Uint32T + ReservedF20 c.Uint32T + ReservedF24 c.Uint32T + ReservedF28 c.Uint32T + ReservedF2c c.Uint32T + ReservedF30 c.Uint32T + ReservedF34 c.Uint32T + ReservedF38 c.Uint32T + ReservedF3c c.Uint32T + ReservedF40 c.Uint32T + ReservedF44 c.Uint32T + ReservedF48 c.Uint32T + ReservedF4c c.Uint32T + ReservedF50 c.Uint32T + ReservedF54 c.Uint32T + ReservedF58 c.Uint32T + ReservedF5c c.Uint32T + ReservedF60 c.Uint32T + ReservedF64 c.Uint32T + ReservedF68 c.Uint32T + ReservedF6c c.Uint32T + ReservedF70 c.Uint32T + ReservedF74 c.Uint32T + ReservedF78 c.Uint32T + ReservedF7c c.Uint32T + ReservedF80 c.Uint32T + ReservedF84 c.Uint32T + ReservedF88 c.Uint32T + ReservedF8c c.Uint32T + ReservedF90 c.Uint32T + ReservedF94 c.Uint32T + ReservedF98 c.Uint32T + ReservedF9c c.Uint32T + ReservedFa0 c.Uint32T + ReservedFa4 c.Uint32T + ReservedFa8 c.Uint32T + ReservedFac c.Uint32T + ReservedFb0 c.Uint32T + ReservedFb4 c.Uint32T + ReservedFb8 c.Uint32T + ReservedFbc c.Uint32T + ReservedFc0 c.Uint32T + ReservedFc4 c.Uint32T + ReservedFc8 c.Uint32T + ReservedFcc c.Uint32T + ReservedFd0 c.Uint32T + ReservedFd4 c.Uint32T + ReservedFd8 c.Uint32T + ReservedFdc c.Uint32T + ReservedFe0 c.Uint32T + ReservedFe4 c.Uint32T + ReservedFe8 c.Uint32T + ReservedFec c.Uint32T + ReservedFf0 c.Uint32T + ReservedFf4 c.Uint32T + ReservedFf8 c.Uint32T + Date struct { + Val c.Uint32T + } +} +type SystemDevT SystemDevS diff --git a/esp32/systimer.go b/esp32/systimer.go new file mode 100644 index 00000000..0196f45b --- /dev/null +++ b/esp32/systimer.go @@ -0,0 +1,30 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const SYSTIMER_COUNTER_ESPTIMER = 0 +const SYSTIMER_COUNTER_OS_TICK = 1 +const SYSTIMER_ALARM_OS_TICK_CORE0 = 0 +const SYSTIMER_ALARM_OS_TICK_CORE1 = 1 +const SYSTIMER_ALARM_ESPTIMER = 2 + +/** + * @brief Convert ticks to microseconds + * + * @param ticks ticks to convert + * @return microseconds + */ +//go:linkname SystimerTicksToUs C.systimer_ticks_to_us +func SystimerTicksToUs(ticks c.Uint64T) c.Uint64T + +/** + * @brief Convert microseconds to ticks + * + * @param us microseconds to convert + * @return ticks + */ +//go:linkname SystimerUsToTicks C.systimer_us_to_ticks +func SystimerUsToTicks(us c.Uint64T) c.Uint64T diff --git a/esp32/systimer_hal.go b/esp32/systimer_hal.go new file mode 100644 index 00000000..3bc8a8e6 --- /dev/null +++ b/esp32/systimer_hal.go @@ -0,0 +1,150 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type SystimerSocHandleT *SystimerDevT + +// llgo:type C +type TicksToUsFuncT func(c.Uint64T) c.Uint64T + +// llgo:type C +type UsToTicksFuncT func(c.Uint64T) c.Uint64T + +/** + * @brief systimer HAL context structure + */ + +type SystimerHalContextT struct { + Dev SystimerSocHandleT + TicksToUs TicksToUsFuncT + UsToTicks UsToTicksFuncT +} + +/** + * @brief systimer HAL configuration structure + */ + +type SystimerHalTickRateOpsT struct { + TicksToUs TicksToUsFuncT + UsToTicks UsToTicksFuncT +} +type SystimerClockSourceT SocPeriphSystimerClkSrcT + +/** + * @brief initialize systimer in HAL layer + */ +// llgo:link (*SystimerHalContextT).SystimerHalInit C.systimer_hal_init +func (recv_ *SystimerHalContextT) SystimerHalInit() { +} + +/** + * @brief Deinitialize systimer HAL layer + */ +// llgo:link (*SystimerHalContextT).SystimerHalDeinit C.systimer_hal_deinit +func (recv_ *SystimerHalContextT) SystimerHalDeinit() { +} + +/** + * @brief Set tick rate operation functions + */ +// llgo:link (*SystimerHalContextT).SystimerHalSetTickRateOps C.systimer_hal_set_tick_rate_ops +func (recv_ *SystimerHalContextT) SystimerHalSetTickRateOps(ops *SystimerHalTickRateOpsT) { +} + +/** + * @brief enable systimer counter + */ +// llgo:link (*SystimerHalContextT).SystimerHalEnableCounter C.systimer_hal_enable_counter +func (recv_ *SystimerHalContextT) SystimerHalEnableCounter(counter_id c.Uint32T) { +} + +/** + * @brief get current counter value + */ +// llgo:link (*SystimerHalContextT).SystimerHalGetCounterValue C.systimer_hal_get_counter_value +func (recv_ *SystimerHalContextT) SystimerHalGetCounterValue(counter_id c.Uint32T) c.Uint64T { + return 0 +} + +/** + * @brief get current time (in microseconds) + */ +// llgo:link (*SystimerHalContextT).SystimerHalGetTime C.systimer_hal_get_time +func (recv_ *SystimerHalContextT) SystimerHalGetTime(counter_id c.Uint32T) c.Uint64T { + return 0 +} + +/* + * @brief set alarm target value (used in one-shot mode) + */ +// llgo:link (*SystimerHalContextT).SystimerHalSetAlarmTarget C.systimer_hal_set_alarm_target +func (recv_ *SystimerHalContextT) SystimerHalSetAlarmTarget(alarm_id c.Uint32T, target c.Uint64T) { +} + +/** + * @brief set alarm period value (used in period mode) + */ +// llgo:link (*SystimerHalContextT).SystimerHalSetAlarmPeriod C.systimer_hal_set_alarm_period +func (recv_ *SystimerHalContextT) SystimerHalSetAlarmPeriod(alarm_id c.Uint32T, period c.Uint32T) { +} + +/** + * @brief get alarm time + */ +// llgo:link (*SystimerHalContextT).SystimerHalGetAlarmValue C.systimer_hal_get_alarm_value +func (recv_ *SystimerHalContextT) SystimerHalGetAlarmValue(alarm_id c.Uint32T) c.Uint64T { + return 0 +} + +/** + * @brief enable alarm interrupt + */ +// llgo:link (*SystimerHalContextT).SystimerHalEnableAlarmInt C.systimer_hal_enable_alarm_int +func (recv_ *SystimerHalContextT) SystimerHalEnableAlarmInt(alarm_id c.Uint32T) { +} + +/** + * @brief select alarm mode + */ +// llgo:link (*SystimerHalContextT).SystimerHalSelectAlarmMode C.systimer_hal_select_alarm_mode +func (recv_ *SystimerHalContextT) SystimerHalSelectAlarmMode(alarm_id c.Uint32T, mode SystimerAlarmModeT) { +} + +/** + * @brief update systimer step when apb clock gets changed + */ +// llgo:link (*SystimerHalContextT).SystimerHalOnApbFreqUpdate C.systimer_hal_on_apb_freq_update +func (recv_ *SystimerHalContextT) SystimerHalOnApbFreqUpdate(apb_ticks_per_us c.Uint32T) { +} + +/** + * @brief move systimer counter value forward or backward + */ +// llgo:link (*SystimerHalContextT).SystimerHalCounterValueAdvance C.systimer_hal_counter_value_advance +func (recv_ *SystimerHalContextT) SystimerHalCounterValueAdvance(counter_id c.Uint32T, time_us c.Int64T) { +} + +/** + * @brief connect alarm unit to selected counter + */ +// llgo:link (*SystimerHalContextT).SystimerHalConnectAlarmCounter C.systimer_hal_connect_alarm_counter +func (recv_ *SystimerHalContextT) SystimerHalConnectAlarmCounter(alarm_id c.Uint32T, counter_id c.Uint32T) { +} + +/** + * @brief set if a counter should be stalled when CPU is halted by the debugger + */ +// llgo:link (*SystimerHalContextT).SystimerHalCounterCanStallByCpu C.systimer_hal_counter_can_stall_by_cpu +func (recv_ *SystimerHalContextT) SystimerHalCounterCanStallByCpu(counter_id c.Uint32T, cpu_id c.Uint32T, can bool) { +} + +/** + * @brief Get Systimer clock source + */ +// llgo:link (*SystimerHalContextT).SystimerHalGetClockSource C.systimer_hal_get_clock_source +func (recv_ *SystimerHalContextT) SystimerHalGetClockSource() SystimerClockSourceT { + return 0 +} diff --git a/esp32/systimer_ll.go b/esp32/systimer_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/systimer_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/systimer_reg.go b/esp32/systimer_reg.go new file mode 100644 index 00000000..03a5727c --- /dev/null +++ b/esp32/systimer_reg.go @@ -0,0 +1,152 @@ +package freertos + +import _ "unsafe" + +const SYSTIMER_SYSTIMER_CLK_FO_V = 0x00000001 +const SYSTIMER_SYSTIMER_CLK_FO_S = 0 +const SYSTIMER_TARGET2_WORK_EN_V = 0x00000001 +const SYSTIMER_TARGET2_WORK_EN_S = 22 +const SYSTIMER_TARGET1_WORK_EN_V = 0x00000001 +const SYSTIMER_TARGET1_WORK_EN_S = 23 +const SYSTIMER_TARGET0_WORK_EN_V = 0x00000001 +const SYSTIMER_TARGET0_WORK_EN_S = 24 +const SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V = 0x00000001 +const SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S = 25 +const SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V = 0x00000001 +const SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S = 26 +const SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V = 0x00000001 +const SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S = 27 +const SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V = 0x00000001 +const SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S = 28 +const SYSTIMER_TIMER_UNIT1_WORK_EN_V = 0x00000001 +const SYSTIMER_TIMER_UNIT1_WORK_EN_S = 29 +const SYSTIMER_TIMER_UNIT0_WORK_EN_V = 0x00000001 +const SYSTIMER_TIMER_UNIT0_WORK_EN_S = 30 +const SYSTIMER_CLK_EN_V = 0x00000001 +const SYSTIMER_CLK_EN_S = 31 +const SYSTIMER_TIMER_UNIT0_VALUE_VALID_V = 0x00000001 +const SYSTIMER_TIMER_UNIT0_VALUE_VALID_S = 29 +const SYSTIMER_TIMER_UNIT0_UPDATE_V = 0x00000001 +const SYSTIMER_TIMER_UNIT0_UPDATE_S = 30 +const SYSTIMER_TIMER_UNIT1_VALUE_VALID_V = 0x00000001 +const SYSTIMER_TIMER_UNIT1_VALUE_VALID_S = 29 +const SYSTIMER_TIMER_UNIT1_UPDATE_V = 0x00000001 +const SYSTIMER_TIMER_UNIT1_UPDATE_S = 30 +const SYSTIMER_TIMER_UNIT0_LOAD_HI = 0x000FFFFF +const SYSTIMER_TIMER_UNIT0_LOAD_HI_V = 0x000FFFFF +const SYSTIMER_TIMER_UNIT0_LOAD_HI_S = 0 +const SYSTIMER_TIMER_UNIT0_LOAD_LO = 0xFFFFFFFF +const SYSTIMER_TIMER_UNIT0_LOAD_LO_V = 0xFFFFFFFF +const SYSTIMER_TIMER_UNIT0_LOAD_LO_S = 0 +const SYSTIMER_TIMER_UNIT1_LOAD_HI = 0x000FFFFF +const SYSTIMER_TIMER_UNIT1_LOAD_HI_V = 0x000FFFFF +const SYSTIMER_TIMER_UNIT1_LOAD_HI_S = 0 +const SYSTIMER_TIMER_UNIT1_LOAD_LO = 0xFFFFFFFF +const SYSTIMER_TIMER_UNIT1_LOAD_LO_V = 0xFFFFFFFF +const SYSTIMER_TIMER_UNIT1_LOAD_LO_S = 0 +const SYSTIMER_TIMER_TARGET0_HI = 0x000FFFFF +const SYSTIMER_TIMER_TARGET0_HI_V = 0x000FFFFF +const SYSTIMER_TIMER_TARGET0_HI_S = 0 +const SYSTIMER_TIMER_TARGET0_LO = 0xFFFFFFFF +const SYSTIMER_TIMER_TARGET0_LO_V = 0xFFFFFFFF +const SYSTIMER_TIMER_TARGET0_LO_S = 0 +const SYSTIMER_TIMER_TARGET1_HI = 0x000FFFFF +const SYSTIMER_TIMER_TARGET1_HI_V = 0x000FFFFF +const SYSTIMER_TIMER_TARGET1_HI_S = 0 +const SYSTIMER_TIMER_TARGET1_LO = 0xFFFFFFFF +const SYSTIMER_TIMER_TARGET1_LO_V = 0xFFFFFFFF +const SYSTIMER_TIMER_TARGET1_LO_S = 0 +const SYSTIMER_TIMER_TARGET2_HI = 0x000FFFFF +const SYSTIMER_TIMER_TARGET2_HI_V = 0x000FFFFF +const SYSTIMER_TIMER_TARGET2_HI_S = 0 +const SYSTIMER_TIMER_TARGET2_LO = 0xFFFFFFFF +const SYSTIMER_TIMER_TARGET2_LO_V = 0xFFFFFFFF +const SYSTIMER_TIMER_TARGET2_LO_S = 0 +const SYSTIMER_TARGET0_PERIOD = 0x03FFFFFF +const SYSTIMER_TARGET0_PERIOD_V = 0x03FFFFFF +const SYSTIMER_TARGET0_PERIOD_S = 0 +const SYSTIMER_TARGET0_PERIOD_MODE_V = 0x00000001 +const SYSTIMER_TARGET0_PERIOD_MODE_S = 30 +const SYSTIMER_TARGET0_TIMER_UNIT_SEL_V = 0x00000001 +const SYSTIMER_TARGET0_TIMER_UNIT_SEL_S = 31 +const SYSTIMER_TARGET1_PERIOD = 0x03FFFFFF +const SYSTIMER_TARGET1_PERIOD_V = 0x03FFFFFF +const SYSTIMER_TARGET1_PERIOD_S = 0 +const SYSTIMER_TARGET1_PERIOD_MODE_V = 0x00000001 +const SYSTIMER_TARGET1_PERIOD_MODE_S = 30 +const SYSTIMER_TARGET1_TIMER_UNIT_SEL_V = 0x00000001 +const SYSTIMER_TARGET1_TIMER_UNIT_SEL_S = 31 +const SYSTIMER_TARGET2_PERIOD = 0x03FFFFFF +const SYSTIMER_TARGET2_PERIOD_V = 0x03FFFFFF +const SYSTIMER_TARGET2_PERIOD_S = 0 +const SYSTIMER_TARGET2_PERIOD_MODE_V = 0x00000001 +const SYSTIMER_TARGET2_PERIOD_MODE_S = 30 +const SYSTIMER_TARGET2_TIMER_UNIT_SEL_V = 0x00000001 +const SYSTIMER_TARGET2_TIMER_UNIT_SEL_S = 31 +const SYSTIMER_TIMER_UNIT0_VALUE_HI = 0x000FFFFF +const SYSTIMER_TIMER_UNIT0_VALUE_HI_V = 0x000FFFFF +const SYSTIMER_TIMER_UNIT0_VALUE_HI_S = 0 +const SYSTIMER_TIMER_UNIT0_VALUE_LO = 0xFFFFFFFF +const SYSTIMER_TIMER_UNIT0_VALUE_LO_V = 0xFFFFFFFF +const SYSTIMER_TIMER_UNIT0_VALUE_LO_S = 0 +const SYSTIMER_TIMER_UNIT1_VALUE_HI = 0x000FFFFF +const SYSTIMER_TIMER_UNIT1_VALUE_HI_V = 0x000FFFFF +const SYSTIMER_TIMER_UNIT1_VALUE_HI_S = 0 +const SYSTIMER_TIMER_UNIT1_VALUE_LO = 0xFFFFFFFF +const SYSTIMER_TIMER_UNIT1_VALUE_LO_V = 0xFFFFFFFF +const SYSTIMER_TIMER_UNIT1_VALUE_LO_S = 0 +const SYSTIMER_TIMER_COMP0_LOAD_V = 0x00000001 +const SYSTIMER_TIMER_COMP0_LOAD_S = 0 +const SYSTIMER_TIMER_COMP1_LOAD_V = 0x00000001 +const SYSTIMER_TIMER_COMP1_LOAD_S = 0 +const SYSTIMER_TIMER_COMP2_LOAD_V = 0x00000001 +const SYSTIMER_TIMER_COMP2_LOAD_S = 0 +const SYSTIMER_TIMER_UNIT0_LOAD_V = 0x00000001 +const SYSTIMER_TIMER_UNIT0_LOAD_S = 0 +const SYSTIMER_TIMER_UNIT1_LOAD_V = 0x00000001 +const SYSTIMER_TIMER_UNIT1_LOAD_S = 0 +const SYSTIMER_TARGET0_INT_ENA_V = 0x00000001 +const SYSTIMER_TARGET0_INT_ENA_S = 0 +const SYSTIMER_TARGET1_INT_ENA_V = 0x00000001 +const SYSTIMER_TARGET1_INT_ENA_S = 1 +const SYSTIMER_TARGET2_INT_ENA_V = 0x00000001 +const SYSTIMER_TARGET2_INT_ENA_S = 2 +const SYSTIMER_TARGET0_INT_RAW_V = 0x00000001 +const SYSTIMER_TARGET0_INT_RAW_S = 0 +const SYSTIMER_TARGET1_INT_RAW_V = 0x00000001 +const SYSTIMER_TARGET1_INT_RAW_S = 1 +const SYSTIMER_TARGET2_INT_RAW_V = 0x00000001 +const SYSTIMER_TARGET2_INT_RAW_S = 2 +const SYSTIMER_TARGET0_INT_CLR_V = 0x00000001 +const SYSTIMER_TARGET0_INT_CLR_S = 0 +const SYSTIMER_TARGET1_INT_CLR_V = 0x00000001 +const SYSTIMER_TARGET1_INT_CLR_S = 1 +const SYSTIMER_TARGET2_INT_CLR_V = 0x00000001 +const SYSTIMER_TARGET2_INT_CLR_S = 2 +const SYSTIMER_TARGET0_INT_ST_V = 0x00000001 +const SYSTIMER_TARGET0_INT_ST_S = 0 +const SYSTIMER_TARGET1_INT_ST_V = 0x00000001 +const SYSTIMER_TARGET1_INT_ST_S = 1 +const SYSTIMER_TARGET2_INT_ST_V = 0x00000001 +const SYSTIMER_TARGET2_INT_ST_S = 2 +const SYSTIMER_TARGET0_LO_RO = 0xFFFFFFFF +const SYSTIMER_TARGET0_LO_RO_V = 0xFFFFFFFF +const SYSTIMER_TARGET0_LO_RO_S = 0 +const SYSTIMER_TARGET0_HI_RO = 0x000FFFFF +const SYSTIMER_TARGET0_HI_RO_V = 0x000FFFFF +const SYSTIMER_TARGET0_HI_RO_S = 0 +const SYSTIMER_TARGET1_LO_RO = 0xFFFFFFFF +const SYSTIMER_TARGET1_LO_RO_V = 0xFFFFFFFF +const SYSTIMER_TARGET1_LO_RO_S = 0 +const SYSTIMER_TARGET1_HI_RO = 0x000FFFFF +const SYSTIMER_TARGET1_HI_RO_V = 0x000FFFFF +const SYSTIMER_TARGET1_HI_RO_S = 0 +const SYSTIMER_TARGET2_LO_RO = 0xFFFFFFFF +const SYSTIMER_TARGET2_LO_RO_V = 0xFFFFFFFF +const SYSTIMER_TARGET2_LO_RO_S = 0 +const SYSTIMER_TARGET2_HI_RO = 0x000FFFFF +const SYSTIMER_TARGET2_HI_RO_V = 0x000FFFFF +const SYSTIMER_TARGET2_HI_RO_S = 0 +const SYSTIMER_DATE = 0xFFFFFFFF +const SYSTIMER_DATE_V = 0xFFFFFFFF +const SYSTIMER_DATE_S = 0 diff --git a/esp32/systimer_struct.go b/esp32/systimer_struct.go new file mode 100644 index 00000000..97c299dd --- /dev/null +++ b/esp32/systimer_struct.go @@ -0,0 +1,186 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** SYSTEM TIMER CLK CONTROL REGISTER */ +/** Type of conf register + * Configure system timer clock + */ + +type SystimerConfRegT struct { + Val c.Uint32T +} + +/** Type of unit_op register + * SYSTIMER_UNIT_OP. + */ + +type SystimerUnitOpRegT struct { + Val c.Uint32T +} + +/** Type of unit_load register + * SYSTIMER_UNIT_LOAD + */ + +type SystimerUnitLoadValRegT struct { + Hi struct { + Val c.Uint32T + } + Lo struct { + Val c.Uint32T + } +} + +/** Type of target register + * SYSTIMER_TARGET. + */ + +type SystimerTargetValRegT struct { + Hi struct { + Val c.Uint32T + } + Lo struct { + Val c.Uint32T + } +} + +/** Type of target_conf register + * SYSTIMER_TARGET_CONF. + */ + +type SystimerTargetConfRegT struct { + Val c.Uint32T +} + +/** Type of unit_value_hi register + * SYSTIMER_UNIT_VALUE_HI. + */ + +type SystimerUnitValueRegT struct { + Hi struct { + Val c.Uint32T + } + Lo struct { + Val c.Uint32T + } +} + +/** Type of comp_load register + * SYSTIMER_COMP_LOAD. + */ + +type SystimerCompLoadRegT struct { + Val c.Uint32T +} + +/** Type of unit_load register + * SYSTIMER_UNIT_LOAD. + */ + +type SystimerUnitLoadRegT struct { + Val c.Uint32T +} + +/** SYSTEM TIMER INTERRUPT REGISTER */ +/** Type of int_ena register + * systimer interrupt enable register + */ + +type SystimerIntEnaRegT struct { + Val c.Uint32T +} + +/** Type of int_raw register + * systimer interrupt raw register + */ + +type SystimerIntRawRegT struct { + Val c.Uint32T +} + +/** Type of int_clr register + * systimer interrupt clear register + */ + +type SystimerIntClrRegT struct { + Val c.Uint32T +} + +/** Type of int_st register + * systimer interrupt status register + */ + +type SystimerIntStRegT struct { + Val c.Uint32T +} + +/** SYSTEM TIMER COMP STATUS REGISTER + * systimer comp actual target value low register + */ + +type SystimerRealTargetValRegT struct { + Lo struct { + Val c.Uint32T + } + Hi struct { + Val c.Uint32T + } +} + +/** VERSION REGISTER */ +/** Type of date register + * system timer version control register + */ + +type SystimerDateRegT struct { + Val c.Uint32T +} + +type SystimerDevT struct { + Conf SystimerConfRegT + UnitOp [2]SystimerUnitOpRegT + UnitLoadVal [2]SystimerUnitLoadValRegT + TargetVal [3]SystimerTargetValRegT + TargetConf [3]SystimerTargetConfRegT + UnitVal [2]SystimerUnitValueRegT + CompLoad [3]SystimerCompLoadRegT + UnitLoad [2]SystimerUnitLoadRegT + IntEna SystimerIntEnaRegT + IntRaw SystimerIntRawRegT + IntClr SystimerIntClrRegT + IntSt SystimerIntStRegT + RealTargetVal [3]SystimerRealTargetValRegT + Reserved08c c.Uint32T + Reserved090 c.Uint32T + Reserved094 c.Uint32T + Reserved098 c.Uint32T + Reserved09c c.Uint32T + Reserved0a0 c.Uint32T + Reserved0a4 c.Uint32T + Reserved0a8 c.Uint32T + Reserved0ac c.Uint32T + Reserved0b0 c.Uint32T + Reserved0b4 c.Uint32T + Reserved0b8 c.Uint32T + Reserved0bc c.Uint32T + Reserved0c0 c.Uint32T + Reserved0c4 c.Uint32T + Reserved0c8 c.Uint32T + Reserved0cc c.Uint32T + Reserved0d0 c.Uint32T + Reserved0d4 c.Uint32T + Reserved0d8 c.Uint32T + Reserved0dc c.Uint32T + Reserved0e0 c.Uint32T + Reserved0e4 c.Uint32T + Reserved0e8 c.Uint32T + Reserved0ec c.Uint32T + Reserved0f0 c.Uint32T + Reserved0f4 c.Uint32T + Reserved0f8 c.Uint32T + Date SystimerDateRegT +} diff --git a/esp32/systimer_types.go b/esp32/systimer_types.go new file mode 100644 index 00000000..3da02431 --- /dev/null +++ b/esp32/systimer_types.go @@ -0,0 +1,21 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* + * @brief The structure of the counter value in systimer + * + */ + +type SystimerCounterValueT struct { + Unused [8]uint8 +} +type SystimerAlarmModeT c.Int + +const ( + SYSTIMER_ALARM_MODE_ONESHOT SystimerAlarmModeT = 0 + SYSTIMER_ALARM_MODE_PERIOD SystimerAlarmModeT = 1 +) diff --git a/esp32/task.go b/esp32/task.go new file mode 100644 index 00000000..9b81698b --- /dev/null +++ b/esp32/task.go @@ -0,0 +1,2179 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const TskKERNEL_VERSION_NUMBER = "V10.5.1" +const TskKERNEL_VERSION_MAJOR = 10 +const TskKERNEL_VERSION_MINOR = 5 +const TskKERNEL_VERSION_BUILD = 1 + +/** + * + * Type by which tasks are referenced. For example, a call to xTaskCreate + * returns (via a pointer parameter) an TaskHandle_t variable that can then + * be used as a parameter to vTaskDelete to delete the task. + * + * \ingroup Tasks + */ + +type TskTaskControlBlock struct { + Unused [8]uint8 +} +type TaskHandleT *TskTaskControlBlock + +// llgo:type C +type TaskHookFunctionT func(c.Pointer) BaseTypeT +type ETaskState c.Int + +const ( + ERunning ETaskState = 0 + EReady ETaskState = 1 + EBlocked ETaskState = 2 + ESuspended ETaskState = 3 + EDeleted ETaskState = 4 + EInvalid ETaskState = 5 +) + +type ENotifyAction c.Int + +const ( + ENoAction ENotifyAction = 0 + ESetBits ENotifyAction = 1 + EIncrement ENotifyAction = 2 + ESetValueWithOverwrite ENotifyAction = 3 + ESetValueWithoutOverwrite ENotifyAction = 4 +) + +/* + * Used internally only. + */ + +type XTIMEOUT struct { + XOverflowCount BaseTypeT + XTimeOnEntering TickTypeT +} +type TimeOutT XTIMEOUT + +/* + * Defines the memory ranges allocated to the task when an MPU is used. + */ + +type XMEMORYREGION struct { + PvBaseAddress c.Pointer + UlLengthInBytes c.Uint32T + UlParameters c.Uint32T +} +type MemoryRegionT XMEMORYREGION + +/* + * Parameters required to create an MPU protected task. + */ + +type XTASKPARAMETERS struct { + PvTaskCode c.Int + PcName *c.Char + UsStackDepth c.Uint32T + PvParameters c.Pointer + UxPriority UBaseTypeT + PuxStackBuffer *StackTypeT + XRegions [1]MemoryRegionT +} +type TaskParametersT XTASKPARAMETERS + +/** Used with the uxTaskGetSystemState() function to return the state of each task + * in the system. */ + +type XTASKSTATUS struct { + XHandle TaskHandleT + PcTaskName *c.Char + XTaskNumber UBaseTypeT + ECurrentState ETaskState + UxCurrentPriority UBaseTypeT + UxBasePriority UBaseTypeT + UlRunTimeCounter c.Uint32T + PxStackBase *StackTypeT + UsStackHighWaterMark c.Uint32T +} +type TaskStatusT XTASKSTATUS +type ESleepModeStatus c.Int + +const ( + EAbortSleep ESleepModeStatus = 0 + EStandardSleep ESleepModeStatus = 1 + ENoTasksWaitingTimeout ESleepModeStatus = 2 +) + +/** + * + * Memory regions are assigned to a restricted task when the task is created by + * a call to xTaskCreateRestricted(). These regions can be redefined using + * vTaskAllocateMPURegions(). + * + * @param xTask The handle of the task being updated. + * + * @param pxRegions A pointer to a MemoryRegion_t structure that contains the + * new memory region definitions. + * + * Example usage: + * @code{c} + * // Define an array of MemoryRegion_t structures that configures an MPU region + * // allowing read/write access for 1024 bytes starting at the beginning of the + * // ucOneKByte array. The other two of the maximum 3 definable regions are + * // unused so set to zero. + * static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] = + * { + * // Base address Length Parameters + * { ucOneKByte, 1024, portMPU_REGION_READ_WRITE }, + * { 0, 0, 0 }, + * { 0, 0, 0 } + * }; + * + * void vATask( void *pvParameters ) + * { + * // This task was created such that it has access to certain regions of + * // memory as defined by the MPU configuration. At some point it is + * // desired that these MPU regions are replaced with that defined in the + * // xAltRegions const struct above. Use a call to vTaskAllocateMPURegions() + * // for this purpose. NULL is used as the task handle to indicate that this + * // function should modify the MPU regions of the calling task. + * vTaskAllocateMPURegions( NULL, xAltRegions ); + * + * // Now the task can continue its function, but from this point on can only + * // access its stack and the ucOneKByte array (unless any other statically + * // defined or shared regions have been declared elsewhere). + * } + * @endcode + * \ingroup Tasks + */ +//go:linkname VTaskAllocateMPURegions C.vTaskAllocateMPURegions +func VTaskAllocateMPURegions(xTask TaskHandleT, pxRegions *MemoryRegionT) + +/** + * + * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Remove a task from the RTOS real time kernel's management. The task being + * deleted will be removed from all ready, blocked, suspended and event lists. + * + * NOTE: The idle task is responsible for freeing the kernel allocated + * memory from tasks that have been deleted. It is therefore important that + * the idle task is not starved of microcontroller processing time if your + * application makes any calls to vTaskDelete (). Memory allocated by the + * task code is not automatically freed, and should be freed before the task + * is deleted. + * + * See the demo application file death.c for sample code that utilises + * vTaskDelete (). + * + * @param xTaskToDelete The handle of the task to be deleted. Passing NULL will + * cause the calling task to be deleted. + * + * Example usage: + * @code{c} + * void vOtherFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create the task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // Use the handle to delete the task. + * vTaskDelete( xHandle ); + * } + * @endcode + * \ingroup Tasks + */ +//go:linkname VTaskDelete C.vTaskDelete +func VTaskDelete(xTaskToDelete TaskHandleT) + +/** + * + * Delay a task for a given number of ticks. The actual time that the + * task remains blocked depends on the tick rate. The constant + * portTICK_PERIOD_MS can be used to calculate real time from the tick + * rate - with the resolution of one tick period. + * + * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * + * vTaskDelay() specifies a time at which the task wishes to unblock relative to + * the time at which vTaskDelay() is called. For example, specifying a block + * period of 100 ticks will cause the task to unblock 100 ticks after + * vTaskDelay() is called. vTaskDelay() does not therefore provide a good method + * of controlling the frequency of a periodic task as the path taken through the + * code, as well as other task and interrupt activity, will affect the frequency + * at which vTaskDelay() gets called and therefore the time at which the task + * next executes. See xTaskDelayUntil() for an alternative API function designed + * to facilitate fixed frequency execution. It does this by specifying an + * absolute time (rather than a relative time) at which the calling task should + * unblock. + * + * @param xTicksToDelay The amount of time, in tick periods, that + * the calling task should block. + * + * Example usage: + * @code{c} + * void vTaskFunction( void * pvParameters ) + * { + * // Block for 500ms. + * const TickType_t xDelay = 500 / portTICK_PERIOD_MS; + * + * for( ;; ) + * { + * // Simply toggle the LED every 500ms, blocking between each toggle. + * vToggleLED(); + * vTaskDelay( xDelay ); + * } + * } + * @endcode + * \ingroup TaskCtrl + */ +// llgo:link TickTypeT.VTaskDelay C.vTaskDelay +func (recv_ TickTypeT) VTaskDelay() { +} + +/** + * + * INCLUDE_xTaskDelayUntil must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Delay a task until a specified time. This function can be used by periodic + * tasks to ensure a constant execution frequency. + * + * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will + * cause a task to block for the specified number of ticks from the time vTaskDelay () is + * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed + * execution frequency as the time between a task starting to execute and that task + * calling vTaskDelay () may not be fixed [the task may take a different path though the + * code between calls, or may get interrupted or preempted a different number of times + * each time it executes]. + * + * Whereas vTaskDelay () specifies a wake time relative to the time at which the function + * is called, xTaskDelayUntil () specifies the absolute (exact) time at which it wishes to + * unblock. + * + * The macro pdMS_TO_TICKS() can be used to calculate the number of ticks from a + * time specified in milliseconds with a resolution of one tick period. + * + * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the + * task was last unblocked. The variable must be initialised with the current time + * prior to its first use (see the example below). Following this the variable is + * automatically updated within xTaskDelayUntil (). + * + * @param xTimeIncrement The cycle time period. The task will be unblocked at + * time *pxPreviousWakeTime + xTimeIncrement. Calling xTaskDelayUntil with the + * same xTimeIncrement parameter value will cause the task to execute with + * a fixed interface period. + * + * @return Value which can be used to check whether the task was actually delayed. + * Will be pdTRUE if the task way delayed and pdFALSE otherwise. A task will not + * be delayed if the next expected wake time is in the past. + * + * Example usage: + * @code{c} + * // Perform an action every 10 ticks. + * void vTaskFunction( void * pvParameters ) + * { + * TickType_t xLastWakeTime; + * const TickType_t xFrequency = 10; + * BaseType_t xWasDelayed; + * + * // Initialise the xLastWakeTime variable with the current time. + * xLastWakeTime = xTaskGetTickCount (); + * for( ;; ) + * { + * // Wait for the next cycle. + * xWasDelayed = xTaskDelayUntil( &xLastWakeTime, xFrequency ); + * + * // Perform action here. xWasDelayed value can be used to determine + * // whether a deadline was missed if the code here took too long. + * } + * } + * @endcode + * \ingroup TaskCtrl + */ +// llgo:link (*TickTypeT).XTaskDelayUntil C.xTaskDelayUntil +func (recv_ *TickTypeT) XTaskDelayUntil(xTimeIncrement TickTypeT) BaseTypeT { + return 0 +} + +/** + * + * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this + * function to be available. + * + * A task will enter the Blocked state when it is waiting for an event. The + * event it is waiting for can be a temporal event (waiting for a time), such + * as when vTaskDelay() is called, or an event on an object, such as when + * xQueueReceive() or ulTaskNotifyTake() is called. If the handle of a task + * that is in the Blocked state is used in a call to xTaskAbortDelay() then the + * task will leave the Blocked state, and return from whichever function call + * placed the task into the Blocked state. + * + * There is no 'FromISR' version of this function as an interrupt would need to + * know which object a task was blocked on in order to know which actions to + * take. For example, if the task was blocked on a queue the interrupt handler + * would then need to know if the queue was locked. + * + * @param xTask The handle of the task to remove from the Blocked state. + * + * @return If the task referenced by xTask was not in the Blocked state then + * pdFAIL is returned. Otherwise pdPASS is returned. + * + * \ingroup TaskCtrl + */ +//go:linkname XTaskAbortDelay C.xTaskAbortDelay +func XTaskAbortDelay(xTask TaskHandleT) BaseTypeT + +/** + * + * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the priority of any task. + * + * @param xTask Handle of the task to be queried. Passing a NULL + * handle results in the priority of the calling task being returned. + * + * @return The priority of xTask. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to obtain the priority of the created task. + * // It was created with tskIDLE_PRIORITY, but may have changed + * // it itself. + * if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY ) + * { + * // The task has changed it's priority. + * } + * + * // ... + * + * // Is our priority higher than the created task? + * if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) ) + * { + * // Our priority (obtained using NULL handle) is higher. + * } + * } + * @endcode + * \ingroup TaskCtrl + */ +//go:linkname UxTaskPriorityGet C.uxTaskPriorityGet +func UxTaskPriorityGet(xTask TaskHandleT) UBaseTypeT + +/** + * + * A version of uxTaskPriorityGet() that can be used from an ISR. + */ +//go:linkname UxTaskPriorityGetFromISR C.uxTaskPriorityGetFromISR +func UxTaskPriorityGetFromISR(xTask TaskHandleT) UBaseTypeT + +/** + * + * INCLUDE_eTaskGetState must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the state of any task. States are encoded by the eTaskState + * enumerated type. + * + * @param xTask Handle of the task to be queried. + * + * @return The state of xTask at the time the function was called. Note the + * state of the task might change between the function being called, and the + * functions return value being tested by the calling task. + */ +//go:linkname ETaskGetState C.eTaskGetState +func ETaskGetState(xTask TaskHandleT) ETaskState + +/** + * + * configUSE_TRACE_FACILITY must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * Populates a TaskStatus_t structure with information about a task. + * + * @param xTask Handle of the task being queried. If xTask is NULL then + * information will be returned about the calling task. + * + * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be + * filled with information about the task referenced by the handle passed using + * the xTask parameter. + * + * @param xGetFreeStackSpace The TaskStatus_t structure contains a member to report + * the stack high water mark of the task being queried. Calculating the stack + * high water mark takes a relatively long time, and can make the system + * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to + * allow the high water mark checking to be skipped. The high watermark value + * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is + * not set to pdFALSE; + * + * @param eState The TaskStatus_t structure contains a member to report the + * state of the task being queried. Obtaining the task state is not as fast as + * a simple assignment - so the eState parameter is provided to allow the state + * information to be omitted from the TaskStatus_t structure. To obtain state + * information then set eState to eInvalid - otherwise the value passed in + * eState will be reported as the task state in the TaskStatus_t structure. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * TaskStatus_t xTaskDetails; + * + * // Obtain the handle of a task from its name. + * xHandle = xTaskGetHandle( "Task_Name" ); + * + * // Check the handle is not NULL. + * configASSERT( xHandle ); + * + * // Use the handle to obtain further information about the task. + * vTaskGetInfo( xHandle, + * &xTaskDetails, + * pdTRUE, // Include the high water mark in xTaskDetails. + * eInvalid ); // Include the task state in xTaskDetails. + * } + * @endcode + * \ingroup TaskCtrl + */ +//go:linkname VTaskGetInfo C.vTaskGetInfo +func VTaskGetInfo(xTask TaskHandleT, pxTaskStatus *TaskStatusT, xGetFreeStackSpace BaseTypeT, eState ETaskState) + +/** + * + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Set the priority of any task. + * + * A context switch will occur before the function returns if the priority + * being set is higher than the currently executing task. + * + * @param xTask Handle to the task for which the priority is being set. + * Passing a NULL handle results in the priority of the calling task being set. + * + * @param uxNewPriority The priority to which the task will be set. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to raise the priority of the created task. + * vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 ); + * + * // ... + * + * // Use a NULL handle to raise our priority to the same value. + * vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 ); + * } + * @endcode + * \ingroup TaskCtrl + */ +//go:linkname VTaskPrioritySet C.vTaskPrioritySet +func VTaskPrioritySet(xTask TaskHandleT, uxNewPriority UBaseTypeT) + +/** + * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Suspend any task. When suspended a task will never get any microcontroller + * processing time, no matter what its priority. + * + * Calls to vTaskSuspend are not accumulative - + * i.e. calling vTaskSuspend () twice on the same task still only requires one + * call to vTaskResume () to ready the suspended task. + * + * @param xTaskToSuspend Handle to the task being suspended. Passing a NULL + * handle will cause the calling task to be suspended. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to suspend the created task. + * vTaskSuspend( xHandle ); + * + * // ... + * + * // The created task will not run during this period, unless + * // another task calls vTaskResume( xHandle ). + * + * //... + * + * + * // Suspend ourselves. + * vTaskSuspend( NULL ); + * + * // We cannot get here unless another task calls vTaskResume + * // with our handle as the parameter. + * } + * @endcode + * \ingroup TaskCtrl + */ +//go:linkname VTaskSuspend C.vTaskSuspend +func VTaskSuspend(xTaskToSuspend TaskHandleT) + +/** + * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Resumes a suspended task. + * + * A task that has been suspended by one or more calls to vTaskSuspend () + * will be made available for running again by a single call to + * vTaskResume (). + * + * @param xTaskToResume Handle to the task being readied. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to suspend the created task. + * vTaskSuspend( xHandle ); + * + * // ... + * + * // The created task will not run during this period, unless + * // another task calls vTaskResume( xHandle ). + * + * //... + * + * + * // Resume the suspended task ourselves. + * vTaskResume( xHandle ); + * + * // The created task will once again get microcontroller processing + * // time in accordance with its priority within the system. + * } + * @endcode + * \ingroup TaskCtrl + */ +//go:linkname VTaskResume C.vTaskResume +func VTaskResume(xTaskToResume TaskHandleT) + +/** + * + * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * An implementation of vTaskResume() that can be called from within an ISR. + * + * A task that has been suspended by one or more calls to vTaskSuspend () + * will be made available for running again by a single call to + * xTaskResumeFromISR (). + * + * xTaskResumeFromISR() should not be used to synchronise a task with an + * interrupt if there is a chance that the interrupt could arrive prior to the + * task being suspended - as this can lead to interrupts being missed. Use of a + * semaphore as a synchronisation mechanism would avoid this eventuality. + * + * @param xTaskToResume Handle to the task being readied. + * + * @return pdTRUE if resuming the task should result in a context switch, + * otherwise pdFALSE. This is used by the ISR to determine if a context switch + * may be required following the ISR. + * + * \ingroup TaskCtrl + */ +//go:linkname XTaskResumeFromISR C.xTaskResumeFromISR +func XTaskResumeFromISR(xTaskToResume TaskHandleT) BaseTypeT + +/** + * + * Starts the real time kernel tick processing. After calling the kernel + * has control over which tasks are executed and when. + * + * See the demo application file main.c for an example of creating + * tasks and starting the kernel. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * // Create at least one task before starting the kernel. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + * + * // Start the real time kernel with preemption. + * vTaskStartScheduler (); + * + * // Will not get here unless a task calls vTaskEndScheduler () + * } + * @endcode + * + * \ingroup SchedulerControl + */ +//go:linkname VTaskStartScheduler C.vTaskStartScheduler +func VTaskStartScheduler() + +/** + * + * NOTE: At the time of writing only the x86 real mode port, which runs on a PC + * in place of DOS, implements this function. + * + * Stops the real time kernel tick. All created tasks will be automatically + * deleted and multitasking (either preemptive or cooperative) will + * stop. Execution then resumes from the point where vTaskStartScheduler () + * was called, as if vTaskStartScheduler () had just returned. + * + * See the demo application file main. c in the demo/PC directory for an + * example that uses vTaskEndScheduler (). + * + * vTaskEndScheduler () requires an exit function to be defined within the + * portable layer (see vPortEndScheduler () in port. c for the PC port). This + * performs hardware specific operations such as stopping the kernel tick. + * + * vTaskEndScheduler () will cause all of the resources allocated by the + * kernel to be freed - but will not free resources allocated by application + * tasks. + * + * Example usage: + * @code{c} + * void vTaskCode( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * + * // At some point we want to end the real time kernel processing + * // so call ... + * vTaskEndScheduler (); + * } + * } + * + * void vAFunction( void ) + * { + * // Create at least one task before starting the kernel. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + * + * // Start the real time kernel with preemption. + * vTaskStartScheduler (); + * + * // Will only get here when the vTaskCode () task has called + * // vTaskEndScheduler (). When we get here we are back to single task + * // execution. + * } + * @endcode + * + * \ingroup SchedulerControl + */ +//go:linkname VTaskEndScheduler C.vTaskEndScheduler +func VTaskEndScheduler() + +/** + * + * Suspends the scheduler without disabling interrupts. Context switches will + * not occur while the scheduler is suspended. + * + * After calling vTaskSuspendAll () the calling task will continue to execute + * without risk of being swapped out until a call to xTaskResumeAll () has been + * made. + * + * API functions that have the potential to cause a context switch (for example, + * xTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler + * is suspended. + * + * Example usage: + * @code{c} + * void vTask1( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * + * // ... + * + * // At some point the task wants to perform a long operation during + * // which it does not want to get swapped out. It cannot use + * // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the + * // operation may cause interrupts to be missed - including the + * // ticks. + * + * // Prevent the real time kernel swapping out the task. + * vTaskSuspendAll (); + * + * // Perform the operation here. There is no need to use critical + * // sections as we have all the microcontroller processing time. + * // During this time interrupts will still operate and the kernel + * // tick count will be maintained. + * + * // ... + * + * // The operation is complete. Restart the kernel. + * xTaskResumeAll (); + * } + * } + * @endcode + * \ingroup SchedulerControl + */ +//go:linkname VTaskSuspendAll C.vTaskSuspendAll +func VTaskSuspendAll() + +/** + * + * Resumes scheduler activity after it was suspended by a call to + * vTaskSuspendAll(). + * + * xTaskResumeAll() only resumes the scheduler. It does not unsuspend tasks + * that were previously suspended by a call to vTaskSuspend(). + * + * @return If resuming the scheduler caused a context switch then pdTRUE is + * returned, otherwise pdFALSE is returned. + * + * Example usage: + * @code{c} + * void vTask1( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * + * // ... + * + * // At some point the task wants to perform a long operation during + * // which it does not want to get swapped out. It cannot use + * // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the + * // operation may cause interrupts to be missed - including the + * // ticks. + * + * // Prevent the real time kernel swapping out the task. + * vTaskSuspendAll (); + * + * // Perform the operation here. There is no need to use critical + * // sections as we have all the microcontroller processing time. + * // During this time interrupts will still operate and the real + * // time kernel tick count will be maintained. + * + * // ... + * + * // The operation is complete. Restart the kernel. We want to force + * // a context switch - but there is no point if resuming the scheduler + * // caused a context switch already. + * if( !xTaskResumeAll () ) + * { + * taskYIELD (); + * } + * } + * } + * @endcode + * \ingroup SchedulerControl + */ +//go:linkname XTaskResumeAll C.xTaskResumeAll +func XTaskResumeAll() BaseTypeT + +/** + * + * @return The count of ticks since vTaskStartScheduler was called. + * + * \ingroup TaskUtils + */ +//go:linkname XTaskGetTickCount C.xTaskGetTickCount +func XTaskGetTickCount() TickTypeT + +/** + * + * @return The count of ticks since vTaskStartScheduler was called. + * + * This is a version of xTaskGetTickCount() that is safe to be called from an + * ISR - provided that TickType_t is the natural word size of the + * microcontroller being used or interrupt nesting is either not supported or + * not being used. + * + * \ingroup TaskUtils + */ +//go:linkname XTaskGetTickCountFromISR C.xTaskGetTickCountFromISR +func XTaskGetTickCountFromISR() TickTypeT + +/** + * + * @return The number of tasks that the real time kernel is currently managing. + * This includes all ready, blocked and suspended tasks. A task that + * has been deleted but not yet freed by the idle task will also be + * included in the count. + * + * \ingroup TaskUtils + */ +//go:linkname UxTaskGetNumberOfTasks C.uxTaskGetNumberOfTasks +func UxTaskGetNumberOfTasks() UBaseTypeT + +/** + * + * @return The text (human readable) name of the task referenced by the handle + * xTaskToQuery. A task can query its own name by either passing in its own + * handle, or by setting xTaskToQuery to NULL. + * + * \ingroup TaskUtils + */ +//go:linkname PcTaskGetName C.pcTaskGetName +func PcTaskGetName(xTaskToQuery TaskHandleT) *c.Char + +/** + * + * NOTE: This function takes a relatively long time to complete and should be + * used sparingly. + * + * @return The handle of the task that has the human readable name pcNameToQuery. + * NULL is returned if no matching name is found. INCLUDE_xTaskGetHandle + * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available. + * + * \ingroup TaskUtils + */ +//go:linkname XTaskGetHandle C.xTaskGetHandle +func XTaskGetHandle(pcNameToQuery *c.Char) TaskHandleT + +/** + * + * Retrieve pointers to a statically created task's data structure + * buffer and stack buffer. These are the same buffers that are supplied + * at the time of creation. + * + * @param xTask The task for which to retrieve the buffers. + * + * @param ppuxStackBuffer Used to return a pointer to the task's stack buffer. + * + * @param ppxTaskBuffer Used to return a pointer to the task's data structure + * buffer. + * + * @return pdTRUE if buffers were retrieved, pdFALSE otherwise. + * + * \ingroup TaskUtils + */ +//go:linkname XTaskGetStaticBuffers C.xTaskGetStaticBuffers +func XTaskGetStaticBuffers(xTask TaskHandleT, ppuxStackBuffer **StackTypeT, ppxTaskBuffer **StaticTaskT) BaseTypeT + +/** + * + * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the high water mark of the stack associated with xTask. That is, + * the minimum free stack space there has been (in words, so on a 32 bit machine + * a value of 1 means 4 bytes) since the task started. The smaller the returned + * number the closer the task has come to overflowing its stack. + * + * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. + * + * @param xTask Handle of the task associated with the stack to be checked. + * Set xTask to NULL to check the stack of the calling task. + * + * @return The smallest amount of free stack space there has been (in words, so + * actual spaces on the stack rather than bytes) since the task referenced by + * xTask was created. + */ +//go:linkname UxTaskGetStackHighWaterMark C.uxTaskGetStackHighWaterMark +func UxTaskGetStackHighWaterMark(xTask TaskHandleT) UBaseTypeT + +/** + * + * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the high water mark of the stack associated with xTask. That is, + * the minimum free stack space there has been (in words, so on a 32 bit machine + * a value of 1 means 4 bytes) since the task started. The smaller the returned + * number the closer the task has come to overflowing its stack. + * + * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. + * + * @param xTask Handle of the task associated with the stack to be checked. + * Set xTask to NULL to check the stack of the calling task. + * + * @return The smallest amount of free stack space there has been (in words, so + * actual spaces on the stack rather than bytes) since the task referenced by + * xTask was created. + */ +//go:linkname UxTaskGetStackHighWaterMark2 C.uxTaskGetStackHighWaterMark2 +func UxTaskGetStackHighWaterMark2(xTask TaskHandleT) c.Uint32T + +/** Each task contains an array of pointers that is dimensioned by the + * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. The + * kernel does not use the pointers itself, so the application writer can use + * the pointers for any purpose they wish. The following two functions are + * used to set and query a pointer respectively. */ +//go:linkname VTaskSetThreadLocalStoragePointer C.vTaskSetThreadLocalStoragePointer +func VTaskSetThreadLocalStoragePointer(xTaskToSet TaskHandleT, xIndex BaseTypeT, pvValue c.Pointer) + +//go:linkname PvTaskGetThreadLocalStoragePointer C.pvTaskGetThreadLocalStoragePointer +func PvTaskGetThreadLocalStoragePointer(xTaskToQuery TaskHandleT, xIndex BaseTypeT) c.Pointer + +/** + * + * The application stack overflow hook is called when a stack overflow is detected for a task. + * + * Details on stack overflow detection can be found here: https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html + * + * @param xTask the task that just exceeded its stack boundaries. + * @param pcTaskName A character string containing the name of the offending task. + */ +//go:linkname VApplicationStackOverflowHook C.vApplicationStackOverflowHook +func VApplicationStackOverflowHook(xTask TaskHandleT, pcTaskName *c.Char) + +/** + * + * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Task TCB. This function is required when + * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION + * + * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer + * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task + * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer + */ +//go:linkname VApplicationGetIdleTaskMemory C.vApplicationGetIdleTaskMemory +func VApplicationGetIdleTaskMemory(ppxIdleTaskTCBBuffer **StaticTaskT, ppxIdleTaskStackBuffer **StackTypeT, pulIdleTaskStackSize *c.Uint32T) + +/** + * + * Calls the hook function associated with xTask. Passing xTask as NULL has + * the effect of calling the Running tasks (the calling task) hook function. + * + * pvParameter is passed to the hook function for the task to interpret as it + * wants. The return value is the value returned by the task hook function + * registered by the user. + */ +//go:linkname XTaskCallApplicationTaskHook C.xTaskCallApplicationTaskHook +func XTaskCallApplicationTaskHook(xTask TaskHandleT, pvParameter c.Pointer) BaseTypeT + +/** + * xTaskGetIdleTaskHandle() is only available if + * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h. + * + * Simply returns the handle of the idle task of the current core. It is not + * valid to call xTaskGetIdleTaskHandle() before the scheduler has been started. + */ +//go:linkname XTaskGetIdleTaskHandle C.xTaskGetIdleTaskHandle +func XTaskGetIdleTaskHandle() TaskHandleT + +/** + * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for + * uxTaskGetSystemState() to be available. + * + * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in + * the system. TaskStatus_t structures contain, among other things, members + * for the task handle, task name, task priority, task state, and total amount + * of run time consumed by the task. See the TaskStatus_t structure + * definition in this file for the full member list. + * + * NOTE: This function is intended for debugging use only as its use results in + * the scheduler remaining suspended for an extended period. + * + * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures. + * The array must contain at least one TaskStatus_t structure for each task + * that is under the control of the RTOS. The number of tasks under the control + * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function. + * + * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray + * parameter. The size is specified as the number of indexes in the array, or + * the number of TaskStatus_t structures contained in the array, not by the + * number of bytes in the array. + * + * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in + * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the + * total run time (as defined by the run time stats clock, see + * https://www.FreeRTOS.org/rtos-run-time-stats.html) since the target booted. + * pulTotalRunTime can be set to NULL to omit the total run time information. + * + * @return The number of TaskStatus_t structures that were populated by + * uxTaskGetSystemState(). This should equal the number returned by the + * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed + * in the uxArraySize parameter was too small. + * + * Example usage: + * @code{c} + * // This example demonstrates how a human readable table of run time stats + * // information is generated from raw data provided by uxTaskGetSystemState(). + * // The human readable table is written to pcWriteBuffer + * void vTaskGetRunTimeStats( char *pcWriteBuffer ) + * { + * TaskStatus_t *pxTaskStatusArray; + * volatile UBaseType_t uxArraySize, x; + * configRUN_TIME_COUNTER_TYPE ulTotalRunTime, ulStatsAsPercentage; + * + * // Make sure the write buffer does not contain a string. + * pcWriteBuffer = 0x00; + * + * // Take a snapshot of the number of tasks in case it changes while this + * // function is executing. + * uxArraySize = uxTaskGetNumberOfTasks(); + * + * // Allocate a TaskStatus_t structure for each task. An array could be + * // allocated statically at compile time. + * pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) ); + * + * if( pxTaskStatusArray != NULL ) + * { + * // Generate raw status information about each task. + * uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime ); + * + * // For percentage calculations. + * ulTotalRunTime /= 100UL; + * + * // Avoid divide by zero errors. + * if( ulTotalRunTime > 0 ) + * { + * // For each populated position in the pxTaskStatusArray array, + * // format the raw data as human readable ASCII data + * for( x = 0; x < uxArraySize; x++ ) + * { + * // What percentage of the total run time has the task used? + * // This will always be rounded down to the nearest integer. + * // ulTotalRunTimeDiv100 has already been divided by 100. + * ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime; + * + * if( ulStatsAsPercentage > 0UL ) + * { + * sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage ); + * } + * else + * { + * // If the percentage is zero here then the task has + * // consumed less than 1% of the total run time. + * sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter ); + * } + * + * pcWriteBuffer += strlen( ( char * ) pcWriteBuffer ); + * } + * } + * + * // The array is no longer needed, free the memory it consumes. + * vPortFree( pxTaskStatusArray ); + * } + * } + * @endcode + */ +// llgo:link (*TaskStatusT).UxTaskGetSystemState C.uxTaskGetSystemState +func (recv_ *TaskStatusT) UxTaskGetSystemState(uxArraySize UBaseTypeT, pulTotalRunTime *c.Uint32T) UBaseTypeT { + return 0 +} + +/** + * + * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must + * both be defined as 1 for this function to be available. See the + * configuration section of the FreeRTOS.org website for more information. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Lists all the current tasks, along with their current state and stack + * usage high water mark. + * + * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or + * suspended ('S'). + * + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskList() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays task: + * names, states, priority, stack usage and task number. + * Stack usage specified as the number of unused StackType_t words stack can hold + * on top of stack - not the number of bytes. + * + * vTaskList() has a dependency on the sprintf() C library function that might + * bloat the code size, use a lot of stack, and provide different results on + * different platforms. An alternative, tiny, third party, and limited + * functionality implementation of sprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly through a + * call to vTaskList(). + * + * @param pcWriteBuffer A buffer into which the above mentioned details + * will be written, in ASCII form. This buffer is assumed to be large + * enough to contain the generated report. Approximately 40 bytes per + * task should be sufficient. + * + * \ingroup TaskUtils + */ +//go:linkname VTaskList C.vTaskList +func VTaskList(pcWriteBuffer *c.Char) + +/** + * + * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS + * must both be defined as 1 for this function to be available. The application + * must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() + * to configure a peripheral timer/counter and return the timers current count + * value respectively. The counter should be at least 10 times the frequency of + * the tick count. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * Calling vTaskGetRunTimeStats() writes the total execution time of each + * task into a buffer, both as an absolute count value and as a percentage + * of the total system execution time. + * + * NOTE 2: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays the + * amount of time each task has spent in the Running state in both absolute and + * percentage terms. + * + * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function + * that might bloat the code size, use a lot of stack, and provide different + * results on different platforms. An alternative, tiny, third party, and + * limited functionality implementation of sprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() directly + * to get access to raw stats data, rather than indirectly through a call to + * vTaskGetRunTimeStats(). + * + * @param pcWriteBuffer A buffer into which the execution times will be + * written, in ASCII form. This buffer is assumed to be large enough to + * contain the generated report. Approximately 40 bytes per task should + * be sufficient. + * + * \ingroup TaskUtils + */ +//go:linkname VTaskGetRunTimeStats C.vTaskGetRunTimeStats +func VTaskGetRunTimeStats(pcWriteBuffer *c.Char) + +/** + * + * configGENERATE_RUN_TIME_STATS, configUSE_STATS_FORMATTING_FUNCTIONS and + * INCLUDE_xTaskGetIdleTaskHandle must all be defined as 1 for these functions + * to be available. The application must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() + * to configure a peripheral timer/counter and return the timers current count + * value respectively. The counter should be at least 10 times the frequency of + * the tick count. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total + * execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter() + * returns the total execution time of just the idle task and + * ulTaskGetIdleRunTimePercent() returns the percentage of the CPU time used by + * just the idle task. + * + * Note the amount of idle time is only a good measure of the slack time in a + * system if there are no other tasks executing at the idle priority, tickless + * idle is not used, and configIDLE_SHOULD_YIELD is set to 0. + * + * @note If configNUMBER_OF_CORES > 1, calling this function will query the idle + * task of the current core. + * + * @return The total run time of the idle task or the percentage of the total + * run time consumed by the idle task. This is the amount of time the + * idle task has actually been executing. The unit of time is dependent on the + * frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and + * portGET_RUN_TIME_COUNTER_VALUE() macros. + * + * \ingroup TaskUtils + */ +//go:linkname UlTaskGetIdleRunTimeCounter C.ulTaskGetIdleRunTimeCounter +func UlTaskGetIdleRunTimeCounter() c.Uint32T + +//go:linkname UlTaskGetIdleRunTimePercent C.ulTaskGetIdleRunTimePercent +func UlTaskGetIdleRunTimePercent() c.Uint32T + +/** + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Sends a direct to task notification to a task, with an optional value and + * action. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A task can use xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() to + * [optionally] block to wait for a notification to be pending. The task does + * not consume any CPU time while it is in the Blocked state. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotify() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotify() is equivalent to calling xTaskNotifyIndexed() + * with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotify() does + * not have this parameter and always sends notifications to index 0. + * + * @param ulValue Data that can be sent with the notification. How the data is + * used depends on the value of the eAction parameter. + * + * @param eAction Specifies how the notification updates the task's notification + * value, if at all. Valid values for eAction are as follows: + * + * eSetBits - + * The target notification value is bitwise ORed with ulValue. + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eIncrement - + * The target notification value is incremented. ulValue is not used and + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eSetValueWithOverwrite - + * The target notification value is set to the value of ulValue, even if the + * task being notified had not yet processed the previous notification at the + * same array index (the task already had a notification pending at that index). + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eSetValueWithoutOverwrite - + * If the task being notified did not already have a notification pending at the + * same array index then the target notification value is set to ulValue and + * xTaskNotifyIndexed() will return pdPASS. If the task being notified already + * had a notification pending at the same array index then no action is + * performed and pdFAIL is returned. + * + * eNoAction - + * The task receives a notification at the specified array index without the + * notification value at that index being updated. ulValue is not used and + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * pulPreviousNotificationValue - + * Can be used to pass out the subject task's notification value before any + * bits are modified by the notify function. + * + * @return Dependent on the value of eAction. See the description of the + * eAction parameter. + * + * \ingroup TaskNotifications + */ +/** @cond !DOC_EXCLUDE_HEADER_SECTION */ +//go:linkname XTaskGenericNotify C.xTaskGenericNotify +func XTaskGenericNotify(xTaskToNotify TaskHandleT, uxIndexToNotify UBaseTypeT, ulValue c.Uint32T, eAction ENotifyAction, pulPreviousNotificationValue *c.Uint32T) BaseTypeT + +/** + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * A version of xTaskNotifyIndexed() that can be used from an interrupt service + * routine (ISR). + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block + * to wait for a notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyFromISR() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyFromISR() is equivalent to calling + * xTaskNotifyIndexedFromISR() with the uxIndexToNotify parameter set to 0. + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyFromISR() + * does not have this parameter and always sends notifications to index 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param ulValue Data that can be sent with the notification. How the data is + * used depends on the value of the eAction parameter. + * + * @param eAction Specifies how the notification updates the task's notification + * value, if at all. Valid values for eAction are as follows: + * + * eSetBits - + * The task's notification value is bitwise ORed with ulValue. xTaskNotify() + * always returns pdPASS in this case. + * + * eIncrement - + * The task's notification value is incremented. ulValue is not used and + * xTaskNotify() always returns pdPASS in this case. + * + * eSetValueWithOverwrite - + * The task's notification value is set to the value of ulValue, even if the + * task being notified had not yet processed the previous notification (the + * task already had a notification pending). xTaskNotify() always returns + * pdPASS in this case. + * + * eSetValueWithoutOverwrite - + * If the task being notified did not already have a notification pending then + * the task's notification value is set to ulValue and xTaskNotify() will + * return pdPASS. If the task being notified already had a notification + * pending then no action is performed and pdFAIL is returned. + * + * eNoAction - + * The task receives a notification without its notification value being + * updated. ulValue is not used and xTaskNotify() always returns pdPASS in + * this case. + * + * @param pxHigherPriorityTaskWoken xTaskNotifyFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the + * task to which the notification was sent to leave the Blocked state, and the + * unblocked task has a priority higher than the currently running task. If + * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should + * be requested before the interrupt is exited. How a context switch is + * requested from an ISR is dependent on the port - see the documentation page + * for the port in use. + * + * @return Dependent on the value of eAction. See the description of the + * eAction parameter. + * + * \ingroup TaskNotifications + */ +/** @cond !DOC_EXCLUDE_HEADER_SECTION */ +//go:linkname XTaskGenericNotifyFromISR C.xTaskGenericNotifyFromISR +func XTaskGenericNotifyFromISR(xTaskToNotify TaskHandleT, uxIndexToNotify UBaseTypeT, ulValue c.Uint32T, eAction ENotifyAction, pulPreviousNotificationValue *c.Uint32T, pxHigherPriorityTaskWoken *BaseTypeT) BaseTypeT + +/** + * + * Waits for a direct to task notification to be pending at a given index within + * an array of direct to task notifications. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block + * to wait for a notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyWait() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotifyWait() is equivalent to calling + * xTaskNotifyWaitIndexed() with the uxIndexToWaitOn parameter set to 0. + * + * @param uxIndexToWaitOn The index within the calling task's array of + * notification values on which the calling task will wait for a notification to + * be received. uxIndexToWaitOn must be less than + * configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyWait() does + * not have this parameter and always waits for notifications on index 0. + * + * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value + * will be cleared in the calling task's notification value before the task + * checks to see if any notifications are pending, and optionally blocks if no + * notifications are pending. Setting ulBitsToClearOnEntry to ULONG_MAX (if + * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have + * the effect of resetting the task's notification value to 0. Setting + * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged. + * + * @param ulBitsToClearOnExit If a notification is pending or received before + * the calling task exits the xTaskNotifyWait() function then the task's + * notification value (see the xTaskNotify() API function) is passed out using + * the pulNotificationValue parameter. Then any bits that are set in + * ulBitsToClearOnExit will be cleared in the task's notification value (note + * *pulNotificationValue is set before any bits are cleared). Setting + * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL + * (if limits.h is not included) will have the effect of resetting the task's + * notification value to 0 before the function exits. Setting + * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged + * when the function exits (in which case the value passed out in + * pulNotificationValue will match the task's notification value). + * + * @param pulNotificationValue Used to pass the task's notification value out + * of the function. Note the value passed out will not be effected by the + * clearing of any bits caused by ulBitsToClearOnExit being non-zero. + * + * @param xTicksToWait The maximum amount of time that the task should wait in + * the Blocked state for a notification to be received, should a notification + * not already be pending when xTaskNotifyWait() was called. The task + * will not consume any processing time while it is in the Blocked state. This + * is specified in kernel ticks, the macro pdMS_TO_TICKS( value_in_ms ) can be + * used to convert a time specified in milliseconds to a time specified in + * ticks. + * + * @return If a notification was received (including notifications that were + * already pending when xTaskNotifyWait was called) then pdPASS is + * returned. Otherwise pdFAIL is returned. + * + * \ingroup TaskNotifications + */ +// llgo:link UBaseTypeT.XTaskGenericNotifyWait C.xTaskGenericNotifyWait +func (recv_ UBaseTypeT) XTaskGenericNotifyWait(ulBitsToClearOnEntry c.Uint32T, ulBitsToClearOnExit c.Uint32T, pulNotificationValue *c.Uint32T, xTicksToWait TickTypeT) BaseTypeT { + return 0 +} + +/** + * + * A version of xTaskNotifyGiveIndexed() that can be called from an interrupt + * service routine (ISR). + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro + * to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * vTaskNotifyGiveIndexedFromISR() is intended for use when task notifications + * are used as light weight and faster binary or counting semaphore equivalents. + * Actual FreeRTOS semaphores are given from an ISR using the + * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses + * a task notification is vTaskNotifyGiveIndexedFromISR(). + * + * When task notifications are being used as a binary or counting semaphore + * equivalent then the task being notified should wait for the notification + * using the ulTaskNotifyTakeIndexed() API function rather than the + * xTaskNotifyWaitIndexed() API function. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyFromISR() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyGiveFromISR() is equivalent to calling + * xTaskNotifyGiveIndexedFromISR() with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * xTaskNotifyGiveFromISR() does not have this parameter and always sends + * notifications to index 0. + * + * @param pxHigherPriorityTaskWoken vTaskNotifyGiveFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the + * task to which the notification was sent to leave the Blocked state, and the + * unblocked task has a priority higher than the currently running task. If + * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch + * should be requested before the interrupt is exited. How a context switch is + * requested from an ISR is dependent on the port - see the documentation page + * for the port in use. + * + * \ingroup TaskNotifications + */ +//go:linkname VTaskGenericNotifyGiveFromISR C.vTaskGenericNotifyGiveFromISR +func VTaskGenericNotifyGiveFromISR(xTaskToNotify TaskHandleT, uxIndexToNotify UBaseTypeT, pxHigherPriorityTaskWoken *BaseTypeT) + +/** + * + * Waits for a direct to task notification on a particular index in the calling + * task's notification array in a manner similar to taking a counting semaphore. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * ulTaskNotifyTakeIndexed() is intended for use when a task notification is + * used as a faster and lighter weight binary or counting semaphore alternative. + * Actual FreeRTOS semaphores are taken using the xSemaphoreTake() API function, + * the equivalent action that instead uses a task notification is + * ulTaskNotifyTakeIndexed(). + * + * When a task is using its notification value as a binary or counting semaphore + * other tasks should send notifications to it using the xTaskNotifyGiveIndexed() + * macro, or xTaskNotifyIndex() function with the eAction parameter set to + * eIncrement. + * + * ulTaskNotifyTakeIndexed() can either clear the task's notification value at + * the array index specified by the uxIndexToWaitOn parameter to zero on exit, + * in which case the notification value acts like a binary semaphore, or + * decrement the notification value on exit, in which case the notification + * value acts like a counting semaphore. + * + * A task can use ulTaskNotifyTakeIndexed() to [optionally] block to wait for + * a notification. The task does not consume any CPU time while it is in the + * Blocked state. + * + * Where as xTaskNotifyWaitIndexed() will return when a notification is pending, + * ulTaskNotifyTakeIndexed() will return when the task's notification value is + * not zero. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. ulTaskNotifyTake() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling ulTaskNotifyTake() is equivalent to calling + * ulTaskNotifyTakeIndexed() with the uxIndexToWaitOn parameter set to 0. + * + * @param uxIndexToWaitOn The index within the calling task's array of + * notification values on which the calling task will wait for a notification to + * be non-zero. uxIndexToWaitOn must be less than + * configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyTake() does + * not have this parameter and always waits for notifications on index 0. + * + * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's + * notification value is decremented when the function exits. In this way the + * notification value acts like a counting semaphore. If xClearCountOnExit is + * not pdFALSE then the task's notification value is cleared to zero when the + * function exits. In this way the notification value acts like a binary + * semaphore. + * + * @param xTicksToWait The maximum amount of time that the task should wait in + * the Blocked state for the task's notification value to be greater than zero, + * should the count not already be greater than zero when + * ulTaskNotifyTake() was called. The task will not consume any processing + * time while it is in the Blocked state. This is specified in kernel ticks, + * the macro pdMS_TO_TICKS( value_in_ms ) can be used to convert a time + * specified in milliseconds to a time specified in ticks. + * + * @return The task's notification count before it is either cleared to zero or + * decremented (see the xClearCountOnExit parameter). + * + * \ingroup TaskNotifications + */ +/** @cond !DOC_EXCLUDE_HEADER_SECTION */ +// llgo:link UBaseTypeT.UlTaskGenericNotifyTake C.ulTaskGenericNotifyTake +func (recv_ UBaseTypeT) UlTaskGenericNotifyTake(xClearCountOnExit BaseTypeT, xTicksToWait TickTypeT) c.Uint32T { + return 0 +} + +/** + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * If a notification is sent to an index within the array of notifications then + * the notification at that index is said to be 'pending' until it is read or + * explicitly cleared by the receiving task. xTaskNotifyStateClearIndexed() + * is the function that clears a pending notification without reading the + * notification value. The notification value at the same array index is not + * altered. Set xTask to NULL to clear the notification state of the calling + * task. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyStateClear() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyStateClear() is equivalent to calling + * xTaskNotifyStateClearIndexed() with the uxIndexToNotify parameter set to 0. + * + * @param xTask The handle of the RTOS task that will have a notification state + * cleared. Set xTask to NULL to clear a notification state in the calling + * task. To obtain a task's handle create the task using xTaskCreate() and + * make use of the pxCreatedTask parameter, or create the task using + * xTaskCreateStatic() and store the returned value, or use the task's name in + * a call to xTaskGetHandle(). + * + * @param uxIndexToClear The index within the target task's array of + * notification values to act upon. For example, setting uxIndexToClear to 1 + * will clear the state of the notification at index 1 within the array. + * uxIndexToClear must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * ulTaskNotifyStateClear() does not have this parameter and always acts on the + * notification at index 0. + * + * @return pdTRUE if the task's notification state was set to + * eNotWaitingNotification, otherwise pdFALSE. + * + * \ingroup TaskNotifications + */ +//go:linkname XTaskGenericNotifyStateClear C.xTaskGenericNotifyStateClear +func XTaskGenericNotifyStateClear(xTask TaskHandleT, uxIndexToClear UBaseTypeT) BaseTypeT + +/** + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * ulTaskNotifyValueClearIndexed() clears the bits specified by the + * ulBitsToClear bit mask in the notification value at array index uxIndexToClear + * of the task referenced by xTask. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. ulTaskNotifyValueClear() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling ulTaskNotifyValueClear() is equivalent to calling + * ulTaskNotifyValueClearIndexed() with the uxIndexToClear parameter set to 0. + * + * @param xTask The handle of the RTOS task that will have bits in one of its + * notification values cleared. Set xTask to NULL to clear bits in a + * notification value of the calling task. To obtain a task's handle create the + * task using xTaskCreate() and make use of the pxCreatedTask parameter, or + * create the task using xTaskCreateStatic() and store the returned value, or + * use the task's name in a call to xTaskGetHandle(). + * + * @param uxIndexToClear The index within the target task's array of + * notification values in which to clear the bits. uxIndexToClear + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * ulTaskNotifyValueClear() does not have this parameter and always clears bits + * in the notification value at index 0. + * + * @param ulBitsToClear Bit mask of the bits to clear in the notification value of + * xTask. Set a bit to 1 to clear the corresponding bits in the task's notification + * value. Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear + * the notification value to 0. Set ulBitsToClear to 0 to query the task's + * notification value without clearing any bits. + * + * + * @return The value of the target task's notification value before the bits + * specified by ulBitsToClear were cleared. + * \ingroup TaskNotifications + */ +//go:linkname UlTaskGenericNotifyValueClear C.ulTaskGenericNotifyValueClear +func UlTaskGenericNotifyValueClear(xTask TaskHandleT, uxIndexToClear UBaseTypeT, ulBitsToClear c.Uint32T) c.Uint32T + +/** + * + * Capture the current time for future use with xTaskCheckForTimeOut(). + * + * @param pxTimeOut Pointer to a timeout object into which the current time + * is to be captured. The captured time includes the tick count and the number + * of times the tick count has overflowed since the system first booted. + * \ingroup TaskCtrl + */ +// llgo:link (*TimeOutT).VTaskSetTimeOutState C.vTaskSetTimeOutState +func (recv_ *TimeOutT) VTaskSetTimeOutState() { +} + +/** + * + * Determines if pxTicksToWait ticks has passed since a time was captured + * using a call to vTaskSetTimeOutState(). The captured time includes the tick + * count and the number of times the tick count has overflowed. + * + * @param pxTimeOut The time status as captured previously using + * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated + * to reflect the current time status. + * @param pxTicksToWait The number of ticks to check for timeout i.e. if + * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by + * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred. + * If the timeout has not occurred, pxTicksToWait is updated to reflect the + * number of remaining ticks. + * + * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is + * returned and pxTicksToWait is updated to reflect the number of remaining + * ticks. + * + * @see https://www.FreeRTOS.org/xTaskCheckForTimeOut.html + * + * Example Usage: + * @code{c} + * // Driver library function used to receive uxWantedBytes from an Rx buffer + * // that is filled by a UART interrupt. If there are not enough bytes in the + * // Rx buffer then the task enters the Blocked state until it is notified that + * // more data has been placed into the buffer. If there is still not enough + * // data then the task re-enters the Blocked state, and xTaskCheckForTimeOut() + * // is used to re-calculate the Block time to ensure the total amount of time + * // spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This + * // continues until either the buffer contains at least uxWantedBytes bytes, + * // or the total amount of time spent in the Blocked state reaches + * // MAX_TIME_TO_WAIT - at which point the task reads however many bytes are + * // available up to a maximum of uxWantedBytes. + * + * size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes ) + * { + * size_t uxReceived = 0; + * TickType_t xTicksToWait = MAX_TIME_TO_WAIT; + * TimeOut_t xTimeOut; + * + * // Initialize xTimeOut. This records the time at which this function + * // was entered. + * vTaskSetTimeOutState( &xTimeOut ); + * + * // Loop until the buffer contains the wanted number of bytes, or a + * // timeout occurs. + * while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes ) + * { + * // The buffer didn't contain enough data so this task is going to + * // enter the Blocked state. Adjusting xTicksToWait to account for + * // any time that has been spent in the Blocked state within this + * // function so far to ensure the total amount of time spent in the + * // Blocked state does not exceed MAX_TIME_TO_WAIT. + * if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE ) + * { + * //Timed out before the wanted number of bytes were available, + * // exit the loop. + * break; + * } + * + * // Wait for a maximum of xTicksToWait ticks to be notified that the + * // receive interrupt has placed more data into the buffer. + * ulTaskNotifyTake( pdTRUE, xTicksToWait ); + * } + * + * // Attempt to read uxWantedBytes from the receive buffer into pucBuffer. + * // The actual number of bytes read (which might be less than + * // uxWantedBytes) is returned. + * uxReceived = UART_read_from_receive_buffer( pxUARTInstance, + * pucBuffer, + * uxWantedBytes ); + * + * return uxReceived; + * } + * @endcode + * \ingroup TaskCtrl + */ +// llgo:link (*TimeOutT).XTaskCheckForTimeOut C.xTaskCheckForTimeOut +func (recv_ *TimeOutT) XTaskCheckForTimeOut(pxTicksToWait *TickTypeT) BaseTypeT { + return 0 +} + +/** + * + * This function corrects the tick count value after the application code has held + * interrupts disabled for an extended period resulting in tick interrupts having + * been missed. + * + * This function is similar to vTaskStepTick(), however, unlike + * vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a + * time at which a task should be removed from the blocked state. That means + * tasks may have to be removed from the blocked state as the tick count is + * moved. + * + * @param xTicksToCatchUp The number of tick interrupts that have been missed due to + * interrupts being disabled. Its value is not computed automatically, so must be + * computed by the application writer. + * + * @return pdTRUE if moving the tick count forward resulted in a task leaving the + * blocked state and a context switch being performed. Otherwise pdFALSE. + * + * \ingroup TaskCtrl + */ +// llgo:link TickTypeT.XTaskCatchUpTicks C.xTaskCatchUpTicks +func (recv_ TickTypeT) XTaskCatchUpTicks() BaseTypeT { + return 0 +} + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Called from the real time kernel tick (either preemptive or cooperative), + * this increments the tick count and checks if any tasks that are blocked + * for a finite period required removing from a blocked list and placing on + * a ready list. If a non-zero value is returned then a context switch is + * required because either: + * + A task was removed from a blocked list because its timeout had expired, + * or + * + Time slicing is in use and there is a task of equal priority to the + * currently running task. + * + * Note: If configNUMBER_OF_CORES > 1, this function must only be called by + * core 0. Other cores should call xTaskIncrementTickOtherCores() instead. + */ +//go:linkname XTaskIncrementTick C.xTaskIncrementTick +func XTaskIncrementTick() BaseTypeT + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes the calling task from the ready list and places it both + * on the list of tasks waiting for a particular event, and the + * list of delayed tasks. The task will be removed from both lists + * and replaced on the ready list should either the event occur (and + * there be no higher priority tasks waiting on the same event) or + * the delay period expires. + * + * The 'unordered' version replaces the event list item value with the + * xItemValue value, and inserts the list item at the end of the list. + * + * The 'ordered' version uses the existing event list item value (which is the + * owning task's priority) to insert the list item into the event list in task + * priority order. + * + * @param pxEventList The list containing tasks that are blocked waiting + * for the event to occur. + * + * @param xItemValue The item value to use for the event list item when the + * event list is not ordered by task priority. + * + * @param xTicksToWait The maximum amount of time that the task should wait + * for the event to occur. This is specified in kernel ticks, the constant + * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time + * period. + */ +// llgo:link (*ListT).VTaskPlaceOnEventList C.vTaskPlaceOnEventList +func (recv_ *ListT) VTaskPlaceOnEventList(xTicksToWait TickTypeT) { +} + +// llgo:link (*ListT).VTaskPlaceOnUnorderedEventList C.vTaskPlaceOnUnorderedEventList +func (recv_ *ListT) VTaskPlaceOnUnorderedEventList(xItemValue TickTypeT, xTicksToWait TickTypeT) { +} + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * This function performs nearly the same function as vTaskPlaceOnEventList(). + * The difference being that this function does not permit tasks to block + * indefinitely, whereas vTaskPlaceOnEventList() does. + * + */ +// llgo:link (*ListT).VTaskPlaceOnEventListRestricted C.vTaskPlaceOnEventListRestricted +func (recv_ *ListT) VTaskPlaceOnEventListRestricted(xTicksToWait TickTypeT, xWaitIndefinitely BaseTypeT) { +} + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes a task from both the specified event list and the list of blocked + * tasks, and places it on a ready queue. + * + * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called + * if either an event occurs to unblock a task, or the block timeout period + * expires. + * + * xTaskRemoveFromEventList() is used when the event list is in task priority + * order. It removes the list item from the head of the event list as that will + * have the highest priority owning task of all the tasks on the event list. + * vTaskRemoveFromUnorderedEventList() is used when the event list is not + * ordered and the event list items hold something other than the owning tasks + * priority. In this case the event list item value is updated to the value + * passed in the xItemValue parameter. + * + * @return pdTRUE if the task being removed has a higher priority than the task + * making the call, otherwise pdFALSE. + */ +// llgo:link (*ListT).XTaskRemoveFromEventList C.xTaskRemoveFromEventList +func (recv_ *ListT) XTaskRemoveFromEventList() BaseTypeT { + return 0 +} + +// llgo:link (*ListItemT).VTaskRemoveFromUnorderedEventList C.vTaskRemoveFromUnorderedEventList +func (recv_ *ListItemT) VTaskRemoveFromUnorderedEventList(xItemValue TickTypeT) { +} + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Sets the pointer to the current TCB to the TCB of the highest priority task + * that is ready to run. + */ +//go:linkname VTaskSwitchContext C.vTaskSwitchContext +func VTaskSwitchContext() + +/* + * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE. THEY ARE USED BY + * THE EVENT BITS MODULE. + */ +//go:linkname UxTaskResetEventItemValue C.uxTaskResetEventItemValue +func UxTaskResetEventItemValue() TickTypeT + +/* + * Return the handle of the calling task. + */ +//go:linkname XTaskGetCurrentTaskHandle C.xTaskGetCurrentTaskHandle +func XTaskGetCurrentTaskHandle() TaskHandleT + +/* + * Shortcut used by the queue implementation to prevent unnecessary call to + * taskYIELD(); + */ +//go:linkname VTaskMissedYield C.vTaskMissedYield +func VTaskMissedYield() + +/* + * Returns the scheduler state as taskSCHEDULER_RUNNING, + * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED. + */ +//go:linkname XTaskGetSchedulerState C.xTaskGetSchedulerState +func XTaskGetSchedulerState() BaseTypeT + +/* + * Raises the priority of the mutex holder to that of the calling task should + * the mutex holder have a priority less than the calling task. + */ +//go:linkname XTaskPriorityInherit C.xTaskPriorityInherit +func XTaskPriorityInherit(pxMutexHolder TaskHandleT) BaseTypeT + +/* + * Set the priority of a task back to its proper priority in the case that it + * inherited a higher priority while it was holding a semaphore. + */ +//go:linkname XTaskPriorityDisinherit C.xTaskPriorityDisinherit +func XTaskPriorityDisinherit(pxMutexHolder TaskHandleT) BaseTypeT + +/* + * If a higher priority task attempting to obtain a mutex caused a lower + * priority task to inherit the higher priority task's priority - but the higher + * priority task then timed out without obtaining the mutex, then the lower + * priority task will disinherit the priority again - but only down as far as + * the highest priority task that is still waiting for the mutex (if there were + * more than one task waiting for the mutex). + */ +//go:linkname VTaskPriorityDisinheritAfterTimeout C.vTaskPriorityDisinheritAfterTimeout +func VTaskPriorityDisinheritAfterTimeout(pxMutexHolder TaskHandleT, uxHighestPriorityWaitingTask UBaseTypeT) + +/* + * Get the uxTaskNumber assigned to the task referenced by the xTask parameter. + */ +//go:linkname UxTaskGetTaskNumber C.uxTaskGetTaskNumber +func UxTaskGetTaskNumber(xTask TaskHandleT) UBaseTypeT + +/* + * Set the uxTaskNumber of the task referenced by the xTask parameter to + * uxHandle. + */ +//go:linkname VTaskSetTaskNumber C.vTaskSetTaskNumber +func VTaskSetTaskNumber(xTask TaskHandleT, uxHandle UBaseTypeT) + +/* + * Only available when configUSE_TICKLESS_IDLE is set to 1. + * If tickless mode is being used, or a low power mode is implemented, then + * the tick interrupt will not execute during idle periods. When this is the + * case, the tick count value maintained by the scheduler needs to be kept up + * to date with the actual execution time by being skipped forward by a time + * equal to the idle period. + */ +// llgo:link TickTypeT.VTaskStepTick C.vTaskStepTick +func (recv_ TickTypeT) VTaskStepTick() { +} + +/* + * Only available when configUSE_TICKLESS_IDLE is set to 1. + * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port + * specific sleep function to determine if it is ok to proceed with the sleep, + * and if it is ok to proceed, if it is ok to sleep indefinitely. + * + * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only + * called with the scheduler suspended, not from within a critical section. It + * is therefore possible for an interrupt to request a context switch between + * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being + * entered. eTaskConfirmSleepModeStatus() should be called from a short + * critical section between the timer being stopped and the sleep mode being + * entered to ensure it is ok to proceed into the sleep mode. + */ +//go:linkname ETaskConfirmSleepModeStatus C.eTaskConfirmSleepModeStatus +func ETaskConfirmSleepModeStatus() ESleepModeStatus + +/* + * For internal use only. Increment the mutex held count when a mutex is + * taken and return the handle of the task that has taken the mutex. + */ +//go:linkname PvTaskIncrementMutexHeldCount C.pvTaskIncrementMutexHeldCount +func PvTaskIncrementMutexHeldCount() TaskHandleT + +/* + * For internal use only. Same as vTaskSetTimeOutState(), but without a critical + * section. + */ +// llgo:link (*TimeOutT).VTaskInternalSetTimeOutState C.vTaskInternalSetTimeOutState +func (recv_ *TimeOutT) VTaskInternalSetTimeOutState() { +} diff --git a/esp32/temperature_sensor_ll.go b/esp32/temperature_sensor_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/temperature_sensor_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/temperature_sensor_periph.go b/esp32/temperature_sensor_periph.go new file mode 100644 index 00000000..f0b37af1 --- /dev/null +++ b/esp32/temperature_sensor_periph.go @@ -0,0 +1,14 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type TemperatureSensorAttributeT struct { + Offset c.Int + RegVal c.Int + RangeMin c.Int + RangeMax c.Int + ErrorMax c.Int +} diff --git a/esp32/temperature_sensor_types.go b/esp32/temperature_sensor_types.go new file mode 100644 index 00000000..53d41d5f --- /dev/null +++ b/esp32/temperature_sensor_types.go @@ -0,0 +1,22 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type TemperatureSensorClkSrcT SocPeriphTemperatureSensorClkSrcT +type TemperatureSensorEtmEventTypeT c.Int + +const ( + TEMPERATURE_SENSOR_EVENT_OVER_LIMIT TemperatureSensorEtmEventTypeT = 0 + TEMPERATURE_SENSOR_EVENT_MAX TemperatureSensorEtmEventTypeT = 1 +) + +type TemperatureSensorEtmTaskTypeT c.Int + +const ( + TEMPERATURE_SENSOR_TASK_START TemperatureSensorEtmTaskTypeT = 0 + TEMPERATURE_SENSOR_TASK_STOP TemperatureSensorEtmTaskTypeT = 1 + TEMPERATURE_SENSOR_TASK_MAX TemperatureSensorEtmTaskTypeT = 2 +) diff --git a/esp32/tie-asm.go b/esp32/tie-asm.go new file mode 100644 index 00000000..1f991274 --- /dev/null +++ b/esp32/tie-asm.go @@ -0,0 +1,19 @@ +package freertos + +import _ "unsafe" + +const XTHAL_SAS_TIE = 0x0001 +const XTHAL_SAS_OPT = 0x0002 +const XTHAL_SAS_ANYOT = 0x0003 +const XTHAL_SAS_NOCC = 0x0004 +const XTHAL_SAS_CC = 0x0008 +const XTHAL_SAS_ANYCC = 0x000C +const XTHAL_SAS_CALR = 0x0010 +const XTHAL_SAS_CALE = 0x0020 +const XTHAL_SAS_GLOB = 0x0040 +const XTHAL_SAS_ANYABI = 0x0070 +const XTHAL_SAS_ALL = 0xFFFF +const XCHAL_NCP_NUM_ATMPS = 1 +const XCHAL_CP0_NUM_ATMPS = 1 +const XCHAL_CP3_NUM_ATMPS = 1 +const XCHAL_SA_NUM_ATMPS = 1 diff --git a/esp32/tie.go b/esp32/tie.go new file mode 100644 index 00000000..5b58174d --- /dev/null +++ b/esp32/tie.go @@ -0,0 +1,41 @@ +package freertos + +import _ "unsafe" + +const XCHAL_CP_NUM = 2 +const XCHAL_CP_MAX = 4 +const XCHAL_CP_MASK = 0x09 +const XCHAL_CP_PORT_MASK = 0x00 +const XCHAL_CP0_NAME = "FPU" +const XCHAL_CP0_SA_SIZE = 72 +const XCHAL_CP0_SA_ALIGN = 4 +const XCHAL_CP_ID_FPU = 0 +const XCHAL_CP3_NAME = "cop_ai" +const XCHAL_CP3_SA_SIZE = 208 +const XCHAL_CP3_SA_ALIGN = 16 +const XCHAL_CP_ID_COP_AI = 3 +const XCHAL_CP1_SA_SIZE = 0 +const XCHAL_CP1_SA_ALIGN = 1 +const XCHAL_CP2_SA_SIZE = 0 +const XCHAL_CP2_SA_ALIGN = 1 +const XCHAL_CP4_SA_SIZE = 0 +const XCHAL_CP4_SA_ALIGN = 1 +const XCHAL_CP5_SA_SIZE = 0 +const XCHAL_CP5_SA_ALIGN = 1 +const XCHAL_CP6_SA_SIZE = 0 +const XCHAL_CP6_SA_ALIGN = 1 +const XCHAL_CP7_SA_SIZE = 0 +const XCHAL_CP7_SA_ALIGN = 1 +const XCHAL_NCP_SA_SIZE = 36 +const XCHAL_NCP_SA_ALIGN = 4 +const XCHAL_TOTAL_SA_SIZE = 336 +const XCHAL_TOTAL_SA_ALIGN = 16 +const XCHAL_NCP_SA_NUM = 9 +const XCHAL_CP0_SA_NUM = 18 +const XCHAL_CP1_SA_NUM = 0 +const XCHAL_CP2_SA_NUM = 0 +const XCHAL_CP3_SA_NUM = 26 +const XCHAL_CP4_SA_NUM = 0 +const XCHAL_CP5_SA_NUM = 0 +const XCHAL_CP6_SA_NUM = 0 +const XCHAL_CP7_SA_NUM = 0 diff --git a/esp32/timer_group_reg.go b/esp32/timer_group_reg.go new file mode 100644 index 00000000..16144e9f --- /dev/null +++ b/esp32/timer_group_reg.go @@ -0,0 +1,73 @@ +package freertos + +import _ "unsafe" + +const TIMG_T0_USE_XTAL_S = 9 +const TIMG_T0_ALARM_EN_S = 10 +const TIMG_T0_DIVIDER_S = 13 +const TIMG_T0_AUTORELOAD_S = 29 +const TIMG_T0_INCREASE_S = 30 +const TIMG_T0_EN_S = 31 +const TIMG_T0_LO_S = 0 +const TIMG_T0_HI_S = 0 +const TIMG_T0_UPDATE_S = 31 +const TIMG_T0_ALARM_LO_S = 0 +const TIMG_T0_ALARM_HI_S = 0 +const TIMG_T0_LOAD_LO_S = 0 +const TIMG_T0_LOAD_HI_S = 0 +const TIMG_T0_LOAD_S = 0 +const TIMG_T1_USE_XTAL_S = 9 +const TIMG_T1_ALARM_EN_S = 10 +const TIMG_T1_DIVIDER_S = 13 +const TIMG_T1_AUTORELOAD_S = 29 +const TIMG_T1_INCREASE_S = 30 +const TIMG_T1_EN_S = 31 +const TIMG_T1_LO_S = 0 +const TIMG_T1_HI_S = 0 +const TIMG_T1_UPDATE_S = 31 +const TIMG_T1_ALARM_LO_S = 0 +const TIMG_T1_ALARM_HI_S = 0 +const TIMG_T1_LOAD_LO_S = 0 +const TIMG_T1_LOAD_HI_S = 0 +const TIMG_T1_LOAD_S = 0 +const TIMG_WDT_APPCPU_RESET_EN_S = 12 +const TIMG_WDT_PROCPU_RESET_EN_S = 13 +const TIMG_WDT_FLASHBOOT_MOD_EN_S = 14 +const TIMG_WDT_SYS_RESET_LENGTH_S = 15 +const TIMG_WDT_CPU_RESET_LENGTH_S = 18 +const TIMG_WDT_STG3_S = 23 +const TIMG_WDT_STG2_S = 25 +const TIMG_WDT_STG1_S = 27 +const TIMG_WDT_STG0_S = 29 +const TIMG_WDT_EN_S = 31 +const TIMG_WDT_CLK_PRESCALE_S = 16 +const TIMG_WDT_STG0_HOLD_S = 0 +const TIMG_WDT_STG1_HOLD_S = 0 +const TIMG_WDT_STG2_HOLD_S = 0 +const TIMG_WDT_STG3_HOLD_S = 0 +const TIMG_WDT_FEED_S = 0 +const TIMG_WDT_WKEY_S = 0 +const TIMG_RTC_CALI_START_CYCLING_S = 12 +const TIMG_RTC_CALI_CLK_SEL_S = 13 +const TIMG_RTC_CALI_RDY_S = 15 +const TIMG_RTC_CALI_MAX_S = 16 +const TIMG_RTC_CALI_START_S = 31 +const TIMG_RTC_CALI_CYCLING_DATA_VLD_S = 0 +const TIMG_RTC_CALI_VALUE_S = 7 +const TIMG_T0_INT_ENA_S = 0 +const TIMG_T1_INT_ENA_S = 1 +const TIMG_WDT_INT_ENA_S = 2 +const TIMG_T0_INT_RAW_S = 0 +const TIMG_T1_INT_RAW_S = 1 +const TIMG_WDT_INT_RAW_S = 2 +const TIMG_T0_INT_ST_S = 0 +const TIMG_T1_INT_ST_S = 1 +const TIMG_WDT_INT_ST_S = 2 +const TIMG_T0_INT_CLR_S = 0 +const TIMG_T1_INT_CLR_S = 1 +const TIMG_WDT_INT_CLR_S = 2 +const TIMG_RTC_CALI_TIMEOUT_S = 0 +const TIMG_RTC_CALI_TIMEOUT_RST_CNT_S = 3 +const TIMG_RTC_CALI_TIMEOUT_THRES_S = 7 +const TIMG_NTIMERS_DATE_S = 0 +const TIMG_CLK_EN_S = 31 diff --git a/esp32/timer_group_struct.go b/esp32/timer_group_struct.go new file mode 100644 index 00000000..cb3fe7c7 --- /dev/null +++ b/esp32/timer_group_struct.go @@ -0,0 +1,253 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** Group: Configuration and control registers */ +/** Type of tnconfig register + * Timer n configuration register + */ + +type TimgTnconfigRegT struct { + Val c.Uint32T +} + +/** Type of tnlo register + * Timer n current value, low 32 bits + */ + +type TimgTnloRegT struct { + Val c.Uint32T +} + +/** Type of tnhi register + * Timer n current value, high 22 bits + */ + +type TimgTnhiRegT struct { + Val c.Uint32T +} + +/** Type of tnupdate register + * Write to copy current timer value to TIMGn_Tn_(LO/HI)_REG + */ + +type TimgTnupdateRegT struct { + Val c.Uint32T +} + +/** Type of tnalarmlo register + * Timer n alarm value, low 32 bits + */ + +type TimgTnalarmloRegT struct { + Val c.Uint32T +} + +/** Type of tnalarmhi register + * Timer n alarm value, high bits + */ + +type TimgTnalarmhiRegT struct { + Val c.Uint32T +} + +/** Type of tnloadlo register + * Timer n reload value, low 32 bits + */ + +type TimgTnloadloRegT struct { + Val c.Uint32T +} + +/** Type of tnloadhi register + * Timer n reload value, high 22 bits + */ + +type TimgTnloadhiRegT struct { + Val c.Uint32T +} + +/** Type of tnload register + * Write to reload timer from TIMG_Tn_(LOADLOLOADHI)_REG + */ + +type TimgTnloadRegT struct { + Val c.Uint32T +} + +/** Group: Configuration and control registers for WDT */ +/** Type of wdtconfig0 register + * Watchdog timer configuration register + */ + +type TimgWdtconfig0RegT struct { + Val c.Uint32T +} + +/** Type of wdtconfig1 register + * Watchdog timer prescaler register + */ + +type TimgWdtconfig1RegT struct { + Val c.Uint32T +} + +/** Type of wdtconfig2 register + * Watchdog timer stage 0 timeout value + */ + +type TimgWdtconfig2RegT struct { + Val c.Uint32T +} + +/** Type of wdtconfig3 register + * Watchdog timer stage 1 timeout value + */ + +type TimgWdtconfig3RegT struct { + Val c.Uint32T +} + +/** Type of wdtconfig4 register + * Watchdog timer stage 2 timeout value + */ + +type TimgWdtconfig4RegT struct { + Val c.Uint32T +} + +/** Type of wdtconfig5 register + * Watchdog timer stage 3 timeout value + */ + +type TimgWdtconfig5RegT struct { + Val c.Uint32T +} + +/** Type of wdtfeed register + * Write to feed the watchdog timer + */ + +type TimgWdtfeedRegT struct { + Val c.Uint32T +} + +/** Type of wdtwprotect register + * Watchdog write protect register + */ + +type TimgWdtwprotectRegT struct { + Val c.Uint32T +} + +/** Group: Configuration and control registers for RTC CALI */ +/** Type of rtccalicfg register + * RTC calibration configure register + */ + +type TimgRtccalicfgRegT struct { + Val c.Uint32T +} + +/** Type of rtccalicfg1 register + * RTC calibration configure1 register + */ + +type TimgRtccalicfg1RegT struct { + Val c.Uint32T +} + +/** Type of rtccalicfg2 register + * Timer group calibration register + */ + +type TimgRtccalicfg2RegT struct { + Val c.Uint32T +} + +/** Group: Interrupt registers */ +/** Type of int_ena_timers register + * Interrupt enable bits + */ + +type TimgIntEnaTimersRegT struct { + Val c.Uint32T +} + +/** Type of int_raw_timers register + * Raw interrupt status + */ + +type TimgIntRawTimersRegT struct { + Val c.Uint32T +} + +/** Type of int_st_timers register + * Masked interrupt status + */ + +type TimgIntStTimersRegT struct { + Val c.Uint32T +} + +/** Type of int_clr_timers register + * Interrupt clear bits + */ + +type TimgIntClrTimersRegT struct { + Val c.Uint32T +} + +/** Group: Configuration registers */ +/** Type of ntimers_date register + * Timer version control register + */ + +type TimgNtimersDateRegT struct { + Val c.Uint32T +} + +/** Type of regclk register + * Timer group clock gate register + */ + +type TimgRegclkRegT struct { + Val c.Uint32T +} + +type TimgHwtimerRegT struct { + Config TimgTnconfigRegT + Lo TimgTnloRegT + Hi TimgTnhiRegT + Update TimgTnupdateRegT + Alarmlo TimgTnalarmloRegT + Alarmhi TimgTnalarmhiRegT + Loadlo TimgTnloadloRegT + Loadhi TimgTnloadhiRegT + Load TimgTnloadRegT +} + +type TimgDevT struct { + HwTimer [2]TimgHwtimerRegT + Wdtconfig0 TimgWdtconfig0RegT + Wdtconfig1 TimgWdtconfig1RegT + Wdtconfig2 TimgWdtconfig2RegT + Wdtconfig3 TimgWdtconfig3RegT + Wdtconfig4 TimgWdtconfig4RegT + Wdtconfig5 TimgWdtconfig5RegT + Wdtfeed TimgWdtfeedRegT + Wdtwprotect TimgWdtwprotectRegT + Rtccalicfg TimgRtccalicfgRegT + Rtccalicfg1 TimgRtccalicfg1RegT + IntEnaTimers TimgIntEnaTimersRegT + IntRawTimers TimgIntRawTimersRegT + IntStTimers TimgIntStTimersRegT + IntClrTimers TimgIntClrTimersRegT + Rtccalicfg2 TimgRtccalicfg2RegT + Reserved084 [29]c.Uint32T + NtimersDate TimgNtimersDateRegT + Regclk TimgRegclkRegT +} diff --git a/esp32/timer_hal.go b/esp32/timer_hal.go new file mode 100644 index 00000000..14f1fb94 --- /dev/null +++ b/esp32/timer_hal.go @@ -0,0 +1,58 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type GptimerSocHandleT *TimgDevT + +/** + * Context that should be maintained by both the driver and the HAL + */ + +type TimerHalContextT struct { + Dev GptimerSocHandleT + TimerId c.Uint32T +} + +/** + * @brief Init the timer hal. This function should be called first before other hal layer function is called + * + * @param hal Context of the HAL layer + * @param group_num The timer group number + * @param timer_num The timer number + */ +// llgo:link (*TimerHalContextT).TimerHalInit C.timer_hal_init +func (recv_ *TimerHalContextT) TimerHalInit(group_num c.Uint32T, timer_num c.Uint32T) { +} + +/** + * @brief Deinit timer hal context. + * + * @param hal Context of HAL layer + */ +// llgo:link (*TimerHalContextT).TimerHalDeinit C.timer_hal_deinit +func (recv_ *TimerHalContextT) TimerHalDeinit() { +} + +/** + * @brief Load counter value into time-base counter + * + * @param hal Context of the HAL layer + * @param load_val Counter value + */ +// llgo:link (*TimerHalContextT).TimerHalSetCounterValue C.timer_hal_set_counter_value +func (recv_ *TimerHalContextT) TimerHalSetCounterValue(load_val c.Uint64T) { +} + +/** + * @brief Trigger a software capture event and then return the captured count value + * + * @param hal Context of the HAL layer + * @return Counter value + */ +// llgo:link (*TimerHalContextT).TimerHalCaptureAndGetCounterValue C.timer_hal_capture_and_get_counter_value +func (recv_ *TimerHalContextT) TimerHalCaptureAndGetCounterValue() c.Uint64T { + return 0 +} diff --git a/esp32/timer_ll.go b/esp32/timer_ll.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/timer_ll.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/timer_periph.go b/esp32/timer_periph.go new file mode 100644 index 00000000..2bbd699d --- /dev/null +++ b/esp32/timer_periph.go @@ -0,0 +1,13 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type TimerGroupSignalConnT struct { + Groups [2]struct { + Module PeriphModuleT + TimerIrqId [2]c.Int + } +} diff --git a/esp32/timer_types.go b/esp32/timer_types.go new file mode 100644 index 00000000..332f7f1e --- /dev/null +++ b/esp32/timer_types.go @@ -0,0 +1,14 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type GptimerClockSourceT SocPeriphGptimerClkSrcT +type GptimerCountDirectionT c.Int + +const ( + GPTIMER_COUNT_DOWN GptimerCountDirectionT = 0 + GPTIMER_COUNT_UP GptimerCountDirectionT = 1 +) diff --git a/esp32/timers.go b/esp32/timers.go new file mode 100644 index 00000000..d458d4c1 --- /dev/null +++ b/esp32/timers.go @@ -0,0 +1,604 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Type by which software timers are referenced. For example, a call to + * xTimerCreate() returns an TimerHandle_t variable that can then be used to + * reference the subject timer in calls to other software timer API functions + * (for example, xTimerStart(), xTimerReset(), etc.). + */ + +type TmrTimerControl struct { + Unused [8]uint8 +} +type TimerHandleT *TmrTimerControl + +// llgo:type C +type TimerCallbackFunctionT func(TimerHandleT) + +// llgo:type C +type PendedFunctionT func(c.Pointer, c.Uint32T) + +/** + * + * Creates a new software timer instance, and returns a handle by which the + * created software timer can be referenced. + * + * Internally, within the FreeRTOS implementation, software timers use a block + * of memory, in which the timer data structure is stored. If a software timer + * is created using xTimerCreate() then the required memory is automatically + * dynamically allocated inside the xTimerCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a software timer is created using + * xTimerCreateStatic() then the application writer must provide the memory that + * will get used by the software timer. xTimerCreateStatic() therefore allows a + * software timer to be created without using any dynamic memory allocation. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a + * timer into the active state. + * + * @param pcTimerName A text name that is assigned to the timer. This is done + * purely to assist debugging. The kernel itself only ever references a timer + * by its handle, and never by its name. + * + * @param xTimerPeriodInTicks The timer period. The time is defined in tick + * periods so the constant portTICK_PERIOD_MS can be used to convert a time that + * has been specified in milliseconds. For example, if the timer must expire + * after 100 ticks, then xTimerPeriodInTicks should be set to 100. + * Alternatively, if the timer must expire after 500ms, then xPeriod can be set + * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or + * equal to 1000. Time timer period must be greater than 0. + * + * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. + * If xAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + * + * @param pvTimerID An identifier that is assigned to the timer being created. + * Typically this would be used in the timer callback function to identify which + * timer expired when the same callback function is assigned to more than one + * timer. + * + * @param pxCallbackFunction The function to call when the timer expires. + * Callback functions must have the prototype defined by TimerCallbackFunction_t, + * which is "void vCallbackFunction( TimerHandle_t xTimer );". + * + * @return If the timer is successfully created then a handle to the newly + * created timer is returned. If the timer cannot be created because there is + * insufficient FreeRTOS heap remaining to allocate the timer + * structures then NULL is returned. + * + * Example usage: + * @verbatim + * #define NUM_TIMERS 5 + * + * // An array to hold handles to the created timers. + * TimerHandle_t xTimers[ NUM_TIMERS ]; + * + * // An array to hold a count of the number of times each timer expires. + * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 }; + * + * // Define a callback function that will be used by multiple timer instances. + * // The callback function does nothing but count the number of times the + * // associated timer expires, and stop the timer once the timer has expired + * // 10 times. + * void vTimerCallback( TimerHandle_t pxTimer ) + * { + * int32_t lArrayIndex; + * const int32_t xMaxExpiryCountBeforeStopping = 10; + * + * // Optionally do something if the pxTimer parameter is NULL. + * configASSERT( pxTimer ); + * + * // Which timer expired? + * lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer ); + * + * // Increment the number of times that pxTimer has expired. + * lExpireCounters[ lArrayIndex ] += 1; + * + * // If the timer has expired 10 times then stop it from running. + * if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping ) + * { + * // Do not use a block time if calling a timer API function from a + * // timer callback function, as doing so could cause a deadlock! + * xTimerStop( pxTimer, 0 ); + * } + * } + * + * void main( void ) + * { + * int32_t x; + * + * // Create then start some timers. Starting the timers before the scheduler + * // has been started means the timers will start running immediately that + * // the scheduler starts. + * for( x = 0; x < NUM_TIMERS; x++ ) + * { + * xTimers[ x ] = xTimerCreate( "Timer", // Just a text name, not used by the kernel. + * ( 100 * ( x + 1 ) ), // The timer period in ticks. + * pdTRUE, // The timers will auto-reload themselves when they expire. + * ( void * ) x, // Assign each timer a unique id equal to its array index. + * vTimerCallback // Each timer calls the same callback when it expires. + * ); + * + * if( xTimers[ x ] == NULL ) + * { + * // The timer was not created. + * } + * else + * { + * // Start the timer. No block time is specified, and even if one was + * // it would be ignored because the scheduler has not yet been + * // started. + * if( xTimerStart( xTimers[ x ], 0 ) != pdPASS ) + * { + * // The timer could not be set into the Active state. + * } + * } + * } + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timers running as they have already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +//go:linkname XTimerCreate C.xTimerCreate +func XTimerCreate(pcTimerName *c.Char, xTimerPeriodInTicks TickTypeT, xAutoReload BaseTypeT, pvTimerID c.Pointer, pxCallbackFunction TimerCallbackFunctionT) TimerHandleT + +/** + * + * Creates a new software timer instance, and returns a handle by which the + * created software timer can be referenced. + * + * Internally, within the FreeRTOS implementation, software timers use a block + * of memory, in which the timer data structure is stored. If a software timer + * is created using xTimerCreate() then the required memory is automatically + * dynamically allocated inside the xTimerCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a software timer is created using + * xTimerCreateStatic() then the application writer must provide the memory that + * will get used by the software timer. xTimerCreateStatic() therefore allows a + * software timer to be created without using any dynamic memory allocation. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a + * timer into the active state. + * + * @param pcTimerName A text name that is assigned to the timer. This is done + * purely to assist debugging. The kernel itself only ever references a timer + * by its handle, and never by its name. + * + * @param xTimerPeriodInTicks The timer period. The time is defined in tick + * periods so the constant portTICK_PERIOD_MS can be used to convert a time that + * has been specified in milliseconds. For example, if the timer must expire + * after 100 ticks, then xTimerPeriodInTicks should be set to 100. + * Alternatively, if the timer must expire after 500ms, then xPeriod can be set + * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or + * equal to 1000. The timer period must be greater than 0. + * + * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. + * If xAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + * + * @param pvTimerID An identifier that is assigned to the timer being created. + * Typically this would be used in the timer callback function to identify which + * timer expired when the same callback function is assigned to more than one + * timer. + * + * @param pxCallbackFunction The function to call when the timer expires. + * Callback functions must have the prototype defined by TimerCallbackFunction_t, + * which is "void vCallbackFunction( TimerHandle_t xTimer );". + * + * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which + * will be then be used to hold the software timer's data structures, removing + * the need for the memory to be allocated dynamically. + * + * @return If the timer is created then a handle to the created timer is + * returned. If pxTimerBuffer was NULL then NULL is returned. + * + * Example usage: + * @verbatim + * + * // The buffer used to hold the software timer's data structure. + * static StaticTimer_t xTimerBuffer; + * + * // A variable that will be incremented by the software timer's callback + * // function. + * UBaseType_t uxVariableToIncrement = 0; + * + * // A software timer callback function that increments a variable passed to + * // it when the software timer was created. After the 5th increment the + * // callback function stops the software timer. + * static void prvTimerCallback( TimerHandle_t xExpiredTimer ) + * { + * UBaseType_t *puxVariableToIncrement; + * BaseType_t xReturned; + * + * // Obtain the address of the variable to increment from the timer ID. + * puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer ); + * + * // Increment the variable to show the timer callback has executed. + * ( *puxVariableToIncrement )++; + * + * // If this callback has executed the required number of times, stop the + * // timer. + * if( *puxVariableToIncrement == 5 ) + * { + * // This is called from a timer callback so must not block. + * xTimerStop( xExpiredTimer, staticDONT_BLOCK ); + * } + * } + * + * + * void main( void ) + * { + * // Create the software time. xTimerCreateStatic() has an extra parameter + * // than the normal xTimerCreate() API function. The parameter is a pointer + * // to the StaticTimer_t structure that will hold the software timer + * // structure. If the parameter is passed as NULL then the structure will be + * // allocated dynamically, just as if xTimerCreate() had been called. + * xTimer = xTimerCreateStatic( "T1", // Text name for the task. Helps debugging only. Not used by FreeRTOS. + * xTimerPeriod, // The period of the timer in ticks. + * pdTRUE, // This is an auto-reload timer. + * ( void * ) &uxVariableToIncrement, // A variable incremented by the software timer's callback function + * prvTimerCallback, // The function to execute when the timer expires. + * &xTimerBuffer ); // The buffer that will hold the software timer structure. + * + * // The scheduler has not started yet so a block time is not used. + * xReturned = xTimerStart( xTimer, 0 ); + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timers running as they have already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +//go:linkname XTimerCreateStatic C.xTimerCreateStatic +func XTimerCreateStatic(pcTimerName *c.Char, xTimerPeriodInTicks TickTypeT, xAutoReload BaseTypeT, pvTimerID c.Pointer, pxCallbackFunction TimerCallbackFunctionT, pxTimerBuffer *StaticTimerT) TimerHandleT + +/** + * + * Returns the ID assigned to the timer. + * + * IDs are assigned to timers using the pvTimerID parameter of the call to + * xTimerCreated() that was used to create the timer, and by calling the + * vTimerSetTimerID() API function. + * + * If the same callback function is assigned to multiple timers then the timer + * ID can be used as time specific (timer local) storage. + * + * @param xTimer The timer being queried. + * + * @return The ID assigned to the timer being queried. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + */ +//go:linkname PvTimerGetTimerID C.pvTimerGetTimerID +func PvTimerGetTimerID(xTimer TimerHandleT) c.Pointer + +/** + * + * Sets the ID assigned to the timer. + * + * IDs are assigned to timers using the pvTimerID parameter of the call to + * xTimerCreated() that was used to create the timer. + * + * If the same callback function is assigned to multiple timers then the timer + * ID can be used as time specific (timer local) storage. + * + * @param xTimer The timer being updated. + * + * @param pvNewID The ID to assign to the timer. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + */ +//go:linkname VTimerSetTimerID C.vTimerSetTimerID +func VTimerSetTimerID(xTimer TimerHandleT, pvNewID c.Pointer) + +/** + * + * Queries a timer to see if it is active or dormant. + * + * A timer will be dormant if: + * 1) It has been created but not started, or + * 2) It is an expired one-shot timer that has not been restarted. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the + * active state. + * + * @param xTimer The timer being queried. + * + * @return pdFALSE will be returned if the timer is dormant. A value other than + * pdFALSE will be returned if the timer is active. + * + * Example usage: + * @verbatim + * // This function assumes xTimer has already been created. + * void vAFunction( TimerHandle_t xTimer ) + * { + * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )" + * { + * // xTimer is active, do something. + * } + * else + * { + * // xTimer is not active, do something else. + * } + * } + * @endverbatim + */ +//go:linkname XTimerIsTimerActive C.xTimerIsTimerActive +func XTimerIsTimerActive(xTimer TimerHandleT) BaseTypeT + +/** + * + * Simply returns the handle of the timer service/daemon task. It it not valid + * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started. + */ +//go:linkname XTimerGetTimerDaemonTaskHandle C.xTimerGetTimerDaemonTaskHandle +func XTimerGetTimerDaemonTaskHandle() TaskHandleT + +/** + * + * + * Used from application interrupt service routines to defer the execution of a + * function to the RTOS daemon task (the timer service task, hence this function + * is implemented in timers.c and is prefixed with 'Timer'). + * + * Ideally an interrupt service routine (ISR) is kept as short as possible, but + * sometimes an ISR either has a lot of processing to do, or needs to perform + * processing that is not deterministic. In these cases + * xTimerPendFunctionCallFromISR() can be used to defer processing of a function + * to the RTOS daemon task. + * + * A mechanism is provided that allows the interrupt to return directly to the + * task that will subsequently execute the pended callback function. This + * allows the callback function to execute contiguously in time with the + * interrupt - just as if the callback had executed in the interrupt itself. + * + * @param xFunctionToPend The function to execute from the timer service/ + * daemon task. The function must conform to the PendedFunction_t + * prototype. + * + * @param pvParameter1 The value of the callback function's first parameter. + * The parameter has a void * type to allow it to be used to pass any type. + * For example, unsigned longs can be cast to a void *, or the void * can be + * used to point to a structure. + * + * @param ulParameter2 The value of the callback function's second parameter. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task (which is set using + * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of + * the currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE within + * xTimerPendFunctionCallFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return pdPASS is returned if the message was successfully sent to the + * timer daemon task, otherwise pdFALSE is returned. + * + * Example usage: + * @verbatim + * + * // The callback function that will execute in the context of the daemon task. + * // Note callback functions must all use this same prototype. + * void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 ) + * { + * BaseType_t xInterfaceToService; + * + * // The interface that requires servicing is passed in the second + * // parameter. The first parameter is not used in this case. + * xInterfaceToService = ( BaseType_t ) ulParameter2; + * + * // ...Perform the processing here... + * } + * + * // An ISR that receives data packets from multiple interfaces + * void vAnISR( void ) + * { + * BaseType_t xInterfaceToService, xHigherPriorityTaskWoken; + * + * // Query the hardware to determine which interface needs processing. + * xInterfaceToService = prvCheckInterfaces(); + * + * // The actual processing is to be deferred to a task. Request the + * // vProcessInterface() callback function is executed, passing in the + * // number of the interface that needs processing. The interface to + * // service is passed in the second parameter. The first parameter is + * // not used in this case. + * xHigherPriorityTaskWoken = pdFALSE; + * xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken ); + * + * // If xHigherPriorityTaskWoken is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and will + * // be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to + * // the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * + * } + * @endverbatim + */ +//go:linkname XTimerPendFunctionCallFromISR C.xTimerPendFunctionCallFromISR +func XTimerPendFunctionCallFromISR(xFunctionToPend PendedFunctionT, pvParameter1 c.Pointer, ulParameter2 c.Uint32T, pxHigherPriorityTaskWoken *BaseTypeT) BaseTypeT + +/** + * + * + * Used to defer the execution of a function to the RTOS daemon task (the timer + * service task, hence this function is implemented in timers.c and is prefixed + * with 'Timer'). + * + * @param xFunctionToPend The function to execute from the timer service/ + * daemon task. The function must conform to the PendedFunction_t + * prototype. + * + * @param pvParameter1 The value of the callback function's first parameter. + * The parameter has a void * type to allow it to be used to pass any type. + * For example, unsigned longs can be cast to a void *, or the void * can be + * used to point to a structure. + * + * @param ulParameter2 The value of the callback function's second parameter. + * + * @param xTicksToWait Calling this function will result in a message being + * sent to the timer daemon task on a queue. xTicksToWait is the amount of + * time the calling task should remain in the Blocked state (so not using any + * processing time) for space to become available on the timer queue if the + * queue is found to be full. + * + * @return pdPASS is returned if the message was successfully sent to the + * timer daemon task, otherwise pdFALSE is returned. + * + */ +//go:linkname XTimerPendFunctionCall C.xTimerPendFunctionCall +func XTimerPendFunctionCall(xFunctionToPend PendedFunctionT, pvParameter1 c.Pointer, ulParameter2 c.Uint32T, xTicksToWait TickTypeT) BaseTypeT + +/** + * + * Returns the name that was assigned to a timer when the timer was created. + * + * @param xTimer The handle of the timer being queried. + * + * @return The name assigned to the timer specified by the xTimer parameter. + */ +//go:linkname PcTimerGetName C.pcTimerGetName +func PcTimerGetName(xTimer TimerHandleT) *c.Char + +/** + * + * Updates a timer to be either an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being updated. + * + * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the timer's period (see the + * xTimerPeriodInTicks parameter of the xTimerCreate() API function). If + * xAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + */ +//go:linkname VTimerSetReloadMode C.vTimerSetReloadMode +func VTimerSetReloadMode(xTimer TimerHandleT, xAutoReload BaseTypeT) + +/** + * + * Queries a timer to determine if it is an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise + * pdFALSE is returned. + */ +//go:linkname XTimerGetReloadMode C.xTimerGetReloadMode +func XTimerGetReloadMode(xTimer TimerHandleT) BaseTypeT + +/** + * + * Queries a timer to determine if it is an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise + * pdFALSE is returned. + */ +//go:linkname UxTimerGetReloadMode C.uxTimerGetReloadMode +func UxTimerGetReloadMode(xTimer TimerHandleT) UBaseTypeT + +/** + * + * Returns the period of a timer. + * + * @param xTimer The handle of the timer being queried. + * + * @return The period of the timer in ticks. + */ +//go:linkname XTimerGetPeriod C.xTimerGetPeriod +func XTimerGetPeriod(xTimer TimerHandleT) TickTypeT + +/** + * + * Returns the time in ticks at which the timer will expire. If this is less + * than the current tick count then the expiry time has overflowed from the + * current time. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is running then the time in ticks at which the timer + * will next expire is returned. If the timer is not running then the return + * value is undefined. + */ +//go:linkname XTimerGetExpiryTime C.xTimerGetExpiryTime +func XTimerGetExpiryTime(xTimer TimerHandleT) TickTypeT + +/** + * + * Retrieve pointer to a statically created timer's data structure + * buffer. This is the same buffer that is supplied at the time of + * creation. + * + * @param xTimer The timer for which to retrieve the buffer. + * + * @param ppxTimerBuffer Used to return a pointer to the timers's data + * structure buffer. + * + * @return pdTRUE if the buffer was retrieved, pdFALSE otherwise. + */ +//go:linkname XTimerGetStaticBuffer C.xTimerGetStaticBuffer +func XTimerGetStaticBuffer(xTimer TimerHandleT, ppxTimerBuffer **StaticTimerT) BaseTypeT + +/* + * Functions beyond this part are not part of the public API and are intended + * for use by the kernel only. + */ +//go:linkname XTimerCreateTimerTask C.xTimerCreateTimerTask +func XTimerCreateTimerTask() BaseTypeT + +//go:linkname XTimerGenericCommand C.xTimerGenericCommand +func XTimerGenericCommand(xTimer TimerHandleT, xCommandID BaseTypeT, xOptionalValue TickTypeT, pxHigherPriorityTaskWoken *BaseTypeT, xTicksToWait TickTypeT) BaseTypeT + +/** + * + * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Timer Task TCB. This function is required when + * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION + * + * @param ppxTimerTaskTCBBuffer A handle to a statically allocated TCB buffer + * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task + * @param pulTimerTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer + */ +//go:linkname VApplicationGetTimerTaskMemory C.vApplicationGetTimerTaskMemory +func VApplicationGetTimerTaskMemory(ppxTimerTaskTCBBuffer **StaticTaskT, ppxTimerTaskStackBuffer **StackTypeT, pulTimerTaskStackSize *c.Uint32T) diff --git a/esp32/tjpgd.go b/esp32/tjpgd.go new file mode 100644 index 00000000..c52f76c5 --- /dev/null +++ b/esp32/tjpgd.go @@ -0,0 +1,82 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const JD_SZBUF = 512 +const JD_FORMAT = 0 +const JD_USE_SCALE = 1 +const JD_TBLCLIP = 1 + +type INT c.Int +type UINT c.Uint +type CHAR c.Char +type UCHAR c.Char +type BYTE c.Char +type SHORT int16 +type USHORT uint16 +type WORD uint16 +type WCHAR uint16 +type LONG c.Long +type ULONG c.Ulong +type DWORD c.Ulong +type JRESULT c.Int + +const ( + JDR_OK JRESULT = 0 + JDR_INTR JRESULT = 1 + JDR_INP JRESULT = 2 + JDR_MEM1 JRESULT = 3 + JDR_MEM2 JRESULT = 4 + JDR_PAR JRESULT = 5 + JDR_FMT1 JRESULT = 6 + JDR_FMT2 JRESULT = 7 + JDR_FMT3 JRESULT = 8 +) + +/* Rectangular structure */ + +type JRECT struct { + Left WORD + Right WORD + Top WORD + Bottom WORD +} + +type JDEC struct { + Dctr UINT + Dptr *BYTE + Inbuf *BYTE + Dmsk BYTE + Scale BYTE + Msx BYTE + Msy BYTE + Qtid [3]BYTE + Dcv [3]SHORT + Nrst WORD + Width UINT + Height UINT + Huffbits [2][2]*BYTE + Huffcode [2][2]*WORD + Huffdata [2][2]*BYTE + Qttbl [4]*LONG + Workbuf c.Pointer + Mcubuf *BYTE + Pool c.Pointer + SzPool UINT + Infunc c.Pointer + Device c.Pointer +} + +/* TJpgDec API functions */ +// llgo:link (*JDEC).JdPrepare C.jd_prepare +func (recv_ *JDEC) JdPrepare(func(*JDEC, *BYTE, UINT) UINT, c.Pointer, UINT, c.Pointer) JRESULT { + return 0 +} + +// llgo:link (*JDEC).JdDecomp C.jd_decomp +func (recv_ *JDEC) JdDecomp(func(*JDEC, c.Pointer, *JRECT) UINT, BYTE) JRESULT { + return 0 +} diff --git a/esp32/touch_channel.go b/esp32/touch_channel.go new file mode 100644 index 00000000..93480386 --- /dev/null +++ b/esp32/touch_channel.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +const TOUCH_PAD_NUM0_GPIO_NUM = 4 diff --git a/esp32/touch_sensor_channel.go b/esp32/touch_sensor_channel.go new file mode 100644 index 00000000..a716c8de --- /dev/null +++ b/esp32/touch_sensor_channel.go @@ -0,0 +1,18 @@ +package freertos + +import _ "unsafe" + +const TOUCH_PAD_NUM1_GPIO_NUM = 1 +const TOUCH_PAD_NUM2_GPIO_NUM = 2 +const TOUCH_PAD_NUM3_GPIO_NUM = 3 +const TOUCH_PAD_NUM4_GPIO_NUM = 4 +const TOUCH_PAD_NUM5_GPIO_NUM = 5 +const TOUCH_PAD_NUM6_GPIO_NUM = 6 +const TOUCH_PAD_NUM7_GPIO_NUM = 7 +const TOUCH_PAD_NUM8_GPIO_NUM = 8 +const TOUCH_PAD_NUM9_GPIO_NUM = 9 +const TOUCH_PAD_NUM10_GPIO_NUM = 10 +const TOUCH_PAD_NUM11_GPIO_NUM = 11 +const TOUCH_PAD_NUM12_GPIO_NUM = 12 +const TOUCH_PAD_NUM13_GPIO_NUM = 13 +const TOUCH_PAD_NUM14_GPIO_NUM = 14 diff --git a/esp32/touch_sensor_hal.go b/esp32/touch_sensor_hal.go new file mode 100644 index 00000000..6e1c9185 --- /dev/null +++ b/esp32/touch_sensor_hal.go @@ -0,0 +1,160 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Set parameter of touch sensor filter and detection algorithm. + * For more details on the detection algorithm, please refer to the application documentation. + * + * @param filter_info select filter type and threshold of detection algorithm + */ +// llgo:link (*TouchFilterConfigT).TouchHalFilterSetConfig C.touch_hal_filter_set_config +func (recv_ *TouchFilterConfigT) TouchHalFilterSetConfig() { +} + +/** + * Get parameter of touch sensor filter and detection algorithm. + * For more details on the detection algorithm, please refer to the application documentation. + * + * @param filter_info select filter type and threshold of detection algorithm + */ +// llgo:link (*TouchFilterConfigT).TouchHalFilterGetConfig C.touch_hal_filter_get_config +func (recv_ *TouchFilterConfigT) TouchHalFilterGetConfig() { +} + +/** + * set parameter of denoise pad (TOUCH_PAD_NUM0). + * T0 is an internal channel that does not have a corresponding external GPIO. + * T0 will work simultaneously with the measured channel Tn. Finally, the actual + * measured value of Tn is the value after subtracting lower bits of T0. + * This denoise function filters out interference introduced on all channels, + * such as noise introduced by the power supply and external EMI. + * + * @param denoise parameter of denoise + */ +// llgo:link (*TouchPadDenoiseT).TouchHalDenoiseSetConfig C.touch_hal_denoise_set_config +func (recv_ *TouchPadDenoiseT) TouchHalDenoiseSetConfig() { +} + +/** + * @brief get parameter of denoise pad (TOUCH_PAD_NUM0). + * + * @param denoise Pointer to parameter of denoise + */ +// llgo:link (*TouchPadDenoiseT).TouchHalDenoiseGetConfig C.touch_hal_denoise_get_config +func (recv_ *TouchPadDenoiseT) TouchHalDenoiseGetConfig() { +} + +/** + * Enable denoise function. + * T0 is an internal channel that does not have a corresponding external GPIO. + * T0 will work simultaneously with the measured channel Tn. Finally, the actual + * measured value of Tn is the value after subtracting lower bits of T0. + * This denoise function filters out interference introduced on all channels, + * such as noise introduced by the power supply and external EMI. + */ +//go:linkname TouchHalDenoiseEnable C.touch_hal_denoise_enable +func TouchHalDenoiseEnable() + +/** + * Set parameter of waterproof function. + * + * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel. + * Guard pad is used to detect the large area of water covering the touch panel. + * Shield pad is used to shield the influence of water droplets covering the touch panel. + * It is generally designed as a grid and is placed around the touch buttons. + * + * @param waterproof parameter of waterproof + */ +// llgo:link (*TouchPadWaterproofT).TouchHalWaterproofSetConfig C.touch_hal_waterproof_set_config +func (recv_ *TouchPadWaterproofT) TouchHalWaterproofSetConfig() { +} + +/** + * Get parameter of waterproof function. + * + * @param waterproof parameter of waterproof. + */ +// llgo:link (*TouchPadWaterproofT).TouchHalWaterproofGetConfig C.touch_hal_waterproof_get_config +func (recv_ *TouchPadWaterproofT) TouchHalWaterproofGetConfig() { +} + +/** + * Enable parameter of waterproof function. + * Should be called after function ``touch_hal_waterproof_set_config``. + */ +//go:linkname TouchHalWaterproofEnable C.touch_hal_waterproof_enable +func TouchHalWaterproofEnable() + +/** + * Enable/disable proximity function of touch channels. + * The proximity sensor measurement is the accumulation of touch channel measurements. + * + * @note Supports up to three touch channels configured as proximity sensors. + * @param touch_num touch pad index + * @param enabled true: enable the proximity function; false: disable the proximity function + * @return + * - true: Configured correctly. + * - false: Configured error. + */ +// llgo:link TouchPadT.TouchHalEnableProximity C.touch_hal_enable_proximity +func (recv_ TouchPadT) TouchHalEnableProximity(enabled bool) bool { + return false +} + +/** + * Get parameter of touch sensor sleep channel. + * The touch sensor can works in sleep mode to wake up sleep. + * After the sleep channel is configured, users should query the channel reading using a specific function. + * + * @param slp_config Point to touch sleep pad config. + */ +// llgo:link (*TouchPadSleepChannelT).TouchHalSleepChannelGetConfig C.touch_hal_sleep_channel_get_config +func (recv_ *TouchPadSleepChannelT) TouchHalSleepChannelGetConfig() { +} + +/** + * Set parameter of touch sensor sleep channel. + * The touch sensor can works in sleep mode to wake up sleep. + * After the sleep channel is configured, users should query the channel reading using a specific function. + * + * @note ESP32S2 only support one channel to be set sleep channel. + * + * @param pad_num touch sleep pad number. + * @param enable Enable/disable sleep pad function. + */ +// llgo:link TouchPadT.TouchHalSleepChannelEnable C.touch_hal_sleep_channel_enable +func (recv_ TouchPadT) TouchHalSleepChannelEnable(enable bool) { +} + +/** + * Change the operating frequency of touch pad in deep sleep state. Reducing the operating frequency can effectively reduce power consumption. + * If this function is not called, the working frequency of touch in the deep sleep state is the same as that in the wake-up state. + * + * @param sleep_cycle The touch sensor will sleep after each measurement. + * sleep_cycle decide the interval between each measurement. + * t_sleep = sleep_cycle / (RTC_SLOW_CLK frequency). + * The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function. + * @param meas_times The times of charge and discharge in each measure process of touch channels. + * The timer frequency is 8Mhz. Range: 0 ~ 0xffff. + * Recommended typical value: Modify this value to make the measurement time around 1ms. + */ +//go:linkname TouchHalSleepChannelSetWorkTime C.touch_hal_sleep_channel_set_work_time +func TouchHalSleepChannelSetWorkTime(sleep_cycle c.Uint16T, meas_times c.Uint16T) + +/** + * Get the operating frequency of touch pad in deep sleep state. Reducing the operating frequency can effectively reduce power consumption. + * + * @param sleep_cycle The touch sensor will sleep after each measurement. + * sleep_cycle decide the interval between each measurement. + * t_sleep = sleep_cycle / (RTC_SLOW_CLK frequency). + * The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function. + * @param meas_times The times of charge and discharge in each measure process of touch channels. + * The timer frequency is 8Mhz. Range: 0 ~ 0xffff. + * Recommended typical value: Modify this value to make the measurement time around 1ms. + */ +//go:linkname TouchHalSleepChannelGetWorkTime C.touch_hal_sleep_channel_get_work_time +func TouchHalSleepChannelGetWorkTime(sleep_cycle *c.Uint16T, meas_times *c.Uint16T) diff --git a/esp32/touch_sensor_ll.go b/esp32/touch_sensor_ll.go new file mode 100644 index 00000000..ece62750 --- /dev/null +++ b/esp32/touch_sensor_ll.go @@ -0,0 +1,9 @@ +package freertos + +import _ "unsafe" + +const TOUCH_LL_READ_RAW = 0x0 +const TOUCH_LL_READ_BENCHMARK = 0x2 +const TOUCH_LL_READ_SMOOTH = 0x3 +const TOUCH_LL_TIMER_FORCE_DONE = 0x3 +const TOUCH_LL_TIMER_DONE = 0x0 diff --git a/esp32/touch_sensor_pins.go b/esp32/touch_sensor_pins.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/touch_sensor_pins.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/touch_sensor_types.go b/esp32/touch_sensor_types.go new file mode 100644 index 00000000..fc6b6c1e --- /dev/null +++ b/esp32/touch_sensor_types.go @@ -0,0 +1,221 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type TouchPadT c.Int + +const ( + TOUCH_PAD_NUM0 TouchPadT = 0 + TOUCH_PAD_NUM1 TouchPadT = 1 + TOUCH_PAD_NUM2 TouchPadT = 2 + TOUCH_PAD_NUM3 TouchPadT = 3 + TOUCH_PAD_NUM4 TouchPadT = 4 + TOUCH_PAD_NUM5 TouchPadT = 5 + TOUCH_PAD_NUM6 TouchPadT = 6 + TOUCH_PAD_NUM7 TouchPadT = 7 + TOUCH_PAD_NUM8 TouchPadT = 8 + TOUCH_PAD_NUM9 TouchPadT = 9 + TOUCH_PAD_NUM10 TouchPadT = 10 + TOUCH_PAD_NUM11 TouchPadT = 11 + TOUCH_PAD_NUM12 TouchPadT = 12 + TOUCH_PAD_NUM13 TouchPadT = 13 + TOUCH_PAD_NUM14 TouchPadT = 14 + TOUCH_PAD_MAX TouchPadT = 15 +) + +type TouchHighVoltT c.Int + +const ( + TOUCH_HVOLT_KEEP TouchHighVoltT = -1 + TOUCH_HVOLT_2V4 TouchHighVoltT = 0 + TOUCH_HVOLT_2V5 TouchHighVoltT = 1 + TOUCH_HVOLT_2V6 TouchHighVoltT = 2 + TOUCH_HVOLT_2V7 TouchHighVoltT = 3 + TOUCH_HVOLT_MAX TouchHighVoltT = 4 +) + +type TouchLowVoltT c.Int + +const ( + TOUCH_LVOLT_KEEP TouchLowVoltT = -1 + TOUCH_LVOLT_0V5 TouchLowVoltT = 0 + TOUCH_LVOLT_0V6 TouchLowVoltT = 1 + TOUCH_LVOLT_0V7 TouchLowVoltT = 2 + TOUCH_LVOLT_0V8 TouchLowVoltT = 3 + TOUCH_LVOLT_MAX TouchLowVoltT = 4 +) + +type TouchVoltAttenT c.Int + +const ( + TOUCH_HVOLT_ATTEN_KEEP TouchVoltAttenT = -1 + TOUCH_HVOLT_ATTEN_1V5 TouchVoltAttenT = 0 + TOUCH_HVOLT_ATTEN_1V TouchVoltAttenT = 1 + TOUCH_HVOLT_ATTEN_0V5 TouchVoltAttenT = 2 + TOUCH_HVOLT_ATTEN_0V TouchVoltAttenT = 3 + TOUCH_HVOLT_ATTEN_MAX TouchVoltAttenT = 4 +) + +type TouchCntSlopeT c.Int + +const ( + TOUCH_PAD_SLOPE_0 TouchCntSlopeT = 0 + TOUCH_PAD_SLOPE_1 TouchCntSlopeT = 1 + TOUCH_PAD_SLOPE_2 TouchCntSlopeT = 2 + TOUCH_PAD_SLOPE_3 TouchCntSlopeT = 3 + TOUCH_PAD_SLOPE_4 TouchCntSlopeT = 4 + TOUCH_PAD_SLOPE_5 TouchCntSlopeT = 5 + TOUCH_PAD_SLOPE_6 TouchCntSlopeT = 6 + TOUCH_PAD_SLOPE_7 TouchCntSlopeT = 7 + TOUCH_PAD_SLOPE_MAX TouchCntSlopeT = 8 +) + +type TouchTieOptT c.Int + +const ( + TOUCH_PAD_TIE_OPT_LOW TouchTieOptT = 0 + TOUCH_PAD_TIE_OPT_HIGH TouchTieOptT = 1 + TOUCH_PAD_TIE_OPT_FLOAT TouchTieOptT = 2 + TOUCH_PAD_TIE_OPT_MAX TouchTieOptT = 3 +) + +type TouchFsmModeT c.Int + +const ( + TOUCH_FSM_MODE_TIMER TouchFsmModeT = 0 + TOUCH_FSM_MODE_SW TouchFsmModeT = 1 + TOUCH_FSM_MODE_MAX TouchFsmModeT = 2 +) + +type TouchTriggerModeT c.Int + +const ( + TOUCH_TRIGGER_BELOW TouchTriggerModeT = 0 + TOUCH_TRIGGER_ABOVE TouchTriggerModeT = 1 + TOUCH_TRIGGER_MAX TouchTriggerModeT = 2 +) + +type TouchTriggerSrcT c.Int + +const ( + TOUCH_TRIGGER_SOURCE_BOTH TouchTriggerSrcT = 0 + TOUCH_TRIGGER_SOURCE_SET1 TouchTriggerSrcT = 1 + TOUCH_TRIGGER_SOURCE_MAX TouchTriggerSrcT = 2 +) + +type TouchPadIntrMaskT c.Int + +const ( + TOUCH_PAD_INTR_MASK_DONE TouchPadIntrMaskT = 1 + TOUCH_PAD_INTR_MASK_ACTIVE TouchPadIntrMaskT = 2 + TOUCH_PAD_INTR_MASK_INACTIVE TouchPadIntrMaskT = 4 + TOUCH_PAD_INTR_MASK_SCAN_DONE TouchPadIntrMaskT = 8 + TOUCH_PAD_INTR_MASK_TIMEOUT TouchPadIntrMaskT = 16 + TOUCH_PAD_INTR_MASK_PROXI_MEAS_DONE TouchPadIntrMaskT = 32 + TOUCH_PAD_INTR_MASK_MAX TouchPadIntrMaskT = 33 +) + +type TouchPadDenoiseGradeT c.Int + +const ( + TOUCH_PAD_DENOISE_BIT12 TouchPadDenoiseGradeT = 0 + TOUCH_PAD_DENOISE_BIT10 TouchPadDenoiseGradeT = 1 + TOUCH_PAD_DENOISE_BIT8 TouchPadDenoiseGradeT = 2 + TOUCH_PAD_DENOISE_BIT4 TouchPadDenoiseGradeT = 3 + TOUCH_PAD_DENOISE_MAX TouchPadDenoiseGradeT = 4 +) + +type TouchPadDenoiseCapT c.Int + +const ( + TOUCH_PAD_DENOISE_CAP_L0 TouchPadDenoiseCapT = 0 + TOUCH_PAD_DENOISE_CAP_L1 TouchPadDenoiseCapT = 1 + TOUCH_PAD_DENOISE_CAP_L2 TouchPadDenoiseCapT = 2 + TOUCH_PAD_DENOISE_CAP_L3 TouchPadDenoiseCapT = 3 + TOUCH_PAD_DENOISE_CAP_L4 TouchPadDenoiseCapT = 4 + TOUCH_PAD_DENOISE_CAP_L5 TouchPadDenoiseCapT = 5 + TOUCH_PAD_DENOISE_CAP_L6 TouchPadDenoiseCapT = 6 + TOUCH_PAD_DENOISE_CAP_L7 TouchPadDenoiseCapT = 7 + TOUCH_PAD_DENOISE_CAP_MAX TouchPadDenoiseCapT = 8 +) + +/** Touch sensor denoise configuration */ + +type TouchPadDenoise struct { + Grade TouchPadDenoiseGradeT + CapLevel TouchPadDenoiseCapT +} +type TouchPadDenoiseT TouchPadDenoise +type TouchPadShieldDriverT c.Int + +const ( + TOUCH_PAD_SHIELD_DRV_L0 TouchPadShieldDriverT = 0 + TOUCH_PAD_SHIELD_DRV_L1 TouchPadShieldDriverT = 1 + TOUCH_PAD_SHIELD_DRV_L2 TouchPadShieldDriverT = 2 + TOUCH_PAD_SHIELD_DRV_L3 TouchPadShieldDriverT = 3 + TOUCH_PAD_SHIELD_DRV_L4 TouchPadShieldDriverT = 4 + TOUCH_PAD_SHIELD_DRV_L5 TouchPadShieldDriverT = 5 + TOUCH_PAD_SHIELD_DRV_L6 TouchPadShieldDriverT = 6 + TOUCH_PAD_SHIELD_DRV_L7 TouchPadShieldDriverT = 7 + TOUCH_PAD_SHIELD_DRV_MAX TouchPadShieldDriverT = 8 +) + +/** Touch sensor waterproof configuration */ + +type TouchPadWaterproof struct { + GuardRingPad TouchPadT + ShieldDriver TouchPadShieldDriverT +} +type TouchPadWaterproofT TouchPadWaterproof +type TouchPadConnTypeT c.Int + +const ( + TOUCH_PAD_CONN_HIGHZ TouchPadConnTypeT = 0 + TOUCH_PAD_CONN_GND TouchPadConnTypeT = 1 + TOUCH_PAD_CONN_MAX TouchPadConnTypeT = 2 +) + +type TouchFilterModeT c.Int + +const ( + TOUCH_PAD_FILTER_IIR_4 TouchFilterModeT = 0 + TOUCH_PAD_FILTER_IIR_8 TouchFilterModeT = 1 + TOUCH_PAD_FILTER_IIR_16 TouchFilterModeT = 2 + TOUCH_PAD_FILTER_IIR_32 TouchFilterModeT = 3 + TOUCH_PAD_FILTER_IIR_64 TouchFilterModeT = 4 + TOUCH_PAD_FILTER_IIR_128 TouchFilterModeT = 5 + TOUCH_PAD_FILTER_IIR_256 TouchFilterModeT = 6 + TOUCH_PAD_FILTER_JITTER TouchFilterModeT = 7 + TOUCH_PAD_FILTER_MAX TouchFilterModeT = 8 +) + +type TouchSmoothModeT c.Int + +const ( + TOUCH_PAD_SMOOTH_OFF TouchSmoothModeT = 0 + TOUCH_PAD_SMOOTH_IIR_2 TouchSmoothModeT = 1 + TOUCH_PAD_SMOOTH_IIR_4 TouchSmoothModeT = 2 + TOUCH_PAD_SMOOTH_IIR_8 TouchSmoothModeT = 3 + TOUCH_PAD_SMOOTH_MAX TouchSmoothModeT = 4 +) + +/** Touch sensor filter configuration */ + +type TouchFilterConfig struct { + Mode TouchFilterModeT + DebounceCnt c.Uint32T + NoiseThr c.Uint32T + JitterStep c.Uint32T + SmhLvl TouchSmoothModeT +} +type TouchFilterConfigT TouchFilterConfig + +/** Touch sensor channel sleep configuration */ + +type TouchPadSleepChannelT struct { + TouchNum TouchPadT + EnProximity bool +} diff --git a/esp32/tracemem_config.go b/esp32/tracemem_config.go new file mode 100644 index 00000000..abc0c24c --- /dev/null +++ b/esp32/tracemem_config.go @@ -0,0 +1,6 @@ +package freertos + +import _ "unsafe" + +const TRACEMEM_MUX_BLK0_NUM = 22 +const TRACEMEM_MUX_BLK1_NUM = 26 diff --git a/esp32/trax.go b/esp32/trax.go new file mode 100644 index 00000000..a4a91ed9 --- /dev/null +++ b/esp32/trax.go @@ -0,0 +1,69 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type TraxDowncountUnitT c.Int + +const ( + TRAX_DOWNCOUNT_WORDS TraxDowncountUnitT = 0 + TRAX_DOWNCOUNT_INSTRUCTIONS TraxDowncountUnitT = 1 +) + +type TraxEnaSelectT c.Int + +const ( + TRAX_ENA_NONE TraxEnaSelectT = 0 + TRAX_ENA_PRO TraxEnaSelectT = 1 + TRAX_ENA_APP TraxEnaSelectT = 2 + TRAX_ENA_PRO_APP TraxEnaSelectT = 3 + TRAX_ENA_PRO_APP_SWAP TraxEnaSelectT = 4 +) + +/** + * @brief Enable the trax memory blocks to be used as Trax memory. + * + * @param pro_cpu_enable : true if Trax needs to be enabled for the pro CPU + * @param app_cpu_enable : true if Trax needs to be enabled for the pro CPU + * @param swap_regions : Normally, the pro CPU writes to Trax mem block 0 while + * the app cpu writes to block 1. Setting this to true + * inverts this. + * + * @return esp_err_t. Fails with ESP_ERR_NO_MEM if Trax enable is requested for 2 CPUs + * but memmap only has room for 1, or if Trax memmap is disabled + * entirely. + */ +// llgo:link TraxEnaSelectT.TraxEnable C.trax_enable +func (recv_ TraxEnaSelectT) TraxEnable() c.Int { + return 0 +} + +/** + * @brief Start a Trax trace on the current CPU + * + * @param units_until_stop : Set the units of the delay that gets passed to + * trax_trigger_traceend_after_delay. One of TRAX_DOWNCOUNT_WORDS + * or TRAX_DOWNCOUNT_INSTRUCTIONS. + * + * @return esp_err_t. Fails with ESP_ERR_NO_MEM if Trax is disabled. + */ +// llgo:link TraxDowncountUnitT.TraxStartTrace C.trax_start_trace +func (recv_ TraxDowncountUnitT) TraxStartTrace() c.Int { + return 0 +} + +/** + * @brief Trigger a Trax trace stop after the indicated delay. If this is called + * before and the previous delay hasn't ended yet, this will overwrite + * that delay with the new value. The delay will always start at the time + * the function is called. + * + * @param delay : The delay to stop the trace in, in the unit indicated to + * trax_start_trace. Note: the trace memory has 4K words available. + * + * @return esp_err_t + */ +//go:linkname TraxTriggerTraceendAfterDelay C.trax_trigger_traceend_after_delay +func TraxTriggerTraceendAfterDelay(delay c.Int) c.Int diff --git a/esp32/traxreg.go b/esp32/traxreg.go new file mode 100644 index 00000000..095b1261 --- /dev/null +++ b/esp32/traxreg.go @@ -0,0 +1,76 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const SHOW = 1 +const HIDE = 0 +const RO = 0 +const RW = 1 +const TRAX_ID_PRODNO = 0xf0000000 +const TRAX_ID_PRODOPT = 0x0f000000 +const TRAX_ID_MIW64 = 0x08000000 +const TRAX_ID_AMTRAX = 0x04000000 +const TRAX_ID_STDCFG = 0x00010000 +const TRAX_ID_CFGID = 0x0000ffff +const TRAX_ID_MEMSHARED = 0x00001000 +const TRAX_VER_1_0 = 0x10 +const TRAX_VER_1_1 = 0x11 +const TRAX_VER_2_0 = 0x20 +const TRAX_VER_2_1 = 0x21 +const TRAX_VER_3_0 = 0x30 +const TRAX_VER_3_1 = 0x31 +const TRAX_CONTROL_TREN = 0x00000001 +const TRAX_CONTROL_TRSTP = 0x00000002 +const TRAX_CONTROL_PCMEN = 0x00000004 +const TRAX_CONTROL_PTIEN = 0x00000010 +const TRAX_CONTROL_CTIEN = 0x00000020 +const TRAX_CONTROL_TMEN = 0x00000080 +const TRAX_CONTROL_CNTU = 0x00000200 +const TRAX_CONTROL_BIEN = 0x00000400 +const TRAX_CONTROL_BOEN = 0x00000800 +const TRAX_CONTROL_TSEN = 0x00000800 +const TRAX_CONTROL_SMPER = 0x00007000 +const TRAX_CONTROL_SMPER_SHIFT = 12 +const TRAX_CONTROL_PTOWT = 0x00010000 +const TRAX_CONTROL_CTOWT = 0x00020000 +const TRAX_CONTROL_PTOWS = 0x00100000 +const TRAX_CONTROL_CTOWS = 0x00200000 +const TRAX_CONTROL_ATID = 0x7F000000 +const TRAX_CONTROL_ATID_SHIFT = 24 +const TRAX_CONTROL_ATEN = 0x80000000 +const TRAX_CONTROL_PTOWS_ER = 0x00020000 +const TRAX_CONTROL_CTOWT_ER = 0x00100000 +const TRAX_CONTROL_ITCTO = 0x00400000 +const TRAX_CONTROL_ITCTIA = 0x00800000 +const TRAX_CONTROL_ITATV = 0x01000000 +const TRAX_STATUS_TRACT = 0x00000001 +const TRAX_STATUS_TRIG = 0x00000002 +const TRAX_STATUS_PCMTG = 0x00000004 +const TRAX_STATUS_BUSY = 0x00000008 +const TRAX_STATUS_PTITG = 0x00000010 +const TRAX_STATUS_CTITG = 0x00000020 +const TRAX_STATUS_MEMSZ = 0x00001F00 +const TRAX_STATUS_MEMSZ_SHIFT = 8 +const TRAX_STATUS_PTO = 0x00010000 +const TRAX_STATUS_CTO = 0x00020000 +const TRAX_STATUS_ITCTOA = 0x00400000 +const TRAX_STATUS_ITCTI = 0x00800000 +const TRAX_STATUS_ITATR = 0x01000000 +const TRAX_ADDRESS_TWSAT = 0x80000000 +const TRAX_ADDRESS_TWSAT_SHIFT = 31 +const TRAX_ADDRESS_TOTALMASK = 0x00FFFFFF +const TRAX_ADDRESS_WRAPCNT = 0x7FE00000 +const TRAX_ADDRESS_WRAP_SHIFT = 21 +const TRAX_PCMATCH_PCML = 0x0000001F +const TRAX_PCMATCH_PCML_SHIFT = 0 +const TRAX_PCMATCH_PCMS = 0x80000000 + +/* Prototypes: */ +//go:linkname TraxFindReg C.trax_find_reg +func TraxFindReg(regname *c.Char, errmsg **c.Char) c.Int + +//go:linkname TraxRegname C.trax_regname +func TraxRegname(regno c.Int) *c.Char diff --git a/esp32/twai_hal.go b/esp32/twai_hal.go new file mode 100644 index 00000000..fce24653 --- /dev/null +++ b/esp32/twai_hal.go @@ -0,0 +1,121 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type TwaiHalFrameT TwaiLlFrameBufferT + +type TwaiHalContextT struct { + Dev *TwaiDevT + StateFlags c.Uint32T + ClockSourceHz c.Uint32T +} + +/* ---------------------------- Init and Config ----------------------------- */ + +type TwaiHalConfigT struct { + ControllerId c.Int + ClockSourceHz c.Uint32T +} + +/** + * @brief Initialize TWAI peripheral and HAL context + * + * Sets HAL context, puts TWAI peripheral into reset mode, then sets some + * registers with default values. + * + * @param hal_ctx Context of the HAL layer + * @param config HAL driver configuration + * @return True if successfully initialized, false otherwise. + */ +// llgo:link (*TwaiHalContextT).TwaiHalInit C.twai_hal_init +func (recv_ *TwaiHalContextT) TwaiHalInit(config *TwaiHalConfigT) bool { + return false +} + +/** + * @brief Deinitialize the TWAI peripheral and HAL context + * + * Clears any unhandled interrupts and unsets HAL context + * + * @param hal_ctx Context of the HAL layer + */ +// llgo:link (*TwaiHalContextT).TwaiHalDeinit C.twai_hal_deinit +func (recv_ *TwaiHalContextT) TwaiHalDeinit() { +} + +/** + * @brief Configure the TWAI peripheral + * + * @param hal_ctx Context of the HAL layer + * @param t_config Pointer to timing configuration structure + * @param f_config Pointer to filter configuration structure + * @param intr_mask Mask of interrupts to enable + * @param clkout_divider Clock divider value for CLKOUT. Set to -1 to disable CLKOUT + */ +// llgo:link (*TwaiHalContextT).TwaiHalConfigure C.twai_hal_configure +func (recv_ *TwaiHalContextT) TwaiHalConfigure(t_config *TwaiTimingConfigT, f_config *TwaiFilterConfigT, intr_mask c.Uint32T, clkout_divider c.Uint32T) { +} + +/** + * @brief Start the TWAI peripheral + * + * Start the TWAI peripheral by configuring its operating mode, then exiting + * reset mode so that the TWAI peripheral can participate in bus activities. + * + * @param hal_ctx Context of the HAL layer + * @param mode Operating mode + */ +// llgo:link (*TwaiHalContextT).TwaiHalStart C.twai_hal_start +func (recv_ *TwaiHalContextT) TwaiHalStart(mode TwaiModeT) { +} + +/** + * @brief Stop the TWAI peripheral + * + * Stop the TWAI peripheral by entering reset mode to stop any bus activity, then + * setting the operating mode to Listen Only so that REC is frozen. + * + * @param hal_ctx Context of the HAL layer + */ +// llgo:link (*TwaiHalContextT).TwaiHalStop C.twai_hal_stop +func (recv_ *TwaiHalContextT) TwaiHalStop() { +} + +/** + * @brief Get a bit mask of the events that triggered that triggered an interrupt + * + * This function should be called at the beginning of an interrupt. This function will do the following: + * - Read and clear interrupt register + * - Calculate what events have triggered the interrupt + * - Respond to low latency interrupt events + * - Bus off: Change to LOM to freeze TEC/REC. Errata 1 Fix + * - Recovery complete: Enter reset mode + * - Clear ECC and ALC so that their interrupts are re-armed + * - Update HAL state flags based on interrupts that have occurred. + * - For the ESP32, check for errata conditions. If a HW reset is required, this function + * will set the TWAI_HAL_EVENT_NEED_PERIPH_RESET event. + * + * @param hal_ctx Context of the HAL layer + * @return Bit mask of events that have occurred + */ +// llgo:link (*TwaiHalContextT).TwaiHalGetEvents C.twai_hal_get_events +func (recv_ *TwaiHalContextT) TwaiHalGetEvents() c.Uint32T { + return 0 +} + +/** + * @brief Copy a frame into the TX buffer and transmit + * + * This function copies a formatted TX frame into the TX buffer, and the + * transmit by setting the correct transmit command (e.g. normal, single shot, + * self RX) in the command register. + * + * @param hal_ctx Context of the HAL layer + * @param tx_frame Pointer to structure containing formatted TX frame + */ +// llgo:link (*TwaiHalContextT).TwaiHalSetTxBufferAndTransmit C.twai_hal_set_tx_buffer_and_transmit +func (recv_ *TwaiHalContextT) TwaiHalSetTxBufferAndTransmit(tx_frame *TwaiHalFrameT) { +} diff --git a/esp32/twai_ll.go b/esp32/twai_ll.go new file mode 100644 index 00000000..421ed320 --- /dev/null +++ b/esp32/twai_ll.go @@ -0,0 +1,19 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* + * The following frame structure has an NEARLY identical bit field layout to + * each byte of the TX buffer. This allows for formatting and parsing frames to + * be done outside of time critical regions (i.e., ISRs). All the ISR needs to + * do is to copy byte by byte to/from the TX/RX buffer. The two reserved bits in + * TX buffer are used in the frame structure to store the self_reception and + * single_shot flags which in turn indicate the type of transmission to execute. + */ + +type TwaiLlFrameBufferT struct { + Bytes [13]c.Uint8T +} diff --git a/esp32/twai_periph.go b/esp32/twai_periph.go new file mode 100644 index 00000000..5fa8faef --- /dev/null +++ b/esp32/twai_periph.go @@ -0,0 +1,18 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type TwaiControllerSignalConnT struct { + Controllers [1]struct { + Module PeriphModuleT + IrqId c.Int + TxSig c.Int + RxSig c.Int + ClkOutSig c.Int + BusOffSig c.Int + StandBySig c.Int + } +} diff --git a/esp32/twai_struct.go b/esp32/twai_struct.go new file mode 100644 index 00000000..4ed6c076 --- /dev/null +++ b/esp32/twai_struct.go @@ -0,0 +1,62 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* The TWAI peripheral's registers are 8bits, however the ESP32-S3 can only access + * peripheral registers every 32bits. Therefore each TWAI register is mapped to + * the least significant byte of every 32bits. + */ + +type TwaiDevS struct { + ModeReg struct { + Val c.Uint32T + } + CommandReg struct { + Val c.Uint32T + } + StatusReg struct { + Val c.Uint32T + } + InterruptReg struct { + Val c.Uint32T + } + InterruptEnableReg struct { + Val c.Uint32T + } + Reserved14 c.Uint32T + BusTiming0Reg struct { + Val c.Uint32T + } + BusTiming1Reg struct { + Val c.Uint32T + } + Reserved20 c.Uint32T + Reserved24 c.Uint32T + Reserved28 c.Uint32T + ArbitrationLostCaptueReg struct { + Val c.Uint32T + } + ErrorCodeCaptureReg struct { + Val c.Uint32T + } + ErrorWarningLimitReg struct { + Val c.Uint32T + } + RxErrorCounterReg struct { + Val c.Uint32T + } + TxErrorCounterReg struct { + Val c.Uint32T + } + RxMessageCounterReg struct { + Val c.Uint32T + } + Reserved78 c.Uint32T + ClockDividerReg struct { + Val c.Uint32T + } +} +type TwaiDevT TwaiDevS diff --git a/esp32/twai_types.go b/esp32/twai_types.go new file mode 100644 index 00000000..aacac488 --- /dev/null +++ b/esp32/twai_types.go @@ -0,0 +1,68 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const TWAI_EXTD_ID_MASK = 0x1FFFFFFF +const TWAI_STD_ID_MASK = 0x7FF +const TWAI_FRAME_MAX_DLC = 8 +const TWAI_FRAME_EXTD_ID_LEN_BYTES = 4 +const TWAI_FRAME_STD_ID_LEN_BYTES = 2 +const TWAI_ERR_PASS_THRESH = 128 +const TWAI_MSG_FLAG_NONE = 0x00 +const TWAI_MSG_FLAG_EXTD = 0x01 +const TWAI_MSG_FLAG_RTR = 0x02 +const TWAI_MSG_FLAG_SS = 0x04 +const TWAI_MSG_FLAG_SELF = 0x08 +const TWAI_MSG_FLAG_DLC_NON_COMP = 0x10 + +type TwaiModeT c.Int + +const ( + TWAI_MODE_NORMAL TwaiModeT = 0 + TWAI_MODE_NO_ACK TwaiModeT = 1 + TWAI_MODE_LISTEN_ONLY TwaiModeT = 2 +) + +/** + * @brief Structure to store a TWAI message + * + * @note The flags member is deprecated + */ + +type TwaiMessageT struct { + Identifier c.Uint32T + DataLengthCode c.Uint8T + Data [8]c.Uint8T +} +type TwaiClockSourceT SocPeriphTwaiClkSrcT + +/** + * @brief Structure for bit timing configuration of the TWAI driver + * + * @note Macro initializers are available for this structure + */ + +type TwaiTimingConfigT struct { + ClkSrc TwaiClockSourceT + QuantaResolutionHz c.Uint32T + Brp c.Uint32T + Tseg1 c.Uint8T + Tseg2 c.Uint8T + Sjw c.Uint8T + TripleSampling bool +} + +/** + * @brief Structure for acceptance filter configuration of the TWAI driver (see documentation) + * + * @note Macro initializers are available for this structure + */ + +type TwaiFilterConfigT struct { + AcceptanceCode c.Uint32T + AcceptanceMask c.Uint32T + SingleFilter bool +} diff --git a/esp32/uart.go b/esp32/uart.go new file mode 100644 index 00000000..84528c82 --- /dev/null +++ b/esp32/uart.go @@ -0,0 +1,317 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const RX_BUFF_SIZE = 0x400 +const TX_BUFF_SIZE = 100 +const UART_INT_FLAG_MASK = 0x0E +const FRAME_FLAG = 0x7E + +type UartIntType c.Int + +const ( + UART_LINE_STATUS_INT_FLAG UartIntType = 6 + UART_RCV_FIFO_INT_FLAG UartIntType = 4 + UART_RCV_TMOUT_INT_FLAG UartIntType = 12 + UART_TXBUFF_EMPTY_INT_FLAG UartIntType = 2 +) + +type UartRcvFifoTrgLvl c.Int + +const ( + RCV_ONE_BYTE UartRcvFifoTrgLvl = 0 + RCV_FOUR_BYTE UartRcvFifoTrgLvl = 1 + RCV_EIGHT_BYTE UartRcvFifoTrgLvl = 2 + RCV_FOURTEEN_BYTE UartRcvFifoTrgLvl = 3 +) + +type UartBitsNum4Char c.Int + +const ( + FIVE_BITS UartBitsNum4Char = 0 + SIX_BITS UartBitsNum4Char = 1 + SEVEN_BITS UartBitsNum4Char = 2 + EIGHT_BITS UartBitsNum4Char = 3 +) + +type UartStopBitsNum c.Int + +const ( + ONE_STOP_BIT UartStopBitsNum = 1 + ONE_HALF_STOP_BIT UartStopBitsNum = 2 + TWO_STOP_BIT UartStopBitsNum = 3 +) + +type UartParityMode c.Int + +const ( + NONE_BITS UartParityMode = 0 + ODD_BITS UartParityMode = 2 + EVEN_BITS UartParityMode = 3 +) + +type UartExistParity c.Int + +const ( + STICK_PARITY_DIS UartExistParity = 0 + STICK_PARITY_EN UartExistParity = 2 +) + +type UartBautRate c.Int + +const ( + BIT_RATE_9600 UartBautRate = 9600 + BIT_RATE_19200 UartBautRate = 19200 + BIT_RATE_38400 UartBautRate = 38400 + BIT_RATE_57600 UartBautRate = 57600 + BIT_RATE_115200 UartBautRate = 115200 + BIT_RATE_230400 UartBautRate = 230400 + BIT_RATE_460800 UartBautRate = 460800 + BIT_RATE_921600 UartBautRate = 921600 +) + +type UartFlowCtrl c.Int + +const ( + NONE_CTRL UartFlowCtrl = 0 + HARDWARE_CTRL UartFlowCtrl = 1 + XON_XOFF_CTRL UartFlowCtrl = 2 +) + +type RcvMsgBuffState c.Int + +const ( + EMPTY RcvMsgBuffState = 0 + UNDER_WRITE RcvMsgBuffState = 1 + WRITE_OVER RcvMsgBuffState = 2 +) + +type RcvMsgBuff struct { + PRcvMsgBuff *c.Uint8T + PWritePos *c.Uint8T + PReadPos *c.Uint8T + TrigLvl c.Uint8T + BuffState RcvMsgBuffState +} + +type TrxMsgBuff struct { + TrxBuffSize c.Uint32T + PTrxBuff *c.Uint8T +} +type RcvMsgState c.Int + +const ( + BAUD_RATE_DET RcvMsgState = 0 + WAIT_SYNC_FRM RcvMsgState = 1 + SRCH_MSG_HEAD RcvMsgState = 2 + RCV_MSG_BODY RcvMsgState = 3 + RCV_ESC_CHAR RcvMsgState = 4 +) + +type UartDevice struct { + BautRate UartBautRate + DataBits UartBitsNum4Char + ExistParity UartExistParity + Parity UartParityMode + StopBits UartStopBitsNum + FlowCtrl UartFlowCtrl + BuffUartNo c.Uint8T + RcvBuff RcvMsgBuff + RcvState RcvMsgState + Received c.Int +} + +/** + * @brief Init uart device struct value and reset uart0/uart1 rx. + * Please do not call this function in SDK. + * + * @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL + * + * @return None + */ +//go:linkname UartAttach C.uartAttach +func UartAttach(rxBuffer c.Pointer) + +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, else for UART1. + * + * @param uint32_t clock : clock used by uart module, to adjust baudrate. + * + * @return None + */ +//go:linkname UartInit C.Uart_Init +func UartInit(uart_no c.Uint8T, clock c.Uint32T) + +/** + * @brief Modify uart baudrate. + * This function will reset RX/TX fifo for uart. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint32_t DivLatchValue : (clock << 4)/baudrate. + * + * @return None + */ +//go:linkname UartDivModify C.uart_div_modify +func UartDivModify(uart_no c.Uint8T, DivLatchValue c.Uint32T) + +/** + * @brief Switch printf channel of uart_tx_one_char. + * Please do not call this function when printf. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +//go:linkname UartTxSwitch C.uart_tx_switch +func UartTxSwitch(uart_no c.Uint8T) + +/** + * @brief Output a char to printf channel, wait until fifo not full. + * + * @param None + * + * @return OK. + */ +//go:linkname UartTxOneChar C.uart_tx_one_char +func UartTxOneChar(TxChar c.Uint8T) ETSSTATUS + +/** + * @brief Output a char to message exchange channel, wait until fifo not full. + * Please do not call this function in SDK. + * + * @param None + * + * @return OK. + */ +//go:linkname UartTxOneChar2 C.uart_tx_one_char2 +func UartTxOneChar2(TxChar c.Uint8T) ETSSTATUS + +/** + * @brief Wait until uart tx full empty. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None. + */ +//go:linkname UartTxFlush C.uart_tx_flush +func UartTxFlush(uart_no c.Uint8T) + +/** + * @brief Wait until uart tx full empty and the last char send ok. + * + * @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2 + * + * The function defined in ROM code has a bug, so we define the correct version + * here for compatibility. + */ +//go:linkname UartTxWaitIdle C.uart_tx_wait_idle +func UartTxWaitIdle(uart_no c.Uint8T) + +/** + * @brief Get an input char from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pRxChar : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +//go:linkname UartRxOneChar C.uart_rx_one_char +func UartRxOneChar(pRxChar *c.Uint8T) ETSSTATUS + +/** + * @brief Get an input char from message channel, wait until successful. + * Please do not call this function in SDK. + * + * @param None + * + * @return char : input char value. + */ +//go:linkname UartRxOneCharBlock C.uart_rx_one_char_block +func UartRxOneCharBlock() c.Char + +/** + * @brief Get an input string line from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pString : the pointer to store the string. + * + * @param uint8_t MaxStrlen : the max string length, include '\0'. + * + * @return OK. + */ +//go:linkname UartRxString C.UartRxString +func UartRxString(pString *c.Uint8T, MaxStrlen c.Uint8T) ETSSTATUS + +/** + * @brief Get an char from receive buffer. + * Please do not call this function in SDK. + * + * @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer. + * + * @param uint8_t *pRxByte : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +// llgo:link (*RcvMsgBuff).UartRxReadbuff C.uart_rx_readbuff +func (recv_ *RcvMsgBuff) UartRxReadbuff(pRxByte *c.Uint8T) ETSSTATUS { + return 0 +} + +/** + * @brief Get uart configuration struct. + * Please do not call this function in SDK. + * + * @param None + * + * @return UartDevice * : uart configuration struct pointer. + */ +//go:linkname GetUartDevice C.GetUartDevice +func GetUartDevice() *UartDevice + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to output string. + * + * @param int len : the string length. + * + * @return None. + */ +//go:linkname SendPacket C.send_packet +func SendPacket(p *c.Uint8T, len c.Int) + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to input string. + * + * @param int len : If string length > len, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return int : the length of the string. + */ +//go:linkname RecvPacket C.recv_packet +func RecvPacket(p *c.Uint8T, len c.Int, is_sync c.Uint8T) c.Int + +/** + * @brief Initialize the USB ACM UART + * Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have. + * + * @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code + * @param cdc_acm_work_mem_len Length of work mem + */ +//go:linkname UartInitUSB C.Uart_Init_USB +func UartInitUSB(cdc_acm_work_mem c.Pointer, cdc_acm_work_mem_len c.Int) diff --git a/esp32/uart_channel.go b/esp32/uart_channel.go new file mode 100644 index 00000000..e0a4ed32 --- /dev/null +++ b/esp32/uart_channel.go @@ -0,0 +1,12 @@ +package freertos + +import _ "unsafe" + +const UART_NUM_0_TXD_DIRECT_GPIO_NUM = 43 +const UART_NUM_0_RXD_DIRECT_GPIO_NUM = 44 +const UART_NUM_0_CTS_DIRECT_GPIO_NUM = 16 +const UART_NUM_0_RTS_DIRECT_GPIO_NUM = 15 +const UART_NUM_1_TXD_DIRECT_GPIO_NUM = 17 +const UART_NUM_1_RXD_DIRECT_GPIO_NUM = 18 +const UART_NUM_1_CTS_DIRECT_GPIO_NUM = 20 +const UART_NUM_1_RTS_DIRECT_GPIO_NUM = 19 diff --git a/esp32/uart_hal.go b/esp32/uart_hal.go new file mode 100644 index 00000000..7806cfa3 --- /dev/null +++ b/esp32/uart_hal.go @@ -0,0 +1,395 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Context that should be maintained by both the driver and the HAL + */ + +type UartHalContextT struct { + Dev *UartDevT +} + +/** + * @brief Read data from the UART rxfifo + * + * @param[in] hal Context of the HAL layer + * @param[in] buf Pointer to the buffer used to store the read data. The buffer size should be large than 128 byte + * @param[inout] inout_rd_len As input, the size of output buffer to read (set to 0 to read all available data). + * As output, returns the actual size written into the output buffer. + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalReadRxfifo C.uart_hal_read_rxfifo +func (recv_ *UartHalContextT) UartHalReadRxfifo(buf *c.Uint8T, inout_rd_len *c.Int) { +} + +/** + * @brief Write data into the UART txfifo + * + * @param hal Context of the HAL layer + * @param buf Pointer of the data buffer need to be written to txfifo + * @param data_size The data size(in byte) need to be written + * @param write_size The size has been written + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalWriteTxfifo C.uart_hal_write_txfifo +func (recv_ *UartHalContextT) UartHalWriteTxfifo(buf *c.Uint8T, data_size c.Uint32T, write_size *c.Uint32T) { +} + +/** + * @brief Reset the UART txfifo + * @note On ESP32, this function is reserved for UART1 and UART2. + * + * @param hal Context of the HAL layer + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalTxfifoRst C.uart_hal_txfifo_rst +func (recv_ *UartHalContextT) UartHalTxfifoRst() { +} + +/** + * @brief Reset the UART rxfifo + * + * @param hal Context of the HAL layer + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalRxfifoRst C.uart_hal_rxfifo_rst +func (recv_ *UartHalContextT) UartHalRxfifoRst() { +} + +/** + * @brief Init the UART hal and set the UART to the default configuration. + * + * @param hal Context of the HAL layer + * @param uart_num The uart port number, the max port number is (UART_NUM_MAX -1) + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalInit C.uart_hal_init +func (recv_ *UartHalContextT) UartHalInit(uart_num UartPortT) { +} + +/** + * @brief Get the UART source clock type + * + * @param hal Context of the HAL layer + * @param sclk The pointer to accept the UART source clock type + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalGetSclk C.uart_hal_get_sclk +func (recv_ *UartHalContextT) UartHalGetSclk(sclk *SocModuleClkT) { +} + +/** + * @brief Configure the UART stop bit + * + * @param hal Context of the HAL layer + * @param stop_bit The stop bit to be set + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalSetStopBits C.uart_hal_set_stop_bits +func (recv_ *UartHalContextT) UartHalSetStopBits(stop_bit UartStopBitsT) { +} + +/** + * @brief Configure the UART data bit + * + * @param hal Context of the HAL layer + * @param data_bit The data bit to be set + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalSetDataBitNum C.uart_hal_set_data_bit_num +func (recv_ *UartHalContextT) UartHalSetDataBitNum(data_bit UartWordLengthT) { +} + +/** + * @brief Configure the UART parity mode + * + * @param hal Context of the HAL layer + * @param parity_mode The UART parity mode to be set + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalSetParity C.uart_hal_set_parity +func (recv_ *UartHalContextT) UartHalSetParity(parity_mode UartParityT) { +} + +/** + * @brief Configure the UART hardware flow control + * + * @param hal Context of the HAL layer + * @param flow_ctrl The flow control mode to be set + * @param rx_thresh The rts flow control signal will be active if the data length in rxfifo is large than this value + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalSetHwFlowCtrl C.uart_hal_set_hw_flow_ctrl +func (recv_ *UartHalContextT) UartHalSetHwFlowCtrl(flow_ctrl UartHwFlowcontrolT, rx_thresh c.Uint8T) { +} + +/** + * @brief Configure the UART AT cmd char detect function. When the receiver receives a continuous AT cmd char, it will produce a interrupt + * + * @param hal Context of the HAL layer + * @param at_cmd The AT cmd char detect configuration + * + * @return None. + */ +// llgo:link (*UartHalContextT).UartHalSetAtCmdChar C.uart_hal_set_at_cmd_char +func (recv_ *UartHalContextT) UartHalSetAtCmdChar(at_cmd *UartAtCmdT) { +} + +/** + * @brief Set the timeout value of the UART receiver + * + * @param hal Context of the HAL layer + * @param tout The timeout value for receiver to receive a data + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalSetRxTimeout C.uart_hal_set_rx_timeout +func (recv_ *UartHalContextT) UartHalSetRxTimeout(tout c.Uint8T) { +} + +/** + * @brief Set the UART dtr signal active level + * + * @param hal Context of the HAL layer + * @param active_level The dtr active level. The active level is low if set to 0. The active level is high if set to 1 + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalSetDtr C.uart_hal_set_dtr +func (recv_ *UartHalContextT) UartHalSetDtr(active_level c.Int) { +} + +/** + * @brief Set the UART software flow control + * + * @param hal Context of the HAL layer + * @param flow_ctrl The software flow control configuration + * @param sw_flow_ctrl_en Set true to enable the software flow control, otherwise set it false + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalSetSwFlowCtrl C.uart_hal_set_sw_flow_ctrl +func (recv_ *UartHalContextT) UartHalSetSwFlowCtrl(flow_ctrl *UartSwFlowctrlT, sw_flow_ctrl_en bool) { +} + +/** + * @brief Set the UART tx idle number + * + * @param hal Context of the HAL layer + * @param idle_num The cycle number betwin the two transmission + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalSetTxIdleNum C.uart_hal_set_tx_idle_num +func (recv_ *UartHalContextT) UartHalSetTxIdleNum(idle_num c.Uint16T) { +} + +/** + * @brief Set the UART rxfifo full threshold + * + * @param hal Context of the HAL layer + * @param full_thrhd The rxfifo full threshold. If the `UART_RXFIFO_FULL` interrupt is enabled and + * the data length in rxfifo is more than this value, it will generate `UART_RXFIFO_FULL` interrupt + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalSetRxfifoFullThr C.uart_hal_set_rxfifo_full_thr +func (recv_ *UartHalContextT) UartHalSetRxfifoFullThr(full_thrhd c.Uint32T) { +} + +/** + * @brief Set the UART txfifo empty threshold + * + * @param hal Context of the HAL layer + * @param empty_thrhd The txfifo empty threshold to be set. If the `UART_TXFIFO_EMPTY` interrupt is enabled and + * the data length in txfifo is less than this value, it will generate `UART_TXFIFO_EMPTY` interrupt + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalSetTxfifoEmptyThr C.uart_hal_set_txfifo_empty_thr +func (recv_ *UartHalContextT) UartHalSetTxfifoEmptyThr(empty_thrhd c.Uint32T) { +} + +/** + * @brief Configure the UART to send a number of break(NULL) chars + * + * @param hal Context of the HAL layer + * @param break_num The number of the break char need to be send + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalTxBreak C.uart_hal_tx_break +func (recv_ *UartHalContextT) UartHalTxBreak(break_num c.Uint32T) { +} + +/** + * @brief Configure the UART wake up function. + * Note that RXD cannot be input through GPIO Matrix but only through IO_MUX when use this function + * + * @param hal Context of the HAL layer + * @param wakeup_thrd The wake up threshold to be set. The system will be woken up from light-sleep when the input RXD edge changes more times than `wakeup_thrd+2` + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalSetWakeupThrd C.uart_hal_set_wakeup_thrd +func (recv_ *UartHalContextT) UartHalSetWakeupThrd(wakeup_thrd c.Uint32T) { +} + +/** + * @brief Configure the UART mode + * + * @param hal Context of the HAL layer + * @param mode The UART mode to be set + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalSetMode C.uart_hal_set_mode +func (recv_ *UartHalContextT) UartHalSetMode(mode UartModeT) { +} + +/** + * @brief Configure the UART hardware to inverse the signals + * + * @param hal Context of the HAL layer + * @param inv_mask The signal mask needs to be inversed. Use the ORred mask of type `uart_signal_inv_t` + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalInverseSignal C.uart_hal_inverse_signal +func (recv_ *UartHalContextT) UartHalInverseSignal(inv_mask c.Uint32T) { +} + +/** + * @brief Get the UART wakeup threshold configuration + * + * @param hal Context of the HAL layer + * @param wakeup_thrd Pointer to accept the value of UART wakeup threshold configuration + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalGetWakeupThrd C.uart_hal_get_wakeup_thrd +func (recv_ *UartHalContextT) UartHalGetWakeupThrd(wakeup_thrd *c.Uint32T) { +} + +/** + * @brief Get the UART data bit configuration + * + * @param hal Context of the HAL layer + * @param data_bit Pointer to accept the value of UART data bit configuration + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalGetDataBitNum C.uart_hal_get_data_bit_num +func (recv_ *UartHalContextT) UartHalGetDataBitNum(data_bit *UartWordLengthT) { +} + +/** + * @brief Get the UART stop bit configuration + * + * @param hal Context of the HAL layer + * @param stop_bit Pointer to accept the value of UART stop bit configuration + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalGetStopBits C.uart_hal_get_stop_bits +func (recv_ *UartHalContextT) UartHalGetStopBits(stop_bit *UartStopBitsT) { +} + +/** + * @brief Get the UART parity mode configuration + * + * @param hal Context of the HAL layer + * @param parity_mode Pointer to accept the UART parity mode configuration + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalGetParity C.uart_hal_get_parity +func (recv_ *UartHalContextT) UartHalGetParity(parity_mode *UartParityT) { +} + +/** + * @brief Get the UART baud-rate configuration + * + * @param hal Context of the HAL layer + * @param baud_rate Pointer to accept the current baud-rate + * @param sclk_freq Frequency of the clock source of UART, in Hz. + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalGetBaudrate C.uart_hal_get_baudrate +func (recv_ *UartHalContextT) UartHalGetBaudrate(baud_rate *c.Uint32T, sclk_freq c.Uint32T) { +} + +/** + * @brief Get the hw flow control configuration + * + * @param hal Context of the HAL layer + * @param flow_ctrl Pointer to accept the UART flow control configuration + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalGetHwFlowCtrl C.uart_hal_get_hw_flow_ctrl +func (recv_ *UartHalContextT) UartHalGetHwFlowCtrl(flow_ctrl *UartHwFlowcontrolT) { +} + +/** + * @brief Check if the UART rts flow control is enabled + * + * @param hal Context of the HAL layer + * + * @return True if rts flow control is enabled, otherwise false will be returned + */ +// llgo:link (*UartHalContextT).UartHalIsHwRtsEn C.uart_hal_is_hw_rts_en +func (recv_ *UartHalContextT) UartHalIsHwRtsEn() bool { + return false +} + +/** + * @brief Configure TX signal loop back to RX module, just for the testing purposes + * + * @param hal Context of the HAL layer + * @param loop_back_en Set true to enable the loop back function, else set it false. + * + * @return None + */ +// llgo:link (*UartHalContextT).UartHalSetLoopBack C.uart_hal_set_loop_back +func (recv_ *UartHalContextT) UartHalSetLoopBack(loop_back_en bool) { +} + +/** + * @brief Calculate uart symbol bit length, as defined in configuration. + * + * @param hw Beginning address of the peripheral registers. + * + * @return number of bits per UART symbol. + */ +// llgo:link (*UartHalContextT).UartHalGetSymbLen C.uart_hal_get_symb_len +func (recv_ *UartHalContextT) UartHalGetSymbLen() c.Uint8T { + return 0 +} + +/** + * @brief Get UART maximum timeout threshold. + * + * @param hw Beginning address of the peripheral registers. + * + * @return maximum timeout threshold value for target. + */ +// llgo:link (*UartHalContextT).UartHalGetMaxRxTimeoutThrd C.uart_hal_get_max_rx_timeout_thrd +func (recv_ *UartHalContextT) UartHalGetMaxRxTimeoutThrd() c.Uint16T { + return 0 +} diff --git a/esp32/uart_ll.go b/esp32/uart_ll.go new file mode 100644 index 00000000..9051a067 --- /dev/null +++ b/esp32/uart_ll.go @@ -0,0 +1,31 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type UartIntrT c.Int + +const ( + UART_INTR_RXFIFO_FULL UartIntrT = 1 + UART_INTR_TXFIFO_EMPTY UartIntrT = 2 + UART_INTR_PARITY_ERR UartIntrT = 4 + UART_INTR_FRAM_ERR UartIntrT = 8 + UART_INTR_RXFIFO_OVF UartIntrT = 16 + UART_INTR_DSR_CHG UartIntrT = 32 + UART_INTR_CTS_CHG UartIntrT = 64 + UART_INTR_BRK_DET UartIntrT = 128 + UART_INTR_RXFIFO_TOUT UartIntrT = 256 + UART_INTR_SW_XON UartIntrT = 512 + UART_INTR_SW_XOFF UartIntrT = 1024 + UART_INTR_GLITCH_DET UartIntrT = 2048 + UART_INTR_TX_BRK_DONE UartIntrT = 4096 + UART_INTR_TX_BRK_IDLE UartIntrT = 8192 + UART_INTR_TX_DONE UartIntrT = 16384 + UART_INTR_RS485_PARITY_ERR UartIntrT = 32768 + UART_INTR_RS485_FRM_ERR UartIntrT = 65536 + UART_INTR_RS485_CLASH UartIntrT = 131072 + UART_INTR_CMD_CHAR_DET UartIntrT = 262144 + UART_INTR_WAKEUP UartIntrT = 524288 +) diff --git a/esp32/uart_periph.go b/esp32/uart_periph.go new file mode 100644 index 00000000..8191c57e --- /dev/null +++ b/esp32/uart_periph.go @@ -0,0 +1,18 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type UartPeriphSigT struct { + DefaultGpio c.Int32T + IomuxFunc c.Int32T + Input c.Uint32T + Signal c.Uint32T +} + +type UartSignalConnT struct { + Pins [4]UartPeriphSigT + Irq c.Uint8T +} diff --git a/esp32/uart_pins.go b/esp32/uart_pins.go new file mode 100644 index 00000000..c7051f61 --- /dev/null +++ b/esp32/uart_pins.go @@ -0,0 +1,12 @@ +package freertos + +import _ "unsafe" + +const U0RXD_GPIO_NUM = 44 +const U0TXD_GPIO_NUM = 43 +const U0CTS_GPIO_NUM = 16 +const U0RTS_GPIO_NUM = 15 +const U1RXD_GPIO_NUM = 18 +const U1TXD_GPIO_NUM = 17 +const U1CTS_GPIO_NUM = 20 +const U1RTS_GPIO_NUM = 19 diff --git a/esp32/uart_reg.go b/esp32/uart_reg.go new file mode 100644 index 00000000..2a485655 --- /dev/null +++ b/esp32/uart_reg.go @@ -0,0 +1,187 @@ +package freertos + +import _ "unsafe" + +const UART_RXFIFO_RD_BYTE_S = 0 +const UART_RXFIFO_FULL_INT_RAW_S = 0 +const UART_TXFIFO_EMPTY_INT_RAW_S = 1 +const UART_PARITY_ERR_INT_RAW_S = 2 +const UART_FRM_ERR_INT_RAW_S = 3 +const UART_RXFIFO_OVF_INT_RAW_S = 4 +const UART_DSR_CHG_INT_RAW_S = 5 +const UART_CTS_CHG_INT_RAW_S = 6 +const UART_BRK_DET_INT_RAW_S = 7 +const UART_RXFIFO_TOUT_INT_RAW_S = 8 +const UART_SW_XON_INT_RAW_S = 9 +const UART_SW_XOFF_INT_RAW_S = 10 +const UART_GLITCH_DET_INT_RAW_S = 11 +const UART_TX_BRK_DONE_INT_RAW_S = 12 +const UART_TX_BRK_IDLE_DONE_INT_RAW_S = 13 +const UART_TX_DONE_INT_RAW_S = 14 +const UART_RS485_PARITY_ERR_INT_RAW_S = 15 +const UART_RS485_FRM_ERR_INT_RAW_S = 16 +const UART_RS485_CLASH_INT_RAW_S = 17 +const UART_AT_CMD_CHAR_DET_INT_RAW_S = 18 +const UART_WAKEUP_INT_RAW_S = 19 +const UART_RXFIFO_FULL_INT_ST_S = 0 +const UART_TXFIFO_EMPTY_INT_ST_S = 1 +const UART_PARITY_ERR_INT_ST_S = 2 +const UART_FRM_ERR_INT_ST_S = 3 +const UART_RXFIFO_OVF_INT_ST_S = 4 +const UART_DSR_CHG_INT_ST_S = 5 +const UART_CTS_CHG_INT_ST_S = 6 +const UART_BRK_DET_INT_ST_S = 7 +const UART_RXFIFO_TOUT_INT_ST_S = 8 +const UART_SW_XON_INT_ST_S = 9 +const UART_SW_XOFF_INT_ST_S = 10 +const UART_GLITCH_DET_INT_ST_S = 11 +const UART_TX_BRK_DONE_INT_ST_S = 12 +const UART_TX_BRK_IDLE_DONE_INT_ST_S = 13 +const UART_TX_DONE_INT_ST_S = 14 +const UART_RS485_PARITY_ERR_INT_ST_S = 15 +const UART_RS485_FRM_ERR_INT_ST_S = 16 +const UART_RS485_CLASH_INT_ST_S = 17 +const UART_AT_CMD_CHAR_DET_INT_ST_S = 18 +const UART_WAKEUP_INT_ST_S = 19 +const UART_RXFIFO_FULL_INT_ENA_S = 0 +const UART_TXFIFO_EMPTY_INT_ENA_S = 1 +const UART_PARITY_ERR_INT_ENA_S = 2 +const UART_FRM_ERR_INT_ENA_S = 3 +const UART_RXFIFO_OVF_INT_ENA_S = 4 +const UART_DSR_CHG_INT_ENA_S = 5 +const UART_CTS_CHG_INT_ENA_S = 6 +const UART_BRK_DET_INT_ENA_S = 7 +const UART_RXFIFO_TOUT_INT_ENA_S = 8 +const UART_SW_XON_INT_ENA_S = 9 +const UART_SW_XOFF_INT_ENA_S = 10 +const UART_GLITCH_DET_INT_ENA_S = 11 +const UART_TX_BRK_DONE_INT_ENA_S = 12 +const UART_TX_BRK_IDLE_DONE_INT_ENA_S = 13 +const UART_TX_DONE_INT_ENA_S = 14 +const UART_RS485_PARITY_ERR_INT_ENA_S = 15 +const UART_RS485_FRM_ERR_INT_ENA_S = 16 +const UART_RS485_CLASH_INT_ENA_S = 17 +const UART_AT_CMD_CHAR_DET_INT_ENA_S = 18 +const UART_WAKEUP_INT_ENA_S = 19 +const UART_RXFIFO_FULL_INT_CLR_S = 0 +const UART_TXFIFO_EMPTY_INT_CLR_S = 1 +const UART_PARITY_ERR_INT_CLR_S = 2 +const UART_FRM_ERR_INT_CLR_S = 3 +const UART_RXFIFO_OVF_INT_CLR_S = 4 +const UART_DSR_CHG_INT_CLR_S = 5 +const UART_CTS_CHG_INT_CLR_S = 6 +const UART_BRK_DET_INT_CLR_S = 7 +const UART_RXFIFO_TOUT_INT_CLR_S = 8 +const UART_SW_XON_INT_CLR_S = 9 +const UART_SW_XOFF_INT_CLR_S = 10 +const UART_GLITCH_DET_INT_CLR_S = 11 +const UART_TX_BRK_DONE_INT_CLR_S = 12 +const UART_TX_BRK_IDLE_DONE_INT_CLR_S = 13 +const UART_TX_DONE_INT_CLR_S = 14 +const UART_RS485_PARITY_ERR_INT_CLR_S = 15 +const UART_RS485_FRM_ERR_INT_CLR_S = 16 +const UART_RS485_CLASH_INT_CLR_S = 17 +const UART_AT_CMD_CHAR_DET_INT_CLR_S = 18 +const UART_WAKEUP_INT_CLR_S = 19 +const UART_CLKDIV_S = 0 +const UART_CLKDIV_FRAG_S = 20 +const UART_GLITCH_FILT_S = 0 +const UART_GLITCH_FILT_EN_S = 8 +const UART_RXFIFO_CNT_S = 0 +const UART_DSRN_S = 13 +const UART_CTSN_S = 14 +const UART_RXD_S = 15 +const UART_TXFIFO_CNT_S = 16 +const UART_DTRN_S = 29 +const UART_RTSN_S = 30 +const UART_TXD_S = 31 +const UART_PARITY_S = 0 +const UART_PARITY_EN_S = 1 +const UART_BIT_NUM_S = 2 +const UART_STOP_BIT_NUM_S = 4 +const UART_SW_RTS_S = 6 +const UART_SW_DTR_S = 7 +const UART_TXD_BRK_S = 8 +const UART_IRDA_DPLX_S = 9 +const UART_IRDA_TX_EN_S = 10 +const UART_IRDA_WCTL_S = 11 +const UART_IRDA_TX_INV_S = 12 +const UART_IRDA_RX_INV_S = 13 +const UART_LOOPBACK_S = 14 +const UART_TX_FLOW_EN_S = 15 +const UART_IRDA_EN_S = 16 +const UART_RXFIFO_RST_S = 17 +const UART_TXFIFO_RST_S = 18 +const UART_RXD_INV_S = 19 +const UART_CTS_INV_S = 20 +const UART_DSR_INV_S = 21 +const UART_TXD_INV_S = 22 +const UART_RTS_INV_S = 23 +const UART_DTR_INV_S = 24 +const UART_CLK_EN_S = 25 +const UART_ERR_WR_MASK_S = 26 +const UART_AUTOBAUD_EN_S = 27 +const UART_MEM_CLK_EN_S = 28 +const UART_RXFIFO_FULL_THRHD_S = 0 +const UART_TXFIFO_EMPTY_THRHD_S = 10 +const UART_DIS_RX_DAT_OVF_S = 20 +const UART_RX_TOUT_FLOW_DIS_S = 21 +const UART_RX_FLOW_EN_S = 22 +const UART_RX_TOUT_EN_S = 23 +const UART_LOWPULSE_MIN_CNT_S = 0 +const UART_HIGHPULSE_MIN_CNT_S = 0 +const UART_RXD_EDGE_CNT_S = 0 +const UART_SW_FLOW_CON_EN_S = 0 +const UART_XONOFF_DEL_S = 1 +const UART_FORCE_XON_S = 2 +const UART_FORCE_XOFF_S = 3 +const UART_SEND_XON_S = 4 +const UART_SEND_XOFF_S = 5 +const UART_ACTIVE_THRESHOLD_S = 0 +const UART_XOFF_THRESHOLD_S = 0 +const UART_XOFF_CHAR_S = 10 +const UART_XON_THRESHOLD_S = 0 +const UART_XON_CHAR_S = 10 +const UART_TX_BRK_NUM_S = 0 +const UART_RX_IDLE_THRHD_S = 0 +const UART_TX_IDLE_NUM_S = 10 +const UART_RS485_EN_S = 0 +const UART_DL0_EN_S = 1 +const UART_DL1_EN_S = 2 +const UART_RS485TX_RX_EN_S = 3 +const UART_RS485RXBY_TX_EN_S = 4 +const UART_RS485_RX_DLY_NUM_S = 5 +const UART_RS485_TX_DLY_NUM_S = 6 +const UART_PRE_IDLE_NUM_S = 0 +const UART_POST_IDLE_NUM_S = 0 +const UART_RX_GAP_TOUT_S = 0 +const UART_AT_CMD_CHAR_S = 0 +const UART_CHAR_NUM_S = 8 +const UART_RX_SIZE_S = 1 +const UART_TX_SIZE_S = 4 +const UART_RX_FLOW_THRHD_S = 7 +const UART_RX_TOUT_THRHD_S = 17 +const UART_MEM_FORCE_PD_S = 27 +const UART_MEM_FORCE_PU_S = 28 +const UART_APB_TX_WADDR_S = 0 +const UART_TX_RADDR_S = 11 +const UART_APB_RX_RADDR_S = 0 +const UART_RX_WADDR_S = 11 +const UART_ST_URX_OUT_S = 0 +const UART_ST_UTX_OUT_S = 4 +const UART_POSEDGE_MIN_CNT_S = 0 +const UART_NEGEDGE_MIN_CNT_S = 0 +const UART_SCLK_DIV_B_S = 0 +const UART_SCLK_DIV_A_S = 6 +const UART_SCLK_DIV_NUM_S = 12 +const UART_SCLK_SEL_S = 20 +const UART_SCLK_EN_S = 22 +const UART_RST_CORE_S = 23 +const UART_TX_SCLK_EN_S = 24 +const UART_RX_SCLK_EN_S = 25 +const UART_TX_RST_CORE_S = 26 +const UART_RX_RST_CORE_S = 27 +const UART_DATE_S = 0 +const UART_ID_S = 0 +const UART_HIGH_SPEED_S = 30 +const UART_REG_UPDATE_S = 31 diff --git a/esp32/uart_share_hw_ctrl.go b/esp32/uart_share_hw_ctrl.go new file mode 100644 index 00000000..f68c4eee --- /dev/null +++ b/esp32/uart_share_hw_ctrl.go @@ -0,0 +1,3 @@ +package freertos + +import _ "unsafe" diff --git a/esp32/uart_struct.go b/esp32/uart_struct.go new file mode 100644 index 00000000..882298a3 --- /dev/null +++ b/esp32/uart_struct.go @@ -0,0 +1,313 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** Group: FIFO Configuration */ +/** Type of fifo register + * FIFO data register + */ + +type UartFifoRegT struct { + Val c.Uint32T +} + +/** Type of mem_conf register + * UART threshold and allocation configuration + */ + +type UartMemConfRegT struct { + Val c.Uint32T +} + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ + +type UartIntRawRegT struct { + Val c.Uint32T +} + +/** Type of int_st register + * Masked interrupt status + */ + +type UartIntStRegT struct { + Val c.Uint32T +} + +/** Type of int_ena register + * Interrupt enable bits + */ + +type UartIntEnaRegT struct { + Val c.Uint32T +} + +/** Type of int_clr register + * Interrupt clear bits + */ + +type UartIntClrRegT struct { + Val c.Uint32T +} + +/** Group: Configuration Register */ +/** Type of clkdiv register + * Clock divider configuration + */ + +type UartClkdivRegT struct { + Val c.Uint32T +} + +/** Type of rx_filt register + * Rx Filter configuration + */ + +type UartRxFiltRegT struct { + Val c.Uint32T +} + +/** Type of conf0 register + * a + */ + +type UartConf0RegT struct { + Val c.Uint32T +} + +/** Type of conf1 register + * Configuration register 1 + */ + +type UartConf1RegT struct { + Val c.Uint32T +} + +/** Type of flow_conf register + * Software flow-control configuration + */ + +type UartFlowConfRegT struct { + Val c.Uint32T +} + +/** Type of sleep_conf register + * Sleep-mode configuration + */ + +type UartSleepConfRegT struct { + Val c.Uint32T +} + +/** Type of swfc_conf0 register + * Software flow-control character configuration + */ + +type UartSwfcConf0RegT struct { + Val c.Uint32T +} + +/** Type of swfc_conf1 register + * Software flow-control character configuration + */ + +type UartSwfcConf1RegT struct { + Val c.Uint32T +} + +/** Type of txbrk_conf register + * Tx Break character configuration + */ + +type UartTxbrkConfRegT struct { + Val c.Uint32T +} + +/** Type of idle_conf register + * Frame-end idle configuration + */ + +type UartIdleConfRegT struct { + Val c.Uint32T +} + +/** Type of rs485_conf register + * RS485 mode configuration + */ + +type UartRs485ConfRegT struct { + Val c.Uint32T +} + +/** Type of clk_conf register + * UART core clock configuration + */ + +type UartClkConfRegT struct { + Val c.Uint32T +} + +/** Group: Status Register */ +/** Type of status register + * UART status register + */ + +type UartStatusRegT struct { + Val c.Uint32T +} + +/** Type of mem_tx_status register + * Tx-FIFO write and read offset address. + */ + +type UartMemTxStatusRegT struct { + Val c.Uint32T +} + +/** Type of mem_rx_status register + * Rx-FIFO write and read offset address. + */ + +type UartMemRxStatusRegT struct { + Val c.Uint32T +} + +/** Type of fsm_status register + * UART transmit and receive status. + */ + +type UartFsmStatusRegT struct { + Val c.Uint32T +} + +/** Group: Autobaud Register */ +/** Type of lowpulse register + * Autobaud minimum low pulse duration register + */ + +type UartLowpulseRegT struct { + Val c.Uint32T +} + +/** Type of highpulse register + * Autobaud minimum high pulse duration register + */ + +type UartHighpulseRegT struct { + Val c.Uint32T +} + +/** Type of rxd_cnt register + * Autobaud edge change count register + */ + +type UartRxdCntRegT struct { + Val c.Uint32T +} + +/** Type of pospulse register + * Autobaud high pulse register + */ + +type UartPospulseRegT struct { + Val c.Uint32T +} + +/** Type of negpulse register + * Autobaud low pulse register + */ + +type UartNegpulseRegT struct { + Val c.Uint32T +} + +/** Group: AT Escape Sequence Selection Configuration */ +/** Type of at_cmd_precnt register + * Pre-sequence timing configuration + */ + +type UartAtCmdPrecntRegT struct { + Val c.Uint32T +} + +/** Type of at_cmd_postcnt register + * Post-sequence timing configuration + */ + +type UartAtCmdPostcntRegT struct { + Val c.Uint32T +} + +/** Type of at_cmd_gaptout register + * Timeout configuration + */ + +type UartAtCmdGaptoutRegT struct { + Val c.Uint32T +} + +/** Type of at_cmd_char register + * AT escape sequence detection configuration + */ + +type UartAtCmdCharRegT struct { + Val c.Uint32T +} + +/** Group: Version Register */ +/** Type of date register + * UART Version register + */ + +type UartDateRegT struct { + Val c.Uint32T +} + +/** Type of id register + * UART ID register + */ + +type UartIdRegT struct { + Val c.Uint32T +} + +type UartDevT struct { + Fifo UartFifoRegT + IntRaw UartIntRawRegT + IntSt UartIntStRegT + IntEna UartIntEnaRegT + IntClr UartIntClrRegT + Clkdiv UartClkdivRegT + RxFilt UartRxFiltRegT + Status UartStatusRegT + Conf0 UartConf0RegT + Conf1 UartConf1RegT + Lowpulse UartLowpulseRegT + Highpulse UartHighpulseRegT + RxdCnt UartRxdCntRegT + FlowConf UartFlowConfRegT + SleepConf UartSleepConfRegT + SwfcConf0 UartSwfcConf0RegT + SwfcConf1 UartSwfcConf1RegT + TxbrkConf UartTxbrkConfRegT + IdleConf UartIdleConfRegT + Rs485Conf UartRs485ConfRegT + AtCmdPrecnt UartAtCmdPrecntRegT + AtCmdPostcnt UartAtCmdPostcntRegT + AtCmdGaptout UartAtCmdGaptoutRegT + AtCmdChar UartAtCmdCharRegT + MemConf UartMemConfRegT + MemTxStatus UartMemTxStatusRegT + MemRxStatus UartMemRxStatusRegT + FsmStatus UartFsmStatusRegT + Pospulse UartPospulseRegT + Negpulse UartNegpulseRegT + ClkConf UartClkConfRegT + Date UartDateRegT + Id UartIdRegT +} diff --git a/esp32/uart_types.go b/esp32/uart_types.go new file mode 100644 index 00000000..48848c63 --- /dev/null +++ b/esp32/uart_types.go @@ -0,0 +1,102 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type UartPortT c.Int + +const ( + UART_NUM_0 UartPortT = 0 + UART_NUM_1 UartPortT = 1 + UART_NUM_2 UartPortT = 2 + UART_NUM_MAX UartPortT = 3 +) + +type UartModeT c.Int + +const ( + UART_MODE_UART UartModeT = 0 + UART_MODE_RS485_HALF_DUPLEX UartModeT = 1 + UART_MODE_IRDA UartModeT = 2 + UART_MODE_RS485_COLLISION_DETECT UartModeT = 3 + UART_MODE_RS485_APP_CTRL UartModeT = 4 +) + +type UartWordLengthT c.Int + +const ( + UART_DATA_5_BITS UartWordLengthT = 0 + UART_DATA_6_BITS UartWordLengthT = 1 + UART_DATA_7_BITS UartWordLengthT = 2 + UART_DATA_8_BITS UartWordLengthT = 3 + UART_DATA_BITS_MAX UartWordLengthT = 4 +) + +type UartStopBitsT c.Int + +const ( + UART_STOP_BITS_1 UartStopBitsT = 1 + UART_STOP_BITS_1_5 UartStopBitsT = 2 + UART_STOP_BITS_2 UartStopBitsT = 3 + UART_STOP_BITS_MAX UartStopBitsT = 4 +) + +type UartParityT c.Int + +const ( + UART_PARITY_DISABLE UartParityT = 0 + UART_PARITY_EVEN UartParityT = 2 + UART_PARITY_ODD UartParityT = 3 +) + +type UartHwFlowcontrolT c.Int + +const ( + UART_HW_FLOWCTRL_DISABLE UartHwFlowcontrolT = 0 + UART_HW_FLOWCTRL_RTS UartHwFlowcontrolT = 1 + UART_HW_FLOWCTRL_CTS UartHwFlowcontrolT = 2 + UART_HW_FLOWCTRL_CTS_RTS UartHwFlowcontrolT = 3 + UART_HW_FLOWCTRL_MAX UartHwFlowcontrolT = 4 +) + +type UartSignalInvT c.Int + +const ( + UART_SIGNAL_INV_DISABLE UartSignalInvT = 0 + UART_SIGNAL_IRDA_TX_INV UartSignalInvT = 1 + UART_SIGNAL_IRDA_RX_INV UartSignalInvT = 2 + UART_SIGNAL_RXD_INV UartSignalInvT = 4 + UART_SIGNAL_CTS_INV UartSignalInvT = 8 + UART_SIGNAL_DSR_INV UartSignalInvT = 16 + UART_SIGNAL_TXD_INV UartSignalInvT = 32 + UART_SIGNAL_RTS_INV UartSignalInvT = 64 + UART_SIGNAL_DTR_INV UartSignalInvT = 128 +) + +type UartSclkT SocPeriphUartClkSrcLegacyT + +/** + * @brief UART AT cmd char configuration parameters + * Note that this function may different on different chip. Please refer to the TRM at confirguration. + */ + +type UartAtCmdT struct { + CmdChar c.Uint8T + CharNum c.Uint8T + GapTout c.Uint32T + PreIdle c.Uint32T + PostIdle c.Uint32T +} + +/** + * @brief UART software flow control configuration parameters + */ + +type UartSwFlowctrlT struct { + XonChar c.Uint8T + XoffChar c.Uint8T + XonThrd c.Uint8T + XoffThrd c.Uint8T +} diff --git a/esp32/uhci_ll.go b/esp32/uhci_ll.go new file mode 100644 index 00000000..d8118da0 --- /dev/null +++ b/esp32/uhci_ll.go @@ -0,0 +1,15 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type UhciRxeofCfgT c.Int + +const ( + UHCI_RX_BREAK_CHR_EOF UhciRxeofCfgT = 1 + UHCI_RX_IDLE_EOF UhciRxeofCfgT = 2 + UHCI_RX_LEN_EOF UhciRxeofCfgT = 4 + UHCI_RX_EOF_MAX UhciRxeofCfgT = 7 +) diff --git a/esp32/uhci_reg.go b/esp32/uhci_reg.go new file mode 100644 index 00000000..587f8cb0 --- /dev/null +++ b/esp32/uhci_reg.go @@ -0,0 +1,265 @@ +package freertos + +import _ "unsafe" + +const UHCI_UART_RX_BRK_EOF_EN_V = 0x1 +const UHCI_UART_RX_BRK_EOF_EN_S = 12 +const UHCI_CLK_EN_V = 0x1 +const UHCI_CLK_EN_S = 11 +const UHCI_ENCODE_CRC_EN_V = 0x1 +const UHCI_ENCODE_CRC_EN_S = 10 +const UHCI_LEN_EOF_EN_V = 0x1 +const UHCI_LEN_EOF_EN_S = 9 +const UHCI_UART_IDLE_EOF_EN_V = 0x1 +const UHCI_UART_IDLE_EOF_EN_S = 8 +const UHCI_CRC_REC_EN_V = 0x1 +const UHCI_CRC_REC_EN_S = 7 +const UHCI_HEAD_EN_V = 0x1 +const UHCI_HEAD_EN_S = 6 +const UHCI_SEPER_EN_V = 0x1 +const UHCI_SEPER_EN_S = 5 +const UHCI_UART2_CE_V = 0x1 +const UHCI_UART2_CE_S = 4 +const UHCI_UART1_CE_V = 0x1 +const UHCI_UART1_CE_S = 3 +const UHCI_UART0_CE_V = 0x1 +const UHCI_UART0_CE_S = 2 +const UHCI_RX_RST_V = 0x1 +const UHCI_RX_RST_S = 1 +const UHCI_TX_RST_V = 0x1 +const UHCI_TX_RST_S = 0 +const UHCI_APP_CTRL1_INT_RAW_V = 0x1 +const UHCI_APP_CTRL1_INT_RAW_S = 8 +const UHCI_APP_CTRL0_INT_RAW_V = 0x1 +const UHCI_APP_CTRL0_INT_RAW_S = 7 +const UHCI_OUTLINK_EOF_ERR_INT_RAW_V = 0x1 +const UHCI_OUTLINK_EOF_ERR_INT_RAW_S = 6 +const UHCI_SEND_A_Q_INT_RAW_V = 0x1 +const UHCI_SEND_A_Q_INT_RAW_S = 5 +const UHCI_SEND_S_Q_INT_RAW_V = 0x1 +const UHCI_SEND_S_Q_INT_RAW_S = 4 +const UHCI_TX_HUNG_INT_RAW_V = 0x1 +const UHCI_TX_HUNG_INT_RAW_S = 3 +const UHCI_RX_HUNG_INT_RAW_V = 0x1 +const UHCI_RX_HUNG_INT_RAW_S = 2 +const UHCI_TX_START_INT_RAW_V = 0x1 +const UHCI_TX_START_INT_RAW_S = 1 +const UHCI_RX_START_INT_RAW_V = 0x1 +const UHCI_RX_START_INT_RAW_S = 0 +const UHCI_APP_CTRL1_INT_ST_V = 0x1 +const UHCI_APP_CTRL1_INT_ST_S = 8 +const UHCI_APP_CTRL0_INT_ST_V = 0x1 +const UHCI_APP_CTRL0_INT_ST_S = 7 +const UHCI_OUTLINK_EOF_ERR_INT_ST_V = 0x1 +const UHCI_OUTLINK_EOF_ERR_INT_ST_S = 6 +const UHCI_SEND_A_Q_INT_ST_V = 0x1 +const UHCI_SEND_A_Q_INT_ST_S = 5 +const UHCI_SEND_S_Q_INT_ST_V = 0x1 +const UHCI_SEND_S_Q_INT_ST_S = 4 +const UHCI_TX_HUNG_INT_ST_V = 0x1 +const UHCI_TX_HUNG_INT_ST_S = 3 +const UHCI_RX_HUNG_INT_ST_V = 0x1 +const UHCI_RX_HUNG_INT_ST_S = 2 +const UHCI_TX_START_INT_ST_V = 0x1 +const UHCI_TX_START_INT_ST_S = 1 +const UHCI_RX_START_INT_ST_V = 0x1 +const UHCI_RX_START_INT_ST_S = 0 +const UHCI_APP_CTRL1_INT_ENA_V = 0x1 +const UHCI_APP_CTRL1_INT_ENA_S = 8 +const UHCI_APP_CTRL0_INT_ENA_V = 0x1 +const UHCI_APP_CTRL0_INT_ENA_S = 7 +const UHCI_OUTLINK_EOF_ERR_INT_ENA_V = 0x1 +const UHCI_OUTLINK_EOF_ERR_INT_ENA_S = 6 +const UHCI_SEND_A_Q_INT_ENA_V = 0x1 +const UHCI_SEND_A_Q_INT_ENA_S = 5 +const UHCI_SEND_S_Q_INT_ENA_V = 0x1 +const UHCI_SEND_S_Q_INT_ENA_S = 4 +const UHCI_TX_HUNG_INT_ENA_V = 0x1 +const UHCI_TX_HUNG_INT_ENA_S = 3 +const UHCI_RX_HUNG_INT_ENA_V = 0x1 +const UHCI_RX_HUNG_INT_ENA_S = 2 +const UHCI_TX_START_INT_ENA_V = 0x1 +const UHCI_TX_START_INT_ENA_S = 1 +const UHCI_RX_START_INT_ENA_V = 0x1 +const UHCI_RX_START_INT_ENA_S = 0 +const UHCI_APP_CTRL1_INT_CLR_V = 0x1 +const UHCI_APP_CTRL1_INT_CLR_S = 8 +const UHCI_APP_CTRL0_INT_CLR_V = 0x1 +const UHCI_APP_CTRL0_INT_CLR_S = 7 +const UHCI_OUTLINK_EOF_ERR_INT_CLR_V = 0x1 +const UHCI_OUTLINK_EOF_ERR_INT_CLR_S = 6 +const UHCI_SEND_A_Q_INT_CLR_V = 0x1 +const UHCI_SEND_A_Q_INT_CLR_S = 5 +const UHCI_SEND_S_Q_INT_CLR_V = 0x1 +const UHCI_SEND_S_Q_INT_CLR_S = 4 +const UHCI_TX_HUNG_INT_CLR_V = 0x1 +const UHCI_TX_HUNG_INT_CLR_S = 3 +const UHCI_RX_HUNG_INT_CLR_V = 0x1 +const UHCI_RX_HUNG_INT_CLR_S = 2 +const UHCI_TX_START_INT_CLR_V = 0x1 +const UHCI_TX_START_INT_CLR_S = 1 +const UHCI_RX_START_INT_CLR_V = 0x1 +const UHCI_RX_START_INT_CLR_S = 0 +const UHCI_APP_CTRL1_INT_SET_V = 0x1 +const UHCI_APP_CTRL1_INT_SET_S = 1 +const UHCI_APP_CTRL0_INT_SET_V = 0x1 +const UHCI_APP_CTRL0_INT_SET_S = 0 +const UHCI_SW_START_V = 0x1 +const UHCI_SW_START_S = 8 +const UHCI_WAIT_SW_START_V = 0x1 +const UHCI_WAIT_SW_START_S = 7 +const UHCI_TX_ACK_NUM_RE_V = 0x1 +const UHCI_TX_ACK_NUM_RE_S = 5 +const UHCI_TX_CHECK_SUM_RE_V = 0x1 +const UHCI_TX_CHECK_SUM_RE_S = 4 +const UHCI_SAVE_HEAD_V = 0x1 +const UHCI_SAVE_HEAD_S = 3 +const UHCI_CRC_DISABLE_V = 0x1 +const UHCI_CRC_DISABLE_S = 2 +const UHCI_CHECK_SEQ_EN_V = 0x1 +const UHCI_CHECK_SEQ_EN_S = 1 +const UHCI_CHECK_SUM_EN_V = 0x1 +const UHCI_CHECK_SUM_EN_S = 0 +const UHCI_DECODE_STATE = 0x00000007 +const UHCI_DECODE_STATE_V = 0x7 +const UHCI_DECODE_STATE_S = 3 +const UHCI_RX_ERR_CAUSE = 0x00000007 +const UHCI_RX_ERR_CAUSE_V = 0x7 +const UHCI_RX_ERR_CAUSE_S = 0 +const UHCI_ENCODE_STATE = 0x00000007 +const UHCI_ENCODE_STATE_V = 0x7 +const UHCI_ENCODE_STATE_S = 0 +const UHCI_RX_13_ESC_EN_V = 0x1 +const UHCI_RX_13_ESC_EN_S = 7 +const UHCI_RX_11_ESC_EN_V = 0x1 +const UHCI_RX_11_ESC_EN_S = 6 +const UHCI_RX_DB_ESC_EN_V = 0x1 +const UHCI_RX_DB_ESC_EN_S = 5 +const UHCI_RX_C0_ESC_EN_V = 0x1 +const UHCI_RX_C0_ESC_EN_S = 4 +const UHCI_TX_13_ESC_EN_V = 0x1 +const UHCI_TX_13_ESC_EN_S = 3 +const UHCI_TX_11_ESC_EN_V = 0x1 +const UHCI_TX_11_ESC_EN_S = 2 +const UHCI_TX_DB_ESC_EN_V = 0x1 +const UHCI_TX_DB_ESC_EN_S = 1 +const UHCI_TX_C0_ESC_EN_V = 0x1 +const UHCI_TX_C0_ESC_EN_S = 0 +const UHCI_RXFIFO_TIMEOUT_ENA_V = 0x1 +const UHCI_RXFIFO_TIMEOUT_ENA_S = 23 +const UHCI_RXFIFO_TIMEOUT_SHIFT = 0x00000007 +const UHCI_RXFIFO_TIMEOUT_SHIFT_V = 0x7 +const UHCI_RXFIFO_TIMEOUT_SHIFT_S = 20 +const UHCI_RXFIFO_TIMEOUT = 0x000000FF +const UHCI_RXFIFO_TIMEOUT_V = 0xFF +const UHCI_RXFIFO_TIMEOUT_S = 12 +const UHCI_TXFIFO_TIMEOUT_ENA_V = 0x1 +const UHCI_TXFIFO_TIMEOUT_ENA_S = 11 +const UHCI_TXFIFO_TIMEOUT_SHIFT = 0x00000007 +const UHCI_TXFIFO_TIMEOUT_SHIFT_V = 0x7 +const UHCI_TXFIFO_TIMEOUT_SHIFT_S = 8 +const UHCI_TXFIFO_TIMEOUT = 0x000000FF +const UHCI_TXFIFO_TIMEOUT_V = 0xFF +const UHCI_TXFIFO_TIMEOUT_S = 0 +const UHCI_ACK_NUM_LOAD_V = 0x1 +const UHCI_ACK_NUM_LOAD_S = 3 +const UHCI_ACK_NUM = 0x00000007 +const UHCI_ACK_NUM_V = 0x7 +const UHCI_ACK_NUM_S = 0 +const UHCI_RX_HEAD = 0xFFFFFFFF +const UHCI_RX_HEAD_V = 0xFFFFFFFF +const UHCI_RX_HEAD_S = 0 +const UHCI_ALWAYS_SEND_EN_V = 0x1 +const UHCI_ALWAYS_SEND_EN_S = 7 +const UHCI_ALWAYS_SEND_NUM = 0x00000007 +const UHCI_ALWAYS_SEND_NUM_V = 0x7 +const UHCI_ALWAYS_SEND_NUM_S = 4 +const UHCI_SINGLE_SEND_EN_V = 0x1 +const UHCI_SINGLE_SEND_EN_S = 3 +const UHCI_SINGLE_SEND_NUM = 0x00000007 +const UHCI_SINGLE_SEND_NUM_V = 0x7 +const UHCI_SINGLE_SEND_NUM_S = 0 +const UHCI_SEND_Q0_WORD0 = 0xFFFFFFFF +const UHCI_SEND_Q0_WORD0_V = 0xFFFFFFFF +const UHCI_SEND_Q0_WORD0_S = 0 +const UHCI_SEND_Q0_WORD1 = 0xFFFFFFFF +const UHCI_SEND_Q0_WORD1_V = 0xFFFFFFFF +const UHCI_SEND_Q0_WORD1_S = 0 +const UHCI_SEND_Q1_WORD0 = 0xFFFFFFFF +const UHCI_SEND_Q1_WORD0_V = 0xFFFFFFFF +const UHCI_SEND_Q1_WORD0_S = 0 +const UHCI_SEND_Q1_WORD1 = 0xFFFFFFFF +const UHCI_SEND_Q1_WORD1_V = 0xFFFFFFFF +const UHCI_SEND_Q1_WORD1_S = 0 +const UHCI_SEND_Q2_WORD0 = 0xFFFFFFFF +const UHCI_SEND_Q2_WORD0_V = 0xFFFFFFFF +const UHCI_SEND_Q2_WORD0_S = 0 +const UHCI_SEND_Q2_WORD1 = 0xFFFFFFFF +const UHCI_SEND_Q2_WORD1_V = 0xFFFFFFFF +const UHCI_SEND_Q2_WORD1_S = 0 +const UHCI_SEND_Q3_WORD0 = 0xFFFFFFFF +const UHCI_SEND_Q3_WORD0_V = 0xFFFFFFFF +const UHCI_SEND_Q3_WORD0_S = 0 +const UHCI_SEND_Q3_WORD1 = 0xFFFFFFFF +const UHCI_SEND_Q3_WORD1_V = 0xFFFFFFFF +const UHCI_SEND_Q3_WORD1_S = 0 +const UHCI_SEND_Q4_WORD0 = 0xFFFFFFFF +const UHCI_SEND_Q4_WORD0_V = 0xFFFFFFFF +const UHCI_SEND_Q4_WORD0_S = 0 +const UHCI_SEND_Q4_WORD1 = 0xFFFFFFFF +const UHCI_SEND_Q4_WORD1_V = 0xFFFFFFFF +const UHCI_SEND_Q4_WORD1_S = 0 +const UHCI_SEND_Q5_WORD0 = 0xFFFFFFFF +const UHCI_SEND_Q5_WORD0_V = 0xFFFFFFFF +const UHCI_SEND_Q5_WORD0_S = 0 +const UHCI_SEND_Q5_WORD1 = 0xFFFFFFFF +const UHCI_SEND_Q5_WORD1_V = 0xFFFFFFFF +const UHCI_SEND_Q5_WORD1_S = 0 +const UHCI_SEND_Q6_WORD0 = 0xFFFFFFFF +const UHCI_SEND_Q6_WORD0_V = 0xFFFFFFFF +const UHCI_SEND_Q6_WORD0_S = 0 +const UHCI_SEND_Q6_WORD1 = 0xFFFFFFFF +const UHCI_SEND_Q6_WORD1_V = 0xFFFFFFFF +const UHCI_SEND_Q6_WORD1_S = 0 +const UHCI_SEPER_ESC_CHAR1 = 0x000000FF +const UHCI_SEPER_ESC_CHAR1_V = 0xFF +const UHCI_SEPER_ESC_CHAR1_S = 16 +const UHCI_SEPER_ESC_CHAR0 = 0x000000FF +const UHCI_SEPER_ESC_CHAR0_V = 0xFF +const UHCI_SEPER_ESC_CHAR0_S = 8 +const UHCI_SEPER_CHAR = 0x000000FF +const UHCI_SEPER_CHAR_V = 0xFF +const UHCI_SEPER_CHAR_S = 0 +const UHCI_ESC_SEQ0_CHAR1 = 0x000000FF +const UHCI_ESC_SEQ0_CHAR1_V = 0xFF +const UHCI_ESC_SEQ0_CHAR1_S = 16 +const UHCI_ESC_SEQ0_CHAR0 = 0x000000FF +const UHCI_ESC_SEQ0_CHAR0_V = 0xFF +const UHCI_ESC_SEQ0_CHAR0_S = 8 +const UHCI_ESC_SEQ0 = 0x000000FF +const UHCI_ESC_SEQ0_V = 0xFF +const UHCI_ESC_SEQ0_S = 0 +const UHCI_ESC_SEQ1_CHAR1 = 0x000000FF +const UHCI_ESC_SEQ1_CHAR1_V = 0xFF +const UHCI_ESC_SEQ1_CHAR1_S = 16 +const UHCI_ESC_SEQ1_CHAR0 = 0x000000FF +const UHCI_ESC_SEQ1_CHAR0_V = 0xFF +const UHCI_ESC_SEQ1_CHAR0_S = 8 +const UHCI_ESC_SEQ1 = 0x000000FF +const UHCI_ESC_SEQ1_V = 0xFF +const UHCI_ESC_SEQ1_S = 0 +const UHCI_ESC_SEQ2_CHAR1 = 0x000000FF +const UHCI_ESC_SEQ2_CHAR1_V = 0xFF +const UHCI_ESC_SEQ2_CHAR1_S = 16 +const UHCI_ESC_SEQ2_CHAR0 = 0x000000FF +const UHCI_ESC_SEQ2_CHAR0_V = 0xFF +const UHCI_ESC_SEQ2_CHAR0_S = 8 +const UHCI_ESC_SEQ2 = 0x000000FF +const UHCI_ESC_SEQ2_V = 0xFF +const UHCI_ESC_SEQ2_S = 0 +const UHCI_PKT_THRS = 0x00001FFF +const UHCI_PKT_THRS_V = 0x1FFF +const UHCI_PKT_THRS_S = 0 +const UHCI_DATE = 0xFFFFFFFF +const UHCI_DATE_V = 0xFFFFFFFF +const UHCI_DATE_S = 0 diff --git a/esp32/uhci_struct.go b/esp32/uhci_struct.go new file mode 100644 index 00000000..2d68813d --- /dev/null +++ b/esp32/uhci_struct.go @@ -0,0 +1,69 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type UhciDevS struct { + Conf0 struct { + Val c.Uint32T + } + IntRaw struct { + Val c.Uint32T + } + IntSt struct { + Val c.Uint32T + } + IntEna struct { + Val c.Uint32T + } + IntClr struct { + Val c.Uint32T + } + AppIntSet struct { + Val c.Uint32T + } + Conf1 struct { + Val c.Uint32T + } + State0 struct { + Val c.Uint32T + } + State1 struct { + Val c.Uint32T + } + EscapeConf struct { + Val c.Uint32T + } + HungConf struct { + Val c.Uint32T + } + AckNum struct { + Val c.Uint32T + } + RxHead c.Uint32T + QuickSent struct { + Val c.Uint32T + } + QData [7]struct { + Word [2]c.Uint32T + } + EscConf0 struct { + Val c.Uint32T + } + EscConf1 struct { + Val c.Uint32T + } + EscConf2 struct { + Val c.Uint32T + } + EscConf3 struct { + Val c.Uint32T + } + PktThres struct { + Val c.Uint32T + } + Date c.Uint32T +} +type UhciDevT UhciDevS diff --git a/esp32/uhci_types.go b/esp32/uhci_types.go new file mode 100644 index 00000000..99643542 --- /dev/null +++ b/esp32/uhci_types.go @@ -0,0 +1,31 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief UHCI escape sequence + */ + +type UhciSeperChrT struct { + SeperChr c.Uint8T + SubChr1 c.Uint8T + SubChr2 c.Uint8T + SubChrEn bool +} + +/** + * @brief UHCI software flow control + */ + +type UhciSwflowCtrlSubChrT struct { + XonChr c.Uint8T + XonSub1 c.Uint8T + XonSub2 c.Uint8T + XoffChr c.Uint8T + XoffSub1 c.Uint8T + XoffSub2 c.Uint8T + FlowEn c.Uint8T +} diff --git a/esp32/usb_cdc.go b/esp32/usb_cdc.go new file mode 100644 index 00000000..e8a69b8d --- /dev/null +++ b/esp32/usb_cdc.go @@ -0,0 +1,116 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const CDC_SRN_1_20 = 0x0120 +const ACM_SUBCLASS = 0x02 +const ECM_SUBCLASS = 0x06 +const EEM_SUBCLASS = 0x0c +const AT_CMD_V250_PROTOCOL = 0x01 +const EEM_PROTOCOL = 0x07 +const DATA_INTERFACE_CLASS = 0x0A +const CS_INTERFACE = 0x24 +const CS_ENDPOINT = 0x25 +const HEADER_FUNC_DESC = 0x00 +const CALL_MANAGEMENT_FUNC_DESC = 0x01 +const ACM_FUNC_DESC = 0x02 +const UNION_FUNC_DESC = 0x06 +const ETHERNET_FUNC_DESC = 0x0F +const CDC_SEND_ENC_CMD = 0x00 +const CDC_GET_ENC_RSP = 0x01 +const SET_LINE_CODING = 0x20 +const GET_LINE_CODING = 0x21 +const SET_CONTROL_LINE_STATE = 0x22 +const SET_CONTROL_LINE_STATE_RTS = 0x02 +const SET_CONTROL_LINE_STATE_DTR = 0x01 +const SERIAL_STATE_OVERRUN = 0x40 +const SERIAL_STATE_PARITY = 0x20 +const SERIAL_STATE_FRAMING = 0x10 +const SERIAL_STATE_RING = 0x08 +const SERIAL_STATE_BREAK = 0x04 +const SERIAL_STATE_TX_CARRIER = 0x02 +const SERIAL_STATE_RX_CARRIER = 0x01 +const SET_ETHERNET_MULTICAST_FILTERS = 0x40 +const SET_ETHERNET_PM_FILTER = 0x41 +const GET_ETHERNET_PM_FILTER = 0x42 +const SET_ETHERNET_PACKET_FILTER = 0x43 +const GET_ETHERNET_STATISTIC = 0x44 +const PACKET_TYPE_MULTICAST = 0x10 +const PACKET_TYPE_BROADCAST = 0x08 +const PACKET_TYPE_DIRECTED = 0x04 +const PACKET_TYPE_ALL_MULTICAST = 0x02 +const PACKET_TYPE_PROMISCUOUS = 0x01 + +/** Header Functional Descriptor */ + +type CdcHeaderDescriptor struct { + BFunctionLength c.Uint8T + BDescriptorType c.Uint8T + BDescriptorSubtype c.Uint8T + BcdCDC c.Uint16T +} + +/** Union Interface Functional Descriptor */ + +type CdcUnionDescriptor struct { + BFunctionLength c.Uint8T + BDescriptorType c.Uint8T + BDescriptorSubtype c.Uint8T + BControlInterface c.Uint8T + BSubordinateInterface0 c.Uint8T +} + +/** Call Management Functional Descriptor */ + +type CdcCmDescriptor struct { + BFunctionLength c.Uint8T + BDescriptorType c.Uint8T + BDescriptorSubtype c.Uint8T + BmCapabilities c.Uint8T + BDataInterface c.Uint8T +} + +/** Abstract Control Management Functional Descriptor */ + +type CdcAcmDescriptor struct { + BFunctionLength c.Uint8T + BDescriptorType c.Uint8T + BDescriptorSubtype c.Uint8T + BmCapabilities c.Uint8T +} + +/** Data structure for GET_LINE_CODING / SET_LINE_CODING class requests */ + +type CdcAcmLineCoding struct { + DwDTERate c.Uint32T + BCharFormat c.Uint8T + BParityType c.Uint8T + BDataBits c.Uint8T +} + +/** Data structure for the notification about SerialState */ + +type CdcAcmNotification struct { + BmRequestType c.Uint8T + BNotificationType c.Uint8T + WValue c.Uint16T + WIndex c.Uint16T + WLength c.Uint16T + Data c.Uint16T +} + +/** Ethernet Networking Functional Descriptor */ + +type CdcEcmDescriptor struct { + BFunctionLength c.Uint8T + BDescriptorType c.Uint8T + BDescriptorSubtype c.Uint8T + IMACAddress c.Uint8T + BmEthernetStatistics c.Uint32T + WMaxSegmentSize c.Uint16T + WNumberMCFilters c.Uint16T + BNumberPowerFilters c.Uint8T +} diff --git a/esp32/usb_console.go b/esp32/usb_console.go new file mode 100644 index 00000000..b7e3f984 --- /dev/null +++ b/esp32/usb_console.go @@ -0,0 +1,86 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:type C +type EspUsbConsoleCbT func(c.Pointer) + +/** + * Initialize USB console output using ROM USB CDC driver. + * This function is called by the early startup code if USB CDC is + * selected as the console output option. + * @return + * - ESP_OK on success + * - ESP_ERR_NO_MEM + * - other error codes from the interrupt allocator + */ +//go:linkname EspUsbConsoleInit C.esp_usb_console_init +func EspUsbConsoleInit() EspErrT + +/** + * Write a buffer to USB CDC + * @param buf data to write + * @param size size of the data, in bytes + * @return -1 on error, otherwise the number of bytes + */ +//go:linkname EspUsbConsoleWriteBuf C.esp_usb_console_write_buf +func EspUsbConsoleWriteBuf(buf *c.Char, size c.SizeT) c.SsizeT + +/** + * @brief Wait until all buffered USB CDC output is written + * + * @return ssize_t Number of bytes written, or -1 if the driver is not initialized + */ +//go:linkname EspUsbConsoleFlush C.esp_usb_console_flush +func EspUsbConsoleFlush() c.SsizeT + +/** + * @brief Read data from USB CDC + * + * May read less data than requested. + * + * @param buf Buffer to read data into + * @param buf_size Size of the buffer + * @return ssize_t Number of bytes written into the buffer, or -1 if the driver is not initialized + */ +//go:linkname EspUsbConsoleReadBuf C.esp_usb_console_read_buf +func EspUsbConsoleReadBuf(buf *c.Char, buf_size c.SizeT) c.SsizeT + +/** + * @brief Get the number of bytes available for reading from USB CDC + * + * @return ssize_t Number of bytes available, or -1 if the driver is not initialized + */ +//go:linkname EspUsbConsoleAvailableForRead C.esp_usb_console_available_for_read +func EspUsbConsoleAvailableForRead() c.SsizeT + +/** + * @brief Check if data can be written into USB CDC + * + * @return true if data can be written now without blocking + */ +//go:linkname EspUsbConsoleWriteAvailable C.esp_usb_console_write_available +func EspUsbConsoleWriteAvailable() bool + +/** + * @brief Set RX/TX callback functions to be called from ISR + * + * @param rx_cb RX callback function + * @param tx_cb TX callback function + * @param arg callback-specific context pointer + * @return ESP_OK if the callbacks were set, ESP_ERR_INVALID_STATE if the driver is not initialized + */ +//go:linkname EspUsbConsoleSetCb C.esp_usb_console_set_cb +func EspUsbConsoleSetCb(rx_cb EspUsbConsoleCbT, tx_cb EspUsbConsoleCbT, arg c.Pointer) EspErrT + +/** + * @brief Call the USB interrupt handler while any interrupts + * are pending, but not more than a few times. Non-static to + * allow placement into IRAM by ldgen. + * + */ +//go:linkname EspUsbConsolePollInterrupts C.esp_usb_console_poll_interrupts +func EspUsbConsolePollInterrupts() diff --git a/esp32/usb_dc.go b/esp32/usb_dc.go new file mode 100644 index 00000000..a34521c7 --- /dev/null +++ b/esp32/usb_dc.go @@ -0,0 +1,394 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const USB_EP_DIR_MASK = 0x80 +const USB_EP_DIR_IN = 0x80 +const USB_EP_DIR_OUT = 0x00 + +type UsbDcStatusCode c.Int + +const ( + USB_DC_ERROR UsbDcStatusCode = 0 + USB_DC_RESET UsbDcStatusCode = 1 + USB_DC_CONNECTED UsbDcStatusCode = 2 + USB_DC_CONFIGURED UsbDcStatusCode = 3 + USB_DC_DISCONNECTED UsbDcStatusCode = 4 + USB_DC_SUSPEND UsbDcStatusCode = 5 + USB_DC_RESUME UsbDcStatusCode = 6 + USB_DC_INTERFACE UsbDcStatusCode = 7 + USB_DC_SET_HALT UsbDcStatusCode = 8 + USB_DC_CLEAR_HALT UsbDcStatusCode = 9 + USB_DC_UNKNOWN UsbDcStatusCode = 10 +) + +type UsbDcEpCbStatusCode c.Int + +const ( + USB_DC_EP_SETUP UsbDcEpCbStatusCode = 0 + USB_DC_EP_DATA_OUT UsbDcEpCbStatusCode = 1 + USB_DC_EP_DATA_IN UsbDcEpCbStatusCode = 2 +) + +type UsbDcEpType c.Int + +const ( + USB_DC_EP_CONTROL UsbDcEpType = 0 + USB_DC_EP_ISOCHRONOUS UsbDcEpType = 1 + USB_DC_EP_BULK UsbDcEpType = 2 + USB_DC_EP_INTERRUPT UsbDcEpType = 3 +) + +/** + * USB Endpoint Configuration. + */ + +type UsbDcEpCfgData struct { + EpAddr c.Uint8T + EpMps c.Uint16T + EpType UsbDcEpType +} + +// llgo:type C +type UsbDcEpCallback func(c.Uint8T, UsbDcEpCbStatusCode) + +// llgo:type C +type UsbDcStatusCallback func(UsbDcStatusCode, *c.Uint8T) + +/** + * @brief attach USB for device connection + * + * Function to attach USB for device connection. Upon success, the USB PLL + * is enabled, and the USB device is now capable of transmitting and receiving + * on the USB bus and of generating interrupts. + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcAttach C.usb_dc_attach +func UsbDcAttach() c.Int + +/** + * @brief detach the USB device + * + * Function to detach the USB device. Upon success, the USB hardware PLL + * is powered down and USB communication is disabled. + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcDetach C.usb_dc_detach +func UsbDcDetach() c.Int + +/** + * @brief reset the USB device + * + * This function returns the USB device and firmware back to it's initial state. + * N.B. the USB PLL is handled by the usb_detach function + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcReset C.usb_dc_reset +func UsbDcReset() c.Int + +/** + * @brief set USB device address + * + * @param[in] addr device address + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcSetAddress C.usb_dc_set_address +func UsbDcSetAddress(addr c.Uint8T) c.Int + +/** + * @brief set USB device controller status callback + * + * Function to set USB device controller status callback. The registered + * callback is used to report changes in the status of the device controller. + * + * @param[in] cb callback function + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcSetStatusCallback C.usb_dc_set_status_callback +func UsbDcSetStatusCallback(cb UsbDcStatusCallback) c.Int + +/** + * @brief check endpoint capabilities + * + * Function to check capabilities of an endpoint. usb_dc_ep_cfg_data structure + * provides the endpoint configuration parameters: endpoint address, + * endpoint maximum packet size and endpoint type. + * The driver should check endpoint capabilities and return 0 if the + * endpoint configuration is possible. + * + * @param[in] cfg Endpoint config + * + * @return 0 on success, negative errno code on fail. + */ +// llgo:link (*UsbDcEpCfgData).UsbDcEpCheckCap C.usb_dc_ep_check_cap +func (recv_ *UsbDcEpCfgData) UsbDcEpCheckCap() c.Int { + return 0 +} + +/** + * @brief configure endpoint + * + * Function to configure an endpoint. usb_dc_ep_cfg_data structure provides + * the endpoint configuration parameters: endpoint address, endpoint maximum + * packet size and endpoint type. + * + * @param[in] cfg Endpoint config + * + * @return 0 on success, negative errno code on fail. + */ +// llgo:link (*UsbDcEpCfgData).UsbDcEpConfigure C.usb_dc_ep_configure +func (recv_ *UsbDcEpCfgData) UsbDcEpConfigure() c.Int { + return 0 +} + +/** + * @brief set stall condition for the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcEpSetStall C.usb_dc_ep_set_stall +func UsbDcEpSetStall(ep c.Uint8T) c.Int + +/** + * @brief clear stall condition for the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcEpClearStall C.usb_dc_ep_clear_stall +func UsbDcEpClearStall(ep c.Uint8T) c.Int + +/** + * @brief check if selected endpoint is stalled + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[out] stalled Endpoint stall status + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcEpIsStalled C.usb_dc_ep_is_stalled +func UsbDcEpIsStalled(ep c.Uint8T, stalled *c.Uint8T) c.Int + +/** + * @brief halt the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcEpHalt C.usb_dc_ep_halt +func UsbDcEpHalt(ep c.Uint8T) c.Int + +/** + * @brief enable the selected endpoint + * + * Function to enable the selected endpoint. Upon success interrupts are + * enabled for the corresponding endpoint and the endpoint is ready for + * transmitting/receiving data. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcEpEnable C.usb_dc_ep_enable +func UsbDcEpEnable(ep c.Uint8T) c.Int + +/** + * @brief disable the selected endpoint + * + * Function to disable the selected endpoint. Upon success interrupts are + * disabled for the corresponding endpoint and the endpoint is no longer able + * for transmitting/receiving data. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcEpDisable C.usb_dc_ep_disable +func UsbDcEpDisable(ep c.Uint8T) c.Int + +/** + * @brief flush the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcEpFlush C.usb_dc_ep_flush +func UsbDcEpFlush(ep c.Uint8T) c.Int + +/** + * @brief write data to the specified endpoint + * + * This function is called to write data to the specified endpoint. The supplied + * usb_ep_callback function will be called when data is transmitted out. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data pointer to data to write + * @param[in] data_len length of data requested to write. This may + * be zero for a zero length status packet. + * @param[out] ret_bytes bytes scheduled for transmission. This value + * may be NULL if the application expects all + * bytes to be written + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcEpWrite C.usb_dc_ep_write +func UsbDcEpWrite(ep c.Uint8T, data *c.Uint8T, data_len c.Uint32T, ret_bytes *c.Uint32T) c.Int + +/** + * @brief Indicate if the write to an IN endpoint (using usb_dc_ep_write) would block + * to wait until the endpoint has enoug space + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 when writable, 0 when not, negative errno code on fail. + */ +//go:linkname UsbDcEpWriteWouldBlock C.usb_dc_ep_write_would_block +func UsbDcEpWriteWouldBlock(ep c.Uint8T) c.Int + +/** + * @brief read data from the specified endpoint + * + * This function is called by the Endpoint handler function, after an OUT + * interrupt has been received for that EP. The application must only call this + * function through the supplied usb_ep_callback function. This function clears + * the ENDPOINT NAK, if all data in the endpoint FIFO has been read, + * so as to accept more data from host. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data pointer to data buffer to write to + * @param[in] max_data_len max length of data to read + * @param[out] read_bytes Number of bytes read. If data is NULL and + * max_data_len is 0 the number of bytes + * available for read should be returned. + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcEpRead C.usb_dc_ep_read +func UsbDcEpRead(ep c.Uint8T, data *c.Uint8T, max_data_len c.Uint32T, read_bytes *c.Uint32T) c.Int + +/** + * @brief set callback function for the specified endpoint + * + * Function to set callback function for notification of data received and + * available to application or transmit done on the selected endpoint, + * NULL if callback not required by application code. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] cb callback function + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcEpSetCallback C.usb_dc_ep_set_callback +func UsbDcEpSetCallback(ep c.Uint8T, cb UsbDcEpCallback) c.Int + +/** + * @brief read data from the specified endpoint + * + * This is similar to usb_dc_ep_read, the difference being that, it doesn't + * clear the endpoint NAKs so that the consumer is not bogged down by further + * upcalls till he is done with the processing of the data. The caller should + * reactivate ep by invoking usb_dc_ep_read_continue() do so. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data pointer to data buffer to write to + * @param[in] max_data_len max length of data to read + * @param[out] read_bytes Number of bytes read. If data is NULL and + * max_data_len is 0 the number of bytes + * available for read should be returned. + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcEpReadWait C.usb_dc_ep_read_wait +func UsbDcEpReadWait(ep c.Uint8T, data *c.Uint8T, max_data_len c.Uint32T, read_bytes *c.Uint32T) c.Int + +/** + * @brief Continue reading data from the endpoint + * + * Clear the endpoint NAK and enable the endpoint to accept more data + * from the host. Usually called after usb_dc_ep_read_wait() when the consumer + * is fine to accept more data. Thus these calls together acts as flow control + * mechanism. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbDcEpReadContinue C.usb_dc_ep_read_continue +func UsbDcEpReadContinue(ep c.Uint8T) c.Int + +/** + * @brief Get endpoint max packet size + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return endpoint max packet size (mps) + */ +//go:linkname UsbDcEpMps C.usb_dc_ep_mps +func UsbDcEpMps(ep c.Uint8T) c.Int + +/** + * @brief Poll for interrupts that need to be handled + * + * When the USB interrupt is not hooked up to an actual CPU interrupt, you + * can call this periodically to handle the USB events that need handling. + */ +//go:linkname UsbDcCheckPollForInterrupts C.usb_dc_check_poll_for_interrupts +func UsbDcCheckPollForInterrupts() + +/* + * @brief Prepare for USB persist + * + * This takes the USB peripheral offline in such a way that it seems 'just busy' to the + * host. This way, the chip can reboot (e.g. into bootloader mode) and pick up the USB + * configuration again, without the connection to the host being interrupted. + * + * @note Actual persistence is depending on USBDC_PERSIST_ENA being set in flags, as this + * is also used to e.g. reboot into DFU mode. + * + * @note Please reboot soon after calling this. + */ +//go:linkname UsbDcPreparePersist C.usb_dc_prepare_persist +func UsbDcPreparePersist() c.Int + +/* + * @brief USB interrupt handler + * + * This can be hooked up by the OS to the USB peripheral interrupt. + */ +//go:linkname UsbDwIsrHandler C.usb_dw_isr_handler +func UsbDwIsrHandler() + +/** + * @brief Provide IDF with an interface to clear the static variable usb_dw_ctrl + * + * + */ +//go:linkname UsbDwCtrlDeinit C.usb_dw_ctrl_deinit +func UsbDwCtrlDeinit() diff --git a/esp32/usb_descriptor.go b/esp32/usb_descriptor.go new file mode 100644 index 00000000..ed37ce42 --- /dev/null +++ b/esp32/usb_descriptor.go @@ -0,0 +1,15 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const USB_DESCRIPTOR_TYPE_ACM = 0 +const USB_DESCRIPTOR_TYPE_DFU = 1 + +//go:linkname UsbSetCurrentDescriptor C.usb_set_current_descriptor +func UsbSetCurrentDescriptor(descriptor_type c.Int) + +//go:linkname UsbGetDescriptor C.usb_get_descriptor +func UsbGetDescriptor(type_index c.Uint16T, lang_id c.Uint16T, len *c.Int32T, data **c.Uint8T) bool diff --git a/esp32/usb_device.go b/esp32/usb_device.go new file mode 100644 index 00000000..a0fffbce --- /dev/null +++ b/esp32/usb_device.go @@ -0,0 +1,311 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const MAX_PACKET_SIZE0 = 64 + +/** setup packet definitions */ + +type UsbSetupPacket struct { + BmRequestType c.Uint8T + BRequest c.Uint8T + WValue c.Uint16T + WIndex c.Uint16T + WLength c.Uint16T +} + +// llgo:type C +type UsbStatusCallback func(UsbDcStatusCode, *c.Uint8T) + +// llgo:type C +type UsbEpCallback func(c.Uint8T, UsbDcEpCbStatusCode) + +// llgo:type C +type UsbRequestHandler func(*UsbSetupPacket, *c.Int32T, **c.Uint8T) c.Int + +// llgo:type C +type UsbInterfaceConfig func(c.Uint8T) + +/* + * USB Endpoint Configuration + */ + +type UsbEpCfgData struct { + EpCb UsbEpCallback + EpAddr c.Uint8T +} + +/** + * USB Interface Configuration + */ + +type UsbInterfaceCfgData struct { + ClassHandler UsbRequestHandler + VendorHandler UsbRequestHandler + CustomHandler UsbRequestHandler + PayloadData *c.Uint8T + VendorData *c.Uint8T +} + +/* + * @brief USB device configuration + * + * The Application instantiates this with given parameters added + * using the "usb_set_config" function. Once this function is called + * changes to this structure will result in undefined behaviour. This structure + * may only be updated after calls to usb_deconfig + */ + +type UsbCfgData struct { + UsbDeviceDescription *c.Uint8T + InterfaceDescriptor c.Pointer + InterfaceConfig UsbInterfaceConfig + CbUsbStatus UsbStatusCallback + Interface UsbInterfaceCfgData + NumEndpoints c.Uint8T + Endpoint *UsbEpCfgData +} + +/* + * @brief configure USB controller + * + * Function to configure USB controller. + * Configuration parameters must be valid or an error is returned + * + * @param[in] config Pointer to configuration structure + * + * @return 0 on success, negative errno code on fail + */ +// llgo:link (*UsbCfgData).UsbSetConfig C.usb_set_config +func (recv_ *UsbCfgData) UsbSetConfig() c.Int { + return 0 +} + +/* + * @brief return the USB device to it's initial state + * + * @return 0 on success, negative errno code on fail + */ +//go:linkname UsbDeconfig C.usb_deconfig +func UsbDeconfig() c.Int + +/* + * @brief enable USB for host/device connection + * + * Function to enable USB for host/device connection. + * Upon success, the USB module is no longer clock gated in hardware, + * it is now capable of transmitting and receiving on the USB bus and + * of generating interrupts. + * + * @return 0 on success, negative errno code on fail. + */ +// llgo:link (*UsbCfgData).UsbEnable C.usb_enable +func (recv_ *UsbCfgData) UsbEnable() c.Int { + return 0 +} + +/* + * @brief disable the USB device. + * + * Function to disable the USB device. + * Upon success, the specified USB interface is clock gated in hardware, + * it is no longer capable of generating interrupts. + * + * @return 0 on success, negative errno code on fail + */ +//go:linkname UsbDisable C.usb_disable +func UsbDisable() c.Int + +/* + * @brief Check if a write to an in ep would block until there is enough space + * in the fifo + * + * @param[in] ep Endpoint address corresponding to the one listed in the + * device configuration table + * + * @return 0 if free to write, 1 if a write would block, negative errno code on fail + */ +//go:linkname UsbWriteWouldBlock C.usb_write_would_block +func UsbWriteWouldBlock(ep c.Uint8T) c.Int + +/* + * @brief write data to the specified endpoint + * + * Function to write data to the specified endpoint. The supplied + * usb_ep_callback will be called when transmission is done. + * + * @param[in] ep Endpoint address corresponding to the one listed in the + * device configuration table + * @param[in] data Pointer to data to write + * @param[in] data_len Length of data requested to write. This may be zero for + * a zero length status packet. + * @param[out] bytes_ret Bytes written to the EP FIFO. This value may be NULL if + * the application expects all bytes to be written + * + * @return 0 on success, negative errno code on fail + */ +//go:linkname UsbWrite C.usb_write +func UsbWrite(ep c.Uint8T, data *c.Uint8T, data_len c.Uint32T, bytes_ret *c.Uint32T) c.Int + +/* + * @brief read data from the specified endpoint + * + * This function is called by the Endpoint handler function, after an + * OUT interrupt has been received for that EP. The application must + * only call this function through the supplied usb_ep_callback function. + * + * @param[in] ep Endpoint address corresponding to the one listed in + * the device configuration table + * @param[in] data Pointer to data buffer to write to + * @param[in] max_data_len Max length of data to read + * @param[out] ret_bytes Number of bytes read. If data is NULL and + * max_data_len is 0 the number of bytes available + * for read is returned. + * + * @return 0 on success, negative errno code on fail + */ +//go:linkname UsbRead C.usb_read +func UsbRead(ep c.Uint8T, data *c.Uint8T, max_data_len c.Uint32T, ret_bytes *c.Uint32T) c.Int + +/* + * @brief set STALL condition on the specified endpoint + * + * This function is called by USB device class handler code to set stall + * condition on endpoint. + * + * @param[in] ep Endpoint address corresponding to the one listed in + * the device configuration table + * + * @return 0 on success, negative errno code on fail + */ +//go:linkname UsbEpSetStall C.usb_ep_set_stall +func UsbEpSetStall(ep c.Uint8T) c.Int + +/* + * @brief clears STALL condition on the specified endpoint + * + * This function is called by USB device class handler code to clear stall + * condition on endpoint. + * + * @param[in] ep Endpoint address corresponding to the one listed in + * the device configuration table + * + * @return 0 on success, negative errno code on fail + */ +//go:linkname UsbEpClearStall C.usb_ep_clear_stall +func UsbEpClearStall(ep c.Uint8T) c.Int + +/** + * @brief read data from the specified endpoint + * + * This is similar to usb_ep_read, the difference being that, it doesn't + * clear the endpoint NAKs so that the consumer is not bogged down by further + * upcalls till he is done with the processing of the data. The caller should + * reactivate ep by invoking usb_ep_read_continue() do so. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data pointer to data buffer to write to + * @param[in] max_data_len max length of data to read + * @param[out] read_bytes Number of bytes read. If data is NULL and + * max_data_len is 0 the number of bytes + * available for read should be returned. + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbEpReadWait C.usb_ep_read_wait +func UsbEpReadWait(ep c.Uint8T, data *c.Uint8T, max_data_len c.Uint32T, read_bytes *c.Uint32T) c.Int + +/** + * @brief Continue reading data from the endpoint + * + * Clear the endpoint NAK and enable the endpoint to accept more data + * from the host. Usually called after usb_ep_read_wait() when the consumer + * is fine to accept more data. Thus these calls together acts as flow control + * mechanism. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbEpReadContinue C.usb_ep_read_continue +func UsbEpReadContinue(ep c.Uint8T) c.Int + +// llgo:type C +type UsbTransferCallback func(c.Uint8T, c.Int, c.Pointer) + +/** + * @brief Transfer management endpoint callback + * + * If a USB class driver wants to use high-level transfer functions, driver + * needs to register this callback as usb endpoint callback. + */ +//go:linkname UsbTransferEpCallback C.usb_transfer_ep_callback +func UsbTransferEpCallback(ep c.Uint8T, __llgo_arg_1 UsbDcEpCbStatusCode) + +/** + * @brief Start a transfer + * + * Start a usb transfer to/from the data buffer. This function is asynchronous + * and can be executed in IRQ context. The provided callback will be called + * on transfer completion (or error) in thread context. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data buffer to write-to/read-from + * @param[in] dlen Size of data buffer + * @param[in] flags Transfer flags (USB_TRANS_READ, USB_TRANS_WRITE...) + * @param[in] cb Function called on transfer completion/failure + * @param[in] priv Data passed back to the transfer completion callback + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbTransfer C.usb_transfer +func UsbTransfer(ep c.Uint8T, data *c.Uint8T, dlen c.SizeT, flags c.Uint, cb UsbTransferCallback, priv c.Pointer) c.Int + +/** + * @brief Start a transfer and block-wait for completion + * + * Synchronous version of usb_transfer, wait for transfer completion before + * returning. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data buffer to write-to/read-from + * @param[in] dlen Size of data buffer + * @param[in] flags Transfer flags + + * + * @return number of bytes transferred on success, negative errno code on fail. + */ +//go:linkname UsbTransferSync C.usb_transfer_sync +func UsbTransferSync(ep c.Uint8T, data *c.Uint8T, dlen c.SizeT, flags c.Uint) c.Int + +/** + * @brief Cancel any ongoing transfer on the specified endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +//go:linkname UsbCancelTransfer C.usb_cancel_transfer +func UsbCancelTransfer(ep c.Uint8T) + +/** + * @brief Provide IDF with an interface to clear the static variable usb_dev + * + * + */ +//go:linkname UsbDevDeinit C.usb_dev_deinit +func UsbDevDeinit() + +//go:linkname UsbDevResume C.usb_dev_resume +func UsbDevResume(configuration c.Int) + +//go:linkname UsbDevGetConfiguration C.usb_dev_get_configuration +func UsbDevGetConfiguration() c.Int diff --git a/esp32/usb_dfu.go b/esp32/usb_dfu.go new file mode 100644 index 00000000..7ee3cb9d --- /dev/null +++ b/esp32/usb_dfu.go @@ -0,0 +1,99 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const DFU_SUBCLASS = 0x01 +const DFU_RT_PROTOCOL = 0x01 +const DFU_MODE_PROTOCOL = 0x02 +const DFU_DETACH = 0x00 +const DFU_DNLOAD = 0x01 +const DFU_UPLOAD = 0x02 +const DFU_GETSTATUS = 0x03 +const DFU_CLRSTATUS = 0x04 +const DFU_GETSTATE = 0x05 +const DFU_ABORT = 0x06 +const DFU_FUNC_DESC = 0x21 +const DFU_ATTR_WILL_DETACH = 0x08 +const DFU_ATTR_MANIFESTATION_TOLERANT = 0x04 +const DFU_ATTR_CAN_UPLOAD = 0x02 +const DFU_ATTR_CAN_DNLOAD = 0x01 +const DFU_VERSION = 0x0110 + +/** Run-Time Functional Descriptor */ + +type DfuRuntimeDescriptor struct { + BLength c.Uint8T + BDescriptorType c.Uint8T + BmAttributes c.Uint8T + WDetachTimeOut c.Uint16T + WTransferSize c.Uint16T + BcdDFUVersion c.Uint16T +} +type DfuStatus c.Int + +const ( + StatusOK DfuStatus = 0 + ErrTARGET DfuStatus = 1 + ErrFILE DfuStatus = 2 + ErrWRITE DfuStatus = 3 + ErrERASE DfuStatus = 4 + ErrCHECK_ERASED DfuStatus = 5 + ErrPROG DfuStatus = 6 + ErrVERIFY DfuStatus = 7 + ErrADDRESS DfuStatus = 8 + ErrNOTDONE DfuStatus = 9 + ErrFIRMWARE DfuStatus = 10 + ErrVENDOR DfuStatus = 11 + ErrUSB DfuStatus = 12 + ErrPOR DfuStatus = 13 + ErrUNKNOWN DfuStatus = 14 + ErrSTALLEDPKT DfuStatus = 15 +) + +type DfuState c.Int + +const ( + AppIDLE DfuState = 0 + AppDETACH DfuState = 1 + DfuIDLE DfuState = 2 + DfuDNLOAD_SYNC DfuState = 3 + DfuDNBUSY DfuState = 4 + DfuDNLOAD_IDLE DfuState = 5 + DfuMANIFEST_SYNC DfuState = 6 + DfuMANIFEST DfuState = 7 + DfuMANIFEST_WAIT_RST DfuState = 8 + DfuUPLOAD_IDLE DfuState = 9 + DfuERROR DfuState = 10 +) + +/* + These callbacks are made public so the ACM driver can call them to handle the switch to DFU. +*/ +// llgo:link (*UsbSetupPacket).DfuClassHandleReq C.dfu_class_handle_req +func (recv_ *UsbSetupPacket) DfuClassHandleReq(data_len *c.Int32T, data **c.Uint8T) c.Int { + return 0 +} + +// llgo:link UsbDcStatusCode.DfuStatusCb C.dfu_status_cb +func (recv_ UsbDcStatusCode) DfuStatusCb(param *c.Uint8T) { +} + +//go:linkname UsbDfuInit C.usb_dfu_init +func UsbDfuInit() c.Int + +// llgo:link (*UsbSetupPacket).DfuCustomHandleReq C.dfu_custom_handle_req +func (recv_ *UsbSetupPacket) DfuCustomHandleReq(data_len *c.Int32T, data **c.Uint8T) c.Int { + return 0 +} + +// llgo:type C +type UsbDfuDetachRoutineT func(c.Int) + +//go:linkname UsbDfuSetDetachCb C.usb_dfu_set_detach_cb +func UsbDfuSetDetachCb(cb UsbDfuDetachRoutineT) + +//go:linkname UsbDfuForceDetach C.usb_dfu_force_detach +func UsbDfuForceDetach() diff --git a/esp32/usb_dwc_cfg.go b/esp32/usb_dwc_cfg.go new file mode 100644 index 00000000..575af01f --- /dev/null +++ b/esp32/usb_dwc_cfg.go @@ -0,0 +1,54 @@ +package freertos + +import _ "unsafe" + +const OTG_MODE = 0 +const OTG_ARCHITECTURE = 2 +const OTG_SINGLE_POINT = 1 +const OTG_ENABLE_LPM = 0 +const OTG_EN_DED_TX_FIFO = 1 +const OTG_EN_DESC_DMA = 1 +const OTG_MULTI_PROC_INTRPT = 0 +const OTG_HSPHY_INTERFACE = 0 +const OTG_FSPHY_INTERFACE = 1 +const OTG_ENABLE_IC_USB = 0 +const OTG_I2C_INTERFACE = 0 +const OTG_ADP_SUPPORT = 0 +const OTG_BC_SUPPORT = 0 +const OTG_NUM_EPS = 6 +const OTG_NUM_IN_EPS = 5 +const OTG_NUM_CRL_EPS = 0 +const OTG_NUM_HOST_CHAN = 8 +const OTG_EN_PERIO_HOST = 1 +const OTG_DFIFO_DEPTH = 256 +const OTG_DFIFO_DYNAMIC = 1 +const OTG_RX_DFIFO_DEPTH = 256 +const OTG_TX_HNPERIO_DFIFO_DEPTH = 256 +const OTG_TX_NPERIO_DFIFO_DEPTH = 256 +const OTG_TX_HPERIO_DFIFO_DEPTH = 256 +const OTG_NPERIO_TX_QUEUE_DEPTH = 4 +const OTG_PERIO_TX_QUEUE_DEPTH = 8 +const OTG_TRANS_COUNT_WIDTH = 16 +const OTG_PACKET_COUNT_WIDTH = 7 +const OTG_RM_OPT_FEATURES = 1 +const OTG_EN_PWROPT = 1 +const OTG_SYNC_RESET_TYPE = 0 +const OTG_EN_IDDIG_FILTER = 1 +const OTG_EN_VBUSVALID_FILTER = 1 +const OTG_EN_A_VALID_FILTER = 1 +const OTG_EN_B_VALID_FILTER = 1 +const OTG_EN_SESSIONEND_FILTER = 1 +const OTG_EXCP_CNTL_XFER_FLOW = 1 +const OTG_PWR_CLAMP = 0 +const OTG_PWR_SWITCH_POLARITY = 0 +const OTG_EP_DIR_1 = 0 +const OTG_EP_DIR_2 = 0 +const OTG_EP_DIR_3 = 0 +const OTG_EP_DIR_4 = 0 +const OTG_EP_DIR_5 = 0 +const OTG_EP_DIR_6 = 0 +const OTG_TX_DINEP_DFIFO_DEPTH_1 = 256 +const OTG_TX_DINEP_DFIFO_DEPTH_2 = 256 +const OTG_TX_DINEP_DFIFO_DEPTH_3 = 256 +const OTG_TX_DINEP_DFIFO_DEPTH_4 = 256 +const U2UB_EN = 0 diff --git a/esp32/usb_dwc_hal.go b/esp32/usb_dwc_hal.go new file mode 100644 index 00000000..3349f8f8 --- /dev/null +++ b/esp32/usb_dwc_hal.go @@ -0,0 +1,347 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const USB_DWC_HAL_XFER_DESC_FLAG_IN = 0x01 +const USB_DWC_HAL_XFER_DESC_FLAG_SETUP = 0x02 +const USB_DWC_HAL_XFER_DESC_FLAG_HOC = 0x04 + +type UsbHalFifoBiasT c.Int + +const ( + USB_HAL_FIFO_BIAS_DEFAULT UsbHalFifoBiasT = 0 + USB_HAL_FIFO_BIAS_RX UsbHalFifoBiasT = 1 + USB_HAL_FIFO_BIAS_PTX UsbHalFifoBiasT = 2 +) + +/** + * @brief MPS limits based on FIFO configuration + * + * In bytes + * + * The resulting values depend on + * 1. FIFO total size (chip specific) + * 2. Set FIFO bias + */ + +type UsbHalFifoMpsLimitsT struct { + InMps c.Uint + NonPeriodicOutMps c.Uint + PeriodicOutMps c.Uint +} + +/** + * @brief FIFO size configuration structure + */ + +type UsbDwcHalFifoConfigT struct { + RxFifoLines c.Uint32T + NptxFifoLines c.Uint32T + PtxFifoLines c.Uint32T +} +type UsbDwcHalPortEventT c.Int + +const ( + USB_DWC_HAL_PORT_EVENT_NONE UsbDwcHalPortEventT = 0 + USB_DWC_HAL_PORT_EVENT_CHAN UsbDwcHalPortEventT = 1 + USB_DWC_HAL_PORT_EVENT_CONN UsbDwcHalPortEventT = 2 + USB_DWC_HAL_PORT_EVENT_DISCONN UsbDwcHalPortEventT = 3 + USB_DWC_HAL_PORT_EVENT_ENABLED UsbDwcHalPortEventT = 4 + USB_DWC_HAL_PORT_EVENT_DISABLED UsbDwcHalPortEventT = 5 + USB_DWC_HAL_PORT_EVENT_OVRCUR UsbDwcHalPortEventT = 6 + USB_DWC_HAL_PORT_EVENT_OVRCUR_CLR UsbDwcHalPortEventT = 7 +) + +type UsbDwcHalChanEventT c.Int + +const ( + USB_DWC_HAL_CHAN_EVENT_CPLT UsbDwcHalChanEventT = 0 + USB_DWC_HAL_CHAN_EVENT_ERROR UsbDwcHalChanEventT = 1 + USB_DWC_HAL_CHAN_EVENT_HALT_REQ UsbDwcHalChanEventT = 2 + USB_DWC_HAL_CHAN_EVENT_NONE UsbDwcHalChanEventT = 3 +) + +type UsbDwcHalChanErrorT c.Int + +const ( + USB_DWC_HAL_CHAN_ERROR_XCS_XACT UsbDwcHalChanErrorT = 0 + USB_DWC_HAL_CHAN_ERROR_BNA UsbDwcHalChanErrorT = 1 + USB_DWC_HAL_CHAN_ERROR_PKT_BBL UsbDwcHalChanErrorT = 2 + USB_DWC_HAL_CHAN_ERROR_STALL UsbDwcHalChanErrorT = 3 +) + +/** + * @brief Endpoint characteristics structure + */ + +type UsbDwcHalEpCharT struct { + Periodic struct { + Interval c.Uint + Offset c.Uint32T + IsHs bool + } +} + +/** + * @brief Channel object + */ + +type UsbDwcHalChanT struct { + Flags struct { + Val c.Uint32T + } + Regs *UsbDwcHostChanRegsT + Error UsbDwcHalChanErrorT + Type UsbDwcXferTypeT + ChanCtx c.Pointer +} + +/** + * @brief HAL context structure + */ + +type UsbDwcHalContextT struct { + Dev *UsbDwcDevT + PeriodicFrameList *c.Uint32T + FrameListLen UsbHalFrameListLenT + FifoConfig UsbDwcHalFifoConfigT + ConstantConfig struct { + ChanNumTotal c.Uint + HsphyType c.Uint + FifoSize c.Uint + } + Flags struct { + Val c.Uint32T + } + Channels struct { + NumAllocated c.Int + ChanPendIntrsMsk c.Uint32T + Hdls **UsbDwcHalChanT + } +} + +/** + * @brief Initialize the HAL context and check if DWC_OTG is alive + * + * Entry: + * - The peripheral must have been reset and clock un-gated + * - The USB PHY (internal or external) and associated GPIOs must already be configured + * - GPIO pins configured + * - Interrupt allocated but DISABLED (in case of an unknown interrupt state) + * Exit: + * - Checks to see if DWC_OTG is alive, and if HW version/config is correct + * - HAL context initialized + * - Read and save relevant USB-DWC configuration parameters + * - Sets default values to some global and OTG registers (GAHBCFG and GUSBCFG) + * - Umask global interrupt signal + * - Put DWC_OTG into host mode. Require 25ms delay before this takes effect. + * - State -> USB_DWC_HAL_PORT_STATE_OTG + * - Interrupts cleared. Users can now enable their ISR + * + * @attention The user must allocate memory for channel handlers with + * `hal->channels.hdls = malloc(hal->constant_config.chan_num_total * sizeof(usb_dwc_hal_chan_t*))` + * @param[inout] hal Context of the HAL layer + * @param[in] port_id USB port ID + */ +// llgo:link (*UsbDwcHalContextT).UsbDwcHalInit C.usb_dwc_hal_init +func (recv_ *UsbDwcHalContextT) UsbDwcHalInit(port_id c.Int) { +} + +/** + * @brief Deinitialize the HAL context + * + * Entry: + * - All channels must be properly disabled, and any pending events handled + * Exit: + * - DWC_OTG global interrupt disabled + * - HAL context deinitialized + * + * @param hal Context of the HAL layer + */ +// llgo:link (*UsbDwcHalContextT).UsbDwcHalDeinit C.usb_dwc_hal_deinit +func (recv_ *UsbDwcHalContextT) UsbDwcHalDeinit() { +} + +/** + * @brief Issue a soft reset to the controller + * + * This should be called when the host port encounters an error event or has been disconnected. Before calling this, + * users are responsible for safely freeing all channels as a soft reset will wipe all host port and channel registers. + * This function will result in the host port being put back into same state as after calling usb_dwc_hal_init(). + * + * @note This has nothing to do with a USB bus reset. It simply resets the peripheral + * + * @param[in] hal Context of the HAL layer + */ +// llgo:link (*UsbDwcHalContextT).UsbDwcHalCoreSoftReset C.usb_dwc_hal_core_soft_reset +func (recv_ *UsbDwcHalContextT) UsbDwcHalCoreSoftReset() { +} + +/** + * @brief Set FIFO bias + * + * This function will set the sizes of each of the FIFOs (RX FIFO, Non-periodic TX FIFO, Periodic TX FIFO) and must be + * called at least once before allocating the channel. Based on the type of endpoints (and the endpoints' MPS), there + * may be situations where this function may need to be called again to resize the FIFOs. If resizing FIFOs dynamically, + * it is the user's responsibility to ensure there are no active channels when this function is called. + * + * @note After a port reset, the FIFO size registers will reset to their default values, so this function must be called + * again post reset. + * + * @param[in] hal Context of the HAL layer + * @param[in] fifo_bias FIFO bias configuration + */ +// llgo:link (*UsbDwcHalContextT).UsbDwcHalSetFifoBias C.usb_dwc_hal_set_fifo_bias +func (recv_ *UsbDwcHalContextT) UsbDwcHalSetFifoBias(fifo_bias UsbHalFifoBiasT) { +} + +/** + * @brief Get MPS limits + * + * @param[in] hal Context of the HAL layer + * @param[out] mps_limits MPS limits + */ +// llgo:link (*UsbDwcHalContextT).UsbDwcHalGetMpsLimits C.usb_dwc_hal_get_mps_limits +func (recv_ *UsbDwcHalContextT) UsbDwcHalGetMpsLimits(mps_limits *UsbHalFifoMpsLimitsT) { +} + +/** + * @brief Enable the host port + * + * Entry: + * - Host port enabled event triggered following a reset + * Exit: + * - Host port enabled to operate in scatter/gather DMA mode + * - DMA fifo sizes configured + * + * @param hal Context of the HAL layer + */ +// llgo:link (*UsbDwcHalContextT).UsbDwcHalPortEnable C.usb_dwc_hal_port_enable +func (recv_ *UsbDwcHalContextT) UsbDwcHalPortEnable() { +} + +/** + * @brief Allocate a channel + * + * @param[in] hal Context of the HAL layer + * @param[inout] chan_obj Empty channel object + * @param[in] chan_ctx Context variable for the allocator of the channel + * @return true Channel successfully allocated + * @return false Failed to allocate channel + */ +// llgo:link (*UsbDwcHalContextT).UsbDwcHalChanAlloc C.usb_dwc_hal_chan_alloc +func (recv_ *UsbDwcHalContextT) UsbDwcHalChanAlloc(chan_obj *UsbDwcHalChanT, chan_ctx c.Pointer) bool { + return false +} + +/** + * @brief Free a channel + * + * @param[in] hal Context of the HAL layer + * @param[in] chan_obj Channel object + */ +// llgo:link (*UsbDwcHalContextT).UsbDwcHalChanFree C.usb_dwc_hal_chan_free +func (recv_ *UsbDwcHalContextT) UsbDwcHalChanFree(chan_obj *UsbDwcHalChanT) { +} + +/** + * @brief Set the endpoint information for a particular channel + * + * This should be called when a channel switches target from one EP to another + * + * @note the channel must be in the disabled state in order to change its EP + * information + * + * @param hal Context of the HAL layer + * @param chan_obj Channel object + * @param ep_char Endpoint characteristics + */ +// llgo:link (*UsbDwcHalContextT).UsbDwcHalChanSetEpChar C.usb_dwc_hal_chan_set_ep_char +func (recv_ *UsbDwcHalContextT) UsbDwcHalChanSetEpChar(chan_obj *UsbDwcHalChanT, ep_char *UsbDwcHalEpCharT) { +} + +/** + * @brief Activate a channel + * + * Activating a channel will cause the channel to start executing transfer descriptors. + * + * @note This function should only be called on channels that were previously halted + * @note An event will be generated when the channel is halted + * + * @param chan_obj Channel object + * @param xfer_desc_list A filled transfer descriptor list + * @param desc_list_len Transfer descriptor list length + * @param start_idx Index of the starting transfer descriptor in the list + */ +// llgo:link (*UsbDwcHalChanT).UsbDwcHalChanActivate C.usb_dwc_hal_chan_activate +func (recv_ *UsbDwcHalChanT) UsbDwcHalChanActivate(xfer_desc_list c.Pointer, desc_list_len c.Int, start_idx c.Int) { +} + +/** + * @brief Request to halt a channel + * + * This function should be called in order to halt a channel. If the channel is already halted, this function will + * return true. If the channel is still active, this function will return false and users must wait for the + * USB_DWC_HAL_CHAN_EVENT_HALT_REQ event before treating the channel as halted. + * + * @note When a transfer is in progress (i.e., the channel is active) and a halt is requested, the channel will halt + * after the next USB packet is completed. If the transfer has more pending packets, the transfer will just be + * marked as USB_DWC_HAL_XFER_DESC_STS_NOT_EXECUTED. + * + * @param chan_obj Channel object + * @return true The channel is already halted + * @return false The halt was requested, wait for USB_DWC_HAL_CHAN_EVENT_HALT_REQ + */ +// llgo:link (*UsbDwcHalChanT).UsbDwcHalChanRequestHalt C.usb_dwc_hal_chan_request_halt +func (recv_ *UsbDwcHalChanT) UsbDwcHalChanRequestHalt() bool { + return false +} + +/** + * @brief Decode global and host port interrupts + * + * - Reads and clears global and host port interrupt registers + * - Decodes the interrupt bits to determine what host port event occurred + * + * @note This should be the first interrupt decode function to be run + * + * @param hal Context of the HAL layer + * @return usb_dwc_hal_port_event_t Host port event + */ +// llgo:link (*UsbDwcHalContextT).UsbDwcHalDecodeIntr C.usb_dwc_hal_decode_intr +func (recv_ *UsbDwcHalContextT) UsbDwcHalDecodeIntr() UsbDwcHalPortEventT { + return 0 +} + +/** + * @brief Gets the next channel with a pending interrupt + * + * If no channel is pending an interrupt, this function will return NULL. If one or more channels are pending an + * interrupt, this function returns one of the channel's objects. Call this function repeatedly until it returns NULL. + * + * @param hal Context of the HAL layer + * @return usb_dwc_hal_chan_t* Channel object. NULL if no channel are pending an interrupt. + */ +// llgo:link (*UsbDwcHalContextT).UsbDwcHalGetChanPendingIntr C.usb_dwc_hal_get_chan_pending_intr +func (recv_ *UsbDwcHalContextT) UsbDwcHalGetChanPendingIntr() *UsbDwcHalChanT { + return nil +} + +/** + * @brief Decode a particular channel's interrupt + * + * - Reads and clears the interrupt register of the channel + * - Returns the corresponding event for that channel + * + * @param chan_obj Channel object + * @note If the host port has an error (e.g., a sudden disconnect or an port error), any active channels will not + * receive an interrupt. Each active channel must be manually halted. + * @return usb_dwc_hal_chan_event_t Channel event + */ +// llgo:link (*UsbDwcHalChanT).UsbDwcHalChanDecodeIntr C.usb_dwc_hal_chan_decode_intr +func (recv_ *UsbDwcHalChanT) UsbDwcHalChanDecodeIntr() UsbDwcHalChanEventT { + return 0 +} diff --git a/esp32/usb_dwc_ll.go b/esp32/usb_dwc_ll.go new file mode 100644 index 00000000..c460d8b6 --- /dev/null +++ b/esp32/usb_dwc_ll.go @@ -0,0 +1,26 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const USB_DWC_QTD_LIST_MEM_ALIGN = 512 +const USB_DWC_FRAME_LIST_MEM_ALIGN = 512 +const USB_DWC_LL_QTD_STATUS_SUCCESS = 0x0 +const USB_DWC_LL_QTD_STATUS_PKTERR = 0x1 +const USB_DWC_LL_QTD_STATUS_BUFFER = 0x3 +const USB_DWC_LL_QTD_STATUS_NOT_EXECUTED = 0x4 + +/* + * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode. + * Each QTD describes one transfer. Scatter gather mode will automatically split + * a transfer into multiple MPS packets. Each QTD is 64bits in size + * + * Note: The status information part of the QTD is interpreted differently depending + * on IN or OUT, and ISO or non-ISO + */ + +type UsbDwcLlDmaQtdT struct { + Buffer *c.Uint8T +} diff --git a/esp32/usb_dwc_periph.go b/esp32/usb_dwc_periph.go new file mode 100644 index 00000000..204238ea --- /dev/null +++ b/esp32/usb_dwc_periph.go @@ -0,0 +1,114 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type UsbPhyInstT c.Int + +const ( + USB_PHY_INST_FSLS_INTERN_0 UsbPhyInstT = 1 + USB_PHY_INST_FSLS_INTERN_1 UsbPhyInstT = 2 + USB_PHY_INST_UTMI_0 UsbPhyInstT = 4 + USB_PHY_INST_EXTERN UsbPhyInstT = 8 +) + +/** + * @brief USB PHY FSLS Serial Interface Signals + * + * Structure to store the GPIO matrix signal indexes for a USB PHY FSLS Serial + * interface's signals. + * + * @note Refer to section "2.2.1.13 FsLsSerialMode" of the UTMI+ for more + * details regarding the FSLS Serial Interface. + */ + +type UsbFslsSerialSignalConnT struct { + RxDp c.Int + RxDm c.Int + RxRcv c.Int + SuspendN c.Int + TxEnableN c.Int + TxDp c.Int + TxDm c.Int + FsEdgeSel c.Int +} + +/** + * @brief USB PHY UTMI OTG Interface Signal Index Type + * + * Structure to store the GPIO matrix signal indexes for a UTMI PHY interface's + * OTG signals. + */ + +type UsbOtgSignalConnT struct { + Iddig c.Int + Avalid c.Int + Bvalid c.Int + Vbusvalid c.Int + Sessend c.Int + Idpullup c.Int + Dppulldown c.Int + Dmpulldown c.Int + Drvvbus c.Int + Chrgvbus c.Int + Dischrgvbus c.Int +} + +/** + * @brief Internal USB PHY IO + * + * Structure to store the IO numbers for a particular internal USB PHY + */ + +type UsbInternalPhyIoT struct { + Dp c.Int + Dm c.Int +} + +/** + * @brief USB Controller Information + * + * Structure to store information for all USB-DWC instances + * + * For targets with multiple USB controllers, we support only fixed mapping of the PHYs. + * This is a software limitation; the hardware supports swapping Controllers and PHYs. + */ + +type UsbDwcInfoT struct { + Controllers [1]struct { + FslsSignals *UsbFslsSerialSignalConnT + OtgSignals *UsbOtgSignalConnT + InternalPhyIo *UsbInternalPhyIoT + SupportedPhys UsbPhyInstT + Irq c.Int + Irq2ndCpu c.Int + } +} + +/* +Stores a bunch of USB-peripheral data. +*/ +type UsbPhySignalConnT struct { + ExtphyVpIn c.Uint8T + ExtphyVmIn c.Uint8T + ExtphyRcvIn c.Uint8T + ExtphyOenOut c.Uint8T + ExtphyVpoOut c.Uint8T + ExtphyVmoOut c.Uint8T + ExtphySuspendIn c.Uint8T + ExtphySpeedIn c.Uint8T + SrpBvalidIn c.Uint8T + SrpSessendIn c.Uint8T + SrpChrgvbusOut c.Uint8T + SrpDischrgvbusOut c.Uint8T + OtgIddigIn c.Uint8T + OtgAvalidIn c.Uint8T + OtgVbusvalidIn c.Uint8T + OtgIdpullupOut c.Uint8T + OtgDppulldownOut c.Uint8T + OtgDmpulldownOut c.Uint8T + OtgDrvvbusOut c.Uint8T + Module PeriphModuleT +} diff --git a/esp32/usb_dwc_struct.go b/esp32/usb_dwc_struct.go new file mode 100644 index 00000000..f42012fc --- /dev/null +++ b/esp32/usb_dwc_struct.go @@ -0,0 +1,408 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* ---------------------------- Register Types ------------------------------ */ + +type UsbDwcGotgctlRegT struct { + Val c.Uint32T +} + +type UsbDwcGotgintRegT struct { + Val c.Uint32T +} + +type UsbDwcGahbcfgRegT struct { + Val c.Uint32T +} + +type UsbDwcGusbcfgRegT struct { + Val c.Uint32T +} + +type UsbDwcGrstctlRegT struct { + Val c.Uint32T +} + +type UsbDwcGintstsRegT struct { + Val c.Uint32T +} + +type UsbDwcGintmskRegT struct { + Val c.Uint32T +} + +type UsbDwcGrxstsrRegT struct { + Val c.Uint32T +} + +type UsbDwcGrxstspRegT struct { + Val c.Uint32T +} + +type UsbDwcGrxfsizRegT struct { + Val c.Uint32T +} + +type UsbDwcGnptxfsizRegT struct { + Val c.Uint32T +} + +type UsbDwcGnptxstsRegT struct { + Val c.Uint32T +} + +type UsbDwcGsnpsidRegT struct { + Val c.Uint32T +} + +type UsbDwcGhwcfg1RegT struct { + Val c.Uint32T +} + +type UsbDwcGhwcfg2RegT struct { + Val c.Uint32T +} + +type UsbDwcGhwcfg3RegT struct { + Val c.Uint32T +} + +type UsbDwcGhwcfg4RegT struct { + Val c.Uint32T +} + +type UsbDwcGdfifocfgRegT struct { + Val c.Uint32T +} + +type UsbDwcHptxfsizRegT struct { + Val c.Uint32T +} + +type UsbDwcDieptxfiRegT struct { + Val c.Uint32T +} + +type UsbDwcHcfgRegT struct { + Val c.Uint32T +} + +type UsbDwcHfirRegT struct { + Val c.Uint32T +} + +type UsbDwcHfnumRegT struct { + Val c.Uint32T +} + +type UsbDwcHptxstsRegT struct { + Val c.Uint32T +} + +type UsbDwcHaintRegT struct { + Val c.Uint32T +} + +type UsbDwcHaintmskRegT struct { + Val c.Uint32T +} + +type UsbDwcHflbaddrRegT struct { + Val c.Uint32T +} + +type UsbDwcHprtRegT struct { + Val c.Uint32T +} + +type UsbDwcHccharRegT struct { + Val c.Uint32T +} + +type UsbDwcHcintRegT struct { + Val c.Uint32T +} + +type UsbDwcHcintmskRegT struct { + Val c.Uint32T +} + +type UsbDwcHctsizRegT struct { + Val c.Uint32T +} + +type UsbDwcHcdmaRegT struct { + Val c.Uint32T +} + +type UsbDwcHcdmabRegT struct { + Val c.Uint32T +} + +type UsbDwcDcfgRegT struct { + Val c.Uint32T +} + +type UsbDwcDctlRegT struct { + Val c.Uint32T +} + +type UsbDwcDstsRegT struct { + Val c.Uint32T +} + +type UsbDwcDiepmskRegT struct { + Val c.Uint32T +} + +type UsbDwcDoepmskRegT struct { + Val c.Uint32T +} + +type UsbDwcDaintRegT struct { + Val c.Uint32T +} + +type UsbDwcDaintmskRegT struct { + Val c.Uint32T +} + +type UsbDwcDvbusdisRegT struct { + Val c.Uint32T +} + +type UsbDwcDvbuspulseRegT struct { + Val c.Uint32T +} + +type UsbDwcDthrctlRegT struct { + Val c.Uint32T +} + +type UsbDwcDiepempmskRegT struct { + Val c.Uint32T +} + +type UsbDwcDiepctl0RegT struct { + Val c.Uint32T +} + +type UsbDwcDiepint0RegT struct { + Val c.Uint32T +} + +type UsbDwcDieptsiz0RegT struct { + Val c.Uint32T +} + +type UsbDwcDiepdma0RegT struct { + Val c.Uint32T +} + +type UsbDwcDtxfsts0RegT struct { + Val c.Uint32T +} + +type UsbDwcDiepdmab0RegT struct { + Val c.Uint32T +} + +type UsbDwcDiepctlRegT struct { + Val c.Uint32T +} + +type UsbDwcDiepintRegT struct { + Val c.Uint32T +} + +type UsbDwcDieptsizRegT struct { + Val c.Uint32T +} + +type UsbDwcDiepdmaRegT struct { + Val c.Uint32T +} + +type UsbDwcDtxfstsRegT struct { + Val c.Uint32T +} + +type UsbDwcDiepdmabRegT struct { + Val c.Uint32T +} + +type UsbDwcDoepctl0RegT struct { + Val c.Uint32T +} + +type UsbDwcDoepint0RegT struct { + Val c.Uint32T +} + +type UsbDwcDoeptsiz0RegT struct { + Val c.Uint32T +} + +type UsbDwcDoepdma0RegT struct { + Val c.Uint32T +} + +type UsbDwcDoepdmab0RegT struct { + Val c.Uint32T +} + +type UsbDwcDoepctlRegT struct { + Val c.Uint32T +} + +type UsbDwcDoepintRegT struct { + Val c.Uint32T +} + +type UsbDwcDoeptsizRegT struct { + Val c.Uint32T +} + +type UsbDwcDoepdmaRegT struct { + Val c.Uint32T +} + +type UsbDwcDoepdmabRegT struct { + Val c.Uint32T +} + +type UsbDwcPcgcctlRegT struct { + Val c.Uint32T +} + +/* --------------------------- Register Groups ------------------------------ */ + +type UsbDwcHostChanRegsT struct { + HccharReg UsbDwcHccharRegT + Reserved0x04 [1]c.Uint32T + HcintReg UsbDwcHcintRegT + HcintmskReg UsbDwcHcintmskRegT + HctsizReg UsbDwcHctsizRegT + HcdmaReg UsbDwcHcdmaRegT + Reserved0x18 [1]c.Uint32T + HcdmabReg UsbDwcHcdmabRegT +} + +type UsbDwcInEpRegsT struct { + DiepctlReg UsbDwcDiepctlRegT + Reserved0x04 [1]c.Uint32T + DiepintReg UsbDwcDiepintRegT + Reserved0x0c [1]c.Uint32T + DieptsizReg UsbDwcDieptsizRegT + DiepdmaReg UsbDwcDiepdmaRegT + DtxfstsReg UsbDwcDtxfstsRegT + DiepdmabReg UsbDwcDiepdmabRegT +} + +type UsbDwcOutEpRegsT struct { + DoepctlReg UsbDwcDoepctlRegT + Reserved0x04 [1]c.Uint32T + DoepintReg UsbDwcDoepintRegT + Reserved0x0c [1]c.Uint32T + DoeptsizReg UsbDwcDoeptsizRegT + DoepdmaReg UsbDwcDoepdmaRegT + Reserved0x18 [1]c.Uint32T + DoepdmabReg UsbDwcDoepdmabRegT +} + +/* --------------------------- Register Layout ------------------------------ */ + +type UsbDwcDevT struct { + GotgctlReg UsbDwcGotgctlRegT + GotgintReg UsbDwcGotgintRegT + GahbcfgReg UsbDwcGahbcfgRegT + GusbcfgReg UsbDwcGusbcfgRegT + GrstctlReg UsbDwcGrstctlRegT + GintstsReg UsbDwcGintstsRegT + GintmskReg UsbDwcGintmskRegT + GrxstsrReg UsbDwcGrxstsrRegT + GrxstspReg UsbDwcGrxstspRegT + GrxfsizReg UsbDwcGrxfsizRegT + GnptxfsizReg UsbDwcGnptxfsizRegT + GnptxstsReg UsbDwcGnptxstsRegT + Reserved0x0030 c.Uint32T + Reserved0x0034 c.Uint32T + Reserved0x0038 c.Uint32T + Reserved0x003c c.Uint32T + GsnpsidReg UsbDwcGsnpsidRegT + Ghwcfg1Reg UsbDwcGhwcfg1RegT + Ghwcfg2Reg UsbDwcGhwcfg2RegT + Ghwcfg3Reg UsbDwcGhwcfg3RegT + Ghwcfg4Reg UsbDwcGhwcfg4RegT + Reserved0x0054 c.Uint32T + Reserved0x0058 c.Uint32T + GdfifocfgReg UsbDwcGdfifocfgRegT + Reserved0x0060 c.Uint32T + Reserved0x00640x0100 [39]c.Uint32T + HptxfsizReg UsbDwcHptxfsizRegT + DieptxfRegs [4]UsbDwcDieptxfiRegT + Reserved0x01140x013c [11]UsbDwcDieptxfiRegT + Reserved0x1400x3fc [176]c.Uint32T + HcfgReg UsbDwcHcfgRegT + HfirReg UsbDwcHfirRegT + HfnumReg UsbDwcHfnumRegT + Reserved0x40c [1]c.Uint32T + HptxstsReg UsbDwcHptxstsRegT + HaintReg UsbDwcHaintRegT + HaintmskReg UsbDwcHaintmskRegT + HflbaddrReg UsbDwcHflbaddrRegT + Reserved0x4200x43c [8]c.Uint32T + HprtReg UsbDwcHprtRegT + Reserved0x04440x04fc [47]c.Uint32T + HostChans [8]UsbDwcHostChanRegsT + Reserved0x06000x06fc [8]UsbDwcHostChanRegsT + Reserved0x07000x07fc [64]c.Uint32T + DcfgReg UsbDwcDcfgRegT + DctlReg UsbDwcDctlRegT + DstsReg UsbDwcDstsRegT + Reserved0x080c [1]c.Uint32T + DiepmskReg UsbDwcDiepmskRegT + DoepmskReg UsbDwcDoepmskRegT + DaintReg UsbDwcDaintRegT + DaintmskReg UsbDwcDaintmskRegT + Reserved0x0820 c.Uint32T + Reserved0x0824 c.Uint32T + DvbusdisReg UsbDwcDvbusdisRegT + DvbuspulseReg UsbDwcDvbuspulseRegT + DthrctlReg UsbDwcDthrctlRegT + DiepempmskReg UsbDwcDiepempmskRegT + Reserved0x0838 c.Uint32T + Reserved0x083c c.Uint32T + Reserved0x0840 c.Uint32T + Reserved0x08440x087c [15]c.Uint32T + Reserved0x0880 c.Uint32T + Reserved0x08840x08c0 [15]c.Uint32T + Reserved0x08c40x08fc [16]c.Uint32T + Diepctl0Reg UsbDwcDiepctl0RegT + Reserved0x0904 [1]c.Uint32T + Diepint0Reg UsbDwcDiepint0RegT + Reserved0x090c [1]c.Uint32T + Dieptsiz0Reg UsbDwcDieptsiz0RegT + Diepdma0Reg UsbDwcDiepdma0RegT + Dtxfsts0Reg UsbDwcDtxfsts0RegT + Diepdmab0Reg UsbDwcDiepdmab0RegT + InEps [6]UsbDwcInEpRegsT + Reserved0x09e00x0afc [9]UsbDwcInEpRegsT + Doepctl0Reg UsbDwcDoepctl0RegT + Reserved0x0b04 [1]c.Uint32T + Doepint0Reg UsbDwcDoepint0RegT + Reserved0x0b0c [1]c.Uint32T + Doeptsiz0Reg UsbDwcDoeptsiz0RegT + Doepdma0Reg UsbDwcDoepdma0RegT + Reserved0x0b18 [1]c.Uint32T + Doepdmab0Reg UsbDwcDoepdmab0RegT + OutEps [6]UsbDwcOutEpRegsT + Reserved0x0be00x0d00 [9]UsbDwcOutEpRegsT + Reserved0x0d000x0dfc [64]c.Uint32T + PcgcctlReg UsbDwcPcgcctlRegT + Reserved0x0e04 [1]c.Uint32T +} diff --git a/esp32/usb_dwc_types.go b/esp32/usb_dwc_types.go new file mode 100644 index 00000000..f8af65a4 --- /dev/null +++ b/esp32/usb_dwc_types.go @@ -0,0 +1,32 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type UsbDwcSpeedT c.Int + +const ( + USB_DWC_SPEED_HIGH UsbDwcSpeedT = 0 + USB_DWC_SPEED_FULL UsbDwcSpeedT = 1 + USB_DWC_SPEED_LOW UsbDwcSpeedT = 2 +) + +type UsbDwcXferTypeT c.Int + +const ( + USB_DWC_XFER_TYPE_CTRL UsbDwcXferTypeT = 0 + USB_DWC_XFER_TYPE_ISOCHRONOUS UsbDwcXferTypeT = 1 + USB_DWC_XFER_TYPE_BULK UsbDwcXferTypeT = 2 + USB_DWC_XFER_TYPE_INTR UsbDwcXferTypeT = 3 +) + +type UsbHalFrameListLenT c.Int + +const ( + USB_HAL_FRAME_LIST_LEN_8 UsbHalFrameListLenT = 8 + USB_HAL_FRAME_LIST_LEN_16 UsbHalFrameListLenT = 16 + USB_HAL_FRAME_LIST_LEN_32 UsbHalFrameListLenT = 32 + USB_HAL_FRAME_LIST_LEN_64 UsbHalFrameListLenT = 64 +) diff --git a/esp32/usb_os_glue.go b/esp32/usb_os_glue.go new file mode 100644 index 00000000..40c43094 --- /dev/null +++ b/esp32/usb_os_glue.go @@ -0,0 +1,18 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:type C +type UsbOsglueIntdisenaRoutineT func() + +// llgo:type C +type UsbOsglueWaitRoutineT func(c.Int) c.Int + +type UsbOsglueDataT struct { + IntDisProc UsbOsglueIntdisenaRoutineT + IntEnaProc UsbOsglueIntdisenaRoutineT + WaitProc UsbOsglueWaitRoutineT +} diff --git a/esp32/usb_periph.go b/esp32/usb_periph.go new file mode 100644 index 00000000..c9deb67e --- /dev/null +++ b/esp32/usb_periph.go @@ -0,0 +1,23 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief A pin descriptor for init (DEPRECATED) + * + * Todo: Remove in IDF v6.0 (IDF-9029) + * + * @note These IO pins are deprecated. When connecting USB OTG to an external + * FSLS PHY, the FSLS Serial Interface signals can be routed to any GPIO via the + * GPI0 matrix. Thus, this mapping of signals to IO pins is meaningless. + */ + +type UsbIopinDscT struct { + Pin c.Int + Func c.Int + IsOutput bool + ExtPhyOnly c.Int +} diff --git a/esp32/usb_persist.go b/esp32/usb_persist.go new file mode 100644 index 00000000..78d0610e --- /dev/null +++ b/esp32/usb_persist.go @@ -0,0 +1,17 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const USBDC_TESTAMENT_LOC_MASK = 0x7FFFF + +// The testament is a FIFO. The ROM will output all data between textstart and textend; if textend is lower than textstart it will +// output everything from textstart to memend, then memstart to textend. +type UsbdcTestamentT struct { + Memstart *c.Char + Memend *c.Char + Textstart *c.Char + Textend *c.Char +} diff --git a/esp32/usb_phy_types.go b/esp32/usb_phy_types.go new file mode 100644 index 00000000..e635ea7b --- /dev/null +++ b/esp32/usb_phy_types.go @@ -0,0 +1,42 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type UsbPhyTargetT c.Int + +const ( + USB_PHY_TARGET_INT UsbPhyTargetT = 0 + USB_PHY_TARGET_UTMI UsbPhyTargetT = 1 + USB_PHY_TARGET_EXT UsbPhyTargetT = 2 + USB_PHY_TARGET_MAX UsbPhyTargetT = 3 +) + +type UsbPhyControllerT c.Int + +const ( + USB_PHY_CTRL_OTG UsbPhyControllerT = 0 + USB_PHY_CTRL_SERIAL_JTAG UsbPhyControllerT = 1 + USB_PHY_CTRL_MAX UsbPhyControllerT = 2 +) + +type UsbOtgModeT c.Int + +const ( + USB_PHY_MODE_DEFAULT UsbOtgModeT = 0 + USB_OTG_MODE_HOST UsbOtgModeT = 1 + USB_OTG_MODE_DEVICE UsbOtgModeT = 2 + USB_OTG_MODE_MAX UsbOtgModeT = 3 +) + +type UsbPhySpeedT c.Int + +const ( + USB_PHY_SPEED_UNDEFINED UsbPhySpeedT = 0 + USB_PHY_SPEED_LOW UsbPhySpeedT = 1 + USB_PHY_SPEED_FULL UsbPhySpeedT = 2 + USB_PHY_SPEED_HIGH UsbPhySpeedT = 3 + USB_PHY_SPEED_MAX UsbPhySpeedT = 4 +) diff --git a/esp32/usb_pins.go b/esp32/usb_pins.go new file mode 100644 index 00000000..4816c4e1 --- /dev/null +++ b/esp32/usb_pins.go @@ -0,0 +1,12 @@ +package freertos + +import _ "unsafe" + +const USBPHY_VP_NUM = 42 +const USBPHY_VM_NUM = 41 +const USBPHY_RCV_NUM = 21 +const USBPHY_OEN_NUM = 40 +const USBPHY_VPO_NUM = 39 +const USBPHY_VMO_NUM = 38 +const USBPHY_DP_NUM = 20 +const USBPHY_DM_NUM = 19 diff --git a/esp32/usb_reg.go b/esp32/usb_reg.go new file mode 100644 index 00000000..62bd703c --- /dev/null +++ b/esp32/usb_reg.go @@ -0,0 +1,2428 @@ +package freertos + +import _ "unsafe" + +const USB_SESREQSCS_V = 0x00000001 +const USB_SESREQSCS_S = 0 +const USB_SESREQ_V = 0x00000001 +const USB_SESREQ_S = 1 +const USB_VBVALIDOVEN_V = 0x00000001 +const USB_VBVALIDOVEN_S = 2 +const USB_VBVALIDOVVAL_V = 0x00000001 +const USB_VBVALIDOVVAL_S = 3 +const USB_AVALIDOVEN_V = 0x00000001 +const USB_AVALIDOVEN_S = 4 +const USB_AVALIDOVVAL_V = 0x00000001 +const USB_AVALIDOVVAL_S = 5 +const USB_BVALIDOVEN_V = 0x00000001 +const USB_BVALIDOVEN_S = 6 +const USB_BVALIDOVVAL_V = 0x00000001 +const USB_BVALIDOVVAL_S = 7 +const USB_HSTNEGSCS_V = 0x00000001 +const USB_HSTNEGSCS_S = 8 +const USB_HNPREQ_V = 0x00000001 +const USB_HNPREQ_S = 9 +const USB_HSTSETHNPEN_V = 0x00000001 +const USB_HSTSETHNPEN_S = 10 +const USB_DEVHNPEN_V = 0x00000001 +const USB_DEVHNPEN_S = 11 +const USB_EHEN_V = 0x00000001 +const USB_EHEN_S = 12 +const USB_DBNCEFLTRBYPASS_V = 0x00000001 +const USB_DBNCEFLTRBYPASS_S = 15 +const USB_CONIDSTS_V = 0x00000001 +const USB_CONIDSTS_S = 16 +const USB_DBNCTIME_V = 0x00000001 +const USB_DBNCTIME_S = 17 +const USB_ASESVLD_V = 0x00000001 +const USB_ASESVLD_S = 18 +const USB_BSESVLD_V = 0x00000001 +const USB_BSESVLD_S = 19 +const USB_OTGVER_V = 0x00000001 +const USB_OTGVER_S = 20 +const USB_CURMOD_V = 0x00000001 +const USB_CURMOD_S = 21 +const USB_GDFIFOCFG = 0x0000FFFF +const USB_GDFIFOCFG_V = 0x0000FFFF +const USB_GDFIFOCFG_S = 0 +const USB_EPINFOBASEADDR = 0x0000FFFF +const USB_EPINFOBASEADDR_V = 0x0000FFFF +const USB_EPINFOBASEADDR_S = 16 +const USB_PTXFSTADDR = 0x0000FFFF +const USB_PTXFSTADDR_V = 0x0000FFFF +const USB_PTXFSTADDR_S = 0 +const USB_PTXFSIZE = 0x0000FFFF +const USB_PTXFSIZE_V = 0x0000FFFF +const USB_PTXFSIZE_S = 16 +const USB_INEP1TXFSTADDR = 0x0000FFFF +const USB_INEP1TXFSTADDR_V = 0x0000FFFF +const USB_INEP1TXFSTADDR_S = 0 +const USB_INEP1TXFDEP = 0x0000FFFF +const USB_INEP1TXFDEP_V = 0x0000FFFF +const USB_INEP1TXFDEP_S = 16 +const USB_INEP2TXFSTADDR = 0x0000FFFF +const USB_INEP2TXFSTADDR_V = 0x0000FFFF +const USB_INEP2TXFSTADDR_S = 0 +const USB_INEP2TXFDEP = 0x0000FFFF +const USB_INEP2TXFDEP_V = 0x0000FFFF +const USB_INEP2TXFDEP_S = 16 +const USB_INEP3TXFSTADDR = 0x0000FFFF +const USB_INEP3TXFSTADDR_V = 0x0000FFFF +const USB_INEP3TXFSTADDR_S = 0 +const USB_INEP3TXFDEP = 0x0000FFFF +const USB_INEP3TXFDEP_V = 0x0000FFFF +const USB_INEP3TXFDEP_S = 16 +const USB_INEP4TXFSTADDR = 0x0000FFFF +const USB_INEP4TXFSTADDR_V = 0x0000FFFF +const USB_INEP4TXFSTADDR_S = 0 +const USB_INEP4TXFDEP = 0x0000FFFF +const USB_INEP4TXFDEP_V = 0x0000FFFF +const USB_INEP4TXFDEP_S = 16 +const USB_H_FSLSPCLKSEL = 0x00000003 +const USB_H_FSLSPCLKSEL_V = 0x00000003 +const USB_H_FSLSPCLKSEL_S = 0 +const USB_H_FSLSSUPP_V = 0x00000001 +const USB_H_FSLSSUPP_S = 2 +const USB_H_ENA32KHZS_V = 0x00000001 +const USB_H_ENA32KHZS_S = 7 +const USB_H_DESCDMA_V = 0x00000001 +const USB_H_DESCDMA_S = 23 +const USB_H_FRLISTEN = 0x00000003 +const USB_H_FRLISTEN_V = 0x00000003 +const USB_H_FRLISTEN_S = 24 +const USB_H_PERSCHEDENA_V = 0x00000001 +const USB_H_PERSCHEDENA_S = 26 +const USB_H_MODECHTIMEN_V = 0x00000001 +const USB_H_MODECHTIMEN_S = 31 +const USB_FRINT = 0x0000FFFF +const USB_FRINT_V = 0x0000FFFF +const USB_FRINT_S = 0 +const USB_HFIRRLDCTRL_V = 0x00000001 +const USB_HFIRRLDCTRL_S = 16 +const USB_HFLBADDR = 0xFFFFFFFF +const USB_HFLBADDR_V = 0xFFFFFFFF +const USB_HFLBADDR_S = 0 +const USB_PRTCONNSTS_V = 0x00000001 +const USB_PRTCONNSTS_S = 0 +const USB_PRTCONNDET_V = 0x00000001 +const USB_PRTCONNDET_S = 1 +const USB_PRTENA_V = 0x00000001 +const USB_PRTENA_S = 2 +const USB_PRTENCHNG_V = 0x00000001 +const USB_PRTENCHNG_S = 3 +const USB_PRTOVRCURRACT_V = 0x00000001 +const USB_PRTOVRCURRACT_S = 4 +const USB_PRTOVRCURRCHNG_V = 0x00000001 +const USB_PRTOVRCURRCHNG_S = 5 +const USB_PRTRES_V = 0x00000001 +const USB_PRTRES_S = 6 +const USB_PRTSUSP_V = 0x00000001 +const USB_PRTSUSP_S = 7 +const USB_PRTRST_V = 0x00000001 +const USB_PRTRST_S = 8 +const USB_PRTLNSTS = 0x00000003 +const USB_PRTLNSTS_V = 0x00000003 +const USB_PRTLNSTS_S = 10 +const USB_PRTPWR_V = 0x00000001 +const USB_PRTPWR_S = 12 +const USB_PRTTSTCTL = 0x0000000F +const USB_PRTTSTCTL_V = 0x0000000F +const USB_PRTTSTCTL_S = 13 +const USB_PRTSPD = 0x00000003 +const USB_PRTSPD_V = 0x00000003 +const USB_PRTSPD_S = 17 +const USB_H_MPS0 = 0x000007FF +const USB_H_MPS0_V = 0x000007FF +const USB_H_MPS0_S = 0 +const USB_H_EPNUM0 = 0x0000000F +const USB_H_EPNUM0_V = 0x0000000F +const USB_H_EPNUM0_S = 11 +const USB_H_EPDIR0_V = 0x00000001 +const USB_H_EPDIR0_S = 15 +const USB_H_LSPDDEV0_V = 0x00000001 +const USB_H_LSPDDEV0_S = 17 +const USB_H_EPTYPE0 = 0x00000003 +const USB_H_EPTYPE0_V = 0x00000003 +const USB_H_EPTYPE0_S = 18 +const USB_H_EC0_V = 0x00000001 +const USB_H_EC0_S = 21 +const USB_H_DEVADDR0 = 0x0000007F +const USB_H_DEVADDR0_V = 0x0000007F +const USB_H_DEVADDR0_S = 22 +const USB_H_ODDFRM0_V = 0x00000001 +const USB_H_ODDFRM0_S = 29 +const USB_H_CHDIS0_V = 0x00000001 +const USB_H_CHDIS0_S = 30 +const USB_H_CHENA0_V = 0x00000001 +const USB_H_CHENA0_S = 31 +const USB_H_DMAADDR0 = 0xFFFFFFFF +const USB_H_DMAADDR0_V = 0xFFFFFFFF +const USB_H_DMAADDR0_S = 0 +const USB_H_MPS1 = 0x000007FF +const USB_H_MPS1_V = 0x000007FF +const USB_H_MPS1_S = 0 +const USB_H_EPNUM1 = 0x0000000F +const USB_H_EPNUM1_V = 0x0000000F +const USB_H_EPNUM1_S = 11 +const USB_H_EPDIR1_V = 0x00000001 +const USB_H_EPDIR1_S = 15 +const USB_H_LSPDDEV1_V = 0x00000001 +const USB_H_LSPDDEV1_S = 17 +const USB_H_EPTYPE1 = 0x00000003 +const USB_H_EPTYPE1_V = 0x00000003 +const USB_H_EPTYPE1_S = 18 +const USB_H_EC1_V = 0x00000001 +const USB_H_EC1_S = 21 +const USB_H_DEVADDR1 = 0x0000007F +const USB_H_DEVADDR1_V = 0x0000007F +const USB_H_DEVADDR1_S = 22 +const USB_H_ODDFRM1_V = 0x00000001 +const USB_H_ODDFRM1_S = 29 +const USB_H_CHDIS1_V = 0x00000001 +const USB_H_CHDIS1_S = 30 +const USB_H_CHENA1_V = 0x00000001 +const USB_H_CHENA1_S = 31 +const USB_H_DMAADDR1 = 0xFFFFFFFF +const USB_H_DMAADDR1_V = 0xFFFFFFFF +const USB_H_DMAADDR1_S = 0 +const USB_H_MPS2 = 0x000007FF +const USB_H_MPS2_V = 0x000007FF +const USB_H_MPS2_S = 0 +const USB_H_EPNUM2 = 0x0000000F +const USB_H_EPNUM2_V = 0x0000000F +const USB_H_EPNUM2_S = 11 +const USB_H_EPDIR2_V = 0x00000001 +const USB_H_EPDIR2_S = 15 +const USB_H_LSPDDEV2_V = 0x00000001 +const USB_H_LSPDDEV2_S = 17 +const USB_H_EPTYPE2 = 0x00000003 +const USB_H_EPTYPE2_V = 0x00000003 +const USB_H_EPTYPE2_S = 18 +const USB_H_EC2_V = 0x00000001 +const USB_H_EC2_S = 21 +const USB_H_DEVADDR2 = 0x0000007F +const USB_H_DEVADDR2_V = 0x0000007F +const USB_H_DEVADDR2_S = 22 +const USB_H_ODDFRM2_V = 0x00000001 +const USB_H_ODDFRM2_S = 29 +const USB_H_CHDIS2_V = 0x00000001 +const USB_H_CHDIS2_S = 30 +const USB_H_CHENA2_V = 0x00000001 +const USB_H_CHENA2_S = 31 +const USB_H_DMAADDR2 = 0xFFFFFFFF +const USB_H_DMAADDR2_V = 0xFFFFFFFF +const USB_H_DMAADDR2_S = 0 +const USB_H_MPS3 = 0x000007FF +const USB_H_MPS3_V = 0x000007FF +const USB_H_MPS3_S = 0 +const USB_H_EPNUM3 = 0x0000000F +const USB_H_EPNUM3_V = 0x0000000F +const USB_H_EPNUM3_S = 11 +const USB_H_EPDIR3_V = 0x00000001 +const USB_H_EPDIR3_S = 15 +const USB_H_LSPDDEV3_V = 0x00000001 +const USB_H_LSPDDEV3_S = 17 +const USB_H_EPTYPE3 = 0x00000003 +const USB_H_EPTYPE3_V = 0x00000003 +const USB_H_EPTYPE3_S = 18 +const USB_H_EC3_V = 0x00000001 +const USB_H_EC3_S = 21 +const USB_H_DEVADDR3 = 0x0000007F +const USB_H_DEVADDR3_V = 0x0000007F +const USB_H_DEVADDR3_S = 22 +const USB_H_ODDFRM3_V = 0x00000001 +const USB_H_ODDFRM3_S = 29 +const USB_H_CHDIS3_V = 0x00000001 +const USB_H_CHDIS3_S = 30 +const USB_H_CHENA3_V = 0x00000001 +const USB_H_CHENA3_S = 31 +const USB_H_DMAADDR3 = 0xFFFFFFFF +const USB_H_DMAADDR3_V = 0xFFFFFFFF +const USB_H_DMAADDR3_S = 0 +const USB_H_MPS4 = 0x000007FF +const USB_H_MPS4_V = 0x000007FF +const USB_H_MPS4_S = 0 +const USB_H_EPNUM4 = 0x0000000F +const USB_H_EPNUM4_V = 0x0000000F +const USB_H_EPNUM4_S = 11 +const USB_H_EPDIR4_V = 0x00000001 +const USB_H_EPDIR4_S = 15 +const USB_H_LSPDDEV4_V = 0x00000001 +const USB_H_LSPDDEV4_S = 17 +const USB_H_EPTYPE4 = 0x00000003 +const USB_H_EPTYPE4_V = 0x00000003 +const USB_H_EPTYPE4_S = 18 +const USB_H_EC4_V = 0x00000001 +const USB_H_EC4_S = 21 +const USB_H_DEVADDR4 = 0x0000007F +const USB_H_DEVADDR4_V = 0x0000007F +const USB_H_DEVADDR4_S = 22 +const USB_H_ODDFRM4_V = 0x00000001 +const USB_H_ODDFRM4_S = 29 +const USB_H_CHDIS4_V = 0x00000001 +const USB_H_CHDIS4_S = 30 +const USB_H_CHENA4_V = 0x00000001 +const USB_H_CHENA4_S = 31 +const USB_H_DMAADDR4 = 0xFFFFFFFF +const USB_H_DMAADDR4_V = 0xFFFFFFFF +const USB_H_DMAADDR4_S = 0 +const USB_H_MPS5 = 0x000007FF +const USB_H_MPS5_V = 0x000007FF +const USB_H_MPS5_S = 0 +const USB_H_EPNUM5 = 0x0000000F +const USB_H_EPNUM5_V = 0x0000000F +const USB_H_EPNUM5_S = 11 +const USB_H_EPDIR5_V = 0x00000001 +const USB_H_EPDIR5_S = 15 +const USB_H_LSPDDEV5_V = 0x00000001 +const USB_H_LSPDDEV5_S = 17 +const USB_H_EPTYPE5 = 0x00000003 +const USB_H_EPTYPE5_V = 0x00000003 +const USB_H_EPTYPE5_S = 18 +const USB_H_EC5_V = 0x00000001 +const USB_H_EC5_S = 21 +const USB_H_DEVADDR5 = 0x0000007F +const USB_H_DEVADDR5_V = 0x0000007F +const USB_H_DEVADDR5_S = 22 +const USB_H_ODDFRM5_V = 0x00000001 +const USB_H_ODDFRM5_S = 29 +const USB_H_CHDIS5_V = 0x00000001 +const USB_H_CHDIS5_S = 30 +const USB_H_CHENA5_V = 0x00000001 +const USB_H_CHENA5_S = 31 +const USB_H_DMAADDR5 = 0xFFFFFFFF +const USB_H_DMAADDR5_V = 0xFFFFFFFF +const USB_H_DMAADDR5_S = 0 +const USB_H_MPS6 = 0x000007FF +const USB_H_MPS6_V = 0x000007FF +const USB_H_MPS6_S = 0 +const USB_H_EPNUM6 = 0x0000000F +const USB_H_EPNUM6_V = 0x0000000F +const USB_H_EPNUM6_S = 11 +const USB_H_EPDIR6_V = 0x00000001 +const USB_H_EPDIR6_S = 15 +const USB_H_LSPDDEV6_V = 0x00000001 +const USB_H_LSPDDEV6_S = 17 +const USB_H_EPTYPE6 = 0x00000003 +const USB_H_EPTYPE6_V = 0x00000003 +const USB_H_EPTYPE6_S = 18 +const USB_H_EC6_V = 0x00000001 +const USB_H_EC6_S = 21 +const USB_H_DEVADDR6 = 0x0000007F +const USB_H_DEVADDR6_V = 0x0000007F +const USB_H_DEVADDR6_S = 22 +const USB_H_ODDFRM6_V = 0x00000001 +const USB_H_ODDFRM6_S = 29 +const USB_H_CHDIS6_V = 0x00000001 +const USB_H_CHDIS6_S = 30 +const USB_H_CHENA6_V = 0x00000001 +const USB_H_CHENA6_S = 31 +const USB_H_DMAADDR6 = 0xFFFFFFFF +const USB_H_DMAADDR6_V = 0xFFFFFFFF +const USB_H_DMAADDR6_S = 0 +const USB_H_MPS7 = 0x000007FF +const USB_H_MPS7_V = 0x000007FF +const USB_H_MPS7_S = 0 +const USB_H_EPNUM7 = 0x0000000F +const USB_H_EPNUM7_V = 0x0000000F +const USB_H_EPNUM7_S = 11 +const USB_H_EPDIR7_V = 0x00000001 +const USB_H_EPDIR7_S = 15 +const USB_H_LSPDDEV7_V = 0x00000001 +const USB_H_LSPDDEV7_S = 17 +const USB_H_EPTYPE7 = 0x00000003 +const USB_H_EPTYPE7_V = 0x00000003 +const USB_H_EPTYPE7_S = 18 +const USB_H_EC7_V = 0x00000001 +const USB_H_EC7_S = 21 +const USB_H_DEVADDR7 = 0x0000007F +const USB_H_DEVADDR7_V = 0x0000007F +const USB_H_DEVADDR7_S = 22 +const USB_H_ODDFRM7_V = 0x00000001 +const USB_H_ODDFRM7_S = 29 +const USB_H_CHDIS7_V = 0x00000001 +const USB_H_CHDIS7_S = 30 +const USB_H_CHENA7_V = 0x00000001 +const USB_H_CHENA7_S = 31 +const USB_H_DMAADDR7 = 0xFFFFFFFF +const USB_H_DMAADDR7_V = 0xFFFFFFFF +const USB_H_DMAADDR7_S = 0 +const USB_NZSTSOUTHSHK_V = 0x00000001 +const USB_NZSTSOUTHSHK_S = 2 +const USB_ENA32KHZSUSP_V = 0x00000001 +const USB_ENA32KHZSUSP_S = 3 +const USB_DEVADDR = 0x0000007F +const USB_DEVADDR_V = 0x0000007F +const USB_DEVADDR_S = 4 +const USB_PERFRLINT = 0x00000003 +const USB_PERFRLINT_V = 0x00000003 +const USB_PERFRLINT_S = 11 +const USB_ENDEVOUTNAK_V = 0x00000001 +const USB_ENDEVOUTNAK_S = 13 +const USB_XCVRDLY_V = 0x00000001 +const USB_XCVRDLY_S = 14 +const USB_ERRATICINTMSK_V = 0x00000001 +const USB_ERRATICINTMSK_S = 15 +const USB_EPMISCNT = 0x0000001F +const USB_EPMISCNT_V = 0x0000001F +const USB_EPMISCNT_S = 18 +const USB_DESCDMA_V = 0x00000001 +const USB_DESCDMA_S = 23 +const USB_PERSCHINTVL = 0x00000003 +const USB_PERSCHINTVL_V = 0x00000003 +const USB_PERSCHINTVL_S = 24 +const USB_RESVALID = 0x0000003F +const USB_RESVALID_V = 0x0000003F +const USB_RESVALID_S = 26 +const USB_RMTWKUPSIG_V = 0x00000001 +const USB_RMTWKUPSIG_S = 0 +const USB_SFTDISCON_V = 0x00000001 +const USB_SFTDISCON_S = 1 +const USB_GNPINNAKSTS_V = 0x00000001 +const USB_GNPINNAKSTS_S = 2 +const USB_GOUTNAKSTS_V = 0x00000001 +const USB_GOUTNAKSTS_S = 3 +const USB_TSTCTL = 0x00000007 +const USB_TSTCTL_V = 0x00000007 +const USB_TSTCTL_S = 4 +const USB_SGNPINNAK_V = 0x00000001 +const USB_SGNPINNAK_S = 7 +const USB_CGNPINNAK_V = 0x00000001 +const USB_CGNPINNAK_S = 8 +const USB_SGOUTNAK_V = 0x00000001 +const USB_SGOUTNAK_S = 9 +const USB_CGOUTNAK_V = 0x00000001 +const USB_CGOUTNAK_S = 10 +const USB_PWRONPRGDONE_V = 0x00000001 +const USB_PWRONPRGDONE_S = 11 +const USB_GMC = 0x00000003 +const USB_GMC_V = 0x00000003 +const USB_GMC_S = 13 +const USB_IGNRFRMNUM_V = 0x00000001 +const USB_IGNRFRMNUM_S = 15 +const USB_NAKONBBLE_V = 0x00000001 +const USB_NAKONBBLE_S = 16 +const USB_ENCOUNTONBNA_V = 0x00000001 +const USB_ENCOUNTONBNA_S = 17 +const USB_DEEPSLEEPBESLREJECT_V = 0x00000001 +const USB_DEEPSLEEPBESLREJECT_S = 18 +const USB_DVBUSDIS = 0x0000FFFF +const USB_DVBUSDIS_V = 0x0000FFFF +const USB_DVBUSDIS_S = 0 +const USB_DVBUSPULSE = 0x00000FFF +const USB_DVBUSPULSE_V = 0x00000FFF +const USB_DVBUSPULSE_S = 0 +const USB_NONISOTHREN_V = 0x00000001 +const USB_NONISOTHREN_S = 0 +const USB_ISOTHREN_V = 0x00000001 +const USB_ISOTHREN_S = 1 +const USB_TXTHRLEN = 0x000001FF +const USB_TXTHRLEN_V = 0x000001FF +const USB_TXTHRLEN_S = 2 +const USB_AHBTHRRATIO = 0x00000003 +const USB_AHBTHRRATIO_V = 0x00000003 +const USB_AHBTHRRATIO_S = 11 +const USB_RXTHREN_V = 0x00000001 +const USB_RXTHREN_S = 16 +const USB_RXTHRLEN = 0x000001FF +const USB_RXTHRLEN_V = 0x000001FF +const USB_RXTHRLEN_S = 17 +const USB_ARBPRKEN_V = 0x00000001 +const USB_ARBPRKEN_S = 27 +const USB_D_MPS0 = 0x00000003 +const USB_D_MPS0_V = 0x00000003 +const USB_D_MPS0_S = 0 +const USB_D_USBACTEP0_V = 0x00000001 +const USB_D_USBACTEP0_S = 15 +const USB_D_NAKSTS0_V = 0x00000001 +const USB_D_NAKSTS0_S = 17 +const USB_D_EPTYPE0 = 0x00000003 +const USB_D_EPTYPE0_V = 0x00000003 +const USB_D_EPTYPE0_S = 18 +const USB_D_STALL0_V = 0x00000001 +const USB_D_STALL0_S = 21 +const USB_D_TXFNUM0 = 0x0000000F +const USB_D_TXFNUM0_V = 0x0000000F +const USB_D_TXFNUM0_S = 22 +const USB_D_CNAK0_V = 0x00000001 +const USB_D_CNAK0_S = 26 +const USB_DI_SNAK0_V = 0x00000001 +const USB_DI_SNAK0_S = 27 +const USB_D_EPDIS0_V = 0x00000001 +const USB_D_EPDIS0_S = 30 +const USB_D_EPENA0_V = 0x00000001 +const USB_D_EPENA0_S = 31 +const USB_D_XFERSIZE0 = 0x0000007F +const USB_D_XFERSIZE0_V = 0x0000007F +const USB_D_XFERSIZE0_S = 0 +const USB_D_PKTCNT0 = 0x00000003 +const USB_D_PKTCNT0_V = 0x00000003 +const USB_D_PKTCNT0_S = 19 +const USB_D_DMAADDR0 = 0xFFFFFFFF +const USB_D_DMAADDR0_V = 0xFFFFFFFF +const USB_D_DMAADDR0_S = 0 +const USB_D_MPS1 = 0x00000003 +const USB_D_MPS1_V = 0x00000003 +const USB_D_MPS1_S = 0 +const USB_D_USBACTEP1_V = 0x00000001 +const USB_D_USBACTEP1_S = 15 +const USB_D_NAKSTS1_V = 0x00000001 +const USB_D_NAKSTS1_S = 17 +const USB_D_EPTYPE1 = 0x00000003 +const USB_D_EPTYPE1_V = 0x00000003 +const USB_D_EPTYPE1_S = 18 +const USB_D_STALL1_V = 0x00000001 +const USB_D_STALL1_S = 21 +const USB_D_TXFNUM1 = 0x0000000F +const USB_D_TXFNUM1_V = 0x0000000F +const USB_D_TXFNUM1_S = 22 +const USB_D_CNAK1_V = 0x00000001 +const USB_D_CNAK1_S = 26 +const USB_DI_SNAK1_V = 0x00000001 +const USB_DI_SNAK1_S = 27 +const USB_DI_SETD0PID1_V = 0x00000001 +const USB_DI_SETD0PID1_S = 28 +const USB_DI_SETD1PID1_V = 0x00000001 +const USB_DI_SETD1PID1_S = 29 +const USB_D_EPDIS1_V = 0x00000001 +const USB_D_EPDIS1_S = 30 +const USB_D_EPENA1_V = 0x00000001 +const USB_D_EPENA1_S = 31 +const USB_D_XFERSIZE1 = 0x0000007F +const USB_D_XFERSIZE1_V = 0x0000007F +const USB_D_XFERSIZE1_S = 0 +const USB_D_PKTCNT1 = 0x00000003 +const USB_D_PKTCNT1_V = 0x00000003 +const USB_D_PKTCNT1_S = 19 +const USB_D_DMAADDR1 = 0xFFFFFFFF +const USB_D_DMAADDR1_V = 0xFFFFFFFF +const USB_D_DMAADDR1_S = 0 +const USB_D_MPS2 = 0x00000003 +const USB_D_MPS2_V = 0x00000003 +const USB_D_MPS2_S = 0 +const USB_D_USBACTEP2_V = 0x00000001 +const USB_D_USBACTEP2_S = 15 +const USB_D_NAKSTS2_V = 0x00000001 +const USB_D_NAKSTS2_S = 17 +const USB_D_EPTYPE2 = 0x00000003 +const USB_D_EPTYPE2_V = 0x00000003 +const USB_D_EPTYPE2_S = 18 +const USB_D_STALL2_V = 0x00000001 +const USB_D_STALL2_S = 21 +const USB_D_TXFNUM2 = 0x0000000F +const USB_D_TXFNUM2_V = 0x0000000F +const USB_D_TXFNUM2_S = 22 +const USB_D_CNAK2_V = 0x00000001 +const USB_D_CNAK2_S = 26 +const USB_DI_SNAK2_V = 0x00000001 +const USB_DI_SNAK2_S = 27 +const USB_DI_SETD0PID2_V = 0x00000001 +const USB_DI_SETD0PID2_S = 28 +const USB_DI_SETD1PID2_V = 0x00000001 +const USB_DI_SETD1PID2_S = 29 +const USB_D_EPDIS2_V = 0x00000001 +const USB_D_EPDIS2_S = 30 +const USB_D_EPENA2_V = 0x00000001 +const USB_D_EPENA2_S = 31 +const USB_D_XFERSIZE2 = 0x0000007F +const USB_D_XFERSIZE2_V = 0x0000007F +const USB_D_XFERSIZE2_S = 0 +const USB_D_PKTCNT2 = 0x00000003 +const USB_D_PKTCNT2_V = 0x00000003 +const USB_D_PKTCNT2_S = 19 +const USB_D_DMAADDR2 = 0xFFFFFFFF +const USB_D_DMAADDR2_V = 0xFFFFFFFF +const USB_D_DMAADDR2_S = 0 +const USB_DI_MPS3 = 0x00000003 +const USB_DI_MPS3_V = 0x00000003 +const USB_DI_MPS3_S = 0 +const USB_DI_USBACTEP3_V = 0x00000001 +const USB_DI_USBACTEP3_S = 15 +const USB_DI_NAKSTS3_V = 0x00000001 +const USB_DI_NAKSTS3_S = 17 +const USB_DI_EPTYPE3 = 0x00000003 +const USB_DI_EPTYPE3_V = 0x00000003 +const USB_DI_EPTYPE3_S = 18 +const USB_DI_STALL3_V = 0x00000001 +const USB_DI_STALL3_S = 21 +const USB_DI_TXFNUM3 = 0x0000000F +const USB_DI_TXFNUM3_V = 0x0000000F +const USB_DI_TXFNUM3_S = 22 +const USB_DI_CNAK3_V = 0x00000001 +const USB_DI_CNAK3_S = 26 +const USB_DI_SNAK3_V = 0x00000001 +const USB_DI_SNAK3_S = 27 +const USB_DI_SETD0PID3_V = 0x00000001 +const USB_DI_SETD0PID3_S = 28 +const USB_DI_SETD1PID3_V = 0x00000001 +const USB_DI_SETD1PID3_S = 29 +const USB_DI_EPDIS3_V = 0x00000001 +const USB_DI_EPDIS3_S = 30 +const USB_DI_EPENA3_V = 0x00000001 +const USB_DI_EPENA3_S = 31 +const USB_D_XFERSIZE3 = 0x0000007F +const USB_D_XFERSIZE3_V = 0x0000007F +const USB_D_XFERSIZE3_S = 0 +const USB_D_PKTCNT3 = 0x00000003 +const USB_D_PKTCNT3_V = 0x00000003 +const USB_D_PKTCNT3_S = 19 +const USB_D_DMAADDR3 = 0xFFFFFFFF +const USB_D_DMAADDR3_V = 0xFFFFFFFF +const USB_D_DMAADDR3_S = 0 +const USB_D_MPS4 = 0x00000003 +const USB_D_MPS4_V = 0x00000003 +const USB_D_MPS4_S = 0 +const USB_D_USBACTEP4_V = 0x00000001 +const USB_D_USBACTEP4_S = 15 +const USB_D_NAKSTS4_V = 0x00000001 +const USB_D_NAKSTS4_S = 17 +const USB_D_EPTYPE4 = 0x00000003 +const USB_D_EPTYPE4_V = 0x00000003 +const USB_D_EPTYPE4_S = 18 +const USB_D_STALL4_V = 0x00000001 +const USB_D_STALL4_S = 21 +const USB_D_TXFNUM4 = 0x0000000F +const USB_D_TXFNUM4_V = 0x0000000F +const USB_D_TXFNUM4_S = 22 +const USB_D_CNAK4_V = 0x00000001 +const USB_D_CNAK4_S = 26 +const USB_DI_SNAK4_V = 0x00000001 +const USB_DI_SNAK4_S = 27 +const USB_DI_SETD0PID4_V = 0x00000001 +const USB_DI_SETD0PID4_S = 28 +const USB_DI_SETD1PID4_V = 0x00000001 +const USB_DI_SETD1PID4_S = 29 +const USB_D_EPDIS4_V = 0x00000001 +const USB_D_EPDIS4_S = 30 +const USB_D_EPENA4_V = 0x00000001 +const USB_D_EPENA4_S = 31 +const USB_D_XFERSIZE4 = 0x0000007F +const USB_D_XFERSIZE4_V = 0x0000007F +const USB_D_XFERSIZE4_S = 0 +const USB_D_PKTCNT4 = 0x00000003 +const USB_D_PKTCNT4_V = 0x00000003 +const USB_D_PKTCNT4_S = 19 +const USB_D_DMAADDR4 = 0xFFFFFFFF +const USB_D_DMAADDR4_V = 0xFFFFFFFF +const USB_D_DMAADDR4_S = 0 +const USB_DI_MPS5 = 0x00000003 +const USB_DI_MPS5_V = 0x00000003 +const USB_DI_MPS5_S = 0 +const USB_DI_USBACTEP5_V = 0x00000001 +const USB_DI_USBACTEP5_S = 15 +const USB_DI_NAKSTS5_V = 0x00000001 +const USB_DI_NAKSTS5_S = 17 +const USB_DI_EPTYPE5 = 0x00000003 +const USB_DI_EPTYPE5_V = 0x00000003 +const USB_DI_EPTYPE5_S = 18 +const USB_DI_STALL5_V = 0x00000001 +const USB_DI_STALL5_S = 21 +const USB_DI_TXFNUM5 = 0x0000000F +const USB_DI_TXFNUM5_V = 0x0000000F +const USB_DI_TXFNUM5_S = 22 +const USB_DI_CNAK5_V = 0x00000001 +const USB_DI_CNAK5_S = 26 +const USB_DI_SNAK5_V = 0x00000001 +const USB_DI_SNAK5_S = 27 +const USB_DI_SETD0PID5_V = 0x00000001 +const USB_DI_SETD0PID5_S = 28 +const USB_DI_SETD1PID5_V = 0x00000001 +const USB_DI_SETD1PID5_S = 29 +const USB_DI_EPDIS5_V = 0x00000001 +const USB_DI_EPDIS5_S = 30 +const USB_DI_EPENA5_V = 0x00000001 +const USB_DI_EPENA5_S = 31 +const USB_D_XFERSIZE5 = 0x0000007F +const USB_D_XFERSIZE5_V = 0x0000007F +const USB_D_XFERSIZE5_S = 0 +const USB_D_PKTCNT5 = 0x00000003 +const USB_D_PKTCNT5_V = 0x00000003 +const USB_D_PKTCNT5_S = 19 +const USB_D_DMAADDR5 = 0xFFFFFFFF +const USB_D_DMAADDR5_V = 0xFFFFFFFF +const USB_D_DMAADDR5_S = 0 +const USB_D_MPS6 = 0x00000003 +const USB_D_MPS6_V = 0x00000003 +const USB_D_MPS6_S = 0 +const USB_D_USBACTEP6_V = 0x00000001 +const USB_D_USBACTEP6_S = 15 +const USB_D_NAKSTS6_V = 0x00000001 +const USB_D_NAKSTS6_S = 17 +const USB_D_EPTYPE6 = 0x00000003 +const USB_D_EPTYPE6_V = 0x00000003 +const USB_D_EPTYPE6_S = 18 +const USB_D_STALL6_V = 0x00000001 +const USB_D_STALL6_S = 21 +const USB_D_TXFNUM6 = 0x0000000F +const USB_D_TXFNUM6_V = 0x0000000F +const USB_D_TXFNUM6_S = 22 +const USB_D_CNAK6_V = 0x00000001 +const USB_D_CNAK6_S = 26 +const USB_DI_SNAK6_V = 0x00000001 +const USB_DI_SNAK6_S = 27 +const USB_DI_SETD0PID6_V = 0x00000001 +const USB_DI_SETD0PID6_S = 28 +const USB_DI_SETD1PID6_V = 0x00000001 +const USB_DI_SETD1PID6_S = 29 +const USB_D_EPDIS6_V = 0x00000001 +const USB_D_EPDIS6_S = 30 +const USB_D_EPENA6_V = 0x00000001 +const USB_D_EPENA6_S = 31 +const USB_D_XFERSIZE6 = 0x0000007F +const USB_D_XFERSIZE6_V = 0x0000007F +const USB_D_XFERSIZE6_S = 0 +const USB_D_PKTCNT6 = 0x00000003 +const USB_D_PKTCNT6_V = 0x00000003 +const USB_D_PKTCNT6_S = 19 +const USB_D_DMAADDR6 = 0xFFFFFFFF +const USB_D_DMAADDR6_V = 0xFFFFFFFF +const USB_D_DMAADDR6_S = 0 +const USB_MPS0 = 0x00000003 +const USB_MPS0_V = 0x00000003 +const USB_MPS0_S = 0 +const USB_USBACTEP0_V = 0x00000001 +const USB_USBACTEP0_S = 15 +const USB_NAKSTS0_V = 0x00000001 +const USB_NAKSTS0_S = 17 +const USB_EPTYPE0 = 0x00000003 +const USB_EPTYPE0_V = 0x00000003 +const USB_EPTYPE0_S = 18 +const USB_SNP0_V = 0x00000001 +const USB_SNP0_S = 20 +const USB_STALL0_V = 0x00000001 +const USB_STALL0_S = 21 +const USB_CNAK0_V = 0x00000001 +const USB_CNAK0_S = 26 +const USB_DO_SNAK0_V = 0x00000001 +const USB_DO_SNAK0_S = 27 +const USB_EPDIS0_V = 0x00000001 +const USB_EPDIS0_S = 30 +const USB_EPENA0_V = 0x00000001 +const USB_EPENA0_S = 31 +const USB_XFERSIZE0 = 0x0000007F +const USB_XFERSIZE0_V = 0x0000007F +const USB_XFERSIZE0_S = 0 +const USB_PKTCNT0_V = 0x00000001 +const USB_PKTCNT0_S = 19 +const USB_SUPCNT0 = 0x00000003 +const USB_SUPCNT0_V = 0x00000003 +const USB_SUPCNT0_S = 29 +const USB_DMAADDR0 = 0xFFFFFFFF +const USB_DMAADDR0_V = 0xFFFFFFFF +const USB_DMAADDR0_S = 0 +const USB_DMABUFFERADDR0 = 0xFFFFFFFF +const USB_DMABUFFERADDR0_V = 0xFFFFFFFF +const USB_DMABUFFERADDR0_S = 0 +const USB_MPS1 = 0x000007FF +const USB_MPS1_V = 0x000007FF +const USB_MPS1_S = 0 +const USB_USBACTEP1_V = 0x00000001 +const USB_USBACTEP1_S = 15 +const USB_NAKSTS1_V = 0x00000001 +const USB_NAKSTS1_S = 17 +const USB_EPTYPE1 = 0x00000003 +const USB_EPTYPE1_V = 0x00000003 +const USB_EPTYPE1_S = 18 +const USB_SNP1_V = 0x00000001 +const USB_SNP1_S = 20 +const USB_STALL1_V = 0x00000001 +const USB_STALL1_S = 21 +const USB_CNAK1_V = 0x00000001 +const USB_CNAK1_S = 26 +const USB_DO_SNAK1_V = 0x00000001 +const USB_DO_SNAK1_S = 27 +const USB_DO_SETD0PID1_V = 0x00000001 +const USB_DO_SETD0PID1_S = 28 +const USB_DO_SETD1PID1_V = 0x00000001 +const USB_DO_SETD1PID1_S = 29 +const USB_EPDIS1_V = 0x00000001 +const USB_EPDIS1_S = 30 +const USB_EPENA1_V = 0x00000001 +const USB_EPENA1_S = 31 +const USB_XFERSIZE1 = 0x0000007F +const USB_XFERSIZE1_V = 0x0000007F +const USB_XFERSIZE1_S = 0 +const USB_PKTCNT1_V = 0x00000001 +const USB_PKTCNT1_S = 19 +const USB_SUPCNT1 = 0x00000003 +const USB_SUPCNT1_V = 0x00000003 +const USB_SUPCNT1_S = 29 +const USB_DMAADDR1 = 0xFFFFFFFF +const USB_DMAADDR1_V = 0xFFFFFFFF +const USB_DMAADDR1_S = 0 +const USB_DMABUFFERADDR1 = 0xFFFFFFFF +const USB_DMABUFFERADDR1_V = 0xFFFFFFFF +const USB_DMABUFFERADDR1_S = 0 +const USB_MPS2 = 0x000007FF +const USB_MPS2_V = 0x000007FF +const USB_MPS2_S = 0 +const USB_USBACTEP2_V = 0x00000001 +const USB_USBACTEP2_S = 15 +const USB_NAKSTS2_V = 0x00000001 +const USB_NAKSTS2_S = 17 +const USB_EPTYPE2 = 0x00000003 +const USB_EPTYPE2_V = 0x00000003 +const USB_EPTYPE2_S = 18 +const USB_SNP2_V = 0x00000001 +const USB_SNP2_S = 20 +const USB_STALL2_V = 0x00000001 +const USB_STALL2_S = 21 +const USB_CNAK2_V = 0x00000001 +const USB_CNAK2_S = 26 +const USB_DO_SNAK2_V = 0x00000001 +const USB_DO_SNAK2_S = 27 +const USB_DO_SETD0PID2_V = 0x00000001 +const USB_DO_SETD0PID2_S = 28 +const USB_DO_SETD1PID2_V = 0x00000001 +const USB_DO_SETD1PID2_S = 29 +const USB_EPDIS2_V = 0x00000001 +const USB_EPDIS2_S = 30 +const USB_EPENA2_V = 0x00000001 +const USB_EPENA2_S = 31 +const USB_XFERSIZE2 = 0x0000007F +const USB_XFERSIZE2_V = 0x0000007F +const USB_XFERSIZE2_S = 0 +const USB_PKTCNT2_V = 0x00000001 +const USB_PKTCNT2_S = 19 +const USB_SUPCNT2 = 0x00000003 +const USB_SUPCNT2_V = 0x00000003 +const USB_SUPCNT2_S = 29 +const USB_DMAADDR2 = 0xFFFFFFFF +const USB_DMAADDR2_V = 0xFFFFFFFF +const USB_DMAADDR2_S = 0 +const USB_DMABUFFERADDR2 = 0xFFFFFFFF +const USB_DMABUFFERADDR2_V = 0xFFFFFFFF +const USB_DMABUFFERADDR2_S = 0 +const USB_MPS3 = 0x000007FF +const USB_MPS3_V = 0x000007FF +const USB_MPS3_S = 0 +const USB_USBACTEP3_V = 0x00000001 +const USB_USBACTEP3_S = 15 +const USB_NAKSTS3_V = 0x00000001 +const USB_NAKSTS3_S = 17 +const USB_EPTYPE3 = 0x00000003 +const USB_EPTYPE3_V = 0x00000003 +const USB_EPTYPE3_S = 18 +const USB_SNP3_V = 0x00000001 +const USB_SNP3_S = 20 +const USB_STALL3_V = 0x00000001 +const USB_STALL3_S = 21 +const USB_CNAK3_V = 0x00000001 +const USB_CNAK3_S = 26 +const USB_DO_SNAK3_V = 0x00000001 +const USB_DO_SNAK3_S = 27 +const USB_DO_SETD0PID3_V = 0x00000001 +const USB_DO_SETD0PID3_S = 28 +const USB_DO_SETD1PID3_V = 0x00000001 +const USB_DO_SETD1PID3_S = 29 +const USB_EPDIS3_V = 0x00000001 +const USB_EPDIS3_S = 30 +const USB_EPENA3_V = 0x00000001 +const USB_EPENA3_S = 31 +const USB_XFERSIZE3 = 0x0000007F +const USB_XFERSIZE3_V = 0x0000007F +const USB_XFERSIZE3_S = 0 +const USB_PKTCNT3_V = 0x00000001 +const USB_PKTCNT3_S = 19 +const USB_SUPCNT3 = 0x00000003 +const USB_SUPCNT3_V = 0x00000003 +const USB_SUPCNT3_S = 29 +const USB_DMAADDR3 = 0xFFFFFFFF +const USB_DMAADDR3_V = 0xFFFFFFFF +const USB_DMAADDR3_S = 0 +const USB_DMABUFFERADDR3 = 0xFFFFFFFF +const USB_DMABUFFERADDR3_V = 0xFFFFFFFF +const USB_DMABUFFERADDR3_S = 0 +const USB_MPS4 = 0x000007FF +const USB_MPS4_V = 0x000007FF +const USB_MPS4_S = 0 +const USB_USBACTEP4_V = 0x00000001 +const USB_USBACTEP4_S = 15 +const USB_NAKSTS4_V = 0x00000001 +const USB_NAKSTS4_S = 17 +const USB_EPTYPE4 = 0x00000003 +const USB_EPTYPE4_V = 0x00000003 +const USB_EPTYPE4_S = 18 +const USB_SNP4_V = 0x00000001 +const USB_SNP4_S = 20 +const USB_STALL4_V = 0x00000001 +const USB_STALL4_S = 21 +const USB_CNAK4_V = 0x00000001 +const USB_CNAK4_S = 26 +const USB_DO_SNAK4_V = 0x00000001 +const USB_DO_SNAK4_S = 27 +const USB_DO_SETD0PID4_V = 0x00000001 +const USB_DO_SETD0PID4_S = 28 +const USB_DO_SETD1PID4_V = 0x00000001 +const USB_DO_SETD1PID4_S = 29 +const USB_EPDIS4_V = 0x00000001 +const USB_EPDIS4_S = 30 +const USB_EPENA4_V = 0x00000001 +const USB_EPENA4_S = 31 +const USB_XFERSIZE4 = 0x0000007F +const USB_XFERSIZE4_V = 0x0000007F +const USB_XFERSIZE4_S = 0 +const USB_PKTCNT4_V = 0x00000001 +const USB_PKTCNT4_S = 19 +const USB_SUPCNT4 = 0x00000003 +const USB_SUPCNT4_V = 0x00000003 +const USB_SUPCNT4_S = 29 +const USB_DMAADDR4 = 0xFFFFFFFF +const USB_DMAADDR4_V = 0xFFFFFFFF +const USB_DMAADDR4_S = 0 +const USB_DMABUFFERADDR4 = 0xFFFFFFFF +const USB_DMABUFFERADDR4_V = 0xFFFFFFFF +const USB_DMABUFFERADDR4_S = 0 +const USB_MPS5 = 0x000007FF +const USB_MPS5_V = 0x000007FF +const USB_MPS5_S = 0 +const USB_USBACTEP5_V = 0x00000001 +const USB_USBACTEP5_S = 15 +const USB_NAKSTS5_V = 0x00000001 +const USB_NAKSTS5_S = 17 +const USB_EPTYPE5 = 0x00000003 +const USB_EPTYPE5_V = 0x00000003 +const USB_EPTYPE5_S = 18 +const USB_SNP5_V = 0x00000001 +const USB_SNP5_S = 20 +const USB_STALL5_V = 0x00000001 +const USB_STALL5_S = 21 +const USB_CNAK5_V = 0x00000001 +const USB_CNAK5_S = 26 +const USB_DO_SNAK5_V = 0x00000001 +const USB_DO_SNAK5_S = 27 +const USB_DO_SETD0PID5_V = 0x00000001 +const USB_DO_SETD0PID5_S = 28 +const USB_DO_SETD1PID5_V = 0x00000001 +const USB_DO_SETD1PID5_S = 29 +const USB_EPDIS5_V = 0x00000001 +const USB_EPDIS5_S = 30 +const USB_EPENA5_V = 0x00000001 +const USB_EPENA5_S = 31 +const USB_XFERSIZE5 = 0x0000007F +const USB_XFERSIZE5_V = 0x0000007F +const USB_XFERSIZE5_S = 0 +const USB_PKTCNT5_V = 0x00000001 +const USB_PKTCNT5_S = 19 +const USB_SUPCNT5 = 0x00000003 +const USB_SUPCNT5_V = 0x00000003 +const USB_SUPCNT5_S = 29 +const USB_DMAADDR5 = 0xFFFFFFFF +const USB_DMAADDR5_V = 0xFFFFFFFF +const USB_DMAADDR5_S = 0 +const USB_DMABUFFERADDR5 = 0xFFFFFFFF +const USB_DMABUFFERADDR5_V = 0xFFFFFFFF +const USB_DMABUFFERADDR5_S = 0 +const USB_MPS6 = 0x000007FF +const USB_MPS6_V = 0x000007FF +const USB_MPS6_S = 0 +const USB_USBACTEP6_V = 0x00000001 +const USB_USBACTEP6_S = 15 +const USB_NAKSTS6_V = 0x00000001 +const USB_NAKSTS6_S = 17 +const USB_EPTYPE6 = 0x00000003 +const USB_EPTYPE6_V = 0x00000003 +const USB_EPTYPE6_S = 18 +const USB_SNP6_V = 0x00000001 +const USB_SNP6_S = 20 +const USB_STALL6_V = 0x00000001 +const USB_STALL6_S = 21 +const USB_CNAK6_V = 0x00000001 +const USB_CNAK6_S = 26 +const USB_DO_SNAK6_V = 0x00000001 +const USB_DO_SNAK6_S = 27 +const USB_DO_SETD0PID6_V = 0x00000001 +const USB_DO_SETD0PID6_S = 28 +const USB_DO_SETD1PID6_V = 0x00000001 +const USB_DO_SETD1PID6_S = 29 +const USB_EPDIS6_V = 0x00000001 +const USB_EPDIS6_S = 30 +const USB_EPENA6_V = 0x00000001 +const USB_EPENA6_S = 31 +const USB_XFERSIZE6 = 0x0000007F +const USB_XFERSIZE6_V = 0x0000007F +const USB_XFERSIZE6_S = 0 +const USB_PKTCNT6_V = 0x00000001 +const USB_PKTCNT6_S = 19 +const USB_SUPCNT6 = 0x00000003 +const USB_SUPCNT6_V = 0x00000003 +const USB_SUPCNT6_S = 29 +const USB_DMAADDR6 = 0xFFFFFFFF +const USB_DMAADDR6_V = 0xFFFFFFFF +const USB_DMAADDR6_S = 0 +const USB_DMABUFFERADDR6 = 0xFFFFFFFF +const USB_DMABUFFERADDR6_V = 0xFFFFFFFF +const USB_DMABUFFERADDR6_S = 0 +const USB_STOPPCLK_V = 0x00000001 +const USB_STOPPCLK_S = 0 +const USB_GATEHCLK_V = 0x00000001 +const USB_GATEHCLK_S = 1 +const USB_PWRCLMP_V = 0x00000001 +const USB_PWRCLMP_S = 2 +const USB_RSTPDWNMODULE_V = 0x00000001 +const USB_RSTPDWNMODULE_S = 3 +const USB_PHYSLEEP_V = 0x00000001 +const USB_PHYSLEEP_S = 6 +const USB_L1SUSPENDED_V = 0x00000001 +const USB_L1SUSPENDED_S = 7 +const USB_RESETAFTERSUSP_V = 0x00000001 +const USB_RESETAFTERSUSP_S = 8 +const USB_SESENDDET_V = 0x00000001 +const USB_SESENDDET_S = 2 +const USB_SESREQSUCSTSCHNG_V = 0x00000001 +const USB_SESREQSUCSTSCHNG_S = 8 +const USB_HSTNEGSUCSTSCHNG_V = 0x00000001 +const USB_HSTNEGSUCSTSCHNG_S = 9 +const USB_HSTNEGDET_V = 0x00000001 +const USB_HSTNEGDET_S = 17 +const USB_ADEVTOUTCHG_V = 0x00000001 +const USB_ADEVTOUTCHG_S = 18 +const USB_DBNCEDONE_V = 0x00000001 +const USB_DBNCEDONE_S = 19 +const USB_CURMOD_INT_V = 0x00000001 +const USB_CURMOD_INT_S = 0 +const USB_MODEMIS_V = 0x00000001 +const USB_MODEMIS_S = 1 +const USB_OTGINT_V = 0x00000001 +const USB_OTGINT_S = 2 +const USB_SOF_V = 0x00000001 +const USB_SOF_S = 3 +const USB_RXFLVI_V = 0x00000001 +const USB_RXFLVI_S = 4 +const USB_NPTXFEMP_V = 0x00000001 +const USB_NPTXFEMP_S = 5 +const USB_GINNAKEFF_V = 0x00000001 +const USB_GINNAKEFF_S = 6 +const USB_GOUTNAKEFF_V = 0x00000001 +const USB_GOUTNAKEFF_S = 7 +const USB_ERLYSUSP_V = 0x00000001 +const USB_ERLYSUSP_S = 10 +const USB_USBSUSP_V = 0x00000001 +const USB_USBSUSP_S = 11 +const USB_USBRST_V = 0x00000001 +const USB_USBRST_S = 12 +const USB_ENUMDONE_V = 0x00000001 +const USB_ENUMDONE_S = 13 +const USB_ISOOUTDROP_V = 0x00000001 +const USB_ISOOUTDROP_S = 14 +const USB_EOPF_V = 0x00000001 +const USB_EOPF_S = 15 +const USB_EPMIS_V = 0x00000001 +const USB_EPMIS_S = 17 +const USB_IEPINT_V = 0x00000001 +const USB_IEPINT_S = 18 +const USB_OEPINT_V = 0x00000001 +const USB_OEPINT_S = 19 +const USB_INCOMPISOIN_V = 0x00000001 +const USB_INCOMPISOIN_S = 20 +const USB_INCOMPIP_V = 0x00000001 +const USB_INCOMPIP_S = 21 +const USB_FETSUSP_V = 0x00000001 +const USB_FETSUSP_S = 22 +const USB_RESETDET_V = 0x00000001 +const USB_RESETDET_S = 23 +const USB_PRTLNT_V = 0x00000001 +const USB_PRTLNT_S = 24 +const USB_HCHLNT_V = 0x00000001 +const USB_HCHLNT_S = 25 +const USB_PTXFEMP_V = 0x00000001 +const USB_PTXFEMP_S = 26 +const USB_CONIDSTSCHNG_V = 0x00000001 +const USB_CONIDSTSCHNG_S = 28 +const USB_DISCONNINT_V = 0x00000001 +const USB_DISCONNINT_S = 29 +const USB_SESSREQINT_V = 0x00000001 +const USB_SESSREQINT_S = 30 +const USB_WKUPINT_V = 0x00000001 +const USB_WKUPINT_S = 31 +const USB_MODEMISMSK_V = 0x00000001 +const USB_MODEMISMSK_S = 1 +const USB_OTGINTMSK_V = 0x00000001 +const USB_OTGINTMSK_S = 2 +const USB_SOFMSK_V = 0x00000001 +const USB_SOFMSK_S = 3 +const USB_RXFLVIMSK_V = 0x00000001 +const USB_RXFLVIMSK_S = 4 +const USB_NPTXFEMPMSK_V = 0x00000001 +const USB_NPTXFEMPMSK_S = 5 +const USB_GINNAKEFFMSK_V = 0x00000001 +const USB_GINNAKEFFMSK_S = 6 +const USB_GOUTNACKEFFMSK_V = 0x00000001 +const USB_GOUTNACKEFFMSK_S = 7 +const USB_ERLYSUSPMSK_V = 0x00000001 +const USB_ERLYSUSPMSK_S = 10 +const USB_USBSUSPMSK_V = 0x00000001 +const USB_USBSUSPMSK_S = 11 +const USB_USBRSTMSK_V = 0x00000001 +const USB_USBRSTMSK_S = 12 +const USB_ENUMDONEMSK_V = 0x00000001 +const USB_ENUMDONEMSK_S = 13 +const USB_ISOOUTDROPMSK_V = 0x00000001 +const USB_ISOOUTDROPMSK_S = 14 +const USB_EOPFMSK_V = 0x00000001 +const USB_EOPFMSK_S = 15 +const USB_EPMISMSK_V = 0x00000001 +const USB_EPMISMSK_S = 17 +const USB_IEPINTMSK_V = 0x00000001 +const USB_IEPINTMSK_S = 18 +const USB_OEPINTMSK_V = 0x00000001 +const USB_OEPINTMSK_S = 19 +const USB_INCOMPISOINMSK_V = 0x00000001 +const USB_INCOMPISOINMSK_S = 20 +const USB_INCOMPIPMSK_V = 0x00000001 +const USB_INCOMPIPMSK_S = 21 +const USB_FETSUSPMSK_V = 0x00000001 +const USB_FETSUSPMSK_S = 22 +const USB_RESETDETMSK_V = 0x00000001 +const USB_RESETDETMSK_S = 23 +const USB_PRTLNTMSK_V = 0x00000001 +const USB_PRTLNTMSK_S = 24 +const USB_HCHINTMSK_V = 0x00000001 +const USB_HCHINTMSK_S = 25 +const USB_PTXFEMPMSK_V = 0x00000001 +const USB_PTXFEMPMSK_S = 26 +const USB_CONIDSTSCHNGMSK_V = 0x00000001 +const USB_CONIDSTSCHNGMSK_S = 28 +const USB_DISCONNINTMSK_V = 0x00000001 +const USB_DISCONNINTMSK_S = 29 +const USB_SESSREQINTMSK_V = 0x00000001 +const USB_SESSREQINTMSK_S = 30 +const USB_WKUPINTMSK_V = 0x00000001 +const USB_WKUPINTMSK_S = 31 +const USB_HAINT = 0x000000FF +const USB_HAINT_V = 0x000000FF +const USB_HAINT_S = 0 +const USB_HAINTMSK = 0x000000FF +const USB_HAINTMSK_V = 0x000000FF +const USB_HAINTMSK_S = 0 +const USB_H_XFERCOMPL0_V = 0x00000001 +const USB_H_XFERCOMPL0_S = 0 +const USB_H_CHHLTD0_V = 0x00000001 +const USB_H_CHHLTD0_S = 1 +const USB_H_AHBERR0_V = 0x00000001 +const USB_H_AHBERR0_S = 2 +const USB_H_STALL0_V = 0x00000001 +const USB_H_STALL0_S = 3 +const USB_H_NACK0_V = 0x00000001 +const USB_H_NACK0_S = 4 +const USB_H_ACK0_V = 0x00000001 +const USB_H_ACK0_S = 5 +const USB_H_NYET0_V = 0x00000001 +const USB_H_NYET0_S = 6 +const USB_H_XACTERR0_V = 0x00000001 +const USB_H_XACTERR0_S = 7 +const USB_H_BBLERR0_V = 0x00000001 +const USB_H_BBLERR0_S = 8 +const USB_H_FRMOVRUN0_V = 0x00000001 +const USB_H_FRMOVRUN0_S = 9 +const USB_H_DATATGLERR0_V = 0x00000001 +const USB_H_DATATGLERR0_S = 10 +const USB_H_BNAINTR0_V = 0x00000001 +const USB_H_BNAINTR0_S = 11 +const USB_H_XCS_XACT_ERR0_V = 0x00000001 +const USB_H_XCS_XACT_ERR0_S = 12 +const USB_H_DESC_LST_ROLLINTR0_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTR0_S = 13 +const USB_H_XFERCOMPLMSK0_V = 0x00000001 +const USB_H_XFERCOMPLMSK0_S = 0 +const USB_H_CHHLTDMSK0_V = 0x00000001 +const USB_H_CHHLTDMSK0_S = 1 +const USB_H_AHBERRMSK0_V = 0x00000001 +const USB_H_AHBERRMSK0_S = 2 +const USB_H_STALLMSK0_V = 0x00000001 +const USB_H_STALLMSK0_S = 3 +const USB_H_NAKMSK0_V = 0x00000001 +const USB_H_NAKMSK0_S = 4 +const USB_H_ACKMSK0_V = 0x00000001 +const USB_H_ACKMSK0_S = 5 +const USB_H_NYETMSK0_V = 0x00000001 +const USB_H_NYETMSK0_S = 6 +const USB_H_XACTERRMSK0_V = 0x00000001 +const USB_H_XACTERRMSK0_S = 7 +const USB_H_BBLERRMSK0_V = 0x00000001 +const USB_H_BBLERRMSK0_S = 8 +const USB_H_FRMOVRUNMSK0_V = 0x00000001 +const USB_H_FRMOVRUNMSK0_S = 9 +const USB_H_DATATGLERRMSK0_V = 0x00000001 +const USB_H_DATATGLERRMSK0_S = 10 +const USB_H_BNAINTRMSK0_V = 0x00000001 +const USB_H_BNAINTRMSK0_S = 11 +const USB_H_DESC_LST_ROLLINTRMSK0_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTRMSK0_S = 13 +const USB_H_XFERCOMPL1_V = 0x00000001 +const USB_H_XFERCOMPL1_S = 0 +const USB_H_CHHLTD1_V = 0x00000001 +const USB_H_CHHLTD1_S = 1 +const USB_H_AHBERR1_V = 0x00000001 +const USB_H_AHBERR1_S = 2 +const USB_H_STALL1_V = 0x00000001 +const USB_H_STALL1_S = 3 +const USB_H_NACK1_V = 0x00000001 +const USB_H_NACK1_S = 4 +const USB_H_ACK1_V = 0x00000001 +const USB_H_ACK1_S = 5 +const USB_H_NYET1_V = 0x00000001 +const USB_H_NYET1_S = 6 +const USB_H_XACTERR1_V = 0x00000001 +const USB_H_XACTERR1_S = 7 +const USB_H_BBLERR1_V = 0x00000001 +const USB_H_BBLERR1_S = 8 +const USB_H_FRMOVRUN1_V = 0x00000001 +const USB_H_FRMOVRUN1_S = 9 +const USB_H_DATATGLERR1_V = 0x00000001 +const USB_H_DATATGLERR1_S = 10 +const USB_H_BNAINTR1_V = 0x00000001 +const USB_H_BNAINTR1_S = 11 +const USB_H_XCS_XACT_ERR1_V = 0x00000001 +const USB_H_XCS_XACT_ERR1_S = 12 +const USB_H_DESC_LST_ROLLINTR1_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTR1_S = 13 +const USB_H_XFERCOMPLMSK1_V = 0x00000001 +const USB_H_XFERCOMPLMSK1_S = 0 +const USB_H_CHHLTDMSK1_V = 0x00000001 +const USB_H_CHHLTDMSK1_S = 1 +const USB_H_AHBERRMSK1_V = 0x00000001 +const USB_H_AHBERRMSK1_S = 2 +const USB_H_STALLMSK1_V = 0x00000001 +const USB_H_STALLMSK1_S = 3 +const USB_H_NAKMSK1_V = 0x00000001 +const USB_H_NAKMSK1_S = 4 +const USB_H_ACKMSK1_V = 0x00000001 +const USB_H_ACKMSK1_S = 5 +const USB_H_NYETMSK1_V = 0x00000001 +const USB_H_NYETMSK1_S = 6 +const USB_H_XACTERRMSK1_V = 0x00000001 +const USB_H_XACTERRMSK1_S = 7 +const USB_H_BBLERRMSK1_V = 0x00000001 +const USB_H_BBLERRMSK1_S = 8 +const USB_H_FRMOVRUNMSK1_V = 0x00000001 +const USB_H_FRMOVRUNMSK1_S = 9 +const USB_H_DATATGLERRMSK1_V = 0x00000001 +const USB_H_DATATGLERRMSK1_S = 10 +const USB_H_BNAINTRMSK1_V = 0x00000001 +const USB_H_BNAINTRMSK1_S = 11 +const USB_H_DESC_LST_ROLLINTRMSK1_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTRMSK1_S = 13 +const USB_H_XFERCOMPL2_V = 0x00000001 +const USB_H_XFERCOMPL2_S = 0 +const USB_H_CHHLTD2_V = 0x00000001 +const USB_H_CHHLTD2_S = 1 +const USB_H_AHBERR2_V = 0x00000001 +const USB_H_AHBERR2_S = 2 +const USB_H_STALL2_V = 0x00000001 +const USB_H_STALL2_S = 3 +const USB_H_NACK2_V = 0x00000001 +const USB_H_NACK2_S = 4 +const USB_H_ACK2_V = 0x00000001 +const USB_H_ACK2_S = 5 +const USB_H_NYET2_V = 0x00000001 +const USB_H_NYET2_S = 6 +const USB_H_XACTERR2_V = 0x00000001 +const USB_H_XACTERR2_S = 7 +const USB_H_BBLERR2_V = 0x00000001 +const USB_H_BBLERR2_S = 8 +const USB_H_FRMOVRUN2_V = 0x00000001 +const USB_H_FRMOVRUN2_S = 9 +const USB_H_DATATGLERR2_V = 0x00000001 +const USB_H_DATATGLERR2_S = 10 +const USB_H_BNAINTR2_V = 0x00000001 +const USB_H_BNAINTR2_S = 11 +const USB_H_XCS_XACT_ERR2_V = 0x00000001 +const USB_H_XCS_XACT_ERR2_S = 12 +const USB_H_DESC_LST_ROLLINTR2_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTR2_S = 13 +const USB_H_XFERCOMPLMSK2_V = 0x00000001 +const USB_H_XFERCOMPLMSK2_S = 0 +const USB_H_CHHLTDMSK2_V = 0x00000001 +const USB_H_CHHLTDMSK2_S = 1 +const USB_H_AHBERRMSK2_V = 0x00000001 +const USB_H_AHBERRMSK2_S = 2 +const USB_H_STALLMSK2_V = 0x00000001 +const USB_H_STALLMSK2_S = 3 +const USB_H_NAKMSK2_V = 0x00000001 +const USB_H_NAKMSK2_S = 4 +const USB_H_ACKMSK2_V = 0x00000001 +const USB_H_ACKMSK2_S = 5 +const USB_H_NYETMSK2_V = 0x00000001 +const USB_H_NYETMSK2_S = 6 +const USB_H_XACTERRMSK2_V = 0x00000001 +const USB_H_XACTERRMSK2_S = 7 +const USB_H_BBLERRMSK2_V = 0x00000001 +const USB_H_BBLERRMSK2_S = 8 +const USB_H_FRMOVRUNMSK2_V = 0x00000001 +const USB_H_FRMOVRUNMSK2_S = 9 +const USB_H_DATATGLERRMSK2_V = 0x00000001 +const USB_H_DATATGLERRMSK2_S = 10 +const USB_H_BNAINTRMSK2_V = 0x00000001 +const USB_H_BNAINTRMSK2_S = 11 +const USB_H_DESC_LST_ROLLINTRMSK2_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTRMSK2_S = 13 +const USB_H_XFERCOMPL3_V = 0x00000001 +const USB_H_XFERCOMPL3_S = 0 +const USB_H_CHHLTD3_V = 0x00000001 +const USB_H_CHHLTD3_S = 1 +const USB_H_AHBERR3_V = 0x00000001 +const USB_H_AHBERR3_S = 2 +const USB_H_STALL3_V = 0x00000001 +const USB_H_STALL3_S = 3 +const USB_H_NACK3_V = 0x00000001 +const USB_H_NACK3_S = 4 +const USB_H_ACK3_V = 0x00000001 +const USB_H_ACK3_S = 5 +const USB_H_NYET3_V = 0x00000001 +const USB_H_NYET3_S = 6 +const USB_H_XACTERR3_V = 0x00000001 +const USB_H_XACTERR3_S = 7 +const USB_H_BBLERR3_V = 0x00000001 +const USB_H_BBLERR3_S = 8 +const USB_H_FRMOVRUN3_V = 0x00000001 +const USB_H_FRMOVRUN3_S = 9 +const USB_H_DATATGLERR3_V = 0x00000001 +const USB_H_DATATGLERR3_S = 10 +const USB_H_BNAINTR3_V = 0x00000001 +const USB_H_BNAINTR3_S = 11 +const USB_H_XCS_XACT_ERR3_V = 0x00000001 +const USB_H_XCS_XACT_ERR3_S = 12 +const USB_H_DESC_LST_ROLLINTR3_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTR3_S = 13 +const USB_H_XFERCOMPLMSK3_V = 0x00000001 +const USB_H_XFERCOMPLMSK3_S = 0 +const USB_H_CHHLTDMSK3_V = 0x00000001 +const USB_H_CHHLTDMSK3_S = 1 +const USB_H_AHBERRMSK3_V = 0x00000001 +const USB_H_AHBERRMSK3_S = 2 +const USB_H_STALLMSK3_V = 0x00000001 +const USB_H_STALLMSK3_S = 3 +const USB_H_NAKMSK3_V = 0x00000001 +const USB_H_NAKMSK3_S = 4 +const USB_H_ACKMSK3_V = 0x00000001 +const USB_H_ACKMSK3_S = 5 +const USB_H_NYETMSK3_V = 0x00000001 +const USB_H_NYETMSK3_S = 6 +const USB_H_XACTERRMSK3_V = 0x00000001 +const USB_H_XACTERRMSK3_S = 7 +const USB_H_BBLERRMSK3_V = 0x00000001 +const USB_H_BBLERRMSK3_S = 8 +const USB_H_FRMOVRUNMSK3_V = 0x00000001 +const USB_H_FRMOVRUNMSK3_S = 9 +const USB_H_DATATGLERRMSK3_V = 0x00000001 +const USB_H_DATATGLERRMSK3_S = 10 +const USB_H_BNAINTRMSK3_V = 0x00000001 +const USB_H_BNAINTRMSK3_S = 11 +const USB_H_DESC_LST_ROLLINTRMSK3_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTRMSK3_S = 13 +const USB_H_XFERCOMPL4_V = 0x00000001 +const USB_H_XFERCOMPL4_S = 0 +const USB_H_CHHLTD4_V = 0x00000001 +const USB_H_CHHLTD4_S = 1 +const USB_H_AHBERR4_V = 0x00000001 +const USB_H_AHBERR4_S = 2 +const USB_H_STALL4_V = 0x00000001 +const USB_H_STALL4_S = 3 +const USB_H_NACK4_V = 0x00000001 +const USB_H_NACK4_S = 4 +const USB_H_ACK4_V = 0x00000001 +const USB_H_ACK4_S = 5 +const USB_H_NYET4_V = 0x00000001 +const USB_H_NYET4_S = 6 +const USB_H_XACTERR4_V = 0x00000001 +const USB_H_XACTERR4_S = 7 +const USB_H_BBLERR4_V = 0x00000001 +const USB_H_BBLERR4_S = 8 +const USB_H_FRMOVRUN4_V = 0x00000001 +const USB_H_FRMOVRUN4_S = 9 +const USB_H_DATATGLERR4_V = 0x00000001 +const USB_H_DATATGLERR4_S = 10 +const USB_H_BNAINTR4_V = 0x00000001 +const USB_H_BNAINTR4_S = 11 +const USB_H_XCS_XACT_ERR4_V = 0x00000001 +const USB_H_XCS_XACT_ERR4_S = 12 +const USB_H_DESC_LST_ROLLINTR4_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTR4_S = 13 +const USB_H_XFERCOMPLMSK4_V = 0x00000001 +const USB_H_XFERCOMPLMSK4_S = 0 +const USB_H_CHHLTDMSK4_V = 0x00000001 +const USB_H_CHHLTDMSK4_S = 1 +const USB_H_AHBERRMSK4_V = 0x00000001 +const USB_H_AHBERRMSK4_S = 2 +const USB_H_STALLMSK4_V = 0x00000001 +const USB_H_STALLMSK4_S = 3 +const USB_H_NAKMSK4_V = 0x00000001 +const USB_H_NAKMSK4_S = 4 +const USB_H_ACKMSK4_V = 0x00000001 +const USB_H_ACKMSK4_S = 5 +const USB_H_NYETMSK4_V = 0x00000001 +const USB_H_NYETMSK4_S = 6 +const USB_H_XACTERRMSK4_V = 0x00000001 +const USB_H_XACTERRMSK4_S = 7 +const USB_H_BBLERRMSK4_V = 0x00000001 +const USB_H_BBLERRMSK4_S = 8 +const USB_H_FRMOVRUNMSK4_V = 0x00000001 +const USB_H_FRMOVRUNMSK4_S = 9 +const USB_H_DATATGLERRMSK4_V = 0x00000001 +const USB_H_DATATGLERRMSK4_S = 10 +const USB_H_BNAINTRMSK4_V = 0x00000001 +const USB_H_BNAINTRMSK4_S = 11 +const USB_H_DESC_LST_ROLLINTRMSK4_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTRMSK4_S = 13 +const USB_H_XFERCOMPL5_V = 0x00000001 +const USB_H_XFERCOMPL5_S = 0 +const USB_H_CHHLTD5_V = 0x00000001 +const USB_H_CHHLTD5_S = 1 +const USB_H_AHBERR5_V = 0x00000001 +const USB_H_AHBERR5_S = 2 +const USB_H_STALL5_V = 0x00000001 +const USB_H_STALL5_S = 3 +const USB_H_NACK5_V = 0x00000001 +const USB_H_NACK5_S = 4 +const USB_H_ACK5_V = 0x00000001 +const USB_H_ACK5_S = 5 +const USB_H_NYET5_V = 0x00000001 +const USB_H_NYET5_S = 6 +const USB_H_XACTERR5_V = 0x00000001 +const USB_H_XACTERR5_S = 7 +const USB_H_BBLERR5_V = 0x00000001 +const USB_H_BBLERR5_S = 8 +const USB_H_FRMOVRUN5_V = 0x00000001 +const USB_H_FRMOVRUN5_S = 9 +const USB_H_DATATGLERR5_V = 0x00000001 +const USB_H_DATATGLERR5_S = 10 +const USB_H_BNAINTR5_V = 0x00000001 +const USB_H_BNAINTR5_S = 11 +const USB_H_XCS_XACT_ERR5_V = 0x00000001 +const USB_H_XCS_XACT_ERR5_S = 12 +const USB_H_DESC_LST_ROLLINTR5_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTR5_S = 13 +const USB_H_XFERCOMPLMSK5_V = 0x00000001 +const USB_H_XFERCOMPLMSK5_S = 0 +const USB_H_CHHLTDMSK5_V = 0x00000001 +const USB_H_CHHLTDMSK5_S = 1 +const USB_H_AHBERRMSK5_V = 0x00000001 +const USB_H_AHBERRMSK5_S = 2 +const USB_H_STALLMSK5_V = 0x00000001 +const USB_H_STALLMSK5_S = 3 +const USB_H_NAKMSK5_V = 0x00000001 +const USB_H_NAKMSK5_S = 4 +const USB_H_ACKMSK5_V = 0x00000001 +const USB_H_ACKMSK5_S = 5 +const USB_H_NYETMSK5_V = 0x00000001 +const USB_H_NYETMSK5_S = 6 +const USB_H_XACTERRMSK5_V = 0x00000001 +const USB_H_XACTERRMSK5_S = 7 +const USB_H_BBLERRMSK5_V = 0x00000001 +const USB_H_BBLERRMSK5_S = 8 +const USB_H_FRMOVRUNMSK5_V = 0x00000001 +const USB_H_FRMOVRUNMSK5_S = 9 +const USB_H_DATATGLERRMSK5_V = 0x00000001 +const USB_H_DATATGLERRMSK5_S = 10 +const USB_H_BNAINTRMSK5_V = 0x00000001 +const USB_H_BNAINTRMSK5_S = 11 +const USB_H_DESC_LST_ROLLINTRMSK5_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTRMSK5_S = 13 +const USB_H_XFERCOMPL6_V = 0x00000001 +const USB_H_XFERCOMPL6_S = 0 +const USB_H_CHHLTD6_V = 0x00000001 +const USB_H_CHHLTD6_S = 1 +const USB_H_AHBERR6_V = 0x00000001 +const USB_H_AHBERR6_S = 2 +const USB_H_STALL6_V = 0x00000001 +const USB_H_STALL6_S = 3 +const USB_H_NACK6_V = 0x00000001 +const USB_H_NACK6_S = 4 +const USB_H_ACK6_V = 0x00000001 +const USB_H_ACK6_S = 5 +const USB_H_NYET6_V = 0x00000001 +const USB_H_NYET6_S = 6 +const USB_H_XACTERR6_V = 0x00000001 +const USB_H_XACTERR6_S = 7 +const USB_H_BBLERR6_V = 0x00000001 +const USB_H_BBLERR6_S = 8 +const USB_H_FRMOVRUN6_V = 0x00000001 +const USB_H_FRMOVRUN6_S = 9 +const USB_H_DATATGLERR6_V = 0x00000001 +const USB_H_DATATGLERR6_S = 10 +const USB_H_BNAINTR6_V = 0x00000001 +const USB_H_BNAINTR6_S = 11 +const USB_H_XCS_XACT_ERR6_V = 0x00000001 +const USB_H_XCS_XACT_ERR6_S = 12 +const USB_H_DESC_LST_ROLLINTR6_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTR6_S = 13 +const USB_H_XFERCOMPLMSK6_V = 0x00000001 +const USB_H_XFERCOMPLMSK6_S = 0 +const USB_H_CHHLTDMSK6_V = 0x00000001 +const USB_H_CHHLTDMSK6_S = 1 +const USB_H_AHBERRMSK6_V = 0x00000001 +const USB_H_AHBERRMSK6_S = 2 +const USB_H_STALLMSK6_V = 0x00000001 +const USB_H_STALLMSK6_S = 3 +const USB_H_NAKMSK6_V = 0x00000001 +const USB_H_NAKMSK6_S = 4 +const USB_H_ACKMSK6_V = 0x00000001 +const USB_H_ACKMSK6_S = 5 +const USB_H_NYETMSK6_V = 0x00000001 +const USB_H_NYETMSK6_S = 6 +const USB_H_XACTERRMSK6_V = 0x00000001 +const USB_H_XACTERRMSK6_S = 7 +const USB_H_BBLERRMSK6_V = 0x00000001 +const USB_H_BBLERRMSK6_S = 8 +const USB_H_FRMOVRUNMSK6_V = 0x00000001 +const USB_H_FRMOVRUNMSK6_S = 9 +const USB_H_DATATGLERRMSK6_V = 0x00000001 +const USB_H_DATATGLERRMSK6_S = 10 +const USB_H_BNAINTRMSK6_V = 0x00000001 +const USB_H_BNAINTRMSK6_S = 11 +const USB_H_DESC_LST_ROLLINTRMSK6_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTRMSK6_S = 13 +const USB_H_XFERCOMPL7_V = 0x00000001 +const USB_H_XFERCOMPL7_S = 0 +const USB_H_CHHLTD7_V = 0x00000001 +const USB_H_CHHLTD7_S = 1 +const USB_H_AHBERR7_V = 0x00000001 +const USB_H_AHBERR7_S = 2 +const USB_H_STALL7_V = 0x00000001 +const USB_H_STALL7_S = 3 +const USB_H_NACK7_V = 0x00000001 +const USB_H_NACK7_S = 4 +const USB_H_ACK7_V = 0x00000001 +const USB_H_ACK7_S = 5 +const USB_H_NYET7_V = 0x00000001 +const USB_H_NYET7_S = 6 +const USB_H_XACTERR7_V = 0x00000001 +const USB_H_XACTERR7_S = 7 +const USB_H_BBLERR7_V = 0x00000001 +const USB_H_BBLERR7_S = 8 +const USB_H_FRMOVRUN7_V = 0x00000001 +const USB_H_FRMOVRUN7_S = 9 +const USB_H_DATATGLERR7_V = 0x00000001 +const USB_H_DATATGLERR7_S = 10 +const USB_H_BNAINTR7_V = 0x00000001 +const USB_H_BNAINTR7_S = 11 +const USB_H_XCS_XACT_ERR7_V = 0x00000001 +const USB_H_XCS_XACT_ERR7_S = 12 +const USB_H_DESC_LST_ROLLINTR7_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTR7_S = 13 +const USB_H_XFERCOMPLMSK7_V = 0x00000001 +const USB_H_XFERCOMPLMSK7_S = 0 +const USB_H_CHHLTDMSK7_V = 0x00000001 +const USB_H_CHHLTDMSK7_S = 1 +const USB_H_AHBERRMSK7_V = 0x00000001 +const USB_H_AHBERRMSK7_S = 2 +const USB_H_STALLMSK7_V = 0x00000001 +const USB_H_STALLMSK7_S = 3 +const USB_H_NAKMSK7_V = 0x00000001 +const USB_H_NAKMSK7_S = 4 +const USB_H_ACKMSK7_V = 0x00000001 +const USB_H_ACKMSK7_S = 5 +const USB_H_NYETMSK7_V = 0x00000001 +const USB_H_NYETMSK7_S = 6 +const USB_H_XACTERRMSK7_V = 0x00000001 +const USB_H_XACTERRMSK7_S = 7 +const USB_H_BBLERRMSK7_V = 0x00000001 +const USB_H_BBLERRMSK7_S = 8 +const USB_H_FRMOVRUNMSK7_V = 0x00000001 +const USB_H_FRMOVRUNMSK7_S = 9 +const USB_H_DATATGLERRMSK7_V = 0x00000001 +const USB_H_DATATGLERRMSK7_S = 10 +const USB_H_BNAINTRMSK7_V = 0x00000001 +const USB_H_BNAINTRMSK7_S = 11 +const USB_H_DESC_LST_ROLLINTRMSK7_V = 0x00000001 +const USB_H_DESC_LST_ROLLINTRMSK7_S = 13 +const USB_DI_XFERCOMPLMSK_V = 0x00000001 +const USB_DI_XFERCOMPLMSK_S = 0 +const USB_DI_EPDISBLDMSK_V = 0x00000001 +const USB_DI_EPDISBLDMSK_S = 1 +const USB_DI_AHBERMSK_V = 0x00000001 +const USB_DI_AHBERMSK_S = 2 +const USB_TIMEOUTMSK_V = 0x00000001 +const USB_TIMEOUTMSK_S = 3 +const USB_INTKNTXFEMPMSK_V = 0x00000001 +const USB_INTKNTXFEMPMSK_S = 4 +const USB_INTKNEPMISMSK_V = 0x00000001 +const USB_INTKNEPMISMSK_S = 5 +const USB_INEPNAKEFFMSK_V = 0x00000001 +const USB_INEPNAKEFFMSK_S = 6 +const USB_TXFIFOUNDRNMSK_V = 0x00000001 +const USB_TXFIFOUNDRNMSK_S = 8 +const USB_BNAININTRMSK_V = 0x00000001 +const USB_BNAININTRMSK_S = 9 +const USB_DI_NAKMSK_V = 0x00000001 +const USB_DI_NAKMSK_S = 13 +const USB_XFERCOMPLMSK_V = 0x00000001 +const USB_XFERCOMPLMSK_S = 0 +const USB_EPDISBLDMSK_V = 0x00000001 +const USB_EPDISBLDMSK_S = 1 +const USB_AHBERMSK_V = 0x00000001 +const USB_AHBERMSK_S = 2 +const USB_SETUPMSK_V = 0x00000001 +const USB_SETUPMSK_S = 3 +const USB_OUTTKNEPDISMSK_V = 0x00000001 +const USB_OUTTKNEPDISMSK_S = 4 +const USB_STSPHSERCVDMSK_V = 0x00000001 +const USB_STSPHSERCVDMSK_S = 5 +const USB_BACK2BACKSETUP_V = 0x00000001 +const USB_BACK2BACKSETUP_S = 6 +const USB_OUTPKTERRMSK_V = 0x00000001 +const USB_OUTPKTERRMSK_S = 8 +const USB_BNAOUTINTRMSK_V = 0x00000001 +const USB_BNAOUTINTRMSK_S = 9 +const USB_BBLEERRMSK_V = 0x00000001 +const USB_BBLEERRMSK_S = 12 +const USB_NAKMSK_V = 0x00000001 +const USB_NAKMSK_S = 13 +const USB_NYETMSK_V = 0x00000001 +const USB_NYETMSK_S = 14 +const USB_INEPINT0_V = 0x00000001 +const USB_INEPINT0_S = 0 +const USB_INEPINT1_V = 0x00000001 +const USB_INEPINT1_S = 1 +const USB_INEPINT2_V = 0x00000001 +const USB_INEPINT2_S = 2 +const USB_INEPINT3_V = 0x00000001 +const USB_INEPINT3_S = 3 +const USB_INEPINT4_V = 0x00000001 +const USB_INEPINT4_S = 4 +const USB_INEPINT5_V = 0x00000001 +const USB_INEPINT5_S = 5 +const USB_INEPINT6_V = 0x00000001 +const USB_INEPINT6_S = 6 +const USB_OUTEPINT0_V = 0x00000001 +const USB_OUTEPINT0_S = 16 +const USB_OUTEPINT1_V = 0x00000001 +const USB_OUTEPINT1_S = 17 +const USB_OUTEPINT2_V = 0x00000001 +const USB_OUTEPINT2_S = 18 +const USB_OUTEPINT3_V = 0x00000001 +const USB_OUTEPINT3_S = 19 +const USB_OUTEPINT4_V = 0x00000001 +const USB_OUTEPINT4_S = 20 +const USB_OUTEPINT5_V = 0x00000001 +const USB_OUTEPINT5_S = 21 +const USB_OUTEPINT6_V = 0x00000001 +const USB_OUTEPINT6_S = 22 +const USB_INEPMSK0_V = 0x00000001 +const USB_INEPMSK0_S = 0 +const USB_INEPMSK1_V = 0x00000001 +const USB_INEPMSK1_S = 1 +const USB_INEPMSK2_V = 0x00000001 +const USB_INEPMSK2_S = 2 +const USB_INEPMSK3_V = 0x00000001 +const USB_INEPMSK3_S = 3 +const USB_INEPMSK4_V = 0x00000001 +const USB_INEPMSK4_S = 4 +const USB_INEPMSK5_V = 0x00000001 +const USB_INEPMSK5_S = 5 +const USB_INEPMSK6_V = 0x00000001 +const USB_INEPMSK6_S = 6 +const USB_OUTEPMSK0_V = 0x00000001 +const USB_OUTEPMSK0_S = 16 +const USB_OUTEPMSK1_V = 0x00000001 +const USB_OUTEPMSK1_S = 17 +const USB_OUTEPMSK2_V = 0x00000001 +const USB_OUTEPMSK2_S = 18 +const USB_OUTEPMSK3_V = 0x00000001 +const USB_OUTEPMSK3_S = 19 +const USB_OUTEPMSK4_V = 0x00000001 +const USB_OUTEPMSK4_S = 20 +const USB_OUTEPMSK5_V = 0x00000001 +const USB_OUTEPMSK5_S = 21 +const USB_OUTEPMSK6_V = 0x00000001 +const USB_OUTEPMSK6_S = 22 +const USB_D_INEPTXFEMPMSK = 0x0000FFFF +const USB_D_INEPTXFEMPMSK_V = 0x0000FFFF +const USB_D_INEPTXFEMPMSK_S = 0 +const USB_D_XFERCOMPL0_V = 0x00000001 +const USB_D_XFERCOMPL0_S = 0 +const USB_D_EPDISBLD0_V = 0x00000001 +const USB_D_EPDISBLD0_S = 1 +const USB_D_AHBERR0_V = 0x00000001 +const USB_D_AHBERR0_S = 2 +const USB_D_TIMEOUT0_V = 0x00000001 +const USB_D_TIMEOUT0_S = 3 +const USB_D_INTKNTXFEMP0_V = 0x00000001 +const USB_D_INTKNTXFEMP0_S = 4 +const USB_D_INTKNEPMIS0_V = 0x00000001 +const USB_D_INTKNEPMIS0_S = 5 +const USB_D_INEPNAKEFF0_V = 0x00000001 +const USB_D_INEPNAKEFF0_S = 6 +const USB_D_TXFEMP0_V = 0x00000001 +const USB_D_TXFEMP0_S = 7 +const USB_D_TXFIFOUNDRN0_V = 0x00000001 +const USB_D_TXFIFOUNDRN0_S = 8 +const USB_D_BNAINTR0_V = 0x00000001 +const USB_D_BNAINTR0_S = 9 +const USB_D_PKTDRPSTS0_V = 0x00000001 +const USB_D_PKTDRPSTS0_S = 11 +const USB_D_BBLEERR0_V = 0x00000001 +const USB_D_BBLEERR0_S = 12 +const USB_D_NAKINTRPT0_V = 0x00000001 +const USB_D_NAKINTRPT0_S = 13 +const USB_D_NYETINTRPT0_V = 0x00000001 +const USB_D_NYETINTRPT0_S = 14 +const USB_D_XFERCOMPL1_V = 0x00000001 +const USB_D_XFERCOMPL1_S = 0 +const USB_D_EPDISBLD1_V = 0x00000001 +const USB_D_EPDISBLD1_S = 1 +const USB_D_AHBERR1_V = 0x00000001 +const USB_D_AHBERR1_S = 2 +const USB_D_TIMEOUT1_V = 0x00000001 +const USB_D_TIMEOUT1_S = 3 +const USB_D_INTKNTXFEMP1_V = 0x00000001 +const USB_D_INTKNTXFEMP1_S = 4 +const USB_D_INTKNEPMIS1_V = 0x00000001 +const USB_D_INTKNEPMIS1_S = 5 +const USB_D_INEPNAKEFF1_V = 0x00000001 +const USB_D_INEPNAKEFF1_S = 6 +const USB_D_TXFEMP1_V = 0x00000001 +const USB_D_TXFEMP1_S = 7 +const USB_D_TXFIFOUNDRN1_V = 0x00000001 +const USB_D_TXFIFOUNDRN1_S = 8 +const USB_D_BNAINTR1_V = 0x00000001 +const USB_D_BNAINTR1_S = 9 +const USB_D_PKTDRPSTS1_V = 0x00000001 +const USB_D_PKTDRPSTS1_S = 11 +const USB_D_BBLEERR1_V = 0x00000001 +const USB_D_BBLEERR1_S = 12 +const USB_D_NAKINTRPT1_V = 0x00000001 +const USB_D_NAKINTRPT1_S = 13 +const USB_D_NYETINTRPT1_V = 0x00000001 +const USB_D_NYETINTRPT1_S = 14 +const USB_D_XFERCOMPL2_V = 0x00000001 +const USB_D_XFERCOMPL2_S = 0 +const USB_D_EPDISBLD2_V = 0x00000001 +const USB_D_EPDISBLD2_S = 1 +const USB_D_AHBERR2_V = 0x00000001 +const USB_D_AHBERR2_S = 2 +const USB_D_TIMEOUT2_V = 0x00000001 +const USB_D_TIMEOUT2_S = 3 +const USB_D_INTKNTXFEMP2_V = 0x00000001 +const USB_D_INTKNTXFEMP2_S = 4 +const USB_D_INTKNEPMIS2_V = 0x00000001 +const USB_D_INTKNEPMIS2_S = 5 +const USB_D_INEPNAKEFF2_V = 0x00000001 +const USB_D_INEPNAKEFF2_S = 6 +const USB_D_TXFEMP2_V = 0x00000001 +const USB_D_TXFEMP2_S = 7 +const USB_D_TXFIFOUNDRN2_V = 0x00000001 +const USB_D_TXFIFOUNDRN2_S = 8 +const USB_D_BNAINTR2_V = 0x00000001 +const USB_D_BNAINTR2_S = 9 +const USB_D_PKTDRPSTS2_V = 0x00000001 +const USB_D_PKTDRPSTS2_S = 11 +const USB_D_BBLEERR2_V = 0x00000001 +const USB_D_BBLEERR2_S = 12 +const USB_D_NAKINTRPT2_V = 0x00000001 +const USB_D_NAKINTRPT2_S = 13 +const USB_D_NYETINTRPT2_V = 0x00000001 +const USB_D_NYETINTRPT2_S = 14 +const USB_D_XFERCOMPL3_V = 0x00000001 +const USB_D_XFERCOMPL3_S = 0 +const USB_D_EPDISBLD3_V = 0x00000001 +const USB_D_EPDISBLD3_S = 1 +const USB_D_AHBERR3_V = 0x00000001 +const USB_D_AHBERR3_S = 2 +const USB_D_TIMEOUT3_V = 0x00000001 +const USB_D_TIMEOUT3_S = 3 +const USB_D_INTKNTXFEMP3_V = 0x00000001 +const USB_D_INTKNTXFEMP3_S = 4 +const USB_D_INTKNEPMIS3_V = 0x00000001 +const USB_D_INTKNEPMIS3_S = 5 +const USB_D_INEPNAKEFF3_V = 0x00000001 +const USB_D_INEPNAKEFF3_S = 6 +const USB_D_TXFEMP3_V = 0x00000001 +const USB_D_TXFEMP3_S = 7 +const USB_D_TXFIFOUNDRN3_V = 0x00000001 +const USB_D_TXFIFOUNDRN3_S = 8 +const USB_D_BNAINTR3_V = 0x00000001 +const USB_D_BNAINTR3_S = 9 +const USB_D_PKTDRPSTS3_V = 0x00000001 +const USB_D_PKTDRPSTS3_S = 11 +const USB_D_BBLEERR3_V = 0x00000001 +const USB_D_BBLEERR3_S = 12 +const USB_D_NAKINTRPT3_V = 0x00000001 +const USB_D_NAKINTRPT3_S = 13 +const USB_D_NYETINTRPT3_V = 0x00000001 +const USB_D_NYETINTRPT3_S = 14 +const USB_D_XFERCOMPL4_V = 0x00000001 +const USB_D_XFERCOMPL4_S = 0 +const USB_D_EPDISBLD4_V = 0x00000001 +const USB_D_EPDISBLD4_S = 1 +const USB_D_AHBERR4_V = 0x00000001 +const USB_D_AHBERR4_S = 2 +const USB_D_TIMEOUT4_V = 0x00000001 +const USB_D_TIMEOUT4_S = 3 +const USB_D_INTKNTXFEMP4_V = 0x00000001 +const USB_D_INTKNTXFEMP4_S = 4 +const USB_D_INTKNEPMIS4_V = 0x00000001 +const USB_D_INTKNEPMIS4_S = 5 +const USB_D_INEPNAKEFF4_V = 0x00000001 +const USB_D_INEPNAKEFF4_S = 6 +const USB_D_TXFEMP4_V = 0x00000001 +const USB_D_TXFEMP4_S = 7 +const USB_D_TXFIFOUNDRN4_V = 0x00000001 +const USB_D_TXFIFOUNDRN4_S = 8 +const USB_D_BNAINTR4_V = 0x00000001 +const USB_D_BNAINTR4_S = 9 +const USB_D_PKTDRPSTS4_V = 0x00000001 +const USB_D_PKTDRPSTS4_S = 11 +const USB_D_BBLEERR4_V = 0x00000001 +const USB_D_BBLEERR4_S = 12 +const USB_D_NAKINTRPT4_V = 0x00000001 +const USB_D_NAKINTRPT4_S = 13 +const USB_D_NYETINTRPT4_V = 0x00000001 +const USB_D_NYETINTRPT4_S = 14 +const USB_D_XFERCOMPL5_V = 0x00000001 +const USB_D_XFERCOMPL5_S = 0 +const USB_D_EPDISBLD5_V = 0x00000001 +const USB_D_EPDISBLD5_S = 1 +const USB_D_AHBERR5_V = 0x00000001 +const USB_D_AHBERR5_S = 2 +const USB_D_TIMEOUT5_V = 0x00000001 +const USB_D_TIMEOUT5_S = 3 +const USB_D_INTKNTXFEMP5_V = 0x00000001 +const USB_D_INTKNTXFEMP5_S = 4 +const USB_D_INTKNEPMIS5_V = 0x00000001 +const USB_D_INTKNEPMIS5_S = 5 +const USB_D_INEPNAKEFF5_V = 0x00000001 +const USB_D_INEPNAKEFF5_S = 6 +const USB_D_TXFEMP5_V = 0x00000001 +const USB_D_TXFEMP5_S = 7 +const USB_D_TXFIFOUNDRN5_V = 0x00000001 +const USB_D_TXFIFOUNDRN5_S = 8 +const USB_D_BNAINTR5_V = 0x00000001 +const USB_D_BNAINTR5_S = 9 +const USB_D_PKTDRPSTS5_V = 0x00000001 +const USB_D_PKTDRPSTS5_S = 11 +const USB_D_BBLEERR5_V = 0x00000001 +const USB_D_BBLEERR5_S = 12 +const USB_D_NAKINTRPT5_V = 0x00000001 +const USB_D_NAKINTRPT5_S = 13 +const USB_D_NYETINTRPT5_V = 0x00000001 +const USB_D_NYETINTRPT5_S = 14 +const USB_D_XFERCOMPL6_V = 0x00000001 +const USB_D_XFERCOMPL6_S = 0 +const USB_D_EPDISBLD6_V = 0x00000001 +const USB_D_EPDISBLD6_S = 1 +const USB_D_AHBERR6_V = 0x00000001 +const USB_D_AHBERR6_S = 2 +const USB_D_TIMEOUT6_V = 0x00000001 +const USB_D_TIMEOUT6_S = 3 +const USB_D_INTKNTXFEMP6_V = 0x00000001 +const USB_D_INTKNTXFEMP6_S = 4 +const USB_D_INTKNEPMIS6_V = 0x00000001 +const USB_D_INTKNEPMIS6_S = 5 +const USB_D_INEPNAKEFF6_V = 0x00000001 +const USB_D_INEPNAKEFF6_S = 6 +const USB_D_TXFEMP6_V = 0x00000001 +const USB_D_TXFEMP6_S = 7 +const USB_D_TXFIFOUNDRN6_V = 0x00000001 +const USB_D_TXFIFOUNDRN6_S = 8 +const USB_D_BNAINTR6_V = 0x00000001 +const USB_D_BNAINTR6_S = 9 +const USB_D_PKTDRPSTS6_V = 0x00000001 +const USB_D_PKTDRPSTS6_S = 11 +const USB_D_BBLEERR6_V = 0x00000001 +const USB_D_BBLEERR6_S = 12 +const USB_D_NAKINTRPT6_V = 0x00000001 +const USB_D_NAKINTRPT6_S = 13 +const USB_D_NYETINTRPT6_V = 0x00000001 +const USB_D_NYETINTRPT6_S = 14 +const USB_XFERCOMPL0_V = 0x00000001 +const USB_XFERCOMPL0_S = 0 +const USB_EPDISBLD0_V = 0x00000001 +const USB_EPDISBLD0_S = 1 +const USB_AHBERR0_V = 0x00000001 +const USB_AHBERR0_S = 2 +const USB_SETUP0_V = 0x00000001 +const USB_SETUP0_S = 3 +const USB_OUTTKNEPDIS0_V = 0x00000001 +const USB_OUTTKNEPDIS0_S = 4 +const USB_STSPHSERCVD0_V = 0x00000001 +const USB_STSPHSERCVD0_S = 5 +const USB_BACK2BACKSETUP0_V = 0x00000001 +const USB_BACK2BACKSETUP0_S = 6 +const USB_OUTPKTERR0_V = 0x00000001 +const USB_OUTPKTERR0_S = 8 +const USB_BNAINTR0_V = 0x00000001 +const USB_BNAINTR0_S = 9 +const USB_PKTDRPSTS0_V = 0x00000001 +const USB_PKTDRPSTS0_S = 11 +const USB_BBLEERR0_V = 0x00000001 +const USB_BBLEERR0_S = 12 +const USB_NAKINTRPT0_V = 0x00000001 +const USB_NAKINTRPT0_S = 13 +const USB_NYEPINTRPT0_V = 0x00000001 +const USB_NYEPINTRPT0_S = 14 +const USB_STUPPKTRCVD0_V = 0x00000001 +const USB_STUPPKTRCVD0_S = 15 +const USB_XFERCOMPL1_V = 0x00000001 +const USB_XFERCOMPL1_S = 0 +const USB_EPDISBLD1_V = 0x00000001 +const USB_EPDISBLD1_S = 1 +const USB_AHBERR1_V = 0x00000001 +const USB_AHBERR1_S = 2 +const USB_SETUP1_V = 0x00000001 +const USB_SETUP1_S = 3 +const USB_OUTTKNEPDIS1_V = 0x00000001 +const USB_OUTTKNEPDIS1_S = 4 +const USB_STSPHSERCVD1_V = 0x00000001 +const USB_STSPHSERCVD1_S = 5 +const USB_BACK2BACKSETUP1_V = 0x00000001 +const USB_BACK2BACKSETUP1_S = 6 +const USB_OUTPKTERR1_V = 0x00000001 +const USB_OUTPKTERR1_S = 8 +const USB_BNAINTR1_V = 0x00000001 +const USB_BNAINTR1_S = 9 +const USB_PKTDRPSTS1_V = 0x00000001 +const USB_PKTDRPSTS1_S = 11 +const USB_BBLEERR1_V = 0x00000001 +const USB_BBLEERR1_S = 12 +const USB_NAKINTRPT1_V = 0x00000001 +const USB_NAKINTRPT1_S = 13 +const USB_NYEPINTRPT1_V = 0x00000001 +const USB_NYEPINTRPT1_S = 14 +const USB_STUPPKTRCVD1_V = 0x00000001 +const USB_STUPPKTRCVD1_S = 15 +const USB_XFERCOMPL2_V = 0x00000001 +const USB_XFERCOMPL2_S = 0 +const USB_EPDISBLD2_V = 0x00000001 +const USB_EPDISBLD2_S = 1 +const USB_AHBERR2_V = 0x00000001 +const USB_AHBERR2_S = 2 +const USB_SETUP2_V = 0x00000001 +const USB_SETUP2_S = 3 +const USB_OUTTKNEPDIS2_V = 0x00000001 +const USB_OUTTKNEPDIS2_S = 4 +const USB_STSPHSERCVD2_V = 0x00000001 +const USB_STSPHSERCVD2_S = 5 +const USB_BACK2BACKSETUP2_V = 0x00000001 +const USB_BACK2BACKSETUP2_S = 6 +const USB_OUTPKTERR2_V = 0x00000001 +const USB_OUTPKTERR2_S = 8 +const USB_BNAINTR2_V = 0x00000001 +const USB_BNAINTR2_S = 9 +const USB_PKTDRPSTS2_V = 0x00000001 +const USB_PKTDRPSTS2_S = 11 +const USB_BBLEERR2_V = 0x00000001 +const USB_BBLEERR2_S = 12 +const USB_NAKINTRPT2_V = 0x00000001 +const USB_NAKINTRPT2_S = 13 +const USB_NYEPINTRPT2_V = 0x00000001 +const USB_NYEPINTRPT2_S = 14 +const USB_STUPPKTRCVD2_V = 0x00000001 +const USB_STUPPKTRCVD2_S = 15 +const USB_XFERCOMPL3_V = 0x00000001 +const USB_XFERCOMPL3_S = 0 +const USB_EPDISBLD3_V = 0x00000001 +const USB_EPDISBLD3_S = 1 +const USB_AHBERR3_V = 0x00000001 +const USB_AHBERR3_S = 2 +const USB_SETUP3_V = 0x00000001 +const USB_SETUP3_S = 3 +const USB_OUTTKNEPDIS3_V = 0x00000001 +const USB_OUTTKNEPDIS3_S = 4 +const USB_STSPHSERCVD3_V = 0x00000001 +const USB_STSPHSERCVD3_S = 5 +const USB_BACK2BACKSETUP3_V = 0x00000001 +const USB_BACK2BACKSETUP3_S = 6 +const USB_OUTPKTERR3_V = 0x00000001 +const USB_OUTPKTERR3_S = 8 +const USB_BNAINTR3_V = 0x00000001 +const USB_BNAINTR3_S = 9 +const USB_PKTDRPSTS3_V = 0x00000001 +const USB_PKTDRPSTS3_S = 11 +const USB_BBLEERR3_V = 0x00000001 +const USB_BBLEERR3_S = 12 +const USB_NAKINTRPT3_V = 0x00000001 +const USB_NAKINTRPT3_S = 13 +const USB_NYEPINTRPT3_V = 0x00000001 +const USB_NYEPINTRPT3_S = 14 +const USB_STUPPKTRCVD3_V = 0x00000001 +const USB_STUPPKTRCVD3_S = 15 +const USB_XFERCOMPL4_V = 0x00000001 +const USB_XFERCOMPL4_S = 0 +const USB_EPDISBLD4_V = 0x00000001 +const USB_EPDISBLD4_S = 1 +const USB_AHBERR4_V = 0x00000001 +const USB_AHBERR4_S = 2 +const USB_SETUP4_V = 0x00000001 +const USB_SETUP4_S = 3 +const USB_OUTTKNEPDIS4_V = 0x00000001 +const USB_OUTTKNEPDIS4_S = 4 +const USB_STSPHSERCVD4_V = 0x00000001 +const USB_STSPHSERCVD4_S = 5 +const USB_BACK2BACKSETUP4_V = 0x00000001 +const USB_BACK2BACKSETUP4_S = 6 +const USB_OUTPKTERR4_V = 0x00000001 +const USB_OUTPKTERR4_S = 8 +const USB_BNAINTR4_V = 0x00000001 +const USB_BNAINTR4_S = 9 +const USB_PKTDRPSTS4_V = 0x00000001 +const USB_PKTDRPSTS4_S = 11 +const USB_BBLEERR4_V = 0x00000001 +const USB_BBLEERR4_S = 12 +const USB_NAKINTRPT4_V = 0x00000001 +const USB_NAKINTRPT4_S = 13 +const USB_NYEPINTRPT4_V = 0x00000001 +const USB_NYEPINTRPT4_S = 14 +const USB_STUPPKTRCVD4_V = 0x00000001 +const USB_STUPPKTRCVD4_S = 15 +const USB_XFERCOMPL5_V = 0x00000001 +const USB_XFERCOMPL5_S = 0 +const USB_EPDISBLD5_V = 0x00000001 +const USB_EPDISBLD5_S = 1 +const USB_AHBERR5_V = 0x00000001 +const USB_AHBERR5_S = 2 +const USB_SETUP5_V = 0x00000001 +const USB_SETUP5_S = 3 +const USB_OUTTKNEPDIS5_V = 0x00000001 +const USB_OUTTKNEPDIS5_S = 4 +const USB_STSPHSERCVD5_V = 0x00000001 +const USB_STSPHSERCVD5_S = 5 +const USB_BACK2BACKSETUP5_V = 0x00000001 +const USB_BACK2BACKSETUP5_S = 6 +const USB_OUTPKTERR5_V = 0x00000001 +const USB_OUTPKTERR5_S = 8 +const USB_BNAINTR5_V = 0x00000001 +const USB_BNAINTR5_S = 9 +const USB_PKTDRPSTS5_V = 0x00000001 +const USB_PKTDRPSTS5_S = 11 +const USB_BBLEERR5_V = 0x00000001 +const USB_BBLEERR5_S = 12 +const USB_NAKINTRPT5_V = 0x00000001 +const USB_NAKINTRPT5_S = 13 +const USB_NYEPINTRPT5_V = 0x00000001 +const USB_NYEPINTRPT5_S = 14 +const USB_STUPPKTRCVD5_V = 0x00000001 +const USB_STUPPKTRCVD5_S = 15 +const USB_XFERCOMPL6_V = 0x00000001 +const USB_XFERCOMPL6_S = 0 +const USB_EPDISBLD6_V = 0x00000001 +const USB_EPDISBLD6_S = 1 +const USB_AHBERR6_V = 0x00000001 +const USB_AHBERR6_S = 2 +const USB_SETUP6_V = 0x00000001 +const USB_SETUP6_S = 3 +const USB_OUTTKNEPDIS6_V = 0x00000001 +const USB_OUTTKNEPDIS6_S = 4 +const USB_STSPHSERCVD6_V = 0x00000001 +const USB_STSPHSERCVD6_S = 5 +const USB_BACK2BACKSETUP6_V = 0x00000001 +const USB_BACK2BACKSETUP6_S = 6 +const USB_OUTPKTERR6_V = 0x00000001 +const USB_OUTPKTERR6_S = 8 +const USB_BNAINTR6_V = 0x00000001 +const USB_BNAINTR6_S = 9 +const USB_PKTDRPSTS6_V = 0x00000001 +const USB_PKTDRPSTS6_S = 11 +const USB_BBLEERR6_V = 0x00000001 +const USB_BBLEERR6_S = 12 +const USB_NAKINTRPT6_V = 0x00000001 +const USB_NAKINTRPT6_S = 13 +const USB_NYEPINTRPT6_V = 0x00000001 +const USB_NYEPINTRPT6_S = 14 +const USB_STUPPKTRCVD6_V = 0x00000001 +const USB_STUPPKTRCVD6_S = 15 +const USB_GLBLLNTRMSK_V = 0x00000001 +const USB_GLBLLNTRMSK_S = 0 +const USB_HBSTLEN = 0x0000000F +const USB_HBSTLEN_V = 0x0000000F +const USB_HBSTLEN_S = 1 +const USB_DMAEN_V = 0x00000001 +const USB_DMAEN_S = 5 +const USB_NPTXFEMPLVL_V = 0x00000001 +const USB_NPTXFEMPLVL_S = 7 +const USB_PTXFEMPLVL_V = 0x00000001 +const USB_PTXFEMPLVL_S = 8 +const USB_REMMEMSUPP_V = 0x00000001 +const USB_REMMEMSUPP_S = 21 +const USB_NOTIALLDMAWRIT_V = 0x00000001 +const USB_NOTIALLDMAWRIT_S = 22 +const USB_AHBSINGLE_V = 0x00000001 +const USB_AHBSINGLE_S = 23 +const USB_INVDESCENDIANESS_V = 0x00000001 +const USB_INVDESCENDIANESS_S = 24 +const USB_TOUTCAL = 0x00000007 +const USB_TOUTCAL_V = 0x00000007 +const USB_TOUTCAL_S = 0 +const USB_PHYIF_V = 0x00000001 +const USB_PHYIF_S = 3 +const USB_ULPI_UTMI_SEL_V = 0x00000001 +const USB_ULPI_UTMI_SEL_S = 4 +const USB_FSINTF_V = 0x00000001 +const USB_FSINTF_S = 5 +const USB_PHYSEL_V = 0x00000001 +const USB_PHYSEL_S = 6 +const USB_SRPCAP_V = 0x00000001 +const USB_SRPCAP_S = 8 +const USB_HNPCAP_V = 0x00000001 +const USB_HNPCAP_S = 9 +const USB_USBTRDTIM = 0x0000000F +const USB_USBTRDTIM_V = 0x0000000F +const USB_USBTRDTIM_S = 10 +const USB_TERMSELDLPULSE_V = 0x00000001 +const USB_TERMSELDLPULSE_S = 22 +const USB_TXENDDELAY_V = 0x00000001 +const USB_TXENDDELAY_S = 28 +const USB_FORCEHSTMODE_V = 0x00000001 +const USB_FORCEHSTMODE_S = 29 +const USB_FORCEDEVMODE_V = 0x00000001 +const USB_FORCEDEVMODE_S = 30 +const USB_CORRUPTTXPKT_V = 0x00000001 +const USB_CORRUPTTXPKT_S = 31 +const USB_CSFTRST_V = 0x00000001 +const USB_CSFTRST_S = 0 +const USB_PIUFSSFTRST_V = 0x00000001 +const USB_PIUFSSFTRST_S = 1 +const USB_FRMCNTRRST_V = 0x00000001 +const USB_FRMCNTRRST_S = 2 +const USB_RXFFLSH_V = 0x00000001 +const USB_RXFFLSH_S = 4 +const USB_TXFFLSH_V = 0x00000001 +const USB_TXFFLSH_S = 5 +const USB_TXFNUM = 0x0000001F +const USB_TXFNUM_V = 0x0000001F +const USB_TXFNUM_S = 6 +const USB_DMAREQ_V = 0x00000001 +const USB_DMAREQ_S = 30 +const USB_AHBIDLE_V = 0x00000001 +const USB_AHBIDLE_S = 31 +const USB_RXFDEP = 0x0000FFFF +const USB_RXFDEP_V = 0x0000FFFF +const USB_RXFDEP_S = 0 +const USB_NPTXFSTADDR = 0x0000FFFF +const USB_NPTXFSTADDR_V = 0x0000FFFF +const USB_NPTXFSTADDR_S = 0 +const USB_NPTXFDEP = 0x0000FFFF +const USB_NPTXFDEP_V = 0x0000FFFF +const USB_NPTXFDEP_S = 16 +const USB_NPTXFSPCAVAIL = 0x0000FFFF +const USB_NPTXFSPCAVAIL_V = 0x0000FFFF +const USB_NPTXFSPCAVAIL_S = 0 +const USB_NPTXQSPCAVAIL = 0x0000000F +const USB_NPTXQSPCAVAIL_V = 0x0000000F +const USB_NPTXQSPCAVAIL_S = 16 +const USB_NPTXQTOP = 0x0000007F +const USB_NPTXQTOP_V = 0x0000007F +const USB_NPTXQTOP_S = 24 +const USB_H_XFERSIZE0 = 0x0007FFFF +const USB_H_XFERSIZE0_V = 0x0007FFFF +const USB_H_XFERSIZE0_S = 0 +const USB_H_PKTCNT0 = 0x000003FF +const USB_H_PKTCNT0_V = 0x000003FF +const USB_H_PKTCNT0_S = 19 +const USB_H_PID0 = 0x00000003 +const USB_H_PID0_V = 0x00000003 +const USB_H_PID0_S = 29 +const USB_H_DOPNG0_V = 0x00000001 +const USB_H_DOPNG0_S = 31 +const USB_H_XFERSIZE1 = 0x0007FFFF +const USB_H_XFERSIZE1_V = 0x0007FFFF +const USB_H_XFERSIZE1_S = 0 +const USB_H_PKTCNT1 = 0x000003FF +const USB_H_PKTCNT1_V = 0x000003FF +const USB_H_PKTCNT1_S = 19 +const USB_H_PID1 = 0x00000003 +const USB_H_PID1_V = 0x00000003 +const USB_H_PID1_S = 29 +const USB_H_DOPNG1_V = 0x00000001 +const USB_H_DOPNG1_S = 31 +const USB_H_XFERSIZE2 = 0x0007FFFF +const USB_H_XFERSIZE2_V = 0x0007FFFF +const USB_H_XFERSIZE2_S = 0 +const USB_H_PKTCNT2 = 0x000003FF +const USB_H_PKTCNT2_V = 0x000003FF +const USB_H_PKTCNT2_S = 19 +const USB_H_PID2 = 0x00000003 +const USB_H_PID2_V = 0x00000003 +const USB_H_PID2_S = 29 +const USB_H_DOPNG2_V = 0x00000001 +const USB_H_DOPNG2_S = 31 +const USB_H_XFERSIZE3 = 0x0007FFFF +const USB_H_XFERSIZE3_V = 0x0007FFFF +const USB_H_XFERSIZE3_S = 0 +const USB_H_PKTCNT3 = 0x000003FF +const USB_H_PKTCNT3_V = 0x000003FF +const USB_H_PKTCNT3_S = 19 +const USB_H_PID3 = 0x00000003 +const USB_H_PID3_V = 0x00000003 +const USB_H_PID3_S = 29 +const USB_H_DOPNG3_V = 0x00000001 +const USB_H_DOPNG3_S = 31 +const USB_H_XFERSIZE4 = 0x0007FFFF +const USB_H_XFERSIZE4_V = 0x0007FFFF +const USB_H_XFERSIZE4_S = 0 +const USB_H_PKTCNT4 = 0x000003FF +const USB_H_PKTCNT4_V = 0x000003FF +const USB_H_PKTCNT4_S = 19 +const USB_H_PID4 = 0x00000003 +const USB_H_PID4_V = 0x00000003 +const USB_H_PID4_S = 29 +const USB_H_DOPNG4_V = 0x00000001 +const USB_H_DOPNG4_S = 31 +const USB_H_XFERSIZE5 = 0x0007FFFF +const USB_H_XFERSIZE5_V = 0x0007FFFF +const USB_H_XFERSIZE5_S = 0 +const USB_H_PKTCNT5 = 0x000003FF +const USB_H_PKTCNT5_V = 0x000003FF +const USB_H_PKTCNT5_S = 19 +const USB_H_PID5 = 0x00000003 +const USB_H_PID5_V = 0x00000003 +const USB_H_PID5_S = 29 +const USB_H_DOPNG5_V = 0x00000001 +const USB_H_DOPNG5_S = 31 +const USB_H_XFERSIZE6 = 0x0007FFFF +const USB_H_XFERSIZE6_V = 0x0007FFFF +const USB_H_XFERSIZE6_S = 0 +const USB_H_PKTCNT6 = 0x000003FF +const USB_H_PKTCNT6_V = 0x000003FF +const USB_H_PKTCNT6_S = 19 +const USB_H_PID6 = 0x00000003 +const USB_H_PID6_V = 0x00000003 +const USB_H_PID6_S = 29 +const USB_H_DOPNG6_V = 0x00000001 +const USB_H_DOPNG6_S = 31 +const USB_H_XFERSIZE7 = 0x0007FFFF +const USB_H_XFERSIZE7_V = 0x0007FFFF +const USB_H_XFERSIZE7_S = 0 +const USB_H_PKTCNT7 = 0x000003FF +const USB_H_PKTCNT7_V = 0x000003FF +const USB_H_PKTCNT7_S = 19 +const USB_H_PID7 = 0x00000003 +const USB_H_PID7_V = 0x00000003 +const USB_H_PID7_S = 29 +const USB_H_DOPNG7_V = 0x00000001 +const USB_H_DOPNG7_S = 31 +const USB_G_CHNUM = 0x0000000F +const USB_G_CHNUM_V = 0x0000000F +const USB_G_CHNUM_S = 0 +const USB_G_BCNT = 0x000007FF +const USB_G_BCNT_V = 0x000007FF +const USB_G_BCNT_S = 4 +const USB_G_DPID = 0x00000003 +const USB_G_DPID_V = 0x00000003 +const USB_G_DPID_S = 15 +const USB_G_PKTSTS = 0x0000000F +const USB_G_PKTSTS_V = 0x0000000F +const USB_G_PKTSTS_S = 17 +const USB_G_FN = 0x0000000F +const USB_G_FN_V = 0x0000000F +const USB_G_FN_S = 21 +const USB_CHNUM = 0x0000000F +const USB_CHNUM_V = 0x0000000F +const USB_CHNUM_S = 0 +const USB_BCNT = 0x000007FF +const USB_BCNT_V = 0x000007FF +const USB_BCNT_S = 4 +const USB_DPID = 0x00000003 +const USB_DPID_V = 0x00000003 +const USB_DPID_S = 15 +const USB_PKTSTS = 0x0000000F +const USB_PKTSTS_V = 0x0000000F +const USB_PKTSTS_S = 17 +const USB_FN = 0x0000000F +const USB_FN_V = 0x0000000F +const USB_FN_S = 21 +const USB_SYNOPSYSID = 0xFFFFFFFF +const USB_SYNOPSYSID_V = 0xFFFFFFFF +const USB_SYNOPSYSID_S = 0 +const USB_EPDIR = 0xFFFFFFFF +const USB_EPDIR_V = 0xFFFFFFFF +const USB_EPDIR_S = 0 +const USB_OTGMODE = 0x00000007 +const USB_OTGMODE_V = 0x00000007 +const USB_OTGMODE_S = 0 +const USB_OTGARCH = 0x00000003 +const USB_OTGARCH_V = 0x00000003 +const USB_OTGARCH_S = 3 +const USB_SINGPNT_V = 0x00000001 +const USB_SINGPNT_S = 5 +const USB_HSPHYTYPE = 0x00000003 +const USB_HSPHYTYPE_V = 0x00000003 +const USB_HSPHYTYPE_S = 6 +const USB_FSPHYTYPE = 0x00000003 +const USB_FSPHYTYPE_V = 0x00000003 +const USB_FSPHYTYPE_S = 8 +const USB_NUMDEVEPS = 0x0000000F +const USB_NUMDEVEPS_V = 0x0000000F +const USB_NUMDEVEPS_S = 10 +const USB_NUMHSTCHNL = 0x0000000F +const USB_NUMHSTCHNL_V = 0x0000000F +const USB_NUMHSTCHNL_S = 14 +const USB_PERIOSUPPORT_V = 0x00000001 +const USB_PERIOSUPPORT_S = 18 +const USB_DYNFIFOSIZING_V = 0x00000001 +const USB_DYNFIFOSIZING_S = 19 +const USB_MULTIPROCINTRPT_V = 0x00000001 +const USB_MULTIPROCINTRPT_S = 20 +const USB_NPTXQDEPTH = 0x00000003 +const USB_NPTXQDEPTH_V = 0x00000003 +const USB_NPTXQDEPTH_S = 22 +const USB_PTXQDEPTH = 0x00000003 +const USB_PTXQDEPTH_V = 0x00000003 +const USB_PTXQDEPTH_S = 24 +const USB_TKNQDEPTH = 0x0000001F +const USB_TKNQDEPTH_V = 0x0000001F +const USB_TKNQDEPTH_S = 26 +const USB_OTG_ENABLE_IC_USB_V = 0x00000001 +const USB_OTG_ENABLE_IC_USB_S = 31 +const USB_XFERSIZEWIDTH = 0x0000000F +const USB_XFERSIZEWIDTH_V = 0x0000000F +const USB_XFERSIZEWIDTH_S = 0 +const USB_PKTSIZEWIDTH = 0x00000007 +const USB_PKTSIZEWIDTH_V = 0x00000007 +const USB_PKTSIZEWIDTH_S = 4 +const USB_OTGEN_V = 0x00000001 +const USB_OTGEN_S = 7 +const USB_I2CINTSEL_V = 0x00000001 +const USB_I2CINTSEL_S = 8 +const USB_VNDCTLSUPT_V = 0x00000001 +const USB_VNDCTLSUPT_S = 9 +const USB_OPTFEATURE_V = 0x00000001 +const USB_OPTFEATURE_S = 10 +const USB_RSTTYPE_V = 0x00000001 +const USB_RSTTYPE_S = 11 +const USB_ADPSUPPORT_V = 0x00000001 +const USB_ADPSUPPORT_S = 12 +const USB_HSICMODE_V = 0x00000001 +const USB_HSICMODE_S = 13 +const USB_BCSUPPORT_V = 0x00000001 +const USB_BCSUPPORT_S = 14 +const USB_LPMMODE_V = 0x00000001 +const USB_LPMMODE_S = 15 +const USB_DFIFODEPTH = 0x0000FFFF +const USB_DFIFODEPTH_V = 0x0000FFFF +const USB_DFIFODEPTH_S = 16 +const USB_G_NUMDEVPERIOEPS = 0x0000000F +const USB_G_NUMDEVPERIOEPS_V = 0x0000000F +const USB_G_NUMDEVPERIOEPS_S = 0 +const USB_G_PARTIALPWRDN_V = 0x00000001 +const USB_G_PARTIALPWRDN_S = 4 +const USB_G_AHBFREQ_V = 0x00000001 +const USB_G_AHBFREQ_S = 5 +const USB_G_HIBERNATION_V = 0x00000001 +const USB_G_HIBERNATION_S = 6 +const USB_G_EXTENDEDHIBERNATION_V = 0x00000001 +const USB_G_EXTENDEDHIBERNATION_S = 7 +const USB_G_ACGSUPT_V = 0x00000001 +const USB_G_ACGSUPT_S = 12 +const USB_G_ENHANCEDLPMSUPT_V = 0x00000001 +const USB_G_ENHANCEDLPMSUPT_S = 13 +const USB_G_PHYDATAWIDTH = 0x00000003 +const USB_G_PHYDATAWIDTH_V = 0x00000003 +const USB_G_PHYDATAWIDTH_S = 14 +const USB_G_NUMCTLEPS = 0x0000000F +const USB_G_NUMCTLEPS_V = 0x0000000F +const USB_G_NUMCTLEPS_S = 16 +const USB_G_IDDQFLTR_V = 0x00000001 +const USB_G_IDDQFLTR_S = 20 +const USB_G_VBUSVALIDFLTR_V = 0x00000001 +const USB_G_VBUSVALIDFLTR_S = 21 +const USB_G_AVALIDFLTR_V = 0x00000001 +const USB_G_AVALIDFLTR_S = 22 +const USB_G_BVALIDFLTR_V = 0x00000001 +const USB_G_BVALIDFLTR_S = 23 +const USB_G_SESSENDFLTR_V = 0x00000001 +const USB_G_SESSENDFLTR_S = 24 +const USB_G_DEDFIFOMODE_V = 0x00000001 +const USB_G_DEDFIFOMODE_S = 25 +const USB_G_INEPS = 0x0000000F +const USB_G_INEPS_V = 0x0000000F +const USB_G_INEPS_S = 26 +const USB_G_DESCDMAENABLED_V = 0x00000001 +const USB_G_DESCDMAENABLED_S = 30 +const USB_G_DESCDMA_V = 0x00000001 +const USB_G_DESCDMA_S = 31 +const USB_FRNUM = 0x00003FFF +const USB_FRNUM_V = 0x00003FFF +const USB_FRNUM_S = 0 +const USB_FRREM = 0x0000FFFF +const USB_FRREM_V = 0x0000FFFF +const USB_FRREM_S = 16 +const USB_PTXFSPCAVAIL = 0x0000FFFF +const USB_PTXFSPCAVAIL_V = 0x0000FFFF +const USB_PTXFSPCAVAIL_S = 0 +const USB_PTXQSPCAVAIL = 0x0000001F +const USB_PTXQSPCAVAIL_V = 0x0000001F +const USB_PTXQSPCAVAIL_S = 16 +const USB_PTXQTOP = 0x000000FF +const USB_PTXQTOP_V = 0x000000FF +const USB_PTXQTOP_S = 24 +const USB_H_HCDMAB0 = 0xFFFFFFFF +const USB_H_HCDMAB0_V = 0xFFFFFFFF +const USB_H_HCDMAB0_S = 0 +const USB_H_HCDMAB1 = 0xFFFFFFFF +const USB_H_HCDMAB1_V = 0xFFFFFFFF +const USB_H_HCDMAB1_S = 0 +const USB_H_HCDMAB2 = 0xFFFFFFFF +const USB_H_HCDMAB2_V = 0xFFFFFFFF +const USB_H_HCDMAB2_S = 0 +const USB_H_HCDMAB3 = 0xFFFFFFFF +const USB_H_HCDMAB3_V = 0xFFFFFFFF +const USB_H_HCDMAB3_S = 0 +const USB_H_HCDMAB4 = 0xFFFFFFFF +const USB_H_HCDMAB4_V = 0xFFFFFFFF +const USB_H_HCDMAB4_S = 0 +const USB_H_HCDMAB5 = 0xFFFFFFFF +const USB_H_HCDMAB5_V = 0xFFFFFFFF +const USB_H_HCDMAB5_S = 0 +const USB_H_HCDMAB6 = 0xFFFFFFFF +const USB_H_HCDMAB6_V = 0xFFFFFFFF +const USB_H_HCDMAB6_S = 0 +const USB_H_HCDMAB7 = 0xFFFFFFFF +const USB_H_HCDMAB7_V = 0xFFFFFFFF +const USB_H_HCDMAB7_S = 0 +const USB_SUSPSTS_V = 0x00000001 +const USB_SUSPSTS_S = 0 +const USB_ENUMSPD = 0x00000003 +const USB_ENUMSPD_V = 0x00000003 +const USB_ENUMSPD_S = 1 +const USB_ERRTICERR_V = 0x00000001 +const USB_ERRTICERR_S = 3 +const USB_SOFFN = 0x00003FFF +const USB_SOFFN_V = 0x00003FFF +const USB_SOFFN_S = 8 +const USB_DEVLNSTS = 0x00000003 +const USB_DEVLNSTS_V = 0x00000003 +const USB_DEVLNSTS_S = 22 +const USB_D_INEPTXFSPCAVAIL0 = 0x0000FFFF +const USB_D_INEPTXFSPCAVAIL0_V = 0x0000FFFF +const USB_D_INEPTXFSPCAVAIL0_S = 0 +const USB_D_DMABUFFERADDR0 = 0xFFFFFFFF +const USB_D_DMABUFFERADDR0_V = 0xFFFFFFFF +const USB_D_DMABUFFERADDR0_S = 0 +const USB_D_INEPTXFSPCAVAIL1 = 0x0000FFFF +const USB_D_INEPTXFSPCAVAIL1_V = 0x0000FFFF +const USB_D_INEPTXFSPCAVAIL1_S = 0 +const USB_D_DMABUFFERADDR1 = 0xFFFFFFFF +const USB_D_DMABUFFERADDR1_V = 0xFFFFFFFF +const USB_D_DMABUFFERADDR1_S = 0 +const USB_D_INEPTXFSPCAVAIL2 = 0x0000FFFF +const USB_D_INEPTXFSPCAVAIL2_V = 0x0000FFFF +const USB_D_INEPTXFSPCAVAIL2_S = 0 +const USB_D_DMABUFFERADDR2 = 0xFFFFFFFF +const USB_D_DMABUFFERADDR2_V = 0xFFFFFFFF +const USB_D_DMABUFFERADDR2_S = 0 +const USB_D_INEPTXFSPCAVAIL3 = 0x0000FFFF +const USB_D_INEPTXFSPCAVAIL3_V = 0x0000FFFF +const USB_D_INEPTXFSPCAVAIL3_S = 0 +const USB_D_DMABUFFERADDR3 = 0xFFFFFFFF +const USB_D_DMABUFFERADDR3_V = 0xFFFFFFFF +const USB_D_DMABUFFERADDR3_S = 0 +const USB_D_INEPTXFSPCAVAIL4 = 0x0000FFFF +const USB_D_INEPTXFSPCAVAIL4_V = 0x0000FFFF +const USB_D_INEPTXFSPCAVAIL4_S = 0 +const USB_D_DMABUFFERADDR4 = 0xFFFFFFFF +const USB_D_DMABUFFERADDR4_V = 0xFFFFFFFF +const USB_D_DMABUFFERADDR4_S = 0 +const USB_D_INEPTXFSPCAVAIL5 = 0x0000FFFF +const USB_D_INEPTXFSPCAVAIL5_V = 0x0000FFFF +const USB_D_INEPTXFSPCAVAIL5_S = 0 +const USB_D_DMABUFFERADDR5 = 0xFFFFFFFF +const USB_D_DMABUFFERADDR5_V = 0xFFFFFFFF +const USB_D_DMABUFFERADDR5_S = 0 +const USB_D_INEPTXFSPCAVAIL6 = 0x0000FFFF +const USB_D_INEPTXFSPCAVAIL6_V = 0x0000FFFF +const USB_D_INEPTXFSPCAVAIL6_S = 0 +const USB_D_DMABUFFERADDR6 = 0xFFFFFFFF +const USB_D_DMABUFFERADDR6_V = 0xFFFFFFFF +const USB_D_DMABUFFERADDR6_S = 0 diff --git a/esp32/usb_serial_jtag_hal.go b/esp32/usb_serial_jtag_hal.go new file mode 100644 index 00000000..f26b6bdb --- /dev/null +++ b/esp32/usb_serial_jtag_hal.go @@ -0,0 +1,30 @@ +package freertos + +import _ "unsafe" + +/** + * @brief HAL context type of USJ driver + */ + +type UsbSerialJtagHalContextT struct { + Dev *UsbSerialJtagDevT +} + +/** + * @brief Initialize the USJ HAL driver + * + * @param hal USJ HAL context + */ +// llgo:link (*UsbSerialJtagHalContextT).UsbSerialJtagHalInit C.usb_serial_jtag_hal_init +func (recv_ *UsbSerialJtagHalContextT) UsbSerialJtagHalInit() { +} + +/** + * @brief Configure whether USJ is routed to internal/external FSLS PHY + * + * @param hal USJ HAL context + * @param external True if external, False if internal + */ +// llgo:link (*UsbSerialJtagHalContextT).UsbSerialJtagHalPhySetExternal C.usb_serial_jtag_hal_phy_set_external +func (recv_ *UsbSerialJtagHalContextT) UsbSerialJtagHalPhySetExternal(external bool) { +} diff --git a/esp32/usb_serial_jtag_ll.go b/esp32/usb_serial_jtag_ll.go new file mode 100644 index 00000000..88c396b2 --- /dev/null +++ b/esp32/usb_serial_jtag_ll.go @@ -0,0 +1,19 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const USB_SERIAL_JTAG_LL_EXT_PHY_SUPPORTED = 1 + +type UsbSerialJtagIntrT c.Int + +const ( + USB_SERIAL_JTAG_INTR_SOF UsbSerialJtagIntrT = 2 + USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT UsbSerialJtagIntrT = 4 + USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY UsbSerialJtagIntrT = 8 + USB_SERIAL_JTAG_INTR_TOKEN_REC_IN_EP1 UsbSerialJtagIntrT = 256 + USB_SERIAL_JTAG_INTR_BUS_RESET UsbSerialJtagIntrT = 512 + USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD UsbSerialJtagIntrT = 1024 +) diff --git a/esp32/usb_serial_jtag_reg.go b/esp32/usb_serial_jtag_reg.go new file mode 100644 index 00000000..c8baceac --- /dev/null +++ b/esp32/usb_serial_jtag_reg.go @@ -0,0 +1,251 @@ +package freertos + +import _ "unsafe" + +const USB_SERIAL_JTAG_RDWR_BYTE = 0x000000FF +const USB_SERIAL_JTAG_RDWR_BYTE_V = 0xFF +const USB_SERIAL_JTAG_RDWR_BYTE_S = 0 +const USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V = 0x1 +const USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S = 2 +const USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V = 0x1 +const USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S = 1 +const USB_SERIAL_JTAG_WR_DONE_V = 0x1 +const USB_SERIAL_JTAG_WR_DONE_S = 0 +const USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V = 0x1 +const USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S = 11 +const USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V = 0x1 +const USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S = 10 +const USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V = 0x1 +const USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S = 9 +const USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V = 0x1 +const USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S = 8 +const USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V = 0x1 +const USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S = 7 +const USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V = 0x1 +const USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S = 6 +const USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V = 0x1 +const USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S = 5 +const USB_SERIAL_JTAG_PID_ERR_INT_RAW_V = 0x1 +const USB_SERIAL_JTAG_PID_ERR_INT_RAW_S = 4 +const USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V = 0x1 +const USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S = 3 +const USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V = 0x1 +const USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S = 2 +const USB_SERIAL_JTAG_SOF_INT_RAW_V = 0x1 +const USB_SERIAL_JTAG_SOF_INT_RAW_S = 1 +const USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V = 0x1 +const USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S = 0 +const USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V = 0x1 +const USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S = 11 +const USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V = 0x1 +const USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S = 10 +const USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V = 0x1 +const USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S = 9 +const USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V = 0x1 +const USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S = 8 +const USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V = 0x1 +const USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S = 7 +const USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V = 0x1 +const USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S = 6 +const USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V = 0x1 +const USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S = 5 +const USB_SERIAL_JTAG_PID_ERR_INT_ST_V = 0x1 +const USB_SERIAL_JTAG_PID_ERR_INT_ST_S = 4 +const USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V = 0x1 +const USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S = 3 +const USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V = 0x1 +const USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S = 2 +const USB_SERIAL_JTAG_SOF_INT_ST_V = 0x1 +const USB_SERIAL_JTAG_SOF_INT_ST_S = 1 +const USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V = 0x1 +const USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S = 0 +const USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V = 0x1 +const USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S = 11 +const USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V = 0x1 +const USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S = 10 +const USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V = 0x1 +const USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S = 9 +const USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V = 0x1 +const USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S = 8 +const USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V = 0x1 +const USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S = 7 +const USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V = 0x1 +const USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S = 6 +const USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V = 0x1 +const USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S = 5 +const USB_SERIAL_JTAG_PID_ERR_INT_ENA_V = 0x1 +const USB_SERIAL_JTAG_PID_ERR_INT_ENA_S = 4 +const USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V = 0x1 +const USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S = 3 +const USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V = 0x1 +const USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S = 2 +const USB_SERIAL_JTAG_SOF_INT_ENA_V = 0x1 +const USB_SERIAL_JTAG_SOF_INT_ENA_S = 1 +const USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V = 0x1 +const USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S = 0 +const USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V = 0x1 +const USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S = 11 +const USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V = 0x1 +const USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S = 10 +const USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V = 0x1 +const USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S = 9 +const USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V = 0x1 +const USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S = 8 +const USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V = 0x1 +const USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S = 7 +const USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V = 0x1 +const USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S = 6 +const USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V = 0x1 +const USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S = 5 +const USB_SERIAL_JTAG_PID_ERR_INT_CLR_V = 0x1 +const USB_SERIAL_JTAG_PID_ERR_INT_CLR_S = 4 +const USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V = 0x1 +const USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S = 3 +const USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V = 0x1 +const USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S = 2 +const USB_SERIAL_JTAG_SOF_INT_CLR_V = 0x1 +const USB_SERIAL_JTAG_SOF_INT_CLR_S = 1 +const USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V = 0x1 +const USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S = 0 +const USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V = 0x1 +const USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S = 16 +const USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_V = 0x1 +const USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_S = 15 +const USB_SERIAL_JTAG_USB_PAD_ENABLE_V = 0x1 +const USB_SERIAL_JTAG_USB_PAD_ENABLE_S = 14 +const USB_SERIAL_JTAG_PULLUP_VALUE_V = 0x1 +const USB_SERIAL_JTAG_PULLUP_VALUE_S = 13 +const USB_SERIAL_JTAG_DM_PULLDOWN_V = 0x1 +const USB_SERIAL_JTAG_DM_PULLDOWN_S = 12 +const USB_SERIAL_JTAG_DM_PULLUP_V = 0x1 +const USB_SERIAL_JTAG_DM_PULLUP_S = 11 +const USB_SERIAL_JTAG_DP_PULLDOWN_V = 0x1 +const USB_SERIAL_JTAG_DP_PULLDOWN_S = 10 +const USB_SERIAL_JTAG_DP_PULLUP_V = 0x1 +const USB_SERIAL_JTAG_DP_PULLUP_S = 9 +const USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V = 0x1 +const USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S = 8 +const USB_SERIAL_JTAG_VREF_OVERRIDE_V = 0x1 +const USB_SERIAL_JTAG_VREF_OVERRIDE_S = 7 +const USB_SERIAL_JTAG_VREFL = 0x00000003 +const USB_SERIAL_JTAG_VREFL_V = 0x3 +const USB_SERIAL_JTAG_VREFL_S = 5 +const USB_SERIAL_JTAG_VREFH = 0x00000003 +const USB_SERIAL_JTAG_VREFH_V = 0x3 +const USB_SERIAL_JTAG_VREFH_S = 3 +const USB_SERIAL_JTAG_EXCHG_PINS_V = 0x1 +const USB_SERIAL_JTAG_EXCHG_PINS_S = 2 +const USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V = 0x1 +const USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S = 1 +const USB_SERIAL_JTAG_PHY_SEL_V = 0x1 +const USB_SERIAL_JTAG_PHY_SEL_S = 0 +const USB_SERIAL_JTAG_TEST_RX_DM_V = 0x1 +const USB_SERIAL_JTAG_TEST_RX_DM_S = 6 +const USB_SERIAL_JTAG_TEST_RX_DP_V = 0x1 +const USB_SERIAL_JTAG_TEST_RX_DP_S = 5 +const USB_SERIAL_JTAG_TEST_RX_RCV_V = 0x1 +const USB_SERIAL_JTAG_TEST_RX_RCV_S = 4 +const USB_SERIAL_JTAG_TEST_TX_DM_V = 0x1 +const USB_SERIAL_JTAG_TEST_TX_DM_S = 3 +const USB_SERIAL_JTAG_TEST_TX_DP_V = 0x1 +const USB_SERIAL_JTAG_TEST_TX_DP_S = 2 +const USB_SERIAL_JTAG_TEST_USB_OE_V = 0x1 +const USB_SERIAL_JTAG_TEST_USB_OE_S = 1 +const USB_SERIAL_JTAG_TEST_ENABLE_V = 0x1 +const USB_SERIAL_JTAG_TEST_ENABLE_S = 0 +const USB_SERIAL_JTAG_OUT_FIFO_RESET_V = 0x1 +const USB_SERIAL_JTAG_OUT_FIFO_RESET_S = 9 +const USB_SERIAL_JTAG_IN_FIFO_RESET_V = 0x1 +const USB_SERIAL_JTAG_IN_FIFO_RESET_S = 8 +const USB_SERIAL_JTAG_OUT_FIFO_FULL_V = 0x1 +const USB_SERIAL_JTAG_OUT_FIFO_FULL_S = 7 +const USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V = 0x1 +const USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S = 6 +const USB_SERIAL_JTAG_OUT_FIFO_CNT = 0x00000003 +const USB_SERIAL_JTAG_OUT_FIFO_CNT_V = 0x3 +const USB_SERIAL_JTAG_OUT_FIFO_CNT_S = 4 +const USB_SERIAL_JTAG_IN_FIFO_FULL_V = 0x1 +const USB_SERIAL_JTAG_IN_FIFO_FULL_S = 3 +const USB_SERIAL_JTAG_IN_FIFO_EMPTY_V = 0x1 +const USB_SERIAL_JTAG_IN_FIFO_EMPTY_S = 2 +const USB_SERIAL_JTAG_IN_FIFO_CNT = 0x00000003 +const USB_SERIAL_JTAG_IN_FIFO_CNT_V = 0x3 +const USB_SERIAL_JTAG_IN_FIFO_CNT_S = 0 +const USB_SERIAL_JTAG_SOF_FRAME_INDEX = 0x000007FF +const USB_SERIAL_JTAG_SOF_FRAME_INDEX_V = 0x7FF +const USB_SERIAL_JTAG_SOF_FRAME_INDEX_S = 0 +const USB_SERIAL_JTAG_IN_EP0_RD_ADDR = 0x0000007F +const USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V = 0x7F +const USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S = 9 +const USB_SERIAL_JTAG_IN_EP0_WR_ADDR = 0x0000007F +const USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V = 0x7F +const USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S = 2 +const USB_SERIAL_JTAG_IN_EP0_STATE = 0x00000003 +const USB_SERIAL_JTAG_IN_EP0_STATE_V = 0x3 +const USB_SERIAL_JTAG_IN_EP0_STATE_S = 0 +const USB_SERIAL_JTAG_IN_EP1_RD_ADDR = 0x0000007F +const USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V = 0x7F +const USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S = 9 +const USB_SERIAL_JTAG_IN_EP1_WR_ADDR = 0x0000007F +const USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V = 0x7F +const USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S = 2 +const USB_SERIAL_JTAG_IN_EP1_STATE = 0x00000003 +const USB_SERIAL_JTAG_IN_EP1_STATE_V = 0x3 +const USB_SERIAL_JTAG_IN_EP1_STATE_S = 0 +const USB_SERIAL_JTAG_IN_EP2_RD_ADDR = 0x0000007F +const USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V = 0x7F +const USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S = 9 +const USB_SERIAL_JTAG_IN_EP2_WR_ADDR = 0x0000007F +const USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V = 0x7F +const USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S = 2 +const USB_SERIAL_JTAG_IN_EP2_STATE = 0x00000003 +const USB_SERIAL_JTAG_IN_EP2_STATE_V = 0x3 +const USB_SERIAL_JTAG_IN_EP2_STATE_S = 0 +const USB_SERIAL_JTAG_IN_EP3_RD_ADDR = 0x0000007F +const USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V = 0x7F +const USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S = 9 +const USB_SERIAL_JTAG_IN_EP3_WR_ADDR = 0x0000007F +const USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V = 0x7F +const USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S = 2 +const USB_SERIAL_JTAG_IN_EP3_STATE = 0x00000003 +const USB_SERIAL_JTAG_IN_EP3_STATE_V = 0x3 +const USB_SERIAL_JTAG_IN_EP3_STATE_S = 0 +const USB_SERIAL_JTAG_OUT_EP0_RD_ADDR = 0x0000007F +const USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V = 0x7F +const USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S = 9 +const USB_SERIAL_JTAG_OUT_EP0_WR_ADDR = 0x0000007F +const USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V = 0x7F +const USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S = 2 +const USB_SERIAL_JTAG_OUT_EP0_STATE = 0x00000003 +const USB_SERIAL_JTAG_OUT_EP0_STATE_V = 0x3 +const USB_SERIAL_JTAG_OUT_EP0_STATE_S = 0 +const USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT = 0x0000007F +const USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V = 0x7F +const USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S = 16 +const USB_SERIAL_JTAG_OUT_EP1_RD_ADDR = 0x0000007F +const USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V = 0x7F +const USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S = 9 +const USB_SERIAL_JTAG_OUT_EP1_WR_ADDR = 0x0000007F +const USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V = 0x7F +const USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S = 2 +const USB_SERIAL_JTAG_OUT_EP1_STATE = 0x00000003 +const USB_SERIAL_JTAG_OUT_EP1_STATE_V = 0x3 +const USB_SERIAL_JTAG_OUT_EP1_STATE_S = 0 +const USB_SERIAL_JTAG_OUT_EP2_RD_ADDR = 0x0000007F +const USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V = 0x7F +const USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S = 9 +const USB_SERIAL_JTAG_OUT_EP2_WR_ADDR = 0x0000007F +const USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V = 0x7F +const USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S = 2 +const USB_SERIAL_JTAG_OUT_EP2_STATE = 0x00000003 +const USB_SERIAL_JTAG_OUT_EP2_STATE_V = 0x3 +const USB_SERIAL_JTAG_OUT_EP2_STATE_S = 0 +const USB_SERIAL_JTAG_CLK_EN_V = 0x1 +const USB_SERIAL_JTAG_CLK_EN_S = 0 +const USB_SERIAL_JTAG_USB_MEM_CLK_EN_V = 0x1 +const USB_SERIAL_JTAG_USB_MEM_CLK_EN_S = 1 +const USB_SERIAL_JTAG_USB_MEM_PD_V = 0x1 +const USB_SERIAL_JTAG_USB_MEM_PD_S = 0 +const USB_SERIAL_JTAG_DATE = 0xFFFFFFFF +const USB_SERIAL_JTAG_DATE_V = 0xFFFFFFFF +const USB_SERIAL_JTAG_DATE_S = 0 diff --git a/esp32/usb_serial_jtag_struct.go b/esp32/usb_serial_jtag_struct.go new file mode 100644 index 00000000..921fa695 --- /dev/null +++ b/esp32/usb_serial_jtag_struct.go @@ -0,0 +1,81 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type UsbSerialJtagDevS struct { + Ep1 struct { + Val c.Uint32T + } + Ep1Conf struct { + Val c.Uint32T + } + IntRaw struct { + Val c.Uint32T + } + IntSt struct { + Val c.Uint32T + } + IntEna struct { + Val c.Uint32T + } + IntClr struct { + Val c.Uint32T + } + Conf0 struct { + Val c.Uint32T + } + Test struct { + Val c.Uint32T + } + JfifoSt struct { + Val c.Uint32T + } + FramNum struct { + Val c.Uint32T + } + InEp0St struct { + Val c.Uint32T + } + InEp1St struct { + Val c.Uint32T + } + InEp2St struct { + Val c.Uint32T + } + InEp3St struct { + Val c.Uint32T + } + OutEp0St struct { + Val c.Uint32T + } + OutEp1St struct { + Val c.Uint32T + } + OutEp2St struct { + Val c.Uint32T + } + MiscConf struct { + Val c.Uint32T + } + MemConf struct { + Val c.Uint32T + } + Reserved4c c.Uint32T + Reserved50 c.Uint32T + Reserved54 c.Uint32T + Reserved58 c.Uint32T + Reserved5c c.Uint32T + Reserved60 c.Uint32T + Reserved64 c.Uint32T + Reserved68 c.Uint32T + Reserved6c c.Uint32T + Reserved70 c.Uint32T + Reserved74 c.Uint32T + Reserved78 c.Uint32T + Reserved7c c.Uint32T + Date c.Uint32T +} +type UsbSerialJtagDevT UsbSerialJtagDevS diff --git a/esp32/usb_serial_jtag_types.go b/esp32/usb_serial_jtag_types.go new file mode 100644 index 00000000..06066b5b --- /dev/null +++ b/esp32/usb_serial_jtag_types.go @@ -0,0 +1,17 @@ +package freertos + +import _ "unsafe" + +/** + * @brief USJ test mode values + * + * Specifies the logic values of each of the USB FSLS Serial PHY interface + * signals when in test mode. + */ + +type UsbSerialJtagPullOverrideValsT struct { + DpPu bool + DmPu bool + DpPd bool + DmPd bool +} diff --git a/esp32/usb_struct.go b/esp32/usb_struct.go new file mode 100644 index 00000000..e91c0f06 --- /dev/null +++ b/esp32/usb_struct.go @@ -0,0 +1,101 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/* USB IN EP Register block type */ + +type UsbInEpReg struct { + Diepctl c.Uint32T + Reserved c.Uint32T + Diepint c.Uint32T + Reserved1 c.Uint32T + Dieptsiz c.Uint32T + Diepdma c.Uint32T + Dtxfsts c.Uint32T + Reserved2 c.Uint32T +} +type UsbInEndpointT UsbInEpReg + +/* USB OUT EP Register block type */ + +type UsbOutEpReg struct { + Doepctl c.Uint32T + Reserved c.Uint32T + Doepint c.Uint32T + Reserved1 c.Uint32T + Doeptsiz c.Uint32T + Doepdma c.Uint32T + Reserved2 c.Uint32T + Reserved3 c.Uint32T +} +type UsbOutEndpointT UsbOutEpReg + +type UsbReg struct { + Gotgctl c.Uint32T + Gotgint c.Uint32T + Gahbcfg c.Uint32T + Gusbcfg c.Uint32T + Grstctl c.Uint32T + Gintsts c.Uint32T + Gintmsk c.Uint32T + Grxstsr c.Uint32T + Grxstsp c.Uint32T + Grxfsiz c.Uint32T + Gnptxfsiz c.Uint32T + Gnptxsts c.Uint32T + Reserved0x00300x0040 [4]c.Uint32T + Gsnpsid c.Uint32T + Ghwcfg1 c.Uint32T + Ghwcfg2 c.Uint32T + Ghwcfg3 c.Uint32T + Ghwcfg4 c.Uint32T + Reserved0x00540x005c [2]c.Uint32T + Gdfifocfg c.Uint32T + Reserved0x00600x0100 [40]c.Uint32T + Hptxfsiz c.Uint32T + Dieptxf [4]c.Uint32T + Reserved0x01140x0140 [11]c.Uint32T + Reserved0x01400x0400 [176]c.Uint32T + Hcfg c.Uint32T + Hfir c.Uint32T + Hfnum c.Uint32T + Reserved0x40C c.Uint32T + Hptxsts c.Uint32T + Haint c.Uint32T + Haintmsk c.Uint32T + Hflbaddr c.Uint32T + Reserved0x04200x0440 [8]c.Uint32T + Hprt c.Uint32T + Reserved0x04440x0500 [47]c.Uint32T + HostChanRegs [128]c.Uint32T + Reserved0x07000x0800 [64]c.Uint32T + Dcfg c.Uint32T + Dctl c.Uint32T + Dsts c.Uint32T + Reserved0x80c c.Uint32T + Diepmsk c.Uint32T + Doepmsk c.Uint32T + Daint c.Uint32T + Daintmsk c.Uint32T + Reserved0x08200x0828 [2]c.Uint32T + Dvbusdis c.Uint32T + Dvbuspulse c.Uint32T + Dthrctl c.Uint32T + Dtknqr4Fifoemptymsk c.Uint32T + Reserved0x08380x0900 [50]c.Uint32T + InEpReg [7]UsbInEndpointT + Reserved0x09e00x0b00 [72]c.Uint32T + OutEpReg [7]UsbOutEndpointT + Reserved0x0be00x0d00 [72]c.Uint32T + Reserved0x0d000x0e00 [64]c.Uint32T + Pcgctrl c.Uint32T + Reserved0x0e04 c.Uint32T + Reserved8 [504]c.Uint8T + Fifo [16][1024]c.Uint32T + Reserved0x11000 [61440]c.Uint8T + DbgFifo [131072]c.Uint32T +} +type UsbDevT UsbReg diff --git a/esp32/usb_wrap_hal.go b/esp32/usb_wrap_hal.go new file mode 100644 index 00000000..8fd32eb8 --- /dev/null +++ b/esp32/usb_wrap_hal.go @@ -0,0 +1,38 @@ +package freertos + +import _ "unsafe" + +/** + * @brief HAL context type of USB WRAP driver + */ + +type UsbWrapHalContextT struct { + Dev *UsbWrapDevT +} + +/** + * @brief Initialize the USB WRAP HAL driver + * + * @param hal USB WRAP HAL context + */ +// llgo:link (*UsbWrapHalContextT).X_usbWrapHalInit C._usb_wrap_hal_init +func (recv_ *UsbWrapHalContextT) X_usbWrapHalInit() { +} + +/** + * @brief Disable USB WRAP + * + * Disable clock to the peripheral + */ +//go:linkname X_usbWrapHalDisable C._usb_wrap_hal_disable +func X_usbWrapHalDisable() + +/** + * @brief Configure whether USB WRAP is routed to internal/external FSLS PHY + * + * @param hal USB WRAP HAL context + * @param external True if external, False if internal + */ +// llgo:link (*UsbWrapHalContextT).UsbWrapHalPhySetExternal C.usb_wrap_hal_phy_set_external +func (recv_ *UsbWrapHalContextT) UsbWrapHalPhySetExternal(external bool) { +} diff --git a/esp32/usb_wrap_ll.go b/esp32/usb_wrap_ll.go new file mode 100644 index 00000000..7ff76892 --- /dev/null +++ b/esp32/usb_wrap_ll.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +const USB_WRAP_LL_EXT_PHY_SUPPORTED = 1 diff --git a/esp32/usb_wrap_reg.go b/esp32/usb_wrap_reg.go new file mode 100644 index 00000000..6b11956b --- /dev/null +++ b/esp32/usb_wrap_reg.go @@ -0,0 +1,67 @@ +package freertos + +import _ "unsafe" + +const USB_WRAP_CLK_EN_V = 0x1 +const USB_WRAP_CLK_EN_S = 31 +const USB_WRAP_DFIFO_FORCE_PU_V = 0x1 +const USB_WRAP_DFIFO_FORCE_PU_S = 22 +const USB_WRAP_PHY_TX_EDGE_SEL_V = 0x1 +const USB_WRAP_PHY_TX_EDGE_SEL_S = 21 +const USB_WRAP_PHY_CLK_FORCE_ON_V = 0x1 +const USB_WRAP_PHY_CLK_FORCE_ON_S = 20 +const USB_WRAP_AHB_CLK_FORCE_ON_V = 0x1 +const USB_WRAP_AHB_CLK_FORCE_ON_S = 19 +const USB_WRAP_USB_PAD_ENABLE_V = 0x1 +const USB_WRAP_USB_PAD_ENABLE_S = 18 +const USB_WRAP_PULLUP_VALUE_V = 0x1 +const USB_WRAP_PULLUP_VALUE_S = 17 +const USB_WRAP_DM_PULLDOWN_V = 0x1 +const USB_WRAP_DM_PULLDOWN_S = 16 +const USB_WRAP_DM_PULLUP_V = 0x1 +const USB_WRAP_DM_PULLUP_S = 15 +const USB_WRAP_DP_PULLDOWN_V = 0x1 +const USB_WRAP_DP_PULLDOWN_S = 14 +const USB_WRAP_DP_PULLUP_V = 0x1 +const USB_WRAP_DP_PULLUP_S = 13 +const USB_WRAP_PAD_PULL_OVERRIDE_V = 0x1 +const USB_WRAP_PAD_PULL_OVERRIDE_S = 12 +const USB_WRAP_VREF_OVERRIDE_V = 0x1 +const USB_WRAP_VREF_OVERRIDE_S = 11 +const USB_WRAP_VREFL = 0x00000003 +const USB_WRAP_VREFL_V = 0x3 +const USB_WRAP_VREFL_S = 9 +const USB_WRAP_VREFH = 0x00000003 +const USB_WRAP_VREFH_V = 0x3 +const USB_WRAP_VREFH_S = 7 +const USB_WRAP_EXCHG_PINS_V = 0x1 +const USB_WRAP_EXCHG_PINS_S = 6 +const USB_WRAP_EXCHG_PINS_OVERRIDE_V = 0x1 +const USB_WRAP_EXCHG_PINS_OVERRIDE_S = 5 +const USB_WRAP_DBNCE_FLTR_BYPASS_V = 0x1 +const USB_WRAP_DBNCE_FLTR_BYPASS_S = 4 +const USB_WRAP_DFIFO_FORCE_PD_V = 0x1 +const USB_WRAP_DFIFO_FORCE_PD_S = 3 +const USB_WRAP_PHY_SEL_V = 0x1 +const USB_WRAP_PHY_SEL_S = 2 +const USB_WRAP_SRP_SESSEND_VALUE_V = 0x1 +const USB_WRAP_SRP_SESSEND_VALUE_S = 1 +const USB_WRAP_SRP_SESSEND_OVERRIDE_V = 0x1 +const USB_WRAP_SRP_SESSEND_OVERRIDE_S = 0 +const USB_WRAP_TEST_RX_DM_V = 0x1 +const USB_WRAP_TEST_RX_DM_S = 6 +const USB_WRAP_TEST_RX_DP_V = 0x1 +const USB_WRAP_TEST_RX_DP_S = 5 +const USB_WRAP_TEST_RX_RCV_V = 0x1 +const USB_WRAP_TEST_RX_RCV_S = 4 +const USB_WRAP_TEST_TX_DM_V = 0x1 +const USB_WRAP_TEST_TX_DM_S = 3 +const USB_WRAP_TEST_TX_DP_V = 0x1 +const USB_WRAP_TEST_TX_DP_S = 2 +const USB_WRAP_TEST_USB_OE_V = 0x1 +const USB_WRAP_TEST_USB_OE_S = 1 +const USB_WRAP_TEST_ENABLE_V = 0x1 +const USB_WRAP_TEST_ENABLE_S = 0 +const USB_WRAP_DATE = 0xFFFFFFFF +const USB_WRAP_DATE_V = 0xFFFFFFFF +const USB_WRAP_DATE_S = 0 diff --git a/esp32/usb_wrap_struct.go b/esp32/usb_wrap_struct.go new file mode 100644 index 00000000..47e5bcd8 --- /dev/null +++ b/esp32/usb_wrap_struct.go @@ -0,0 +1,291 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** Control/Status registers */ +/** Type of otg_conf register + * PAD/DFIFO/PHY configuration register. + */ + +type UsbWrapOtgConfRegT struct { + Val c.Uint32T +} + +/** Type of test_conf register + * TEST relative configuration registers. + */ + +type UsbWrapTestConfRegT struct { + Val c.Uint32T +} + +/** Status registers */ +/** Type of date register + * Version register. + */ + +type UsbWrapDateRegT struct { + Val c.Uint32T +} + +type UsbWrapDevT struct { + OtgConf UsbWrapOtgConfRegT + TestConf UsbWrapTestConfRegT + Reserved008 c.Uint32T + Reserved00c c.Uint32T + Reserved010 c.Uint32T + Reserved014 c.Uint32T + Reserved018 c.Uint32T + Reserved01c c.Uint32T + Reserved020 c.Uint32T + Reserved024 c.Uint32T + Reserved028 c.Uint32T + Reserved02c c.Uint32T + Reserved030 c.Uint32T + Reserved034 c.Uint32T + Reserved038 c.Uint32T + Reserved03c c.Uint32T + Reserved040 c.Uint32T + Reserved044 c.Uint32T + Reserved048 c.Uint32T + Reserved04c c.Uint32T + Reserved050 c.Uint32T + Reserved054 c.Uint32T + Reserved058 c.Uint32T + Reserved05c c.Uint32T + Reserved060 c.Uint32T + Reserved064 c.Uint32T + Reserved068 c.Uint32T + Reserved06c c.Uint32T + Reserved070 c.Uint32T + Reserved074 c.Uint32T + Reserved078 c.Uint32T + Reserved07c c.Uint32T + Reserved080 c.Uint32T + Reserved084 c.Uint32T + Reserved088 c.Uint32T + Reserved08c c.Uint32T + Reserved090 c.Uint32T + Reserved094 c.Uint32T + Reserved098 c.Uint32T + Reserved09c c.Uint32T + Reserved0a0 c.Uint32T + Reserved0a4 c.Uint32T + Reserved0a8 c.Uint32T + Reserved0ac c.Uint32T + Reserved0b0 c.Uint32T + Reserved0b4 c.Uint32T + Reserved0b8 c.Uint32T + Reserved0bc c.Uint32T + Reserved0c0 c.Uint32T + Reserved0c4 c.Uint32T + Reserved0c8 c.Uint32T + Reserved0cc c.Uint32T + Reserved0d0 c.Uint32T + Reserved0d4 c.Uint32T + Reserved0d8 c.Uint32T + Reserved0dc c.Uint32T + Reserved0e0 c.Uint32T + Reserved0e4 c.Uint32T + Reserved0e8 c.Uint32T + Reserved0ec c.Uint32T + Reserved0f0 c.Uint32T + Reserved0f4 c.Uint32T + Reserved0f8 c.Uint32T + Reserved0fc c.Uint32T + Reserved100 c.Uint32T + Reserved104 c.Uint32T + Reserved108 c.Uint32T + Reserved10c c.Uint32T + Reserved110 c.Uint32T + Reserved114 c.Uint32T + Reserved118 c.Uint32T + Reserved11c c.Uint32T + Reserved120 c.Uint32T + Reserved124 c.Uint32T + Reserved128 c.Uint32T + Reserved12c c.Uint32T + Reserved130 c.Uint32T + Reserved134 c.Uint32T + Reserved138 c.Uint32T + Reserved13c c.Uint32T + Reserved140 c.Uint32T + Reserved144 c.Uint32T + Reserved148 c.Uint32T + Reserved14c c.Uint32T + Reserved150 c.Uint32T + Reserved154 c.Uint32T + Reserved158 c.Uint32T + Reserved15c c.Uint32T + Reserved160 c.Uint32T + Reserved164 c.Uint32T + Reserved168 c.Uint32T + Reserved16c c.Uint32T + Reserved170 c.Uint32T + Reserved174 c.Uint32T + Reserved178 c.Uint32T + Reserved17c c.Uint32T + Reserved180 c.Uint32T + Reserved184 c.Uint32T + Reserved188 c.Uint32T + Reserved18c c.Uint32T + Reserved190 c.Uint32T + Reserved194 c.Uint32T + Reserved198 c.Uint32T + Reserved19c c.Uint32T + Reserved1a0 c.Uint32T + Reserved1a4 c.Uint32T + Reserved1a8 c.Uint32T + Reserved1ac c.Uint32T + Reserved1b0 c.Uint32T + Reserved1b4 c.Uint32T + Reserved1b8 c.Uint32T + Reserved1bc c.Uint32T + Reserved1c0 c.Uint32T + Reserved1c4 c.Uint32T + Reserved1c8 c.Uint32T + Reserved1cc c.Uint32T + Reserved1d0 c.Uint32T + Reserved1d4 c.Uint32T + Reserved1d8 c.Uint32T + Reserved1dc c.Uint32T + Reserved1e0 c.Uint32T + Reserved1e4 c.Uint32T + Reserved1e8 c.Uint32T + Reserved1ec c.Uint32T + Reserved1f0 c.Uint32T + Reserved1f4 c.Uint32T + Reserved1f8 c.Uint32T + Reserved1fc c.Uint32T + Reserved200 c.Uint32T + Reserved204 c.Uint32T + Reserved208 c.Uint32T + Reserved20c c.Uint32T + Reserved210 c.Uint32T + Reserved214 c.Uint32T + Reserved218 c.Uint32T + Reserved21c c.Uint32T + Reserved220 c.Uint32T + Reserved224 c.Uint32T + Reserved228 c.Uint32T + Reserved22c c.Uint32T + Reserved230 c.Uint32T + Reserved234 c.Uint32T + Reserved238 c.Uint32T + Reserved23c c.Uint32T + Reserved240 c.Uint32T + Reserved244 c.Uint32T + Reserved248 c.Uint32T + Reserved24c c.Uint32T + Reserved250 c.Uint32T + Reserved254 c.Uint32T + Reserved258 c.Uint32T + Reserved25c c.Uint32T + Reserved260 c.Uint32T + Reserved264 c.Uint32T + Reserved268 c.Uint32T + Reserved26c c.Uint32T + Reserved270 c.Uint32T + Reserved274 c.Uint32T + Reserved278 c.Uint32T + Reserved27c c.Uint32T + Reserved280 c.Uint32T + Reserved284 c.Uint32T + Reserved288 c.Uint32T + Reserved28c c.Uint32T + Reserved290 c.Uint32T + Reserved294 c.Uint32T + Reserved298 c.Uint32T + Reserved29c c.Uint32T + Reserved2a0 c.Uint32T + Reserved2a4 c.Uint32T + Reserved2a8 c.Uint32T + Reserved2ac c.Uint32T + Reserved2b0 c.Uint32T + Reserved2b4 c.Uint32T + Reserved2b8 c.Uint32T + Reserved2bc c.Uint32T + Reserved2c0 c.Uint32T + Reserved2c4 c.Uint32T + Reserved2c8 c.Uint32T + Reserved2cc c.Uint32T + Reserved2d0 c.Uint32T + Reserved2d4 c.Uint32T + Reserved2d8 c.Uint32T + Reserved2dc c.Uint32T + Reserved2e0 c.Uint32T + Reserved2e4 c.Uint32T + Reserved2e8 c.Uint32T + Reserved2ec c.Uint32T + Reserved2f0 c.Uint32T + Reserved2f4 c.Uint32T + Reserved2f8 c.Uint32T + Reserved2fc c.Uint32T + Reserved300 c.Uint32T + Reserved304 c.Uint32T + Reserved308 c.Uint32T + Reserved30c c.Uint32T + Reserved310 c.Uint32T + Reserved314 c.Uint32T + Reserved318 c.Uint32T + Reserved31c c.Uint32T + Reserved320 c.Uint32T + Reserved324 c.Uint32T + Reserved328 c.Uint32T + Reserved32c c.Uint32T + Reserved330 c.Uint32T + Reserved334 c.Uint32T + Reserved338 c.Uint32T + Reserved33c c.Uint32T + Reserved340 c.Uint32T + Reserved344 c.Uint32T + Reserved348 c.Uint32T + Reserved34c c.Uint32T + Reserved350 c.Uint32T + Reserved354 c.Uint32T + Reserved358 c.Uint32T + Reserved35c c.Uint32T + Reserved360 c.Uint32T + Reserved364 c.Uint32T + Reserved368 c.Uint32T + Reserved36c c.Uint32T + Reserved370 c.Uint32T + Reserved374 c.Uint32T + Reserved378 c.Uint32T + Reserved37c c.Uint32T + Reserved380 c.Uint32T + Reserved384 c.Uint32T + Reserved388 c.Uint32T + Reserved38c c.Uint32T + Reserved390 c.Uint32T + Reserved394 c.Uint32T + Reserved398 c.Uint32T + Reserved39c c.Uint32T + Reserved3a0 c.Uint32T + Reserved3a4 c.Uint32T + Reserved3a8 c.Uint32T + Reserved3ac c.Uint32T + Reserved3b0 c.Uint32T + Reserved3b4 c.Uint32T + Reserved3b8 c.Uint32T + Reserved3bc c.Uint32T + Reserved3c0 c.Uint32T + Reserved3c4 c.Uint32T + Reserved3c8 c.Uint32T + Reserved3cc c.Uint32T + Reserved3d0 c.Uint32T + Reserved3d4 c.Uint32T + Reserved3d8 c.Uint32T + Reserved3dc c.Uint32T + Reserved3e0 c.Uint32T + Reserved3e4 c.Uint32T + Reserved3e8 c.Uint32T + Reserved3ec c.Uint32T + Reserved3f0 c.Uint32T + Reserved3f4 c.Uint32T + Reserved3f8 c.Uint32T + Date UsbWrapDateRegT +} diff --git a/esp32/usb_wrap_types.go b/esp32/usb_wrap_types.go new file mode 100644 index 00000000..9cb2fdf7 --- /dev/null +++ b/esp32/usb_wrap_types.go @@ -0,0 +1,36 @@ +package freertos + +import _ "unsafe" + +/** + * @brief USB WRAP pull up/down resistor override values + * + * Specifies whether each pull up/down resistor should be enabled/disabled when + * overriding connected USB PHY's pull resistors. + */ + +type UsbWrapPullOverrideValsT struct { + DpPu bool + DmPu bool + DpPd bool + DmPd bool +} + +/** + * @brief USB WRAP test mode values + * + * Specifies the logic values of each of the USB FSLS Serial PHY interface + * signals when in test mode. + * + * @note See section "2.2.1.13 FsLsSerialMode" of UTMI+ specification for more + * details of each signal. + */ + +type UsbWrapTestModeValsT struct { + TxEnableN bool + TxDp bool + TxDm bool + RxDp bool + RxDm bool + RxRcv bool +} diff --git a/esp32/wait_for_event.go b/esp32/wait_for_event.go new file mode 100644 index 00000000..7420c8d6 --- /dev/null +++ b/esp32/wait_for_event.go @@ -0,0 +1,31 @@ +package freertos + +import ( + "github.com/goplus/lib/c/time" + _ "unsafe" +) + +type Event struct { + Unused [8]uint8 +} + +//go:linkname EventCreate C.event_create +func EventCreate() *Event + +// llgo:link (*Event).EventDelete C.event_delete +func (recv_ *Event) EventDelete() { +} + +// llgo:link (*Event).EventWait C.event_wait +func (recv_ *Event) EventWait() bool { + return false +} + +// llgo:link (*Event).EventWaitTimed C.event_wait_timed +func (recv_ *Event) EventWaitTimed(ms time.TimeT) bool { + return false +} + +// llgo:link (*Event).EventSignal C.event_signal +func (recv_ *Event) EventSignal() { +} diff --git a/esp32/wdev_reg.go b/esp32/wdev_reg.go new file mode 100644 index 00000000..6a32f15a --- /dev/null +++ b/esp32/wdev_reg.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +const WDEV_RND_REG = 0x6003507C diff --git a/esp32/wdt_hal.go b/esp32/wdt_hal.go new file mode 100644 index 00000000..6d6d6d1a --- /dev/null +++ b/esp32/wdt_hal.go @@ -0,0 +1,167 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * Context that should be maintained by both the driver and the HAL + */ + +type WdtHalContextT struct { + Inst WdtInstT +} + +/** + * @brief Initialize one of the WDTs associated HAL context + * + * This function initializes one of the WDTs (MWDT0, MWDT1, or RWDT) hardware by + * doing the following: + * - Disables the WDT and all of its stages + * - Sets some registers with default values + * - Sets the WDTs source clock prescaler (not applicable to RWDT) + * - Optionally enables the level interrupt + * + * The HAL context is initialized by storing the type (i.e. MWDT or RWDT) of + * this WDT instance, and a pointer to the associated registers. + * + * @param hal Context of HAL layer + * @param wdt_inst Which WDT instance to initialize (MWDT0, MWDT1, or RWDT) + * @param prescaler MWDT source clock prescaler. Unused for RWDT + * @param enable_intr True to enable level interrupt. False to disable + * + * @note Although the WDTs on the ESP32 have an edge interrupt, this HAL does + * not utilize it and will always disables it. + * @note RWDT does not have a prescaler. Its tick rate is equal to the + * frequency of its source clock (RTC slow clock). + */ +// llgo:link (*WdtHalContextT).WdtHalInit C.wdt_hal_init +func (recv_ *WdtHalContextT) WdtHalInit(wdt_inst WdtInstT, prescaler c.Uint32T, enable_intr bool) { +} + +/** + * @brief Deinitialize a WDT and its HAL context + * + * This function deinitializes a WDT by feeding then disabling it. The WDT's + * interrupt is also cleared and disabled. The HAL context is cleared. + * + * @param hal Context of HAL layer + */ +// llgo:link (*WdtHalContextT).WdtHalDeinit C.wdt_hal_deinit +func (recv_ *WdtHalContextT) WdtHalDeinit() { +} + +/** + * @brief Configure a particular stage of a WDT + * + * @param hal Context of HAL layer + * @param stage Stage to configure (0 to 3) + * @param timeout Number of WDT ticks for the stage to time out + * @param behavior What action to take when the stage times out. Note that only + * the RWDT supports the RTC reset action. + * + * @note This function can only be called when the WDT is unlocked. Call + * wdt_hal_write_protect_disable() first. + */ +// llgo:link (*WdtHalContextT).WdtHalConfigStage C.wdt_hal_config_stage +func (recv_ *WdtHalContextT) WdtHalConfigStage(stage WdtStageT, timeout c.Uint32T, behavior WdtStageActionT) { +} + +/** + * @brief Disable write protection of the WDT registers + * + * @param hal Context of HAL layer + */ +// llgo:link (*WdtHalContextT).WdtHalWriteProtectDisable C.wdt_hal_write_protect_disable +func (recv_ *WdtHalContextT) WdtHalWriteProtectDisable() { +} + +/** + * @brief Enable write protection of the WDT registers + * + * @param hal Context of HAL layer + */ +// llgo:link (*WdtHalContextT).WdtHalWriteProtectEnable C.wdt_hal_write_protect_enable +func (recv_ *WdtHalContextT) WdtHalWriteProtectEnable() { +} + +/** + * @brief Enable the WDT + * + * The WDT will start counting when enabled. This function also feeds the WDT + * before enabling it. + * + * @param hal Context of HAL layer + * + * @note This function can only be called when the WDT is unlocked. Call + * wdt_hal_write_protect_disable() first. + */ +// llgo:link (*WdtHalContextT).WdtHalEnable C.wdt_hal_enable +func (recv_ *WdtHalContextT) WdtHalEnable() { +} + +/** + * @brief Disable the WDT + * + * @param hal Context of HAL layer + * + * @note This function can only be called when the WDT is unlocked. Call + * wdt_hal_write_protect_disable() first. + */ +// llgo:link (*WdtHalContextT).WdtHalDisable C.wdt_hal_disable +func (recv_ *WdtHalContextT) WdtHalDisable() { +} + +/** + * @brief Handle WDT interrupt + * + * Clears the interrupt status bit and feeds the WDT + * + * @param hal Context of HAL layer + * + * @note This function can only be called when the WDT is unlocked. Call + * wdt_hal_write_protect_disable() first. + */ +// llgo:link (*WdtHalContextT).WdtHalHandleIntr C.wdt_hal_handle_intr +func (recv_ *WdtHalContextT) WdtHalHandleIntr() { +} + +/** + * @brief Feed the WDT + * + * Feeding the WDT will reset the internal count and current stage. + * + * @param hal Context of HAL layer + * + * @note This function can only be called when the WDT is unlocked. Call + * wdt_hal_write_protect_disable() first. + */ +// llgo:link (*WdtHalContextT).WdtHalFeed C.wdt_hal_feed +func (recv_ *WdtHalContextT) WdtHalFeed() { +} + +/** + * @brief Enable/Disable the WDT flash boot mode + * + * @param hal Context of HAL layer + * @param enable True to enable flash boot mode, false to disable. + * + * @note Flash boot mode can trigger a time out even if the WDT is disabled. + * @note This function can only be called when the WDT is unlocked. Call + * wdt_hal_write_protect_disable() first. + */ +// llgo:link (*WdtHalContextT).WdtHalSetFlashbootEn C.wdt_hal_set_flashboot_en +func (recv_ *WdtHalContextT) WdtHalSetFlashbootEn(enable bool) { +} + +/** + * @brief Check if the WDT is enabled + * + * @param hal Context of HAL layer + * @return True if enabled, false otherwise + */ +// llgo:link (*WdtHalContextT).WdtHalIsEnabled C.wdt_hal_is_enabled +func (recv_ *WdtHalContextT) WdtHalIsEnabled() bool { + return false +} diff --git a/esp32/wdt_periph.go b/esp32/wdt_periph.go new file mode 100644 index 00000000..5d5c92ce --- /dev/null +++ b/esp32/wdt_periph.go @@ -0,0 +1,5 @@ +package freertos + +import _ "unsafe" + +const TIMG_WDT_WKEY_VALUE = 0x50D83AA1 diff --git a/esp32/wdt_types.go b/esp32/wdt_types.go new file mode 100644 index 00000000..b5762f01 --- /dev/null +++ b/esp32/wdt_types.go @@ -0,0 +1,48 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type WdtInstT c.Int + +const ( + WDT_RWDT WdtInstT = 0 + WDT_MWDT0 WdtInstT = 1 + WDT_MWDT1 WdtInstT = 2 +) + +type WdtStageT c.Int + +const ( + WDT_STAGE0 WdtStageT = 0 + WDT_STAGE1 WdtStageT = 1 + WDT_STAGE2 WdtStageT = 2 + WDT_STAGE3 WdtStageT = 3 +) + +type WdtStageActionT c.Int + +const ( + WDT_STAGE_ACTION_OFF WdtStageActionT = 0 + WDT_STAGE_ACTION_INT WdtStageActionT = 1 + WDT_STAGE_ACTION_RESET_CPU WdtStageActionT = 2 + WDT_STAGE_ACTION_RESET_SYSTEM WdtStageActionT = 3 + WDT_STAGE_ACTION_RESET_RTC WdtStageActionT = 4 +) + +type WdtResetSigLengthT c.Int + +const ( + WDT_RESET_SIG_LENGTH_100ns WdtResetSigLengthT = 0 + WDT_RESET_SIG_LENGTH_200ns WdtResetSigLengthT = 1 + WDT_RESET_SIG_LENGTH_300ns WdtResetSigLengthT = 2 + WDT_RESET_SIG_LENGTH_400ns WdtResetSigLengthT = 3 + WDT_RESET_SIG_LENGTH_500ns WdtResetSigLengthT = 4 + WDT_RESET_SIG_LENGTH_800ns WdtResetSigLengthT = 5 + WDT_RESET_SIG_LENGTH_1_6us WdtResetSigLengthT = 6 + WDT_RESET_SIG_LENGTH_3_2us WdtResetSigLengthT = 7 +) + +type MwdtClockSourceT SocPeriphMwdtClkSrcT diff --git a/esp32/world_controller_reg.go b/esp32/world_controller_reg.go new file mode 100644 index 00000000..bcf6196a --- /dev/null +++ b/esp32/world_controller_reg.go @@ -0,0 +1,150 @@ +package freertos + +import _ "unsafe" + +const WCL_CORE_0_ENTRY_1_ADDR_S = 0 +const WCL_CORE_0_ENTRY_2_ADDR_S = 0 +const WCL_CORE_0_ENTRY_3_ADDR_S = 0 +const WCL_CORE_0_ENTRY_4_ADDR_S = 0 +const WCL_CORE_0_ENTRY_5_ADDR_S = 0 +const WCL_CORE_0_ENTRY_6_ADDR_S = 0 +const WCL_CORE_0_ENTRY_7_ADDR_S = 0 +const WCL_CORE_0_ENTRY_8_ADDR_S = 0 +const WCL_CORE_0_ENTRY_9_ADDR_S = 0 +const WCL_CORE_0_ENTRY_10_ADDR_S = 0 +const WCL_CORE_0_ENTRY_11_ADDR_S = 0 +const WCL_CORE_0_ENTRY_12_ADDR_S = 0 +const WCL_CORE_0_ENTRY_13_ADDR_S = 0 +const WCL_CORE_0_ENTRY_CHECK_S = 1 +const WCL_CORE_0_FROM_WORLD_1_S = 0 +const WCL_CORE_0_FROM_ENTRY_1_S = 1 +const WCL_CORE_0_CURRENT_1_S = 5 +const WCL_CORE_0_FROM_WORLD_2_S = 0 +const WCL_CORE_0_FROM_ENTRY_2_S = 1 +const WCL_CORE_0_CURRENT_2_S = 5 +const WCL_CORE_0_FROM_WORLD_3_S = 0 +const WCL_CORE_0_FROM_ENTRY_3_S = 1 +const WCL_CORE_0_CURRENT_3_S = 5 +const WCL_CORE_0_FROM_WORLD_4_S = 0 +const WCL_CORE_0_FROM_ENTRY_4_S = 1 +const WCL_CORE_0_CURRENT_4_S = 5 +const WCL_CORE_0_FROM_WORLD_5_S = 0 +const WCL_CORE_0_FROM_ENTRY_5_S = 1 +const WCL_CORE_0_CURRENT_5_S = 5 +const WCL_CORE_0_FROM_WORLD_6_S = 0 +const WCL_CORE_0_FROM_ENTRY_6_S = 1 +const WCL_CORE_0_CURRENT_6_S = 5 +const WCL_CORE_0_FROM_WORLD_7_S = 0 +const WCL_CORE_0_FROM_ENTRY_7_S = 1 +const WCL_CORE_0_CURRENT_7_S = 5 +const WCL_CORE_0_FROM_WORLD_8_S = 0 +const WCL_CORE_0_FROM_ENTRY_8_S = 1 +const WCL_CORE_0_CURRENT_8_S = 5 +const WCL_CORE_0_FROM_WORLD_9_S = 0 +const WCL_CORE_0_FROM_ENTRY_9_S = 1 +const WCL_CORE_0_CURRENT_9_S = 5 +const WCL_CORE_0_FROM_WORLD_10_S = 0 +const WCL_CORE_0_FROM_ENTRY_10_S = 1 +const WCL_CORE_0_CURRENT_10_S = 5 +const WCL_CORE_0_FROM_WORLD_11_S = 0 +const WCL_CORE_0_FROM_ENTRY_11_S = 1 +const WCL_CORE_0_CURRENT_11_S = 5 +const WCL_CORE_0_FROM_WORLD_12_S = 0 +const WCL_CORE_0_FROM_ENTRY_12_S = 1 +const WCL_CORE_0_CURRENT_12_S = 5 +const WCL_CORE_0_FROM_WORLD_13_S = 0 +const WCL_CORE_0_FROM_ENTRY_13_S = 1 +const WCL_CORE_0_CURRENT_13_S = 5 +const WCL_CORE_0_STATUSTABLE_CURRENT_S = 1 +const WCL_CORE_0_MESSAGE_ADDR_S = 0 +const WCL_CORE_0_MESSAGE_MAX_S = 0 +const WCL_CORE_0_MESSAGE_MATCH_S = 0 +const WCL_CORE_0_MESSAGE_EXPECT_S = 1 +const WCL_CORE_0_MESSAGE_DATAPHASE_S = 5 +const WCL_CORE_0_MESSAGE_ADDRESSPHASE_S = 6 +const WCL_CORE_0_WORLD_TRIGGER_ADDR_S = 0 +const WCL_CORE_0_WORLD_PREPARE_S = 0 +const WCL_CORE_0_UPDATE_S = 0 +const WCL_CORE_0_WORLD_CANCEL_S = 0 +const WCL_CORE_0_WORLD_IRAM0_S = 0 +const WCL_CORE_0_WORLD_DRAM0_PIF_S = 0 +const WCL_CORE_0_WORLD_PHASE_S = 0 +const WCL_CORE_0_NMI_MASK_ENABLE_S = 0 +const WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_S = 0 +const WCL_CORE_0_NMI_MASK_DISABLE_S = 0 +const WCL_CORE_0_NMI_MASK_CANCEL_S = 0 +const WCL_CORE_0_NMI_MASK_S = 0 +const WCL_CORE_0_NMI_MASK_PHASE_S = 0 +const WCL_CORE_1_ENTRY_1_ADDR_S = 0 +const WCL_CORE_1_ENTRY_2_ADDR_S = 0 +const WCL_CORE_1_ENTRY_3_ADDR_S = 0 +const WCL_CORE_1_ENTRY_4_ADDR_S = 0 +const WCL_CORE_1_ENTRY_5_ADDR_S = 0 +const WCL_CORE_1_ENTRY_6_ADDR_S = 0 +const WCL_CORE_1_ENTRY_7_ADDR_S = 0 +const WCL_CORE_1_ENTRY_8_ADDR_S = 0 +const WCL_CORE_1_ENTRY_9_ADDR_S = 0 +const WCL_CORE_1_ENTRY_10_ADDR_S = 0 +const WCL_CORE_1_ENTRY_11_ADDR_S = 0 +const WCL_CORE_1_ENTRY_12_ADDR_S = 0 +const WCL_CORE_1_ENTRY_13_ADDR_S = 0 +const WCL_CORE_1_ENTRY_CHECK_S = 1 +const WCL_CORE_1_FROM_WORLD_1_S = 0 +const WCL_CORE_1_FROM_ENTRY_1_S = 1 +const WCL_CORE_1_CURRENT_1_S = 5 +const WCL_CORE_1_FROM_WORLD_2_S = 0 +const WCL_CORE_1_FROM_ENTRY_2_S = 1 +const WCL_CORE_1_CURRENT_2_S = 5 +const WCL_CORE_1_FROM_WORLD_3_S = 0 +const WCL_CORE_1_FROM_ENTRY_3_S = 1 +const WCL_CORE_1_CURRENT_3_S = 5 +const WCL_CORE_1_FROM_WORLD_4_S = 0 +const WCL_CORE_1_FROM_ENTRY_4_S = 1 +const WCL_CORE_1_CURRENT_4_S = 5 +const WCL_CORE_1_FROM_WORLD_5_S = 0 +const WCL_CORE_1_FROM_ENTRY_5_S = 1 +const WCL_CORE_1_CURRENT_5_S = 5 +const WCL_CORE_1_FROM_WORLD_6_S = 0 +const WCL_CORE_1_FROM_ENTRY_6_S = 1 +const WCL_CORE_1_CURRENT_6_S = 5 +const WCL_CORE_1_FROM_WORLD_7_S = 0 +const WCL_CORE_1_FROM_ENTRY_7_S = 1 +const WCL_CORE_1_CURRENT_7_S = 5 +const WCL_CORE_1_FROM_WORLD_8_S = 0 +const WCL_CORE_1_FROM_ENTRY_8_S = 1 +const WCL_CORE_1_CURRENT_8_S = 5 +const WCL_CORE_1_FROM_WORLD_9_S = 0 +const WCL_CORE_1_FROM_ENTRY_9_S = 1 +const WCL_CORE_1_CURRENT_9_S = 5 +const WCL_CORE_1_FROM_WORLD_10_S = 0 +const WCL_CORE_1_FROM_ENTRY_10_S = 1 +const WCL_CORE_1_CURRENT_10_S = 5 +const WCL_CORE_1_FROM_WORLD_11_S = 0 +const WCL_CORE_1_FROM_ENTRY_11_S = 1 +const WCL_CORE_1_CURRENT_11_S = 5 +const WCL_CORE_1_FROM_WORLD_12_S = 0 +const WCL_CORE_1_FROM_ENTRY_12_S = 1 +const WCL_CORE_1_CURRENT_12_S = 5 +const WCL_CORE_1_FROM_WORLD_13_S = 0 +const WCL_CORE_1_FROM_ENTRY_13_S = 1 +const WCL_CORE_1_CURRENT_13_S = 5 +const WCL_CORE_1_STATUSTABLE_CURRENT_S = 1 +const WCL_CORE_1_MESSAGE_ADDR_S = 0 +const WCL_CORE_1_MESSAGE_MAX_S = 0 +const WCL_CORE_1_MESSAGE_MATCH_S = 0 +const WCL_CORE_1_MESSAGE_EXPECT_S = 1 +const WCL_CORE_1_MESSAGE_DATAPHASE_S = 5 +const WCL_CORE_1_MESSAGE_ADDRESSPHASE_S = 6 +const WCL_CORE_1_WORLD_TRIGGER_ADDR_S = 0 +const WCL_CORE_1_WORLD_PREPARE_S = 0 +const WCL_CORE_1_UPDATE_S = 0 +const WCL_CORE_1_WORLD_CANCEL_S = 0 +const WCL_CORE_1_WORLD_IRAM0_S = 0 +const WCL_CORE_1_WORLD_DRAM0_PIF_S = 0 +const WCL_CORE_1_WORLD_PHASE_S = 0 +const WCL_CORE_1_NMI_MASK_ENABLE_S = 0 +const WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_S = 0 +const WCL_CORE_1_NMI_MASK_DISABLE_S = 0 +const WCL_CORE_1_NMI_MASK_CANCEL_S = 0 +const WCL_CORE_1_NMI_MASK_S = 0 +const WCL_CORE_1_NMI_MASK_PHASE_S = 0 diff --git a/esp32/world_controller_struct.go b/esp32/world_controller_struct.go new file mode 100644 index 00000000..71d99c3a --- /dev/null +++ b/esp32/world_controller_struct.go @@ -0,0 +1,814 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** Group: WORLD1 to WORLD0 configuration Registers */ +/** Type of core_0_entry_1_addr register + * Core_0 Entry 1 address configuration Register + */ + +type WclCore0Entry1AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_entry_2_addr register + * Core_0 Entry 2 address configuration Register + */ + +type WclCore0Entry2AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_entry_3_addr register + * Core_0 Entry 3 address configuration Register + */ + +type WclCore0Entry3AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_entry_4_addr register + * Core_0 Entry 4 address configuration Register + */ + +type WclCore0Entry4AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_entry_5_addr register + * Core_0 Entry 5 address configuration Register + */ + +type WclCore0Entry5AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_entry_6_addr register + * Core_0 Entry 6 address configuration Register + */ + +type WclCore0Entry6AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_entry_7_addr register + * Core_0 Entry 7 address configuration Register + */ + +type WclCore0Entry7AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_entry_8_addr register + * Core_0 Entry 8 address configuration Register + */ + +type WclCore0Entry8AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_entry_9_addr register + * Core_0 Entry 9 address configuration Register + */ + +type WclCore0Entry9AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_entry_10_addr register + * Core_0 Entry 10 address configuration Register + */ + +type WclCore0Entry10AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_entry_11_addr register + * Core_0 Entry 11 address configuration Register + */ + +type WclCore0Entry11AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_entry_12_addr register + * Core_0 Entry 12 address configuration Register + */ + +type WclCore0Entry12AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_entry_13_addr register + * Core_0 Entry 13 address configuration Register + */ + +type WclCore0Entry13AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_entry_check register + * Core_0 Entry check configuration Register + */ + +type WclCore0EntryCheckRegT struct { + Val c.Uint32T +} + +/** Type of core_0_message_addr register + * Clear writer_buffer write address configuration register + */ + +type WclCore0MessageAddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_message_max register + * Clear writer_buffer write number configuration register + */ + +type WclCore0MessageMaxRegT struct { + Val c.Uint32T +} + +/** Type of core_0_message_phase register + * Clear writer_buffer status register + */ + +type WclCore0MessagePhaseRegT struct { + Val c.Uint32T +} + +/** Type of core_1_entry_1_addr register + * Core_1 Entry 1 address configuration Register + */ + +type WclCore1Entry1AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_entry_2_addr register + * Core_1 Entry 2 address configuration Register + */ + +type WclCore1Entry2AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_entry_3_addr register + * Core_1 Entry 3 address configuration Register + */ + +type WclCore1Entry3AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_entry_4_addr register + * Core_1 Entry 4 address configuration Register + */ + +type WclCore1Entry4AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_entry_5_addr register + * Core_1 Entry 5 address configuration Register + */ + +type WclCore1Entry5AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_entry_6_addr register + * Core_1 Entry 6 address configuration Register + */ + +type WclCore1Entry6AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_entry_7_addr register + * Core_1 Entry 7 address configuration Register + */ + +type WclCore1Entry7AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_entry_8_addr register + * Core_1 Entry 8 address configuration Register + */ + +type WclCore1Entry8AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_entry_9_addr register + * Core_1 Entry 9 address configuration Register + */ + +type WclCore1Entry9AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_entry_10_addr register + * Core_1 Entry 10 address configuration Register + */ + +type WclCore1Entry10AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_entry_11_addr register + * Core_1 Entry 11 address configuration Register + */ + +type WclCore1Entry11AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_entry_12_addr register + * Core_1 Entry 12 address configuration Register + */ + +type WclCore1Entry12AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_entry_13_addr register + * Core_1 Entry 13 address configuration Register + */ + +type WclCore1Entry13AddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_entry_check register + * Core_1 Entry check configuration Register + */ + +type WclCore1EntryCheckRegT struct { + Val c.Uint32T +} + +/** Type of core_1_message_addr register + * Clear writer_buffer write address configuration register + */ + +type WclCore1MessageAddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_message_max register + * Clear writer_buffer write number configuration register + */ + +type WclCore1MessageMaxRegT struct { + Val c.Uint32T +} + +/** Type of core_1_message_phase register + * Clear writer_buffer status register + */ + +type WclCore1MessagePhaseRegT struct { + Val c.Uint32T +} + +/** Group: StatusTable Registers */ +/** Type of core_0_statustable1 register + * Status register of world switch of entry 1 + */ + +type WclCore0Statustable1RegT struct { + Val c.Uint32T +} + +/** Type of core_0_statustable2 register + * Status register of world switch of entry 2 + */ + +type WclCore0Statustable2RegT struct { + Val c.Uint32T +} + +/** Type of core_0_statustable3 register + * Status register of world switch of entry 3 + */ + +type WclCore0Statustable3RegT struct { + Val c.Uint32T +} + +/** Type of core_0_statustable4 register + * Status register of world switch of entry 4 + */ + +type WclCore0Statustable4RegT struct { + Val c.Uint32T +} + +/** Type of core_0_statustable5 register + * Status register of world switch of entry 5 + */ + +type WclCore0Statustable5RegT struct { + Val c.Uint32T +} + +/** Type of core_0_statustable6 register + * Status register of world switch of entry 6 + */ + +type WclCore0Statustable6RegT struct { + Val c.Uint32T +} + +/** Type of core_0_statustable7 register + * Status register of world switch of entry 7 + */ + +type WclCore0Statustable7RegT struct { + Val c.Uint32T +} + +/** Type of core_0_statustable8 register + * Status register of world switch of entry 8 + */ + +type WclCore0Statustable8RegT struct { + Val c.Uint32T +} + +/** Type of core_0_statustable9 register + * Status register of world switch of entry 9 + */ + +type WclCore0Statustable9RegT struct { + Val c.Uint32T +} + +/** Type of core_0_statustable10 register + * Status register of world switch of entry 10 + */ + +type WclCore0Statustable10RegT struct { + Val c.Uint32T +} + +/** Type of core_0_statustable11 register + * Status register of world switch of entry 11 + */ + +type WclCore0Statustable11RegT struct { + Val c.Uint32T +} + +/** Type of core_0_statustable12 register + * Status register of world switch of entry 12 + */ + +type WclCore0Statustable12RegT struct { + Val c.Uint32T +} + +/** Type of core_0_statustable13 register + * Status register of world switch of entry 13 + */ + +type WclCore0Statustable13RegT struct { + Val c.Uint32T +} + +/** Type of core_0_statustable_current register + * Status register of statustable current + */ + +type WclCore0StatustableCurrentRegT struct { + Val c.Uint32T +} + +/** Type of core_1_statustable1 register + * Status register of world switch of entry 1 + */ + +type WclCore1Statustable1RegT struct { + Val c.Uint32T +} + +/** Type of core_1_statustable2 register + * Status register of world switch of entry 2 + */ + +type WclCore1Statustable2RegT struct { + Val c.Uint32T +} + +/** Type of core_1_statustable3 register + * Status register of world switch of entry 3 + */ + +type WclCore1Statustable3RegT struct { + Val c.Uint32T +} + +/** Type of core_1_statustable4 register + * Status register of world switch of entry 4 + */ + +type WclCore1Statustable4RegT struct { + Val c.Uint32T +} + +/** Type of core_1_statustable5 register + * Status register of world switch of entry 5 + */ + +type WclCore1Statustable5RegT struct { + Val c.Uint32T +} + +/** Type of core_1_statustable6 register + * Status register of world switch of entry 6 + */ + +type WclCore1Statustable6RegT struct { + Val c.Uint32T +} + +/** Type of core_1_statustable7 register + * Status register of world switch of entry 7 + */ + +type WclCore1Statustable7RegT struct { + Val c.Uint32T +} + +/** Type of core_1_statustable8 register + * Status register of world switch of entry 8 + */ + +type WclCore1Statustable8RegT struct { + Val c.Uint32T +} + +/** Type of core_1_statustable9 register + * Status register of world switch of entry 9 + */ + +type WclCore1Statustable9RegT struct { + Val c.Uint32T +} + +/** Type of core_1_statustable10 register + * Status register of world switch of entry 10 + */ + +type WclCore1Statustable10RegT struct { + Val c.Uint32T +} + +/** Type of core_1_statustable11 register + * Status register of world switch of entry 11 + */ + +type WclCore1Statustable11RegT struct { + Val c.Uint32T +} + +/** Type of core_1_statustable12 register + * Status register of world switch of entry 12 + */ + +type WclCore1Statustable12RegT struct { + Val c.Uint32T +} + +/** Type of core_1_statustable13 register + * Status register of world switch of entry 13 + */ + +type WclCore1Statustable13RegT struct { + Val c.Uint32T +} + +/** Type of core_1_statustable_current register + * Status register of statustable current + */ + +type WclCore1StatustableCurrentRegT struct { + Val c.Uint32T +} + +/** Group: WORLD0 to WORLD1 configuration Registers */ +/** Type of core_0_world_trigger_addr register + * Core_0 trigger address configuration Register + */ + +type WclCore0WorldTriggerAddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_world_prepare register + * Core_0 prepare world configuration Register + */ + +type WclCore0WorldPrepareRegT struct { + Val c.Uint32T +} + +/** Type of core_0_world_update register + * Core_0 configuration update register + */ + +type WclCore0WorldUpdateRegT struct { + Val c.Uint32T +} + +/** Type of core_0_world_cancel register + * Core_0 configuration cancel register + */ + +type WclCore0WorldCancelRegT struct { + Val c.Uint32T +} + +/** Type of core_0_world_iram0 register + * Core_0 Iram0 world register + */ + +type WclCore0WorldIram0RegT struct { + Val c.Uint32T +} + +/** Type of core_0_world_dram0_pif register + * Core_0 dram0 and PIF world register + */ + +type WclCore0WorldDram0PifRegT struct { + Val c.Uint32T +} + +/** Type of core_0_world_phase register + * Core_0 world status register + */ + +type WclCore0WorldPhaseRegT struct { + Val c.Uint32T +} + +/** Type of core_1_world_trigger_addr register + * Core_1 trigger address configuration Register + */ + +type WclCore1WorldTriggerAddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_world_prepare register + * Core_1 prepare world configuration Register + */ + +type WclCore1WorldPrepareRegT struct { + Val c.Uint32T +} + +/** Type of core_1_world_update register + * Core_1 configuration update register + */ + +type WclCore1WorldUpdateRegT struct { + Val c.Uint32T +} + +/** Type of core_1_world_cancel register + * Core_1 configuration cancel register + */ + +type WclCore1WorldCancelRegT struct { + Val c.Uint32T +} + +/** Type of core_1_world_iram0 register + * Core_1 Iram0 world register + */ + +type WclCore1WorldIram0RegT struct { + Val c.Uint32T +} + +/** Type of core_1_world_dram0_pif register + * Core_1 dram0 and PIF world register + */ + +type WclCore1WorldDram0PifRegT struct { + Val c.Uint32T +} + +/** Type of core_1_world_phase register + * Core_0 world status register + */ + +type WclCore1WorldPhaseRegT struct { + Val c.Uint32T +} + +/** Group: NMI mask configuration Registers */ +/** Type of core_0_nmi_mask_enable register + * Core_0 NMI mask enable register + */ + +type WclCore0NmiMaskEnableRegT struct { + Val c.Uint32T +} + +/** Type of core_0_nmi_mask_trigger_addr register + * Core_0 NMI mask trigger address register + */ + +type WclCore0NmiMaskTriggerAddrRegT struct { + Val c.Uint32T +} + +/** Type of core_0_nmi_mask_disable register + * Core_0 NMI mask disable register + */ + +type WclCore0NmiMaskDisableRegT struct { + Val c.Uint32T +} + +/** Type of core_0_nmi_mask_cancle register + * Core_0 NMI mask disable register + */ + +type WclCore0NmiMaskCancleRegT struct { + Val c.Uint32T +} + +/** Type of core_0_nmi_mask register + * Core_0 NMI mask register + */ + +type WclCore0NmiMaskRegT struct { + Val c.Uint32T +} + +/** Type of core_0_nmi_mask_phase register + * Core_0 NMI mask phase register + */ + +type WclCore0NmiMaskPhaseRegT struct { + Val c.Uint32T +} + +/** Type of core_1_nmi_mask_enable register + * Core_1 NMI mask enable register + */ + +type WclCore1NmiMaskEnableRegT struct { + Val c.Uint32T +} + +/** Type of core_1_nmi_mask_trigger_addr register + * Core_1 NMI mask trigger addr register + */ + +type WclCore1NmiMaskTriggerAddrRegT struct { + Val c.Uint32T +} + +/** Type of core_1_nmi_mask_disable register + * Core_1 NMI mask disable register + */ + +type WclCore1NmiMaskDisableRegT struct { + Val c.Uint32T +} + +/** Type of core_1_nmi_mask_cancle register + * Core_1 NMI mask disable register + */ + +type WclCore1NmiMaskCancleRegT struct { + Val c.Uint32T +} + +/** Type of core_1_nmi_mask register + * Core_1 NMI mask register + */ + +type WclCore1NmiMaskRegT struct { + Val c.Uint32T +} + +/** Type of core_1_nmi_mask_phase register + * Core_1 NMI mask phase register + */ + +type WclCore1NmiMaskPhaseRegT struct { + Val c.Uint32T +} + +type WclDevT struct { + Core0Entry1Addr WclCore0Entry1AddrRegT + Core0Entry2Addr WclCore0Entry2AddrRegT + Core0Entry3Addr WclCore0Entry3AddrRegT + Core0Entry4Addr WclCore0Entry4AddrRegT + Core0Entry5Addr WclCore0Entry5AddrRegT + Core0Entry6Addr WclCore0Entry6AddrRegT + Core0Entry7Addr WclCore0Entry7AddrRegT + Core0Entry8Addr WclCore0Entry8AddrRegT + Core0Entry9Addr WclCore0Entry9AddrRegT + Core0Entry10Addr WclCore0Entry10AddrRegT + Core0Entry11Addr WclCore0Entry11AddrRegT + Core0Entry12Addr WclCore0Entry12AddrRegT + Core0Entry13Addr WclCore0Entry13AddrRegT + Reserved034 [18]c.Uint32T + Core0EntryCheck WclCore0EntryCheckRegT + Core0Statustable1 WclCore0Statustable1RegT + Core0Statustable2 WclCore0Statustable2RegT + Core0Statustable3 WclCore0Statustable3RegT + Core0Statustable4 WclCore0Statustable4RegT + Core0Statustable5 WclCore0Statustable5RegT + Core0Statustable6 WclCore0Statustable6RegT + Core0Statustable7 WclCore0Statustable7RegT + Core0Statustable8 WclCore0Statustable8RegT + Core0Statustable9 WclCore0Statustable9RegT + Core0Statustable10 WclCore0Statustable10RegT + Core0Statustable11 WclCore0Statustable11RegT + Core0Statustable12 WclCore0Statustable12RegT + Core0Statustable13 WclCore0Statustable13RegT + Reserved0b4 [18]c.Uint32T + Core0StatustableCurrent WclCore0StatustableCurrentRegT + Core0MessageAddr WclCore0MessageAddrRegT + Core0MessageMax WclCore0MessageMaxRegT + Core0MessagePhase WclCore0MessagePhaseRegT + Reserved10c [13]c.Uint32T + Core0WorldTriggerAddr WclCore0WorldTriggerAddrRegT + Core0WorldPrepare WclCore0WorldPrepareRegT + Core0WorldUpdate WclCore0WorldUpdateRegT + Core0WorldCancel WclCore0WorldCancelRegT + Core0WorldIram0 WclCore0WorldIram0RegT + Core0WorldDram0Pif WclCore0WorldDram0PifRegT + Core0WorldPhase WclCore0WorldPhaseRegT + Reserved15c [9]c.Uint32T + Core0NmiMaskEnable WclCore0NmiMaskEnableRegT + Core0NmiMaskTriggerAddr WclCore0NmiMaskTriggerAddrRegT + Core0NmiMaskDisable WclCore0NmiMaskDisableRegT + Core0NmiMaskCancle WclCore0NmiMaskCancleRegT + Core0NmiMask WclCore0NmiMaskRegT + Core0NmiMaskPhase WclCore0NmiMaskPhaseRegT + Reserved198 [154]c.Uint32T + Core1Entry1Addr WclCore1Entry1AddrRegT + Core1Entry2Addr WclCore1Entry2AddrRegT + Core1Entry3Addr WclCore1Entry3AddrRegT + Core1Entry4Addr WclCore1Entry4AddrRegT + Core1Entry5Addr WclCore1Entry5AddrRegT + Core1Entry6Addr WclCore1Entry6AddrRegT + Core1Entry7Addr WclCore1Entry7AddrRegT + Core1Entry8Addr WclCore1Entry8AddrRegT + Core1Entry9Addr WclCore1Entry9AddrRegT + Core1Entry10Addr WclCore1Entry10AddrRegT + Core1Entry11Addr WclCore1Entry11AddrRegT + Core1Entry12Addr WclCore1Entry12AddrRegT + Core1Entry13Addr WclCore1Entry13AddrRegT + Reserved434 [18]c.Uint32T + Core1EntryCheck WclCore1EntryCheckRegT + Core1Statustable1 WclCore1Statustable1RegT + Core1Statustable2 WclCore1Statustable2RegT + Core1Statustable3 WclCore1Statustable3RegT + Core1Statustable4 WclCore1Statustable4RegT + Core1Statustable5 WclCore1Statustable5RegT + Core1Statustable6 WclCore1Statustable6RegT + Core1Statustable7 WclCore1Statustable7RegT + Core1Statustable8 WclCore1Statustable8RegT + Core1Statustable9 WclCore1Statustable9RegT + Core1Statustable10 WclCore1Statustable10RegT + Core1Statustable11 WclCore1Statustable11RegT + Core1Statustable12 WclCore1Statustable12RegT + Core1Statustable13 WclCore1Statustable13RegT + Reserved4b4 [18]c.Uint32T + Core1StatustableCurrent WclCore1StatustableCurrentRegT + Core1MessageAddr WclCore1MessageAddrRegT + Core1MessageMax WclCore1MessageMaxRegT + Core1MessagePhase WclCore1MessagePhaseRegT + Reserved50c [13]c.Uint32T + Core1WorldTriggerAddr WclCore1WorldTriggerAddrRegT + Core1WorldPrepare WclCore1WorldPrepareRegT + Core1WorldUpdate WclCore1WorldUpdateRegT + Core1WorldCancel WclCore1WorldCancelRegT + Core1WorldIram0 WclCore1WorldIram0RegT + Core1WorldDram0Pif WclCore1WorldDram0PifRegT + Core1WorldPhase WclCore1WorldPhaseRegT + Reserved55c [9]c.Uint32T + Core1NmiMaskEnable WclCore1NmiMaskEnableRegT + Core1NmiMaskTriggerAddr WclCore1NmiMaskTriggerAddrRegT + Core1NmiMaskDisable WclCore1NmiMaskDisableRegT + Core1NmiMaskCancle WclCore1NmiMaskCancleRegT + Core1NmiMask WclCore1NmiMaskRegT + Core1NmiMaskPhase WclCore1NmiMaskPhaseRegT +} diff --git a/esp32/xdm-regs.go b/esp32/xdm-regs.go new file mode 100644 index 00000000..edc6624a --- /dev/null +++ b/esp32/xdm-regs.go @@ -0,0 +1,262 @@ +package freertos + +import _ "unsafe" + +const XDM_TRAX_ID = 0x100000 +const XDM_TRAX_CONTROL = 0x100004 +const XDM_TRAX_STATUS = 0x100008 +const XDM_TRAX_DATA = 0x10000C +const XDM_TRAX_ADDRESS = 0x100010 +const XDM_TRAX_TRIGGER = 0x100014 +const XDM_TRAX_MATCH = 0x100018 +const XDM_TRAX_DELAY = 0x10001C +const XDM_TRAX_STARTADDR = 0x100020 +const XDM_TRAX_ENDADDR = 0x100024 +const XDM_TRAX_DEBUGPC = 0x10003C +const XDM_TRAX_P4CHANGE = 0x100040 +const XDM_TRAX_TIME0 = 0x100040 +const XDM_TRAX_P4REV = 0x100044 +const XDM_TRAX_TIME1 = 0x100044 +const XDM_TRAX_P4DATE = 0x100048 +const XDM_TRAX_INTTIME_MAX = 0x100048 +const XDM_TRAX_P4TIME = 0x10004C +const XDM_TRAX_PDSTATUS = 0x100050 +const XDM_TRAX_PDDATA = 0x100054 +const XDM_TRAX_STOP_PC = 0x100058 +const XDM_TRAX_STOP_ICNT = 0x10005C +const XDM_TRAX_MSG_STATUS = 0x100060 +const XDM_TRAX_FSM_STATUS = 0x100064 +const XDM_TRAX_IB_STATUS = 0x100068 +const XDM_TRAX_STOPCNT = 0x10006C +const XDM_PERF_PMG = 0x101000 +const XDM_PERF_INTPC = 0x101010 +const XDM_PERF_PM0 = 0x101080 +const XDM_PERF_PM1 = 0x101084 +const XDM_PERF_PM2 = 0x101088 +const XDM_PERF_PM3 = 0x10108C +const XDM_PERF_PM4 = 0x101090 +const XDM_PERF_PM5 = 0x101094 +const XDM_PERF_PM6 = 0x101098 +const XDM_PERF_PM7 = 0x10109C +const XDM_PERF_PMCTRL0 = 0x101100 +const XDM_PERF_PMCTRL1 = 0x101104 +const XDM_PERF_PMCTRL2 = 0x101108 +const XDM_PERF_PMCTRL3 = 0x10110C +const XDM_PERF_PMCTRL4 = 0x101110 +const XDM_PERF_PMCTRL5 = 0x101114 +const XDM_PERF_PMCTRL6 = 0x101118 +const XDM_PERF_PMCTRL7 = 0x10111C +const XDM_PERF_PMSTAT0 = 0x101180 +const XDM_PERF_PMSTAT1 = 0x101184 +const XDM_PERF_PMSTAT2 = 0x101188 +const XDM_PERF_PMSTAT3 = 0x10118C +const XDM_PERF_PMSTAT4 = 0x101190 +const XDM_PERF_PMSTAT5 = 0x101194 +const XDM_PERF_PMSTAT6 = 0x101198 +const XDM_PERF_PMSTAT7 = 0x10119C +const XDM_OCD_ID = 0x102000 +const XDM_OCD_DCR_CLR = 0x102008 +const XDM_OCD_DCR_SET = 0x10200C +const XDM_OCD_DSR = 0x102010 +const XDM_OCD_DDR = 0x102014 +const XDM_OCD_DDREXEC = 0x102018 +const XDM_OCD_DIR0EXEC = 0x10201C +const XDM_OCD_DIR0 = 0x102020 +const XDM_OCD_DIR1 = 0x102024 +const XDM_OCD_DIR2 = 0x102028 +const XDM_OCD_DIR3 = 0x10202C +const XDM_OCD_DIR4 = 0x102030 +const XDM_OCD_DIR5 = 0x102034 +const XDM_OCD_DIR6 = 0x102038 +const XDM_OCD_DIR7 = 0x10203C +const XDM_MISC_PWRCTL = 0x103020 +const XDM_MISC_PWRSTAT = 0x103024 +const XDM_MISC_ERISTAT = 0x103028 +const XDM_MISC_DATETIME = 0x103034 +const XDM_MISC_CONFIGID1_V0 = 0x103034 +const XDM_MISC_CONFIGID1_V2 = 0x10007c +const XDM_MISC_CONFIGID0_V2 = 0x100078 +const XDM_MISC_UBID = 0x103038 +const XDM_MISC_CID = 0x10303C +const XDM_CS_ITCTRL = 0x103F00 +const XDM_CS_CLAIMSET = 0x103FA0 +const XDM_CS_CLAIMCLR = 0x103FA4 +const XDM_CS_LOCK_ACCESS = 0x103FB0 +const XDM_CS_LOCK_STATUS = 0x103FB4 +const XDM_CS_AUTH_STATUS = 0x103FB8 +const XDM_CS_DEV_ID = 0x103FC8 +const XDM_CS_DEV_TYPE = 0x103FCC +const XDM_CS_PER_ID4 = 0x103FD0 +const XDM_CS_PER_ID5 = 0x103FD4 +const XDM_CS_PER_ID6 = 0x103FD8 +const XDM_CS_PER_ID7 = 0x103FDC +const XDM_CS_PER_ID0 = 0x103FE0 +const XDM_CS_PER_ID1 = 0x103FE4 +const XDM_CS_PER_ID2 = 0x103FE8 +const XDM_CS_PER_ID3 = 0x103FEC +const XDM_CS_COMP_ID0 = 0x103FF0 +const XDM_CS_COMP_ID1 = 0x103FF4 +const XDM_CS_COMP_ID2 = 0x103FF8 +const XDM_CS_COMP_ID3 = 0x103FFC +const CS_PER_ID0 = 0x00000003 +const CS_PER_ID1 = 0x00000021 +const CS_PER_ID2 = 0x0000000f +const CS_PER_ID3 = 0x00000000 +const CS_PER_ID4 = 0x00000024 +const CS_COMP_ID0 = 0x0000000d +const CS_COMP_ID1 = 0x00000090 +const CS_COMP_ID2 = 0x00000005 +const CS_COMP_ID3 = 0x000000b1 +const CS_DEV_TYPE = 0x00000015 +const XTENSA_IDCODE = 0x120034e5 +const CS_DEV_ID_v0_MASK = 0x00000FFF +const CS_DEV_ID_v2_MASK = 0xF0000000 +const OCD_ID_LSDDRP = 0x01000000 +const OCD_ID_LSDDRP_SHIFT = 24 +const OCD_ID_ENDIANESS = 0x00000001 +const OCD_ID_ENDIANESS_SHIFT = 0 +const OCD_ID_PSO = 0x0000000C +const OCD_ID_PSO_SHIFT = 2 +const OCD_ID_TRACEPORT = 0x00000080 +const OCD_ID_TRACEPORT_SHIFT = 7 +const OCD_ID_LSDDRP_XEA3 = 0x00000400 +const PWRSTAT_CORE_DOMAIN_ON = 0x00000001 +const PWRSTAT_CORE_DOMAIN_ON_SHIFT = 0 +const PWRSTAT_WAKEUP_RESET = 0x00000002 +const PWRSTAT_WAKEUP_RESET_SHIFT = 1 +const PWRSTAT_CACHES_LOST_POWER = 0x00000004 +const PWRSTAT_CACHES_LOST_POWER_SHIFT = 2 +const PWRSTAT_CORE_STILL_NEEDED = 0x00000010 +const PWRSTAT_CORE_STILL_NEEDED_SHIFT = 4 +const PWRSTAT_MEM_DOMAIN_ON = 0x00000100 +const PWRSTAT_MEM_DOMAIN_ON_SHIFT = 8 +const PWRSTAT_DEBUG_DOMAIN_ON = 0x00001000 +const PWRSTAT_DEBUG_DOMAIN_ON_SHIFT = 12 +const PWRSTAT_CORE_WAS_RESET = 0x00010000 +const PWRSTAT_CORE_WAS_RESET_SHIFT = 16 +const PWRSTAT_DEBUG_WAS_RESET = 0x10000000 +const PWRSTAT_DEBUG_WAS_RESET_SHIFT = 28 +const J_PWRSTAT_CORE_DOMAIN_ON = 0x01 +const J_PWRSTAT_MEM_DOMAIN_ON = 0x02 +const J_PWRSTAT_DEBUG_DOMAIN_ON = 0x04 +const J_PWRSTAT_CORE_STILL_NEEDED = 0x08 +const J_PWRSTAT_CORE_WAS_RESET = 0x10 +const J_PWRSTAT_DEBUG_WAS_RESET = 0x40 +const PWRCTL_CORE_SHUTOFF = 0x00000001 +const PWRCTL_CORE_SHUTOFF_SHIFT = 0 +const PWRCTL_CORE_WAKEUP = 0x00000001 +const PWRCTL_CORE_WAKEUP_SHIFT = 0 +const PWRCTL_MEM_WAKEUP = 0x00000100 +const PWRCTL_MEM_WAKEUP_SHIFT = 8 +const PWRCTL_DEBUG_WAKEUP = 0x00001000 +const PWRCTL_DEBUG_WAKEUP_SHIFT = 12 +const PWRCTL_CORE_RESET = 0x00010000 +const PWRCTL_CORE_RESET_SHIFT = 16 +const PWRCTL_DEBUG_RESET = 0x10000000 +const PWRCTL_DEBUG_RESET_SHIFT = 28 +const J_PWRCTL_CORE_WAKEUP = 0x01 +const J_PWRCTL_MEM_WAKEUP = 0x02 +const J_PWRCTL_DEBUG_WAKEUP = 0x04 +const J_DEBUG_USE = 0x80 +const J_PWRCTL_CORE_RESET = 0x10 +const J_PWRCTL_DEBUG_RESET = 0x40 +const J_PWRCTL_WRITE_MASK = 0xFF +const J_PWRSTAT_WRITE_MASK = 0xFF +const XDM_IR_PWRCTL = 0x08 +const XDM_IR_PWRSTAT = 0x09 +const XDM_IR_NAR_SEL = 0x1c +const XDM_IR_NDR_SEL = 0x1d +const XDM_IR_IDCODE = 0x1e +const XDM_IR_BYPASS = 0x1f +const XDM_IR_WIDTH = 5 +const XDM_NAR_WRITE = 0x01 +const XDM_NAR_ADDR_MASK = 0xFE +const XDM_NAR_ADDR_SHIFT = 1 +const XDM_NAR_BUSY = 0x02 +const XDM_NAR_ERROR = 0x01 +const NEXUS_DIR_READ = 0x00 +const NEXUS_DIR_WRITE = 0x01 +const DCR_ENABLEOCD = 0x0000001 +const DCR_ENABLEOCD_SHIFT = 0 +const DCR_DEBUG_INT = 0x0000002 +const DCR_DEBUG_INT_SHIFT = 1 +const DCR_DEBUG_OVERRIDE = 0x0000004 +const DCR_DEBUG_OVERRIDE_SHIFT = 2 +const DCR_DEBUG_SS_REQ = 0x0000008 +const DCR_DEBUG_SS_REQ_SHIFT = 3 +const DCR_DEBUG_OVERRIDE_CW = 0x0000010 +const DCR_DEBUG_OVERRIDE_CW_SHIFT = 4 +const DCR_MASK_NMI = 0x0000020 +const DCR_MASK_NMI_SHIFT = 5 +const DCR_STEP_ENABLE = 0x0000040 +const DCR_STEP_ENABLE_SHIFT = 6 +const DCR_BREAK_IN_EN = 0x0010000 +const DCR_BREAK_IN_EN_SHIFT = 16 +const DCR_BREAK_OUT_EN = 0x0020000 +const DCR_BREAK_OUT_EN_SHIFT = 17 +const DCR_DEBUG_INT_EN = 0x0040000 +const DCR_DEBUG_INT_EN_SHIFT = 18 +const DCR_DBG_SW_ACTIVE = 0x0100000 +const DCR_DBG_SW_ACTIVE_SHIFT = 20 +const DCR_STALL_IN_EN = 0x0200000 +const DCR_STALL_IN_EN_SHIFT = 21 +const DCR_DEBUG_OUT_EN = 0x0400000 +const DCR_DEBUG_OUT_EN_SHIFT = 22 +const DCR_BREAK_OUT_ITO = 0x1000000 +const DCR_STALL_OUT_ITO = 0x2000000 +const DCR_STALL_OUT_ITO_SHIFT = 25 +const DOSR_STOP_CAUSE_SHIFT = 5 +const DOSR_STOP_CAUSE_MASK = 0xF +const DOSR_EXECDONE_SHIFT = 0 +const DOSR_EXECDONE_ER = 0x01 +const DOSR_EXCEPTION_ER = 0x02 +const DOSR_EXCEPTION_SHIFT = 1 +const DOSR_BUSY = 0x04 +const DOSR_BUSY_SHIFT = 2 +const DOSR_OVERRUN = 0x08 +const DOSR_OVERRUN_SHIFT = 3 +const DOSR_INOCDMODE_ER = 0x10 +const DOSR_INOCDMODE_SHIFT = 4 +const DOSR_CORE_WROTE_DDR_ER = 0x400 +const DOSR_CORE_WROTE_DDR_SHIFT = 10 +const DOSR_CORE_READ_DDR_ER = 0x800 +const DOSR_CORE_READ_DDR_SHIFT = 11 +const DOSR_HOST_WROTE_DDR_ER = 0x4000 +const DOSR_HOST_WROTE_DDR_SHIFT = 14 +const DOSR_HOST_READ_DDR_ER = 0x8000 +const DOSR_HOST_READ_DDR_SHIFT = 15 +const DOSR_DEBUG_PEND_BIN = 0x10000 +const DOSR_DEBUG_PEND_HOST = 0x20000 +const DOSR_DEBUG_PEND_TRAX = 0x40000 +const DOSR_DEBUG_BIN = 0x100000 +const DOSR_DEBUG_HOST = 0x200000 +const DOSR_DEBUG_TRAX = 0x400000 +const DOSR_DEBUG_PEND_BIN_SHIFT = 16 +const DOSR_DEBUG_PEND_HOST_SHIFT = 17 +const DOSR_DEBUG_PEND_TRAX_SHIFT = 18 +const DOSR_DEBUG_BREAKIN = 0x0100000 +const DOSR_DEBUG_BREAKIN_SHIFT = 20 +const DOSR_DEBUG_HOST_SHIFT = 21 +const DOSR_DEBUG_TRAX_SHIFT = 22 +const DOSR_DEBUG_STALL = 0x1000000 +const DOSR_DEBUG_STALL_SHIFT = 24 +const DOSR_CORE_ON = 0x40000000 +const DOSR_CORE_ON_SHIFT = 30 +const DOSR_DEBUG_ON = 0x80000000 +const DOSR_DEBUG_ON_SHIFT = 31 +const PERF_PMG_ENABLE = 0x00000001 +const PERF_PMG_ENABLE_SHIFT = 0 +const PERF_PMCTRL_INT_ENABLE = 0x00000001 +const PERF_PMCTRL_INT_ENABLE_SHIFT = 0 +const PERF_PMCTRL_KRNLCNT = 0x00000008 +const PERF_PMCTRL_KRNLCNT_SHIFT = 3 +const PERF_PMCTRL_TRACELEVEL = 0x000000F0 +const PERF_PMCTRL_TRACELEVEL_SHIFT = 4 +const PERF_PMCTRL_SELECT = 0x00001F00 +const PERF_PMCTRL_SELECT_SHIFT = 8 +const PERF_PMCTRL_MASK = 0xFFFF0000 +const PERF_PMCTRL_MASK_SHIFT = 16 +const PERF_PMSTAT_OVERFLOW = 0x00000001 +const PERF_PMSTAT_OVERFLOW_SHIFT = 0 +const PERF_PMSTAT_INT = 0x00000010 +const PERF_PMSTAT_INT_SHIFT = 4 diff --git a/esp32/xt_instr_macros.go b/esp32/xt_instr_macros.go new file mode 100644 index 00000000..ac2c554f --- /dev/null +++ b/esp32/xt_instr_macros.go @@ -0,0 +1,7 @@ +package freertos + +import _ "unsafe" + +const EXTRA_SAVE_AREA_SIZE = 32 +const BASE_SAVE_AREA_SIZE = 16 +const BASE_AREA_SP_OFFSET = 12 diff --git a/esp32/xt_perf_consts.go b/esp32/xt_perf_consts.go new file mode 100644 index 00000000..5308a404 --- /dev/null +++ b/esp32/xt_perf_consts.go @@ -0,0 +1,159 @@ +package freertos + +import _ "unsafe" + +const XTPERF_CNT_COMMITTED_INSN = 0x8002 +const XTPERF_CNT_BRANCH_PENALTY = 0x8003 +const XTPERF_CNT_PIPELINE_INTERLOCKS = 0x8004 +const XTPERF_CNT_ICACHE_MISSES = 0x8005 +const XTPERF_CNT_DCACHE_MISSES = 0x8006 +const XTPERF_CNT_CYCLES = 0 +const XTPERF_CNT_OVERFLOW = 1 +const XTPERF_CNT_INSN = 2 +const XTPERF_CNT_D_STALL = 3 +const XTPERF_CNT_I_STALL = 4 +const XTPERF_CNT_EXR = 5 +const XTPERF_CNT_BUBBLES = 6 +const XTPERF_CNT_I_TLB = 7 +const XTPERF_CNT_I_MEM = 8 +const XTPERF_CNT_D_TLB = 9 +const XTPERF_CNT_D_LOAD_U1 = 10 +const XTPERF_CNT_D_STORE_U1 = 11 +const XTPERF_CNT_D_ACCESS_U1 = 12 +const XTPERF_CNT_D_LOAD_U2 = 13 +const XTPERF_CNT_D_STORE_U2 = 14 +const XTPERF_CNT_D_ACCESS_U2 = 15 +const XTPERF_CNT_D_LOAD_U3 = 16 +const XTPERF_CNT_D_STORE_U3 = 17 +const XTPERF_CNT_D_ACCESS_U3 = 18 +const XTPERF_CNT_MULTIPLE_LS = 22 +const XTPERF_CNT_OUTBOUND_PIF = 23 +const XTPERF_CNT_INBOUND_PIF = 24 +const XTPERF_CNT_PREFETCH = 26 +const XTPERF_CNT_IDMA = 27 +const XTPERF_CNT_INSN_LENGTH = 28 +const XTPERF_MASK_COMMITTED_INSN = 0x0001 +const XTPERF_MASK_BRANCH_PENALTY = 0x0001 +const XTPERF_MASK_PIPELINE_INTERLOCKS = 0x0001 +const XTPERF_MASK_ICACHE_MISSES = 0x0001 +const XTPERF_MASK_DCACHE_MISSES = 0x0001 +const XTPERF_MASK_CYCLES = 0x0001 +const XTPERF_MASK_OVERFLOW = 0x0001 +const XTPERF_MASK_INSN_ALL = 0x8DFF +const XTPERF_MASK_INSN_JX = 0x0001 +const XTPERF_MASK_INSN_CALLX = 0x0002 +const XTPERF_MASK_INSN_RET = 0x0004 +const XTPERF_MASK_INSN_RF = 0x0008 +const XTPERF_MASK_INSN_BRANCH_TAKEN = 0x0010 +const XTPERF_MASK_INSN_J = 0x0020 +const XTPERF_MASK_INSN_CALL = 0x0040 +const XTPERF_MASK_INSN_BRANCH_NOT_TAKEN = 0x0080 +const XTPERF_MASK_INSN_LOOP_TAKEN = 0x0100 +const XTPERF_MASK_INSN_LOOP_BEG = 0x0400 +const XTPERF_MASK_INSN_LOOP_END = 0x0800 +const XTPERF_MASK_INSN_NON_BRANCH = 0x8000 +const XTPERF_MASK_D_STALL_ALL = 0x01FE +const XTPERF_MASK_D_STALL_STORE_BUF_FULL = 0x0002 +const XTPERF_MASK_D_STALL_STORE_BUF_CONFLICT = 0x0004 +const XTPERF_MASK_D_STALL_CACHE_MISS = 0x0008 +const XTPERF_MASK_D_STALL_BUSY = 0x0010 +const XTPERF_MASK_D_STALL_IN_PIF = 0x0020 +const XTPERF_MASK_D_STALL_MHT_LOOKUP = 0x0040 +const XTPERF_MASK_D_STALL_UNCACHED_LOAD = 0x0080 +const XTPERF_MASK_D_STALL_BANK_CONFLICT = 0x0100 +const XTPERF_MASK_I_STALL_ALL = 0x01FF +const XTPERF_MASK_I_STALL_CACHE_MISS = 0x0001 +const XTPERF_MASK_I_STALL_BUSY = 0x0002 +const XTPERF_MASK_I_STALL_IN_PIF = 0x0004 +const XTPERF_MASK_I_STALL_TIE_PORT = 0x0008 +const XTPERF_MASK_I_STALL_EXTERNAL_SIGNAL = 0x0010 +const XTPERF_MASK_I_STALL_UNCACHED_FETCH = 0x0020 +const XTPERF_MASK_I_STALL_FAST_L32R = 0x0040 +const XTPERF_MASK_I_STALL_ITERATIVE_MUL = 0x0080 +const XTPERF_MASK_I_STALL_ITERATIVE_DIV = 0x0100 +const XTPERF_MASK_EXR_ALL = 0x01FF +const XTPERF_MASK_EXR_REPLAYS = 0x0001 +const XTPERF_MASK_EXR_LEVEL1_INT = 0x0002 +const XTPERF_MASK_EXR_LEVELH_INT = 0x0004 +const XTPERF_MASK_EXR_DEBUG = 0x0008 +const XTPERF_MASK_EXR_NMI = 0x0010 +const XTPERF_MASK_EXR_WINDOW = 0x0020 +const XTPERF_MASK_EXR_ALLOCA = 0x0040 +const XTPERF_MASK_EXR_OTHER = 0x0080 +const XTPERF_MASK_EXR_MEM_ERR = 0x0100 +const XTPERF_MASK_BUBBLES_ALL = 0x01FD +const XTPERF_MASK_BUBBLES_PSO = 0x0001 +const XTPERF_MASK_BUBBLES_R_HOLD_D_CACHE_MISS = 0x0004 +const XTPERF_MASK_BUBBLES_R_HOLD_STORE_RELEASE = 0x0008 +const XTPERF_MASK_BUBBLES_R_HOLD_REG_DEP = 0x0010 +const XTPERF_MASK_BUBBLES_R_HOLD_WAIT = 0x0020 +const XTPERF_MASK_BUBBLES_R_HOLD_HALT = 0x0040 +const XTPERF_MASK_BUBBLES_CTI = 0x0080 +const XTPERF_MASK_BUBBLES_WAITI = 0x0100 +const XTPERF_MASK_I_TLB_ALL = 0x000F +const XTPERF_MASK_I_TLB_HITS = 0x0001 +const XTPERF_MASK_I_TLB_REPLAYS = 0x0002 +const XTPERF_MASK_I_TLB_REFILLS = 0x0004 +const XTPERF_MASK_I_TLB_MISSES = 0x0008 +const XTPERF_MASK_I_MEM_ALL = 0x000F +const XTPERF_MASK_I_MEM_CACHE_HITS = 0x0001 +const XTPERF_MASK_I_MEM_CACHE_MISSES = 0x0002 +const XTPERF_MASK_I_MEM_IRAM = 0x0004 +const XTPERF_MASK_I_MEM_BYPASS = 0x0008 +const XTPERF_MASK_D_TLB_ALL = 0x000F +const XTPERF_MASK_D_TLB_HITS = 0x0001 +const XTPERF_MASK_D_TLB_REPLAYS = 0x0002 +const XTPERF_MASK_D_TLB_REFILLS = 0x0004 +const XTPERF_MASK_D_TLB_MISSES = 0x0008 +const XTPERF_MASK_D_LOAD_ALL = 0x000F +const XTPERF_MASK_D_LOAD_CACHE_HITS = 0x0001 +const XTPERF_MASK_D_LOAD_CACHE_MISSES = 0x0002 +const XTPERF_MASK_D_LOAD_LOCAL_MEM = 0x0004 +const XTPERF_MASK_D_LOAD_BYPASS = 0x0008 +const XTPERF_MASK_D_STORE_ALL = 0x000F +const XTPERF_MASK_D_STORE_CACHE_HITS = 0x0001 +const XTPERF_MASK_D_STORE_CACHE_MISSES = 0x0002 +const XTPERF_MASK_D_STORE_LOCAL_MEM = 0x0004 +const XTPERF_MASK_D_STORE_PIF = 0x0008 +const XTPERF_MASK_D_ACCESS_ALL = 0x000F +const XTPERF_MASK_D_ACCESS_CACHE_MISSES = 0x0001 +const XTPERF_MASK_D_ACCESS_HITS_SHARED = 0x0002 +const XTPERF_MASK_D_ACCESS_HITS_EXCLUSIVE = 0x0004 +const XTPERF_MASK_D_ACCESS_HITS_MODIFIED = 0x0008 +const XTPERF_MASK_MULTIPLE_LS_ALL = 0x003F +const XTPERF_MASK_MULTIPLE_LS_0S_0L = 0x0001 +const XTPERF_MASK_MULTIPLE_LS_0S_1L = 0x0002 +const XTPERF_MASK_MULTIPLE_LS_1S_0L = 0x0004 +const XTPERF_MASK_MULTIPLE_LS_1S_1L = 0x0008 +const XTPERF_MASK_MULTIPLE_LS_0S_2L = 0x0010 +const XTPERF_MASK_MULTIPLE_LS_2S_0L = 0x0020 +const XTPERF_MASK_OUTBOUND_PIF_ALL = 0x0003 +const XTPERF_MASK_OUTBOUND_PIF_CASTOUT = 0x0001 +const XTPERF_MASK_OUTBOUND_PIF_PREFETCH = 0x0002 +const XTPERF_MASK_INBOUND_PIF_ALL = 0x0003 +const XTPERF_MASK_INBOUND_PIF_I_DMA = 0x0001 +const XTPERF_MASK_INBOUND_PIF_D_DMA = 0x0002 +const XTPERF_MASK_PREFETCH_ALL = 0x002F +const XTPERF_MASK_PREFETCH_I_HIT = 0x0001 +const XTPERF_MASK_PREFETCH_D_HIT = 0x0002 +const XTPERF_MASK_PREFETCH_I_MISS = 0x0004 +const XTPERF_MASK_PREFETCH_D_MISS = 0x0008 +const XTPERF_MASK_PREFETCH_D_L1_FILL = 0x0020 +const XTPERF_MASK_IDMA_ALL = 0x0001 +const XTPERF_MASK_IDMA_ACTIVE_CYCLES = 0x0001 +const XTPERF_MASK_INSN_LENGTH_ALL = 0x7FFF +const XTPERF_MASK_INSN_LENGTH_16 = 0x0001 +const XTPERF_MASK_INSN_LENGTH_24 = 0x0002 +const XTPERF_MASK_INSN_LENGTH_32 = 0x0004 +const XTPERF_MASK_INSN_LENGTH_40 = 0x0008 +const XTPERF_MASK_INSN_LENGTH_48 = 0x0010 +const XTPERF_MASK_INSN_LENGTH_56 = 0x0020 +const XTPERF_MASK_INSN_LENGTH_64 = 0x0040 +const XTPERF_MASK_INSN_LENGTH_72 = 0x0080 +const XTPERF_MASK_INSN_LENGTH_80 = 0x0100 +const XTPERF_MASK_INSN_LENGTH_88 = 0x0200 +const XTPERF_MASK_INSN_LENGTH_96 = 0x0400 +const XTPERF_MASK_INSN_LENGTH_104 = 0x0800 +const XTPERF_MASK_INSN_LENGTH_112 = 0x1000 +const XTPERF_MASK_INSN_LENGTH_120 = 0x2000 +const XTPERF_MASK_INSN_LENGTH_128 = 0x4000 diff --git a/esp32/xt_trax.go b/esp32/xt_trax.go new file mode 100644 index 00000000..a3682ddb --- /dev/null +++ b/esp32/xt_trax.go @@ -0,0 +1,42 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Start a Trax trace on the current CPU with instructions as unit of delay. + * Memory blocks to be used as Trax memory must be enabled before + * calling this function, if needed. + */ +//go:linkname XtTraxStartTraceInstructions C.xt_trax_start_trace_instructions +func XtTraxStartTraceInstructions() + +/** + * @brief Start a Trax trace on the current CPU with words as unit of delay. + * Memory blocks to be used as Trax memory must be enabled before + * calling this function, if needed. + */ +//go:linkname XtTraxStartTraceWords C.xt_trax_start_trace_words +func XtTraxStartTraceWords() + +/** + * @brief Check if Trax trace is active on current CPU. + * + * @return bool. Return true if trace is active. + */ +//go:linkname XtTraxTraceIsActive C.xt_trax_trace_is_active +func XtTraxTraceIsActive() bool + +/** + * @brief Trigger a Trax trace stop after the indicated delay. If this is called + * before and the previous delay hasn't ended yet, this will overwrite + * that delay with the new value. The delay will always start at the time + * the function is called. + * + * @param delay : The delay to stop the trace in, in the unit indicated to + * trax_start_trace. Note: the trace memory has 4K words available. + */ +//go:linkname XtTraxTriggerTraceendAfterDelay C.xt_trax_trigger_traceend_after_delay +func XtTraxTriggerTraceendAfterDelay(delay c.Int) diff --git a/esp32/xt_wdt_hal.go b/esp32/xt_wdt_hal.go new file mode 100644 index 00000000..973bdd56 --- /dev/null +++ b/esp32/xt_wdt_hal.go @@ -0,0 +1,51 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +type XtWdtHalContextT struct { + Dev *RtcCntlDevT +} + +type XtWdtHalConfigT struct { + Timeout c.Uint32T +} + +/** + * @brief Initialize the WDTs associated HAL context + * + * Prepares the register for enabling the WDT and sets the timeout value + * + * @param hal Pointer to the HAL layer context + * @param config Pointer to config struct + */ +// llgo:link (*XtWdtHalContextT).XtWdtHalInit C.xt_wdt_hal_init +func (recv_ *XtWdtHalContextT) XtWdtHalInit(config *XtWdtHalConfigT) { +} + +/** + * @brief Enable or disable the WDT + * + * @param hal Pointer to the HAL layer context + * @param enable true for enable WDT, false for disable + */ +// llgo:link (*XtWdtHalContextT).XtWdtHalEnable C.xt_wdt_hal_enable +func (recv_ *XtWdtHalContextT) XtWdtHalEnable(enable bool) { +} + +/** + * @brief Enable the automatic RTC backup clock with the given frequency + * + * Calculates and sets the necessary hardware parameters to meet the desired + * backup clock frequency + * + * @param hal Pointer to the HAL layer context + * @param rtc_clk_frequency_khz desired frequency for the backup clock + * @return uint32_t the calculated clock factor value + */ +// llgo:link (*XtWdtHalContextT).XtWdtHalEnableBackupClk C.xt_wdt_hal_enable_backup_clk +func (recv_ *XtWdtHalContextT) XtWdtHalEnableBackupClk(rtc_clk_frequency_khz c.Uint32T) c.Uint32T { + return 0 +} diff --git a/esp32/xt_wdt_ll.go b/esp32/xt_wdt_ll.go new file mode 100644 index 00000000..55b5bb8a --- /dev/null +++ b/esp32/xt_wdt_ll.go @@ -0,0 +1,75 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +/** + * @brief Enable the XT_WDT + * + * @param hw Start address of the peripheral registers. + */ +// llgo:link (*RtcCntlDevT).XtWdtLlEnable C.xt_wdt_ll_enable +func (recv_ *RtcCntlDevT) XtWdtLlEnable(enable bool) { +} + +/** + * @brief Check if the XT_WDT is enabled + * + * @param hw Start address of the peripheral registers. + * @return True if XT WDT is enabled + */ +// llgo:link (*RtcCntlDevT).XtWdtLlCheckIfEnabled C.xt_wdt_ll_check_if_enabled +func (recv_ *RtcCntlDevT) XtWdtLlCheckIfEnabled() bool { + return false +} + +/** + * @brief Set the watchdog timeout value + * + * @param hw Start address of the peripheral registers. + * @param timeout timeout value in RTC_CLK cycles + */ +// llgo:link (*RtcCntlDevT).XtWdtLlSetTimeout C.xt_wdt_ll_set_timeout +func (recv_ *RtcCntlDevT) XtWdtLlSetTimeout(timeout c.Uint8T) { +} + +/** + * @brief Reset the XT_WDT + * + * @param hw Start address of the peripheral registers. + */ +// llgo:link (*RtcCntlDevT).XtWdtLlReset C.xt_wdt_ll_reset +func (recv_ *RtcCntlDevT) XtWdtLlReset() { +} + +/** + * @brief Set the backup clock value + * + * @param hw Start address of the peripheral registers. + * @param backup_clk_val Backup clock value, see TRM for definition + */ +// llgo:link (*RtcCntlDevT).XtWdtLlSetBackupClkFactor C.xt_wdt_ll_set_backup_clk_factor +func (recv_ *RtcCntlDevT) XtWdtLlSetBackupClkFactor(backup_clk_val c.Uint32T) { +} + +/** + * @brief Enable the auto-backup clock feature + * + * @param hw Start address of the peripheral registers. + * @param enable True - enable, False - disable + */ +// llgo:link (*RtcCntlDevT).XtWdtLlAutoBackupEnable C.xt_wdt_ll_auto_backup_enable +func (recv_ *RtcCntlDevT) XtWdtLlAutoBackupEnable(enable bool) { +} + +/** + * @brief Enable the timeout interrupt + * + * @param hw Start address of the peripheral registers. + * @param enable True - enable, False - disable + */ +// llgo:link (*RtcCntlDevT).XtWdtLlIntrEnable C.xt_wdt_ll_intr_enable +func (recv_ *RtcCntlDevT) XtWdtLlIntrEnable(enable bool) { +} diff --git a/esp32/xtensa-debug-module.go b/esp32/xtensa-debug-module.go new file mode 100644 index 00000000..e4e602d5 --- /dev/null +++ b/esp32/xtensa-debug-module.go @@ -0,0 +1,24 @@ +package freertos + +import _ "unsafe" + +const ERI_DEBUG_OFFSET = 0x100000 +const TRAXCTRL_SMPER_SHIFT = 12 +const TRAXCTRL_SMPER_MASK = 0x7 +const TRAXCTRL_ATID_MASK = 0x7F +const TRAXCTRL_ATID_SHIFT = 24 +const TRAXSTAT_MEMSZ_SHIFT = 8 +const TRAXSTAT_MEMSZ_MASK = 0x1F +const TRAXADDR_TADDR_SHIFT = 0 +const TRAXADDR_TADDR_MASK = 0x1FFFFF +const TRAXADDR_TWRAP_SHIFT = 21 +const TRAXADDR_TWRAP_MASK = 0x3FF +const PCMATCHCTRL_PCML_SHIFT = 0 +const PCMATCHCTRL_PCML_MASK = 0x1F +const PMCTRL_KRNLCNT_SHIFT = 3 +const PMCTRL_TRACELEVEL_SHIFT = 4 +const PMCTRL_TRACELEVEL_MASK = 0xf +const PMCTRL_SELECT_SHIFT = 8 +const PMCTRL_SELECT_MASK = 0x1f +const PMCTRL_MASK_SHIFT = 16 +const PMCTRL_MASK_MASK = 0xffff diff --git a/esp32/xtensa-libdb-macros.go b/esp32/xtensa-libdb-macros.go new file mode 100644 index 00000000..5893dcbd --- /dev/null +++ b/esp32/xtensa-libdb-macros.go @@ -0,0 +1,7 @@ +package freertos + +import _ "unsafe" + +const XTENSA_DBREGN_PC = 0x0020 +const XTENSA_DBREGN_MASK = 0xFFFF +const XTENSA_DBREGN_WRITE_SIDE = 0x04000000 diff --git a/esp32/xtensa-versions.go b/esp32/xtensa-versions.go new file mode 100644 index 00000000..3fc1a6fb --- /dev/null +++ b/esp32/xtensa-versions.go @@ -0,0 +1,292 @@ +package freertos + +import _ "unsafe" + +const XTENSA_HWVERSION_T1020_0 = 102000 +const XTENSA_HWCIDSCHEME_T1020_0 = 10 +const XTENSA_HWCIDVERS_T1020_0 = 2 +const XTENSA_HWVERSION_T1020_1 = 102001 +const XTENSA_HWCIDSCHEME_T1020_1 = 10 +const XTENSA_HWCIDVERS_T1020_1 = 3 +const XTENSA_HWVERSION_T1020_2 = 102002 +const XTENSA_HWCIDSCHEME_T1020_2 = 10 +const XTENSA_HWCIDVERS_T1020_2 = 4 +const XTENSA_HWVERSION_T1020_2B = 102002 +const XTENSA_HWCIDSCHEME_T1020_2B = 10 +const XTENSA_HWCIDVERS_T1020_2B = 5 +const XTENSA_HWVERSION_T1020_3 = 102003 +const XTENSA_HWCIDSCHEME_T1020_3 = 10 +const XTENSA_HWCIDVERS_T1020_3 = 6 +const XTENSA_HWVERSION_T1020_4 = 102004 +const XTENSA_HWCIDSCHEME_T1020_4 = 10 +const XTENSA_HWCIDVERS_T1020_4 = 7 +const XTENSA_HWVERSION_T1030_0 = 103000 +const XTENSA_HWCIDSCHEME_T1030_0 = 10 +const XTENSA_HWCIDVERS_T1030_0 = 9 +const XTENSA_HWVERSION_T1030_1 = 103001 +const XTENSA_HWCIDSCHEME_T1030_1 = 10 +const XTENSA_HWCIDVERS_T1030_1 = 10 +const XTENSA_HWVERSION_T1030_2 = 103002 +const XTENSA_HWCIDSCHEME_T1030_2 = 10 +const XTENSA_HWCIDVERS_T1030_2 = 11 +const XTENSA_HWVERSION_T1030_3 = 103003 +const XTENSA_HWCIDSCHEME_T1030_3 = 10 +const XTENSA_HWCIDVERS_T1030_3 = 12 +const XTENSA_HWVERSION_T1040_0 = 104000 +const XTENSA_HWCIDSCHEME_T1040_0 = 10 +const XTENSA_HWCIDVERS_T1040_0 = 15 +const XTENSA_HWVERSION_T1040_1 = 104001 +const XTENSA_HWCIDSCHEME_T1040_1 = 1 +const XTENSA_HWCIDVERS_T1040_1 = 32 +const XTENSA_HWVERSION_T1040_1P = 104001 +const XTENSA_HWCIDSCHEME_T1040_1P = 10 +const XTENSA_HWCIDVERS_T1040_1P = 16 +const XTENSA_HWVERSION_T1040_2 = 104002 +const XTENSA_HWCIDSCHEME_T1040_2 = 1 +const XTENSA_HWCIDVERS_T1040_2 = 33 +const XTENSA_HWVERSION_T1040_3 = 104003 +const XTENSA_HWCIDSCHEME_T1040_3 = 1 +const XTENSA_HWCIDVERS_T1040_3 = 34 +const XTENSA_HWVERSION_T1050_0 = 105000 +const XTENSA_HWCIDSCHEME_T1050_0 = 1100 +const XTENSA_HWCIDVERS_T1050_0 = 1 +const XTENSA_HWVERSION_T1050_1 = 105001 +const XTENSA_HWCIDSCHEME_T1050_1 = 1100 +const XTENSA_HWCIDVERS_T1050_1 = 2 +const XTENSA_HWVERSION_T1050_2 = 105002 +const XTENSA_HWCIDSCHEME_T1050_2 = 1100 +const XTENSA_HWCIDVERS_T1050_2 = 4 +const XTENSA_HWVERSION_T1050_3 = 105003 +const XTENSA_HWCIDSCHEME_T1050_3 = 1100 +const XTENSA_HWCIDVERS_T1050_3 = 6 +const XTENSA_HWVERSION_T1050_4 = 105004 +const XTENSA_HWCIDSCHEME_T1050_4 = 1100 +const XTENSA_HWCIDVERS_T1050_4 = 7 +const XTENSA_HWVERSION_T1050_5 = 105005 +const XTENSA_HWCIDSCHEME_T1050_5 = 1100 +const XTENSA_HWCIDVERS_T1050_5 = 8 +const XTENSA_HWVERSION_RA_2004_1 = 210000 +const XTENSA_HWCIDSCHEME_RA_2004_1 = 1100 +const XTENSA_HWCIDVERS_RA_2004_1 = 3 +const XTENSA_HWVERSION_RA_2005_1 = 210001 +const XTENSA_HWCIDSCHEME_RA_2005_1 = 1100 +const XTENSA_HWCIDVERS_RA_2005_1 = 20 +const XTENSA_HWVERSION_RA_2005_2 = 210002 +const XTENSA_HWCIDSCHEME_RA_2005_2 = 1100 +const XTENSA_HWCIDVERS_RA_2005_2 = 21 +const XTENSA_HWVERSION_RA_2005_3 = 210003 +const XTENSA_HWCIDSCHEME_RA_2005_3 = 1100 +const XTENSA_HWCIDVERS_RA_2005_3 = 22 +const XTENSA_HWVERSION_RA_2006_4 = 210004 +const XTENSA_HWCIDSCHEME_RA_2006_4 = 1100 +const XTENSA_HWCIDVERS_RA_2006_4 = 23 +const XTENSA_HWVERSION_RA_2006_5 = 210005 +const XTENSA_HWCIDSCHEME_RA_2006_5 = 1100 +const XTENSA_HWCIDVERS_RA_2006_5 = 24 +const XTENSA_HWVERSION_RA_2006_6 = 210006 +const XTENSA_HWCIDSCHEME_RA_2006_6 = 1100 +const XTENSA_HWCIDVERS_RA_2006_6 = 25 +const XTENSA_HWVERSION_RA_2007_7 = 210007 +const XTENSA_HWCIDSCHEME_RA_2007_7 = 1100 +const XTENSA_HWCIDVERS_RA_2007_7 = 26 +const XTENSA_HWVERSION_RA_2008_8 = 210008 +const XTENSA_HWCIDSCHEME_RA_2008_8 = 1100 +const XTENSA_HWCIDVERS_RA_2008_8 = 27 +const XTENSA_HWVERSION_RB_2006_0 = 220000 +const XTENSA_HWCIDSCHEME_RB_2006_0 = 1100 +const XTENSA_HWCIDVERS_RB_2006_0 = 48 +const XTENSA_HWVERSION_RB_2007_1 = 220001 +const XTENSA_HWCIDSCHEME_RB_2007_1 = 1100 +const XTENSA_HWCIDVERS_RB_2007_1 = 49 +const XTENSA_HWVERSION_RB_2007_2 = 221000 +const XTENSA_HWCIDSCHEME_RB_2007_2 = 1100 +const XTENSA_HWCIDVERS_RB_2007_2 = 52 +const XTENSA_HWVERSION_RB_2008_3 = 221001 +const XTENSA_HWCIDSCHEME_RB_2008_3 = 1100 +const XTENSA_HWCIDVERS_RB_2008_3 = 53 +const XTENSA_HWVERSION_RB_2008_4 = 221002 +const XTENSA_HWCIDSCHEME_RB_2008_4 = 1100 +const XTENSA_HWCIDVERS_RB_2008_4 = 54 +const XTENSA_HWVERSION_RB_2009_5 = 221003 +const XTENSA_HWCIDSCHEME_RB_2009_5 = 1100 +const XTENSA_HWCIDVERS_RB_2009_5 = 55 +const XTENSA_HWVERSION_RB_2007_2_MP = 221100 +const XTENSA_HWCIDSCHEME_RB_2007_2_MP = 1100 +const XTENSA_HWCIDVERS_RB_2007_2_MP = 64 +const XTENSA_HWVERSION_RC_2009_0 = 230000 +const XTENSA_HWCIDSCHEME_RC_2009_0 = 1100 +const XTENSA_HWCIDVERS_RC_2009_0 = 65 +const XTENSA_HWVERSION_RC_2010_1 = 230001 +const XTENSA_HWCIDSCHEME_RC_2010_1 = 1100 +const XTENSA_HWCIDVERS_RC_2010_1 = 66 +const XTENSA_HWVERSION_RC_2010_2 = 230002 +const XTENSA_HWCIDSCHEME_RC_2010_2 = 1100 +const XTENSA_HWCIDVERS_RC_2010_2 = 67 +const XTENSA_HWVERSION_RC_2011_3 = 230003 +const XTENSA_HWCIDSCHEME_RC_2011_3 = 1100 +const XTENSA_HWCIDVERS_RC_2011_3 = 68 +const XTENSA_HWVERSION_RD_2010_0 = 240000 +const XTENSA_HWCIDSCHEME_RD_2010_0 = 1100 +const XTENSA_HWCIDVERS_RD_2010_0 = 80 +const XTENSA_HWVERSION_RD_2011_1 = 240001 +const XTENSA_HWCIDSCHEME_RD_2011_1 = 1100 +const XTENSA_HWCIDVERS_RD_2011_1 = 81 +const XTENSA_HWVERSION_RD_2011_2 = 240002 +const XTENSA_HWCIDSCHEME_RD_2011_2 = 1100 +const XTENSA_HWCIDVERS_RD_2011_2 = 82 +const XTENSA_HWVERSION_RD_2011_3 = 240003 +const XTENSA_HWCIDSCHEME_RD_2011_3 = 1100 +const XTENSA_HWCIDVERS_RD_2011_3 = 83 +const XTENSA_HWVERSION_RD_2012_4 = 240004 +const XTENSA_HWCIDSCHEME_RD_2012_4 = 1100 +const XTENSA_HWCIDVERS_RD_2012_4 = 84 +const XTENSA_HWVERSION_RD_2012_5 = 240005 +const XTENSA_HWCIDSCHEME_RD_2012_5 = 1100 +const XTENSA_HWCIDVERS_RD_2012_5 = 85 +const XTENSA_HWVERSION_RE_2012_0 = 250000 +const XTENSA_HWCIDSCHEME_RE_2012_0 = 1100 +const XTENSA_HWCIDVERS_RE_2012_0 = 96 +const XTENSA_HWVERSION_RE_2012_1 = 250001 +const XTENSA_HWCIDSCHEME_RE_2012_1 = 1100 +const XTENSA_HWCIDVERS_RE_2012_1 = 97 +const XTENSA_HWVERSION_RE_2013_2 = 250002 +const XTENSA_HWCIDSCHEME_RE_2013_2 = 1100 +const XTENSA_HWCIDVERS_RE_2013_2 = 98 +const XTENSA_HWVERSION_RE_2013_3 = 250003 +const XTENSA_HWCIDSCHEME_RE_2013_3 = 1100 +const XTENSA_HWCIDVERS_RE_2013_3 = 99 +const XTENSA_HWVERSION_RE_2013_4 = 250004 +const XTENSA_HWCIDSCHEME_RE_2013_4 = 1100 +const XTENSA_HWCIDVERS_RE_2013_4 = 100 +const XTENSA_HWVERSION_RE_2014_5 = 250005 +const XTENSA_HWCIDSCHEME_RE_2014_5 = 1100 +const XTENSA_HWCIDVERS_RE_2014_5 = 101 +const XTENSA_HWVERSION_RE_2015_6 = 250006 +const XTENSA_HWCIDSCHEME_RE_2015_6 = 1100 +const XTENSA_HWCIDVERS_RE_2015_6 = 102 +const XTENSA_HWVERSION_RF_2014_0 = 260000 +const XTENSA_HWCIDSCHEME_RF_2014_0 = 1100 +const XTENSA_HWCIDVERS_RF_2014_0 = 112 +const XTENSA_HWVERSION_RF_2014_1 = 260001 +const XTENSA_HWCIDSCHEME_RF_2014_1 = 1100 +const XTENSA_HWCIDVERS_RF_2014_1 = 113 +const XTENSA_HWVERSION_RF_2015_2 = 260002 +const XTENSA_HWCIDSCHEME_RF_2015_2 = 1100 +const XTENSA_HWCIDVERS_RF_2015_2 = 114 +const XTENSA_HWVERSION_RF_2015_3 = 260003 +const XTENSA_HWCIDSCHEME_RF_2015_3 = 1100 +const XTENSA_HWCIDVERS_RF_2015_3 = 115 +const XTENSA_HWVERSION_RF_2016_4 = 260004 +const XTENSA_HWCIDSCHEME_RF_2016_4 = 1100 +const XTENSA_HWCIDVERS_RF_2016_4 = 116 +const XTENSA_HWVERSION_RG_2015_0 = 270000 +const XTENSA_HWCIDSCHEME_RG_2015_0 = 1100 +const XTENSA_HWCIDVERS_RG_2015_0 = 128 +const XTENSA_HWVERSION_RG_2015_1 = 270001 +const XTENSA_HWCIDSCHEME_RG_2015_1 = 1100 +const XTENSA_HWCIDVERS_RG_2015_1 = 129 +const XTENSA_HWVERSION_RG_2015_2 = 270002 +const XTENSA_HWCIDSCHEME_RG_2015_2 = 1100 +const XTENSA_HWCIDVERS_RG_2015_2 = 130 +const XTENSA_HWVERSION_RG_2016_3 = 270003 +const XTENSA_HWCIDSCHEME_RG_2016_3 = 1100 +const XTENSA_HWCIDVERS_RG_2016_3 = 131 +const XTENSA_HWVERSION_RG_2016_4 = 270004 +const XTENSA_HWCIDSCHEME_RG_2016_4 = 1100 +const XTENSA_HWCIDVERS_RG_2016_4 = 132 +const XTENSA_HWVERSION_RG_2017_5 = 270005 +const XTENSA_HWCIDSCHEME_RG_2017_5 = 1100 +const XTENSA_HWCIDVERS_RG_2017_5 = 133 +const XTENSA_HWVERSION_RG_2017_6 = 270006 +const XTENSA_HWCIDSCHEME_RG_2017_6 = 1100 +const XTENSA_HWCIDVERS_RG_2017_6 = 134 +const XTENSA_HWVERSION_RG_2017_7 = 270007 +const XTENSA_HWCIDSCHEME_RG_2017_7 = 1100 +const XTENSA_HWCIDVERS_RG_2017_7 = 135 +const XTENSA_HWVERSION_RG_2017_8 = 270008 +const XTENSA_HWCIDSCHEME_RG_2017_8 = 1100 +const XTENSA_HWCIDVERS_RG_2017_8 = 136 +const XTENSA_HWVERSION_RG_2018_9 = 270009 +const XTENSA_HWCIDSCHEME_RG_2018_9 = 1100 +const XTENSA_HWCIDVERS_RG_2018_9 = 137 +const XTENSA_HWVERSION_RH_2016_0 = 280000 +const XTENSA_HWCIDSCHEME_RH_2016_0 = 1100 +const XTENSA_HWCIDVERS_RH_2016_0 = 144 +const XTENSA_SWVERSION_T1020_0 = 102000 +const XTENSA_SWVERSION_T1020_1 = 102001 +const XTENSA_SWVERSION_T1020_2 = 102002 +const XTENSA_SWVERSION_T1020_2B = 102002 +const XTENSA_SWVERSION_T1020_3 = 102003 +const XTENSA_SWVERSION_T1020_4 = 102004 +const XTENSA_SWVERSION_T1030_0 = 103000 +const XTENSA_SWVERSION_T1030_1 = 103001 +const XTENSA_SWVERSION_T1030_2 = 103002 +const XTENSA_SWVERSION_T1030_3 = 103003 +const XTENSA_SWVERSION_T1040_0 = 104000 +const XTENSA_SWVERSION_T1040_1 = 104001 +const XTENSA_SWVERSION_T1040_1P = 104001 +const XTENSA_SWVERSION_T1040_2 = 104002 +const XTENSA_SWVERSION_T1040_3 = 104003 +const XTENSA_SWVERSION_T1050_0 = 105000 +const XTENSA_SWVERSION_T1050_1 = 105001 +const XTENSA_SWVERSION_T1050_2 = 105002 +const XTENSA_SWVERSION_T1050_3 = 105003 +const XTENSA_SWVERSION_T1050_4 = 105004 +const XTENSA_SWVERSION_T1050_5 = 105005 +const XTENSA_SWVERSION_RA_2004_1 = 600000 +const XTENSA_SWVERSION_RA_2005_1 = 600001 +const XTENSA_SWVERSION_RA_2005_2 = 600002 +const XTENSA_SWVERSION_RA_2005_3 = 600003 +const XTENSA_SWVERSION_RA_2006_4 = 600004 +const XTENSA_SWVERSION_RA_2006_5 = 600005 +const XTENSA_SWVERSION_RA_2006_6 = 600006 +const XTENSA_SWVERSION_RA_2007_7 = 600007 +const XTENSA_SWVERSION_RA_2008_8 = 600008 +const XTENSA_SWVERSION_RB_2006_0 = 700000 +const XTENSA_SWVERSION_RB_2007_1 = 700001 +const XTENSA_SWVERSION_RB_2007_2 = 701000 +const XTENSA_SWVERSION_RB_2008_3 = 701001 +const XTENSA_SWVERSION_RB_2008_4 = 701002 +const XTENSA_SWVERSION_RB_2009_5 = 701003 +const XTENSA_SWVERSION_RB_2007_2_MP = 701100 +const XTENSA_SWVERSION_RC_2009_0 = 800000 +const XTENSA_SWVERSION_RC_2010_1 = 800001 +const XTENSA_SWVERSION_RC_2010_2 = 800002 +const XTENSA_SWVERSION_RC_2011_3 = 800003 +const XTENSA_SWVERSION_RD_2010_0 = 900000 +const XTENSA_SWVERSION_RD_2011_1 = 900001 +const XTENSA_SWVERSION_RD_2011_2 = 900002 +const XTENSA_SWVERSION_RD_2011_3 = 900003 +const XTENSA_SWVERSION_RD_2012_4 = 900004 +const XTENSA_SWVERSION_RD_2012_5 = 900005 +const XTENSA_SWVERSION_RE_2012_0 = 1000000 +const XTENSA_SWVERSION_RE_2012_1 = 1000001 +const XTENSA_SWVERSION_RE_2013_2 = 1000002 +const XTENSA_SWVERSION_RE_2013_3 = 1000003 +const XTENSA_SWVERSION_RE_2013_4 = 1000004 +const XTENSA_SWVERSION_RE_2014_5 = 1000005 +const XTENSA_SWVERSION_RE_2015_6 = 1000006 +const XTENSA_SWVERSION_RF_2014_0 = 1100000 +const XTENSA_SWVERSION_RF_2014_1 = 1100001 +const XTENSA_SWVERSION_RF_2015_2 = 1100002 +const XTENSA_SWVERSION_RF_2015_3 = 1100003 +const XTENSA_SWVERSION_RF_2016_4 = 1100004 +const XTENSA_SWVERSION_RG_2015_0 = 1200000 +const XTENSA_SWVERSION_RG_2015_1 = 1200001 +const XTENSA_SWVERSION_RG_2015_2 = 1200002 +const XTENSA_SWVERSION_RG_2016_3 = 1200003 +const XTENSA_SWVERSION_RG_2016_4 = 1200004 +const XTENSA_SWVERSION_RG_2017_5 = 1200005 +const XTENSA_SWVERSION_RG_2017_6 = 1200006 +const XTENSA_SWVERSION_RG_2017_7 = 1200007 +const XTENSA_SWVERSION_RG_2017_8 = 1200008 +const XTENSA_SWVERSION_RG_2018_9 = 1200009 +const XTENSA_SWVERSION_RH_2016_0 = 1300000 +const XTENSA_RELEASE_NAME = "RG-2018.9" +const XTENSA_RELEASE_CANONICAL_NAME = "RG-2018.9" +const XTENSA_SWVERSION_NAME = "12.0.9" +const XTENSA_SWVERSION_NAME_IDENT = 12_0_9 +const XTENSA_SWVERSION_CANONICAL_NAME = "12.0.9" +const XTENSA_SWVERSION_MAJORMID_NAME = "12.0" +const XTENSA_SWVERSION_MAJOR_NAME = "12" +const XTENSA_SWVERSION_LICENSE_NAME = "12.0" diff --git a/esp32/xtensa-xer.go b/esp32/xtensa-xer.go new file mode 100644 index 00000000..31e6cf2a --- /dev/null +++ b/esp32/xtensa-xer.go @@ -0,0 +1,30 @@ +package freertos + +import _ "unsafe" + +const NUM_INTERRUPTS = 27 +const NUM_CORES = 4 +const XER_MIROUT = 0x0000 +const XER_MIPICAUSE = 0x0100 +const XER_MIPICAUSE_FIELD_A_FIRST = 0x0 +const XER_MIPICAUSE_FIELD_A_LAST = 0x0 +const XER_MIPICAUSE_FIELD_B_FIRST = 0x1 +const XER_MIPICAUSE_FIELD_B_LAST = 0x3 +const XER_MIPICAUSE_FIELD_C_FIRST = 0x4 +const XER_MIPICAUSE_FIELD_C_LAST = 0x7 +const XER_MIPICAUSE_FIELD_D_FIRST = 0x8 +const XER_MIPICAUSE_FIELD_D_LAST = 0xF +const XER_MIPISET = 0x0140 +const XER_MIPISET_LAST = 0x014F +const XER_MIENG = 0x0180 +const XER_MIENG_SET = 0x0184 +const XER_MIASG = 0x0188 +const XER_MIASG_SET = 0x018C +const XER_PART = 0x0190 +const XER_IPI0 = 0x0 +const XER_IPI1 = 0x1 +const XER_IPI2 = 0x2 +const XER_IPI3 = 0x3 +const XER_SYSCFGID = 0x01A0 +const XER_MPSCORE = 0x0200 +const XER_CCON = 0x0220 diff --git a/esp32/xtensa_api.go b/esp32/xtensa_api.go new file mode 100644 index 00000000..3d5c984a --- /dev/null +++ b/esp32/xtensa_api.go @@ -0,0 +1,85 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +// llgo:type C +type XtExcHandler func(*XtExcFrame) + +/* +------------------------------------------------------------------------------- + Call this function to set a handler for the specified exception. The handler + will be installed on the core that calls this function. + + n - Exception number (type) + f - Handler function address, NULL to uninstall handler. + + The handler will be passed a pointer to the exception frame, which is created + on the stack of the thread that caused the exception. + + If the handler returns, the thread context will be restored and the faulting + instruction will be retried. Any values in the exception frame that are + modified by the handler will be restored as part of the context. For details + of the exception frame structure see xtensa_context.h. +------------------------------------------------------------------------------- +*/ +//go:linkname XtSetExceptionHandler C.xt_set_exception_handler +func XtSetExceptionHandler(n c.Int, f XtExcHandler) XtExcHandler + +/* +------------------------------------------------------------------------------- + Call this function to set a handler for the specified interrupt. The handler + will be installed on the core that calls this function. + + n - Interrupt number. + f - Handler function address, NULL to uninstall handler. + arg - Argument to be passed to handler. +------------------------------------------------------------------------------- +*/ +//go:linkname XtSetInterruptHandler C.xt_set_interrupt_handler +func XtSetInterruptHandler(n c.Int, f c.Int, arg c.Pointer) c.Int + +/* +------------------------------------------------------------------------------- + Call this function to enable the specified interrupts on the core that runs + this code. + + mask - Bit mask of interrupts to be enabled. +------------------------------------------------------------------------------- +*/ +//go:linkname XtIntsOn C.xt_ints_on +func XtIntsOn(mask c.Uint) + +/* +------------------------------------------------------------------------------- + Call this function to disable the specified interrupts on the core that runs + this code. + + mask - Bit mask of interrupts to be disabled. +------------------------------------------------------------------------------- +*/ +//go:linkname XtIntsOff C.xt_ints_off +func XtIntsOff(mask c.Uint) + +/* +------------------------------------------------------------------------------- + Call this function to get handler's argument for the specified interrupt. + + n - Interrupt number. +------------------------------------------------------------------------------- +*/ +//go:linkname XtGetInterruptHandlerArg C.xt_get_interrupt_handler_arg +func XtGetInterruptHandlerArg(n c.Int) c.Pointer + +/* +------------------------------------------------------------------------------- + Call this function to check if the specified interrupt is free to use. + + intr - Interrupt number. + cpu - cpu number. +------------------------------------------------------------------------------- +*/ +//go:linkname XtIntHasHandler C.xt_int_has_handler +func XtIntHasHandler(intr c.Int, cpu c.Int) bool diff --git a/esp32/xtensa_config.go b/esp32/xtensa_config.go new file mode 100644 index 00000000..07288e69 --- /dev/null +++ b/esp32/xtensa_config.go @@ -0,0 +1,8 @@ +package freertos + +import _ "unsafe" + +const STK_INTEXC_EXTRA = 0 +const XT_USE_THREAD_SAFE_CLIB = 1 +const XT_HAVE_THREAD_SAFE_CLIB = 1 +const XT_USER_SIZE = 0x400 diff --git a/esp32/xtensa_context.go b/esp32/xtensa_context.go new file mode 100644 index 00000000..8c3c9999 --- /dev/null +++ b/esp32/xtensa_context.go @@ -0,0 +1,108 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const XT_CP0_SA = 0 +const XT_CPENABLE = 0 +const XT_CPSTORED = 2 +const XT_CP_CS_ST = 4 +const XT_CP_ASA = 8 +const CORE_ID_REGVAL_PRO = 0xCDCD +const CORE_ID_REGVAL_APP = 0xABAB + +/* +------------------------------------------------------------------------------- + + INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT + + A stack frame of this structure is allocated for any interrupt or exception. + It goes on the current stack. If the RTOS has a system stack for handling + interrupts, every thread stack must allow space for just one interrupt stack + frame, then nested interrupt stack frames go on the system stack. + + The frame includes basic registers (explicit) and "extra" registers introduced + by user TIE or the use of the MAC16 option in the user's Xtensa config. + The frame size is minimized by omitting regs not applicable to user's config. + + For Windowed ABI, this stack frame includes the interruptee's base save area, + another base save area to manage gcc nested functions, and a little temporary + space to help manage the spilling of the register windows. + +------------------------------------------------------------------------------- +*/ +type XtExcFrame struct { + Exit c.Long + Pc c.Long + Ps c.Long + A0 c.Long + A1 c.Long + A2 c.Long + A3 c.Long + A4 c.Long + A5 c.Long + A6 c.Long + A7 c.Long + A8 c.Long + A9 c.Long + A10 c.Long + A11 c.Long + A12 c.Long + A13 c.Long + A14 c.Long + A15 c.Long + Sar c.Long + Exccause c.Long + Excvaddr c.Long + Lbeg c.Long + Lend c.Long + Lcount c.Long + Tmp0 c.Long + Tmp1 c.Long + Tmp2 c.Long +} + +/* +------------------------------------------------------------------------------- + + SOLICITED STACK FRAME FOR A THREAD + + A stack frame of this structure is allocated whenever a thread enters the + RTOS kernel intentionally (and synchronously) to submit to thread scheduling. + It goes on the current thread's stack. + + The solicited frame only includes registers that are required to be preserved + by the callee according to the compiler's ABI conventions, some space to save + the return address for returning to the caller, and the caller's PS register. + + Note: Although the xtensa ABI considers the threadptr as "global" across + functions (meanig it is neither caller or callee saved), it is treated as a + callee-saved register in a solicited stack frame. This omits the need for the + OS to include extra logic to save "global" registers on each context switch. + Only the threadptr register is treated as callee-saved, as all other NCP + (non-coprocessor extra) registers are caller-saved. See "tie.h" for more + details. + + For Windowed ABI, this stack frame includes the caller's base save area. + + Note on XT_SOL_EXIT field: + It is necessary to distinguish a solicited from an interrupt stack frame. + This field corresponds to XT_STK_EXIT in the interrupt stack frame and is + always at the same offset (0). It can be written with a code (usually 0) + to distinguish a solicted frame from an interrupt frame. An RTOS port may + opt to ignore this field if it has another way of distinguishing frames. + +------------------------------------------------------------------------------- +*/ +type XtSolFrame struct { + Exit c.Long + Pc c.Long + Ps c.Long + Threadptr c.Long + A0 c.Long + A1 c.Long + A2 c.Long + A3 c.Long +} diff --git a/esp32/xtensa_rtos.go b/esp32/xtensa_rtos.go new file mode 100644 index 00000000..90e56698 --- /dev/null +++ b/esp32/xtensa_rtos.go @@ -0,0 +1,13 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const XT_BOARD = 1 +const XTENSA_PORT_VERSION = 1.7 +const XTENSA_PORT_VERSION_STRING = "1.7" + +// llgo:type C +type XTINTEXCHOOK func(c.Uint) c.Uint diff --git a/esp32/xtensa_timer.go b/esp32/xtensa_timer.go new file mode 100644 index 00000000..78907d5c --- /dev/null +++ b/esp32/xtensa_timer.go @@ -0,0 +1,8 @@ +package freertos + +import _ "unsafe" + +const XT_TIMER_INDEX = 1 + +//go:linkname X_xtTickDivisorInit C._xt_tick_divisor_init +func X_xtTickDivisorInit() diff --git a/esp32/xtruntime-core-state.go b/esp32/xtruntime-core-state.go new file mode 100644 index 00000000..ac49ce4a --- /dev/null +++ b/esp32/xtruntime-core-state.go @@ -0,0 +1,54 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const CORE_STATE_SIGNATURE = 0xB1C5AFED + +/* + * Save area for saving entire core state, such as across Power Shut-Off (PSO). + */ + +type XtosCoreState struct { + Signature c.Long + RestoreLabel c.Long + AftersaveLabel c.Long + Areg [64]c.Long + CallerRegs [16]c.Long + CallerRegsSaved c.Long + Windowbase c.Long + Windowstart c.Long + Sar c.Long + Epc1 c.Long + Ps c.Long + Excsave1 c.Long + Depc c.Long + Epc [6]c.Long + Eps [6]c.Long + Excsave [6]c.Long + Lcount c.Long + Lbeg c.Long + Lend c.Long + Vecbase c.Long + Atomctl c.Long + Memctl c.Long + Ccount c.Long + Ccompare [3]c.Long + Intenable c.Long + Interrupt c.Long + Icount c.Long + Icountlevel c.Long + Debugcause c.Long + Dbreakc [2]c.Long + Dbreaka [2]c.Long + Ibreaka [2]c.Long + Ibreakenable c.Long + Misc [4]c.Long + Cpenable c.Long + Tlbs [16]c.Long + Ncp [36]c.Char + Cp0 [72]c.Char + Cp3 [208]c.Char +} diff --git a/esp32/xtruntime-frames.go b/esp32/xtruntime-frames.go new file mode 100644 index 00000000..023b332f --- /dev/null +++ b/esp32/xtruntime-frames.go @@ -0,0 +1,57 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const CALL0_ABI = 0 +const KERNELSTACKSIZE = 1024 + +/* + * Kernel vector mode exception stack frame. + * + * NOTE: due to the limited range of addi used in the current + * kernel exception vector, and the fact that historically + * the vector is limited to 12 bytes, the size of this + * stack frame is limited to 128 bytes (currently at 64). + */ + +type KernelFrame struct { + Pc c.Long + Ps c.Long + Areg [4]c.Long + Sar c.Long + Lcount c.Long + Lbeg c.Long + Lend c.Long + Acclo c.Long + Acchi c.Long + Mr [4]c.Long +} + +/* + * User vector mode exception stack frame: + * + * WARNING: if you modify this structure, you MUST modify the + * computation of the pad size (ALIGNPAD) accordingly. + */ + +type UserFrame struct { + Pc c.Long + Ps c.Long + Sar c.Long + Vpri c.Long + A2 c.Long + A3 c.Long + A4 c.Long + A5 c.Long + Exccause c.Long + Lcount c.Long + Lbeg c.Long + Lend c.Long + Acclo c.Long + Acchi c.Long + Mr [4]c.Long + Pad [2]c.Long +} diff --git a/esp32/xtruntime.go b/esp32/xtruntime.go new file mode 100644 index 00000000..006574ec --- /dev/null +++ b/esp32/xtruntime.go @@ -0,0 +1,99 @@ +package freertos + +import ( + "github.com/goplus/lib/c" + _ "unsafe" +) + +const XTOS_KEEPON_MEM = 0x00000100 +const XTOS_KEEPON_MEM_SHIFT = 8 +const XTOS_KEEPON_DEBUG = 0x00001000 +const XTOS_KEEPON_DEBUG_SHIFT = 12 +const XTOS_IDMA_NO_WAIT = 0x00010000 +const XTOS_IDMA_WAIT_STANDBY = 0x00020000 +const XTOS_COREF_PSO = 0x00000001 +const XTOS_COREF_PSO_SHIFT = 0 + +// llgo:type C +type X_xtosHandlerFunc func() +type X_xtosHandler *X_xtosHandlerFunc + +/* These two are deprecated. Use the newer functions below. */ +//go:linkname X_xtosIntsOff C._xtos_ints_off +func X_xtosIntsOff(mask c.Uint) c.Uint + +//go:linkname X_xtosIntsOn C._xtos_ints_on +func X_xtosIntsOn(mask c.Uint) c.Uint + +//go:linkname X_xtosSetIntlevel C._xtos_set_intlevel +func X_xtosSetIntlevel(intlevel c.Int) c.Uint + +//go:linkname X_xtosSetMinIntlevel C._xtos_set_min_intlevel +func X_xtosSetMinIntlevel(intlevel c.Int) c.Uint + +//go:linkname X_xtosRestoreIntlevel C._xtos_restore_intlevel +func X_xtosRestoreIntlevel(restoreval c.Uint) c.Uint + +//go:linkname X_xtosRestoreJustIntlevel C._xtos_restore_just_intlevel +func X_xtosRestoreJustIntlevel(restoreval c.Uint) c.Uint + +//go:linkname X_xtosSetInterruptHandler C._xtos_set_interrupt_handler +func X_xtosSetInterruptHandler(n c.Int, f X_xtosHandler) X_xtosHandler + +//go:linkname X_xtosSetInterruptHandlerArg C._xtos_set_interrupt_handler_arg +func X_xtosSetInterruptHandlerArg(n c.Int, f X_xtosHandler, arg c.Pointer) X_xtosHandler + +//go:linkname X_xtosSetExceptionHandler C._xtos_set_exception_handler +func X_xtosSetExceptionHandler(n c.Int, f X_xtosHandler) X_xtosHandler + +//go:linkname X_xtosMemepInitrams C._xtos_memep_initrams +func X_xtosMemepInitrams() + +//go:linkname X_xtosMemepEnable C._xtos_memep_enable +func X_xtosMemepEnable(flags c.Int) + +/* For use with the tiny LSP (see LSP reference manual). */ +//go:linkname X_xtosDispatchLevel1Interrupts C._xtos_dispatch_level1_interrupts +func X_xtosDispatchLevel1Interrupts() + +//go:linkname X_xtosDispatchLevel2Interrupts C._xtos_dispatch_level2_interrupts +func X_xtosDispatchLevel2Interrupts() + +//go:linkname X_xtosDispatchLevel3Interrupts C._xtos_dispatch_level3_interrupts +func X_xtosDispatchLevel3Interrupts() + +//go:linkname X_xtosDispatchLevel4Interrupts C._xtos_dispatch_level4_interrupts +func X_xtosDispatchLevel4Interrupts() + +//go:linkname X_xtosDispatchLevel5Interrupts C._xtos_dispatch_level5_interrupts +func X_xtosDispatchLevel5Interrupts() + +//go:linkname X_xtosDispatchLevel6Interrupts C._xtos_dispatch_level6_interrupts +func X_xtosDispatchLevel6Interrupts() + +/* Deprecated (but kept because they were documented): */ +//go:linkname X_xtosReadInts C._xtos_read_ints +func X_xtosReadInts() c.Uint + +//go:linkname X_xtosClearInts C._xtos_clear_ints +func X_xtosClearInts(mask c.Uint) + +/* Power shut-off related routines. */ +//go:linkname X_xtosCoreShutoff C._xtos_core_shutoff +func X_xtosCoreShutoff(flags c.Uint) c.Int + +//go:linkname X_xtosCoreSave C._xtos_core_save +func X_xtosCoreSave(flags c.Uint, savearea *XtosCoreState, code c.Pointer) c.Int + +//go:linkname X_xtosCoreRestore C._xtos_core_restore +func X_xtosCoreRestore(retvalue c.Uint, savearea *XtosCoreState) + +/* Deprecated: */ +//go:linkname X_xtosTimer0Delta C._xtos_timer_0_delta +func X_xtosTimer0Delta(cycles c.Int) + +//go:linkname X_xtosTimer1Delta C._xtos_timer_1_delta +func X_xtosTimer1Delta(cycles c.Int) + +//go:linkname X_xtosTimer2Delta C._xtos_timer_2_delta +func X_xtosTimer2Delta(cycles c.Int)