From 9938bb6f5c11e5f205e75da5385ba4eb708efe0b Mon Sep 17 00:00:00 2001 From: Qiuweihong <953950914@qq.com> Date: Mon, 12 Jan 2026 16:01:59 +0800 Subject: [PATCH] riscv64: add disassembly support and tests for zacas --- riscv64/riscv64asm/plan9x.go | 4 +- riscv64/riscv64asm/tables.go | 48 ++++++++++++++++++++++ riscv64/riscv64asm/testdata/gnucases.txt | 12 ++++++ riscv64/riscv64asm/testdata/plan9cases.txt | 12 ++++++ riscv64/riscv64spec/spec.go | 2 + 5 files changed, 77 insertions(+), 1 deletion(-) diff --git a/riscv64/riscv64asm/plan9x.go b/riscv64/riscv64asm/plan9x.go index b68deb3..8df65f0 100644 --- a/riscv64/riscv64asm/plan9x.go +++ b/riscv64/riscv64asm/plan9x.go @@ -48,7 +48,9 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text case AMOADD_D, AMOADD_D_AQ, AMOADD_D_RL, AMOADD_D_AQRL, AMOADD_W, AMOADD_W_AQ, AMOADD_W_RL, AMOADD_W_AQRL, AMOAND_D, AMOAND_D_AQ, AMOAND_D_RL, AMOAND_D_AQRL, - AMOAND_W, AMOAND_W_AQ, AMOAND_W_RL, AMOAND_W_AQRL, AMOMAXU_D, AMOMAXU_D_AQ, + AMOAND_W, AMOAND_W_AQ, AMOAND_W_RL, AMOAND_W_AQRL, AMOCAS_D, AMOCAS_D_AQ, + AMOCAS_D_AQRL, AMOCAS_D_RL, AMOCAS_Q, AMOCAS_Q_AQ, AMOCAS_Q_AQRL, AMOCAS_Q_RL, + AMOCAS_W, AMOCAS_W_AQ, AMOCAS_W_AQRL, AMOCAS_W_RL, AMOMAXU_D, AMOMAXU_D_AQ, AMOMAXU_D_RL, AMOMAXU_D_AQRL, AMOMAXU_W, AMOMAXU_W_AQ, AMOMAXU_W_RL, AMOMAXU_W_AQRL, AMOMAX_D, AMOMAX_D_AQ, AMOMAX_D_RL, AMOMAX_D_AQRL, AMOMAX_W, AMOMAX_W_AQ, AMOMAX_W_RL, AMOMAX_W_AQRL, AMOMINU_D, AMOMINU_D_AQ, AMOMINU_D_RL, AMOMINU_D_AQRL, AMOMINU_W, diff --git a/riscv64/riscv64asm/tables.go b/riscv64/riscv64asm/tables.go index 2a951f9..0d7a3f1 100644 --- a/riscv64/riscv64asm/tables.go +++ b/riscv64/riscv64asm/tables.go @@ -30,6 +30,18 @@ const ( AMOAND_W_AQ AMOAND_W_AQRL AMOAND_W_RL + AMOCAS_D + AMOCAS_D_AQ + AMOCAS_D_AQRL + AMOCAS_D_RL + AMOCAS_Q + AMOCAS_Q_AQ + AMOCAS_Q_AQRL + AMOCAS_Q_RL + AMOCAS_W + AMOCAS_W_AQ + AMOCAS_W_AQRL + AMOCAS_W_RL AMOMAXU_D AMOMAXU_D_AQ AMOMAXU_D_AQRL @@ -1026,6 +1038,18 @@ var opstr = [...]string{ AMOAND_W_AQ: "AMOAND.W.AQ", AMOAND_W_AQRL: "AMOAND.W.AQRL", AMOAND_W_RL: "AMOAND.W.RL", + AMOCAS_D: "AMOCAS.D", + AMOCAS_D_AQ: "AMOCAS.D.AQ", + AMOCAS_D_AQRL: "AMOCAS.D.AQRL", + AMOCAS_D_RL: "AMOCAS.D.RL", + AMOCAS_Q: "AMOCAS.Q", + AMOCAS_Q_AQ: "AMOCAS.Q.AQ", + AMOCAS_Q_AQRL: "AMOCAS.Q.AQRL", + AMOCAS_Q_RL: "AMOCAS.Q.RL", + AMOCAS_W: "AMOCAS.W", + AMOCAS_W_AQ: "AMOCAS.W.AQ", + AMOCAS_W_AQRL: "AMOCAS.W.AQRL", + AMOCAS_W_RL: "AMOCAS.W.RL", AMOMAXU_D: "AMOMAXU.D", AMOMAXU_D_AQ: "AMOMAXU.D.AQ", AMOMAXU_D_AQRL: "AMOMAXU.D.AQRL", @@ -2043,6 +2067,30 @@ var instFormats = [...]instFormat{ {mask: 0xfe00707f, value: 0x6600202f, op: AMOAND_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, // AMOAND.W.RL rd, rs2, rs1_ptr {mask: 0xfe00707f, value: 0x6200202f, op: AMOAND_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, + // AMOCAS.D rd, rs2, rs1_ptr + {mask: 0xfe00707f, value: 0x2800302f, op: AMOCAS_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, + // AMOCAS.D.AQ rd, rs2, rs1_ptr + {mask: 0xfe00707f, value: 0x2c00302f, op: AMOCAS_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, + // AMOCAS.D.AQRL rd, rs2, rs1_ptr + {mask: 0xfe00707f, value: 0x2e00302f, op: AMOCAS_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, + // AMOCAS.D.RL rd, rs2, rs1_ptr + {mask: 0xfe00707f, value: 0x2a00302f, op: AMOCAS_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, + // AMOCAS.Q rd, rs2, rs1_ptr + {mask: 0xfe00707f, value: 0x2800402f, op: AMOCAS_Q, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, + // AMOCAS.Q.AQ rd, rs2, rs1_ptr + {mask: 0xfe00707f, value: 0x2c00402f, op: AMOCAS_Q_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, + // AMOCAS.Q.AQRL rd, rs2, rs1_ptr + {mask: 0xfe00707f, value: 0x2e00402f, op: AMOCAS_Q_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, + // AMOCAS.Q.RL rd, rs2, rs1_ptr + {mask: 0xfe00707f, value: 0x2a00402f, op: AMOCAS_Q_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, + // AMOCAS.W rd, rs2, rs1_ptr + {mask: 0xfe00707f, value: 0x2800202f, op: AMOCAS_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, + // AMOCAS.W.AQ rd, rs2, rs1_ptr + {mask: 0xfe00707f, value: 0x2c00202f, op: AMOCAS_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, + // AMOCAS.W.AQRL rd, rs2, rs1_ptr + {mask: 0xfe00707f, value: 0x2e00202f, op: AMOCAS_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, + // AMOCAS.W.RL rd, rs2, rs1_ptr + {mask: 0xfe00707f, value: 0x2a00202f, op: AMOCAS_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, // AMOMAXU.D rd, rs2, rs1_ptr {mask: 0xfe00707f, value: 0xe000302f, op: AMOMAXU_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}}, // AMOMAXU.D.AQ rd, rs2, rs1_ptr diff --git a/riscv64/riscv64asm/testdata/gnucases.txt b/riscv64/riscv64asm/testdata/gnucases.txt index cbebf83..7c55151 100644 --- a/riscv64/riscv64asm/testdata/gnucases.txt +++ b/riscv64/riscv64asm/testdata/gnucases.txt @@ -19,6 +19,18 @@ afb26362| amoand.d.rl x5,x6,(x7) afa26360| amoand.w x5,x6,(x7) afa26364| amoand.w.aq x5,x6,(x7) afa26362| amoand.w.rl x5,x6,(x7) +afa2632e| amocas.w.aqrl x5,x6,(x7) +afa2632c| amocas.w.aq x5,x6,(x7) +afa2632a| amocas.w.rl x5,x6,(x7) +afa26328| amocas.w x5,x6,(x7) +afb2632e| amocas.d.aqrl x5,x6,(x7) +afb2632c| amocas.d.aq x5,x6,(x7) +afb2632a| amocas.d.rl x5,x6,(x7) +afb26328| amocas.d x5,x6,(x7) +afc2632e| amocas.q.aqrl x5,x6,(x7) +afc2632c| amocas.q.aq x5,x6,(x7) +afc2632a| amocas.q.rl x5,x6,(x7) +afc26328| amocas.q x5,x6,(x7) afb263e0| amomaxu.d x5,x6,(x7) afb263e4| amomaxu.d.aq x5,x6,(x7) afb263e2| amomaxu.d.rl x5,x6,(x7) diff --git a/riscv64/riscv64asm/testdata/plan9cases.txt b/riscv64/riscv64asm/testdata/plan9cases.txt index d4fd713..23392d3 100644 --- a/riscv64/riscv64asm/testdata/plan9cases.txt +++ b/riscv64/riscv64asm/testdata/plan9cases.txt @@ -19,6 +19,18 @@ afb26362| AMOANDD X6, (X7), X5 afa26360| AMOANDW X6, (X7), X5 afa26364| AMOANDW X6, (X7), X5 afa26362| AMOANDW X6, (X7), X5 +afa2632e| AMOCASW X6, (X7), X5 +afa2632c| AMOCASW X6, (X7), X5 +afa2632a| AMOCASW X6, (X7), X5 +afa26328| AMOCASW X6, (X7), X5 +afb2632e| AMOCASD X6, (X7), X5 +afb2632c| AMOCASD X6, (X7), X5 +afb2632a| AMOCASD X6, (X7), X5 +afb26328| AMOCASD X6, (X7), X5 +afc2632e| AMOCASQ X6, (X7), X5 +afc2632c| AMOCASQ X6, (X7), X5 +afc2632a| AMOCASQ X6, (X7), X5 +afc26328| AMOCASQ X6, (X7), X5 afb263e0| AMOMAXUD X6, (X7), X5 afb263e4| AMOMAXUD X6, (X7), X5 afb263e2| AMOMAXUD X6, (X7), X5 diff --git a/riscv64/riscv64spec/spec.go b/riscv64/riscv64spec/spec.go index 392965a..647f6e6 100644 --- a/riscv64/riscv64spec/spec.go +++ b/riscv64/riscv64spec/spec.go @@ -32,6 +32,7 @@ var extensions = []string{ "rv_m", "rv_q", "rv_v", + "rv_zacas", "rv_zba", "rv_zbb", "rv_zbs", @@ -46,6 +47,7 @@ var extensions = []string{ "rv64_i", "rv64_m", "rv64_q", + "rv64_zacas", "rv64_zba", "rv64_zbb", "rv64_zbs",