Support 64-bits address in C_M_AXI_MEM_BUS_ADDR_WIDTH #6
Description
Zynq-7000 devices are 32 bits, therefore, C_M_AXI_MEM_BUS_ADDR_WIDTH = 32.
However, for Ultrascale devices, C_M_AXI_MEM_BUS_ADDR_WIDTH could be 64 bits
if the IPs are synthesized with config_interface -m_axi_addr64
At this moment, even for Ultrascale devices, DART uses C_M_AXI_MEM_BUS_ADDR_WIDTH is fixed to 32 bits. Thus, when using a dart-generated design, make sure that FRED server is compiled without the define HW_TASKS_A64, to make it compatible with 32 bits.