logipi_wishbone: clock_gen missing

[peepo]

tried to synthesize:

WARNING:ProjectMgmt - File /ipcore_dir/clock_gen/example_design/clock_gen_exdes.ucf is missing.
WARNING:ProjectMgmt - File /ipcore_dir/clock_gen/example_design/clock_gen_exdes.vhd is missing.

[jpiat]

This is the same problem as earlier. To minimize git size and have a better organization we chose not to include the PLL files generated by Xilinx tools. I'll try to fix this in most project, but a solution is to generate the PLL by hands.

[peepo]

okay, I came across something maybe related trying to synth some of the other projects.

this probably needs a wiki write up to explain.
is this per individual project?

found Clocking Wizard, but clearly would need procedure to instantiate.

[jpiat]

I'll change the project to not use the wizard but do an instanciation straight in the VHDL.

[peepo]

your choice, but please bear in mind the user may wish to understand the process...

ie this is why one wants to build from sources....

I'm not yet in a position to comment, but note the sources are already large...

~:"