Stable, Dev and missing dependencies

[peepo]

Jonathan,

please accept my apologies if I have misconstrued how to build these projects.
I'm only just starting and they are quite large, at least for me....
It's a little difficult for me to give sufficient but not superfluous detail, please bear with me.

I am happy to contribute to either fpga-logi or fpga-logi-dev, but both might fry my brains.
please advise...

I am trying to synthesise logi_camera_test.xise,
though I may work through all the projects,
but camera & hardCV is my concern.

using fpga-logi-dev:
logi-hard is missing directory wishbone and contents, nb clock_gen is present vv
see: https://github.com/fpga-logi-dev/logi-hard

using fpga-logi:
directory logi-projects/logi-camera-test/hw/logipi/ise/ipcore_dir/clock_gen is missing
see: https://github.com/fpga-logi/logi-projects/tree/master/logi-camera-test/hw/logipi/ise/ipcore_dir

please advise what would be the most efficient approach.

I am keen to minimise both confusion, and the number of pull requests.

many thanks once again,

~:"

[jpiat]

I'll need to fix this project, the problem is that the clock_gen has to be
generated locally. GIve me a day to do the fix.

2015-01-20 15:13 GMT+01:00 Jonathan Chetwynd notifications@github.com:

Jonathan,

please accept my apologies if I have misconstrued how to build these
projects.
I'm only just starting and they are quite large, at least for me....
It's a little difficult for me to give sufficient but not superfluous
detail, please bear with me.

I am happy to contribute to either fpga-logi or fpga-logi-dev, but both
might fry my brains.
please advise...

I am trying to synthesise logi_camera_test.xise,
though I may work through all the projects,
but camera & hardCV is my concern.

using fpga-logi-dev:
logi-hard is missing directory wishbone and contents, nb clock_gen is
present vv
see: https://github.com/fpga-logi-dev/logi-hard

using fpga-logi:
directory
logi-projects/logi-camera-test/hw/logipi/ise/ipcore_dir/clock_gen is missing
see:
https://github.com/fpga-logi/logi-projects/tree/master/logi-camera-test/hw/logipi/ise/ipcore_dir

please advise what would be the most efficient approach.

I am keen to minimise both confusion, and the number of pull requests.

many thanks once again,

~:"

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#4.

[peepo]

sticking with fpga-logi,

the attached all look clock related,
but please check,
as iirc there were some other non-clock related typo errors.

~:"

Line 244: Formal port/generic <b_burst_size> is not declared in <wishbone_fifo>

ERROR:HDLCompiler:XXXX - ".../logi-projects/logi-camera-test/hw/logipi/hdl/logi_camera_test.vhd"

Line 262: Formal port/generic is not declared in <wishbone_fifo>
Line 240: Formal <write_fifo> has no actual or default value.
Line 354: Formal port/generic is not declared in <yuv_camera_interface>
Line 349: Formal has no actual or default value.
Line 378: Formal port/generic <pixel_clock> is not declared in <down_scaler>
Line 373: Formal <pixel_in_clk> has no actual or default value.
Line 388: <yuv_pixel2fifo> is not declared.
Line 67: Unit ignored due to previous errors.

[peepo]

Jonathan,

please can you advise on further progress?

thanks again

[jpiat]

Just made the changes. Can you try to synthesize on your side ? You'll need
to update logi-projects and hard-cv

2015-01-23 8:48 GMT+01:00 Jonathan Chetwynd notifications@github.com:

Jonathan,

please can you advise on further progress?

thanks again

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#4 (comment)
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[peepo]

okay, apologies, but bogged down in a morass just now...

will try today or else over weekend

[jpiat]

Don't hesistate to report more bugs. There was some changes in logi-hard
and hard-cv and not all the projects were updated acordingly.

2015-01-23 11:02 GMT+01:00 Jonathan Chetwynd notifications@github.com:

okay, apologies, but bogged down in a morass just now...

will try today or else over weekend

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#4 (comment)
.

[peepo]

Jonathan,

is logi-camera-test the best place to start?
there maybe simpler examples that do synthesise.
or where I can provide more support,
perhaps you can suggest an order that I could take the projects in?

regarding the original issue as described:
today I created a new folder and placed new hard-cv, new logi-projects together with logi-hard.

I tried to synthesise logi-camera-test:
dialogue: source files in the project cannot be found (1):
missing files: .../hard-cv/hw/rtl/image/yuv_to_fifo.vhd

only reference to yuv_to_fifo.vhd on Google: image_pack.vhd

component yuv_to_fifo is
port(
clk, resetn, sreset : in std_logic ;
pixel_in_clk,pixel_in_hsync,pixel_in_vsync : in std_logic;
pixel_in_y_data, pixel_in_u_data, pixel_in_v_data : in std_logic_vector(7 downto 0);
fifo_data : out std_logic_vector(15 downto 0);
fifo_wr : out std_logic
);
end component;

appreciate your patience.

[jpiat]

I just pushed the file on the git again. Can you update hard-cv and see if
it works ?

What is your experience with VHDL ?

2015-01-23 13:17 GMT+01:00 Jonathan Chetwynd notifications@github.com:

Jonathan,

is logi-camera-test the best place to start?
there maybe simpler examples that do synthesise.
or where I can provide more support,
perhaps you can suggest an order that I could take the projects in?

regarding the original issue as described:
today I created a new folder and placed new hard-cv, new logi-projects
together with logi-hard.

I tried to synthesise logi-camera-test:
dialogue: source files in the project cannot be found (1):
missing files: .../hard-cv/hw/rtl/image/yuv_to_fifo.vhd

only reference to yuv_to_fifo.vhd on Google: image_pack.vhd

component yuv_to_fifo is
port(
clk, resetn, sreset : in std_logic ;
pixel_in_clk,pixel_in_hsync,pixel_in_vsync : in std_logic;
pixel_in_y_data, pixel_in_u_data, pixel_in_v_data : in std_logic_vector(7
downto 0);
fifo_data : out std_logic_vector(15 downto 0);
fifo_wr : out std_logic
);
end component;

appreciate your patience.

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#4 (comment)
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[peepo]

I tried what I believe was a fully up to date build of logi-camera-demo[1]
however logipi-hw.xise requires yuv_pixel2fifo.vhd
but hard-cv has no such file.[2]

please advise

[1]https://github.com/fpga-logi/logi-projects/blob/master/logi-camera-demo/hw/logipi/ise/logipi-hw.xise
[2]https://github.com/jpiat/hard-cv/tree/master/hw/rtl/image/

[jpiat]

can you try again just comitted the changes

2015-02-08 19:49 GMT+01:00 Jonathan Chetwynd notifications@github.com:

I tried what I believe was a fully up to date build of logi-camera-demo[1]
however logipi-hw.xise requires yuv_pixel2fifo.vhd
but hard-cv has no such file.[2]

please advise

[1]
https://github.com/fpga-logi/logi-projects/blob/master/logi-camera-demo/hw/logipi/ise/logipi-hw.xise
[2]https://github.com/jpiat/hard-cv/tree/master/hw/rtl/image/

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#4 (comment)
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[peepo]

I updated and tried again, same result. please read previous comment:

Line 138 of /logipi-hw.xise in logi-camera-demo requires yuv_pixel2fifo.vhd which is not present in hard-cv.

it may be there is also an issue with clocks, but cannot confirm until this is fixed.

[jpiat]

It should be fine now. Everything was fine but i forgot to commit the
project file.

2015-02-09 8:45 GMT+01:00 Jonathan Chetwynd notifications@github.com:

I updated and tried again, same result. please read previous comment:

Line 138 of /logipi-hw.xise in logi-camera-demo requires
yuv_pixel2fifo.vhd which is not present in hard-cv.

it may be there is also an issue with clocks, but cannot confirm until
this is fixed.

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#4 (comment)
.

[jpiat]

You are ritgh, the clock will also create a problem as it requires the user
to create the clock_gen component from ip_core. I'll fix this.

2015-02-09 8:56 GMT+01:00 Jonathan Piat piat.jonathan@gmail.com:

It should be fine now. Everything was fine but i forgot to commit the
project file.

2015-02-09 8:45 GMT+01:00 Jonathan Chetwynd notifications@github.com:

I updated and tried again, same result. please read previous comment:

Line 138 of /logipi-hw.xise in logi-camera-demo requires
yuv_pixel2fifo.vhd which is not present in hard-cv.

it may be there is also an issue with clocks, but cannot confirm until
this is fixed.

—
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#4 (comment)
.

[peepo]

yup will need plenty of patience from both of us...

i'm working on other logi-projects, but one at a time as it were...

many thanks

~:"

---

From: Piat Jonathan notifications@github.com
Sent: 09 February 2015 07:56
To: fpga-logi/logi-projects
Cc: Jonathan Chetwynd
Subject: Re: [logi-projects] Stable, Dev and missing dependencies (#4)

It should be fine now. Everything was fine but i forgot to commit the
project file.

2015-02-09 8:45 GMT+01:00 Jonathan Chetwynd notifications@github.com:

I updated and tried again, same result. please read previous comment:

Line 138 of /logipi-hw.xise in logi-camera-demo requires
yuv_pixel2fifo.vhd which is not present in hard-cv.

it may be there is also an issue with clocks, but cannot confirm until
this is fixed.

Reply to this email directly or view it on GitHub
#4 (comment)
.

Reply to this email directly or view it on GitHubhttps://github.com//issues/4#issuecomment-73469659.

[jpiat]

Sure, problem is that we have multi-component that evolve over time but its
hard to keep track of all the changes and reflect all of them into the
projects. One solution could be to create releases of both logi-hard,
logi-projects, hard-cv to make sure that things are all working at a point
in time.

2015-02-09 8:59 GMT+01:00 Jonathan Chetwynd notifications@github.com:

yup will need plenty of patience from both of us...

i'm working on other logi-projects, but one at a time as it were...

many thanks

~:"

---

From: Piat Jonathan notifications@github.com
Sent: 09 February 2015 07:56
To: fpga-logi/logi-projects
Cc: Jonathan Chetwynd
Subject: Re: [logi-projects] Stable, Dev and missing dependencies (#4)

It should be fine now. Everything was fine but i forgot to commit the
project file.

2015-02-09 8:45 GMT+01:00 Jonathan Chetwynd notifications@github.com:

I updated and tried again, same result. please read previous comment:

Line 138 of /logipi-hw.xise in logi-camera-demo requires
yuv_pixel2fifo.vhd which is not present in hard-cv.

it may be there is also an issue with clocks, but cannot confirm until
this is fixed.

Reply to this email directly or view it on GitHub
<
https://github.com/fpga-logi/logi-projects/issues/4#issuecomment-73468644>
.

Reply to this email directly or view it on GitHub<
#4 (comment)

.

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#4 (comment)
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