Hi experts,
I am trying to get familiar with the Logibone studying the logi-wishbone project. In the gpmc_wishbone_wrapper module there is a clock domain crossing between the GPMC and the Wishbone, but the destination domain only presents a single FF before the signals are sent to the Wishbone interconnect network. Should not it use a dual FF synchronizer to avoid metastability?
In the same file, the attribute IOB of iob_writedata is set to true. After reading Xilinx documentation, I understand that this attribute is used to pull a register into an IOB cell, but iob_writedata is not a registered signal (it connects directly to the three-state buffer in the IO pad). Should not the attribute apply to a registered signal to have any effect?
I apologize if my comments are not issues at all. I am not an expert in hardware design and sometimes I find Xilinx documentation overwhelming (even confusing), so I might miss some details.
Thank you,
JC
Hi experts,
I am trying to get familiar with the Logibone studying the logi-wishbone project. In the gpmc_wishbone_wrapper module there is a clock domain crossing between the GPMC and the Wishbone, but the destination domain only presents a single FF before the signals are sent to the Wishbone interconnect network. Should not it use a dual FF synchronizer to avoid metastability?
In the same file, the attribute IOB of iob_writedata is set to true. After reading Xilinx documentation, I understand that this attribute is used to pull a register into an IOB cell, but iob_writedata is not a registered signal (it connects directly to the three-state buffer in the IO pad). Should not the attribute apply to a registered signal to have any effect?
I apologize if my comments are not issues at all. I am not an expert in hardware design and sometimes I find Xilinx documentation overwhelming (even confusing), so I might miss some details.
Thank you,
JC