testing project in zedboard

[fpgasdr]

Hello @asuardi,
running the commands of the steps you provide in Xilinx Vivado design flow example design in tcl command line I'm stucked in the last step when i want to run the test in the zedboard.

the command runs and remains running without any output and never ends.

the last output in terminal is:
Calling Matlab to test the IP running on the FPGA evaluation board...
and in progress bar I can read:
running common::set_param..
I tried this step in two machines one with ubuntu and another with windows 7 but both of them do the same.
Looking at the ip_prototype_test.tcl it seems could be wait for Matlab to finish but because Matlab never starts but I tried to path corectly the Matlab.exe and still get the same result.
maybe the problem is may connection with the zedboard?.I followed the steps you provide in configuring interfaces.
Do you have any idea what could be happening?.

Thanks,
regards.

[fpgasdr]

I've discovered that changing the code of the ip_prototype_test.tcl located in C:\Xilinx\Vivado\2015.4\data\XilinxTclStore\tclapp\icl\protoip doesn't change the running command. where it should be located?, because looking for this script in all xilinx folder doesn't find any other place.