From 3f18409278692071dbd491840c0e440049af3503 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Fri, 19 Dec 2025 09:13:05 -0800
Subject: [PATCH] Verilog: test for name collision between typedef and module
 instance name

---
 .../verilog/typedef/typedef_name_collision3.desc    |  7 +++++++
 .../verilog/typedef/typedef_name_collision3.sv      | 13 +++++++++++++
 2 files changed, 20 insertions(+)
 create mode 100644 regression/verilog/typedef/typedef_name_collision3.desc
 create mode 100644 regression/verilog/typedef/typedef_name_collision3.sv

diff --git a/regression/verilog/typedef/typedef_name_collision3.desc b/regression/verilog/typedef/typedef_name_collision3.desc
new file mode 100644
index 000000000..c8bfa0b47
--- /dev/null
+++ b/regression/verilog/typedef/typedef_name_collision3.desc
@@ -0,0 +1,7 @@
+CORE
+typedef_name_collision3.sv
+
+^file .* line 11: duplicate definition of identifier `some_identifier' in module `main'$
+^EXIT=2$
+^SIGNAL=0$
+--
diff --git a/regression/verilog/typedef/typedef_name_collision3.sv b/regression/verilog/typedef/typedef_name_collision3.sv
new file mode 100644
index 000000000..2b8d99cb2
--- /dev/null
+++ b/regression/verilog/typedef/typedef_name_collision3.sv
@@ -0,0 +1,13 @@
+module sub;
+
+
+endmodule
+
+module main;
+
+  wire some_identifier;
+
+  // name collision
+  sub some_identifier();
+
+endmodule