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Description
Proteus' JTAG core was built first, but in the long run it should support more wire (ISC) protocols.
Proteus should also be able to combine multiple wire protocols at once.
For example, on a system with an FPGA attached to a flash chip (containing the FPGA's startup configuration) over spi. A common approach to programming the SPI Flash is to load a program into the FPGA's RAM that turns the FPGA into a flash chip writer so the Flash device can be programmed over JTAG (with the FPGA as an adapter).
Proteus should be able to load a flashing program into the FPGA's RAM, and then use the FPGA as an SPI controller (automatically adapting the JTAG calls).
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