How to represent links between tiles and mem with spec?

[yuqisun]

Hi @tancheng ,

One question, looks no field to represent link(s) between tile(s) and mem? Or default all tiles near mem connect?

dataflow/test/arch_spec/arch_spec_example.yaml

Lines 28 to 51 in 1cb3c7c

	link_overrides:
	- src_cgra_x: 0
	src_cgra_y: 0
	dst_cgra_x: 0
	dst_cgra_y: 0
	src_tile_x: 0
	src_tile_y: 0
	dst_tile_x: 1
	dst_tile_y: 1
	latency: 2
	bandwidth: 32
	existence: true
	- src_cgra_x: 1
	src_cgra_y: 0
	dst_cgra_x: 1
	dst_cgra_y: 0
	src_tile_x: 1
	src_tile_y: 1
	dst_tile_x: 0
	dst_tile_y: 0
	latency: 2
	bandwidth: 32
	existence: true

Thanks,

[tancheng]

Ah, you are right, I think we can use the tile's ["load"/"store"] to indicate whether a tile is connecting to the mem.

dataflow/test/arch_spec/arch_spec_example.yaml

Lines 53 to 60 in 1cb3c7c

	tile_overrides:
	- cgra_x: 0
	cgra_y: 0
	tile_x: 0
	tile_y: 0
	operations: ["load"]
	num_registers: 32
	existence: true

If either "load" or "store" exists, bidirectional links should be there. How does this sound?