diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
index ec6d82cdf2..02f3147253 100644
--- a/src/main/scala/rocket/RocketCore.scala
+++ b/src/main/scala/rocket/RocketCore.scala
@@ -847,6 +847,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
 
     io.trace_core_ingress.get.group(0) <> trace_ingress.io.out
     io.trace_core_ingress.get.priv := csr.io.trace(0).priv 
+    io.trace_core_ingress.get.ctx := csr.io.ptbr.asid
     io.trace_core_ingress.get.tval := csr.io.tval
     io.trace_core_ingress.get.cause := csr.io.cause
     io.trace_core_ingress.get.time := csr.io.time
diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index be709854f3..9a05a09fa5 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -92,7 +92,7 @@ class RocketTile private(
    * and selecting trace sink
    */
   val trace_encoder_controller = rocketParams.traceParams.map { t =>
-    val trace_encoder_controller = LazyModule(new TraceEncoderController(t.encoderBaseAddr, xBytes))
+    val trace_encoder_controller = LazyModule(new TraceEncoderController(t.encoderBaseAddr, xBytes, tileId))
     connectTLSlave(trace_encoder_controller.node, xBytes)
     trace_encoder_controller
   }
diff --git a/src/main/scala/trace/TraceCoreIngress.scala b/src/main/scala/trace/TraceCoreIngress.scala
index ce4b021fea..214d54ed07 100644
--- a/src/main/scala/trace/TraceCoreIngress.scala
+++ b/src/main/scala/trace/TraceCoreIngress.scala
@@ -43,7 +43,7 @@ class TraceCoreIngress(val params: TraceCoreParams) extends Module {
         itype := TraceItype.ITNothing
     }
     itype
-}
+  }
   
   io.out.iretire := io.in.valid
   io.out.iaddr := io.in.pc
diff --git a/src/main/scala/trace/TraceCoreInterface.scala b/src/main/scala/trace/TraceCoreInterface.scala
index 64eb16eb70..c5f79d1bb1 100644
--- a/src/main/scala/trace/TraceCoreInterface.scala
+++ b/src/main/scala/trace/TraceCoreInterface.scala
@@ -43,6 +43,7 @@ class TraceCoreGroup (val params: TraceCoreParams) extends Bundle {
 class TraceCoreInterface (val params: TraceCoreParams) extends Bundle {
   val group = Vec(params.nGroups, new TraceCoreGroup(params))
   val priv = UInt(4.W)
+  val ctx = UInt(params.xlen.W)
   val tval = UInt(params.xlen.W)
   val cause = UInt(params.xlen.W)
   val time = UInt(params.xlen.W)
diff --git a/src/main/scala/trace/TraceEncoderController.scala b/src/main/scala/trace/TraceEncoderController.scala
index 6a5c2bc7b6..f80f321791 100644
--- a/src/main/scala/trace/TraceEncoderController.scala
+++ b/src/main/scala/trace/TraceEncoderController.scala
@@ -21,15 +21,14 @@ class TraceEncoderControlInterface() extends Bundle {
   val target = UInt(TraceSinkTarget.width.W)
   val bp_mode = UInt(32.W)
 }
-class TraceEncoderController(addr: BigInt, beatBytes: Int)(implicit p: Parameters) extends LazyModule {
+class TraceEncoderController(addr: BigInt, beatBytes: Int, hartId: Int)(implicit p: Parameters) extends LazyModule {
 
-  val device = new SimpleDevice("trace-encoder-controller", Seq("ucbbar,trace0"))
+  val device = new SimpleDevice(s"trace-encoder-controller$hartId", Seq("ucbbar,trace"))
   val node = TLRegisterNode(
     address = Seq(AddressSet(addr, 0xFF)),
     device = device,
     beatBytes = beatBytes
   )
-  
   override lazy val module = new Impl
   class Impl extends LazyModuleImp(this) {
     val io = IO(new Bundle {
@@ -73,7 +72,7 @@ class TraceEncoderController(addr: BigInt, beatBytes: Int)(implicit p: Parameter
             RegFieldDesc("impl", "Trace encoder implementation"))
         ),
         0x20 -> Seq(
-          RegField(1, trace_sink_target,
+          RegField(8, trace_sink_target,
             RegFieldDesc("target", "Trace sink target"))
         ),
         0x24 -> Seq(