From 31e40127b4e27a1eb2b172d853ce750a12fcbddf Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 1 Sep 2025 14:57:19 -0700
Subject: [PATCH] Fix for chisel7 compat

---
 src/main/scala/rocket/CSR.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala
index a608c57938..0e93138806 100644
--- a/src/main/scala/rocket/CSR.scala
+++ b/src/main/scala/rocket/CSR.scala
@@ -325,8 +325,8 @@ class VConfig(implicit p: Parameters) extends CoreBundle {
 
 object VType {
   def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = {
-    val res = 0.U.asTypeOf(new VType)
-    val in = that.asTypeOf(res)
+    val res = WireInit(0.U.asTypeOf(new VType))
+    val in = that.asTypeOf(new VType)
     val vill = (in.max_vsew.U < in.vsew) || !in.lmul_ok || in.reserved =/= 0.U || in.vill
     when (!vill || ignore_vill.B) {
       res := in