Sync dev into master #3757

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Merged

jerryz123 merged 40 commits into master from dev

Sep 1, 2025

.github/workflows/mill-ci.yml

            
                      Original file line number
                      Diff line number
                      Diff line change
                  
    @@ -27,17 +27,17 @@ jobs:
  
          matrix:

            config: [DefaultConfig, DefaultBufferlessConfig, DefaultRV32Config, TinyConfig, DefaultFP16Config, DefaultBConfig, DefaultRV32BConfig]

        steps:

          - uses: actions/checkout@v2

          - uses: actions/checkout@v4

            with:

              submodules: 'true'

          - uses: cachix/install-nix-action@v19

          - uses: cachix/install-nix-action@v31

            with:

              install_url: https://releases.nixos.org/nix/nix-2.13.3/install

              nix_path: nixpkgs=channel:nixos-unstable

          - name: Coursier Cache

            uses: coursier/cache-action@v5

            uses: coursier/cache-action@v6

          - name: run riscv-tests

            run: |

    @@ -50,17 +50,17 @@ jobs:
  
          matrix:

            config: [DefaultSmallConfig, DualBankConfig, DualChannelConfig, DualChannelDualBankConfig, RoccExampleConfig, Edge128BitConfig, Edge32BitConfig, QuadChannelBenchmarkConfig, EightChannelConfig, DualCoreConfig, MemPortOnlyConfig, MMIOPortOnlyConfig, CloneTileConfig, HypervisorConfig]

        steps:

          - uses: actions/checkout@v2

          - uses: actions/checkout@v4

            with:

              submodules: 'true'

          - uses: cachix/install-nix-action@v19

          - uses: cachix/install-nix-action@v31

            with:

              install_url: https://releases.nixos.org/nix/nix-2.13.3/install

              nix_path: nixpkgs=channel:nixos-unstable

          - name: Coursier Cache

            uses: coursier/cache-action@v5

            uses: coursier/cache-action@v6

          - name: compile emulator

            run: |

    @@ -74,12 +74,12 @@ jobs:
  
          matrix:

            config: ["DefaultRV32Config,32,RV32IMACZicsr_Zifencei", "DefaultConfig,64,RV64IMACZicsr_Zifencei"]

        steps:

          - uses: actions/checkout@v2

          - uses: actions/checkout@v4

            with:

              submodules: 'true'

          - name: install nix

            uses: cachix/install-nix-action@v19

            uses: cachix/install-nix-action@v31

            with:

              install_url: https://releases.nixos.org/nix/nix-2.13.3/install

              nix_path: nixpkgs=channel:nixos-unstable

    @@ -98,12 +98,12 @@ jobs:
  
          matrix:

            config: ["freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultConfig", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultRV32Config", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultConfig", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultRV32Config"]

        steps:

          - uses: actions/checkout@v2

          - uses: actions/checkout@v4

            with:

              submodules: 'true'

          - name: install nix

            uses: cachix/install-nix-action@v19

            uses: cachix/install-nix-action@v31

            with:

              install_url: https://releases.nixos.org/nix/nix-2.13.3/install

              nix_path: nixpkgs=channel:nixos-unstable

build.sc

            
                      Original file line number
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    @@ -12,7 +12,7 @@ object v {
  
      val scala = "2.13.12"

      // the first version in this Map is the mainly supported version which will be used to run tests

      val chiselCrossVersions = Map(

        "5.1.0" -> (ivy"org.chipsalliance::chisel:5.1.0", ivy"org.chipsalliance:::chisel-plugin:5.1.0"),

        "6.7.0" -> (ivy"org.chipsalliance::chisel:6.7.0", ivy"org.chipsalliance:::chisel-plugin:6.7.0"),

        // build from project from source

        "source" -> (ivy"org.chipsalliance::chisel:99", ivy"org.chipsalliance:::chisel-plugin:99"),

      )

src/main/scala/amba/ahb/Nodes.scala

-Original file line number
+Diff line change
@@ Expand Up @@
       override def monitor(bundle: AHBSlaveBundle, edge: AHBEdgeParameters): Unit = {
         edge.params.lift(AHBSlaveMonitorBuilder).foreach { builder =>
           val monitor = Module(builder(AHBSlaveMonitorArgs(edge)))
-          monitor.io.in := bundle
+          monitor.io.in :#= bundle
         }
       }
@@ Expand All @@
       override def monitor(bundle: AHBMasterBundle, edge: AHBEdgeParameters): Unit = {
         edge.params.lift(AHBMasterMonitorBuilder).foreach { builder =>
           val monitor = Module(builder(AHBMasterMonitorArgs(edge)))
-          monitor.io.in := bundle
+          monitor.io.in :#= bundle
         }
       }
@@ Expand Down @@

src/main/scala/amba/ahb/Xbar.scala

-Original file line number
+Diff line change
@@ Expand Up @@
             requestKeys    = seq.flatMap(_.requestKeys).distinct,
             responseFields = BundleField.union(seq.flatMap(_.responseFields))) }
       ){
-        override def circuitIdentity = outputs == 1 && inputs == 1
+        override def circuitIdentity = outputs.size == 1 && inputs.size == 1
       }
       lazy val module = new Impl
@@ Expand Down @@

src/main/scala/amba/apb/Nodes.scala

-Original file line number
+Diff line change
@@ Expand Up @@
       override def monitor(bundle: APBBundle, edge: APBEdgeParameters): Unit = {
         edge.params.lift(APBMonitorBuilder).foreach { builder =>
           val monitor = Module(builder(APBMonitorArgs(edge)))
-          monitor.io.in := bundle
+          monitor.io.in :#= bundle
         }
       }
@@ Expand Down @@

src/main/scala/amba/apb/Xbar.scala

-Original file line number
+Diff line change
@@ Expand Up @@
             requestKeys    = seq.flatMap(_.requestKeys).distinct,
             responseFields = BundleField.union(seq.flatMap(_.responseFields))) }
       ){
-        override def circuitIdentity = outputs == 1 && inputs == 1
+        override def circuitIdentity = outputs.size == 1 && inputs.size == 1
       }
       lazy val module = new Impl
@@ Expand Down @@

src/main/scala/amba/axi4/Buffer.scala

-Original file line number
+Diff line change
@@ Expand Up / @@ -68,4 +68,16 @@ object AXI4Buffer @@
         val axi4buf = LazyModule(new AXI4Buffer(aw, w, b, ar, r))
         axi4buf.node
       }
+      def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[AXI4Node] = {
+        val buffers = Seq.fill(depth) { LazyModule(new AXI4Buffer()) }
+        name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
+        buffers.map(_.node)
+      }
+      def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): AXI4Node = {
+        chain(depth, name)
+          .reduceLeftOption(_ :*=* _)
+          .getOrElse(AXI4NameNode("no_buffer"))
+      }
     }

src/main/scala/amba/axi4/Nodes.scala

-Original file line number
+Diff line change
@@ Expand Up @@
       override def monitor(bundle: AXI4Bundle, edge: AXI4EdgeParameters): Unit = {
         edge.params.lift(AXI4MonitorBuilder).foreach { builder =>
           val monitor = Module(builder(AXI4MonitorArgs(edge)))
-          monitor.io.in := bundle
+          monitor.io.in :#= bundle
         }
       }
@@ Expand Down @@

src/main/scala/amba/axi4/SRAM.scala

            
                      Original file line number
                      Diff line number
                      Diff line change
                  
    @@ -75,8 +75,8 @@ class AXI4RAM(
  
        val w_full = RegInit(false.B)

        val w_id   = Reg(UInt())

        val w_echo = Reg(BundleMap(in.params.echoFields))

        val r_sel1 = RegNext(r_sel0)

        val w_sel1 = RegNext(w_sel0)

        val r_sel1 = Reg(Bool())

        val w_sel1 = Reg(Bool())

        when (in. b.fire) { w_full := false.B }

        when (in.aw.fire) { w_full := true.B }

src/main/scala/amba/axi4/Xbar.scala

-Original file line number
+Diff line change
@@ Expand Up / @@ -53,7 +53,7 @@ class AXI4Xbar( @@
           )
         }
       ){
-        override def circuitIdentity = outputs == 1 && inputs == 1
+        override def circuitIdentity = outputs.size == 1 && inputs.size == 1
       }
       lazy val module = new Impl
@@ Expand Down @@

src/main/scala/devices/debug/Debug.scala

-Original file line number
+Diff line change
@@ Expand Up @@
     import freechips.rocketchip.rocket.{CSRs, Instructions}
     import freechips.rocketchip.tile.MaxHartIdBits
     import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar}
-    import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle}
+    import freechips.rocketchip.util.{AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle}
     import freechips.rocketchip.util.SeqBoolBitwiseOps
     import freechips.rocketchip.util.SeqToAugmentedSeq
@@ Expand Down Expand Up @@
       lazy val module = new Impl
       class Impl extends LazyModuleImp(this){
         val nComponents = getNComponents()
-        Annotated.params(this, cfg)
         val supportHartArray = cfg.supportHartArray & (nComponents > 1)
         val nExtTriggers = cfg.nExtTriggers
         val nHaltGroups = if ((nComponents > 1) | (nExtTriggers > 0)) cfg.nHaltGroups
@@ Expand Down @@

src/main/scala/devices/tilelink/BootROM.scala

            
                      Original file line number
                      Diff line number
                      Diff line change
                  
    @@ -13,6 +13,7 @@ import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
  
    import freechips.rocketchip.resources.{Resource, SimpleDevice}

    import freechips.rocketchip.subsystem._

    import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters}

    import freechips.rocketchip.util.{FileName, SystemFileName, ResourceFileName}

    import java.nio.ByteBuffer

    import java.nio.file.{Files, Paths}

    @@ -22,7 +23,11 @@ case class BootROMParams(
  
      address: BigInt = 0x10000,

      size: Int = 0x10000,

      hang: BigInt = 0x10040, // The hang parameter is used as the power-on reset vector

      contentFileName: String)

      driveResetVector: Boolean = true,

      appendDTB: Boolean = true,

      name: String = "bootrom",

      contentFileName: FileName = SystemFileName("./bootrom/bootrom.img")

    )

    class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,

      resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule

    @@ -63,7 +68,7 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec
  
      }

    }

    case class BootROMLocated(loc: HierarchicalLocation) extends Field[Option[BootROMParams]](None)

    case class BootROMLocated(loc: HierarchicalLocation) extends Field[Seq[BootROMParams]](Nil)

    object BootROM {

      /** BootROM.attach not only instantiates a TLROM and attaches it to the tilelink interconnect

    @@ -73,27 +78,40 @@ object BootROM {
  
      def attach(params: BootROMParams, subsystem: BaseSubsystem with HasHierarchicalElements with HasTileInputConstants, where: TLBusWrapperLocation)

                (implicit p: Parameters): TLROM = {

        val tlbus = subsystem.locateTLBusWrapper(where)

        val bootROMDomainWrapper = tlbus.generateSynchronousDomain("BootROM").suggestName("bootrom_domain")

        val bootROMDomainWrapper = tlbus.generateSynchronousDomain(params.name).suggestName(s"${params.name}_domain")

        val bootROMResetVectorSourceNode = BundleBridgeSource[UInt]()

        lazy val contents = {

          val romdata = Files.readAllBytes(Paths.get(params.contentFileName))

          val rom = ByteBuffer.wrap(romdata)

          rom.array() ++ subsystem.dtb.contents

        val rom = params.contentFileName match {

          case SystemFileName(fileName) => {

            val romdata = Files.readAllBytes(Paths.get(fileName))

            ByteBuffer.wrap(romdata).array()

          }

          case ResourceFileName(fileName) => {

            val file = os.resource / os.RelPath(fileName.dropWhile(_ == '/'))

            os.read.bytes(file)

          }

        }

        lazy val contents = if (params.appendDTB) {

          rom ++ subsystem.dtb.contents

        } else {

          rom

        }

        val bootrom = bootROMDomainWrapper {

          LazyModule(new TLROM(params.address, params.size, contents, true, tlbus.beatBytes))

        }

        bootrom.node := tlbus.coupleTo("bootrom"){ TLFragmenter(tlbus, Some("BootROM")) := _ }

        bootrom.node := tlbus.coupleTo(params.name){ TLFragmenter(tlbus, Some(params.name)) := _ }

        // Drive the `subsystem` reset vector to the `hang` address of this Boot ROM.

        subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode

        InModuleBody {

          val reset_vector_source = bootROMResetVectorSourceNode.bundle

          require(reset_vector_source.getWidth >= params.hang.bitLength,

            s"BootROM defined with a reset vector (${params.hang})too large for physical address space (${reset_vector_source.getWidth})")

          bootROMResetVectorSourceNode.bundle := params.hang.U

        if (params.driveResetVector) {

          subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode

          InModuleBody {

            val reset_vector_source = bootROMResetVectorSourceNode.bundle

            require(reset_vector_source.getWidth >= params.hang.bitLength,

              s"BootROM defined with a reset vector (${params.hang})too large for physical address space (${reset_vector_source.getWidth})")

            bootROMResetVectorSourceNode.bundle := params.hang.U

          }

        }

        bootrom

      }

src/main/scala/devices/tilelink/CLINT.scala

-Original file line number
+Diff line change
@@ Expand Up @@
     import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
     import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
     import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
-    import freechips.rocketchip.util.Annotated
     object CLINTConsts
     {
@@ Expand Down Expand Up @@
       lazy val module = new Impl
       class Impl extends LazyModuleImp(this) {
-        Annotated.params(this, params)
         require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them")
         val io = IO(new Bundle {
@@ Expand Down @@

src/main/scala/devices/tilelink/Plic.scala

-Original file line number
+Diff line change
@@ Expand Up @@
     import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn}
     import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
     import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
-    import freechips.rocketchip.util.{Annotated, MuxT, property}
+    import freechips.rocketchip.util.{MuxT, property}
     import scala.math.min
@@ Expand Down Expand Up @@
       lazy val module = new Impl
       class Impl extends LazyModuleImp(this) {
-        Annotated.params(this, params)
         val (io_devices, edgesIn) = intnode.in.unzip
         val (io_harts, _) = intnode.out.unzip
@@ Expand Down @@

src/main/scala/interrupts/Xbar.scala

            
                      Original file line number
                      Diff line number
                      Diff line change
                  
    @@ -15,7 +15,7 @@ class IntXbar()(implicit p: Parameters) extends LazyModule
  
          }.flatten)

        })

      {

        override def circuitIdentity = outputs == 1 && inputs == 1

        override def circuitIdentity = outputs.size == 1 && inputs.size == 1

      }

      lazy val module = new Impl

    @@ -36,7 +36,7 @@ class IntSyncXbar()(implicit p: Parameters) extends LazyModule
  
          }.flatten)

        })

      {

        override def circuitIdentity = outputs == 1 && inputs == 1

        override def circuitIdentity = outputs.size == 1 && inputs.size == 1

      }

      lazy val module = new Impl

src/main/scala/rocket/BTB.scala

-Original file line number
+Diff line change
@@ Expand Up @@
       val nPages = (btbParams.nPages + 1) / 2 * 2 // control logic assumes 2 divides pages
     }
-    abstract class BtbModule(implicit val p: Parameters) extends Module with HasBtbParameters {
-      Annotated.params(this, btbParams)
-    }
+    abstract class BtbModule(implicit val p: Parameters) extends Module with HasBtbParameters
     abstract class BtbBundle(implicit val p: Parameters) extends Bundle with HasBtbParameters
@@ Expand Down Expand Up / @@ -301,7 +299,7 @@ class BTB(implicit p: Parameters) extends BtbModule { @@
       }
       if (btbParams.bhtParams.nonEmpty) {
-        val bht = new BHT(Annotated.params(this, btbParams.bhtParams.get))
+        val bht = new BHT(btbParams.bhtParams.get)
         val isBranch = (idxHit & cfiType.map(_ === CFIType.branch).asUInt).orR
         val res = bht.get(io.req.bits.addr)
         when (io.bht_advance.valid) {
@@ Expand Down @@

src/main/scala/rocket/DCache.scala

-Original file line number
+Diff line change
@@ Expand Up / @@ -25,9 +25,7 @@ import freechips.rocketchip.util.SeqBoolBitwiseOps @@
     // TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits
     trait InlineInstance { self: chisel3.experimental.BaseModule =>
-      chisel3.experimental.annotate(
-        new chisel3.experimental.ChiselAnnotation {
-          def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } )
+      chisel3.experimental.annotate(self)(Seq(firrtl.passes.InlineAnnotation(self.toNamed)))
     }
     class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p)
@@ Expand Down @@

src/main/scala/rocket/Multiplier.scala

-Original file line number
+Diff line change
@@ Expand Up @@
       io.req.ready := state === s_ready
     }
-    class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed {
+    class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module {
       val io = IO(new Bundle {
         val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr))))
         val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr)))
@@ Expand Down @@

src/main/scala/rocket/RocketCore.scala

-Original file line number
+Diff line change
@@ Expand Up @@
         v_decode.io.vconfig := csr.io.vector.get.vconfig
         id_ctrl.vec := v_decode.io.vector
         when (v_decode.io.legal) {
-          id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill
+          id_ctrl.legal := true.B
           id_ctrl.fp := v_decode.io.fp
           id_ctrl.rocc := false.B
           id_ctrl.branch := false.B
@@ Expand Down Expand Up @@
         (id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') ||
         id_ctrl.amo && !csr.io.status.isa('a'-'a') ||
         id_ctrl.fp && (csr.io.decode(0).fp_illegal || (io.fpu.illegal_rm && !id_ctrl.vec)) ||
-        id_set_vconfig && csr.io.decode(0).vector_illegal ||
-        id_ctrl.vec && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) ||
+        (id_ctrl.vec || id_set_vconfig) && csr.io.decode(0).vector_illegal ||
         id_ctrl.dp && !csr.io.status.isa('d'-'a') ||
         ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||
         id_raddr2_illegal && id_ctrl.rxs2 ||
@@ Expand Down @@

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