diff --git a/.github/workflows/mill-ci.yml b/.github/workflows/mill-ci.yml
index a75ab0300fc..04a2c133b27 100644
--- a/.github/workflows/mill-ci.yml
+++ b/.github/workflows/mill-ci.yml
@@ -27,17 +27,17 @@ jobs:
       matrix:
         config: [DefaultConfig, DefaultBufferlessConfig, DefaultRV32Config, TinyConfig, DefaultFP16Config, DefaultBConfig, DefaultRV32BConfig]
     steps:
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v4
         with:
           submodules: 'true'
 
-      - uses: cachix/install-nix-action@v19
+      - uses: cachix/install-nix-action@v31
         with:
           install_url: https://releases.nixos.org/nix/nix-2.13.3/install
           nix_path: nixpkgs=channel:nixos-unstable
 
       - name: Coursier Cache
-        uses: coursier/cache-action@v5
+        uses: coursier/cache-action@v6
 
       - name: run riscv-tests
         run: |
@@ -50,17 +50,17 @@ jobs:
       matrix:
         config: [DefaultSmallConfig, DualBankConfig, DualChannelConfig, DualChannelDualBankConfig, RoccExampleConfig, Edge128BitConfig, Edge32BitConfig, QuadChannelBenchmarkConfig, EightChannelConfig, DualCoreConfig, MemPortOnlyConfig, MMIOPortOnlyConfig, CloneTileConfig, HypervisorConfig]
     steps:
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v4
         with:
           submodules: 'true'
 
-      - uses: cachix/install-nix-action@v19
+      - uses: cachix/install-nix-action@v31
         with:
           install_url: https://releases.nixos.org/nix/nix-2.13.3/install
           nix_path: nixpkgs=channel:nixos-unstable
 
       - name: Coursier Cache
-        uses: coursier/cache-action@v5
+        uses: coursier/cache-action@v6
 
       - name: compile emulator
         run: |
@@ -74,12 +74,12 @@ jobs:
       matrix:
         config: ["DefaultRV32Config,32,RV32IMACZicsr_Zifencei", "DefaultConfig,64,RV64IMACZicsr_Zifencei"]
     steps:
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v4
         with:
           submodules: 'true'
 
       - name: install nix
-        uses: cachix/install-nix-action@v19
+        uses: cachix/install-nix-action@v31
         with:
           install_url: https://releases.nixos.org/nix/nix-2.13.3/install
           nix_path: nixpkgs=channel:nixos-unstable
@@ -98,12 +98,12 @@ jobs:
       matrix:
         config: ["freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultConfig", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultRV32Config", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultConfig", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultRV32Config"]
     steps:
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v4
         with:
           submodules: 'true'
 
       - name: install nix
-        uses: cachix/install-nix-action@v19
+        uses: cachix/install-nix-action@v31
         with:
           install_url: https://releases.nixos.org/nix/nix-2.13.3/install
           nix_path: nixpkgs=channel:nixos-unstable
diff --git a/build.sc b/build.sc
index cf602b2a8ab..1f5142996a8 100644
--- a/build.sc
+++ b/build.sc
@@ -12,7 +12,7 @@ object v {
   val scala = "2.13.12"
   // the first version in this Map is the mainly supported version which will be used to run tests
   val chiselCrossVersions = Map(
-    "5.1.0" -> (ivy"org.chipsalliance::chisel:5.1.0", ivy"org.chipsalliance:::chisel-plugin:5.1.0"),
+    "6.7.0" -> (ivy"org.chipsalliance::chisel:6.7.0", ivy"org.chipsalliance:::chisel-plugin:6.7.0"),
     // build from project from source
     "source" -> (ivy"org.chipsalliance::chisel:99", ivy"org.chipsalliance:::chisel-plugin:99"),
   )
diff --git a/src/main/scala/amba/ahb/Nodes.scala b/src/main/scala/amba/ahb/Nodes.scala
index 33c33ccd213..a0b6318971f 100644
--- a/src/main/scala/amba/ahb/Nodes.scala
+++ b/src/main/scala/amba/ahb/Nodes.scala
@@ -22,7 +22,7 @@ object AHBImpSlave extends SimpleNodeImp[AHBMasterPortParameters, AHBSlavePortPa
   override def monitor(bundle: AHBSlaveBundle, edge: AHBEdgeParameters): Unit = {
     edge.params.lift(AHBSlaveMonitorBuilder).foreach { builder =>
       val monitor = Module(builder(AHBSlaveMonitorArgs(edge)))
-      monitor.io.in := bundle
+      monitor.io.in :#= bundle
     }
   }
 
@@ -44,7 +44,7 @@ object AHBImpMaster extends SimpleNodeImp[AHBMasterPortParameters, AHBSlavePortP
   override def monitor(bundle: AHBMasterBundle, edge: AHBEdgeParameters): Unit = {
     edge.params.lift(AHBMasterMonitorBuilder).foreach { builder =>
       val monitor = Module(builder(AHBMasterMonitorArgs(edge)))
-      monitor.io.in := bundle
+      monitor.io.in :#= bundle
     }
   }
 
diff --git a/src/main/scala/amba/ahb/Xbar.scala b/src/main/scala/amba/ahb/Xbar.scala
index d685ac1bed9..faabc25455d 100644
--- a/src/main/scala/amba/ahb/Xbar.scala
+++ b/src/main/scala/amba/ahb/Xbar.scala
@@ -21,7 +21,7 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule {
         requestKeys    = seq.flatMap(_.requestKeys).distinct,
         responseFields = BundleField.union(seq.flatMap(_.responseFields))) }
   ){
-    override def circuitIdentity = outputs == 1 && inputs == 1
+    override def circuitIdentity = outputs.size == 1 && inputs.size == 1
   }
 
   lazy val module = new Impl
diff --git a/src/main/scala/amba/apb/Nodes.scala b/src/main/scala/amba/apb/Nodes.scala
index e2dd9307c74..95dfccbbe61 100644
--- a/src/main/scala/amba/apb/Nodes.scala
+++ b/src/main/scala/amba/apb/Nodes.scala
@@ -21,7 +21,7 @@ object APBImp extends SimpleNodeImp[APBMasterPortParameters, APBSlavePortParamet
   override def monitor(bundle: APBBundle, edge: APBEdgeParameters): Unit = {
     edge.params.lift(APBMonitorBuilder).foreach { builder =>
       val monitor = Module(builder(APBMonitorArgs(edge)))
-      monitor.io.in := bundle
+      monitor.io.in :#= bundle
     }
   }
 
diff --git a/src/main/scala/amba/apb/Xbar.scala b/src/main/scala/amba/apb/Xbar.scala
index 3f50fbb4ea1..1a69f3192df 100644
--- a/src/main/scala/amba/apb/Xbar.scala
+++ b/src/main/scala/amba/apb/Xbar.scala
@@ -21,7 +21,7 @@ class APBFanout()(implicit p: Parameters) extends LazyModule {
         requestKeys    = seq.flatMap(_.requestKeys).distinct,
         responseFields = BundleField.union(seq.flatMap(_.responseFields))) }
   ){
-    override def circuitIdentity = outputs == 1 && inputs == 1
+    override def circuitIdentity = outputs.size == 1 && inputs.size == 1
   }
 
   lazy val module = new Impl
diff --git a/src/main/scala/amba/axi4/Buffer.scala b/src/main/scala/amba/axi4/Buffer.scala
index 2b768e87ca5..87f81989db7 100644
--- a/src/main/scala/amba/axi4/Buffer.scala
+++ b/src/main/scala/amba/axi4/Buffer.scala
@@ -68,4 +68,16 @@ object AXI4Buffer
     val axi4buf = LazyModule(new AXI4Buffer(aw, w, b, ar, r))
     axi4buf.node
   }
+
+  def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[AXI4Node] = {
+    val buffers = Seq.fill(depth) { LazyModule(new AXI4Buffer()) }
+    name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
+    buffers.map(_.node)
+  }
+
+  def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): AXI4Node = {
+    chain(depth, name)
+      .reduceLeftOption(_ :*=* _)
+      .getOrElse(AXI4NameNode("no_buffer"))
+  }
 }
diff --git a/src/main/scala/amba/axi4/Nodes.scala b/src/main/scala/amba/axi4/Nodes.scala
index da53aa92ea6..aa581cac082 100644
--- a/src/main/scala/amba/axi4/Nodes.scala
+++ b/src/main/scala/amba/axi4/Nodes.scala
@@ -23,7 +23,7 @@ object AXI4Imp extends SimpleNodeImp[AXI4MasterPortParameters, AXI4SlavePortPara
   override def monitor(bundle: AXI4Bundle, edge: AXI4EdgeParameters): Unit = {
     edge.params.lift(AXI4MonitorBuilder).foreach { builder =>
       val monitor = Module(builder(AXI4MonitorArgs(edge)))
-      monitor.io.in := bundle
+      monitor.io.in :#= bundle
     }
   }
 
diff --git a/src/main/scala/amba/axi4/SRAM.scala b/src/main/scala/amba/axi4/SRAM.scala
index f4838b73ab0..d5afbe6e2d9 100644
--- a/src/main/scala/amba/axi4/SRAM.scala
+++ b/src/main/scala/amba/axi4/SRAM.scala
@@ -75,8 +75,8 @@ class AXI4RAM(
     val w_full = RegInit(false.B)
     val w_id   = Reg(UInt())
     val w_echo = Reg(BundleMap(in.params.echoFields))
-    val r_sel1 = RegNext(r_sel0)
-    val w_sel1 = RegNext(w_sel0)
+    val r_sel1 = Reg(Bool())
+    val w_sel1 = Reg(Bool())
 
     when (in. b.fire) { w_full := false.B }
     when (in.aw.fire) { w_full := true.B }
diff --git a/src/main/scala/amba/axi4/Xbar.scala b/src/main/scala/amba/axi4/Xbar.scala
index 291e92acdbe..04b98a878d5 100644
--- a/src/main/scala/amba/axi4/Xbar.scala
+++ b/src/main/scala/amba/axi4/Xbar.scala
@@ -53,7 +53,7 @@ class AXI4Xbar(
       )
     }
   ){
-    override def circuitIdentity = outputs == 1 && inputs == 1
+    override def circuitIdentity = outputs.size == 1 && inputs.size == 1
   }
 
   lazy val module = new Impl
diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala
index 7c6716b0e2d..a3a1fb6abe8 100755
--- a/src/main/scala/devices/debug/Debug.scala
+++ b/src/main/scala/devices/debug/Debug.scala
@@ -19,7 +19,7 @@ import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDes
 import freechips.rocketchip.rocket.{CSRs, Instructions}
 import freechips.rocketchip.tile.MaxHartIdBits
 import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar}
-import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle}
+import freechips.rocketchip.util.{AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle}
 
 import freechips.rocketchip.util.SeqBoolBitwiseOps
 import freechips.rocketchip.util.SeqToAugmentedSeq
@@ -789,7 +789,6 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this){
     val nComponents = getNComponents()
-    Annotated.params(this, cfg)
     val supportHartArray = cfg.supportHartArray & (nComponents > 1)
     val nExtTriggers = cfg.nExtTriggers
     val nHaltGroups = if ((nComponents > 1) | (nExtTriggers > 0)) cfg.nHaltGroups
diff --git a/src/main/scala/devices/tilelink/BootROM.scala b/src/main/scala/devices/tilelink/BootROM.scala
index 7cbfcca6df8..d4fcda2b136 100644
--- a/src/main/scala/devices/tilelink/BootROM.scala
+++ b/src/main/scala/devices/tilelink/BootROM.scala
@@ -13,6 +13,7 @@ import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
 import freechips.rocketchip.resources.{Resource, SimpleDevice}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters}
+import freechips.rocketchip.util.{FileName, SystemFileName, ResourceFileName}
 
 import java.nio.ByteBuffer
 import java.nio.file.{Files, Paths}
@@ -22,7 +23,11 @@ case class BootROMParams(
   address: BigInt = 0x10000,
   size: Int = 0x10000,
   hang: BigInt = 0x10040, // The hang parameter is used as the power-on reset vector
-  contentFileName: String)
+  driveResetVector: Boolean = true,
+  appendDTB: Boolean = true,
+  name: String = "bootrom",
+  contentFileName: FileName = SystemFileName("./bootrom/bootrom.img")
+)
 
 class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
   resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule
@@ -63,7 +68,7 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec
   }
 }
 
-case class BootROMLocated(loc: HierarchicalLocation) extends Field[Option[BootROMParams]](None)
+case class BootROMLocated(loc: HierarchicalLocation) extends Field[Seq[BootROMParams]](Nil)
 
 object BootROM {
   /** BootROM.attach not only instantiates a TLROM and attaches it to the tilelink interconnect
@@ -73,27 +78,40 @@ object BootROM {
   def attach(params: BootROMParams, subsystem: BaseSubsystem with HasHierarchicalElements with HasTileInputConstants, where: TLBusWrapperLocation)
             (implicit p: Parameters): TLROM = {
     val tlbus = subsystem.locateTLBusWrapper(where)
-    val bootROMDomainWrapper = tlbus.generateSynchronousDomain("BootROM").suggestName("bootrom_domain")
+    val bootROMDomainWrapper = tlbus.generateSynchronousDomain(params.name).suggestName(s"${params.name}_domain")
 
     val bootROMResetVectorSourceNode = BundleBridgeSource[UInt]()
-    lazy val contents = {
-      val romdata = Files.readAllBytes(Paths.get(params.contentFileName))
-      val rom = ByteBuffer.wrap(romdata)
-      rom.array() ++ subsystem.dtb.contents
+    val rom = params.contentFileName match {
+      case SystemFileName(fileName) => {
+        val romdata = Files.readAllBytes(Paths.get(fileName))
+        ByteBuffer.wrap(romdata).array()
+      }
+      case ResourceFileName(fileName) => {
+        val file = os.resource / os.RelPath(fileName.dropWhile(_ == '/'))
+        os.read.bytes(file)
+      }
+    }
+
+    lazy val contents = if (params.appendDTB) {
+      rom ++ subsystem.dtb.contents
+    } else {
+      rom
     }
 
     val bootrom = bootROMDomainWrapper {
       LazyModule(new TLROM(params.address, params.size, contents, true, tlbus.beatBytes))
     }
 
-    bootrom.node := tlbus.coupleTo("bootrom"){ TLFragmenter(tlbus, Some("BootROM")) := _ }
+    bootrom.node := tlbus.coupleTo(params.name){ TLFragmenter(tlbus, Some(params.name)) := _ }
     // Drive the `subsystem` reset vector to the `hang` address of this Boot ROM.
-    subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode
-    InModuleBody {
-      val reset_vector_source = bootROMResetVectorSourceNode.bundle
-      require(reset_vector_source.getWidth >= params.hang.bitLength,
-        s"BootROM defined with a reset vector (${params.hang})too large for physical address space (${reset_vector_source.getWidth})")
-      bootROMResetVectorSourceNode.bundle := params.hang.U
+    if (params.driveResetVector) {
+      subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode
+      InModuleBody {
+        val reset_vector_source = bootROMResetVectorSourceNode.bundle
+        require(reset_vector_source.getWidth >= params.hang.bitLength,
+          s"BootROM defined with a reset vector (${params.hang})too large for physical address space (${reset_vector_source.getWidth})")
+        bootROMResetVectorSourceNode.bundle := params.hang.U
+      }
     }
     bootrom
   }
diff --git a/src/main/scala/devices/tilelink/CLINT.scala b/src/main/scala/devices/tilelink/CLINT.scala
index 81c7051ae46..9d765ce1d86 100644
--- a/src/main/scala/devices/tilelink/CLINT.scala
+++ b/src/main/scala/devices/tilelink/CLINT.scala
@@ -14,7 +14,6 @@ import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSink
 import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
 import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
 import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
-import freechips.rocketchip.util.Annotated
 
 object CLINTConsts
 {
@@ -63,7 +62,6 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends
 
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) {
-    Annotated.params(this, params)
     require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them")
 
     val io = IO(new Bundle {
diff --git a/src/main/scala/devices/tilelink/Plic.scala b/src/main/scala/devices/tilelink/Plic.scala
index 75cf30edf4b..ba849241757 100644
--- a/src/main/scala/devices/tilelink/Plic.scala
+++ b/src/main/scala/devices/tilelink/Plic.scala
@@ -15,7 +15,7 @@ import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSink
 import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn}
 import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
 import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
-import freechips.rocketchip.util.{Annotated, MuxT, property}
+import freechips.rocketchip.util.{MuxT, property}
 
 import scala.math.min
 
@@ -130,8 +130,6 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
 
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) {
-    Annotated.params(this, params)
-
     val (io_devices, edgesIn) = intnode.in.unzip
     val (io_harts, _) = intnode.out.unzip
 
diff --git a/src/main/scala/interrupts/Xbar.scala b/src/main/scala/interrupts/Xbar.scala
index 65c3e045ac4..1f227aa2e47 100644
--- a/src/main/scala/interrupts/Xbar.scala
+++ b/src/main/scala/interrupts/Xbar.scala
@@ -15,7 +15,7 @@ class IntXbar()(implicit p: Parameters) extends LazyModule
       }.flatten)
     })
   {
-    override def circuitIdentity = outputs == 1 && inputs == 1
+    override def circuitIdentity = outputs.size == 1 && inputs.size == 1
   }
 
   lazy val module = new Impl
@@ -36,7 +36,7 @@ class IntSyncXbar()(implicit p: Parameters) extends LazyModule
       }.flatten)
     })
   {
-    override def circuitIdentity = outputs == 1 && inputs == 1
+    override def circuitIdentity = outputs.size == 1 && inputs.size == 1
   }
 
   lazy val module = new Impl
diff --git a/src/main/scala/rocket/BTB.scala b/src/main/scala/rocket/BTB.scala
index 75126dd121b..cb8392a7c29 100644
--- a/src/main/scala/rocket/BTB.scala
+++ b/src/main/scala/rocket/BTB.scala
@@ -32,9 +32,7 @@ trait HasBtbParameters extends HasCoreParameters { this: InstanceId =>
   val nPages = (btbParams.nPages + 1) / 2 * 2 // control logic assumes 2 divides pages
 }
 
-abstract class BtbModule(implicit val p: Parameters) extends Module with HasBtbParameters {
-  Annotated.params(this, btbParams)
-}
+abstract class BtbModule(implicit val p: Parameters) extends Module with HasBtbParameters
 
 abstract class BtbBundle(implicit val p: Parameters) extends Bundle with HasBtbParameters
 
@@ -301,7 +299,7 @@ class BTB(implicit p: Parameters) extends BtbModule {
   }
 
   if (btbParams.bhtParams.nonEmpty) {
-    val bht = new BHT(Annotated.params(this, btbParams.bhtParams.get))
+    val bht = new BHT(btbParams.bhtParams.get)
     val isBranch = (idxHit & cfiType.map(_ === CFIType.branch).asUInt).orR
     val res = bht.get(io.req.bits.addr)
     when (io.bht_advance.valid) {
diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala
index edbd7328277..4e456d785c4 100644
--- a/src/main/scala/rocket/DCache.scala
+++ b/src/main/scala/rocket/DCache.scala
@@ -25,9 +25,7 @@ import freechips.rocketchip.util.SeqBoolBitwiseOps
 
 // TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits
 trait InlineInstance { self: chisel3.experimental.BaseModule =>
-  chisel3.experimental.annotate(
-    new chisel3.experimental.ChiselAnnotation {
-      def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } )
+  chisel3.experimental.annotate(self)(Seq(firrtl.passes.InlineAnnotation(self.toNamed)))
 }
 
 class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p)
diff --git a/src/main/scala/rocket/Multiplier.scala b/src/main/scala/rocket/Multiplier.scala
index 081dd0c841f..a4882bd1ae4 100644
--- a/src/main/scala/rocket/Multiplier.scala
+++ b/src/main/scala/rocket/Multiplier.scala
@@ -183,7 +183,7 @@ class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module {
   io.req.ready := state === s_ready
 }
 
-class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed {
+class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module {
   val io = IO(new Bundle {
     val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr))))
     val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr)))
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
index cc5ab6fccda..ec6d82cdf29 100644
--- a/src/main/scala/rocket/RocketCore.scala
+++ b/src/main/scala/rocket/RocketCore.scala
@@ -359,7 +359,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
     v_decode.io.vconfig := csr.io.vector.get.vconfig
     id_ctrl.vec := v_decode.io.vector
     when (v_decode.io.legal) {
-      id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill
+      id_ctrl.legal := true.B
       id_ctrl.fp := v_decode.io.fp
       id_ctrl.rocc := false.B
       id_ctrl.branch := false.B
@@ -389,8 +389,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
     (id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') ||
     id_ctrl.amo && !csr.io.status.isa('a'-'a') ||
     id_ctrl.fp && (csr.io.decode(0).fp_illegal || (io.fpu.illegal_rm && !id_ctrl.vec)) ||
-    id_set_vconfig && csr.io.decode(0).vector_illegal ||
-    id_ctrl.vec && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) ||
+    (id_ctrl.vec || id_set_vconfig) && csr.io.decode(0).vector_illegal ||
     id_ctrl.dp && !csr.io.status.isa('d'-'a') ||
     ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||
     id_raddr2_illegal && id_ctrl.rxs2 ||
diff --git a/src/main/scala/subsystem/BaseSubsystem.scala b/src/main/scala/subsystem/BaseSubsystem.scala
index e5aaa6242aa..c9436dfe390 100644
--- a/src/main/scala/subsystem/BaseSubsystem.scala
+++ b/src/main/scala/subsystem/BaseSubsystem.scala
@@ -15,7 +15,7 @@ import freechips.rocketchip.resources.{
   ResourceAnchors, AddressMapEntry}
 import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockGroupAggregator, ClockGroupSourceNode, ClockGroupSourceParameters}
 import freechips.rocketchip.tilelink.TLBusWrapper
-import freechips.rocketchip.util.{Location, ElaborationArtefacts, PlusArgArtefacts, RecordMap, Annotated}
+import freechips.rocketchip.util.{Location, ElaborationArtefacts, PlusArgArtefacts, RecordMap}
 
 case object SubsystemDriveClockGroupsFromIO extends Field[Boolean](true)
 case class TLNetworkTopologyLocated(where: HierarchicalLocation) extends Field[Seq[CanInstantiateWithinContextThatHasTileLinkLocations with CanConnectWithinContextThatHasTileLinkLocations]]
@@ -142,13 +142,11 @@ abstract class BaseSubsystem(val location: HierarchicalLocation = InSubsystem)
 
 abstract class BaseSubsystemModuleImp[+L <: BaseSubsystem](_outer: L) extends BareSubsystemModuleImp(_outer) with HasDTSImp[L] {
   def dtsLM: L = _outer
-  private val mapping: Seq[AddressMapEntry] = Annotated.addressMapping(this, {
+  private val mapping: Seq[AddressMapEntry] = {
     dtsLM.collectResourceAddresses.groupBy(_._2).toList.flatMap { case (key, seq) =>
       AddressRange.fromSets(key.address).map { r => AddressMapEntry(r, key.permissions, seq.map(_._1)) }
     }.sortBy(_.range)
-  })
-
-  Annotated.addressMapping(this, mapping)
+  }
 
   println("Generated Address Map")
   mapping.foreach(entry => println(entry.toString((dtsLM.tlBusWrapperLocationMap(p(TLManagerViewpointLocated(dtsLM.location))).busView.bundle.addressBits-1)/4 + 1)))
diff --git a/src/main/scala/subsystem/Cluster.scala b/src/main/scala/subsystem/Cluster.scala
index f4419fa9efd..a1dc1cef3da 100644
--- a/src/main/scala/subsystem/Cluster.scala
+++ b/src/main/scala/subsystem/Cluster.scala
@@ -19,10 +19,20 @@ import scala.collection.immutable.SortedMap
 
 case class ClustersLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachCluster]](Nil)
 
+trait BaseClusterParams extends HierarchicalElementParams {
+  val clusterId: Int
+}
+
+abstract class InstantiableClusterParams[ClusterType <: Cluster]
+    extends HierarchicalElementParams
+    with BaseClusterParams {
+  def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByClusterIdImpl)(implicit p: Parameters): ClusterType
+}
+
 case class ClusterParams(
   val clusterId: Int,
   val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
-) extends HierarchicalElementParams {
+) extends InstantiableClusterParams[Cluster] {
   val baseName = "cluster"
   val uniqueName = s"${baseName}_$clusterId"
   def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByClusterIdImpl)(implicit p: Parameters): Cluster = {
@@ -31,7 +41,7 @@ case class ClusterParams(
 }
 
 class Cluster(
-  val thisClusterParams: ClusterParams,
+  val thisClusterParams: BaseClusterParams,
   crossing: ClockCrossingType,
   lookup: LookupByClusterIdImpl)(implicit p: Parameters) extends BaseHierarchicalElement(crossing)(p)
     with Attachable
@@ -55,8 +65,6 @@ class Cluster(
   val slaveNode = ccbus.inwardNode
   val masterNode = cmbus.outwardNode
 
-
-
   lazy val ibus = LazyModule(new InterruptBusWrapper)
   ibus.clockNode := csbus.fixedClockNode
 
@@ -64,9 +72,10 @@ class Cluster(
   def meipDomain = this
   def seipDomain = this
   def toPlicDomain = this
+  def hasSupervisorTileIdList: Seq[Int] = totalTiles.filter(_._2.tileParams.core.hasSupervisorMode).keys.toSeq.sorted
   lazy val msipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(SortedMap)
   lazy val meipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(SortedMap)
-  lazy val seipNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(SortedMap)
+  lazy val seipNodes = hasSupervisorTileIdList.map { i => (i, IntIdentityNode()) }.to(SortedMap)
   lazy val tileToPlicNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(SortedMap)
   lazy val debugNodes = totalTileIdList.map { i => (i, IntSyncIdentityNode()) }.to(SortedMap)
   lazy val nmiNodes = totalTiles.filter { case (i,t) => t.tileParams.core.useNMI }
@@ -79,7 +88,7 @@ class Cluster(
   // TODO fix: shouldn't need to connect dummy notifications
   tileHaltXbarNode := NullIntSource()
   tileWFIXbarNode := NullIntSource()
-  tileCeaseXbarNode := NullIntSource()
+  // tileCeaseXbarNode := NullIntSource()
 
   override lazy val module = new ClusterModuleImp(this)
 }
@@ -88,12 +97,12 @@ class ClusterModuleImp(outer: Cluster) extends BaseHierarchicalElementModuleImp[
 
 case class InCluster(id: Int) extends HierarchicalLocation(s"Cluster$id")
 
-class ClusterPRCIDomain(
+abstract class ClusterPRCIDomain[ClusterType <: Cluster](
   clockSinkParams: ClockSinkParameters,
   crossingParams: HierarchicalElementCrossingParamsLike,
-  clusterParams: ClusterParams,
+  clusterParams: InstantiableClusterParams[ClusterType],
   lookup: LookupByClusterIdImpl)
-  (implicit p: Parameters) extends HierarchicalElementPRCIDomain[Cluster](clockSinkParams, crossingParams)
+  (implicit p: Parameters) extends HierarchicalElementPRCIDomain[ClusterType](clockSinkParams, crossingParams)
 {
   val element = element_reset_domain {
     LazyModule(clusterParams.instantiate(crossingParams, lookup))
@@ -104,19 +113,19 @@ class ClusterPRCIDomain(
 
 
 trait CanAttachCluster {
+  type ClusterType <: Cluster
   type ClusterContextType <: DefaultHierarchicalElementContextType
-
-  def clusterParams: ClusterParams
+  def clusterParams: InstantiableClusterParams[ClusterType]
   def crossingParams: HierarchicalElementCrossingParamsLike
 
-  def instantiate(allClusterParams: Seq[ClusterParams], instantiatedClusters: SortedMap[Int, ClusterPRCIDomain])(implicit p: Parameters): ClusterPRCIDomain = {
+  def instantiate(allClusterParams: Seq[BaseClusterParams], instantiatedClusters: SortedMap[Int, ClusterPRCIDomain[_]])(implicit p: Parameters): ClusterPRCIDomain[ClusterType] = {
     val clockSinkParams = clusterParams.clockSinkParams.copy(name = Some(clusterParams.uniqueName))
-    val cluster_prci_domain = LazyModule(new ClusterPRCIDomain(
-      clockSinkParams, crossingParams, clusterParams, PriorityMuxClusterIdFromSeq(allClusterParams)))
+    val cluster_prci_domain = LazyModule(new ClusterPRCIDomain[ClusterType](
+      clockSinkParams, crossingParams, clusterParams, PriorityMuxClusterIdFromSeq(allClusterParams)) {})
     cluster_prci_domain
   }
 
-  def connect(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = {
+  def connect(domain: ClusterPRCIDomain[ClusterType], context: ClusterContextType): Unit = {
     connectMasterPorts(domain, context)
     connectSlavePorts(domain, context)
     connectInterrupts(domain, context)
@@ -126,21 +135,21 @@ trait CanAttachCluster {
     connectTrace(domain, context)
   }
 
-  def connectMasterPorts(domain: ClusterPRCIDomain, context: Attachable): Unit = {
+  def connectMasterPorts(domain: ClusterPRCIDomain[ClusterType], context: Attachable): Unit = {
     implicit val p = context.p
     val dataBus = context.locateTLBusWrapper(crossingParams.master.where)
     dataBus.coupleFrom(clusterParams.baseName) { bus =>
       bus :=* crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType)
     }
   }
-  def connectSlavePorts(domain: ClusterPRCIDomain, context: Attachable): Unit = {
+  def connectSlavePorts(domain: ClusterPRCIDomain[ClusterType], context: Attachable): Unit = {
     implicit val p = context.p
     val controlBus = context.locateTLBusWrapper(crossingParams.slave.where)
     controlBus.coupleTo(clusterParams.baseName) { bus =>
       domain.crossSlavePort(crossingParams.crossingType) :*= crossingParams.slave.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus
     }
   }
-  def connectInterrupts(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = {
+  def connectInterrupts(domain: ClusterPRCIDomain[ClusterType], context: ClusterContextType): Unit = {
     implicit val p = context.p
 
     domain.element.debugNodes.foreach { case (hartid, node) =>
@@ -170,7 +179,7 @@ trait CanAttachCluster {
     }
   }
 
-  def connectPRC(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = {
+  def connectPRC(domain: ClusterPRCIDomain[ClusterType], context: ClusterContextType): Unit = {
     implicit val p = context.p
     domain.element.allClockGroupsNode :*= context.allClockGroupsNode
     domain {
@@ -178,7 +187,7 @@ trait CanAttachCluster {
     }
   }
 
-  def connectOutputNotifications(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = {
+  def connectOutputNotifications(domain: ClusterPRCIDomain[ClusterType], context: ClusterContextType): Unit = {
     implicit val p = context.p
     context.tileHaltXbarNode  :=* domain.crossIntOut(NoCrossing, domain.element.tileHaltXbarNode)
     context.tileWFIXbarNode   :=* domain.crossIntOut(NoCrossing, domain.element.tileWFIXbarNode)
@@ -186,7 +195,7 @@ trait CanAttachCluster {
 
   }
 
-  def connectInputConstants(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = {
+  def connectInputConstants(domain: ClusterPRCIDomain[ClusterType], context: ClusterContextType): Unit = {
     implicit val p = context.p
     val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere)
     domain.element.tileHartIdNodes.foreach { case (hartid, node) =>
@@ -197,7 +206,7 @@ trait CanAttachCluster {
     }
   }
 
-  def connectTrace(domain: ClusterPRCIDomain, context: ClusterContextType): Unit = {
+  def connectTrace(domain: ClusterPRCIDomain[ClusterType], context: ClusterContextType): Unit = {
     implicit val p = context.p
     domain.element.traceNodes.foreach { case (hartid, node) =>
       val traceNexusNode = BundleBridgeBlockDuringReset[TraceBundle](
@@ -212,23 +221,26 @@ trait CanAttachCluster {
   }
 }
 
-case class ClusterAttachParams(
+case class ClusterAttachParams (
   clusterParams: ClusterParams,
   crossingParams: HierarchicalElementCrossingParamsLike
-) extends CanAttachCluster
+) extends CanAttachCluster {
+  type ClusterType = Cluster
+}
 
 case class CloneClusterAttachParams(
   sourceClusterId: Int,
   cloneParams: CanAttachCluster
 ) extends CanAttachCluster {
+  type ClusterType = cloneParams.ClusterType
   def clusterParams = cloneParams.clusterParams
   def crossingParams = cloneParams.crossingParams
 
-  override def instantiate(allClusterParams: Seq[ClusterParams], instantiatedClusters: SortedMap[Int, ClusterPRCIDomain])(implicit p: Parameters): ClusterPRCIDomain = {
+  override def instantiate(allClusterParams: Seq[BaseClusterParams], instantiatedClusters: SortedMap[Int, ClusterPRCIDomain[_]])(implicit p: Parameters): ClusterPRCIDomain[ClusterType] = {
     require(instantiatedClusters.contains(sourceClusterId))
     val clockSinkParams = clusterParams.clockSinkParams.copy(name = Some(clusterParams.uniqueName))
     val cluster_prci_domain = CloneLazyModule(
-      new ClusterPRCIDomain(clockSinkParams, crossingParams, clusterParams, PriorityMuxClusterIdFromSeq(allClusterParams)),
+      new ClusterPRCIDomain[ClusterType](clockSinkParams, crossingParams, clusterParams, PriorityMuxClusterIdFromSeq(allClusterParams)) {},
       instantiatedClusters(sourceClusterId)
     )
     cluster_prci_domain
diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
index 37001b39fd3..6d269192351 100644
--- a/src/main/scala/subsystem/Configs.scala
+++ b/src/main/scala/subsystem/Configs.scala
@@ -1,3 +1,4 @@
+
 // See LICENSE.SiFive for license details.
 // See LICENSE.Berkeley for license details.
 
@@ -22,7 +23,7 @@ import freechips.rocketchip.resources.{
 import freechips.rocketchip.tile.{
   MaxHartIdBits, RocketTileParams, BuildRoCC, AccumulatorExample, OpcodeSet, TranslatorExample, CharacterCountExample, BlackBoxExample
 }
-import freechips.rocketchip.util.ClockGateModelFile
+import freechips.rocketchip.util.{ClockGateModelFile, SystemFileName}
 import scala.reflect.ClassTag
 
 case object MaxXLen extends Field[Int]
@@ -54,7 +55,7 @@ class BaseSubsystemConfig extends Config ((site, here, up) => {
     beatBytes = 8,
     blockBytes = site(CacheBlockBytes))
   // Additional device Parameters
-  case BootROMLocated(InSubsystem) => Some(BootROMParams(contentFileName = "./bootrom/bootrom.img"))
+  case BootROMLocated(InSubsystem) => Seq(BootROMParams(contentFileName = SystemFileName("./bootrom/bootrom.img")))
   case HasTilesExternalResetVectorKey => false
   case DebugModuleKey => Some(DefaultDebugModuleParams(64))
   case CLINTKey => Some(CLINTParams())
@@ -207,7 +208,7 @@ class WithIncoherentTiles extends Config((site, here, up) => {
 })
 
 class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
-  case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = bootROMFile))
+  case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName=SystemFileName(bootROMFile)))
 })
 
 class WithClockGateModel(file: String = "/vsrc/EICG_wrapper.v") extends Config((site, here, up) => {
diff --git a/src/main/scala/subsystem/HasHierarchicalElements.scala b/src/main/scala/subsystem/HasHierarchicalElements.scala
index 56659d2d301..c7078f53975 100644
--- a/src/main/scala/subsystem/HasHierarchicalElements.scala
+++ b/src/main/scala/subsystem/HasHierarchicalElements.scala
@@ -92,16 +92,16 @@ trait InstantiatesHierarchicalElements { this: LazyModule with Attachable =>
   }
 
   val clusterAttachParams: Seq[CanAttachCluster] = p(ClustersLocated(location)).sortBy(_.clusterParams.clusterId)
-  val clusterParams: Seq[ClusterParams] = clusterAttachParams.map(_.clusterParams)
+  val clusterParams: Seq[BaseClusterParams] = clusterAttachParams.map(_.clusterParams)
   val clusterCrossingTypes: Seq[ClockCrossingType] = clusterAttachParams.map(_.crossingParams.crossingType)
-  val cluster_prci_domains: SortedMap[Int, ClusterPRCIDomain] = clusterAttachParams.foldLeft(SortedMap[Int, ClusterPRCIDomain]()) {
+  val cluster_prci_domains: SortedMap[Int, ClusterPRCIDomain[_]] = clusterAttachParams.foldLeft(SortedMap[Int, ClusterPRCIDomain[_]]()) {
     case (instantiated, params) => instantiated + (params.clusterParams.clusterId -> params.instantiate(clusterParams, instantiated)(p))
   }
 
   val element_prci_domains: Seq[HierarchicalElementPRCIDomain[_]] = tile_prci_domains.values.toSeq ++ cluster_prci_domains.values.toSeq
 
   val leafTiles: SortedMap[Int, BaseTile] = SortedMap(tile_prci_domains.mapValues(_.element.asInstanceOf[BaseTile]).toSeq.sortBy(_._1):_*)
-  val totalTiles: SortedMap[Int, BaseTile] = (leafTiles ++ cluster_prci_domains.values.map(_.element.totalTiles).flatten)
+  val totalTiles: SortedMap[Int, BaseTile] = (leafTiles ++ cluster_prci_domains.values.map(_.element.asInstanceOf[Cluster].totalTiles).flatten)
 
   // Helper functions for accessing certain parameters that are popular to refer to in subsystem code
   def nLeafTiles: Int = leafTiles.size
@@ -123,7 +123,7 @@ trait HasHierarchicalElements extends DefaultHierarchicalElementContextType
     params.connect(tile_prci_domains(params.tileParams.tileId).asInstanceOf[TilePRCIDomain[params.TileType]], this.asInstanceOf[params.TileContextType])
   }
   clusterAttachParams.foreach { params =>
-    params.connect(cluster_prci_domains(params.clusterParams.clusterId).asInstanceOf[ClusterPRCIDomain], this.asInstanceOf[params.ClusterContextType])
+    params.connect(cluster_prci_domains(params.clusterParams.clusterId).asInstanceOf[ClusterPRCIDomain[params.ClusterType]], this.asInstanceOf[params.ClusterContextType])
   }
 }
 
diff --git a/src/main/scala/subsystem/LookupByClusterId.scala b/src/main/scala/subsystem/LookupByClusterId.scala
index d0c5c21a5ab..7bf4ec7d9b2 100644
--- a/src/main/scala/subsystem/LookupByClusterId.scala
+++ b/src/main/scala/subsystem/LookupByClusterId.scala
@@ -6,14 +6,14 @@ import chisel3._
 import chisel3.util._
 
 abstract class LookupByClusterIdImpl {
-  def apply[T <: Data](f: ClusterParams => Option[T], clusterId: UInt): T
+  def apply[T <: Data](f: BaseClusterParams => Option[T], clusterId: UInt): T
 }
 
-case class ClustersWontDeduplicate(t: ClusterParams) extends LookupByClusterIdImpl {
-  def apply[T <: Data](f: ClusterParams => Option[T], clusterId: UInt): T = f(t).get
+case class ClustersWontDeduplicate(t: BaseClusterParams) extends LookupByClusterIdImpl {
+  def apply[T <: Data](f: BaseClusterParams => Option[T], clusterId: UInt): T = f(t).get
 }
 
-case class PriorityMuxClusterIdFromSeq(seq: Seq[ClusterParams]) extends LookupByClusterIdImpl {
-  def apply[T <: Data](f: ClusterParams => Option[T], clusterId: UInt): T =
+case class PriorityMuxClusterIdFromSeq(seq: Seq[BaseClusterParams]) extends LookupByClusterIdImpl {
+  def apply[T <: Data](f: BaseClusterParams => Option[T], clusterId: UInt): T =
     PriorityMux(seq.collect { case t if f(t).isDefined => (t.clusterId.U === clusterId) -> f(t).get })
 }
diff --git a/src/main/scala/subsystem/Ports.scala b/src/main/scala/subsystem/Ports.scala
index d3ed70c5e98..7a9fda1ca84 100644
--- a/src/main/scala/subsystem/Ports.scala
+++ b/src/main/scala/subsystem/Ports.scala
@@ -105,8 +105,9 @@ trait CanHaveMasterAXI4MemPort { this: BaseSubsystem =>
     })
 
     mbus.coupleTo(s"memory_controller_port_named_$portName") {
-      (memAXI4Node
-        := AXI4UserYanker()
+      // Disable monitors on this connection since the class with this trait (i.e. DigitalTop) doesn't provide an
+      // implicit clock for the monitor.
+      (DisableMonitors { implicit p => memAXI4Node := AXI4UserYanker() }
         := AXI4IdIndexer(idBits)
         := TLToAXI4()
         := TLWidthWidget(mbus.beatBytes)
diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala
index e0fa46793b6..5fdb35c1462 100644
--- a/src/main/scala/tile/FPU.scala
+++ b/src/main/scala/tile/FPU.scala
@@ -450,7 +450,7 @@ trait HasFPUParameters {
 
 abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
 
-class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
+class FPToInt(implicit p: Parameters) extends FPUModule()(p) {
   class Output extends Bundle {
     val in = new FPInput
     val lt = Bool()
@@ -525,7 +525,7 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetime
   io.out.bits.in := in
 }
 
-class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
+class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
   val io = IO(new Bundle {
     val in = Flipped(Valid(new IntToFPInput))
     val out = Valid(new FPResult)
@@ -570,7 +570,7 @@ class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) w
   io.out <> Pipe(in.valid, mux, latency-1)
 }
 
-class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
+class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
   val io = IO(new Bundle {
     val in = Flipped(Valid(new FPInput))
     val out = Valid(new FPResult)
@@ -695,7 +695,7 @@ class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
 }
 
 class FPUFMAPipe(val latency: Int, val t: FType)
-                (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
+                (implicit p: Parameters) extends FPUModule()(p) {
   override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
   require(latency>0)
 
diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index 4ec2211358b..be709854f38 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -24,7 +24,7 @@ import freechips.rocketchip.rocket.{
 }
 import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike
 import freechips.rocketchip.prci.{ClockSinkParameters, RationalCrossing, ClockCrossingType}
-import freechips.rocketchip.util.{Annotated, InOrderArbiter}
+import freechips.rocketchip.util.InOrderArbiter
 import freechips.rocketchip.trace.{TraceEncoderParams,TraceEncoderController, TraceSinkArbiter}
 import freechips.rocketchip.subsystem._
 
@@ -166,8 +166,6 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
     with HasFpuOpt
     with HasLazyRoCCModule
     with HasICacheFrontendModule {
-  Annotated.params(this, outer.rocketParams)
-
   val core = Module(new Rocket(outer)(outer.p))
   outer.vector_unit.foreach { v =>
     core.io.vector.get <> v.module.io.core
diff --git a/src/main/scala/tilelink/Nodes.scala b/src/main/scala/tilelink/Nodes.scala
index 6b193f8ec0b..519c9bd1e7b 100644
--- a/src/main/scala/tilelink/Nodes.scala
+++ b/src/main/scala/tilelink/Nodes.scala
@@ -25,7 +25,7 @@ object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEd
 
   override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
     val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
-    monitor.io.in := bundle
+    monitor.io.in :#= bundle
   }
 
   override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters  =
diff --git a/src/main/scala/tilelink/RegisterRouter.scala b/src/main/scala/tilelink/RegisterRouter.scala
index f66a018bf23..8a133d2b721 100644
--- a/src/main/scala/tilelink/RegisterRouter.scala
+++ b/src/main/scala/tilelink/RegisterRouter.scala
@@ -123,13 +123,6 @@ case class TLRegisterNode(
       suffix = suffix + 1
     }
     ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
-
-    val module = Module.currentModule.get.asInstanceOf[RawModule]
-    GenRegDescsAnno.anno(
-      module,
-      base,
-      mapping:_*)
-
   }
 }
 
diff --git a/src/main/scala/trace/TraceEncoderController.scala b/src/main/scala/trace/TraceEncoderController.scala
index 2d94bf696a5..6a5c2bc7b62 100644
--- a/src/main/scala/trace/TraceEncoderController.scala
+++ b/src/main/scala/trace/TraceEncoderController.scala
@@ -19,8 +19,7 @@ object TraceSinkTarget {
 class TraceEncoderControlInterface() extends Bundle {
   val enable = Bool()
   val target = UInt(TraceSinkTarget.width.W)
-  val hpmcounter_enable = UInt(32.W)
-  val hpmcounter_report_interval = UInt(32.W)
+  val bp_mode = UInt(32.W)
 }
 class TraceEncoderController(addr: BigInt, beatBytes: Int)(implicit p: Parameters) extends LazyModule {
 
@@ -48,11 +47,8 @@ class TraceEncoderController(addr: BigInt, beatBytes: Int)(implicit p: Parameter
     val trace_sink_target = RegInit(0.U(TraceSinkTarget.width.W))
     io.control.target := trace_sink_target.asUInt
 
-    val trace_hpmcounter_enable = RegInit(0.U(32.W))
-    io.control.hpmcounter_enable := trace_hpmcounter_enable
-
-    val trace_hpmcounter_report_interval = RegInit(0.U(32.W))
-    io.control.hpmcounter_report_interval := trace_hpmcounter_report_interval
+    val trace_bp_mode = RegInit(0.U(32.W))
+    io.control.bp_mode := trace_bp_mode
 
     def traceEncoderControlRegWrite(valid: Bool, bits: UInt): Bool = {
       control_reg_write_valid := valid
@@ -79,6 +75,10 @@ class TraceEncoderController(addr: BigInt, beatBytes: Int)(implicit p: Parameter
         0x20 -> Seq(
           RegField(1, trace_sink_target,
             RegFieldDesc("target", "Trace sink target"))
+        ),
+        0x24 -> Seq(
+          RegField(32, trace_bp_mode,
+            RegFieldDesc("bp_mode", "Trace branch predictor mode"))
         )
       ):_*
     )
diff --git a/src/main/scala/util/Annotations.scala b/src/main/scala/util/Annotations.scala
index 851571ba46e..db53fd74306 100644
--- a/src/main/scala/util/Annotations.scala
+++ b/src/main/scala/util/Annotations.scala
@@ -3,160 +3,12 @@
 package freechips.rocketchip.util
 
 import chisel3._
-import chisel3.experimental.{annotate, ChiselAnnotation}
 
-import firrtl.annotations._
-
-import org.chipsalliance.diplomacy
-
-import freechips.rocketchip.diplomacy.{AddressRange, AddressSet}
-import freechips.rocketchip.resources.{AddressMapEntry, ResourcePermissions}
-import freechips.rocketchip.regmapper.{RegField, RegFieldDescSer, RegistersSer}
+import freechips.rocketchip.regmapper.RegField
 
 import org.json4s.JsonDSL._
 import org.json4s.jackson.JsonMethods.{pretty, render}
 
-/** Record a sram. */
-case class SRAMAnnotation(target: Named,
-  address_width: Int,
-  name: String,
-  data_width: Int,
-  depth: BigInt,
-  description: String,
-  write_mask_granularity: Int) extends SingleTargetAnnotation[Named] {
-  def duplicate(n: Named) = this.copy(n)
-}
-
-/** Record a set of interrupts. */
-case class InterruptsPortAnnotation(target: Named, name: String, interruptIndexes: Seq[Int]) extends SingleTargetAnnotation[Named] {
-  def duplicate(n: Named) = this.copy(n)
-}
-
-/** Record a case class that was used to parameterize this target. */
-case class GlobalConstantsAnnotation(target: Named, xLen: Int) extends SingleTargetAnnotation[Named] {
-  def duplicate(n: Named) = this.copy(n)
-}
-
-case class GlobalConstantsChiselAnnotation[T <: Product](target: InstanceId, xLen: Int) extends ChiselAnnotation {
-  def toFirrtl = GlobalConstantsAnnotation(target.toNamed, xLen)
-}
-
-/** Record a case class that was used to parameterize this target. */
-case class ParamsAnnotation(target: Named, paramsClassName: String, params: Map[String,Any]) extends SingleTargetAnnotation[Named] {
-  def duplicate(n: Named) = this.copy(n)
-}
-
-case class ParamsChiselAnnotation[T <: Product](target: InstanceId, params: T) extends ChiselAnnotation {
-  private val paramMap = params.getClass.getDeclaredFields.map(_.getName).zip(params.productIterator).toMap
-  def toFirrtl = ParamsAnnotation(target.toNamed, params.getClass.getName, paramMap)
-}
-
-/** Record an address map. */
-case class AddressMapAnnotation(target: Named, mapping: Seq[AddressMapEntry], label: String) extends SingleTargetAnnotation[Named] {
-  def duplicate(n: Named) = this.copy(n)
-
-  def toUVM: String =
-    s"// Instance Name: ${target.serialize}\n" +
-      mapping.map(_.range.toUVM).mkString("\n")
-
-  def toJSON: String =
-    s"""{\n  "${label}":  [\n""" +
-      mapping.map(_.range.toJSON).mkString(",\n") +
-      "\n  ]\n}"
-}
-
-/** Marks this module as a candidate for register retiming */
-case class RetimeModuleAnnotation(target: ModuleName) extends SingleTargetAnnotation[ModuleName] {
-  def duplicate(n: ModuleName) = this.copy(n)
-}
-
-/** Annotation capturing information about port slave devices. */
-case class SlaveAddressMapChiselAnnotation(
-    target: InstanceId,
-    addresses: Seq[AddressSet],
-    perms: ResourcePermissions) extends ChiselAnnotation {
-  private val range = AddressRange.fromSets(addresses)
-  def toFirrtl = AddressMapAnnotation(
-    target = target.toNamed,
-    mapping = range.map { r => AddressMapEntry(r, perms, Nil) },
-    label = "slaves")
-}
-
-/** Record information about a top-level port of the design */
-case class TopLevelPortAnnotation(
-  target: ComponentName,
-  protocol: String,
-  tags: Seq[String],
-  names: Seq[String],
-  width: Int,
-  address: Seq[AddressSet]) extends SingleTargetAnnotation[ComponentName] {
-  def duplicate(n: ComponentName): TopLevelPortAnnotation = this.copy(n)
-}
-
-/** Record the resetVector. */
-case class ResetVectorAnnotation(target: Named, resetVec: BigInt) extends SingleTargetAnnotation[Named] {
-  def duplicate(n: Named): ResetVectorAnnotation = this.copy(n)
-}
-
-/** Helper object containing methods for applying annotations to targets */
-object Annotated {
-
-  def srams(
-    component: InstanceId,
-    name: String,
-    address_width: Int,
-    data_width: Int,
-    depth: BigInt,
-    description: String,
-    write_mask_granularity: Int): Unit = {
-    annotate(new ChiselAnnotation {def toFirrtl: Annotation = SRAMAnnotation(
-      component.toNamed,
-      address_width = address_width,
-      name = name,
-      data_width = data_width,
-      depth = depth,
-      description = description,
-      write_mask_granularity = write_mask_granularity
-    )})}
-
-  def interrupts(component: InstanceId, name: String, interrupts: Seq[Int]): Unit = {
-    annotate(new ChiselAnnotation {def toFirrtl: Annotation = InterruptsPortAnnotation(
-      component.toNamed,
-      name,
-      interrupts
-    )})
-  }
-
-  def resetVector(component: InstanceId, resetVec: BigInt): Unit = {
-    annotate(new ChiselAnnotation {def toFirrtl: Annotation = ResetVectorAnnotation(component.toNamed, resetVec)})
-  }
-
-  def constants(component: InstanceId, xLen: Int): Unit = {
-    annotate(GlobalConstantsChiselAnnotation(component, xLen ))
-  }
-
-  def params[T <: Product](component: InstanceId, params: T): T = {
-    annotate(ParamsChiselAnnotation(component, params))
-    params
-  }
-
-  def addressMapping(component: InstanceId, mapping: Seq[AddressMapEntry]): Seq[AddressMapEntry] = {
-    annotate(new ChiselAnnotation { def toFirrtl = AddressMapAnnotation(component.toNamed, mapping, "mapping") })
-    mapping
-  }
-
-  def port[T <: Data](
-    data: T,
-    protocol: String,
-    tags: Seq[String],
-    names: Seq[String],
-    width: Int,
-    address: Seq[AddressSet] = Nil): T = {
-    annotate(new ChiselAnnotation { def toFirrtl = TopLevelPortAnnotation(data.toNamed, protocol, tags, names, width, address) })
-    data
-  }
-}
-
 /** Mix this into a Module class or instance to mark its ports as untouchable */
 trait DontTouch { self: RawModule =>
   // TODO: replace this with an implicit class from UserModule that uses getPorts
@@ -182,108 +34,8 @@ trait DontTouch { self: RawModule =>
   }
 }
 
-/** Mix this into a Module class or instance to mark it for register retiming */
-trait ShouldBeRetimed { self: RawModule =>
-  chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl: RetimeModuleAnnotation = RetimeModuleAnnotation(self.toNamed) })
-}
-
-case class RegFieldDescMappingAnnotation(
-  target: ModuleName,
-  regMappingSer: RegistersSer) extends SingleTargetAnnotation[ModuleName] {
-  def duplicate(n: ModuleName): RegFieldDescMappingAnnotation = this.copy(target = n)
-}
-
-object InterruptsPortAnnotation {
-  val GLOBAL_EXTERNAL_INTERRUPTS = "global-external-interrupts"
-  val LOCAL_EXTERNAL_INTERRUPTS = "local-external-interrupts"
-  val LOCAL_INTERRUPTS_STARTING_NUMBER = 16 /* TODO the ISA specfication reserves the first 12 interrupts but
-  somewhere in DTS 16 is used as the starting number. */
-
-}
-
 object GenRegDescsAnno {
 
-  def makeRegMappingSer(
-    rawModule: RawModule,
-    moduleName: String,
-    baseAddress: BigInt,
-    width: Int,
-    byteOffset: Int,
-    bitOffset: Int,
-    regField: RegField): RegFieldDescSer = {
-
-    val anonRegFieldName = s"unnamedRegField${byteOffset.toHexString}_${bitOffset}"
-    val selectedRegFieldName = regField.desc.map(_.name).getOrElse(anonRegFieldName)
-
-    val map = Map[BigInt, (String, String)]() // TODO
-
-// TODO: enumerations will be handled in upcoming PR
-//    ("enumerations" -> desc.map {d =>
-//      Option(d.enumerations.map { case (key, (name, edesc)) =>
-//        (("value" -> key) ~ ("name" -> name) ~ ("description" -> edesc))
-//      }).filter(_.nonEmpty)}) )
-
-    val desc = regField.desc
-
-    val regFieldDescSer = RegFieldDescSer(
-      byteOffset = s"0x${byteOffset.toInt.toHexString}",
-      bitOffset = bitOffset,
-      bitWidth = width,
-      name = selectedRegFieldName,
-      desc = desc.map {_.desc}.getOrElse("None"),
-      group = desc.map {_.group.getOrElse("None")}.getOrElse("None"),
-      groupDesc = desc.map {_.groupDesc.getOrElse("None")}.getOrElse("None"),
-      accessType = desc.map {_.access.toString}.getOrElse("None"),
-      wrType = desc.map(_.wrType.toString).getOrElse("None"),
-      rdAction = desc.map(_.rdAction.toString).getOrElse("None"),
-      volatile = desc.map(_.volatile).getOrElse(false),
-      hasReset = desc.map {_.reset != None }.getOrElse(false),
-      resetValue = desc.map{_.reset.getOrElse(BigInt(0))}.getOrElse(BigInt(0)),
-      enumerations = map
-    )
-
-    regFieldDescSer
-  }
-
-
-  def anno(
-    rawModule: RawModule,
-    baseAddress: BigInt,
-    mapping: RegField.Map*): Seq[RegField.Map] = {
-
-    val moduleName = rawModule.name
-    val baseHex = s"0x${baseAddress.toInt.toHexString}"
-    val displayName = s"${moduleName}.${baseHex}"
-
-    val regFieldSers = mapping.flatMap {
-      case (byteOffset, seq) =>
-        seq.map(_.width).scanLeft(0)(_ + _).zip(seq).map { case (bitOffset, regField) =>
-          makeRegMappingSer(
-            rawModule,
-            moduleName,
-            baseAddress,
-            regField.width,
-            byteOffset,
-            bitOffset,
-            regField
-          )
-        }
-    }
-
-    val registersSer = RegistersSer(
-      displayName = moduleName,
-      deviceName = moduleName,
-      baseAddress = baseAddress,
-      regFields = regFieldSers // Seq[RegFieldSer]()
-    )
-    
-    /* annotate the module with the registers */
-    annotate(new ChiselAnnotation { def toFirrtl = RegFieldDescMappingAnnotation(rawModule.toNamed, registersSer) })
-
-    mapping
-  }
-
-
   def serialize(base: BigInt, name: String, mapping: RegField.Map*): String = {
 
 
diff --git a/src/main/scala/util/DescribedSRAM.scala b/src/main/scala/util/DescribedSRAM.scala
index 2484a56b278..9e86cdabee4 100644
--- a/src/main/scala/util/DescribedSRAM.scala
+++ b/src/main/scala/util/DescribedSRAM.scala
@@ -25,16 +25,6 @@ object DescribedSRAM {
 
     val uid = 0
 
-    Annotated.srams(
-      component = mem,
-      name = name,
-      address_width = log2Ceil(size),
-      data_width = data.getWidth,
-      depth = size,
-      description = desc,
-      write_mask_granularity = granWidth
-    )
-
     mem
   }
 }
diff --git a/src/main/scala/util/ElaborationArtefactAnnotation.scala b/src/main/scala/util/ElaborationArtefactAnnotation.scala
deleted file mode 100644
index 4f7f6cf7ccd..00000000000
--- a/src/main/scala/util/ElaborationArtefactAnnotation.scala
+++ /dev/null
@@ -1,155 +0,0 @@
-// See LICENSE.SiFive for license details.
-
-package freechips.rocketchip.util
-
-import firrtl.RenameMap
-import firrtl.annotations.{Annotation, HasSerializationHints}
-import firrtl.annotations.{IsModule, ReferenceTarget}
-
-import chisel3.{Data, SyncReadMem}
-import chisel3.experimental.{BaseModule, ChiselAnnotation}
-
-import scala.collection.mutable
-
-/** Like [[ElaborationArtefact]] but in annotation form.
-  *
-  * Does not implement [[CustomFileEmission]] because outputFile should be
-  * interpreted as the final, static filepath instead of computing from
-  * [[StageOptions]]. This is because the full outputFile path is computed by
-  * chisel but the contents are emitted by firrtl, which may have a different
-  * set of [[StageOptions]].
-  *
-  * FIXME: tokens should be [[List[Token]]] but JSON serialization fails with
-  *        "no usable constructor for Token"
-  */
-case class ElaborationArtefactAnnotation(outputFile: String, tokens: List[Any]) extends Annotation with HasSerializationHints {
-  def update(renames: RenameMap): Seq[Annotation] = {
-    Seq(this.copy(tokens = tokens.collect {
-      case t: Token => t.update(renames)
-      case other => Seq(other)
-    }.flatten))
-  }
-
-  def typeHints: Seq[Class[_]] = Seq(
-    classOf[Token],
-    classOf[StringToken],
-    classOf[ModulePathToken],
-    classOf[ReferencePathToken],
-  )
-}
-
-object ElaborationArtefactAnnotation {
-  /** Emits [[ElaborationArtefactAnnotation]] for the given filename extension and tokens.
-    */
-  def annotate(filename: String, tokens: => Seq[Token]): Unit = {
-    chisel3.experimental.annotate(new ChiselAnnotation {
-      def toFirrtl = ElaborationArtefactAnnotation(filename, tokens.toList)
-    })
-  }
-}
-
-
-sealed trait Token {
-  def update(renames: RenameMap): Seq[Token]
-}
-
-case class StringToken(value: String) extends Token {
-  def update(renames: RenameMap) = Seq(this)
-}
-
-case class ModulePathToken(target: IsModule) extends Token {
-  def update(renames: RenameMap) = {
-    renames.get(target) match {
-      case None => Seq(this)
-      case Some(Seq(newModule: IsModule)) => Seq(this.copy(target = newModule))
-      case Some(other) => throw new Exception(s"module $target cannot be renamed to $other")
-    }
-  }
-}
-
-case class MemoryPathToken(target: ReferenceTarget) extends Token {
-  def update(renames: RenameMap) = {
-    renames.get(target) match {
-      case None => Seq(this)
-      case Some(Seq()) => throw new Exception(s"memory $target was deleted")
-      case Some(Seq(one: ReferenceTarget)) => Seq(this.copy(target = one))
-      case Some(many) =>
-        many.tail.foldLeft(Seq[Token](MemoryPathToken(many.head.asInstanceOf[ReferenceTarget]))) {
-          case (tokens, r: ReferenceTarget) => this.copy(target = r) +: StringToken(" ") +: tokens
-        }.reverse
-    }
-  }
-}
-
-case class ReferencePathToken(target: ReferenceTarget) extends Token {
-  def update(renames: RenameMap) = {
-    renames.get(target) match {
-      case None => Seq(this)
-      case Some(Seq(newRef: ReferenceTarget)) => Seq(this.copy(target = newRef))
-      case Some(other) => throw new Exception(s"reference $target cannot be renamed to $other")
-    }
-  }
-}
-
-object Token {
-  /** An interpolator that generates tokens. Arguments for which a
-    * [[Tokenizer]] instance is defined will be turned into a [[Token]] using
-    * the [[Tokenizer]] instance, [[Seq]] elements will be recursively
-    * converted to Tokens, and all other values will be turned into
-    * [[StringToken]]s using their .toString method.
-    */
-  implicit class TokensInterpolator(private val sc: StringContext) extends AnyVal {
-    def tokens(args: Any*): Seq[Token] = {
-      val strings = sc.parts.map(StringContext.treatEscapes).iterator
-      val expressions = args.iterator
-      var tokenBuf = new mutable.ArrayBuffer[Token]()
-      // buffer to build up the next string token
-      val stringBuf = new StringBuilder(strings.next())
-      def append(any: Any): Unit = {
-        var nonStringToken: Option[Token] = None
-        any match {
-          case s: String => stringBuf ++= s
-          case d: Data => nonStringToken = Some(Token(d))
-          case m: SyncReadMem[_] => nonStringToken= Some(Token(m))
-          case m: BaseModule => nonStringToken = Some(Token(m))
-          case t: Token => nonStringToken = Some(t)
-          case seq: Seq[_] => seq.foreach(append)
-          case other => stringBuf ++= other.toString
-        }
-        if (nonStringToken.isDefined) {
-          if (stringBuf.nonEmpty) {
-            tokenBuf += StringToken(stringBuf.toString)
-            stringBuf.clear()
-          }
-          tokenBuf += nonStringToken.get
-        }
-      }
-      while (strings.hasNext) {
-        append(expressions.next())
-        stringBuf ++= strings.next()
-      }
-      tokenBuf += StringToken(stringBuf.toString)
-      tokenBuf.toSeq
-    }
-  }
-
-  def apply[T: Tokenizer](t: T): Token = Tokenizer[T].toToken(t)
-}
-
-
-sealed trait Tokenizer[T] {
-  def toToken(t: T): Token
-}
-
-object Tokenizer {
-  def apply[T: Tokenizer] = implicitly[Tokenizer[T]]
-
-  private def tokenizer[T](fn: T => Token): Tokenizer[T] = new Tokenizer[T] {
-    def toToken(t: T) = fn(t)
-  }
-
-  implicit def stringTokenizer: Tokenizer[String] = tokenizer(StringToken(_: String))
-  implicit def modulePathTokenizer: Tokenizer[BaseModule] = tokenizer((m: BaseModule) => ModulePathToken(m.toTarget))
-  implicit def memPathTokenizer[T <: Data]: Tokenizer[SyncReadMem[T]] = tokenizer((m: SyncReadMem[_]) => MemoryPathToken(m.toTarget))
-  implicit def refPathTokenizer[T <: Data]: Tokenizer[T] = tokenizer((d: T) => ReferencePathToken(d.toTarget))
-}
diff --git a/src/main/scala/util/package.scala b/src/main/scala/util/package.scala
index 6ca4961d580..e1443d13298 100644
--- a/src/main/scala/util/package.scala
+++ b/src/main/scala/util/package.scala
@@ -300,4 +300,10 @@ package object util {
   def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
   @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
   val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
+
+  trait FileName {
+    val fileName: String
+  }
+  case class SystemFileName(fileName: String) extends FileName
+  case class ResourceFileName(fileName: String) extends FileName
 }