From 68b39aaaf3fd045c595fa4626a3bb433c71aa864 Mon Sep 17 00:00:00 2001
From: Jiuyang Liu <liu@jiuyang.me>
Date: Fri, 28 May 2021 09:32:42 +0000
Subject: [PATCH 1/3] remove DefRegInit, change DefReg API with option
 defination.

---
 core/src/main/scala/chisel3/Reg.scala                     | 4 ++--
 .../main/scala/chisel3/internal/firrtl/Converter.scala    | 8 +++-----
 core/src/main/scala/chisel3/internal/firrtl/IR.scala      | 6 ++++--
 src/main/scala/chisel3/aop/Select.scala                   | 1 -
 src/main/scala/chisel3/internal/firrtl/Emitter.scala      | 3 +--
 5 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/core/src/main/scala/chisel3/Reg.scala b/core/src/main/scala/chisel3/Reg.scala
index bd9e5311436..2fa1d4da472 100644
--- a/core/src/main/scala/chisel3/Reg.scala
+++ b/core/src/main/scala/chisel3/Reg.scala
@@ -42,7 +42,7 @@ object Reg {
     val clock = Node(Builder.forcedClock)
 
     reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen()))
-    pushCommand(DefReg(sourceInfo, reg, clock))
+    pushCommand(DefReg(sourceInfo, reg, clock, None, None))
     reg
   }
 
@@ -176,7 +176,7 @@ object RegInit {
 
     reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen()))
     requireIsHardware(init, "reg initializer")
-    pushCommand(DefRegInit(sourceInfo, reg, clock.ref, reset.ref, init.ref))
+    pushCommand(DefReg(sourceInfo, reg, clock.ref, Some(reset.ref), Some(init.ref)))
     reg
   }
 
diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
index ff0fa77089d..eb3a0fd90da 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
@@ -106,12 +106,10 @@ private[chisel3] object Converter {
       Some(fir.DefNode(convert(e.sourceInfo), e.name, expr))
     case e @ DefWire(info, id) =>
       Some(fir.DefWire(convert(info), e.name, extractType(id, info)))
-    case e @ DefReg(info, id, clock) =>
+    case e @ DefReg(info, id, clock, reset, init) =>
       Some(fir.DefRegister(convert(info), e.name, extractType(id, info), convert(clock, ctx, info),
-                           firrtl.Utils.zero, convert(getRef(id, info), ctx, info)))
-    case e @ DefRegInit(info, id, clock, reset, init) =>
-      Some(fir.DefRegister(convert(info), e.name, extractType(id, info), convert(clock, ctx, info),
-                           convert(reset, ctx, info), convert(init, ctx, info)))
+        reset.map(r => convert(r, ctx, info)).getOrElse(firrtl.Utils.zero),
+        init.map(i => convert(i, ctx, info)).getOrElse(convert(getRef(id, info), ctx, info))))
     case e @ DefMemory(info, id, t, size) =>
       Some(firrtl.CDefMemory(convert(info), e.name, extractType(t, info), size, false))
     case e @ DefSeqMemory(info, id, t, size, ruw) =>
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 81b4f7ab313..edf8b830fca 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -743,8 +743,10 @@ abstract class Definition extends Command {
 case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition
 case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command
 case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition
-case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition
-case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
+case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Option[Arg], init: Option[Arg]) extends Definition {
+  assert((reset.isDefined && init.isDefined) || (reset.isEmpty && init.isEmpty))
+  val hasInit: Boolean = reset.isDefined
+}
 case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition
 case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition
 case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition
diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala
index b9ad808b51c..876d2ab42fb 100644
--- a/src/main/scala/chisel3/aop/Select.scala
+++ b/src/main/scala/chisel3/aop/Select.scala
@@ -96,7 +96,6 @@ object Select {
     check(module)
     module._component.get.asInstanceOf[DefModule].commands.collect {
       case r: DefReg => r.id
-      case r: DefRegInit => r.id
     }
   }
 
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index ad4df80ae3b..98c2561faa1 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -66,8 +66,7 @@ private class Emitter(circuit: Circuit) {
     val firrtlLine = e match {
       case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})"
       case e: DefWire => s"wire ${e.name} : ${emitType(e.id)}"
-      case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}"
-      case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))"
+      case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}${ if (e.hasInit) "with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" else ""}"
       case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]"
       case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}], ${e.readUnderWrite}"
       case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"

From 8f2567010b1e748f3190c08d71ea4201edd95d40 Mon Sep 17 00:00:00 2001
From: Jiuyang Liu <liu@jiuyang.me>
Date: Fri, 28 May 2021 12:12:13 +0000
Subject: [PATCH 2/3] add error message

---
 core/src/main/scala/chisel3/internal/firrtl/IR.scala | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index edf8b830fca..54a5d3c2e92 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -744,7 +744,10 @@ case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: A
 case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command
 case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition
 case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Option[Arg], init: Option[Arg]) extends Definition {
-  assert((reset.isDefined && init.isDefined) || (reset.isEmpty && init.isEmpty))
+  assert(
+    (reset.isDefined && init.isDefined) || (reset.isEmpty && init.isEmpty),
+    "reset and init should exist(a register with init) or non-exist(a register without init) at the same time."
+  )
   val hasInit: Boolean = reset.isDefined
 }
 case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition

From 4a753f01771edffa204aa0c4fda350eb70068e6b Mon Sep 17 00:00:00 2001
From: Jiuyang Liu <liu@jiuyang.me>
Date: Wed, 2 Jun 2021 05:46:15 +0000
Subject: [PATCH 3/3] use Option[RegInitIR].

---
 core/src/main/scala/chisel3/Reg.scala                    | 4 ++--
 .../main/scala/chisel3/internal/firrtl/Converter.scala   | 8 +++++---
 core/src/main/scala/chisel3/internal/firrtl/IR.scala     | 9 ++-------
 src/main/scala/chisel3/internal/firrtl/Emitter.scala     | 2 +-
 4 files changed, 10 insertions(+), 13 deletions(-)

diff --git a/core/src/main/scala/chisel3/Reg.scala b/core/src/main/scala/chisel3/Reg.scala
index 2fa1d4da472..9cdbf6a1d39 100644
--- a/core/src/main/scala/chisel3/Reg.scala
+++ b/core/src/main/scala/chisel3/Reg.scala
@@ -42,7 +42,7 @@ object Reg {
     val clock = Node(Builder.forcedClock)
 
     reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen()))
-    pushCommand(DefReg(sourceInfo, reg, clock, None, None))
+    pushCommand(DefReg(sourceInfo, reg, clock, None))
     reg
   }
 
@@ -176,7 +176,7 @@ object RegInit {
 
     reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen()))
     requireIsHardware(init, "reg initializer")
-    pushCommand(DefReg(sourceInfo, reg, clock.ref, Some(reset.ref), Some(init.ref)))
+    pushCommand(DefReg(sourceInfo, reg, clock.ref, Some(RegInitIR(reset.ref, init.ref))))
     reg
   }
 
diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
index eb3a0fd90da..30aea47cbae 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
@@ -106,10 +106,12 @@ private[chisel3] object Converter {
       Some(fir.DefNode(convert(e.sourceInfo), e.name, expr))
     case e @ DefWire(info, id) =>
       Some(fir.DefWire(convert(info), e.name, extractType(id, info)))
-    case e @ DefReg(info, id, clock, reset, init) =>
+    case e @ DefReg(info, id, clock, None) =>
       Some(fir.DefRegister(convert(info), e.name, extractType(id, info), convert(clock, ctx, info),
-        reset.map(r => convert(r, ctx, info)).getOrElse(firrtl.Utils.zero),
-        init.map(i => convert(i, ctx, info)).getOrElse(convert(getRef(id, info), ctx, info))))
+                           firrtl.Utils.zero, convert(getRef(id, info), ctx, info)))
+    case e @ DefReg(info, id, clock, Some(RegInitIR(reset, init))) =>
+      Some(fir.DefRegister(convert(info), e.name, extractType(id, info), convert(clock, ctx, info),
+                           convert(reset, ctx, info), convert(init, ctx, info)))
     case e @ DefMemory(info, id, t, size) =>
       Some(firrtl.CDefMemory(convert(info), e.name, extractType(t, info), size, false))
     case e @ DefSeqMemory(info, id, t, size, ruw) =>
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 54a5d3c2e92..29a80015244 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -743,13 +743,8 @@ abstract class Definition extends Command {
 case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition
 case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command
 case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition
-case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Option[Arg], init: Option[Arg]) extends Definition {
-  assert(
-    (reset.isDefined && init.isDefined) || (reset.isEmpty && init.isEmpty),
-    "reset and init should exist(a register with init) or non-exist(a register without init) at the same time."
-  )
-  val hasInit: Boolean = reset.isDefined
-}
+case class RegInitIR(reset: Arg, init: Arg)
+case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg, regInit: Option[RegInitIR]) extends Definition
 case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition
 case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition
 case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 98c2561faa1..347039fea71 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -66,7 +66,7 @@ private class Emitter(circuit: Circuit) {
     val firrtlLine = e match {
       case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})"
       case e: DefWire => s"wire ${e.name} : ${emitType(e.id)}"
-      case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}${ if (e.hasInit) "with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" else ""}"
+      case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}${ if (e.regInit.isDefined) "with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" else ""}"
       case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]"
       case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}], ${e.readUnderWrite}"
       case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"