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Interval literal creation is inconsistent

API Modification

bug

Status: Open.

#1507 In chipsalliance/chisel;

· chick opened on Jul 7, 2020

Vec of Module IO strips directions and can connect to Bundle with different directions

Challenge IssueA nice-to-have but difficult to implementA nice-to-have but difficult to implement

feature request

Status: Open.

#571 In chipsalliance/chisel;

· jackkoenig opened on Apr 3, 2017

ChiselEnum: cannot use .asUInt.litValue to get the litValue

bug

FeatureNew feature, will be included in release notesNew feature, will be included in release notes

feature request

usability

Status: Open.

#1871 In chipsalliance/chisel;

· edwardcwang opened on Apr 21, 2021

Top level <code>InlineInstance</code> crashes FIRRTL

Status: Open.

#1851 In chipsalliance/chisel;

· kammoh opened on Apr 2, 2021

Reading binary by loadMemoryFromFile() causes MalformedInputException

Status: Open.

#1835 In chipsalliance/chisel;

· learning-chip opened on Mar 26, 2021

Make asUInt on Bundle Literals work outside of Builder context

Status: Open.

#1830 In chipsalliance/chisel;

· KasperHesse opened on Mar 23, 2021

Name sanitation behavior changed between Chisel v3.3 and v3.4

Status: Open.

#1784 In chipsalliance/chisel;

· jackkoenig opened on Feb 10, 2021

only last register of ShiftRegister can be renamed by suggestName

Status: Open.

#1722 In chipsalliance/chisel;

· sequencer opened on Jan 12, 2021

Implement module prefix API

FeatureNew feature, will be included in release notesNew feature, will be included in release notes

Status: Draft (not ready).

chipsalliance/chiselnumber 2155

#2155 In chipsalliance/chisel;

· jared-barocsi opened on Oct 7, 2021