diff --git a/verilog/includes/includes.gl.caravel_openframe b/verilog/includes/includes.gl.caravel_openframe
new file mode 100644
index 00000000..04f83234
--- /dev/null
+++ b/verilog/includes/includes.gl.caravel_openframe
@@ -0,0 +1,21 @@
+# OpenFrame GL includes
+# Caravel/OpenFrame padframe and infrastructure - gate level
+
+# PDK cells
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v
+
+# OpenFrame GL netlists
+-v $(CARAVEL_VERILOG_PATH)/rtl/defines.v
+-v $(CARAVEL_VERILOG_PATH)/rtl/user_defines.v
+-v $(CARAVEL_VERILOG_PATH)/rtl/pads.v
+-v $(CARAVEL_VERILOG_PATH)/gl/user_id_programming.v
+-v $(CARAVEL_VERILOG_PATH)/gl/chip_io_openframe.v
+-v $(CARAVEL_VERILOG_PATH)/gl/constant_block.v
+-v $(CARAVEL_VERILOG_PATH)/gl/xres_buf.v
+-v $(CARAVEL_VERILOG_PATH)/gl/caravel_openframe.v
+-v $(CARAVEL_VERILOG_PATH)/rtl/simple_por.v
diff --git a/verilog/includes/includes.rtl.caravel b/verilog/includes/includes.rtl.caravel
new file mode 100644
index 00000000..6858d50a
--- /dev/null
+++ b/verilog/includes/includes.rtl.caravel
@@ -0,0 +1,13 @@
+# Standard Caravel RTL includes
+# This is a placeholder - full Caravel requires MCW_ROOT
+
+# PDK cells
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v
+
+# Note: Standard Caravel includes require MCW_ROOT for the management SoC
+# This file is for OpenFrame mode only
diff --git a/verilog/includes/includes.rtl.caravel_openframe b/verilog/includes/includes.rtl.caravel_openframe
new file mode 100644
index 00000000..19ed187d
--- /dev/null
+++ b/verilog/includes/includes.rtl.caravel_openframe
@@ -0,0 +1,21 @@
+# OpenFrame RTL includes
+# Caravel/OpenFrame padframe and infrastructure
+
+# PDK cells
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v
+-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v
+
+# OpenFrame RTL
+-v $(CARAVEL_VERILOG_PATH)/rtl/defines.v
+-v $(CARAVEL_VERILOG_PATH)/rtl/user_defines.v
+-v $(CARAVEL_VERILOG_PATH)/rtl/pads.v
+-v $(CARAVEL_VERILOG_PATH)/rtl/user_id_programming.v
+-v $(CARAVEL_VERILOG_PATH)/rtl/chip_io_openframe.v
+-v $(CARAVEL_VERILOG_PATH)/rtl/constant_block.v
+-v $(CARAVEL_VERILOG_PATH)/rtl/xres_buf.v
+-v $(CARAVEL_VERILOG_PATH)/rtl/caravel_openframe.v
+-v $(CARAVEL_VERILOG_PATH)/rtl/simple_por.v
diff --git a/verilog/rtl/toplevel_cocotb.v b/verilog/rtl/toplevel_cocotb.v
index a56754c5..8205a127 100644
--- a/verilog/rtl/toplevel_cocotb.v
+++ b/verilog/rtl/toplevel_cocotb.v
@@ -173,6 +173,8 @@ caravel uut (
 		.resetb	  (resetb_tb)
 	);
 
+	// SPI flash is optional for OpenFrame - only instantiate if USE_SPIFLASH is defined
+	`ifdef USE_SPIFLASH
     spiflash #(
         .FILENAME(FILENAME)
     ) spiflash (
@@ -183,6 +185,8 @@ caravel uut (
         .io2(mprj_io_tb[36]),
         .io3(mprj_io_tb[37])
     );
+	`endif // USE_SPIFLASH
+
 	// do anything to the unused wires so cocotb can read them when iverilog is used
 	// apparently iverilog can't read the unused wires and that causes an error in python 
 	assign gpio_tb = 0;