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878 lines (874 loc) · 62.9 KB
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#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Wed Nov 6 09:26:15 2024
# Process ID: 22572
# Current directory: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15744 D:\BKU\HK241\Logic_Design_Project\Draftv1.1\Effect_Led_Project\Draft.xpr
# Log file: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/vivado.log
# Journal file: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
open_project: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 724.238 ; gain = 61.613
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs synth_1 -jobs 16
[Wed Nov 6 09:28:45 2024] Launched synth_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/synth_1/runme.log
reset_run synth_1
launch_runs synth_1 -jobs 16
[Wed Nov 6 09:30:15 2024] Launched synth_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/synth_1/runme.log
reset_run synth_1
launch_runs synth_1 -jobs 16
[Wed Nov 6 09:30:42 2024] Launched synth_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/synth_1/runme.log
launch_runs impl_1 -jobs 16
[Wed Nov 6 09:31:21 2024] Launched impl_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/runme.log
reset_run impl_1 -prev_step
reset_run synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/synth_1
launch_runs synth_1 -jobs 16
[Wed Nov 6 09:34:22 2024] Launched synth_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/synth_1/runme.log
launch_runs impl_1 -jobs 16
[Wed Nov 6 09:35:02 2024] Launched impl_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/runme.log
open_run impl_1
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.061 . Memory (MB): peak = 1720.941 ; gain = 0.000
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 1720.941 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1720.941 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
open_run: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1880.273 ; gain = 873.793
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'EffectLed_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj EffectLed_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Display7SEG.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Display7SEG
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_3
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_4
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_5
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/effectMode.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module effectMode
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/frequency.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module frequency
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/timer.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module timer
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sim_1/new/EffectLed_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed_tb
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xelab -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'inNum' [D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v:74]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.frequency
Compiling module xil_defaultlib.timer
Compiling module xil_defaultlib.effectMode
Compiling module xil_defaultlib.Effect_1
Compiling module xil_defaultlib.Effect_2
Compiling module xil_defaultlib.Effect_3
Compiling module xil_defaultlib.Effect_4
Compiling module xil_defaultlib.Effect_5
Compiling module xil_defaultlib.Display7SEG
Compiling module xil_defaultlib.EffectLed
Compiling module xil_defaultlib.EffectLed_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot EffectLed_tb_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "EffectLed_tb_behav -key {Behavioral:sim_1:Functional:EffectLed_tb} -tclbatch {EffectLed_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source EffectLed_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'EffectLed_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 1898.688 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'EffectLed_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj EffectLed_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Display7SEG.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Display7SEG
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_3
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_4
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_5
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/effectMode.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module effectMode
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/frequency.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module frequency
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/timer.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module timer
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sim_1/new/EffectLed_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed_tb
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xelab -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'inNum' [D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v:74]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.frequency
Compiling module xil_defaultlib.timer
Compiling module xil_defaultlib.effectMode
Compiling module xil_defaultlib.Effect_1
Compiling module xil_defaultlib.Effect_2
Compiling module xil_defaultlib.Effect_3
Compiling module xil_defaultlib.Effect_4
Compiling module xil_defaultlib.Effect_5
Compiling module xil_defaultlib.Display7SEG
Compiling module xil_defaultlib.EffectLed
Compiling module xil_defaultlib.EffectLed_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot EffectLed_tb_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "EffectLed_tb_behav -key {Behavioral:sim_1:Functional:EffectLed_tb} -tclbatch {EffectLed_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source EffectLed_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'EffectLed_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 1945.453 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'EffectLed_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj EffectLed_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Display7SEG.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Display7SEG
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_3
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_4
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_5
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/effectMode.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module effectMode
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/frequency.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module frequency
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/timer.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module timer
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sim_1/new/EffectLed_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed_tb
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xelab -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'inNum' [D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v:74]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.frequency
Compiling module xil_defaultlib.timer
Compiling module xil_defaultlib.effectMode
Compiling module xil_defaultlib.Effect_1
Compiling module xil_defaultlib.Effect_2
Compiling module xil_defaultlib.Effect_3
Compiling module xil_defaultlib.Effect_4
Compiling module xil_defaultlib.Effect_5
Compiling module xil_defaultlib.Display7SEG
Compiling module xil_defaultlib.EffectLed
Compiling module xil_defaultlib.EffectLed_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot EffectLed_tb_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "EffectLed_tb_behav -key {Behavioral:sim_1:Functional:EffectLed_tb} -tclbatch {EffectLed_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source EffectLed_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'EffectLed_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
close_design
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'EffectLed_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj EffectLed_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Display7SEG.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Display7SEG
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_3
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_4
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_5
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/effectMode.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module effectMode
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/frequency.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module frequency
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/timer.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module timer
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sim_1/new/EffectLed_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed_tb
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xelab -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'inNum' [D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v:74]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.frequency
Compiling module xil_defaultlib.timer
Compiling module xil_defaultlib.effectMode
Compiling module xil_defaultlib.Effect_1
Compiling module xil_defaultlib.Effect_2
Compiling module xil_defaultlib.Effect_3
Compiling module xil_defaultlib.Effect_4
Compiling module xil_defaultlib.Effect_5
Compiling module xil_defaultlib.Display7SEG
Compiling module xil_defaultlib.EffectLed
Compiling module xil_defaultlib.EffectLed_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot EffectLed_tb_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "EffectLed_tb_behav -key {Behavioral:sim_1:Functional:EffectLed_tb} -tclbatch {EffectLed_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source EffectLed_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'EffectLed_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 2080.777 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'EffectLed_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj EffectLed_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Display7SEG.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Display7SEG
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_3
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_4
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_5
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/effectMode.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module effectMode
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/frequency.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module frequency
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/timer.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module timer
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sim_1/new/EffectLed_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed_tb
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xelab -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'inNum' [D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v:74]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.frequency
Compiling module xil_defaultlib.timer
Compiling module xil_defaultlib.effectMode
Compiling module xil_defaultlib.Effect_1
Compiling module xil_defaultlib.Effect_2
Compiling module xil_defaultlib.Effect_3
Compiling module xil_defaultlib.Effect_4
Compiling module xil_defaultlib.Effect_5
Compiling module xil_defaultlib.Display7SEG
Compiling module xil_defaultlib.EffectLed
Compiling module xil_defaultlib.EffectLed_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot EffectLed_tb_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "EffectLed_tb_behav -key {Behavioral:sim_1:Functional:EffectLed_tb} -tclbatch {EffectLed_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source EffectLed_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'EffectLed_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 2080.777 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'EffectLed_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj EffectLed_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Display7SEG.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Display7SEG
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_3
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_4
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_5
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/effectMode.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module effectMode
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/frequency.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module frequency
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/timer.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module timer
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sim_1/new/EffectLed_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed_tb
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xelab -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'inNum' [D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v:74]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.frequency
Compiling module xil_defaultlib.timer
Compiling module xil_defaultlib.effectMode
Compiling module xil_defaultlib.Effect_1
Compiling module xil_defaultlib.Effect_2
Compiling module xil_defaultlib.Effect_3
Compiling module xil_defaultlib.Effect_4
Compiling module xil_defaultlib.Effect_5
Compiling module xil_defaultlib.Display7SEG
Compiling module xil_defaultlib.EffectLed
Compiling module xil_defaultlib.EffectLed_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot EffectLed_tb_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "EffectLed_tb_behav -key {Behavioral:sim_1:Functional:EffectLed_tb} -tclbatch {EffectLed_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source EffectLed_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'EffectLed_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'EffectLed_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj EffectLed_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Display7SEG.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Display7SEG
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_3
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_4
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_5
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/effectMode.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module effectMode
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/frequency.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module frequency
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/timer.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module timer
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sim_1/new/EffectLed_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed_tb
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xelab -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'inNum' [D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v:74]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.frequency
Compiling module xil_defaultlib.timer
Compiling module xil_defaultlib.effectMode
Compiling module xil_defaultlib.Effect_1
Compiling module xil_defaultlib.Effect_2
Compiling module xil_defaultlib.Effect_3
Compiling module xil_defaultlib.Effect_4
Compiling module xil_defaultlib.Effect_5
Compiling module xil_defaultlib.Display7SEG
Compiling module xil_defaultlib.EffectLed
Compiling module xil_defaultlib.EffectLed_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot EffectLed_tb_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "EffectLed_tb_behav -key {Behavioral:sim_1:Functional:EffectLed_tb} -tclbatch {EffectLed_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source EffectLed_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'EffectLed_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'EffectLed_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj EffectLed_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Display7SEG.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Display7SEG
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_3
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_4
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_5
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/effectMode.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module effectMode
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/frequency.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module frequency
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/timer.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module timer
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sim_1/new/EffectLed_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed_tb
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xelab -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'inNum' [D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v:74]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.frequency
Compiling module xil_defaultlib.timer
Compiling module xil_defaultlib.effectMode
Compiling module xil_defaultlib.Effect_1
Compiling module xil_defaultlib.Effect_2
Compiling module xil_defaultlib.Effect_3
Compiling module xil_defaultlib.Effect_4
Compiling module xil_defaultlib.Effect_5
Compiling module xil_defaultlib.Display7SEG
Compiling module xil_defaultlib.EffectLed
Compiling module xil_defaultlib.EffectLed_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot EffectLed_tb_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "EffectLed_tb_behav -key {Behavioral:sim_1:Functional:EffectLed_tb} -tclbatch {EffectLed_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source EffectLed_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'EffectLed_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'EffectLed_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj EffectLed_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Display7SEG.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Display7SEG
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_3
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_4
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/Effect_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Effect_5
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/effectMode.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module effectMode
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/frequency.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module frequency
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/timer.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module timer
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sim_1/new/EffectLed_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module EffectLed_tb
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
"xelab -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 34e9bbf9c09a40f18c91e874179b9ba7 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot EffectLed_tb_behav xil_defaultlib.EffectLed_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'inNum' [D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v:74]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.frequency
Compiling module xil_defaultlib.timer
Compiling module xil_defaultlib.effectMode
Compiling module xil_defaultlib.Effect_1
Compiling module xil_defaultlib.Effect_2
Compiling module xil_defaultlib.Effect_3
Compiling module xil_defaultlib.Effect_4
Compiling module xil_defaultlib.Effect_5
Compiling module xil_defaultlib.Display7SEG
Compiling module xil_defaultlib.EffectLed
Compiling module xil_defaultlib.EffectLed_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot EffectLed_tb_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "EffectLed_tb_behav -key {Behavioral:sim_1:Functional:EffectLed_tb} -tclbatch {EffectLed_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source EffectLed_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'EffectLed_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
reset_run synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/synth_1
launch_runs synth_1 -jobs 16
[Wed Nov 6 09:57:28 2024] Launched synth_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/synth_1/runme.log
launch_runs impl_1 -jobs 16
[Wed Nov 6 09:58:01 2024] Launched impl_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/runme.log
add_bp {D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sim_1/new/EffectLed_tb.v} 41
remove_bps -file {D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sim_1/new/EffectLed_tb.v} -line 41
open_run impl_1
INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 2080.777 ; gain = 0.000
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 2080.777 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.777 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
close_design
close_sim
INFO: [Simtcl 6-16] Simulation closed
reset_run synth_1
launch_runs synth_1 -jobs 16
[Wed Nov 6 10:03:44 2024] Launched synth_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/synth_1/runme.log
launch_runs impl_1 -jobs 16
[Wed Nov 6 10:04:36 2024] Launched impl_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/runme.log
reset_run synth_1
launch_runs synth_1 -jobs 16
[Wed Nov 6 10:06:19 2024] Launched synth_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/synth_1/runme.log
launch_runs impl_1 -jobs 16
[Wed Nov 6 10:06:52 2024] Launched impl_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/runme.log
launch_runs impl_1 -to_step write_bitstream -jobs 16
[Wed Nov 6 10:07:55 2024] Launched impl_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/runme.log
close_project
open_project D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs synth_1 -jobs 16
CRITICAL WARNING: [HDL 9-806] Syntax error near ")". [D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.srcs/sources_1/new/EffectLed.v:29]
CRITICAL WARNING: [filemgmt 20-742] The top module "EffectLed" specified for this project can not be validated. The current project is using automatic hierarchy update mode, and hence a new suitable replacement top will be automatically selected. If this is not desired, please change the hierarchy update mode to one of the manual compile order modes first, and then set top to any desired value.
Resolution: To switch to manual update order go to the Sources view, right-click on any node in the hierarchy and in the context menu select: 'Hierarchy Update' option 'No Update' or run the following Tcl Command: set_property source_mgmt_mode None [current_project] (which is the Manual Compile Order mode).
[Wed Nov 6 10:10:46 2024] Launched synth_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/synth_1/runme.log
update_compile_order -fileset sources_1
reset_run synth_1
update_compile_order -fileset sources_1
launch_runs synth_1 -jobs 16
[Wed Nov 6 10:12:10 2024] Launched synth_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/synth_1/runme.log
launch_runs impl_1 -jobs 16
[Wed Nov 6 10:12:49 2024] Launched impl_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/runme.log
exit
INFO: [Common 17-206] Exiting Vivado at Wed Nov 6 10:14:20 2024...