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#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Wed Nov 6 17:17:59 2024
# Process ID: 16100
# Current directory: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent3080 D:\BKU\HK241\Logic_Design_Project\Draftv1.1\Effect_Led_Project\Draft.xpr
# Log file: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/vivado.log
# Journal file: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs synth_1 -jobs 16
[Wed Nov 6 17:18:57 2024] Launched synth_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/synth_1/runme.log
launch_runs impl_1 -jobs 16
[Wed Nov 6 17:19:32 2024] Launched impl_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/runme.log
launch_runs impl_1 -to_step write_bitstream -jobs 16
[Wed Nov 6 17:21:05 2024] Launched impl_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2019.1
**** Build date : May 24 2019 at 15:13:31
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/003017B3FA2CA
open_hw_target: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1896.766 ; gain = 1009.238
set_property PROGRAM.FILE {D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/EffectLed.bit} [get_hw_devices xc7z020_1]
current_hw_device [get_hw_devices xc7z020_1]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z020_1] 0]
INFO: [Labtools 27-1434] Device xc7z020 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
set_property PROBES.FILE {} [get_hw_devices xc7z020_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z020_1]
set_property PROGRAM.FILE {D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/EffectLed.bit} [get_hw_devices xc7z020_1]
program_hw_devices [get_hw_devices xc7z020_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
INFO: [Labtools 27-1434] Device xc7z020 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
close_hw
reset_run synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/synth_1
launch_runs synth_1 -jobs 16
[Wed Nov 6 17:24:27 2024] Launched synth_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/synth_1/runme.log
launch_runs impl_1 -jobs 16
[Wed Nov 6 17:25:18 2024] Launched impl_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/runme.log
launch_runs impl_1 -to_step write_bitstream -jobs 16
[Wed Nov 6 17:26:14 2024] Launched impl_1...
Run output will be captured here: D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2019.1
**** Build date : May 24 2019 at 15:13:31
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/003017B3FA2CA
set_property PROGRAM.FILE {D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/EffectLed.bit} [get_hw_devices xc7z020_1]
current_hw_device [get_hw_devices xc7z020_1]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z020_1] 0]
INFO: [Labtools 27-1434] Device xc7z020 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
set_property PROBES.FILE {} [get_hw_devices xc7z020_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z020_1]
set_property PROGRAM.FILE {D:/BKU/HK241/Logic_Design_Project/Draftv1.1/Effect_Led_Project/Draft.runs/impl_1/EffectLed.bit} [get_hw_devices xc7z020_1]
program_hw_devices [get_hw_devices xc7z020_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
INFO: [Labtools 27-1434] Device xc7z020 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
exit
INFO: [Common 17-206] Exiting Vivado at Wed Nov 6 17:28:31 2024...