diff --git a/build.sbt b/build.sbt index e4b1fcf7..6c46c303 100644 --- a/build.sbt +++ b/build.sbt @@ -9,6 +9,9 @@ libraryDependencies ++= Seq( "org.scala-lang.modules" %% "scala-parser-combinators" % "1.1.2", "com.lihaoyi" %% "pprint" % "0.5.6", + // Language Processing + "org.bitbucket.inkytonik.kiama" %% "kiama" % "2.4.0", + // SMT Solving "io.github.tudo-aqua" % "z3-turnkey" % "4.8.7.1", diff --git a/src/main/scala/pipedsl/Interpreter.scala b/src/main/scala/pipedsl/Interpreter.scala index f456f143..a16e2f68 100644 --- a/src/main/scala/pipedsl/Interpreter.scala +++ b/src/main/scala/pipedsl/Interpreter.scala @@ -102,7 +102,7 @@ class Interpreter(val maxIterations: Int) { interp_command(fbr, env) } } - case CAssign(lhs, rhs) => { + case CAssign(lhs, rhs, typ) => { val rval = interp_expr(rhs, env) lhs match { case EVar(id) => { @@ -114,7 +114,7 @@ class Interpreter(val maxIterations: Int) { case _ => throw Errors.UnexpectedExpr(lhs) } } - case CRecv(lhs, rhs) => { + case CRecv(lhs, rhs, typ) => { val rval = interp_expr(rhs, env) lhs match { case EVar(id) => { diff --git a/src/main/scala/pipedsl/Main.scala b/src/main/scala/pipedsl/Main.scala index 370217b2..2fb4cc63 100644 --- a/src/main/scala/pipedsl/Main.scala +++ b/src/main/scala/pipedsl/Main.scala @@ -3,8 +3,10 @@ package pipedsl import java.io.{File, PrintWriter} import java.nio.file.{Files, Paths, StandardCopyOption} +import com.microsoft.z3.Context import com.typesafe.scalalogging.Logger import org.apache.commons.io.FilenameUtils +import pipedsl.analysis.{PredicateAnalysis, TimingAnalysis, TypeAnalysis, TypeInference} import pipedsl.codegen.bsv.{BSVPrettyPrinter, BluespecInterfaces} import pipedsl.codegen.bsv.BluespecGeneration.BluespecProgramGenerator import pipedsl.common.DAGSyntax.PStage @@ -66,18 +68,19 @@ object Main { val pinfo = new ProgInfo(prog) try { val canonProg = CanonicalizePass.run(prog) - val basetypes = BaseTypeChecker.check(canonProg, None) - val nprog = new BindModuleTypes(basetypes).run(canonProg) - TimingTypeChecker.check(nprog, Some(basetypes)) - MarkNonRecursiveModulePass.run(nprog) - val recvProg = SimplifyRecvPass.run(nprog) - LockRegionChecker.check(recvProg, None) + TypeInference.checkProgram(canonProg) + TypeAnalysis.get(canonProg).checkProg() + TimingAnalysis.get(canonProg).checkProg() + MarkNonRecursiveModulePass.run(canonProg) + val recvProg = SimplifyRecvPass.run(canonProg) + new LockRegionChecker(recvProg).check(recvProg, None) val lockWellformedChecker = new LockWellformedChecker() val locks = lockWellformedChecker.check(canonProg) pinfo.addLockInfo(lockWellformedChecker.getModLockTypeMap) - val lockChecker = new LockConstraintChecker(locks, lockWellformedChecker.getModLockTypeMap) + val ctx = new Context() + val lockChecker = new LockConstraintChecker(PredicateAnalysis.get(recvProg, ctx), locks, lockWellformedChecker.getModLockTypeMap, ctx) lockChecker.check(recvProg, None) - SpeculationChecker.check(recvProg, Some(basetypes)) + //SpeculationChecker.check(recvProg, Some(basetypes)) if (printOutput) { val writer = new PrintWriter(outputFile) writer.write("Passed") @@ -103,7 +106,7 @@ object Main { //Run the transformation passes on the stage representation stageInfo map { case (n, stgs) => //Change Recv statements into send + recv pairs - new ConvertAsyncPass(n).run(stgs) + new ConvertAsyncPass(n, TypeAnalysis.get(prog)).run(stgs) //Convert lock ops into ops that track explicit handles LockOpTranslationPass.run(stgs) //Add in extra conditionals to ensure address locks are not double acquired diff --git a/src/main/scala/pipedsl/Parser.scala b/src/main/scala/pipedsl/Parser.scala index dc9d6900..bf7439cd 100644 --- a/src/main/scala/pipedsl/Parser.scala +++ b/src/main/scala/pipedsl/Parser.scala @@ -143,14 +143,13 @@ class Parser extends RegexParsers with PackratParsers { lazy val lhs: Parser[Expr] = memAccess | variable lazy val simpleCmd: P[Command] = positioned { - typ.? ~ variable ~ "=" ~ expr ^^ { case t ~ n ~ _ ~ r => n.typ = t; CAssign(n, r) } | - typ.? ~ lhs ~ "<-" ~ expr ^^ { case t ~ l ~ _ ~ r => l.typ = t - CRecv(l, r) + typ.? ~ variable ~ "=" ~ expr ^^ { case t ~ n ~ _ ~ r => CAssign(n, r, t) } | + typ.? ~ lhs ~ "<-" ~ expr ^^ { case t ~ l ~ _ ~ r => CRecv(l, r, t) } | check | "start" ~> parens(iden) ^^ { i => CLockStart(i) } | "end" ~> parens(iden) ^^ { i => CLockEnd(i) } | - "acquire" ~> parens(lockArg) ^^ { i => CSeq(CLockOp(i, Reserved), CLockOp(i, Acquired)) } | + "acquire" ~> parens(lockArg) ^^ { i => CSeq(CLockOp(i, Reserved), CLockOp(copyLockArg(i), Acquired)) } | "reserve" ~> parens(lockArg) ^^ { i => CLockOp(i, Reserved)} | "block" ~> parens(lockArg) ^^ { i => CLockOp(i, Acquired) } | "release" ~> parens(lockArg) ^^ { i => CLockOp(i, Released)} | @@ -160,6 +159,15 @@ class Parser extends RegexParsers with PackratParsers { expr ^^ (e => CExpr(e)) } + private def copyLockArg(l: LockArg): LockArg = { + val evar = l.evar match { + case Some(e) => Some(e.copy(id = e.id.copy())) + case None => None + } + LockArg(l.id.copy(), evar) + } + + lazy val lockArg: P[LockArg] = positioned { iden ~ brackets(variable).? ^^ {case i ~ v => LockArg(i, v)} } @@ -171,7 +179,6 @@ class Parser extends RegexParsers with PackratParsers { lazy val speculate: P[Command] = positioned { "speculate" ~> parens(typ ~ variable ~ "=" ~ expr ~ "," ~ block ~ "," ~ block) ^^ { case t ~ v ~ _ ~ ev ~ _ ~ cv ~ _ ~ cs => - v.typ = Some(t) CSpeculate(v, ev, cv, cs) } } @@ -186,23 +193,23 @@ class Parser extends RegexParsers with PackratParsers { "default:" ~> block } lazy val split: P[Command] = positioned { - "split" ~> braces(rep(casestmt) ~ defaultcase.?) ^^ { case cl ~ dc => CSplit(cl, if (dc.isDefined) dc.get else CEmpty) } + "split" ~> braces(rep(casestmt) ~ defaultcase.?) ^^ { case cl ~ dc => CSplit(cl, if (dc.isDefined) dc.get else CEmpty()) } } lazy val block: P[Command] = { - braces(cmd.?) ^^ (c => c.getOrElse(CEmpty)) + braces(cmd.?) ^^ (c => c.getOrElse(CEmpty())) } lazy val conditional: P[Command] = positioned { "if" ~> parens(expr) ~ block ~ ("else" ~> blockCmd).? ^^ { - case cond ~ cons ~ alt => CIf(cond, cons, if (alt.isDefined) alt.get else CEmpty) + case cond ~ cons ~ alt => CIf(cond, cons, if (alt.isDefined) alt.get else CEmpty()) } } - lazy val seqCmd: P[Command] = { + lazy val seqCmd: P[Command] = { simpleCmd ~ ";" ~ seqCmd ^^ { case c1 ~ _ ~ c2 => CSeq(c1, c2) } | blockCmd ~ seqCmd ^^ { case c1 ~ c2 => CSeq(c1, c2) } | - simpleCmd <~ ";" | blockCmd | "" ^^ { _ => CEmpty } + simpleCmd <~ ";" | blockCmd | "" ^^ { _ => CEmpty() } } lazy val cmd: P[Command] = positioned { @@ -210,7 +217,7 @@ class Parser extends RegexParsers with PackratParsers { seqCmd } - lazy val sizedInt: P[Type] = "int" ~> angular(posint) ^^ { bits => TSizedInt(bits, unsigned = true) } + lazy val sizedInt: P[Type] = "int" ~> angular(posint) ^^ { bits => TSizedInt(TBitWidthLen(bits), unsigned = true) } lazy val latency: P[Latency.Latency] = "c" ^^ { _ => Latency.Combinational } | "s" ^^ { _ => Latency.Sequential } | "a" ^^ { _ => Latency.Asynchronous } @@ -234,7 +241,6 @@ class Parser extends RegexParsers with PackratParsers { lazy val typeName: P[Type] = iden ^^ { i => TNamedType(i) } lazy val param: P[Param] = iden ~ ":" ~ (typ | typeName) ^^ { case i ~ _ ~ t => - i.typ = Some(t) Param(i, t) } diff --git a/src/main/scala/pipedsl/analysis/AnalysisProvider.scala b/src/main/scala/pipedsl/analysis/AnalysisProvider.scala new file mode 100644 index 00000000..3e762a42 --- /dev/null +++ b/src/main/scala/pipedsl/analysis/AnalysisProvider.scala @@ -0,0 +1,9 @@ +package pipedsl.analysis + +import pipedsl.common.Syntax.Prog + +trait AnalysisProvider[Analysis] { + + def get(program: Prog): Analysis + +} diff --git a/src/main/scala/pipedsl/analysis/PredicateAnalysis.scala b/src/main/scala/pipedsl/analysis/PredicateAnalysis.scala new file mode 100644 index 00000000..b58bd44b --- /dev/null +++ b/src/main/scala/pipedsl/analysis/PredicateAnalysis.scala @@ -0,0 +1,109 @@ +package pipedsl.analysis + +import com.microsoft.z3.{AST => Z3AST, BoolExpr => Z3BoolExpr, Context => Z3Context, Expr => Z3Expr} +import org.bitbucket.inkytonik.kiama.attribution.Attribution +import org.bitbucket.inkytonik.kiama.relation.Tree +import pipedsl.common.Syntax +import pipedsl.common.Syntax.{BoolOp, BoolUOp, CIf, CSeq, CSplit, CaseObj, Command, EVar, EqOp, Expr, ModuleDef, Prog, ProgramNode} +import pipedsl.common.Utilities.{mkAnd, mkOr} + +class PredicateAnalysis(program: Tree[ProgramNode, Prog], typeAnalysis: TypeAnalysis, ctx: Z3Context) extends Attribution{ + + private val intArray = ctx.mkArraySort(ctx.getIntSort, ctx.getIntSort) + private var incrementer = 0 + + val increment: Unit => Int = { + _ => + incrementer += 1 + incrementer + } + + private def addPredicate(cond: Expr): Z3Expr = abstractInterp(cond) match { + case Some(value) => value + case None => ctx.mkEq(ctx.mkBoolConst("__TOPCONSTANT__" + increment()), ctx.mkTrue()) + } + + // Gives the condition for a branch + val branchCond: ProgramNode => Z3BoolExpr = attr { + case program.prev.pair(p: Command, program.parent.pair(prev: Expr, c@CIf(cond, cons, alt))) => + addPredicate(cond).asInstanceOf[Z3BoolExpr] + case program.prev.pair(p: Command, program.parent.pair(prev: Command, c@CIf(cond, cons, alt))) => + ctx.mkNot(branchCond(prev)) + case program.prev.pair(c@CaseObj(_, _), prev@CaseObj(_, _)) => mkAnd(ctx, ctx.mkNot(runningConds(prev)), caseCond(c)) + case program.prev.pair(default: Command, prev@CaseObj(_, _)) => ctx.mkNot(runningConds(prev)) + case program.parent.pair(c@CaseObj(_, _), p@CSplit(_, _)) => caseCond(c) + } + + val caseCond: CaseObj => Z3BoolExpr = attr { + case c@CaseObj(cond, body) => addPredicate(cond).asInstanceOf[Z3BoolExpr] + } + + val runningConds: CaseObj => Z3BoolExpr = attr { + case program.prev.pair(c@CaseObj(_,_), cprev@CaseObj(_, _)) => mkOr(ctx, runningConds(cprev), caseCond(c)) + case c: CaseObj => caseCond(c) + } + + //TODO: Add error in case of unexpected case, this is only called in lock constraint checker though + val predicate: ProgramNode => Z3BoolExpr = { + attr { + case program.parent.pair(c: Command, cif@CIf(_, _, _)) => mkAnd(ctx, predicate(cif), branchCond(c)) + case program.parent.pair(p, c: CSplit) => mkAnd(ctx, predicate(c), branchCond(p)) + case program.parent(_:ModuleDef) => ctx.mkTrue() + case program.parent(p) => predicate(p) + } + } + + val abstractInterp: Expr => Option[Z3Expr] = + attr { + case evar: EVar => Some(declareConstant(evar)) + case Syntax.EInt(v, base, bits) => Some(ctx.mkInt(v)) + case Syntax.EBool(v) => if (v) Some(ctx.mkTrue()) else Some(ctx.mkFalse()) + case Syntax.EUop(op, ex) => + val absex = abstractInterp(ex) + (op, absex) match { + case (BoolUOp(o), Some(v)) if o == "!" => Some(ctx.mkNot(v.asInstanceOf[Z3BoolExpr])) + case _ => None + } + case Syntax.EBinop(op, e1, e2) => + val abse1 = abstractInterp(e1) + val abse2 = abstractInterp(e2) + (op, abse1, abse2) match { + case (EqOp(o), Some(v1), Some(v2)) if o == "==" => Some(ctx.mkEq(v1, v2)) + case (EqOp(o), Some(v1), Some(v2)) if o == "!=" => Some(ctx.mkNot(ctx.mkEq(v1, v2))) + case (BoolOp(o, _), Some(v1), Some(v2)) if o == "&&" => + Some(ctx.mkAnd(v1.asInstanceOf[Z3BoolExpr], v2.asInstanceOf[Z3BoolExpr])) + case (BoolOp(o, _), Some(v1), Some(v2)) if o == "||" => + Some(ctx.mkOr(v1.asInstanceOf[Z3BoolExpr], v2.asInstanceOf[Z3BoolExpr])) + case _ => None + } + case Syntax.ETernary(cond, tval, fval) => + val abscond = abstractInterp(cond) + val abstval = abstractInterp(tval) + val absfval = abstractInterp(fval) + (abscond, abstval, absfval) match { + case (Some(vcond), Some(vtval), Some(vfval)) => + Some(ctx.mkITE(vcond.asInstanceOf[Z3BoolExpr], vtval, vfval)) + case _ => + None + } + case _ => None + } + + def declareConstant(evar: EVar): Z3Expr = + typeAnalysis.typeCheck(evar) match { + case _: Syntax.TSizedInt => ctx.mkIntConst(evar.id.v); + case _: Syntax.TBool => ctx.mkBoolConst(evar.id.v) + case _: Syntax.TMemType => ctx.mkConst(evar.id.v, intArray) + case _ => throw new RuntimeException("Unexpected type") + } +} +object PredicateAnalysis extends Attribution { + val instance: Z3Context => Prog => PredicateAnalysis = + paramAttr { + ctx => { + case p => new PredicateAnalysis(new Tree[ProgramNode, Prog](p), TypeAnalysis.get(p), ctx) + } + } + def get(program: Prog, ctx: Z3Context): PredicateAnalysis = instance(ctx)(program) +} + diff --git a/src/main/scala/pipedsl/analysis/TimingAnalysis.scala b/src/main/scala/pipedsl/analysis/TimingAnalysis.scala new file mode 100644 index 00000000..c7e27cb2 --- /dev/null +++ b/src/main/scala/pipedsl/analysis/TimingAnalysis.scala @@ -0,0 +1,213 @@ +package pipedsl.analysis + +import org.bitbucket.inkytonik.kiama.attribution.Attribution +import org.bitbucket.inkytonik.kiama.relation.Tree +import pipedsl.common.Errors.{UnavailableArgUse, UnexpectedAsyncReference, UnexpectedType} +import pipedsl.common.Syntax.Latency.{Asynchronous, Combinational, Latency} +import pipedsl.common.Syntax.{CAssign, CCheck, CEmpty, CExpr, CIf, CLockEnd, CLockOp, CLockStart, COutput, CPrint, CRecv, CReturn, CSeq, CSpeculate, CSplit, CTBar, Command, EApp, EBinop, EBitExtract, ECall, ECast, EMemAccess, ERecAccess, ETernary, EUop, EVar, Id, Latency, ModuleDef, Prog, ProgramNode, TMemType, Expr} + +class TimingAnalysis(program: Tree[ProgramNode, Prog], typeAnalysis: TypeAnalysis) extends Attribution{ + + type Available = Set[Id] + val NoneAvailable: Available = Set[Id]() + + def checkProg(): Unit = program.root.moddefs.foreach(checkModule(_)) + def checkModule(m: ModuleDef): Unit = checkCommand(m.body) + def checkCommand(c: Command): Unit = c match { + case CSeq(c1, c2) => checkCommand(c1); checkCommand(c2) + case CTBar(c1, c2) => checkCommand(c2); checkCommand(c2) + case CIf(cond, cons, alt) => + if (latency(cond) != Latency.Combinational) { + throw UnexpectedAsyncReference(cond.pos, cond.toString) + } + checkCommand(cons) + checkCommand(alt) + case CAssign(lhs, rhs, typ) => + if (latency(rhs) != Latency.Combinational) { + throw UnexpectedAsyncReference(rhs.pos, rhs.toString) + } + case CRecv(lhs, rhs, typ) => + latency(lhs) + latency(rhs) + case CPrint(evar) => latency(evar) + case COutput(exp) => + if (latency(exp) != Combinational) { + throw UnexpectedAsyncReference(exp.pos, exp.toString) + } + case CReturn(exp) => + if (latency(exp) != Combinational) { + throw UnexpectedAsyncReference(exp.pos, exp.toString) + } + case CExpr(exp) => latency(exp) + case CSpeculate(predVar, predVal, verify, body) => + case CCheck(predVar) => + case CSplit(cases, default) => + checkCommand(default) + for (c <- cases) { + if(latency(c.cond) != Latency.Combinational) { + throw UnexpectedAsyncReference(c.cond.pos, c.cond.toString) + } + checkCommand(c.body) + } + case CLockOp(mem, op) => + if (mem.evar.isDefined) { + latency(mem.evar.get) + } + case CLockStart(mod) => + case CLockEnd(mod) => + case CEmpty() => + case _ => + } + + /** + * Gives the variables available this cycle at a program node + */ + val availableNow: ProgramNode => Available = { + attr { + case program.prev(program.parent(c@CSeq(c1, c2))) => availableNow(c1) ++ generatedAvailableNow(NoneAvailable)(c1) + case program.prev(program.parent(c@CTBar(c1, c2))) => availableNow(c1) ++ generatedAvailableNow(NoneAvailable)(c1) ++ generatedAvailableNext(NoneAvailable)(c1) + case program.parent(m@ModuleDef(name, inputs, modules, ret, body)) => + val inputs = m.inputs.foldLeft[Available](NoneAvailable)((av,p) => { + av + p.name + }) + val allAvailable = m.modules.foldLeft[Available](inputs)((av, m) => { + av + m.name + }) + allAvailable + case program.parent(p) => availableNow(p) + } + } + + /** + * Gives the variables available the next cycle at this program node + */ + val availableNext: ProgramNode => Available = + attr { + case program.prev(program.parent(c@CSeq(c1, c2))) => availableNext(c1) ++ generatedAvailableNext(NoneAvailable)(c1) + case program.prev(program.parent(c@CTBar(c1, c2))) => NoneAvailable + case program.parent(m@ModuleDef(name, inputs, modules, ret, body)) => NoneAvailable + case program.parent(p) => availableNext(p) + } + + /** + * Gives the variables made available this cycle generated by a node + */ + val generatedAvailableNow: Available => ProgramNode => Available = { + paramAttr { + avail => { + case CSeq(c1, c2) => val a1 = generatedAvailableNow(avail)(c1); generatedAvailableNow(a1)(c2) + case CTBar(c1, c2) => val a1 = generatedAvailableNow(avail)(c1); generatedAvailableNow(a1 ++ generatedAvailableNext(NoneAvailable)(c1))(c2) + case CAssign(lhs@EVar(id), rhs, typ) => avail + id + case CIf(cond, cons, alt) => generatedAvailableNow(avail)(cons).intersect(generatedAvailableNow(avail)(alt)) + case CSplit(cases, default) => + var runningAvail: Available = generatedAvailableNow(avail)(default) + for (c <- cases) { + runningAvail = runningAvail.intersect(generatedAvailableNow(avail)(c)) + } + runningAvail + case _ => avail + } + } + } + + /** + * Gives the variables made available next cycle generated by a node + */ + val generatedAvailableNext: Available => ProgramNode => Available = { + paramAttr { + avail => { + case CSeq(c1, c2) => val a1 = generatedAvailableNext(avail)(c1); generatedAvailableNext(a1)(c2) + case CTBar(c1, c2) => generatedAvailableNext(NoneAvailable)(c2) + case CRecv(lhs, rhs, typ) => + (lhs, rhs) match { + case (EVar(id), EMemAccess(_, _)) => avail + id + case (EVar(id), ECall(_, _)) => avail + id + case (EVar(id), _) => avail + id + case (EMemAccess(_, _), EMemAccess(_, _)) => throw UnexpectedAsyncReference(lhs.pos, "Both sides of <- cannot be memory or modules references") + case _ => avail + } + case CIf(cond, cons, alt) => generatedAvailableNext(avail)(cons).intersect(generatedAvailableNext(avail)(alt)) + case CSplit(cases, default) => + var runningAvail: Available = generatedAvailableNext(avail)(default) + for (c <- cases) { + runningAvail = runningAvail.intersect(generatedAvailableNext(avail)(c)) + } + runningAvail + case _ => avail + } + } + } + + /** + * Gives the latency of an expression + */ + val latency: Expr => Latency = { + case EUop(_, e) => latency(e) match { + case Combinational => Combinational + case _ => throw UnexpectedAsyncReference(e.pos, e.toString) + } + case EBinop(_, e1, e2) => + (latency(e1), latency(e2)) match { + case (Combinational, Combinational) => Combinational + case (Combinational, _) => throw UnexpectedAsyncReference(e2.pos, e2.toString) + case (_, Combinational) => throw UnexpectedAsyncReference(e1.pos, e1.toString) + } + case ERecAccess(rec, _) => latency(rec) match { + case Combinational => Combinational + case _ => throw UnexpectedAsyncReference(rec.pos, rec.toString) + } + case e@EMemAccess(m, index) => typeAnalysis.typeCheck(m) match { + case TMemType(_, _, rLat, wLat) => + val memLat = if (isRhs(e)) { rLat } else { wLat } + val indexExpr = latency(index) + indexExpr match { + case Combinational => memLat + case _ => throw UnexpectedAsyncReference(index.pos, index.toString) + } + case _ => throw UnexpectedType(m.pos, m.v, "Mem Type",typeAnalysis.typeCheck(m)) + } + case EBitExtract(num, _, _) => latency(num) match { + case Combinational => Combinational + case _ => throw UnexpectedAsyncReference(num.pos, num.toString) + } + case ETernary(cond, tval, fval) => + (latency(cond), latency(tval), latency(fval)) match { + case (Combinational, Combinational, Combinational) => Combinational + case (_, Combinational, Combinational) => throw UnexpectedAsyncReference(cond.pos, cond.toString) + case (_, _, Combinational) => throw UnexpectedAsyncReference(tval.pos, tval.toString) + case _ => throw UnexpectedAsyncReference(fval.pos, fval.toString) + } + case EApp(_, args) => + args.foreach(a => if(latency(a) != Combinational) { + throw UnexpectedAsyncReference(a.pos, a.toString) + }) + Combinational + case ECall(_, args) => + args.foreach(a => if(latency(a) != Combinational) { + throw UnexpectedAsyncReference(a.pos, a.toString) + }) + Asynchronous + case e@EVar(id) => if(!availableNow(e)(id) && isRhs(e)) { throw UnavailableArgUse(e.pos, id.toString)} else { Combinational } + case ECast(_, exp) => latency(exp) + case _ => Combinational + } + + /** + * Returns whether or a node is the RHS of a declaration statement + */ + val isRhs: ProgramNode => Boolean = { + attr { + case program.prev(program.parent(_:CAssign)) => true + case program.prev(program.parent(_:CRecv)) => true + case _ => false + } + } +} + +object TimingAnalysis extends Attribution with AnalysisProvider[TimingAnalysis] { + val instance: Prog => TimingAnalysis = + attr { + case p => new TimingAnalysis(new Tree[ProgramNode, Prog](p), TypeAnalysis.get(p)) + } + override def get(program: Prog): TimingAnalysis = instance(program) +} diff --git a/src/main/scala/pipedsl/analysis/TypeAnalysis.scala b/src/main/scala/pipedsl/analysis/TypeAnalysis.scala new file mode 100644 index 00000000..11e9cf59 --- /dev/null +++ b/src/main/scala/pipedsl/analysis/TypeAnalysis.scala @@ -0,0 +1,435 @@ +package pipedsl.analysis + +import org.bitbucket.inkytonik.kiama.attribution.Attribution +import org.bitbucket.inkytonik.kiama.relation.Tree +import pipedsl.common.Errors.{ArgLengthMismatch, IllegalCast, MalformedFunction, MissingType, UnexpectedAssignment, UnexpectedCase, UnexpectedCommand, UnexpectedReturn, UnexpectedSubtype, UnexpectedType} +import pipedsl.common.Syntax +import pipedsl.common.Syntax.Latency.{Asynchronous, Combinational, Sequential} +import pipedsl.common.Syntax._ +import pipedsl.typechecker.Environments.{EmptyTypeEnv, Environment, TypeEnv} +import pipedsl.typechecker.Subtypes.{areEqual, isSubtype} + +class TypeAnalysis(program: Tree[ProgramNode, Prog]) extends Attribution { + + def checkProg(): Unit = { + val prog = program.root + prog.fdefs.foreach(f => { + checkCommand(f.body) + val rt = checkFuncWellFormed(f.body) + if (rt.isEmpty) { + throw MalformedFunction(f.pos, "Missing return statement") + } else if (!areEqual(f.ret, rt.get)) { + throw UnexpectedType(f.pos, s"${f.name} return type", f.ret.toString(), rt.get) + } + }) + prog.moddefs.foreach(m => { + checkCommand(m.body) + checkModuleBodyWellFormed(m.body, Set()) + }) + checkCircuit(prog.circ) + } + + /** + * This checks that the function doesn't include any disallowed expressions + * or commands (such as Calls) and checks that it does not have code following + * its return statement. This function is recursively defined and should be + * called on the function's body (which is a single command) + * @param c The command to check for well-formedness + * @return Some(return type) if the analyzed command returns a value or None other wise + */ + private def checkFuncWellFormed(c: Command): Option[Type] = c match { + case CSeq(c1, c2) => { + val r1 = checkFuncWellFormed(c1) + val r2 = checkFuncWellFormed(c2) + (r1, r2) match { + case (Some(_), Some(_)) => throw MalformedFunction(c.pos, "Multiple return statements in execution") + case (Some(_), _) => r1 + case (_, Some(_)) => r2 + case (None, None) => None + } + } + case _: CTBar | _: CSplit | _: CSpeculate | _: CCheck | _:COutput => + throw MalformedFunction(c.pos, "Command not supported in combinational functions") + case CIf(_, cons, alt) => + val rt = checkFuncWellFormed(cons) + val rf = checkFuncWellFormed(alt) + (rt, rf) match { + case (Some(t1), Some(t2)) if areEqual(t1, t2) => rt + case (Some(t1), Some(t2)) => throw MalformedFunction(c.pos, s"Mismatched return types ${t1.toString()}, and ${t2.toString()}") + case (None, None) => None + case _ => throw MalformedFunction(c.pos, "Missing return in branch of if") + } + case CReturn(exp) => Some(typeCheck(exp)) + case _ => None + } + + /** + * Checks that no variable is assigned multiple times in the command. + * @param c The command to check. + * @return The set of variables that get assigned in this command. + */ + private def checkModuleBodyWellFormed(c: Command, assignees: Set[Id]): Set[Id] = c match { + case CSeq(c1, c2) => + val a2 = checkModuleBodyWellFormed(c1, assignees) + checkModuleBodyWellFormed(c2,a2) + case CTBar(c1, c2) => + val a2 = checkModuleBodyWellFormed(c1, assignees) + checkModuleBodyWellFormed(c2, a2) + case CSplit(cs, d) => + val branches = cs.map(c => c.body) :+ d + //check all branches in same context + branches.foldLeft(assignees)((res, c) => { + val cassgns = checkModuleBodyWellFormed(c, assignees) + res ++ cassgns + }) + case CIf(_, cons, alt) => + val ast = checkModuleBodyWellFormed(cons, assignees) + val asf = checkModuleBodyWellFormed(alt, assignees) + ast ++ asf + case CRecv(lhs@EVar(id), _, _) => + if (assignees(id)) { throw UnexpectedAssignment(lhs.pos, id) } else { + assignees + id + } + case CAssign(lhs@EVar(id), _, _) => + if (assignees(id)) { throw UnexpectedAssignment(lhs.pos, id) } else { + assignees + id + } + //returns are only for function calls + case CReturn(_) => throw UnexpectedReturn(c.pos) + case _ => assignees + } + + def checkCommand(c: Command): Unit = { + val tenv = context(c) + c match { + case CSeq(c1, c2) => checkCommand(c1); checkCommand(c2); + case CTBar(c1, c2) => checkCommand(c1); checkCommand(c2); + case CIf(cond, cons, alt) => + typeCheck(cond).matchOrError(cond.pos, "if condition", "boolean") { case _: TBool => () } + checkCommand(cons) + checkCommand(alt) + case CAssign(lhs, rhs, typ) => + val lTyp = typeCheck(lhs) + val rTyp = typeCheck(rhs) + if (isSubtype(rTyp, lTyp)) TVoid() else throw UnexpectedSubtype(rhs.pos, "assignment", lTyp, rTyp) + case CRecv(lhs, rhs, typ) => + val lTyp = typeCheck(lhs) + val rTyp = typeCheck(rhs) + if (isSubtype(rTyp, lTyp)) TVoid() else throw UnexpectedSubtype(rhs.pos, "assignment", lTyp, rTyp) + case Syntax.CPrint(evar) => + val t = typeCheck(evar) + if (! (t.isInstanceOf[TSizedInt] || t.isInstanceOf[TString] || t.isInstanceOf[TBool])) { + throw UnexpectedType(evar.pos, evar.toString, "Need a printable type", t) + } + case Syntax.COutput(exp) => typeCheck(exp) + case Syntax.CReturn(exp) => typeCheck(exp) + case Syntax.CExpr(exp) => typeCheck(exp) + case CLockStart(mod) => tenv(mod).matchOrError(mod.pos, "lock reservation start", "Memory or Module Type") + { + case _: TModType => () + case _: TMemType => () + } + case CLockEnd(mod) => tenv(mod).matchOrError(mod.pos, "lock reservation start", "Memory or Module Type") + { + case _: TModType => () + case _: TMemType => () + } + case CLockOp(mem, _) => { + tenv(mem.id).matchOrError(mem.pos, "lock operation", "Memory or Module Type") + { + case t: TModType => + if (mem.evar.isDefined) throw UnexpectedType(t.pos, "address lock operation", "Memory Type", t) + case memt: TMemType => { + if(!mem.evar.isEmpty) { + val idxt = typeCheck(mem.evar.get) + idxt match { + case TSizedInt(l, true) if l.asInstanceOf[TBitWidthLen].len == memt.addrSize => () + case _ => throw UnexpectedType(mem.pos, "lock operation", "ubit<" + memt.addrSize + ">", idxt) + } + } + } + } + } + case CSplit(cases, default) => + for (c <- cases) { + val condTyp = typeCheck(c.cond) + condTyp.matchOrError(c.cond.pos, "case condition", "boolean") { case _: TBool => () } + checkCommand(c.body) + } + checkCommand(default) + case Syntax.CSpeculate(predVar, predVal, verify, body) => + case Syntax.CCheck(predVar) => + case Syntax.CEmpty() => + case _ => throw UnexpectedCommand(c) + } + } + + def checkCircuit(c: Circuit): Unit = { + c match { + case CirSeq(c1, c2) => { + checkCircuit(c1) + checkCircuit(c2) + } + case CirConnect(name, c) => + val t = typeCheck(c) + case CirExprStmt(ce) => typeCheck(ce) + } + } + + val contextAfterCommand: Environment[Id, Type] => Command => Environment[Id, Type] = { + paramAttr { + env => { + case c@CSeq(c1, c2) => val e1 = contextAfterCommand(env)(c1); contextAfterCommand(e1)(c2) + case c@CTBar(c1, c2) => val e1 = contextAfterCommand(env)(c1); contextAfterCommand(e1)(c2) + case c@CIf(cond, cons, alt) => contextAfterCommand(env)(cons).intersect(contextAfterCommand(env)(alt)) + case c@CSplit(cases, default) => + var runningEnv = contextAfterCommand(env)(default) + for (c <- cases) { + runningEnv = runningEnv.intersect(contextAfterCommand(env)(c.body)) + } + runningEnv + case c@CAssign(lhs@EVar(id), rhs, typ) => env.add(id, typ.get) + case c@CRecv(lhs@EVar(id), rhs, typ) => env.add(id, typ.get) + case _ => env + } + } + } + + val context: ProgramNode => Environment[Id, Type] = { + attr { + //Context is prev OR parent + //Need to match prev with CAssign, CIf,or CSplit, or CRecV + case program.prev(program.parent(c@CSeq(c1, c2))) => context(c1).union(contextAfterCommand(EmptyTypeEnv)(c1)) + case program.prev(program.parent(c@CTBar(c1, c2))) => context(c1).union(contextAfterCommand(EmptyTypeEnv)(c1)) + case program.parent(m@ModuleDef(name,inputs,modules,ret,body)) => + val tenv = context(m) + val inEnv = inputs.foldLeft[Environment[Id, Type]](tenv)((env, p) => { env.add(p.name, p.typ) }) + val pipeEnv = modules.foldLeft[Environment[Id, Type]](inEnv)((env, p) => + { env.add(p.name, replaceNamedType(p.typ, m)) }) + pipeEnv.add(m.name, typeCheck(m)) + case program.parent(f@FuncDef(name, args, ret, body)) => + val tenv = context(f) + f.args.foldLeft[Environment[Id, Type]](tenv)((env, p) => { env.add(p.name, p.typ)}) + case program.prev(f@FuncDef(name, args, ret, body))=> + context(f).add(f.name, typeCheck(f)) + case program.prev(m@ModuleDef(name, inputs, modules, ret, body)) => + context(m).add(m.name, typeCheck(m)) + case program.prev(cc@CirConnect(name, c)) => context(cc).add(name, checkCirExpr(c)) + case program.parent(p) => context(p) + case program.root => TypeEnv() + } + } + + //Module parameters can't be given a proper type during parsing if they refer to another module + //This uses module names in the type environment to lookup their already checked types + private def replaceNamedType(t: Type, mod: ModuleDef): Type = t match { + case TNamedType(name) => context(mod)(name) + case _ => t + } + + val typeCheck: ProgramNode => Type = { + attr { + //used to get the defined type of a node + case program.next(program.parent(p@CAssign(lhs@EVar(id), rhs, typ))) => typ.get + case program.next(program.parent(p@CRecv(lhs@EVar(id), rhs, typ))) => typ.get + case program.parent.pair(id: Id, evar: EVar) => typeCheck(evar) + case program.parent.pair(id: Id, mod: ModuleDef) => typeCheck(mod) + case program.parent.pair(id: Id, func: FuncDef) => typeCheck(func) + case i:Id => context(i)(i) + case ce: CirExpr => checkCirExpr(ce) + case e: Syntax.Expr => checkExpr(e) + case m: ModuleDef => //TODO disallow memories + val inputTyps = m.inputs.foldLeft[List[Type]](List())((l, p) => { l :+ p.typ }) + //TODO require memory or module types + val modTyps = m.modules.foldLeft[List[Type]](List())((l, p) => { l :+ replaceNamedType(p.typ, m) }) + TModType(inputTyps, modTyps, m.ret, Some(m.name)) + case f: FuncDef => + val typList = f.args.foldLeft[List[Type]](List())((l, p) => { l :+ p.typ }) //TODO disallow memories as params + TFun(typList, f.ret) + + } + } + + private def checkExpr(e: Expr): Type = { + val tenv = context(e) + e match { + case Syntax.EInt(v, base, bits) => TSizedInt(TBitWidthLen(bits), unsigned = true) + case Syntax.EString(v) =>TString() + case Syntax.EBool(v) =>TBool() + case Syntax.EUop(op, ex) => + val t1= typeCheck(ex) + op match { + case BoolUOp(op) => t1.matchOrError(e.pos, "boolean op", "boolean") { case _: TBool => TBool() } + case NumUOp(op) => t1.matchOrError(e.pos, "number op", "number") { case t: TSizedInt => t } + case BitUOp(op) => t1.matchOrError(e.pos, "bit op", "sized integer") { case t: TSizedInt => t } + } + case Syntax.EBinop(op, e1, e2) => + val t1 = typeCheck(e1) + val t2 = typeCheck(e2) + op match { + case BitOp("++", _) => (t1, t2) match { + case (TSizedInt(l1, u1), TSizedInt(l2, u2)) if u1 == u2 => TSizedInt(TBitWidthLen(l1.asInstanceOf[TBitWidthLen].len + l2.asInstanceOf[TBitWidthLen].len), u1) + case (_, _) => throw UnexpectedType(e.pos, "concat", "sized number", t1) + } + case BitOp("<<", _) => (t1, t2) match { + case (TSizedInt(l1, u1), TSizedInt(_, _)) => TSizedInt(l1, u1) + } + case BitOp(">>", _) => (t1, t2) match { + case (TSizedInt(l1, u1), TSizedInt(_, _)) => TSizedInt(l1, u1) + } + case NumOp("*", _) => (t1, t2) match { + case (TSizedInt(l1, u1), TSizedInt(l2, u2)) if u1 == u2 => TSizedInt(TBitWidthLen(l1.asInstanceOf[TBitWidthLen].len + l2.asInstanceOf[TBitWidthLen].len), u1) + case (_, _) => throw UnexpectedType(e.pos, "concat", "sized number", t1) + } + case _ => if (!areEqual(t1, t2)) { throw UnexpectedType(e2.pos, e2.toString, t1.toString(), t2) } else { + op match { + case EqOp(_) => TBool() + case CmpOp(_) => TBool() + case BoolOp(_, _) => t1.matchOrError(e1.pos, "boolean op", "boolean") { case _: TBool => TBool() } + case NumOp(_, _) => t1.matchOrError(e1.pos, "number op", "number") { case t: TSizedInt => t} + case BitOp(_, _) => t1.matchOrError(e1.pos, "bit op", "sized integer") { case t: TSizedInt => t } + } + } + } + case Syntax.ERecAccess(rec, fieldName) => + val rt = typeCheck(rec) + rt match { + case TRecType(n, fs) => fs.get(fieldName) match { + case Some(t) => t + case _ => throw MissingType(fieldName.pos, s"Field $n. ${fieldName.v}") + } + case _ => throw UnexpectedType(e.pos, "record access", "record type", rt) + } + case Syntax.ERecLiteral(fields) => + val ftyps = fields map { case (n, e) => (n, typeCheck(e)) } + TRecType(Id("anon"), ftyps)//TODO these are wrong, maybe just remove these + case Syntax.EMemAccess(mem, index) => + val memt = tenv(mem) + val idxt= typeCheck(index) + (memt, idxt) match { + case (TMemType(e, s, _, _), TSizedInt(l, true)) if l.asInstanceOf[TBitWidthLen].len == s => e + case _ => throw UnexpectedType(e.pos, "memory access", "mismatched types", memt) + } + case Syntax.EBitExtract(num, start, end) => + val ntyp = typeCheck(num) + val bitsLeft = math.abs(end - start) + 1 + ntyp.matchOrError(e.pos, "bit extract", "sized number") { + case TSizedInt(l, u) if l.asInstanceOf[TBitWidthLen].len >= bitsLeft => TSizedInt(TBitWidthLen(bitsLeft), u) + case _ => throw UnexpectedType(e.pos, "bit extract", "sized number larger than extract range", ntyp) + } + case Syntax.ETernary(cond, tval, fval) => + val ctyp = typeCheck(cond) + ctyp.matchOrError(cond.pos, "ternary condition", "boolean") { case _: TBool => () } + val ttyp = typeCheck(tval) + val ftyp = typeCheck(fval) + if (areEqual(ttyp, ftyp)) ttyp + else throw UnexpectedType(e.pos, "ternary", s"false condition must match ${ttyp.toString}", ftyp) + case Syntax.EApp(func, args) => + val ftyp = tenv(func) + ftyp match { + case TFun(targs, tret) => { + if (targs.length != args.length) { + throw ArgLengthMismatch(e.pos, targs.length, args.length) + } + targs.zip(args).foreach { + case (expectedT, a) => + val atyp = typeCheck(a) + if (!isSubtype(atyp, expectedT)) { + throw UnexpectedSubtype(e.pos, a.toString, expectedT, atyp) + } + } + tret + } + case _ => throw UnexpectedType(func.pos, "function call", "function type", ftyp) + } + case Syntax.ECall(mod, args) => + val mtyp = tenv(mod) + mtyp match { + case TModType(inputs, _, retType, _) => { + if (inputs.length != args.length) { + throw ArgLengthMismatch(e.pos, inputs.length, args.length) + } + inputs.zip(args).foreach { + case (expectedT, a) => + val atyp = typeCheck(a) + if (!isSubtype(atyp, expectedT)) { + throw UnexpectedSubtype(e.pos, a.toString, expectedT, atyp) + } + } + if (retType.isDefined) retType.get else TVoid() + } + case _ => throw UnexpectedType(mod.pos, "module name", "module type", mtyp) + } + case EVar(id) => tenv(id) + case Syntax.ECast(ctyp, exp) => + val etyp = typeCheck(exp) + (ctyp, etyp) match { + case (t1, t2) if !areEqual(t1, t2) => throw IllegalCast(e.pos, t1, t2) + case _ => () + } + ctyp + case _ => print(e); throw UnexpectedCase(e.pos) + } + } + + private def checkCirExpr(c: CirExpr): Type = { + val tenv = context(c) + c match { + case CirMem(elemTyp, addrSize) => { + val mtyp = TMemType(elemTyp, addrSize, Asynchronous, Asynchronous) + mtyp + } + case CirRegFile(elemTyp, addrSize) => { + val mtyp = TMemType(elemTyp, addrSize, Combinational, Sequential) + mtyp + } + case CirNew(mod, mods) => { + val mtyp = context(c)(mod) + mtyp match { + case TModType(_, refs, _, _) => { + if(refs.length != mods.length) { + throw ArgLengthMismatch(c.pos, mods.length, refs.length) + } + refs.zip(mods).foreach { + case (reftyp, mname) => { + if (!(isSubtype(tenv(mname), reftyp))) { + throw UnexpectedSubtype(mname.pos, mname.toString, reftyp, tenv(mname)) + } + } + } + mtyp + } + case x => throw UnexpectedType(c.pos, c.toString, "Module Type", x) + } + } + case CirCall(mod, inits) => { + val mtyp = tenv(mod) + mtyp match { + case TModType(ityps, _, _, _) => { + if(ityps.length != inits.length) { + throw ArgLengthMismatch(c.pos, inits.length, ityps.length) + } + ityps.zip(inits).foreach { + case (expectedT, arg) => { + val atyp = typeCheck(arg) + if (!isSubtype(atyp, expectedT)) { + throw UnexpectedSubtype(arg.pos, arg.toString, expectedT, atyp) + } + } + } + mtyp + } + case x => throw UnexpectedType(c.pos, c.toString, "Module Type", x) + } + } + } + } +} + +object TypeAnalysis extends Attribution with AnalysisProvider[TypeAnalysis] { + val instance: Prog => TypeAnalysis = + attr { + case p => new TypeAnalysis(new Tree[ProgramNode, Prog](p)) + } + override def get(program: Prog): TypeAnalysis = instance(program) +} diff --git a/src/main/scala/pipedsl/analysis/TypeInference.scala b/src/main/scala/pipedsl/analysis/TypeInference.scala new file mode 100644 index 00000000..4d45337b --- /dev/null +++ b/src/main/scala/pipedsl/analysis/TypeInference.scala @@ -0,0 +1,505 @@ +package pipedsl.analysis + +import pipedsl.common.Errors.{ArgLengthMismatch, MalformedLockTypes, UnexpectedReturn, UnexpectedSubtype, UnexpectedType, UnificationError} +import pipedsl.common.Syntax._ +import pipedsl.typechecker.Subtypes.{areEqual, isSubtype} +import pipedsl.common.Errors +import pipedsl.common.Syntax.Latency.{Asynchronous, Combinational, Sequential} +import pipedsl.typechecker.Environments.{Environment, TypeEnv} + +object TypeInference { + + type Subst = List[(Id, Type)] + private var currentDef: Id = Id("-invalid-") + private var counter = 0 + + def checkProgram(p: Prog): Environment[Id, Type] = { + val funcEnvs = p.fdefs.foldLeft[Environment[Id, Type]](TypeEnv())( + (env, f) => { + currentDef = f.name + checkFunc(f, env.asInstanceOf[TypeEnv]) + }) + val modEnvs = p.moddefs.foldLeft[Environment[Id, Type]](funcEnvs)( + (env, m) => { + currentDef = m.name + checkModule(m, env.asInstanceOf[TypeEnv]) + }) + checkCircuit(p.circ, modEnvs) + } + + def checkCircuit(c: Circuit, tenv: Environment[Id, Type]): Environment[Id, Type] = c match { + case CirSeq(c1, c2) => { + val e1 = checkCircuit(c1, tenv) + checkCircuit(c2, e1) + } + case CirConnect(name, c) => + val (t, env2) = checkCirExpr(c, tenv) + env2.add(name, t) + case CirExprStmt(ce) => checkCirExpr(ce, tenv)._2 + } + + private def checkCirExpr(c: CirExpr, tenv: Environment[Id, Type]): (Type, Environment[Id, Type]) = c match { + case CirMem(elemTyp, addrSize) => { + val mtyp = TMemType(elemTyp, addrSize, Asynchronous, Asynchronous) + (mtyp, tenv) + } + case CirRegFile(elemTyp, addrSize) => { + val mtyp = TMemType(elemTyp, addrSize, Combinational, Sequential) + (mtyp, tenv) + } + case CirNew(mod, mods) => { + val mtyp = tenv(mod) + mtyp match { + case TModType(_, refs, _, _) => { + if(refs.length != mods.length) { + throw ArgLengthMismatch(c.pos, mods.length, refs.length) + } + refs.zip(mods).foreach { + case (reftyp, mname) => { + if (!(isSubtype(tenv(mname), reftyp))) { + throw UnexpectedSubtype(mname.pos, mname.toString, reftyp, tenv(mname)) + } + } + } + (mtyp, tenv) + } + case x => throw UnexpectedType(c.pos, c.toString, "Module Type", x) + } + } + case CirCall(mod, inits) => { + val mtyp = tenv(mod) + mtyp match { + case TModType(ityps, _, _, _) => { + if(ityps.length != inits.length) { + throw ArgLengthMismatch(c.pos, inits.length, ityps.length) + } + ityps.zip(inits).foreach { + case (expectedT, arg) => { + val (subst, atyp, aenv) = infer(tenv.asInstanceOf[TypeEnv], arg) + if (!isSubtype(atyp, expectedT)) { + throw UnexpectedSubtype(arg.pos, arg.toString, expectedT, atyp) + } + } + } + (mtyp, tenv) + } + case x => throw UnexpectedType(c.pos, c.toString, "Module Type", x) + } + } + } + + def checkModule(m: ModuleDef, env: TypeEnv): Environment[Id, Type] = { + val inputTypes = m.inputs.map(p => p.typ) + val modTypes = m.modules.map(m => replaceNamedType(m.typ, env)) + val modEnv = env.add(m.name, TModType(inputTypes, modTypes, m.ret, Some(m.name))) + val inEnv = m.inputs.foldLeft[Environment[Id, Type]](modEnv)((env, p) => env.add(p.name, p.typ)) + val pipeEnv = m.modules.zip(modTypes).foldLeft[Environment[Id, Type]](inEnv)((env, m) => env.add(m._1.name, m._2)) + checkCommand(m.body, pipeEnv.asInstanceOf[TypeEnv], List()) + modEnv + } + + def checkFunc(f: FuncDef, env: TypeEnv): Environment[Id, Type] = { + val inputTypes = f.args.map(a => a.typ) + val funType = TFun(inputTypes, f.ret) + val funEnv = env.add(f.name, funType) + val inEnv = f.args.foldLeft[Environment[Id, Type]](funEnv)((env, a) => env.add(a.name, a.typ)) + checkCommand(f.body, inEnv.asInstanceOf[TypeEnv], List()) + funEnv + } + + private def replaceNamedType(t: Type, tenv: TypeEnv): Type = t match { + case TNamedType(name) => tenv(name) + case _ => t + } +//INVARIANTS +//Transforms the argument sub by composing any additional substitution +//Transforms the argument env by subbing in the returned substitution and adding any relevatn variables + def checkCommand(c: Command, env: TypeEnv, sub: Subst): (TypeEnv, Subst) = { + c match { + case CLockOp(mem, op) => //test basic first + env(mem.id) match { + case t@TMemType(elem, addrSize, readLatency, writeLatency) => mem.evar match { + case Some(value) => + val (s, t, e) = infer(env, value) + val tempSub = compose_subst(sub, s) + val tNew = apply_subst_typ(tempSub, t) + val newSub = compose_subst(tempSub, unify(tNew, TSizedInt(TBitWidthLen(addrSize), true))) + (e.apply_subst_typeenv(newSub), newSub) + case None => (env, sub) + } + case TModType(inputs, refs, retType, name) => + if (mem.evar.isDefined) throw MalformedLockTypes("Pipeline modules can not have specific locks") + (env, sub) + case b => throw UnexpectedType(mem.id.pos, c.toString, "Memory or Module Type", b) + } + case CEmpty() => (env, sub) + case CReturn(exp) => + val (s, t, e) = infer(env, exp) + val tempSub = compose_subst(sub, s) + val tNew = apply_subst_typ(tempSub, t) + val funT = env(currentDef) + funT match { + case TFun(args, ret) => + val retSub = compose_subst(tempSub, unify(tNew, ret)) + (e.apply_subst_typeenv(retSub), retSub) + case b => throw UnexpectedType(c.pos, c.toString, funT.toString, b) + } + case CLockStart(mod) => + if(!(env(mod).isInstanceOf[TMemType] || env(mod).isInstanceOf[TModType])) { + throw UnexpectedType(mod.pos, c.toString, "Memory or Module Type", env(mod)) + } + (env, sub) + case CIf(cond, cons, alt) => + val (condS, condT, env1) = infer(env, cond) + val tempSub = compose_subst(sub, condS) + val condTyp = apply_subst_typ(tempSub, condT) + val newSub = compose_subst(tempSub, unify(condTyp, TBool())) + val newEnv = env1.apply_subst_typeenv(newSub) + val (consEnv, consSub) = checkCommand(cons, newEnv, newSub) + val newEnv2 = newEnv.apply_subst_typeenv(consSub) + val (altEnv, altSub) = checkCommand(alt, newEnv2, consSub) + //TODO: Intersection of both envs? + (consEnv.apply_subst_typeenv(altSub).intersect(altEnv).asInstanceOf[TypeEnv], altSub) + case CLockEnd(mod) => + if(!(env(mod).isInstanceOf[TMemType] || env(mod).isInstanceOf[TModType])) { + throw UnexpectedType(mod.pos, c.toString, "Memory or Module Type", env(mod)) + } + (env, sub) + case CSplit(cases, default) => //TODO + var (runningEnv, runningSub) = checkCommand(default, env, sub) + for (c <- cases) { + val (condS, condT, env1) = infer(env, c.cond) + val tempSub = compose_subst(runningSub, condS) + val condTyp = apply_subst_typ(tempSub, condT) + val newSub = compose_subst(tempSub, unify(condTyp, TBool())) + //apply substitution to original environmnet, which you will use to check the body + val newEnv = env1.apply_subst_typeenv(newSub) + val (caseEnv, caseSub) = checkCommand(c.body, newEnv, newSub) + runningSub = caseSub + runningEnv = runningEnv.apply_subst_typeenv(runningSub).intersect(caseEnv).asInstanceOf[TypeEnv] + } + (runningEnv, runningSub) + case CExpr(exp) => + val (s, t, e) = infer(env, exp) + val retS = compose_subst(sub, s) + (e.apply_subst_typeenv(retS), retS) //TODO + case CCheck(predVar) => (env, sub) + case CTBar(c1, c2) => + val (e, s) = checkCommand(c1, env, sub) + val (e2, s2) = checkCommand(c2, e, s) + (e2, s2) + case CPrint(evar) => (env, sub) + //how to unify or conditions> This I guess is an polymorphic function with restrictions + case CSpeculate(predVar, predVal, verify, body) => (env, sub) + case COutput(exp) => + val (s, t, e) = infer(env, exp) + val tempSub = compose_subst(sub, s) + val tNew = apply_subst_typ(tempSub, t) + val modT = env(currentDef) + modT match { + case TModType(inputs, refs, retType, name) => + retType match { + case Some(value) => + val retSub = compose_subst(tempSub, unify(tNew, value)) + (e.apply_subst_typeenv(retSub), retSub) + case None => (e.apply_subst_typeenv(tempSub), tempSub) + } + case b => throw UnexpectedType(c.pos, c.toString, modT.toString, b) + } + //How to check wellformedness with the module body + case CRecv(lhs, rhs, typ) => + val (slhs, tlhs, lhsEnv) = lhs match { + case EVar(id) => (List(), typ.getOrElse(generateTypeVar()), env) + case _ => infer(env, lhs) + } + val (srhs, trhs, rhsEnv) = infer(lhsEnv, rhs) + val tempSub = compose_many_subst(sub, slhs, srhs) + val lhstyp = apply_subst_typ(tempSub, tlhs) + val rhstyp = apply_subst_typ(tempSub, trhs) + val s1 = unify(rhstyp, lhstyp) + val sret = compose_many_subst(tempSub, s1, typ match { + case Some(value) => compose_subst(unify(lhstyp, value), unify(rhstyp, value)) + case None => List() + }) + val newEnv = lhs match { + case EVar(id) => rhsEnv.add(id, tlhs) + case _ => rhsEnv + } + (newEnv.asInstanceOf[TypeEnv].apply_subst_typeenv(sret), sret) + case CAssign(lhs, rhs, typ) => + val (slhs, tlhs, lhsEnv) = (List(), typ.getOrElse(generateTypeVar()), env) + val (srhs, trhs, rhsEnv) = infer(lhsEnv, rhs) + val tempSub = compose_many_subst(sub, slhs, srhs) + val lhstyp = apply_subst_typ(tempSub, tlhs) + val rhstyp = apply_subst_typ(tempSub, trhs) + val s1 = unify(rhstyp, lhstyp) + val sret = compose_many_subst(tempSub, s1, typ match { + case Some(value) => compose_subst(unify(lhstyp, value), unify(rhstyp, value)) + case None => List() + }) + val newEnv = lhs match { + case EVar(id) => rhsEnv.add(id, tlhs) + case _ => rhsEnv + } + (newEnv.asInstanceOf[TypeEnv].apply_subst_typeenv(sret), sret) + case CSeq(c1, c2) => + val (e1, s) = checkCommand(c1, env, sub) + val (e2, s2) = checkCommand(c2, e1, s) + (e2, s2) +} + } + + private def generateTypeVar(): TNamedType = { + counter += 1 + TNamedType(Id("__TYPE__" + counter)) + } + + private def generateBitWidthTypeVar(): TBitWidthVar = { + counter += 1 + TBitWidthVar(Id("__BITWIDTH__" + counter)) + } + + private def occursIn(name: Id, b: Type): Boolean = b match { + case TSizedInt(len, unsigned) => occursIn(name, len) + case TString() => false + case TVoid() => false + case TBool() => false + case TFun(args, ret) => args.foldLeft[Boolean](false)((b, t) => b || occursIn(name, t)) || occursIn(name, ret) + case TRecType(name, fields) =>false + case TMemType(elem, addrSize, readLatency, writeLatency) => false + case TModType(inputs, refs, retType, name) => false + case TNamedType(name1) => name1 == name + case TBitWidthVar(name1) => name1 == name + case TBitWidthAdd(b1, b2) => occursIn(name, b1) || occursIn(name, b2) + case TBitWidthMax(b1, b2) => occursIn(name, b1) || occursIn(name, b2) + case TBitWidthLen(len) => false + } + + private def subst_into_type(typevar: Id, toType: Type, inType: Type): Type = inType match { + case t@TMemType(elem, addrSize, readLatency, writeLatency) => t.copy(elem=subst_into_type(typevar, toType, elem)) + case TSizedInt(len, unsigned) => TSizedInt(subst_into_type(typevar, toType, len).asInstanceOf[TBitWidth], unsigned) + case TString() => inType + case TBool() => inType + case TVoid() => inType + case TFun(args, ret) => TFun(args.map(a=>subst_into_type(typevar, toType, a)), subst_into_type(typevar, toType, ret)) + case TNamedType(name) => if(name == typevar) toType else inType + case TModType(inputs, refs, retType, name) => + TModType( + inputs.map(i => subst_into_type(typevar, toType, i)), + refs.map(r => subst_into_type(typevar, toType, r)), + retType match { + case Some(value) => Some(subst_into_type(typevar, toType, value)) + case None => None + }, name) + case t: TBitWidth => + t match { + case TBitWidthVar(name) => if (name == typevar) toType else inType + case TBitWidthLen(len) => inType + case TBitWidthAdd(b1, b2) => + val t1 = TBitWidthAdd(subst_into_type(typevar, toType, b1).asInstanceOf[TBitWidth], subst_into_type(typevar, toType, b2).asInstanceOf[TBitWidth]) + (t1.b1, t1.b2) match { + case (TBitWidthLen(len1), TBitWidthLen(len2)) => TBitWidthLen(len1 + len2) + case _ => t1 + } + case TBitWidthMax(b1, b2) => + val t1 = TBitWidthMax(subst_into_type(typevar, toType, b1).asInstanceOf[TBitWidth], subst_into_type(typevar, toType, b2).asInstanceOf[TBitWidth]) + (t1.b1, t1.b2) match { + case (TBitWidthLen(len1), TBitWidthLen(len2)) => TBitWidthLen(len1.max(len2)) + case _ => t1 + } + } + } + + def apply_subst_typ(subst: Subst, t: Type): Type = subst.foldLeft[Type](t)((t1, s) => subst_into_type(s._1, s._2, t1)) + + private def apply_subst_substs(subst: Subst, inSubst: Subst): Subst = + inSubst.foldLeft[Subst](List())((s, c) => s :+ ((c._1, apply_subst_typ(subst, c._2)))) + + private def compose_subst(sub1: Subst, sub2: Subst): Subst = + sub1 ++ apply_subst_substs(sub1, sub2) + + private def compose_many_subst(subs: Subst*): Subst = + subs.foldRight[Subst](List())((s1, s2) => compose_subst(s1, s2)) + + //for subtyping bit widths, t1 is the subtype, t2 is the supertype. so t2 is the expected + private def unify(a: Type, b: Type): Subst = (a,b) match { + case (t1: TNamedType, t2) => if (!occursIn(t1.name, t2)) List((t1.name, t2)) else List() + case (t1, t2: TNamedType) => if (!occursIn(t2.name, t1)) List((t2.name, t1)) else List() + case (_:TString, _:TString) => List() + case (_: TBool, _:TBool) => List() + case (_: TVoid, _:TVoid) => List() + case (TSizedInt(len1, unsigned1), TSizedInt(len2, unsigned)) => unify(len1, len2) + //TODO: TSIZEDINT + case (TFun(args1, ret1), TFun(args2, ret2)) if args1.length == args2.length => + val s1 = args1.zip(args2).foldLeft[Subst](List())((s, t) => compose_subst(s, unify(apply_subst_typ(s, t._1), apply_subst_typ(s, t._2)))) + compose_subst(s1, unify(apply_subst_typ(s1, ret1), apply_subst_typ(s1, ret2))) + case (TModType(input1, refs1, retType1, name1), TModType(input2, refs2, retType2, name2)) => + //TODO: Name?\ + if (name1 != name2) throw UnificationError(a,b) + val s1 = input1.zip(input2).foldLeft[Subst](List())((s, t) => compose_subst(s, unify(apply_subst_typ(s, t._1), apply_subst_typ(s, t._2)))) + val s2 = refs1.zip(refs2).foldLeft[Subst](s1)((s,t) => compose_subst(s, unify(apply_subst_typ(s, t._1), apply_subst_typ(s, t._2)))) + compose_subst(s2, + ((retType1, retType2) match { + case (Some(t1:Type), Some(t2:Type)) => unify(apply_subst_typ(s2, t1), apply_subst_typ(s2,t2)) + case (None, None) => List() + case _ => throw UnificationError(a,b) + })) + case (TMemType(elem1, addrSize1, readLatency1, writeLatency1), TMemType(elem2, addrSize2, readLatency2, writeLatency2)) => + if (addrSize1 != addrSize2 || readLatency1 != readLatency2 || writeLatency1 != writeLatency2) throw UnificationError(a, b) + unify(elem1, elem2) + case (t1: TBitWidthVar, t2: TBitWidth) => if(!occursIn(t1.name, t2)) List((t1.name, t2)) else List() + case (t1: TBitWidth, t2: TBitWidthVar) => if(!occursIn(t2.name, t1)) List((t2.name, t1)) else List() + case (t1: TBitWidthLen, t2: TBitWidthLen) => if (t2.len < t1.len) throw UnificationError(t1, t2) else List() //TODO: need to figure this out: we want this subtyping rule to throw error when its being used, but not when its a binop!!! + case _ => throw UnificationError(a, b) + } + + //Updating the type environment with the new substitution whenever you generate one allows errors to be found :D + //The environment returned is guaratneed to already have been substituted into with the returned substitution + private def infer(env: TypeEnv, e: Expr): (Subst, Type, TypeEnv) = e match { + case EInt(v, base, bits) => (List(), TSizedInt(TBitWidthLen(bits), true), env) + case EString(v) => (List(), TString(), env) + case EBool(v) => (List(), TBool(), env) + case EUop(op, ex) => + val (s, t, env1) = infer(env, ex) + val retType = generateTypeVar() + val tNew = apply_subst_typ(s, t) + val subst = unify(TFun(List(tNew), retType), uOpExpectedType(op)) + val retSubst = compose_subst(s, subst) + val retTyp = apply_subst_typ(retSubst, retType) + (retSubst, retTyp, env1.apply_subst_typeenv(retSubst)) + case EBinop(op, e1, e2) => + val (s1, t1, env1) = infer(env, e1) + val (s2, t2, env2) = infer(env1, e2) + val retType = generateTypeVar() + val subTemp = compose_subst(s1, s2) + val t1New = apply_subst_typ(subTemp, t1) + val t2New = apply_subst_typ(subTemp, t2) + val subst = unify(TFun(List(t1New,t2New), retType), binOpExpectedType(op)) + val retSubst = compose_many_subst(subTemp, subst) + val retTyp = apply_subst_typ(retSubst, retType) + (retSubst, retTyp, env2.apply_subst_typeenv(retSubst)) + case EMemAccess(mem, index) => + if(!env(mem).isInstanceOf[TMemType]) throw UnexpectedType(e.pos, "Memory Access", "TMemtype", env(mem)) + val retType = generateTypeVar() + val (s, t, env1) = infer(env, index) + val tTemp = apply_subst_typ(s, t) + val subst = unify(TFun(List(tTemp), retType), getMemAccessType(env1(mem).asInstanceOf[TMemType])) + val retSubst = compose_subst(s,subst) + val retTyp = apply_subst_typ(retSubst, retType) + (retSubst, retTyp, env1.apply_subst_typeenv(retSubst)) + case EBitExtract(num, start, end) => + val (s, t, e) = infer(env, num) + t match { + case TSizedInt(TBitWidthLen(len), unsigned) if len >= (math.abs(end - start) + 1) => (s, TSizedInt(TBitWidthLen(math.abs(end - start) + 1), true), e) + case b => throw UnificationError(b, TSizedInt(TBitWidthLen(32), true)) //TODO Add better error message + } + //TODO + case ETernary(cond, tval, fval) => + val (sc, tc, env1) = infer(env, cond) + val (st, tt, env2) = infer(env1, tval) + val (sf, tf, env3) = infer(env2, fval) + val substSoFar = compose_many_subst(sc, st, sf) + val tcNew = apply_subst_typ(substSoFar, tc) + val ttNew = apply_subst_typ(substSoFar, tt) + val tfNew = apply_subst_typ(substSoFar, tf) + val substc = unify(tcNew, TBool()) + val subst = unify(ttNew, tfNew) //TODO this will fail with bad subtyping stuff going on currently bc for sized ints, we don't care which one is bigger right + val retSubst = compose_many_subst(sc, st, sf, substc, subst) + val retType = apply_subst_typ(retSubst, ttNew) + (retSubst, retType, env3.apply_subst_typeenv(retSubst)) + case EApp(func, args) => + val expectedType = env(func) + val retType = generateTypeVar() + var runningEnv: TypeEnv = env + var runningSubst: Subst = List() + var typeList: List[Type] = List() + for (a <- args) { + val (sub, typ, env1) = infer(runningEnv, a) + runningSubst = compose_subst(runningSubst, sub) + typeList = typeList :+ typ + runningEnv = env1 + } + typeList = typeList.map(t => apply_subst_typ(runningSubst, t)) + val subst = unify(TFun(typeList, retType), expectedType) + val retSubst = compose_subst(runningSubst, subst) + val retEnv = runningEnv.apply_subst_typeenv(retSubst) + val retTyp = apply_subst_typ(retSubst, retType) + (retSubst, retTyp, retEnv) + case ECall(mod, args) => + if (!env(mod).isInstanceOf[TModType]) throw UnexpectedType(e.pos, "Module Call", "TModType", env(mod)) + val expectedType = getArrowModType(env(mod).asInstanceOf[TModType]) + val retType = generateTypeVar() + var runningEnv: TypeEnv = env + var runningSubst: Subst = List() + var typeList: List[Type] = List() + for (a <- args) { + val (sub, typ, env1) = infer(runningEnv, a) + runningSubst = compose_subst(runningSubst, sub) + typeList = typeList :+ typ + runningEnv = env1 + } + typeList = typeList.map(t=> apply_subst_typ(runningSubst, t)) + val subst = unify(TFun(typeList, retType), expectedType) + val retSubst = compose_subst(runningSubst, subst) + val retEnv = runningEnv.apply_subst_typeenv(retSubst) + val retTyp = apply_subst_typ(retSubst, retType) + (retSubst, retTyp, retEnv) + case EVar(id) => (List(), env(id), env) + case ECast(ctyp, exp) => + //TODO this is wrong probably + val (s, t, env1) = infer(env, exp) + val newT = apply_subst_typ(s, t) + if (!areEqual(ctyp, newT)) throw Errors.IllegalCast(e.pos, ctyp, newT) + (s, ctyp, env1) + } + + + private def binOpExpectedType(b: BOp): Type = b match { + case EqOp(op) => + val t = generateTypeVar() // TODO: This can be anything? + TFun(List(t, t), TBool()) + case CmpOp(op) => TFun(List(TSizedInt(generateBitWidthTypeVar(), true), TSizedInt(generateBitWidthTypeVar(), true)), TBool())//TODO: TSizedInt? + case BoolOp(op, fun) => TFun(List(TBool(), TBool()), TBool()) + case NumOp(op, fun) => + val b1 = generateBitWidthTypeVar() + val b2 = generateBitWidthTypeVar() + op match { + case "/" => TFun(List(TSizedInt(b1, true), TSizedInt(b2, true)), TSizedInt(b1, true)) + case "*" => TFun(List(TSizedInt(b1, true), TSizedInt(b2, true)), TSizedInt(TBitWidthAdd(b1, b2), true)) + case "+" => TFun(List(TSizedInt(b1, true), TSizedInt(b2, true)), TSizedInt(TBitWidthMax(b1, b2), true)) + case "-" => TFun(List(TSizedInt(b1, true), TSizedInt(b2, true)), TSizedInt(TBitWidthMax(b1, b2), true)) + case "%" => TFun(List(TSizedInt(b1, true), TSizedInt(b2, true)), TSizedInt(b1, true)) + } + case BitOp(op, fun) => + val b1 = generateBitWidthTypeVar() + val b2 = generateBitWidthTypeVar() + op match { + case "++" => TFun(List(TSizedInt(b1, true), TSizedInt(b2, true)), TSizedInt(TBitWidthAdd(b1, b2), true)) + case _ => TFun(List(TSizedInt(b1, true), TSizedInt(b2, true)), TSizedInt(b1, true)) + } + } + + private def uOpExpectedType(u: UOp): Type = u match { + case BitUOp(op) => + val b1 = generateBitWidthTypeVar() + //TODO: Fix this + TFun(List(TSizedInt(b1, true)), TSizedInt(b1, true)) + case BoolUOp(op) => TFun(List(TBool()), TBool()) + case NumUOp(op) => + val b1 = generateBitWidthTypeVar() + TFun(List(TSizedInt(b1, true)), TSizedInt(b1, true)) + + } + + private def getArrowModType(t: TModType): TFun = { + TFun(t.inputs, t.retType match { + case None => TVoid() + case Some(value) => value + }) + } + + private def getMemAccessType(t: TMemType): TFun = { + TFun(List(TSizedInt(TBitWidthLen(t.addrSize), unsigned=true)), t.elem) + } + +} diff --git a/src/main/scala/pipedsl/codegen/bsv/BSVSyntax.scala b/src/main/scala/pipedsl/codegen/bsv/BSVSyntax.scala index 3a9d1607..70eacecb 100644 --- a/src/main/scala/pipedsl/codegen/bsv/BSVSyntax.scala +++ b/src/main/scala/pipedsl/codegen/bsv/BSVSyntax.scala @@ -1,5 +1,6 @@ package pipedsl.codegen.bsv +import pipedsl.analysis.TypeAnalysis import pipedsl.common.Errors.{UnexpectedBSVType, UnexpectedCommand, UnexpectedExpr, UnexpectedType} import pipedsl.common.Syntax.Latency.Combinational import pipedsl.common.Syntax._ @@ -26,7 +27,7 @@ object BSVSyntax { case object BEmptyModule extends BSVType class BSVTranslator(val bsints: BluespecInterfaces, - val modmap: Map[Id, BSVType] = Map(), val handleMap: Map[BSVType, BSVType] = Map()) { + val modmap: Map[Id, BSVType] = Map(), val handleMap: Map[BSVType, BSVType] = Map(), val typeAnalysis: TypeAnalysis) { private var variablePrefix = "" @@ -37,7 +38,7 @@ object BSVSyntax { bsints.getMemType(isAsync = rlat != Combinational, BSizedInt(unsigned = true, addrSize), toBSVType(elem), Some(bsints.getDefaultMemHandleType)) - case TSizedInt(len, unsigned) => BSizedInt(unsigned, len) + case TSizedInt(len, unsigned) => BSizedInt(unsigned, len.asInstanceOf[TBitWidthLen].len) case TBool() => BBool case TString() => BString case TModType(_, _, _, Some(n)) => modmap(n) @@ -46,15 +47,15 @@ object BSVSyntax { if (isLock) { BInterface("Maybe", List(BVar("basehandletyp", bsints.getDefaultLockHandleType))) } else { - val modtyp = toBSVType(n.typ.get) + val modtyp = toBSVType(typeAnalysis.typeCheck(n)) if (handleMap.contains(modtyp)) { handleMap(modtyp) } else { //if not in the handle map, use the appropriate default handle size. If the //handle is for a normal module then there is no default - n.typ.get match { + typeAnalysis.typeCheck(n) match { case _: TMemType => bsints.getDefaultMemHandleType - case _ => throw UnexpectedType(n.pos, "Module request handle", "A defined module req type", n.typ.get) + case _ => throw UnexpectedType(n.pos, "Module request handle", "A defined module req type", typeAnalysis.typeCheck(n)) } } } @@ -71,7 +72,7 @@ object BSVSyntax { } def toBSVVar(i: Id): BVar = { - BVar(variablePrefix + i.v, toBSVType(i.typ.get)) + BVar(variablePrefix + i.v, toBSVType(typeAnalysis.typeCheck(i))) } def toBSVVar(v: EVar): BVar = { @@ -105,7 +106,7 @@ object BSVSyntax { case EApp(func, args) => BFuncCall(func.v, args.map(a => toBSVExpr(a))) case ERecAccess(_, _) => throw UnexpectedExpr(e) case ERecLiteral(_) => throw UnexpectedExpr(e) - case EMemAccess(mem, index) => bsints.getCombRead(BVar(mem.v, toBSVType(mem.typ.get)), toBSVExpr(index)) + case EMemAccess(mem, index) => bsints.getCombRead(BVar(mem.v, toBSVType(typeAnalysis.typeCheck(mem))), toBSVExpr(index)) case ec@ECast(_, _) => translateCast(ec) case EIsValid(ex) => BIsValid(toBSVExpr(ex)) case EInvalid => BInvalid @@ -153,14 +154,14 @@ object BSVSyntax { translateFuncBody(c1) ++ translateFuncBody(c2) case CIf(cond, cons, alt) => List(BIf(toBSVExpr(cond), translateFuncBody(cons), translateFuncBody(alt))) - case CAssign(lhs, rhs) => + case CAssign(lhs, rhs, _) => List(BDecl(toBSVVar(lhs), Some(toBSVExpr(rhs)))) case CReturn(exp) => List(BReturnStmt(toBSVExpr(exp))) case CExpr(exp) => List(BExprStmt(toBSVExpr(exp))) //TODO case Syntax.CSplit(cases, default) => - case CEmpty => List() + case CEmpty() => List() case _ => throw UnexpectedCommand(c) } } diff --git a/src/main/scala/pipedsl/codegen/bsv/BluespecGeneration.scala b/src/main/scala/pipedsl/codegen/bsv/BluespecGeneration.scala index 19c52018..2231b514 100644 --- a/src/main/scala/pipedsl/codegen/bsv/BluespecGeneration.scala +++ b/src/main/scala/pipedsl/codegen/bsv/BluespecGeneration.scala @@ -1,6 +1,7 @@ package pipedsl.codegen.bsv import BSVSyntax._ +import pipedsl.analysis.TypeAnalysis import pipedsl.common.DAGSyntax.{PStage, PipelineEdge} import pipedsl.common.Errors.{UnexpectedCommand, UnexpectedExpr, UnexpectedType} import pipedsl.common.{Locks, ProgInfo} @@ -20,7 +21,7 @@ object BluespecGeneration { debug: Boolean = false, bsInts: BluespecInterfaces, funcmodname: String = "Functions", memInit:Map[String, String] = Map(), addSubInts: Boolean = false) { - + val typeAnalysis: TypeAnalysis = TypeAnalysis.get(prog) val funcModule: String = funcmodname private val funcImport = BImport(funcmodname) @@ -38,7 +39,7 @@ object BluespecGeneration { }) val newmod = new BluespecModuleGenerator( mod, stageInfo(mod.name).head, flattenStageList(stageInfo(mod.name).tail), modtyps, modHandles, - pinfo, bsInts, debug, funcImport + pinfo, bsInts, debug, funcImport, typeAnalysis ).getBSV mapping + ( mod.name -> newmod ) }) @@ -50,7 +51,7 @@ object BluespecGeneration { }) private val translator = new BSVTranslator(bsInts, - modMap map { case (i, p) => (i, p.topModule.typ.get) }, modToHandle) + modMap map { case (i, p) => (i, p.topModule.typ.get) }, modToHandle, typeAnalysis) private val funcMap: Map[Id, BFuncDef] = prog.fdefs.foldLeft(Map[Id, BFuncDef]())((fmap, fdef) => { fmap + (fdef.name -> translator.toBSVFunc(fdef)) @@ -179,10 +180,10 @@ object BluespecGeneration { private class BluespecModuleGenerator(val mod: ModuleDef, val firstStage: PStage, val otherStages: List[PStage], val bsvMods: Map[Id, BInterface], val bsvHandles: Map[BSVType, BSVType], val progInfo: ProgInfo, - val bsInts: BluespecInterfaces, val debug:Boolean = false, val funcImport: BImport) { + val bsInts: BluespecInterfaces, val debug:Boolean = false, val funcImport: BImport, val typeAnalysis: TypeAnalysis) { private val modInfo = progInfo.getModInfo(mod.name) - private val translator = new BSVTranslator(bsInts, bsvMods, bsvHandles) + private val translator = new BSVTranslator(bsInts, bsvMods, bsvHandles, typeAnalysis) private val threadIdName = "_threadID" @@ -312,7 +313,7 @@ object BluespecGeneration { stgs.foldLeft[Map[PipelineEdge, BStructDef]](Map())((m, s) => { s.inEdges.foldLeft[Map[PipelineEdge, BStructDef]](m)((ms, e) => { var sfields = e.values.foldLeft(List[BVar]())((l, id) => { - l :+ BVar(id.v, translator.toBSVType(id.typ.get)) + l :+ BVar(id.v, translator.toBSVType(typeAnalysis.typeCheck(id))) }) if (addTId) sfields = sfields :+ threadIdVar val styp = BStruct(genStructName(e), sfields) @@ -325,7 +326,7 @@ object BluespecGeneration { private def getFirstEdgeStructInfo(stg: PStage, fieldOrder: Iterable[Id]): BStructDef = { val inedge = stg.inEdges.head //must be only one for the first stage val sfields = fieldOrder.foldLeft(List[BVar]())((l, id) => { - l :+ BVar(id.v, translator.toBSVType(id.typ.get)) + l :+ BVar(id.v, translator.toBSVType(typeAnalysis.typeCheck(id))) }) :+ threadIdVar val styp = BStruct(genStructName(inedge), sfields) BStructDef(styp, List("Bits", "Eq")) @@ -513,7 +514,7 @@ object BluespecGeneration { val pvar = translator.toBSVVar(v) body = body :+ BDecl(pvar, Some(BStructAccess(paramExpr, //but don't rename the struct field names - BVar(v.v, translator.toBSVType(v.typ.get))))) + BVar(v.v, translator.toBSVType(typeAnalysis.typeCheck(v)))))) declaredVars = declaredVars + pvar }) //only read threadIDs from an unconditional edge @@ -531,7 +532,7 @@ object BluespecGeneration { val condEdgeExpr = condIn.foldLeft[BExpr](BDontCare)((expr, edge) => { val paramExpr = bsInts.getFifoPeek(edgeParams(edge)) BTernaryExpr(translator.toBSVExpr(edge.condRecv.get), - BStructAccess(paramExpr, BVar(v.v, translator.toBSVType(v.typ.get))), + BStructAccess(paramExpr, BVar(v.v, translator.toBSVType(typeAnalysis.typeCheck(v)))), expr) }) val bvar = translator.toBSVVar(v) @@ -662,7 +663,7 @@ object BluespecGeneration { } private def getCombinationalDeclaration(cmd: Command): Option[BDecl] = cmd match { - case CAssign(lhs, _) => Some(BDecl(translator.toBSVVar(lhs), None)) + case CAssign(lhs, _, _) => Some(BDecl(translator.toBSVVar(lhs), None)) case IMemRecv(_, _, data) => data match { case Some(v) => Some(BDecl(translator.toBSVVar(v), None)) case None => None @@ -689,7 +690,7 @@ object BluespecGeneration { * @return Some(translation) if cmd is combinational, otherwise None */ private def getCombinationalCommand(cmd: Command): Option[BStatement] = cmd match { - case CAssign(lhs, rhs) => + case CAssign(lhs, rhs, _) => Some(BAssign(translator.toBSVVar(lhs), translator.toBSVExpr(rhs))) case ICondCommand(cond: Expr, cs) => val stmtlist = cs.foldLeft(List[BStatement]())((l, c) => { @@ -713,7 +714,7 @@ object BluespecGeneration { case CLockEnd(_) => None case CLockOp(_, _) => None case CCheck(_) => None - case CEmpty => None + case CEmpty() => None case _: ISpeculate => None case _: IUpdate => None case _: ICheck => None @@ -722,7 +723,7 @@ object BluespecGeneration { case _: InternalCommand => None case COutput(_) => None case CPrint(_) => None - case CRecv(_, _) => throw UnexpectedCommand(cmd) + case CRecv(_, _, _) => throw UnexpectedCommand(cmd) case CIf(_, _, _) => throw UnexpectedCommand(cmd) case CSeq(_, _) => throw UnexpectedCommand(cmd) case CTBar(_, _) => throw UnexpectedCommand(cmd) @@ -877,12 +878,12 @@ object BluespecGeneration { case _: ICheckLockFree => None case _: ICheckLockOwned => None case _: ILockNoOp => None - case CAssign(_, _) => None + case CAssign(_, _, _) => None case CExpr(_) => None - case CEmpty => None + case CEmpty() => None case _: InternalCommand => throw UnexpectedCommand(cmd) case CCheck(_) => throw UnexpectedCommand(cmd) - case CRecv(_, _) => throw UnexpectedCommand(cmd) + case CRecv(_, _, _) => throw UnexpectedCommand(cmd) case CSeq(_, _) => throw UnexpectedCommand(cmd) case CTBar(_, _) => throw UnexpectedCommand(cmd) case CIf(_, _, _) => throw UnexpectedCommand(cmd) diff --git a/src/main/scala/pipedsl/common/DAGSyntax.scala b/src/main/scala/pipedsl/common/DAGSyntax.scala index b82c301a..4b306f50 100644 --- a/src/main/scala/pipedsl/common/DAGSyntax.scala +++ b/src/main/scala/pipedsl/common/DAGSyntax.scala @@ -272,9 +272,10 @@ object DAGSyntax { def specId = Id("__spec__" + specVar.id.v) val predVar = EVar(predId) - predVar.typ = specVar.typ + //TODO Uncomment + //predVar.typ = specVar.typ //extract prediction to variable - this.addCmd(CAssign(predVar, specVal)) + //this.addCmd(CAssign(predVar, specVal)) //set pred(specId) = prediction this.addCmd(ISpeculate(specId, specVar, predVar)) //At end of verification update the predction success @@ -290,9 +291,9 @@ object DAGSyntax { * Additionally, it will send data to the head of either the true or false stages based * on the result of the condition * @param n The unique identifier for this stage - * @param cond The conditional expression - * @param trueStages The list of stages to execute if cond is true - * @param falseStages The list of stages to execute if cond is false + * @param conds The conditional expressions + * @param condStages The list of stages to execute with cond + * @param defaultStages The list of stages to execute if all conds are false * @param joinStage The stage to execute after one of the branches. */ class IfStage(n: Id, val conds: List[Expr], var condStages: List[List[PStage]], @@ -304,13 +305,11 @@ object DAGSyntax { val defaultNum = conds.size val condVar = EVar(Id("__cond" + n.v)) val intSize = log2(defaultNum) - condVar.typ = Some(TSizedInt(intSize, true)) - condVar.id.typ = condVar.typ var eTernary = ETernary(conds(defaultNum - 1), EInt(defaultNum - 1, bits = intSize), EInt(defaultNum, bits = intSize)) for(i <- defaultNum-2 to 0 by -1 ) { eTernary = ETernary(conds(i), EInt(i, bits = intSize), eTernary.copy()) } - this.addCmd(CAssign(condVar, eTernary)) + this.addCmd(CAssign(condVar, eTernary, Some(TSizedInt(TBitWidthLen(intSize), true)))) for (i <- 0 until defaultNum) { this.addEdgeTo(condStages(i).head, condSend = Some (EBinop(EqOp("=="), condVar, EInt(i, bits = intSize)))) condStages(i).last.addEdgeTo(joinStage, condRecv = Some (EBinop(EqOp("=="), condVar, EInt(i, bits = intSize)))) diff --git a/src/main/scala/pipedsl/common/Errors.scala b/src/main/scala/pipedsl/common/Errors.scala index 2b68e3a4..a210478f 100644 --- a/src/main/scala/pipedsl/common/Errors.scala +++ b/src/main/scala/pipedsl/common/Errors.scala @@ -128,4 +128,8 @@ object Errors { case class UnexpectedBSVType(msg: String) extends RuntimeException(msg) case class MalformedLockTypes(msg: String) extends RuntimeException(msg) + + case class UnificationError(t1: Type, t2: Type) extends RuntimeException( + s"Unable to unify type $t1 and type $t2" + ) } diff --git a/src/main/scala/pipedsl/common/PrettyPrinter.scala b/src/main/scala/pipedsl/common/PrettyPrinter.scala index 2de4cc30..a290ec3a 100644 --- a/src/main/scala/pipedsl/common/PrettyPrinter.scala +++ b/src/main/scala/pipedsl/common/PrettyPrinter.scala @@ -2,6 +2,7 @@ package pipedsl.common import java.io.{File, FileOutputStream, OutputStreamWriter} +import pipedsl.analysis.TypeAnalysis import pipedsl.common.DAGSyntax.{IfStage, PStage, PipelineEdge, SpecStage} import pipedsl.common.Errors.UnexpectedType import pipedsl.common.Syntax._ @@ -25,7 +26,10 @@ class PrettyPrinter(output: Option[File]) { def printHelper(s: String, i: Int): Unit = pline((" " * i) + s) + var typeAnalysis: TypeAnalysis = null + def printProgram(p: Prog): Unit = { + typeAnalysis = TypeAnalysis.get(p) p.fdefs.foreach(f => printFunction(f)) p.moddefs.foreach(m => printModule(m)) printCircuit(p.circ) @@ -85,9 +89,9 @@ class PrettyPrinter(output: Option[File]) { printCmdToString(cons, indent + 4) + "\n" + ins + "} else {\n" + printCmdToString(alt, indent + 4) + "\n" + ins + "}" - case Syntax.CAssign(lhs, rhs) => ins + (if (lhs.typ.isDefined) printTypeToString(lhs.typ.get) + " " else "") + + case Syntax.CAssign(lhs, rhs, typ) => ins + (if (typ.isDefined) printTypeToString(typeAnalysis.typeCheck(lhs)) + " " else "") + printExprToString(lhs) + " = " + printExprToString(rhs) + ";" - case Syntax.CRecv(lhs, rhs) => ins + (if (lhs.typ.isDefined) printTypeToString(lhs.typ.get) + " " else "") + + case Syntax.CRecv(lhs, rhs, typ) => ins + (if (typ.isDefined) printTypeToString(typeAnalysis.typeCheck(lhs)) + " " else "") + printExprToString(lhs) + " <- " + printExprToString(rhs) + ";" case Syntax.COutput(exp) => ins + "output " + printExprToString(exp) + ";" case Syntax.CReturn(exp) => ins + "return " + printExprToString(exp) + ";" @@ -97,16 +101,16 @@ class PrettyPrinter(output: Option[File]) { case Syntax.CLockStart(mod) => ins + "start(" + mod.v + ");" case Syntax.CLockEnd(mod) => ins + "end(" + mod.v + ");" case Syntax.CSpeculate(predVar, predVal, verify, body) => ins + "speculate (" + - printTypeToString(predVar.typ.get) + " " + printExprToString(predVar) + " = " + + printTypeToString(typeAnalysis.typeCheck(predVar)) + " " + printExprToString(predVar) + " = " + printExprToString(predVal) + ", {\n" + printCmdToString(verify, indent + 4) + "\n" + ins + "}, {\n" + printCmdToString(body, indent + 4) + "\n" + ins + "}" case Syntax.CCheck(predVar) => ins + "check(" + predVar.v + ");" case Syntax.CPrint(evar) => ins + "print(" + printExprToString(evar) + ");" - case Syntax.CEmpty => ins + case Syntax.CEmpty() => ins case Syntax.ICondCommand(cond, cmd) => ins + printExprToString(cond) + " ? " + cmd.foldLeft("")((s, c) => s + printCmdToString(c)) - case Syntax.IUpdate(specId, value, originalSpec) => ins + printTypeToString(originalSpec.typ.get) + " " + + case Syntax.IUpdate(specId, value, originalSpec) => ins + printTypeToString(typeAnalysis.typeCheck(originalSpec)) + " " + printExprToString(originalSpec) + " = update(" + specId + ", " + printExprToString(value) + ");" case Syntax.ISpeculate(specId, specVar, value) => ins + specId + "= speculate(" + printExprToString(specVar) + ", " + printExprToString(value) + ");" diff --git a/src/main/scala/pipedsl/common/Syntax.scala b/src/main/scala/pipedsl/common/Syntax.scala index 36757a91..cbd5de99 100644 --- a/src/main/scala/pipedsl/common/Syntax.scala +++ b/src/main/scala/pipedsl/common/Syntax.scala @@ -10,9 +10,6 @@ object Syntax { * Annotations added by the various passes of the type checker. */ object Annotations { - sealed trait TypeAnnotation { - var typ: Option[Type] = None - } sealed trait LabelAnnotation { var lbl: Option[Label] = None } @@ -61,11 +58,11 @@ object Syntax { import Annotations._ - case class Id(v: String) extends Positional with TypeAnnotation { + case class Id(v: String) extends ProgramNode { override def toString = s"$v" } - sealed trait Type extends Positional with LabelAnnotation with SpeculativeAnnotation { + sealed trait Type extends ProgramNode with LabelAnnotation with SpeculativeAnnotation { override def toString: String = this match { case _: TVoid => "void" case _: TBool => "bool" @@ -77,11 +74,15 @@ object Syntax { case TModType(ins, refs, _, _) => s"${ins.mkString("->")} ++ ${refs.mkString("=>")})" case TRequestHandle(m, _) => s"${m}_Request" case TNamedType(n) => n.toString + case TBitWidthAdd(b1, b2) => "add(" + b1 + ", " + b2 + ")" + case TBitWidthLen(len) => len.toString() + case TBitWidthMax(b1, b2) => "max(" + b1 + ", " + b2 + ")" + case TBitWidthVar(name) => "bitVar(" + name + ")" } } // Types that can be upcast to Ints sealed trait IntType - case class TSizedInt(len: Int, unsigned: Boolean) extends Type with IntType + case class TSizedInt(len: TBitWidth, unsigned: Boolean) extends Type with IntType // Use case class instead of case object to get unique positions case class TString() extends Type case class TVoid() extends Type @@ -93,6 +94,11 @@ object Syntax { case class TRequestHandle(mod: Id, isLock: Boolean) extends Type //This is primarily used for parsing and is basically just a type variable case class TNamedType(name: Id) extends Type + sealed trait TBitWidth extends Type + case class TBitWidthVar(name: Id) extends TBitWidth + case class TBitWidthLen(len: Int) extends TBitWidth + case class TBitWidthAdd(b1: TBitWidth, b2: TBitWidth) extends TBitWidth + case class TBitWidthMax(b1: TBitWidth, b2: TBitWidth) extends TBitWidth /** * Define common helper methods implicit classes. @@ -107,7 +113,7 @@ object Syntax { } } - sealed trait UOp extends Positional { + sealed trait UOp extends ProgramNode { val op: String; override def toString: String = this.op def operate(v1: Any): Option[Any] = this match { @@ -129,7 +135,7 @@ object Syntax { def OrOp(e1: Expr, e2: Expr): EBinop = EBinop(BoolOp("||", OpConstructor.or), e1, e2) def EqOp(e1: Expr, e2: Expr): EBinop = EBinop(EqOp("=="), e1, e2) - sealed trait BOp extends Positional { + sealed trait BOp extends ProgramNode { val op: String; override def toString = this.op def operate(v1: Any, v2: Any): Option[Any] = this match { @@ -160,7 +166,7 @@ object Syntax { case class NumOp(op: String, fun: (Int, Int) => Int) extends BOp case class BitOp(op: String, fun: (Int, Int) => Int) extends BOp - sealed trait Expr extends Positional with TypeAnnotation { + sealed trait Expr extends ProgramNode{ def isLVal = this match { case _:EVar => true case _:EMemAccess => true @@ -168,12 +174,11 @@ object Syntax { } def copyMeta(from: Expr): Expr = { setPos(from.pos) - typ = from.typ this } } - case class LockArg(id: Id, evar: Option[EVar]) extends Positional + case class LockArg(id: Id, evar: Option[EVar]) extends ProgramNode case object EInvalid extends Expr case class EIsValid(ex: Expr) extends Expr @@ -196,14 +201,14 @@ object Syntax { def MemoryWrite(index: Expr, value: Expr): ERecLiteral = ERecLiteral(Map((Id("index"), index), (Id("value"),value))) def MemoryRead(index: Expr): ERecLiteral = ERecLiteral(Map((Id("index"), index))) - sealed trait Command extends Positional + sealed trait Command extends ProgramNode case class CSeq(c1: Command, c2: Command) extends Command case class CTBar(c1: Command, c2: Command) extends Command case class CIf(cond: Expr, cons: Command, alt: Command) extends Command - case class CAssign(lhs: EVar, rhs: Expr) extends Command { + case class CAssign(lhs: EVar, rhs: Expr, typ: Option[Type]) extends Command { if (!lhs.isLVal) throw UnexpectedLVal(lhs, "assignment") } - case class CRecv(lhs: Expr, rhs: Expr) extends Command { + case class CRecv(lhs: Expr, rhs: Expr, typ: Option[Type]) extends Command { if (!lhs.isLVal) throw UnexpectedLVal(lhs, "assignment") } case class CPrint(evar: EVar) extends Command @@ -216,8 +221,8 @@ object Syntax { case class CSpeculate(predVar: EVar, predVal: Expr, verify: Command, body: Command) extends Command case class CCheck(predVar: Id) extends Command case class CSplit(cases: List[CaseObj], default: Command) extends Command - case object CEmpty extends Command - + case class CEmpty() extends Command + sealed trait InternalCommand extends Command case class ICondCommand(cond: Expr, cs: List[Command]) extends InternalCommand @@ -238,9 +243,9 @@ object Syntax { //needed for internal compiler passes to track branches with explicitly no lockstate change case class ILockNoOp(mem: LockArg) extends InternalCommand - case class CaseObj(cond: Expr, body: Command) extends Positional + case class CaseObj(cond: Expr, body: Command) extends ProgramNode - sealed trait Definition extends Positional + sealed trait Definition extends ProgramNode case class FuncDef( name: Id, @@ -255,14 +260,16 @@ object Syntax { ret: Option[Type], body: Command) extends Definition with RecursiveAnnotation - case class Param(name: Id, typ: Type) extends Positional + case class Param(name: Id, typ: Type) extends ProgramNode case class Prog( fdefs: List[FuncDef], moddefs: List[ModuleDef], - circ: Circuit) extends Positional + circ: Circuit) extends ProgramNode + + sealed abstract class ProgramNode extends Positional with Product - sealed trait Circuit extends Positional + sealed trait Circuit extends ProgramNode case class CirSeq(c1: Circuit, c2: Circuit) extends Circuit case class CirConnect(name: Id, c: CirExpr) extends Circuit case class CirExprStmt(ce: CirExpr) extends Circuit diff --git a/src/main/scala/pipedsl/common/Utilities.scala b/src/main/scala/pipedsl/common/Utilities.scala index 7618c148..5bf6fab3 100644 --- a/src/main/scala/pipedsl/common/Utilities.scala +++ b/src/main/scala/pipedsl/common/Utilities.scala @@ -3,6 +3,8 @@ package pipedsl.common import Syntax._ import pipedsl.common.DAGSyntax.PStage import pipedsl.common.Errors.UnexpectedCommand +import com.microsoft.z3.{AST => Z3AST, BoolExpr => Z3BoolExpr, Context => Z3Context} + object Utilities { @@ -44,8 +46,8 @@ object Utilities { v ++ getUsedVars(c.cond) ++ getAllVarNames(c.body) }) case CIf(cond, cons, alt) => getUsedVars(cond) ++ getAllVarNames(cons) ++ getAllVarNames(alt) - case CAssign(lhs, rhs) => getUsedVars(lhs) ++ getUsedVars(rhs) - case CRecv(lhs, rhs) => getUsedVars(lhs) ++ getUsedVars(rhs) + case CAssign(lhs, rhs, typ) => getUsedVars(lhs) ++ getUsedVars(rhs) + case CRecv(lhs, rhs, typ) => getUsedVars(lhs) ++ getUsedVars(rhs) case CLockStart(mod) => Set(mod) case CLockEnd(mod) => Set(mod) case CLockOp(mem, _) => if (mem.evar.isDefined) Set(mem.id, mem.evar.get.id) else Set(mem.id) @@ -59,7 +61,7 @@ object Utilities { case ICondCommand(cond, cs) => getUsedVars(cond) ++ cs.foldLeft(Set[Id]())((s, c) => getAllVarNames(c) ++ s) case ISpeculate(specId, specVar, value) => getUsedVars(value) + specId ++ getUsedVars(specVar) case IUpdate(specId,value,originalSpec) => getUsedVars(value) ++ getUsedVars(originalSpec) + specId - case Syntax.CEmpty => Set() + case Syntax.CEmpty() => Set() case _ => throw UnexpectedCommand(c) } @@ -71,8 +73,8 @@ object Utilities { v ++ getWrittenVars(c.body) }) case CIf(_, cons, alt) => getWrittenVars(cons) ++ getWrittenVars(alt) - case CAssign(lhs, _) => lhs match { case EVar(id) => Set(id) ; case _ => Set() } - case CRecv(lhs, _) => lhs match { case EVar(id) => Set(id) ; case _ => Set() } + case CAssign(lhs, _, _) => lhs match { case EVar(id) => Set(id) ; case _ => Set() } + case CRecv(lhs, _, _) => lhs match { case EVar(id) => Set(id) ; case _ => Set() } case CSpeculate(_, _, verify, body) => getWrittenVars(verify) ++ getWrittenVars(body) case ICondCommand(_, c2) => getWrittenVars(c2) case ISpeculate(s, svar, _) => Set(s, svar.id) @@ -105,8 +107,8 @@ object Utilities { }) case CPrint(evar) => Set(evar.id) case CIf(cond, cons, alt) => getUsedVars(cond) ++ getUsedVars(cons) ++ getUsedVars(alt) - case CAssign(_, rhs) => getUsedVars(rhs) - case CRecv(lhs, rhs) => getUsedVars(rhs) ++ (lhs match { + case CAssign(_, rhs, _) => getUsedVars(rhs) + case CRecv(lhs, rhs, _) => getUsedVars(rhs) ++ (lhs match { case e:EMemAccess => getUsedVars(e) case _ => Set() }) @@ -137,7 +139,7 @@ object Utilities { case ICheckLockFree(_) => Set() case CLockStart(_) => Set() case CLockEnd(_) => Set() - case CEmpty => Set() + case CEmpty() => Set() } /** @@ -157,7 +159,7 @@ object Utilities { case EApp(_, args) => args.foldLeft[Set[Id]](Set())((s, a) => { s ++ getUsedVars(a) }) //functions are also externally defined case ECall(id, args) => args.foldLeft[Set[Id]](Set(id))((s, a) => { s ++ getUsedVars(a) }) - case EVar(id) => id.typ = e.typ; Set(id) + case EVar(id) => Set(id) case ECast(_, exp) => getUsedVars(exp) case EFromMaybe(ex) => getUsedVars(ex) case EIsValid(ex) => getUsedVars(ex) @@ -285,6 +287,15 @@ object Utilities { case None => throw except } } + + /** Like [[Z3Context.mkAnd]], but automatically casts inputs to [[Z3BoolExpr]]s. */ + def mkAnd(ctx: Z3Context, expressions: Z3AST *): Z3BoolExpr = + ctx.mkAnd(expressions.map(ast => ast.asInstanceOf[Z3BoolExpr]):_*) - + /** Like [[Z3Context.mkImplies]], but automatically casts inputs to [[Z3BoolExpr]]s. */ + def mkImplies(ctx: Z3Context, t1: Z3AST, t2: Z3AST): Z3BoolExpr = + ctx.mkImplies(t1.asInstanceOf[Z3BoolExpr], t2.asInstanceOf[Z3BoolExpr]) + + def mkOr(ctx: Z3Context, expressions: Z3AST *): Z3BoolExpr = + ctx.mkOr(expressions.map(ast => ast.asInstanceOf[Z3BoolExpr]):_*) } diff --git a/src/main/scala/pipedsl/passes/CanonicalizePass.scala b/src/main/scala/pipedsl/passes/CanonicalizePass.scala index 1e45c1e2..2d989eaf 100644 --- a/src/main/scala/pipedsl/passes/CanonicalizePass.scala +++ b/src/main/scala/pipedsl/passes/CanonicalizePass.scala @@ -24,9 +24,9 @@ object CanonicalizePass extends CommandPass[Command] with ModulePass[ModuleDef] * @return The same command with no cseqs to/from empty commands */ def removeCEmpty(c: Command): Command = c match { - case CSeq(CEmpty, CEmpty) => CEmpty - case CSeq(c1, CEmpty) => removeCEmpty(c1) - case CSeq(CEmpty, c2) => removeCEmpty(c2) + case CSeq(CEmpty(), CEmpty()) => CEmpty() + case CSeq(c1, CEmpty()) => removeCEmpty(c1) + case CSeq(CEmpty(), c2) => removeCEmpty(c2) case CSeq(c1, c2) => CSeq(removeCEmpty(c1), removeCEmpty(c2)).setPos(c.pos) case CTBar(c1, c2) => CTBar(removeCEmpty(c1), removeCEmpty(c2)).setPos(c.pos) case CIf(cond, cons, alt) => CIf(cond, removeCEmpty(cons), removeCEmpty(alt)).setPos(c.pos) diff --git a/src/main/scala/pipedsl/passes/ConvertAsyncPass.scala b/src/main/scala/pipedsl/passes/ConvertAsyncPass.scala index dd4d42b8..54b6f2fb 100644 --- a/src/main/scala/pipedsl/passes/ConvertAsyncPass.scala +++ b/src/main/scala/pipedsl/passes/ConvertAsyncPass.scala @@ -1,5 +1,6 @@ package pipedsl.passes +import pipedsl.analysis.TypeAnalysis import pipedsl.common.Syntax._ import pipedsl.common.DAGSyntax.PStage import pipedsl.common.Errors.{UnexpectedExpr, UnexpectedType} @@ -11,7 +12,7 @@ import pipedsl.passes.Passes.StagePass * of Send and Recv pairs. The Send produces a reference * which the Recv uses to request the result. */ -class ConvertAsyncPass(modName: Id) extends StagePass[List[PStage]] { +class ConvertAsyncPass(modName: Id, typeAnalysis: TypeAnalysis) extends StagePass[List[PStage]] { private var msgCount = 0 override def run(stgs: List[PStage]): List[PStage] = { @@ -54,7 +55,7 @@ class ConvertAsyncPass(modName: Id) extends StagePass[List[PStage]] { val recv = IMemRecv(mem, handle, Some(lhs)) (send, recv) //Mem Write - case (EMemAccess(mem, index@EVar(_)), data@EVar(_)) => mem.typ.get match { + case (EMemAccess(mem, index@EVar(_)), data@EVar(_)) => typeAnalysis.typeCheck(mem) match { case TMemType(_, _, _, Latency.Asynchronous) => val handle = freshMessage(mem) val send = IMemSend(handle, isWrite = true, mem, Some(data), index) @@ -62,8 +63,8 @@ class ConvertAsyncPass(modName: Id) extends StagePass[List[PStage]] { (send, recv) //if the memory is sequential we don't use handle since it //is assumed to complete at the end of the cycle - case TMemType(_, _, _, _) => (IMemWrite(mem, index, data), CEmpty) - case _ => throw UnexpectedType(mem.pos, "Memory Write Statement", "Memory Type", mem.typ.get) + case TMemType(_, _, _, _) => (IMemWrite(mem, index, data), CEmpty()) + case _ => throw UnexpectedType(mem.pos, "Memory Write Statement", "Memory Type", typeAnalysis.typeCheck(mem)) } //module calls case (lhs@EVar(_), call@ECall(_, _)) => @@ -104,8 +105,8 @@ class ConvertAsyncPass(modName: Id) extends StagePass[List[PStage]] { private def freshMessage(m: Id): EVar = { val res = EVar(Id("_request_" + msgCount)) - res.typ = Some(TRequestHandle(m, isLock = false)) - res.id.typ = res.typ + //res.typ = Some(TRequestHandle(m, isLock = false)) + // res.id.typ = res.typ msgCount += 1 res } diff --git a/src/main/scala/pipedsl/passes/LockOpTranslationPass.scala b/src/main/scala/pipedsl/passes/LockOpTranslationPass.scala index c7a3b149..142febc7 100644 --- a/src/main/scala/pipedsl/passes/LockOpTranslationPass.scala +++ b/src/main/scala/pipedsl/passes/LockOpTranslationPass.scala @@ -9,12 +9,12 @@ import pipedsl.passes.Passes.StagePass object LockOpTranslationPass extends StagePass[List[PStage]] { - private def lockVar(l: LockArg): EVar = { val lockname = "_lock_id_" + l.id.v + (if (l.evar.isDefined) "_" + l.evar.get.id.v else "") val res = EVar(Id(lockname)) - res.typ = Some(TRequestHandle(l.id, isLock = true)) - res.id.typ = res.typ + //TODO: Need to figure this out + //res.typ = Some(TRequestHandle(l.id, isLock = true)) + //res.id.typ = res.typ res } diff --git a/src/main/scala/pipedsl/passes/MarkNonRecursiveModulePass.scala b/src/main/scala/pipedsl/passes/MarkNonRecursiveModulePass.scala index ecb869fe..c371f674 100644 --- a/src/main/scala/pipedsl/passes/MarkNonRecursiveModulePass.scala +++ b/src/main/scala/pipedsl/passes/MarkNonRecursiveModulePass.scala @@ -29,8 +29,8 @@ object MarkNonRecursiveModulePass extends ModulePass[ModuleDef] with ProgPass[Pr case CSeq(c1, c2) => hasRecursiveCall(c1, mod) || hasRecursiveCall(c2, mod) case CTBar(c1, c2) => hasRecursiveCall(c1, mod) || hasRecursiveCall(c2, mod) case CIf(_, cons, alt) => hasRecursiveCall(cons, mod) || hasRecursiveCall(alt, mod) - case CAssign(_, rhs) => hasRecCall(rhs, mod) - case CRecv(_, rhs) => hasRecCall(rhs, mod) + case CAssign(_, rhs, _) => hasRecCall(rhs, mod) + case CRecv(_, rhs, _) => hasRecCall(rhs, mod) case COutput(exp) => hasRecCall(exp, mod) case CExpr(exp) => hasRecCall(exp, mod) case _ => false diff --git a/src/main/scala/pipedsl/passes/RemoveReentrantPass.scala b/src/main/scala/pipedsl/passes/RemoveReentrantPass.scala index 7894b161..5119cc2a 100644 --- a/src/main/scala/pipedsl/passes/RemoveReentrantPass.scala +++ b/src/main/scala/pipedsl/passes/RemoveReentrantPass.scala @@ -120,9 +120,9 @@ object RemoveReentrantPass extends StagePass[List[PStage]] { private def getReassignedHandle(handle: EVar): EVar = { val newId = Id(handle.id.v + "_done") - newId.typ = handle.id.typ + //newId.typ = handle.id.typ val newVar = EVar(newId) - newVar.typ = handle.typ + //newVar.typ = handle.typ newVar } diff --git a/src/main/scala/pipedsl/passes/RemoveTimingPass.scala b/src/main/scala/pipedsl/passes/RemoveTimingPass.scala index 2e4241f3..7b72377f 100644 --- a/src/main/scala/pipedsl/passes/RemoveTimingPass.scala +++ b/src/main/scala/pipedsl/passes/RemoveTimingPass.scala @@ -1,5 +1,6 @@ package pipedsl.passes +import pipedsl.analysis.TypeAnalysis import pipedsl.common.Syntax._ import pipedsl.passes.Passes.{CommandPass, ModulePass, ProgPass} @@ -7,8 +8,10 @@ import scala.collection.mutable.ListBuffer object RemoveTimingPass extends CommandPass[Command] with ModulePass[ModuleDef] with ProgPass[Prog] { var calls: ListBuffer[Command] = new ListBuffer[Command]() + var typeAnalysis: TypeAnalysis = null override def run(p: Prog): Prog = { + typeAnalysis = TypeAnalysis.get(p) p.copy(moddefs = p.moddefs.map(m => run(m))).setPos(p.pos) } @@ -25,9 +28,9 @@ object RemoveTimingPass extends CommandPass[Command] with ModulePass[ModuleDef] case CSeq(c1, c2) => CSeq(removeTimingConstructs(c1), removeTimingConstructs(c2)) case CIf(cond, cons, alt) => CIf(cond, removeTimingConstructs(cons), removeTimingConstructs(alt)) case CTBar(c1, c2) => CSeq(removeTimingConstructs(c1), removeTimingConstructs(c2)); - case CLockOp(_,_) => CEmpty - case CSpeculate(_, _, _, _) => CEmpty - case CCheck(_) => CEmpty + case CLockOp(_,_) => CEmpty() + case CSpeculate(_, _, _, _) => CEmpty() + case CCheck(_) => CEmpty() case CSplit(cases, default) => val newCases = List[CaseObj]() val newDefault = removeTimingConstructs(default) @@ -41,7 +44,7 @@ object RemoveTimingPass extends CommandPass[Command] with ModulePass[ModuleDef] val newArgs: ListBuffer[Expr] = new ListBuffer[Expr]() for (index <- args.indices) { val arg = EVar(Id("__" + id.v + "__" + calls.length + index)) - assigns.addOne(CAssign(arg, args(index))) + assigns.addOne(CAssign(arg, args(index), Some(typeAnalysis.typeCheck(args(index))))) newArgs.addOne(arg) } calls.addOne(CExpr(ECall(id, newArgs.toList))) @@ -52,7 +55,7 @@ object RemoveTimingPass extends CommandPass[Command] with ModulePass[ModuleDef] def convertCListToCSeq(commands: ListBuffer[Command], i: Int): Command = { if (i > commands.length-1) { - CEmpty + CEmpty() } else { CSeq(commands(i), convertCListToCSeq(commands, i+1)) } diff --git a/src/main/scala/pipedsl/passes/SimplifyRecvPass.scala b/src/main/scala/pipedsl/passes/SimplifyRecvPass.scala index ae3f59f0..7b153d98 100644 --- a/src/main/scala/pipedsl/passes/SimplifyRecvPass.scala +++ b/src/main/scala/pipedsl/passes/SimplifyRecvPass.scala @@ -1,6 +1,7 @@ package pipedsl.passes import Passes.{CommandPass, ModulePass, ProgPass} +import pipedsl.analysis.TypeAnalysis import pipedsl.common.Errors.UnexpectedCase import pipedsl.common.Syntax._ import pipedsl.common.Utilities._ @@ -13,12 +14,14 @@ import scala.util.parsing.input.Position * This includes index expressions on the LHS of memory assignments, not just RHS expressions. */ object SimplifyRecvPass extends CommandPass[Command] with ModulePass[ModuleDef] with ProgPass[Prog] { - + var usedVars: Set[Id] = Set() var counter: Int = 0 + var typeAnalysis: TypeAnalysis = null override def run(p: Prog): Prog = { usedVars = p.fdefs.foldLeft[Set[Id]](usedVars)((s,f) => s + f.name) + typeAnalysis = TypeAnalysis.get(p) p.copy(moddefs = p.moddefs.map(m => run(m))).setPos(p.pos) } @@ -34,13 +37,11 @@ object SimplifyRecvPass extends CommandPass[Command] with ModulePass[ModuleDef] runHelper(c) } - private def newVar(s: String, p: Position, t: Option[Type]): EVar = { + private def newVar(s: String, p: Position): EVar = { val (nvar, nused, ncnt) = freshVar(s, usedVars, counter) - nvar.typ = t usedVars = nused counter = ncnt val v = EVar(nvar).setPos(p) - v.typ = t v } @@ -56,45 +57,43 @@ object SimplifyRecvPass extends CommandPass[Command] with ModulePass[ModuleDef] CSplit(newcases, runHelper(default).setPos(default.pos)).setPos(c.pos) case CIf(cond, cons, alt) => CIf(cond, runHelper(cons), runHelper(alt)).setPos(c.pos) case CSpeculate(predVar, predVal, verify, body) => CSpeculate(predVar, predVal, runHelper(verify), runHelper(body)).setPos(c.pos) - case CRecv(lhs, rhs) => (lhs, rhs) match { + case CRecv(lhs, rhs, typ) => (lhs, rhs) match { case (EVar(_), EMemAccess(_, EVar(_))) => c //leave it alone, already in the form we want case (EVar(_), EMemAccess(mem, idx)) => //separate out the index computation - val idxAssgn = CAssign(newVar("index", idx.pos, idx.typ), idx).setPos(idx.pos) - CSeq(idxAssgn, CRecv(lhs, EMemAccess(mem, idxAssgn.lhs).setPos(rhs.pos))).setPos(c.pos) + val idxAssgn = CAssign(newVar("index", idx.pos), idx, Some(typeAnalysis.typeCheck(idx))).setPos(idx.pos) + CSeq(idxAssgn, CRecv(lhs, EMemAccess(mem, idxAssgn.lhs).setPos(rhs.pos), typ)).setPos(c.pos) case (EMemAccess(_, EVar(_)), EVar(_)) => c //leave it alone, already in form we want case (EMemAccess(_,EVar(_)), _) => // separate out the RHS computation - val rhsAssgn = CAssign(newVar("msg", rhs.pos, rhs.typ), rhs).setPos(rhs.pos) - CSeq(rhsAssgn, CRecv(lhs, rhsAssgn.lhs).setPos(c.pos)).setPos(c.pos) + val rhsAssgn = CAssign(newVar("msg", rhs.pos), rhs, Some(typeAnalysis.typeCheck(rhs))).setPos(rhs.pos) + CSeq(rhsAssgn, CRecv(lhs, rhsAssgn.lhs, typ).setPos(c.pos)).setPos(c.pos) case (EMemAccess(mem,idx), EVar(_)) => //separate out the index computation - val idxAssgn = CAssign(newVar("index", idx.pos, idx.typ), idx).setPos(idx.pos) + val idxAssgn = CAssign(newVar("index", idx.pos), idx, Some(typeAnalysis.typeCheck(idx))).setPos(idx.pos) val access = EMemAccess(mem, idxAssgn.lhs).setPos(lhs.pos) - access.typ = lhs.typ - CSeq(idxAssgn, CRecv(access, rhs).setPos(c.pos)).setPos(c.pos) + CSeq(idxAssgn, CRecv(access, rhs, typ).setPos(c.pos)).setPos(c.pos) case (EMemAccess(mem,idx), _) => //separate the index computation AND the rhs computation into new variables - val idxAssgn = CAssign(newVar("index", idx.pos, idx.typ), idx).setPos(idx.pos) - val rhsAssgn = CAssign(newVar("msg", rhs.pos, rhs.typ), rhs).setPos(rhs.pos) + val idxAssgn = CAssign(newVar("index", idx.pos), idx, Some(typeAnalysis.typeCheck(idx))).setPos(idx.pos) + val rhsAssgn = CAssign(newVar("msg", rhs.pos), rhs, Some(typeAnalysis.typeCheck(rhs))).setPos(rhs.pos) val access = EMemAccess(mem, idxAssgn.lhs).setPos(lhs.pos) - access.typ = lhs.typ CSeq(idxAssgn, CSeq(rhsAssgn, - CRecv(access, rhsAssgn.lhs).setPos(c.pos)) + CRecv(access, rhsAssgn.lhs, typ).setPos(c.pos)) .setPos(c.pos)) .setPos(c.pos) case (EVar(_), ECall(id, args)) => //TODO cleanup and stop copying code - val argAssgns = args.foldLeft[(Command, List[Expr])]((CEmpty, List()))((cs, a) => { - val argAssn = CAssign(newVar("carg", a.pos, a.typ), a).setPos(a.pos) + val argAssgns = args.foldLeft[(Command, List[Expr])]((CEmpty(), List()))((cs, a) => { + val argAssn = CAssign(newVar("carg", a.pos), a, Some(typeAnalysis.typeCheck(a))).setPos(a.pos) (CSeq(cs._1, argAssn).setPos(a.pos), cs._2 :+ argAssn.lhs) }) - CSeq(argAssgns._1, CRecv(lhs, ECall(id, argAssgns._2).setPos(c.pos)).setPos(c.pos)).setPos(c.pos) + CSeq(argAssgns._1, CRecv(lhs, ECall(id, argAssgns._2).setPos(c.pos), typ).setPos(c.pos)).setPos(c.pos) case (l@EVar(_), _) => - CAssign(l, rhs).setPos(c.pos) + CAssign(l, rhs, typ).setPos(c.pos) case _ => throw UnexpectedCase(c.pos) } //calls also get translated to send statements later case CExpr(ECall(id, args)) => - val argAssgns = args.foldLeft[(Command, List[Expr])]((CEmpty, List()))((cs, a) => { - val argAssn = CAssign(newVar("carg", a.pos, a.typ), a).setPos(a.pos) + val argAssgns = args.foldLeft[(Command, List[Expr])]((CEmpty(), List()))((cs, a) => { + val argAssn = CAssign(newVar("carg", a.pos), a, Some(typeAnalysis.typeCheck(a))).setPos(a.pos) (CSeq(cs._1, argAssn).setPos(a.pos), cs._2 :+ argAssn.lhs) }) CSeq(argAssgns._1, CExpr(ECall(id, argAssgns._2).setPos(c.pos)).setPos(c.pos)).setPos(c.pos) diff --git a/src/main/scala/pipedsl/passes/SplitStagesPass.scala b/src/main/scala/pipedsl/passes/SplitStagesPass.scala index e4ec86ad..194e28c4 100644 --- a/src/main/scala/pipedsl/passes/SplitStagesPass.scala +++ b/src/main/scala/pipedsl/passes/SplitStagesPass.scala @@ -81,7 +81,7 @@ class SplitStagesPass extends CommandPass[List[PStage]] with ModulePass[List[PSt case CSeq(c1, c2) => val nstage = splitToStages(c1, curStage) nstage.init ++ splitToStages(c2, nstage.last) - case CEmpty => List(curStage) + case CEmpty() => List(curStage) case _ => curStage.addCmd(c); List(curStage) } diff --git a/src/main/scala/pipedsl/testOutputs/Circuit.bsv b/src/main/scala/pipedsl/testOutputs/Circuit.bsv deleted file mode 100644 index 891c1ba0..00000000 --- a/src/main/scala/pipedsl/testOutputs/Circuit.bsv +++ /dev/null @@ -1,34 +0,0 @@ -import Memories :: *; -import Hist :: *; -import Functions :: *; - - - -interface TopMod; - interface Hist _inthg; -endinterface - -(* synthesize *) -module mkTB ( Empty _unused_ ); - Reg#( UInt#(3) ) reg_unused_0 <- mkReg ( 0 ); - Reg#( Bool ) started <- mkReg ( False ); - TopMod m <- mkCircuit ( ); - rule initTB (( ! started )); - UInt#(3) _unused_0 = ?; - _unused_0 <- m._inthg.req(10'd0); - reg_unused_0 <= _unused_0; - started <= True; - endrule - rule stopTB (m._inthg.checkHandle(reg_unused_0)); - $finish(); - endrule -endmodule - -(* synthesize *) -module mkCircuit ( TopMod _unused_ ); - CombMem#( UInt#(10), UInt#(10) ) f <- mkCombMem ( True, "f" ); - CombMem#( UInt#(32), UInt#(10) ) w <- mkCombMem ( True, "w" ); - CombMem#( UInt#(32), UInt#(10) ) h <- mkCombMem ( True, "h" ); - Hist hg <- mkHist ( f, w, h ); - interface Hist _inthg = hg; -endmodule diff --git a/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkCircuit.cxx b/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkCircuit.cxx deleted file mode 100644 index e25f7215..00000000 --- a/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkCircuit.cxx +++ /dev/null @@ -1,2205 +0,0 @@ -/* - * Generated by Bluespec Compiler - * - */ -#include "bluesim_primitives.h" -#include "mkCircuit.h" - - -/* String declarations */ -static std::string const __str_literal_1("f", 1u); -static std::string const __str_literal_2("h", 1u); -static std::string const __str_literal_3("w", 1u); - - -/* Constructor */ -MOD_mkCircuit::MOD_mkCircuit(tSimStateHdl simHdl, char const *name, Module *parent) - : Module(simHdl, name, parent), - __clk_handle_0(BAD_CLOCK_HANDLE), - INST_f_rf(simHdl, "f_rf", this, __str_literal_1, 10u, 10u, 0u, 1023u, (tUInt8)0u), - INST_h_rf(simHdl, "h_rf", this, __str_literal_2, 10u, 32u, 0u, 1023u, (tUInt8)0u), - INST_hg(simHdl, "hg", this, 3u, (tUInt8)0u, (tUInt8)0u), - INST_hg_busyReg(simHdl, "hg_busyReg", this, 1u, (tUInt8)0u, (tUInt8)0u), - INST_hg_feature_lock_entryVec_0(simHdl, "hg_feature_lock_entryVec_0", this, 11u, 682u, (tUInt8)0u), - INST_hg_feature_lock_entryVec_1(simHdl, "hg_feature_lock_entryVec_1", this, 11u, 682u, (tUInt8)0u), - INST_hg_feature_lock_entryVec_2(simHdl, "hg_feature_lock_entryVec_2", this, 11u, 682u, (tUInt8)0u), - INST_hg_feature_lock_entryVec_3(simHdl, "hg_feature_lock_entryVec_3", this, 11u, 682u, (tUInt8)0u), - INST_hg_feature_lock_lockVec_0_cnt(simHdl, - "hg_feature_lock_lockVec_0_cnt", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_feature_lock_lockVec_0_held(simHdl, "hg_feature_lock_lockVec_0_held", this, 2u, 4u, 1u, 0u), - INST_hg_feature_lock_lockVec_0_nextId(simHdl, - "hg_feature_lock_lockVec_0_nextId", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_feature_lock_lockVec_1_cnt(simHdl, - "hg_feature_lock_lockVec_1_cnt", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_feature_lock_lockVec_1_held(simHdl, "hg_feature_lock_lockVec_1_held", this, 2u, 4u, 1u, 0u), - INST_hg_feature_lock_lockVec_1_nextId(simHdl, - "hg_feature_lock_lockVec_1_nextId", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_feature_lock_lockVec_2_cnt(simHdl, - "hg_feature_lock_lockVec_2_cnt", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_feature_lock_lockVec_2_held(simHdl, "hg_feature_lock_lockVec_2_held", this, 2u, 4u, 1u, 0u), - INST_hg_feature_lock_lockVec_2_nextId(simHdl, - "hg_feature_lock_lockVec_2_nextId", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_feature_lock_lockVec_3_cnt(simHdl, - "hg_feature_lock_lockVec_3_cnt", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_feature_lock_lockVec_3_held(simHdl, "hg_feature_lock_lockVec_3_held", this, 2u, 4u, 1u, 0u), - INST_hg_feature_lock_lockVec_3_nextId(simHdl, - "hg_feature_lock_lockVec_3_nextId", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_feature_lock_region(simHdl, "hg_feature_lock_region", this, 1u, (tUInt8)1u, (tUInt8)0u), - INST_hg_fifo_Stage__1_TO_Stage__2(simHdl, "hg_fifo_Stage__1_TO_Stage__2", this, 48u, 2u, 1u, 0u), - INST_hg_fifo_Stage__2_TO_Stage__3(simHdl, "hg_fifo_Stage__2_TO_Stage__3", this, 3u, 2u, 1u, 0u), - INST_hg_fifo_Start_TO_Stage__1(simHdl, "hg_fifo_Start_TO_Stage__1", this, 45u, 2u, 1u, 0u), - INST_hg_fifo__input__TO_Start(simHdl, "hg_fifo__input__TO_Start", this, 13u, 2u, 1u, 0u), - INST_hg_h_lock_entryVec_0(simHdl, "hg_h_lock_entryVec_0", this, 11u, 682u, (tUInt8)0u), - INST_hg_h_lock_entryVec_1(simHdl, "hg_h_lock_entryVec_1", this, 11u, 682u, (tUInt8)0u), - INST_hg_h_lock_entryVec_2(simHdl, "hg_h_lock_entryVec_2", this, 11u, 682u, (tUInt8)0u), - INST_hg_h_lock_entryVec_3(simHdl, "hg_h_lock_entryVec_3", this, 11u, 682u, (tUInt8)0u), - INST_hg_h_lock_lockVec_0_cnt(simHdl, "hg_h_lock_lockVec_0_cnt", this, 2u, (tUInt8)0u, (tUInt8)0u), - INST_hg_h_lock_lockVec_0_held(simHdl, "hg_h_lock_lockVec_0_held", this, 2u, 4u, 1u, 0u), - INST_hg_h_lock_lockVec_0_nextId(simHdl, - "hg_h_lock_lockVec_0_nextId", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_h_lock_lockVec_1_cnt(simHdl, "hg_h_lock_lockVec_1_cnt", this, 2u, (tUInt8)0u, (tUInt8)0u), - INST_hg_h_lock_lockVec_1_held(simHdl, "hg_h_lock_lockVec_1_held", this, 2u, 4u, 1u, 0u), - INST_hg_h_lock_lockVec_1_nextId(simHdl, - "hg_h_lock_lockVec_1_nextId", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_h_lock_lockVec_2_cnt(simHdl, "hg_h_lock_lockVec_2_cnt", this, 2u, (tUInt8)0u, (tUInt8)0u), - INST_hg_h_lock_lockVec_2_held(simHdl, "hg_h_lock_lockVec_2_held", this, 2u, 4u, 1u, 0u), - INST_hg_h_lock_lockVec_2_nextId(simHdl, - "hg_h_lock_lockVec_2_nextId", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_h_lock_lockVec_3_cnt(simHdl, "hg_h_lock_lockVec_3_cnt", this, 2u, (tUInt8)0u, (tUInt8)0u), - INST_hg_h_lock_lockVec_3_held(simHdl, "hg_h_lock_lockVec_3_held", this, 2u, 4u, 1u, 0u), - INST_hg_h_lock_lockVec_3_nextId(simHdl, - "hg_h_lock_lockVec_3_nextId", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_h_lock_region(simHdl, "hg_h_lock_region", this, 1u, (tUInt8)1u, (tUInt8)0u), - INST_hg_outputQueue(simHdl, "hg_outputQueue", this, 4u, 2u, 1u, 0u), - INST_hg_weight_lock_entryVec_0(simHdl, "hg_weight_lock_entryVec_0", this, 11u, 682u, (tUInt8)0u), - INST_hg_weight_lock_entryVec_1(simHdl, "hg_weight_lock_entryVec_1", this, 11u, 682u, (tUInt8)0u), - INST_hg_weight_lock_entryVec_2(simHdl, "hg_weight_lock_entryVec_2", this, 11u, 682u, (tUInt8)0u), - INST_hg_weight_lock_entryVec_3(simHdl, "hg_weight_lock_entryVec_3", this, 11u, 682u, (tUInt8)0u), - INST_hg_weight_lock_lockVec_0_cnt(simHdl, - "hg_weight_lock_lockVec_0_cnt", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_weight_lock_lockVec_0_held(simHdl, "hg_weight_lock_lockVec_0_held", this, 2u, 4u, 1u, 0u), - INST_hg_weight_lock_lockVec_0_nextId(simHdl, - "hg_weight_lock_lockVec_0_nextId", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_weight_lock_lockVec_1_cnt(simHdl, - "hg_weight_lock_lockVec_1_cnt", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_weight_lock_lockVec_1_held(simHdl, "hg_weight_lock_lockVec_1_held", this, 2u, 4u, 1u, 0u), - INST_hg_weight_lock_lockVec_1_nextId(simHdl, - "hg_weight_lock_lockVec_1_nextId", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_weight_lock_lockVec_2_cnt(simHdl, - "hg_weight_lock_lockVec_2_cnt", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_weight_lock_lockVec_2_held(simHdl, "hg_weight_lock_lockVec_2_held", this, 2u, 4u, 1u, 0u), - INST_hg_weight_lock_lockVec_2_nextId(simHdl, - "hg_weight_lock_lockVec_2_nextId", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_weight_lock_lockVec_3_cnt(simHdl, - "hg_weight_lock_lockVec_3_cnt", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_weight_lock_lockVec_3_held(simHdl, "hg_weight_lock_lockVec_3_held", this, 2u, 4u, 1u, 0u), - INST_hg_weight_lock_lockVec_3_nextId(simHdl, - "hg_weight_lock_lockVec_3_nextId", - this, - 2u, - (tUInt8)0u, - (tUInt8)0u), - INST_hg_weight_lock_region(simHdl, "hg_weight_lock_region", this, 1u, (tUInt8)1u, (tUInt8)0u), - INST_w_rf(simHdl, "w_rf", this, __str_literal_3, 10u, 32u, 0u, 1023u, (tUInt8)0u), - PORT_RST_N((tUInt8)1u) -{ - PORT_EN__inthg_req = false; - symbol_count = 87u; - symbols = new tSym[symbol_count]; - init_symbols_0(); -} - - -/* Symbol init fns */ - -void MOD_mkCircuit::init_symbols_0() -{ - init_symbol(&symbols[0u], "b__h8408", SYM_DEF, &DEF_b__h8408, 10u); - init_symbol(&symbols[1u], "b__h8449", SYM_DEF, &DEF_b__h8449, 10u); - init_symbol(&symbols[2u], "b__h8480", SYM_DEF, &DEF_b__h8480, 10u); - init_symbol(&symbols[3u], "b__h8511", SYM_DEF, &DEF_b__h8511, 10u); - init_symbol(&symbols[4u], "EN__inthg_req", SYM_PORT, &PORT_EN__inthg_req, 1u); - init_symbol(&symbols[5u], "f_rf", SYM_MODULE, &INST_f_rf); - init_symbol(&symbols[6u], "h_rf", SYM_MODULE, &INST_h_rf); - init_symbol(&symbols[7u], "hg", SYM_MODULE, &INST_hg); - init_symbol(&symbols[8u], "hg_busyReg", SYM_MODULE, &INST_hg_busyReg); - init_symbol(&symbols[9u], "hg_busyReg__h7113", SYM_DEF, &DEF_hg_busyReg__h7113, 1u); - init_symbol(&symbols[10u], - "hg_feature_lock_entryVec_0", - SYM_MODULE, - &INST_hg_feature_lock_entryVec_0); - init_symbol(&symbols[11u], - "hg_feature_lock_entryVec_1", - SYM_MODULE, - &INST_hg_feature_lock_entryVec_1); - init_symbol(&symbols[12u], - "hg_feature_lock_entryVec_2", - SYM_MODULE, - &INST_hg_feature_lock_entryVec_2); - init_symbol(&symbols[13u], - "hg_feature_lock_entryVec_3", - SYM_MODULE, - &INST_hg_feature_lock_entryVec_3); - init_symbol(&symbols[14u], - "hg_feature_lock_lockVec_0_cnt", - SYM_MODULE, - &INST_hg_feature_lock_lockVec_0_cnt); - init_symbol(&symbols[15u], - "hg_feature_lock_lockVec_0_held", - SYM_MODULE, - &INST_hg_feature_lock_lockVec_0_held); - init_symbol(&symbols[16u], - "hg_feature_lock_lockVec_0_nextId", - SYM_MODULE, - &INST_hg_feature_lock_lockVec_0_nextId); - init_symbol(&symbols[17u], - "hg_feature_lock_lockVec_1_cnt", - SYM_MODULE, - &INST_hg_feature_lock_lockVec_1_cnt); - init_symbol(&symbols[18u], - "hg_feature_lock_lockVec_1_held", - SYM_MODULE, - &INST_hg_feature_lock_lockVec_1_held); - init_symbol(&symbols[19u], - "hg_feature_lock_lockVec_1_nextId", - SYM_MODULE, - &INST_hg_feature_lock_lockVec_1_nextId); - init_symbol(&symbols[20u], - "hg_feature_lock_lockVec_2_cnt", - SYM_MODULE, - &INST_hg_feature_lock_lockVec_2_cnt); - init_symbol(&symbols[21u], - "hg_feature_lock_lockVec_2_held", - SYM_MODULE, - &INST_hg_feature_lock_lockVec_2_held); - init_symbol(&symbols[22u], - "hg_feature_lock_lockVec_2_nextId", - SYM_MODULE, - &INST_hg_feature_lock_lockVec_2_nextId); - init_symbol(&symbols[23u], - "hg_feature_lock_lockVec_3_cnt", - SYM_MODULE, - &INST_hg_feature_lock_lockVec_3_cnt); - init_symbol(&symbols[24u], - "hg_feature_lock_lockVec_3_held", - SYM_MODULE, - &INST_hg_feature_lock_lockVec_3_held); - init_symbol(&symbols[25u], - "hg_feature_lock_lockVec_3_nextId", - SYM_MODULE, - &INST_hg_feature_lock_lockVec_3_nextId); - init_symbol(&symbols[26u], "hg_feature_lock_region", SYM_MODULE, &INST_hg_feature_lock_region); - init_symbol(&symbols[27u], "hg_fifo__input__TO_Start", SYM_MODULE, &INST_hg_fifo__input__TO_Start); - init_symbol(&symbols[28u], - "hg_fifo_Stage__1_TO_Stage__2", - SYM_MODULE, - &INST_hg_fifo_Stage__1_TO_Stage__2); - init_symbol(&symbols[29u], - "hg_fifo_Stage__2_TO_Stage__3", - SYM_MODULE, - &INST_hg_fifo_Stage__2_TO_Stage__3); - init_symbol(&symbols[30u], - "hg_fifo_Start_TO_Stage__1", - SYM_MODULE, - &INST_hg_fifo_Start_TO_Stage__1); - init_symbol(&symbols[31u], "hg_h_lock_entryVec_0", SYM_MODULE, &INST_hg_h_lock_entryVec_0); - init_symbol(&symbols[32u], "hg_h_lock_entryVec_1", SYM_MODULE, &INST_hg_h_lock_entryVec_1); - init_symbol(&symbols[33u], "hg_h_lock_entryVec_2", SYM_MODULE, &INST_hg_h_lock_entryVec_2); - init_symbol(&symbols[34u], "hg_h_lock_entryVec_3", SYM_MODULE, &INST_hg_h_lock_entryVec_3); - init_symbol(&symbols[35u], "hg_h_lock_lockVec_0_cnt", SYM_MODULE, &INST_hg_h_lock_lockVec_0_cnt); - init_symbol(&symbols[36u], "hg_h_lock_lockVec_0_held", SYM_MODULE, &INST_hg_h_lock_lockVec_0_held); - init_symbol(&symbols[37u], - "hg_h_lock_lockVec_0_nextId", - SYM_MODULE, - &INST_hg_h_lock_lockVec_0_nextId); - init_symbol(&symbols[38u], "hg_h_lock_lockVec_1_cnt", SYM_MODULE, &INST_hg_h_lock_lockVec_1_cnt); - init_symbol(&symbols[39u], "hg_h_lock_lockVec_1_held", SYM_MODULE, &INST_hg_h_lock_lockVec_1_held); - init_symbol(&symbols[40u], - "hg_h_lock_lockVec_1_nextId", - SYM_MODULE, - &INST_hg_h_lock_lockVec_1_nextId); - init_symbol(&symbols[41u], "hg_h_lock_lockVec_2_cnt", SYM_MODULE, &INST_hg_h_lock_lockVec_2_cnt); - init_symbol(&symbols[42u], "hg_h_lock_lockVec_2_held", SYM_MODULE, &INST_hg_h_lock_lockVec_2_held); - init_symbol(&symbols[43u], - "hg_h_lock_lockVec_2_nextId", - SYM_MODULE, - &INST_hg_h_lock_lockVec_2_nextId); - init_symbol(&symbols[44u], "hg_h_lock_lockVec_3_cnt", SYM_MODULE, &INST_hg_h_lock_lockVec_3_cnt); - init_symbol(&symbols[45u], "hg_h_lock_lockVec_3_held", SYM_MODULE, &INST_hg_h_lock_lockVec_3_held); - init_symbol(&symbols[46u], - "hg_h_lock_lockVec_3_nextId", - SYM_MODULE, - &INST_hg_h_lock_lockVec_3_nextId); - init_symbol(&symbols[47u], "hg_h_lock_region", SYM_MODULE, &INST_hg_h_lock_region); - init_symbol(&symbols[48u], "hg_outputQueue", SYM_MODULE, &INST_hg_outputQueue); - init_symbol(&symbols[49u], - "hg_weight_lock_entryVec_0", - SYM_MODULE, - &INST_hg_weight_lock_entryVec_0); - init_symbol(&symbols[50u], - "hg_weight_lock_entryVec_1", - SYM_MODULE, - &INST_hg_weight_lock_entryVec_1); - init_symbol(&symbols[51u], - "hg_weight_lock_entryVec_2", - SYM_MODULE, - &INST_hg_weight_lock_entryVec_2); - init_symbol(&symbols[52u], - "hg_weight_lock_entryVec_3", - SYM_MODULE, - &INST_hg_weight_lock_entryVec_3); - init_symbol(&symbols[53u], - "hg_weight_lock_lockVec_0_cnt", - SYM_MODULE, - &INST_hg_weight_lock_lockVec_0_cnt); - init_symbol(&symbols[54u], - "hg_weight_lock_lockVec_0_held", - SYM_MODULE, - &INST_hg_weight_lock_lockVec_0_held); - init_symbol(&symbols[55u], - "hg_weight_lock_lockVec_0_nextId", - SYM_MODULE, - &INST_hg_weight_lock_lockVec_0_nextId); - init_symbol(&symbols[56u], - "hg_weight_lock_lockVec_1_cnt", - SYM_MODULE, - &INST_hg_weight_lock_lockVec_1_cnt); - init_symbol(&symbols[57u], - "hg_weight_lock_lockVec_1_held", - SYM_MODULE, - &INST_hg_weight_lock_lockVec_1_held); - init_symbol(&symbols[58u], - "hg_weight_lock_lockVec_1_nextId", - SYM_MODULE, - &INST_hg_weight_lock_lockVec_1_nextId); - init_symbol(&symbols[59u], - "hg_weight_lock_lockVec_2_cnt", - SYM_MODULE, - &INST_hg_weight_lock_lockVec_2_cnt); - init_symbol(&symbols[60u], - "hg_weight_lock_lockVec_2_held", - SYM_MODULE, - &INST_hg_weight_lock_lockVec_2_held); - init_symbol(&symbols[61u], - "hg_weight_lock_lockVec_2_nextId", - SYM_MODULE, - &INST_hg_weight_lock_lockVec_2_nextId); - init_symbol(&symbols[62u], - "hg_weight_lock_lockVec_3_cnt", - SYM_MODULE, - &INST_hg_weight_lock_lockVec_3_cnt); - init_symbol(&symbols[63u], - "hg_weight_lock_lockVec_3_held", - SYM_MODULE, - &INST_hg_weight_lock_lockVec_3_held); - init_symbol(&symbols[64u], - "hg_weight_lock_lockVec_3_nextId", - SYM_MODULE, - &INST_hg_weight_lock_lockVec_3_nextId); - init_symbol(&symbols[65u], "hg_weight_lock_region", SYM_MODULE, &INST_hg_weight_lock_region); - init_symbol(&symbols[66u], "RL_hg_feature_lock_freelock", SYM_RULE); - init_symbol(&symbols[67u], "RL_hg_feature_lock_freelock_1", SYM_RULE); - init_symbol(&symbols[68u], "RL_hg_feature_lock_freelock_2", SYM_RULE); - init_symbol(&symbols[69u], "RL_hg_feature_lock_freelock_3", SYM_RULE); - init_symbol(&symbols[70u], "RL_hg_h_lock_freelock", SYM_RULE); - init_symbol(&symbols[71u], "RL_hg_h_lock_freelock_1", SYM_RULE); - init_symbol(&symbols[72u], "RL_hg_h_lock_freelock_2", SYM_RULE); - init_symbol(&symbols[73u], "RL_hg_h_lock_freelock_3", SYM_RULE); - init_symbol(&symbols[74u], "RL_hg_s_Stage__1_execute", SYM_RULE); - init_symbol(&symbols[75u], "RL_hg_s_Stage__2_execute", SYM_RULE); - init_symbol(&symbols[76u], "RL_hg_s_Stage__3_execute", SYM_RULE); - init_symbol(&symbols[77u], "RL_hg_s_Start_execute", SYM_RULE); - init_symbol(&symbols[78u], "RL_hg_weight_lock_freelock", SYM_RULE); - init_symbol(&symbols[79u], "RL_hg_weight_lock_freelock_1", SYM_RULE); - init_symbol(&symbols[80u], "RL_hg_weight_lock_freelock_2", SYM_RULE); - init_symbol(&symbols[81u], "RL_hg_weight_lock_freelock_3", SYM_RULE); - init_symbol(&symbols[82u], "WILL_FIRE__inthg_req", SYM_DEF, &DEF_WILL_FIRE__inthg_req, 1u); - init_symbol(&symbols[83u], "w_rf", SYM_MODULE, &INST_w_rf); - init_symbol(&symbols[84u], "x__h10519", SYM_DEF, &DEF_x__h10519, 2u); - init_symbol(&symbols[85u], "x__h8976", SYM_DEF, &DEF_x__h8976, 2u); - init_symbol(&symbols[86u], "x__h9842", SYM_DEF, &DEF_x__h9842, 2u); -} - - -/* Rule actions */ - -void MOD_mkCircuit::RL_hg_feature_lock_freelock() -{ - tUInt8 DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty_AN_ETC___d5; - DEF_hg_feature_lock_entryVec_0___d3 = INST_hg_feature_lock_entryVec_0.METH_read(); - DEF_hg_feature_lock_entryVec_0_BIT_10___d4 = (tUInt8)(DEF_hg_feature_lock_entryVec_0___d3 >> 10u); - DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty___d2 = !INST_hg_feature_lock_lockVec_0_held.METH_notEmpty(); - DEF__0_CONCAT_DONTCARE___d6 = 682u; - DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty_AN_ETC___d5 = DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty___d2 && DEF_hg_feature_lock_entryVec_0_BIT_10___d4; - if (DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty_AN_ETC___d5) - INST_hg_feature_lock_entryVec_0.METH_write(DEF__0_CONCAT_DONTCARE___d6); -} - -void MOD_mkCircuit::RL_hg_feature_lock_freelock_1() -{ - tUInt8 DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty_AN_ETC___d11; - DEF_hg_feature_lock_entryVec_1___d9 = INST_hg_feature_lock_entryVec_1.METH_read(); - DEF_hg_feature_lock_entryVec_1_BIT_10___d10 = (tUInt8)(DEF_hg_feature_lock_entryVec_1___d9 >> 10u); - DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty___d8 = !INST_hg_feature_lock_lockVec_1_held.METH_notEmpty(); - DEF__0_CONCAT_DONTCARE___d6 = 682u; - DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty_AN_ETC___d11 = DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty___d8 && DEF_hg_feature_lock_entryVec_1_BIT_10___d10; - if (DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty_AN_ETC___d11) - INST_hg_feature_lock_entryVec_1.METH_write(DEF__0_CONCAT_DONTCARE___d6); -} - -void MOD_mkCircuit::RL_hg_feature_lock_freelock_2() -{ - tUInt8 DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2_ETC___d16; - DEF_hg_feature_lock_entryVec_2___d14 = INST_hg_feature_lock_entryVec_2.METH_read(); - DEF_hg_feature_lock_entryVec_2_4_BIT_10___d15 = (tUInt8)(DEF_hg_feature_lock_entryVec_2___d14 >> 10u); - DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2___d13 = !INST_hg_feature_lock_lockVec_2_held.METH_notEmpty(); - DEF__0_CONCAT_DONTCARE___d6 = 682u; - DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2_ETC___d16 = DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2___d13 && DEF_hg_feature_lock_entryVec_2_4_BIT_10___d15; - if (DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2_ETC___d16) - INST_hg_feature_lock_entryVec_2.METH_write(DEF__0_CONCAT_DONTCARE___d6); -} - -void MOD_mkCircuit::RL_hg_feature_lock_freelock_3() -{ - tUInt8 DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7_ETC___d21; - DEF_hg_feature_lock_entryVec_3___d19 = INST_hg_feature_lock_entryVec_3.METH_read(); - DEF_hg_feature_lock_entryVec_3_9_BIT_10___d20 = (tUInt8)(DEF_hg_feature_lock_entryVec_3___d19 >> 10u); - DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7___d18 = !INST_hg_feature_lock_lockVec_3_held.METH_notEmpty(); - DEF__0_CONCAT_DONTCARE___d6 = 682u; - DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7_ETC___d21 = DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7___d18 && DEF_hg_feature_lock_entryVec_3_9_BIT_10___d20; - if (DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7_ETC___d21) - INST_hg_feature_lock_entryVec_3.METH_write(DEF__0_CONCAT_DONTCARE___d6); -} - -void MOD_mkCircuit::RL_hg_weight_lock_freelock() -{ - tUInt8 DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2__ETC___d26; - DEF_hg_weight_lock_entryVec_0___d24 = INST_hg_weight_lock_entryVec_0.METH_read(); - DEF_hg_weight_lock_entryVec_0_4_BIT_10___d25 = (tUInt8)(DEF_hg_weight_lock_entryVec_0___d24 >> 10u); - DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2___d23 = !INST_hg_weight_lock_lockVec_0_held.METH_notEmpty(); - DEF__0_CONCAT_DONTCARE___d6 = 682u; - DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2__ETC___d26 = DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2___d23 && DEF_hg_weight_lock_entryVec_0_4_BIT_10___d25; - if (DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2__ETC___d26) - INST_hg_weight_lock_entryVec_0.METH_write(DEF__0_CONCAT_DONTCARE___d6); -} - -void MOD_mkCircuit::RL_hg_weight_lock_freelock_1() -{ - tUInt8 DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7__ETC___d31; - DEF_hg_weight_lock_entryVec_1___d29 = INST_hg_weight_lock_entryVec_1.METH_read(); - DEF_hg_weight_lock_entryVec_1_9_BIT_10___d30 = (tUInt8)(DEF_hg_weight_lock_entryVec_1___d29 >> 10u); - DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7___d28 = !INST_hg_weight_lock_lockVec_1_held.METH_notEmpty(); - DEF__0_CONCAT_DONTCARE___d6 = 682u; - DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7__ETC___d31 = DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7___d28 && DEF_hg_weight_lock_entryVec_1_9_BIT_10___d30; - if (DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7__ETC___d31) - INST_hg_weight_lock_entryVec_1.METH_write(DEF__0_CONCAT_DONTCARE___d6); -} - -void MOD_mkCircuit::RL_hg_weight_lock_freelock_2() -{ - tUInt8 DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2__ETC___d36; - DEF_hg_weight_lock_entryVec_2___d34 = INST_hg_weight_lock_entryVec_2.METH_read(); - DEF_hg_weight_lock_entryVec_2_4_BIT_10___d35 = (tUInt8)(DEF_hg_weight_lock_entryVec_2___d34 >> 10u); - DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2___d33 = !INST_hg_weight_lock_lockVec_2_held.METH_notEmpty(); - DEF__0_CONCAT_DONTCARE___d6 = 682u; - DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2__ETC___d36 = DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2___d33 && DEF_hg_weight_lock_entryVec_2_4_BIT_10___d35; - if (DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2__ETC___d36) - INST_hg_weight_lock_entryVec_2.METH_write(DEF__0_CONCAT_DONTCARE___d6); -} - -void MOD_mkCircuit::RL_hg_weight_lock_freelock_3() -{ - tUInt8 DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7__ETC___d41; - DEF_hg_weight_lock_entryVec_3___d39 = INST_hg_weight_lock_entryVec_3.METH_read(); - DEF_hg_weight_lock_entryVec_3_9_BIT_10___d40 = (tUInt8)(DEF_hg_weight_lock_entryVec_3___d39 >> 10u); - DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7___d38 = !INST_hg_weight_lock_lockVec_3_held.METH_notEmpty(); - DEF__0_CONCAT_DONTCARE___d6 = 682u; - DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7__ETC___d41 = DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7___d38 && DEF_hg_weight_lock_entryVec_3_9_BIT_10___d40; - if (DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7__ETC___d41) - INST_hg_weight_lock_entryVec_3.METH_write(DEF__0_CONCAT_DONTCARE___d6); -} - -void MOD_mkCircuit::RL_hg_h_lock_freelock() -{ - tUInt8 DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2_3_AND_ETC___d46; - DEF_hg_h_lock_entryVec_0___d44 = INST_hg_h_lock_entryVec_0.METH_read(); - DEF_hg_h_lock_entryVec_0_4_BIT_10___d45 = (tUInt8)(DEF_hg_h_lock_entryVec_0___d44 >> 10u); - DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2___d43 = !INST_hg_h_lock_lockVec_0_held.METH_notEmpty(); - DEF__0_CONCAT_DONTCARE___d6 = 682u; - DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2_3_AND_ETC___d46 = DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2___d43 && DEF_hg_h_lock_entryVec_0_4_BIT_10___d45; - if (DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2_3_AND_ETC___d46) - INST_hg_h_lock_entryVec_0.METH_write(DEF__0_CONCAT_DONTCARE___d6); -} - -void MOD_mkCircuit::RL_hg_h_lock_freelock_1() -{ - tUInt8 DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7_8_AND_ETC___d51; - DEF_hg_h_lock_entryVec_1___d49 = INST_hg_h_lock_entryVec_1.METH_read(); - DEF_hg_h_lock_entryVec_1_9_BIT_10___d50 = (tUInt8)(DEF_hg_h_lock_entryVec_1___d49 >> 10u); - DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7___d48 = !INST_hg_h_lock_lockVec_1_held.METH_notEmpty(); - DEF__0_CONCAT_DONTCARE___d6 = 682u; - DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7_8_AND_ETC___d51 = DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7___d48 && DEF_hg_h_lock_entryVec_1_9_BIT_10___d50; - if (DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7_8_AND_ETC___d51) - INST_hg_h_lock_entryVec_1.METH_write(DEF__0_CONCAT_DONTCARE___d6); -} - -void MOD_mkCircuit::RL_hg_h_lock_freelock_2() -{ - tUInt8 DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2_3_AND_ETC___d56; - DEF_hg_h_lock_entryVec_2___d54 = INST_hg_h_lock_entryVec_2.METH_read(); - DEF_hg_h_lock_entryVec_2_4_BIT_10___d55 = (tUInt8)(DEF_hg_h_lock_entryVec_2___d54 >> 10u); - DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2___d53 = !INST_hg_h_lock_lockVec_2_held.METH_notEmpty(); - DEF__0_CONCAT_DONTCARE___d6 = 682u; - DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2_3_AND_ETC___d56 = DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2___d53 && DEF_hg_h_lock_entryVec_2_4_BIT_10___d55; - if (DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2_3_AND_ETC___d56) - INST_hg_h_lock_entryVec_2.METH_write(DEF__0_CONCAT_DONTCARE___d6); -} - -void MOD_mkCircuit::RL_hg_h_lock_freelock_3() -{ - tUInt8 DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7_8_AND_ETC___d61; - DEF_hg_h_lock_entryVec_3___d59 = INST_hg_h_lock_entryVec_3.METH_read(); - DEF_hg_h_lock_entryVec_3_9_BIT_10___d60 = (tUInt8)(DEF_hg_h_lock_entryVec_3___d59 >> 10u); - DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7___d58 = !INST_hg_h_lock_lockVec_3_held.METH_notEmpty(); - DEF__0_CONCAT_DONTCARE___d6 = 682u; - DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7_8_AND_ETC___d61 = DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7___d58 && DEF_hg_h_lock_entryVec_3_9_BIT_10___d60; - if (DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7_8_AND_ETC___d61) - INST_hg_h_lock_entryVec_3.METH_write(DEF__0_CONCAT_DONTCARE___d6); -} - -void MOD_mkCircuit::RL_hg_s_Start_execute() -{ - tUInt8 DEF_hg_fifo__input__TO_Start_first__3_BITS_2_TO_0__ETC___d161; - tUInt32 DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d160; - tUInt64 DEF_f_rf_sub_hg_fifo__input__TO_Start_first__3_BIT_ETC___d164; - tUInt8 DEF_hg_fifo__input__TO_Start_first__3_BITS_2_TO_0___d159; - tUInt32 DEF_b__h8314; - tUInt32 DEF_b__h8326; - DEF_hg_fifo__input__TO_Start_first____d63 = INST_hg_fifo__input__TO_Start.METH_first(); - DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64 = (tUInt32)(DEF_hg_fifo__input__TO_Start_first____d63 >> 3u); - DEF_b__h8326 = INST_w_rf.METH_sub(DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64); - DEF_b__h8314 = INST_f_rf.METH_sub(DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64); - DEF_hg_fifo__input__TO_Start_first__3_BITS_2_TO_0___d159 = (tUInt8)((tUInt8)7u & DEF_hg_fifo__input__TO_Start_first____d63); - DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 = DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64 < 1000u; - DEF_f_rf_sub_hg_fifo__input__TO_Start_first__3_BIT_ETC___d164 = 35184372088831llu & (((((tUInt64)(DEF_b__h8314)) << 35u) | (((tUInt64)(DEF_b__h8326)) << 3u)) | (tUInt64)(DEF_hg_fifo__input__TO_Start_first__3_BITS_2_TO_0___d159)); - DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d160 = 8191u & (((1023u & (DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64 + 1u)) << 3u) | (tUInt32)(DEF_hg_fifo__input__TO_Start_first__3_BITS_2_TO_0___d159)); - DEF_hg_fifo__input__TO_Start_first__3_BITS_2_TO_0__ETC___d161 = (tUInt8)15u & ((DEF_hg_fifo__input__TO_Start_first__3_BITS_2_TO_0___d159 << 1u) | (tUInt8)1u); - DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74 = !DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65; - if (DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65) - INST_hg_fifo__input__TO_Start.METH_enq(DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d160); - if (DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74) - INST_hg_busyReg.METH_write((tUInt8)0u); - if (DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74) - INST_hg_outputQueue.METH_enq(DEF_hg_fifo__input__TO_Start_first__3_BITS_2_TO_0__ETC___d161); - if (DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65) - INST_hg_fifo_Start_TO_Stage__1.METH_enq(DEF_f_rf_sub_hg_fifo__input__TO_Start_first__3_BIT_ETC___d164); - INST_hg_fifo__input__TO_Start.METH_deq(); -} - -void MOD_mkCircuit::RL_hg_s_Stage__1_execute() -{ - tUInt8 DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265; - tUInt32 DEF__1_CONCAT_hg_fifo_Start_TO_Stage__1_first__68_B_ETC___d267; - tUInt64 DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_ETC___d280; - tUInt8 DEF_SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d276; - tUInt8 DEF_SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d275; - tUInt8 DEF_b__h9577; - tUInt8 DEF_b__h9653; - tUInt8 DEF_b__h9729; - tUInt8 DEF_b__h9805; - tUInt32 DEF_b__h9009; - tUInt32 DEF_h_rf_sub_hg_fifo_Start_TO_Stage__1_first__68_B_ETC___d235; - tUInt32 DEF_unsigned_h_rf_sub_hg_fifo_Start_TO_Stage__1_f_ETC___d236; - tUInt8 DEF__dfoo1; - tUInt8 DEF_hg_h_lock_lockVec_3_cnt_59_PLUS_1___d260; - tUInt8 DEF__dfoo2; - tUInt8 DEF_hg_h_lock_lockVec_3_nextId_57_PLUS_1___d258; - tUInt8 DEF__dfoo4; - tUInt8 DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d273; - tUInt8 DEF_b__h9504; - tUInt8 DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d256; - tUInt8 DEF__dfoo6; - tUInt8 DEF__dfoo7; - tUInt8 DEF_hg_h_lock_lockVec_2_cnt_53_PLUS_1___d254; - tUInt8 DEF__dfoo8; - tUInt8 DEF_hg_h_lock_lockVec_2_nextId_51_PLUS_1___d252; - tUInt8 DEF__dfoo10; - tUInt8 DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d271; - tUInt8 DEF_b__h9483; - tUInt8 DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d250; - tUInt8 DEF__dfoo12; - tUInt8 DEF__dfoo13; - tUInt8 DEF_hg_h_lock_lockVec_1_cnt_47_PLUS_1___d248; - tUInt8 DEF__dfoo14; - tUInt8 DEF_hg_h_lock_lockVec_1_nextId_45_PLUS_1___d246; - tUInt8 DEF__dfoo16; - tUInt8 DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d269; - tUInt8 DEF_b__h9462; - tUInt8 DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d244; - tUInt8 DEF__dfoo18; - tUInt8 DEF__dfoo19; - tUInt8 DEF_hg_h_lock_lockVec_0_cnt_41_PLUS_1___d242; - tUInt8 DEF__dfoo20; - tUInt8 DEF_hg_h_lock_lockVec_0_nextId_39_PLUS_1___d240; - tUInt8 DEF__dfoo22; - tUInt8 DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d266; - tUInt8 DEF_b__h9441; - tUInt8 DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d238; - tUInt8 DEF__dfoo24; - tUInt8 DEF__dfoo23; - tUInt8 DEF__dfoo21; - tUInt8 DEF__dfoo17; - tUInt8 DEF__dfoo15; - tUInt8 DEF__dfoo11; - tUInt8 DEF__dfoo9; - tUInt8 DEF__dfoo5; - tUInt8 DEF__dfoo3; - DEF_b__h9441 = INST_hg_h_lock_lockVec_0_nextId.METH_read(); - DEF_hg_h_lock_lockVec_0_nextId_39_PLUS_1___d240 = (tUInt8)3u & (DEF_b__h9441 + (tUInt8)1u); - DEF_b__h9462 = INST_hg_h_lock_lockVec_1_nextId.METH_read(); - DEF_hg_h_lock_lockVec_1_nextId_45_PLUS_1___d246 = (tUInt8)3u & (DEF_b__h9462 + (tUInt8)1u); - DEF_b__h9483 = INST_hg_h_lock_lockVec_2_nextId.METH_read(); - DEF_hg_h_lock_lockVec_2_nextId_51_PLUS_1___d252 = (tUInt8)3u & (DEF_b__h9483 + (tUInt8)1u); - DEF_b__h9504 = INST_hg_h_lock_lockVec_3_nextId.METH_read(); - DEF_hg_h_lock_lockVec_3_nextId_57_PLUS_1___d258 = (tUInt8)3u & (DEF_b__h9504 + (tUInt8)1u); - DEF_hg_fifo_Start_TO_Stage__1_first____d168 = INST_hg_fifo_Start_TO_Stage__1.METH_first(); - DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169 = (tUInt32)(DEF_hg_fifo_Start_TO_Stage__1_first____d168 >> 35u); - DEF_b__h9009 = INST_h_rf.METH_sub(DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169); - DEF_h_rf_sub_hg_fifo_Start_TO_Stage__1_first__68_B_ETC___d235 = DEF_b__h9009 + ((tUInt32)(DEF_hg_fifo_Start_TO_Stage__1_first____d168 >> 3u)); - DEF_unsigned_h_rf_sub_hg_fifo_Start_TO_Stage__1_f_ETC___d236 = DEF_h_rf_sub_hg_fifo_Start_TO_Stage__1_first__68_B_ETC___d235; - DEF_hg_h_lock_entryVec_3___d59 = INST_hg_h_lock_entryVec_3.METH_read(); - DEF_hg_h_lock_entryVec_3_9_BIT_10___d60 = (tUInt8)(DEF_hg_h_lock_entryVec_3___d59 >> 10u); - DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209 = !DEF_hg_h_lock_entryVec_3_9_BIT_10___d60; - DEF_hg_h_lock_entryVec_1___d49 = INST_hg_h_lock_entryVec_1.METH_read(); - DEF_hg_h_lock_entryVec_1_9_BIT_10___d50 = (tUInt8)(DEF_hg_h_lock_entryVec_1___d49 >> 10u); - DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187 = !DEF_hg_h_lock_entryVec_1_9_BIT_10___d50; - DEF_hg_h_lock_entryVec_2___d54 = INST_hg_h_lock_entryVec_2.METH_read(); - DEF_hg_h_lock_entryVec_2_4_BIT_10___d55 = (tUInt8)(DEF_hg_h_lock_entryVec_2___d54 >> 10u); - DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184 = !DEF_hg_h_lock_entryVec_2_4_BIT_10___d55; - DEF_hg_h_lock_entryVec_0___d44 = INST_hg_h_lock_entryVec_0.METH_read(); - DEF_hg_h_lock_entryVec_0_4_BIT_10___d45 = (tUInt8)(DEF_hg_h_lock_entryVec_0___d44 >> 10u); - DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190 = !DEF_hg_h_lock_entryVec_0_4_BIT_10___d45; - DEF_b__h9805 = INST_hg_h_lock_lockVec_3_cnt.METH_read(); - DEF_hg_h_lock_lockVec_3_cnt_59_PLUS_1___d260 = (tUInt8)3u & (DEF_b__h9805 + (tUInt8)1u); - DEF_b__h9729 = INST_hg_h_lock_lockVec_2_cnt.METH_read(); - DEF_hg_h_lock_lockVec_2_cnt_53_PLUS_1___d254 = (tUInt8)3u & (DEF_b__h9729 + (tUInt8)1u); - DEF_b__h9653 = INST_hg_h_lock_lockVec_1_cnt.METH_read(); - DEF_hg_h_lock_lockVec_1_cnt_47_PLUS_1___d248 = (tUInt8)3u & (DEF_b__h9653 + (tUInt8)1u); - DEF_b__h9577 = INST_hg_h_lock_lockVec_0_cnt.METH_read(); - DEF_hg_h_lock_lockVec_0_cnt_41_PLUS_1___d242 = (tUInt8)3u & (DEF_b__h9577 + (tUInt8)1u); - DEF_b__h8511 = (tUInt32)(1023u & DEF_hg_h_lock_entryVec_3___d59); - DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170 = DEF_b__h8511 == DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169; - DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171 = DEF_hg_h_lock_entryVec_3_9_BIT_10___d60 && DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170; - DEF_b__h8408 = (tUInt32)(1023u & DEF_hg_h_lock_entryVec_0___d44); - DEF_b__h8480 = (tUInt32)(1023u & DEF_hg_h_lock_entryVec_2___d54); - DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173 = DEF_b__h8480 == DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169; - DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174 = DEF_hg_h_lock_entryVec_2_4_BIT_10___d55 && DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173; - DEF_b__h8449 = (tUInt32)(1023u & DEF_hg_h_lock_entryVec_1___d49); - DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176 = DEF_b__h8449 == DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169; - DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177 = DEF_hg_h_lock_entryVec_1_9_BIT_10___d50 && DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176; - DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226 = DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209 || (DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184 || (DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187 || DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190)); - DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179 = DEF_b__h8408 == DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169; - DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183 = DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171 || (DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174 || (DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177 || (DEF_hg_h_lock_entryVec_0_4_BIT_10___d45 && DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179))); - DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192 = DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190 || !DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179; - DEF__1_CONCAT_hg_fifo_Start_TO_Stage__1_first__68_B_ETC___d267 = 2047u & ((((tUInt32)((tUInt8)1u)) << 10u) | DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169); - DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206 = DEF_hg_h_lock_entryVec_1_9_BIT_10___d50 && DEF_hg_h_lock_entryVec_0_4_BIT_10___d45; - DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207 = DEF_hg_h_lock_entryVec_2_4_BIT_10___d55 && DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206; - DEF_x__h9842 = DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207 && DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209 ? (tUInt8)3u : (DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206 && DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184 ? (tUInt8)2u : (DEF_hg_h_lock_entryVec_0_4_BIT_10___d45 && DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187 ? (tUInt8)1u : (tUInt8)0u)); - switch (DEF_x__h9842) { - case (tUInt8)0u: - DEF_SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d276 = DEF_b__h9441; - break; - case (tUInt8)1u: - DEF_SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d276 = DEF_b__h9462; - break; - case (tUInt8)2u: - DEF_SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d276 = DEF_b__h9483; - break; - case (tUInt8)3u: - DEF_SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d276 = DEF_b__h9504; - break; - default: - DEF_SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d276 = (tUInt8)2u; - } - DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193 = (DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187 || !DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176) && DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192; - DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194 = (DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184 || !DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173) && DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193; - DEF_x__h8976 = DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194 && DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171 ? (tUInt8)3u : (DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193 && DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174 ? (tUInt8)2u : (DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192 && DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177 ? (tUInt8)1u : (tUInt8)0u)); - DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d238 = DEF_x__h8976 == (tUInt8)0u && DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183; - DEF__dfoo24 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d238 ? DEF_b__h9441 : DEF_b__h9441; - DEF__dfoo22 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d238 ? DEF_hg_h_lock_lockVec_0_nextId_39_PLUS_1___d240 : DEF_hg_h_lock_lockVec_0_nextId_39_PLUS_1___d240; - DEF__dfoo20 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d238 ? DEF_hg_h_lock_lockVec_0_cnt_41_PLUS_1___d242 : DEF_hg_h_lock_lockVec_0_cnt_41_PLUS_1___d242; - DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d244 = DEF_x__h8976 == (tUInt8)1u && DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183; - DEF__dfoo18 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d244 ? DEF_b__h9462 : DEF_b__h9462; - DEF__dfoo16 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d244 ? DEF_hg_h_lock_lockVec_1_nextId_45_PLUS_1___d246 : DEF_hg_h_lock_lockVec_1_nextId_45_PLUS_1___d246; - DEF__dfoo14 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d244 ? DEF_hg_h_lock_lockVec_1_cnt_47_PLUS_1___d248 : DEF_hg_h_lock_lockVec_1_cnt_47_PLUS_1___d248; - DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d250 = DEF_x__h8976 == (tUInt8)2u && DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183; - DEF__dfoo12 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d250 ? DEF_b__h9483 : DEF_b__h9483; - DEF__dfoo10 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d250 ? DEF_hg_h_lock_lockVec_2_nextId_51_PLUS_1___d252 : DEF_hg_h_lock_lockVec_2_nextId_51_PLUS_1___d252; - DEF__dfoo8 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d250 ? DEF_hg_h_lock_lockVec_2_cnt_53_PLUS_1___d254 : DEF_hg_h_lock_lockVec_2_cnt_53_PLUS_1___d254; - DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d256 = DEF_x__h8976 == (tUInt8)3u && DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183; - DEF__dfoo6 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d256 ? DEF_b__h9504 : DEF_b__h9504; - DEF__dfoo4 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d256 ? DEF_hg_h_lock_lockVec_3_nextId_57_PLUS_1___d258 : DEF_hg_h_lock_lockVec_3_nextId_57_PLUS_1___d258; - DEF__dfoo2 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d256 ? DEF_hg_h_lock_lockVec_3_cnt_59_PLUS_1___d260 : DEF_hg_h_lock_lockVec_3_cnt_59_PLUS_1___d260; - switch (DEF_x__h8976) { - case (tUInt8)0u: - DEF_SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d275 = DEF_b__h9441; - break; - case (tUInt8)1u: - DEF_SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d275 = DEF_b__h9462; - break; - case (tUInt8)2u: - DEF_SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d275 = DEF_b__h9483; - break; - case (tUInt8)3u: - DEF_SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d275 = DEF_b__h9504; - break; - default: - DEF_SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d275 = (tUInt8)2u; - } - DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_ETC___d280 = 281474976710655llu & (((((((tUInt64)(DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169)) << 38u) | (((tUInt64)(DEF_h_rf_sub_hg_fifo_Start_TO_Stage__1_first__68_B_ETC___d235)) << 6u)) | (((tUInt64)((tUInt8)1u)) << 5u)) | (((tUInt64)(DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183 ? DEF_SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d275 : DEF_SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d276)) << 3u)) | (tUInt64)((tUInt8)((tUInt8)7u & DEF_hg_fifo_Start_TO_Stage__1_first____d168))); - DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265 = ((DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209 || !DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170) && DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194) && DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226; - DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d266 = DEF_x__h9842 == (tUInt8)0u && DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265; - DEF__dfoo21 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d238 || DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d266; - DEF__dfoo23 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d238 || DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d266; - DEF__dfoo19 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d238 || DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d266; - DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d269 = DEF_x__h9842 == (tUInt8)1u && DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265; - DEF__dfoo15 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d244 || DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d269; - DEF__dfoo17 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d244 || DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d269; - DEF__dfoo13 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d244 || DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d269; - DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d271 = DEF_x__h9842 == (tUInt8)2u && DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265; - DEF__dfoo9 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d250 || DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d271; - DEF__dfoo11 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d250 || DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d271; - DEF__dfoo7 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d250 || DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d271; - DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d273 = DEF_x__h9842 == (tUInt8)3u && DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265; - DEF__dfoo3 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d256 || DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d273; - DEF__dfoo5 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d256 || DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d273; - DEF__dfoo1 = DEF_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d256 || DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d273; - if (!(PORT_RST_N == (tUInt8)0u)) - dollar_display(sim_hdl, this, "32", DEF_unsigned_h_rf_sub_hg_fifo_Start_TO_Stage__1_f_ETC___d236); - if (DEF__dfoo23) - INST_hg_h_lock_lockVec_0_held.METH_enq(DEF__dfoo24); - if (DEF__dfoo21) - INST_hg_h_lock_lockVec_0_nextId.METH_write(DEF__dfoo22); - if (DEF__dfoo19) - INST_hg_h_lock_lockVec_0_cnt.METH_write(DEF__dfoo20); - if (DEF__dfoo15) - INST_hg_h_lock_lockVec_1_nextId.METH_write(DEF__dfoo16); - if (DEF__dfoo17) - INST_hg_h_lock_lockVec_1_held.METH_enq(DEF__dfoo18); - if (DEF__dfoo13) - INST_hg_h_lock_lockVec_1_cnt.METH_write(DEF__dfoo14); - if (DEF__dfoo11) - INST_hg_h_lock_lockVec_2_held.METH_enq(DEF__dfoo12); - if (DEF__dfoo9) - INST_hg_h_lock_lockVec_2_nextId.METH_write(DEF__dfoo10); - if (DEF__dfoo7) - INST_hg_h_lock_lockVec_2_cnt.METH_write(DEF__dfoo8); - if (DEF__dfoo5) - INST_hg_h_lock_lockVec_3_held.METH_enq(DEF__dfoo6); - if (DEF__dfoo1) - INST_hg_h_lock_lockVec_3_cnt.METH_write(DEF__dfoo2); - if (DEF__dfoo3) - INST_hg_h_lock_lockVec_3_nextId.METH_write(DEF__dfoo4); - if (DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d266) - INST_hg_h_lock_entryVec_0.METH_write(DEF__1_CONCAT_hg_fifo_Start_TO_Stage__1_first__68_B_ETC___d267); - if (DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d269) - INST_hg_h_lock_entryVec_1.METH_write(DEF__1_CONCAT_hg_fifo_Start_TO_Stage__1_first__68_B_ETC___d267); - if (DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d271) - INST_hg_h_lock_entryVec_2.METH_write(DEF__1_CONCAT_hg_fifo_Start_TO_Stage__1_first__68_B_ETC___d267); - if (DEF_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lo_ETC___d273) - INST_hg_h_lock_entryVec_3.METH_write(DEF__1_CONCAT_hg_fifo_Start_TO_Stage__1_first__68_B_ETC___d267); - INST_hg_fifo_Start_TO_Stage__1.METH_deq(); - INST_hg_fifo_Stage__1_TO_Stage__2.METH_enq(DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_ETC___d280); -} - -void MOD_mkCircuit::RL_hg_s_Stage__2_execute() -{ - tUInt8 DEF_hg_h_lock_lockVec_0_held_first__18_EQ_IF_hg_fi_ETC___d329; - tUInt8 DEF_hg_h_lock_lockVec_1_held_first__30_EQ_IF_hg_fi_ETC___d334; - tUInt8 DEF_hg_h_lock_lockVec_2_held_first__35_EQ_IF_hg_fi_ETC___d339; - tUInt8 DEF_hg_h_lock_lockVec_3_held_first__40_EQ_IF_hg_fi_ETC___d344; - tUInt8 DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d327; - tUInt8 DEF_IF_hg_fifo_Stage__1_TO_Stage__2_first__83_BIT__ETC___d321; - tUInt8 DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_2__ETC___d345; - tUInt32 DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_37_ETC___d317; - DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283 = INST_hg_fifo_Stage__1_TO_Stage__2.METH_first(); - DEF_hg_h_lock_entryVec_3___d59 = INST_hg_h_lock_entryVec_3.METH_read(); - DEF_hg_h_lock_entryVec_3_9_BIT_10___d60 = (tUInt8)(DEF_hg_h_lock_entryVec_3___d59 >> 10u); - DEF_hg_h_lock_entryVec_2___d54 = INST_hg_h_lock_entryVec_2.METH_read(); - DEF_hg_h_lock_entryVec_2_4_BIT_10___d55 = (tUInt8)(DEF_hg_h_lock_entryVec_2___d54 >> 10u); - DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184 = !DEF_hg_h_lock_entryVec_2_4_BIT_10___d55; - DEF_hg_h_lock_entryVec_1___d49 = INST_hg_h_lock_entryVec_1.METH_read(); - DEF_hg_h_lock_entryVec_1_9_BIT_10___d50 = (tUInt8)(DEF_hg_h_lock_entryVec_1___d49 >> 10u); - DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187 = !DEF_hg_h_lock_entryVec_1_9_BIT_10___d50; - DEF_hg_h_lock_entryVec_0___d44 = INST_hg_h_lock_entryVec_0.METH_read(); - DEF_hg_h_lock_entryVec_0_4_BIT_10___d45 = (tUInt8)(DEF_hg_h_lock_entryVec_0___d44 >> 10u); - DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190 = !DEF_hg_h_lock_entryVec_0_4_BIT_10___d45; - DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_37_ETC___d317 = (tUInt32)(DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283 >> 6u); - DEF_b__h8480 = (tUInt32)(1023u & DEF_hg_h_lock_entryVec_2___d54); - DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284 = (tUInt32)(DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283 >> 38u); - DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288 = DEF_b__h8480 == DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284; - DEF_b__h8511 = (tUInt32)(1023u & DEF_hg_h_lock_entryVec_3___d59); - DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285 = DEF_b__h8511 == DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284; - DEF_b__h8449 = (tUInt32)(1023u & DEF_hg_h_lock_entryVec_1___d49); - DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291 = DEF_b__h8449 == DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284; - DEF_b__h8408 = (tUInt32)(1023u & DEF_hg_h_lock_entryVec_0___d44); - DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_2__ETC___d345 = (tUInt8)((tUInt8)7u & DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283); - DEF_IF_hg_fifo_Stage__1_TO_Stage__2_first__83_BIT__ETC___d321 = (tUInt8)((tUInt8)1u & (DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283 >> 5u)) ? (tUInt8)((tUInt8)3u & (DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283 >> 3u)) : (tUInt8)0u; - DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294 = DEF_b__h8408 == DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284; - DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300 = DEF_hg_h_lock_entryVec_3_9_BIT_10___d60 && DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285; - DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302 = DEF_hg_h_lock_entryVec_2_4_BIT_10___d55 && DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288; - DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304 = DEF_hg_h_lock_entryVec_1_9_BIT_10___d50 && DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291; - DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d327 = DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300 || (DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302 || (DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304 || (DEF_hg_h_lock_entryVec_0_4_BIT_10___d45 && DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294))); - DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296 = DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190 || !DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294; - DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297 = (DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187 || !DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291) && DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296; - DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298 = (DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184 || !DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288) && DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297; - DEF_x__h10519 = DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298 && DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300 ? (tUInt8)3u : (DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297 && DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302 ? (tUInt8)2u : (DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296 && DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304 ? (tUInt8)1u : (tUInt8)0u)); - DEF_hg_h_lock_lockVec_3_held_first__40_EQ_IF_hg_fi_ETC___d344 = INST_hg_h_lock_lockVec_3_held.METH_first() == DEF_IF_hg_fifo_Stage__1_TO_Stage__2_first__83_BIT__ETC___d321 && (DEF_x__h10519 == (tUInt8)3u && DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d327); - DEF_hg_h_lock_lockVec_2_held_first__35_EQ_IF_hg_fi_ETC___d339 = INST_hg_h_lock_lockVec_2_held.METH_first() == DEF_IF_hg_fifo_Stage__1_TO_Stage__2_first__83_BIT__ETC___d321 && (DEF_x__h10519 == (tUInt8)2u && DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d327); - DEF_hg_h_lock_lockVec_1_held_first__30_EQ_IF_hg_fi_ETC___d334 = INST_hg_h_lock_lockVec_1_held.METH_first() == DEF_IF_hg_fifo_Stage__1_TO_Stage__2_first__83_BIT__ETC___d321 && (DEF_x__h10519 == (tUInt8)1u && DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d327); - DEF_hg_h_lock_lockVec_0_held_first__18_EQ_IF_hg_fi_ETC___d329 = INST_hg_h_lock_lockVec_0_held.METH_first() == DEF_IF_hg_fifo_Stage__1_TO_Stage__2_first__83_BIT__ETC___d321 && (DEF_x__h10519 == (tUInt8)0u && DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d327); - INST_h_rf.METH_upd(DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284, - DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_37_ETC___d317); - if (DEF_hg_h_lock_lockVec_0_held_first__18_EQ_IF_hg_fi_ETC___d329) - INST_hg_h_lock_lockVec_0_held.METH_deq(); - if (DEF_hg_h_lock_lockVec_1_held_first__30_EQ_IF_hg_fi_ETC___d334) - INST_hg_h_lock_lockVec_1_held.METH_deq(); - if (DEF_hg_h_lock_lockVec_2_held_first__35_EQ_IF_hg_fi_ETC___d339) - INST_hg_h_lock_lockVec_2_held.METH_deq(); - if (DEF_hg_h_lock_lockVec_3_held_first__40_EQ_IF_hg_fi_ETC___d344) - INST_hg_h_lock_lockVec_3_held.METH_deq(); - INST_hg_fifo_Stage__1_TO_Stage__2.METH_deq(); - INST_hg_fifo_Stage__2_TO_Stage__3.METH_enq(DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_2__ETC___d345); -} - -void MOD_mkCircuit::RL_hg_s_Stage__3_execute() -{ - INST_hg_fifo_Stage__2_TO_Stage__3.METH_deq(); -} - - -/* Methods */ - -tUInt8 MOD_mkCircuit::METH__inthg_req(tUInt32 ARG__inthg_req_counter) -{ - tUInt8 DEF_hg_47_PLUS_1___d349; - tUInt32 DEF_inthg_req_counter_CONCAT_hg_47___d348; - tUInt8 DEF_b__h10847; - tUInt8 PORT__inthg_req; - PORT_EN__inthg_req = (tUInt8)1u; - DEF_WILL_FIRE__inthg_req = (tUInt8)1u; - DEF_b__h10847 = INST_hg.METH_read(); - PORT__inthg_req = DEF_b__h10847; - DEF_inthg_req_counter_CONCAT_hg_47___d348 = 8191u & ((ARG__inthg_req_counter << 3u) | (tUInt32)(DEF_b__h10847)); - DEF_hg_47_PLUS_1___d349 = (tUInt8)7u & (DEF_b__h10847 + (tUInt8)1u); - INST_hg_fifo__input__TO_Start.METH_enq(DEF_inthg_req_counter_CONCAT_hg_47___d348); - INST_hg_busyReg.METH_write((tUInt8)1u); - INST_hg.METH_write(DEF_hg_47_PLUS_1___d349); - return PORT__inthg_req; -} - -tUInt8 MOD_mkCircuit::METH_RDY__inthg_req() -{ - tUInt8 DEF_CAN_FIRE__inthg_req; - tUInt8 PORT_RDY__inthg_req; - DEF_hg_fifo__input__TO_Start_i_notFull____d66 = INST_hg_fifo__input__TO_Start.METH_i_notFull(); - DEF_hg_busyReg__h7113 = INST_hg_busyReg.METH_read(); - DEF_CAN_FIRE__inthg_req = !DEF_hg_busyReg__h7113 && DEF_hg_fifo__input__TO_Start_i_notFull____d66; - PORT_RDY__inthg_req = DEF_CAN_FIRE__inthg_req; - return PORT_RDY__inthg_req; -} - -void MOD_mkCircuit::METH__inthg_resp() -{ - INST_hg_outputQueue.METH_deq(); -} - -tUInt8 MOD_mkCircuit::METH_RDY__inthg_resp() -{ - tUInt8 DEF_CAN_FIRE__inthg_resp; - tUInt8 PORT_RDY__inthg_resp; - DEF_hg_outputQueue_i_notEmpty____d351 = INST_hg_outputQueue.METH_i_notEmpty(); - DEF_CAN_FIRE__inthg_resp = DEF_hg_outputQueue_i_notEmpty____d351; - PORT_RDY__inthg_resp = DEF_CAN_FIRE__inthg_resp; - return PORT_RDY__inthg_resp; -} - -tUInt8 MOD_mkCircuit::METH__inthg_checkHandle(tUInt8 ARG__inthg_checkHandle_handle) -{ - tUInt8 DEF_hg_outputQueue_first__52_BITS_3_TO_1___d353; - tUInt8 PORT__inthg_checkHandle; - DEF_hg_outputQueue_first____d352 = INST_hg_outputQueue.METH_first(); - DEF_hg_outputQueue_first__52_BITS_3_TO_1___d353 = (tUInt8)(DEF_hg_outputQueue_first____d352 >> 1u); - PORT__inthg_checkHandle = ARG__inthg_checkHandle_handle == DEF_hg_outputQueue_first__52_BITS_3_TO_1___d353; - return PORT__inthg_checkHandle; -} - -tUInt8 MOD_mkCircuit::METH_RDY__inthg_checkHandle() -{ - tUInt8 DEF_CAN_FIRE__inthg_checkHandle; - tUInt8 PORT_RDY__inthg_checkHandle; - DEF_hg_outputQueue_i_notEmpty____d351 = INST_hg_outputQueue.METH_i_notEmpty(); - DEF_CAN_FIRE__inthg_checkHandle = DEF_hg_outputQueue_i_notEmpty____d351; - PORT_RDY__inthg_checkHandle = DEF_CAN_FIRE__inthg_checkHandle; - return PORT_RDY__inthg_checkHandle; -} - -tUInt8 MOD_mkCircuit::METH__inthg_peek() -{ - tUInt8 PORT__inthg_peek; - DEF_hg_outputQueue_first____d352 = INST_hg_outputQueue.METH_first(); - PORT__inthg_peek = (tUInt8)((tUInt8)1u & DEF_hg_outputQueue_first____d352); - return PORT__inthg_peek; -} - -tUInt8 MOD_mkCircuit::METH_RDY__inthg_peek() -{ - tUInt8 DEF_CAN_FIRE__inthg_peek; - tUInt8 PORT_RDY__inthg_peek; - DEF_hg_outputQueue_i_notEmpty____d351 = INST_hg_outputQueue.METH_i_notEmpty(); - DEF_CAN_FIRE__inthg_peek = DEF_hg_outputQueue_i_notEmpty____d351; - PORT_RDY__inthg_peek = DEF_CAN_FIRE__inthg_peek; - return PORT_RDY__inthg_peek; -} - - -/* Reset routines */ - -void MOD_mkCircuit::reset_RST_N(tUInt8 ARG_rst_in) -{ - PORT_RST_N = ARG_rst_in; - INST_hg_weight_lock_region.reset_RST(ARG_rst_in); - INST_hg_weight_lock_lockVec_3_nextId.reset_RST(ARG_rst_in); - INST_hg_weight_lock_lockVec_3_held.reset_RST(ARG_rst_in); - INST_hg_weight_lock_lockVec_3_cnt.reset_RST(ARG_rst_in); - INST_hg_weight_lock_lockVec_2_nextId.reset_RST(ARG_rst_in); - INST_hg_weight_lock_lockVec_2_held.reset_RST(ARG_rst_in); - INST_hg_weight_lock_lockVec_2_cnt.reset_RST(ARG_rst_in); - INST_hg_weight_lock_lockVec_1_nextId.reset_RST(ARG_rst_in); - INST_hg_weight_lock_lockVec_1_held.reset_RST(ARG_rst_in); - INST_hg_weight_lock_lockVec_1_cnt.reset_RST(ARG_rst_in); - INST_hg_weight_lock_lockVec_0_nextId.reset_RST(ARG_rst_in); - INST_hg_weight_lock_lockVec_0_held.reset_RST(ARG_rst_in); - INST_hg_weight_lock_lockVec_0_cnt.reset_RST(ARG_rst_in); - INST_hg_weight_lock_entryVec_3.reset_RST(ARG_rst_in); - INST_hg_weight_lock_entryVec_2.reset_RST(ARG_rst_in); - INST_hg_weight_lock_entryVec_1.reset_RST(ARG_rst_in); - INST_hg_weight_lock_entryVec_0.reset_RST(ARG_rst_in); - INST_hg_outputQueue.reset_RST(ARG_rst_in); - INST_hg_h_lock_region.reset_RST(ARG_rst_in); - INST_hg_h_lock_lockVec_3_nextId.reset_RST(ARG_rst_in); - INST_hg_h_lock_lockVec_3_held.reset_RST(ARG_rst_in); - INST_hg_h_lock_lockVec_3_cnt.reset_RST(ARG_rst_in); - INST_hg_h_lock_lockVec_2_nextId.reset_RST(ARG_rst_in); - INST_hg_h_lock_lockVec_2_held.reset_RST(ARG_rst_in); - INST_hg_h_lock_lockVec_2_cnt.reset_RST(ARG_rst_in); - INST_hg_h_lock_lockVec_1_nextId.reset_RST(ARG_rst_in); - INST_hg_h_lock_lockVec_1_held.reset_RST(ARG_rst_in); - INST_hg_h_lock_lockVec_1_cnt.reset_RST(ARG_rst_in); - INST_hg_h_lock_lockVec_0_nextId.reset_RST(ARG_rst_in); - INST_hg_h_lock_lockVec_0_held.reset_RST(ARG_rst_in); - INST_hg_h_lock_lockVec_0_cnt.reset_RST(ARG_rst_in); - INST_hg_h_lock_entryVec_3.reset_RST(ARG_rst_in); - INST_hg_h_lock_entryVec_2.reset_RST(ARG_rst_in); - INST_hg_h_lock_entryVec_1.reset_RST(ARG_rst_in); - INST_hg_h_lock_entryVec_0.reset_RST(ARG_rst_in); - INST_hg_fifo__input__TO_Start.reset_RST(ARG_rst_in); - INST_hg_fifo_Start_TO_Stage__1.reset_RST(ARG_rst_in); - INST_hg_fifo_Stage__2_TO_Stage__3.reset_RST(ARG_rst_in); - INST_hg_fifo_Stage__1_TO_Stage__2.reset_RST(ARG_rst_in); - INST_hg_feature_lock_region.reset_RST(ARG_rst_in); - INST_hg_feature_lock_lockVec_3_nextId.reset_RST(ARG_rst_in); - INST_hg_feature_lock_lockVec_3_held.reset_RST(ARG_rst_in); - INST_hg_feature_lock_lockVec_3_cnt.reset_RST(ARG_rst_in); - INST_hg_feature_lock_lockVec_2_nextId.reset_RST(ARG_rst_in); - INST_hg_feature_lock_lockVec_2_held.reset_RST(ARG_rst_in); - INST_hg_feature_lock_lockVec_2_cnt.reset_RST(ARG_rst_in); - INST_hg_feature_lock_lockVec_1_nextId.reset_RST(ARG_rst_in); - INST_hg_feature_lock_lockVec_1_held.reset_RST(ARG_rst_in); - INST_hg_feature_lock_lockVec_1_cnt.reset_RST(ARG_rst_in); - INST_hg_feature_lock_lockVec_0_nextId.reset_RST(ARG_rst_in); - INST_hg_feature_lock_lockVec_0_held.reset_RST(ARG_rst_in); - INST_hg_feature_lock_lockVec_0_cnt.reset_RST(ARG_rst_in); - INST_hg_feature_lock_entryVec_3.reset_RST(ARG_rst_in); - INST_hg_feature_lock_entryVec_2.reset_RST(ARG_rst_in); - INST_hg_feature_lock_entryVec_1.reset_RST(ARG_rst_in); - INST_hg_feature_lock_entryVec_0.reset_RST(ARG_rst_in); - INST_hg_busyReg.reset_RST(ARG_rst_in); - INST_hg.reset_RST(ARG_rst_in); -} - - -/* Static handles to reset routines */ - - -/* Functions for the parent module to register its reset fns */ - - -/* Functions to set the elaborated clock id */ - -void MOD_mkCircuit::set_clk_0(char const *s) -{ - __clk_handle_0 = bk_get_or_define_clock(sim_hdl, s); -} - - -/* State dumping routine */ -void MOD_mkCircuit::dump_state(unsigned int indent) -{ - printf("%*s%s:\n", indent, "", inst_name); - INST_f_rf.dump_state(indent + 2u); - INST_h_rf.dump_state(indent + 2u); - INST_hg.dump_state(indent + 2u); - INST_hg_busyReg.dump_state(indent + 2u); - INST_hg_feature_lock_entryVec_0.dump_state(indent + 2u); - INST_hg_feature_lock_entryVec_1.dump_state(indent + 2u); - INST_hg_feature_lock_entryVec_2.dump_state(indent + 2u); - INST_hg_feature_lock_entryVec_3.dump_state(indent + 2u); - INST_hg_feature_lock_lockVec_0_cnt.dump_state(indent + 2u); - INST_hg_feature_lock_lockVec_0_held.dump_state(indent + 2u); - INST_hg_feature_lock_lockVec_0_nextId.dump_state(indent + 2u); - INST_hg_feature_lock_lockVec_1_cnt.dump_state(indent + 2u); - INST_hg_feature_lock_lockVec_1_held.dump_state(indent + 2u); - INST_hg_feature_lock_lockVec_1_nextId.dump_state(indent + 2u); - INST_hg_feature_lock_lockVec_2_cnt.dump_state(indent + 2u); - INST_hg_feature_lock_lockVec_2_held.dump_state(indent + 2u); - INST_hg_feature_lock_lockVec_2_nextId.dump_state(indent + 2u); - INST_hg_feature_lock_lockVec_3_cnt.dump_state(indent + 2u); - INST_hg_feature_lock_lockVec_3_held.dump_state(indent + 2u); - INST_hg_feature_lock_lockVec_3_nextId.dump_state(indent + 2u); - INST_hg_feature_lock_region.dump_state(indent + 2u); - INST_hg_fifo_Stage__1_TO_Stage__2.dump_state(indent + 2u); - INST_hg_fifo_Stage__2_TO_Stage__3.dump_state(indent + 2u); - INST_hg_fifo_Start_TO_Stage__1.dump_state(indent + 2u); - INST_hg_fifo__input__TO_Start.dump_state(indent + 2u); - INST_hg_h_lock_entryVec_0.dump_state(indent + 2u); - INST_hg_h_lock_entryVec_1.dump_state(indent + 2u); - INST_hg_h_lock_entryVec_2.dump_state(indent + 2u); - INST_hg_h_lock_entryVec_3.dump_state(indent + 2u); - INST_hg_h_lock_lockVec_0_cnt.dump_state(indent + 2u); - INST_hg_h_lock_lockVec_0_held.dump_state(indent + 2u); - INST_hg_h_lock_lockVec_0_nextId.dump_state(indent + 2u); - INST_hg_h_lock_lockVec_1_cnt.dump_state(indent + 2u); - INST_hg_h_lock_lockVec_1_held.dump_state(indent + 2u); - INST_hg_h_lock_lockVec_1_nextId.dump_state(indent + 2u); - INST_hg_h_lock_lockVec_2_cnt.dump_state(indent + 2u); - INST_hg_h_lock_lockVec_2_held.dump_state(indent + 2u); - INST_hg_h_lock_lockVec_2_nextId.dump_state(indent + 2u); - INST_hg_h_lock_lockVec_3_cnt.dump_state(indent + 2u); - INST_hg_h_lock_lockVec_3_held.dump_state(indent + 2u); - INST_hg_h_lock_lockVec_3_nextId.dump_state(indent + 2u); - INST_hg_h_lock_region.dump_state(indent + 2u); - INST_hg_outputQueue.dump_state(indent + 2u); - INST_hg_weight_lock_entryVec_0.dump_state(indent + 2u); - INST_hg_weight_lock_entryVec_1.dump_state(indent + 2u); - INST_hg_weight_lock_entryVec_2.dump_state(indent + 2u); - INST_hg_weight_lock_entryVec_3.dump_state(indent + 2u); - INST_hg_weight_lock_lockVec_0_cnt.dump_state(indent + 2u); - INST_hg_weight_lock_lockVec_0_held.dump_state(indent + 2u); - INST_hg_weight_lock_lockVec_0_nextId.dump_state(indent + 2u); - INST_hg_weight_lock_lockVec_1_cnt.dump_state(indent + 2u); - INST_hg_weight_lock_lockVec_1_held.dump_state(indent + 2u); - INST_hg_weight_lock_lockVec_1_nextId.dump_state(indent + 2u); - INST_hg_weight_lock_lockVec_2_cnt.dump_state(indent + 2u); - INST_hg_weight_lock_lockVec_2_held.dump_state(indent + 2u); - INST_hg_weight_lock_lockVec_2_nextId.dump_state(indent + 2u); - INST_hg_weight_lock_lockVec_3_cnt.dump_state(indent + 2u); - INST_hg_weight_lock_lockVec_3_held.dump_state(indent + 2u); - INST_hg_weight_lock_lockVec_3_nextId.dump_state(indent + 2u); - INST_hg_weight_lock_region.dump_state(indent + 2u); - INST_w_rf.dump_state(indent + 2u); -} - - -/* VCD dumping routines */ - -unsigned int MOD_mkCircuit::dump_VCD_defs(unsigned int levels) -{ - vcd_write_scope_start(sim_hdl, inst_name); - vcd_num = vcd_reserve_ids(sim_hdl, 148u); - unsigned int num = vcd_num; - for (unsigned int clk = 0u; clk < bk_num_clocks(sim_hdl); ++clk) - vcd_add_clock_def(sim_hdl, this, bk_clock_name(sim_hdl, clk), bk_clock_vcd_num(sim_hdl, clk)); - vcd_write_def(sim_hdl, bk_clock_vcd_num(sim_hdl, __clk_handle_0), "CLK", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_feature_lock_lockVec_0_held_notEmpty___d2", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_feature_lock_lockVec_1_held_notEmpty___d8", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_feature_lock_lockVec_2_held_notEmpty__2___d13", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_feature_lock_lockVec_3_held_notEmpty__7___d18", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_lockVec_0_held_notEmpty__2___d43", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_lockVec_1_held_notEmpty__7___d48", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_lockVec_2_held_notEmpty__2___d53", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_h_lock_lockVec_3_held_notEmpty__7___d58", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_weight_lock_lockVec_0_held_notEmpty__2___d23", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_weight_lock_lockVec_1_held_notEmpty__7___d28", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_weight_lock_lockVec_2_held_notEmpty__2___d33", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "NOT_hg_weight_lock_lockVec_3_held_notEmpty__7___d38", 1u); - vcd_write_def(sim_hdl, num++, "RST_N", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "WILL_FIRE__inthg_req", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "_0_CONCAT_DONTCARE___d6", 11u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "b__h8408", 10u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "b__h8449", 10u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "b__h8480", 10u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "b__h8511", 10u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_busyReg__h7113", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_feature_lock_entryVec_0_BIT_10___d4", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_feature_lock_entryVec_0___d3", 11u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_feature_lock_entryVec_1_BIT_10___d10", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_feature_lock_entryVec_1___d9", 11u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_feature_lock_entryVec_2_4_BIT_10___d15", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_feature_lock_entryVec_2___d14", 11u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_feature_lock_entryVec_3_9_BIT_10___d20", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_feature_lock_entryVec_3___d19", 11u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284", 10u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_fifo_Stage__1_TO_Stage__2_first____d283", 48u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169", 10u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_fifo_Start_TO_Stage__1_first____d168", 45u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64", 10u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_fifo__input__TO_Start_first____d63", 13u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_fifo__input__TO_Start_i_notFull____d66", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_0_4_BIT_10___d45", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_0___d44", 11u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_1_9_BIT_10___d50", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_1___d49", 11u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_2_4_BIT_10___d55", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_2___d54", 11u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_3_9_BIT_10___d60", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_h_lock_entryVec_3___d59", 11u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_outputQueue_first____d352", 4u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_outputQueue_i_notEmpty____d351", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_weight_lock_entryVec_0_4_BIT_10___d25", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_weight_lock_entryVec_0___d24", 11u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_weight_lock_entryVec_1_9_BIT_10___d30", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_weight_lock_entryVec_1___d29", 11u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_weight_lock_entryVec_2_4_BIT_10___d35", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_weight_lock_entryVec_2___d34", 11u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_weight_lock_entryVec_3_9_BIT_10___d40", 1u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "hg_weight_lock_entryVec_3___d39", 11u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "x__h10519", 2u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "x__h8976", 2u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "x__h9842", 2u); - vcd_set_clock(sim_hdl, num, __clk_handle_0); - vcd_write_def(sim_hdl, num++, "EN__inthg_req", 1u); - num = INST_f_rf.dump_VCD_defs(num); - num = INST_h_rf.dump_VCD_defs(num); - num = INST_hg.dump_VCD_defs(num); - num = INST_hg_busyReg.dump_VCD_defs(num); - num = INST_hg_feature_lock_entryVec_0.dump_VCD_defs(num); - num = INST_hg_feature_lock_entryVec_1.dump_VCD_defs(num); - num = INST_hg_feature_lock_entryVec_2.dump_VCD_defs(num); - num = INST_hg_feature_lock_entryVec_3.dump_VCD_defs(num); - num = INST_hg_feature_lock_lockVec_0_cnt.dump_VCD_defs(num); - num = INST_hg_feature_lock_lockVec_0_held.dump_VCD_defs(num); - num = INST_hg_feature_lock_lockVec_0_nextId.dump_VCD_defs(num); - num = INST_hg_feature_lock_lockVec_1_cnt.dump_VCD_defs(num); - num = INST_hg_feature_lock_lockVec_1_held.dump_VCD_defs(num); - num = INST_hg_feature_lock_lockVec_1_nextId.dump_VCD_defs(num); - num = INST_hg_feature_lock_lockVec_2_cnt.dump_VCD_defs(num); - num = INST_hg_feature_lock_lockVec_2_held.dump_VCD_defs(num); - num = INST_hg_feature_lock_lockVec_2_nextId.dump_VCD_defs(num); - num = INST_hg_feature_lock_lockVec_3_cnt.dump_VCD_defs(num); - num = INST_hg_feature_lock_lockVec_3_held.dump_VCD_defs(num); - num = INST_hg_feature_lock_lockVec_3_nextId.dump_VCD_defs(num); - num = INST_hg_feature_lock_region.dump_VCD_defs(num); - num = INST_hg_fifo_Stage__1_TO_Stage__2.dump_VCD_defs(num); - num = INST_hg_fifo_Stage__2_TO_Stage__3.dump_VCD_defs(num); - num = INST_hg_fifo_Start_TO_Stage__1.dump_VCD_defs(num); - num = INST_hg_fifo__input__TO_Start.dump_VCD_defs(num); - num = INST_hg_h_lock_entryVec_0.dump_VCD_defs(num); - num = INST_hg_h_lock_entryVec_1.dump_VCD_defs(num); - num = INST_hg_h_lock_entryVec_2.dump_VCD_defs(num); - num = INST_hg_h_lock_entryVec_3.dump_VCD_defs(num); - num = INST_hg_h_lock_lockVec_0_cnt.dump_VCD_defs(num); - num = INST_hg_h_lock_lockVec_0_held.dump_VCD_defs(num); - num = INST_hg_h_lock_lockVec_0_nextId.dump_VCD_defs(num); - num = INST_hg_h_lock_lockVec_1_cnt.dump_VCD_defs(num); - num = INST_hg_h_lock_lockVec_1_held.dump_VCD_defs(num); - num = INST_hg_h_lock_lockVec_1_nextId.dump_VCD_defs(num); - num = INST_hg_h_lock_lockVec_2_cnt.dump_VCD_defs(num); - num = INST_hg_h_lock_lockVec_2_held.dump_VCD_defs(num); - num = INST_hg_h_lock_lockVec_2_nextId.dump_VCD_defs(num); - num = INST_hg_h_lock_lockVec_3_cnt.dump_VCD_defs(num); - num = INST_hg_h_lock_lockVec_3_held.dump_VCD_defs(num); - num = INST_hg_h_lock_lockVec_3_nextId.dump_VCD_defs(num); - num = INST_hg_h_lock_region.dump_VCD_defs(num); - num = INST_hg_outputQueue.dump_VCD_defs(num); - num = INST_hg_weight_lock_entryVec_0.dump_VCD_defs(num); - num = INST_hg_weight_lock_entryVec_1.dump_VCD_defs(num); - num = INST_hg_weight_lock_entryVec_2.dump_VCD_defs(num); - num = INST_hg_weight_lock_entryVec_3.dump_VCD_defs(num); - num = INST_hg_weight_lock_lockVec_0_cnt.dump_VCD_defs(num); - num = INST_hg_weight_lock_lockVec_0_held.dump_VCD_defs(num); - num = INST_hg_weight_lock_lockVec_0_nextId.dump_VCD_defs(num); - num = INST_hg_weight_lock_lockVec_1_cnt.dump_VCD_defs(num); - num = INST_hg_weight_lock_lockVec_1_held.dump_VCD_defs(num); - num = INST_hg_weight_lock_lockVec_1_nextId.dump_VCD_defs(num); - num = INST_hg_weight_lock_lockVec_2_cnt.dump_VCD_defs(num); - num = INST_hg_weight_lock_lockVec_2_held.dump_VCD_defs(num); - num = INST_hg_weight_lock_lockVec_2_nextId.dump_VCD_defs(num); - num = INST_hg_weight_lock_lockVec_3_cnt.dump_VCD_defs(num); - num = INST_hg_weight_lock_lockVec_3_held.dump_VCD_defs(num); - num = INST_hg_weight_lock_lockVec_3_nextId.dump_VCD_defs(num); - num = INST_hg_weight_lock_region.dump_VCD_defs(num); - num = INST_w_rf.dump_VCD_defs(num); - vcd_write_scope_end(sim_hdl); - return num; -} - -void MOD_mkCircuit::dump_VCD(tVCDDumpType dt, unsigned int levels, MOD_mkCircuit &backing) -{ - vcd_defs(dt, backing); - vcd_prims(dt, backing); -} - -void MOD_mkCircuit::vcd_defs(tVCDDumpType dt, MOD_mkCircuit &backing) -{ - unsigned int num = vcd_num; - if (dt == VCD_DUMP_XS) - { - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 11u); - vcd_write_x(sim_hdl, num++, 10u); - vcd_write_x(sim_hdl, num++, 10u); - vcd_write_x(sim_hdl, num++, 10u); - vcd_write_x(sim_hdl, num++, 10u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 11u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 11u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 11u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 11u); - vcd_write_x(sim_hdl, num++, 10u); - vcd_write_x(sim_hdl, num++, 48u); - vcd_write_x(sim_hdl, num++, 10u); - vcd_write_x(sim_hdl, num++, 45u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 10u); - vcd_write_x(sim_hdl, num++, 13u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 11u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 11u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 11u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 11u); - vcd_write_x(sim_hdl, num++, 4u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 11u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 11u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 11u); - vcd_write_x(sim_hdl, num++, 1u); - vcd_write_x(sim_hdl, num++, 11u); - vcd_write_x(sim_hdl, num++, 2u); - vcd_write_x(sim_hdl, num++, 2u); - vcd_write_x(sim_hdl, num++, 2u); - vcd_write_x(sim_hdl, num++, 1u); - } - else - if (dt == VCD_DUMP_CHANGES) - { - if ((backing.DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty___d2) != DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty___d2) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty___d2, 1u); - backing.DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty___d2 = DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty___d2; - } - ++num; - if ((backing.DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty___d8) != DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty___d8) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty___d8, 1u); - backing.DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty___d8 = DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty___d8; - } - ++num; - if ((backing.DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2___d13) != DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2___d13) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2___d13, 1u); - backing.DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2___d13 = DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2___d13; - } - ++num; - if ((backing.DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7___d18) != DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7___d18) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7___d18, 1u); - backing.DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7___d18 = DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7___d18; - } - ++num; - if ((backing.DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74) != DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74, 1u); - backing.DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74 = DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192) != DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192 = DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296) != DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296 = DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190) != DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190 = DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193) != DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193 = DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297) != DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297 = DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187) != DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187 = DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194) != DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194 = DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298) != DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298 = DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184) != DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184 = DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226) != DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226 = DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209) != DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209 = DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2___d43) != DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2___d43) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2___d43, 1u); - backing.DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2___d43 = DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2___d43; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7___d48) != DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7___d48) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7___d48, 1u); - backing.DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7___d48 = DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7___d48; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2___d53) != DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2___d53) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2___d53, 1u); - backing.DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2___d53 = DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2___d53; - } - ++num; - if ((backing.DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7___d58) != DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7___d58) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7___d58, 1u); - backing.DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7___d58 = DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7___d58; - } - ++num; - if ((backing.DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2___d23) != DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2___d23) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2___d23, 1u); - backing.DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2___d23 = DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2___d23; - } - ++num; - if ((backing.DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7___d28) != DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7___d28) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7___d28, 1u); - backing.DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7___d28 = DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7___d28; - } - ++num; - if ((backing.DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2___d33) != DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2___d33) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2___d33, 1u); - backing.DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2___d33 = DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2___d33; - } - ++num; - if ((backing.DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7___d38) != DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7___d38) - { - vcd_write_val(sim_hdl, num, DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7___d38, 1u); - backing.DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7___d38 = DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7___d38; - } - ++num; - if ((backing.PORT_RST_N) != PORT_RST_N) - { - vcd_write_val(sim_hdl, num, PORT_RST_N, 1u); - backing.PORT_RST_N = PORT_RST_N; - } - ++num; - if ((backing.DEF_WILL_FIRE__inthg_req) != DEF_WILL_FIRE__inthg_req) - { - vcd_write_val(sim_hdl, num, DEF_WILL_FIRE__inthg_req, 1u); - backing.DEF_WILL_FIRE__inthg_req = DEF_WILL_FIRE__inthg_req; - } - ++num; - if ((backing.DEF__0_CONCAT_DONTCARE___d6) != DEF__0_CONCAT_DONTCARE___d6) - { - vcd_write_val(sim_hdl, num, DEF__0_CONCAT_DONTCARE___d6, 11u); - backing.DEF__0_CONCAT_DONTCARE___d6 = DEF__0_CONCAT_DONTCARE___d6; - } - ++num; - if ((backing.DEF_b__h8408) != DEF_b__h8408) - { - vcd_write_val(sim_hdl, num, DEF_b__h8408, 10u); - backing.DEF_b__h8408 = DEF_b__h8408; - } - ++num; - if ((backing.DEF_b__h8449) != DEF_b__h8449) - { - vcd_write_val(sim_hdl, num, DEF_b__h8449, 10u); - backing.DEF_b__h8449 = DEF_b__h8449; - } - ++num; - if ((backing.DEF_b__h8480) != DEF_b__h8480) - { - vcd_write_val(sim_hdl, num, DEF_b__h8480, 10u); - backing.DEF_b__h8480 = DEF_b__h8480; - } - ++num; - if ((backing.DEF_b__h8511) != DEF_b__h8511) - { - vcd_write_val(sim_hdl, num, DEF_b__h8511, 10u); - backing.DEF_b__h8511 = DEF_b__h8511; - } - ++num; - if ((backing.DEF_hg_busyReg__h7113) != DEF_hg_busyReg__h7113) - { - vcd_write_val(sim_hdl, num, DEF_hg_busyReg__h7113, 1u); - backing.DEF_hg_busyReg__h7113 = DEF_hg_busyReg__h7113; - } - ++num; - if ((backing.DEF_hg_feature_lock_entryVec_0_BIT_10___d4) != DEF_hg_feature_lock_entryVec_0_BIT_10___d4) - { - vcd_write_val(sim_hdl, num, DEF_hg_feature_lock_entryVec_0_BIT_10___d4, 1u); - backing.DEF_hg_feature_lock_entryVec_0_BIT_10___d4 = DEF_hg_feature_lock_entryVec_0_BIT_10___d4; - } - ++num; - if ((backing.DEF_hg_feature_lock_entryVec_0___d3) != DEF_hg_feature_lock_entryVec_0___d3) - { - vcd_write_val(sim_hdl, num, DEF_hg_feature_lock_entryVec_0___d3, 11u); - backing.DEF_hg_feature_lock_entryVec_0___d3 = DEF_hg_feature_lock_entryVec_0___d3; - } - ++num; - if ((backing.DEF_hg_feature_lock_entryVec_1_BIT_10___d10) != DEF_hg_feature_lock_entryVec_1_BIT_10___d10) - { - vcd_write_val(sim_hdl, num, DEF_hg_feature_lock_entryVec_1_BIT_10___d10, 1u); - backing.DEF_hg_feature_lock_entryVec_1_BIT_10___d10 = DEF_hg_feature_lock_entryVec_1_BIT_10___d10; - } - ++num; - if ((backing.DEF_hg_feature_lock_entryVec_1___d9) != DEF_hg_feature_lock_entryVec_1___d9) - { - vcd_write_val(sim_hdl, num, DEF_hg_feature_lock_entryVec_1___d9, 11u); - backing.DEF_hg_feature_lock_entryVec_1___d9 = DEF_hg_feature_lock_entryVec_1___d9; - } - ++num; - if ((backing.DEF_hg_feature_lock_entryVec_2_4_BIT_10___d15) != DEF_hg_feature_lock_entryVec_2_4_BIT_10___d15) - { - vcd_write_val(sim_hdl, num, DEF_hg_feature_lock_entryVec_2_4_BIT_10___d15, 1u); - backing.DEF_hg_feature_lock_entryVec_2_4_BIT_10___d15 = DEF_hg_feature_lock_entryVec_2_4_BIT_10___d15; - } - ++num; - if ((backing.DEF_hg_feature_lock_entryVec_2___d14) != DEF_hg_feature_lock_entryVec_2___d14) - { - vcd_write_val(sim_hdl, num, DEF_hg_feature_lock_entryVec_2___d14, 11u); - backing.DEF_hg_feature_lock_entryVec_2___d14 = DEF_hg_feature_lock_entryVec_2___d14; - } - ++num; - if ((backing.DEF_hg_feature_lock_entryVec_3_9_BIT_10___d20) != DEF_hg_feature_lock_entryVec_3_9_BIT_10___d20) - { - vcd_write_val(sim_hdl, num, DEF_hg_feature_lock_entryVec_3_9_BIT_10___d20, 1u); - backing.DEF_hg_feature_lock_entryVec_3_9_BIT_10___d20 = DEF_hg_feature_lock_entryVec_3_9_BIT_10___d20; - } - ++num; - if ((backing.DEF_hg_feature_lock_entryVec_3___d19) != DEF_hg_feature_lock_entryVec_3___d19) - { - vcd_write_val(sim_hdl, num, DEF_hg_feature_lock_entryVec_3___d19, 11u); - backing.DEF_hg_feature_lock_entryVec_3___d19 = DEF_hg_feature_lock_entryVec_3___d19; - } - ++num; - if ((backing.DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284) != DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284) - { - vcd_write_val(sim_hdl, num, DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284, 10u); - backing.DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284 = DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284; - } - ++num; - if ((backing.DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283) != DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283) - { - vcd_write_val(sim_hdl, num, DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283, 48u); - backing.DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283 = DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283; - } - ++num; - if ((backing.DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169) != DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169) - { - vcd_write_val(sim_hdl, num, DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169, 10u); - backing.DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169 = DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169; - } - ++num; - if ((backing.DEF_hg_fifo_Start_TO_Stage__1_first____d168) != DEF_hg_fifo_Start_TO_Stage__1_first____d168) - { - vcd_write_val(sim_hdl, num, DEF_hg_fifo_Start_TO_Stage__1_first____d168, 45u); - backing.DEF_hg_fifo_Start_TO_Stage__1_first____d168 = DEF_hg_fifo_Start_TO_Stage__1_first____d168; - } - ++num; - if ((backing.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65) != DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65) - { - vcd_write_val(sim_hdl, num, DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65, 1u); - backing.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 = DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65; - } - ++num; - if ((backing.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64) != DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64) - { - vcd_write_val(sim_hdl, num, DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64, 10u); - backing.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64 = DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64; - } - ++num; - if ((backing.DEF_hg_fifo__input__TO_Start_first____d63) != DEF_hg_fifo__input__TO_Start_first____d63) - { - vcd_write_val(sim_hdl, num, DEF_hg_fifo__input__TO_Start_first____d63, 13u); - backing.DEF_hg_fifo__input__TO_Start_first____d63 = DEF_hg_fifo__input__TO_Start_first____d63; - } - ++num; - if ((backing.DEF_hg_fifo__input__TO_Start_i_notFull____d66) != DEF_hg_fifo__input__TO_Start_i_notFull____d66) - { - vcd_write_val(sim_hdl, num, DEF_hg_fifo__input__TO_Start_i_notFull____d66, 1u); - backing.DEF_hg_fifo__input__TO_Start_i_notFull____d66 = DEF_hg_fifo__input__TO_Start_i_notFull____d66; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179) != DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179, 1u); - backing.DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179 = DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294) != DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294, 1u); - backing.DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294 = DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_0_4_BIT_10___d45) != DEF_hg_h_lock_entryVec_0_4_BIT_10___d45) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_0_4_BIT_10___d45, 1u); - backing.DEF_hg_h_lock_entryVec_0_4_BIT_10___d45 = DEF_hg_h_lock_entryVec_0_4_BIT_10___d45; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_0___d44) != DEF_hg_h_lock_entryVec_0___d44) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_0___d44, 11u); - backing.DEF_hg_h_lock_entryVec_0___d44 = DEF_hg_h_lock_entryVec_0___d44; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176) != DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176, 1u); - backing.DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176 = DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291) != DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291, 1u); - backing.DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291 = DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177) != DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177, 1u); - backing.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177 = DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206) != DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206, 1u); - backing.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206 = DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304) != DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304, 1u); - backing.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304 = DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_1_9_BIT_10___d50) != DEF_hg_h_lock_entryVec_1_9_BIT_10___d50) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_1_9_BIT_10___d50, 1u); - backing.DEF_hg_h_lock_entryVec_1_9_BIT_10___d50 = DEF_hg_h_lock_entryVec_1_9_BIT_10___d50; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_1___d49) != DEF_hg_h_lock_entryVec_1___d49) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_1___d49, 11u); - backing.DEF_hg_h_lock_entryVec_1___d49 = DEF_hg_h_lock_entryVec_1___d49; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173) != DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173, 1u); - backing.DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173 = DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288) != DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288, 1u); - backing.DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288 = DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174) != DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174, 1u); - backing.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174 = DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207) != DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207, 1u); - backing.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207 = DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302) != DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302, 1u); - backing.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302 = DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_2_4_BIT_10___d55) != DEF_hg_h_lock_entryVec_2_4_BIT_10___d55) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_2_4_BIT_10___d55, 1u); - backing.DEF_hg_h_lock_entryVec_2_4_BIT_10___d55 = DEF_hg_h_lock_entryVec_2_4_BIT_10___d55; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_2___d54) != DEF_hg_h_lock_entryVec_2___d54) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_2___d54, 11u); - backing.DEF_hg_h_lock_entryVec_2___d54 = DEF_hg_h_lock_entryVec_2___d54; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170) != DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170, 1u); - backing.DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170 = DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285) != DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285, 1u); - backing.DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285 = DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171) != DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171, 1u); - backing.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171 = DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183) != DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183, 1u); - backing.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183 = DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300) != DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300, 1u); - backing.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300 = DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_3_9_BIT_10___d60) != DEF_hg_h_lock_entryVec_3_9_BIT_10___d60) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_3_9_BIT_10___d60, 1u); - backing.DEF_hg_h_lock_entryVec_3_9_BIT_10___d60 = DEF_hg_h_lock_entryVec_3_9_BIT_10___d60; - } - ++num; - if ((backing.DEF_hg_h_lock_entryVec_3___d59) != DEF_hg_h_lock_entryVec_3___d59) - { - vcd_write_val(sim_hdl, num, DEF_hg_h_lock_entryVec_3___d59, 11u); - backing.DEF_hg_h_lock_entryVec_3___d59 = DEF_hg_h_lock_entryVec_3___d59; - } - ++num; - if ((backing.DEF_hg_outputQueue_first____d352) != DEF_hg_outputQueue_first____d352) - { - vcd_write_val(sim_hdl, num, DEF_hg_outputQueue_first____d352, 4u); - backing.DEF_hg_outputQueue_first____d352 = DEF_hg_outputQueue_first____d352; - } - ++num; - if ((backing.DEF_hg_outputQueue_i_notEmpty____d351) != DEF_hg_outputQueue_i_notEmpty____d351) - { - vcd_write_val(sim_hdl, num, DEF_hg_outputQueue_i_notEmpty____d351, 1u); - backing.DEF_hg_outputQueue_i_notEmpty____d351 = DEF_hg_outputQueue_i_notEmpty____d351; - } - ++num; - if ((backing.DEF_hg_weight_lock_entryVec_0_4_BIT_10___d25) != DEF_hg_weight_lock_entryVec_0_4_BIT_10___d25) - { - vcd_write_val(sim_hdl, num, DEF_hg_weight_lock_entryVec_0_4_BIT_10___d25, 1u); - backing.DEF_hg_weight_lock_entryVec_0_4_BIT_10___d25 = DEF_hg_weight_lock_entryVec_0_4_BIT_10___d25; - } - ++num; - if ((backing.DEF_hg_weight_lock_entryVec_0___d24) != DEF_hg_weight_lock_entryVec_0___d24) - { - vcd_write_val(sim_hdl, num, DEF_hg_weight_lock_entryVec_0___d24, 11u); - backing.DEF_hg_weight_lock_entryVec_0___d24 = DEF_hg_weight_lock_entryVec_0___d24; - } - ++num; - if ((backing.DEF_hg_weight_lock_entryVec_1_9_BIT_10___d30) != DEF_hg_weight_lock_entryVec_1_9_BIT_10___d30) - { - vcd_write_val(sim_hdl, num, DEF_hg_weight_lock_entryVec_1_9_BIT_10___d30, 1u); - backing.DEF_hg_weight_lock_entryVec_1_9_BIT_10___d30 = DEF_hg_weight_lock_entryVec_1_9_BIT_10___d30; - } - ++num; - if ((backing.DEF_hg_weight_lock_entryVec_1___d29) != DEF_hg_weight_lock_entryVec_1___d29) - { - vcd_write_val(sim_hdl, num, DEF_hg_weight_lock_entryVec_1___d29, 11u); - backing.DEF_hg_weight_lock_entryVec_1___d29 = DEF_hg_weight_lock_entryVec_1___d29; - } - ++num; - if ((backing.DEF_hg_weight_lock_entryVec_2_4_BIT_10___d35) != DEF_hg_weight_lock_entryVec_2_4_BIT_10___d35) - { - vcd_write_val(sim_hdl, num, DEF_hg_weight_lock_entryVec_2_4_BIT_10___d35, 1u); - backing.DEF_hg_weight_lock_entryVec_2_4_BIT_10___d35 = DEF_hg_weight_lock_entryVec_2_4_BIT_10___d35; - } - ++num; - if ((backing.DEF_hg_weight_lock_entryVec_2___d34) != DEF_hg_weight_lock_entryVec_2___d34) - { - vcd_write_val(sim_hdl, num, DEF_hg_weight_lock_entryVec_2___d34, 11u); - backing.DEF_hg_weight_lock_entryVec_2___d34 = DEF_hg_weight_lock_entryVec_2___d34; - } - ++num; - if ((backing.DEF_hg_weight_lock_entryVec_3_9_BIT_10___d40) != DEF_hg_weight_lock_entryVec_3_9_BIT_10___d40) - { - vcd_write_val(sim_hdl, num, DEF_hg_weight_lock_entryVec_3_9_BIT_10___d40, 1u); - backing.DEF_hg_weight_lock_entryVec_3_9_BIT_10___d40 = DEF_hg_weight_lock_entryVec_3_9_BIT_10___d40; - } - ++num; - if ((backing.DEF_hg_weight_lock_entryVec_3___d39) != DEF_hg_weight_lock_entryVec_3___d39) - { - vcd_write_val(sim_hdl, num, DEF_hg_weight_lock_entryVec_3___d39, 11u); - backing.DEF_hg_weight_lock_entryVec_3___d39 = DEF_hg_weight_lock_entryVec_3___d39; - } - ++num; - if ((backing.DEF_x__h10519) != DEF_x__h10519) - { - vcd_write_val(sim_hdl, num, DEF_x__h10519, 2u); - backing.DEF_x__h10519 = DEF_x__h10519; - } - ++num; - if ((backing.DEF_x__h8976) != DEF_x__h8976) - { - vcd_write_val(sim_hdl, num, DEF_x__h8976, 2u); - backing.DEF_x__h8976 = DEF_x__h8976; - } - ++num; - if ((backing.DEF_x__h9842) != DEF_x__h9842) - { - vcd_write_val(sim_hdl, num, DEF_x__h9842, 2u); - backing.DEF_x__h9842 = DEF_x__h9842; - } - ++num; - if ((backing.PORT_EN__inthg_req) != PORT_EN__inthg_req) - { - vcd_write_val(sim_hdl, num, PORT_EN__inthg_req, 1u); - backing.PORT_EN__inthg_req = PORT_EN__inthg_req; - } - ++num; - } - else - { - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty___d2, 1u); - backing.DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty___d2 = DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty___d2; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty___d8, 1u); - backing.DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty___d8 = DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty___d8; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2___d13, 1u); - backing.DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2___d13 = DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2___d13; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7___d18, 1u); - backing.DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7___d18 = DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7___d18; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74, 1u); - backing.DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74 = DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192 = DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296 = DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190 = DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193 = DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297 = DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187 = DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194 = DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298 = DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184 = DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226 = DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209, 1u); - backing.DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209 = DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2___d43, 1u); - backing.DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2___d43 = DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2___d43; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7___d48, 1u); - backing.DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7___d48 = DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7___d48; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2___d53, 1u); - backing.DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2___d53 = DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2___d53; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7___d58, 1u); - backing.DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7___d58 = DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7___d58; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2___d23, 1u); - backing.DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2___d23 = DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2___d23; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7___d28, 1u); - backing.DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7___d28 = DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7___d28; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2___d33, 1u); - backing.DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2___d33 = DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2___d33; - vcd_write_val(sim_hdl, num++, DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7___d38, 1u); - backing.DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7___d38 = DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7___d38; - vcd_write_val(sim_hdl, num++, PORT_RST_N, 1u); - backing.PORT_RST_N = PORT_RST_N; - vcd_write_val(sim_hdl, num++, DEF_WILL_FIRE__inthg_req, 1u); - backing.DEF_WILL_FIRE__inthg_req = DEF_WILL_FIRE__inthg_req; - vcd_write_val(sim_hdl, num++, DEF__0_CONCAT_DONTCARE___d6, 11u); - backing.DEF__0_CONCAT_DONTCARE___d6 = DEF__0_CONCAT_DONTCARE___d6; - vcd_write_val(sim_hdl, num++, DEF_b__h8408, 10u); - backing.DEF_b__h8408 = DEF_b__h8408; - vcd_write_val(sim_hdl, num++, DEF_b__h8449, 10u); - backing.DEF_b__h8449 = DEF_b__h8449; - vcd_write_val(sim_hdl, num++, DEF_b__h8480, 10u); - backing.DEF_b__h8480 = DEF_b__h8480; - vcd_write_val(sim_hdl, num++, DEF_b__h8511, 10u); - backing.DEF_b__h8511 = DEF_b__h8511; - vcd_write_val(sim_hdl, num++, DEF_hg_busyReg__h7113, 1u); - backing.DEF_hg_busyReg__h7113 = DEF_hg_busyReg__h7113; - vcd_write_val(sim_hdl, num++, DEF_hg_feature_lock_entryVec_0_BIT_10___d4, 1u); - backing.DEF_hg_feature_lock_entryVec_0_BIT_10___d4 = DEF_hg_feature_lock_entryVec_0_BIT_10___d4; - vcd_write_val(sim_hdl, num++, DEF_hg_feature_lock_entryVec_0___d3, 11u); - backing.DEF_hg_feature_lock_entryVec_0___d3 = DEF_hg_feature_lock_entryVec_0___d3; - vcd_write_val(sim_hdl, num++, DEF_hg_feature_lock_entryVec_1_BIT_10___d10, 1u); - backing.DEF_hg_feature_lock_entryVec_1_BIT_10___d10 = DEF_hg_feature_lock_entryVec_1_BIT_10___d10; - vcd_write_val(sim_hdl, num++, DEF_hg_feature_lock_entryVec_1___d9, 11u); - backing.DEF_hg_feature_lock_entryVec_1___d9 = DEF_hg_feature_lock_entryVec_1___d9; - vcd_write_val(sim_hdl, num++, DEF_hg_feature_lock_entryVec_2_4_BIT_10___d15, 1u); - backing.DEF_hg_feature_lock_entryVec_2_4_BIT_10___d15 = DEF_hg_feature_lock_entryVec_2_4_BIT_10___d15; - vcd_write_val(sim_hdl, num++, DEF_hg_feature_lock_entryVec_2___d14, 11u); - backing.DEF_hg_feature_lock_entryVec_2___d14 = DEF_hg_feature_lock_entryVec_2___d14; - vcd_write_val(sim_hdl, num++, DEF_hg_feature_lock_entryVec_3_9_BIT_10___d20, 1u); - backing.DEF_hg_feature_lock_entryVec_3_9_BIT_10___d20 = DEF_hg_feature_lock_entryVec_3_9_BIT_10___d20; - vcd_write_val(sim_hdl, num++, DEF_hg_feature_lock_entryVec_3___d19, 11u); - backing.DEF_hg_feature_lock_entryVec_3___d19 = DEF_hg_feature_lock_entryVec_3___d19; - vcd_write_val(sim_hdl, num++, DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284, 10u); - backing.DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284 = DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284; - vcd_write_val(sim_hdl, num++, DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283, 48u); - backing.DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283 = DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283; - vcd_write_val(sim_hdl, num++, DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169, 10u); - backing.DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169 = DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169; - vcd_write_val(sim_hdl, num++, DEF_hg_fifo_Start_TO_Stage__1_first____d168, 45u); - backing.DEF_hg_fifo_Start_TO_Stage__1_first____d168 = DEF_hg_fifo_Start_TO_Stage__1_first____d168; - vcd_write_val(sim_hdl, num++, DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65, 1u); - backing.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 = DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65; - vcd_write_val(sim_hdl, num++, DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64, 10u); - backing.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64 = DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64; - vcd_write_val(sim_hdl, num++, DEF_hg_fifo__input__TO_Start_first____d63, 13u); - backing.DEF_hg_fifo__input__TO_Start_first____d63 = DEF_hg_fifo__input__TO_Start_first____d63; - vcd_write_val(sim_hdl, num++, DEF_hg_fifo__input__TO_Start_i_notFull____d66, 1u); - backing.DEF_hg_fifo__input__TO_Start_i_notFull____d66 = DEF_hg_fifo__input__TO_Start_i_notFull____d66; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179, 1u); - backing.DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179 = DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294, 1u); - backing.DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294 = DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_0_4_BIT_10___d45, 1u); - backing.DEF_hg_h_lock_entryVec_0_4_BIT_10___d45 = DEF_hg_h_lock_entryVec_0_4_BIT_10___d45; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_0___d44, 11u); - backing.DEF_hg_h_lock_entryVec_0___d44 = DEF_hg_h_lock_entryVec_0___d44; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176, 1u); - backing.DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176 = DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291, 1u); - backing.DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291 = DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177, 1u); - backing.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177 = DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206, 1u); - backing.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206 = DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304, 1u); - backing.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304 = DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_1_9_BIT_10___d50, 1u); - backing.DEF_hg_h_lock_entryVec_1_9_BIT_10___d50 = DEF_hg_h_lock_entryVec_1_9_BIT_10___d50; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_1___d49, 11u); - backing.DEF_hg_h_lock_entryVec_1___d49 = DEF_hg_h_lock_entryVec_1___d49; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173, 1u); - backing.DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173 = DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288, 1u); - backing.DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288 = DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174, 1u); - backing.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174 = DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207, 1u); - backing.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207 = DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302, 1u); - backing.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302 = DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_2_4_BIT_10___d55, 1u); - backing.DEF_hg_h_lock_entryVec_2_4_BIT_10___d55 = DEF_hg_h_lock_entryVec_2_4_BIT_10___d55; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_2___d54, 11u); - backing.DEF_hg_h_lock_entryVec_2___d54 = DEF_hg_h_lock_entryVec_2___d54; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170, 1u); - backing.DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170 = DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285, 1u); - backing.DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285 = DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171, 1u); - backing.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171 = DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183, 1u); - backing.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183 = DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300, 1u); - backing.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300 = DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_3_9_BIT_10___d60, 1u); - backing.DEF_hg_h_lock_entryVec_3_9_BIT_10___d60 = DEF_hg_h_lock_entryVec_3_9_BIT_10___d60; - vcd_write_val(sim_hdl, num++, DEF_hg_h_lock_entryVec_3___d59, 11u); - backing.DEF_hg_h_lock_entryVec_3___d59 = DEF_hg_h_lock_entryVec_3___d59; - vcd_write_val(sim_hdl, num++, DEF_hg_outputQueue_first____d352, 4u); - backing.DEF_hg_outputQueue_first____d352 = DEF_hg_outputQueue_first____d352; - vcd_write_val(sim_hdl, num++, DEF_hg_outputQueue_i_notEmpty____d351, 1u); - backing.DEF_hg_outputQueue_i_notEmpty____d351 = DEF_hg_outputQueue_i_notEmpty____d351; - vcd_write_val(sim_hdl, num++, DEF_hg_weight_lock_entryVec_0_4_BIT_10___d25, 1u); - backing.DEF_hg_weight_lock_entryVec_0_4_BIT_10___d25 = DEF_hg_weight_lock_entryVec_0_4_BIT_10___d25; - vcd_write_val(sim_hdl, num++, DEF_hg_weight_lock_entryVec_0___d24, 11u); - backing.DEF_hg_weight_lock_entryVec_0___d24 = DEF_hg_weight_lock_entryVec_0___d24; - vcd_write_val(sim_hdl, num++, DEF_hg_weight_lock_entryVec_1_9_BIT_10___d30, 1u); - backing.DEF_hg_weight_lock_entryVec_1_9_BIT_10___d30 = DEF_hg_weight_lock_entryVec_1_9_BIT_10___d30; - vcd_write_val(sim_hdl, num++, DEF_hg_weight_lock_entryVec_1___d29, 11u); - backing.DEF_hg_weight_lock_entryVec_1___d29 = DEF_hg_weight_lock_entryVec_1___d29; - vcd_write_val(sim_hdl, num++, DEF_hg_weight_lock_entryVec_2_4_BIT_10___d35, 1u); - backing.DEF_hg_weight_lock_entryVec_2_4_BIT_10___d35 = DEF_hg_weight_lock_entryVec_2_4_BIT_10___d35; - vcd_write_val(sim_hdl, num++, DEF_hg_weight_lock_entryVec_2___d34, 11u); - backing.DEF_hg_weight_lock_entryVec_2___d34 = DEF_hg_weight_lock_entryVec_2___d34; - vcd_write_val(sim_hdl, num++, DEF_hg_weight_lock_entryVec_3_9_BIT_10___d40, 1u); - backing.DEF_hg_weight_lock_entryVec_3_9_BIT_10___d40 = DEF_hg_weight_lock_entryVec_3_9_BIT_10___d40; - vcd_write_val(sim_hdl, num++, DEF_hg_weight_lock_entryVec_3___d39, 11u); - backing.DEF_hg_weight_lock_entryVec_3___d39 = DEF_hg_weight_lock_entryVec_3___d39; - vcd_write_val(sim_hdl, num++, DEF_x__h10519, 2u); - backing.DEF_x__h10519 = DEF_x__h10519; - vcd_write_val(sim_hdl, num++, DEF_x__h8976, 2u); - backing.DEF_x__h8976 = DEF_x__h8976; - vcd_write_val(sim_hdl, num++, DEF_x__h9842, 2u); - backing.DEF_x__h9842 = DEF_x__h9842; - vcd_write_val(sim_hdl, num++, PORT_EN__inthg_req, 1u); - backing.PORT_EN__inthg_req = PORT_EN__inthg_req; - } -} - -void MOD_mkCircuit::vcd_prims(tVCDDumpType dt, MOD_mkCircuit &backing) -{ - INST_f_rf.dump_VCD(dt, backing.INST_f_rf); - INST_h_rf.dump_VCD(dt, backing.INST_h_rf); - INST_hg.dump_VCD(dt, backing.INST_hg); - INST_hg_busyReg.dump_VCD(dt, backing.INST_hg_busyReg); - INST_hg_feature_lock_entryVec_0.dump_VCD(dt, backing.INST_hg_feature_lock_entryVec_0); - INST_hg_feature_lock_entryVec_1.dump_VCD(dt, backing.INST_hg_feature_lock_entryVec_1); - INST_hg_feature_lock_entryVec_2.dump_VCD(dt, backing.INST_hg_feature_lock_entryVec_2); - INST_hg_feature_lock_entryVec_3.dump_VCD(dt, backing.INST_hg_feature_lock_entryVec_3); - INST_hg_feature_lock_lockVec_0_cnt.dump_VCD(dt, backing.INST_hg_feature_lock_lockVec_0_cnt); - INST_hg_feature_lock_lockVec_0_held.dump_VCD(dt, backing.INST_hg_feature_lock_lockVec_0_held); - INST_hg_feature_lock_lockVec_0_nextId.dump_VCD(dt, backing.INST_hg_feature_lock_lockVec_0_nextId); - INST_hg_feature_lock_lockVec_1_cnt.dump_VCD(dt, backing.INST_hg_feature_lock_lockVec_1_cnt); - INST_hg_feature_lock_lockVec_1_held.dump_VCD(dt, backing.INST_hg_feature_lock_lockVec_1_held); - INST_hg_feature_lock_lockVec_1_nextId.dump_VCD(dt, backing.INST_hg_feature_lock_lockVec_1_nextId); - INST_hg_feature_lock_lockVec_2_cnt.dump_VCD(dt, backing.INST_hg_feature_lock_lockVec_2_cnt); - INST_hg_feature_lock_lockVec_2_held.dump_VCD(dt, backing.INST_hg_feature_lock_lockVec_2_held); - INST_hg_feature_lock_lockVec_2_nextId.dump_VCD(dt, backing.INST_hg_feature_lock_lockVec_2_nextId); - INST_hg_feature_lock_lockVec_3_cnt.dump_VCD(dt, backing.INST_hg_feature_lock_lockVec_3_cnt); - INST_hg_feature_lock_lockVec_3_held.dump_VCD(dt, backing.INST_hg_feature_lock_lockVec_3_held); - INST_hg_feature_lock_lockVec_3_nextId.dump_VCD(dt, backing.INST_hg_feature_lock_lockVec_3_nextId); - INST_hg_feature_lock_region.dump_VCD(dt, backing.INST_hg_feature_lock_region); - INST_hg_fifo_Stage__1_TO_Stage__2.dump_VCD(dt, backing.INST_hg_fifo_Stage__1_TO_Stage__2); - INST_hg_fifo_Stage__2_TO_Stage__3.dump_VCD(dt, backing.INST_hg_fifo_Stage__2_TO_Stage__3); - INST_hg_fifo_Start_TO_Stage__1.dump_VCD(dt, backing.INST_hg_fifo_Start_TO_Stage__1); - INST_hg_fifo__input__TO_Start.dump_VCD(dt, backing.INST_hg_fifo__input__TO_Start); - INST_hg_h_lock_entryVec_0.dump_VCD(dt, backing.INST_hg_h_lock_entryVec_0); - INST_hg_h_lock_entryVec_1.dump_VCD(dt, backing.INST_hg_h_lock_entryVec_1); - INST_hg_h_lock_entryVec_2.dump_VCD(dt, backing.INST_hg_h_lock_entryVec_2); - INST_hg_h_lock_entryVec_3.dump_VCD(dt, backing.INST_hg_h_lock_entryVec_3); - INST_hg_h_lock_lockVec_0_cnt.dump_VCD(dt, backing.INST_hg_h_lock_lockVec_0_cnt); - INST_hg_h_lock_lockVec_0_held.dump_VCD(dt, backing.INST_hg_h_lock_lockVec_0_held); - INST_hg_h_lock_lockVec_0_nextId.dump_VCD(dt, backing.INST_hg_h_lock_lockVec_0_nextId); - INST_hg_h_lock_lockVec_1_cnt.dump_VCD(dt, backing.INST_hg_h_lock_lockVec_1_cnt); - INST_hg_h_lock_lockVec_1_held.dump_VCD(dt, backing.INST_hg_h_lock_lockVec_1_held); - INST_hg_h_lock_lockVec_1_nextId.dump_VCD(dt, backing.INST_hg_h_lock_lockVec_1_nextId); - INST_hg_h_lock_lockVec_2_cnt.dump_VCD(dt, backing.INST_hg_h_lock_lockVec_2_cnt); - INST_hg_h_lock_lockVec_2_held.dump_VCD(dt, backing.INST_hg_h_lock_lockVec_2_held); - INST_hg_h_lock_lockVec_2_nextId.dump_VCD(dt, backing.INST_hg_h_lock_lockVec_2_nextId); - INST_hg_h_lock_lockVec_3_cnt.dump_VCD(dt, backing.INST_hg_h_lock_lockVec_3_cnt); - INST_hg_h_lock_lockVec_3_held.dump_VCD(dt, backing.INST_hg_h_lock_lockVec_3_held); - INST_hg_h_lock_lockVec_3_nextId.dump_VCD(dt, backing.INST_hg_h_lock_lockVec_3_nextId); - INST_hg_h_lock_region.dump_VCD(dt, backing.INST_hg_h_lock_region); - INST_hg_outputQueue.dump_VCD(dt, backing.INST_hg_outputQueue); - INST_hg_weight_lock_entryVec_0.dump_VCD(dt, backing.INST_hg_weight_lock_entryVec_0); - INST_hg_weight_lock_entryVec_1.dump_VCD(dt, backing.INST_hg_weight_lock_entryVec_1); - INST_hg_weight_lock_entryVec_2.dump_VCD(dt, backing.INST_hg_weight_lock_entryVec_2); - INST_hg_weight_lock_entryVec_3.dump_VCD(dt, backing.INST_hg_weight_lock_entryVec_3); - INST_hg_weight_lock_lockVec_0_cnt.dump_VCD(dt, backing.INST_hg_weight_lock_lockVec_0_cnt); - INST_hg_weight_lock_lockVec_0_held.dump_VCD(dt, backing.INST_hg_weight_lock_lockVec_0_held); - INST_hg_weight_lock_lockVec_0_nextId.dump_VCD(dt, backing.INST_hg_weight_lock_lockVec_0_nextId); - INST_hg_weight_lock_lockVec_1_cnt.dump_VCD(dt, backing.INST_hg_weight_lock_lockVec_1_cnt); - INST_hg_weight_lock_lockVec_1_held.dump_VCD(dt, backing.INST_hg_weight_lock_lockVec_1_held); - INST_hg_weight_lock_lockVec_1_nextId.dump_VCD(dt, backing.INST_hg_weight_lock_lockVec_1_nextId); - INST_hg_weight_lock_lockVec_2_cnt.dump_VCD(dt, backing.INST_hg_weight_lock_lockVec_2_cnt); - INST_hg_weight_lock_lockVec_2_held.dump_VCD(dt, backing.INST_hg_weight_lock_lockVec_2_held); - INST_hg_weight_lock_lockVec_2_nextId.dump_VCD(dt, backing.INST_hg_weight_lock_lockVec_2_nextId); - INST_hg_weight_lock_lockVec_3_cnt.dump_VCD(dt, backing.INST_hg_weight_lock_lockVec_3_cnt); - INST_hg_weight_lock_lockVec_3_held.dump_VCD(dt, backing.INST_hg_weight_lock_lockVec_3_held); - INST_hg_weight_lock_lockVec_3_nextId.dump_VCD(dt, backing.INST_hg_weight_lock_lockVec_3_nextId); - INST_hg_weight_lock_region.dump_VCD(dt, backing.INST_hg_weight_lock_region); - INST_w_rf.dump_VCD(dt, backing.INST_w_rf); -} diff --git a/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkCircuit.h b/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkCircuit.h deleted file mode 100644 index 3cd53273..00000000 --- a/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkCircuit.h +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Generated by Bluespec Compiler - * - */ - -/* Generation options: */ -#ifndef __mkCircuit_h__ -#define __mkCircuit_h__ - -#include "bluesim_types.h" -#include "bs_module.h" -#include "bluesim_primitives.h" -#include "bs_vcd.h" - - -/* Class declaration for the mkCircuit module */ -class MOD_mkCircuit : public Module { - - /* Clock handles */ - private: - tClock __clk_handle_0; - - /* Clock gate handles */ - public: - tUInt8 *clk_gate[0]; - - /* Instantiation parameters */ - public: - - /* Module state */ - public: - MOD_RegFile INST_f_rf; - MOD_RegFile INST_h_rf; - MOD_Reg INST_hg; - MOD_Reg INST_hg_busyReg; - MOD_Reg INST_hg_feature_lock_entryVec_0; - MOD_Reg INST_hg_feature_lock_entryVec_1; - MOD_Reg INST_hg_feature_lock_entryVec_2; - MOD_Reg INST_hg_feature_lock_entryVec_3; - MOD_Reg INST_hg_feature_lock_lockVec_0_cnt; - MOD_Fifo INST_hg_feature_lock_lockVec_0_held; - MOD_Reg INST_hg_feature_lock_lockVec_0_nextId; - MOD_Reg INST_hg_feature_lock_lockVec_1_cnt; - MOD_Fifo INST_hg_feature_lock_lockVec_1_held; - MOD_Reg INST_hg_feature_lock_lockVec_1_nextId; - MOD_Reg INST_hg_feature_lock_lockVec_2_cnt; - MOD_Fifo INST_hg_feature_lock_lockVec_2_held; - MOD_Reg INST_hg_feature_lock_lockVec_2_nextId; - MOD_Reg INST_hg_feature_lock_lockVec_3_cnt; - MOD_Fifo INST_hg_feature_lock_lockVec_3_held; - MOD_Reg INST_hg_feature_lock_lockVec_3_nextId; - MOD_Reg INST_hg_feature_lock_region; - MOD_Fifo INST_hg_fifo_Stage__1_TO_Stage__2; - MOD_Fifo INST_hg_fifo_Stage__2_TO_Stage__3; - MOD_Fifo INST_hg_fifo_Start_TO_Stage__1; - MOD_Fifo INST_hg_fifo__input__TO_Start; - MOD_Reg INST_hg_h_lock_entryVec_0; - MOD_Reg INST_hg_h_lock_entryVec_1; - MOD_Reg INST_hg_h_lock_entryVec_2; - MOD_Reg INST_hg_h_lock_entryVec_3; - MOD_Reg INST_hg_h_lock_lockVec_0_cnt; - MOD_Fifo INST_hg_h_lock_lockVec_0_held; - MOD_Reg INST_hg_h_lock_lockVec_0_nextId; - MOD_Reg INST_hg_h_lock_lockVec_1_cnt; - MOD_Fifo INST_hg_h_lock_lockVec_1_held; - MOD_Reg INST_hg_h_lock_lockVec_1_nextId; - MOD_Reg INST_hg_h_lock_lockVec_2_cnt; - MOD_Fifo INST_hg_h_lock_lockVec_2_held; - MOD_Reg INST_hg_h_lock_lockVec_2_nextId; - MOD_Reg INST_hg_h_lock_lockVec_3_cnt; - MOD_Fifo INST_hg_h_lock_lockVec_3_held; - MOD_Reg INST_hg_h_lock_lockVec_3_nextId; - MOD_Reg INST_hg_h_lock_region; - MOD_Fifo INST_hg_outputQueue; - MOD_Reg INST_hg_weight_lock_entryVec_0; - MOD_Reg INST_hg_weight_lock_entryVec_1; - MOD_Reg INST_hg_weight_lock_entryVec_2; - MOD_Reg INST_hg_weight_lock_entryVec_3; - MOD_Reg INST_hg_weight_lock_lockVec_0_cnt; - MOD_Fifo INST_hg_weight_lock_lockVec_0_held; - MOD_Reg INST_hg_weight_lock_lockVec_0_nextId; - MOD_Reg INST_hg_weight_lock_lockVec_1_cnt; - MOD_Fifo INST_hg_weight_lock_lockVec_1_held; - MOD_Reg INST_hg_weight_lock_lockVec_1_nextId; - MOD_Reg INST_hg_weight_lock_lockVec_2_cnt; - MOD_Fifo INST_hg_weight_lock_lockVec_2_held; - MOD_Reg INST_hg_weight_lock_lockVec_2_nextId; - MOD_Reg INST_hg_weight_lock_lockVec_3_cnt; - MOD_Fifo INST_hg_weight_lock_lockVec_3_held; - MOD_Reg INST_hg_weight_lock_lockVec_3_nextId; - MOD_Reg INST_hg_weight_lock_region; - MOD_RegFile INST_w_rf; - - /* Constructor */ - public: - MOD_mkCircuit(tSimStateHdl simHdl, char const *name, Module *parent); - - /* Symbol init methods */ - private: - void init_symbols_0(); - - /* Reset signal definitions */ - private: - tUInt8 PORT_RST_N; - - /* Port definitions */ - public: - tUInt8 PORT_EN__inthg_req; - - /* Publicly accessible definitions */ - public: - tUInt8 DEF_hg_outputQueue_i_notEmpty____d351; - tUInt8 DEF_WILL_FIRE__inthg_req; - tUInt8 DEF_hg_fifo__input__TO_Start_i_notFull____d66; - tUInt8 DEF_hg_h_lock_entryVec_3_9_BIT_10___d60; - tUInt8 DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285; - tUInt8 DEF_hg_h_lock_entryVec_2_4_BIT_10___d55; - tUInt8 DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288; - tUInt8 DEF_hg_h_lock_entryVec_1_9_BIT_10___d50; - tUInt8 DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291; - tUInt8 DEF_x__h8976; - tUInt8 DEF_hg_h_lock_entryVec_0_4_BIT_10___d45; - tUInt8 DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183; - tUInt8 DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192; - tUInt8 DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174; - tUInt8 DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177; - tUInt8 DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171; - tUInt8 DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209; - tUInt8 DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170; - tUInt8 DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184; - tUInt8 DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173; - tUInt8 DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176; - tUInt8 DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187; - tUInt8 DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190; - tUInt8 DEF_hg_weight_lock_entryVec_3_9_BIT_10___d40; - tUInt8 DEF_hg_weight_lock_entryVec_2_4_BIT_10___d35; - tUInt8 DEF_hg_weight_lock_entryVec_1_9_BIT_10___d30; - tUInt8 DEF_hg_feature_lock_entryVec_3_9_BIT_10___d20; - tUInt8 DEF_hg_feature_lock_entryVec_2_4_BIT_10___d15; - tUInt8 DEF_hg_feature_lock_entryVec_1_BIT_10___d10; - tUInt64 DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283; - tUInt64 DEF_hg_fifo_Start_TO_Stage__1_first____d168; - tUInt32 DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169; - tUInt32 DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64; - tUInt32 DEF_hg_fifo__input__TO_Start_first____d63; - tUInt32 DEF_hg_h_lock_entryVec_3___d59; - tUInt32 DEF_hg_h_lock_entryVec_2___d54; - tUInt32 DEF_hg_h_lock_entryVec_1___d49; - tUInt32 DEF_hg_h_lock_entryVec_0___d44; - tUInt32 DEF_hg_weight_lock_entryVec_3___d39; - tUInt32 DEF_hg_weight_lock_entryVec_2___d34; - tUInt32 DEF_hg_weight_lock_entryVec_1___d29; - tUInt32 DEF_hg_weight_lock_entryVec_0___d24; - tUInt32 DEF_hg_feature_lock_entryVec_3___d19; - tUInt32 DEF_hg_feature_lock_entryVec_2___d14; - tUInt32 DEF_hg_feature_lock_entryVec_1___d9; - tUInt32 DEF_hg_feature_lock_entryVec_0___d3; - tUInt8 DEF_hg_busyReg__h7113; - tUInt8 DEF_x__h10519; - tUInt8 DEF_x__h9842; - tUInt32 DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284; - tUInt32 DEF_b__h8511; - tUInt32 DEF_b__h8480; - tUInt32 DEF_b__h8449; - tUInt32 DEF_b__h8408; - tUInt8 DEF_hg_weight_lock_entryVec_0_4_BIT_10___d25; - tUInt8 DEF_hg_feature_lock_entryVec_0_BIT_10___d4; - tUInt8 DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2___d43; - tUInt8 DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7___d48; - tUInt8 DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2___d53; - tUInt8 DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7___d58; - tUInt8 DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2___d23; - tUInt8 DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7___d28; - tUInt8 DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2___d33; - tUInt8 DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7___d38; - tUInt8 DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty___d2; - tUInt8 DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty___d8; - tUInt8 DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2___d13; - tUInt8 DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7___d18; - tUInt8 DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226; - tUInt8 DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65; - tUInt8 DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294; - tUInt8 DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179; - tUInt8 DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300; - tUInt8 DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302; - tUInt8 DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304; - tUInt8 DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296; - tUInt8 DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74; - tUInt8 DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298; - tUInt8 DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297; - tUInt8 DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194; - tUInt8 DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207; - tUInt8 DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206; - tUInt8 DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193; - - /* Local definitions */ - private: - tUInt8 DEF_hg_outputQueue_first____d352; - tUInt32 DEF__0_CONCAT_DONTCARE___d6; - - /* Rules */ - public: - void RL_hg_feature_lock_freelock(); - void RL_hg_feature_lock_freelock_1(); - void RL_hg_feature_lock_freelock_2(); - void RL_hg_feature_lock_freelock_3(); - void RL_hg_weight_lock_freelock(); - void RL_hg_weight_lock_freelock_1(); - void RL_hg_weight_lock_freelock_2(); - void RL_hg_weight_lock_freelock_3(); - void RL_hg_h_lock_freelock(); - void RL_hg_h_lock_freelock_1(); - void RL_hg_h_lock_freelock_2(); - void RL_hg_h_lock_freelock_3(); - void RL_hg_s_Start_execute(); - void RL_hg_s_Stage__1_execute(); - void RL_hg_s_Stage__2_execute(); - void RL_hg_s_Stage__3_execute(); - - /* Methods */ - public: - tUInt8 METH__inthg_req(tUInt32 ARG__inthg_req_counter); - tUInt8 METH_RDY__inthg_req(); - void METH__inthg_resp(); - tUInt8 METH_RDY__inthg_resp(); - tUInt8 METH__inthg_checkHandle(tUInt8 ARG__inthg_checkHandle_handle); - tUInt8 METH_RDY__inthg_checkHandle(); - tUInt8 METH__inthg_peek(); - tUInt8 METH_RDY__inthg_peek(); - - /* Reset routines */ - public: - void reset_RST_N(tUInt8 ARG_rst_in); - - /* Static handles to reset routines */ - public: - - /* Pointers to reset fns in parent module for asserting output resets */ - private: - - /* Functions for the parent module to register its reset fns */ - public: - - /* Functions to set the elaborated clock id */ - public: - void set_clk_0(char const *s); - - /* State dumping routine */ - public: - void dump_state(unsigned int indent); - - /* VCD dumping routines */ - public: - unsigned int dump_VCD_defs(unsigned int levels); - void dump_VCD(tVCDDumpType dt, unsigned int levels, MOD_mkCircuit &backing); - void vcd_defs(tVCDDumpType dt, MOD_mkCircuit &backing); - void vcd_prims(tVCDDumpType dt, MOD_mkCircuit &backing); -}; - -#endif /* ifndef __mkCircuit_h__ */ diff --git a/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkCircuit.o b/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkCircuit.o deleted file mode 100644 index cbd5ee2a..00000000 Binary files a/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkCircuit.o and /dev/null differ diff --git a/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkTB.cxx b/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkTB.cxx deleted file mode 100644 index a46ff9c0..00000000 --- a/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkTB.cxx +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Generated by Bluespec Compiler - * - */ -#include "bluesim_primitives.h" -#include "mkTB.h" - - -/* Constructor */ -MOD_mkTB::MOD_mkTB(tSimStateHdl simHdl, char const *name, Module *parent) - : Module(simHdl, name, parent), - __clk_handle_0(BAD_CLOCK_HANDLE), - INST_m(simHdl, "m", this), - INST_reg_unused_0(simHdl, "reg_unused_0", this, 3u, (tUInt8)0u, (tUInt8)0u), - INST_started(simHdl, "started", this, 1u, (tUInt8)0u, (tUInt8)0u), - PORT_RST_N((tUInt8)1u) -{ - symbol_count = 5u; - symbols = new tSym[symbol_count]; - init_symbols_0(); -} - - -/* Symbol init fns */ - -void MOD_mkTB::init_symbols_0() -{ - init_symbol(&symbols[0u], "m", SYM_MODULE, &INST_m); - init_symbol(&symbols[1u], "RL_initTB", SYM_RULE); - init_symbol(&symbols[2u], "RL_stopTB", SYM_RULE); - init_symbol(&symbols[3u], "reg_unused_0", SYM_MODULE, &INST_reg_unused_0); - init_symbol(&symbols[4u], "started", SYM_MODULE, &INST_started); -} - - -/* Rule actions */ - -void MOD_mkTB::RL_initTB() -{ - tUInt8 DEF_m__inthg_req___d5; - tUInt8 DEF_AVMeth_m__inthg_req; - DEF_AVMeth_m__inthg_req = INST_m.METH__inthg_req(0u); - DEF_m__inthg_req___d5 = DEF_AVMeth_m__inthg_req; - INST_reg_unused_0.METH_write(DEF_m__inthg_req___d5); - INST_started.METH_write((tUInt8)1u); -} - -void MOD_mkTB::RL_stopTB() -{ - if (!(PORT_RST_N == (tUInt8)0u)) - dollar_finish(sim_hdl, "32", 1u); -} - - -/* Methods */ - - -/* Reset routines */ - -void MOD_mkTB::reset_RST_N(tUInt8 ARG_rst_in) -{ - PORT_RST_N = ARG_rst_in; - INST_started.reset_RST(ARG_rst_in); - INST_reg_unused_0.reset_RST(ARG_rst_in); - INST_m.reset_RST_N(ARG_rst_in); -} - - -/* Static handles to reset routines */ - - -/* Functions for the parent module to register its reset fns */ - - -/* Functions to set the elaborated clock id */ - -void MOD_mkTB::set_clk_0(char const *s) -{ - __clk_handle_0 = bk_get_or_define_clock(sim_hdl, s); -} - - -/* State dumping routine */ -void MOD_mkTB::dump_state(unsigned int indent) -{ - printf("%*s%s:\n", indent, "", inst_name); - INST_m.dump_state(indent + 2u); - INST_reg_unused_0.dump_state(indent + 2u); - INST_started.dump_state(indent + 2u); -} - - -/* VCD dumping routines */ - -unsigned int MOD_mkTB::dump_VCD_defs(unsigned int levels) -{ - vcd_write_scope_start(sim_hdl, inst_name); - vcd_num = vcd_reserve_ids(sim_hdl, 3u); - unsigned int num = vcd_num; - for (unsigned int clk = 0u; clk < bk_num_clocks(sim_hdl); ++clk) - vcd_add_clock_def(sim_hdl, this, bk_clock_name(sim_hdl, clk), bk_clock_vcd_num(sim_hdl, clk)); - vcd_write_def(sim_hdl, bk_clock_vcd_num(sim_hdl, __clk_handle_0), "CLK", 1u); - vcd_write_def(sim_hdl, num++, "RST_N", 1u); - num = INST_reg_unused_0.dump_VCD_defs(num); - num = INST_started.dump_VCD_defs(num); - if (levels != 1u) - { - unsigned int l = levels == 0u ? 0u : levels - 1u; - num = INST_m.dump_VCD_defs(l); - } - vcd_write_scope_end(sim_hdl); - return num; -} - -void MOD_mkTB::dump_VCD(tVCDDumpType dt, unsigned int levels, MOD_mkTB &backing) -{ - vcd_defs(dt, backing); - vcd_prims(dt, backing); - if (levels != 1u) - vcd_submodules(dt, levels - 1u, backing); -} - -void MOD_mkTB::vcd_defs(tVCDDumpType dt, MOD_mkTB &backing) -{ - unsigned int num = vcd_num; - if (dt == VCD_DUMP_XS) - { - vcd_write_x(sim_hdl, num++, 1u); - } - else - if (dt == VCD_DUMP_CHANGES) - { - if ((backing.PORT_RST_N) != PORT_RST_N) - { - vcd_write_val(sim_hdl, num, PORT_RST_N, 1u); - backing.PORT_RST_N = PORT_RST_N; - } - ++num; - } - else - { - vcd_write_val(sim_hdl, num++, PORT_RST_N, 1u); - backing.PORT_RST_N = PORT_RST_N; - } -} - -void MOD_mkTB::vcd_prims(tVCDDumpType dt, MOD_mkTB &backing) -{ - INST_reg_unused_0.dump_VCD(dt, backing.INST_reg_unused_0); - INST_started.dump_VCD(dt, backing.INST_started); -} - -void MOD_mkTB::vcd_submodules(tVCDDumpType dt, unsigned int levels, MOD_mkTB &backing) -{ - INST_m.dump_VCD(dt, levels, backing.INST_m); -} diff --git a/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkTB.h b/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkTB.h deleted file mode 100644 index 8857b671..00000000 --- a/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkTB.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Generated by Bluespec Compiler - * - */ - -/* Generation options: */ -#ifndef __mkTB_h__ -#define __mkTB_h__ - -#include "bluesim_types.h" -#include "bs_module.h" -#include "bluesim_primitives.h" -#include "bs_vcd.h" -#include "mkCircuit.h" - - -/* Class declaration for the mkTB module */ -class MOD_mkTB : public Module { - - /* Clock handles */ - private: - tClock __clk_handle_0; - - /* Clock gate handles */ - public: - tUInt8 *clk_gate[0]; - - /* Instantiation parameters */ - public: - - /* Module state */ - public: - MOD_mkCircuit INST_m; - MOD_Reg INST_reg_unused_0; - MOD_Reg INST_started; - - /* Constructor */ - public: - MOD_mkTB(tSimStateHdl simHdl, char const *name, Module *parent); - - /* Symbol init methods */ - private: - void init_symbols_0(); - - /* Reset signal definitions */ - private: - tUInt8 PORT_RST_N; - - /* Port definitions */ - public: - - /* Publicly accessible definitions */ - public: - - /* Local definitions */ - private: - - /* Rules */ - public: - void RL_initTB(); - void RL_stopTB(); - - /* Methods */ - public: - - /* Reset routines */ - public: - void reset_RST_N(tUInt8 ARG_rst_in); - - /* Static handles to reset routines */ - public: - - /* Pointers to reset fns in parent module for asserting output resets */ - private: - - /* Functions for the parent module to register its reset fns */ - public: - - /* Functions to set the elaborated clock id */ - public: - void set_clk_0(char const *s); - - /* State dumping routine */ - public: - void dump_state(unsigned int indent); - - /* VCD dumping routines */ - public: - unsigned int dump_VCD_defs(unsigned int levels); - void dump_VCD(tVCDDumpType dt, unsigned int levels, MOD_mkTB &backing); - void vcd_defs(tVCDDumpType dt, MOD_mkTB &backing); - void vcd_prims(tVCDDumpType dt, MOD_mkTB &backing); - void vcd_submodules(tVCDDumpType dt, unsigned int levels, MOD_mkTB &backing); -}; - -#endif /* ifndef __mkTB_h__ */ diff --git a/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkTB.o b/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkTB.o deleted file mode 100644 index aaed6a33..00000000 Binary files a/src/main/scala/pipedsl/testOutputs/Circuit_sim/mkTB.o and /dev/null differ diff --git a/src/main/scala/pipedsl/testOutputs/Circuit_sim/model_mkTB.cxx b/src/main/scala/pipedsl/testOutputs/Circuit_sim/model_mkTB.cxx deleted file mode 100644 index 194dea26..00000000 --- a/src/main/scala/pipedsl/testOutputs/Circuit_sim/model_mkTB.cxx +++ /dev/null @@ -1,565 +0,0 @@ -/* - * Generated by Bluespec Compiler - * - */ -#include "bluesim_primitives.h" -#include "model_mkTB.h" - -#include -#include -#include "bluesim_kernel_api.h" -#include "bs_vcd.h" -#include "bs_reset.h" - - -/* Constructor */ -MODEL_mkTB::MODEL_mkTB() -{ - mkTB_instance = NULL; -} - -/* Function for creating a new model */ -void * new_MODEL_mkTB() -{ - MODEL_mkTB *model = new MODEL_mkTB(); - return (void *)(model); -} - -/* Schedule functions */ - -static void schedule_posedge_CLK(tSimStateHdl simHdl, void *instance_ptr) - { - MOD_mkTB &INST_top = *((MOD_mkTB *)(instance_ptr)); - tUInt8 DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_1_BIT_10_0_4_OR_N_ETC___d100; - tUInt8 DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_1_9_BIT_10_0_35_OR_ETC___d141; - tUInt8 DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_0_BITS_9_TO_0_4_EQ_hg_ETC___d85; - tUInt8 DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_0_4_BITS_9_TO_0_25_EQ__ETC___d126; - tUInt8 DEF_INST_top_INST_m_DEF_x__h7932; - tUInt8 DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_weight_lock_lockVec_0_held_notE_ETC___d149; - tUInt8 DEF_INST_top_INST_m_DEF_x__h7468; - tUInt8 DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_feature_lock_lockVec_0_held_not_ETC___d108; - tUInt8 DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_h_lock_lockVec_0_held_notEmpty__ETC___d229; - tUInt32 DEF_INST_top_INST_m_DEF_b__h7212; - tUInt32 DEF_INST_top_INST_m_DEF_b__h7182; - tUInt32 DEF_INST_top_INST_m_DEF_b__h7243; - tUInt32 DEF_INST_top_INST_m_DEF_b__h7274; - tUInt32 DEF_INST_top_INST_m_DEF_b__h7646; - tUInt32 DEF_INST_top_INST_m_DEF_b__h7676; - tUInt32 DEF_INST_top_INST_m_DEF_b__h7707; - tUInt32 DEF_INST_top_INST_m_DEF_b__h7738; - tUInt8 DEF_INST_top_INST_m_DEF_CASE_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_ETC___d216; - tUInt8 DEF_INST_top_INST_m_DEF_CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d205; - tUInt8 DEF_INST_top_INST_m_DEF_CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d313; - tUInt8 DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_0_held_i_notFull____d201; - tUInt8 DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_1_held_i_notFull____d202; - tUInt8 DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_2_held_i_notFull____d203; - tUInt8 DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_3_held_i_notFull____d204; - tUInt8 DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_0_BIT_10___d97; - tUInt8 DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_1_BIT_10_0___d94; - tUInt8 DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_1_BITS_9_TO_0_1_EQ_hg_ETC___d82; - tUInt8 DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_2_4_BITS_9_TO_0_8_EQ__ETC___d79; - tUInt8 DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_2_4_BIT_10_5___d91; - tUInt8 DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_3_9_BIT_10_0_AND_hg_f_ETC___d77; - tUInt8 DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_1_BIT_10_0_AND_hg_fea_ETC___d83; - tUInt8 DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_2_4_BIT_10_5_AND_hg_f_ETC___d80; - tUInt8 DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_0_BIT_10_7_OR_NOT_ETC___d99; - tUInt8 DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_0_4_BIT_10_5___d138; - tUInt8 DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_1_9_BIT_10_0___d135; - tUInt8 DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_1_9_BITS_9_TO_0_22_EQ__ETC___d123; - tUInt8 DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_2_4_BITS_9_TO_0_19_EQ__ETC___d120; - tUInt8 DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_2_4_BIT_10_5___d132; - tUInt8 DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_3_9_BIT_10_0_AND_hg_we_ETC___d118; - tUInt8 DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_1_9_BIT_10_0_AND_hg_we_ETC___d124; - tUInt8 DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_2_4_BIT_10_5_AND_hg_we_ETC___d121; - tUInt8 DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_0_4_BIT_10_5_38_OR_ETC___d140; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_feature_lock_freelock; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_feature_lock_freelock; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_feature_lock_freelock_1; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_feature_lock_freelock_1; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_feature_lock_freelock_2; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_feature_lock_freelock_2; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_feature_lock_freelock_3; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_feature_lock_freelock_3; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_weight_lock_freelock; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_weight_lock_freelock; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_weight_lock_freelock_1; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_weight_lock_freelock_1; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_weight_lock_freelock_2; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_weight_lock_freelock_2; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_weight_lock_freelock_3; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_weight_lock_freelock_3; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_h_lock_freelock; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_h_lock_freelock; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_h_lock_freelock_1; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_h_lock_freelock_1; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_h_lock_freelock_2; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_h_lock_freelock_2; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_h_lock_freelock_3; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_h_lock_freelock_3; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_s_Start_execute; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Start_execute; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_s_Stage__1_execute; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__1_execute; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_s_Stage__2_execute; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__2_execute; - tUInt8 DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_s_Stage__3_execute; - tUInt8 DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__3_execute; - tUInt8 DEF_INST_top_DEF_started__h160; - tUInt8 DEF_INST_top_DEF_b__h231; - tUInt8 DEF_INST_top_DEF_CAN_FIRE_RL_initTB; - tUInt8 DEF_INST_top_DEF_WILL_FIRE_RL_initTB; - tUInt8 DEF_INST_top_DEF_CAN_FIRE_RL_stopTB; - tUInt8 DEF_INST_top_DEF_WILL_FIRE_RL_stopTB; - INST_top.INST_m.PORT_EN__inthg_req = (tUInt8)0u; - INST_top.INST_m.DEF_WILL_FIRE__inthg_req = (tUInt8)0u; - DEF_INST_top_DEF_started__h160 = INST_top.INST_started.METH_read(); - DEF_INST_top_DEF_CAN_FIRE_RL_initTB = INST_top.INST_m.METH_RDY__inthg_req() && !DEF_INST_top_DEF_started__h160; - DEF_INST_top_DEF_WILL_FIRE_RL_initTB = DEF_INST_top_DEF_CAN_FIRE_RL_initTB; - DEF_INST_top_DEF_b__h231 = INST_top.INST_reg_unused_0.METH_read(); - DEF_INST_top_DEF_CAN_FIRE_RL_stopTB = INST_top.INST_m.METH_RDY__inthg_checkHandle() && INST_top.INST_m.METH__inthg_checkHandle(DEF_INST_top_DEF_b__h231); - DEF_INST_top_DEF_WILL_FIRE_RL_stopTB = DEF_INST_top_DEF_CAN_FIRE_RL_stopTB; - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_feature_lock_freelock = (tUInt8)1u; - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_feature_lock_freelock = DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_feature_lock_freelock; - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_feature_lock_freelock_1 = (tUInt8)1u; - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_feature_lock_freelock_1 = DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_feature_lock_freelock_1; - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_feature_lock_freelock_2 = (tUInt8)1u; - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_feature_lock_freelock_2 = DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_feature_lock_freelock_2; - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_feature_lock_freelock_3 = (tUInt8)1u; - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_feature_lock_freelock_3 = DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_feature_lock_freelock_3; - INST_top.INST_m.DEF_hg_fifo_Start_TO_Stage__1_first____d168 = INST_top.INST_m.INST_hg_fifo_Start_TO_Stage__1.METH_first(); - INST_top.INST_m.DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169 = (tUInt32)((INST_top.INST_m.DEF_hg_fifo_Start_TO_Stage__1_first____d168) >> 35u); - INST_top.INST_m.DEF_hg_h_lock_entryVec_3___d59 = INST_top.INST_m.INST_hg_h_lock_entryVec_3.METH_read(); - INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BIT_10___d60 = (tUInt8)((INST_top.INST_m.DEF_hg_h_lock_entryVec_3___d59) >> 10u); - INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209 = !(INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BIT_10___d60); - INST_top.INST_m.DEF_hg_h_lock_entryVec_1___d49 = INST_top.INST_m.INST_hg_h_lock_entryVec_1.METH_read(); - INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BIT_10___d50 = (tUInt8)((INST_top.INST_m.DEF_hg_h_lock_entryVec_1___d49) >> 10u); - INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187 = !(INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BIT_10___d50); - INST_top.INST_m.DEF_hg_h_lock_entryVec_2___d54 = INST_top.INST_m.INST_hg_h_lock_entryVec_2.METH_read(); - INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BIT_10___d55 = (tUInt8)((INST_top.INST_m.DEF_hg_h_lock_entryVec_2___d54) >> 10u); - INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184 = !(INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BIT_10___d55); - INST_top.INST_m.DEF_hg_h_lock_entryVec_0___d44 = INST_top.INST_m.INST_hg_h_lock_entryVec_0.METH_read(); - INST_top.INST_m.DEF_hg_h_lock_entryVec_0_4_BIT_10___d45 = (tUInt8)((INST_top.INST_m.DEF_hg_h_lock_entryVec_0___d44) >> 10u); - INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190 = !(INST_top.INST_m.DEF_hg_h_lock_entryVec_0_4_BIT_10___d45); - DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_3_held_i_notFull____d204 = INST_top.INST_m.INST_hg_h_lock_lockVec_3_held.METH_i_notFull(); - DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_2_held_i_notFull____d203 = INST_top.INST_m.INST_hg_h_lock_lockVec_2_held.METH_i_notFull(); - DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_1_held_i_notFull____d202 = INST_top.INST_m.INST_hg_h_lock_lockVec_1_held.METH_i_notFull(); - DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_0_held_i_notFull____d201 = INST_top.INST_m.INST_hg_h_lock_lockVec_0_held.METH_i_notFull(); - INST_top.INST_m.DEF_b__h8511 = (tUInt32)(1023u & (INST_top.INST_m.DEF_hg_h_lock_entryVec_3___d59)); - INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170 = (INST_top.INST_m.DEF_b__h8511) == (INST_top.INST_m.DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169); - INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171 = INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BIT_10___d60 && INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170; - INST_top.INST_m.DEF_b__h8480 = (tUInt32)(1023u & (INST_top.INST_m.DEF_hg_h_lock_entryVec_2___d54)); - INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173 = (INST_top.INST_m.DEF_b__h8480) == (INST_top.INST_m.DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169); - INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174 = INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BIT_10___d55 && INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173; - INST_top.INST_m.DEF_b__h8449 = (tUInt32)(1023u & (INST_top.INST_m.DEF_hg_h_lock_entryVec_1___d49)); - INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176 = (INST_top.INST_m.DEF_b__h8449) == (INST_top.INST_m.DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169); - INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177 = INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BIT_10___d50 && INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176; - INST_top.INST_m.DEF_b__h8408 = (tUInt32)(1023u & (INST_top.INST_m.DEF_hg_h_lock_entryVec_0___d44)); - INST_top.INST_m.DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2___d43 = !INST_top.INST_m.INST_hg_h_lock_lockVec_0_held.METH_notEmpty(); - INST_top.INST_m.DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7___d48 = !INST_top.INST_m.INST_hg_h_lock_lockVec_1_held.METH_notEmpty(); - INST_top.INST_m.DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2___d53 = !INST_top.INST_m.INST_hg_h_lock_lockVec_2_held.METH_notEmpty(); - INST_top.INST_m.DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7___d58 = !INST_top.INST_m.INST_hg_h_lock_lockVec_3_held.METH_notEmpty(); - INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226 = INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209 || (INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184 || (INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187 || INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190)); - INST_top.INST_m.DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179 = (INST_top.INST_m.DEF_b__h8408) == (INST_top.INST_m.DEF_hg_fifo_Start_TO_Stage__1_first__68_BITS_44_TO_35___d169); - INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183 = INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171 || (INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174 || (INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177 || (INST_top.INST_m.DEF_hg_h_lock_entryVec_0_4_BIT_10___d45 && INST_top.INST_m.DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179))); - INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192 = INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190 || !(INST_top.INST_m.DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179); - INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206 = INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BIT_10___d50 && INST_top.INST_m.DEF_hg_h_lock_entryVec_0_4_BIT_10___d45; - INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207 = INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BIT_10___d55 && INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206; - INST_top.INST_m.DEF_x__h9842 = INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207 && INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209 ? (tUInt8)3u : (INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d206 && INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184 ? (tUInt8)2u : (INST_top.INST_m.DEF_hg_h_lock_entryVec_0_4_BIT_10___d45 && INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187 ? (tUInt8)1u : (tUInt8)0u)); - switch (INST_top.INST_m.DEF_x__h9842) { - case (tUInt8)0u: - DEF_INST_top_INST_m_DEF_CASE_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_ETC___d216 = DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_0_held_i_notFull____d201; - break; - case (tUInt8)1u: - DEF_INST_top_INST_m_DEF_CASE_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_ETC___d216 = DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_1_held_i_notFull____d202; - break; - case (tUInt8)2u: - DEF_INST_top_INST_m_DEF_CASE_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_ETC___d216 = DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_2_held_i_notFull____d203; - break; - case (tUInt8)3u: - DEF_INST_top_INST_m_DEF_CASE_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_ETC___d216 = DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_3_held_i_notFull____d204; - break; - default: - DEF_INST_top_INST_m_DEF_CASE_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_ETC___d216 = (tUInt8)1u; - } - INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193 = (INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187 || !(INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176)) && INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192; - INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194 = (INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184 || !(INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173)) && INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193; - INST_top.INST_m.DEF_x__h8976 = INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194 && INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d171 ? (tUInt8)3u : (INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d193 && INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d174 ? (tUInt8)2u : (INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d192 && INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d177 ? (tUInt8)1u : (tUInt8)0u)); - switch (INST_top.INST_m.DEF_x__h8976) { - case (tUInt8)0u: - DEF_INST_top_INST_m_DEF_CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d205 = DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_0_held_i_notFull____d201; - break; - case (tUInt8)1u: - DEF_INST_top_INST_m_DEF_CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d205 = DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_1_held_i_notFull____d202; - break; - case (tUInt8)2u: - DEF_INST_top_INST_m_DEF_CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d205 = DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_2_held_i_notFull____d203; - break; - case (tUInt8)3u: - DEF_INST_top_INST_m_DEF_CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d205 = DEF_INST_top_INST_m_DEF_hg_h_lock_lockVec_3_held_i_notFull____d204; - break; - default: - DEF_INST_top_INST_m_DEF_CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d205 = (tUInt8)1u; - } - switch (INST_top.INST_m.DEF_x__h8976) { - case (tUInt8)0u: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_h_lock_lockVec_0_held_notEmpty__ETC___d229 = INST_top.INST_m.DEF_NOT_hg_h_lock_lockVec_0_held_notEmpty__2___d43; - break; - case (tUInt8)1u: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_h_lock_lockVec_0_held_notEmpty__ETC___d229 = INST_top.INST_m.DEF_NOT_hg_h_lock_lockVec_1_held_notEmpty__7___d48; - break; - case (tUInt8)2u: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_h_lock_lockVec_0_held_notEmpty__ETC___d229 = INST_top.INST_m.DEF_NOT_hg_h_lock_lockVec_2_held_notEmpty__2___d53; - break; - case (tUInt8)3u: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_h_lock_lockVec_0_held_notEmpty__ETC___d229 = INST_top.INST_m.DEF_NOT_hg_h_lock_lockVec_3_held_notEmpty__7___d58; - break; - default: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_h_lock_lockVec_0_held_notEmpty__ETC___d229 = (tUInt8)0u; - } - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_s_Stage__1_execute = (INST_top.INST_m.INST_hg_fifo_Start_TO_Stage__1.METH_i_notEmpty() && (INST_top.INST_m.INST_hg_fifo_Stage__1_TO_Stage__2.METH_i_notFull() && (INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183 ? DEF_INST_top_INST_m_DEF_CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d205 : (INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BIT_10___d60 && INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d207) || DEF_INST_top_INST_m_DEF_CASE_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_ETC___d216))) && (((INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170 || (INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173 || (INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176 || INST_top.INST_m.DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179))) || INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226) && (INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d183 ? DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_h_lock_lockVec_0_held_notEmpty__ETC___d229 : INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226)); - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__1_execute = DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_s_Stage__1_execute; - INST_top.INST_m.DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283 = INST_top.INST_m.INST_hg_fifo_Stage__1_TO_Stage__2.METH_first(); - INST_top.INST_m.DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284 = (tUInt32)((INST_top.INST_m.DEF_hg_fifo_Stage__1_TO_Stage__2_first____d283) >> 38u); - INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285 = (INST_top.INST_m.DEF_b__h8511) == (INST_top.INST_m.DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284); - INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288 = (INST_top.INST_m.DEF_b__h8480) == (INST_top.INST_m.DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284); - INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291 = (INST_top.INST_m.DEF_b__h8449) == (INST_top.INST_m.DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284); - INST_top.INST_m.DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294 = (INST_top.INST_m.DEF_b__h8408) == (INST_top.INST_m.DEF_hg_fifo_Stage__1_TO_Stage__2_first__83_BITS_47_ETC___d284); - INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302 = INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BIT_10___d55 && INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288; - INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300 = INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BIT_10___d60 && INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285; - INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304 = INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BIT_10___d50 && INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291; - INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296 = INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5___d190 || !(INST_top.INST_m.DEF_hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294); - INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297 = (INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0___d187 || !(INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291)) && INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296; - INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298 = (INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5___d184 || !(INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288)) && INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297; - INST_top.INST_m.DEF_x__h10519 = INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298 && INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lock__ETC___d300 ? (tUInt8)3u : (INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d297 && INST_top.INST_m.DEF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d302 ? (tUInt8)2u : (INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_NOT__ETC___d296 && INST_top.INST_m.DEF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lock__ETC___d304 ? (tUInt8)1u : (tUInt8)0u)); - switch (INST_top.INST_m.DEF_x__h10519) { - case (tUInt8)0u: - DEF_INST_top_INST_m_DEF_CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d313 = INST_top.INST_m.INST_hg_h_lock_lockVec_0_held.METH_i_notEmpty(); - break; - case (tUInt8)1u: - DEF_INST_top_INST_m_DEF_CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d313 = INST_top.INST_m.INST_hg_h_lock_lockVec_1_held.METH_i_notEmpty(); - break; - case (tUInt8)2u: - DEF_INST_top_INST_m_DEF_CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d313 = INST_top.INST_m.INST_hg_h_lock_lockVec_2_held.METH_i_notEmpty(); - break; - case (tUInt8)3u: - DEF_INST_top_INST_m_DEF_CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d313 = INST_top.INST_m.INST_hg_h_lock_lockVec_3_held.METH_i_notEmpty(); - break; - default: - DEF_INST_top_INST_m_DEF_CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d313 = (tUInt8)1u; - } - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_s_Stage__2_execute = INST_top.INST_m.INST_hg_fifo_Stage__1_TO_Stage__2.METH_i_notEmpty() && (INST_top.INST_m.INST_hg_fifo_Stage__2_TO_Stage__3.METH_i_notFull() && (((INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_3_9_BIT_10_0___d209 || !(INST_top.INST_m.DEF_hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285)) && INST_top.INST_m.DEF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298) || DEF_INST_top_INST_m_DEF_CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d313)); - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__2_execute = DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_s_Stage__2_execute && !DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__1_execute; - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_h_lock_freelock = (tUInt8)1u; - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_h_lock_freelock = (DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_h_lock_freelock && !DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__2_execute) && !DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__1_execute; - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_h_lock_freelock_1 = (tUInt8)1u; - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_h_lock_freelock_1 = (DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_h_lock_freelock_1 && !DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__2_execute) && !DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__1_execute; - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_h_lock_freelock_2 = (tUInt8)1u; - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_h_lock_freelock_2 = (DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_h_lock_freelock_2 && !DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__2_execute) && !DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__1_execute; - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_h_lock_freelock_3 = (tUInt8)1u; - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_h_lock_freelock_3 = (DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_h_lock_freelock_3 && !DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__2_execute) && !DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__1_execute; - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_s_Stage__3_execute = INST_top.INST_m.INST_hg_fifo_Stage__2_TO_Stage__3.METH_i_notEmpty(); - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__3_execute = DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_s_Stage__3_execute; - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_weight_lock_freelock = (tUInt8)1u; - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_weight_lock_freelock = DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_weight_lock_freelock; - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_weight_lock_freelock_2 = (tUInt8)1u; - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_weight_lock_freelock_2 = DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_weight_lock_freelock_2; - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_weight_lock_freelock_1 = (tUInt8)1u; - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_weight_lock_freelock_1 = DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_weight_lock_freelock_1; - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_weight_lock_freelock_3 = (tUInt8)1u; - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_weight_lock_freelock_3 = DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_weight_lock_freelock_3; - if (DEF_INST_top_DEF_WILL_FIRE_RL_stopTB) - INST_top.RL_stopTB(); - if (DEF_INST_top_DEF_WILL_FIRE_RL_initTB) - INST_top.RL_initTB(); - INST_top.INST_m.DEF_WILL_FIRE__inthg_req = INST_top.INST_m.PORT_EN__inthg_req; - INST_top.INST_m.DEF_hg_fifo__input__TO_Start_i_notFull____d66 = INST_top.INST_m.INST_hg_fifo__input__TO_Start.METH_i_notFull(); - INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first____d63 = INST_top.INST_m.INST_hg_fifo__input__TO_Start.METH_first(); - INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64 = (tUInt32)((INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first____d63) >> 3u); - INST_top.INST_m.DEF_hg_weight_lock_entryVec_3___d39 = INST_top.INST_m.INST_hg_weight_lock_entryVec_3.METH_read(); - INST_top.INST_m.DEF_hg_weight_lock_entryVec_3_9_BIT_10___d40 = (tUInt8)((INST_top.INST_m.DEF_hg_weight_lock_entryVec_3___d39) >> 10u); - INST_top.INST_m.DEF_hg_weight_lock_entryVec_1___d29 = INST_top.INST_m.INST_hg_weight_lock_entryVec_1.METH_read(); - INST_top.INST_m.DEF_hg_weight_lock_entryVec_1_9_BIT_10___d30 = (tUInt8)((INST_top.INST_m.DEF_hg_weight_lock_entryVec_1___d29) >> 10u); - DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_1_9_BIT_10_0___d135 = !(INST_top.INST_m.DEF_hg_weight_lock_entryVec_1_9_BIT_10___d30); - INST_top.INST_m.DEF_hg_weight_lock_entryVec_2___d34 = INST_top.INST_m.INST_hg_weight_lock_entryVec_2.METH_read(); - INST_top.INST_m.DEF_hg_weight_lock_entryVec_2_4_BIT_10___d35 = (tUInt8)((INST_top.INST_m.DEF_hg_weight_lock_entryVec_2___d34) >> 10u); - DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_2_4_BIT_10_5___d132 = !(INST_top.INST_m.DEF_hg_weight_lock_entryVec_2_4_BIT_10___d35); - INST_top.INST_m.DEF_hg_weight_lock_entryVec_0___d24 = INST_top.INST_m.INST_hg_weight_lock_entryVec_0.METH_read(); - INST_top.INST_m.DEF_hg_feature_lock_entryVec_3___d19 = INST_top.INST_m.INST_hg_feature_lock_entryVec_3.METH_read(); - INST_top.INST_m.DEF_hg_feature_lock_entryVec_3_9_BIT_10___d20 = (tUInt8)((INST_top.INST_m.DEF_hg_feature_lock_entryVec_3___d19) >> 10u); - INST_top.INST_m.DEF_hg_feature_lock_entryVec_2___d14 = INST_top.INST_m.INST_hg_feature_lock_entryVec_2.METH_read(); - INST_top.INST_m.DEF_hg_feature_lock_entryVec_2_4_BIT_10___d15 = (tUInt8)((INST_top.INST_m.DEF_hg_feature_lock_entryVec_2___d14) >> 10u); - DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_2_4_BIT_10_5___d91 = !(INST_top.INST_m.DEF_hg_feature_lock_entryVec_2_4_BIT_10___d15); - INST_top.INST_m.DEF_hg_feature_lock_entryVec_1___d9 = INST_top.INST_m.INST_hg_feature_lock_entryVec_1.METH_read(); - INST_top.INST_m.DEF_hg_feature_lock_entryVec_1_BIT_10___d10 = (tUInt8)((INST_top.INST_m.DEF_hg_feature_lock_entryVec_1___d9) >> 10u); - DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_1_BIT_10_0___d94 = !(INST_top.INST_m.DEF_hg_feature_lock_entryVec_1_BIT_10___d10); - INST_top.INST_m.DEF_hg_feature_lock_entryVec_0___d3 = INST_top.INST_m.INST_hg_feature_lock_entryVec_0.METH_read(); - INST_top.INST_m.DEF_hg_busyReg__h7113 = INST_top.INST_m.INST_hg_busyReg.METH_read(); - DEF_INST_top_INST_m_DEF_b__h7738 = (tUInt32)(1023u & (INST_top.INST_m.DEF_hg_weight_lock_entryVec_3___d39)); - DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_3_9_BIT_10_0_AND_hg_we_ETC___d118 = INST_top.INST_m.DEF_hg_weight_lock_entryVec_3_9_BIT_10___d40 && DEF_INST_top_INST_m_DEF_b__h7738 == (INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64); - DEF_INST_top_INST_m_DEF_b__h7707 = (tUInt32)(1023u & (INST_top.INST_m.DEF_hg_weight_lock_entryVec_2___d34)); - DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_2_4_BITS_9_TO_0_19_EQ__ETC___d120 = DEF_INST_top_INST_m_DEF_b__h7707 == (INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64); - DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_2_4_BIT_10_5_AND_hg_we_ETC___d121 = INST_top.INST_m.DEF_hg_weight_lock_entryVec_2_4_BIT_10___d35 && DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_2_4_BITS_9_TO_0_19_EQ__ETC___d120; - DEF_INST_top_INST_m_DEF_b__h7676 = (tUInt32)(1023u & (INST_top.INST_m.DEF_hg_weight_lock_entryVec_1___d29)); - DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_1_9_BITS_9_TO_0_22_EQ__ETC___d123 = DEF_INST_top_INST_m_DEF_b__h7676 == (INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64); - DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_1_9_BIT_10_0_AND_hg_we_ETC___d124 = INST_top.INST_m.DEF_hg_weight_lock_entryVec_1_9_BIT_10___d30 && DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_1_9_BITS_9_TO_0_22_EQ__ETC___d123; - DEF_INST_top_INST_m_DEF_b__h7646 = (tUInt32)(1023u & (INST_top.INST_m.DEF_hg_weight_lock_entryVec_0___d24)); - DEF_INST_top_INST_m_DEF_b__h7274 = (tUInt32)(1023u & (INST_top.INST_m.DEF_hg_feature_lock_entryVec_3___d19)); - DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_3_9_BIT_10_0_AND_hg_f_ETC___d77 = INST_top.INST_m.DEF_hg_feature_lock_entryVec_3_9_BIT_10___d20 && DEF_INST_top_INST_m_DEF_b__h7274 == (INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64); - DEF_INST_top_INST_m_DEF_b__h7243 = (tUInt32)(1023u & (INST_top.INST_m.DEF_hg_feature_lock_entryVec_2___d14)); - DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_2_4_BITS_9_TO_0_8_EQ__ETC___d79 = DEF_INST_top_INST_m_DEF_b__h7243 == (INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64); - DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_2_4_BIT_10_5_AND_hg_f_ETC___d80 = INST_top.INST_m.DEF_hg_feature_lock_entryVec_2_4_BIT_10___d15 && DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_2_4_BITS_9_TO_0_8_EQ__ETC___d79; - DEF_INST_top_INST_m_DEF_b__h7182 = (tUInt32)(1023u & (INST_top.INST_m.DEF_hg_feature_lock_entryVec_0___d3)); - DEF_INST_top_INST_m_DEF_b__h7212 = (tUInt32)(1023u & (INST_top.INST_m.DEF_hg_feature_lock_entryVec_1___d9)); - DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_1_BITS_9_TO_0_1_EQ_hg_ETC___d82 = DEF_INST_top_INST_m_DEF_b__h7212 == (INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64); - DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_1_BIT_10_0_AND_hg_fea_ETC___d83 = INST_top.INST_m.DEF_hg_feature_lock_entryVec_1_BIT_10___d10 && DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_1_BITS_9_TO_0_1_EQ_hg_ETC___d82; - INST_top.INST_m.DEF_hg_weight_lock_entryVec_0_4_BIT_10___d25 = (tUInt8)((INST_top.INST_m.DEF_hg_weight_lock_entryVec_0___d24) >> 10u); - DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_0_4_BIT_10_5___d138 = !(INST_top.INST_m.DEF_hg_weight_lock_entryVec_0_4_BIT_10___d25); - INST_top.INST_m.DEF_hg_feature_lock_entryVec_0_BIT_10___d4 = (tUInt8)((INST_top.INST_m.DEF_hg_feature_lock_entryVec_0___d3) >> 10u); - DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_0_BIT_10___d97 = !(INST_top.INST_m.DEF_hg_feature_lock_entryVec_0_BIT_10___d4); - INST_top.INST_m.DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2___d23 = !INST_top.INST_m.INST_hg_weight_lock_lockVec_0_held.METH_notEmpty(); - INST_top.INST_m.DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7___d28 = !INST_top.INST_m.INST_hg_weight_lock_lockVec_1_held.METH_notEmpty(); - INST_top.INST_m.DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2___d33 = !INST_top.INST_m.INST_hg_weight_lock_lockVec_2_held.METH_notEmpty(); - INST_top.INST_m.DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7___d38 = !INST_top.INST_m.INST_hg_weight_lock_lockVec_3_held.METH_notEmpty(); - INST_top.INST_m.DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty___d2 = !INST_top.INST_m.INST_hg_feature_lock_lockVec_0_held.METH_notEmpty(); - INST_top.INST_m.DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty___d8 = !INST_top.INST_m.INST_hg_feature_lock_lockVec_1_held.METH_notEmpty(); - INST_top.INST_m.DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2___d13 = !INST_top.INST_m.INST_hg_feature_lock_lockVec_2_held.METH_notEmpty(); - INST_top.INST_m.DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7___d18 = !INST_top.INST_m.INST_hg_feature_lock_lockVec_3_held.METH_notEmpty(); - INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 = (INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64) < 1000u; - DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_0_4_BITS_9_TO_0_25_EQ__ETC___d126 = DEF_INST_top_INST_m_DEF_b__h7646 == (INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64); - DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_0_4_BIT_10_5_38_OR_ETC___d140 = DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_0_4_BIT_10_5___d138 || !DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_0_4_BITS_9_TO_0_25_EQ__ETC___d126; - DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_0_BITS_9_TO_0_4_EQ_hg_ETC___d85 = DEF_INST_top_INST_m_DEF_b__h7182 == (INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3___d64); - DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_0_BIT_10_7_OR_NOT_ETC___d99 = DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_0_BIT_10___d97 || !DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_0_BITS_9_TO_0_4_EQ_hg_ETC___d85; - INST_top.INST_m.DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74 = !(INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65); - DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_1_9_BIT_10_0_35_OR_ETC___d141 = (DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_1_9_BIT_10_0___d135 || !DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_1_9_BITS_9_TO_0_22_EQ__ETC___d123) && DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_0_4_BIT_10_5_38_OR_ETC___d140; - DEF_INST_top_INST_m_DEF_x__h7932 = ((DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_2_4_BIT_10_5___d132 || !DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_2_4_BITS_9_TO_0_19_EQ__ETC___d120) && DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_1_9_BIT_10_0_35_OR_ETC___d141) && DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_3_9_BIT_10_0_AND_hg_we_ETC___d118 ? (tUInt8)3u : (DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_1_9_BIT_10_0_35_OR_ETC___d141 && DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_2_4_BIT_10_5_AND_hg_we_ETC___d121 ? (tUInt8)2u : (DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_0_4_BIT_10_5_38_OR_ETC___d140 && DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_1_9_BIT_10_0_AND_hg_we_ETC___d124 ? (tUInt8)1u : (tUInt8)0u)); - switch (DEF_INST_top_INST_m_DEF_x__h7932) { - case (tUInt8)0u: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_weight_lock_lockVec_0_held_notE_ETC___d149 = INST_top.INST_m.DEF_NOT_hg_weight_lock_lockVec_0_held_notEmpty__2___d23; - break; - case (tUInt8)1u: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_weight_lock_lockVec_0_held_notE_ETC___d149 = INST_top.INST_m.DEF_NOT_hg_weight_lock_lockVec_1_held_notEmpty__7___d28; - break; - case (tUInt8)2u: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_weight_lock_lockVec_0_held_notE_ETC___d149 = INST_top.INST_m.DEF_NOT_hg_weight_lock_lockVec_2_held_notEmpty__2___d33; - break; - case (tUInt8)3u: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_weight_lock_lockVec_0_held_notE_ETC___d149 = INST_top.INST_m.DEF_NOT_hg_weight_lock_lockVec_3_held_notEmpty__7___d38; - break; - default: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_weight_lock_lockVec_0_held_notE_ETC___d149 = (tUInt8)0u; - } - DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_1_BIT_10_0_4_OR_N_ETC___d100 = (DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_1_BIT_10_0___d94 || !DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_1_BITS_9_TO_0_1_EQ_hg_ETC___d82) && DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_0_BIT_10_7_OR_NOT_ETC___d99; - DEF_INST_top_INST_m_DEF_x__h7468 = ((DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_2_4_BIT_10_5___d91 || !DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_2_4_BITS_9_TO_0_8_EQ__ETC___d79) && DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_1_BIT_10_0_4_OR_N_ETC___d100) && DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_3_9_BIT_10_0_AND_hg_f_ETC___d77 ? (tUInt8)3u : (DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_1_BIT_10_0_4_OR_N_ETC___d100 && DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_2_4_BIT_10_5_AND_hg_f_ETC___d80 ? (tUInt8)2u : (DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_0_BIT_10_7_OR_NOT_ETC___d99 && DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_1_BIT_10_0_AND_hg_fea_ETC___d83 ? (tUInt8)1u : (tUInt8)0u)); - switch (DEF_INST_top_INST_m_DEF_x__h7468) { - case (tUInt8)0u: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_feature_lock_lockVec_0_held_not_ETC___d108 = INST_top.INST_m.DEF_NOT_hg_feature_lock_lockVec_0_held_notEmpty___d2; - break; - case (tUInt8)1u: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_feature_lock_lockVec_0_held_not_ETC___d108 = INST_top.INST_m.DEF_NOT_hg_feature_lock_lockVec_1_held_notEmpty___d8; - break; - case (tUInt8)2u: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_feature_lock_lockVec_0_held_not_ETC___d108 = INST_top.INST_m.DEF_NOT_hg_feature_lock_lockVec_2_held_notEmpty__2___d13; - break; - case (tUInt8)3u: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_feature_lock_lockVec_0_held_not_ETC___d108 = INST_top.INST_m.DEF_NOT_hg_feature_lock_lockVec_3_held_notEmpty__7___d18; - break; - default: - DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_feature_lock_lockVec_0_held_not_ETC___d108 = (tUInt8)0u; - } - DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_s_Start_execute = (INST_top.INST_m.INST_hg_fifo__input__TO_Start.METH_i_notEmpty() && (INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 ? INST_top.INST_m.DEF_hg_fifo__input__TO_Start_i_notFull____d66 && INST_top.INST_m.INST_hg_fifo_Start_TO_Stage__1.METH_i_notFull() : INST_top.INST_m.INST_hg_outputQueue.METH_i_notFull())) && (((INST_top.INST_m.DEF_hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 || INST_top.INST_m.DEF_hg_busyReg__h7113) && (INST_top.INST_m.DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74 || (DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_3_9_BIT_10_0_AND_hg_f_ETC___d77 || (DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_2_4_BIT_10_5_AND_hg_f_ETC___d80 || (DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_1_BIT_10_0_AND_hg_fea_ETC___d83 || (INST_top.INST_m.DEF_hg_feature_lock_entryVec_0_BIT_10___d4 && DEF_INST_top_INST_m_DEF_hg_feature_lock_entryVec_0_BITS_9_TO_0_4_EQ_hg_ETC___d85))) ? DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_feature_lock_lockVec_0_held_not_ETC___d108 : !(INST_top.INST_m.DEF_hg_feature_lock_entryVec_3_9_BIT_10___d20) || (DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_2_4_BIT_10_5___d91 || (DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_1_BIT_10_0___d94 || DEF_INST_top_INST_m_DEF_NOT_hg_feature_lock_entryVec_0_BIT_10___d97))))) && (INST_top.INST_m.DEF_NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d74 || (DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_3_9_BIT_10_0_AND_hg_we_ETC___d118 || (DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_2_4_BIT_10_5_AND_hg_we_ETC___d121 || (DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_1_9_BIT_10_0_AND_hg_we_ETC___d124 || (INST_top.INST_m.DEF_hg_weight_lock_entryVec_0_4_BIT_10___d25 && DEF_INST_top_INST_m_DEF_hg_weight_lock_entryVec_0_4_BITS_9_TO_0_25_EQ__ETC___d126))) ? DEF_INST_top_INST_m_DEF_SEL_ARR_NOT_hg_weight_lock_lockVec_0_held_notE_ETC___d149 : !(INST_top.INST_m.DEF_hg_weight_lock_entryVec_3_9_BIT_10___d40) || (DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_2_4_BIT_10_5___d132 || (DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_1_9_BIT_10_0___d135 || DEF_INST_top_INST_m_DEF_NOT_hg_weight_lock_entryVec_0_4_BIT_10_5___d138))))); - DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Start_execute = DEF_INST_top_INST_m_DEF_CAN_FIRE_RL_hg_s_Start_execute && !(INST_top.INST_m.DEF_WILL_FIRE__inthg_req); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_h_lock_freelock) - INST_top.INST_m.RL_hg_h_lock_freelock(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_h_lock_freelock_1) - INST_top.INST_m.RL_hg_h_lock_freelock_1(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_h_lock_freelock_2) - INST_top.INST_m.RL_hg_h_lock_freelock_2(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_h_lock_freelock_3) - INST_top.INST_m.RL_hg_h_lock_freelock_3(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__1_execute) - INST_top.INST_m.RL_hg_s_Stage__1_execute(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__2_execute) - INST_top.INST_m.RL_hg_s_Stage__2_execute(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Stage__3_execute) - INST_top.INST_m.RL_hg_s_Stage__3_execute(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_s_Start_execute) - INST_top.INST_m.RL_hg_s_Start_execute(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_feature_lock_freelock) - INST_top.INST_m.RL_hg_feature_lock_freelock(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_feature_lock_freelock_1) - INST_top.INST_m.RL_hg_feature_lock_freelock_1(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_feature_lock_freelock_2) - INST_top.INST_m.RL_hg_feature_lock_freelock_2(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_feature_lock_freelock_3) - INST_top.INST_m.RL_hg_feature_lock_freelock_3(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_weight_lock_freelock) - INST_top.INST_m.RL_hg_weight_lock_freelock(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_weight_lock_freelock_1) - INST_top.INST_m.RL_hg_weight_lock_freelock_1(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_weight_lock_freelock_2) - INST_top.INST_m.RL_hg_weight_lock_freelock_2(); - if (DEF_INST_top_INST_m_DEF_WILL_FIRE_RL_hg_weight_lock_freelock_3) - INST_top.INST_m.RL_hg_weight_lock_freelock_3(); - if (do_reset_ticks(simHdl)) - { - INST_top.INST_m.INST_hg_fifo__input__TO_Start.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_fifo_Start_TO_Stage__1.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_fifo_Stage__1_TO_Stage__2.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_fifo_Stage__2_TO_Stage__3.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_lockVec_0_nextId.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_lockVec_0_held.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_lockVec_0_cnt.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_lockVec_1_nextId.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_lockVec_1_held.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_lockVec_1_cnt.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_lockVec_2_nextId.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_lockVec_2_held.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_lockVec_2_cnt.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_lockVec_3_nextId.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_lockVec_3_held.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_lockVec_3_cnt.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_entryVec_0.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_entryVec_1.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_entryVec_2.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_entryVec_3.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_lockVec_0_nextId.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_lockVec_0_held.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_lockVec_0_cnt.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_lockVec_1_nextId.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_lockVec_1_held.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_lockVec_1_cnt.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_lockVec_2_nextId.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_lockVec_2_held.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_lockVec_2_cnt.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_lockVec_3_nextId.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_lockVec_3_held.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_lockVec_3_cnt.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_entryVec_0.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_entryVec_1.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_entryVec_2.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_entryVec_3.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_lockVec_0_nextId.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_lockVec_0_held.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_lockVec_0_cnt.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_lockVec_1_nextId.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_lockVec_1_held.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_lockVec_1_cnt.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_lockVec_2_nextId.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_lockVec_2_held.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_lockVec_2_cnt.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_lockVec_3_nextId.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_lockVec_3_held.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_lockVec_3_cnt.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_entryVec_0.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_entryVec_1.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_entryVec_2.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_entryVec_3.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_feature_lock_region.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_weight_lock_region.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_h_lock_region.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_busyReg.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_m.INST_hg_outputQueue.rst_tick_clk((tUInt8)1u); - INST_top.INST_m.INST_hg.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_reg_unused_0.rst_tick__clk__1((tUInt8)1u); - INST_top.INST_started.rst_tick__clk__1((tUInt8)1u); - } - }; - -/* Model creation/destruction functions */ - -void MODEL_mkTB::create_model(tSimStateHdl simHdl, bool master) -{ - sim_hdl = simHdl; - init_reset_request_counters(sim_hdl); - mkTB_instance = new MOD_mkTB(sim_hdl, "top", NULL); - bk_get_or_define_clock(sim_hdl, "CLK"); - if (master) - { - bk_alter_clock(sim_hdl, bk_get_clock_by_name(sim_hdl, "CLK"), CLK_LOW, false, 0llu, 5llu, 5llu); - bk_use_default_reset(sim_hdl); - } - bk_set_clock_event_fn(sim_hdl, - bk_get_clock_by_name(sim_hdl, "CLK"), - schedule_posedge_CLK, - NULL, - (tEdgeDirection)(POSEDGE)); - (mkTB_instance->INST_m.INST_hg_fifo__input__TO_Start.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_fifo_Start_TO_Stage__1.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_fifo_Stage__1_TO_Stage__2.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_fifo_Stage__2_TO_Stage__3.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_feature_lock_lockVec_0_held.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_feature_lock_lockVec_1_held.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_feature_lock_lockVec_2_held.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_feature_lock_lockVec_3_held.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_weight_lock_lockVec_0_held.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_weight_lock_lockVec_1_held.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_weight_lock_lockVec_2_held.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_weight_lock_lockVec_3_held.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_h_lock_lockVec_0_held.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_h_lock_lockVec_1_held.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_h_lock_lockVec_2_held.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_h_lock_lockVec_3_held.set_clk_0)("CLK"); - (mkTB_instance->INST_m.INST_hg_outputQueue.set_clk_0)("CLK"); - (mkTB_instance->INST_m.set_clk_0)("CLK"); - (mkTB_instance->set_clk_0)("CLK"); -} -void MODEL_mkTB::destroy_model() -{ - delete mkTB_instance; - mkTB_instance = NULL; -} -void MODEL_mkTB::reset_model(bool asserted) -{ - (mkTB_instance->reset_RST_N)(asserted ? (tUInt8)0u : (tUInt8)1u); -} -void * MODEL_mkTB::get_instance() -{ - return mkTB_instance; -} - -/* Fill in version numbers */ -void MODEL_mkTB::get_version(unsigned int *year, - unsigned int *month, - char const **annotation, - char const **build) -{ - *year = 0u; - *month = 0u; - *annotation = NULL; - *build = NULL; -} - -/* Get the model creation time */ -time_t MODEL_mkTB::get_creation_time() -{ - - /* Thu Jan 1 00:00:00 UTC 1970 */ - return 0llu; -} - -/* State dumping function */ -void MODEL_mkTB::dump_state() -{ - (mkTB_instance->dump_state)(0u); -} - -/* VCD dumping functions */ -MOD_mkTB & mkTB_backing(tSimStateHdl simHdl) -{ - static MOD_mkTB *instance = NULL; - if (instance == NULL) - { - vcd_set_backing_instance(simHdl, true); - instance = new MOD_mkTB(simHdl, "top", NULL); - vcd_set_backing_instance(simHdl, false); - } - return *instance; -} -void MODEL_mkTB::dump_VCD_defs() -{ - (mkTB_instance->dump_VCD_defs)(vcd_depth(sim_hdl)); -} -void MODEL_mkTB::dump_VCD(tVCDDumpType dt) -{ - (mkTB_instance->dump_VCD)(dt, vcd_depth(sim_hdl), mkTB_backing(sim_hdl)); -} diff --git a/src/main/scala/pipedsl/testOutputs/Circuit_sim/model_mkTB.h b/src/main/scala/pipedsl/testOutputs/Circuit_sim/model_mkTB.h deleted file mode 100644 index e4b02ccf..00000000 --- a/src/main/scala/pipedsl/testOutputs/Circuit_sim/model_mkTB.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Generated by Bluespec Compiler - * - */ - -/* Generation options: */ -#ifndef __model_mkTB_h__ -#define __model_mkTB_h__ - -#include "bluesim_types.h" -#include "bs_module.h" -#include "bluesim_primitives.h" -#include "bs_vcd.h" - -#include "bs_model.h" -#include "mkTB.h" - -/* Class declaration for a model of mkTB */ -class MODEL_mkTB : public Model { - - /* Top-level module instance */ - private: - MOD_mkTB *mkTB_instance; - - /* Handle to the simulation kernel */ - private: - tSimStateHdl sim_hdl; - - /* Constructor */ - public: - MODEL_mkTB(); - - /* Functions required by the kernel */ - public: - void create_model(tSimStateHdl simHdl, bool master); - void destroy_model(); - void reset_model(bool asserted); - void get_version(unsigned int *year, - unsigned int *month, - char const **annotation, - char const **build); - time_t get_creation_time(); - void * get_instance(); - void dump_state(); - void dump_VCD_defs(); - void dump_VCD(tVCDDumpType dt); -}; - -/* Function for creating a new model */ -extern "C" { - void * new_MODEL_mkTB(); -} - -#endif /* ifndef __model_mkTB_h__ */ diff --git a/src/main/scala/pipedsl/testOutputs/Circuit_sim/model_mkTB.o b/src/main/scala/pipedsl/testOutputs/Circuit_sim/model_mkTB.o deleted file mode 100644 index 5775b340..00000000 Binary files a/src/main/scala/pipedsl/testOutputs/Circuit_sim/model_mkTB.o and /dev/null differ diff --git a/src/main/scala/pipedsl/testOutputs/Circuit_verilog/mkCircuit.v b/src/main/scala/pipedsl/testOutputs/Circuit_verilog/mkCircuit.v deleted file mode 100644 index a2d6e976..00000000 --- a/src/main/scala/pipedsl/testOutputs/Circuit_verilog/mkCircuit.v +++ /dev/null @@ -1,2047 +0,0 @@ -// -// Generated by Bluespec Compiler -// -// -// Ports: -// Name I/O size props -// _inthg_req O 3 reg -// RDY__inthg_req O 1 -// RDY__inthg_resp O 1 reg -// _inthg_checkHandle O 1 -// RDY__inthg_checkHandle O 1 reg -// _inthg_peek O 1 reg -// RDY__inthg_peek O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// _inthg_req_counter I 10 -// _inthg_checkHandle_handle I 3 -// EN__inthg_resp I 1 -// EN__inthg_req I 1 -// -// Combinational paths from inputs to outputs: -// _inthg_checkHandle_handle -> _inthg_checkHandle -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCircuit(CLK, - RST_N, - - _inthg_req_counter, - EN__inthg_req, - _inthg_req, - RDY__inthg_req, - - EN__inthg_resp, - RDY__inthg_resp, - - _inthg_checkHandle_handle, - _inthg_checkHandle, - RDY__inthg_checkHandle, - - _inthg_peek, - RDY__inthg_peek); - input CLK; - input RST_N; - - // actionvalue method _inthg_req - input [9 : 0] _inthg_req_counter; - input EN__inthg_req; - output [2 : 0] _inthg_req; - output RDY__inthg_req; - - // action method _inthg_resp - input EN__inthg_resp; - output RDY__inthg_resp; - - // value method _inthg_checkHandle - input [2 : 0] _inthg_checkHandle_handle; - output _inthg_checkHandle; - output RDY__inthg_checkHandle; - - // value method _inthg_peek - output _inthg_peek; - output RDY__inthg_peek; - - // signals for module outputs - wire [2 : 0] _inthg_req; - wire RDY__inthg_checkHandle, - RDY__inthg_peek, - RDY__inthg_req, - RDY__inthg_resp, - _inthg_checkHandle, - _inthg_peek; - - // register hg - reg [2 : 0] hg; - wire [2 : 0] hg$D_IN; - wire hg$EN; - - // register hg_busyReg - reg hg_busyReg; - wire hg_busyReg$D_IN, hg_busyReg$EN; - - // register hg_feature_lock_entryVec_0 - reg [10 : 0] hg_feature_lock_entryVec_0; - wire [10 : 0] hg_feature_lock_entryVec_0$D_IN; - wire hg_feature_lock_entryVec_0$EN; - - // register hg_feature_lock_entryVec_1 - reg [10 : 0] hg_feature_lock_entryVec_1; - wire [10 : 0] hg_feature_lock_entryVec_1$D_IN; - wire hg_feature_lock_entryVec_1$EN; - - // register hg_feature_lock_entryVec_2 - reg [10 : 0] hg_feature_lock_entryVec_2; - wire [10 : 0] hg_feature_lock_entryVec_2$D_IN; - wire hg_feature_lock_entryVec_2$EN; - - // register hg_feature_lock_entryVec_3 - reg [10 : 0] hg_feature_lock_entryVec_3; - wire [10 : 0] hg_feature_lock_entryVec_3$D_IN; - wire hg_feature_lock_entryVec_3$EN; - - // register hg_feature_lock_lockVec_0_cnt - reg [1 : 0] hg_feature_lock_lockVec_0_cnt; - wire [1 : 0] hg_feature_lock_lockVec_0_cnt$D_IN; - wire hg_feature_lock_lockVec_0_cnt$EN; - - // register hg_feature_lock_lockVec_0_nextId - reg [1 : 0] hg_feature_lock_lockVec_0_nextId; - wire [1 : 0] hg_feature_lock_lockVec_0_nextId$D_IN; - wire hg_feature_lock_lockVec_0_nextId$EN; - - // register hg_feature_lock_lockVec_1_cnt - reg [1 : 0] hg_feature_lock_lockVec_1_cnt; - wire [1 : 0] hg_feature_lock_lockVec_1_cnt$D_IN; - wire hg_feature_lock_lockVec_1_cnt$EN; - - // register hg_feature_lock_lockVec_1_nextId - reg [1 : 0] hg_feature_lock_lockVec_1_nextId; - wire [1 : 0] hg_feature_lock_lockVec_1_nextId$D_IN; - wire hg_feature_lock_lockVec_1_nextId$EN; - - // register hg_feature_lock_lockVec_2_cnt - reg [1 : 0] hg_feature_lock_lockVec_2_cnt; - wire [1 : 0] hg_feature_lock_lockVec_2_cnt$D_IN; - wire hg_feature_lock_lockVec_2_cnt$EN; - - // register hg_feature_lock_lockVec_2_nextId - reg [1 : 0] hg_feature_lock_lockVec_2_nextId; - wire [1 : 0] hg_feature_lock_lockVec_2_nextId$D_IN; - wire hg_feature_lock_lockVec_2_nextId$EN; - - // register hg_feature_lock_lockVec_3_cnt - reg [1 : 0] hg_feature_lock_lockVec_3_cnt; - wire [1 : 0] hg_feature_lock_lockVec_3_cnt$D_IN; - wire hg_feature_lock_lockVec_3_cnt$EN; - - // register hg_feature_lock_lockVec_3_nextId - reg [1 : 0] hg_feature_lock_lockVec_3_nextId; - wire [1 : 0] hg_feature_lock_lockVec_3_nextId$D_IN; - wire hg_feature_lock_lockVec_3_nextId$EN; - - // register hg_feature_lock_region - reg hg_feature_lock_region; - wire hg_feature_lock_region$D_IN, hg_feature_lock_region$EN; - - // register hg_h_lock_entryVec_0 - reg [10 : 0] hg_h_lock_entryVec_0; - wire [10 : 0] hg_h_lock_entryVec_0$D_IN; - wire hg_h_lock_entryVec_0$EN; - - // register hg_h_lock_entryVec_1 - reg [10 : 0] hg_h_lock_entryVec_1; - wire [10 : 0] hg_h_lock_entryVec_1$D_IN; - wire hg_h_lock_entryVec_1$EN; - - // register hg_h_lock_entryVec_2 - reg [10 : 0] hg_h_lock_entryVec_2; - wire [10 : 0] hg_h_lock_entryVec_2$D_IN; - wire hg_h_lock_entryVec_2$EN; - - // register hg_h_lock_entryVec_3 - reg [10 : 0] hg_h_lock_entryVec_3; - wire [10 : 0] hg_h_lock_entryVec_3$D_IN; - wire hg_h_lock_entryVec_3$EN; - - // register hg_h_lock_lockVec_0_cnt - reg [1 : 0] hg_h_lock_lockVec_0_cnt; - wire [1 : 0] hg_h_lock_lockVec_0_cnt$D_IN; - wire hg_h_lock_lockVec_0_cnt$EN; - - // register hg_h_lock_lockVec_0_nextId - reg [1 : 0] hg_h_lock_lockVec_0_nextId; - wire [1 : 0] hg_h_lock_lockVec_0_nextId$D_IN; - wire hg_h_lock_lockVec_0_nextId$EN; - - // register hg_h_lock_lockVec_1_cnt - reg [1 : 0] hg_h_lock_lockVec_1_cnt; - wire [1 : 0] hg_h_lock_lockVec_1_cnt$D_IN; - wire hg_h_lock_lockVec_1_cnt$EN; - - // register hg_h_lock_lockVec_1_nextId - reg [1 : 0] hg_h_lock_lockVec_1_nextId; - wire [1 : 0] hg_h_lock_lockVec_1_nextId$D_IN; - wire hg_h_lock_lockVec_1_nextId$EN; - - // register hg_h_lock_lockVec_2_cnt - reg [1 : 0] hg_h_lock_lockVec_2_cnt; - wire [1 : 0] hg_h_lock_lockVec_2_cnt$D_IN; - wire hg_h_lock_lockVec_2_cnt$EN; - - // register hg_h_lock_lockVec_2_nextId - reg [1 : 0] hg_h_lock_lockVec_2_nextId; - wire [1 : 0] hg_h_lock_lockVec_2_nextId$D_IN; - wire hg_h_lock_lockVec_2_nextId$EN; - - // register hg_h_lock_lockVec_3_cnt - reg [1 : 0] hg_h_lock_lockVec_3_cnt; - wire [1 : 0] hg_h_lock_lockVec_3_cnt$D_IN; - wire hg_h_lock_lockVec_3_cnt$EN; - - // register hg_h_lock_lockVec_3_nextId - reg [1 : 0] hg_h_lock_lockVec_3_nextId; - wire [1 : 0] hg_h_lock_lockVec_3_nextId$D_IN; - wire hg_h_lock_lockVec_3_nextId$EN; - - // register hg_h_lock_region - reg hg_h_lock_region; - wire hg_h_lock_region$D_IN, hg_h_lock_region$EN; - - // register hg_weight_lock_entryVec_0 - reg [10 : 0] hg_weight_lock_entryVec_0; - wire [10 : 0] hg_weight_lock_entryVec_0$D_IN; - wire hg_weight_lock_entryVec_0$EN; - - // register hg_weight_lock_entryVec_1 - reg [10 : 0] hg_weight_lock_entryVec_1; - wire [10 : 0] hg_weight_lock_entryVec_1$D_IN; - wire hg_weight_lock_entryVec_1$EN; - - // register hg_weight_lock_entryVec_2 - reg [10 : 0] hg_weight_lock_entryVec_2; - wire [10 : 0] hg_weight_lock_entryVec_2$D_IN; - wire hg_weight_lock_entryVec_2$EN; - - // register hg_weight_lock_entryVec_3 - reg [10 : 0] hg_weight_lock_entryVec_3; - wire [10 : 0] hg_weight_lock_entryVec_3$D_IN; - wire hg_weight_lock_entryVec_3$EN; - - // register hg_weight_lock_lockVec_0_cnt - reg [1 : 0] hg_weight_lock_lockVec_0_cnt; - wire [1 : 0] hg_weight_lock_lockVec_0_cnt$D_IN; - wire hg_weight_lock_lockVec_0_cnt$EN; - - // register hg_weight_lock_lockVec_0_nextId - reg [1 : 0] hg_weight_lock_lockVec_0_nextId; - wire [1 : 0] hg_weight_lock_lockVec_0_nextId$D_IN; - wire hg_weight_lock_lockVec_0_nextId$EN; - - // register hg_weight_lock_lockVec_1_cnt - reg [1 : 0] hg_weight_lock_lockVec_1_cnt; - wire [1 : 0] hg_weight_lock_lockVec_1_cnt$D_IN; - wire hg_weight_lock_lockVec_1_cnt$EN; - - // register hg_weight_lock_lockVec_1_nextId - reg [1 : 0] hg_weight_lock_lockVec_1_nextId; - wire [1 : 0] hg_weight_lock_lockVec_1_nextId$D_IN; - wire hg_weight_lock_lockVec_1_nextId$EN; - - // register hg_weight_lock_lockVec_2_cnt - reg [1 : 0] hg_weight_lock_lockVec_2_cnt; - wire [1 : 0] hg_weight_lock_lockVec_2_cnt$D_IN; - wire hg_weight_lock_lockVec_2_cnt$EN; - - // register hg_weight_lock_lockVec_2_nextId - reg [1 : 0] hg_weight_lock_lockVec_2_nextId; - wire [1 : 0] hg_weight_lock_lockVec_2_nextId$D_IN; - wire hg_weight_lock_lockVec_2_nextId$EN; - - // register hg_weight_lock_lockVec_3_cnt - reg [1 : 0] hg_weight_lock_lockVec_3_cnt; - wire [1 : 0] hg_weight_lock_lockVec_3_cnt$D_IN; - wire hg_weight_lock_lockVec_3_cnt$EN; - - // register hg_weight_lock_lockVec_3_nextId - reg [1 : 0] hg_weight_lock_lockVec_3_nextId; - wire [1 : 0] hg_weight_lock_lockVec_3_nextId$D_IN; - wire hg_weight_lock_lockVec_3_nextId$EN; - - // register hg_weight_lock_region - reg hg_weight_lock_region; - wire hg_weight_lock_region$D_IN, hg_weight_lock_region$EN; - - // ports of submodule f_rf - wire [9 : 0] f_rf$ADDR_1, - f_rf$ADDR_2, - f_rf$ADDR_3, - f_rf$ADDR_4, - f_rf$ADDR_5, - f_rf$ADDR_IN, - f_rf$D_IN, - f_rf$D_OUT_1; - wire f_rf$WE; - - // ports of submodule h_rf - wire [31 : 0] h_rf$D_IN, h_rf$D_OUT_1; - wire [9 : 0] h_rf$ADDR_1, - h_rf$ADDR_2, - h_rf$ADDR_3, - h_rf$ADDR_4, - h_rf$ADDR_5, - h_rf$ADDR_IN; - wire h_rf$WE; - - // ports of submodule hg_feature_lock_lockVec_0_held - wire [1 : 0] hg_feature_lock_lockVec_0_held$D_IN; - wire hg_feature_lock_lockVec_0_held$CLR, - hg_feature_lock_lockVec_0_held$DEQ, - hg_feature_lock_lockVec_0_held$EMPTY_N, - hg_feature_lock_lockVec_0_held$ENQ; - - // ports of submodule hg_feature_lock_lockVec_1_held - wire [1 : 0] hg_feature_lock_lockVec_1_held$D_IN; - wire hg_feature_lock_lockVec_1_held$CLR, - hg_feature_lock_lockVec_1_held$DEQ, - hg_feature_lock_lockVec_1_held$EMPTY_N, - hg_feature_lock_lockVec_1_held$ENQ; - - // ports of submodule hg_feature_lock_lockVec_2_held - wire [1 : 0] hg_feature_lock_lockVec_2_held$D_IN; - wire hg_feature_lock_lockVec_2_held$CLR, - hg_feature_lock_lockVec_2_held$DEQ, - hg_feature_lock_lockVec_2_held$EMPTY_N, - hg_feature_lock_lockVec_2_held$ENQ; - - // ports of submodule hg_feature_lock_lockVec_3_held - wire [1 : 0] hg_feature_lock_lockVec_3_held$D_IN; - wire hg_feature_lock_lockVec_3_held$CLR, - hg_feature_lock_lockVec_3_held$DEQ, - hg_feature_lock_lockVec_3_held$EMPTY_N, - hg_feature_lock_lockVec_3_held$ENQ; - - // ports of submodule hg_fifo_Stage__1_TO_Stage__2 - wire [47 : 0] hg_fifo_Stage__1_TO_Stage__2$D_IN, - hg_fifo_Stage__1_TO_Stage__2$D_OUT; - wire hg_fifo_Stage__1_TO_Stage__2$CLR, - hg_fifo_Stage__1_TO_Stage__2$DEQ, - hg_fifo_Stage__1_TO_Stage__2$EMPTY_N, - hg_fifo_Stage__1_TO_Stage__2$ENQ, - hg_fifo_Stage__1_TO_Stage__2$FULL_N; - - // ports of submodule hg_fifo_Stage__2_TO_Stage__3 - wire [2 : 0] hg_fifo_Stage__2_TO_Stage__3$D_IN; - wire hg_fifo_Stage__2_TO_Stage__3$CLR, - hg_fifo_Stage__2_TO_Stage__3$DEQ, - hg_fifo_Stage__2_TO_Stage__3$EMPTY_N, - hg_fifo_Stage__2_TO_Stage__3$ENQ, - hg_fifo_Stage__2_TO_Stage__3$FULL_N; - - // ports of submodule hg_fifo_Start_TO_Stage__1 - wire [44 : 0] hg_fifo_Start_TO_Stage__1$D_IN, - hg_fifo_Start_TO_Stage__1$D_OUT; - wire hg_fifo_Start_TO_Stage__1$CLR, - hg_fifo_Start_TO_Stage__1$DEQ, - hg_fifo_Start_TO_Stage__1$EMPTY_N, - hg_fifo_Start_TO_Stage__1$ENQ, - hg_fifo_Start_TO_Stage__1$FULL_N; - - // ports of submodule hg_fifo__input__TO_Start - wire [12 : 0] hg_fifo__input__TO_Start$D_IN, hg_fifo__input__TO_Start$D_OUT; - wire hg_fifo__input__TO_Start$CLR, - hg_fifo__input__TO_Start$DEQ, - hg_fifo__input__TO_Start$EMPTY_N, - hg_fifo__input__TO_Start$ENQ, - hg_fifo__input__TO_Start$FULL_N; - - // ports of submodule hg_h_lock_lockVec_0_held - wire [1 : 0] hg_h_lock_lockVec_0_held$D_IN, hg_h_lock_lockVec_0_held$D_OUT; - wire hg_h_lock_lockVec_0_held$CLR, - hg_h_lock_lockVec_0_held$DEQ, - hg_h_lock_lockVec_0_held$EMPTY_N, - hg_h_lock_lockVec_0_held$ENQ, - hg_h_lock_lockVec_0_held$FULL_N; - - // ports of submodule hg_h_lock_lockVec_1_held - wire [1 : 0] hg_h_lock_lockVec_1_held$D_IN, hg_h_lock_lockVec_1_held$D_OUT; - wire hg_h_lock_lockVec_1_held$CLR, - hg_h_lock_lockVec_1_held$DEQ, - hg_h_lock_lockVec_1_held$EMPTY_N, - hg_h_lock_lockVec_1_held$ENQ, - hg_h_lock_lockVec_1_held$FULL_N; - - // ports of submodule hg_h_lock_lockVec_2_held - wire [1 : 0] hg_h_lock_lockVec_2_held$D_IN, hg_h_lock_lockVec_2_held$D_OUT; - wire hg_h_lock_lockVec_2_held$CLR, - hg_h_lock_lockVec_2_held$DEQ, - hg_h_lock_lockVec_2_held$EMPTY_N, - hg_h_lock_lockVec_2_held$ENQ, - hg_h_lock_lockVec_2_held$FULL_N; - - // ports of submodule hg_h_lock_lockVec_3_held - wire [1 : 0] hg_h_lock_lockVec_3_held$D_IN, hg_h_lock_lockVec_3_held$D_OUT; - wire hg_h_lock_lockVec_3_held$CLR, - hg_h_lock_lockVec_3_held$DEQ, - hg_h_lock_lockVec_3_held$EMPTY_N, - hg_h_lock_lockVec_3_held$ENQ, - hg_h_lock_lockVec_3_held$FULL_N; - - // ports of submodule hg_outputQueue - wire [3 : 0] hg_outputQueue$D_IN, hg_outputQueue$D_OUT; - wire hg_outputQueue$CLR, - hg_outputQueue$DEQ, - hg_outputQueue$EMPTY_N, - hg_outputQueue$ENQ, - hg_outputQueue$FULL_N; - - // ports of submodule hg_weight_lock_lockVec_0_held - wire [1 : 0] hg_weight_lock_lockVec_0_held$D_IN; - wire hg_weight_lock_lockVec_0_held$CLR, - hg_weight_lock_lockVec_0_held$DEQ, - hg_weight_lock_lockVec_0_held$EMPTY_N, - hg_weight_lock_lockVec_0_held$ENQ; - - // ports of submodule hg_weight_lock_lockVec_1_held - wire [1 : 0] hg_weight_lock_lockVec_1_held$D_IN; - wire hg_weight_lock_lockVec_1_held$CLR, - hg_weight_lock_lockVec_1_held$DEQ, - hg_weight_lock_lockVec_1_held$EMPTY_N, - hg_weight_lock_lockVec_1_held$ENQ; - - // ports of submodule hg_weight_lock_lockVec_2_held - wire [1 : 0] hg_weight_lock_lockVec_2_held$D_IN; - wire hg_weight_lock_lockVec_2_held$CLR, - hg_weight_lock_lockVec_2_held$DEQ, - hg_weight_lock_lockVec_2_held$EMPTY_N, - hg_weight_lock_lockVec_2_held$ENQ; - - // ports of submodule hg_weight_lock_lockVec_3_held - wire [1 : 0] hg_weight_lock_lockVec_3_held$D_IN; - wire hg_weight_lock_lockVec_3_held$CLR, - hg_weight_lock_lockVec_3_held$DEQ, - hg_weight_lock_lockVec_3_held$EMPTY_N, - hg_weight_lock_lockVec_3_held$ENQ; - - // ports of submodule w_rf - wire [31 : 0] w_rf$D_IN, w_rf$D_OUT_1; - wire [9 : 0] w_rf$ADDR_1, - w_rf$ADDR_2, - w_rf$ADDR_3, - w_rf$ADDR_4, - w_rf$ADDR_5, - w_rf$ADDR_IN; - wire w_rf$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_hg_s_Start_execute, - WILL_FIRE_RL_hg_h_lock_freelock, - WILL_FIRE_RL_hg_s_Stage__1_execute, - WILL_FIRE_RL_hg_s_Stage__2_execute, - WILL_FIRE_RL_hg_s_Start_execute; - - // inputs to muxes for submodule ports - wire [12 : 0] MUX_hg_fifo__input__TO_Start$enq_1__VAL_1, - MUX_hg_fifo__input__TO_Start$enq_1__VAL_2; - wire [10 : 0] MUX_hg_h_lock_entryVec_0$write_1__VAL_2; - wire MUX_hg_busyReg$write_1__SEL_1, - MUX_hg_fifo__input__TO_Start$enq_1__SEL_1, - MUX_hg_h_lock_entryVec_0$write_1__SEL_1, - MUX_hg_h_lock_entryVec_1$write_1__SEL_1, - MUX_hg_h_lock_entryVec_2$write_1__SEL_1, - MUX_hg_h_lock_entryVec_3$write_1__SEL_1; - - // remaining internal signals - reg [1 : 0] SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d275, - SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d276; - reg CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d205, - CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d313, - CASE_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_ETC___d216, - SEL_ARR_NOT_hg_feature_lock_lockVec_0_held_not_ETC___d108, - SEL_ARR_NOT_hg_h_lock_lockVec_0_held_notEmpty__ETC___d229, - SEL_ARR_NOT_hg_weight_lock_lockVec_0_held_notE_ETC___d149; - wire [31 : 0] h_rf_sub_hg_fifo_Start_TO_Stage__1_first__68_B_ETC___d235; - wire [1 : 0] IF_NOT_hg_feature_lock_entryVec_0_BIT_10_7_OR__ETC___d105, - IF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_N_ETC___d198, - IF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_N_ETC___d306, - IF_NOT_hg_weight_lock_entryVec_0_4_BIT_10_5_38_ETC___d146, - IF_hg_fifo_Stage__1_TO_Stage__2_first__83_BIT__ETC___d321, - IF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lo_ETC___d214, - IF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lo_ETC___d277, - x__h10519, - x__h7468, - x__h7932, - x__h8976, - x__h9842; - wire IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d238, - IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d244, - IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d250, - IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d256, - IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d328, - IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d333, - IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d338, - IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d343, - IF_hg_fifo__input__TO_Start_first__3_BITS_12_T_ETC___d70, - IF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lo_ETC___d218, - IF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lo_ETC___d230, - NOT_hg_feature_lock_entryVec_1_BIT_10_0_4_OR_N_ETC___d103, - NOT_hg_feature_lock_entryVec_2_4_BIT_10_5_1_OR_ETC___d101, - NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d114, - NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d155, - NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d196, - NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d303, - NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194, - NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298, - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226, - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265, - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d314, - NOT_hg_weight_lock_entryVec_1_9_BIT_10_0_35_OR_ETC___d144, - NOT_hg_weight_lock_entryVec_2_4_BIT_10_5_32_OR_ETC___d142, - hg_feature_lock_entryVec_0_BITS_9_TO_0_4_EQ_hg_ETC___d85, - hg_feature_lock_entryVec_1_BITS_9_TO_0_1_EQ_hg_ETC___d82, - hg_feature_lock_entryVec_2_4_BITS_9_TO_0_8_EQ__ETC___d79, - hg_feature_lock_entryVec_2_4_BIT_10_5_AND_hg_f_ETC___d88, - hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65, - hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179, - hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294, - hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176, - hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291, - hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173, - hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288, - hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d182, - hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d326, - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170, - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285, - hg_weight_lock_entryVec_0_4_BITS_9_TO_0_25_EQ__ETC___d126, - hg_weight_lock_entryVec_1_9_BITS_9_TO_0_22_EQ__ETC___d123, - hg_weight_lock_entryVec_2_4_BITS_9_TO_0_19_EQ__ETC___d120, - hg_weight_lock_entryVec_2_4_BIT_10_5_AND_hg_we_ETC___d129; - - // actionvalue method _inthg_req - assign _inthg_req = hg ; - assign RDY__inthg_req = !hg_busyReg && hg_fifo__input__TO_Start$FULL_N ; - - // action method _inthg_resp - assign RDY__inthg_resp = hg_outputQueue$EMPTY_N ; - - // value method _inthg_checkHandle - assign _inthg_checkHandle = - _inthg_checkHandle_handle == hg_outputQueue$D_OUT[3:1] ; - assign RDY__inthg_checkHandle = hg_outputQueue$EMPTY_N ; - - // value method _inthg_peek - assign _inthg_peek = hg_outputQueue$D_OUT[0] ; - assign RDY__inthg_peek = hg_outputQueue$EMPTY_N ; - - // submodule f_rf - RegFileLoad #(.file("f"), - .addr_width(32'd10), - .data_width(32'd10), - .lo(10'h0), - .hi(10'd1023), - .binary(1'd0)) f_rf(.CLK(CLK), - .ADDR_1(f_rf$ADDR_1), - .ADDR_2(f_rf$ADDR_2), - .ADDR_3(f_rf$ADDR_3), - .ADDR_4(f_rf$ADDR_4), - .ADDR_5(f_rf$ADDR_5), - .ADDR_IN(f_rf$ADDR_IN), - .D_IN(f_rf$D_IN), - .WE(f_rf$WE), - .D_OUT_1(f_rf$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule h_rf - RegFileLoad #(.file("h"), - .addr_width(32'd10), - .data_width(32'd32), - .lo(10'h0), - .hi(10'd1023), - .binary(1'd0)) h_rf(.CLK(CLK), - .ADDR_1(h_rf$ADDR_1), - .ADDR_2(h_rf$ADDR_2), - .ADDR_3(h_rf$ADDR_3), - .ADDR_4(h_rf$ADDR_4), - .ADDR_5(h_rf$ADDR_5), - .ADDR_IN(h_rf$ADDR_IN), - .D_IN(h_rf$D_IN), - .WE(h_rf$WE), - .D_OUT_1(h_rf$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule hg_feature_lock_lockVec_0_held - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) hg_feature_lock_lockVec_0_held(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_feature_lock_lockVec_0_held$D_IN), - .ENQ(hg_feature_lock_lockVec_0_held$ENQ), - .DEQ(hg_feature_lock_lockVec_0_held$DEQ), - .CLR(hg_feature_lock_lockVec_0_held$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N(hg_feature_lock_lockVec_0_held$EMPTY_N)); - - // submodule hg_feature_lock_lockVec_1_held - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) hg_feature_lock_lockVec_1_held(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_feature_lock_lockVec_1_held$D_IN), - .ENQ(hg_feature_lock_lockVec_1_held$ENQ), - .DEQ(hg_feature_lock_lockVec_1_held$DEQ), - .CLR(hg_feature_lock_lockVec_1_held$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N(hg_feature_lock_lockVec_1_held$EMPTY_N)); - - // submodule hg_feature_lock_lockVec_2_held - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) hg_feature_lock_lockVec_2_held(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_feature_lock_lockVec_2_held$D_IN), - .ENQ(hg_feature_lock_lockVec_2_held$ENQ), - .DEQ(hg_feature_lock_lockVec_2_held$DEQ), - .CLR(hg_feature_lock_lockVec_2_held$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N(hg_feature_lock_lockVec_2_held$EMPTY_N)); - - // submodule hg_feature_lock_lockVec_3_held - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) hg_feature_lock_lockVec_3_held(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_feature_lock_lockVec_3_held$D_IN), - .ENQ(hg_feature_lock_lockVec_3_held$ENQ), - .DEQ(hg_feature_lock_lockVec_3_held$DEQ), - .CLR(hg_feature_lock_lockVec_3_held$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N(hg_feature_lock_lockVec_3_held$EMPTY_N)); - - // submodule hg_fifo_Stage__1_TO_Stage__2 - FIFO2 #(.width(32'd48), - .guarded(32'd1)) hg_fifo_Stage__1_TO_Stage__2(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_fifo_Stage__1_TO_Stage__2$D_IN), - .ENQ(hg_fifo_Stage__1_TO_Stage__2$ENQ), - .DEQ(hg_fifo_Stage__1_TO_Stage__2$DEQ), - .CLR(hg_fifo_Stage__1_TO_Stage__2$CLR), - .D_OUT(hg_fifo_Stage__1_TO_Stage__2$D_OUT), - .FULL_N(hg_fifo_Stage__1_TO_Stage__2$FULL_N), - .EMPTY_N(hg_fifo_Stage__1_TO_Stage__2$EMPTY_N)); - - // submodule hg_fifo_Stage__2_TO_Stage__3 - FIFO2 #(.width(32'd3), - .guarded(32'd1)) hg_fifo_Stage__2_TO_Stage__3(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_fifo_Stage__2_TO_Stage__3$D_IN), - .ENQ(hg_fifo_Stage__2_TO_Stage__3$ENQ), - .DEQ(hg_fifo_Stage__2_TO_Stage__3$DEQ), - .CLR(hg_fifo_Stage__2_TO_Stage__3$CLR), - .D_OUT(), - .FULL_N(hg_fifo_Stage__2_TO_Stage__3$FULL_N), - .EMPTY_N(hg_fifo_Stage__2_TO_Stage__3$EMPTY_N)); - - // submodule hg_fifo_Start_TO_Stage__1 - FIFO2 #(.width(32'd45), - .guarded(32'd1)) hg_fifo_Start_TO_Stage__1(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_fifo_Start_TO_Stage__1$D_IN), - .ENQ(hg_fifo_Start_TO_Stage__1$ENQ), - .DEQ(hg_fifo_Start_TO_Stage__1$DEQ), - .CLR(hg_fifo_Start_TO_Stage__1$CLR), - .D_OUT(hg_fifo_Start_TO_Stage__1$D_OUT), - .FULL_N(hg_fifo_Start_TO_Stage__1$FULL_N), - .EMPTY_N(hg_fifo_Start_TO_Stage__1$EMPTY_N)); - - // submodule hg_fifo__input__TO_Start - FIFO2 #(.width(32'd13), - .guarded(32'd1)) hg_fifo__input__TO_Start(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_fifo__input__TO_Start$D_IN), - .ENQ(hg_fifo__input__TO_Start$ENQ), - .DEQ(hg_fifo__input__TO_Start$DEQ), - .CLR(hg_fifo__input__TO_Start$CLR), - .D_OUT(hg_fifo__input__TO_Start$D_OUT), - .FULL_N(hg_fifo__input__TO_Start$FULL_N), - .EMPTY_N(hg_fifo__input__TO_Start$EMPTY_N)); - - // submodule hg_h_lock_lockVec_0_held - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) hg_h_lock_lockVec_0_held(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_h_lock_lockVec_0_held$D_IN), - .ENQ(hg_h_lock_lockVec_0_held$ENQ), - .DEQ(hg_h_lock_lockVec_0_held$DEQ), - .CLR(hg_h_lock_lockVec_0_held$CLR), - .D_OUT(hg_h_lock_lockVec_0_held$D_OUT), - .FULL_N(hg_h_lock_lockVec_0_held$FULL_N), - .EMPTY_N(hg_h_lock_lockVec_0_held$EMPTY_N)); - - // submodule hg_h_lock_lockVec_1_held - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) hg_h_lock_lockVec_1_held(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_h_lock_lockVec_1_held$D_IN), - .ENQ(hg_h_lock_lockVec_1_held$ENQ), - .DEQ(hg_h_lock_lockVec_1_held$DEQ), - .CLR(hg_h_lock_lockVec_1_held$CLR), - .D_OUT(hg_h_lock_lockVec_1_held$D_OUT), - .FULL_N(hg_h_lock_lockVec_1_held$FULL_N), - .EMPTY_N(hg_h_lock_lockVec_1_held$EMPTY_N)); - - // submodule hg_h_lock_lockVec_2_held - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) hg_h_lock_lockVec_2_held(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_h_lock_lockVec_2_held$D_IN), - .ENQ(hg_h_lock_lockVec_2_held$ENQ), - .DEQ(hg_h_lock_lockVec_2_held$DEQ), - .CLR(hg_h_lock_lockVec_2_held$CLR), - .D_OUT(hg_h_lock_lockVec_2_held$D_OUT), - .FULL_N(hg_h_lock_lockVec_2_held$FULL_N), - .EMPTY_N(hg_h_lock_lockVec_2_held$EMPTY_N)); - - // submodule hg_h_lock_lockVec_3_held - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) hg_h_lock_lockVec_3_held(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_h_lock_lockVec_3_held$D_IN), - .ENQ(hg_h_lock_lockVec_3_held$ENQ), - .DEQ(hg_h_lock_lockVec_3_held$DEQ), - .CLR(hg_h_lock_lockVec_3_held$CLR), - .D_OUT(hg_h_lock_lockVec_3_held$D_OUT), - .FULL_N(hg_h_lock_lockVec_3_held$FULL_N), - .EMPTY_N(hg_h_lock_lockVec_3_held$EMPTY_N)); - - // submodule hg_outputQueue - FIFO2 #(.width(32'd4), .guarded(32'd1)) hg_outputQueue(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_outputQueue$D_IN), - .ENQ(hg_outputQueue$ENQ), - .DEQ(hg_outputQueue$DEQ), - .CLR(hg_outputQueue$CLR), - .D_OUT(hg_outputQueue$D_OUT), - .FULL_N(hg_outputQueue$FULL_N), - .EMPTY_N(hg_outputQueue$EMPTY_N)); - - // submodule hg_weight_lock_lockVec_0_held - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) hg_weight_lock_lockVec_0_held(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_weight_lock_lockVec_0_held$D_IN), - .ENQ(hg_weight_lock_lockVec_0_held$ENQ), - .DEQ(hg_weight_lock_lockVec_0_held$DEQ), - .CLR(hg_weight_lock_lockVec_0_held$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N(hg_weight_lock_lockVec_0_held$EMPTY_N)); - - // submodule hg_weight_lock_lockVec_1_held - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) hg_weight_lock_lockVec_1_held(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_weight_lock_lockVec_1_held$D_IN), - .ENQ(hg_weight_lock_lockVec_1_held$ENQ), - .DEQ(hg_weight_lock_lockVec_1_held$DEQ), - .CLR(hg_weight_lock_lockVec_1_held$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N(hg_weight_lock_lockVec_1_held$EMPTY_N)); - - // submodule hg_weight_lock_lockVec_2_held - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) hg_weight_lock_lockVec_2_held(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_weight_lock_lockVec_2_held$D_IN), - .ENQ(hg_weight_lock_lockVec_2_held$ENQ), - .DEQ(hg_weight_lock_lockVec_2_held$DEQ), - .CLR(hg_weight_lock_lockVec_2_held$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N(hg_weight_lock_lockVec_2_held$EMPTY_N)); - - // submodule hg_weight_lock_lockVec_3_held - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) hg_weight_lock_lockVec_3_held(.RST(RST_N), - .CLK(CLK), - .D_IN(hg_weight_lock_lockVec_3_held$D_IN), - .ENQ(hg_weight_lock_lockVec_3_held$ENQ), - .DEQ(hg_weight_lock_lockVec_3_held$DEQ), - .CLR(hg_weight_lock_lockVec_3_held$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N(hg_weight_lock_lockVec_3_held$EMPTY_N)); - - // submodule w_rf - RegFileLoad #(.file("w"), - .addr_width(32'd10), - .data_width(32'd32), - .lo(10'h0), - .hi(10'd1023), - .binary(1'd0)) w_rf(.CLK(CLK), - .ADDR_1(w_rf$ADDR_1), - .ADDR_2(w_rf$ADDR_2), - .ADDR_3(w_rf$ADDR_3), - .ADDR_4(w_rf$ADDR_4), - .ADDR_5(w_rf$ADDR_5), - .ADDR_IN(w_rf$ADDR_IN), - .D_IN(w_rf$D_IN), - .WE(w_rf$WE), - .D_OUT_1(w_rf$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // rule RL_hg_s_Start_execute - assign CAN_FIRE_RL_hg_s_Start_execute = - hg_fifo__input__TO_Start$EMPTY_N && - IF_hg_fifo__input__TO_Start_first__3_BITS_12_T_ETC___d70 && - (hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 || - hg_busyReg) && - NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d114 && - NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d155 ; - assign WILL_FIRE_RL_hg_s_Start_execute = - CAN_FIRE_RL_hg_s_Start_execute && !EN__inthg_req ; - - // rule RL_hg_s_Stage__1_execute - assign WILL_FIRE_RL_hg_s_Stage__1_execute = - hg_fifo_Start_TO_Stage__1$EMPTY_N && - hg_fifo_Stage__1_TO_Stage__2$FULL_N && - IF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lo_ETC___d218 && - (hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170 || - hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173 || - hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176 || - hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179 || - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226) && - IF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lo_ETC___d230 ; - - // rule RL_hg_s_Stage__2_execute - assign WILL_FIRE_RL_hg_s_Stage__2_execute = - hg_fifo_Stage__1_TO_Stage__2$EMPTY_N && - hg_fifo_Stage__2_TO_Stage__3$FULL_N && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d314 && - !WILL_FIRE_RL_hg_s_Stage__1_execute ; - - // rule RL_hg_h_lock_freelock - assign WILL_FIRE_RL_hg_h_lock_freelock = - !WILL_FIRE_RL_hg_s_Stage__2_execute && - !WILL_FIRE_RL_hg_s_Stage__1_execute ; - - // inputs to muxes for submodule ports - assign MUX_hg_busyReg$write_1__SEL_1 = - WILL_FIRE_RL_hg_s_Start_execute && - !hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 ; - assign MUX_hg_fifo__input__TO_Start$enq_1__SEL_1 = - WILL_FIRE_RL_hg_s_Start_execute && - hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 ; - assign MUX_hg_h_lock_entryVec_0$write_1__SEL_1 = - WILL_FIRE_RL_hg_h_lock_freelock && - !hg_h_lock_lockVec_0_held$EMPTY_N && - hg_h_lock_entryVec_0[10] ; - assign MUX_hg_h_lock_entryVec_1$write_1__SEL_1 = - WILL_FIRE_RL_hg_h_lock_freelock && - !hg_h_lock_lockVec_1_held$EMPTY_N && - hg_h_lock_entryVec_1[10] ; - assign MUX_hg_h_lock_entryVec_2$write_1__SEL_1 = - WILL_FIRE_RL_hg_h_lock_freelock && - !hg_h_lock_lockVec_2_held$EMPTY_N && - hg_h_lock_entryVec_2[10] ; - assign MUX_hg_h_lock_entryVec_3$write_1__SEL_1 = - WILL_FIRE_RL_hg_h_lock_freelock && - !hg_h_lock_lockVec_3_held$EMPTY_N && - hg_h_lock_entryVec_3[10] ; - assign MUX_hg_fifo__input__TO_Start$enq_1__VAL_1 = - { hg_fifo__input__TO_Start$D_OUT[12:3] + 10'd1, - hg_fifo__input__TO_Start$D_OUT[2:0] } ; - assign MUX_hg_fifo__input__TO_Start$enq_1__VAL_2 = - { _inthg_req_counter, hg } ; - assign MUX_hg_h_lock_entryVec_0$write_1__VAL_2 = - { 1'd1, hg_fifo_Start_TO_Stage__1$D_OUT[44:35] } ; - - // register hg - assign hg$D_IN = hg + 3'd1 ; - assign hg$EN = EN__inthg_req ; - - // register hg_busyReg - assign hg_busyReg$D_IN = !MUX_hg_busyReg$write_1__SEL_1 ; - assign hg_busyReg$EN = - WILL_FIRE_RL_hg_s_Start_execute && - !hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 || - EN__inthg_req ; - - // register hg_feature_lock_entryVec_0 - assign hg_feature_lock_entryVec_0$D_IN = 11'd682 ; - assign hg_feature_lock_entryVec_0$EN = - !hg_feature_lock_lockVec_0_held$EMPTY_N && - hg_feature_lock_entryVec_0[10] ; - - // register hg_feature_lock_entryVec_1 - assign hg_feature_lock_entryVec_1$D_IN = 11'd682 ; - assign hg_feature_lock_entryVec_1$EN = - !hg_feature_lock_lockVec_1_held$EMPTY_N && - hg_feature_lock_entryVec_1[10] ; - - // register hg_feature_lock_entryVec_2 - assign hg_feature_lock_entryVec_2$D_IN = 11'd682 ; - assign hg_feature_lock_entryVec_2$EN = - !hg_feature_lock_lockVec_2_held$EMPTY_N && - hg_feature_lock_entryVec_2[10] ; - - // register hg_feature_lock_entryVec_3 - assign hg_feature_lock_entryVec_3$D_IN = 11'd682 ; - assign hg_feature_lock_entryVec_3$EN = - !hg_feature_lock_lockVec_3_held$EMPTY_N && - hg_feature_lock_entryVec_3[10] ; - - // register hg_feature_lock_lockVec_0_cnt - assign hg_feature_lock_lockVec_0_cnt$D_IN = 2'h0 ; - assign hg_feature_lock_lockVec_0_cnt$EN = 1'b0 ; - - // register hg_feature_lock_lockVec_0_nextId - assign hg_feature_lock_lockVec_0_nextId$D_IN = 2'h0 ; - assign hg_feature_lock_lockVec_0_nextId$EN = 1'b0 ; - - // register hg_feature_lock_lockVec_1_cnt - assign hg_feature_lock_lockVec_1_cnt$D_IN = 2'h0 ; - assign hg_feature_lock_lockVec_1_cnt$EN = 1'b0 ; - - // register hg_feature_lock_lockVec_1_nextId - assign hg_feature_lock_lockVec_1_nextId$D_IN = 2'h0 ; - assign hg_feature_lock_lockVec_1_nextId$EN = 1'b0 ; - - // register hg_feature_lock_lockVec_2_cnt - assign hg_feature_lock_lockVec_2_cnt$D_IN = 2'h0 ; - assign hg_feature_lock_lockVec_2_cnt$EN = 1'b0 ; - - // register hg_feature_lock_lockVec_2_nextId - assign hg_feature_lock_lockVec_2_nextId$D_IN = 2'h0 ; - assign hg_feature_lock_lockVec_2_nextId$EN = 1'b0 ; - - // register hg_feature_lock_lockVec_3_cnt - assign hg_feature_lock_lockVec_3_cnt$D_IN = 2'h0 ; - assign hg_feature_lock_lockVec_3_cnt$EN = 1'b0 ; - - // register hg_feature_lock_lockVec_3_nextId - assign hg_feature_lock_lockVec_3_nextId$D_IN = 2'h0 ; - assign hg_feature_lock_lockVec_3_nextId$EN = 1'b0 ; - - // register hg_feature_lock_region - assign hg_feature_lock_region$D_IN = 1'b0 ; - assign hg_feature_lock_region$EN = 1'b0 ; - - // register hg_h_lock_entryVec_0 - assign hg_h_lock_entryVec_0$D_IN = - MUX_hg_h_lock_entryVec_0$write_1__SEL_1 ? - 11'd682 : - MUX_hg_h_lock_entryVec_0$write_1__VAL_2 ; - assign hg_h_lock_entryVec_0$EN = - WILL_FIRE_RL_hg_h_lock_freelock && - !hg_h_lock_lockVec_0_held$EMPTY_N && - hg_h_lock_entryVec_0[10] || - WILL_FIRE_RL_hg_s_Stage__1_execute && x__h9842 == 2'd0 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265 ; - - // register hg_h_lock_entryVec_1 - assign hg_h_lock_entryVec_1$D_IN = - MUX_hg_h_lock_entryVec_1$write_1__SEL_1 ? - 11'd682 : - MUX_hg_h_lock_entryVec_0$write_1__VAL_2 ; - assign hg_h_lock_entryVec_1$EN = - WILL_FIRE_RL_hg_h_lock_freelock && - !hg_h_lock_lockVec_1_held$EMPTY_N && - hg_h_lock_entryVec_1[10] || - WILL_FIRE_RL_hg_s_Stage__1_execute && x__h9842 == 2'd1 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265 ; - - // register hg_h_lock_entryVec_2 - assign hg_h_lock_entryVec_2$D_IN = - MUX_hg_h_lock_entryVec_2$write_1__SEL_1 ? - 11'd682 : - MUX_hg_h_lock_entryVec_0$write_1__VAL_2 ; - assign hg_h_lock_entryVec_2$EN = - WILL_FIRE_RL_hg_h_lock_freelock && - !hg_h_lock_lockVec_2_held$EMPTY_N && - hg_h_lock_entryVec_2[10] || - WILL_FIRE_RL_hg_s_Stage__1_execute && x__h9842 == 2'd2 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265 ; - - // register hg_h_lock_entryVec_3 - assign hg_h_lock_entryVec_3$D_IN = - MUX_hg_h_lock_entryVec_3$write_1__SEL_1 ? - 11'd682 : - MUX_hg_h_lock_entryVec_0$write_1__VAL_2 ; - assign hg_h_lock_entryVec_3$EN = - WILL_FIRE_RL_hg_h_lock_freelock && - !hg_h_lock_lockVec_3_held$EMPTY_N && - hg_h_lock_entryVec_3[10] || - WILL_FIRE_RL_hg_s_Stage__1_execute && x__h9842 == 2'd3 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265 ; - - // register hg_h_lock_lockVec_0_cnt - assign hg_h_lock_lockVec_0_cnt$D_IN = hg_h_lock_lockVec_0_cnt + 2'd1 ; - assign hg_h_lock_lockVec_0_cnt$EN = - WILL_FIRE_RL_hg_s_Stage__1_execute && - (IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d238 || - x__h9842 == 2'd0 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265) ; - - // register hg_h_lock_lockVec_0_nextId - assign hg_h_lock_lockVec_0_nextId$D_IN = hg_h_lock_lockVec_0_nextId + 2'd1 ; - assign hg_h_lock_lockVec_0_nextId$EN = - WILL_FIRE_RL_hg_s_Stage__1_execute && - (IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d238 || - x__h9842 == 2'd0 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265) ; - - // register hg_h_lock_lockVec_1_cnt - assign hg_h_lock_lockVec_1_cnt$D_IN = hg_h_lock_lockVec_1_cnt + 2'd1 ; - assign hg_h_lock_lockVec_1_cnt$EN = - WILL_FIRE_RL_hg_s_Stage__1_execute && - (IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d244 || - x__h9842 == 2'd1 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265) ; - - // register hg_h_lock_lockVec_1_nextId - assign hg_h_lock_lockVec_1_nextId$D_IN = hg_h_lock_lockVec_1_nextId + 2'd1 ; - assign hg_h_lock_lockVec_1_nextId$EN = - WILL_FIRE_RL_hg_s_Stage__1_execute && - (IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d244 || - x__h9842 == 2'd1 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265) ; - - // register hg_h_lock_lockVec_2_cnt - assign hg_h_lock_lockVec_2_cnt$D_IN = hg_h_lock_lockVec_2_cnt + 2'd1 ; - assign hg_h_lock_lockVec_2_cnt$EN = - WILL_FIRE_RL_hg_s_Stage__1_execute && - (IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d250 || - x__h9842 == 2'd2 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265) ; - - // register hg_h_lock_lockVec_2_nextId - assign hg_h_lock_lockVec_2_nextId$D_IN = hg_h_lock_lockVec_2_nextId + 2'd1 ; - assign hg_h_lock_lockVec_2_nextId$EN = - WILL_FIRE_RL_hg_s_Stage__1_execute && - (IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d250 || - x__h9842 == 2'd2 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265) ; - - // register hg_h_lock_lockVec_3_cnt - assign hg_h_lock_lockVec_3_cnt$D_IN = hg_h_lock_lockVec_3_cnt + 2'd1 ; - assign hg_h_lock_lockVec_3_cnt$EN = - WILL_FIRE_RL_hg_s_Stage__1_execute && - (IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d256 || - x__h9842 == 2'd3 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265) ; - - // register hg_h_lock_lockVec_3_nextId - assign hg_h_lock_lockVec_3_nextId$D_IN = hg_h_lock_lockVec_3_nextId + 2'd1 ; - assign hg_h_lock_lockVec_3_nextId$EN = - WILL_FIRE_RL_hg_s_Stage__1_execute && - (IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d256 || - x__h9842 == 2'd3 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265) ; - - // register hg_h_lock_region - assign hg_h_lock_region$D_IN = 1'b0 ; - assign hg_h_lock_region$EN = 1'b0 ; - - // register hg_weight_lock_entryVec_0 - assign hg_weight_lock_entryVec_0$D_IN = 11'd682 ; - assign hg_weight_lock_entryVec_0$EN = - !hg_weight_lock_lockVec_0_held$EMPTY_N && - hg_weight_lock_entryVec_0[10] ; - - // register hg_weight_lock_entryVec_1 - assign hg_weight_lock_entryVec_1$D_IN = 11'd682 ; - assign hg_weight_lock_entryVec_1$EN = - !hg_weight_lock_lockVec_1_held$EMPTY_N && - hg_weight_lock_entryVec_1[10] ; - - // register hg_weight_lock_entryVec_2 - assign hg_weight_lock_entryVec_2$D_IN = 11'd682 ; - assign hg_weight_lock_entryVec_2$EN = - !hg_weight_lock_lockVec_2_held$EMPTY_N && - hg_weight_lock_entryVec_2[10] ; - - // register hg_weight_lock_entryVec_3 - assign hg_weight_lock_entryVec_3$D_IN = 11'd682 ; - assign hg_weight_lock_entryVec_3$EN = - !hg_weight_lock_lockVec_3_held$EMPTY_N && - hg_weight_lock_entryVec_3[10] ; - - // register hg_weight_lock_lockVec_0_cnt - assign hg_weight_lock_lockVec_0_cnt$D_IN = 2'h0 ; - assign hg_weight_lock_lockVec_0_cnt$EN = 1'b0 ; - - // register hg_weight_lock_lockVec_0_nextId - assign hg_weight_lock_lockVec_0_nextId$D_IN = 2'h0 ; - assign hg_weight_lock_lockVec_0_nextId$EN = 1'b0 ; - - // register hg_weight_lock_lockVec_1_cnt - assign hg_weight_lock_lockVec_1_cnt$D_IN = 2'h0 ; - assign hg_weight_lock_lockVec_1_cnt$EN = 1'b0 ; - - // register hg_weight_lock_lockVec_1_nextId - assign hg_weight_lock_lockVec_1_nextId$D_IN = 2'h0 ; - assign hg_weight_lock_lockVec_1_nextId$EN = 1'b0 ; - - // register hg_weight_lock_lockVec_2_cnt - assign hg_weight_lock_lockVec_2_cnt$D_IN = 2'h0 ; - assign hg_weight_lock_lockVec_2_cnt$EN = 1'b0 ; - - // register hg_weight_lock_lockVec_2_nextId - assign hg_weight_lock_lockVec_2_nextId$D_IN = 2'h0 ; - assign hg_weight_lock_lockVec_2_nextId$EN = 1'b0 ; - - // register hg_weight_lock_lockVec_3_cnt - assign hg_weight_lock_lockVec_3_cnt$D_IN = 2'h0 ; - assign hg_weight_lock_lockVec_3_cnt$EN = 1'b0 ; - - // register hg_weight_lock_lockVec_3_nextId - assign hg_weight_lock_lockVec_3_nextId$D_IN = 2'h0 ; - assign hg_weight_lock_lockVec_3_nextId$EN = 1'b0 ; - - // register hg_weight_lock_region - assign hg_weight_lock_region$D_IN = 1'b0 ; - assign hg_weight_lock_region$EN = 1'b0 ; - - // submodule f_rf - assign f_rf$ADDR_1 = hg_fifo__input__TO_Start$D_OUT[12:3] ; - assign f_rf$ADDR_2 = 10'h0 ; - assign f_rf$ADDR_3 = 10'h0 ; - assign f_rf$ADDR_4 = 10'h0 ; - assign f_rf$ADDR_5 = 10'h0 ; - assign f_rf$ADDR_IN = 10'h0 ; - assign f_rf$D_IN = 10'h0 ; - assign f_rf$WE = 1'b0 ; - - // submodule h_rf - assign h_rf$ADDR_1 = hg_fifo_Start_TO_Stage__1$D_OUT[44:35] ; - assign h_rf$ADDR_2 = 10'h0 ; - assign h_rf$ADDR_3 = 10'h0 ; - assign h_rf$ADDR_4 = 10'h0 ; - assign h_rf$ADDR_5 = 10'h0 ; - assign h_rf$ADDR_IN = hg_fifo_Stage__1_TO_Stage__2$D_OUT[47:38] ; - assign h_rf$D_IN = hg_fifo_Stage__1_TO_Stage__2$D_OUT[37:6] ; - assign h_rf$WE = WILL_FIRE_RL_hg_s_Stage__2_execute ; - - // submodule hg_feature_lock_lockVec_0_held - assign hg_feature_lock_lockVec_0_held$D_IN = 2'h0 ; - assign hg_feature_lock_lockVec_0_held$ENQ = 1'b0 ; - assign hg_feature_lock_lockVec_0_held$DEQ = 1'b0 ; - assign hg_feature_lock_lockVec_0_held$CLR = 1'b0 ; - - // submodule hg_feature_lock_lockVec_1_held - assign hg_feature_lock_lockVec_1_held$D_IN = 2'h0 ; - assign hg_feature_lock_lockVec_1_held$ENQ = 1'b0 ; - assign hg_feature_lock_lockVec_1_held$DEQ = 1'b0 ; - assign hg_feature_lock_lockVec_1_held$CLR = 1'b0 ; - - // submodule hg_feature_lock_lockVec_2_held - assign hg_feature_lock_lockVec_2_held$D_IN = 2'h0 ; - assign hg_feature_lock_lockVec_2_held$ENQ = 1'b0 ; - assign hg_feature_lock_lockVec_2_held$DEQ = 1'b0 ; - assign hg_feature_lock_lockVec_2_held$CLR = 1'b0 ; - - // submodule hg_feature_lock_lockVec_3_held - assign hg_feature_lock_lockVec_3_held$D_IN = 2'h0 ; - assign hg_feature_lock_lockVec_3_held$ENQ = 1'b0 ; - assign hg_feature_lock_lockVec_3_held$DEQ = 1'b0 ; - assign hg_feature_lock_lockVec_3_held$CLR = 1'b0 ; - - // submodule hg_fifo_Stage__1_TO_Stage__2 - assign hg_fifo_Stage__1_TO_Stage__2$D_IN = - { hg_fifo_Start_TO_Stage__1$D_OUT[44:35], - h_rf_sub_hg_fifo_Start_TO_Stage__1_first__68_B_ETC___d235, - 1'd1, - IF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lo_ETC___d277, - hg_fifo_Start_TO_Stage__1$D_OUT[2:0] } ; - assign hg_fifo_Stage__1_TO_Stage__2$ENQ = - WILL_FIRE_RL_hg_s_Stage__1_execute ; - assign hg_fifo_Stage__1_TO_Stage__2$DEQ = - WILL_FIRE_RL_hg_s_Stage__2_execute ; - assign hg_fifo_Stage__1_TO_Stage__2$CLR = 1'b0 ; - - // submodule hg_fifo_Stage__2_TO_Stage__3 - assign hg_fifo_Stage__2_TO_Stage__3$D_IN = - hg_fifo_Stage__1_TO_Stage__2$D_OUT[2:0] ; - assign hg_fifo_Stage__2_TO_Stage__3$ENQ = - WILL_FIRE_RL_hg_s_Stage__2_execute ; - assign hg_fifo_Stage__2_TO_Stage__3$DEQ = - hg_fifo_Stage__2_TO_Stage__3$EMPTY_N ; - assign hg_fifo_Stage__2_TO_Stage__3$CLR = 1'b0 ; - - // submodule hg_fifo_Start_TO_Stage__1 - assign hg_fifo_Start_TO_Stage__1$D_IN = - { f_rf$D_OUT_1, - w_rf$D_OUT_1, - hg_fifo__input__TO_Start$D_OUT[2:0] } ; - assign hg_fifo_Start_TO_Stage__1$ENQ = - MUX_hg_fifo__input__TO_Start$enq_1__SEL_1 ; - assign hg_fifo_Start_TO_Stage__1$DEQ = WILL_FIRE_RL_hg_s_Stage__1_execute ; - assign hg_fifo_Start_TO_Stage__1$CLR = 1'b0 ; - - // submodule hg_fifo__input__TO_Start - assign hg_fifo__input__TO_Start$D_IN = - MUX_hg_fifo__input__TO_Start$enq_1__SEL_1 ? - MUX_hg_fifo__input__TO_Start$enq_1__VAL_1 : - MUX_hg_fifo__input__TO_Start$enq_1__VAL_2 ; - assign hg_fifo__input__TO_Start$ENQ = - WILL_FIRE_RL_hg_s_Start_execute && - hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 || - EN__inthg_req ; - assign hg_fifo__input__TO_Start$DEQ = WILL_FIRE_RL_hg_s_Start_execute ; - assign hg_fifo__input__TO_Start$CLR = 1'b0 ; - - // submodule hg_h_lock_lockVec_0_held - assign hg_h_lock_lockVec_0_held$D_IN = hg_h_lock_lockVec_0_nextId ; - assign hg_h_lock_lockVec_0_held$ENQ = - WILL_FIRE_RL_hg_s_Stage__1_execute && - (IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d238 || - x__h9842 == 2'd0 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265) ; - assign hg_h_lock_lockVec_0_held$DEQ = - WILL_FIRE_RL_hg_s_Stage__2_execute && - hg_h_lock_lockVec_0_held$D_OUT == - IF_hg_fifo_Stage__1_TO_Stage__2_first__83_BIT__ETC___d321 && - IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d328 ; - assign hg_h_lock_lockVec_0_held$CLR = 1'b0 ; - - // submodule hg_h_lock_lockVec_1_held - assign hg_h_lock_lockVec_1_held$D_IN = hg_h_lock_lockVec_1_nextId ; - assign hg_h_lock_lockVec_1_held$ENQ = - WILL_FIRE_RL_hg_s_Stage__1_execute && - (IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d244 || - x__h9842 == 2'd1 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265) ; - assign hg_h_lock_lockVec_1_held$DEQ = - WILL_FIRE_RL_hg_s_Stage__2_execute && - hg_h_lock_lockVec_1_held$D_OUT == - IF_hg_fifo_Stage__1_TO_Stage__2_first__83_BIT__ETC___d321 && - IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d333 ; - assign hg_h_lock_lockVec_1_held$CLR = 1'b0 ; - - // submodule hg_h_lock_lockVec_2_held - assign hg_h_lock_lockVec_2_held$D_IN = hg_h_lock_lockVec_2_nextId ; - assign hg_h_lock_lockVec_2_held$ENQ = - WILL_FIRE_RL_hg_s_Stage__1_execute && - (IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d250 || - x__h9842 == 2'd2 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265) ; - assign hg_h_lock_lockVec_2_held$DEQ = - WILL_FIRE_RL_hg_s_Stage__2_execute && - hg_h_lock_lockVec_2_held$D_OUT == - IF_hg_fifo_Stage__1_TO_Stage__2_first__83_BIT__ETC___d321 && - IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d338 ; - assign hg_h_lock_lockVec_2_held$CLR = 1'b0 ; - - // submodule hg_h_lock_lockVec_3_held - assign hg_h_lock_lockVec_3_held$D_IN = hg_h_lock_lockVec_3_nextId ; - assign hg_h_lock_lockVec_3_held$ENQ = - WILL_FIRE_RL_hg_s_Stage__1_execute && - (IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d256 || - x__h9842 == 2'd3 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265) ; - assign hg_h_lock_lockVec_3_held$DEQ = - WILL_FIRE_RL_hg_s_Stage__2_execute && - hg_h_lock_lockVec_3_held$D_OUT == - IF_hg_fifo_Stage__1_TO_Stage__2_first__83_BIT__ETC___d321 && - IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d343 ; - assign hg_h_lock_lockVec_3_held$CLR = 1'b0 ; - - // submodule hg_outputQueue - assign hg_outputQueue$D_IN = { hg_fifo__input__TO_Start$D_OUT[2:0], 1'd1 } ; - assign hg_outputQueue$ENQ = MUX_hg_busyReg$write_1__SEL_1 ; - assign hg_outputQueue$DEQ = EN__inthg_resp ; - assign hg_outputQueue$CLR = 1'b0 ; - - // submodule hg_weight_lock_lockVec_0_held - assign hg_weight_lock_lockVec_0_held$D_IN = 2'h0 ; - assign hg_weight_lock_lockVec_0_held$ENQ = 1'b0 ; - assign hg_weight_lock_lockVec_0_held$DEQ = 1'b0 ; - assign hg_weight_lock_lockVec_0_held$CLR = 1'b0 ; - - // submodule hg_weight_lock_lockVec_1_held - assign hg_weight_lock_lockVec_1_held$D_IN = 2'h0 ; - assign hg_weight_lock_lockVec_1_held$ENQ = 1'b0 ; - assign hg_weight_lock_lockVec_1_held$DEQ = 1'b0 ; - assign hg_weight_lock_lockVec_1_held$CLR = 1'b0 ; - - // submodule hg_weight_lock_lockVec_2_held - assign hg_weight_lock_lockVec_2_held$D_IN = 2'h0 ; - assign hg_weight_lock_lockVec_2_held$ENQ = 1'b0 ; - assign hg_weight_lock_lockVec_2_held$DEQ = 1'b0 ; - assign hg_weight_lock_lockVec_2_held$CLR = 1'b0 ; - - // submodule hg_weight_lock_lockVec_3_held - assign hg_weight_lock_lockVec_3_held$D_IN = 2'h0 ; - assign hg_weight_lock_lockVec_3_held$ENQ = 1'b0 ; - assign hg_weight_lock_lockVec_3_held$DEQ = 1'b0 ; - assign hg_weight_lock_lockVec_3_held$CLR = 1'b0 ; - - // submodule w_rf - assign w_rf$ADDR_1 = hg_fifo__input__TO_Start$D_OUT[12:3] ; - assign w_rf$ADDR_2 = 10'h0 ; - assign w_rf$ADDR_3 = 10'h0 ; - assign w_rf$ADDR_4 = 10'h0 ; - assign w_rf$ADDR_5 = 10'h0 ; - assign w_rf$ADDR_IN = 10'h0 ; - assign w_rf$D_IN = 32'h0 ; - assign w_rf$WE = 1'b0 ; - - // remaining internal signals - assign IF_NOT_hg_feature_lock_entryVec_0_BIT_10_7_OR__ETC___d105 = - ((!hg_feature_lock_entryVec_0[10] || - !hg_feature_lock_entryVec_0_BITS_9_TO_0_4_EQ_hg_ETC___d85) && - hg_feature_lock_entryVec_1[10] && - hg_feature_lock_entryVec_1_BITS_9_TO_0_1_EQ_hg_ETC___d82) ? - 2'd1 : - 2'd0 ; - assign IF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_N_ETC___d198 = - ((!hg_h_lock_entryVec_0[10] || - !hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179) && - hg_h_lock_entryVec_1[10] && - hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176) ? - 2'd1 : - 2'd0 ; - assign IF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_N_ETC___d306 = - ((!hg_h_lock_entryVec_0[10] || - !hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294) && - hg_h_lock_entryVec_1[10] && - hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291) ? - 2'd1 : - 2'd0 ; - assign IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d238 = - x__h8976 == 2'd0 && - (hg_h_lock_entryVec_3[10] && - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170 || - hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d182) ; - assign IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d244 = - x__h8976 == 2'd1 && - (hg_h_lock_entryVec_3[10] && - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170 || - hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d182) ; - assign IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d250 = - x__h8976 == 2'd2 && - (hg_h_lock_entryVec_3[10] && - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170 || - hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d182) ; - assign IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d256 = - x__h8976 == 2'd3 && - (hg_h_lock_entryVec_3[10] && - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170 || - hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d182) ; - assign IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d328 = - x__h10519 == 2'd0 && - (hg_h_lock_entryVec_3[10] && - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285 || - hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d326) ; - assign IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d333 = - x__h10519 == 2'd1 && - (hg_h_lock_entryVec_3[10] && - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285 || - hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d326) ; - assign IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d338 = - x__h10519 == 2'd2 && - (hg_h_lock_entryVec_3[10] && - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285 || - hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d326) ; - assign IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_N_ETC___d343 = - x__h10519 == 2'd3 && - (hg_h_lock_entryVec_3[10] && - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285 || - hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d326) ; - assign IF_NOT_hg_weight_lock_entryVec_0_4_BIT_10_5_38_ETC___d146 = - ((!hg_weight_lock_entryVec_0[10] || - !hg_weight_lock_entryVec_0_4_BITS_9_TO_0_25_EQ__ETC___d126) && - hg_weight_lock_entryVec_1[10] && - hg_weight_lock_entryVec_1_9_BITS_9_TO_0_22_EQ__ETC___d123) ? - 2'd1 : - 2'd0 ; - assign IF_hg_fifo_Stage__1_TO_Stage__2_first__83_BIT__ETC___d321 = - hg_fifo_Stage__1_TO_Stage__2$D_OUT[5] ? - hg_fifo_Stage__1_TO_Stage__2$D_OUT[4:3] : - 2'd0 ; - assign IF_hg_fifo__input__TO_Start_first__3_BITS_12_T_ETC___d70 = - hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 ? - hg_fifo__input__TO_Start$FULL_N && - hg_fifo_Start_TO_Stage__1$FULL_N : - hg_outputQueue$FULL_N ; - assign IF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lo_ETC___d214 = - (hg_h_lock_entryVec_1[10] && hg_h_lock_entryVec_0[10] && - !hg_h_lock_entryVec_2[10]) ? - 2'd2 : - ((hg_h_lock_entryVec_0[10] && !hg_h_lock_entryVec_1[10]) ? - 2'd1 : - 2'd0) ; - assign IF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lo_ETC___d218 = - (hg_h_lock_entryVec_3[10] && - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170 || - hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d182) ? - CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d205 : - hg_h_lock_entryVec_3[10] && hg_h_lock_entryVec_2[10] && - hg_h_lock_entryVec_1[10] && - hg_h_lock_entryVec_0[10] || - CASE_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_ETC___d216 ; - assign IF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lo_ETC___d230 = - (hg_h_lock_entryVec_3[10] && - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170 || - hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d182) ? - SEL_ARR_NOT_hg_h_lock_lockVec_0_held_notEmpty__ETC___d229 : - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226 ; - assign IF_hg_h_lock_entryVec_3_9_BIT_10_0_AND_hg_h_lo_ETC___d277 = - (hg_h_lock_entryVec_3[10] && - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170 || - hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d182) ? - SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d275 : - SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d276 ; - assign NOT_hg_feature_lock_entryVec_1_BIT_10_0_4_OR_N_ETC___d103 = - (!hg_feature_lock_entryVec_1[10] || - !hg_feature_lock_entryVec_1_BITS_9_TO_0_1_EQ_hg_ETC___d82) && - (!hg_feature_lock_entryVec_0[10] || - !hg_feature_lock_entryVec_0_BITS_9_TO_0_4_EQ_hg_ETC___d85) && - hg_feature_lock_entryVec_2[10] && - hg_feature_lock_entryVec_2_4_BITS_9_TO_0_8_EQ__ETC___d79 ; - assign NOT_hg_feature_lock_entryVec_2_4_BIT_10_5_1_OR_ETC___d101 = - (!hg_feature_lock_entryVec_2[10] || - !hg_feature_lock_entryVec_2_4_BITS_9_TO_0_8_EQ__ETC___d79) && - (!hg_feature_lock_entryVec_1[10] || - !hg_feature_lock_entryVec_1_BITS_9_TO_0_1_EQ_hg_ETC___d82) && - (!hg_feature_lock_entryVec_0[10] || - !hg_feature_lock_entryVec_0_BITS_9_TO_0_4_EQ_hg_ETC___d85) ; - assign NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d114 = - !hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 || - ((hg_feature_lock_entryVec_3[10] && - hg_feature_lock_entryVec_3[9:0] == - hg_fifo__input__TO_Start$D_OUT[12:3] || - hg_feature_lock_entryVec_2_4_BIT_10_5_AND_hg_f_ETC___d88) ? - SEL_ARR_NOT_hg_feature_lock_lockVec_0_held_not_ETC___d108 : - !hg_feature_lock_entryVec_3[10] || - !hg_feature_lock_entryVec_2[10] || - !hg_feature_lock_entryVec_1[10] || - !hg_feature_lock_entryVec_0[10]) ; - assign NOT_hg_fifo__input__TO_Start_first__3_BITS_12__ETC___d155 = - !hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 || - ((hg_weight_lock_entryVec_3[10] && - hg_weight_lock_entryVec_3[9:0] == - hg_fifo__input__TO_Start$D_OUT[12:3] || - hg_weight_lock_entryVec_2_4_BIT_10_5_AND_hg_we_ETC___d129) ? - SEL_ARR_NOT_hg_weight_lock_lockVec_0_held_notE_ETC___d149 : - !hg_weight_lock_entryVec_3[10] || - !hg_weight_lock_entryVec_2[10] || - !hg_weight_lock_entryVec_1[10] || - !hg_weight_lock_entryVec_0[10]) ; - assign NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d196 = - (!hg_h_lock_entryVec_1[10] || - !hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176) && - (!hg_h_lock_entryVec_0[10] || - !hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179) && - hg_h_lock_entryVec_2[10] && - hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173 ; - assign NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d303 = - (!hg_h_lock_entryVec_1[10] || - !hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291) && - (!hg_h_lock_entryVec_0[10] || - !hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294) && - hg_h_lock_entryVec_2[10] && - hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288 ; - assign NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194 = - (!hg_h_lock_entryVec_2[10] || - !hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173) && - (!hg_h_lock_entryVec_1[10] || - !hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176) && - (!hg_h_lock_entryVec_0[10] || - !hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179) ; - assign NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298 = - (!hg_h_lock_entryVec_2[10] || - !hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288) && - (!hg_h_lock_entryVec_1[10] || - !hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291) && - (!hg_h_lock_entryVec_0[10] || - !hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294) ; - assign NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226 = - !hg_h_lock_entryVec_3[10] || !hg_h_lock_entryVec_2[10] || - !hg_h_lock_entryVec_1[10] || - !hg_h_lock_entryVec_0[10] ; - assign NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d265 = - (!hg_h_lock_entryVec_3[10] || - !hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170) && - NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194 && - NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d226 ; - assign NOT_hg_h_lock_entryVec_3_9_BIT_10_0_09_OR_NOT__ETC___d314 = - (!hg_h_lock_entryVec_3[10] || - !hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285) && - NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298 || - CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d313 ; - assign NOT_hg_weight_lock_entryVec_1_9_BIT_10_0_35_OR_ETC___d144 = - (!hg_weight_lock_entryVec_1[10] || - !hg_weight_lock_entryVec_1_9_BITS_9_TO_0_22_EQ__ETC___d123) && - (!hg_weight_lock_entryVec_0[10] || - !hg_weight_lock_entryVec_0_4_BITS_9_TO_0_25_EQ__ETC___d126) && - hg_weight_lock_entryVec_2[10] && - hg_weight_lock_entryVec_2_4_BITS_9_TO_0_19_EQ__ETC___d120 ; - assign NOT_hg_weight_lock_entryVec_2_4_BIT_10_5_32_OR_ETC___d142 = - (!hg_weight_lock_entryVec_2[10] || - !hg_weight_lock_entryVec_2_4_BITS_9_TO_0_19_EQ__ETC___d120) && - (!hg_weight_lock_entryVec_1[10] || - !hg_weight_lock_entryVec_1_9_BITS_9_TO_0_22_EQ__ETC___d123) && - (!hg_weight_lock_entryVec_0[10] || - !hg_weight_lock_entryVec_0_4_BITS_9_TO_0_25_EQ__ETC___d126) ; - assign h_rf_sub_hg_fifo_Start_TO_Stage__1_first__68_B_ETC___d235 = - h_rf$D_OUT_1 + hg_fifo_Start_TO_Stage__1$D_OUT[34:3] ; - assign hg_feature_lock_entryVec_0_BITS_9_TO_0_4_EQ_hg_ETC___d85 = - hg_feature_lock_entryVec_0[9:0] == - hg_fifo__input__TO_Start$D_OUT[12:3] ; - assign hg_feature_lock_entryVec_1_BITS_9_TO_0_1_EQ_hg_ETC___d82 = - hg_feature_lock_entryVec_1[9:0] == - hg_fifo__input__TO_Start$D_OUT[12:3] ; - assign hg_feature_lock_entryVec_2_4_BITS_9_TO_0_8_EQ__ETC___d79 = - hg_feature_lock_entryVec_2[9:0] == - hg_fifo__input__TO_Start$D_OUT[12:3] ; - assign hg_feature_lock_entryVec_2_4_BIT_10_5_AND_hg_f_ETC___d88 = - hg_feature_lock_entryVec_2[10] && - hg_feature_lock_entryVec_2_4_BITS_9_TO_0_8_EQ__ETC___d79 || - hg_feature_lock_entryVec_1[10] && - hg_feature_lock_entryVec_1_BITS_9_TO_0_1_EQ_hg_ETC___d82 || - hg_feature_lock_entryVec_0[10] && - hg_feature_lock_entryVec_0_BITS_9_TO_0_4_EQ_hg_ETC___d85 ; - assign hg_fifo__input__TO_Start_first__3_BITS_12_TO_3_ETC___d65 = - hg_fifo__input__TO_Start$D_OUT[12:3] < 10'd1000 ; - assign hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179 = - hg_h_lock_entryVec_0[9:0] == - hg_fifo_Start_TO_Stage__1$D_OUT[44:35] ; - assign hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294 = - hg_h_lock_entryVec_0[9:0] == - hg_fifo_Stage__1_TO_Stage__2$D_OUT[47:38] ; - assign hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176 = - hg_h_lock_entryVec_1[9:0] == - hg_fifo_Start_TO_Stage__1$D_OUT[44:35] ; - assign hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291 = - hg_h_lock_entryVec_1[9:0] == - hg_fifo_Stage__1_TO_Stage__2$D_OUT[47:38] ; - assign hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173 = - hg_h_lock_entryVec_2[9:0] == - hg_fifo_Start_TO_Stage__1$D_OUT[44:35] ; - assign hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288 = - hg_h_lock_entryVec_2[9:0] == - hg_fifo_Stage__1_TO_Stage__2$D_OUT[47:38] ; - assign hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d182 = - hg_h_lock_entryVec_2[10] && - hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d173 || - hg_h_lock_entryVec_1[10] && - hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d176 || - hg_h_lock_entryVec_0[10] && - hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d179 ; - assign hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_h_lock__ETC___d326 = - hg_h_lock_entryVec_2[10] && - hg_h_lock_entryVec_2_4_BITS_9_TO_0_72_EQ_hg_fi_ETC___d288 || - hg_h_lock_entryVec_1[10] && - hg_h_lock_entryVec_1_9_BITS_9_TO_0_75_EQ_hg_fi_ETC___d291 || - hg_h_lock_entryVec_0[10] && - hg_h_lock_entryVec_0_4_BITS_9_TO_0_78_EQ_hg_fi_ETC___d294 ; - assign hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170 = - hg_h_lock_entryVec_3[9:0] == - hg_fifo_Start_TO_Stage__1$D_OUT[44:35] ; - assign hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285 = - hg_h_lock_entryVec_3[9:0] == - hg_fifo_Stage__1_TO_Stage__2$D_OUT[47:38] ; - assign hg_weight_lock_entryVec_0_4_BITS_9_TO_0_25_EQ__ETC___d126 = - hg_weight_lock_entryVec_0[9:0] == - hg_fifo__input__TO_Start$D_OUT[12:3] ; - assign hg_weight_lock_entryVec_1_9_BITS_9_TO_0_22_EQ__ETC___d123 = - hg_weight_lock_entryVec_1[9:0] == - hg_fifo__input__TO_Start$D_OUT[12:3] ; - assign hg_weight_lock_entryVec_2_4_BITS_9_TO_0_19_EQ__ETC___d120 = - hg_weight_lock_entryVec_2[9:0] == - hg_fifo__input__TO_Start$D_OUT[12:3] ; - assign hg_weight_lock_entryVec_2_4_BIT_10_5_AND_hg_we_ETC___d129 = - hg_weight_lock_entryVec_2[10] && - hg_weight_lock_entryVec_2_4_BITS_9_TO_0_19_EQ__ETC___d120 || - hg_weight_lock_entryVec_1[10] && - hg_weight_lock_entryVec_1_9_BITS_9_TO_0_22_EQ__ETC___d123 || - hg_weight_lock_entryVec_0[10] && - hg_weight_lock_entryVec_0_4_BITS_9_TO_0_25_EQ__ETC___d126 ; - assign x__h10519 = - (NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d298 && - hg_h_lock_entryVec_3[10] && - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d285) ? - 2'd3 : - (NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d303 ? - 2'd2 : - IF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_N_ETC___d306) ; - assign x__h7468 = - (NOT_hg_feature_lock_entryVec_2_4_BIT_10_5_1_OR_ETC___d101 && - hg_feature_lock_entryVec_3[10] && - hg_feature_lock_entryVec_3[9:0] == - hg_fifo__input__TO_Start$D_OUT[12:3]) ? - 2'd3 : - (NOT_hg_feature_lock_entryVec_1_BIT_10_0_4_OR_N_ETC___d103 ? - 2'd2 : - IF_NOT_hg_feature_lock_entryVec_0_BIT_10_7_OR__ETC___d105) ; - assign x__h7932 = - (NOT_hg_weight_lock_entryVec_2_4_BIT_10_5_32_OR_ETC___d142 && - hg_weight_lock_entryVec_3[10] && - hg_weight_lock_entryVec_3[9:0] == - hg_fifo__input__TO_Start$D_OUT[12:3]) ? - 2'd3 : - (NOT_hg_weight_lock_entryVec_1_9_BIT_10_0_35_OR_ETC___d144 ? - 2'd2 : - IF_NOT_hg_weight_lock_entryVec_0_4_BIT_10_5_38_ETC___d146) ; - assign x__h8976 = - (NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_OR_NOT__ETC___d194 && - hg_h_lock_entryVec_3[10] && - hg_h_lock_entryVec_3_9_BITS_9_TO_0_67_EQ_hg_fi_ETC___d170) ? - 2'd3 : - (NOT_hg_h_lock_entryVec_1_9_BIT_10_0_87_OR_NOT__ETC___d196 ? - 2'd2 : - IF_NOT_hg_h_lock_entryVec_0_4_BIT_10_5_90_OR_N_ETC___d198) ; - assign x__h9842 = - (hg_h_lock_entryVec_2[10] && hg_h_lock_entryVec_1[10] && - hg_h_lock_entryVec_0[10] && - !hg_h_lock_entryVec_3[10]) ? - 2'd3 : - IF_hg_h_lock_entryVec_1_9_BIT_10_0_AND_hg_h_lo_ETC___d214 ; - always@(x__h7932 or - hg_weight_lock_lockVec_0_held$EMPTY_N or - hg_weight_lock_lockVec_1_held$EMPTY_N or - hg_weight_lock_lockVec_2_held$EMPTY_N or - hg_weight_lock_lockVec_3_held$EMPTY_N) - begin - case (x__h7932) - 2'd0: - SEL_ARR_NOT_hg_weight_lock_lockVec_0_held_notE_ETC___d149 = - !hg_weight_lock_lockVec_0_held$EMPTY_N; - 2'd1: - SEL_ARR_NOT_hg_weight_lock_lockVec_0_held_notE_ETC___d149 = - !hg_weight_lock_lockVec_1_held$EMPTY_N; - 2'd2: - SEL_ARR_NOT_hg_weight_lock_lockVec_0_held_notE_ETC___d149 = - !hg_weight_lock_lockVec_2_held$EMPTY_N; - 2'd3: - SEL_ARR_NOT_hg_weight_lock_lockVec_0_held_notE_ETC___d149 = - !hg_weight_lock_lockVec_3_held$EMPTY_N; - endcase - end - always@(x__h7468 or - hg_feature_lock_lockVec_0_held$EMPTY_N or - hg_feature_lock_lockVec_1_held$EMPTY_N or - hg_feature_lock_lockVec_2_held$EMPTY_N or - hg_feature_lock_lockVec_3_held$EMPTY_N) - begin - case (x__h7468) - 2'd0: - SEL_ARR_NOT_hg_feature_lock_lockVec_0_held_not_ETC___d108 = - !hg_feature_lock_lockVec_0_held$EMPTY_N; - 2'd1: - SEL_ARR_NOT_hg_feature_lock_lockVec_0_held_not_ETC___d108 = - !hg_feature_lock_lockVec_1_held$EMPTY_N; - 2'd2: - SEL_ARR_NOT_hg_feature_lock_lockVec_0_held_not_ETC___d108 = - !hg_feature_lock_lockVec_2_held$EMPTY_N; - 2'd3: - SEL_ARR_NOT_hg_feature_lock_lockVec_0_held_not_ETC___d108 = - !hg_feature_lock_lockVec_3_held$EMPTY_N; - endcase - end - always@(x__h8976 or - hg_h_lock_lockVec_0_held$EMPTY_N or - hg_h_lock_lockVec_1_held$EMPTY_N or - hg_h_lock_lockVec_2_held$EMPTY_N or - hg_h_lock_lockVec_3_held$EMPTY_N) - begin - case (x__h8976) - 2'd0: - SEL_ARR_NOT_hg_h_lock_lockVec_0_held_notEmpty__ETC___d229 = - !hg_h_lock_lockVec_0_held$EMPTY_N; - 2'd1: - SEL_ARR_NOT_hg_h_lock_lockVec_0_held_notEmpty__ETC___d229 = - !hg_h_lock_lockVec_1_held$EMPTY_N; - 2'd2: - SEL_ARR_NOT_hg_h_lock_lockVec_0_held_notEmpty__ETC___d229 = - !hg_h_lock_lockVec_2_held$EMPTY_N; - 2'd3: - SEL_ARR_NOT_hg_h_lock_lockVec_0_held_notEmpty__ETC___d229 = - !hg_h_lock_lockVec_3_held$EMPTY_N; - endcase - end - always@(x__h8976 or - hg_h_lock_lockVec_0_held$FULL_N or - hg_h_lock_lockVec_1_held$FULL_N or - hg_h_lock_lockVec_2_held$FULL_N or hg_h_lock_lockVec_3_held$FULL_N) - begin - case (x__h8976) - 2'd0: - CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d205 = - hg_h_lock_lockVec_0_held$FULL_N; - 2'd1: - CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d205 = - hg_h_lock_lockVec_1_held$FULL_N; - 2'd2: - CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d205 = - hg_h_lock_lockVec_2_held$FULL_N; - 2'd3: - CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d205 = - hg_h_lock_lockVec_3_held$FULL_N; - endcase - end - always@(x__h9842 or - hg_h_lock_lockVec_0_held$FULL_N or - hg_h_lock_lockVec_1_held$FULL_N or - hg_h_lock_lockVec_2_held$FULL_N or hg_h_lock_lockVec_3_held$FULL_N) - begin - case (x__h9842) - 2'd0: - CASE_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_ETC___d216 = - hg_h_lock_lockVec_0_held$FULL_N; - 2'd1: - CASE_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_ETC___d216 = - hg_h_lock_lockVec_1_held$FULL_N; - 2'd2: - CASE_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_ETC___d216 = - hg_h_lock_lockVec_2_held$FULL_N; - 2'd3: - CASE_IF_hg_h_lock_entryVec_2_4_BIT_10_5_AND_hg_ETC___d216 = - hg_h_lock_lockVec_3_held$FULL_N; - endcase - end - always@(x__h10519 or - hg_h_lock_lockVec_0_held$EMPTY_N or - hg_h_lock_lockVec_1_held$EMPTY_N or - hg_h_lock_lockVec_2_held$EMPTY_N or - hg_h_lock_lockVec_3_held$EMPTY_N) - begin - case (x__h10519) - 2'd0: - CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d313 = - hg_h_lock_lockVec_0_held$EMPTY_N; - 2'd1: - CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d313 = - hg_h_lock_lockVec_1_held$EMPTY_N; - 2'd2: - CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d313 = - hg_h_lock_lockVec_2_held$EMPTY_N; - 2'd3: - CASE_IF_NOT_hg_h_lock_entryVec_2_4_BIT_10_5_84_ETC___d313 = - hg_h_lock_lockVec_3_held$EMPTY_N; - endcase - end - always@(x__h8976 or - hg_h_lock_lockVec_0_nextId or - hg_h_lock_lockVec_1_nextId or - hg_h_lock_lockVec_2_nextId or hg_h_lock_lockVec_3_nextId) - begin - case (x__h8976) - 2'd0: - SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d275 = - hg_h_lock_lockVec_0_nextId; - 2'd1: - SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d275 = - hg_h_lock_lockVec_1_nextId; - 2'd2: - SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d275 = - hg_h_lock_lockVec_2_nextId; - 2'd3: - SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d275 = - hg_h_lock_lockVec_3_nextId; - endcase - end - always@(x__h9842 or - hg_h_lock_lockVec_0_nextId or - hg_h_lock_lockVec_1_nextId or - hg_h_lock_lockVec_2_nextId or hg_h_lock_lockVec_3_nextId) - begin - case (x__h9842) - 2'd0: - SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d276 = - hg_h_lock_lockVec_0_nextId; - 2'd1: - SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d276 = - hg_h_lock_lockVec_1_nextId; - 2'd2: - SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d276 = - hg_h_lock_lockVec_2_nextId; - 2'd3: - SEL_ARR_hg_h_lock_lockVec_0_nextId_39_hg_h_loc_ETC___d276 = - hg_h_lock_lockVec_3_nextId; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - hg <= `BSV_ASSIGNMENT_DELAY 3'd0; - hg_busyReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - hg_feature_lock_entryVec_0 <= `BSV_ASSIGNMENT_DELAY 11'd682; - hg_feature_lock_entryVec_1 <= `BSV_ASSIGNMENT_DELAY 11'd682; - hg_feature_lock_entryVec_2 <= `BSV_ASSIGNMENT_DELAY 11'd682; - hg_feature_lock_entryVec_3 <= `BSV_ASSIGNMENT_DELAY 11'd682; - hg_feature_lock_lockVec_0_cnt <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_feature_lock_lockVec_0_nextId <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_feature_lock_lockVec_1_cnt <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_feature_lock_lockVec_1_nextId <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_feature_lock_lockVec_2_cnt <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_feature_lock_lockVec_2_nextId <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_feature_lock_lockVec_3_cnt <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_feature_lock_lockVec_3_nextId <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_feature_lock_region <= `BSV_ASSIGNMENT_DELAY 1'd1; - hg_h_lock_entryVec_0 <= `BSV_ASSIGNMENT_DELAY 11'd682; - hg_h_lock_entryVec_1 <= `BSV_ASSIGNMENT_DELAY 11'd682; - hg_h_lock_entryVec_2 <= `BSV_ASSIGNMENT_DELAY 11'd682; - hg_h_lock_entryVec_3 <= `BSV_ASSIGNMENT_DELAY 11'd682; - hg_h_lock_lockVec_0_cnt <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_h_lock_lockVec_0_nextId <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_h_lock_lockVec_1_cnt <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_h_lock_lockVec_1_nextId <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_h_lock_lockVec_2_cnt <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_h_lock_lockVec_2_nextId <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_h_lock_lockVec_3_cnt <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_h_lock_lockVec_3_nextId <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_h_lock_region <= `BSV_ASSIGNMENT_DELAY 1'd1; - hg_weight_lock_entryVec_0 <= `BSV_ASSIGNMENT_DELAY 11'd682; - hg_weight_lock_entryVec_1 <= `BSV_ASSIGNMENT_DELAY 11'd682; - hg_weight_lock_entryVec_2 <= `BSV_ASSIGNMENT_DELAY 11'd682; - hg_weight_lock_entryVec_3 <= `BSV_ASSIGNMENT_DELAY 11'd682; - hg_weight_lock_lockVec_0_cnt <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_weight_lock_lockVec_0_nextId <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_weight_lock_lockVec_1_cnt <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_weight_lock_lockVec_1_nextId <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_weight_lock_lockVec_2_cnt <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_weight_lock_lockVec_2_nextId <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_weight_lock_lockVec_3_cnt <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_weight_lock_lockVec_3_nextId <= `BSV_ASSIGNMENT_DELAY 2'd0; - hg_weight_lock_region <= `BSV_ASSIGNMENT_DELAY 1'd1; - end - else - begin - if (hg$EN) hg <= `BSV_ASSIGNMENT_DELAY hg$D_IN; - if (hg_busyReg$EN) - hg_busyReg <= `BSV_ASSIGNMENT_DELAY hg_busyReg$D_IN; - if (hg_feature_lock_entryVec_0$EN) - hg_feature_lock_entryVec_0 <= `BSV_ASSIGNMENT_DELAY - hg_feature_lock_entryVec_0$D_IN; - if (hg_feature_lock_entryVec_1$EN) - hg_feature_lock_entryVec_1 <= `BSV_ASSIGNMENT_DELAY - hg_feature_lock_entryVec_1$D_IN; - if (hg_feature_lock_entryVec_2$EN) - hg_feature_lock_entryVec_2 <= `BSV_ASSIGNMENT_DELAY - hg_feature_lock_entryVec_2$D_IN; - if (hg_feature_lock_entryVec_3$EN) - hg_feature_lock_entryVec_3 <= `BSV_ASSIGNMENT_DELAY - hg_feature_lock_entryVec_3$D_IN; - if (hg_feature_lock_lockVec_0_cnt$EN) - hg_feature_lock_lockVec_0_cnt <= `BSV_ASSIGNMENT_DELAY - hg_feature_lock_lockVec_0_cnt$D_IN; - if (hg_feature_lock_lockVec_0_nextId$EN) - hg_feature_lock_lockVec_0_nextId <= `BSV_ASSIGNMENT_DELAY - hg_feature_lock_lockVec_0_nextId$D_IN; - if (hg_feature_lock_lockVec_1_cnt$EN) - hg_feature_lock_lockVec_1_cnt <= `BSV_ASSIGNMENT_DELAY - hg_feature_lock_lockVec_1_cnt$D_IN; - if (hg_feature_lock_lockVec_1_nextId$EN) - hg_feature_lock_lockVec_1_nextId <= `BSV_ASSIGNMENT_DELAY - hg_feature_lock_lockVec_1_nextId$D_IN; - if (hg_feature_lock_lockVec_2_cnt$EN) - hg_feature_lock_lockVec_2_cnt <= `BSV_ASSIGNMENT_DELAY - hg_feature_lock_lockVec_2_cnt$D_IN; - if (hg_feature_lock_lockVec_2_nextId$EN) - hg_feature_lock_lockVec_2_nextId <= `BSV_ASSIGNMENT_DELAY - hg_feature_lock_lockVec_2_nextId$D_IN; - if (hg_feature_lock_lockVec_3_cnt$EN) - hg_feature_lock_lockVec_3_cnt <= `BSV_ASSIGNMENT_DELAY - hg_feature_lock_lockVec_3_cnt$D_IN; - if (hg_feature_lock_lockVec_3_nextId$EN) - hg_feature_lock_lockVec_3_nextId <= `BSV_ASSIGNMENT_DELAY - hg_feature_lock_lockVec_3_nextId$D_IN; - if (hg_feature_lock_region$EN) - hg_feature_lock_region <= `BSV_ASSIGNMENT_DELAY - hg_feature_lock_region$D_IN; - if (hg_h_lock_entryVec_0$EN) - hg_h_lock_entryVec_0 <= `BSV_ASSIGNMENT_DELAY - hg_h_lock_entryVec_0$D_IN; - if (hg_h_lock_entryVec_1$EN) - hg_h_lock_entryVec_1 <= `BSV_ASSIGNMENT_DELAY - hg_h_lock_entryVec_1$D_IN; - if (hg_h_lock_entryVec_2$EN) - hg_h_lock_entryVec_2 <= `BSV_ASSIGNMENT_DELAY - hg_h_lock_entryVec_2$D_IN; - if (hg_h_lock_entryVec_3$EN) - hg_h_lock_entryVec_3 <= `BSV_ASSIGNMENT_DELAY - hg_h_lock_entryVec_3$D_IN; - if (hg_h_lock_lockVec_0_cnt$EN) - hg_h_lock_lockVec_0_cnt <= `BSV_ASSIGNMENT_DELAY - hg_h_lock_lockVec_0_cnt$D_IN; - if (hg_h_lock_lockVec_0_nextId$EN) - hg_h_lock_lockVec_0_nextId <= `BSV_ASSIGNMENT_DELAY - hg_h_lock_lockVec_0_nextId$D_IN; - if (hg_h_lock_lockVec_1_cnt$EN) - hg_h_lock_lockVec_1_cnt <= `BSV_ASSIGNMENT_DELAY - hg_h_lock_lockVec_1_cnt$D_IN; - if (hg_h_lock_lockVec_1_nextId$EN) - hg_h_lock_lockVec_1_nextId <= `BSV_ASSIGNMENT_DELAY - hg_h_lock_lockVec_1_nextId$D_IN; - if (hg_h_lock_lockVec_2_cnt$EN) - hg_h_lock_lockVec_2_cnt <= `BSV_ASSIGNMENT_DELAY - hg_h_lock_lockVec_2_cnt$D_IN; - if (hg_h_lock_lockVec_2_nextId$EN) - hg_h_lock_lockVec_2_nextId <= `BSV_ASSIGNMENT_DELAY - hg_h_lock_lockVec_2_nextId$D_IN; - if (hg_h_lock_lockVec_3_cnt$EN) - hg_h_lock_lockVec_3_cnt <= `BSV_ASSIGNMENT_DELAY - hg_h_lock_lockVec_3_cnt$D_IN; - if (hg_h_lock_lockVec_3_nextId$EN) - hg_h_lock_lockVec_3_nextId <= `BSV_ASSIGNMENT_DELAY - hg_h_lock_lockVec_3_nextId$D_IN; - if (hg_h_lock_region$EN) - hg_h_lock_region <= `BSV_ASSIGNMENT_DELAY hg_h_lock_region$D_IN; - if (hg_weight_lock_entryVec_0$EN) - hg_weight_lock_entryVec_0 <= `BSV_ASSIGNMENT_DELAY - hg_weight_lock_entryVec_0$D_IN; - if (hg_weight_lock_entryVec_1$EN) - hg_weight_lock_entryVec_1 <= `BSV_ASSIGNMENT_DELAY - hg_weight_lock_entryVec_1$D_IN; - if (hg_weight_lock_entryVec_2$EN) - hg_weight_lock_entryVec_2 <= `BSV_ASSIGNMENT_DELAY - hg_weight_lock_entryVec_2$D_IN; - if (hg_weight_lock_entryVec_3$EN) - hg_weight_lock_entryVec_3 <= `BSV_ASSIGNMENT_DELAY - hg_weight_lock_entryVec_3$D_IN; - if (hg_weight_lock_lockVec_0_cnt$EN) - hg_weight_lock_lockVec_0_cnt <= `BSV_ASSIGNMENT_DELAY - hg_weight_lock_lockVec_0_cnt$D_IN; - if (hg_weight_lock_lockVec_0_nextId$EN) - hg_weight_lock_lockVec_0_nextId <= `BSV_ASSIGNMENT_DELAY - hg_weight_lock_lockVec_0_nextId$D_IN; - if (hg_weight_lock_lockVec_1_cnt$EN) - hg_weight_lock_lockVec_1_cnt <= `BSV_ASSIGNMENT_DELAY - hg_weight_lock_lockVec_1_cnt$D_IN; - if (hg_weight_lock_lockVec_1_nextId$EN) - hg_weight_lock_lockVec_1_nextId <= `BSV_ASSIGNMENT_DELAY - hg_weight_lock_lockVec_1_nextId$D_IN; - if (hg_weight_lock_lockVec_2_cnt$EN) - hg_weight_lock_lockVec_2_cnt <= `BSV_ASSIGNMENT_DELAY - hg_weight_lock_lockVec_2_cnt$D_IN; - if (hg_weight_lock_lockVec_2_nextId$EN) - hg_weight_lock_lockVec_2_nextId <= `BSV_ASSIGNMENT_DELAY - hg_weight_lock_lockVec_2_nextId$D_IN; - if (hg_weight_lock_lockVec_3_cnt$EN) - hg_weight_lock_lockVec_3_cnt <= `BSV_ASSIGNMENT_DELAY - hg_weight_lock_lockVec_3_cnt$D_IN; - if (hg_weight_lock_lockVec_3_nextId$EN) - hg_weight_lock_lockVec_3_nextId <= `BSV_ASSIGNMENT_DELAY - hg_weight_lock_lockVec_3_nextId$D_IN; - if (hg_weight_lock_region$EN) - hg_weight_lock_region <= `BSV_ASSIGNMENT_DELAY - hg_weight_lock_region$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - hg = 3'h2; - hg_busyReg = 1'h0; - hg_feature_lock_entryVec_0 = 11'h2AA; - hg_feature_lock_entryVec_1 = 11'h2AA; - hg_feature_lock_entryVec_2 = 11'h2AA; - hg_feature_lock_entryVec_3 = 11'h2AA; - hg_feature_lock_lockVec_0_cnt = 2'h2; - hg_feature_lock_lockVec_0_nextId = 2'h2; - hg_feature_lock_lockVec_1_cnt = 2'h2; - hg_feature_lock_lockVec_1_nextId = 2'h2; - hg_feature_lock_lockVec_2_cnt = 2'h2; - hg_feature_lock_lockVec_2_nextId = 2'h2; - hg_feature_lock_lockVec_3_cnt = 2'h2; - hg_feature_lock_lockVec_3_nextId = 2'h2; - hg_feature_lock_region = 1'h0; - hg_h_lock_entryVec_0 = 11'h2AA; - hg_h_lock_entryVec_1 = 11'h2AA; - hg_h_lock_entryVec_2 = 11'h2AA; - hg_h_lock_entryVec_3 = 11'h2AA; - hg_h_lock_lockVec_0_cnt = 2'h2; - hg_h_lock_lockVec_0_nextId = 2'h2; - hg_h_lock_lockVec_1_cnt = 2'h2; - hg_h_lock_lockVec_1_nextId = 2'h2; - hg_h_lock_lockVec_2_cnt = 2'h2; - hg_h_lock_lockVec_2_nextId = 2'h2; - hg_h_lock_lockVec_3_cnt = 2'h2; - hg_h_lock_lockVec_3_nextId = 2'h2; - hg_h_lock_region = 1'h0; - hg_weight_lock_entryVec_0 = 11'h2AA; - hg_weight_lock_entryVec_1 = 11'h2AA; - hg_weight_lock_entryVec_2 = 11'h2AA; - hg_weight_lock_entryVec_3 = 11'h2AA; - hg_weight_lock_lockVec_0_cnt = 2'h2; - hg_weight_lock_lockVec_0_nextId = 2'h2; - hg_weight_lock_lockVec_1_cnt = 2'h2; - hg_weight_lock_lockVec_1_nextId = 2'h2; - hg_weight_lock_lockVec_2_cnt = 2'h2; - hg_weight_lock_lockVec_2_nextId = 2'h2; - hg_weight_lock_lockVec_3_cnt = 2'h2; - hg_weight_lock_lockVec_3_nextId = 2'h2; - hg_weight_lock_region = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_hg_s_Stage__1_execute) - $display($unsigned(h_rf_sub_hg_fifo_Start_TO_Stage__1_first__68_B_ETC___d235)); - end - // synopsys translate_on -endmodule // mkCircuit - diff --git a/src/main/scala/pipedsl/testOutputs/Circuit_verilog/mkTB.v b/src/main/scala/pipedsl/testOutputs/Circuit_verilog/mkTB.v deleted file mode 100644 index 1d1c028e..00000000 --- a/src/main/scala/pipedsl/testOutputs/Circuit_verilog/mkTB.v +++ /dev/null @@ -1,118 +0,0 @@ -// -// Generated by Bluespec Compiler -// -// -// Ports: -// Name I/O size props -// CLK I 1 clock -// RST_N I 1 reset -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTB(CLK, - RST_N); - input CLK; - input RST_N; - - // register reg_unused_0 - reg [2 : 0] reg_unused_0; - wire [2 : 0] reg_unused_0$D_IN; - wire reg_unused_0$EN; - - // register started - reg started; - wire started$D_IN, started$EN; - - // ports of submodule m - wire [9 : 0] m$_inthg_req_counter; - wire [2 : 0] m$_inthg_checkHandle_handle, m$_inthg_req; - wire m$EN__inthg_req, - m$EN__inthg_resp, - m$RDY__inthg_checkHandle, - m$RDY__inthg_req, - m$_inthg_checkHandle; - - // submodule m - mkCircuit m(.CLK(CLK), - .RST_N(RST_N), - ._inthg_checkHandle_handle(m$_inthg_checkHandle_handle), - ._inthg_req_counter(m$_inthg_req_counter), - .EN__inthg_req(m$EN__inthg_req), - .EN__inthg_resp(m$EN__inthg_resp), - ._inthg_req(m$_inthg_req), - .RDY__inthg_req(m$RDY__inthg_req), - .RDY__inthg_resp(), - ._inthg_checkHandle(m$_inthg_checkHandle), - .RDY__inthg_checkHandle(m$RDY__inthg_checkHandle), - ._inthg_peek(), - .RDY__inthg_peek()); - - // register reg_unused_0 - assign reg_unused_0$D_IN = m$_inthg_req ; - assign reg_unused_0$EN = m$RDY__inthg_req && !started ; - - // register started - assign started$D_IN = 1'd1 ; - assign started$EN = m$RDY__inthg_req && !started ; - - // submodule m - assign m$_inthg_checkHandle_handle = reg_unused_0 ; - assign m$_inthg_req_counter = 10'd0 ; - assign m$EN__inthg_req = m$RDY__inthg_req && !started ; - assign m$EN__inthg_resp = 1'b0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - reg_unused_0 <= `BSV_ASSIGNMENT_DELAY 3'd0; - started <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (reg_unused_0$EN) - reg_unused_0 <= `BSV_ASSIGNMENT_DELAY reg_unused_0$D_IN; - if (started$EN) started <= `BSV_ASSIGNMENT_DELAY started$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - reg_unused_0 = 3'h2; - started = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (m$RDY__inthg_checkHandle && m$_inthg_checkHandle) $finish(32'd1); - end - // synopsys translate_on -endmodule // mkTB - diff --git a/src/main/scala/pipedsl/testOutputs/Cpu.bsv b/src/main/scala/pipedsl/testOutputs/Cpu.bsv deleted file mode 100644 index 24762506..00000000 --- a/src/main/scala/pipedsl/testOutputs/Cpu.bsv +++ /dev/null @@ -1,258 +0,0 @@ -import FIFOF :: *; -import Locks :: *; -import Memories :: *; -import Functions :: *; -import Multi_stg_mul :: *; -import Multi_stg_div :: *; - -export Cpu (..); -export mkCpu ; - -typedef struct { UInt#(16) pc; UInt#(4) _threadID ; } E__input__TO_Start deriving( Bits,Eq ); -typedef struct { Bool __condStage__16; UInt#(4) _threadID ; } E_Stage__5_TO_Stage__15 deriving( Bits,Eq ); -typedef struct { UInt#(2) _request_2; UInt#(5) rd; Maybe#( LockId#(4) ) _lock_id_rf_rd; UInt#(4) _threadID ; } E_Stage__5_TO_Stage__10 deriving( Bits,Eq ); -typedef struct { UInt#(32) res; UInt#(5) rd; Maybe#( LockId#(4) ) _lock_id_rf_rd; UInt#(4) _threadID ; } E_Stage__7_TO_Stage__15 deriving( Bits,Eq ); -typedef struct { UInt#(2) op; UInt#(32) rf2; UInt#(32) rf1; Maybe#( LockId#(4) ) _lock_id_rf_rd; UInt#(5) rd; UInt#(4) _threadID ; } E_Stage__4_TO_Stage__5 deriving( Bits,Eq ); -typedef struct { UInt#(32) res; UInt#(5) rd; Maybe#( LockId#(4) ) _lock_id_rf_rd; UInt#(4) _threadID ; } E_Stage__10_TO_Stage__13 deriving( Bits,Eq ); -typedef struct { UInt#(32) res; UInt#(5) rd; Maybe#( LockId#(4) ) _lock_id_rf_rd; UInt#(4) _threadID ; } E_Stage__12_TO_Stage__13 deriving( Bits,Eq ); -typedef struct { MemId#(8) _request_1; UInt#(4) _threadID ; } E_Start_TO_Stage__4 deriving( Bits,Eq ); -typedef struct { UInt#(1) _request_3; UInt#(5) rd; Maybe#( LockId#(4) ) _lock_id_rf_rd; UInt#(4) _threadID ; } E_Stage__5_TO_Stage__12 deriving( Bits,Eq ); -typedef struct { UInt#(4) _threadID ; } E_Stage__15_TO_Stage__17 deriving( Bits,Eq ); -typedef struct { UInt#(32) rf2; UInt#(32) rf1; Maybe#( LockId#(4) ) _lock_id_rf_rd; UInt#(5) rd; UInt#(4) _threadID ; } E_Stage__5_TO_Stage__7 deriving( Bits,Eq ); -typedef struct { UInt#(32) res; UInt#(5) rd; Maybe#( LockId#(4) ) _lock_id_rf_rd; UInt#(4) _threadID ; } E_Stage__13_TO_Stage__15 deriving( Bits,Eq ); -typedef struct { Bool __condStage__14; UInt#(4) _threadID ; } E_Stage__5_TO_Stage__13 deriving( Bits,Eq ); -typedef struct { UInt#(4) handle ; } OutputQueueInfo deriving( Bits,Eq ); - -interface Cpu; - method ActionValue#(UInt#(4)) req ( UInt#(16) pc ) ; - method Action resp ( ) ; - method Bool checkHandle ( UInt#(4) handle ) ; -endinterface - - -module mkCpu ( CombMem#( UInt#(32), UInt#(5) ) rf, AsyncMem#( UInt#(32), UInt#(16), MemId#(8) ) imem, Multi_stg_mul m, Multi_stg_div f, Cpu _unused_ ); - FIFOF#( E_Stage__5_TO_Stage__15 ) fifo_Stage__5_TO_Stage__15 <- mkFIFOF ( ); - FIFOF#( E_Stage__5_TO_Stage__10 ) fifo_Stage__5_TO_Stage__10 <- mkFIFOF ( ); - FIFOF#( E_Stage__7_TO_Stage__15 ) fifo_Stage__7_TO_Stage__15 <- mkFIFOF ( ); - FIFOF#( E_Stage__4_TO_Stage__5 ) fifo_Stage__4_TO_Stage__5 <- mkFIFOF ( ); - FIFOF#( E_Stage__10_TO_Stage__13 ) fifo_Stage__10_TO_Stage__13 <- mkFIFOF ( ); - FIFOF#( E_Stage__12_TO_Stage__13 ) fifo_Stage__12_TO_Stage__13 <- mkFIFOF ( ); - FIFOF#( E_Start_TO_Stage__4 ) fifo_Start_TO_Stage__4 <- mkFIFOF ( ); - FIFOF#( E_Stage__5_TO_Stage__12 ) fifo_Stage__5_TO_Stage__12 <- mkFIFOF ( ); - FIFOF#( E__input__TO_Start ) fifo__input__TO_Start <- mkFIFOF ( ); - FIFOF#( E_Stage__15_TO_Stage__17 ) fifo_Stage__15_TO_Stage__17 <- mkFIFOF ( ); - FIFOF#( E_Stage__5_TO_Stage__7 ) fifo_Stage__5_TO_Stage__7 <- mkFIFOF ( ); - FIFOF#( E_Stage__13_TO_Stage__15 ) fifo_Stage__13_TO_Stage__15 <- mkFIFOF ( ); - FIFOF#( E_Stage__5_TO_Stage__13 ) fifo_Stage__5_TO_Stage__13 <- mkFIFOF ( ); - AddrLock#( LockId#(4), UInt#(5), 4 ) rf_lock <- mkFAAddrLock ( ); - Lock#( LockId#(4) ) imem_lock <- mkLock ( ); - Lock#( LockId#(4) ) m_lock <- mkLock ( ); - Lock#( LockId#(4) ) f_lock <- mkLock ( ); - Reg#( Bool ) rf_lock_region <- mkReg ( True ); - Reg#( Bool ) imem_lock_region <- mkReg ( True ); - Reg#( Bool ) m_lock_region <- mkReg ( True ); - Reg#( Bool ) f_lock_region <- mkReg ( True ); - Reg#( Bool ) busyReg <- mkReg ( False ); - FIFOF#( OutputQueueInfo ) outputQueue <- mkFIFOF ( ); - Reg#( UInt#(4) ) _threadID <- mkReg ( 0 ); - UInt#(4) _Stage__17__threadID = fifo_Stage__15_TO_Stage__17.first()._threadID; - UInt#(2) _Stage__5_op = fifo_Stage__4_TO_Stage__5.first().op; - UInt#(32) _Stage__5_rf2 = fifo_Stage__4_TO_Stage__5.first().rf2; - UInt#(32) _Stage__5_rf1 = fifo_Stage__4_TO_Stage__5.first().rf1; - Maybe#( LockId#(4) ) _Stage__5__lock_id_rf_rd = fifo_Stage__4_TO_Stage__5.first()._lock_id_rf_rd; - UInt#(5) _Stage__5_rd = fifo_Stage__4_TO_Stage__5.first().rd; - UInt#(4) _Stage__5__threadID = fifo_Stage__4_TO_Stage__5.first()._threadID; - Bool _Stage__5___condStage__16 = ?; - Bool _Stage__5___condStage__14 = ?; - UInt#(32) _Stage__5_carg_5 = ?; - UInt#(32) _Stage__5_carg_6 = ?; - UInt#(32) _Stage__5_carg_7 = ?; - UInt#(32) _Stage__5_carg_8 = ?; - UInt#(32) _Stage__5_carg_9 = ?; - UInt#(32) _Stage__5_carg_10 = ?; - UInt#(5) _Stage__5_carg_11 = ?; - _Stage__5___condStage__16 = ( _Stage__5_op == 2'd0 ); - if ( ( ! _Stage__5___condStage__16 )) - begin - _Stage__5___condStage__14 = ( _Stage__5_op == 2'd1 ); - end - if ( ( ( ! _Stage__5___condStage__16 ) && _Stage__5___condStage__14 )) - begin - _Stage__5_carg_5 = _Stage__5_rf1; - _Stage__5_carg_6 = _Stage__5_rf2; - end - if ( ( ( ! _Stage__5___condStage__16 ) && ( ! _Stage__5___condStage__14 ) )) - begin - _Stage__5_carg_7 = _Stage__5_rf1; - _Stage__5_carg_8 = _Stage__5_rf2; - _Stage__5_carg_9 = 32'd0; - _Stage__5_carg_10 = 32'd0; - _Stage__5_carg_11 = 5'd0; - end - UInt#(1) _Stage__12__request_3 = fifo_Stage__5_TO_Stage__12.first()._request_3; - UInt#(5) _Stage__12_rd = fifo_Stage__5_TO_Stage__12.first().rd; - Maybe#( LockId#(4) ) _Stage__12__lock_id_rf_rd = fifo_Stage__5_TO_Stage__12.first()._lock_id_rf_rd; - UInt#(4) _Stage__12__threadID = fifo_Stage__5_TO_Stage__12.first()._threadID; - UInt#(32) _Stage__12_res = ?; - _Stage__12_res = f.peek(); - MemId#(8) _Stage__4__request_1 = fifo_Start_TO_Stage__4.first()._request_1; - UInt#(4) _Stage__4__threadID = fifo_Start_TO_Stage__4.first()._threadID; - UInt#(32) _Stage__4_insn = ?; - UInt#(2) _Stage__4_op = ?; - UInt#(5) _Stage__4_rs1 = ?; - UInt#(5) _Stage__4_rs2 = ?; - UInt#(5) _Stage__4_rd = ?; - UInt#(32) _Stage__4_rf1 = ?; - UInt#(32) _Stage__4_rf2 = ?; - _Stage__4_insn = imem.peekResp(_Stage__4__request_1); - _Stage__4_op = unpack( pack( _Stage__4_insn ) [ 1 : 0 ] ); - _Stage__4_rs1 = unpack( pack( _Stage__4_insn ) [ 6 : 2 ] ); - _Stage__4_rs2 = unpack( pack( _Stage__4_insn ) [ 11 : 7 ] ); - _Stage__4_rd = unpack( pack( _Stage__4_insn ) [ 16 : 12 ] ); - _Stage__4_rf1 = rf.read(_Stage__4_rs1); - _Stage__4_rf2 = rf.read(_Stage__4_rs2); - UInt#(16) _Start_pc = fifo__input__TO_Start.first().pc; - UInt#(4) _Start__threadID = fifo__input__TO_Start.first()._threadID; - Bool _Start___condStage__3 = ?; - UInt#(16) _Start_carg_4 = ?; - _Start___condStage__3 = ( _Start_pc < 16'd14 ); - if ( _Start___condStage__3) - begin - _Start_carg_4 = ( _Start_pc + 16'd1 ); - end - Bool _Stage__13___condStage__14 = fifo_Stage__5_TO_Stage__13.first().__condStage__14; - UInt#(4) _Stage__13__threadID = fifo_Stage__5_TO_Stage__13.first()._threadID; - UInt#(32) _Stage__13_res = ( ( ! _Stage__13___condStage__14 ) ? fifo_Stage__12_TO_Stage__13.first().res : ( _Stage__13___condStage__14 ? fifo_Stage__10_TO_Stage__13.first().res : ? ) ); - UInt#(5) _Stage__13_rd = ( ( ! _Stage__13___condStage__14 ) ? fifo_Stage__12_TO_Stage__13.first().rd : ( _Stage__13___condStage__14 ? fifo_Stage__10_TO_Stage__13.first().rd : ? ) ); - Maybe#( LockId#(4) ) _Stage__13__lock_id_rf_rd = ( ( ! _Stage__13___condStage__14 ) ? fifo_Stage__12_TO_Stage__13.first()._lock_id_rf_rd : ( _Stage__13___condStage__14 ? fifo_Stage__10_TO_Stage__13.first()._lock_id_rf_rd : ? ) ); - Bool _Stage__15___condStage__16 = fifo_Stage__5_TO_Stage__15.first().__condStage__16; - UInt#(4) _Stage__15__threadID = fifo_Stage__5_TO_Stage__15.first()._threadID; - UInt#(32) _Stage__15_res = ( ( ! _Stage__15___condStage__16 ) ? fifo_Stage__13_TO_Stage__15.first().res : ( _Stage__15___condStage__16 ? fifo_Stage__7_TO_Stage__15.first().res : ? ) ); - UInt#(5) _Stage__15_rd = ( ( ! _Stage__15___condStage__16 ) ? fifo_Stage__13_TO_Stage__15.first().rd : ( _Stage__15___condStage__16 ? fifo_Stage__7_TO_Stage__15.first().rd : ? ) ); - Maybe#( LockId#(4) ) _Stage__15__lock_id_rf_rd = ( ( ! _Stage__15___condStage__16 ) ? fifo_Stage__13_TO_Stage__15.first()._lock_id_rf_rd : ( _Stage__15___condStage__16 ? fifo_Stage__7_TO_Stage__15.first()._lock_id_rf_rd : ? ) ); - UInt#(2) _Stage__10__request_2 = fifo_Stage__5_TO_Stage__10.first()._request_2; - UInt#(5) _Stage__10_rd = fifo_Stage__5_TO_Stage__10.first().rd; - Maybe#( LockId#(4) ) _Stage__10__lock_id_rf_rd = fifo_Stage__5_TO_Stage__10.first()._lock_id_rf_rd; - UInt#(4) _Stage__10__threadID = fifo_Stage__5_TO_Stage__10.first()._threadID; - UInt#(32) _Stage__10_res = ?; - _Stage__10_res = m.peek(); - UInt#(32) _Stage__7_rf2 = fifo_Stage__5_TO_Stage__7.first().rf2; - UInt#(32) _Stage__7_rf1 = fifo_Stage__5_TO_Stage__7.first().rf1; - Maybe#( LockId#(4) ) _Stage__7__lock_id_rf_rd = fifo_Stage__5_TO_Stage__7.first()._lock_id_rf_rd; - UInt#(5) _Stage__7_rd = fifo_Stage__5_TO_Stage__7.first().rd; - UInt#(4) _Stage__7__threadID = fifo_Stage__5_TO_Stage__7.first()._threadID; - UInt#(32) _Stage__7_res = ?; - _Stage__7_res = ( _Stage__7_rf1 + _Stage__7_rf2 ); - rule s_Stage__17_execute ; - fifo_Stage__15_TO_Stage__17.deq(); - $display("cpu:Thread %d:Executing Stage Stage__17 %t", _Stage__17__threadID,$time() ); - endrule - rule s_Stage__5_execute (( ( ! ( ( ! _Stage__5___condStage__16 ) && _Stage__5___condStage__14 ) ) || m_lock.isEmpty() ) && ( ( ! ( ( ! _Stage__5___condStage__16 ) && ( ! _Stage__5___condStage__14 ) ) ) || f_lock.isEmpty() )); - UInt#(2) _Stage__5__request_2 = ?; - UInt#(1) _Stage__5__request_3 = ?; - if ( ( ( ! _Stage__5___condStage__16 ) && _Stage__5___condStage__14 )) - begin - _Stage__5__request_2 <- m.req(_Stage__5_carg_5, _Stage__5_carg_6); - end - if ( ( ( ! _Stage__5___condStage__16 ) && ( ! _Stage__5___condStage__14 ) )) - begin - _Stage__5__request_3 <- f.req(_Stage__5_carg_7, _Stage__5_carg_8, _Stage__5_carg_9, _Stage__5_carg_10, _Stage__5_carg_11); - end - fifo_Stage__5_TO_Stage__15.enq(E_Stage__5_TO_Stage__15 { __condStage__16 : _Stage__5___condStage__16,_threadID : _Stage__5__threadID }); - if ( ( ( ! _Stage__5___condStage__16 ) && _Stage__5___condStage__14 )) - begin - fifo_Stage__5_TO_Stage__10.enq(E_Stage__5_TO_Stage__10 { _request_2 : _Stage__5__request_2,rd : _Stage__5_rd,_lock_id_rf_rd : _Stage__5__lock_id_rf_rd,_threadID : _Stage__5__threadID }); - end - fifo_Stage__4_TO_Stage__5.deq(); - if ( ( ( ! _Stage__5___condStage__16 ) && ( ! _Stage__5___condStage__14 ) )) - begin - fifo_Stage__5_TO_Stage__12.enq(E_Stage__5_TO_Stage__12 { _request_3 : _Stage__5__request_3,rd : _Stage__5_rd,_lock_id_rf_rd : _Stage__5__lock_id_rf_rd,_threadID : _Stage__5__threadID }); - end - if ( ( ! _Stage__5___condStage__16 )) - begin - fifo_Stage__5_TO_Stage__13.enq(E_Stage__5_TO_Stage__13 { __condStage__14 : _Stage__5___condStage__14,_threadID : _Stage__5__threadID }); - end - if ( _Stage__5___condStage__16) - begin - fifo_Stage__5_TO_Stage__7.enq(E_Stage__5_TO_Stage__7 { rf2 : _Stage__5_rf2,rf1 : _Stage__5_rf1,rd : _Stage__5_rd,_threadID : _Stage__5__threadID,_lock_id_rf_rd : _Stage__5__lock_id_rf_rd }); - end - $display("cpu:Thread %d:Executing Stage Stage__5 %t", _Stage__5__threadID,$time() ); - endrule - rule s_Stage__12_execute (f.checkHandle(_Stage__12__request_3)); - f.resp(); - fifo_Stage__12_TO_Stage__13.enq(E_Stage__12_TO_Stage__13 { res : _Stage__12_res,rd : _Stage__12_rd,_lock_id_rf_rd : _Stage__12__lock_id_rf_rd,_threadID : _Stage__12__threadID }); - fifo_Stage__5_TO_Stage__12.deq(); - $display("cpu:Thread %d:Executing Stage Stage__12 %t", _Stage__12__threadID,$time() ); - endrule - rule s_Stage__4_execute (imem.checkRespId(_Stage__4__request_1) && rf_lock.isEmpty(_Stage__4_rs1) && rf_lock.isEmpty(_Stage__4_rs2) && rf_lock.canRes(_Stage__4_rd)); - Maybe#( LockId#(4) ) _Stage__4__lock_id_rf_rd = ?; - imem.resp(_Stage__4__request_1); - _Stage__4__lock_id_rf_rd <- rf_lock.res(_Stage__4_rd); - fifo_Stage__4_TO_Stage__5.enq(E_Stage__4_TO_Stage__5 { rf1 : _Stage__4_rf1,op : _Stage__4_op,_threadID : _Stage__4__threadID,_lock_id_rf_rd : _Stage__4__lock_id_rf_rd,rd : _Stage__4_rd,rf2 : _Stage__4_rf2 }); - fifo_Start_TO_Stage__4.deq(); - $display("cpu:Thread %d:Executing Stage Stage__4 %t", _Stage__4__threadID,$time() ); - endrule - rule s_Start_execute (imem_lock.isEmpty()); - MemId#(8) _Start__request_1 = ?; - if ( _Start___condStage__3) - begin - fifo__input__TO_Start.enq(E__input__TO_Start { pc : _Start_carg_4,_threadID : _Start__threadID }); - end - _Start__request_1 <- imem.req(_Start_pc, ?, False); - fifo__input__TO_Start.deq(); - fifo_Start_TO_Stage__4.enq(E_Start_TO_Stage__4 { _request_1 : _Start__request_1,_threadID : _Start__threadID }); - $display("cpu:Thread %d:Executing Stage Start %t", _Start__threadID,$time() ); - endrule - rule s_Stage__13_execute ; - if ( _Stage__13___condStage__14) - begin - fifo_Stage__10_TO_Stage__13.deq(); - end - if ( ( ! _Stage__13___condStage__14 )) - begin - fifo_Stage__12_TO_Stage__13.deq(); - end - fifo_Stage__13_TO_Stage__15.enq(E_Stage__13_TO_Stage__15 { res : _Stage__13_res,rd : _Stage__13_rd,_lock_id_rf_rd : _Stage__13__lock_id_rf_rd,_threadID : _Stage__13__threadID }); - fifo_Stage__5_TO_Stage__13.deq(); - $display("cpu:Thread %d:Executing Stage Stage__13 %t", _Stage__13__threadID,$time() ); - endrule - rule s_Stage__15_execute (rf_lock.owns(fromMaybe( 0 , _Stage__15__lock_id_rf_rd ), _Stage__15_rd)); - $display(_Stage__15_res); - rf.write(_Stage__15_rd, _Stage__15_res); - rf_lock.rel(fromMaybe( 0 , _Stage__15__lock_id_rf_rd ), _Stage__15_rd); - if ( _Stage__15___condStage__16) - begin - fifo_Stage__7_TO_Stage__15.deq(); - end - if ( ( ! _Stage__15___condStage__16 )) - begin - fifo_Stage__13_TO_Stage__15.deq(); - end - fifo_Stage__15_TO_Stage__17.enq(E_Stage__15_TO_Stage__17 { _threadID : _Stage__15__threadID }); - fifo_Stage__5_TO_Stage__15.deq(); - $display("cpu:Thread %d:Executing Stage Stage__15 %t", _Stage__15__threadID,$time() ); - endrule - rule s_Stage__10_execute (m.checkHandle(_Stage__10__request_2)); - m.resp(); - fifo_Stage__10_TO_Stage__13.enq(E_Stage__10_TO_Stage__13 { res : _Stage__10_res,rd : _Stage__10_rd,_lock_id_rf_rd : _Stage__10__lock_id_rf_rd,_threadID : _Stage__10__threadID }); - fifo_Stage__5_TO_Stage__10.deq(); - $display("cpu:Thread %d:Executing Stage Stage__10 %t", _Stage__10__threadID,$time() ); - endrule - rule s_Stage__7_execute ; - fifo_Stage__7_TO_Stage__15.enq(E_Stage__7_TO_Stage__15 { res : _Stage__7_res,rd : _Stage__7_rd,_lock_id_rf_rd : _Stage__7__lock_id_rf_rd,_threadID : _Stage__7__threadID }); - fifo_Stage__5_TO_Stage__7.deq(); - $display("cpu:Thread %d:Executing Stage Stage__7 %t", _Stage__7__threadID,$time() ); - endrule - method ActionValue#(UInt#(4)) req ( UInt#(16) pc ) if( ( ! busyReg ) ); - fifo__input__TO_Start.enq(E__input__TO_Start { pc : pc,_threadID : _threadID }); - busyReg <= True; - _threadID <= ( _threadID + 1 ); - return _threadID; - endmethod - method Action resp ( ) ; - outputQueue.deq(); - endmethod - method Bool checkHandle ( UInt#(4) handle ) ; - return ( handle == outputQueue.first().handle ); - endmethod -endmodule diff --git a/src/main/scala/pipedsl/testOutputs/Functions.bsv b/src/main/scala/pipedsl/testOutputs/Functions.bsv deleted file mode 100644 index e69de29b..00000000 diff --git a/src/main/scala/pipedsl/testOutputs/Hist.bsv b/src/main/scala/pipedsl/testOutputs/Hist.bsv deleted file mode 100644 index d87fee67..00000000 --- a/src/main/scala/pipedsl/testOutputs/Hist.bsv +++ /dev/null @@ -1,107 +0,0 @@ -import FIFOF :: *; -import Locks :: *; -import Memories :: *; -import Functions :: *; - -export Hist (..); -export mkHist ; - -typedef struct { UInt#(10) counter; UInt#(3) _threadID ; } E__input__TO_Start deriving( Bits,Eq ); -typedef struct { UInt#(10) m; UInt#(32) wt; UInt#(3) _threadID ; } E_Start_TO_Stage__1 deriving( Bits,Eq ); -typedef struct { UInt#(10) m; UInt#(32) nm; Maybe#( LockId#(4) ) _lock_id_h_m; UInt#(3) _threadID ; } E_Stage__1_TO_Stage__2 deriving( Bits,Eq ); -typedef struct { UInt#(3) _threadID ; } E_Stage__2_TO_Stage__3 deriving( Bits,Eq ); -typedef struct { UInt#(3) handle; Bool data ; } OutputQueueInfo deriving( Bits,Eq ); - -interface Hist; - method ActionValue#(UInt#(3)) req ( UInt#(10) counter ) ; - method Action resp ( ) ; - method Bool checkHandle ( UInt#(3) handle ) ; - method Bool peek ( ) ; -endinterface - - -module mkHist ( CombMem#( UInt#(10), UInt#(10) ) feature, CombMem#( UInt#(32), UInt#(10) ) weight, CombMem#( UInt#(32), UInt#(10) ) h, Hist _unused_ ); - FIFOF#( E__input__TO_Start ) fifo__input__TO_Start <- mkFIFOF ( ); - FIFOF#( E_Start_TO_Stage__1 ) fifo_Start_TO_Stage__1 <- mkFIFOF ( ); - FIFOF#( E_Stage__1_TO_Stage__2 ) fifo_Stage__1_TO_Stage__2 <- mkFIFOF ( ); - FIFOF#( E_Stage__2_TO_Stage__3 ) fifo_Stage__2_TO_Stage__3 <- mkFIFOF ( ); - AddrLock#( LockId#(4), UInt#(10), 4 ) feature_lock <- mkFAAddrLock ( ); - AddrLock#( LockId#(4), UInt#(10), 4 ) weight_lock <- mkFAAddrLock ( ); - AddrLock#( LockId#(4), UInt#(10), 4 ) h_lock <- mkFAAddrLock ( ); - Reg#( Bool ) feature_lock_region <- mkReg ( True ); - Reg#( Bool ) weight_lock_region <- mkReg ( True ); - Reg#( Bool ) h_lock_region <- mkReg ( True ); - Reg#( Bool ) busyReg <- mkReg ( False ); - FIFOF#( OutputQueueInfo ) outputQueue <- mkFIFOF ( ); - Reg#( UInt#(3) ) _threadID <- mkReg ( 0 ); - UInt#(10) _Start_counter = fifo__input__TO_Start.first().counter; - UInt#(3) _Start__threadID = fifo__input__TO_Start.first()._threadID; - Bool _Start___condStage__6 = ?; - UInt#(10) _Start_carg = ?; - UInt#(10) _Start_m = ?; - UInt#(32) _Start_wt = ?; - _Start___condStage__6 = ( _Start_counter < 10'd1000 ); - if ( _Start___condStage__6) - begin - _Start_carg = ( _Start_counter + 10'd1 ); - _Start_m = feature.read(_Start_counter); - _Start_wt = weight.read(_Start_counter); - end - UInt#(10) _Stage__1_m = fifo_Start_TO_Stage__1.first().m; - UInt#(32) _Stage__1_wt = fifo_Start_TO_Stage__1.first().wt; - UInt#(3) _Stage__1__threadID = fifo_Start_TO_Stage__1.first()._threadID; - UInt#(32) _Stage__1_nm = ?; - _Stage__1_nm = ( h.read(_Stage__1_m) + _Stage__1_wt ); - UInt#(10) _Stage__2_m = fifo_Stage__1_TO_Stage__2.first().m; - UInt#(32) _Stage__2_nm = fifo_Stage__1_TO_Stage__2.first().nm; - Maybe#( LockId#(4) ) _Stage__2__lock_id_h_m = fifo_Stage__1_TO_Stage__2.first()._lock_id_h_m; - UInt#(3) _Stage__2__threadID = fifo_Stage__1_TO_Stage__2.first()._threadID; - UInt#(3) _Stage__3__threadID = fifo_Stage__2_TO_Stage__3.first()._threadID; - rule s_Start_execute (( ( ! ( ! _Start___condStage__6 ) ) || busyReg ) && ( ( ! _Start___condStage__6 ) || feature_lock.isEmpty(_Start_counter) ) && ( ( ! _Start___condStage__6 ) || weight_lock.isEmpty(_Start_counter) )); - if ( _Start___condStage__6) - begin - fifo__input__TO_Start.enq(E__input__TO_Start { counter : _Start_carg,_threadID : _Start__threadID }); - end - if ( ( ! _Start___condStage__6 )) - begin - busyReg <= False; - outputQueue.enq(OutputQueueInfo { data : True,handle : _Start__threadID }); - end - fifo__input__TO_Start.deq(); - if ( _Start___condStage__6) - begin - fifo_Start_TO_Stage__1.enq(E_Start_TO_Stage__1 { m : _Start_m,wt : _Start_wt,_threadID : _Start__threadID }); - end - endrule - rule s_Stage__1_execute (h_lock.canRes(_Stage__1_m) && h_lock.isEmpty(_Stage__1_m)); - Maybe#( LockId#(4) ) _Stage__1__lock_id_h_m = ?; - $display(_Stage__1_nm); - _Stage__1__lock_id_h_m <- h_lock.res(_Stage__1_m); - fifo_Stage__1_TO_Stage__2.enq(E_Stage__1_TO_Stage__2 { m : _Stage__1_m,nm : _Stage__1_nm,_lock_id_h_m : _Stage__1__lock_id_h_m,_threadID : _Stage__1__threadID }); - fifo_Start_TO_Stage__1.deq(); - endrule - rule s_Stage__2_execute ; - h.write(_Stage__2_m, _Stage__2_nm); - h_lock.rel(fromMaybe( 0 , _Stage__2__lock_id_h_m ), _Stage__2_m); - fifo_Stage__1_TO_Stage__2.deq(); - fifo_Stage__2_TO_Stage__3.enq(E_Stage__2_TO_Stage__3 { _threadID : _Stage__2__threadID }); - endrule - rule s_Stage__3_execute ; - fifo_Stage__2_TO_Stage__3.deq(); - endrule - method ActionValue#(UInt#(3)) req ( UInt#(10) counter ) if( ( ! busyReg ) ); - fifo__input__TO_Start.enq(E__input__TO_Start { counter : counter,_threadID : _threadID }); - busyReg <= True; - _threadID <= ( _threadID + 1 ); - return _threadID; - endmethod - method Action resp ( ) ; - outputQueue.deq(); - endmethod - method Bool peek ( ) ; - return outputQueue.first().data; - endmethod - method Bool checkHandle ( UInt#(3) handle ) ; - return ( handle == outputQueue.first().handle ); - endmethod -endmodule diff --git a/src/main/scala/pipedsl/testOutputs/Multi_stg_div.bsv b/src/main/scala/pipedsl/testOutputs/Multi_stg_div.bsv deleted file mode 100644 index 52ffb16f..00000000 --- a/src/main/scala/pipedsl/testOutputs/Multi_stg_div.bsv +++ /dev/null @@ -1,84 +0,0 @@ -import FIFOF :: *; -import Locks :: *; -import Memories :: *; -import Functions :: *; -import Multi_stg_mul :: *; - -export Multi_stg_div (..); -export mkMulti_stg_div ; - -typedef struct { UInt#(32) num; UInt#(32) denom; UInt#(32) quot; UInt#(32) acc; UInt#(5) cnt; UInt#(1) _threadID ; } E__input__TO_Start deriving( Bits,Eq ); -typedef struct { UInt#(1) handle; UInt#(32) data ; } OutputQueueInfo deriving( Bits,Eq ); - -interface Multi_stg_div; - method ActionValue#(UInt#(1)) req ( UInt#(32) num, UInt#(32) denom, UInt#(32) quot, UInt#(32) acc, UInt#(5) cnt ) ; - method Action resp ( ) ; - method Bool checkHandle ( UInt#(1) handle ) ; - method UInt#(32) peek ( ) ; -endinterface - - -(* synthesize *) -module mkMulti_stg_div ( Multi_stg_div _unused_ ); - FIFOF#( E__input__TO_Start ) fifo__input__TO_Start <- mkFIFOF ( ); - Reg#( Bool ) busyReg <- mkReg ( False ); - FIFOF#( OutputQueueInfo ) outputQueue <- mkFIFOF ( ); - Reg#( UInt#(1) ) _threadID <- mkReg ( 0 ); - UInt#(32) _Start_quot = fifo__input__TO_Start.first().quot; - UInt#(5) _Start_cnt = fifo__input__TO_Start.first().cnt; - UInt#(32) _Start_acc = fifo__input__TO_Start.first().acc; - UInt#(32) _Start_num = fifo__input__TO_Start.first().num; - UInt#(32) _Start_denom = fifo__input__TO_Start.first().denom; - UInt#(1) _Start__threadID = fifo__input__TO_Start.first()._threadID; - UInt#(32) _Start_tmp = ?; - UInt#(32) _Start_na = ?; - UInt#(32) _Start_nq = ?; - UInt#(32) _Start_nnum = ?; - Bool _Start___condStage__3 = ?; - UInt#(32) _Start_carg = ?; - UInt#(32) _Start_carg_0 = ?; - UInt#(32) _Start_carg_1 = ?; - UInt#(32) _Start_carg_2 = ?; - UInt#(5) _Start_carg_3 = ?; - _Start_tmp = unpack( { pack( _Start_acc ) [ 30 : 0 ], pack( _Start_num ) [ 31 : 31 ] } ); - _Start_na = ( ( _Start_tmp >= _Start_denom ) ? ( _Start_tmp - _Start_denom ) : _Start_tmp ); - _Start_nq = ( ( _Start_tmp >= _Start_denom ) ? unpack( { pack( ( _Start_quot << 1'd1 ) ) [ 31 : 1 ], pack( 1'd1 ) } ) : ( _Start_quot << 1'd1 ) ); - _Start_nnum = ( _Start_num << 1'd1 ); - _Start___condStage__3 = ( _Start_cnt == 5'd31 ); - if ( ( ! _Start___condStage__3 )) - begin - _Start_carg = _Start_nnum; - _Start_carg_0 = _Start_denom; - _Start_carg_1 = _Start_nq; - _Start_carg_2 = _Start_na; - _Start_carg_3 = ( _Start_cnt + 5'd1 ); - end - rule s_Start_execute (( ( ! _Start___condStage__3 ) || busyReg )); - if ( _Start___condStage__3) - begin - busyReg <= False; - outputQueue.enq(OutputQueueInfo { data : _Start_nq,handle : _Start__threadID }); - end - if ( ( ! _Start___condStage__3 )) - begin - fifo__input__TO_Start.enq(E__input__TO_Start { acc : _Start_carg_2,cnt : _Start_carg_3,num : _Start_carg,denom : _Start_carg_0,_threadID : _Start__threadID,quot : _Start_carg_1 }); - end - fifo__input__TO_Start.deq(); - $display("multi_stg_div:Thread %d:Executing Stage Start %t", _Start__threadID,$time() ); - endrule - method ActionValue#(UInt#(1)) req ( UInt#(32) num, UInt#(32) denom, UInt#(32) quot, UInt#(32) acc, UInt#(5) cnt ) if( ( ! busyReg ) ); - fifo__input__TO_Start.enq(E__input__TO_Start { num : num,acc : acc,quot : quot,_threadID : _threadID,denom : denom,cnt : cnt }); - busyReg <= True; - _threadID <= ( _threadID + 1 ); - return _threadID; - endmethod - method Action resp ( ) ; - outputQueue.deq(); - endmethod - method UInt#(32) peek ( ) ; - return outputQueue.first().data; - endmethod - method Bool checkHandle ( UInt#(1) handle ) ; - return ( handle == outputQueue.first().handle ); - endmethod -endmodule diff --git a/src/main/scala/pipedsl/testOutputs/Multi_stg_mul.bsv b/src/main/scala/pipedsl/testOutputs/Multi_stg_mul.bsv deleted file mode 100644 index 8be1411b..00000000 --- a/src/main/scala/pipedsl/testOutputs/Multi_stg_mul.bsv +++ /dev/null @@ -1,68 +0,0 @@ -import FIFOF :: *; -import Locks :: *; -import Memories :: *; -import Functions :: *; - -export Multi_stg_mul (..); -export mkMulti_stg_mul ; - -typedef struct { UInt#(32) a1; UInt#(32) a2; UInt#(2) _threadID ; } E__input__TO_Start deriving( Bits,Eq ); -typedef struct { UInt#(32) rr; UInt#(32) lr; UInt#(32) rl; UInt#(2) _threadID ; } E_Start_TO_Stage__0 deriving( Bits,Eq ); -typedef struct { UInt#(2) handle; UInt#(32) data ; } OutputQueueInfo deriving( Bits,Eq ); - -interface Multi_stg_mul; - method ActionValue#(UInt#(2)) req ( UInt#(32) a1, UInt#(32) a2 ) ; - method Action resp ( ) ; - method Bool checkHandle ( UInt#(2) handle ) ; - method UInt#(32) peek ( ) ; -endinterface - - -(* synthesize *) -module mkMulti_stg_mul ( Multi_stg_mul _unused_ ); - FIFOF#( E__input__TO_Start ) fifo__input__TO_Start <- mkFIFOF ( ); - FIFOF#( E_Start_TO_Stage__0 ) fifo_Start_TO_Stage__0 <- mkFIFOF ( ); - FIFOF#( OutputQueueInfo ) outputQueue <- mkFIFOF ( ); - Reg#( UInt#(2) ) _threadID <- mkReg ( 0 ); - UInt#(32) _Start_a1 = fifo__input__TO_Start.first().a1; - UInt#(32) _Start_a2 = fifo__input__TO_Start.first().a2; - UInt#(2) _Start__threadID = fifo__input__TO_Start.first()._threadID; - UInt#(32) _Start_rr = ?; - UInt#(32) _Start_rl = ?; - UInt#(32) _Start_lr = ?; - _Start_rr = unsignedMul( unpack( pack( _Start_a1 ) [ 15 : 0 ] ) , unpack( pack( _Start_a2 ) [ 15 : 0 ] ) ); - _Start_rl = unsignedMul( unpack( pack( _Start_a1 ) [ 15 : 0 ] ) , unpack( pack( _Start_a2 ) [ 31 : 16 ] ) ); - _Start_lr = unsignedMul( unpack( pack( _Start_a1 ) [ 31 : 16 ] ) , unpack( pack( _Start_a2 ) [ 15 : 0 ] ) ); - UInt#(32) _Stage__0_rr = fifo_Start_TO_Stage__0.first().rr; - UInt#(32) _Stage__0_lr = fifo_Start_TO_Stage__0.first().lr; - UInt#(32) _Stage__0_rl = fifo_Start_TO_Stage__0.first().rl; - UInt#(2) _Stage__0__threadID = fifo_Start_TO_Stage__0.first()._threadID; - UInt#(32) _Stage__0_t1 = ?; - UInt#(32) _Stage__0_res = ?; - _Stage__0_t1 = ( _Stage__0_rl + _Stage__0_lr ); - _Stage__0_res = ( ( _Stage__0_t1 << 5'd16 ) + _Stage__0_rr ); - rule s_Start_execute ; - fifo__input__TO_Start.deq(); - fifo_Start_TO_Stage__0.enq(E_Start_TO_Stage__0 { rr : _Start_rr,lr : _Start_lr,rl : _Start_rl,_threadID : _Start__threadID }); - $display("multi_stg_mul:Thread %d:Executing Stage Start %t", _Start__threadID,$time() ); - endrule - rule s_Stage__0_execute ; - outputQueue.enq(OutputQueueInfo { data : _Stage__0_res,handle : _Stage__0__threadID }); - fifo_Start_TO_Stage__0.deq(); - $display("multi_stg_mul:Thread %d:Executing Stage Stage__0 %t", _Stage__0__threadID,$time() ); - endrule - method ActionValue#(UInt#(2)) req ( UInt#(32) a1, UInt#(32) a2 ) ; - fifo__input__TO_Start.enq(E__input__TO_Start { a1 : a1,a2 : a2,_threadID : _threadID }); - _threadID <= ( _threadID + 1 ); - return _threadID; - endmethod - method Action resp ( ) ; - outputQueue.deq(); - endmethod - method UInt#(32) peek ( ) ; - return outputQueue.first().data; - endmethod - method Bool checkHandle ( UInt#(2) handle ) ; - return ( handle == outputQueue.first().handle ); - endmethod -endmodule diff --git a/src/main/scala/pipedsl/testOutputs/clean.sh b/src/main/scala/pipedsl/testOutputs/clean.sh deleted file mode 100644 index e95adbb1..00000000 --- a/src/main/scala/pipedsl/testOutputs/clean.sh +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/bash - -rm -f *.bi *.bo *.ba -rm -f *.cxx *.h *.o *.so *.bexe -rm -f *.v *.vexe -rm -f *.vcd *~ *.fsdb *.log -rm -f *.sched -find * -type d -exec rm -rf {} + - diff --git a/src/main/scala/pipedsl/testOutputs/f b/src/main/scala/pipedsl/testOutputs/f deleted file mode 100644 index 2f16247c..00000000 --- a/src/main/scala/pipedsl/testOutputs/f +++ /dev/null @@ -1,1024 +0,0 @@ -1b9 -1ba -275 -21b -2e4 -3fc -3c6 -197 -1a4 -129 -206 -2b4 -2e -3ea -198 -22e -38 -d2 -129 -200 -1d7 -2b4 -339 -9f -231 -31a -91 -204 -36c -2f1 -2b8 -29f -1cd -17d -3c8 -27d -5c -1dd -342 -18e -6a -178 -289 -105 -1a6 -f7 -1d6 -94 -7e -2ac -319 -2a8 -87 -e3 -22e -bc -2d9 -279 -33d -3b5 -26e -3df -59 -9d -25f -126 -351 -135 -e8 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a/src/main/scala/pipedsl/testOutputs/imemMultiExec +++ /dev/null @@ -1,16 +0,0 @@ -00000000 // 0 + 0 = 0 in rf[0] -00001084 // 1 + 1 = 2 in rf[1] -00002108 // 2 + 2 = 4 in rf[2] -0000318C // 3 + 3 = 6 in rf[3] -00004081 // rf[0] * rf[1] = 0 in rf[4] -//Show off parallelism for multi, divider, and adder, no hazards -0000510D // rf[3] * rf[2] = 6 * 4 = 24 in rf[5] -0000F734 // rf[13] + rf[14] = 13 + 14 = 27 in rf[15] -0000A663 // rf[24] / rf[12] = 24/12 = 2 in rf[10] -00006115 // rf[5] * rf[2] = 24 * 4 = 96 in rf[6] -00016AD0 // rf[20] + rf[21] = 20 + 21 = 41 in rf[22] -//Make sure data hazards arent allowed to be parallelized -0000719A // rf[6] / rf[3] = 96 / 6 = 16 in rf[7] -0000739E // rf[7] / rf[7] = 1 in rf[7] -0000719D // rf[7] * rf[3] = 1 * 6 = 6 in rf[7] -0000719C // rf[7] + rf[3] = 6 + 6 = 12 in rf[7] diff --git a/src/main/scala/pipedsl/testOutputs/mkCircuit.ba b/src/main/scala/pipedsl/testOutputs/mkCircuit.ba deleted file mode 100644 index e40a1c8b..00000000 Binary files a/src/main/scala/pipedsl/testOutputs/mkCircuit.ba and /dev/null differ diff --git a/src/main/scala/pipedsl/testOutputs/mkTB.ba b/src/main/scala/pipedsl/testOutputs/mkTB.ba deleted file mode 100644 index 58a6ecae..00000000 Binary files a/src/main/scala/pipedsl/testOutputs/mkTB.ba and /dev/null differ diff --git a/src/main/scala/pipedsl/testOutputs/mkTB.bexe b/src/main/scala/pipedsl/testOutputs/mkTB.bexe deleted file mode 100755 index 930c50b8..00000000 --- a/src/main/scala/pipedsl/testOutputs/mkTB.bexe +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/sh - -BLUESPECDIR=`echo 'puts $env(BLUESPECDIR)' | bluetcl` - -for arg in $@ -do - if (test "$arg" = "-h") - then - exec $BLUESPECDIR/tcllib/bluespec/bluesim.tcl $0.so mkTB --script_name `basename $0` -h - fi -done -exec $BLUESPECDIR/tcllib/bluespec/bluesim.tcl $0.so mkTB --script_name `basename $0` "$@" diff --git a/src/main/scala/pipedsl/testOutputs/mkTB.bexe.so b/src/main/scala/pipedsl/testOutputs/mkTB.bexe.so deleted file mode 100755 index ec23356f..00000000 Binary files a/src/main/scala/pipedsl/testOutputs/mkTB.bexe.so and /dev/null differ diff --git a/src/main/scala/pipedsl/testOutputs/rfMultiExec b/src/main/scala/pipedsl/testOutputs/rfMultiExec deleted file mode 100644 index 67d81a41..00000000 --- a/src/main/scala/pipedsl/testOutputs/rfMultiExec +++ /dev/null @@ -1,40 +0,0 @@ -00000000 -00000001 -00000002 -00000003 -00000004 -00000005 -00000006 -00000007 -00000008 -00000009 -0000000a -0000000b -0000000c -0000000d -0000000e -0000000f -00000010 -00000011 -00000012 -00000013 -00000014 -00000015 -00000016 -00000017 -00000018 -00000019 -0000001a -0000001b -0000001c -0000001d -0000001e -0000001f - - - - - - - - diff --git a/src/main/scala/pipedsl/testOutputs/runbsc.sh b/src/main/scala/pipedsl/testOutputs/runbsc.sh deleted file mode 100644 index 9672deff..00000000 --- a/src/main/scala/pipedsl/testOutputs/runbsc.sh +++ /dev/null @@ -1,18 +0,0 @@ -#!/bin/bash - -TOP=Circuit -TB="mkTB" -ARGS="-no-show-timestamps -no-show-version --aggressive-conditions" -BPATH="-p .:%/Prelude:%/Libraries:/Users/kevinzhang/Documents/SpecLang/bscRuntime/memories:/Users/kevinzhang/Documents/SpecLang/bscRuntime/locks:/Users/kevinzhang/Documents/SpecLang/bscRuntime/stages" -#Compiling Base Module -#bsc $ARGS $BPATH -show-schedule -verilog $FILE -#Compile test bench -VDIR="$TOP"_verilog -SDIR="$TOP"_sim -mkdir -p $VDIR -mkdir -p $SDIR -bsc $ARGS $BPATH -show-schedule -verilog -vdir $VDIR -u "$TOP".bsv -#Run simulation for like...a million cycles -bsc $ARGS $BPATH -sim -simdir $SDIR -u "$TOP".bsv -bsc $ARGS -sim -simdir $SDIR -o "$TB".bexe -e "$TB" "$TB".ba -./"$TB".bexe > top.sim.out diff --git a/src/main/scala/pipedsl/testOutputs/top.sim.out b/src/main/scala/pipedsl/testOutputs/top.sim.out deleted file mode 100644 index ce43b9ac..00000000 --- a/src/main/scala/pipedsl/testOutputs/top.sim.out +++ /dev/null @@ -1,998 +0,0 @@ - 58205 - 19762 - 32169 - 36716 - 18286 - 23715 - 19698 - 3539 - 31690 - 6886 - 58591 - 7194 - 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-de87 -f7b8 -f907 -70dc -dd78 -51b8 -ff40 -3f3c -56b0 -f21e -9b9 -d3f8 -5361 -b976 -1816 -d466 -c9f9 -11bf -d636 -dafe -8452 -b4d2 -d4c3 -b34e -6de7 -6d6d diff --git a/src/main/scala/pipedsl/typechecker/BaseTypeChecker.scala b/src/main/scala/pipedsl/typechecker/BaseTypeChecker.scala index 4abbcc6c..85645a1d 100644 --- a/src/main/scala/pipedsl/typechecker/BaseTypeChecker.scala +++ b/src/main/scala/pipedsl/typechecker/BaseTypeChecker.scala @@ -1,3 +1,4 @@ +/** package pipedsl.typechecker import pipedsl.common.Errors._ @@ -118,11 +119,11 @@ object BaseTypeChecker extends TypeChecks[Id, Type] { val ast = checkModuleBodyWellFormed(cons, assignees) val asf = checkModuleBodyWellFormed(alt, assignees) ast ++ asf - case CRecv(lhs@EVar(id), _) => + case CRecv(lhs@EVar(id), _, _) => if (assignees(id)) { throw UnexpectedAssignment(lhs.pos, id) } else { assignees + id } - case CAssign(lhs@EVar(id), _) => + case CAssign(lhs@EVar(id), _, _) => if (assignees(id)) { throw UnexpectedAssignment(lhs.pos, id) } else { assignees + id } @@ -227,13 +228,13 @@ object BaseTypeChecker extends TypeChecks[Id, Type] { val efalse = checkCommand(alt, cenv) etrue.intersect(efalse) } - case CAssign(lhs, rhs) => { + case CAssign(lhs, rhs, _) => { val (rTyp, renv) = checkExpression(rhs, tenv) val (lTyp, lenv) = checkExpression(lhs, renv) if (isSubtype(rTyp, lTyp)) lenv else throw UnexpectedSubtype(rhs.pos, "assignment", lTyp, rTyp) } - case CRecv(lhs, rhs) => { + case CRecv(lhs, rhs, _) => { val (rTyp, renv) = checkExpression(rhs, tenv) val (lTyp, lenv) = checkExpression(lhs, renv) if (isSubtype(rTyp, lTyp)) lenv @@ -301,7 +302,7 @@ object BaseTypeChecker extends TypeChecks[Id, Type] { } } - case CEmpty => tenv + case CEmpty() => tenv case _ => throw UnexpectedCommand(c) } @@ -468,3 +469,4 @@ object BaseTypeChecker extends TypeChecks[Id, Type] { case _ => Set() } } + */ diff --git a/src/main/scala/pipedsl/typechecker/Environments.scala b/src/main/scala/pipedsl/typechecker/Environments.scala index e91769b6..933c6db5 100644 --- a/src/main/scala/pipedsl/typechecker/Environments.scala +++ b/src/main/scala/pipedsl/typechecker/Environments.scala @@ -5,6 +5,7 @@ import pipedsl.common.Errors._ import pipedsl.common.Locks._ import pipedsl.common.Syntax._ import pipedsl.common.Utilities._ +import pipedsl.analysis.TypeInference._ object Environments { @@ -49,7 +50,10 @@ object Environments { case class TypeEnv( typeMap: Map[Id, Type] = Map()) extends Environment[Id, Type] { - override def apply(id: Id) = this.get(id).getOrThrow(MissingType(id.pos, id.v)) + override def apply(id: Id) = this.get(id) match { + case Some(value) => value + case None => throw MissingType(id.pos, id.v) + } override def add(name: Id, typ: Type): Environment[Id, Type] = typeMap.get(name) match { case Some(t) => throw AlreadyBoundType(name.pos, name.v, t, typ) @@ -80,6 +84,7 @@ object Environments { } })) } + def apply_subst_typeenv(subst: List[(Id, Type)]): TypeEnv = TypeEnv(typeMap.foldLeft[Map[Id, Type]](Map())((e, kv) => e + (kv._1 -> apply_subst_typ(subst, kv._2)))) } case class LockEnv(lockMap: Map[Id, LockState] = Map()) extends Environment[Id, LockState] { @@ -179,6 +184,6 @@ object Environments { //This is filler code, I don't think we ever actually need this override def union(other: Environment[LockArg, Z3AST]): Environment[LockArg, Z3AST] = other - + } } diff --git a/src/main/scala/pipedsl/typechecker/LockConstraintChecker.scala b/src/main/scala/pipedsl/typechecker/LockConstraintChecker.scala index 4618d59f..b2aa27d1 100644 --- a/src/main/scala/pipedsl/typechecker/LockConstraintChecker.scala +++ b/src/main/scala/pipedsl/typechecker/LockConstraintChecker.scala @@ -1,15 +1,15 @@ package pipedsl.typechecker import com.microsoft.z3.{AST => Z3AST, BoolExpr => Z3BoolExpr, Context => Z3Context, Solver => Z3Solver, Status => Z3Status} +import pipedsl.analysis.{PredicateAnalysis, TypeAnalysis} import pipedsl.common.Errors.UnexpectedCase import pipedsl.common.Locks import pipedsl.common.Locks._ import pipedsl.common.Syntax._ +import pipedsl.common.Utilities.{mkAnd, mkImplies} import pipedsl.typechecker.Environments._ import pipedsl.typechecker.TypeChecker.TypeChecks -import scala.collection.mutable - /** * This checks that all reads and writes to memories * only happen when appropriate. @@ -19,16 +19,9 @@ import scala.collection.mutable * possible, the type checking fails. */ //TODO: Make error case classes -class LockConstraintChecker(lockMap: Map[Id, Set[LockArg]], lockTypeMap: Map[Id, Map[Id, LockType]]) extends TypeChecks[LockArg, Z3AST] { - - private val ctx: Z3Context = new Z3Context() +class LockConstraintChecker(val predicateAnalysis: PredicateAnalysis, lockMap: Map[Id, Set[LockArg]], lockTypeMap: Map[Id, Map[Id, LockType]], val ctx: Z3Context) + extends TypeChecks[LockArg, Z3AST] { private val solver: Z3Solver = ctx.mkSolver() - - private val predicates: mutable.Stack[Z3AST] = mutable.Stack(ctx.mkTrue()) - private val predicateGenerator = new PredicateGenerator(ctx) - - private var incrementer = 0 - private var currentMod = Id("-invalid-") override def emptyEnv(): Environment[LockArg, Z3AST] = ConditionalLockEnv(ctx = ctx) @@ -38,19 +31,19 @@ class LockConstraintChecker(lockMap: Map[Id, Set[LockArg]], lockTypeMap: Map[Id, override def checkModule(m: ModuleDef, env: Environment[LockArg, Z3AST]): Environment[LockArg, Z3AST] = { currentMod = m.name - val nenv = lockMap(m.name).foldLeft[Environment[LockArg, Z3AST]](env)((e, mem) => e.add(mem, makeEquals(mem, Free))) + val nenv = lockMap(m.name).foldLeft[Environment[LockArg, Z3AST]](emptyEnv())((e, mem) => e.add(mem, makeEquals(mem, Free))) val finalenv = checkCommand(m.body, nenv) //At end of execution all locks must be free or released finalenv.getMappedKeys().foreach(id => { - checkState(id, finalenv, Released.order, Free.order) match { + checkState(id, finalenv, ctx.mkTrue(), Released.order, Free.order) match { case Z3Status.SATISFIABLE => throw new RuntimeException("We want everything at end to be free or released") - case _ => + case _ => } }) env //no change to lock map after checking module } - + def checkCommand(c: Command, env: Environment[LockArg, Z3AST]): Environment[LockArg, Z3AST] = { c match { case CSeq(c1, c2) => @@ -62,39 +55,16 @@ class LockConstraintChecker(lockMap: Map[Id, Set[LockArg]], lockTypeMap: Map[Id, checkCommand(c2, l1) case CSplit(cases, default) => - //This will keep track of the not predicates required for all previously seen cases - val runningPredicates = mutable.Stack[Z3AST]() //keeps track of the current environment as iterate through the cases var runningEnv = env //need some special handling for the first case statement var first = true for (caseObj <- cases) { - //get abstract interp of condition - var currentCond: Z3AST = null - predicateGenerator.abstractInterpExpr(caseObj.cond) match { - case Some(value) => currentCond = value - case None => currentCond = ctx.mkEq(ctx.mkBoolConst("__TOPCONSTANT__" + incrementer), ctx.mkTrue()) - } - //Get the not of the current condition - val notCurrentCond = ctx.mkNot(currentCond.asInstanceOf[Z3BoolExpr]) - if (runningPredicates.isEmpty) { - predicates.push(currentCond) - runningPredicates.push(notCurrentCond) - } else { - val runningNot = runningPredicates.pop() - //need to add the current condition and the running Not of the previous cases to the predicates - predicates.push(mkAnd(runningNot, currentCond)) - //add to the current running not - runningPredicates.push(mkAnd(runningNot, notCurrentCond)) - } val newEnv = checkCommand(caseObj.body, env) - //makes new environment with all locks implied by this case val tenv = ConditionalLockEnv(newEnv.getMappedKeys() - .foldLeft[Map[LockArg, Z3AST]](Map())((nenv, id) => nenv + (id -> mkImplies(mkAnd(predicates.toSeq: _*), newEnv(id)))), + .foldLeft[Map[LockArg, Z3AST]](Map())((nenv, id) => nenv + (id -> mkImplies(ctx, predicateAnalysis.predicate(caseObj.body), newEnv(id)))), ctx) - //remove the predicate used for this case statement to reset for the next case - predicates.pop() if (first) { runningEnv = tenv } else { @@ -102,121 +72,109 @@ class LockConstraintChecker(lockMap: Map[Id, Set[LockArg]], lockTypeMap: Map[Id, } first = false } - //For default, all the case statements must be false, so add this to the predicates - predicates.push(runningPredicates.pop()) val defEnv = checkCommand(default, env) val tenv = ConditionalLockEnv(defEnv.getMappedKeys() - .foldLeft[Map[LockArg, Z3AST]](Map())((nenv, id) => nenv + (id -> mkImplies(mkAnd(predicates.toSeq: _*), defEnv(id)))), + .foldLeft[Map[LockArg, Z3AST]](Map())((nenv, id) => nenv + (id -> mkImplies(ctx, mkAnd(ctx, predicateAnalysis.predicate(default)), defEnv(id)))), ctx) - predicates.pop() tenv.intersect(runningEnv) case CIf(expr, cons, alt) => - predicateGenerator.abstractInterpExpr(expr) match { - case Some(value) => predicates.push(value); - case None => predicates.push(ctx.mkEq(ctx.mkBoolConst("__TOPCONSTANT__" + incrementer), ctx.mkTrue())) - } - incrementer += 1 - val lt = checkCommand(cons, env) //makes new environment with all locks implied by true branch val tenv = ConditionalLockEnv(lt.getMappedKeys() - .foldLeft[Map[LockArg, Z3AST]](Map())((nenv, id) => nenv + (id -> mkImplies(mkAnd(predicates.toSeq: _*), lt(id)))), + .foldLeft[Map[LockArg, Z3AST]](Map())((nenv, id) => nenv + (id -> mkImplies(ctx, predicateAnalysis.predicate(cons), lt(id)))), ctx) - val trueBranch = predicates.pop() - predicates.push(ctx.mkNot(trueBranch.asInstanceOf[Z3BoolExpr])) val lf = checkCommand(alt, env) //makes new environment with all locks implied by false branch val fenv = ConditionalLockEnv(lf.getMappedKeys() - .foldLeft[Map[LockArg, Z3AST]](Map())((nenv, id) => nenv + (id -> mkImplies(mkAnd(predicates.toSeq: _*), lf(id)))), + .foldLeft[Map[LockArg, Z3AST]](Map())((nenv, id) => nenv + (id -> mkImplies(ctx, predicateAnalysis.predicate(alt), lf(id)))), ctx) - predicates.pop() - //Merge the two envs tenv.intersect(fenv) //real merge logic lives inside Envrionments.Z3AST case _: CSpeculate => //TODO env - case CAssign(_, rhs) => checkExpr(rhs, env) - case CRecv(lhs, rhs) => (lhs, rhs) match { + case CAssign(_, rhs, typ) => checkExpr(rhs, env, predicateAnalysis.predicate(c)) + case CRecv(lhs, rhs, typ) => (lhs, rhs) match { case (EMemAccess(mem, expr), _) => - checkAcquired(mem, expr, env) + checkAcquired(mem, expr, env, predicateAnalysis.predicate(c)) case (_, EMemAccess(mem, expr)) => - checkAcquired(mem, expr, env) + checkAcquired(mem, expr, env, predicateAnalysis.predicate(c)) case (_, ECall(mod, _)) => //TODO Maybe just from null - checkAcquired(mod, null, env) + checkAcquired(mod, null, env, predicateAnalysis.predicate(c)) case _ => throw UnexpectedCase(c.pos) } - case CLockOp(mem, op) => + case c@CLockOp(mem, op) => val expectedLockState = op match { case Locks.Free => throw new IllegalStateException() // TODO: is this right? case Locks.Reserved => Free case Locks.Acquired => Reserved case Locks.Released => Acquired } - checkState(mem, env, expectedLockState.order) match { - case Z3Status.UNSATISFIABLE => - env.add(mem, mkImplies(mkAnd(predicates.toSeq: _*), makeEquals(mem, op))) - case Z3Status.UNKNOWN => - throw new RuntimeException("An error occurred while attempting to solve the constraints") - case Z3Status.SATISFIABLE => - throw new RuntimeException("A possible thread of execution can cause this to fail: memories needs to be acquired before releasing") - } + checkState(mem, env, predicateAnalysis.predicate(c), expectedLockState.order) match { + case Z3Status.UNSATISFIABLE => + env.add(mem, mkImplies(ctx, predicateAnalysis.predicate(c), makeEquals(mem, op))) + case Z3Status.UNKNOWN => + throw new RuntimeException("An error occurred while attempting to solve the constraints") + case Z3Status.SATISFIABLE => + throw new RuntimeException(s"A possible thread of execution can cause this to fail: memories needs to be $expectedLockState before $op") + } case _ => env } } - private def checkExpr(e: Expr, env: Environment[LockArg, Z3AST]): Environment[LockArg, Z3AST] = e match { - case EUop(_, ex) => checkExpr(ex, env) + private def checkExpr(e: Expr, env: Environment[LockArg, Z3AST], predicates: Z3BoolExpr): Environment[LockArg, Z3AST] = e match { + case EUop(_, ex) => checkExpr(ex, env, predicates) case EBinop(_, e1, e2) => - val env1 = checkExpr(e1, env) - checkExpr(e2, env1) - case EMemAccess(mem, index) => checkAcquired(mem, index, env) + val env1 = checkExpr(e1, env, predicates) + checkExpr(e2, env1, predicates) + case EMemAccess(mem, index) => checkAcquired(mem, index, env, predicates) case ETernary(cond, tval, fval) => - val env1 = checkExpr(cond, env) - val env2 = checkExpr(tval, env1) - checkExpr(fval, env2) - case EApp(_, args) => args.foldLeft(env)((e, a) => checkExpr(a, e)) - case ECall(_, args) => args.foldLeft(env)((e, a) => checkExpr(a, e)) - case ECast(_, exp) => checkExpr(exp, env) + val env1 = checkExpr(cond, env, predicates) + val env2 = checkExpr(tval, env1, predicates) + checkExpr(fval, env2, predicates) + case EApp(_, args) => args.foldLeft(env)((e, a) => checkExpr(a, e, predicates)) + case ECall(_, args) => args.foldLeft(env)((e, a) => checkExpr(a, e, predicates)) + case ECast(_, exp) => checkExpr(exp, env, predicates) case _ => env } override def checkCircuit(c: Circuit, env: Environment[LockArg, Z3AST]): Environment[LockArg, Z3AST] = env - - private def checkState(mem: LockArg, env: Environment[LockArg, Z3AST], lockStateOrders: Int*): Z3Status = { - // Makes an OR of all given lock states + private def checkState(mem: LockArg, env: Environment[LockArg, Z3AST], predicates: Z3BoolExpr, lockStateOrders: Int*): Z3Status = { + + // Makes an OR of all given lock states val stateAST = lockStateOrders.foldLeft(ctx.mkFalse())((ast, order) => ctx.mkOr(ast, ctx.mkEq(ctx.mkIntConst(constructVarName(mem)), ctx.mkInt(order)))) - + // Makes all the current predicates true - solver.add(ctx.mkEq(mkAnd(predicates.toSeq: _*), ctx.mkTrue())) - + solver.add(ctx.mkEq(predicates, ctx.mkTrue())) + // Asserts the state of the lock currently, and checks if its possible for the mem to NOT be in the expected lock states - solver.add(mkAnd(env(mem), ctx.mkNot(stateAST))) + solver.add(mkAnd(ctx, env(mem), ctx.mkNot(stateAST))) val check = solver.check() solver.reset() check } - + private def makeEquals(mem: LockArg, lockState: LockState): Z3AST = { ctx.mkEq(ctx.mkIntConst(constructVarName(mem)), ctx.mkInt(lockState.order)) } - + private def constructVarName(mem: LockArg): String = { mem.id + (if (mem.evar.isDefined) "[" + mem.evar.get.id.v + "]" else "") } - - private def checkAcquired(mem: Id, expr: Expr, env: Environment[LockArg, Z3AST]): Environment[LockArg, Z3AST] = { + + private def checkAcquired(mem: Id, expr: Expr, env: Environment[LockArg, Z3AST], predicates: Z3BoolExpr): Environment[LockArg, Z3AST] = { if (lockTypeMap(currentMod)(mem).equals(Specific) && !expr.isInstanceOf[EVar]) { throw new RuntimeException("We expect the argument in the memory access to be a variable") } checkState(if (lockTypeMap(currentMod)(mem).equals(General)) LockArg(mem, None) else LockArg(mem, Some(expr.asInstanceOf[EVar])), - env, + env, + predicates, Acquired.order) match { case Z3Status.SATISFIABLE => @@ -227,12 +185,4 @@ class LockConstraintChecker(lockMap: Map[Id, Set[LockArg]], lockTypeMap: Map[Id, env } } - - /** Like [[Z3Context.mkAnd]], but automatically casts inputs to [[Z3BoolExpr]]s. */ - private def mkAnd(expressions: Z3AST *): Z3BoolExpr = - ctx.mkAnd(expressions.map(ast => ast.asInstanceOf[Z3BoolExpr]):_*) - - /** Like [[Z3Context.mkImplies]], but automatically casts inputs to [[Z3BoolExpr]]s. */ - private def mkImplies(t1: Z3AST, t2: Z3AST): Z3BoolExpr = - ctx.mkImplies(t1.asInstanceOf[Z3BoolExpr], t2.asInstanceOf[Z3BoolExpr]) } \ No newline at end of file diff --git a/src/main/scala/pipedsl/typechecker/LockRegionChecker.scala b/src/main/scala/pipedsl/typechecker/LockRegionChecker.scala index 3b8d38cd..4c49df36 100644 --- a/src/main/scala/pipedsl/typechecker/LockRegionChecker.scala +++ b/src/main/scala/pipedsl/typechecker/LockRegionChecker.scala @@ -6,6 +6,7 @@ import pipedsl.common.{Locks, Syntax} import pipedsl.common.Syntax._ import pipedsl.typechecker.Environments._ import pipedsl.typechecker.TypeChecker.TypeChecks +import pipedsl.analysis.TypeAnalysis /** * This checks that all lock reservations happen only within a valid lock region. @@ -14,8 +15,9 @@ import pipedsl.typechecker.TypeChecker.TypeChecks * - Checks: That all lock "reserve" statements occur inside the appropriate lock region. * - Checks: That all lock regions are well formed according to the above. */ -object LockRegionChecker extends TypeChecks[Id, LockState] { +class LockRegionChecker(prog:Prog) extends TypeChecks[Id, LockState] { + val typeAnalysis = TypeAnalysis.get(prog) override def emptyEnv(): Environment[Id, LockState] = Environments.EmptyLockEnv //Functions can't interact with locks or memories right now. @@ -23,7 +25,8 @@ object LockRegionChecker extends TypeChecks[Id, LockState] { override def checkFunc(f: FuncDef, env: Environment[Id, LockState]): Environment[Id, LockState] = env override def checkModule(m: ModuleDef, env: Environment[Id, LockState]): Environment[Id, LockState] = { - val nenv = m.modules.foldLeft[Environment[Id, LockState]](env)( (e, m) => m.typ match { + // TODO: Do we need this now that we have attributes? + val nenv = m.modules.foldLeft[Environment[Id, LockState]](env)( (e, m) => typeAnalysis.typeCheck(m.name) match { case TMemType(_, _, _, _) => e.add(m.name, Free) case TModType(_, _, _, _) => e.add(m.name, Free) case _ => throw UnexpectedCase(m.pos) @@ -87,7 +90,7 @@ object LockRegionChecker extends TypeChecks[Id, LockState] { throw InvalidLockState(c.pos, mem.id.v, env(mem.id), Acquired) } env - case Syntax.CEmpty => env + case Syntax.CEmpty() => env case _ => env } diff --git a/src/main/scala/pipedsl/typechecker/LockWellformedChecker.scala b/src/main/scala/pipedsl/typechecker/LockWellformedChecker.scala index fe8fba8c..1efdfb2e 100644 --- a/src/main/scala/pipedsl/typechecker/LockWellformedChecker.scala +++ b/src/main/scala/pipedsl/typechecker/LockWellformedChecker.scala @@ -56,7 +56,7 @@ class LockWellformedChecker() { throw MalformedLockTypes("Memory modules can only have location specific locks or general locks, but not both") else updateLockTypeMap(mem.id, getLockType(mem)) lockArgs + mem - case _ => lockArgs + case _ => lockArgs } private def getLockType(lockArg: LockArg): LockType = lockArg.evar match { diff --git a/src/main/scala/pipedsl/typechecker/PredicateGenerator.scala b/src/main/scala/pipedsl/typechecker/PredicateGenerator.scala index cf723e45..249a908f 100644 --- a/src/main/scala/pipedsl/typechecker/PredicateGenerator.scala +++ b/src/main/scala/pipedsl/typechecker/PredicateGenerator.scala @@ -1,83 +1,49 @@ -package pipedsl.typechecker +/**package pipedsl.typechecker -import com.microsoft.z3.{AST => Z3AST, Expr => Z3Expr, BoolExpr => Z3BoolExpr, Context => Z3Context} +import com.microsoft.z3.{AST => Z3AST, BoolExpr => Z3BoolExpr, Context => Z3Context, Expr => Z3Expr} +import org.bitbucket.inkytonik.kiama.attribution.Attribution import pipedsl.common.Syntax -import pipedsl.common.Syntax.{BoolOp, BoolUOp, CSeq, Command, EVar, EqOp, Expr} +import pipedsl.common.Syntax.{BoolOp, BoolUOp, CSeq, Command, EVar, EqOp, Expr, ProgramNode} -class PredicateGenerator(ctx: Z3Context) { +class PredicateGenerator(ctx: Z3Context) extends Attribution { private val intArray = ctx.mkArraySort(ctx.getIntSort, ctx.getIntSort) - - def generatePostcondition(c: Command, preCondition: Set[Z3AST]): Set[Z3AST] = - c match { - case CSeq(c1, c2) => - val p1 = generatePostcondition(c1, preCondition) - generatePostcondition(c2, p1) - case Syntax.CTBar(c1, c2) => - val p1 = generatePostcondition(c1, preCondition) - generatePostcondition(c2, p1) - case Syntax.CIf(cond, cons, alt) => + def abstractInterpExpr(e: Expr): Option[Z3Expr] = e match { + case evar: EVar => Some(declareConstant(evar)) + case Syntax.EInt(v, base, bits) => Some(ctx.mkInt(v)) + case Syntax.EBool(v) => if (v) Some(ctx.mkTrue()) else Some(ctx.mkFalse()) + case Syntax.EUop(op, ex) => + val absex = abstractInterpExpr(ex) + (op, absex) match { + case (BoolUOp(o), Some(v)) if o == "!" => Some(ctx.mkNot(v.asInstanceOf[Z3BoolExpr])) + case _ => None + } + case Syntax.EBinop(op, e1, e2) => + val abse1 = abstractInterpExpr(e1) + val abse2 = abstractInterpExpr(e2) + (op, abse1, abse2) match { + case (EqOp(o), Some(v1), Some(v2)) if o == "==" => Some(ctx.mkEq(v1, v2)) + case (EqOp(o), Some(v1), Some(v2)) if o == "!=" => Some(ctx.mkNot(ctx.mkEq(v1, v2))) + case (BoolOp(o, _), Some(v1), Some(v2)) if o == "&&" => + Some(ctx.mkAnd(v1.asInstanceOf[Z3BoolExpr], v2.asInstanceOf[Z3BoolExpr])) + case (BoolOp(o, _), Some(v1), Some(v2)) if o == "||" => + Some(ctx.mkOr(v1.asInstanceOf[Z3BoolExpr], v2.asInstanceOf[Z3BoolExpr])) + case _ => None + } + case Syntax.ETernary(cond, tval, fval) => val abscond = abstractInterpExpr(cond) - abscond match { - case Some(value: Z3BoolExpr) => - generatePostcondition(cons, preCondition + value) - .intersect(generatePostcondition(alt, preCondition + ctx.mkNot(value))) - case None => - generatePostcondition(cons, preCondition) - .intersect(generatePostcondition(alt, preCondition)) + val abstval = abstractInterpExpr(tval) + val absfval = abstractInterpExpr(fval) + (abscond, abstval, absfval) match { + case (Some(vcond), Some(vtval), Some(vfval)) => + Some(ctx.mkITE(vcond.asInstanceOf[Z3BoolExpr], vtval, vfval)) + case _ => + None } - case Syntax.CAssign(lhs, rhs) => (lhs, abstractInterpExpr(rhs)) match { - case (evar: EVar, Some(value)) => - val declare = ctx.mkEq(declareConstant(evar), value) - preCondition + declare - case (evar: EVar, None) => preCondition - case _ => preCondition - } - case Syntax.CRecv(lhs, rhs) => (lhs, abstractInterpExpr(rhs)) match { - case (evar: EVar, Some(value)) => - val declare = ctx.mkEq(declareConstant(evar), value) - preCondition + declare - case (evar: EVar, None) => preCondition - case _ => preCondition - } - case _ => preCondition + case _ => None } - def abstractInterpExpr(e: Expr): Option[Z3Expr] = e match { - case evar: EVar => Some(declareConstant(evar)) - case Syntax.EInt(v, base, bits) => Some(ctx.mkInt(v)) - case Syntax.EBool(v) => if (v) Some(ctx.mkTrue()) else Some(ctx.mkFalse()) - case Syntax.EUop(op, ex) => - val absex = abstractInterpExpr(ex) - (op, absex) match { - case (BoolUOp(o), Some(v)) if o == "!" => Some(ctx.mkNot(v.asInstanceOf[Z3BoolExpr])) - case _ => None - } - case Syntax.EBinop(op, e1, e2) => - val abse1 = abstractInterpExpr(e1) - val abse2 = abstractInterpExpr(e2) - (op, abse1, abse2) match { - case (EqOp(o), Some(v1), Some(v2)) if o == "==" => Some(ctx.mkEq(v1, v2)) - case (EqOp(o), Some(v1), Some(v2)) if o == "!=" => Some(ctx.mkNot(ctx.mkEq(v1, v2))) - case (BoolOp(o, _), Some(v1), Some(v2)) if o == "&&" => - Some(ctx.mkAnd(v1.asInstanceOf[Z3BoolExpr], v2.asInstanceOf[Z3BoolExpr])) - case (BoolOp(o, _), Some(v1), Some(v2)) if o == "||" => - Some(ctx.mkOr(v1.asInstanceOf[Z3BoolExpr], v2.asInstanceOf[Z3BoolExpr])) - case _ => None - } - case Syntax.ETernary(cond, tval, fval) => - val abscond = abstractInterpExpr(cond) - val abstval = abstractInterpExpr(tval) - val absfval = abstractInterpExpr(fval) - (abscond, abstval, absfval) match { - case (Some(vcond), Some(vtval), Some(vfval)) => - Some(ctx.mkITE(vcond.asInstanceOf[Z3BoolExpr], vtval, vfval)) - case _ => - None - } - case _ => None - } - + def declareConstant(evar: EVar): Z3Expr = evar.typ match { case Some(value) => value match { @@ -89,3 +55,4 @@ class PredicateGenerator(ctx: Z3Context) { case None => throw new RuntimeException("Missing type") } } + */ diff --git a/src/main/scala/pipedsl/typechecker/SpeculationChecker.scala b/src/main/scala/pipedsl/typechecker/SpeculationChecker.scala index ceb34966..bd9e42d9 100644 --- a/src/main/scala/pipedsl/typechecker/SpeculationChecker.scala +++ b/src/main/scala/pipedsl/typechecker/SpeculationChecker.scala @@ -47,7 +47,7 @@ object SpeculationChecker extends TypeChecks[Id, Type] { } else { specVarsT } - case CRecv(lhs, _) => lhs match { + case CRecv(lhs, _, _) => lhs match { case EMemAccess(_, _) if specVars.nonEmpty => throw UnresolvedSpeculation(lhs.pos, "Memory Write") case _ => specVars diff --git a/src/main/scala/pipedsl/typechecker/TimingTypeChecker.scala b/src/main/scala/pipedsl/typechecker/TimingTypeChecker.scala index e1cb1efb..b62c4a1e 100644 --- a/src/main/scala/pipedsl/typechecker/TimingTypeChecker.scala +++ b/src/main/scala/pipedsl/typechecker/TimingTypeChecker.scala @@ -1,3 +1,5 @@ + +/** package pipedsl.typechecker import pipedsl.common.Syntax._ @@ -70,12 +72,12 @@ object TimingTypeChecker extends TypeChecks[Id, Type] { val (vt, nvt) = checkCommand(cons, vars, nextVars) val (vf, nvf) = checkCommand(alt, vars, nextVars) (vt.intersect(vf), nvt.intersect(nvf)) - case CAssign(lhs, rhs) => + case CAssign(lhs, rhs, _) => if (checkExpr(rhs, vars) != Latency.Combinational) { throw UnexpectedAsyncReference(rhs.pos, rhs.toString) } (vars + lhs.id, nextVars) - case CRecv(lhs, rhs) => + case CRecv(lhs, rhs, _) => val rhsLat = checkExpr(rhs, vars) val lhsLat = checkExpr(lhs, vars, isRhs = false) (lhs, rhs) match { @@ -115,7 +117,7 @@ object TimingTypeChecker extends TypeChecks[Id, Type] { case CExpr(exp) => checkExpr(exp, vars) (vars, nextVars) - case Syntax.CEmpty => (vars, nextVars) + case Syntax.CEmpty() => (vars, nextVars) case CPrint(evar) => checkExpr(evar, vars) (vars, nextVars) @@ -176,3 +178,4 @@ object TimingTypeChecker extends TypeChecks[Id, Type] { override def checkCircuit(c: Circuit, env: Environment[Id, Type]): Environment[Id, Type] = env } +*/ \ No newline at end of file diff --git a/src/test/scala/pipedsl/MainSuite.scala b/src/test/scala/pipedsl/MainSuite.scala index 06cae067..ab5914b3 100644 --- a/src/test/scala/pipedsl/MainSuite.scala +++ b/src/test/scala/pipedsl/MainSuite.scala @@ -274,11 +274,13 @@ class MainSuite extends AnyFunSuite { } - test("Lock Typechecking Tests") { - val testDir = new File("src/test/tests/typecheckTests") + + val testDir = new File("src/test/tests/typecheckTests") for (file <- testDir.listFiles().filter(f => f.isFile)) { - testTypecheck(testDir, file) + test(file.toString()) { + testTypecheck(testDir, file) + } } - } + } diff --git a/src/test/tests/typecheckTests/solutions/type-inference-basic-pass.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-basic-pass.typechecksol new file mode 100644 index 00000000..9fb4ec93 --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-basic-pass.typechecksol @@ -0,0 +1 @@ +Passed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/solutions/type-inference-bit-width-tests.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-bit-width-tests.typechecksol new file mode 100644 index 00000000..9fb4ec93 --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-bit-width-tests.typechecksol @@ -0,0 +1 @@ +Passed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/solutions/type-inference-fail-base-type.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-fail-base-type.typechecksol new file mode 100644 index 00000000..e4d7046a --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-fail-base-type.typechecksol @@ -0,0 +1 @@ +Failed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/solutions/type-inference-fail-bit-too-small-memAccessToosmall.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-fail-bit-too-small-memAccessToosmall.typechecksol new file mode 100644 index 00000000..e4d7046a --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-fail-bit-too-small-memAccessToosmall.typechecksol @@ -0,0 +1 @@ +Failed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/solutions/type-inference-fail-bit-too-small-minus.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-fail-bit-too-small-minus.typechecksol new file mode 100644 index 00000000..e4d7046a --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-fail-bit-too-small-minus.typechecksol @@ -0,0 +1 @@ +Failed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/solutions/type-inference-fail-bit-too-small-mult.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-fail-bit-too-small-mult.typechecksol new file mode 100644 index 00000000..e4d7046a --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-fail-bit-too-small-mult.typechecksol @@ -0,0 +1 @@ +Failed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/solutions/type-inference-fail-bit-too-small-plus.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-fail-bit-too-small-plus.typechecksol new file mode 100644 index 00000000..e4d7046a --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-fail-bit-too-small-plus.typechecksol @@ -0,0 +1 @@ +Failed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/solutions/type-inference-fail-boolBinOp.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-fail-boolBinOp.typechecksol new file mode 100644 index 00000000..e4d7046a --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-fail-boolBinOp.typechecksol @@ -0,0 +1 @@ +Failed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/solutions/type-inference-fail-call-args.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-fail-call-args.typechecksol new file mode 100644 index 00000000..e4d7046a --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-fail-call-args.typechecksol @@ -0,0 +1 @@ +Failed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/solutions/type-inference-fail-call.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-fail-call.typechecksol new file mode 100644 index 00000000..e4d7046a --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-fail-call.typechecksol @@ -0,0 +1 @@ +Failed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/solutions/type-inference-fail-eqBinOp.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-fail-eqBinOp.typechecksol new file mode 100644 index 00000000..e4d7046a --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-fail-eqBinOp.typechecksol @@ -0,0 +1 @@ +Failed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/solutions/type-inference-fail-func-app-arg.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-fail-func-app-arg.typechecksol new file mode 100644 index 00000000..e4d7046a --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-fail-func-app-arg.typechecksol @@ -0,0 +1 @@ +Failed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/solutions/type-inference-fail-funcApp.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-fail-funcApp.typechecksol new file mode 100644 index 00000000..e4d7046a --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-fail-funcApp.typechecksol @@ -0,0 +1 @@ +Failed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/solutions/type-inference-fail-numBinOp.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-fail-numBinOp.typechecksol new file mode 100644 index 00000000..e4d7046a --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-fail-numBinOp.typechecksol @@ -0,0 +1 @@ +Failed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/solutions/type-inference-fail-ternary.typechecksol b/src/test/tests/typecheckTests/solutions/type-inference-fail-ternary.typechecksol new file mode 100644 index 00000000..e4d7046a --- /dev/null +++ b/src/test/tests/typecheckTests/solutions/type-inference-fail-ternary.typechecksol @@ -0,0 +1 @@ +Failed \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-basic-pass.pdl b/src/test/tests/typecheckTests/type-inference-basic-pass.pdl new file mode 100644 index 00000000..bf6f5c44 --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-basic-pass.pdl @@ -0,0 +1,143 @@ + +def helper1(a: int<32>, b:bool, c: String): int<32> { + d = a + 1<32>; + e = b && false; + if (e) { + f = c; + } + return d; +} + +def helper2(a:bool, b: bool): bool { + c = a && b; + return c; +} + +pipe test1(input: int<32>)[rf: int<32>[32]] { + a = input; + b = true; + c = b; + if (c) { + d = a + 5<32>; + } +} + +pipe test2(input: int<32>)[rf: int<32>[32]] { + a = input; + b = true; + c = b; + if (c) { + d = a + 5<32>; + } else { + d = b; + } +} + +pipe test3()[] { + a = true; + b = a; + c = a || b; + d = c || b; + if (c) { + e = 1<32>; + } + if (d) { + f = 1<32>; + } +} + +pipe test4()[] { + a = true; + b = false; + c = a == b; + d = 5<32>; + e = 6<32>; + f = e==d; + if (c) { + + } + if (f) { + + } +} + +pipe test5()[] { + a = 5<32>; + b = 6<32>; + c = a + b; + d = c * b; + e = c / d; + f = e % d; + g = e - f; + h = g > f; + i = g <= f; + j = h && i; + if (j) { + + } +} + + +pipe test6(input: int<32>)[rf: int<32>[32]] { + a = input; + b = true; + c = b; + if (c) { + d = a + 5<32>; + } else { + d = b; + } +} + +pipe test7()[rf: int<32>[32]] { + a = 1<32>; + b = a; + c = rf[a]; + d = c == a; + e = d && d; +} + +pipe test8()[rf: int<32>[32]] { + a = 5<32>; + b = true; + c = false; + if (helper2(helper2(b, c),b)) { + d = a; + } + f = a; + s = "yES"; + e = helper1(f, helper2(b, c), s); + if (e==f) { + + } +} + +pipe test9()[rf: int<32>[32]] { + a = true || false; + b = a; + c = b ; + d = b && c; + e = (b) ? d : c; + if (!e) { + + } +} + +pipe test10(a: bool, b: int<32>)[rf: int<32>[32]]: int<32> { + output(5<32>); +} + +pipe test11()[rf: int<32>[32]] { + a = 5<32>; + b = 10<32>; + c = a + b; + d = false; + e = true; + f = e || d; + g = call test10(f, c); + h = g == b; +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-bit-width-tests.pdl b/src/test/tests/typecheckTests/type-inference-bit-width-tests.pdl new file mode 100644 index 00000000..550a7a6a --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-bit-width-tests.pdl @@ -0,0 +1,50 @@ + +def helper1(a: int<32>, b:bool, c: String): int<32> { + d = a + 1; + f = d + 4; + if (f == d) { + return f; + } +} + +def helper2(a:bool, b: bool): bool { + c = a && b; + return c; +} + +pipe test1(input: int<32>)[rf: int<32>[32]] { + a = 6 * 6; + int<32> b = a; + int<32> c = a + b; +} + +pipe test2(input: int<32>)[rf: int<32>[32]] { + a = 1; + b = rf[a]; +} + +pipe test3(input: int<32>)[rf: int<32>[32]] { + a = 1; + int<32> b = a << 4; + int<5> c = a << 4; +} + +pipe test4(input: int<32>)[rf: int<32>[32]] { + a = 15<32>; + int<32> b = a{0:8}; +} + +pipe test5()[] { + a = 6 * 6; + int<6> b = a; + int<64> c = helper1(a, true, "hi"); +} + +pipe test6()[] { + a = 6 - 6; + int<3> b = a; +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-fail-base-type.pdl b/src/test/tests/typecheckTests/type-inference-fail-base-type.pdl new file mode 100644 index 00000000..72889371 --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-fail-base-type.pdl @@ -0,0 +1,10 @@ +pipe test1(input: int<32>)[rf: int<32>[32]] { + a = input + 2<32>; + if (a) { + + } +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-fail-bit-too-small-memAccessToosmall.pdl b/src/test/tests/typecheckTests/type-inference-fail-bit-too-small-memAccessToosmall.pdl new file mode 100644 index 00000000..dd313404 --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-fail-bit-too-small-memAccessToosmall.pdl @@ -0,0 +1,9 @@ + +pipe test6()[rf: int<32>[32]] { + int<64> a = 6 * 6; + c = rf[a]; +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-fail-bit-too-small-minus.pdl b/src/test/tests/typecheckTests/type-inference-fail-bit-too-small-minus.pdl new file mode 100644 index 00000000..1149577f --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-fail-bit-too-small-minus.pdl @@ -0,0 +1,9 @@ + +pipe test6()[] { + a = 6 - 6; + int<2> b = a; +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-fail-bit-too-small-mult.pdl b/src/test/tests/typecheckTests/type-inference-fail-bit-too-small-mult.pdl new file mode 100644 index 00000000..737be003 --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-fail-bit-too-small-mult.pdl @@ -0,0 +1,9 @@ + +pipe test6()[] { + a = 6 * 6; + int<5> b = a; +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-fail-bit-too-small-plus.pdl b/src/test/tests/typecheckTests/type-inference-fail-bit-too-small-plus.pdl new file mode 100644 index 00000000..deabf477 --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-fail-bit-too-small-plus.pdl @@ -0,0 +1,9 @@ + +pipe test6()[] { + a = 6 + 6; + int<2> b = a; +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-fail-boolBinOp.pdl b/src/test/tests/typecheckTests/type-inference-fail-boolBinOp.pdl new file mode 100644 index 00000000..3a302da6 --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-fail-boolBinOp.pdl @@ -0,0 +1,9 @@ + +pipe test1(input: int<32>)[rf: int<32>[32]] { + a = input; + b = a || a; +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-fail-call-args.pdl b/src/test/tests/typecheckTests/type-inference-fail-call-args.pdl new file mode 100644 index 00000000..379def08 --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-fail-call-args.pdl @@ -0,0 +1,18 @@ +pipe test10(a: bool, b: int<32>)[rf: int<32>[32]]: int<32> { + output(5<32>); +} + +pipe test11()[rf: int<32>[32]] { + a = 5<32>; + b = 10<32>; + c = a + b; + d = false; + e = true; + f = e || d; + g = call test10(c, c); + h = g == b; +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-fail-call.pdl b/src/test/tests/typecheckTests/type-inference-fail-call.pdl new file mode 100644 index 00000000..6bc02fad --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-fail-call.pdl @@ -0,0 +1,18 @@ +pipe test10(a: bool, b: int<32>)[rf: int<32>[32]]: int<32> { + output(5<32>); +} + +pipe test11()[rf: int<32>[32]] { + a = 5<32>; + b = 10<32>; + c = a + b; + d = false; + e = true; + f = e || d; + g = call test10(f, c); + h = g == d; +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-fail-eqBinOp.pdl b/src/test/tests/typecheckTests/type-inference-fail-eqBinOp.pdl new file mode 100644 index 00000000..0d4bae05 --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-fail-eqBinOp.pdl @@ -0,0 +1,8 @@ +pipe test1(input: int<32>)[rf: int<32>[32]] { + a = true; + b = a == input; +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-fail-func-app-arg.pdl b/src/test/tests/typecheckTests/type-inference-fail-func-app-arg.pdl new file mode 100644 index 00000000..c2bb8609 --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-fail-func-app-arg.pdl @@ -0,0 +1,12 @@ +def func(a: bool, b: int<32>): bool { + return b; +} + +pipe test1(input: int<32>)[rf: int<32>[32]] { + a = true; + b = func(a, a); +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-fail-funcApp.pdl b/src/test/tests/typecheckTests/type-inference-fail-funcApp.pdl new file mode 100644 index 00000000..f69d3e87 --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-fail-funcApp.pdl @@ -0,0 +1,12 @@ +def func(a: bool, b: int<32>): bool { + return b; +} + +pipe test1(input: int<32>)[rf: int<32>[32]] { + a = true; + b = func(a, input) + 5<32>; +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-fail-numBinOp.pdl b/src/test/tests/typecheckTests/type-inference-fail-numBinOp.pdl new file mode 100644 index 00000000..3096b3d3 --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-fail-numBinOp.pdl @@ -0,0 +1,8 @@ +pipe test1(input: int<32>)[rf: int<32>[32]] { + a = true; + b = a + a; +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file diff --git a/src/test/tests/typecheckTests/type-inference-fail-ternary.pdl b/src/test/tests/typecheckTests/type-inference-fail-ternary.pdl new file mode 100644 index 00000000..e635be6e --- /dev/null +++ b/src/test/tests/typecheckTests/type-inference-fail-ternary.pdl @@ -0,0 +1,9 @@ +pipe test1(input: int<32>)[rf: int<32>[32]] { + a = true; + b = input; + c = (b) ? a : b; +} + +circuit { + r = memory(int<32>, 32); +} \ No newline at end of file