I made my own target python file for the Genesys2 board, and I am trying to perform rowhammer tests on it but the sdram_init procedure always fails. As far as I am aware, all peripherals and memory have been configured correctly, and the modules are the correct ones as specified by the Digilent genesys2 reference guide.
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write leveling:
tCK equivalent taps: 32
Cmd/Clk scan (0-16)
|Cmd/Clk delay: 0
m0: |00000000000000111111111111110000| delay: 14
m1: |00000000000000111111111111110000| delay: 14
m2: |00000000000001111111111110000000| delay: 13
m3: |00000000000011111111111110000000| delay: 12
AMW: |00000000000000111111111110000000| total: 11
Cmd/Clk delay: 1
m0: |00000000000000011111111111111000| delay: 15
m1: |00000000000000011111111111111000| delay: 15
m2: |00000000000000111111111111000000| delay: 14
m3: |00000000000011111111111111000000| delay: 12
AMW: |00000000000000011111111111000000| total: 11
Cmd/Clk delay: 2
m0: |00000000000000001111111111111100| delay: 16
m1: |00000000000000001111111111111100| delay: 16
m2: |00000000000000011111111111100000| delay: 15
m3: |00000000000001111111111111100000| delay: 13
AMW: |00000000000000001111111111100000| total: 11
Cmd/Clk delay: 3
m0: |00000000000000000111111111111100| delay: 17
m1: |00000000000000000111111111111110| delay: 17
m2: |00000000000000001111111111110000| delay: 16
m3: |00000000000000111111111111110000| delay: 14
AMW: |00000000000000000111111111110000| total: 11
Cmd/Clk delay: 4
m0: |00000000000000000011111111111110| delay: 18
m1: |00000000000000000011111111111111| delay: 18
m2: |00000000000000000111111111111000| delay: 17
m3: |00000000000000011111111111111000| delay: 15
AMW: |00000000000000000011111111111000| total: 11
Cmd/Clk delay: 5
m0: |10000000000000000001111111111111| delay: 19
m1: |10000000000000000001111111111111| delay: 19
m2: |00000000000000000011111111111100| delay: 18
m3: |00000000000000001111111111111100| delay: 16
AMW: |00000000000000000001111111111100| total: 11
Cmd/Clk delay: 6
m0: |11000000000000000000111111111111| delay: 20
m1: |11000000000000000000111111111111| delay: 20
m2: |00000000000000000001111111111111| delay: 19
m3: |00000000000000000111111111111110| delay: 17
AMW: |00000000000000000000111111111110| total: 11
Cmd/Clk delay: 7
m0: |11100000000000000000011111111111| delay: 21
m1: |11100000000000000000011111111111| delay: 21
m2: |10000000000000000000111111111111| delay: 20
m3: |00000000000000000011111111111111| delay: 18
AMW: |00000000000000000000011111111111| total: 11
Cmd/Clk delay: 8
m0: |11110000000000000000001111111111| delay: 22
m1: |11110000000000000000001111111111| delay: 22
m2: |11000000000000000000011111111111| delay: 21
m3: |10000000000000000001111111111111| delay: 19
AMW: |10000000000000000000001111111111| total: 11
Cmd/Clk delay: 9
m0: |11111000000000000000000111111111| delay: 23
m1: |11111100000000000000000111111111| delay: 23
m2: |11100000000000000000001111111111| delay: 22
m3: |11000000000000000000111111111111| delay: 20
AMW: |11000000000000000000000111111111| total: 11
Cmd/Clk delay: 10
m0: |11111100000000000000000011111111| delay: 24
m1: |11111100000000000000000011111111| delay: 24
m2: |11110000000000000000000111111111| delay: 23
m3: |11100000000000000000011111111111| delay: 21
AMW: |11100000000000000000000011111111| total: 11
Cmd/Clk delay: 11
m0: |11111110000000000000000011111111| delay: 24
m1: |11111110000000000000000011111111| delay: 24
m2: |11111000000000000000000011111111| delay: 24
m3: |11110000000000000000001111111111| delay: 22
AMW: |11110000000000000000000011111111| total: 12
Cmd/Clk delay: 12
m0: |11111111000000000000000001111111| delay: -
m1: |11111111100000000000000011111111| delay: 00
m2: |11111100000000000000000011111111| delay: 24
m3: |11111000000000000000000111111111| delay: 23
AMW: |11111000000000000000000001111111| total: -1
Cmd/Clk delay: 13
m0: |11111111100000000000000000111111| delay: 00
m1: |11111111110000000000000001111111| delay: 00
m2: |11111110000000000000000011111111| delay: 24
m3: |11111100000000000000000011111111| delay: 24
AMW: |11111100000000000000000000111111| total: 12
Cmd/Clk delay: 14
m0: |11111111110000000000000000111111| delay: 00
m1: |11111111110000000000000000111111| delay: 00
m2: |11111111000000000000000011111111| delay: -
m3: |11111110000000000000000011111111| delay: 24
AMW: |11111110000000000000000000111111| total: -1
Cmd/Clk delay: 15
m0: |11111111111000000000000000011111| delay: 00
m1: |11111111111000000000000000011111| delay: 00
m2: |11111111100000000000000001111111| delay: 00
m3: |11111111000000000000000001111111| delay: -
AMW: |11111111000000000000000000011111| total: -1
| best: 3
cdly scores: | 848 896 960 960 928 896 832 768 704 640 576 544 -1 256 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -|
Setting Cmd/Clk delay to 3 taps.
Data scan:
m0: |00000000000000000111111111111100| delay: 17
m1: |00000000000000000111111111111110| delay: 17
m2: |00000000000000001111111111110000| delay: 16
m3: |00000000000000111111111111110000| delay: 14
AMW: |00000000000000000111111111110000| total: 11
Write latency calibration:
m0 wb00:
m0, b00: |00000000000000000000000000000000|
m0, b01: |00000000000000000000000000000000|
m0, b02: |00000000000000000000000000000000|
m0, b03: |00000000000000000000000000000000|
m0, b04: |00000000000000000000000000000000|
m0, b05: |00000000000000000000000000000000|
m0, b06: |00000000000000000000000000000000|
m0, b07: |00000000000000000000000000000000|
m0 wb02:
m0, b00: |00000000000000000000000000000000|
m0, b01: |00000000000000000000000000000000|
m0, b02: |00000000000000000000000000000000|
m0, b03: |00000000000000000000000000000000|
m0, b04: |00000000000000000000000000000000|
m0, b05: |00000000000000000000000000000000|
m0, b06: |00000000000000000000000000000000|
m0, b07: |00000000000000000000000000000000|
m0 wb04:
m0, b00: |00000000000000000000000000000000|
m0, b01: |00000000000000000000000000000000|
m0, b02: |00000000000000000000000000000000|
m0, b03: |00000000000000000000000000000000|
m0, b04: |00000000000000000000000000000000|
m0, b05: |00000000000000000000000000000000|
m0, b06: |00000000000000000000000000000000|
m0, b07: |00000000000000000000000000000000|
m0 wb06:
m0, b00: |00000000000000000000000000000000|
m0, b01: |00000000000000000000000000000000|
m0, b02: |00000000000000000000000000000000|
m0, b03: |00000000000000000000000000000000|
m0, b04: |00000000000000000000000000000000|
m0, b05: |00000000000000000000000000000000|
m0, b06: |00000000000000000000000000000000|
m0, b07: |00000000000000000000000000000000|
m0:0
m1 wb00:
m1, b00: |00000000000000000000000000000000|
m1, b01: |00000000000000000000000000000000|
m1, b02: |00000000000000000000000000000000|
m1, b03: |00000000000000000000000000000000|
m1, b04: |00000000000000000000000000000000|
m1, b05: |00000000000000000000000000000000|
m1, b06: |00000000000000000000000000000000|
m1, b07: |00000000000000000000000000000000|
m1 wb02:
m1, b00: |00000000000000000000000000000000|
m1, b01: |00000000000000000000000000000000|
m1, b02: |00000000000000000000000000000000|
m1, b03: |00000000000000000000000000000000|
m1, b04: |00000000000000000000000000000000|
m1, b05: |00000000000000000000000000000000|
m1, b06: |00000000000000000000000000000000|
m1, b07: |00000000000000000000000000000000|
m1 wb04:
m1, b00: |00000000000000000000000000000000|
m1, b01: |00000000000000000000000000000000|
m1, b02: |00000000000000000000000000000000|
m1, b03: |00000000000000000000000000000000|
m1, b04: |00000000000000000000000000000000|
m1, b05: |00000000000000000000000000000000|
m1, b06: |00000000000000000000000000000000|
m1, b07: |00000000000000000000000000000000|
m1 wb06:
m1, b00: |00000000000000000000000000000000|
m1, b01: |00000000000000000000000000000000|
m1, b02: |00000000000000000000000000000000|
m1, b03: |00000000000000000000000000000000|
m1, b04: |00000000000000000000000000000000|
m1, b05: |00000000000000000000000000000000|
m1, b06: |00000000000000000000000000000000|
m1, b07: |00000000000000000000000000000000|
m1:0
m2 wb00:
m2, b00: |00000000000000000000000000000000|
m2, b01: |00000000000000000000000000000000|
m2, b02: |00000000000000000000000000000000|
m2, b03: |00000000000000000000000000000000|
m2, b04: |00000000000000000000000000000000|
m2, b05: |00000000000000000000000000000000|
m2, b06: |00000000000000000000000000000000|
m2, b07: |00000000000000000000000000000000|
m2 wb02:
m2, b00: |00000000000000000000000000000000|
m2, b01: |00000000000000000000000000000000|
m2, b02: |00000000000000000000000000000000|
m2, b03: |00000000000000000000000000000000|
m2, b04: |00000000000000000000000000000000|
m2, b05: |00000000000000000000000000000000|
m2, b06: |00000000000000000000000000000000|
m2, b07: |00000000000000000000000000000000|
m2 wb04:
m2, b00: |00000000000000000000000000000000|
m2, b01: |00000000000000000000000000000000|
m2, b02: |00000000000000000000000000000000|
m2, b03: |00000000000000000000000000000000|
m2, b04: |00000000000000000000000000000000|
m2, b05: |00000000000000000000000000000000|
m2, b06: |00000000000000000000000000000000|
m2, b07: |00000000000000000000000000000000|
m2 wb06:
m2, b00: |00000000000000000000000000000000|
m2, b01: |00000000000000000000000000000000|
m2, b02: |00000000000000000000000000000000|
m2, b03: |00000000000000000000000000000000|
m2, b04: |00000000000000000000000000000000|
m2, b05: |00000000000000000000000000000000|
m2, b06: |00000000000000000000000000000000|
m2, b07: |00000000000000000000000000000000|
m2:0
m3 wb00:
m3, b00: |00000000000000000000000000000000|
m3, b01: |00000000000000000000000000000000|
m3, b02: |00000000000000000000000000000000|
m3, b03: |00000000000000000000000000000000|
m3, b04: |00000000000000000000000000000000|
m3, b05: |00000000000000000000000000000000|
m3, b06: |00000000000000000000000000000000|
m3, b07: |00000000000000000000000000000000|
m3 wb02:
m3, b00: |00000000000000000000000000000000|
m3, b01: |00000000000000000000000000000000|
m3, b02: |00000000000000000000000000000000|
m3, b03: |00000000000000000000000000000000|
m3, b04: |00000000000000000000000000000000|
m3, b05: |00000000000000000000000000000000|
m3, b06: |00000000000000000000000000000000|
m3, b07: |00000000000000000000000000000000|
m3 wb04:
m3, b00: |00000000000000000000000000000000|
m3, b01: |00000000000000000000000000000000|
m3, b02: |00000000000000000000000000000000|
m3, b03: |00000000000000000000000000000000|
m3, b04: |00000000000000000000000000000000|
m3, b05: |00000000000000000000000000000000|
m3, b06: |00000000000000000000000000000000|
m3, b07: |00000000000000000000000000000000|
m3 wb06:
m3, b00: |00000000000000000000000000000000|
m3, b01: |00000000000000000000000000000000|
m3, b02: |00000000000000000000000000000000|
m3, b03: |00000000000000000000000000000000|
m3, b04: |00000000000000000000000000000000|
m3, b05: |00000000000000000000000000000000|
m3, b06: |00000000000000000000000000000000|
m3, b07: |00000000000000000000000000000000|
m3:0
Write DQ-DQS training:
m0: |000000000000000000000000000000000| delays: -
m1: |000000000000000000000000000000000| delays: -
m2: |000000000000000000000000000000000| delays: -
m3: |000000000000000000000000000000000| delays: -
Read leveling:
m0, b00: |00000000000000000000000000000000| delays: -
m0, b01: |00000000000000000000000000000000| delays: -
m0, b02: |00000000000000000000000000000000| delays: -
m0, b03: |00000000000000000000000000000000| delays: -
m0, b04: |00000000000000000000000000000000| delays: -
m0, b05: |00000000000000000000000000000000| delays: -
m0, b06: |00000000000000000000000000000000| delays: -
m0, b07: |00000000000000000000000000000000| delays: -
best: m0, b05 delays: -
m1, b00: |00000000000000000000000000000000| delays: -
m1, b01: |00000000000000000000000000000000| delays: -
m1, b02: |00000000000000000000000000000000| delays: -
m1, b03: |00000000000000000000000000000000| delays: -
m1, b04: |00000000000000000000000000000000| delays: -
m1, b05: |00000000000000000000000000000000| delays: -
m1, b06: |00000000000000000000000000000000| delays: -
m1, b07: |00000000000000000000000000000000| delays: -
best: m1, b05 delays: -
m2, b00: |00000000000000000000000000000000| delays: -
m2, b01: |00000000000000000000000000000000| delays: -
m2, b02: |00000000000000000000000000000000| delays: -
m2, b03: |00000000000000000000000000000000| delays: -
m2, b04: |00000000000000000000000000000000| delays: -
m2, b05: |00000000000000000000000000000000| delays: -
m2, b06: |00000000000000000000000000000000| delays: -
m2, b07: |00000000000000000000000000000000| delays: -
best: m2, b05 delays: -
m3, b00: |00000000000000000000000000000000| delays: -
m3, b01: |00000000000000000000000000000000| delays: -
m3, b02: |00000000000000000000000000000000| delays: -
m3, b03: |00000000000000000000000000000000| delays: -
m3, b04: |00000000000000000000000000000000| delays: -
m3, b05: |00000000000000000000000000000000| delays: -
m3, b06: |00000000000000000000000000000000| delays: -
m3, b07: |00000000000000000000000000000000| delays: -
best: m3, b05 delays: -
Switching SDRAM to hardware control.
Selected bitslips and delays:
Clock delay: 3
module: 0 1 2 3
wb: 0 0 0 0
wdly: 31 31 31 31
rb: 5 5 5 5
rdly: 31 31 31 31
Memtest at 0x40000000 (2.0MiB)...
memtest_bus error @ 0x40000000: 0xaaaa2800 vs 0xaaaaaaaa xor: 0x000082aa
memtest_bus error @ 0x40000020: 0xaaaabafe vs 0xaaaaaaaa xor: 0x00001054
memtest_bus error @ 0x40000040: 0xaaaabafe vs 0xaaaaaaaa xor: 0x00001054
memtest_bus error @ 0x40000060: 0xaaaabafe vs 0xaaaaaaaa xor: 0x00001054
memtest_bus error @ 0x40000080: 0xaaaabafe vs 0xaaaaaaaa xor: 0x00001054
memtest_bus error @ 0x400000a0: 0xaaaabafe vs 0xaaaaaaaa xor: 0x00001054
memtest_bus error @ 0x400000c0: 0xaaaabafe vs 0xaaaaaaaa xor: 0x00001054
memtest_bus error @ 0x400000e0: 0xaaaabafe vs 0xaaaaaaaa xor: 0x00001054
memtest_bus error @ 0x40000100: 0xaaaabafe vs 0xaaaaaaaa xor: 0x00001054
memtest_bus error @ 0x40000120: 0xaaaabaff vs 0xaaaaaaaa xor: 0x00001055
memtest_bus error @ 0x40000140: 0xaaaabafe vs 0xaaaaaaaa xor: 0x00001054
memtest_bus error @ 0x40000160: 0xaaaabafe vs 0xaaaaaaaa xor: 0x00001054
memtest_bus error @ 0x40000180: 0xaaaabafe vs 0xaaaaaaaa xor: 0x00001054
memtest_bus error @ 0x400001a0: 0xaaaabafe vs 0xaaaaaaaa xor: 0x00001054
memtest_bus error @ 0x400001c0: 0xaaaabafe vs 0xaaaaaaaa xor: 0x00001054
memtest_bus error @ 0x400001e0: 0xaaaabafe vs 0xaaaaaaaa xor: 0x00001054
memtest_bus error @ 0x40000000:: 0x55554501 vs 0x55555555 xor: 0x00001054
memtest_bus error @ 0x40000020:: 0x5555d5ff vs 0x55555555 xor: 0x000080aa
memtest_bus error @ 0x40000040:: 0x5555d5df vs 0x55555555 xor: 0x0000808a
memtest_bus error @ 0x40000060:: 0x5555d5ff vs 0x55555555 xor: 0x000080aa
memtest_bus error @ 0x40000080:: 0x5555d5ff vs 0x55555555 xor: 0x000080aa
memtest_bus error @ 0x400000a0:: 0x5555d5ff vs 0x55555555 xor: 0x000080aa
memtest_bus error @ 0x400000c0:: 0x5555d5ff vs 0x55555555 xor: 0x000080aa
memtest_bus error @ 0x400000e0:: 0x5555d5fd vs 0x55555555 xor: 0x000080a8
memtest_bus error @ 0x40000100:: 0x5555d5ff vs 0x55555555 xor: 0x000080aa
memtest_bus error @ 0x40000120:: 0x5555d5ff vs 0x55555555 xor: 0x000080aa
memtest_bus error @ 0x40000140:: 0x5555d5fd vs 0x55555555 xor: 0x000080a8
memtest_bus error @ 0x40000160:: 0x5555d5ff vs 0x55555555 xor: 0x000080aa
memtest_bus error @ 0x40000180:: 0x5555d5ff vs 0x55555555 xor: 0x000080aa
memtest_bus error @ 0x400001a0:: 0x5555d5ff vs 0x55555555 xor: 0x000080aa
memtest_bus error @ 0x400001c0:: 0x5555d5ff vs 0x55555555 xor: 0x000080aa
memtest_bus error @ 0x400001e0:: 0x5555d5ff vs 0x55555555 xor: 0x000080aa
Write: 0x40000000-0x40200000 2.0MiB
memtest_data error @ 0x40000000: 0x80200001 vs 0x80200003 xor: 0x00000002
memtest_data error @ 0x40000004: 0xc0300003 vs 0xc0300002 xor: 0x00000001
memtest_data error @ 0x40000008: 0x60180003 vs 0x60180001 xor: 0x00000002
memtest_data error @ 0x4000000c: 0xb02c0001 vs 0xb02c0003 xor: 0x00000002
memtest_data error @ 0x40000014: 0x6c1b0002 vs 0x6c1b0001 xor: 0x00000003
memtest_data error @ 0x40000018: 0xb62d0001 vs 0xb62d8003 xor: 0x00008002
memtest_data error @ 0x4000001c: 0xb62d8003 vs 0xdb36c002 xor: 0x6d1b4001
memtest_data error @ 0x40000020: 0x6d9bf2ff vs 0x6d9b6001 xor: 0x000092fe
memtest_data error @ 0x40000024: 0xb6ed6001 vs 0xb6edb003 xor: 0x0000d002
memtest_data error @ 0x40000028: 0xdb56d803 vs 0xdb56d802 xor: 0x00000001
memtest_data error @ 0x4000002c: 0x6dabf802 vs 0x6dab6c01 xor: 0x00009403
memtest_data error @ 0x40000030: 0xb6f5a603 vs 0xb6f5b603 xor: 0x00001000
memtest_data error @ 0x40000034: 0xdb5ad303 vs 0xdb5adb02 xor: 0x00000801
memtest_data error @ 0x40000038: 0x6dadfd03 vs 0x6dad6d81 xor: 0x00009082
memtest_data error @ 0x4000003c: 0x6dad6d81 vs 0xb6f6b6c3 xor: 0xdb5bdb42
memtest_data error @ 0x40000040: 0xdb5bdbff vs 0xdb5b5b62 xor: 0x0000809d
memtest_data error @ 0x40000044: 0x6dad7f63 vs 0x6dadadb1 xor: 0x0000d2d2
memtest_data error @ 0x40000048: 0xb6f6c6b1 vs 0xb6f6d6db xor: 0x0000106a
memtest_data error @ 0x4000004c: 0xdb5bf3db vs 0xdb5b6b6e xor: 0x000098b5
memtest_data error @ 0x40000050: 0x6dada56f vs 0x6dadb5b7 xor: 0x000010d8
memtest_data error @ 0x40000054: 0xb6f6d8b7 vs 0xb6f6dad8 xor: 0x0000026f
memtest_data error @ 0x40000058: 0x5b7bfdd8 vs 0x5b7b6d6c xor: 0x000090b4
memtest_data error @ 0x4000005c: 0x5b7b6d6c vs 0x2dbdb6b6 xor: 0x76c6dbda
memtest_data error @ 0x40000060: 0x16dedbff vs 0x16dedb5b xor: 0x000000a4
memtest_data error @ 0x40000064: 0x8b4fff5b vs 0x8b4f6dae xor: 0x000092f5
memtest_data error @ 0x40000068: 0x45a7e6af vs 0x45a7b6d7 xor: 0x00005078
memtest_data error @ 0x4000006c: 0xa2f393d7 vs 0xa2f3db68 xor: 0x000048bf
memtest_data error @ 0x40000070: 0x5179fde8 vs 0x5179edb4 xor: 0x0000105c
memtest_data error @ 0x40000074: 0x28bce4b4 vs 0x28bcf6da xor: 0x0000126e
memtest_data error @ 0x40000078: 0x145efbfb vs 0x145e7b6d xor: 0x00008096
memtest_data error @ 0x4000007c: 0x145e7b6d vs 0x8a0f3db5 xor: 0x9e5146d8
memtest_data error @ 0x40000080: 0xc5279eff vs 0xc5279ed9 xor: 0x00000026
memtest_data error @ 0x40000084: 0xe2b3dfd9 vs 0xe2b3cf6f xor: 0x000010b6
memtest_data error @ 0x40000088: 0xf179e76f vs 0xf179e7b4 xor: 0x000000db
memtest_data error @ 0x4000008c: 0x78bce3b4 vs 0x78bcf3da xor: 0x0000106e
memtest_data error @ 0x40000090: 0x3c5ef9f9 vs 0x3c5e79ed xor: 0x00008014
memtest_data error @ 0x40000094: 0x9e0f7ced vs 0x9e0f3cf5 xor: 0x00004018
memtest_data error @ 0x40000098: 0xcf271ef5 vs 0xcf279e79 xor: 0x0000808c
memtest_data error @ 0x4000009c: 0xcf279e79 vs 0xe7b3cf3f xor: 0x28945146
memtest_data error @ 0x400000a0: 0xf3f9f7fe vs 0xf3f9e79c xor: 0x00001062
memtest_data error @ 0x400000a4: 0x79fce39c vs 0x79fcf3ce xor: 0x00001052
memtest_data error @ 0x400000a8: 0x3cfef9ef vs 0x3cfe79e7 xor: 0x00008008
memtest_data error @ 0x400000ac: 0x9e7f78e7 vs 0x9e5f3cf0 xor: 0x00204417
memtest_data error @ 0x400000b0: 0x4f2f9ef8 vs 0x4f2f9e78 xor: 0x00000080
memtest_data error @ 0x400000b4: 0x2797df78 vs 0x2797cf3c xor: 0x00001044
memtest_data error @ 0x400000b8: 0x13cbe73c vs 0x13cbe79e xor: 0x000000a2
memtest_data error @ 0x400000bc: 0x13cbe79e vs 0x09e5f3cf xor: 0x1a2e1451
memtest_data error @ 0x400000c0: 0x84d2f9ff vs 0x84d2f9e4 xor: 0x0000001b
memtest_data error @ 0x400000c4: 0x4269fce4 vs 0x42697cf2 xor: 0x00008016
memtest_data error @ 0x400000c8: 0x21347ef3 vs 0x2134be79 xor: 0x0000c08a
memtest_data error @ 0x400000cc: 0x90ba9f79 vs 0x90ba5f3f xor: 0x0000c046
memtest_data error @ 0x400000d0: 0xc87d3fbc vs 0xc87d2f9c xor: 0x00001020
memtest_data error @ 0x400000d4: 0x643e0f9c vs 0x643e97ce xor: 0x00009852
memtest_data error @ 0x400000d8: 0x321fdbcf vs 0x321f4be7 xor: 0x00009028
memtest_data error @ 0x400000dc: 0x321f4be7 vs 0x992fa5f0 xor: 0xab30ee17
memtest_data error @ 0x400000e0: 0x4c97d2ff vs 0x4c97d2f8 xor: 0x00000007
memtest_data error @ 0x400000e4: 0x264bf3f8 vs 0x264be97c xor: 0x00001a84
memtest_data error @ 0x400000e8: 0x1325e47c vs 0x1325f4be xor: 0x000010c2
memtest_data error @ 0x400000ec: 0x0992f0be vs 0x0992fa5f xor: 0x00000ae1
memtest_data error @ 0x400000f0: 0x84e9fd5c vs 0x84e97d2c xor: 0x00008070
memtest_data error @ 0x400000f4: 0x42747c2c vs 0x4274be96 xor: 0x0000c2ba
memtest_data error @ 0x400000f8: 0x213adf97 vs 0x213a5f4b xor: 0x000080dc
memtest_data error @ 0x400000fc: 0x213a5f4b vs 0x90bd2fa6 xor: 0xb18770ed
memtest_data error @ 0x40000100: 0x485e97ff vs 0x485e97d3 xor: 0x0000002c
memtest_data error @ 0x40000104: 0xa40fdbd3 vs 0xa40f4bea xor: 0x00009039
memtest_data error @ 0x40000108: 0x520727eb vs 0x5207a5f5 xor: 0x0000821e
memtest_data error @ 0x4000010c: 0xa92380f5 vs 0xa923d2f9 xor: 0x0000520c
memtest_data error @ 0x40000110: 0xd4b1f9f9 vs 0xd4b1e97f xor: 0x00001086
memtest_data error @ 0x40000114: 0xea78e47f vs 0xea78f4bc xor: 0x000010c3
memtest_data error @ 0x40000118: 0x753cfabc vs 0x753c7a5e xor: 0x000080e2
memtest_data error @ 0x4000011c: 0x753c7a5e vs 0x3a9e3d2f xor: 0x4fa24771
memtest_data error @ 0x40000120: 0x9d6f9efe vs 0x9d6f1e94 xor: 0x0000806a
memtest_data error @ 0x40000124: 0x4eb71f94 vs 0x4eb78f4a xor: 0x000090de
memtest_data error @ 0x40000128: 0x275bc749 vs 0x275bc7a5 xor: 0x000000ec
memtest_data error @ 0x4000012c: 0x938de3a5 vs 0x938de3d1 xor: 0x00000074
memtest_data error @ 0x40000130: 0xc9e6e1f3 vs 0xc9e6f1eb xor: 0x00001018
memtest_data error @ 0x40000134: 0xe4d3f0eb vs 0xe4d378f6 xor: 0x0000881d
memtest_data error @ 0x40000138: 0x72697cf7 vs 0x7269bc7b xor: 0x0000c08c
memtest_data error @ 0x4000013c: 0x7269bc7b vs 0xb914de3e xor: 0xcb7d6245
memtest_data error @ 0x40000140: 0x5c8affff vs 0x5c8a6f1f xor: 0x000090e0
memtest_data error @ 0x40000144: 0xae65271f vs 0xae65378c xor: 0x00001093
memtest_data error @ 0x40000148: 0x57321b8c vs 0x57329bc6 xor: 0x0000804a
memtest_data error @ 0x4000014c: 0x2b999bc6 vs 0x2b994de3 xor: 0x0000d625
memtest_data error @ 0x40000150: 0x95eca6e2 vs 0x95eca6f2 xor: 0x00000010
memtest_data error @ 0x40000154: 0x4af683f2 vs 0x4af65379 xor: 0x0000d08b
memtest_data error @ 0x40000158: 0xa55b3979 vs 0xa55b29bf xor: 0x000010c6
memtest_data error @ 0x4000015c: 0xa55b29bf vs 0xd28d94dc xor: 0x77d6bd63
memtest_data error @ 0x40000160: 0x6946daff vs 0x6946ca6e xor: 0x00001091
memtest_data error @ 0x40000164: 0x34a3e76e vs 0x34a36537 xor: 0x00008259
memtest_data error @ 0x40000168: 0x9a716036 vs 0x9a71b298 xor: 0x0000d2ae
memtest_data error @ 0x4000016c: 0x4d389398 vs 0x4d38d94c xor: 0x00004ad4
memtest_data error @ 0x40000170: 0x269cfc4c vs 0x269c6ca6 xor: 0x000090ea
memtest_data error @ 0x40000174: 0x134e64a6 vs 0x134e3653 xor: 0x000052f5
memtest_data error @ 0x40000178: 0x89871b53 vs 0x89871b2a xor: 0x00000079
memtest_data error @ 0x4000017c: 0x89871b2a vs 0x44c38d95 xor: 0xcd4496bf
memtest_data error @ 0x40000180: 0xa241d6ff vs 0xa241c6c9 xor: 0x00001036
memtest_data error @ 0x40000184: 0xd100e3c9 vs 0xd100e367 xor: 0x000000ae
memtest_data error @ 0x40000188: 0xe8a0e167 vs 0xe8a071b0 xor: 0x000090d7
memtest_data error @ 0x4000018c: 0x745070b0 vs 0x745038d8 xor: 0x00004868
memtest_data error @ 0x40000190: 0x3a281cf8 vs 0x3a281c6c xor: 0x00000094
memtest_data error @ 0x40000194: 0x1d141c6c vs 0x1d140e36 xor: 0x0000125a
memtest_data error @ 0x40000198: 0x0e8a0737 vs 0x0e8a071b xor: 0x0000002c
memtest_data error @ 0x4000019c: 0x0e8a071b vs 0x8765038e xor: 0x89ef0495
memtest_data error @ 0x400001a0: 0x43b291ff vs 0x43b281c7 xor: 0x00001038
memtest_data error @ 0x400001a4: 0xa1f9c0c7 vs 0xa1f940e0 xor: 0x00008027
memtest_data error @ 0x400001a8: 0x50fc20e0 vs 0x50fca070 xor: 0x00008090
memtest_data error @ 0x400001ac: 0x287e8070 vs 0x287e5038 xor: 0x0000d048
memtest_data error @ 0x400001b0: 0x143f3838 vs 0x143f281c xor: 0x00001024
memtest_data error @ 0x400001b4: 0x0a1f001c vs 0x0a1f940e xor: 0x00009412
memtest_data error @ 0x400001b8: 0x050fd80f vs 0x050fca07 xor: 0x00001208
memtest_data error @ 0x400001bc: 0x050fca07 vs 0x82a7e500 xor: 0x87a82f07
memtest_data error @ 0x400001c0: 0x4153f2fe vs 0x4153f280 xor: 0x0000007e
memtest_data error @ 0x400001c4: 0x20a9fb80 vs 0x20a9f940 xor: 0x000002c0
memtest_data error @ 0x400001c8: 0x1054fc40 vs 0x1054fca0 xor: 0x000000e0
memtest_data error @ 0x400001cc: 0x082afca0 vs 0x082a7e50 xor: 0x000082f0
memtest_data error @ 0x400001d0: 0x04153f70 vs 0x04153f28 xor: 0x00000058
memtest_data error @ 0x400001d4: 0x020a1f28 vs 0x020a9f94 xor: 0x000080bc
memtest_data error @ 0x400001d8: 0x0105df94 vs 0x01054fca xor: 0x0000905e
memtest_data error @ 0x400001dc: 0x01054fca vs 0x0082a7e5 xor: 0x0187e82f
memtest_data error @ 0x400001e0: 0x8061d3ff vs 0x806153f1 xor: 0x0000800e
memtest_data error @ 0x400001e4: 0xc0107bf1 vs 0xc010a9fb xor: 0x0000d20a
memtest_data error @ 0x400001e8: 0xe028c4fb vs 0xe02854fe xor: 0x00009005
memtest_data error @ 0x400001ec: 0x701474fe vs 0x70142a7f xor: 0x00005e81
memtest_data error @ 0x400001f0: 0xb82a057c vs 0xb82a153c xor: 0x00001040
memtest_data error @ 0x400001f4: 0x5c15183c vs 0x5c150a9e xor: 0x000012a2
memtest_data error @ 0x400001f8: 0x2e0a059f vs 0x2e0a854f xor: 0x000080d0
memtest_data error @ 0x400001fc: 0x2e0a854f vs 0x972542a4 xor: 0xb92fc7eb
memtest_data error @ 0x40000200: 0x4b92b3ff vs 0x4b92a152 xor: 0x000012ad
Read: 0x40000000-0x40200000 2.0MiB
bus errors: 32/256
addr errors: 0/8192
data errors: 523671/524288
Memtest KO
Memory initialization failed
#!/usr/bin/env python3
import math
from migen import *
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.integration.builder import Builder
from litex.soc.cores.clock import S7MMCM, S7IDELAYCTRL
from litex_boards.platforms import digilent_genesys2
from litedram.phy import k7ddrphy
from liteeth.phy import LiteEthS7PHYRGMII
from rowhammer_tester.targets import common
# CRG ----------------------------------------------------------------------------------------------
class CRG(Module):
def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
# self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
# self.clock_domains.cd_sys4x_dqs = ClockDomain()
self.clock_domains.cd_idelay = ClockDomain()
# # #
self.submodules.pll = pll = S7MMCM(speedgrade=-2)
self.comb += pll.reset.eq(~platform.request("cpu_reset_n") | self.rst)
pll.register_clkin(platform.request("clk200"), 200e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
# pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq)
# pll.create_clkout(self.cd_sys4x_dqs, 4 * sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, iodelay_clk_freq)
# platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
# SoC ----------------------------------------------------------------------------------------------
class SoC(common.RowHammerSoC):
def __init__(self, **kwargs):
super().__init__(**kwargs)
# self.add_constant("SDRAM_DEBUG")
# # Analyzer ---------------------------------------------------------------------------------
# analyzer_signals = [
# self.sdram.dfii.ext_dfi_sel,
# *[p.rddata for p in self.ddrphy.dfi.phases],
# *[p.rddata_valid for p in self.ddrphy.dfi.phases],
# *[p.rddata_en for p in self.ddrphy.dfi.phases],
# ]
# from litescope import LiteScopeAnalyzer
# self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
# depth = 512,
# clock_domain = "sys",
# csr_csv = "analyzer.csv")
# self.add_csr("analyzer")
def get_platform(self):
return digilent_genesys2.Platform()
def get_crg(self):
return CRG(self.platform, self.sys_clk_freq,
iodelay_clk_freq=float(self.args.iodelay_clk_freq))
def get_ddrphy(self):
return k7ddrphy.K7DDRPHY(self.platform.request("ddram"),
write_latency_calibration = True,
iodelay_clk_freq = float(self.args.iodelay_clk_freq),
sys_clk_freq = self.sys_clk_freq,
memtype = "DDR3")
def get_sdram_ratio(self):
return "1:4"
def add_host_bridge(self):
self.submodules.ethphy = LiteEthS7PHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"),
with_hw_init_reset=False,
tx_delay=2e-9,
rx_delay=2e-9,
iodelay_clk_freq = float(self.args.iodelay_clk_freq),
)
self.add_etherbone(
phy = self.ethphy,
ip_address = self.ip_address,
mac_address = self.mac_address,
udp_port = self.udp_port,
buffer_depth = 256)
# Build --------------------------------------------------------------------------------------------
def main():
parser = common.ArgumentParser(
description = "LiteX SoC on Genesys 2",
sys_clk_freq = '100e6',
module = 'MT41J256M16',
)
g = parser.add_argument_group(title="Genesys 2")
parser.add(g, "--eth-reset-time", default="10e-3", help="Duration of Ethernet PHY reset")
parser.add(g, "--iodelay-clk-freq", default="200e6", help="IODELAY clock frequency")
vivado_build_args(g)
args = parser.parse_args()
soc_kwargs = common.get_soc_kwargs(args)
soc = SoC(**soc_kwargs)
target_name = 'genesys2'
builder_kwargs = common.get_builder_kwargs(args, target_name=target_name)
builder = Builder(soc, **builder_kwargs)
build_kwargs = vivado_build_argdict(args) if not args.sim else {}
common.run(args, builder, build_kwargs, target_name=target_name)
if __name__ == "__main__":
main()I have a reference litex implementation using only litedram, and that one succeeds when performing the memory training. Numbers shown below:
Hello,
I made my own target python file for the Genesys2 board, and I am trying to perform rowhammer tests on it but the
sdram_initprocedure always fails. As far as I am aware, all peripherals and memory have been configured correctly, and the modules are the correct ones as specified by the Digilent genesys2 reference guide.Output of initializing the memory:
genesys2.py file:
I have a reference litex implementation using only litedram, and that one succeeds when performing the memory training. Numbers shown below:
Litex selected bitslips and delays:
Rowhammer tester selected bitslips and delays:
My questions are: