Add support for FastVDMA in LiteX

[kgugala]

FastVDMA is available here https://github.com/antmicro/fastvdma

To integrate it with LiteX you have to generate Verilog code and wrap it in LiteX. Here is an example how a Verilog module can be wrapped: https://github.com/enjoy-digital/litesdcard/blob/master/litesdcard/emulator/linklayer.py#L109

[kabrodzki]

Can we fork this fastVDMA project? After some quick test I see that we need to change the configuration to use the Wishbone, because now it's generating the verilog source for AXI4
DMATop.scala:

  val csrFrontend = Module(new AXI4LiteCSR(DMATop.addrWidth))
  val readerFrontend = Module(new AXIStreamSlave(DMATop.addrWidth, DMATop.readDataWidth))
  val writerFrontend = Module(new AXI4Writer(DMATop.addrWidth, DMATop.writeDataWidth))

I am also not quite sure how can we test the wrapper alone. I remember that @kgugala mentioned that there is some more extensive paper on this project (I mean more extensive than this and this)

[kgugala]

@kabrodzki I made a fork. You should be able to push there.

As for more info about the DMA you can always ask the author @piotr-binkowski

[rw1nkler]

I don't know if this will be useful, but LiteX is able to convert the AXI to wishbone:
https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/axi.py#L403

But this is like a wrapper on a wrapper, so maybe there is a better option.

[kabrodzki]

I created the repo for the wrapper and uploaded the "Link layer", but I'm not quite sure how to go from there.

[kgugala]

now you should include the DMA in the LiteX system you're working on, so you can access DMA's registers from the CPU

[piotr-binkowski]

you will also need to wrap your wishbone signals as wishbone.Interface() (like here) so that you can later use them with add_wb_master and add_wb_slave in your target.