vhdl_coding/README at master · abdimuna1/vhdl_coding · GitHub

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/*
 * =====================================================================================
 *
 *       Filename:  read.txt
 *
 *    Description:  this is my VHDL project
 *
 *        Version:  1.0
 *        Created:  10/25/12 19:40:22
 *       Revision:  none
 *       Compiler:  ModeSim
 *
 *         Author:  ABDIMUNA (), abdimuna1@gmail.com
 *   Organization:
 *
 * =====================================================================================


# I wrote the code for components shown in .png file
# look that file and see how the components are connected
# #the code of each component is in respective component name
# compile the code by using ModeSim (I used windows version)
# laod the simulator and see if averything works as expected
# CONTRIBUTION/COMMENTS  are  HIGHLY RECOMEMENDED, thanks and enjoy .