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18+ < h2 id ="component " class ="definition "> Component Declaration</ h2 >
19+ < h3 class ="definition "> Description:</ h3 >
20+ < p class ="big-line-height ">
21+ A < b > Component</ b > represents an < b > entity/architecture pair</ b > . < br >
22+ It specifies a subsystem, which can be instantiated in another architecture leading to a hierarchical
23+ specification.
24+ < b > Component instantiation is analogous to a chip in a socket in a board</ b > . < br >
25+ A < b > Component</ b > is instantiated within an
26+ architecture, and is associated entity and architecture during elaboration. < br >
27+ < b > A component must be declared before it is instantiated.</ b >
28+ </ p >
29+ < p class ="big-line-height ">
30+ The binding of a design entity to a given component may be delayed and may be placed either in the
31+ < b > configuration
32+ specification or configuration declaration</ b > . < br > < b > For default configuration, the component name must
33+ match the name of
34+ the corresponding entity to be used in its place, and the entity name must be visible </ b > . < br > Also
35+ generics and ports
36+ must match in name, mode and type.
37+ </ p >
38+ < p class ="big-line-height ">
39+ The component can be defined in < b > a package, design entity, architecture, or block declaration</ b > . If the
40+ component
41+ is declared in an < b > architecture</ b > , it must be declared before the begin statement of the architecture. < br >
42+ In such a
43+ case, the component can be used (instantiated) in the architecture only. < br >
44+
45+ < b > If a component is declared in a package, then such a component is visible in any architecture, which uses
46+ this
47+ package.</ b >
48+ </ p >
49+
50+ < h3 class ="definition "> Syntax:</ h3 >
51+ < pre > < code class ="language-vhdl ">
52+ component component_name [ is ]
53+ [ generic ( generic_list ); ]
54+ [ port ( port_list ); ]
55+ end component [ component_name ];
56+ </ code >
57+ </ pre >
58+ < h3 class ="definition "> Example:</ h3 >
59+ in this example let's assume that < b > my_component</ b > is declared in another < b > entity / architecture
60+ declaration</ b >
61+ < pre > < code class ="language-vhdl ">
62+ -- Entity declaration
63+ entity my_top_entity is
64+ port (
65+ clk, reset : in std_logic;
66+ data_in : in std_logic_vector(7 downto 0);
67+ data_out : out std_logic_vector(7 downto 0)
68+ );
69+ end entity my_top_entity;
70+
71+ -- Architecture declaration
72+ architecture my_arch of my_top_entity is
73+ -- Component declaration(assuming my component is declared elsewhere)
74+ component my_component is
75+ port (
76+ clk, reset : in std_logic;
77+ data_in : in std_logic_vector(7 downto 0);
78+ data_out : out std_logic_vector(7 downto 0)
79+ );
80+ end component;
81+
82+ -- Internal signals
83+ signal internal_data : std_logic_vector(7 downto 0);
84+ begin
85+ -- Component instantiation
86+ my_component_inst : my_component
87+ port map (
88+ clk => clk,
89+ reset => reset,
90+ data_in => data_in,
91+ data_out => internal_data
92+ );
93+
94+ -- Assign output
95+ data_out >= internal_data;
96+ end architecture my_arch;
97+
98+ </ code >
99+ </ pre >
100+ < b >
101+ The component declaration allows you to specify the interface of the component, and the component instantiation
102+ allows you to create an instance of the component and connect it to the rest of the design.
103+ </ b >
104+ < h3 class ="definition "> Notes: </ h3 >
105+ < ul class ="notes ">
106+ < li > A component declaration does not explicitly define which entity/architecture pair is bound to each instance.
107+ < br > If no configuration specification or configuration declaration is defined a default binding is used.</ li >
108+ </ ul >
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